/* Autogenerated file, DO NOT EDIT manually! generated by gen_perf.py
 *
 * Copyright (c) 2015 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <stdint.h>
#include <stdbool.h>

#include <drm-uapi/i915_drm.h>

#include "util/hash_table.h"
#include "util/ralloc.h"

#include "intel_perf_metrics.h"
#include "perf/intel_perf.h"
#include "perf/intel_perf_setup.h"

static const char name[] = {
   /* 0 */ "AMFS 4X4 SHADING REQUEST SLICE0\0"
   /* 32 */ "AMFS 4X4 SHADING REQUEST SLICE1\0"
   /* 64 */ "AMFS 4X4 SHADING REQUEST SLICE2\0"
   /* 96 */ "AMFS 4X4 SHADING REQUEST SLICE3\0"
   /* 128 */ "AMFS 4X4 SHADING REQUEST SLICE4\0"
   /* 160 */ "AMFS 4X4 SHADING REQUEST SLICE5\0"
   /* 192 */ "AMFS 4X4 SHADING REQUEST SLICE6\0"
   /* 224 */ "AMFS 4X4 SHADING REQUEST SLICE7\0"
   /* 256 */ "AMFS CACHE HIT SLICE0\0"
   /* 278 */ "AMFS CACHE HIT SLICE1\0"
   /* 300 */ "AMFS CACHE HIT SLICE2\0"
   /* 322 */ "AMFS CACHE HIT SLICE3\0"
   /* 344 */ "AMFS CACHE HIT SLICE4\0"
   /* 366 */ "AMFS CACHE HIT SLICE5\0"
   /* 388 */ "AMFS CACHE HIT SLICE6\0"
   /* 410 */ "AMFS CACHE HIT SLICE7\0"
   /* 432 */ "AMFS CACHE MISS SLICE0\0"
   /* 455 */ "AMFS CACHE MISS SLICE1\0"
   /* 478 */ "AMFS CACHE MISS SLICE2\0"
   /* 501 */ "AMFS CACHE MISS SLICE3\0"
   /* 524 */ "AMFS CACHE MISS SLICE4\0"
   /* 547 */ "AMFS CACHE MISS SLICE5\0"
   /* 570 */ "AMFS CACHE MISS SLICE6\0"
   /* 593 */ "AMFS CACHE MISS SLICE7\0"
   /* 616 */ "AMFS L3 ACCESS SLICE0\0"
   /* 638 */ "AMFS L3 ACCESS SLICE1\0"
   /* 660 */ "AMFS L3 ACCESS SLICE2\0"
   /* 682 */ "AMFS L3 ACCESS SLICE3\0"
   /* 704 */ "AMFS L3 ACCESS SLICE4\0"
   /* 726 */ "AMFS L3 ACCESS SLICE5\0"
   /* 748 */ "AMFS L3 ACCESS SLICE6\0"
   /* 770 */ "AMFS L3 ACCESS SLICE7\0"
   /* 792 */ "AMFS L3 ATOMIC SLICE0\0"
   /* 814 */ "AMFS L3 ATOMIC SLICE1\0"
   /* 836 */ "AMFS L3 ATOMIC SLICE2\0"
   /* 858 */ "AMFS L3 ATOMIC SLICE3\0"
   /* 880 */ "AMFS L3 ATOMIC SLICE4\0"
   /* 902 */ "AMFS L3 ATOMIC SLICE5\0"
   /* 924 */ "AMFS L3 ATOMIC SLICE6\0"
   /* 946 */ "AMFS L3 ATOMIC SLICE7\0"
   /* 968 */ "AMFS L3 WRITE SLICE0\0"
   /* 989 */ "AMFS L3 WRITE SLICE1\0"
   /* 1010 */ "AMFS L3 WRITE SLICE2\0"
   /* 1031 */ "AMFS L3 WRITE SLICE3\0"
   /* 1052 */ "AMFS L3 WRITE SLICE4\0"
   /* 1073 */ "AMFS L3 WRITE SLICE5\0"
   /* 1094 */ "AMFS L3 WRITE SLICE6\0"
   /* 1115 */ "AMFS L3 WRITE SLICE7\0"
   /* 1136 */ "AMFS STALL ALL INPUT SLICE0\0"
   /* 1164 */ "AMFS STALL ALL INPUT SLICE1\0"
   /* 1192 */ "AMFS STALL ALL INPUT SLICE2\0"
   /* 1220 */ "AMFS STALL ALL INPUT SLICE3\0"
   /* 1248 */ "AMFS STALL ALL INPUT SLICE4\0"
   /* 1276 */ "AMFS STALL ALL INPUT SLICE5\0"
   /* 1304 */ "AMFS STALL ALL INPUT SLICE6\0"
   /* 1332 */ "AMFS STALL ALL INPUT SLICE7\0"
   /* 1360 */ "AMFS STALL ANY INPUT SLICE0\0"
   /* 1388 */ "AMFS STALL ANY INPUT SLICE1\0"
   /* 1416 */ "AMFS STALL ANY INPUT SLICE2\0"
   /* 1444 */ "AMFS STALL ANY INPUT SLICE3\0"
   /* 1472 */ "AMFS STALL ANY INPUT SLICE4\0"
   /* 1500 */ "AMFS STALL ANY INPUT SLICE5\0"
   /* 1528 */ "AMFS STALL ANY INPUT SLICE6\0"
   /* 1556 */ "AMFS STALL ANY INPUT SLICE7\0"
   /* 1584 */ "ASYNC CS EM Pipe Active\0"
   /* 1608 */ "ASYNC CS FPU Pipe Active\0"
   /* 1633 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE0\0"
   /* 1671 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE1\0"
   /* 1709 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE10\0"
   /* 1748 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE11\0"
   /* 1787 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE12\0"
   /* 1826 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE13\0"
   /* 1865 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE14\0"
   /* 1904 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE15\0"
   /* 1943 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE16\0"
   /* 1982 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE17\0"
   /* 2021 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE18\0"
   /* 2060 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE19\0"
   /* 2099 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE2\0"
   /* 2137 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE20\0"
   /* 2176 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE21\0"
   /* 2215 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE22\0"
   /* 2254 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE23\0"
   /* 2293 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE24\0"
   /* 2332 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE25\0"
   /* 2371 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE26\0"
   /* 2410 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE27\0"
   /* 2449 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE28\0"
   /* 2488 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE29\0"
   /* 2527 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE3\0"
   /* 2565 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE30\0"
   /* 2604 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE31\0"
   /* 2643 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE4\0"
   /* 2681 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE5\0"
   /* 2719 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE6\0"
   /* 2757 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE7\0"
   /* 2795 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE8\0"
   /* 2833 */ "ASYNC GPGPU THREAD EXIT COUNT XECORE9\0"
   /* 2871 */ "ASYNC GPGPU THREADGROUP COUNT XECORE0\0"
   /* 2909 */ "ASYNC GPGPU THREADGROUP COUNT XECORE1\0"
   /* 2947 */ "ASYNC GPGPU THREADGROUP COUNT XECORE10\0"
   /* 2986 */ "ASYNC GPGPU THREADGROUP COUNT XECORE11\0"
   /* 3025 */ "ASYNC GPGPU THREADGROUP COUNT XECORE12\0"
   /* 3064 */ "ASYNC GPGPU THREADGROUP COUNT XECORE13\0"
   /* 3103 */ "ASYNC GPGPU THREADGROUP COUNT XECORE14\0"
   /* 3142 */ "ASYNC GPGPU THREADGROUP COUNT XECORE15\0"
   /* 3181 */ "ASYNC GPGPU THREADGROUP COUNT XECORE16\0"
   /* 3220 */ "ASYNC GPGPU THREADGROUP COUNT XECORE17\0"
   /* 3259 */ "ASYNC GPGPU THREADGROUP COUNT XECORE18\0"
   /* 3298 */ "ASYNC GPGPU THREADGROUP COUNT XECORE19\0"
   /* 3337 */ "ASYNC GPGPU THREADGROUP COUNT XECORE2\0"
   /* 3375 */ "ASYNC GPGPU THREADGROUP COUNT XECORE20\0"
   /* 3414 */ "ASYNC GPGPU THREADGROUP COUNT XECORE21\0"
   /* 3453 */ "ASYNC GPGPU THREADGROUP COUNT XECORE22\0"
   /* 3492 */ "ASYNC GPGPU THREADGROUP COUNT XECORE23\0"
   /* 3531 */ "ASYNC GPGPU THREADGROUP COUNT XECORE24\0"
   /* 3570 */ "ASYNC GPGPU THREADGROUP COUNT XECORE25\0"
   /* 3609 */ "ASYNC GPGPU THREADGROUP COUNT XECORE26\0"
   /* 3648 */ "ASYNC GPGPU THREADGROUP COUNT XECORE27\0"
   /* 3687 */ "ASYNC GPGPU THREADGROUP COUNT XECORE28\0"
   /* 3726 */ "ASYNC GPGPU THREADGROUP COUNT XECORE29\0"
   /* 3765 */ "ASYNC GPGPU THREADGROUP COUNT XECORE3\0"
   /* 3803 */ "ASYNC GPGPU THREADGROUP COUNT XECORE30\0"
   /* 3842 */ "ASYNC GPGPU THREADGROUP COUNT XECORE31\0"
   /* 3881 */ "ASYNC GPGPU THREADGROUP COUNT XECORE4\0"
   /* 3919 */ "ASYNC GPGPU THREADGROUP COUNT XECORE5\0"
   /* 3957 */ "ASYNC GPGPU THREADGROUP COUNT XECORE6\0"
   /* 3995 */ "ASYNC GPGPU THREADGROUP COUNT XECORE7\0"
   /* 4033 */ "ASYNC GPGPU THREADGROUP COUNT XECORE8\0"
   /* 4071 */ "ASYNC GPGPU THREADGROUP COUNT XECORE9\0"
   /* 4109 */ "AVG GPU Core Frequency\0"
   /* 4132 */ "All Data Port 0 Reads from L3\0"
   /* 4162 */ "All Data Port 0 Writes to L3\0"
   /* 4191 */ "Alpha Test Fails\0"
   /* 4208 */ "Any Engine Busy\0"
   /* 4224 */ "Any compute engine busy\0"
   /* 4248 */ "AnyRingBusy\0"
   /* 4260 */ "BC Bottleneck\0"
   /* 4274 */ "BC00 Bottleneck\0"
   /* 4290 */ "BC10 Bottleneck\0"
   /* 4306 */ "BC20 Bottleneck\0"
   /* 4322 */ "BC30 Bottleneck\0"
   /* 4338 */ "BC40 Bottleneck\0"
   /* 4354 */ "BC50 Bottleneck\0"
   /* 4370 */ "BC60 Bottleneck\0"
   /* 4386 */ "BC70 Bottleneck\0"
   /* 4402 */ "Blitter Ring Busy\0"
   /* 4420 */ "CL Stall\0"
   /* 4429 */ "CL0 Stall\0"
   /* 4439 */ "CL1 Stall\0"
   /* 4449 */ "CL2 Stall\0"
   /* 4459 */ "CL3 Stall\0"
   /* 4469 */ "CL4 Stall\0"
   /* 4479 */ "CL5 Stall\0"
   /* 4489 */ "CL6 Stall\0"
   /* 4499 */ "CL7 Stall\0"
   /* 4509 */ "CLIPPER INPUT AVAILABLE SLICE0\0"
   /* 4540 */ "CLIPPER INPUT AVAILABLE SLICE1\0"
   /* 4571 */ "CLIPPER INPUT AVAILABLE SLICE2\0"
   /* 4602 */ "CLIPPER INPUT AVAILABLE SLICE3\0"
   /* 4633 */ "CLIPPER INPUT AVAILABLE SLICE4\0"
   /* 4664 */ "CLIPPER INPUT AVAILABLE SLICE5\0"
   /* 4695 */ "CLIPPER INPUT AVAILABLE SLICE6\0"
   /* 4726 */ "CLIPPER INPUT AVAILABLE SLICE7\0"
   /* 4757 */ "CLIPPER INPUT VERTEX SLICE0\0"
   /* 4785 */ "CLIPPER INPUT VERTEX SLICE1\0"
   /* 4813 */ "CLIPPER INPUT VERTEX SLICE2\0"
   /* 4841 */ "CLIPPER INPUT VERTEX SLICE3\0"
   /* 4869 */ "CLIPPER INPUT VERTEX SLICE4\0"
   /* 4897 */ "CLIPPER INPUT VERTEX SLICE5\0"
   /* 4925 */ "CLIPPER INPUT VERTEX SLICE6\0"
   /* 4953 */ "CLIPPER INPUT VERTEX SLICE7\0"
   /* 4981 */ "CLIPPER OUTPUT READY SLICE0\0"
   /* 5009 */ "CLIPPER OUTPUT READY SLICE1\0"
   /* 5037 */ "CLIPPER OUTPUT READY SLICE2\0"
   /* 5065 */ "CLIPPER OUTPUT READY SLICE3\0"
   /* 5093 */ "CLIPPER OUTPUT READY SLICE4\0"
   /* 5121 */ "CLIPPER OUTPUT READY SLICE5\0"
   /* 5149 */ "CLIPPER OUTPUT READY SLICE6\0"
   /* 5177 */ "CLIPPER OUTPUT READY SLICE7\0"
   /* 5205 */ "CLIPPER PRIMITIVE CULL SLICE0\0"
   /* 5235 */ "CLIPPER PRIMITIVE CULL SLICE1\0"
   /* 5265 */ "CLIPPER PRIMITIVE CULL SLICE2\0"
   /* 5295 */ "CLIPPER PRIMITIVE CULL SLICE3\0"
   /* 5325 */ "CLIPPER PRIMITIVE CULL SLICE4\0"
   /* 5355 */ "CLIPPER PRIMITIVE CULL SLICE5\0"
   /* 5385 */ "CLIPPER PRIMITIVE CULL SLICE6\0"
   /* 5415 */ "CLIPPER PRIMITIVE CULL SLICE7\0"
   /* 5445 */ "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0\0"
   /* 5484 */ "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1\0"
   /* 5523 */ "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE2\0"
   /* 5562 */ "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE3\0"
   /* 5601 */ "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE4\0"
   /* 5640 */ "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE5\0"
   /* 5679 */ "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE6\0"
   /* 5718 */ "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE7\0"
   /* 5757 */ "CLIPPER PRIMITIVE OUTPUT SLICE0\0"
   /* 5789 */ "CLIPPER PRIMITIVE OUTPUT SLICE1\0"
   /* 5821 */ "CLIPPER PRIMITIVE OUTPUT SLICE2\0"
   /* 5853 */ "CLIPPER PRIMITIVE OUTPUT SLICE3\0"
   /* 5885 */ "CLIPPER PRIMITIVE OUTPUT SLICE4\0"
   /* 5917 */ "CLIPPER PRIMITIVE OUTPUT SLICE5\0"
   /* 5949 */ "CLIPPER PRIMITIVE OUTPUT SLICE6\0"
   /* 5981 */ "CLIPPER PRIMITIVE OUTPUT SLICE7\0"
   /* 6013 */ "CLIPPER TRANSACTION OUTPUT SLICE0\0"
   /* 6047 */ "CLIPPER TRANSACTION OUTPUT SLICE1\0"
   /* 6081 */ "CLIPPER TRANSACTION OUTPUT SLICE2\0"
   /* 6115 */ "CLIPPER TRANSACTION OUTPUT SLICE3\0"
   /* 6149 */ "CLIPPER TRANSACTION OUTPUT SLICE4\0"
   /* 6183 */ "CLIPPER TRANSACTION OUTPUT SLICE5\0"
   /* 6217 */ "CLIPPER TRANSACTION OUTPUT SLICE6\0"
   /* 6251 */ "CLIPPER TRANSACTION OUTPUT SLICE7\0"
   /* 6285 */ "COLOR L3 ACCESS L3BANK0\0"
   /* 6309 */ "COLOR L3 ACCESS L3BANK1\0"
   /* 6333 */ "COLOR L3 ACCESS L3BANK2\0"
   /* 6357 */ "COLOR L3 ACCESS L3BANK3\0"
   /* 6381 */ "COLOR L3 ACCESS L3BANK4\0"
   /* 6405 */ "COLOR L3 ACCESS L3BANK5\0"
   /* 6429 */ "COLOR L3 ACCESS L3BANK6\0"
   /* 6453 */ "COLOR L3 ACCESS L3BANK7\0"
   /* 6477 */ "COLOR L3 HIT L3BANK0\0"
   /* 6498 */ "COLOR L3 HIT L3BANK1\0"
   /* 6519 */ "COLOR L3 HIT L3BANK10\0"
   /* 6541 */ "COLOR L3 HIT L3BANK11\0"
   /* 6563 */ "COLOR L3 HIT L3BANK12\0"
   /* 6585 */ "COLOR L3 HIT L3BANK13\0"
   /* 6607 */ "COLOR L3 HIT L3BANK14\0"
   /* 6629 */ "COLOR L3 HIT L3BANK15\0"
   /* 6651 */ "COLOR L3 HIT L3BANK16\0"
   /* 6673 */ "COLOR L3 HIT L3BANK17\0"
   /* 6695 */ "COLOR L3 HIT L3BANK18\0"
   /* 6717 */ "COLOR L3 HIT L3BANK19\0"
   /* 6739 */ "COLOR L3 HIT L3BANK2\0"
   /* 6760 */ "COLOR L3 HIT L3BANK20\0"
   /* 6782 */ "COLOR L3 HIT L3BANK21\0"
   /* 6804 */ "COLOR L3 HIT L3BANK22\0"
   /* 6826 */ "COLOR L3 HIT L3BANK23\0"
   /* 6848 */ "COLOR L3 HIT L3BANK24\0"
   /* 6870 */ "COLOR L3 HIT L3BANK25\0"
   /* 6892 */ "COLOR L3 HIT L3BANK26\0"
   /* 6914 */ "COLOR L3 HIT L3BANK27\0"
   /* 6936 */ "COLOR L3 HIT L3BANK28\0"
   /* 6958 */ "COLOR L3 HIT L3BANK29\0"
   /* 6980 */ "COLOR L3 HIT L3BANK3\0"
   /* 7001 */ "COLOR L3 HIT L3BANK30\0"
   /* 7023 */ "COLOR L3 HIT L3BANK31\0"
   /* 7045 */ "COLOR L3 HIT L3BANK4\0"
   /* 7066 */ "COLOR L3 HIT L3BANK5\0"
   /* 7087 */ "COLOR L3 HIT L3BANK6\0"
   /* 7108 */ "COLOR L3 HIT L3BANK7\0"
   /* 7129 */ "COLOR L3 HIT L3BANK8\0"
   /* 7150 */ "COLOR L3 HIT L3BANK9\0"
   /* 7171 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE0\0"
   /* 7210 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE1\0"
   /* 7249 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE10\0"
   /* 7289 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE11\0"
   /* 7329 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE12\0"
   /* 7369 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE13\0"
   /* 7409 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE14\0"
   /* 7449 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE15\0"
   /* 7489 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE2\0"
   /* 7528 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE3\0"
   /* 7567 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE4\0"
   /* 7606 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE5\0"
   /* 7645 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE6\0"
   /* 7684 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE7\0"
   /* 7723 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE8\0"
   /* 7762 */ "COLOR PIPE CACHE LATENCY1 STALL CPIPE9\0"
   /* 7801 */ "COLOR PIPE CACHE LATENCY2 STALL L3NODE0\0"
   /* 7841 */ "COLOR PIPE CACHE LATENCY2 STALL L3NODE1\0"
   /* 7881 */ "COLOR PIPE CACHE LATENCY2 STALL L3NODE2\0"
   /* 7921 */ "COLOR PIPE CACHE LATENCY2 STALL L3NODE3\0"
   /* 7961 */ "COLOR PIPE CACHE LATENCY2 STALL L3NODE4\0"
   /* 8001 */ "COLOR PIPE CACHE LATENCY2 STALL L3NODE5\0"
   /* 8041 */ "COLOR PIPE CACHE LATENCY2 STALL L3NODE6\0"
   /* 8081 */ "COLOR PIPE CACHE LATENCY2 STALL L3NODE7\0"
   /* 8121 */ "COMMAND PARSER COMPUTE ENGINE BUSY\0"
   /* 8156 */ "COMMAND PARSER COMPUTE ENGINE BUSY CCS0\0"
   /* 8196 */ "COMMAND PARSER COMPUTE ENGINE BUSY CCS1\0"
   /* 8236 */ "COMMAND PARSER COMPUTE ENGINE BUSY CCS2\0"
   /* 8276 */ "COMMAND PARSER COMPUTE ENGINE BUSY CCS3\0"
   /* 8316 */ "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT\0"
   /* 8368 */ "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0\0"
   /* 8425 */ "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS1\0"
   /* 8482 */ "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS2\0"
   /* 8539 */ "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS3\0"
   /* 8596 */ "COMMAND PARSER COPY ENGINE BUSY\0"
   /* 8628 */ "COMMAND PARSER FLUSH COUNT\0"
   /* 8655 */ "COMMAND PARSER RENDER ENGINE BUSY\0"
   /* 8689 */ "COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT\0"
   /* 8740 */ "COMMAND PARSER RENDER ENGINE DRAW COUNT\0"
   /* 8780 */ "COMMAND PARSER VIDEO ENGINE BUSY\0"
   /* 8813 */ "COMMAND PARSER VIDEO ENGINE BUSY VDBOX0\0"
   /* 8853 */ "COMMAND PARSER VIDEO ENGINE BUSY VDBOX1\0"
   /* 8893 */ "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY\0"
   /* 8938 */ "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX0\0"
   /* 8990 */ "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX1\0"
   /* 9042 */ "CS AVG Active per Thread\0"
   /* 9067 */ "CS AVG Stall per Thread\0"
   /* 9091 */ "CS Duration\0"
   /* 9103 */ "CS EM Pipe Active\0"
   /* 9121 */ "CS EU Active\0"
   /* 9134 */ "CS EU Stall\0"
   /* 9146 */ "CS FPU Pipe Active\0"
   /* 9165 */ "CS FPU0 Pipe Active\0"
   /* 9185 */ "CS FPU1 Pipe Active\0"
   /* 9205 */ "CS Send Pipe Active\0"
   /* 9225 */ "CS Send Pipeline Active\0"
   /* 9249 */ "CS Threads Dispatched\0"
   /* 9271 */ "Clipper Bottleneck\0"
   /* 9290 */ "Clipper0 Bottleneck\0"
   /* 9310 */ "Clipper1 Bottleneck\0"
   /* 9330 */ "Clipper2 Bottleneck\0"
   /* 9350 */ "Clipper3 Bottleneck\0"
   /* 9370 */ "Clipper4 Bottleneck\0"
   /* 9390 */ "Clipper5 Bottleneck\0"
   /* 9410 */ "Clipper6 Bottleneck\0"
   /* 9430 */ "Clipper7 Bottleneck\0"
   /* 9450 */ "Compute Ring Busy\0"
   /* 9468 */ "ComputeEngine0 Ring Busy\0"
   /* 9493 */ "ComputeEngine1 Ring Busy\0"
   /* 9518 */ "ComputeEngine2 Ring Busy\0"
   /* 9543 */ "ComputeEngine3 Ring Busy\0"
   /* 9568 */ "DATAPORT BYTE READ\0"
   /* 9587 */ "DATAPORT BYTE READ XECORE0\0"
   /* 9614 */ "DATAPORT BYTE READ XECORE1\0"
   /* 9641 */ "DATAPORT BYTE READ XECORE10\0"
   /* 9669 */ "DATAPORT BYTE READ XECORE11\0"
   /* 9697 */ "DATAPORT BYTE READ XECORE12\0"
   /* 9725 */ "DATAPORT BYTE READ XECORE13\0"
   /* 9753 */ "DATAPORT BYTE READ XECORE14\0"
   /* 9781 */ "DATAPORT BYTE READ XECORE15\0"
   /* 9809 */ "DATAPORT BYTE READ XECORE16\0"
   /* 9837 */ "DATAPORT BYTE READ XECORE17\0"
   /* 9865 */ "DATAPORT BYTE READ XECORE18\0"
   /* 9893 */ "DATAPORT BYTE READ XECORE19\0"
   /* 9921 */ "DATAPORT BYTE READ XECORE2\0"
   /* 9948 */ "DATAPORT BYTE READ XECORE20\0"
   /* 9976 */ "DATAPORT BYTE READ XECORE21\0"
   /* 10004 */ "DATAPORT BYTE READ XECORE22\0"
   /* 10032 */ "DATAPORT BYTE READ XECORE23\0"
   /* 10060 */ "DATAPORT BYTE READ XECORE24\0"
   /* 10088 */ "DATAPORT BYTE READ XECORE25\0"
   /* 10116 */ "DATAPORT BYTE READ XECORE26\0"
   /* 10144 */ "DATAPORT BYTE READ XECORE27\0"
   /* 10172 */ "DATAPORT BYTE READ XECORE28\0"
   /* 10200 */ "DATAPORT BYTE READ XECORE29\0"
   /* 10228 */ "DATAPORT BYTE READ XECORE3\0"
   /* 10255 */ "DATAPORT BYTE READ XECORE30\0"
   /* 10283 */ "DATAPORT BYTE READ XECORE31\0"
   /* 10311 */ "DATAPORT BYTE READ XECORE4\0"
   /* 10338 */ "DATAPORT BYTE READ XECORE5\0"
   /* 10365 */ "DATAPORT BYTE READ XECORE6\0"
   /* 10392 */ "DATAPORT BYTE READ XECORE7\0"
   /* 10419 */ "DATAPORT BYTE READ XECORE8\0"
   /* 10446 */ "DATAPORT BYTE READ XECORE9\0"
   /* 10473 */ "DATAPORT BYTE WRITE\0"
   /* 10493 */ "DATAPORT BYTE WRITE XECORE0\0"
   /* 10521 */ "DATAPORT BYTE WRITE XECORE1\0"
   /* 10549 */ "DATAPORT BYTE WRITE XECORE10\0"
   /* 10578 */ "DATAPORT BYTE WRITE XECORE11\0"
   /* 10607 */ "DATAPORT BYTE WRITE XECORE12\0"
   /* 10636 */ "DATAPORT BYTE WRITE XECORE13\0"
   /* 10665 */ "DATAPORT BYTE WRITE XECORE14\0"
   /* 10694 */ "DATAPORT BYTE WRITE XECORE15\0"
   /* 10723 */ "DATAPORT BYTE WRITE XECORE16\0"
   /* 10752 */ "DATAPORT BYTE WRITE XECORE17\0"
   /* 10781 */ "DATAPORT BYTE WRITE XECORE18\0"
   /* 10810 */ "DATAPORT BYTE WRITE XECORE19\0"
   /* 10839 */ "DATAPORT BYTE WRITE XECORE2\0"
   /* 10867 */ "DATAPORT BYTE WRITE XECORE20\0"
   /* 10896 */ "DATAPORT BYTE WRITE XECORE21\0"
   /* 10925 */ "DATAPORT BYTE WRITE XECORE22\0"
   /* 10954 */ "DATAPORT BYTE WRITE XECORE23\0"
   /* 10983 */ "DATAPORT BYTE WRITE XECORE24\0"
   /* 11012 */ "DATAPORT BYTE WRITE XECORE25\0"
   /* 11041 */ "DATAPORT BYTE WRITE XECORE26\0"
   /* 11070 */ "DATAPORT BYTE WRITE XECORE27\0"
   /* 11099 */ "DATAPORT BYTE WRITE XECORE28\0"
   /* 11128 */ "DATAPORT BYTE WRITE XECORE29\0"
   /* 11157 */ "DATAPORT BYTE WRITE XECORE3\0"
   /* 11185 */ "DATAPORT BYTE WRITE XECORE30\0"
   /* 11214 */ "DATAPORT BYTE WRITE XECORE31\0"
   /* 11243 */ "DATAPORT BYTE WRITE XECORE4\0"
   /* 11271 */ "DATAPORT BYTE WRITE XECORE5\0"
   /* 11299 */ "DATAPORT BYTE WRITE XECORE6\0"
   /* 11327 */ "DATAPORT BYTE WRITE XECORE7\0"
   /* 11355 */ "DATAPORT BYTE WRITE XECORE8\0"
   /* 11383 */ "DATAPORT BYTE WRITE XECORE9\0"
   /* 11411 */ "DATAPORT INPUT AVAILABLE XECORE0\0"
   /* 11444 */ "DATAPORT INPUT AVAILABLE XECORE1\0"
   /* 11477 */ "DATAPORT INPUT AVAILABLE XECORE10\0"
   /* 11511 */ "DATAPORT INPUT AVAILABLE XECORE11\0"
   /* 11545 */ "DATAPORT INPUT AVAILABLE XECORE12\0"
   /* 11579 */ "DATAPORT INPUT AVAILABLE XECORE13\0"
   /* 11613 */ "DATAPORT INPUT AVAILABLE XECORE14\0"
   /* 11647 */ "DATAPORT INPUT AVAILABLE XECORE15\0"
   /* 11681 */ "DATAPORT INPUT AVAILABLE XECORE16\0"
   /* 11715 */ "DATAPORT INPUT AVAILABLE XECORE17\0"
   /* 11749 */ "DATAPORT INPUT AVAILABLE XECORE18\0"
   /* 11783 */ "DATAPORT INPUT AVAILABLE XECORE19\0"
   /* 11817 */ "DATAPORT INPUT AVAILABLE XECORE2\0"
   /* 11850 */ "DATAPORT INPUT AVAILABLE XECORE20\0"
   /* 11884 */ "DATAPORT INPUT AVAILABLE XECORE21\0"
   /* 11918 */ "DATAPORT INPUT AVAILABLE XECORE22\0"
   /* 11952 */ "DATAPORT INPUT AVAILABLE XECORE23\0"
   /* 11986 */ "DATAPORT INPUT AVAILABLE XECORE24\0"
   /* 12020 */ "DATAPORT INPUT AVAILABLE XECORE25\0"
   /* 12054 */ "DATAPORT INPUT AVAILABLE XECORE26\0"
   /* 12088 */ "DATAPORT INPUT AVAILABLE XECORE27\0"
   /* 12122 */ "DATAPORT INPUT AVAILABLE XECORE28\0"
   /* 12156 */ "DATAPORT INPUT AVAILABLE XECORE29\0"
   /* 12190 */ "DATAPORT INPUT AVAILABLE XECORE3\0"
   /* 12223 */ "DATAPORT INPUT AVAILABLE XECORE30\0"
   /* 12257 */ "DATAPORT INPUT AVAILABLE XECORE31\0"
   /* 12291 */ "DATAPORT INPUT AVAILABLE XECORE4\0"
   /* 12324 */ "DATAPORT INPUT AVAILABLE XECORE5\0"
   /* 12357 */ "DATAPORT INPUT AVAILABLE XECORE6\0"
   /* 12390 */ "DATAPORT INPUT AVAILABLE XECORE7\0"
   /* 12423 */ "DATAPORT INPUT AVAILABLE XECORE8\0"
   /* 12456 */ "DATAPORT INPUT AVAILABLE XECORE9\0"
   /* 12489 */ "DATAPORT L3 HIT L3BANK0\0"
   /* 12513 */ "DATAPORT L3 HIT L3BANK1\0"
   /* 12537 */ "DATAPORT L3 HIT L3BANK10\0"
   /* 12562 */ "DATAPORT L3 HIT L3BANK11\0"
   /* 12587 */ "DATAPORT L3 HIT L3BANK12\0"
   /* 12612 */ "DATAPORT L3 HIT L3BANK13\0"
   /* 12637 */ "DATAPORT L3 HIT L3BANK14\0"
   /* 12662 */ "DATAPORT L3 HIT L3BANK15\0"
   /* 12687 */ "DATAPORT L3 HIT L3BANK16\0"
   /* 12712 */ "DATAPORT L3 HIT L3BANK17\0"
   /* 12737 */ "DATAPORT L3 HIT L3BANK18\0"
   /* 12762 */ "DATAPORT L3 HIT L3BANK19\0"
   /* 12787 */ "DATAPORT L3 HIT L3BANK2\0"
   /* 12811 */ "DATAPORT L3 HIT L3BANK20\0"
   /* 12836 */ "DATAPORT L3 HIT L3BANK21\0"
   /* 12861 */ "DATAPORT L3 HIT L3BANK22\0"
   /* 12886 */ "DATAPORT L3 HIT L3BANK23\0"
   /* 12911 */ "DATAPORT L3 HIT L3BANK24\0"
   /* 12936 */ "DATAPORT L3 HIT L3BANK25\0"
   /* 12961 */ "DATAPORT L3 HIT L3BANK26\0"
   /* 12986 */ "DATAPORT L3 HIT L3BANK27\0"
   /* 13011 */ "DATAPORT L3 HIT L3BANK28\0"
   /* 13036 */ "DATAPORT L3 HIT L3BANK29\0"
   /* 13061 */ "DATAPORT L3 HIT L3BANK3\0"
   /* 13085 */ "DATAPORT L3 HIT L3BANK30\0"
   /* 13110 */ "DATAPORT L3 HIT L3BANK31\0"
   /* 13135 */ "DATAPORT L3 HIT L3BANK4\0"
   /* 13159 */ "DATAPORT L3 HIT L3BANK5\0"
   /* 13183 */ "DATAPORT L3 HIT L3BANK6\0"
   /* 13207 */ "DATAPORT L3 HIT L3BANK7\0"
   /* 13231 */ "DATAPORT L3 HIT L3BANK8\0"
   /* 13255 */ "DATAPORT L3 HIT L3BANK9\0"
   /* 13279 */ "DATAPORT L3 READ L3BANK0\0"
   /* 13304 */ "DATAPORT L3 READ L3BANK1\0"
   /* 13329 */ "DATAPORT L3 READ L3BANK10\0"
   /* 13355 */ "DATAPORT L3 READ L3BANK11\0"
   /* 13381 */ "DATAPORT L3 READ L3BANK12\0"
   /* 13407 */ "DATAPORT L3 READ L3BANK13\0"
   /* 13433 */ "DATAPORT L3 READ L3BANK14\0"
   /* 13459 */ "DATAPORT L3 READ L3BANK15\0"
   /* 13485 */ "DATAPORT L3 READ L3BANK16\0"
   /* 13511 */ "DATAPORT L3 READ L3BANK17\0"
   /* 13537 */ "DATAPORT L3 READ L3BANK18\0"
   /* 13563 */ "DATAPORT L3 READ L3BANK19\0"
   /* 13589 */ "DATAPORT L3 READ L3BANK2\0"
   /* 13614 */ "DATAPORT L3 READ L3BANK20\0"
   /* 13640 */ "DATAPORT L3 READ L3BANK21\0"
   /* 13666 */ "DATAPORT L3 READ L3BANK22\0"
   /* 13692 */ "DATAPORT L3 READ L3BANK23\0"
   /* 13718 */ "DATAPORT L3 READ L3BANK24\0"
   /* 13744 */ "DATAPORT L3 READ L3BANK25\0"
   /* 13770 */ "DATAPORT L3 READ L3BANK26\0"
   /* 13796 */ "DATAPORT L3 READ L3BANK27\0"
   /* 13822 */ "DATAPORT L3 READ L3BANK28\0"
   /* 13848 */ "DATAPORT L3 READ L3BANK29\0"
   /* 13874 */ "DATAPORT L3 READ L3BANK3\0"
   /* 13899 */ "DATAPORT L3 READ L3BANK30\0"
   /* 13925 */ "DATAPORT L3 READ L3BANK31\0"
   /* 13951 */ "DATAPORT L3 READ L3BANK4\0"
   /* 13976 */ "DATAPORT L3 READ L3BANK5\0"
   /* 14001 */ "DATAPORT L3 READ L3BANK6\0"
   /* 14026 */ "DATAPORT L3 READ L3BANK7\0"
   /* 14051 */ "DATAPORT L3 READ L3BANK8\0"
   /* 14076 */ "DATAPORT L3 READ L3BANK9\0"
   /* 14101 */ "DATAPORT L3 WRITE L3BANK0\0"
   /* 14127 */ "DATAPORT L3 WRITE L3BANK1\0"
   /* 14153 */ "DATAPORT L3 WRITE L3BANK10\0"
   /* 14180 */ "DATAPORT L3 WRITE L3BANK11\0"
   /* 14207 */ "DATAPORT L3 WRITE L3BANK12\0"
   /* 14234 */ "DATAPORT L3 WRITE L3BANK13\0"
   /* 14261 */ "DATAPORT L3 WRITE L3BANK14\0"
   /* 14288 */ "DATAPORT L3 WRITE L3BANK15\0"
   /* 14315 */ "DATAPORT L3 WRITE L3BANK16\0"
   /* 14342 */ "DATAPORT L3 WRITE L3BANK17\0"
   /* 14369 */ "DATAPORT L3 WRITE L3BANK18\0"
   /* 14396 */ "DATAPORT L3 WRITE L3BANK19\0"
   /* 14423 */ "DATAPORT L3 WRITE L3BANK2\0"
   /* 14449 */ "DATAPORT L3 WRITE L3BANK20\0"
   /* 14476 */ "DATAPORT L3 WRITE L3BANK21\0"
   /* 14503 */ "DATAPORT L3 WRITE L3BANK22\0"
   /* 14530 */ "DATAPORT L3 WRITE L3BANK23\0"
   /* 14557 */ "DATAPORT L3 WRITE L3BANK24\0"
   /* 14584 */ "DATAPORT L3 WRITE L3BANK25\0"
   /* 14611 */ "DATAPORT L3 WRITE L3BANK26\0"
   /* 14638 */ "DATAPORT L3 WRITE L3BANK27\0"
   /* 14665 */ "DATAPORT L3 WRITE L3BANK28\0"
   /* 14692 */ "DATAPORT L3 WRITE L3BANK29\0"
   /* 14719 */ "DATAPORT L3 WRITE L3BANK3\0"
   /* 14745 */ "DATAPORT L3 WRITE L3BANK30\0"
   /* 14772 */ "DATAPORT L3 WRITE L3BANK31\0"
   /* 14799 */ "DATAPORT L3 WRITE L3BANK4\0"
   /* 14825 */ "DATAPORT L3 WRITE L3BANK5\0"
   /* 14851 */ "DATAPORT L3 WRITE L3BANK6\0"
   /* 14877 */ "DATAPORT L3 WRITE L3BANK7\0"
   /* 14903 */ "DATAPORT L3 WRITE L3BANK8\0"
   /* 14929 */ "DATAPORT L3 WRITE L3BANK9\0"
   /* 14955 */ "DATAPORT OUTPUT READY XECORE0\0"
   /* 14985 */ "DATAPORT OUTPUT READY XECORE1\0"
   /* 15015 */ "DATAPORT OUTPUT READY XECORE10\0"
   /* 15046 */ "DATAPORT OUTPUT READY XECORE11\0"
   /* 15077 */ "DATAPORT OUTPUT READY XECORE12\0"
   /* 15108 */ "DATAPORT OUTPUT READY XECORE13\0"
   /* 15139 */ "DATAPORT OUTPUT READY XECORE14\0"
   /* 15170 */ "DATAPORT OUTPUT READY XECORE15\0"
   /* 15201 */ "DATAPORT OUTPUT READY XECORE16\0"
   /* 15232 */ "DATAPORT OUTPUT READY XECORE17\0"
   /* 15263 */ "DATAPORT OUTPUT READY XECORE18\0"
   /* 15294 */ "DATAPORT OUTPUT READY XECORE19\0"
   /* 15325 */ "DATAPORT OUTPUT READY XECORE2\0"
   /* 15355 */ "DATAPORT OUTPUT READY XECORE20\0"
   /* 15386 */ "DATAPORT OUTPUT READY XECORE21\0"
   /* 15417 */ "DATAPORT OUTPUT READY XECORE22\0"
   /* 15448 */ "DATAPORT OUTPUT READY XECORE23\0"
   /* 15479 */ "DATAPORT OUTPUT READY XECORE24\0"
   /* 15510 */ "DATAPORT OUTPUT READY XECORE25\0"
   /* 15541 */ "DATAPORT OUTPUT READY XECORE26\0"
   /* 15572 */ "DATAPORT OUTPUT READY XECORE27\0"
   /* 15603 */ "DATAPORT OUTPUT READY XECORE28\0"
   /* 15634 */ "DATAPORT OUTPUT READY XECORE29\0"
   /* 15665 */ "DATAPORT OUTPUT READY XECORE3\0"
   /* 15695 */ "DATAPORT OUTPUT READY XECORE30\0"
   /* 15726 */ "DATAPORT OUTPUT READY XECORE31\0"
   /* 15757 */ "DATAPORT OUTPUT READY XECORE4\0"
   /* 15787 */ "DATAPORT OUTPUT READY XECORE5\0"
   /* 15817 */ "DATAPORT OUTPUT READY XECORE6\0"
   /* 15847 */ "DATAPORT OUTPUT READY XECORE7\0"
   /* 15877 */ "DATAPORT OUTPUT READY XECORE8\0"
   /* 15907 */ "DATAPORT OUTPUT READY XECORE9\0"
   /* 15937 */ "DATAPORT TEXTURE CACHE ACCESS XECORE0\0"
   /* 15975 */ "DATAPORT TEXTURE CACHE ACCESS XECORE1\0"
   /* 16013 */ "DATAPORT TEXTURE CACHE ACCESS XECORE10\0"
   /* 16052 */ "DATAPORT TEXTURE CACHE ACCESS XECORE11\0"
   /* 16091 */ "DATAPORT TEXTURE CACHE ACCESS XECORE12\0"
   /* 16130 */ "DATAPORT TEXTURE CACHE ACCESS XECORE13\0"
   /* 16169 */ "DATAPORT TEXTURE CACHE ACCESS XECORE14\0"
   /* 16208 */ "DATAPORT TEXTURE CACHE ACCESS XECORE15\0"
   /* 16247 */ "DATAPORT TEXTURE CACHE ACCESS XECORE16\0"
   /* 16286 */ "DATAPORT TEXTURE CACHE ACCESS XECORE17\0"
   /* 16325 */ "DATAPORT TEXTURE CACHE ACCESS XECORE18\0"
   /* 16364 */ "DATAPORT TEXTURE CACHE ACCESS XECORE19\0"
   /* 16403 */ "DATAPORT TEXTURE CACHE ACCESS XECORE2\0"
   /* 16441 */ "DATAPORT TEXTURE CACHE ACCESS XECORE20\0"
   /* 16480 */ "DATAPORT TEXTURE CACHE ACCESS XECORE21\0"
   /* 16519 */ "DATAPORT TEXTURE CACHE ACCESS XECORE22\0"
   /* 16558 */ "DATAPORT TEXTURE CACHE ACCESS XECORE23\0"
   /* 16597 */ "DATAPORT TEXTURE CACHE ACCESS XECORE24\0"
   /* 16636 */ "DATAPORT TEXTURE CACHE ACCESS XECORE25\0"
   /* 16675 */ "DATAPORT TEXTURE CACHE ACCESS XECORE26\0"
   /* 16714 */ "DATAPORT TEXTURE CACHE ACCESS XECORE27\0"
   /* 16753 */ "DATAPORT TEXTURE CACHE ACCESS XECORE28\0"
   /* 16792 */ "DATAPORT TEXTURE CACHE ACCESS XECORE29\0"
   /* 16831 */ "DATAPORT TEXTURE CACHE ACCESS XECORE3\0"
   /* 16869 */ "DATAPORT TEXTURE CACHE ACCESS XECORE30\0"
   /* 16908 */ "DATAPORT TEXTURE CACHE ACCESS XECORE31\0"
   /* 16947 */ "DATAPORT TEXTURE CACHE ACCESS XECORE4\0"
   /* 16985 */ "DATAPORT TEXTURE CACHE ACCESS XECORE5\0"
   /* 17023 */ "DATAPORT TEXTURE CACHE ACCESS XECORE6\0"
   /* 17061 */ "DATAPORT TEXTURE CACHE ACCESS XECORE7\0"
   /* 17099 */ "DATAPORT TEXTURE CACHE ACCESS XECORE8\0"
   /* 17137 */ "DATAPORT TEXTURE CACHE ACCESS XECORE9\0"
   /* 17175 */ "DATAPORT TEXTURE CACHE HIT XECORE0\0"
   /* 17210 */ "DATAPORT TEXTURE CACHE HIT XECORE1\0"
   /* 17245 */ "DATAPORT TEXTURE CACHE HIT XECORE10\0"
   /* 17281 */ "DATAPORT TEXTURE CACHE HIT XECORE11\0"
   /* 17317 */ "DATAPORT TEXTURE CACHE HIT XECORE12\0"
   /* 17353 */ "DATAPORT TEXTURE CACHE HIT XECORE13\0"
   /* 17389 */ "DATAPORT TEXTURE CACHE HIT XECORE14\0"
   /* 17425 */ "DATAPORT TEXTURE CACHE HIT XECORE15\0"
   /* 17461 */ "DATAPORT TEXTURE CACHE HIT XECORE16\0"
   /* 17497 */ "DATAPORT TEXTURE CACHE HIT XECORE17\0"
   /* 17533 */ "DATAPORT TEXTURE CACHE HIT XECORE18\0"
   /* 17569 */ "DATAPORT TEXTURE CACHE HIT XECORE19\0"
   /* 17605 */ "DATAPORT TEXTURE CACHE HIT XECORE2\0"
   /* 17640 */ "DATAPORT TEXTURE CACHE HIT XECORE20\0"
   /* 17676 */ "DATAPORT TEXTURE CACHE HIT XECORE21\0"
   /* 17712 */ "DATAPORT TEXTURE CACHE HIT XECORE22\0"
   /* 17748 */ "DATAPORT TEXTURE CACHE HIT XECORE23\0"
   /* 17784 */ "DATAPORT TEXTURE CACHE HIT XECORE24\0"
   /* 17820 */ "DATAPORT TEXTURE CACHE HIT XECORE25\0"
   /* 17856 */ "DATAPORT TEXTURE CACHE HIT XECORE26\0"
   /* 17892 */ "DATAPORT TEXTURE CACHE HIT XECORE27\0"
   /* 17928 */ "DATAPORT TEXTURE CACHE HIT XECORE28\0"
   /* 17964 */ "DATAPORT TEXTURE CACHE HIT XECORE29\0"
   /* 18000 */ "DATAPORT TEXTURE CACHE HIT XECORE3\0"
   /* 18035 */ "DATAPORT TEXTURE CACHE HIT XECORE30\0"
   /* 18071 */ "DATAPORT TEXTURE CACHE HIT XECORE31\0"
   /* 18107 */ "DATAPORT TEXTURE CACHE HIT XECORE4\0"
   /* 18142 */ "DATAPORT TEXTURE CACHE HIT XECORE5\0"
   /* 18177 */ "DATAPORT TEXTURE CACHE HIT XECORE6\0"
   /* 18212 */ "DATAPORT TEXTURE CACHE HIT XECORE7\0"
   /* 18247 */ "DATAPORT TEXTURE CACHE HIT XECORE8\0"
   /* 18282 */ "DATAPORT TEXTURE CACHE HIT XECORE9\0"
   /* 18317 */ "DS Bottleneck\0"
   /* 18331 */ "DS EM Pipe Active\0"
   /* 18349 */ "DS FPU Pipe Active\0"
   /* 18368 */ "DS Send Pipe Active\0"
   /* 18388 */ "DS Stall\0"
   /* 18397 */ "DS Threads Dispatched\0"
   /* 18419 */ "DS0 Bottleneck\0"
   /* 18434 */ "DS0 Stall\0"
   /* 18444 */ "DS1 Bottleneck\0"
   /* 18459 */ "DS1 Stall\0"
   /* 18469 */ "DS2 Bottleneck\0"
   /* 18484 */ "DS2 Stall\0"
   /* 18494 */ "DS3 Bottleneck\0"
   /* 18509 */ "DS3 Stall\0"
   /* 18519 */ "DS4 Bottleneck\0"
   /* 18534 */ "DS4 Stall\0"
   /* 18544 */ "DS5 Bottleneck\0"
   /* 18559 */ "DS5 Stall\0"
   /* 18569 */ "DS6 Bottleneck\0"
   /* 18584 */ "DS6 Stall\0"
   /* 18594 */ "DS7 Bottleneck\0"
   /* 18609 */ "DS7 Stall\0"
   /* 18619 */ "Data Port 0 to L3 Data Reads\0"
   /* 18648 */ "Data Port 0 to L3 Data Writes\0"
   /* 18678 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0\0"
   /* 18718 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1\0"
   /* 18758 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE10\0"
   /* 18799 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE11\0"
   /* 18840 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE12\0"
   /* 18881 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE13\0"
   /* 18922 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE14\0"
   /* 18963 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE15\0"
   /* 19004 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2\0"
   /* 19044 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3\0"
   /* 19084 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE4\0"
   /* 19124 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE5\0"
   /* 19164 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE6\0"
   /* 19204 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE7\0"
   /* 19244 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE8\0"
   /* 19284 */ "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE9\0"
   /* 19324 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE0\0"
   /* 19363 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE1\0"
   /* 19402 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE10\0"
   /* 19442 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE11\0"
   /* 19482 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE12\0"
   /* 19522 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE13\0"
   /* 19562 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE14\0"
   /* 19602 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE15\0"
   /* 19642 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE2\0"
   /* 19681 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE3\0"
   /* 19720 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE4\0"
   /* 19759 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE5\0"
   /* 19798 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE6\0"
   /* 19837 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE7\0"
   /* 19876 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE8\0"
   /* 19915 */ "EARLY DEPTH STENCIL TEST FAIL P ZPIPE9\0"
   /* 19954 */ "EM And FPU Pipes Active\0"
   /* 19978 */ "EM Pipe Active\0"
   /* 19993 */ "EU AVG IPC Rate\0"
   /* 20009 */ "EU Active\0"
   /* 20019 */ "EU Both FPU Pipes Active\0"
   /* 20044 */ "EU FPU And EM Pipes Active\0"
   /* 20071 */ "EU FPU Pipe Active\0"
   /* 20090 */ "EU FPU0 Binary Instruction\0"
   /* 20117 */ "EU FPU0 Hybrid Instruction\0"
   /* 20144 */ "EU FPU0 Move Instruction\0"
   /* 20169 */ "EU FPU0 Pipe Active\0"
   /* 20189 */ "EU FPU0 Ternary Instruction\0"
   /* 20217 */ "EU FPU1 Binary Instruction\0"
   /* 20244 */ "EU FPU1 Hybrid Instruction\0"
   /* 20271 */ "EU FPU1 Move Instruction\0"
   /* 20296 */ "EU FPU1 Pipe Active\0"
   /* 20316 */ "EU FPU1 Pipe Active including Ext Math\0"
   /* 20355 */ "EU FPU1 Ternary Instruction\0"
   /* 20383 */ "EU Idle\0"
   /* 20391 */ "EU Send Pipe Active\0"
   /* 20411 */ "EU Stall\0"
   /* 20420 */ "EU Thread Occupancy\0"
   /* 20440 */ "EU to Data Port 0 Reads 128\0"
   /* 20468 */ "EU to Data Port 0 Reads 256\0"
   /* 20496 */ "EU to Data Port 0 Reads 32\0"
   /* 20523 */ "EU to Data Port 0 Reads 64\0"
   /* 20550 */ "EU to Data Port 0 Writes 128\0"
   /* 20579 */ "EU to Data Port 0 Writes 256B\0"
   /* 20609 */ "EU to Data Port 0 Writes 32B\0"
   /* 20638 */ "EU to Data Port 0 Writes 64B\0"
   /* 20667 */ "Early Depth Bottleneck\0"
   /* 20690 */ "Early Depth Test Fails\0"
   /* 20713 */ "Early Hi-Depth Test Fails\0"
   /* 20739 */ "Eu 64 Untyped Reads 00\0"
   /* 20762 */ "Eu A32 Untyped Reads 00\0"
   /* 20786 */ "Eu A32 Untyped Writes 00\0"
   /* 20811 */ "Eu A64 Untyped Writes 00\0"
   /* 20836 */ "Eu Typed Atomics 00\0"
   /* 20856 */ "Eu Typed Reads 00\0"
   /* 20874 */ "Eu Typed Writes 00\0"
   /* 20893 */ "EuA64UntypedReads0\0"
   /* 20912 */ "EuA64UntypedWrites0\0"
   /* 20932 */ "EuBytesReadPerCacheLine\0"
   /* 20956 */ "EuBytesWrittenPerCacheLine\0"
   /* 20983 */ "EuDataReadsPerCacheLine\0"
   /* 21007 */ "EuDataWritesPerCacheLine\0"
   /* 21032 */ "EuTypedAtomics0\0"
   /* 21048 */ "EuTypedReads0\0"
   /* 21062 */ "EuTypedWrites0\0"
   /* 21077 */ "EuUntypedAtomics0\0"
   /* 21095 */ "EuUntypedReads0\0"
   /* 21111 */ "EuUntypedWrites0\0"
   /* 21128 */ "EuUrbAtomics0\0"
   /* 21142 */ "FPU FLT16 Instruction\0"
   /* 21164 */ "FPU FLT32 Instruction\0"
   /* 21186 */ "FPU FLT64 Instruction\0"
   /* 21208 */ "FS AVG Active per Thread\0"
   /* 21233 */ "FS AVG Stall per Thread\0"
   /* 21257 */ "FS Both FPU Active\0"
   /* 21276 */ "FS Duration\0"
   /* 21288 */ "FS EM Pipe Active\0"
   /* 21306 */ "FS EU Active\0"
   /* 21319 */ "FS EU Stall\0"
   /* 21331 */ "FS FPU Pipe Active\0"
   /* 21350 */ "FS Send Pipe Active\0"
   /* 21370 */ "FS Threads Dispatched\0"
   /* 21392 */ "GPGPU DISPATCH XECORE0\0"
   /* 21415 */ "GPGPU DISPATCH XECORE1\0"
   /* 21438 */ "GPGPU DISPATCH XECORE10\0"
   /* 21462 */ "GPGPU DISPATCH XECORE11\0"
   /* 21486 */ "GPGPU DISPATCH XECORE12\0"
   /* 21510 */ "GPGPU DISPATCH XECORE13\0"
   /* 21534 */ "GPGPU DISPATCH XECORE14\0"
   /* 21558 */ "GPGPU DISPATCH XECORE15\0"
   /* 21582 */ "GPGPU DISPATCH XECORE16\0"
   /* 21606 */ "GPGPU DISPATCH XECORE17\0"
   /* 21630 */ "GPGPU DISPATCH XECORE18\0"
   /* 21654 */ "GPGPU DISPATCH XECORE19\0"
   /* 21678 */ "GPGPU DISPATCH XECORE2\0"
   /* 21701 */ "GPGPU DISPATCH XECORE20\0"
   /* 21725 */ "GPGPU DISPATCH XECORE21\0"
   /* 21749 */ "GPGPU DISPATCH XECORE22\0"
   /* 21773 */ "GPGPU DISPATCH XECORE23\0"
   /* 21797 */ "GPGPU DISPATCH XECORE24\0"
   /* 21821 */ "GPGPU DISPATCH XECORE25\0"
   /* 21845 */ "GPGPU DISPATCH XECORE26\0"
   /* 21869 */ "GPGPU DISPATCH XECORE27\0"
   /* 21893 */ "GPGPU DISPATCH XECORE28\0"
   /* 21917 */ "GPGPU DISPATCH XECORE29\0"
   /* 21941 */ "GPGPU DISPATCH XECORE3\0"
   /* 21964 */ "GPGPU DISPATCH XECORE30\0"
   /* 21988 */ "GPGPU DISPATCH XECORE31\0"
   /* 22012 */ "GPGPU DISPATCH XECORE4\0"
   /* 22035 */ "GPGPU DISPATCH XECORE5\0"
   /* 22058 */ "GPGPU DISPATCH XECORE6\0"
   /* 22081 */ "GPGPU DISPATCH XECORE7\0"
   /* 22104 */ "GPGPU DISPATCH XECORE8\0"
   /* 22127 */ "GPGPU DISPATCH XECORE9\0"
   /* 22150 */ "GPGPU THREADGROUP COUNT XECORE0\0"
   /* 22182 */ "GPGPU THREADGROUP COUNT XECORE1\0"
   /* 22214 */ "GPGPU THREADGROUP COUNT XECORE10\0"
   /* 22247 */ "GPGPU THREADGROUP COUNT XECORE11\0"
   /* 22280 */ "GPGPU THREADGROUP COUNT XECORE12\0"
   /* 22313 */ "GPGPU THREADGROUP COUNT XECORE13\0"
   /* 22346 */ "GPGPU THREADGROUP COUNT XECORE14\0"
   /* 22379 */ "GPGPU THREADGROUP COUNT XECORE15\0"
   /* 22412 */ "GPGPU THREADGROUP COUNT XECORE16\0"
   /* 22445 */ "GPGPU THREADGROUP COUNT XECORE17\0"
   /* 22478 */ "GPGPU THREADGROUP COUNT XECORE18\0"
   /* 22511 */ "GPGPU THREADGROUP COUNT XECORE19\0"
   /* 22544 */ "GPGPU THREADGROUP COUNT XECORE2\0"
   /* 22576 */ "GPGPU THREADGROUP COUNT XECORE20\0"
   /* 22609 */ "GPGPU THREADGROUP COUNT XECORE21\0"
   /* 22642 */ "GPGPU THREADGROUP COUNT XECORE22\0"
   /* 22675 */ "GPGPU THREADGROUP COUNT XECORE23\0"
   /* 22708 */ "GPGPU THREADGROUP COUNT XECORE24\0"
   /* 22741 */ "GPGPU THREADGROUP COUNT XECORE25\0"
   /* 22774 */ "GPGPU THREADGROUP COUNT XECORE26\0"
   /* 22807 */ "GPGPU THREADGROUP COUNT XECORE27\0"
   /* 22840 */ "GPGPU THREADGROUP COUNT XECORE28\0"
   /* 22873 */ "GPGPU THREADGROUP COUNT XECORE29\0"
   /* 22906 */ "GPGPU THREADGROUP COUNT XECORE3\0"
   /* 22938 */ "GPGPU THREADGROUP COUNT XECORE30\0"
   /* 22971 */ "GPGPU THREADGROUP COUNT XECORE31\0"
   /* 23004 */ "GPGPU THREADGROUP COUNT XECORE4\0"
   /* 23036 */ "GPGPU THREADGROUP COUNT XECORE5\0"
   /* 23068 */ "GPGPU THREADGROUP COUNT XECORE6\0"
   /* 23100 */ "GPGPU THREADGROUP COUNT XECORE7\0"
   /* 23132 */ "GPGPU THREADGROUP COUNT XECORE8\0"
   /* 23164 */ "GPGPU THREADGROUP COUNT XECORE9\0"
   /* 23196 */ "GPU Busy\0"
   /* 23205 */ "GPU Core Clocks\0"
   /* 23221 */ "GPU MEMORY 32B TRANSACTION READ\0"
   /* 23253 */ "GPU MEMORY 32B TRANSACTION READ SQIDI0\0"
   /* 23292 */ "GPU MEMORY 32B TRANSACTION READ SQIDI1\0"
   /* 23331 */ "GPU MEMORY 32B TRANSACTION READ SQIDI2\0"
   /* 23370 */ "GPU MEMORY 32B TRANSACTION READ SQIDI3\0"
   /* 23409 */ "GPU MEMORY 32B TRANSACTION READ SQIDI4\0"
   /* 23448 */ "GPU MEMORY 32B TRANSACTION READ SQIDI5\0"
   /* 23487 */ "GPU MEMORY 32B TRANSACTION READ SQIDI6\0"
   /* 23526 */ "GPU MEMORY 32B TRANSACTION READ SQIDI7\0"
   /* 23565 */ "GPU MEMORY 32B TRANSACTION WRITE\0"
   /* 23598 */ "GPU MEMORY 32B TRANSACTION WRITE SQIDI0\0"
   /* 23638 */ "GPU MEMORY 32B TRANSACTION WRITE SQIDI1\0"
   /* 23678 */ "GPU MEMORY 32B TRANSACTION WRITE SQIDI2\0"
   /* 23718 */ "GPU MEMORY 32B TRANSACTION WRITE SQIDI3\0"
   /* 23758 */ "GPU MEMORY 32B TRANSACTION WRITE SQIDI4\0"
   /* 23798 */ "GPU MEMORY 32B TRANSACTION WRITE SQIDI5\0"
   /* 23838 */ "GPU MEMORY 32B TRANSACTION WRITE SQIDI6\0"
   /* 23878 */ "GPU MEMORY 32B TRANSACTION WRITE SQIDI7\0"
   /* 23918 */ "GPU MEMORY 64B TRANSACTION READ\0"
   /* 23950 */ "GPU MEMORY 64B TRANSACTION READ SQIDI0\0"
   /* 23989 */ "GPU MEMORY 64B TRANSACTION READ SQIDI1\0"
   /* 24028 */ "GPU MEMORY 64B TRANSACTION READ SQIDI2\0"
   /* 24067 */ "GPU MEMORY 64B TRANSACTION READ SQIDI3\0"
   /* 24106 */ "GPU MEMORY 64B TRANSACTION READ SQIDI4\0"
   /* 24145 */ "GPU MEMORY 64B TRANSACTION READ SQIDI5\0"
   /* 24184 */ "GPU MEMORY 64B TRANSACTION READ SQIDI6\0"
   /* 24223 */ "GPU MEMORY 64B TRANSACTION READ SQIDI7\0"
   /* 24262 */ "GPU MEMORY 64B TRANSACTION WRITE\0"
   /* 24295 */ "GPU MEMORY 64B TRANSACTION WRITE SQIDI0\0"
   /* 24335 */ "GPU MEMORY 64B TRANSACTION WRITE SQIDI1\0"
   /* 24375 */ "GPU MEMORY 64B TRANSACTION WRITE SQIDI2\0"
   /* 24415 */ "GPU MEMORY 64B TRANSACTION WRITE SQIDI3\0"
   /* 24455 */ "GPU MEMORY 64B TRANSACTION WRITE SQIDI4\0"
   /* 24495 */ "GPU MEMORY 64B TRANSACTION WRITE SQIDI5\0"
   /* 24535 */ "GPU MEMORY 64B TRANSACTION WRITE SQIDI6\0"
   /* 24575 */ "GPU MEMORY 64B TRANSACTION WRITE SQIDI7\0"
   /* 24615 */ "GPU MEMORY ACTIVE\0"
   /* 24633 */ "GPU MEMORY ACTIVE SQIDI0\0"
   /* 24658 */ "GPU MEMORY ACTIVE SQIDI1\0"
   /* 24683 */ "GPU MEMORY ACTIVE SQIDI2\0"
   /* 24708 */ "GPU MEMORY ACTIVE SQIDI3\0"
   /* 24733 */ "GPU MEMORY ACTIVE SQIDI4\0"
   /* 24758 */ "GPU MEMORY ACTIVE SQIDI5\0"
   /* 24783 */ "GPU MEMORY ACTIVE SQIDI6\0"
   /* 24808 */ "GPU MEMORY ACTIVE SQIDI7\0"
   /* 24833 */ "GPU MEMORY BYTE READ\0"
   /* 24854 */ "GPU MEMORY BYTE READ BW\0"
   /* 24878 */ "GPU MEMORY BYTE READ BW SQIDI0\0"
   /* 24909 */ "GPU MEMORY BYTE READ BW SQIDI1\0"
   /* 24940 */ "GPU MEMORY BYTE READ BW SQIDI2\0"
   /* 24971 */ "GPU MEMORY BYTE READ BW SQIDI3\0"
   /* 25002 */ "GPU MEMORY BYTE READ BW SQIDI4\0"
   /* 25033 */ "GPU MEMORY BYTE READ BW SQIDI5\0"
   /* 25064 */ "GPU MEMORY BYTE READ BW SQIDI6\0"
   /* 25095 */ "GPU MEMORY BYTE READ BW SQIDI7\0"
   /* 25126 */ "GPU MEMORY BYTE READ SQIDI0\0"
   /* 25154 */ "GPU MEMORY BYTE READ SQIDI1\0"
   /* 25182 */ "GPU MEMORY BYTE READ SQIDI2\0"
   /* 25210 */ "GPU MEMORY BYTE READ SQIDI3\0"
   /* 25238 */ "GPU MEMORY BYTE READ SQIDI4\0"
   /* 25266 */ "GPU MEMORY BYTE READ SQIDI5\0"
   /* 25294 */ "GPU MEMORY BYTE READ SQIDI6\0"
   /* 25322 */ "GPU MEMORY BYTE READ SQIDI7\0"
   /* 25350 */ "GPU MEMORY BYTE WRITE\0"
   /* 25372 */ "GPU MEMORY BYTE WRITE BW\0"
   /* 25397 */ "GPU MEMORY BYTE WRITE BW SQIDI0\0"
   /* 25429 */ "GPU MEMORY BYTE WRITE BW SQIDI1\0"
   /* 25461 */ "GPU MEMORY BYTE WRITE BW SQIDI2\0"
   /* 25493 */ "GPU MEMORY BYTE WRITE BW SQIDI3\0"
   /* 25525 */ "GPU MEMORY BYTE WRITE BW SQIDI4\0"
   /* 25557 */ "GPU MEMORY BYTE WRITE BW SQIDI5\0"
   /* 25589 */ "GPU MEMORY BYTE WRITE BW SQIDI6\0"
   /* 25621 */ "GPU MEMORY BYTE WRITE BW SQIDI7\0"
   /* 25653 */ "GPU MEMORY BYTE WRITE SQIDI0\0"
   /* 25682 */ "GPU MEMORY BYTE WRITE SQIDI1\0"
   /* 25711 */ "GPU MEMORY BYTE WRITE SQIDI2\0"
   /* 25740 */ "GPU MEMORY BYTE WRITE SQIDI3\0"
   /* 25769 */ "GPU MEMORY BYTE WRITE SQIDI4\0"
   /* 25798 */ "GPU MEMORY BYTE WRITE SQIDI5\0"
   /* 25827 */ "GPU MEMORY BYTE WRITE SQIDI6\0"
   /* 25856 */ "GPU MEMORY BYTE WRITE SQIDI7\0"
   /* 25885 */ "GPU MEMORY L3 READ SQIDI0\0"
   /* 25911 */ "GPU MEMORY L3 READ SQIDI1\0"
   /* 25937 */ "GPU MEMORY L3 READ SQIDI2\0"
   /* 25963 */ "GPU MEMORY L3 READ SQIDI3\0"
   /* 25989 */ "GPU MEMORY L3 READ SQIDI4\0"
   /* 26015 */ "GPU MEMORY L3 READ SQIDI5\0"
   /* 26041 */ "GPU MEMORY L3 READ SQIDI6\0"
   /* 26067 */ "GPU MEMORY L3 READ SQIDI7\0"
   /* 26093 */ "GPU MEMORY L3 WRITE SQIDI0\0"
   /* 26120 */ "GPU MEMORY L3 WRITE SQIDI1\0"
   /* 26147 */ "GPU MEMORY L3 WRITE SQIDI2\0"
   /* 26174 */ "GPU MEMORY L3 WRITE SQIDI3\0"
   /* 26201 */ "GPU MEMORY L3 WRITE SQIDI4\0"
   /* 26228 */ "GPU MEMORY L3 WRITE SQIDI5\0"
   /* 26255 */ "GPU MEMORY L3 WRITE SQIDI6\0"
   /* 26282 */ "GPU MEMORY L3 WRITE SQIDI7\0"
   /* 26309 */ "GPU MEMORY READ\0"
   /* 26325 */ "GPU MEMORY READ SQIDI0\0"
   /* 26348 */ "GPU MEMORY READ SQIDI1\0"
   /* 26371 */ "GPU MEMORY READ SQIDI2\0"
   /* 26394 */ "GPU MEMORY READ SQIDI3\0"
   /* 26417 */ "GPU MEMORY READ SQIDI4\0"
   /* 26440 */ "GPU MEMORY READ SQIDI5\0"
   /* 26463 */ "GPU MEMORY READ SQIDI6\0"
   /* 26486 */ "GPU MEMORY READ SQIDI7\0"
   /* 26509 */ "GPU MEMORY REQUEST QUEUE FULL\0"
   /* 26539 */ "GPU MEMORY REQUEST QUEUE FULL SQIDI0\0"
   /* 26576 */ "GPU MEMORY REQUEST QUEUE FULL SQIDI1\0"
   /* 26613 */ "GPU MEMORY REQUEST QUEUE FULL SQIDI2\0"
   /* 26650 */ "GPU MEMORY REQUEST QUEUE FULL SQIDI3\0"
   /* 26687 */ "GPU MEMORY REQUEST QUEUE FULL SQIDI4\0"
   /* 26724 */ "GPU MEMORY REQUEST QUEUE FULL SQIDI5\0"
   /* 26761 */ "GPU MEMORY REQUEST QUEUE FULL SQIDI6\0"
   /* 26798 */ "GPU MEMORY REQUEST QUEUE FULL SQIDI7\0"
   /* 26835 */ "GPU MEMORY WRITE\0"
   /* 26852 */ "GPU MEMORY WRITE SQIDI0\0"
   /* 26876 */ "GPU MEMORY WRITE SQIDI1\0"
   /* 26900 */ "GPU MEMORY WRITE SQIDI2\0"
   /* 26924 */ "GPU MEMORY WRITE SQIDI3\0"
   /* 26948 */ "GPU MEMORY WRITE SQIDI4\0"
   /* 26972 */ "GPU MEMORY WRITE SQIDI5\0"
   /* 26996 */ "GPU MEMORY WRITE SQIDI6\0"
   /* 27020 */ "GPU MEMORY WRITE SQIDI7\0"
   /* 27044 */ "GPU Time Elapsed\0"
   /* 27061 */ "GS AVG Active per Thread\0"
   /* 27086 */ "GS AVG Stall per Thread\0"
   /* 27110 */ "GS Bottleneck\0"
   /* 27124 */ "GS Duration\0"
   /* 27136 */ "GS EM Pipe Active\0"
   /* 27154 */ "GS EU Active\0"
   /* 27167 */ "GS EU Stall\0"
   /* 27179 */ "GS FPU Pipe Active\0"
   /* 27198 */ "GS Send Pipe Active\0"
   /* 27218 */ "GS Threads Dispatched\0"
   /* 27240 */ "GS0 Bottleneck\0"
   /* 27255 */ "GS1 Bottleneck\0"
   /* 27270 */ "GS2 Bottleneck\0"
   /* 27285 */ "GS3 Bottleneck\0"
   /* 27300 */ "GS4 Bottleneck\0"
   /* 27315 */ "GS5 Bottleneck\0"
   /* 27330 */ "GS6 Bottleneck\0"
   /* 27345 */ "GS7 Bottleneck\0"
   /* 27360 */ "GTI Depth Throughput\0"
   /* 27381 */ "GTI Fixed Pipe Throughput\0"
   /* 27407 */ "GTI HDC TLB Lookup Throughput\0"
   /* 27437 */ "GTI L3 Throughput\0"
   /* 27455 */ "GTI RCC Throughput\0"
   /* 27474 */ "GTI Read Throughput\0"
   /* 27494 */ "GTI Read-Only Stall\0"
   /* 27514 */ "GTI Read-Write Stall\0"
   /* 27535 */ "GTI Ring Throughput\0"
   /* 27555 */ "GTI Write Throughput\0"
   /* 27576 */ "GtiCmdStreamerMemoryReads\0"
   /* 27602 */ "GtiCmdStreamerMemoryWrites\0"
   /* 27629 */ "GtiHiDepthMemoryReads\0"
   /* 27651 */ "GtiHizMemoryReads\0"
   /* 27669 */ "GtiHizMemoryWrites\0"
   /* 27688 */ "GtiL3Bank0Reads\0"
   /* 27704 */ "GtiL3Bank0Writes\0"
   /* 27721 */ "GtiL3Bank1Reads\0"
   /* 27737 */ "GtiL3Bank1Writes\0"
   /* 27754 */ "GtiL3Bank2Reads\0"
   /* 27770 */ "GtiL3Bank2Writes\0"
   /* 27787 */ "GtiL3Bank3Reads\0"
   /* 27803 */ "GtiL3Bank3Writes\0"
   /* 27820 */ "GtiL3Reads\0"
   /* 27831 */ "GtiL3Writes\0"
   /* 27843 */ "GtiMemoryReads\0"
   /* 27858 */ "GtiMemoryWrites\0"
   /* 27874 */ "GtiMscMemoryReads\0"
   /* 27892 */ "GtiMscMemoryWrites\0"
   /* 27911 */ "GtiRccMemoryReads\0"
   /* 27929 */ "GtiRccMemoryWrites\0"
   /* 27948 */ "GtiRczMemoryReads\0"
   /* 27966 */ "GtiRczMemoryWrites\0"
   /* 27985 */ "GtiRingAccesses\0"
   /* 28001 */ "GtiRsMemoryReads\0"
   /* 28018 */ "GtiSoMemoryWrites\0"
   /* 28036 */ "GtiStcMemoryReads\0"
   /* 28054 */ "GtiStcMemoryWrites\0"
   /* 28073 */ "GtiVfMemoryReads\0"
   /* 28090 */ "HDC stalled by L3 (s0.ss0)\0"
   /* 28117 */ "HDC stalled by L3 (s0.ss1)\0"
   /* 28144 */ "HDC stalled by L3 (s0.ss2)\0"
   /* 28171 */ "HIZ DEPTH TEST AMBIG NP ZPIPE0\0"
   /* 28202 */ "HIZ DEPTH TEST AMBIG NP ZPIPE1\0"
   /* 28233 */ "HIZ DEPTH TEST AMBIG NP ZPIPE10\0"
   /* 28265 */ "HIZ DEPTH TEST AMBIG NP ZPIPE11\0"
   /* 28297 */ "HIZ DEPTH TEST AMBIG NP ZPIPE12\0"
   /* 28329 */ "HIZ DEPTH TEST AMBIG NP ZPIPE13\0"
   /* 28361 */ "HIZ DEPTH TEST AMBIG NP ZPIPE14\0"
   /* 28393 */ "HIZ DEPTH TEST AMBIG NP ZPIPE15\0"
   /* 28425 */ "HIZ DEPTH TEST AMBIG NP ZPIPE2\0"
   /* 28456 */ "HIZ DEPTH TEST AMBIG NP ZPIPE3\0"
   /* 28487 */ "HIZ DEPTH TEST AMBIG NP ZPIPE4\0"
   /* 28518 */ "HIZ DEPTH TEST AMBIG NP ZPIPE5\0"
   /* 28549 */ "HIZ DEPTH TEST AMBIG NP ZPIPE6\0"
   /* 28580 */ "HIZ DEPTH TEST AMBIG NP ZPIPE7\0"
   /* 28611 */ "HIZ DEPTH TEST AMBIG NP ZPIPE8\0"
   /* 28642 */ "HIZ DEPTH TEST AMBIG NP ZPIPE9\0"
   /* 28673 */ "HIZ DEPTH TEST AMBIG P ZPIPE0\0"
   /* 28703 */ "HIZ DEPTH TEST AMBIG P ZPIPE1\0"
   /* 28733 */ "HIZ DEPTH TEST AMBIG P ZPIPE10\0"
   /* 28764 */ "HIZ DEPTH TEST AMBIG P ZPIPE11\0"
   /* 28795 */ "HIZ DEPTH TEST AMBIG P ZPIPE12\0"
   /* 28826 */ "HIZ DEPTH TEST AMBIG P ZPIPE13\0"
   /* 28857 */ "HIZ DEPTH TEST AMBIG P ZPIPE14\0"
   /* 28888 */ "HIZ DEPTH TEST AMBIG P ZPIPE15\0"
   /* 28919 */ "HIZ DEPTH TEST AMBIG P ZPIPE2\0"
   /* 28949 */ "HIZ DEPTH TEST AMBIG P ZPIPE3\0"
   /* 28979 */ "HIZ DEPTH TEST AMBIG P ZPIPE4\0"
   /* 29009 */ "HIZ DEPTH TEST AMBIG P ZPIPE5\0"
   /* 29039 */ "HIZ DEPTH TEST AMBIG P ZPIPE6\0"
   /* 29069 */ "HIZ DEPTH TEST AMBIG P ZPIPE7\0"
   /* 29099 */ "HIZ DEPTH TEST AMBIG P ZPIPE8\0"
   /* 29129 */ "HIZ DEPTH TEST AMBIG P ZPIPE9\0"
   /* 29159 */ "HIZ DEPTH TEST FAIL NP ZPIPE0\0"
   /* 29189 */ "HIZ DEPTH TEST FAIL NP ZPIPE1\0"
   /* 29219 */ "HIZ DEPTH TEST FAIL NP ZPIPE10\0"
   /* 29250 */ "HIZ DEPTH TEST FAIL NP ZPIPE11\0"
   /* 29281 */ "HIZ DEPTH TEST FAIL NP ZPIPE12\0"
   /* 29312 */ "HIZ DEPTH TEST FAIL NP ZPIPE13\0"
   /* 29343 */ "HIZ DEPTH TEST FAIL NP ZPIPE14\0"
   /* 29374 */ "HIZ DEPTH TEST FAIL NP ZPIPE15\0"
   /* 29405 */ "HIZ DEPTH TEST FAIL NP ZPIPE2\0"
   /* 29435 */ "HIZ DEPTH TEST FAIL NP ZPIPE3\0"
   /* 29465 */ "HIZ DEPTH TEST FAIL NP ZPIPE4\0"
   /* 29495 */ "HIZ DEPTH TEST FAIL NP ZPIPE5\0"
   /* 29525 */ "HIZ DEPTH TEST FAIL NP ZPIPE6\0"
   /* 29555 */ "HIZ DEPTH TEST FAIL NP ZPIPE7\0"
   /* 29585 */ "HIZ DEPTH TEST FAIL NP ZPIPE8\0"
   /* 29615 */ "HIZ DEPTH TEST FAIL NP ZPIPE9\0"
   /* 29645 */ "HIZ DEPTH TEST FAIL P ZPIPE0\0"
   /* 29674 */ "HIZ DEPTH TEST FAIL P ZPIPE1\0"
   /* 29703 */ "HIZ DEPTH TEST FAIL P ZPIPE10\0"
   /* 29733 */ "HIZ DEPTH TEST FAIL P ZPIPE11\0"
   /* 29763 */ "HIZ DEPTH TEST FAIL P ZPIPE12\0"
   /* 29793 */ "HIZ DEPTH TEST FAIL P ZPIPE13\0"
   /* 29823 */ "HIZ DEPTH TEST FAIL P ZPIPE14\0"
   /* 29853 */ "HIZ DEPTH TEST FAIL P ZPIPE15\0"
   /* 29883 */ "HIZ DEPTH TEST FAIL P ZPIPE2\0"
   /* 29912 */ "HIZ DEPTH TEST FAIL P ZPIPE3\0"
   /* 29941 */ "HIZ DEPTH TEST FAIL P ZPIPE4\0"
   /* 29970 */ "HIZ DEPTH TEST FAIL P ZPIPE5\0"
   /* 29999 */ "HIZ DEPTH TEST FAIL P ZPIPE6\0"
   /* 30028 */ "HIZ DEPTH TEST FAIL P ZPIPE7\0"
   /* 30057 */ "HIZ DEPTH TEST FAIL P ZPIPE8\0"
   /* 30086 */ "HIZ DEPTH TEST FAIL P ZPIPE9\0"
   /* 30115 */ "HIZ DEPTH TEST PASS P ZPIPE0\0"
   /* 30144 */ "HIZ DEPTH TEST PASS P ZPIPE1\0"
   /* 30173 */ "HIZ DEPTH TEST PASS P ZPIPE10\0"
   /* 30203 */ "HIZ DEPTH TEST PASS P ZPIPE11\0"
   /* 30233 */ "HIZ DEPTH TEST PASS P ZPIPE12\0"
   /* 30263 */ "HIZ DEPTH TEST PASS P ZPIPE13\0"
   /* 30293 */ "HIZ DEPTH TEST PASS P ZPIPE14\0"
   /* 30323 */ "HIZ DEPTH TEST PASS P ZPIPE15\0"
   /* 30353 */ "HIZ DEPTH TEST PASS P ZPIPE2\0"
   /* 30382 */ "HIZ DEPTH TEST PASS P ZPIPE3\0"
   /* 30411 */ "HIZ DEPTH TEST PASS P ZPIPE4\0"
   /* 30440 */ "HIZ DEPTH TEST PASS P ZPIPE5\0"
   /* 30469 */ "HIZ DEPTH TEST PASS P ZPIPE6\0"
   /* 30498 */ "HIZ DEPTH TEST PASS P ZPIPE7\0"
   /* 30527 */ "HIZ DEPTH TEST PASS P ZPIPE8\0"
   /* 30556 */ "HIZ DEPTH TEST PASS P ZPIPE9\0"
   /* 30585 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0\0"
   /* 30621 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1\0"
   /* 30657 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE10\0"
   /* 30694 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE11\0"
   /* 30731 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE12\0"
   /* 30768 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE13\0"
   /* 30805 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE14\0"
   /* 30842 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE15\0"
   /* 30879 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2\0"
   /* 30915 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3\0"
   /* 30951 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE4\0"
   /* 30987 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE5\0"
   /* 31023 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE6\0"
   /* 31059 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE7\0"
   /* 31095 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE8\0"
   /* 31131 */ "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE9\0"
   /* 31167 */ "HOST TO GPUMEM BYTE READ\0"
   /* 31192 */ "HOST TO GPUMEM BYTE WRITE\0"
   /* 31218 */ "HOST TO GPUMEM TRANSACTION READ\0"
   /* 31250 */ "HOST TO GPUMEM TRANSACTION WRITE\0"
   /* 31283 */ "HS Bottleneck\0"
   /* 31297 */ "HS EM Pipe Active\0"
   /* 31315 */ "HS FPU Pipe Active\0"
   /* 31334 */ "HS Send Pipe Active\0"
   /* 31354 */ "HS Stall\0"
   /* 31363 */ "HS Threads Dispatched\0"
   /* 31385 */ "HS0 Bottleneck\0"
   /* 31400 */ "HS0 Stall\0"
   /* 31410 */ "HS1 Bottleneck\0"
   /* 31425 */ "HS1 Stall\0"
   /* 31435 */ "HS2 Bottleneck\0"
   /* 31450 */ "HS2 Stall\0"
   /* 31460 */ "HS3 Bottleneck\0"
   /* 31475 */ "HS3 Stall\0"
   /* 31485 */ "HS4 Bottleneck\0"
   /* 31500 */ "HS4 Stall\0"
   /* 31510 */ "HS5 Bottleneck\0"
   /* 31525 */ "HS5 Stall\0"
   /* 31535 */ "HS6 Bottleneck\0"
   /* 31550 */ "HS6 Stall\0"
   /* 31560 */ "HS7 Bottleneck\0"
   /* 31575 */ "HS7 Stall\0"
   /* 31585 */ "Hi-Depth Bottleneck\0"
   /* 31605 */ "Hi-Depth00 Bottleneck\0"
   /* 31627 */ "Hi-Depth01 Bottleneck\0"
   /* 31649 */ "Hi-Depth10 Bottleneck\0"
   /* 31671 */ "Hi-Depth11 Bottleneck\0"
   /* 31693 */ "Hi-Depth20 Bottleneck\0"
   /* 31715 */ "Hi-Depth30 Bottleneck\0"
   /* 31737 */ "Hi-Depth40 Bottleneck\0"
   /* 31759 */ "Hi-Depth50 Bottleneck\0"
   /* 31781 */ "Hi-Depth60 Bottleneck\0"
   /* 31803 */ "Hi-Depth70 Bottleneck\0"
   /* 31825 */ "ICACHE HIT BANK0 XECORE0\0"
   /* 31850 */ "ICACHE HIT BANK0 XECORE1\0"
   /* 31875 */ "ICACHE HIT BANK0 XECORE10\0"
   /* 31901 */ "ICACHE HIT BANK0 XECORE11\0"
   /* 31927 */ "ICACHE HIT BANK0 XECORE12\0"
   /* 31953 */ "ICACHE HIT BANK0 XECORE13\0"
   /* 31979 */ "ICACHE HIT BANK0 XECORE14\0"
   /* 32005 */ "ICACHE HIT BANK0 XECORE15\0"
   /* 32031 */ "ICACHE HIT BANK0 XECORE16\0"
   /* 32057 */ "ICACHE HIT BANK0 XECORE17\0"
   /* 32083 */ "ICACHE HIT BANK0 XECORE18\0"
   /* 32109 */ "ICACHE HIT BANK0 XECORE19\0"
   /* 32135 */ "ICACHE HIT BANK0 XECORE2\0"
   /* 32160 */ "ICACHE HIT BANK0 XECORE20\0"
   /* 32186 */ "ICACHE HIT BANK0 XECORE21\0"
   /* 32212 */ "ICACHE HIT BANK0 XECORE22\0"
   /* 32238 */ "ICACHE HIT BANK0 XECORE23\0"
   /* 32264 */ "ICACHE HIT BANK0 XECORE24\0"
   /* 32290 */ "ICACHE HIT BANK0 XECORE25\0"
   /* 32316 */ "ICACHE HIT BANK0 XECORE26\0"
   /* 32342 */ "ICACHE HIT BANK0 XECORE27\0"
   /* 32368 */ "ICACHE HIT BANK0 XECORE28\0"
   /* 32394 */ "ICACHE HIT BANK0 XECORE29\0"
   /* 32420 */ "ICACHE HIT BANK0 XECORE3\0"
   /* 32445 */ "ICACHE HIT BANK0 XECORE30\0"
   /* 32471 */ "ICACHE HIT BANK0 XECORE31\0"
   /* 32497 */ "ICACHE HIT BANK0 XECORE4\0"
   /* 32522 */ "ICACHE HIT BANK0 XECORE5\0"
   /* 32547 */ "ICACHE HIT BANK0 XECORE6\0"
   /* 32572 */ "ICACHE HIT BANK0 XECORE7\0"
   /* 32597 */ "ICACHE HIT BANK0 XECORE8\0"
   /* 32622 */ "ICACHE HIT BANK0 XECORE9\0"
   /* 32647 */ "ICACHE HIT BANK1 XECORE0\0"
   /* 32672 */ "ICACHE HIT BANK1 XECORE1\0"
   /* 32697 */ "ICACHE HIT BANK1 XECORE10\0"
   /* 32723 */ "ICACHE HIT BANK1 XECORE11\0"
   /* 32749 */ "ICACHE HIT BANK1 XECORE12\0"
   /* 32775 */ "ICACHE HIT BANK1 XECORE13\0"
   /* 32801 */ "ICACHE HIT BANK1 XECORE14\0"
   /* 32827 */ "ICACHE HIT BANK1 XECORE15\0"
   /* 32853 */ "ICACHE HIT BANK1 XECORE16\0"
   /* 32879 */ "ICACHE HIT BANK1 XECORE17\0"
   /* 32905 */ "ICACHE HIT BANK1 XECORE18\0"
   /* 32931 */ "ICACHE HIT BANK1 XECORE19\0"
   /* 32957 */ "ICACHE HIT BANK1 XECORE2\0"
   /* 32982 */ "ICACHE HIT BANK1 XECORE20\0"
   /* 33008 */ "ICACHE HIT BANK1 XECORE21\0"
   /* 33034 */ "ICACHE HIT BANK1 XECORE22\0"
   /* 33060 */ "ICACHE HIT BANK1 XECORE23\0"
   /* 33086 */ "ICACHE HIT BANK1 XECORE24\0"
   /* 33112 */ "ICACHE HIT BANK1 XECORE25\0"
   /* 33138 */ "ICACHE HIT BANK1 XECORE26\0"
   /* 33164 */ "ICACHE HIT BANK1 XECORE27\0"
   /* 33190 */ "ICACHE HIT BANK1 XECORE28\0"
   /* 33216 */ "ICACHE HIT BANK1 XECORE29\0"
   /* 33242 */ "ICACHE HIT BANK1 XECORE3\0"
   /* 33267 */ "ICACHE HIT BANK1 XECORE30\0"
   /* 33293 */ "ICACHE HIT BANK1 XECORE31\0"
   /* 33319 */ "ICACHE HIT BANK1 XECORE4\0"
   /* 33344 */ "ICACHE HIT BANK1 XECORE5\0"
   /* 33369 */ "ICACHE HIT BANK1 XECORE6\0"
   /* 33394 */ "ICACHE HIT BANK1 XECORE7\0"
   /* 33419 */ "ICACHE HIT BANK1 XECORE8\0"
   /* 33444 */ "ICACHE HIT BANK1 XECORE9\0"
   /* 33469 */ "ICACHE HIT BANK2 XECORE0\0"
   /* 33494 */ "ICACHE HIT BANK2 XECORE1\0"
   /* 33519 */ "ICACHE HIT BANK2 XECORE10\0"
   /* 33545 */ "ICACHE HIT BANK2 XECORE11\0"
   /* 33571 */ "ICACHE HIT BANK2 XECORE12\0"
   /* 33597 */ "ICACHE HIT BANK2 XECORE13\0"
   /* 33623 */ "ICACHE HIT BANK2 XECORE14\0"
   /* 33649 */ "ICACHE HIT BANK2 XECORE15\0"
   /* 33675 */ "ICACHE HIT BANK2 XECORE16\0"
   /* 33701 */ "ICACHE HIT BANK2 XECORE17\0"
   /* 33727 */ "ICACHE HIT BANK2 XECORE18\0"
   /* 33753 */ "ICACHE HIT BANK2 XECORE19\0"
   /* 33779 */ "ICACHE HIT BANK2 XECORE2\0"
   /* 33804 */ "ICACHE HIT BANK2 XECORE20\0"
   /* 33830 */ "ICACHE HIT BANK2 XECORE21\0"
   /* 33856 */ "ICACHE HIT BANK2 XECORE22\0"
   /* 33882 */ "ICACHE HIT BANK2 XECORE23\0"
   /* 33908 */ "ICACHE HIT BANK2 XECORE24\0"
   /* 33934 */ "ICACHE HIT BANK2 XECORE25\0"
   /* 33960 */ "ICACHE HIT BANK2 XECORE26\0"
   /* 33986 */ "ICACHE HIT BANK2 XECORE27\0"
   /* 34012 */ "ICACHE HIT BANK2 XECORE28\0"
   /* 34038 */ "ICACHE HIT BANK2 XECORE29\0"
   /* 34064 */ "ICACHE HIT BANK2 XECORE3\0"
   /* 34089 */ "ICACHE HIT BANK2 XECORE30\0"
   /* 34115 */ "ICACHE HIT BANK2 XECORE31\0"
   /* 34141 */ "ICACHE HIT BANK2 XECORE4\0"
   /* 34166 */ "ICACHE HIT BANK2 XECORE5\0"
   /* 34191 */ "ICACHE HIT BANK2 XECORE6\0"
   /* 34216 */ "ICACHE HIT BANK2 XECORE7\0"
   /* 34241 */ "ICACHE HIT BANK2 XECORE8\0"
   /* 34266 */ "ICACHE HIT BANK2 XECORE9\0"
   /* 34291 */ "ICACHE HIT BANK3 XECORE0\0"
   /* 34316 */ "ICACHE HIT BANK3 XECORE1\0"
   /* 34341 */ "ICACHE HIT BANK3 XECORE10\0"
   /* 34367 */ "ICACHE HIT BANK3 XECORE11\0"
   /* 34393 */ "ICACHE HIT BANK3 XECORE12\0"
   /* 34419 */ "ICACHE HIT BANK3 XECORE13\0"
   /* 34445 */ "ICACHE HIT BANK3 XECORE14\0"
   /* 34471 */ "ICACHE HIT BANK3 XECORE15\0"
   /* 34497 */ "ICACHE HIT BANK3 XECORE16\0"
   /* 34523 */ "ICACHE HIT BANK3 XECORE17\0"
   /* 34549 */ "ICACHE HIT BANK3 XECORE18\0"
   /* 34575 */ "ICACHE HIT BANK3 XECORE19\0"
   /* 34601 */ "ICACHE HIT BANK3 XECORE2\0"
   /* 34626 */ "ICACHE HIT BANK3 XECORE20\0"
   /* 34652 */ "ICACHE HIT BANK3 XECORE21\0"
   /* 34678 */ "ICACHE HIT BANK3 XECORE22\0"
   /* 34704 */ "ICACHE HIT BANK3 XECORE23\0"
   /* 34730 */ "ICACHE HIT BANK3 XECORE24\0"
   /* 34756 */ "ICACHE HIT BANK3 XECORE25\0"
   /* 34782 */ "ICACHE HIT BANK3 XECORE26\0"
   /* 34808 */ "ICACHE HIT BANK3 XECORE27\0"
   /* 34834 */ "ICACHE HIT BANK3 XECORE28\0"
   /* 34860 */ "ICACHE HIT BANK3 XECORE29\0"
   /* 34886 */ "ICACHE HIT BANK3 XECORE3\0"
   /* 34911 */ "ICACHE HIT BANK3 XECORE30\0"
   /* 34937 */ "ICACHE HIT BANK3 XECORE31\0"
   /* 34963 */ "ICACHE HIT BANK3 XECORE4\0"
   /* 34988 */ "ICACHE HIT BANK3 XECORE5\0"
   /* 35013 */ "ICACHE HIT BANK3 XECORE6\0"
   /* 35038 */ "ICACHE HIT BANK3 XECORE7\0"
   /* 35063 */ "ICACHE HIT BANK3 XECORE8\0"
   /* 35088 */ "ICACHE HIT BANK3 XECORE9\0"
   /* 35113 */ "ICACHE L3 HIT L3BANK0\0"
   /* 35135 */ "ICACHE L3 HIT L3BANK1\0"
   /* 35157 */ "ICACHE L3 HIT L3BANK10\0"
   /* 35180 */ "ICACHE L3 HIT L3BANK11\0"
   /* 35203 */ "ICACHE L3 HIT L3BANK12\0"
   /* 35226 */ "ICACHE L3 HIT L3BANK13\0"
   /* 35249 */ "ICACHE L3 HIT L3BANK14\0"
   /* 35272 */ "ICACHE L3 HIT L3BANK15\0"
   /* 35295 */ "ICACHE L3 HIT L3BANK16\0"
   /* 35318 */ "ICACHE L3 HIT L3BANK17\0"
   /* 35341 */ "ICACHE L3 HIT L3BANK18\0"
   /* 35364 */ "ICACHE L3 HIT L3BANK19\0"
   /* 35387 */ "ICACHE L3 HIT L3BANK2\0"
   /* 35409 */ "ICACHE L3 HIT L3BANK20\0"
   /* 35432 */ "ICACHE L3 HIT L3BANK21\0"
   /* 35455 */ "ICACHE L3 HIT L3BANK22\0"
   /* 35478 */ "ICACHE L3 HIT L3BANK23\0"
   /* 35501 */ "ICACHE L3 HIT L3BANK24\0"
   /* 35524 */ "ICACHE L3 HIT L3BANK25\0"
   /* 35547 */ "ICACHE L3 HIT L3BANK26\0"
   /* 35570 */ "ICACHE L3 HIT L3BANK27\0"
   /* 35593 */ "ICACHE L3 HIT L3BANK28\0"
   /* 35616 */ "ICACHE L3 HIT L3BANK29\0"
   /* 35639 */ "ICACHE L3 HIT L3BANK3\0"
   /* 35661 */ "ICACHE L3 HIT L3BANK30\0"
   /* 35684 */ "ICACHE L3 HIT L3BANK31\0"
   /* 35707 */ "ICACHE L3 HIT L3BANK4\0"
   /* 35729 */ "ICACHE L3 HIT L3BANK5\0"
   /* 35751 */ "ICACHE L3 HIT L3BANK6\0"
   /* 35773 */ "ICACHE L3 HIT L3BANK7\0"
   /* 35795 */ "ICACHE L3 HIT L3BANK8\0"
   /* 35817 */ "ICACHE L3 HIT L3BANK9\0"
   /* 35839 */ "ICACHE L3 READ L3BANK0\0"
   /* 35862 */ "ICACHE L3 READ L3BANK1\0"
   /* 35885 */ "ICACHE L3 READ L3BANK10\0"
   /* 35909 */ "ICACHE L3 READ L3BANK11\0"
   /* 35933 */ "ICACHE L3 READ L3BANK12\0"
   /* 35957 */ "ICACHE L3 READ L3BANK13\0"
   /* 35981 */ "ICACHE L3 READ L3BANK14\0"
   /* 36005 */ "ICACHE L3 READ L3BANK15\0"
   /* 36029 */ "ICACHE L3 READ L3BANK16\0"
   /* 36053 */ "ICACHE L3 READ L3BANK17\0"
   /* 36077 */ "ICACHE L3 READ L3BANK18\0"
   /* 36101 */ "ICACHE L3 READ L3BANK19\0"
   /* 36125 */ "ICACHE L3 READ L3BANK2\0"
   /* 36148 */ "ICACHE L3 READ L3BANK20\0"
   /* 36172 */ "ICACHE L3 READ L3BANK21\0"
   /* 36196 */ "ICACHE L3 READ L3BANK22\0"
   /* 36220 */ "ICACHE L3 READ L3BANK23\0"
   /* 36244 */ "ICACHE L3 READ L3BANK24\0"
   /* 36268 */ "ICACHE L3 READ L3BANK25\0"
   /* 36292 */ "ICACHE L3 READ L3BANK26\0"
   /* 36316 */ "ICACHE L3 READ L3BANK27\0"
   /* 36340 */ "ICACHE L3 READ L3BANK28\0"
   /* 36364 */ "ICACHE L3 READ L3BANK29\0"
   /* 36388 */ "ICACHE L3 READ L3BANK3\0"
   /* 36411 */ "ICACHE L3 READ L3BANK30\0"
   /* 36435 */ "ICACHE L3 READ L3BANK31\0"
   /* 36459 */ "ICACHE L3 READ L3BANK4\0"
   /* 36482 */ "ICACHE L3 READ L3BANK5\0"
   /* 36505 */ "ICACHE L3 READ L3BANK6\0"
   /* 36528 */ "ICACHE L3 READ L3BANK7\0"
   /* 36551 */ "ICACHE L3 READ L3BANK8\0"
   /* 36574 */ "ICACHE L3 READ L3BANK9\0"
   /* 36597 */ "ICACHE MISS BANK0 XECORE0\0"
   /* 36623 */ "ICACHE MISS BANK0 XECORE1\0"
   /* 36649 */ "ICACHE MISS BANK0 XECORE10\0"
   /* 36676 */ "ICACHE MISS BANK0 XECORE11\0"
   /* 36703 */ "ICACHE MISS BANK0 XECORE12\0"
   /* 36730 */ "ICACHE MISS BANK0 XECORE13\0"
   /* 36757 */ "ICACHE MISS BANK0 XECORE14\0"
   /* 36784 */ "ICACHE MISS BANK0 XECORE15\0"
   /* 36811 */ "ICACHE MISS BANK0 XECORE16\0"
   /* 36838 */ "ICACHE MISS BANK0 XECORE17\0"
   /* 36865 */ "ICACHE MISS BANK0 XECORE18\0"
   /* 36892 */ "ICACHE MISS BANK0 XECORE19\0"
   /* 36919 */ "ICACHE MISS BANK0 XECORE2\0"
   /* 36945 */ "ICACHE MISS BANK0 XECORE20\0"
   /* 36972 */ "ICACHE MISS BANK0 XECORE21\0"
   /* 36999 */ "ICACHE MISS BANK0 XECORE22\0"
   /* 37026 */ "ICACHE MISS BANK0 XECORE23\0"
   /* 37053 */ "ICACHE MISS BANK0 XECORE24\0"
   /* 37080 */ "ICACHE MISS BANK0 XECORE25\0"
   /* 37107 */ "ICACHE MISS BANK0 XECORE26\0"
   /* 37134 */ "ICACHE MISS BANK0 XECORE27\0"
   /* 37161 */ "ICACHE MISS BANK0 XECORE28\0"
   /* 37188 */ "ICACHE MISS BANK0 XECORE29\0"
   /* 37215 */ "ICACHE MISS BANK0 XECORE3\0"
   /* 37241 */ "ICACHE MISS BANK0 XECORE30\0"
   /* 37268 */ "ICACHE MISS BANK0 XECORE31\0"
   /* 37295 */ "ICACHE MISS BANK0 XECORE4\0"
   /* 37321 */ "ICACHE MISS BANK0 XECORE5\0"
   /* 37347 */ "ICACHE MISS BANK0 XECORE6\0"
   /* 37373 */ "ICACHE MISS BANK0 XECORE7\0"
   /* 37399 */ "ICACHE MISS BANK0 XECORE8\0"
   /* 37425 */ "ICACHE MISS BANK0 XECORE9\0"
   /* 37451 */ "ICACHE MISS BANK1 XECORE0\0"
   /* 37477 */ "ICACHE MISS BANK1 XECORE1\0"
   /* 37503 */ "ICACHE MISS BANK1 XECORE10\0"
   /* 37530 */ "ICACHE MISS BANK1 XECORE11\0"
   /* 37557 */ "ICACHE MISS BANK1 XECORE12\0"
   /* 37584 */ "ICACHE MISS BANK1 XECORE13\0"
   /* 37611 */ "ICACHE MISS BANK1 XECORE14\0"
   /* 37638 */ "ICACHE MISS BANK1 XECORE15\0"
   /* 37665 */ "ICACHE MISS BANK1 XECORE16\0"
   /* 37692 */ "ICACHE MISS BANK1 XECORE17\0"
   /* 37719 */ "ICACHE MISS BANK1 XECORE18\0"
   /* 37746 */ "ICACHE MISS BANK1 XECORE19\0"
   /* 37773 */ "ICACHE MISS BANK1 XECORE2\0"
   /* 37799 */ "ICACHE MISS BANK1 XECORE20\0"
   /* 37826 */ "ICACHE MISS BANK1 XECORE21\0"
   /* 37853 */ "ICACHE MISS BANK1 XECORE22\0"
   /* 37880 */ "ICACHE MISS BANK1 XECORE23\0"
   /* 37907 */ "ICACHE MISS BANK1 XECORE24\0"
   /* 37934 */ "ICACHE MISS BANK1 XECORE25\0"
   /* 37961 */ "ICACHE MISS BANK1 XECORE26\0"
   /* 37988 */ "ICACHE MISS BANK1 XECORE27\0"
   /* 38015 */ "ICACHE MISS BANK1 XECORE28\0"
   /* 38042 */ "ICACHE MISS BANK1 XECORE29\0"
   /* 38069 */ "ICACHE MISS BANK1 XECORE3\0"
   /* 38095 */ "ICACHE MISS BANK1 XECORE30\0"
   /* 38122 */ "ICACHE MISS BANK1 XECORE31\0"
   /* 38149 */ "ICACHE MISS BANK1 XECORE4\0"
   /* 38175 */ "ICACHE MISS BANK1 XECORE5\0"
   /* 38201 */ "ICACHE MISS BANK1 XECORE6\0"
   /* 38227 */ "ICACHE MISS BANK1 XECORE7\0"
   /* 38253 */ "ICACHE MISS BANK1 XECORE8\0"
   /* 38279 */ "ICACHE MISS BANK1 XECORE9\0"
   /* 38305 */ "ICACHE MISS BANK2 XECORE0\0"
   /* 38331 */ "ICACHE MISS BANK2 XECORE1\0"
   /* 38357 */ "ICACHE MISS BANK2 XECORE10\0"
   /* 38384 */ "ICACHE MISS BANK2 XECORE11\0"
   /* 38411 */ "ICACHE MISS BANK2 XECORE12\0"
   /* 38438 */ "ICACHE MISS BANK2 XECORE13\0"
   /* 38465 */ "ICACHE MISS BANK2 XECORE14\0"
   /* 38492 */ "ICACHE MISS BANK2 XECORE15\0"
   /* 38519 */ "ICACHE MISS BANK2 XECORE16\0"
   /* 38546 */ "ICACHE MISS BANK2 XECORE17\0"
   /* 38573 */ "ICACHE MISS BANK2 XECORE18\0"
   /* 38600 */ "ICACHE MISS BANK2 XECORE19\0"
   /* 38627 */ "ICACHE MISS BANK2 XECORE2\0"
   /* 38653 */ "ICACHE MISS BANK2 XECORE20\0"
   /* 38680 */ "ICACHE MISS BANK2 XECORE21\0"
   /* 38707 */ "ICACHE MISS BANK2 XECORE22\0"
   /* 38734 */ "ICACHE MISS BANK2 XECORE23\0"
   /* 38761 */ "ICACHE MISS BANK2 XECORE24\0"
   /* 38788 */ "ICACHE MISS BANK2 XECORE25\0"
   /* 38815 */ "ICACHE MISS BANK2 XECORE26\0"
   /* 38842 */ "ICACHE MISS BANK2 XECORE27\0"
   /* 38869 */ "ICACHE MISS BANK2 XECORE28\0"
   /* 38896 */ "ICACHE MISS BANK2 XECORE29\0"
   /* 38923 */ "ICACHE MISS BANK2 XECORE3\0"
   /* 38949 */ "ICACHE MISS BANK2 XECORE30\0"
   /* 38976 */ "ICACHE MISS BANK2 XECORE31\0"
   /* 39003 */ "ICACHE MISS BANK2 XECORE4\0"
   /* 39029 */ "ICACHE MISS BANK2 XECORE5\0"
   /* 39055 */ "ICACHE MISS BANK2 XECORE6\0"
   /* 39081 */ "ICACHE MISS BANK2 XECORE7\0"
   /* 39107 */ "ICACHE MISS BANK2 XECORE8\0"
   /* 39133 */ "ICACHE MISS BANK2 XECORE9\0"
   /* 39159 */ "ICACHE MISS BANK3 XECORE0\0"
   /* 39185 */ "ICACHE MISS BANK3 XECORE1\0"
   /* 39211 */ "ICACHE MISS BANK3 XECORE10\0"
   /* 39238 */ "ICACHE MISS BANK3 XECORE11\0"
   /* 39265 */ "ICACHE MISS BANK3 XECORE12\0"
   /* 39292 */ "ICACHE MISS BANK3 XECORE13\0"
   /* 39319 */ "ICACHE MISS BANK3 XECORE14\0"
   /* 39346 */ "ICACHE MISS BANK3 XECORE15\0"
   /* 39373 */ "ICACHE MISS BANK3 XECORE16\0"
   /* 39400 */ "ICACHE MISS BANK3 XECORE17\0"
   /* 39427 */ "ICACHE MISS BANK3 XECORE18\0"
   /* 39454 */ "ICACHE MISS BANK3 XECORE19\0"
   /* 39481 */ "ICACHE MISS BANK3 XECORE2\0"
   /* 39507 */ "ICACHE MISS BANK3 XECORE20\0"
   /* 39534 */ "ICACHE MISS BANK3 XECORE21\0"
   /* 39561 */ "ICACHE MISS BANK3 XECORE22\0"
   /* 39588 */ "ICACHE MISS BANK3 XECORE23\0"
   /* 39615 */ "ICACHE MISS BANK3 XECORE24\0"
   /* 39642 */ "ICACHE MISS BANK3 XECORE25\0"
   /* 39669 */ "ICACHE MISS BANK3 XECORE26\0"
   /* 39696 */ "ICACHE MISS BANK3 XECORE27\0"
   /* 39723 */ "ICACHE MISS BANK3 XECORE28\0"
   /* 39750 */ "ICACHE MISS BANK3 XECORE29\0"
   /* 39777 */ "ICACHE MISS BANK3 XECORE3\0"
   /* 39803 */ "ICACHE MISS BANK3 XECORE30\0"
   /* 39830 */ "ICACHE MISS BANK3 XECORE31\0"
   /* 39857 */ "ICACHE MISS BANK3 XECORE4\0"
   /* 39883 */ "ICACHE MISS BANK3 XECORE5\0"
   /* 39909 */ "ICACHE MISS BANK3 XECORE6\0"
   /* 39935 */ "ICACHE MISS BANK3 XECORE7\0"
   /* 39961 */ "ICACHE MISS BANK3 XECORE8\0"
   /* 39987 */ "ICACHE MISS BANK3 XECORE9\0"
   /* 40013 */ "IZ OUTPUT READY ZPIPE0\0"
   /* 40036 */ "IZ OUTPUT READY ZPIPE1\0"
   /* 40059 */ "IZ OUTPUT READY ZPIPE10\0"
   /* 40083 */ "IZ OUTPUT READY ZPIPE11\0"
   /* 40107 */ "IZ OUTPUT READY ZPIPE12\0"
   /* 40131 */ "IZ OUTPUT READY ZPIPE13\0"
   /* 40155 */ "IZ OUTPUT READY ZPIPE14\0"
   /* 40179 */ "IZ OUTPUT READY ZPIPE15\0"
   /* 40203 */ "IZ OUTPUT READY ZPIPE2\0"
   /* 40226 */ "IZ OUTPUT READY ZPIPE3\0"
   /* 40249 */ "IZ OUTPUT READY ZPIPE4\0"
   /* 40272 */ "IZ OUTPUT READY ZPIPE5\0"
   /* 40295 */ "IZ OUTPUT READY ZPIPE6\0"
   /* 40318 */ "IZ OUTPUT READY ZPIPE7\0"
   /* 40341 */ "IZ OUTPUT READY ZPIPE8\0"
   /* 40364 */ "IZ OUTPUT READY ZPIPE9\0"
   /* 40387 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE0\0"
   /* 40422 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE1\0"
   /* 40457 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE10\0"
   /* 40493 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE11\0"
   /* 40529 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE12\0"
   /* 40565 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE13\0"
   /* 40601 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE14\0"
   /* 40637 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE15\0"
   /* 40673 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE2\0"
   /* 40708 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE3\0"
   /* 40743 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE4\0"
   /* 40778 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE5\0"
   /* 40813 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE6\0"
   /* 40848 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE7\0"
   /* 40883 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE8\0"
   /* 40918 */ "IZ SUBSPAN LATENCY FIFOFULL ZPIPE9\0"
   /* 40953 */ "L3 ATOMIC ACCESS L3BANK0\0"
   /* 40978 */ "L3 ATOMIC ACCESS L3BANK1\0"
   /* 41003 */ "L3 ATOMIC ACCESS L3BANK10\0"
   /* 41029 */ "L3 ATOMIC ACCESS L3BANK11\0"
   /* 41055 */ "L3 ATOMIC ACCESS L3BANK12\0"
   /* 41081 */ "L3 ATOMIC ACCESS L3BANK13\0"
   /* 41107 */ "L3 ATOMIC ACCESS L3BANK14\0"
   /* 41133 */ "L3 ATOMIC ACCESS L3BANK15\0"
   /* 41159 */ "L3 ATOMIC ACCESS L3BANK16\0"
   /* 41185 */ "L3 ATOMIC ACCESS L3BANK17\0"
   /* 41211 */ "L3 ATOMIC ACCESS L3BANK18\0"
   /* 41237 */ "L3 ATOMIC ACCESS L3BANK19\0"
   /* 41263 */ "L3 ATOMIC ACCESS L3BANK2\0"
   /* 41288 */ "L3 ATOMIC ACCESS L3BANK20\0"
   /* 41314 */ "L3 ATOMIC ACCESS L3BANK21\0"
   /* 41340 */ "L3 ATOMIC ACCESS L3BANK22\0"
   /* 41366 */ "L3 ATOMIC ACCESS L3BANK23\0"
   /* 41392 */ "L3 ATOMIC ACCESS L3BANK24\0"
   /* 41418 */ "L3 ATOMIC ACCESS L3BANK25\0"
   /* 41444 */ "L3 ATOMIC ACCESS L3BANK26\0"
   /* 41470 */ "L3 ATOMIC ACCESS L3BANK27\0"
   /* 41496 */ "L3 ATOMIC ACCESS L3BANK28\0"
   /* 41522 */ "L3 ATOMIC ACCESS L3BANK29\0"
   /* 41548 */ "L3 ATOMIC ACCESS L3BANK3\0"
   /* 41573 */ "L3 ATOMIC ACCESS L3BANK30\0"
   /* 41599 */ "L3 ATOMIC ACCESS L3BANK31\0"
   /* 41625 */ "L3 ATOMIC ACCESS L3BANK4\0"
   /* 41650 */ "L3 ATOMIC ACCESS L3BANK5\0"
   /* 41675 */ "L3 ATOMIC ACCESS L3BANK6\0"
   /* 41700 */ "L3 ATOMIC ACCESS L3BANK7\0"
   /* 41725 */ "L3 ATOMIC ACCESS L3BANK8\0"
   /* 41750 */ "L3 ATOMIC ACCESS L3BANK9\0"
   /* 41775 */ "L3 Accesses\0"
   /* 41787 */ "L3 BANK ACTIVE L3BANK0\0"
   /* 41810 */ "L3 BANK ACTIVE L3BANK1\0"
   /* 41833 */ "L3 BANK ACTIVE L3BANK10\0"
   /* 41857 */ "L3 BANK ACTIVE L3BANK11\0"
   /* 41881 */ "L3 BANK ACTIVE L3BANK12\0"
   /* 41905 */ "L3 BANK ACTIVE L3BANK13\0"
   /* 41929 */ "L3 BANK ACTIVE L3BANK14\0"
   /* 41953 */ "L3 BANK ACTIVE L3BANK15\0"
   /* 41977 */ "L3 BANK ACTIVE L3BANK16\0"
   /* 42001 */ "L3 BANK ACTIVE L3BANK17\0"
   /* 42025 */ "L3 BANK ACTIVE L3BANK18\0"
   /* 42049 */ "L3 BANK ACTIVE L3BANK19\0"
   /* 42073 */ "L3 BANK ACTIVE L3BANK2\0"
   /* 42096 */ "L3 BANK ACTIVE L3BANK20\0"
   /* 42120 */ "L3 BANK ACTIVE L3BANK21\0"
   /* 42144 */ "L3 BANK ACTIVE L3BANK22\0"
   /* 42168 */ "L3 BANK ACTIVE L3BANK23\0"
   /* 42192 */ "L3 BANK ACTIVE L3BANK24\0"
   /* 42216 */ "L3 BANK ACTIVE L3BANK25\0"
   /* 42240 */ "L3 BANK ACTIVE L3BANK26\0"
   /* 42264 */ "L3 BANK ACTIVE L3BANK27\0"
   /* 42288 */ "L3 BANK ACTIVE L3BANK28\0"
   /* 42312 */ "L3 BANK ACTIVE L3BANK29\0"
   /* 42336 */ "L3 BANK ACTIVE L3BANK3\0"
   /* 42359 */ "L3 BANK ACTIVE L3BANK30\0"
   /* 42383 */ "L3 BANK ACTIVE L3BANK31\0"
   /* 42407 */ "L3 BANK ACTIVE L3BANK4\0"
   /* 42430 */ "L3 BANK ACTIVE L3BANK5\0"
   /* 42453 */ "L3 BANK ACTIVE L3BANK6\0"
   /* 42476 */ "L3 BANK ACTIVE L3BANK7\0"
   /* 42499 */ "L3 BANK ACTIVE L3BANK8\0"
   /* 42522 */ "L3 BANK ACTIVE L3BANK9\0"
   /* 42545 */ "L3 BANK INPUT AVAILABLE L3BANK0\0"
   /* 42577 */ "L3 BANK INPUT AVAILABLE L3BANK1\0"
   /* 42609 */ "L3 BANK INPUT AVAILABLE L3BANK10\0"
   /* 42642 */ "L3 BANK INPUT AVAILABLE L3BANK11\0"
   /* 42675 */ "L3 BANK INPUT AVAILABLE L3BANK12\0"
   /* 42708 */ "L3 BANK INPUT AVAILABLE L3BANK13\0"
   /* 42741 */ "L3 BANK INPUT AVAILABLE L3BANK14\0"
   /* 42774 */ "L3 BANK INPUT AVAILABLE L3BANK15\0"
   /* 42807 */ "L3 BANK INPUT AVAILABLE L3BANK16\0"
   /* 42840 */ "L3 BANK INPUT AVAILABLE L3BANK17\0"
   /* 42873 */ "L3 BANK INPUT AVAILABLE L3BANK18\0"
   /* 42906 */ "L3 BANK INPUT AVAILABLE L3BANK19\0"
   /* 42939 */ "L3 BANK INPUT AVAILABLE L3BANK2\0"
   /* 42971 */ "L3 BANK INPUT AVAILABLE L3BANK20\0"
   /* 43004 */ "L3 BANK INPUT AVAILABLE L3BANK21\0"
   /* 43037 */ "L3 BANK INPUT AVAILABLE L3BANK22\0"
   /* 43070 */ "L3 BANK INPUT AVAILABLE L3BANK23\0"
   /* 43103 */ "L3 BANK INPUT AVAILABLE L3BANK24\0"
   /* 43136 */ "L3 BANK INPUT AVAILABLE L3BANK25\0"
   /* 43169 */ "L3 BANK INPUT AVAILABLE L3BANK26\0"
   /* 43202 */ "L3 BANK INPUT AVAILABLE L3BANK27\0"
   /* 43235 */ "L3 BANK INPUT AVAILABLE L3BANK28\0"
   /* 43268 */ "L3 BANK INPUT AVAILABLE L3BANK29\0"
   /* 43301 */ "L3 BANK INPUT AVAILABLE L3BANK3\0"
   /* 43333 */ "L3 BANK INPUT AVAILABLE L3BANK30\0"
   /* 43366 */ "L3 BANK INPUT AVAILABLE L3BANK31\0"
   /* 43399 */ "L3 BANK INPUT AVAILABLE L3BANK4\0"
   /* 43431 */ "L3 BANK INPUT AVAILABLE L3BANK5\0"
   /* 43463 */ "L3 BANK INPUT AVAILABLE L3BANK6\0"
   /* 43495 */ "L3 BANK INPUT AVAILABLE L3BANK7\0"
   /* 43527 */ "L3 BANK INPUT AVAILABLE L3BANK8\0"
   /* 43559 */ "L3 BANK INPUT AVAILABLE L3BANK9\0"
   /* 43591 */ "L3 BANK STALL L3BANK0\0"
   /* 43613 */ "L3 BANK STALL L3BANK1\0"
   /* 43635 */ "L3 BANK STALL L3BANK10\0"
   /* 43658 */ "L3 BANK STALL L3BANK11\0"
   /* 43681 */ "L3 BANK STALL L3BANK12\0"
   /* 43704 */ "L3 BANK STALL L3BANK13\0"
   /* 43727 */ "L3 BANK STALL L3BANK14\0"
   /* 43750 */ "L3 BANK STALL L3BANK15\0"
   /* 43773 */ "L3 BANK STALL L3BANK16\0"
   /* 43796 */ "L3 BANK STALL L3BANK17\0"
   /* 43819 */ "L3 BANK STALL L3BANK18\0"
   /* 43842 */ "L3 BANK STALL L3BANK19\0"
   /* 43865 */ "L3 BANK STALL L3BANK2\0"
   /* 43887 */ "L3 BANK STALL L3BANK20\0"
   /* 43910 */ "L3 BANK STALL L3BANK21\0"
   /* 43933 */ "L3 BANK STALL L3BANK22\0"
   /* 43956 */ "L3 BANK STALL L3BANK23\0"
   /* 43979 */ "L3 BANK STALL L3BANK24\0"
   /* 44002 */ "L3 BANK STALL L3BANK25\0"
   /* 44025 */ "L3 BANK STALL L3BANK26\0"
   /* 44048 */ "L3 BANK STALL L3BANK27\0"
   /* 44071 */ "L3 BANK STALL L3BANK28\0"
   /* 44094 */ "L3 BANK STALL L3BANK29\0"
   /* 44117 */ "L3 BANK STALL L3BANK3\0"
   /* 44139 */ "L3 BANK STALL L3BANK30\0"
   /* 44162 */ "L3 BANK STALL L3BANK31\0"
   /* 44185 */ "L3 BANK STALL L3BANK4\0"
   /* 44207 */ "L3 BANK STALL L3BANK5\0"
   /* 44229 */ "L3 BANK STALL L3BANK6\0"
   /* 44251 */ "L3 BANK STALL L3BANK7\0"
   /* 44273 */ "L3 BANK STALL L3BANK8\0"
   /* 44295 */ "L3 BANK STALL L3BANK9\0"
   /* 44317 */ "L3 BUSY L3BANK0\0"
   /* 44333 */ "L3 BUSY L3BANK1\0"
   /* 44349 */ "L3 BUSY L3BANK2\0"
   /* 44365 */ "L3 BUSY L3BANK3\0"
   /* 44381 */ "L3 BUSY L3BANK4\0"
   /* 44397 */ "L3 BUSY L3BANK5\0"
   /* 44413 */ "L3 BUSY L3BANK6\0"
   /* 44429 */ "L3 BUSY L3BANK7\0"
   /* 44445 */ "L3 BYTE READ\0"
   /* 44458 */ "L3 BYTE WRITE\0"
   /* 44472 */ "L3 Bank 00 Accesses\0"
   /* 44492 */ "L3 Bank 00 IC Accesses\0"
   /* 44515 */ "L3 Bank 00 IC Hits\0"
   /* 44534 */ "L3 Bank 01 Accesses\0"
   /* 44554 */ "L3 Bank 02 Accesses\0"
   /* 44574 */ "L3 Bank 03 Accesses\0"
   /* 44594 */ "L3 Bank 10 Accesses\0"
   /* 44614 */ "L3 Bank 10 IC Accesses\0"
   /* 44637 */ "L3 Bank 10 IC Hits\0"
   /* 44656 */ "L3 Bank 11 Accesses\0"
   /* 44676 */ "L3 Bank 12 Accesses\0"
   /* 44696 */ "L3 Bank 13 Accesses\0"
   /* 44716 */ "L3 HIT L3BANK0\0"
   /* 44731 */ "L3 HIT L3BANK1\0"
   /* 44746 */ "L3 HIT L3BANK10\0"
   /* 44762 */ "L3 HIT L3BANK11\0"
   /* 44778 */ "L3 HIT L3BANK12\0"
   /* 44794 */ "L3 HIT L3BANK13\0"
   /* 44810 */ "L3 HIT L3BANK14\0"
   /* 44826 */ "L3 HIT L3BANK15\0"
   /* 44842 */ "L3 HIT L3BANK16\0"
   /* 44858 */ "L3 HIT L3BANK17\0"
   /* 44874 */ "L3 HIT L3BANK18\0"
   /* 44890 */ "L3 HIT L3BANK19\0"
   /* 44906 */ "L3 HIT L3BANK2\0"
   /* 44921 */ "L3 HIT L3BANK20\0"
   /* 44937 */ "L3 HIT L3BANK21\0"
   /* 44953 */ "L3 HIT L3BANK22\0"
   /* 44969 */ "L3 HIT L3BANK23\0"
   /* 44985 */ "L3 HIT L3BANK24\0"
   /* 45001 */ "L3 HIT L3BANK25\0"
   /* 45017 */ "L3 HIT L3BANK26\0"
   /* 45033 */ "L3 HIT L3BANK27\0"
   /* 45049 */ "L3 HIT L3BANK28\0"
   /* 45065 */ "L3 HIT L3BANK29\0"
   /* 45081 */ "L3 HIT L3BANK3\0"
   /* 45096 */ "L3 HIT L3BANK30\0"
   /* 45112 */ "L3 HIT L3BANK31\0"
   /* 45128 */ "L3 HIT L3BANK4\0"
   /* 45143 */ "L3 HIT L3BANK5\0"
   /* 45158 */ "L3 HIT L3BANK6\0"
   /* 45173 */ "L3 HIT L3BANK7\0"
   /* 45188 */ "L3 HIT L3BANK8\0"
   /* 45203 */ "L3 HIT L3BANK9\0"
   /* 45218 */ "L3 INPUT AVAILABLE L3BANK0\0"
   /* 45245 */ "L3 INPUT AVAILABLE L3BANK1\0"
   /* 45272 */ "L3 INPUT AVAILABLE L3BANK2\0"
   /* 45299 */ "L3 INPUT AVAILABLE L3BANK3\0"
   /* 45326 */ "L3 INPUT AVAILABLE L3BANK4\0"
   /* 45353 */ "L3 INPUT AVAILABLE L3BANK5\0"
   /* 45380 */ "L3 INPUT AVAILABLE L3BANK6\0"
   /* 45407 */ "L3 INPUT AVAILABLE L3BANK7\0"
   /* 45434 */ "L3 Lookup Accesses w/o IC\0"
   /* 45460 */ "L3 MISS L3BANK0\0"
   /* 45476 */ "L3 MISS L3BANK1\0"
   /* 45492 */ "L3 MISS L3BANK10\0"
   /* 45509 */ "L3 MISS L3BANK11\0"
   /* 45526 */ "L3 MISS L3BANK12\0"
   /* 45543 */ "L3 MISS L3BANK13\0"
   /* 45560 */ "L3 MISS L3BANK14\0"
   /* 45577 */ "L3 MISS L3BANK15\0"
   /* 45594 */ "L3 MISS L3BANK16\0"
   /* 45611 */ "L3 MISS L3BANK17\0"
   /* 45628 */ "L3 MISS L3BANK18\0"
   /* 45645 */ "L3 MISS L3BANK19\0"
   /* 45662 */ "L3 MISS L3BANK2\0"
   /* 45678 */ "L3 MISS L3BANK20\0"
   /* 45695 */ "L3 MISS L3BANK21\0"
   /* 45712 */ "L3 MISS L3BANK22\0"
   /* 45729 */ "L3 MISS L3BANK23\0"
   /* 45746 */ "L3 MISS L3BANK24\0"
   /* 45763 */ "L3 MISS L3BANK25\0"
   /* 45780 */ "L3 MISS L3BANK26\0"
   /* 45797 */ "L3 MISS L3BANK27\0"
   /* 45814 */ "L3 MISS L3BANK28\0"
   /* 45831 */ "L3 MISS L3BANK29\0"
   /* 45848 */ "L3 MISS L3BANK3\0"
   /* 45864 */ "L3 MISS L3BANK30\0"
   /* 45881 */ "L3 MISS L3BANK31\0"
   /* 45898 */ "L3 MISS L3BANK4\0"
   /* 45914 */ "L3 MISS L3BANK5\0"
   /* 45930 */ "L3 MISS L3BANK6\0"
   /* 45946 */ "L3 MISS L3BANK7\0"
   /* 45962 */ "L3 MISS L3BANK8\0"
   /* 45978 */ "L3 MISS L3BANK9\0"
   /* 45994 */ "L3 Misses\0"
   /* 46004 */ "L3 OUTPUT READY L3BANK0\0"
   /* 46028 */ "L3 OUTPUT READY L3BANK1\0"
   /* 46052 */ "L3 OUTPUT READY L3BANK10\0"
   /* 46077 */ "L3 OUTPUT READY L3BANK11\0"
   /* 46102 */ "L3 OUTPUT READY L3BANK12\0"
   /* 46127 */ "L3 OUTPUT READY L3BANK13\0"
   /* 46152 */ "L3 OUTPUT READY L3BANK14\0"
   /* 46177 */ "L3 OUTPUT READY L3BANK15\0"
   /* 46202 */ "L3 OUTPUT READY L3BANK16\0"
   /* 46227 */ "L3 OUTPUT READY L3BANK17\0"
   /* 46252 */ "L3 OUTPUT READY L3BANK18\0"
   /* 46277 */ "L3 OUTPUT READY L3BANK19\0"
   /* 46302 */ "L3 OUTPUT READY L3BANK2\0"
   /* 46326 */ "L3 OUTPUT READY L3BANK20\0"
   /* 46351 */ "L3 OUTPUT READY L3BANK21\0"
   /* 46376 */ "L3 OUTPUT READY L3BANK22\0"
   /* 46401 */ "L3 OUTPUT READY L3BANK23\0"
   /* 46426 */ "L3 OUTPUT READY L3BANK24\0"
   /* 46451 */ "L3 OUTPUT READY L3BANK25\0"
   /* 46476 */ "L3 OUTPUT READY L3BANK26\0"
   /* 46501 */ "L3 OUTPUT READY L3BANK27\0"
   /* 46526 */ "L3 OUTPUT READY L3BANK28\0"
   /* 46551 */ "L3 OUTPUT READY L3BANK29\0"
   /* 46576 */ "L3 OUTPUT READY L3BANK3\0"
   /* 46600 */ "L3 OUTPUT READY L3BANK30\0"
   /* 46625 */ "L3 OUTPUT READY L3BANK31\0"
   /* 46650 */ "L3 OUTPUT READY L3BANK4\0"
   /* 46674 */ "L3 OUTPUT READY L3BANK5\0"
   /* 46698 */ "L3 OUTPUT READY L3BANK6\0"
   /* 46722 */ "L3 OUTPUT READY L3BANK7\0"
   /* 46746 */ "L3 OUTPUT READY L3BANK8\0"
   /* 46770 */ "L3 OUTPUT READY L3BANK9\0"
   /* 46794 */ "L3 READ L3BANK0\0"
   /* 46810 */ "L3 READ L3BANK1\0"
   /* 46826 */ "L3 READ L3BANK10\0"
   /* 46843 */ "L3 READ L3BANK11\0"
   /* 46860 */ "L3 READ L3BANK12\0"
   /* 46877 */ "L3 READ L3BANK13\0"
   /* 46894 */ "L3 READ L3BANK14\0"
   /* 46911 */ "L3 READ L3BANK15\0"
   /* 46928 */ "L3 READ L3BANK16\0"
   /* 46945 */ "L3 READ L3BANK17\0"
   /* 46962 */ "L3 READ L3BANK18\0"
   /* 46979 */ "L3 READ L3BANK19\0"
   /* 46996 */ "L3 READ L3BANK2\0"
   /* 47012 */ "L3 READ L3BANK20\0"
   /* 47029 */ "L3 READ L3BANK21\0"
   /* 47046 */ "L3 READ L3BANK22\0"
   /* 47063 */ "L3 READ L3BANK23\0"
   /* 47080 */ "L3 READ L3BANK24\0"
   /* 47097 */ "L3 READ L3BANK25\0"
   /* 47114 */ "L3 READ L3BANK26\0"
   /* 47131 */ "L3 READ L3BANK27\0"
   /* 47148 */ "L3 READ L3BANK28\0"
   /* 47165 */ "L3 READ L3BANK29\0"
   /* 47182 */ "L3 READ L3BANK3\0"
   /* 47198 */ "L3 READ L3BANK30\0"
   /* 47215 */ "L3 READ L3BANK31\0"
   /* 47232 */ "L3 READ L3BANK4\0"
   /* 47248 */ "L3 READ L3BANK5\0"
   /* 47264 */ "L3 READ L3BANK6\0"
   /* 47280 */ "L3 READ L3BANK7\0"
   /* 47296 */ "L3 READ L3BANK8\0"
   /* 47312 */ "L3 READ L3BANK9\0"
   /* 47328 */ "L3 STALL L3BANK0\0"
   /* 47345 */ "L3 STALL L3BANK1\0"
   /* 47362 */ "L3 STALL L3BANK2\0"
   /* 47379 */ "L3 STALL L3BANK3\0"
   /* 47396 */ "L3 STALL L3BANK4\0"
   /* 47413 */ "L3 STALL L3BANK5\0"
   /* 47430 */ "L3 STALL L3BANK6\0"
   /* 47447 */ "L3 STALL L3BANK7\0"
   /* 47464 */ "L3 SUPERQ FULL L3BANK0\0"
   /* 47487 */ "L3 SUPERQ FULL L3BANK1\0"
   /* 47510 */ "L3 SUPERQ FULL L3BANK10\0"
   /* 47534 */ "L3 SUPERQ FULL L3BANK11\0"
   /* 47558 */ "L3 SUPERQ FULL L3BANK12\0"
   /* 47582 */ "L3 SUPERQ FULL L3BANK13\0"
   /* 47606 */ "L3 SUPERQ FULL L3BANK14\0"
   /* 47630 */ "L3 SUPERQ FULL L3BANK15\0"
   /* 47654 */ "L3 SUPERQ FULL L3BANK16\0"
   /* 47678 */ "L3 SUPERQ FULL L3BANK17\0"
   /* 47702 */ "L3 SUPERQ FULL L3BANK18\0"
   /* 47726 */ "L3 SUPERQ FULL L3BANK19\0"
   /* 47750 */ "L3 SUPERQ FULL L3BANK2\0"
   /* 47773 */ "L3 SUPERQ FULL L3BANK20\0"
   /* 47797 */ "L3 SUPERQ FULL L3BANK21\0"
   /* 47821 */ "L3 SUPERQ FULL L3BANK22\0"
   /* 47845 */ "L3 SUPERQ FULL L3BANK23\0"
   /* 47869 */ "L3 SUPERQ FULL L3BANK24\0"
   /* 47893 */ "L3 SUPERQ FULL L3BANK25\0"
   /* 47917 */ "L3 SUPERQ FULL L3BANK26\0"
   /* 47941 */ "L3 SUPERQ FULL L3BANK27\0"
   /* 47965 */ "L3 SUPERQ FULL L3BANK28\0"
   /* 47989 */ "L3 SUPERQ FULL L3BANK29\0"
   /* 48013 */ "L3 SUPERQ FULL L3BANK3\0"
   /* 48036 */ "L3 SUPERQ FULL L3BANK30\0"
   /* 48060 */ "L3 SUPERQ FULL L3BANK31\0"
   /* 48084 */ "L3 SUPERQ FULL L3BANK4\0"
   /* 48107 */ "L3 SUPERQ FULL L3BANK5\0"
   /* 48130 */ "L3 SUPERQ FULL L3BANK6\0"
   /* 48153 */ "L3 SUPERQ FULL L3BANK7\0"
   /* 48176 */ "L3 SUPERQ FULL L3BANK8\0"
   /* 48199 */ "L3 SUPERQ FULL L3BANK9\0"
   /* 48222 */ "L3 Sampler Throughput\0"
   /* 48244 */ "L3 Shader Throughput\0"
   /* 48265 */ "L3 Total Throughput\0"
   /* 48285 */ "L3 WRITE L3BANK0\0"
   /* 48302 */ "L3 WRITE L3BANK1\0"
   /* 48319 */ "L3 WRITE L3BANK10\0"
   /* 48337 */ "L3 WRITE L3BANK11\0"
   /* 48355 */ "L3 WRITE L3BANK12\0"
   /* 48373 */ "L3 WRITE L3BANK13\0"
   /* 48391 */ "L3 WRITE L3BANK14\0"
   /* 48409 */ "L3 WRITE L3BANK15\0"
   /* 48427 */ "L3 WRITE L3BANK16\0"
   /* 48445 */ "L3 WRITE L3BANK17\0"
   /* 48463 */ "L3 WRITE L3BANK18\0"
   /* 48481 */ "L3 WRITE L3BANK19\0"
   /* 48499 */ "L3 WRITE L3BANK2\0"
   /* 48516 */ "L3 WRITE L3BANK20\0"
   /* 48534 */ "L3 WRITE L3BANK21\0"
   /* 48552 */ "L3 WRITE L3BANK22\0"
   /* 48570 */ "L3 WRITE L3BANK23\0"
   /* 48588 */ "L3 WRITE L3BANK24\0"
   /* 48606 */ "L3 WRITE L3BANK25\0"
   /* 48624 */ "L3 WRITE L3BANK26\0"
   /* 48642 */ "L3 WRITE L3BANK27\0"
   /* 48660 */ "L3 WRITE L3BANK28\0"
   /* 48678 */ "L3 WRITE L3BANK29\0"
   /* 48696 */ "L3 WRITE L3BANK3\0"
   /* 48713 */ "L3 WRITE L3BANK30\0"
   /* 48731 */ "L3 WRITE L3BANK31\0"
   /* 48749 */ "L3 WRITE L3BANK4\0"
   /* 48766 */ "L3 WRITE L3BANK5\0"
   /* 48783 */ "L3 WRITE L3BANK6\0"
   /* 48800 */ "L3 WRITE L3BANK7\0"
   /* 48817 */ "L3 WRITE L3BANK8\0"
   /* 48834 */ "L3 WRITE L3BANK9\0"
   /* 48851 */ "LLC GPU Accesses\0"
   /* 48868 */ "LLC GPU Hits\0"
   /* 48881 */ "LLC GPU Read Accesses\0"
   /* 48903 */ "LLC GPU Throughput\0"
   /* 48922 */ "LLC GPU Write Accesses\0"
   /* 48945 */ "LOAD STORE CACHE ACCESS XECORE0\0"
   /* 48977 */ "LOAD STORE CACHE ACCESS XECORE1\0"
   /* 49009 */ "LOAD STORE CACHE ACCESS XECORE10\0"
   /* 49042 */ "LOAD STORE CACHE ACCESS XECORE11\0"
   /* 49075 */ "LOAD STORE CACHE ACCESS XECORE12\0"
   /* 49108 */ "LOAD STORE CACHE ACCESS XECORE13\0"
   /* 49141 */ "LOAD STORE CACHE ACCESS XECORE14\0"
   /* 49174 */ "LOAD STORE CACHE ACCESS XECORE15\0"
   /* 49207 */ "LOAD STORE CACHE ACCESS XECORE16\0"
   /* 49240 */ "LOAD STORE CACHE ACCESS XECORE17\0"
   /* 49273 */ "LOAD STORE CACHE ACCESS XECORE18\0"
   /* 49306 */ "LOAD STORE CACHE ACCESS XECORE19\0"
   /* 49339 */ "LOAD STORE CACHE ACCESS XECORE2\0"
   /* 49371 */ "LOAD STORE CACHE ACCESS XECORE20\0"
   /* 49404 */ "LOAD STORE CACHE ACCESS XECORE21\0"
   /* 49437 */ "LOAD STORE CACHE ACCESS XECORE22\0"
   /* 49470 */ "LOAD STORE CACHE ACCESS XECORE23\0"
   /* 49503 */ "LOAD STORE CACHE ACCESS XECORE24\0"
   /* 49536 */ "LOAD STORE CACHE ACCESS XECORE25\0"
   /* 49569 */ "LOAD STORE CACHE ACCESS XECORE26\0"
   /* 49602 */ "LOAD STORE CACHE ACCESS XECORE27\0"
   /* 49635 */ "LOAD STORE CACHE ACCESS XECORE28\0"
   /* 49668 */ "LOAD STORE CACHE ACCESS XECORE29\0"
   /* 49701 */ "LOAD STORE CACHE ACCESS XECORE3\0"
   /* 49733 */ "LOAD STORE CACHE ACCESS XECORE30\0"
   /* 49766 */ "LOAD STORE CACHE ACCESS XECORE31\0"
   /* 49799 */ "LOAD STORE CACHE ACCESS XECORE4\0"
   /* 49831 */ "LOAD STORE CACHE ACCESS XECORE5\0"
   /* 49863 */ "LOAD STORE CACHE ACCESS XECORE6\0"
   /* 49895 */ "LOAD STORE CACHE ACCESS XECORE7\0"
   /* 49927 */ "LOAD STORE CACHE ACCESS XECORE8\0"
   /* 49959 */ "LOAD STORE CACHE ACCESS XECORE9\0"
   /* 49991 */ "LOAD STORE CACHE BYTE READ\0"
   /* 50018 */ "LOAD STORE CACHE BYTE READ BANK0 XECORE0\0"
   /* 50059 */ "LOAD STORE CACHE BYTE READ BANK0 XECORE1\0"
   /* 50100 */ "LOAD STORE CACHE BYTE READ BANK0 XECORE2\0"
   /* 50141 */ "LOAD STORE CACHE BYTE READ BANK0 XECORE3\0"
   /* 50182 */ "LOAD STORE CACHE BYTE READ BANK0 XECORE4\0"
   /* 50223 */ "LOAD STORE CACHE BYTE READ BANK0 XECORE5\0"
   /* 50264 */ "LOAD STORE CACHE BYTE READ BANK0 XECORE6\0"
   /* 50305 */ "LOAD STORE CACHE BYTE READ BANK0 XECORE7\0"
   /* 50346 */ "LOAD STORE CACHE BYTE READ BANK1 XECORE0\0"
   /* 50387 */ "LOAD STORE CACHE BYTE READ BANK1 XECORE1\0"
   /* 50428 */ "LOAD STORE CACHE BYTE READ BANK1 XECORE2\0"
   /* 50469 */ "LOAD STORE CACHE BYTE READ BANK1 XECORE3\0"
   /* 50510 */ "LOAD STORE CACHE BYTE READ BANK1 XECORE4\0"
   /* 50551 */ "LOAD STORE CACHE BYTE READ BANK1 XECORE5\0"
   /* 50592 */ "LOAD STORE CACHE BYTE READ BANK1 XECORE6\0"
   /* 50633 */ "LOAD STORE CACHE BYTE READ BANK1 XECORE7\0"
   /* 50674 */ "LOAD STORE CACHE BYTE READ BANK2 XECORE0\0"
   /* 50715 */ "LOAD STORE CACHE BYTE READ BANK2 XECORE1\0"
   /* 50756 */ "LOAD STORE CACHE BYTE READ BANK2 XECORE2\0"
   /* 50797 */ "LOAD STORE CACHE BYTE READ BANK2 XECORE3\0"
   /* 50838 */ "LOAD STORE CACHE BYTE READ BANK2 XECORE4\0"
   /* 50879 */ "LOAD STORE CACHE BYTE READ BANK2 XECORE5\0"
   /* 50920 */ "LOAD STORE CACHE BYTE READ BANK2 XECORE6\0"
   /* 50961 */ "LOAD STORE CACHE BYTE READ BANK2 XECORE7\0"
   /* 51002 */ "LOAD STORE CACHE BYTE READ BANK3 XECORE0\0"
   /* 51043 */ "LOAD STORE CACHE BYTE READ BANK3 XECORE1\0"
   /* 51084 */ "LOAD STORE CACHE BYTE READ BANK3 XECORE2\0"
   /* 51125 */ "LOAD STORE CACHE BYTE READ BANK3 XECORE3\0"
   /* 51166 */ "LOAD STORE CACHE BYTE READ BANK3 XECORE4\0"
   /* 51207 */ "LOAD STORE CACHE BYTE READ BANK3 XECORE5\0"
   /* 51248 */ "LOAD STORE CACHE BYTE READ BANK3 XECORE6\0"
   /* 51289 */ "LOAD STORE CACHE BYTE READ BANK3 XECORE7\0"
   /* 51330 */ "LOAD STORE CACHE BYTE WRITE\0"
   /* 51358 */ "LOAD STORE CACHE BYTE WRITE BANK0 XECORE0\0"
   /* 51400 */ "LOAD STORE CACHE BYTE WRITE BANK0 XECORE1\0"
   /* 51442 */ "LOAD STORE CACHE BYTE WRITE BANK0 XECORE2\0"
   /* 51484 */ "LOAD STORE CACHE BYTE WRITE BANK0 XECORE3\0"
   /* 51526 */ "LOAD STORE CACHE BYTE WRITE BANK0 XECORE4\0"
   /* 51568 */ "LOAD STORE CACHE BYTE WRITE BANK0 XECORE5\0"
   /* 51610 */ "LOAD STORE CACHE BYTE WRITE BANK0 XECORE6\0"
   /* 51652 */ "LOAD STORE CACHE BYTE WRITE BANK0 XECORE7\0"
   /* 51694 */ "LOAD STORE CACHE BYTE WRITE BANK1 XECORE0\0"
   /* 51736 */ "LOAD STORE CACHE BYTE WRITE BANK1 XECORE1\0"
   /* 51778 */ "LOAD STORE CACHE BYTE WRITE BANK1 XECORE2\0"
   /* 51820 */ "LOAD STORE CACHE BYTE WRITE BANK1 XECORE3\0"
   /* 51862 */ "LOAD STORE CACHE BYTE WRITE BANK1 XECORE4\0"
   /* 51904 */ "LOAD STORE CACHE BYTE WRITE BANK1 XECORE5\0"
   /* 51946 */ "LOAD STORE CACHE BYTE WRITE BANK1 XECORE6\0"
   /* 51988 */ "LOAD STORE CACHE BYTE WRITE BANK1 XECORE7\0"
   /* 52030 */ "LOAD STORE CACHE BYTE WRITE BANK2 XECORE0\0"
   /* 52072 */ "LOAD STORE CACHE BYTE WRITE BANK2 XECORE1\0"
   /* 52114 */ "LOAD STORE CACHE BYTE WRITE BANK2 XECORE2\0"
   /* 52156 */ "LOAD STORE CACHE BYTE WRITE BANK2 XECORE3\0"
   /* 52198 */ "LOAD STORE CACHE BYTE WRITE BANK2 XECORE4\0"
   /* 52240 */ "LOAD STORE CACHE BYTE WRITE BANK2 XECORE5\0"
   /* 52282 */ "LOAD STORE CACHE BYTE WRITE BANK2 XECORE6\0"
   /* 52324 */ "LOAD STORE CACHE BYTE WRITE BANK2 XECORE7\0"
   /* 52366 */ "LOAD STORE CACHE BYTE WRITE BANK3 XECORE0\0"
   /* 52408 */ "LOAD STORE CACHE BYTE WRITE BANK3 XECORE1\0"
   /* 52450 */ "LOAD STORE CACHE BYTE WRITE BANK3 XECORE2\0"
   /* 52492 */ "LOAD STORE CACHE BYTE WRITE BANK3 XECORE3\0"
   /* 52534 */ "LOAD STORE CACHE BYTE WRITE BANK3 XECORE4\0"
   /* 52576 */ "LOAD STORE CACHE BYTE WRITE BANK3 XECORE5\0"
   /* 52618 */ "LOAD STORE CACHE BYTE WRITE BANK3 XECORE6\0"
   /* 52660 */ "LOAD STORE CACHE BYTE WRITE BANK3 XECORE7\0"
   /* 52702 */ "LOAD STORE CACHE HIT XECORE0\0"
   /* 52731 */ "LOAD STORE CACHE HIT XECORE1\0"
   /* 52760 */ "LOAD STORE CACHE HIT XECORE10\0"
   /* 52790 */ "LOAD STORE CACHE HIT XECORE11\0"
   /* 52820 */ "LOAD STORE CACHE HIT XECORE12\0"
   /* 52850 */ "LOAD STORE CACHE HIT XECORE13\0"
   /* 52880 */ "LOAD STORE CACHE HIT XECORE14\0"
   /* 52910 */ "LOAD STORE CACHE HIT XECORE15\0"
   /* 52940 */ "LOAD STORE CACHE HIT XECORE16\0"
   /* 52970 */ "LOAD STORE CACHE HIT XECORE17\0"
   /* 53000 */ "LOAD STORE CACHE HIT XECORE18\0"
   /* 53030 */ "LOAD STORE CACHE HIT XECORE19\0"
   /* 53060 */ "LOAD STORE CACHE HIT XECORE2\0"
   /* 53089 */ "LOAD STORE CACHE HIT XECORE20\0"
   /* 53119 */ "LOAD STORE CACHE HIT XECORE21\0"
   /* 53149 */ "LOAD STORE CACHE HIT XECORE22\0"
   /* 53179 */ "LOAD STORE CACHE HIT XECORE23\0"
   /* 53209 */ "LOAD STORE CACHE HIT XECORE24\0"
   /* 53239 */ "LOAD STORE CACHE HIT XECORE25\0"
   /* 53269 */ "LOAD STORE CACHE HIT XECORE26\0"
   /* 53299 */ "LOAD STORE CACHE HIT XECORE27\0"
   /* 53329 */ "LOAD STORE CACHE HIT XECORE28\0"
   /* 53359 */ "LOAD STORE CACHE HIT XECORE29\0"
   /* 53389 */ "LOAD STORE CACHE HIT XECORE3\0"
   /* 53418 */ "LOAD STORE CACHE HIT XECORE30\0"
   /* 53448 */ "LOAD STORE CACHE HIT XECORE31\0"
   /* 53478 */ "LOAD STORE CACHE HIT XECORE4\0"
   /* 53507 */ "LOAD STORE CACHE HIT XECORE5\0"
   /* 53536 */ "LOAD STORE CACHE HIT XECORE6\0"
   /* 53565 */ "LOAD STORE CACHE HIT XECORE7\0"
   /* 53594 */ "LOAD STORE CACHE HIT XECORE8\0"
   /* 53623 */ "LOAD STORE CACHE HIT XECORE9\0"
   /* 53652 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE0\0"
   /* 53693 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE1\0"
   /* 53734 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE10\0"
   /* 53776 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE11\0"
   /* 53818 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE12\0"
   /* 53860 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE13\0"
   /* 53902 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE14\0"
   /* 53944 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE15\0"
   /* 53986 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE16\0"
   /* 54028 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE17\0"
   /* 54070 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE18\0"
   /* 54112 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE19\0"
   /* 54154 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE2\0"
   /* 54195 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE20\0"
   /* 54237 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE21\0"
   /* 54279 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE22\0"
   /* 54321 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE23\0"
   /* 54363 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE24\0"
   /* 54405 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE25\0"
   /* 54447 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE26\0"
   /* 54489 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE27\0"
   /* 54531 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE28\0"
   /* 54573 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE29\0"
   /* 54615 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE3\0"
   /* 54656 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE30\0"
   /* 54698 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE31\0"
   /* 54740 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE4\0"
   /* 54781 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE5\0"
   /* 54822 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE6\0"
   /* 54863 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE7\0"
   /* 54904 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE8\0"
   /* 54945 */ "LOAD STORE CACHE INPUT AVAILABLE XECORE9\0"
   /* 54986 */ "LOAD STORE CACHE L3 READ XECORE0\0"
   /* 55019 */ "LOAD STORE CACHE L3 READ XECORE1\0"
   /* 55052 */ "LOAD STORE CACHE L3 READ XECORE10\0"
   /* 55086 */ "LOAD STORE CACHE L3 READ XECORE11\0"
   /* 55120 */ "LOAD STORE CACHE L3 READ XECORE12\0"
   /* 55154 */ "LOAD STORE CACHE L3 READ XECORE13\0"
   /* 55188 */ "LOAD STORE CACHE L3 READ XECORE14\0"
   /* 55222 */ "LOAD STORE CACHE L3 READ XECORE15\0"
   /* 55256 */ "LOAD STORE CACHE L3 READ XECORE16\0"
   /* 55290 */ "LOAD STORE CACHE L3 READ XECORE17\0"
   /* 55324 */ "LOAD STORE CACHE L3 READ XECORE18\0"
   /* 55358 */ "LOAD STORE CACHE L3 READ XECORE19\0"
   /* 55392 */ "LOAD STORE CACHE L3 READ XECORE2\0"
   /* 55425 */ "LOAD STORE CACHE L3 READ XECORE20\0"
   /* 55459 */ "LOAD STORE CACHE L3 READ XECORE21\0"
   /* 55493 */ "LOAD STORE CACHE L3 READ XECORE22\0"
   /* 55527 */ "LOAD STORE CACHE L3 READ XECORE23\0"
   /* 55561 */ "LOAD STORE CACHE L3 READ XECORE24\0"
   /* 55595 */ "LOAD STORE CACHE L3 READ XECORE25\0"
   /* 55629 */ "LOAD STORE CACHE L3 READ XECORE26\0"
   /* 55663 */ "LOAD STORE CACHE L3 READ XECORE27\0"
   /* 55697 */ "LOAD STORE CACHE L3 READ XECORE28\0"
   /* 55731 */ "LOAD STORE CACHE L3 READ XECORE29\0"
   /* 55765 */ "LOAD STORE CACHE L3 READ XECORE3\0"
   /* 55798 */ "LOAD STORE CACHE L3 READ XECORE30\0"
   /* 55832 */ "LOAD STORE CACHE L3 READ XECORE31\0"
   /* 55866 */ "LOAD STORE CACHE L3 READ XECORE4\0"
   /* 55899 */ "LOAD STORE CACHE L3 READ XECORE5\0"
   /* 55932 */ "LOAD STORE CACHE L3 READ XECORE6\0"
   /* 55965 */ "LOAD STORE CACHE L3 READ XECORE7\0"
   /* 55998 */ "LOAD STORE CACHE L3 READ XECORE8\0"
   /* 56031 */ "LOAD STORE CACHE L3 READ XECORE9\0"
   /* 56064 */ "LOAD STORE CACHE L3 WRITE XECORE0\0"
   /* 56098 */ "LOAD STORE CACHE L3 WRITE XECORE1\0"
   /* 56132 */ "LOAD STORE CACHE L3 WRITE XECORE10\0"
   /* 56167 */ "LOAD STORE CACHE L3 WRITE XECORE11\0"
   /* 56202 */ "LOAD STORE CACHE L3 WRITE XECORE12\0"
   /* 56237 */ "LOAD STORE CACHE L3 WRITE XECORE13\0"
   /* 56272 */ "LOAD STORE CACHE L3 WRITE XECORE14\0"
   /* 56307 */ "LOAD STORE CACHE L3 WRITE XECORE15\0"
   /* 56342 */ "LOAD STORE CACHE L3 WRITE XECORE16\0"
   /* 56377 */ "LOAD STORE CACHE L3 WRITE XECORE17\0"
   /* 56412 */ "LOAD STORE CACHE L3 WRITE XECORE18\0"
   /* 56447 */ "LOAD STORE CACHE L3 WRITE XECORE19\0"
   /* 56482 */ "LOAD STORE CACHE L3 WRITE XECORE2\0"
   /* 56516 */ "LOAD STORE CACHE L3 WRITE XECORE20\0"
   /* 56551 */ "LOAD STORE CACHE L3 WRITE XECORE21\0"
   /* 56586 */ "LOAD STORE CACHE L3 WRITE XECORE22\0"
   /* 56621 */ "LOAD STORE CACHE L3 WRITE XECORE23\0"
   /* 56656 */ "LOAD STORE CACHE L3 WRITE XECORE24\0"
   /* 56691 */ "LOAD STORE CACHE L3 WRITE XECORE25\0"
   /* 56726 */ "LOAD STORE CACHE L3 WRITE XECORE26\0"
   /* 56761 */ "LOAD STORE CACHE L3 WRITE XECORE27\0"
   /* 56796 */ "LOAD STORE CACHE L3 WRITE XECORE28\0"
   /* 56831 */ "LOAD STORE CACHE L3 WRITE XECORE29\0"
   /* 56866 */ "LOAD STORE CACHE L3 WRITE XECORE3\0"
   /* 56900 */ "LOAD STORE CACHE L3 WRITE XECORE30\0"
   /* 56935 */ "LOAD STORE CACHE L3 WRITE XECORE31\0"
   /* 56970 */ "LOAD STORE CACHE L3 WRITE XECORE4\0"
   /* 57004 */ "LOAD STORE CACHE L3 WRITE XECORE5\0"
   /* 57038 */ "LOAD STORE CACHE L3 WRITE XECORE6\0"
   /* 57072 */ "LOAD STORE CACHE L3 WRITE XECORE7\0"
   /* 57106 */ "LOAD STORE CACHE L3 WRITE XECORE8\0"
   /* 57140 */ "LOAD STORE CACHE L3 WRITE XECORE9\0"
   /* 57174 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE0\0"
   /* 57227 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE1\0"
   /* 57280 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE10\0"
   /* 57334 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE11\0"
   /* 57388 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE12\0"
   /* 57442 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE13\0"
   /* 57496 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE14\0"
   /* 57550 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE15\0"
   /* 57604 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE16\0"
   /* 57658 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE17\0"
   /* 57712 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE18\0"
   /* 57766 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE19\0"
   /* 57820 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE2\0"
   /* 57873 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE20\0"
   /* 57927 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE21\0"
   /* 57981 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE22\0"
   /* 58035 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE23\0"
   /* 58089 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE24\0"
   /* 58143 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE25\0"
   /* 58197 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE26\0"
   /* 58251 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE27\0"
   /* 58305 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE28\0"
   /* 58359 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE29\0"
   /* 58413 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE3\0"
   /* 58466 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE30\0"
   /* 58520 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE31\0"
   /* 58574 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE4\0"
   /* 58627 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE5\0"
   /* 58680 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE6\0"
   /* 58733 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE7\0"
   /* 58786 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE8\0"
   /* 58839 */ "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE9\0"
   /* 58892 */ "LOAD STORE CACHE OUTPUT READY XECORE0\0"
   /* 58930 */ "LOAD STORE CACHE OUTPUT READY XECORE1\0"
   /* 58968 */ "LOAD STORE CACHE OUTPUT READY XECORE10\0"
   /* 59007 */ "LOAD STORE CACHE OUTPUT READY XECORE11\0"
   /* 59046 */ "LOAD STORE CACHE OUTPUT READY XECORE12\0"
   /* 59085 */ "LOAD STORE CACHE OUTPUT READY XECORE13\0"
   /* 59124 */ "LOAD STORE CACHE OUTPUT READY XECORE14\0"
   /* 59163 */ "LOAD STORE CACHE OUTPUT READY XECORE15\0"
   /* 59202 */ "LOAD STORE CACHE OUTPUT READY XECORE16\0"
   /* 59241 */ "LOAD STORE CACHE OUTPUT READY XECORE17\0"
   /* 59280 */ "LOAD STORE CACHE OUTPUT READY XECORE18\0"
   /* 59319 */ "LOAD STORE CACHE OUTPUT READY XECORE19\0"
   /* 59358 */ "LOAD STORE CACHE OUTPUT READY XECORE2\0"
   /* 59396 */ "LOAD STORE CACHE OUTPUT READY XECORE20\0"
   /* 59435 */ "LOAD STORE CACHE OUTPUT READY XECORE21\0"
   /* 59474 */ "LOAD STORE CACHE OUTPUT READY XECORE22\0"
   /* 59513 */ "LOAD STORE CACHE OUTPUT READY XECORE23\0"
   /* 59552 */ "LOAD STORE CACHE OUTPUT READY XECORE24\0"
   /* 59591 */ "LOAD STORE CACHE OUTPUT READY XECORE25\0"
   /* 59630 */ "LOAD STORE CACHE OUTPUT READY XECORE26\0"
   /* 59669 */ "LOAD STORE CACHE OUTPUT READY XECORE27\0"
   /* 59708 */ "LOAD STORE CACHE OUTPUT READY XECORE28\0"
   /* 59747 */ "LOAD STORE CACHE OUTPUT READY XECORE29\0"
   /* 59786 */ "LOAD STORE CACHE OUTPUT READY XECORE3\0"
   /* 59824 */ "LOAD STORE CACHE OUTPUT READY XECORE30\0"
   /* 59863 */ "LOAD STORE CACHE OUTPUT READY XECORE31\0"
   /* 59902 */ "LOAD STORE CACHE OUTPUT READY XECORE4\0"
   /* 59940 */ "LOAD STORE CACHE OUTPUT READY XECORE5\0"
   /* 59978 */ "LOAD STORE CACHE OUTPUT READY XECORE6\0"
   /* 60016 */ "LOAD STORE CACHE OUTPUT READY XECORE7\0"
   /* 60054 */ "LOAD STORE CACHE OUTPUT READY XECORE8\0"
   /* 60092 */ "LOAD STORE CACHE OUTPUT READY XECORE9\0"
   /* 60130 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0\0"
   /* 60175 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1\0"
   /* 60220 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE10\0"
   /* 60266 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE11\0"
   /* 60312 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE12\0"
   /* 60358 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE13\0"
   /* 60404 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE14\0"
   /* 60450 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE15\0"
   /* 60496 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE16\0"
   /* 60542 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE17\0"
   /* 60588 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE18\0"
   /* 60634 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE19\0"
   /* 60680 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2\0"
   /* 60725 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE20\0"
   /* 60771 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE21\0"
   /* 60817 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE22\0"
   /* 60863 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE23\0"
   /* 60909 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE24\0"
   /* 60955 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE25\0"
   /* 61001 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE26\0"
   /* 61047 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE27\0"
   /* 61093 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE28\0"
   /* 61139 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE29\0"
   /* 61185 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3\0"
   /* 61230 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE30\0"
   /* 61276 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE31\0"
   /* 61322 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4\0"
   /* 61367 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5\0"
   /* 61412 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6\0"
   /* 61457 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7\0"
   /* 61502 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE8\0"
   /* 61547 */ "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE9\0"
   /* 61592 */ "Late Depth Test Fails\0"
   /* 61614 */ "Late Stencil Test Fails\0"
   /* 61638 */ "Non-PS Thread Ready For Dispatch on Slice0 DualSubslice0 Thread Dispatcher\0"
   /* 61713 */ "Non-PS Thread Ready For Dispatch on Slice0 DualSubslice1 Thread Dispatcher\0"
   /* 61788 */ "Non-PS Thread Ready For Dispatch on Slice0 DualSubslice2 Thread Dispatcher\0"
   /* 61863 */ "Non-PS Thread Ready For Dispatch on Slice0 DualSubslice3 Thread Dispatcher\0"
   /* 61938 */ "Non-PS Thread Ready For Dispatch on Slice0 DualSubslice4 Thread Dispatcher\0"
   /* 62013 */ "Non-PS Thread Ready For Dispatch on Slice0 DualSubslice5 Thread Dispatcher\0"
   /* 62088 */ "Non-PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher\0"
   /* 62159 */ "Non-PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher\0"
   /* 62230 */ "Non-PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher\0"
   /* 62301 */ "Non-PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher\0"
   /* 62372 */ "Non-PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher\0"
   /* 62443 */ "Non-PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher\0"
   /* 62514 */ "Non-PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher\0"
   /* 62585 */ "Non-PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher\0"
   /* 62656 */ "Non-PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher\0"
   /* 62726 */ "Non-PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher\0"
   /* 62796 */ "Non-PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher\0"
   /* 62866 */ "Non-PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher\0"
   /* 62936 */ "Non-PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher\0"
   /* 63006 */ "Non-PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher\0"
   /* 63076 */ "Non-PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher\0"
   /* 63146 */ "Non-PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher\0"
   /* 63216 */ "Non-PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher\0"
   /* 63286 */ "Non-PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher\0"
   /* 63356 */ "Non-PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher\0"
   /* 63426 */ "Non-PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher\0"
   /* 63496 */ "Non-PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher\0"
   /* 63566 */ "Non-PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher\0"
   /* 63636 */ "Non-PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher\0"
   /* 63706 */ "Non-PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher\0"
   /* 63776 */ "Non-PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher\0"
   /* 63846 */ "Non-PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher\0"
   /* 63916 */ "Non-PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher\0"
   /* 63986 */ "Non-PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher\0"
   /* 64056 */ "Non-PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher\0"
   /* 64126 */ "Non-PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher\0"
   /* 64196 */ "Non-PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher\0"
   /* 64266 */ "Non-PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher\0"
   /* 64336 */ "Non-PS Thread Ready For Dispatch on Slice6 Xe Core0 Thread Dispatcher\0"
   /* 64406 */ "Non-PS Thread Ready For Dispatch on Slice6 Xe Core1 Thread Dispatcher\0"
   /* 64476 */ "Non-PS Thread Ready For Dispatch on Slice6 Xe Core2 Thread Dispatcher\0"
   /* 64546 */ "Non-PS Thread Ready For Dispatch on Slice6 Xe Core3 Thread Dispatcher\0"
   /* 64616 */ "Non-PS Thread Ready For Dispatch on Slice7 Xe Core0 Thread Dispatcher\0"
   /* 64686 */ "Non-PS Thread Ready For Dispatch on Slice7 Xe Core1 Thread Dispatcher\0"
   /* 64756 */ "Non-PS Thread Ready For Dispatch on Slice7 Xe Core2 Thread Dispatcher\0"
   /* 64826 */ "Non-PS Thread Ready For Dispatch on Slice7 Xe Core3 Thread Dispatcher\0"
   /* 64896 */ "NonPS Thread Ready For Dispatch on Slice0 Subslice0\0"
   /* 64948 */ "NonPS Thread Ready For Dispatch on Slice0 Subslice1\0"
   /* 65000 */ "NonPS Thread Ready For Dispatch on Slice0 Subslice2\0"
   /* 65052 */ "NonPS Thread Ready For Dispatch on Slice1 Subslice0\0"
   /* 65104 */ "NonPS Thread Ready For Dispatch on Slice1 Subslice1\0"
   /* 65156 */ "NonPS Thread Ready For Dispatch on Slice1 Subslice2\0"
   /* 65208 */ "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0\0"
   /* 65257 */ "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1\0"
   /* 65306 */ "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE2\0"
   /* 65355 */ "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE3\0"
   /* 65404 */ "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE4\0"
   /* 65453 */ "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE5\0"
   /* 65502 */ "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE6\0"
   /* 65551 */ "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE7\0"
   /* 65600 */ "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0\0"
   /* 65648 */ "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1\0"
   /* 65696 */ "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE2\0"
   /* 65744 */ "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE3\0"
   /* 65792 */ "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE4\0"
   /* 65840 */ "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE5\0"
   /* 65888 */ "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE6\0"
   /* 65936 */ "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE7\0"
   /* 65984 */ "PIXEL BACKEND INPUT AVAILABLE _L3NODE0\0"
   /* 66023 */ "PIXEL BACKEND INPUT AVAILABLE _L3NODE1\0"
   /* 66062 */ "PIXEL BACKEND OUTPUT READY _L3NODE0\0"
   /* 66098 */ "PIXEL BACKEND OUTPUT READY _L3NODE1\0"
   /* 66134 */ "PIXEL BLEND\0"
   /* 66146 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE0\0"
   /* 66188 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE1\0"
   /* 66230 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE10\0"
   /* 66273 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE11\0"
   /* 66316 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE12\0"
   /* 66359 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE13\0"
   /* 66402 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE14\0"
   /* 66445 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE15\0"
   /* 66488 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE2\0"
   /* 66530 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE3\0"
   /* 66572 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE4\0"
   /* 66614 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE5\0"
   /* 66656 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE6\0"
   /* 66698 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE7\0"
   /* 66740 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE8\0"
   /* 66782 */ "PIXEL POST PROCESS INPUT AVAILABLE CPIPE9\0"
   /* 66824 */ "PIXEL POST PROCESS INPUT AVAILABLE XECORE0\0"
   /* 66867 */ "PIXEL POST PROCESS INPUT AVAILABLE XECORE1\0"
   /* 66910 */ "PIXEL POST PROCESS INPUT AVAILABLE XECORE2\0"
   /* 66953 */ "PIXEL POST PROCESS INPUT AVAILABLE XECORE3\0"
   /* 66996 */ "PIXEL POST PROCESS INPUT AVAILABLE XECORE4\0"
   /* 67039 */ "PIXEL POST PROCESS INPUT AVAILABLE XECORE5\0"
   /* 67082 */ "PIXEL POST PROCESS INPUT AVAILABLE XECORE6\0"
   /* 67125 */ "PIXEL POST PROCESS INPUT AVAILABLE XECORE7\0"
   /* 67168 */ "PIXEL POST PROCESS OUTPUT READY CPIPE0\0"
   /* 67207 */ "PIXEL POST PROCESS OUTPUT READY CPIPE1\0"
   /* 67246 */ "PIXEL POST PROCESS OUTPUT READY CPIPE10\0"
   /* 67286 */ "PIXEL POST PROCESS OUTPUT READY CPIPE11\0"
   /* 67326 */ "PIXEL POST PROCESS OUTPUT READY CPIPE12\0"
   /* 67366 */ "PIXEL POST PROCESS OUTPUT READY CPIPE13\0"
   /* 67406 */ "PIXEL POST PROCESS OUTPUT READY CPIPE14\0"
   /* 67446 */ "PIXEL POST PROCESS OUTPUT READY CPIPE15\0"
   /* 67486 */ "PIXEL POST PROCESS OUTPUT READY CPIPE2\0"
   /* 67525 */ "PIXEL POST PROCESS OUTPUT READY CPIPE3\0"
   /* 67564 */ "PIXEL POST PROCESS OUTPUT READY CPIPE4\0"
   /* 67603 */ "PIXEL POST PROCESS OUTPUT READY CPIPE5\0"
   /* 67642 */ "PIXEL POST PROCESS OUTPUT READY CPIPE6\0"
   /* 67681 */ "PIXEL POST PROCESS OUTPUT READY CPIPE7\0"
   /* 67720 */ "PIXEL POST PROCESS OUTPUT READY CPIPE8\0"
   /* 67759 */ "PIXEL POST PROCESS OUTPUT READY CPIPE9\0"
   /* 67798 */ "PIXEL WRITE\0"
   /* 67810 */ "POSTPS DEPTH STENCIL ALPHA TEST FAIL\0"
   /* 67847 */ "PS EM Pipe Active\0"
   /* 67865 */ "PS FPU Pipe Active\0"
   /* 67884 */ "PS FPU0 Pipe Active\0"
   /* 67904 */ "PS FPU1 Pipe Active\0"
   /* 67924 */ "PS OUTPUT AVAILABLE CPIPE0\0"
   /* 67951 */ "PS OUTPUT AVAILABLE CPIPE1\0"
   /* 67978 */ "PS OUTPUT AVAILABLE CPIPE10\0"
   /* 68006 */ "PS OUTPUT AVAILABLE CPIPE11\0"
   /* 68034 */ "PS OUTPUT AVAILABLE CPIPE12\0"
   /* 68062 */ "PS OUTPUT AVAILABLE CPIPE13\0"
   /* 68090 */ "PS OUTPUT AVAILABLE CPIPE14\0"
   /* 68118 */ "PS OUTPUT AVAILABLE CPIPE15\0"
   /* 68146 */ "PS OUTPUT AVAILABLE CPIPE2\0"
   /* 68173 */ "PS OUTPUT AVAILABLE CPIPE3\0"
   /* 68200 */ "PS OUTPUT AVAILABLE CPIPE4\0"
   /* 68227 */ "PS OUTPUT AVAILABLE CPIPE5\0"
   /* 68254 */ "PS OUTPUT AVAILABLE CPIPE6\0"
   /* 68281 */ "PS OUTPUT AVAILABLE CPIPE7\0"
   /* 68308 */ "PS OUTPUT AVAILABLE CPIPE8\0"
   /* 68335 */ "PS OUTPUT AVAILABLE CPIPE9\0"
   /* 68362 */ "PS Send Pipeline Active\0"
   /* 68386 */ "PS Thread Ready For Dispatch on Slice0 Dualsubslice0 Thread Dispatcher\0"
   /* 68457 */ "PS Thread Ready For Dispatch on Slice0 Dualsubslice1 Thread Dispatcher\0"
   /* 68528 */ "PS Thread Ready For Dispatch on Slice0 Dualsubslice2 Thread Dispatcher\0"
   /* 68599 */ "PS Thread Ready For Dispatch on Slice0 Dualsubslice3 Thread Dispatcher\0"
   /* 68670 */ "PS Thread Ready For Dispatch on Slice0 Dualsubslice4 Thread Dispatcher\0"
   /* 68741 */ "PS Thread Ready For Dispatch on Slice0 Dualsubslice5 Thread Dispatcher\0"
   /* 68812 */ "PS Thread Ready For Dispatch on Slice0 Subslice0\0"
   /* 68861 */ "PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher\0"
   /* 68928 */ "PS Thread Ready For Dispatch on Slice0 Subslice1\0"
   /* 68977 */ "PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher\0"
   /* 69044 */ "PS Thread Ready For Dispatch on Slice0 Subslice2\0"
   /* 69093 */ "PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher\0"
   /* 69160 */ "PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher\0"
   /* 69227 */ "PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher\0"
   /* 69294 */ "PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher\0"
   /* 69361 */ "PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher\0"
   /* 69428 */ "PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher\0"
   /* 69495 */ "PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher\0"
   /* 69561 */ "PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher\0"
   /* 69627 */ "PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher\0"
   /* 69693 */ "PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher\0"
   /* 69759 */ "PS Thread Ready For Dispatch on Slice1 Subslice0\0"
   /* 69808 */ "PS Thread Ready For Dispatch on Slice1 Subslice1\0"
   /* 69857 */ "PS Thread Ready For Dispatch on Slice1 Subslice2\0"
   /* 69906 */ "PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher\0"
   /* 69972 */ "PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher\0"
   /* 70038 */ "PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher\0"
   /* 70104 */ "PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher\0"
   /* 70170 */ "PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher\0"
   /* 70236 */ "PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher\0"
   /* 70302 */ "PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher\0"
   /* 70368 */ "PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher\0"
   /* 70434 */ "PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher\0"
   /* 70500 */ "PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher\0"
   /* 70566 */ "PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher\0"
   /* 70632 */ "PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher\0"
   /* 70698 */ "PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher\0"
   /* 70764 */ "PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher\0"
   /* 70830 */ "PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher\0"
   /* 70896 */ "PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher\0"
   /* 70962 */ "PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher\0"
   /* 71028 */ "PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher\0"
   /* 71094 */ "PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher\0"
   /* 71160 */ "PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher\0"
   /* 71226 */ "PS Thread Ready For Dispatch on Slice6 Xe Core0 Thread Dispatcher\0"
   /* 71292 */ "PS Thread Ready For Dispatch on Slice6 Xe Core1 Thread Dispatcher\0"
   /* 71358 */ "PS Thread Ready For Dispatch on Slice6 Xe Core2 Thread Dispatcher\0"
   /* 71424 */ "PS Thread Ready For Dispatch on Slice6 Xe Core3 Thread Dispatcher\0"
   /* 71490 */ "PS Thread Ready For Dispatch on Slice7 Xe Core0 Thread Dispatcher\0"
   /* 71556 */ "PS Thread Ready For Dispatch on Slice7 Xe Core1 Thread Dispatcher\0"
   /* 71622 */ "PS Thread Ready For Dispatch on Slice7 Xe Core2 Thread Dispatcher\0"
   /* 71688 */ "PS Thread Ready For Dispatch on Slice7 Xe Core3 Thread Dispatcher\0"
   /* 71754 */ "PS Threads Dispatched\0"
   /* 71776 */ "PS00 Output Available\0"
   /* 71798 */ "PS01 Output Available\0"
   /* 71820 */ "PS10 Output Available\0"
   /* 71842 */ "PS11 Output Available\0"
   /* 71864 */ "PS20 Output Available\0"
   /* 71886 */ "PS21 Output Available\0"
   /* 71908 */ "PS30 Output Available\0"
   /* 71930 */ "PS31 Output Available\0"
   /* 71952 */ "Pixel Values 00 Ready\0"
   /* 71974 */ "Pixel Values 01 Ready\0"
   /* 71996 */ "Pixel Values 10 Ready\0"
   /* 72018 */ "Pixel Values 11 Ready\0"
   /* 72040 */ "Pixel Values 20 Ready\0"
   /* 72062 */ "Pixel Values 21 Ready\0"
   /* 72084 */ "Pixel Values 30 Ready\0"
   /* 72106 */ "Pixel Values 31 Ready\0"
   /* 72128 */ "Pixels Failing Tests\0"
   /* 72149 */ "Polygon (Slice0) Data Ready\0"
   /* 72177 */ "Polygon (Slice1) Data Ready\0"
   /* 72205 */ "Polygon (Slice2) Data Ready\0"
   /* 72233 */ "Polygon (Slice3) Data Ready\0"
   /* 72261 */ "Polygon (Slice4) Data Ready\0"
   /* 72289 */ "Polygon (Slice5) Data Ready\0"
   /* 72317 */ "Polygon (Slice6) Data Ready\0"
   /* 72345 */ "Polygon (Slice7) Data Ready\0"
   /* 72373 */ "Polygon Data Ready\0"
   /* 72392 */ "Posh Ring Busy\0"
   /* 72407 */ "Quad0 L3 Bank0 Input Available\0"
   /* 72438 */ "Quad0 L3 Bank0 Output Ready\0"
   /* 72466 */ "Quad0 L3 Bank1 Input Available\0"
   /* 72497 */ "Quad0 L3 Bank1 Output Ready\0"
   /* 72525 */ "Quad0 L3 Bank2 Input Available\0"
   /* 72556 */ "Quad0 L3 Bank2 Output Ready\0"
   /* 72584 */ "Quad0 L3 Bank3 Input Available\0"
   /* 72615 */ "Quad0 L3 Bank3 Output Ready\0"
   /* 72643 */ "Quad0 L3 Bank4 Input Available\0"
   /* 72674 */ "Quad0 L3 Bank4 Output Ready\0"
   /* 72702 */ "Quad0 L3 Bank5 Input Available\0"
   /* 72733 */ "Quad0 L3 Bank5 Output Ready\0"
   /* 72761 */ "Quad0 L3 Bank6 Input Available\0"
   /* 72792 */ "Quad0 L3 Bank6 Output Ready\0"
   /* 72820 */ "Quad0 L3 Bank7 Input Available\0"
   /* 72851 */ "Quad0 L3 Bank7 Output Ready\0"
   /* 72879 */ "Quad1 L3 Bank0 Input Available\0"
   /* 72910 */ "Quad1 L3 Bank0 Output Ready\0"
   /* 72938 */ "Quad1 L3 Bank1 Input Available\0"
   /* 72969 */ "Quad1 L3 Bank1 Output Ready\0"
   /* 72997 */ "Quad1 L3 Bank2 Input Available\0"
   /* 73028 */ "Quad1 L3 Bank2 Output Ready\0"
   /* 73056 */ "Quad1 L3 Bank3 Input Available\0"
   /* 73087 */ "Quad1 L3 Bank3 Output Ready\0"
   /* 73115 */ "Quad1 L3 Bank4 Input Available\0"
   /* 73146 */ "Quad1 L3 Bank4 Output Ready\0"
   /* 73174 */ "Quad1 L3 Bank5 Input Available\0"
   /* 73205 */ "Quad1 L3 Bank5 Output Ready\0"
   /* 73233 */ "Quad1 L3 Bank6 Input Available\0"
   /* 73264 */ "Quad1 L3 Bank6 Output Ready\0"
   /* 73292 */ "Quad1 L3 Bank7 Input Available\0"
   /* 73323 */ "Quad1 L3 Bank7 Output Ready\0"
   /* 73351 */ "Quad2 L3 Bank0 Input Available\0"
   /* 73382 */ "Quad2 L3 Bank0 Output Ready\0"
   /* 73410 */ "Quad2 L3 Bank1 Input Available\0"
   /* 73441 */ "Quad2 L3 Bank1 Output Ready\0"
   /* 73469 */ "Quad2 L3 Bank2 Input Available\0"
   /* 73500 */ "Quad2 L3 Bank2 Output Ready\0"
   /* 73528 */ "Quad2 L3 Bank3 Input Available\0"
   /* 73559 */ "Quad2 L3 Bank3 Output Ready\0"
   /* 73587 */ "Quad2 L3 Bank4 Input Available\0"
   /* 73618 */ "Quad2 L3 Bank4 Output Ready\0"
   /* 73646 */ "Quad2 L3 Bank5 Input Available\0"
   /* 73677 */ "Quad2 L3 Bank5 Output Ready\0"
   /* 73705 */ "Quad2 L3 Bank6 Input Available\0"
   /* 73736 */ "Quad2 L3 Bank6 Output Ready\0"
   /* 73764 */ "Quad2 L3 Bank7 Input Available\0"
   /* 73795 */ "Quad2 L3 Bank7 Output Ready\0"
   /* 73823 */ "Quad3 L3 Bank0 Input Available\0"
   /* 73854 */ "Quad3 L3 Bank0 Output Ready\0"
   /* 73882 */ "Quad3 L3 Bank1 Input Available\0"
   /* 73913 */ "Quad3 L3 Bank1 Output Ready\0"
   /* 73941 */ "Quad3 L3 Bank2 Input Available\0"
   /* 73972 */ "Quad3 L3 Bank2 Output Ready\0"
   /* 74000 */ "Quad3 L3 Bank3 Input Available\0"
   /* 74031 */ "Quad3 L3 Bank3 Output Ready\0"
   /* 74059 */ "Quad3 L3 Bank4 Input Available\0"
   /* 74090 */ "Quad3 L3 Bank4 Output Ready\0"
   /* 74118 */ "Quad3 L3 Bank5 Input Available\0"
   /* 74149 */ "Quad3 L3 Bank5 Output Ready\0"
   /* 74177 */ "Quad3 L3 Bank6 Input Available\0"
   /* 74208 */ "Quad3 L3 Bank6 Output Ready\0"
   /* 74236 */ "Quad3 L3 Bank7 Input Available\0"
   /* 74267 */ "Quad3 L3 Bank7 Output Ready\0"
   /* 74295 */ "RASTERIZER INPUT AVAILABLE SLICE0\0"
   /* 74329 */ "RASTERIZER INPUT AVAILABLE SLICE1\0"
   /* 74363 */ "RASTERIZER INPUT AVAILABLE SLICE2\0"
   /* 74397 */ "RASTERIZER INPUT AVAILABLE SLICE3\0"
   /* 74431 */ "RASTERIZER INPUT AVAILABLE SLICE4\0"
   /* 74465 */ "RASTERIZER INPUT AVAILABLE SLICE5\0"
   /* 74499 */ "RASTERIZER INPUT AVAILABLE SLICE6\0"
   /* 74533 */ "RASTERIZER INPUT AVAILABLE SLICE7\0"
   /* 74567 */ "RASTERIZER OUTPUT READY SLICE0\0"
   /* 74598 */ "RASTERIZER OUTPUT READY SLICE1\0"
   /* 74629 */ "RASTERIZER OUTPUT READY SLICE2\0"
   /* 74660 */ "RASTERIZER OUTPUT READY SLICE3\0"
   /* 74691 */ "RASTERIZER OUTPUT READY SLICE4\0"
   /* 74722 */ "RASTERIZER OUTPUT READY SLICE5\0"
   /* 74753 */ "RASTERIZER OUTPUT READY SLICE6\0"
   /* 74784 */ "RASTERIZER OUTPUT READY SLICE7\0"
   /* 74815 */ "RASTERIZER SAMPLE OUTPUT\0"
   /* 74840 */ "RASTERIZER TRANSACTION OUTPUT SLICE0\0"
   /* 74877 */ "RASTERIZER TRANSACTION OUTPUT SLICE1\0"
   /* 74914 */ "RASTERIZER TRANSACTION OUTPUT SLICE2\0"
   /* 74951 */ "RASTERIZER TRANSACTION OUTPUT SLICE3\0"
   /* 74988 */ "RASTERIZER TRANSACTION OUTPUT SLICE4\0"
   /* 75025 */ "RASTERIZER TRANSACTION OUTPUT SLICE5\0"
   /* 75062 */ "RASTERIZER TRANSACTION OUTPUT SLICE6\0"
   /* 75099 */ "RASTERIZER TRANSACTION OUTPUT SLICE7\0"
   /* 75136 */ "RENDER CACHE ALLOC L3NODE0\0"
   /* 75163 */ "RENDER CACHE ALLOC L3NODE1\0"
   /* 75190 */ "RENDER CACHE ALLOC L3NODE2\0"
   /* 75217 */ "RENDER CACHE ALLOC L3NODE3\0"
   /* 75244 */ "RENDER CACHE ALLOC L3NODE4\0"
   /* 75271 */ "RENDER CACHE ALLOC L3NODE5\0"
   /* 75298 */ "RENDER CACHE ALLOC L3NODE6\0"
   /* 75325 */ "RENDER CACHE ALLOC L3NODE7\0"
   /* 75352 */ "RENDER CACHE HIT L3NODE0\0"
   /* 75377 */ "RENDER CACHE HIT L3NODE1\0"
   /* 75402 */ "RENDER CACHE HIT L3NODE2\0"
   /* 75427 */ "RENDER CACHE HIT L3NODE3\0"
   /* 75452 */ "RENDER CACHE HIT L3NODE4\0"
   /* 75477 */ "RENDER CACHE HIT L3NODE5\0"
   /* 75502 */ "RENDER CACHE HIT L3NODE6\0"
   /* 75527 */ "RENDER CACHE HIT L3NODE7\0"
   /* 75552 */ "RENDER CACHE INPUT AVAILABLE _L3NODE0\0"
   /* 75590 */ "RENDER CACHE INPUT AVAILABLE _L3NODE1\0"
   /* 75628 */ "RENDER CACHE OUTPUT READY _L3NODE0\0"
   /* 75663 */ "RENDER CACHE OUTPUT READY _L3NODE1\0"
   /* 75698 */ "RENDER CACHE READ L3NODE0\0"
   /* 75724 */ "RENDER CACHE READ L3NODE1\0"
   /* 75750 */ "RENDER CACHE READ L3NODE2\0"
   /* 75776 */ "RENDER CACHE READ L3NODE3\0"
   /* 75802 */ "RENDER CACHE READ L3NODE4\0"
   /* 75828 */ "RENDER CACHE READ L3NODE5\0"
   /* 75854 */ "RENDER CACHE READ L3NODE6\0"
   /* 75880 */ "RENDER CACHE READ L3NODE7\0"
   /* 75906 */ "RENDER CACHE WRITE L3NODE0\0"
   /* 75933 */ "RENDER CACHE WRITE L3NODE1\0"
   /* 75960 */ "RENDER CACHE WRITE L3NODE2\0"
   /* 75987 */ "RENDER CACHE WRITE L3NODE3\0"
   /* 76014 */ "RENDER CACHE WRITE L3NODE4\0"
   /* 76041 */ "RENDER CACHE WRITE L3NODE5\0"
   /* 76068 */ "RENDER CACHE WRITE L3NODE6\0"
   /* 76095 */ "RENDER CACHE WRITE L3NODE7\0"
   /* 76122 */ "RENDER_CACHE_INPUT_AVAILABLE _L3NODE0\0"
   /* 76160 */ "RENDER_CACHE_INPUT_AVAILABLE _L3NODE1\0"
   /* 76198 */ "RENDER_CACHE_INPUT_AVAILABLE _L3NODE2\0"
   /* 76236 */ "RENDER_CACHE_INPUT_AVAILABLE _L3NODE3\0"
   /* 76274 */ "RENDER_CACHE_INPUT_AVAILABLE _L3NODE4\0"
   /* 76312 */ "RENDER_CACHE_INPUT_AVAILABLE _L3NODE5\0"
   /* 76350 */ "RENDER_CACHE_INPUT_AVAILABLE _L3NODE6\0"
   /* 76388 */ "RENDER_CACHE_INPUT_AVAILABLE _L3NODE7\0"
   /* 76426 */ "RENDER_CACHE_OUTPUT_READY _L3NODE0\0"
   /* 76461 */ "RENDER_CACHE_OUTPUT_READY _L3NODE1\0"
   /* 76496 */ "RENDER_CACHE_OUTPUT_READY _L3NODE2\0"
   /* 76531 */ "RENDER_CACHE_OUTPUT_READY _L3NODE3\0"
   /* 76566 */ "RENDER_CACHE_OUTPUT_READY _L3NODE4\0"
   /* 76601 */ "RENDER_CACHE_OUTPUT_READY _L3NODE5\0"
   /* 76636 */ "RENDER_CACHE_OUTPUT_READY _L3NODE6\0"
   /* 76671 */ "RENDER_CACHE_OUTPUT_READY _L3NODE7\0"
   /* 76706 */ "RT ANY HIT THREAD RAY DISPATCH XECORE0\0"
   /* 76745 */ "RT ANY HIT THREAD RAY DISPATCH XECORE1\0"
   /* 76784 */ "RT ANY HIT THREAD RAY DISPATCH XECORE10\0"
   /* 76824 */ "RT ANY HIT THREAD RAY DISPATCH XECORE11\0"
   /* 76864 */ "RT ANY HIT THREAD RAY DISPATCH XECORE12\0"
   /* 76904 */ "RT ANY HIT THREAD RAY DISPATCH XECORE13\0"
   /* 76944 */ "RT ANY HIT THREAD RAY DISPATCH XECORE14\0"
   /* 76984 */ "RT ANY HIT THREAD RAY DISPATCH XECORE15\0"
   /* 77024 */ "RT ANY HIT THREAD RAY DISPATCH XECORE16\0"
   /* 77064 */ "RT ANY HIT THREAD RAY DISPATCH XECORE17\0"
   /* 77104 */ "RT ANY HIT THREAD RAY DISPATCH XECORE18\0"
   /* 77144 */ "RT ANY HIT THREAD RAY DISPATCH XECORE19\0"
   /* 77184 */ "RT ANY HIT THREAD RAY DISPATCH XECORE2\0"
   /* 77223 */ "RT ANY HIT THREAD RAY DISPATCH XECORE20\0"
   /* 77263 */ "RT ANY HIT THREAD RAY DISPATCH XECORE21\0"
   /* 77303 */ "RT ANY HIT THREAD RAY DISPATCH XECORE22\0"
   /* 77343 */ "RT ANY HIT THREAD RAY DISPATCH XECORE23\0"
   /* 77383 */ "RT ANY HIT THREAD RAY DISPATCH XECORE24\0"
   /* 77423 */ "RT ANY HIT THREAD RAY DISPATCH XECORE25\0"
   /* 77463 */ "RT ANY HIT THREAD RAY DISPATCH XECORE26\0"
   /* 77503 */ "RT ANY HIT THREAD RAY DISPATCH XECORE27\0"
   /* 77543 */ "RT ANY HIT THREAD RAY DISPATCH XECORE28\0"
   /* 77583 */ "RT ANY HIT THREAD RAY DISPATCH XECORE29\0"
   /* 77623 */ "RT ANY HIT THREAD RAY DISPATCH XECORE3\0"
   /* 77662 */ "RT ANY HIT THREAD RAY DISPATCH XECORE30\0"
   /* 77702 */ "RT ANY HIT THREAD RAY DISPATCH XECORE31\0"
   /* 77742 */ "RT ANY HIT THREAD RAY DISPATCH XECORE4\0"
   /* 77781 */ "RT ANY HIT THREAD RAY DISPATCH XECORE5\0"
   /* 77820 */ "RT ANY HIT THREAD RAY DISPATCH XECORE6\0"
   /* 77859 */ "RT ANY HIT THREAD RAY DISPATCH XECORE7\0"
   /* 77898 */ "RT ANY HIT THREAD RAY DISPATCH XECORE8\0"
   /* 77937 */ "RT ANY HIT THREAD RAY DISPATCH XECORE9\0"
   /* 77976 */ "RT BVH CACHE MISS XECORE0\0"
   /* 78002 */ "RT BVH CACHE MISS XECORE1\0"
   /* 78028 */ "RT BVH CACHE MISS XECORE10\0"
   /* 78055 */ "RT BVH CACHE MISS XECORE11\0"
   /* 78082 */ "RT BVH CACHE MISS XECORE12\0"
   /* 78109 */ "RT BVH CACHE MISS XECORE13\0"
   /* 78136 */ "RT BVH CACHE MISS XECORE14\0"
   /* 78163 */ "RT BVH CACHE MISS XECORE15\0"
   /* 78190 */ "RT BVH CACHE MISS XECORE16\0"
   /* 78217 */ "RT BVH CACHE MISS XECORE17\0"
   /* 78244 */ "RT BVH CACHE MISS XECORE18\0"
   /* 78271 */ "RT BVH CACHE MISS XECORE19\0"
   /* 78298 */ "RT BVH CACHE MISS XECORE2\0"
   /* 78324 */ "RT BVH CACHE MISS XECORE20\0"
   /* 78351 */ "RT BVH CACHE MISS XECORE21\0"
   /* 78378 */ "RT BVH CACHE MISS XECORE22\0"
   /* 78405 */ "RT BVH CACHE MISS XECORE23\0"
   /* 78432 */ "RT BVH CACHE MISS XECORE24\0"
   /* 78459 */ "RT BVH CACHE MISS XECORE25\0"
   /* 78486 */ "RT BVH CACHE MISS XECORE26\0"
   /* 78513 */ "RT BVH CACHE MISS XECORE27\0"
   /* 78540 */ "RT BVH CACHE MISS XECORE28\0"
   /* 78567 */ "RT BVH CACHE MISS XECORE29\0"
   /* 78594 */ "RT BVH CACHE MISS XECORE3\0"
   /* 78620 */ "RT BVH CACHE MISS XECORE30\0"
   /* 78647 */ "RT BVH CACHE MISS XECORE31\0"
   /* 78674 */ "RT BVH CACHE MISS XECORE4\0"
   /* 78700 */ "RT BVH CACHE MISS XECORE5\0"
   /* 78726 */ "RT BVH CACHE MISS XECORE6\0"
   /* 78752 */ "RT BVH CACHE MISS XECORE7\0"
   /* 78778 */ "RT BVH CACHE MISS XECORE8\0"
   /* 78804 */ "RT BVH CACHE MISS XECORE9\0"
   /* 78830 */ "RT CALLABLE THREAD RAY DISPATCH XECORE0\0"
   /* 78870 */ "RT CALLABLE THREAD RAY DISPATCH XECORE1\0"
   /* 78910 */ "RT CALLABLE THREAD RAY DISPATCH XECORE10\0"
   /* 78951 */ "RT CALLABLE THREAD RAY DISPATCH XECORE11\0"
   /* 78992 */ "RT CALLABLE THREAD RAY DISPATCH XECORE12\0"
   /* 79033 */ "RT CALLABLE THREAD RAY DISPATCH XECORE13\0"
   /* 79074 */ "RT CALLABLE THREAD RAY DISPATCH XECORE14\0"
   /* 79115 */ "RT CALLABLE THREAD RAY DISPATCH XECORE15\0"
   /* 79156 */ "RT CALLABLE THREAD RAY DISPATCH XECORE16\0"
   /* 79197 */ "RT CALLABLE THREAD RAY DISPATCH XECORE17\0"
   /* 79238 */ "RT CALLABLE THREAD RAY DISPATCH XECORE18\0"
   /* 79279 */ "RT CALLABLE THREAD RAY DISPATCH XECORE19\0"
   /* 79320 */ "RT CALLABLE THREAD RAY DISPATCH XECORE2\0"
   /* 79360 */ "RT CALLABLE THREAD RAY DISPATCH XECORE20\0"
   /* 79401 */ "RT CALLABLE THREAD RAY DISPATCH XECORE21\0"
   /* 79442 */ "RT CALLABLE THREAD RAY DISPATCH XECORE22\0"
   /* 79483 */ "RT CALLABLE THREAD RAY DISPATCH XECORE23\0"
   /* 79524 */ "RT CALLABLE THREAD RAY DISPATCH XECORE24\0"
   /* 79565 */ "RT CALLABLE THREAD RAY DISPATCH XECORE25\0"
   /* 79606 */ "RT CALLABLE THREAD RAY DISPATCH XECORE26\0"
   /* 79647 */ "RT CALLABLE THREAD RAY DISPATCH XECORE27\0"
   /* 79688 */ "RT CALLABLE THREAD RAY DISPATCH XECORE28\0"
   /* 79729 */ "RT CALLABLE THREAD RAY DISPATCH XECORE29\0"
   /* 79770 */ "RT CALLABLE THREAD RAY DISPATCH XECORE3\0"
   /* 79810 */ "RT CALLABLE THREAD RAY DISPATCH XECORE30\0"
   /* 79851 */ "RT CALLABLE THREAD RAY DISPATCH XECORE31\0"
   /* 79892 */ "RT CALLABLE THREAD RAY DISPATCH XECORE4\0"
   /* 79932 */ "RT CALLABLE THREAD RAY DISPATCH XECORE5\0"
   /* 79972 */ "RT CALLABLE THREAD RAY DISPATCH XECORE6\0"
   /* 80012 */ "RT CALLABLE THREAD RAY DISPATCH XECORE7\0"
   /* 80052 */ "RT CALLABLE THREAD RAY DISPATCH XECORE8\0"
   /* 80092 */ "RT CALLABLE THREAD RAY DISPATCH XECORE9\0"
   /* 80132 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE0\0"
   /* 80175 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE1\0"
   /* 80218 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE10\0"
   /* 80262 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE11\0"
   /* 80306 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE12\0"
   /* 80350 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE13\0"
   /* 80394 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE14\0"
   /* 80438 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE15\0"
   /* 80482 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE16\0"
   /* 80526 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE17\0"
   /* 80570 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE18\0"
   /* 80614 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE19\0"
   /* 80658 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE2\0"
   /* 80701 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE20\0"
   /* 80745 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE21\0"
   /* 80789 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE22\0"
   /* 80833 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE23\0"
   /* 80877 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE24\0"
   /* 80921 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE25\0"
   /* 80965 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE26\0"
   /* 81009 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE27\0"
   /* 81053 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE28\0"
   /* 81097 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE29\0"
   /* 81141 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE3\0"
   /* 81184 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE30\0"
   /* 81228 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE31\0"
   /* 81272 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE4\0"
   /* 81315 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE5\0"
   /* 81358 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE6\0"
   /* 81401 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE7\0"
   /* 81444 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE8\0"
   /* 81487 */ "RT CLOSEST HIT THREAD RAY DISPATCH XECORE9\0"
   /* 81530 */ "RT INPUT AVAILABLE XECORE0\0"
   /* 81557 */ "RT INPUT AVAILABLE XECORE1\0"
   /* 81584 */ "RT INPUT AVAILABLE XECORE10\0"
   /* 81612 */ "RT INPUT AVAILABLE XECORE11\0"
   /* 81640 */ "RT INPUT AVAILABLE XECORE12\0"
   /* 81668 */ "RT INPUT AVAILABLE XECORE13\0"
   /* 81696 */ "RT INPUT AVAILABLE XECORE14\0"
   /* 81724 */ "RT INPUT AVAILABLE XECORE15\0"
   /* 81752 */ "RT INPUT AVAILABLE XECORE16\0"
   /* 81780 */ "RT INPUT AVAILABLE XECORE17\0"
   /* 81808 */ "RT INPUT AVAILABLE XECORE18\0"
   /* 81836 */ "RT INPUT AVAILABLE XECORE19\0"
   /* 81864 */ "RT INPUT AVAILABLE XECORE2\0"
   /* 81891 */ "RT INPUT AVAILABLE XECORE20\0"
   /* 81919 */ "RT INPUT AVAILABLE XECORE21\0"
   /* 81947 */ "RT INPUT AVAILABLE XECORE22\0"
   /* 81975 */ "RT INPUT AVAILABLE XECORE23\0"
   /* 82003 */ "RT INPUT AVAILABLE XECORE24\0"
   /* 82031 */ "RT INPUT AVAILABLE XECORE25\0"
   /* 82059 */ "RT INPUT AVAILABLE XECORE26\0"
   /* 82087 */ "RT INPUT AVAILABLE XECORE27\0"
   /* 82115 */ "RT INPUT AVAILABLE XECORE28\0"
   /* 82143 */ "RT INPUT AVAILABLE XECORE29\0"
   /* 82171 */ "RT INPUT AVAILABLE XECORE3\0"
   /* 82198 */ "RT INPUT AVAILABLE XECORE30\0"
   /* 82226 */ "RT INPUT AVAILABLE XECORE31\0"
   /* 82254 */ "RT INPUT AVAILABLE XECORE4\0"
   /* 82281 */ "RT INPUT AVAILABLE XECORE5\0"
   /* 82308 */ "RT INPUT AVAILABLE XECORE6\0"
   /* 82335 */ "RT INPUT AVAILABLE XECORE7\0"
   /* 82362 */ "RT INPUT AVAILABLE XECORE8\0"
   /* 82389 */ "RT INPUT AVAILABLE XECORE9\0"
   /* 82416 */ "RT INPUT MESSAGE RAY COUNT XECORE0\0"
   /* 82451 */ "RT INPUT MESSAGE RAY COUNT XECORE1\0"
   /* 82486 */ "RT INPUT MESSAGE RAY COUNT XECORE10\0"
   /* 82522 */ "RT INPUT MESSAGE RAY COUNT XECORE11\0"
   /* 82558 */ "RT INPUT MESSAGE RAY COUNT XECORE12\0"
   /* 82594 */ "RT INPUT MESSAGE RAY COUNT XECORE13\0"
   /* 82630 */ "RT INPUT MESSAGE RAY COUNT XECORE14\0"
   /* 82666 */ "RT INPUT MESSAGE RAY COUNT XECORE15\0"
   /* 82702 */ "RT INPUT MESSAGE RAY COUNT XECORE16\0"
   /* 82738 */ "RT INPUT MESSAGE RAY COUNT XECORE17\0"
   /* 82774 */ "RT INPUT MESSAGE RAY COUNT XECORE18\0"
   /* 82810 */ "RT INPUT MESSAGE RAY COUNT XECORE19\0"
   /* 82846 */ "RT INPUT MESSAGE RAY COUNT XECORE2\0"
   /* 82881 */ "RT INPUT MESSAGE RAY COUNT XECORE20\0"
   /* 82917 */ "RT INPUT MESSAGE RAY COUNT XECORE21\0"
   /* 82953 */ "RT INPUT MESSAGE RAY COUNT XECORE22\0"
   /* 82989 */ "RT INPUT MESSAGE RAY COUNT XECORE23\0"
   /* 83025 */ "RT INPUT MESSAGE RAY COUNT XECORE24\0"
   /* 83061 */ "RT INPUT MESSAGE RAY COUNT XECORE25\0"
   /* 83097 */ "RT INPUT MESSAGE RAY COUNT XECORE26\0"
   /* 83133 */ "RT INPUT MESSAGE RAY COUNT XECORE27\0"
   /* 83169 */ "RT INPUT MESSAGE RAY COUNT XECORE28\0"
   /* 83205 */ "RT INPUT MESSAGE RAY COUNT XECORE29\0"
   /* 83241 */ "RT INPUT MESSAGE RAY COUNT XECORE3\0"
   /* 83276 */ "RT INPUT MESSAGE RAY COUNT XECORE30\0"
   /* 83312 */ "RT INPUT MESSAGE RAY COUNT XECORE31\0"
   /* 83348 */ "RT INPUT MESSAGE RAY COUNT XECORE4\0"
   /* 83383 */ "RT INPUT MESSAGE RAY COUNT XECORE5\0"
   /* 83418 */ "RT INPUT MESSAGE RAY COUNT XECORE6\0"
   /* 83453 */ "RT INPUT MESSAGE RAY COUNT XECORE7\0"
   /* 83488 */ "RT INPUT MESSAGE RAY COUNT XECORE8\0"
   /* 83523 */ "RT INPUT MESSAGE RAY COUNT XECORE9\0"
   /* 83558 */ "RT INSTANCE NODE RAY COUNT XECORE0\0"
   /* 83593 */ "RT INSTANCE NODE RAY COUNT XECORE1\0"
   /* 83628 */ "RT INSTANCE NODE RAY COUNT XECORE10\0"
   /* 83664 */ "RT INSTANCE NODE RAY COUNT XECORE11\0"
   /* 83700 */ "RT INSTANCE NODE RAY COUNT XECORE12\0"
   /* 83736 */ "RT INSTANCE NODE RAY COUNT XECORE13\0"
   /* 83772 */ "RT INSTANCE NODE RAY COUNT XECORE14\0"
   /* 83808 */ "RT INSTANCE NODE RAY COUNT XECORE15\0"
   /* 83844 */ "RT INSTANCE NODE RAY COUNT XECORE16\0"
   /* 83880 */ "RT INSTANCE NODE RAY COUNT XECORE17\0"
   /* 83916 */ "RT INSTANCE NODE RAY COUNT XECORE18\0"
   /* 83952 */ "RT INSTANCE NODE RAY COUNT XECORE19\0"
   /* 83988 */ "RT INSTANCE NODE RAY COUNT XECORE2\0"
   /* 84023 */ "RT INSTANCE NODE RAY COUNT XECORE20\0"
   /* 84059 */ "RT INSTANCE NODE RAY COUNT XECORE21\0"
   /* 84095 */ "RT INSTANCE NODE RAY COUNT XECORE22\0"
   /* 84131 */ "RT INSTANCE NODE RAY COUNT XECORE23\0"
   /* 84167 */ "RT INSTANCE NODE RAY COUNT XECORE24\0"
   /* 84203 */ "RT INSTANCE NODE RAY COUNT XECORE25\0"
   /* 84239 */ "RT INSTANCE NODE RAY COUNT XECORE26\0"
   /* 84275 */ "RT INSTANCE NODE RAY COUNT XECORE27\0"
   /* 84311 */ "RT INSTANCE NODE RAY COUNT XECORE28\0"
   /* 84347 */ "RT INSTANCE NODE RAY COUNT XECORE29\0"
   /* 84383 */ "RT INSTANCE NODE RAY COUNT XECORE3\0"
   /* 84418 */ "RT INSTANCE NODE RAY COUNT XECORE30\0"
   /* 84454 */ "RT INSTANCE NODE RAY COUNT XECORE31\0"
   /* 84490 */ "RT INSTANCE NODE RAY COUNT XECORE4\0"
   /* 84525 */ "RT INSTANCE NODE RAY COUNT XECORE5\0"
   /* 84560 */ "RT INSTANCE NODE RAY COUNT XECORE6\0"
   /* 84595 */ "RT INSTANCE NODE RAY COUNT XECORE7\0"
   /* 84630 */ "RT INSTANCE NODE RAY COUNT XECORE8\0"
   /* 84665 */ "RT INSTANCE NODE RAY COUNT XECORE9\0"
   /* 84700 */ "RT INTERNAL NODE RAY COUNT XECORE0\0"
   /* 84735 */ "RT INTERNAL NODE RAY COUNT XECORE1\0"
   /* 84770 */ "RT INTERNAL NODE RAY COUNT XECORE10\0"
   /* 84806 */ "RT INTERNAL NODE RAY COUNT XECORE11\0"
   /* 84842 */ "RT INTERNAL NODE RAY COUNT XECORE12\0"
   /* 84878 */ "RT INTERNAL NODE RAY COUNT XECORE13\0"
   /* 84914 */ "RT INTERNAL NODE RAY COUNT XECORE14\0"
   /* 84950 */ "RT INTERNAL NODE RAY COUNT XECORE15\0"
   /* 84986 */ "RT INTERNAL NODE RAY COUNT XECORE16\0"
   /* 85022 */ "RT INTERNAL NODE RAY COUNT XECORE17\0"
   /* 85058 */ "RT INTERNAL NODE RAY COUNT XECORE18\0"
   /* 85094 */ "RT INTERNAL NODE RAY COUNT XECORE19\0"
   /* 85130 */ "RT INTERNAL NODE RAY COUNT XECORE2\0"
   /* 85165 */ "RT INTERNAL NODE RAY COUNT XECORE20\0"
   /* 85201 */ "RT INTERNAL NODE RAY COUNT XECORE21\0"
   /* 85237 */ "RT INTERNAL NODE RAY COUNT XECORE22\0"
   /* 85273 */ "RT INTERNAL NODE RAY COUNT XECORE23\0"
   /* 85309 */ "RT INTERNAL NODE RAY COUNT XECORE24\0"
   /* 85345 */ "RT INTERNAL NODE RAY COUNT XECORE25\0"
   /* 85381 */ "RT INTERNAL NODE RAY COUNT XECORE26\0"
   /* 85417 */ "RT INTERNAL NODE RAY COUNT XECORE27\0"
   /* 85453 */ "RT INTERNAL NODE RAY COUNT XECORE28\0"
   /* 85489 */ "RT INTERNAL NODE RAY COUNT XECORE29\0"
   /* 85525 */ "RT INTERNAL NODE RAY COUNT XECORE3\0"
   /* 85560 */ "RT INTERNAL NODE RAY COUNT XECORE30\0"
   /* 85596 */ "RT INTERNAL NODE RAY COUNT XECORE31\0"
   /* 85632 */ "RT INTERNAL NODE RAY COUNT XECORE4\0"
   /* 85667 */ "RT INTERNAL NODE RAY COUNT XECORE5\0"
   /* 85702 */ "RT INTERNAL NODE RAY COUNT XECORE6\0"
   /* 85737 */ "RT INTERNAL NODE RAY COUNT XECORE7\0"
   /* 85772 */ "RT INTERNAL NODE RAY COUNT XECORE8\0"
   /* 85807 */ "RT INTERNAL NODE RAY COUNT XECORE9\0"
   /* 85842 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE0\0"
   /* 85886 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE1\0"
   /* 85930 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE10\0"
   /* 85975 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE11\0"
   /* 86020 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE12\0"
   /* 86065 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE13\0"
   /* 86110 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE14\0"
   /* 86155 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE15\0"
   /* 86200 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE16\0"
   /* 86245 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE17\0"
   /* 86290 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE18\0"
   /* 86335 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE19\0"
   /* 86380 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE2\0"
   /* 86424 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE20\0"
   /* 86469 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE21\0"
   /* 86514 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE22\0"
   /* 86559 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE23\0"
   /* 86604 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE24\0"
   /* 86649 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE25\0"
   /* 86694 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE26\0"
   /* 86739 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE27\0"
   /* 86784 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE28\0"
   /* 86829 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE29\0"
   /* 86874 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE3\0"
   /* 86918 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE30\0"
   /* 86963 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE31\0"
   /* 87008 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE4\0"
   /* 87052 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE5\0"
   /* 87096 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE6\0"
   /* 87140 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE7\0"
   /* 87184 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE8\0"
   /* 87228 */ "RT INTERSECTION THREAD RAY DISPATCH XECORE9\0"
   /* 87272 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0\0"
   /* 87319 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1\0"
   /* 87366 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE10\0"
   /* 87414 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE11\0"
   /* 87462 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE12\0"
   /* 87510 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE13\0"
   /* 87558 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE14\0"
   /* 87606 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE15\0"
   /* 87654 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE16\0"
   /* 87702 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE17\0"
   /* 87750 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE18\0"
   /* 87798 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE19\0"
   /* 87846 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2\0"
   /* 87893 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE20\0"
   /* 87941 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE21\0"
   /* 87989 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE22\0"
   /* 88037 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE23\0"
   /* 88085 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE24\0"
   /* 88133 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE25\0"
   /* 88181 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE26\0"
   /* 88229 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE27\0"
   /* 88277 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE28\0"
   /* 88325 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE29\0"
   /* 88373 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3\0"
   /* 88420 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE30\0"
   /* 88468 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE31\0"
   /* 88516 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4\0"
   /* 88563 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5\0"
   /* 88610 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6\0"
   /* 88657 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7\0"
   /* 88704 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE8\0"
   /* 88751 */ "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE9\0"
   /* 88798 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0\0"
   /* 88851 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1\0"
   /* 88904 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE10\0"
   /* 88958 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE11\0"
   /* 89012 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE12\0"
   /* 89066 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE13\0"
   /* 89120 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE14\0"
   /* 89174 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE15\0"
   /* 89228 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE16\0"
   /* 89282 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE17\0"
   /* 89336 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE18\0"
   /* 89390 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE19\0"
   /* 89444 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2\0"
   /* 89497 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE20\0"
   /* 89551 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE21\0"
   /* 89605 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE22\0"
   /* 89659 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE23\0"
   /* 89713 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE24\0"
   /* 89767 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE25\0"
   /* 89821 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE26\0"
   /* 89875 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE27\0"
   /* 89929 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE28\0"
   /* 89983 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE29\0"
   /* 90037 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3\0"
   /* 90090 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE30\0"
   /* 90144 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE31\0"
   /* 90198 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4\0"
   /* 90251 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5\0"
   /* 90304 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6\0"
   /* 90357 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7\0"
   /* 90410 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE8\0"
   /* 90463 */ "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE9\0"
   /* 90516 */ "RT MESSAGE STALL COUNT XECORE0\0"
   /* 90547 */ "RT MESSAGE STALL COUNT XECORE1\0"
   /* 90578 */ "RT MESSAGE STALL COUNT XECORE10\0"
   /* 90610 */ "RT MESSAGE STALL COUNT XECORE11\0"
   /* 90642 */ "RT MESSAGE STALL COUNT XECORE12\0"
   /* 90674 */ "RT MESSAGE STALL COUNT XECORE13\0"
   /* 90706 */ "RT MESSAGE STALL COUNT XECORE14\0"
   /* 90738 */ "RT MESSAGE STALL COUNT XECORE15\0"
   /* 90770 */ "RT MESSAGE STALL COUNT XECORE16\0"
   /* 90802 */ "RT MESSAGE STALL COUNT XECORE17\0"
   /* 90834 */ "RT MESSAGE STALL COUNT XECORE18\0"
   /* 90866 */ "RT MESSAGE STALL COUNT XECORE19\0"
   /* 90898 */ "RT MESSAGE STALL COUNT XECORE2\0"
   /* 90929 */ "RT MESSAGE STALL COUNT XECORE20\0"
   /* 90961 */ "RT MESSAGE STALL COUNT XECORE21\0"
   /* 90993 */ "RT MESSAGE STALL COUNT XECORE22\0"
   /* 91025 */ "RT MESSAGE STALL COUNT XECORE23\0"
   /* 91057 */ "RT MESSAGE STALL COUNT XECORE24\0"
   /* 91089 */ "RT MESSAGE STALL COUNT XECORE25\0"
   /* 91121 */ "RT MESSAGE STALL COUNT XECORE26\0"
   /* 91153 */ "RT MESSAGE STALL COUNT XECORE27\0"
   /* 91185 */ "RT MESSAGE STALL COUNT XECORE28\0"
   /* 91217 */ "RT MESSAGE STALL COUNT XECORE29\0"
   /* 91249 */ "RT MESSAGE STALL COUNT XECORE3\0"
   /* 91280 */ "RT MESSAGE STALL COUNT XECORE30\0"
   /* 91312 */ "RT MESSAGE STALL COUNT XECORE31\0"
   /* 91344 */ "RT MESSAGE STALL COUNT XECORE4\0"
   /* 91375 */ "RT MESSAGE STALL COUNT XECORE5\0"
   /* 91406 */ "RT MESSAGE STALL COUNT XECORE6\0"
   /* 91437 */ "RT MESSAGE STALL COUNT XECORE7\0"
   /* 91468 */ "RT MESSAGE STALL COUNT XECORE8\0"
   /* 91499 */ "RT MESSAGE STALL COUNT XECORE9\0"
   /* 91530 */ "RT MISS THREAD RAY DISPATCH XECORE0\0"
   /* 91566 */ "RT MISS THREAD RAY DISPATCH XECORE1\0"
   /* 91602 */ "RT MISS THREAD RAY DISPATCH XECORE10\0"
   /* 91639 */ "RT MISS THREAD RAY DISPATCH XECORE11\0"
   /* 91676 */ "RT MISS THREAD RAY DISPATCH XECORE12\0"
   /* 91713 */ "RT MISS THREAD RAY DISPATCH XECORE13\0"
   /* 91750 */ "RT MISS THREAD RAY DISPATCH XECORE14\0"
   /* 91787 */ "RT MISS THREAD RAY DISPATCH XECORE15\0"
   /* 91824 */ "RT MISS THREAD RAY DISPATCH XECORE16\0"
   /* 91861 */ "RT MISS THREAD RAY DISPATCH XECORE17\0"
   /* 91898 */ "RT MISS THREAD RAY DISPATCH XECORE18\0"
   /* 91935 */ "RT MISS THREAD RAY DISPATCH XECORE19\0"
   /* 91972 */ "RT MISS THREAD RAY DISPATCH XECORE2\0"
   /* 92008 */ "RT MISS THREAD RAY DISPATCH XECORE20\0"
   /* 92045 */ "RT MISS THREAD RAY DISPATCH XECORE21\0"
   /* 92082 */ "RT MISS THREAD RAY DISPATCH XECORE22\0"
   /* 92119 */ "RT MISS THREAD RAY DISPATCH XECORE23\0"
   /* 92156 */ "RT MISS THREAD RAY DISPATCH XECORE24\0"
   /* 92193 */ "RT MISS THREAD RAY DISPATCH XECORE25\0"
   /* 92230 */ "RT MISS THREAD RAY DISPATCH XECORE26\0"
   /* 92267 */ "RT MISS THREAD RAY DISPATCH XECORE27\0"
   /* 92304 */ "RT MISS THREAD RAY DISPATCH XECORE28\0"
   /* 92341 */ "RT MISS THREAD RAY DISPATCH XECORE29\0"
   /* 92378 */ "RT MISS THREAD RAY DISPATCH XECORE3\0"
   /* 92414 */ "RT MISS THREAD RAY DISPATCH XECORE30\0"
   /* 92451 */ "RT MISS THREAD RAY DISPATCH XECORE31\0"
   /* 92488 */ "RT MISS THREAD RAY DISPATCH XECORE4\0"
   /* 92524 */ "RT MISS THREAD RAY DISPATCH XECORE5\0"
   /* 92560 */ "RT MISS THREAD RAY DISPATCH XECORE6\0"
   /* 92596 */ "RT MISS THREAD RAY DISPATCH XECORE7\0"
   /* 92632 */ "RT MISS THREAD RAY DISPATCH XECORE8\0"
   /* 92668 */ "RT MISS THREAD RAY DISPATCH XECORE9\0"
   /* 92704 */ "RT PROCEDURAL NODE RAY COUNT XECORE0\0"
   /* 92741 */ "RT PROCEDURAL NODE RAY COUNT XECORE1\0"
   /* 92778 */ "RT PROCEDURAL NODE RAY COUNT XECORE10\0"
   /* 92816 */ "RT PROCEDURAL NODE RAY COUNT XECORE11\0"
   /* 92854 */ "RT PROCEDURAL NODE RAY COUNT XECORE12\0"
   /* 92892 */ "RT PROCEDURAL NODE RAY COUNT XECORE13\0"
   /* 92930 */ "RT PROCEDURAL NODE RAY COUNT XECORE14\0"
   /* 92968 */ "RT PROCEDURAL NODE RAY COUNT XECORE15\0"
   /* 93006 */ "RT PROCEDURAL NODE RAY COUNT XECORE16\0"
   /* 93044 */ "RT PROCEDURAL NODE RAY COUNT XECORE17\0"
   /* 93082 */ "RT PROCEDURAL NODE RAY COUNT XECORE18\0"
   /* 93120 */ "RT PROCEDURAL NODE RAY COUNT XECORE19\0"
   /* 93158 */ "RT PROCEDURAL NODE RAY COUNT XECORE2\0"
   /* 93195 */ "RT PROCEDURAL NODE RAY COUNT XECORE20\0"
   /* 93233 */ "RT PROCEDURAL NODE RAY COUNT XECORE21\0"
   /* 93271 */ "RT PROCEDURAL NODE RAY COUNT XECORE22\0"
   /* 93309 */ "RT PROCEDURAL NODE RAY COUNT XECORE23\0"
   /* 93347 */ "RT PROCEDURAL NODE RAY COUNT XECORE24\0"
   /* 93385 */ "RT PROCEDURAL NODE RAY COUNT XECORE25\0"
   /* 93423 */ "RT PROCEDURAL NODE RAY COUNT XECORE26\0"
   /* 93461 */ "RT PROCEDURAL NODE RAY COUNT XECORE27\0"
   /* 93499 */ "RT PROCEDURAL NODE RAY COUNT XECORE28\0"
   /* 93537 */ "RT PROCEDURAL NODE RAY COUNT XECORE29\0"
   /* 93575 */ "RT PROCEDURAL NODE RAY COUNT XECORE3\0"
   /* 93612 */ "RT PROCEDURAL NODE RAY COUNT XECORE30\0"
   /* 93650 */ "RT PROCEDURAL NODE RAY COUNT XECORE31\0"
   /* 93688 */ "RT PROCEDURAL NODE RAY COUNT XECORE4\0"
   /* 93725 */ "RT PROCEDURAL NODE RAY COUNT XECORE5\0"
   /* 93762 */ "RT PROCEDURAL NODE RAY COUNT XECORE6\0"
   /* 93799 */ "RT PROCEDURAL NODE RAY COUNT XECORE7\0"
   /* 93836 */ "RT PROCEDURAL NODE RAY COUNT XECORE8\0"
   /* 93873 */ "RT PROCEDURAL NODE RAY COUNT XECORE9\0"
   /* 93910 */ "RT QUAD LEAF RAY COUNT XECORE0\0"
   /* 93941 */ "RT QUAD LEAF RAY COUNT XECORE1\0"
   /* 93972 */ "RT QUAD LEAF RAY COUNT XECORE10\0"
   /* 94004 */ "RT QUAD LEAF RAY COUNT XECORE11\0"
   /* 94036 */ "RT QUAD LEAF RAY COUNT XECORE12\0"
   /* 94068 */ "RT QUAD LEAF RAY COUNT XECORE13\0"
   /* 94100 */ "RT QUAD LEAF RAY COUNT XECORE14\0"
   /* 94132 */ "RT QUAD LEAF RAY COUNT XECORE15\0"
   /* 94164 */ "RT QUAD LEAF RAY COUNT XECORE16\0"
   /* 94196 */ "RT QUAD LEAF RAY COUNT XECORE17\0"
   /* 94228 */ "RT QUAD LEAF RAY COUNT XECORE18\0"
   /* 94260 */ "RT QUAD LEAF RAY COUNT XECORE19\0"
   /* 94292 */ "RT QUAD LEAF RAY COUNT XECORE2\0"
   /* 94323 */ "RT QUAD LEAF RAY COUNT XECORE20\0"
   /* 94355 */ "RT QUAD LEAF RAY COUNT XECORE21\0"
   /* 94387 */ "RT QUAD LEAF RAY COUNT XECORE22\0"
   /* 94419 */ "RT QUAD LEAF RAY COUNT XECORE23\0"
   /* 94451 */ "RT QUAD LEAF RAY COUNT XECORE24\0"
   /* 94483 */ "RT QUAD LEAF RAY COUNT XECORE25\0"
   /* 94515 */ "RT QUAD LEAF RAY COUNT XECORE26\0"
   /* 94547 */ "RT QUAD LEAF RAY COUNT XECORE27\0"
   /* 94579 */ "RT QUAD LEAF RAY COUNT XECORE28\0"
   /* 94611 */ "RT QUAD LEAF RAY COUNT XECORE29\0"
   /* 94643 */ "RT QUAD LEAF RAY COUNT XECORE3\0"
   /* 94674 */ "RT QUAD LEAF RAY COUNT XECORE30\0"
   /* 94706 */ "RT QUAD LEAF RAY COUNT XECORE31\0"
   /* 94738 */ "RT QUAD LEAF RAY COUNT XECORE4\0"
   /* 94769 */ "RT QUAD LEAF RAY COUNT XECORE5\0"
   /* 94800 */ "RT QUAD LEAF RAY COUNT XECORE6\0"
   /* 94831 */ "RT QUAD LEAF RAY COUNT XECORE7\0"
   /* 94862 */ "RT QUAD LEAF RAY COUNT XECORE8\0"
   /* 94893 */ "RT QUAD LEAF RAY COUNT XECORE9\0"
   /* 94924 */ "RT QUAD TEST RAY COUNT XECORE0\0"
   /* 94955 */ "RT QUAD TEST RAY COUNT XECORE1\0"
   /* 94986 */ "RT QUAD TEST RAY COUNT XECORE10\0"
   /* 95018 */ "RT QUAD TEST RAY COUNT XECORE11\0"
   /* 95050 */ "RT QUAD TEST RAY COUNT XECORE12\0"
   /* 95082 */ "RT QUAD TEST RAY COUNT XECORE13\0"
   /* 95114 */ "RT QUAD TEST RAY COUNT XECORE14\0"
   /* 95146 */ "RT QUAD TEST RAY COUNT XECORE15\0"
   /* 95178 */ "RT QUAD TEST RAY COUNT XECORE16\0"
   /* 95210 */ "RT QUAD TEST RAY COUNT XECORE17\0"
   /* 95242 */ "RT QUAD TEST RAY COUNT XECORE18\0"
   /* 95274 */ "RT QUAD TEST RAY COUNT XECORE19\0"
   /* 95306 */ "RT QUAD TEST RAY COUNT XECORE2\0"
   /* 95337 */ "RT QUAD TEST RAY COUNT XECORE20\0"
   /* 95369 */ "RT QUAD TEST RAY COUNT XECORE21\0"
   /* 95401 */ "RT QUAD TEST RAY COUNT XECORE22\0"
   /* 95433 */ "RT QUAD TEST RAY COUNT XECORE23\0"
   /* 95465 */ "RT QUAD TEST RAY COUNT XECORE24\0"
   /* 95497 */ "RT QUAD TEST RAY COUNT XECORE25\0"
   /* 95529 */ "RT QUAD TEST RAY COUNT XECORE26\0"
   /* 95561 */ "RT QUAD TEST RAY COUNT XECORE27\0"
   /* 95593 */ "RT QUAD TEST RAY COUNT XECORE28\0"
   /* 95625 */ "RT QUAD TEST RAY COUNT XECORE29\0"
   /* 95657 */ "RT QUAD TEST RAY COUNT XECORE3\0"
   /* 95688 */ "RT QUAD TEST RAY COUNT XECORE30\0"
   /* 95720 */ "RT QUAD TEST RAY COUNT XECORE31\0"
   /* 95752 */ "RT QUAD TEST RAY COUNT XECORE4\0"
   /* 95783 */ "RT QUAD TEST RAY COUNT XECORE5\0"
   /* 95814 */ "RT QUAD TEST RAY COUNT XECORE6\0"
   /* 95845 */ "RT QUAD TEST RAY COUNT XECORE7\0"
   /* 95876 */ "RT QUAD TEST RAY COUNT XECORE8\0"
   /* 95907 */ "RT QUAD TEST RAY COUNT XECORE9\0"
   /* 95938 */ "RT REQUEST COLLISION XECORE0\0"
   /* 95967 */ "RT REQUEST COLLISION XECORE1\0"
   /* 95996 */ "RT REQUEST COLLISION XECORE10\0"
   /* 96026 */ "RT REQUEST COLLISION XECORE11\0"
   /* 96056 */ "RT REQUEST COLLISION XECORE12\0"
   /* 96086 */ "RT REQUEST COLLISION XECORE13\0"
   /* 96116 */ "RT REQUEST COLLISION XECORE14\0"
   /* 96146 */ "RT REQUEST COLLISION XECORE15\0"
   /* 96176 */ "RT REQUEST COLLISION XECORE16\0"
   /* 96206 */ "RT REQUEST COLLISION XECORE17\0"
   /* 96236 */ "RT REQUEST COLLISION XECORE18\0"
   /* 96266 */ "RT REQUEST COLLISION XECORE19\0"
   /* 96296 */ "RT REQUEST COLLISION XECORE2\0"
   /* 96325 */ "RT REQUEST COLLISION XECORE20\0"
   /* 96355 */ "RT REQUEST COLLISION XECORE21\0"
   /* 96385 */ "RT REQUEST COLLISION XECORE22\0"
   /* 96415 */ "RT REQUEST COLLISION XECORE23\0"
   /* 96445 */ "RT REQUEST COLLISION XECORE24\0"
   /* 96475 */ "RT REQUEST COLLISION XECORE25\0"
   /* 96505 */ "RT REQUEST COLLISION XECORE26\0"
   /* 96535 */ "RT REQUEST COLLISION XECORE27\0"
   /* 96565 */ "RT REQUEST COLLISION XECORE28\0"
   /* 96595 */ "RT REQUEST COLLISION XECORE29\0"
   /* 96625 */ "RT REQUEST COLLISION XECORE3\0"
   /* 96654 */ "RT REQUEST COLLISION XECORE30\0"
   /* 96684 */ "RT REQUEST COLLISION XECORE31\0"
   /* 96714 */ "RT REQUEST COLLISION XECORE4\0"
   /* 96743 */ "RT REQUEST COLLISION XECORE5\0"
   /* 96772 */ "RT REQUEST COLLISION XECORE6\0"
   /* 96801 */ "RT REQUEST COLLISION XECORE7\0"
   /* 96830 */ "RT REQUEST COLLISION XECORE8\0"
   /* 96859 */ "RT REQUEST COLLISION XECORE9\0"
   /* 96888 */ "RT TRANSFORM RAY COUNT XECORE0\0"
   /* 96919 */ "RT TRANSFORM RAY COUNT XECORE1\0"
   /* 96950 */ "RT TRANSFORM RAY COUNT XECORE10\0"
   /* 96982 */ "RT TRANSFORM RAY COUNT XECORE11\0"
   /* 97014 */ "RT TRANSFORM RAY COUNT XECORE12\0"
   /* 97046 */ "RT TRANSFORM RAY COUNT XECORE13\0"
   /* 97078 */ "RT TRANSFORM RAY COUNT XECORE14\0"
   /* 97110 */ "RT TRANSFORM RAY COUNT XECORE15\0"
   /* 97142 */ "RT TRANSFORM RAY COUNT XECORE16\0"
   /* 97174 */ "RT TRANSFORM RAY COUNT XECORE17\0"
   /* 97206 */ "RT TRANSFORM RAY COUNT XECORE18\0"
   /* 97238 */ "RT TRANSFORM RAY COUNT XECORE19\0"
   /* 97270 */ "RT TRANSFORM RAY COUNT XECORE2\0"
   /* 97301 */ "RT TRANSFORM RAY COUNT XECORE20\0"
   /* 97333 */ "RT TRANSFORM RAY COUNT XECORE21\0"
   /* 97365 */ "RT TRANSFORM RAY COUNT XECORE22\0"
   /* 97397 */ "RT TRANSFORM RAY COUNT XECORE23\0"
   /* 97429 */ "RT TRANSFORM RAY COUNT XECORE24\0"
   /* 97461 */ "RT TRANSFORM RAY COUNT XECORE25\0"
   /* 97493 */ "RT TRANSFORM RAY COUNT XECORE26\0"
   /* 97525 */ "RT TRANSFORM RAY COUNT XECORE27\0"
   /* 97557 */ "RT TRANSFORM RAY COUNT XECORE28\0"
   /* 97589 */ "RT TRANSFORM RAY COUNT XECORE29\0"
   /* 97621 */ "RT TRANSFORM RAY COUNT XECORE3\0"
   /* 97652 */ "RT TRANSFORM RAY COUNT XECORE30\0"
   /* 97684 */ "RT TRANSFORM RAY COUNT XECORE31\0"
   /* 97716 */ "RT TRANSFORM RAY COUNT XECORE4\0"
   /* 97747 */ "RT TRANSFORM RAY COUNT XECORE5\0"
   /* 97778 */ "RT TRANSFORM RAY COUNT XECORE6\0"
   /* 97809 */ "RT TRANSFORM RAY COUNT XECORE7\0"
   /* 97840 */ "RT TRANSFORM RAY COUNT XECORE8\0"
   /* 97871 */ "RT TRANSFORM RAY COUNT XECORE9\0"
   /* 97902 */ "RT TRAVERSAL INPUT RAY COUNT XECORE0\0"
   /* 97939 */ "RT TRAVERSAL INPUT RAY COUNT XECORE1\0"
   /* 97976 */ "RT TRAVERSAL INPUT RAY COUNT XECORE10\0"
   /* 98014 */ "RT TRAVERSAL INPUT RAY COUNT XECORE11\0"
   /* 98052 */ "RT TRAVERSAL INPUT RAY COUNT XECORE12\0"
   /* 98090 */ "RT TRAVERSAL INPUT RAY COUNT XECORE13\0"
   /* 98128 */ "RT TRAVERSAL INPUT RAY COUNT XECORE14\0"
   /* 98166 */ "RT TRAVERSAL INPUT RAY COUNT XECORE15\0"
   /* 98204 */ "RT TRAVERSAL INPUT RAY COUNT XECORE16\0"
   /* 98242 */ "RT TRAVERSAL INPUT RAY COUNT XECORE17\0"
   /* 98280 */ "RT TRAVERSAL INPUT RAY COUNT XECORE18\0"
   /* 98318 */ "RT TRAVERSAL INPUT RAY COUNT XECORE19\0"
   /* 98356 */ "RT TRAVERSAL INPUT RAY COUNT XECORE2\0"
   /* 98393 */ "RT TRAVERSAL INPUT RAY COUNT XECORE20\0"
   /* 98431 */ "RT TRAVERSAL INPUT RAY COUNT XECORE21\0"
   /* 98469 */ "RT TRAVERSAL INPUT RAY COUNT XECORE22\0"
   /* 98507 */ "RT TRAVERSAL INPUT RAY COUNT XECORE23\0"
   /* 98545 */ "RT TRAVERSAL INPUT RAY COUNT XECORE24\0"
   /* 98583 */ "RT TRAVERSAL INPUT RAY COUNT XECORE25\0"
   /* 98621 */ "RT TRAVERSAL INPUT RAY COUNT XECORE26\0"
   /* 98659 */ "RT TRAVERSAL INPUT RAY COUNT XECORE27\0"
   /* 98697 */ "RT TRAVERSAL INPUT RAY COUNT XECORE28\0"
   /* 98735 */ "RT TRAVERSAL INPUT RAY COUNT XECORE29\0"
   /* 98773 */ "RT TRAVERSAL INPUT RAY COUNT XECORE3\0"
   /* 98810 */ "RT TRAVERSAL INPUT RAY COUNT XECORE30\0"
   /* 98848 */ "RT TRAVERSAL INPUT RAY COUNT XECORE31\0"
   /* 98886 */ "RT TRAVERSAL INPUT RAY COUNT XECORE4\0"
   /* 98923 */ "RT TRAVERSAL INPUT RAY COUNT XECORE5\0"
   /* 98960 */ "RT TRAVERSAL INPUT RAY COUNT XECORE6\0"
   /* 98997 */ "RT TRAVERSAL INPUT RAY COUNT XECORE7\0"
   /* 99034 */ "RT TRAVERSAL INPUT RAY COUNT XECORE8\0"
   /* 99071 */ "RT TRAVERSAL INPUT RAY COUNT XECORE9\0"
   /* 99108 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE0\0"
   /* 99146 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE1\0"
   /* 99184 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE10\0"
   /* 99223 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE11\0"
   /* 99262 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE12\0"
   /* 99301 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE13\0"
   /* 99340 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE14\0"
   /* 99379 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE15\0"
   /* 99418 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE16\0"
   /* 99457 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE17\0"
   /* 99496 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE18\0"
   /* 99535 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE19\0"
   /* 99574 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE2\0"
   /* 99612 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE20\0"
   /* 99651 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE21\0"
   /* 99690 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE22\0"
   /* 99729 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE23\0"
   /* 99768 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE24\0"
   /* 99807 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE25\0"
   /* 99846 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE26\0"
   /* 99885 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE27\0"
   /* 99924 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE28\0"
   /* 99963 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE29\0"
   /* 100002 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE3\0"
   /* 100040 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE30\0"
   /* 100079 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE31\0"
   /* 100118 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE4\0"
   /* 100156 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE5\0"
   /* 100194 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE6\0"
   /* 100232 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE7\0"
   /* 100270 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE8\0"
   /* 100308 */ "RT TRAVERSAL OUTPUT RAY COUNT XECORE9\0"
   /* 100346 */ "RT TRAVERSAL STEP RAY COUNT XECORE0\0"
   /* 100382 */ "RT TRAVERSAL STEP RAY COUNT XECORE1\0"
   /* 100418 */ "RT TRAVERSAL STEP RAY COUNT XECORE10\0"
   /* 100455 */ "RT TRAVERSAL STEP RAY COUNT XECORE11\0"
   /* 100492 */ "RT TRAVERSAL STEP RAY COUNT XECORE12\0"
   /* 100529 */ "RT TRAVERSAL STEP RAY COUNT XECORE13\0"
   /* 100566 */ "RT TRAVERSAL STEP RAY COUNT XECORE14\0"
   /* 100603 */ "RT TRAVERSAL STEP RAY COUNT XECORE15\0"
   /* 100640 */ "RT TRAVERSAL STEP RAY COUNT XECORE16\0"
   /* 100677 */ "RT TRAVERSAL STEP RAY COUNT XECORE17\0"
   /* 100714 */ "RT TRAVERSAL STEP RAY COUNT XECORE18\0"
   /* 100751 */ "RT TRAVERSAL STEP RAY COUNT XECORE19\0"
   /* 100788 */ "RT TRAVERSAL STEP RAY COUNT XECORE2\0"
   /* 100824 */ "RT TRAVERSAL STEP RAY COUNT XECORE20\0"
   /* 100861 */ "RT TRAVERSAL STEP RAY COUNT XECORE21\0"
   /* 100898 */ "RT TRAVERSAL STEP RAY COUNT XECORE22\0"
   /* 100935 */ "RT TRAVERSAL STEP RAY COUNT XECORE23\0"
   /* 100972 */ "RT TRAVERSAL STEP RAY COUNT XECORE24\0"
   /* 101009 */ "RT TRAVERSAL STEP RAY COUNT XECORE25\0"
   /* 101046 */ "RT TRAVERSAL STEP RAY COUNT XECORE26\0"
   /* 101083 */ "RT TRAVERSAL STEP RAY COUNT XECORE27\0"
   /* 101120 */ "RT TRAVERSAL STEP RAY COUNT XECORE28\0"
   /* 101157 */ "RT TRAVERSAL STEP RAY COUNT XECORE29\0"
   /* 101194 */ "RT TRAVERSAL STEP RAY COUNT XECORE3\0"
   /* 101230 */ "RT TRAVERSAL STEP RAY COUNT XECORE30\0"
   /* 101267 */ "RT TRAVERSAL STEP RAY COUNT XECORE31\0"
   /* 101304 */ "RT TRAVERSAL STEP RAY COUNT XECORE4\0"
   /* 101340 */ "RT TRAVERSAL STEP RAY COUNT XECORE5\0"
   /* 101376 */ "RT TRAVERSAL STEP RAY COUNT XECORE6\0"
   /* 101412 */ "RT TRAVERSAL STEP RAY COUNT XECORE7\0"
   /* 101448 */ "RT TRAVERSAL STEP RAY COUNT XECORE8\0"
   /* 101484 */ "RT TRAVERSAL STEP RAY COUNT XECORE9\0"
   /* 101520 */ "Rasterized Pixels\0"
   /* 101538 */ "Render Ring Busy\0"
   /* 101555 */ "Render and any compute engines are simultaneously busy\0"
   /* 101610 */ "Render and compute engines are simultaneously busy\0"
   /* 101661 */ "SAMPLER 2X2 READ\0"
   /* 101678 */ "SAMPLER BUSY XECORE0\0"
   /* 101699 */ "SAMPLER BUSY XECORE1\0"
   /* 101720 */ "SAMPLER BUSY XECORE10\0"
   /* 101742 */ "SAMPLER BUSY XECORE11\0"
   /* 101764 */ "SAMPLER BUSY XECORE12\0"
   /* 101786 */ "SAMPLER BUSY XECORE13\0"
   /* 101808 */ "SAMPLER BUSY XECORE14\0"
   /* 101830 */ "SAMPLER BUSY XECORE15\0"
   /* 101852 */ "SAMPLER BUSY XECORE16\0"
   /* 101874 */ "SAMPLER BUSY XECORE17\0"
   /* 101896 */ "SAMPLER BUSY XECORE18\0"
   /* 101918 */ "SAMPLER BUSY XECORE19\0"
   /* 101940 */ "SAMPLER BUSY XECORE2\0"
   /* 101961 */ "SAMPLER BUSY XECORE20\0"
   /* 101983 */ "SAMPLER BUSY XECORE21\0"
   /* 102005 */ "SAMPLER BUSY XECORE22\0"
   /* 102027 */ "SAMPLER BUSY XECORE23\0"
   /* 102049 */ "SAMPLER BUSY XECORE24\0"
   /* 102071 */ "SAMPLER BUSY XECORE25\0"
   /* 102093 */ "SAMPLER BUSY XECORE26\0"
   /* 102115 */ "SAMPLER BUSY XECORE27\0"
   /* 102137 */ "SAMPLER BUSY XECORE28\0"
   /* 102159 */ "SAMPLER BUSY XECORE29\0"
   /* 102181 */ "SAMPLER BUSY XECORE3\0"
   /* 102202 */ "SAMPLER BUSY XECORE30\0"
   /* 102224 */ "SAMPLER BUSY XECORE31\0"
   /* 102246 */ "SAMPLER BUSY XECORE4\0"
   /* 102267 */ "SAMPLER BUSY XECORE5\0"
   /* 102288 */ "SAMPLER BUSY XECORE6\0"
   /* 102309 */ "SAMPLER BUSY XECORE7\0"
   /* 102330 */ "SAMPLER BUSY XECORE8\0"
   /* 102351 */ "SAMPLER BUSY XECORE9\0"
   /* 102372 */ "SAMPLER INPUT AVAILABLE XECORE0\0"
   /* 102404 */ "SAMPLER INPUT AVAILABLE XECORE1\0"
   /* 102436 */ "SAMPLER INPUT AVAILABLE XECORE10\0"
   /* 102469 */ "SAMPLER INPUT AVAILABLE XECORE11\0"
   /* 102502 */ "SAMPLER INPUT AVAILABLE XECORE12\0"
   /* 102535 */ "SAMPLER INPUT AVAILABLE XECORE13\0"
   /* 102568 */ "SAMPLER INPUT AVAILABLE XECORE14\0"
   /* 102601 */ "SAMPLER INPUT AVAILABLE XECORE15\0"
   /* 102634 */ "SAMPLER INPUT AVAILABLE XECORE16\0"
   /* 102667 */ "SAMPLER INPUT AVAILABLE XECORE17\0"
   /* 102700 */ "SAMPLER INPUT AVAILABLE XECORE18\0"
   /* 102733 */ "SAMPLER INPUT AVAILABLE XECORE19\0"
   /* 102766 */ "SAMPLER INPUT AVAILABLE XECORE2\0"
   /* 102798 */ "SAMPLER INPUT AVAILABLE XECORE20\0"
   /* 102831 */ "SAMPLER INPUT AVAILABLE XECORE21\0"
   /* 102864 */ "SAMPLER INPUT AVAILABLE XECORE22\0"
   /* 102897 */ "SAMPLER INPUT AVAILABLE XECORE23\0"
   /* 102930 */ "SAMPLER INPUT AVAILABLE XECORE24\0"
   /* 102963 */ "SAMPLER INPUT AVAILABLE XECORE25\0"
   /* 102996 */ "SAMPLER INPUT AVAILABLE XECORE26\0"
   /* 103029 */ "SAMPLER INPUT AVAILABLE XECORE27\0"
   /* 103062 */ "SAMPLER INPUT AVAILABLE XECORE28\0"
   /* 103095 */ "SAMPLER INPUT AVAILABLE XECORE29\0"
   /* 103128 */ "SAMPLER INPUT AVAILABLE XECORE3\0"
   /* 103160 */ "SAMPLER INPUT AVAILABLE XECORE30\0"
   /* 103193 */ "SAMPLER INPUT AVAILABLE XECORE31\0"
   /* 103226 */ "SAMPLER INPUT AVAILABLE XECORE4\0"
   /* 103258 */ "SAMPLER INPUT AVAILABLE XECORE5\0"
   /* 103290 */ "SAMPLER INPUT AVAILABLE XECORE6\0"
   /* 103322 */ "SAMPLER INPUT AVAILABLE XECORE7\0"
   /* 103354 */ "SAMPLER INPUT AVAILABLE XECORE8\0"
   /* 103386 */ "SAMPLER INPUT AVAILABLE XECORE9\0"
   /* 103418 */ "SAMPLER L3 HIT L3BANK0\0"
   /* 103441 */ "SAMPLER L3 HIT L3BANK1\0"
   /* 103464 */ "SAMPLER L3 HIT L3BANK10\0"
   /* 103488 */ "SAMPLER L3 HIT L3BANK11\0"
   /* 103512 */ "SAMPLER L3 HIT L3BANK12\0"
   /* 103536 */ "SAMPLER L3 HIT L3BANK13\0"
   /* 103560 */ "SAMPLER L3 HIT L3BANK14\0"
   /* 103584 */ "SAMPLER L3 HIT L3BANK15\0"
   /* 103608 */ "SAMPLER L3 HIT L3BANK16\0"
   /* 103632 */ "SAMPLER L3 HIT L3BANK17\0"
   /* 103656 */ "SAMPLER L3 HIT L3BANK18\0"
   /* 103680 */ "SAMPLER L3 HIT L3BANK19\0"
   /* 103704 */ "SAMPLER L3 HIT L3BANK2\0"
   /* 103727 */ "SAMPLER L3 HIT L3BANK20\0"
   /* 103751 */ "SAMPLER L3 HIT L3BANK21\0"
   /* 103775 */ "SAMPLER L3 HIT L3BANK22\0"
   /* 103799 */ "SAMPLER L3 HIT L3BANK23\0"
   /* 103823 */ "SAMPLER L3 HIT L3BANK24\0"
   /* 103847 */ "SAMPLER L3 HIT L3BANK25\0"
   /* 103871 */ "SAMPLER L3 HIT L3BANK26\0"
   /* 103895 */ "SAMPLER L3 HIT L3BANK27\0"
   /* 103919 */ "SAMPLER L3 HIT L3BANK28\0"
   /* 103943 */ "SAMPLER L3 HIT L3BANK29\0"
   /* 103967 */ "SAMPLER L3 HIT L3BANK3\0"
   /* 103990 */ "SAMPLER L3 HIT L3BANK30\0"
   /* 104014 */ "SAMPLER L3 HIT L3BANK31\0"
   /* 104038 */ "SAMPLER L3 HIT L3BANK4\0"
   /* 104061 */ "SAMPLER L3 HIT L3BANK5\0"
   /* 104084 */ "SAMPLER L3 HIT L3BANK6\0"
   /* 104107 */ "SAMPLER L3 HIT L3BANK7\0"
   /* 104130 */ "SAMPLER L3 HIT L3BANK8\0"
   /* 104153 */ "SAMPLER L3 HIT L3BANK9\0"
   /* 104176 */ "SAMPLER L3 READ\0"
   /* 104192 */ "SAMPLER L3 READ L3BANK0\0"
   /* 104216 */ "SAMPLER L3 READ L3BANK1\0"
   /* 104240 */ "SAMPLER L3 READ L3BANK10\0"
   /* 104265 */ "SAMPLER L3 READ L3BANK11\0"
   /* 104290 */ "SAMPLER L3 READ L3BANK12\0"
   /* 104315 */ "SAMPLER L3 READ L3BANK13\0"
   /* 104340 */ "SAMPLER L3 READ L3BANK14\0"
   /* 104365 */ "SAMPLER L3 READ L3BANK15\0"
   /* 104390 */ "SAMPLER L3 READ L3BANK16\0"
   /* 104415 */ "SAMPLER L3 READ L3BANK17\0"
   /* 104440 */ "SAMPLER L3 READ L3BANK18\0"
   /* 104465 */ "SAMPLER L3 READ L3BANK19\0"
   /* 104490 */ "SAMPLER L3 READ L3BANK2\0"
   /* 104514 */ "SAMPLER L3 READ L3BANK20\0"
   /* 104539 */ "SAMPLER L3 READ L3BANK21\0"
   /* 104564 */ "SAMPLER L3 READ L3BANK22\0"
   /* 104589 */ "SAMPLER L3 READ L3BANK23\0"
   /* 104614 */ "SAMPLER L3 READ L3BANK24\0"
   /* 104639 */ "SAMPLER L3 READ L3BANK25\0"
   /* 104664 */ "SAMPLER L3 READ L3BANK26\0"
   /* 104689 */ "SAMPLER L3 READ L3BANK27\0"
   /* 104714 */ "SAMPLER L3 READ L3BANK28\0"
   /* 104739 */ "SAMPLER L3 READ L3BANK29\0"
   /* 104764 */ "SAMPLER L3 READ L3BANK3\0"
   /* 104788 */ "SAMPLER L3 READ L3BANK30\0"
   /* 104813 */ "SAMPLER L3 READ L3BANK31\0"
   /* 104838 */ "SAMPLER L3 READ L3BANK4\0"
   /* 104862 */ "SAMPLER L3 READ L3BANK5\0"
   /* 104886 */ "SAMPLER L3 READ L3BANK6\0"
   /* 104910 */ "SAMPLER L3 READ L3BANK7\0"
   /* 104934 */ "SAMPLER L3 READ L3BANK8\0"
   /* 104958 */ "SAMPLER L3 READ L3BANK9\0"
   /* 104982 */ "SAMPLER MEMORY LATENCY STALL XECORE0\0"
   /* 105019 */ "SAMPLER MEMORY LATENCY STALL XECORE1\0"
   /* 105056 */ "SAMPLER MEMORY LATENCY STALL XECORE10\0"
   /* 105094 */ "SAMPLER MEMORY LATENCY STALL XECORE11\0"
   /* 105132 */ "SAMPLER MEMORY LATENCY STALL XECORE12\0"
   /* 105170 */ "SAMPLER MEMORY LATENCY STALL XECORE13\0"
   /* 105208 */ "SAMPLER MEMORY LATENCY STALL XECORE14\0"
   /* 105246 */ "SAMPLER MEMORY LATENCY STALL XECORE15\0"
   /* 105284 */ "SAMPLER MEMORY LATENCY STALL XECORE16\0"
   /* 105322 */ "SAMPLER MEMORY LATENCY STALL XECORE17\0"
   /* 105360 */ "SAMPLER MEMORY LATENCY STALL XECORE18\0"
   /* 105398 */ "SAMPLER MEMORY LATENCY STALL XECORE19\0"
   /* 105436 */ "SAMPLER MEMORY LATENCY STALL XECORE2\0"
   /* 105473 */ "SAMPLER MEMORY LATENCY STALL XECORE20\0"
   /* 105511 */ "SAMPLER MEMORY LATENCY STALL XECORE21\0"
   /* 105549 */ "SAMPLER MEMORY LATENCY STALL XECORE22\0"
   /* 105587 */ "SAMPLER MEMORY LATENCY STALL XECORE23\0"
   /* 105625 */ "SAMPLER MEMORY LATENCY STALL XECORE24\0"
   /* 105663 */ "SAMPLER MEMORY LATENCY STALL XECORE25\0"
   /* 105701 */ "SAMPLER MEMORY LATENCY STALL XECORE26\0"
   /* 105739 */ "SAMPLER MEMORY LATENCY STALL XECORE27\0"
   /* 105777 */ "SAMPLER MEMORY LATENCY STALL XECORE28\0"
   /* 105815 */ "SAMPLER MEMORY LATENCY STALL XECORE29\0"
   /* 105853 */ "SAMPLER MEMORY LATENCY STALL XECORE3\0"
   /* 105890 */ "SAMPLER MEMORY LATENCY STALL XECORE30\0"
   /* 105928 */ "SAMPLER MEMORY LATENCY STALL XECORE31\0"
   /* 105966 */ "SAMPLER MEMORY LATENCY STALL XECORE4\0"
   /* 106003 */ "SAMPLER MEMORY LATENCY STALL XECORE5\0"
   /* 106040 */ "SAMPLER MEMORY LATENCY STALL XECORE6\0"
   /* 106077 */ "SAMPLER MEMORY LATENCY STALL XECORE7\0"
   /* 106114 */ "SAMPLER MEMORY LATENCY STALL XECORE8\0"
   /* 106151 */ "SAMPLER MEMORY LATENCY STALL XECORE9\0"
   /* 106188 */ "SAMPLER OUTPUT READY XECORE0\0"
   /* 106217 */ "SAMPLER OUTPUT READY XECORE1\0"
   /* 106246 */ "SAMPLER OUTPUT READY XECORE10\0"
   /* 106276 */ "SAMPLER OUTPUT READY XECORE11\0"
   /* 106306 */ "SAMPLER OUTPUT READY XECORE12\0"
   /* 106336 */ "SAMPLER OUTPUT READY XECORE13\0"
   /* 106366 */ "SAMPLER OUTPUT READY XECORE14\0"
   /* 106396 */ "SAMPLER OUTPUT READY XECORE15\0"
   /* 106426 */ "SAMPLER OUTPUT READY XECORE16\0"
   /* 106456 */ "SAMPLER OUTPUT READY XECORE17\0"
   /* 106486 */ "SAMPLER OUTPUT READY XECORE18\0"
   /* 106516 */ "SAMPLER OUTPUT READY XECORE19\0"
   /* 106546 */ "SAMPLER OUTPUT READY XECORE2\0"
   /* 106575 */ "SAMPLER OUTPUT READY XECORE20\0"
   /* 106605 */ "SAMPLER OUTPUT READY XECORE21\0"
   /* 106635 */ "SAMPLER OUTPUT READY XECORE22\0"
   /* 106665 */ "SAMPLER OUTPUT READY XECORE23\0"
   /* 106695 */ "SAMPLER OUTPUT READY XECORE24\0"
   /* 106725 */ "SAMPLER OUTPUT READY XECORE25\0"
   /* 106755 */ "SAMPLER OUTPUT READY XECORE26\0"
   /* 106785 */ "SAMPLER OUTPUT READY XECORE27\0"
   /* 106815 */ "SAMPLER OUTPUT READY XECORE28\0"
   /* 106845 */ "SAMPLER OUTPUT READY XECORE29\0"
   /* 106875 */ "SAMPLER OUTPUT READY XECORE3\0"
   /* 106904 */ "SAMPLER OUTPUT READY XECORE30\0"
   /* 106934 */ "SAMPLER OUTPUT READY XECORE31\0"
   /* 106964 */ "SAMPLER OUTPUT READY XECORE4\0"
   /* 106993 */ "SAMPLER OUTPUT READY XECORE5\0"
   /* 107022 */ "SAMPLER OUTPUT READY XECORE6\0"
   /* 107051 */ "SAMPLER OUTPUT READY XECORE7\0"
   /* 107080 */ "SAMPLER OUTPUT READY XECORE8\0"
   /* 107109 */ "SAMPLER OUTPUT READY XECORE9\0"
   /* 107138 */ "SAMPLER TEXTURE CACHE ACCESS XECORE0\0"
   /* 107175 */ "SAMPLER TEXTURE CACHE ACCESS XECORE1\0"
   /* 107212 */ "SAMPLER TEXTURE CACHE ACCESS XECORE10\0"
   /* 107250 */ "SAMPLER TEXTURE CACHE ACCESS XECORE11\0"
   /* 107288 */ "SAMPLER TEXTURE CACHE ACCESS XECORE12\0"
   /* 107326 */ "SAMPLER TEXTURE CACHE ACCESS XECORE13\0"
   /* 107364 */ "SAMPLER TEXTURE CACHE ACCESS XECORE14\0"
   /* 107402 */ "SAMPLER TEXTURE CACHE ACCESS XECORE15\0"
   /* 107440 */ "SAMPLER TEXTURE CACHE ACCESS XECORE16\0"
   /* 107478 */ "SAMPLER TEXTURE CACHE ACCESS XECORE17\0"
   /* 107516 */ "SAMPLER TEXTURE CACHE ACCESS XECORE18\0"
   /* 107554 */ "SAMPLER TEXTURE CACHE ACCESS XECORE19\0"
   /* 107592 */ "SAMPLER TEXTURE CACHE ACCESS XECORE2\0"
   /* 107629 */ "SAMPLER TEXTURE CACHE ACCESS XECORE20\0"
   /* 107667 */ "SAMPLER TEXTURE CACHE ACCESS XECORE21\0"
   /* 107705 */ "SAMPLER TEXTURE CACHE ACCESS XECORE22\0"
   /* 107743 */ "SAMPLER TEXTURE CACHE ACCESS XECORE23\0"
   /* 107781 */ "SAMPLER TEXTURE CACHE ACCESS XECORE24\0"
   /* 107819 */ "SAMPLER TEXTURE CACHE ACCESS XECORE25\0"
   /* 107857 */ "SAMPLER TEXTURE CACHE ACCESS XECORE26\0"
   /* 107895 */ "SAMPLER TEXTURE CACHE ACCESS XECORE27\0"
   /* 107933 */ "SAMPLER TEXTURE CACHE ACCESS XECORE28\0"
   /* 107971 */ "SAMPLER TEXTURE CACHE ACCESS XECORE29\0"
   /* 108009 */ "SAMPLER TEXTURE CACHE ACCESS XECORE3\0"
   /* 108046 */ "SAMPLER TEXTURE CACHE ACCESS XECORE30\0"
   /* 108084 */ "SAMPLER TEXTURE CACHE ACCESS XECORE31\0"
   /* 108122 */ "SAMPLER TEXTURE CACHE ACCESS XECORE4\0"
   /* 108159 */ "SAMPLER TEXTURE CACHE ACCESS XECORE5\0"
   /* 108196 */ "SAMPLER TEXTURE CACHE ACCESS XECORE6\0"
   /* 108233 */ "SAMPLER TEXTURE CACHE ACCESS XECORE7\0"
   /* 108270 */ "SAMPLER TEXTURE CACHE ACCESS XECORE8\0"
   /* 108307 */ "SAMPLER TEXTURE CACHE ACCESS XECORE9\0"
   /* 108344 */ "SAMPLER TEXTURE CACHE MISS XECORE0\0"
   /* 108379 */ "SAMPLER TEXTURE CACHE MISS XECORE1\0"
   /* 108414 */ "SAMPLER TEXTURE CACHE MISS XECORE10\0"
   /* 108450 */ "SAMPLER TEXTURE CACHE MISS XECORE11\0"
   /* 108486 */ "SAMPLER TEXTURE CACHE MISS XECORE12\0"
   /* 108522 */ "SAMPLER TEXTURE CACHE MISS XECORE13\0"
   /* 108558 */ "SAMPLER TEXTURE CACHE MISS XECORE14\0"
   /* 108594 */ "SAMPLER TEXTURE CACHE MISS XECORE15\0"
   /* 108630 */ "SAMPLER TEXTURE CACHE MISS XECORE16\0"
   /* 108666 */ "SAMPLER TEXTURE CACHE MISS XECORE17\0"
   /* 108702 */ "SAMPLER TEXTURE CACHE MISS XECORE18\0"
   /* 108738 */ "SAMPLER TEXTURE CACHE MISS XECORE19\0"
   /* 108774 */ "SAMPLER TEXTURE CACHE MISS XECORE2\0"
   /* 108809 */ "SAMPLER TEXTURE CACHE MISS XECORE20\0"
   /* 108845 */ "SAMPLER TEXTURE CACHE MISS XECORE21\0"
   /* 108881 */ "SAMPLER TEXTURE CACHE MISS XECORE22\0"
   /* 108917 */ "SAMPLER TEXTURE CACHE MISS XECORE23\0"
   /* 108953 */ "SAMPLER TEXTURE CACHE MISS XECORE24\0"
   /* 108989 */ "SAMPLER TEXTURE CACHE MISS XECORE25\0"
   /* 109025 */ "SAMPLER TEXTURE CACHE MISS XECORE26\0"
   /* 109061 */ "SAMPLER TEXTURE CACHE MISS XECORE27\0"
   /* 109097 */ "SAMPLER TEXTURE CACHE MISS XECORE28\0"
   /* 109133 */ "SAMPLER TEXTURE CACHE MISS XECORE29\0"
   /* 109169 */ "SAMPLER TEXTURE CACHE MISS XECORE3\0"
   /* 109204 */ "SAMPLER TEXTURE CACHE MISS XECORE30\0"
   /* 109240 */ "SAMPLER TEXTURE CACHE MISS XECORE31\0"
   /* 109276 */ "SAMPLER TEXTURE CACHE MISS XECORE4\0"
   /* 109311 */ "SAMPLER TEXTURE CACHE MISS XECORE5\0"
   /* 109346 */ "SAMPLER TEXTURE CACHE MISS XECORE6\0"
   /* 109381 */ "SAMPLER TEXTURE CACHE MISS XECORE7\0"
   /* 109416 */ "SAMPLER TEXTURE CACHE MISS XECORE8\0"
   /* 109451 */ "SAMPLER TEXTURE CACHE MISS XECORE9\0"
   /* 109486 */ "SF Stall\0"
   /* 109495 */ "SF0 Bottleneck\0"
   /* 109510 */ "SF0 Stall\0"
   /* 109520 */ "SF1 Bottleneck\0"
   /* 109535 */ "SF1 Stall\0"
   /* 109545 */ "SF2 Bottleneck\0"
   /* 109560 */ "SF2 Stall\0"
   /* 109570 */ "SF3 Bottleneck\0"
   /* 109585 */ "SF3 Stall\0"
   /* 109595 */ "SF4 Bottleneck\0"
   /* 109610 */ "SF4 Stall\0"
   /* 109620 */ "SF5 Bottleneck\0"
   /* 109635 */ "SF5 Stall\0"
   /* 109645 */ "SF6 Bottleneck\0"
   /* 109660 */ "SF6 Stall\0"
   /* 109670 */ "SF7 Bottleneck\0"
   /* 109685 */ "SF7 Stall\0"
   /* 109695 */ "SLM ACCESS COUNT BANK0 XECORE0\0"
   /* 109726 */ "SLM ACCESS COUNT BANK0 XECORE1\0"
   /* 109757 */ "SLM ACCESS COUNT BANK0 XECORE2\0"
   /* 109788 */ "SLM ACCESS COUNT BANK0 XECORE3\0"
   /* 109819 */ "SLM ACCESS COUNT BANK0 XECORE4\0"
   /* 109850 */ "SLM ACCESS COUNT BANK0 XECORE5\0"
   /* 109881 */ "SLM ACCESS COUNT BANK0 XECORE6\0"
   /* 109912 */ "SLM ACCESS COUNT BANK0 XECORE7\0"
   /* 109943 */ "SLM ACCESS COUNT BANK1 XECORE0\0"
   /* 109974 */ "SLM ACCESS COUNT BANK1 XECORE1\0"
   /* 110005 */ "SLM ACCESS COUNT BANK1 XECORE2\0"
   /* 110036 */ "SLM ACCESS COUNT BANK1 XECORE3\0"
   /* 110067 */ "SLM ACCESS COUNT BANK1 XECORE4\0"
   /* 110098 */ "SLM ACCESS COUNT BANK1 XECORE5\0"
   /* 110129 */ "SLM ACCESS COUNT BANK1 XECORE6\0"
   /* 110160 */ "SLM ACCESS COUNT BANK1 XECORE7\0"
   /* 110191 */ "SLM ACCESS COUNT XECORE0\0"
   /* 110216 */ "SLM ACCESS COUNT XECORE1\0"
   /* 110241 */ "SLM ACCESS COUNT XECORE10\0"
   /* 110267 */ "SLM ACCESS COUNT XECORE11\0"
   /* 110293 */ "SLM ACCESS COUNT XECORE12\0"
   /* 110319 */ "SLM ACCESS COUNT XECORE13\0"
   /* 110345 */ "SLM ACCESS COUNT XECORE14\0"
   /* 110371 */ "SLM ACCESS COUNT XECORE15\0"
   /* 110397 */ "SLM ACCESS COUNT XECORE16\0"
   /* 110423 */ "SLM ACCESS COUNT XECORE17\0"
   /* 110449 */ "SLM ACCESS COUNT XECORE18\0"
   /* 110475 */ "SLM ACCESS COUNT XECORE19\0"
   /* 110501 */ "SLM ACCESS COUNT XECORE2\0"
   /* 110526 */ "SLM ACCESS COUNT XECORE20\0"
   /* 110552 */ "SLM ACCESS COUNT XECORE21\0"
   /* 110578 */ "SLM ACCESS COUNT XECORE22\0"
   /* 110604 */ "SLM ACCESS COUNT XECORE23\0"
   /* 110630 */ "SLM ACCESS COUNT XECORE24\0"
   /* 110656 */ "SLM ACCESS COUNT XECORE25\0"
   /* 110682 */ "SLM ACCESS COUNT XECORE26\0"
   /* 110708 */ "SLM ACCESS COUNT XECORE27\0"
   /* 110734 */ "SLM ACCESS COUNT XECORE28\0"
   /* 110760 */ "SLM ACCESS COUNT XECORE29\0"
   /* 110786 */ "SLM ACCESS COUNT XECORE3\0"
   /* 110811 */ "SLM ACCESS COUNT XECORE30\0"
   /* 110837 */ "SLM ACCESS COUNT XECORE31\0"
   /* 110863 */ "SLM ACCESS COUNT XECORE4\0"
   /* 110888 */ "SLM ACCESS COUNT XECORE5\0"
   /* 110913 */ "SLM ACCESS COUNT XECORE6\0"
   /* 110938 */ "SLM ACCESS COUNT XECORE7\0"
   /* 110963 */ "SLM ACCESS COUNT XECORE8\0"
   /* 110988 */ "SLM ACCESS COUNT XECORE9\0"
   /* 111013 */ "SLM BANK CONFLICT COUNT\0"
   /* 111037 */ "SLM BANK CONFLICT COUNT XECORE0\0"
   /* 111069 */ "SLM BANK CONFLICT COUNT XECORE1\0"
   /* 111101 */ "SLM BANK CONFLICT COUNT XECORE10\0"
   /* 111134 */ "SLM BANK CONFLICT COUNT XECORE11\0"
   /* 111167 */ "SLM BANK CONFLICT COUNT XECORE12\0"
   /* 111200 */ "SLM BANK CONFLICT COUNT XECORE13\0"
   /* 111233 */ "SLM BANK CONFLICT COUNT XECORE14\0"
   /* 111266 */ "SLM BANK CONFLICT COUNT XECORE15\0"
   /* 111299 */ "SLM BANK CONFLICT COUNT XECORE16\0"
   /* 111332 */ "SLM BANK CONFLICT COUNT XECORE17\0"
   /* 111365 */ "SLM BANK CONFLICT COUNT XECORE18\0"
   /* 111398 */ "SLM BANK CONFLICT COUNT XECORE19\0"
   /* 111431 */ "SLM BANK CONFLICT COUNT XECORE2\0"
   /* 111463 */ "SLM BANK CONFLICT COUNT XECORE20\0"
   /* 111496 */ "SLM BANK CONFLICT COUNT XECORE21\0"
   /* 111529 */ "SLM BANK CONFLICT COUNT XECORE22\0"
   /* 111562 */ "SLM BANK CONFLICT COUNT XECORE23\0"
   /* 111595 */ "SLM BANK CONFLICT COUNT XECORE24\0"
   /* 111628 */ "SLM BANK CONFLICT COUNT XECORE25\0"
   /* 111661 */ "SLM BANK CONFLICT COUNT XECORE26\0"
   /* 111694 */ "SLM BANK CONFLICT COUNT XECORE27\0"
   /* 111727 */ "SLM BANK CONFLICT COUNT XECORE28\0"
   /* 111760 */ "SLM BANK CONFLICT COUNT XECORE29\0"
   /* 111793 */ "SLM BANK CONFLICT COUNT XECORE3\0"
   /* 111825 */ "SLM BANK CONFLICT COUNT XECORE30\0"
   /* 111858 */ "SLM BANK CONFLICT COUNT XECORE31\0"
   /* 111891 */ "SLM BANK CONFLICT COUNT XECORE4\0"
   /* 111923 */ "SLM BANK CONFLICT COUNT XECORE5\0"
   /* 111955 */ "SLM BANK CONFLICT COUNT XECORE6\0"
   /* 111987 */ "SLM BANK CONFLICT COUNT XECORE7\0"
   /* 112019 */ "SLM BANK CONFLICT COUNT XECORE8\0"
   /* 112051 */ "SLM BANK CONFLICT COUNT XECORE9\0"
   /* 112083 */ "SLM BYTE READ\0"
   /* 112097 */ "SLM BYTE READ BANK0 XECORE0\0"
   /* 112125 */ "SLM BYTE READ BANK0 XECORE1\0"
   /* 112153 */ "SLM BYTE READ BANK0 XECORE2\0"
   /* 112181 */ "SLM BYTE READ BANK0 XECORE3\0"
   /* 112209 */ "SLM BYTE READ BANK0 XECORE4\0"
   /* 112237 */ "SLM BYTE READ BANK0 XECORE5\0"
   /* 112265 */ "SLM BYTE READ BANK0 XECORE6\0"
   /* 112293 */ "SLM BYTE READ BANK0 XECORE7\0"
   /* 112321 */ "SLM BYTE READ BANK1 XECORE0\0"
   /* 112349 */ "SLM BYTE READ BANK1 XECORE1\0"
   /* 112377 */ "SLM BYTE READ BANK1 XECORE2\0"
   /* 112405 */ "SLM BYTE READ BANK1 XECORE3\0"
   /* 112433 */ "SLM BYTE READ BANK1 XECORE4\0"
   /* 112461 */ "SLM BYTE READ BANK1 XECORE5\0"
   /* 112489 */ "SLM BYTE READ BANK1 XECORE6\0"
   /* 112517 */ "SLM BYTE READ BANK1 XECORE7\0"
   /* 112545 */ "SLM BYTE READ BANK2 XECORE0\0"
   /* 112573 */ "SLM BYTE READ BANK2 XECORE1\0"
   /* 112601 */ "SLM BYTE READ BANK2 XECORE2\0"
   /* 112629 */ "SLM BYTE READ BANK2 XECORE3\0"
   /* 112657 */ "SLM BYTE READ BANK2 XECORE4\0"
   /* 112685 */ "SLM BYTE READ BANK2 XECORE5\0"
   /* 112713 */ "SLM BYTE READ BANK2 XECORE6\0"
   /* 112741 */ "SLM BYTE READ BANK2 XECORE7\0"
   /* 112769 */ "SLM BYTE READ BANK3 XECORE0\0"
   /* 112797 */ "SLM BYTE READ BANK3 XECORE1\0"
   /* 112825 */ "SLM BYTE READ BANK3 XECORE2\0"
   /* 112853 */ "SLM BYTE READ BANK3 XECORE3\0"
   /* 112881 */ "SLM BYTE READ BANK3 XECORE4\0"
   /* 112909 */ "SLM BYTE READ BANK3 XECORE5\0"
   /* 112937 */ "SLM BYTE READ BANK3 XECORE6\0"
   /* 112965 */ "SLM BYTE READ BANK3 XECORE7\0"
   /* 112993 */ "SLM BYTE WRITE\0"
   /* 113008 */ "SLM BYTE WRITE BANK0 XECORE0\0"
   /* 113037 */ "SLM BYTE WRITE BANK0 XECORE1\0"
   /* 113066 */ "SLM BYTE WRITE BANK0 XECORE2\0"
   /* 113095 */ "SLM BYTE WRITE BANK0 XECORE3\0"
   /* 113124 */ "SLM BYTE WRITE BANK0 XECORE4\0"
   /* 113153 */ "SLM BYTE WRITE BANK0 XECORE5\0"
   /* 113182 */ "SLM BYTE WRITE BANK0 XECORE6\0"
   /* 113211 */ "SLM BYTE WRITE BANK0 XECORE7\0"
   /* 113240 */ "SLM BYTE WRITE BANK1 XECORE0\0"
   /* 113269 */ "SLM BYTE WRITE BANK1 XECORE1\0"
   /* 113298 */ "SLM BYTE WRITE BANK1 XECORE2\0"
   /* 113327 */ "SLM BYTE WRITE BANK1 XECORE3\0"
   /* 113356 */ "SLM BYTE WRITE BANK1 XECORE4\0"
   /* 113385 */ "SLM BYTE WRITE BANK1 XECORE5\0"
   /* 113414 */ "SLM BYTE WRITE BANK1 XECORE6\0"
   /* 113443 */ "SLM BYTE WRITE BANK1 XECORE7\0"
   /* 113472 */ "SLM BYTE WRITE BANK2 XECORE0\0"
   /* 113501 */ "SLM BYTE WRITE BANK2 XECORE1\0"
   /* 113530 */ "SLM BYTE WRITE BANK2 XECORE2\0"
   /* 113559 */ "SLM BYTE WRITE BANK2 XECORE3\0"
   /* 113588 */ "SLM BYTE WRITE BANK2 XECORE4\0"
   /* 113617 */ "SLM BYTE WRITE BANK2 XECORE5\0"
   /* 113646 */ "SLM BYTE WRITE BANK2 XECORE6\0"
   /* 113675 */ "SLM BYTE WRITE BANK2 XECORE7\0"
   /* 113704 */ "SLM BYTE WRITE BANK3 XECORE0\0"
   /* 113733 */ "SLM BYTE WRITE BANK3 XECORE1\0"
   /* 113762 */ "SLM BYTE WRITE BANK3 XECORE2\0"
   /* 113791 */ "SLM BYTE WRITE BANK3 XECORE3\0"
   /* 113820 */ "SLM BYTE WRITE BANK3 XECORE4\0"
   /* 113849 */ "SLM BYTE WRITE BANK3 XECORE5\0"
   /* 113878 */ "SLM BYTE WRITE BANK3 XECORE6\0"
   /* 113907 */ "SLM BYTE WRITE BANK3 XECORE7\0"
   /* 113936 */ "SLM Bytes Read\0"
   /* 113951 */ "SLM Bytes Written\0"
   /* 113969 */ "SLM Writes\0"
   /* 113980 */ "SO Bottleneck\0"
   /* 113994 */ "SO Stall\0"
   /* 114003 */ "SO0 Bottleneck\0"
   /* 114018 */ "SO0 Stall\0"
   /* 114028 */ "SO1 Bottleneck\0"
   /* 114043 */ "SO1 Stall\0"
   /* 114053 */ "SO2 Bottleneck\0"
   /* 114068 */ "SO2 Stall\0"
   /* 114078 */ "SO3 Bottleneck\0"
   /* 114093 */ "SO3 Stall\0"
   /* 114103 */ "SO4 Bottleneck\0"
   /* 114118 */ "SO4 Stall\0"
   /* 114128 */ "SO5 Bottleneck\0"
   /* 114143 */ "SO5 Stall\0"
   /* 114153 */ "SO6 Bottleneck\0"
   /* 114168 */ "SO6 Stall\0"
   /* 114178 */ "SO7 Bottleneck\0"
   /* 114193 */ "SO7 Stall\0"
   /* 114203 */ "SQ is full\0"
   /* 114214 */ "SQ00 is full\0"
   /* 114227 */ "SQ01 is full\0"
   /* 114240 */ "SQ10 is full\0"
   /* 114253 */ "SQ11 is full\0"
   /* 114266 */ "SQ20 is full\0"
   /* 114279 */ "SQ30 is full\0"
   /* 114292 */ "SQ40 is full\0"
   /* 114305 */ "SQ50 is full\0"
   /* 114318 */ "SQ60 is full\0"
   /* 114331 */ "SQ70 is full\0"
   /* 114344 */ "STC PMA stall\0"
   /* 114358 */ "STREAMOUT OUTPUT VERTEX COUNT SLICE0\0"
   /* 114395 */ "STREAMOUT OUTPUT VERTEX COUNT SLICE1\0"
   /* 114432 */ "STREAMOUT OUTPUT VERTEX COUNT SLICE2\0"
   /* 114469 */ "STREAMOUT OUTPUT VERTEX COUNT SLICE3\0"
   /* 114506 */ "STREAMOUT OUTPUT VERTEX COUNT SLICE4\0"
   /* 114543 */ "STREAMOUT OUTPUT VERTEX COUNT SLICE5\0"
   /* 114580 */ "STREAMOUT OUTPUT VERTEX COUNT SLICE6\0"
   /* 114617 */ "STREAMOUT OUTPUT VERTEX COUNT SLICE7\0"
   /* 114654 */ "STRIPSFAN OBJECT COUNT SLICE0\0"
   /* 114684 */ "STRIPSFAN OBJECT COUNT SLICE1\0"
   /* 114714 */ "STRIPSFAN OBJECT COUNT SLICE2\0"
   /* 114744 */ "STRIPSFAN OBJECT COUNT SLICE3\0"
   /* 114774 */ "STRIPSFAN OBJECT COUNT SLICE4\0"
   /* 114804 */ "STRIPSFAN OBJECT COUNT SLICE5\0"
   /* 114834 */ "STRIPSFAN OBJECT COUNT SLICE6\0"
   /* 114864 */ "STRIPSFAN OBJECT COUNT SLICE7\0"
   /* 114894 */ "STRIPSFAN OBJECTS CULL SLICE0\0"
   /* 114924 */ "STRIPSFAN OBJECTS CULL SLICE1\0"
   /* 114954 */ "STRIPSFAN OBJECTS CULL SLICE2\0"
   /* 114984 */ "STRIPSFAN OBJECTS CULL SLICE3\0"
   /* 115014 */ "STRIPSFAN OBJECTS CULL SLICE4\0"
   /* 115044 */ "STRIPSFAN OBJECTS CULL SLICE5\0"
   /* 115074 */ "STRIPSFAN OBJECTS CULL SLICE6\0"
   /* 115104 */ "STRIPSFAN OBJECTS CULL SLICE7\0"
   /* 115134 */ "STRIPSFAN OUTPUT READY SLICE0\0"
   /* 115164 */ "STRIPSFAN OUTPUT READY SLICE1\0"
   /* 115194 */ "STRIPSFAN OUTPUT READY SLICE2\0"
   /* 115224 */ "STRIPSFAN OUTPUT READY SLICE3\0"
   /* 115254 */ "STRIPSFAN OUTPUT READY SLICE4\0"
   /* 115284 */ "STRIPSFAN OUTPUT READY SLICE5\0"
   /* 115314 */ "STRIPSFAN OUTPUT READY SLICE6\0"
   /* 115344 */ "STRIPSFAN OUTPUT READY SLICE7\0"
   /* 115374 */ "SYSMEM BYTE READ\0"
   /* 115391 */ "SYSMEM BYTE WRITE\0"
   /* 115409 */ "SYSMEM TRANSACTION READ\0"
   /* 115433 */ "SYSMEM TRANSACTION WRITE\0"
   /* 115458 */ "Sampler 0 Bottleneck\0"
   /* 115479 */ "Sampler 0 Busy\0"
   /* 115494 */ "Sampler 0 Texels LOD0\0"
   /* 115516 */ "Sampler 1 Bottleneck\0"
   /* 115537 */ "Sampler 1 Busy\0"
   /* 115552 */ "Sampler 1 Texels LOD0\0"
   /* 115574 */ "Sampler Accesses\0"
   /* 115591 */ "Sampler Bottleneck\0"
   /* 115610 */ "Sampler Cache Misses\0"
   /* 115631 */ "Sampler L2 cache misses\0"
   /* 115655 */ "Sampler L2 cache misses (ss0)\0"
   /* 115685 */ "Sampler L2 cache misses (ss1)\0"
   /* 115715 */ "Sampler L2 cache misses (ss2)\0"
   /* 115745 */ "Sampler L2 cache misses (ss3)\0"
   /* 115775 */ "Sampler Slice0 Dualsubslice0 is bottleneck\0"
   /* 115818 */ "Sampler Slice0 Xe Core0 is busy\0"
   /* 115850 */ "Sampler Slice2 Xe Core0 is busy\0"
   /* 115882 */ "Sampler Texels\0"
   /* 115897 */ "Sampler Texels LOD0\0"
   /* 115917 */ "Sampler Texels Misses\0"
   /* 115939 */ "Sampler00 Bottleneck\0"
   /* 115960 */ "Sampler00 Busy\0"
   /* 115975 */ "Sampler20 Bottleneck\0"
   /* 115996 */ "Samplers Bottleneck\0"
   /* 116016 */ "Samplers Busy\0"
   /* 116030 */ "Samples Blended\0"
   /* 116046 */ "Samples Killed in FS\0"
   /* 116067 */ "Samples Written\0"
   /* 116083 */ "Send Pipe Active\0"
   /* 116100 */ "Shader Atomic Memory Accesses\0"
   /* 116130 */ "Shader Barrier Messages\0"
   /* 116154 */ "Shader Memory Accesses\0"
   /* 116177 */ "Slice0 DualSubslice0 Input Available\0"
   /* 116214 */ "Slice0 DualSubslice0 Sampler Output Ready\0"
   /* 116256 */ "Slice0 DualSubslice1 Input Available\0"
   /* 116293 */ "Slice0 DualSubslice1 Sampler Output Ready\0"
   /* 116335 */ "Slice0 DualSubslice2 Input Available\0"
   /* 116372 */ "Slice0 DualSubslice2 Sampler Output Ready\0"
   /* 116414 */ "Slice0 DualSubslice3 Input Available\0"
   /* 116451 */ "Slice0 DualSubslice3 Sampler Output Ready\0"
   /* 116493 */ "Slice0 DualSubslice4 Input Available\0"
   /* 116530 */ "Slice0 DualSubslice4 Sampler Output Ready\0"
   /* 116572 */ "Slice0 DualSubslice5 Input Available\0"
   /* 116609 */ "Slice0 DualSubslice5 Sampler Output Ready\0"
   /* 116651 */ "Slice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3\0"
   /* 116712 */ "Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3\0"
   /* 116773 */ "Slice0 Dualsubslice2 Non-sampler Shader Access Stalled On L3\0"
   /* 116834 */ "Slice0 Dualsubslice3 Non-sampler Shader Access Stalled On L3\0"
   /* 116895 */ "Slice0 Dualsubslice4 Non-sampler Shader Access Stalled On L3\0"
   /* 116956 */ "Slice0 Dualsubslice5 Non-sampler Shader Access Stalled On L3\0"
   /* 117017 */ "Slice0 L3 Bank0 Accesses\0"
   /* 117042 */ "Slice0 L3 Bank0 Active\0"
   /* 117065 */ "Slice0 L3 Bank0 Input Available\0"
   /* 117097 */ "Slice0 L3 Bank0 Output Ready\0"
   /* 117126 */ "Slice0 L3 Bank0 Stalled\0"
   /* 117150 */ "Slice0 L3 Bank1 Accesses\0"
   /* 117175 */ "Slice0 L3 Bank1 Active\0"
   /* 117198 */ "Slice0 L3 Bank1 Input Available\0"
   /* 117230 */ "Slice0 L3 Bank1 Output Ready\0"
   /* 117259 */ "Slice0 L3 Bank1 Stalled\0"
   /* 117283 */ "Slice0 L3 Bank2 Accesses\0"
   /* 117308 */ "Slice0 L3 Bank2 Active\0"
   /* 117331 */ "Slice0 L3 Bank2 Input Available\0"
   /* 117363 */ "Slice0 L3 Bank2 Output Ready\0"
   /* 117392 */ "Slice0 L3 Bank2 Stalled\0"
   /* 117416 */ "Slice0 L3 Bank3 Accesses\0"
   /* 117441 */ "Slice0 L3 Bank3 Active\0"
   /* 117464 */ "Slice0 L3 Bank3 Input Available\0"
   /* 117496 */ "Slice0 L3 Bank3 Output Ready\0"
   /* 117525 */ "Slice0 L3 Bank3 Stalled\0"
   /* 117549 */ "Slice0 L3 Bank4 Accesses\0"
   /* 117574 */ "Slice0 L3 Bank4 Active\0"
   /* 117597 */ "Slice0 L3 Bank4 Input Available\0"
   /* 117629 */ "Slice0 L3 Bank4 Output Ready\0"
   /* 117658 */ "Slice0 L3 Bank4 Stalled\0"
   /* 117682 */ "Slice0 L3 Bank5 Accesses\0"
   /* 117707 */ "Slice0 L3 Bank5 Active\0"
   /* 117730 */ "Slice0 L3 Bank5 Input Available\0"
   /* 117762 */ "Slice0 L3 Bank5 Output Ready\0"
   /* 117791 */ "Slice0 L3 Bank5 Stalled\0"
   /* 117815 */ "Slice0 L3 Bank6 Accesses\0"
   /* 117840 */ "Slice0 L3 Bank6 Active\0"
   /* 117863 */ "Slice0 L3 Bank6 Input Available\0"
   /* 117895 */ "Slice0 L3 Bank6 Output Ready\0"
   /* 117924 */ "Slice0 L3 Bank7 Accesses\0"
   /* 117949 */ "Slice0 L3 Bank7 Active\0"
   /* 117972 */ "Slice0 L3 Bank7 Input Available\0"
   /* 118004 */ "Slice0 L3 Bank7 Output Ready\0"
   /* 118033 */ "Slice0 PS Output Available\0"
   /* 118060 */ "Slice0 Pipe0 PS Output Available\0"
   /* 118093 */ "Slice0 Pipe0 Pixel Values Ready\0"
   /* 118125 */ "Slice0 Pipe0 Post-EarlyZ Pixel Data Ready\0"
   /* 118167 */ "Slice0 Pipe1 PS Output Available\0"
   /* 118200 */ "Slice0 Pipe1 Pixel Values Ready\0"
   /* 118232 */ "Slice0 Pipe1 Post-EarlyZ Pixel Data Ready\0"
   /* 118274 */ "Slice0 Pipe2 PS Output Available\0"
   /* 118307 */ "Slice0 Pipe2 Pixel Values Ready\0"
   /* 118339 */ "Slice0 Pipe2 Post-EarlyZ Pixel Data Ready\0"
   /* 118381 */ "Slice0 Pixel Values Ready\0"
   /* 118407 */ "Slice0 Post-EarlyZ Pixel Data Ready\0"
   /* 118443 */ "Slice0 Rasterizer Input Available\0"
   /* 118477 */ "Slice0 Rasterizer Output Ready\0"
   /* 118508 */ "Slice0 Subslice group 0 Non-sampler Shader Access Stalled On L3\0"
   /* 118572 */ "Slice0 Subslice group 1 Non-sampler Shader Access Stalled On L3\0"
   /* 118636 */ "Slice0 Subslice group 2 Non-sampler Shader Access Stalled On L3\0"
   /* 118700 */ "Slice0 Subslice group 3 Non-sampler Shader Access Stalled On L3\0"
   /* 118764 */ "Slice0 Subslice0 Input Available\0"
   /* 118797 */ "Slice0 Subslice0 Sampler Output Ready\0"
   /* 118835 */ "Slice0 Subslice1 Input Available\0"
   /* 118868 */ "Slice0 Subslice1 Sampler Output Ready\0"
   /* 118906 */ "Slice0 Subslice2 Input Available\0"
   /* 118939 */ "Slice0 Subslice2 Sampler Output Ready\0"
   /* 118977 */ "Slice0 Subslice3 Input Available\0"
   /* 119010 */ "Slice0 Subslice3 Sampler Output Ready\0"
   /* 119048 */ "Slice0 Subslice4 Input Available\0"
   /* 119081 */ "Slice0 Subslice4 Sampler Output Ready\0"
   /* 119119 */ "Slice0 Subslice5 Input Available\0"
   /* 119152 */ "Slice0 Subslice5 Sampler Output Ready\0"
   /* 119190 */ "Slice0 Subslice6 Input Available\0"
   /* 119223 */ "Slice0 Subslice6 Sampler Output Ready\0"
   /* 119261 */ "Slice0 Subslice7 Input Available\0"
   /* 119294 */ "Slice0 Subslice7 Sampler Output Ready\0"
   /* 119332 */ "Slice0 Xe Core0 Input Available\0"
   /* 119364 */ "Slice0 Xe Core0 Non-sampler Shader Access Stalled On L3\0"
   /* 119420 */ "Slice0 Xe Core0 Sampler Output Ready\0"
   /* 119457 */ "Slice0 Xe Core1 Input Available\0"
   /* 119489 */ "Slice0 Xe Core1 Non-sampler Shader Access Stalled On L3\0"
   /* 119545 */ "Slice0 Xe Core1 Sampler Output Ready\0"
   /* 119582 */ "Slice0 Xe Core2 Input Available\0"
   /* 119614 */ "Slice0 Xe Core2 Non-sampler Shader Access Stalled On L3\0"
   /* 119670 */ "Slice0 Xe Core2 Sampler Output Ready\0"
   /* 119707 */ "Slice0 Xe Core3 Input Available\0"
   /* 119739 */ "Slice0 Xe Core3 Non-sampler Shader Access Stalled On L3\0"
   /* 119795 */ "Slice0 Xe Core3 Sampler Output Ready\0"
   /* 119832 */ "Slice1 L3 Bank0 Active\0"
   /* 119855 */ "Slice1 L3 Bank0 Stalled\0"
   /* 119879 */ "Slice1 L3 Bank1 Active\0"
   /* 119902 */ "Slice1 L3 Bank1 Stalled\0"
   /* 119926 */ "Slice1 L3 Bank2 Active\0"
   /* 119949 */ "Slice1 L3 Bank2 Stalled\0"
   /* 119973 */ "Slice1 L3 Bank3 Active\0"
   /* 119996 */ "Slice1 L3 Bank3 Stalled\0"
   /* 120020 */ "Slice1 PS Output Available\0"
   /* 120047 */ "Slice1 Pipe0 Post-EarlyZ Pixel Data Ready\0"
   /* 120089 */ "Slice1 Pipe1 Post-EarlyZ Pixel Data Ready\0"
   /* 120131 */ "Slice1 Pixel Values Ready\0"
   /* 120157 */ "Slice1 Post-EarlyZ Pixel Data Ready\0"
   /* 120193 */ "Slice1 Rasterizer Input Available\0"
   /* 120227 */ "Slice1 Rasterizer Output Ready\0"
   /* 120258 */ "Slice1 Subslice0 Input Available\0"
   /* 120291 */ "Slice1 Subslice0 Sampler Output Ready\0"
   /* 120329 */ "Slice1 Subslice1 Input Available\0"
   /* 120362 */ "Slice1 Subslice1 Sampler Output Ready\0"
   /* 120400 */ "Slice1 Subslice2 Input Available\0"
   /* 120433 */ "Slice1 Subslice2 Sampler Output Ready\0"
   /* 120471 */ "Slice1 Xe Core0 Input Available\0"
   /* 120503 */ "Slice1 Xe Core0 Non-sampler Shader Access Stalled On L3\0"
   /* 120559 */ "Slice1 Xe Core0 Sampler Output Ready\0"
   /* 120596 */ "Slice1 Xe Core1 Input Available\0"
   /* 120628 */ "Slice1 Xe Core1 Non-sampler Shader Access Stalled On L3\0"
   /* 120684 */ "Slice1 Xe Core1 Sampler Output Ready\0"
   /* 120721 */ "Slice1 Xe Core2 Input Available\0"
   /* 120753 */ "Slice1 Xe Core2 Non-sampler Shader Access Stalled On L3\0"
   /* 120809 */ "Slice1 Xe Core2 Sampler Output Ready\0"
   /* 120846 */ "Slice1 Xe Core3 Input Available\0"
   /* 120878 */ "Slice1 Xe Core3 Non-sampler Shader Access Stalled On L3\0"
   /* 120934 */ "Slice1 Xe Core3 Sampler Output Ready\0"
   /* 120971 */ "Slice2 Pipe0 Post-EarlyZ Pixel Data Ready\0"
   /* 121013 */ "Slice2 Pipe1 Post-EarlyZ Pixel Data Ready\0"
   /* 121055 */ "Slice2 Rasterizer Input Available\0"
   /* 121089 */ "Slice2 Rasterizer Output Ready\0"
   /* 121120 */ "Slice2 Xe Core0 Input Available\0"
   /* 121152 */ "Slice2 Xe Core0 Non-sampler Shader Access Stalled On L3\0"
   /* 121208 */ "Slice2 Xe Core0 Sampler Output Ready\0"
   /* 121245 */ "Slice2 Xe Core1 Input Available\0"
   /* 121277 */ "Slice2 Xe Core1 Non-sampler Shader Access Stalled On L3\0"
   /* 121333 */ "Slice2 Xe Core1 Sampler Output Ready\0"
   /* 121370 */ "Slice2 Xe Core2 Input Available\0"
   /* 121402 */ "Slice2 Xe Core2 Non-sampler Shader Access Stalled On L3\0"
   /* 121458 */ "Slice2 Xe Core2 Sampler Output Ready\0"
   /* 121495 */ "Slice2 Xe Core3 Input Available\0"
   /* 121527 */ "Slice2 Xe Core3 Non-sampler Shader Access Stalled On L3\0"
   /* 121583 */ "Slice2 Xe Core3 Sampler Output Ready\0"
   /* 121620 */ "Slice3 Pipe0 Post-EarlyZ Pixel Data Ready\0"
   /* 121662 */ "Slice3 Pipe1 Post-EarlyZ Pixel Data Ready\0"
   /* 121704 */ "Slice3 Rasterizer Input Available\0"
   /* 121738 */ "Slice3 Rasterizer Output Ready\0"
   /* 121769 */ "Slice3 Xe Core0 Input Available\0"
   /* 121801 */ "Slice3 Xe Core0 Non-sampler Shader Access Stalled On L3\0"
   /* 121857 */ "Slice3 Xe Core0 Sampler Output Ready\0"
   /* 121894 */ "Slice3 Xe Core1 Input Available\0"
   /* 121926 */ "Slice3 Xe Core1 Non-sampler Shader Access Stalled On L3\0"
   /* 121982 */ "Slice3 Xe Core1 Sampler Output Ready\0"
   /* 122019 */ "Slice3 Xe Core2 Input Available\0"
   /* 122051 */ "Slice3 Xe Core2 Non-sampler Shader Access Stalled On L3\0"
   /* 122107 */ "Slice3 Xe Core2 Sampler Output Ready\0"
   /* 122144 */ "Slice3 Xe Core3 Input Available\0"
   /* 122176 */ "Slice3 Xe Core3 Non-sampler Shader Access Stalled On L3\0"
   /* 122232 */ "Slice3 Xe Core3 Sampler Output Ready\0"
   /* 122269 */ "Slice4 Pipe0 Post-EarlyZ Pixel Data Ready\0"
   /* 122311 */ "Slice4 Pipe1 Post-EarlyZ Pixel Data Ready\0"
   /* 122353 */ "Slice4 Rasterizer Input Available\0"
   /* 122387 */ "Slice4 Rasterizer Output Ready\0"
   /* 122418 */ "Slice4 Xe Core0 Input Available\0"
   /* 122450 */ "Slice4 Xe Core0 Non-sampler Shader Access Stalled On L3\0"
   /* 122506 */ "Slice4 Xe Core0 Sampler Output Ready\0"
   /* 122543 */ "Slice4 Xe Core1 Input Available\0"
   /* 122575 */ "Slice4 Xe Core1 Non-sampler Shader Access Stalled On L3\0"
   /* 122631 */ "Slice4 Xe Core1 Sampler Output Ready\0"
   /* 122668 */ "Slice4 Xe Core2 Input Available\0"
   /* 122700 */ "Slice4 Xe Core2 Non-sampler Shader Access Stalled On L3\0"
   /* 122756 */ "Slice4 Xe Core2 Sampler Output Ready\0"
   /* 122793 */ "Slice4 Xe Core3 Input Available\0"
   /* 122825 */ "Slice4 Xe Core3 Non-sampler Shader Access Stalled On L3\0"
   /* 122881 */ "Slice4 Xe Core3 Sampler Output Ready\0"
   /* 122918 */ "Slice5 Pipe0 Post-EarlyZ Pixel Data Ready\0"
   /* 122960 */ "Slice5 Pipe1 Post-EarlyZ Pixel Data Ready\0"
   /* 123002 */ "Slice5 Rasterizer Input Available\0"
   /* 123036 */ "Slice5 Rasterizer Output Ready\0"
   /* 123067 */ "Slice5 Xe Core0 Input Available\0"
   /* 123099 */ "Slice5 Xe Core0 Non-sampler Shader Access Stalled On L3\0"
   /* 123155 */ "Slice5 Xe Core0 Sampler Output Ready\0"
   /* 123192 */ "Slice5 Xe Core1 Input Available\0"
   /* 123224 */ "Slice5 Xe Core1 Non-sampler Shader Access Stalled On L3\0"
   /* 123280 */ "Slice5 Xe Core1 Sampler Output Ready\0"
   /* 123317 */ "Slice5 Xe Core2 Input Available\0"
   /* 123349 */ "Slice5 Xe Core2 Non-sampler Shader Access Stalled On L3\0"
   /* 123405 */ "Slice5 Xe Core2 Sampler Output Ready\0"
   /* 123442 */ "Slice5 Xe Core3 Input Available\0"
   /* 123474 */ "Slice5 Xe Core3 Non-sampler Shader Access Stalled On L3\0"
   /* 123530 */ "Slice5 Xe Core3 Sampler Output Ready\0"
   /* 123567 */ "Slice6 Pipe0 Post-EarlyZ Pixel Data Ready\0"
   /* 123609 */ "Slice6 Pipe1 Post-EarlyZ Pixel Data Ready\0"
   /* 123651 */ "Slice6 Rasterizer Input Available\0"
   /* 123685 */ "Slice6 Rasterizer Output Ready\0"
   /* 123716 */ "Slice6 Xe Core0 Input Available\0"
   /* 123748 */ "Slice6 Xe Core0 Non-sampler Shader Access Stalled On L3\0"
   /* 123804 */ "Slice6 Xe Core0 Sampler Output Ready\0"
   /* 123841 */ "Slice6 Xe Core1 Input Available\0"
   /* 123873 */ "Slice6 Xe Core1 Non-sampler Shader Access Stalled On L3\0"
   /* 123929 */ "Slice6 Xe Core1 Sampler Output Ready\0"
   /* 123966 */ "Slice6 Xe Core2 Input Available\0"
   /* 123998 */ "Slice6 Xe Core2 Non-sampler Shader Access Stalled On L3\0"
   /* 124054 */ "Slice6 Xe Core2 Sampler Output Ready\0"
   /* 124091 */ "Slice6 Xe Core3 Input Available\0"
   /* 124123 */ "Slice6 Xe Core3 Non-sampler Shader Access Stalled On L3\0"
   /* 124179 */ "Slice6 Xe Core3 Sampler Output Ready\0"
   /* 124216 */ "Slice7 Pipe0 Post-EarlyZ Pixel Data Ready\0"
   /* 124258 */ "Slice7 Pipe1 Post-EarlyZ Pixel Data Ready\0"
   /* 124300 */ "Slice7 Rasterizer Input Available\0"
   /* 124334 */ "Slice7 Rasterizer Output Ready\0"
   /* 124365 */ "Slice7 Xe Core0 Input Available\0"
   /* 124397 */ "Slice7 Xe Core0 Non-sampler Shader Access Stalled On L3\0"
   /* 124453 */ "Slice7 Xe Core0 Sampler Output Ready\0"
   /* 124490 */ "Slice7 Xe Core1 Input Available\0"
   /* 124522 */ "Slice7 Xe Core1 Non-sampler Shader Access Stalled On L3\0"
   /* 124578 */ "Slice7 Xe Core1 Sampler Output Ready\0"
   /* 124615 */ "Slice7 Xe Core2 Input Available\0"
   /* 124647 */ "Slice7 Xe Core2 Non-sampler Shader Access Stalled On L3\0"
   /* 124703 */ "Slice7 Xe Core2 Sampler Output Ready\0"
   /* 124740 */ "Slice7 Xe Core3 Input Available\0"
   /* 124772 */ "Slice7 Xe Core3 Non-sampler Shader Access Stalled On L3\0"
   /* 124828 */ "Slice7 Xe Core3 Sampler Output Ready\0"
   /* 124865 */ "Strip-Fans Bottleneck\0"
   /* 124887 */ "TASK THREAD EXIT COUNT XECORE0\0"
   /* 124918 */ "TASK THREAD EXIT COUNT XECORE1\0"
   /* 124949 */ "TASK THREAD EXIT COUNT XECORE10\0"
   /* 124981 */ "TASK THREAD EXIT COUNT XECORE11\0"
   /* 125013 */ "TASK THREAD EXIT COUNT XECORE12\0"
   /* 125045 */ "TASK THREAD EXIT COUNT XECORE13\0"
   /* 125077 */ "TASK THREAD EXIT COUNT XECORE14\0"
   /* 125109 */ "TASK THREAD EXIT COUNT XECORE15\0"
   /* 125141 */ "TASK THREAD EXIT COUNT XECORE16\0"
   /* 125173 */ "TASK THREAD EXIT COUNT XECORE17\0"
   /* 125205 */ "TASK THREAD EXIT COUNT XECORE18\0"
   /* 125237 */ "TASK THREAD EXIT COUNT XECORE19\0"
   /* 125269 */ "TASK THREAD EXIT COUNT XECORE2\0"
   /* 125300 */ "TASK THREAD EXIT COUNT XECORE20\0"
   /* 125332 */ "TASK THREAD EXIT COUNT XECORE21\0"
   /* 125364 */ "TASK THREAD EXIT COUNT XECORE22\0"
   /* 125396 */ "TASK THREAD EXIT COUNT XECORE23\0"
   /* 125428 */ "TASK THREAD EXIT COUNT XECORE24\0"
   /* 125460 */ "TASK THREAD EXIT COUNT XECORE25\0"
   /* 125492 */ "TASK THREAD EXIT COUNT XECORE26\0"
   /* 125524 */ "TASK THREAD EXIT COUNT XECORE27\0"
   /* 125556 */ "TASK THREAD EXIT COUNT XECORE28\0"
   /* 125588 */ "TASK THREAD EXIT COUNT XECORE29\0"
   /* 125620 */ "TASK THREAD EXIT COUNT XECORE3\0"
   /* 125651 */ "TASK THREAD EXIT COUNT XECORE30\0"
   /* 125683 */ "TASK THREAD EXIT COUNT XECORE31\0"
   /* 125715 */ "TASK THREAD EXIT COUNT XECORE4\0"
   /* 125746 */ "TASK THREAD EXIT COUNT XECORE5\0"
   /* 125777 */ "TASK THREAD EXIT COUNT XECORE6\0"
   /* 125808 */ "TASK THREAD EXIT COUNT XECORE7\0"
   /* 125839 */ "TASK THREAD EXIT COUNT XECORE8\0"
   /* 125870 */ "TASK THREAD EXIT COUNT XECORE9\0"
   /* 125901 */ "TASK THREADGROUP COUNT XECORE0\0"
   /* 125932 */ "TASK THREADGROUP COUNT XECORE1\0"
   /* 125963 */ "TASK THREADGROUP COUNT XECORE10\0"
   /* 125995 */ "TASK THREADGROUP COUNT XECORE11\0"
   /* 126027 */ "TASK THREADGROUP COUNT XECORE12\0"
   /* 126059 */ "TASK THREADGROUP COUNT XECORE13\0"
   /* 126091 */ "TASK THREADGROUP COUNT XECORE14\0"
   /* 126123 */ "TASK THREADGROUP COUNT XECORE15\0"
   /* 126155 */ "TASK THREADGROUP COUNT XECORE16\0"
   /* 126187 */ "TASK THREADGROUP COUNT XECORE17\0"
   /* 126219 */ "TASK THREADGROUP COUNT XECORE18\0"
   /* 126251 */ "TASK THREADGROUP COUNT XECORE19\0"
   /* 126283 */ "TASK THREADGROUP COUNT XECORE2\0"
   /* 126314 */ "TASK THREADGROUP COUNT XECORE20\0"
   /* 126346 */ "TASK THREADGROUP COUNT XECORE21\0"
   /* 126378 */ "TASK THREADGROUP COUNT XECORE22\0"
   /* 126410 */ "TASK THREADGROUP COUNT XECORE23\0"
   /* 126442 */ "TASK THREADGROUP COUNT XECORE24\0"
   /* 126474 */ "TASK THREADGROUP COUNT XECORE25\0"
   /* 126506 */ "TASK THREADGROUP COUNT XECORE26\0"
   /* 126538 */ "TASK THREADGROUP COUNT XECORE27\0"
   /* 126570 */ "TASK THREADGROUP COUNT XECORE28\0"
   /* 126602 */ "TASK THREADGROUP COUNT XECORE29\0"
   /* 126634 */ "TASK THREADGROUP COUNT XECORE3\0"
   /* 126665 */ "TASK THREADGROUP COUNT XECORE30\0"
   /* 126697 */ "TASK THREADGROUP COUNT XECORE31\0"
   /* 126729 */ "TASK THREADGROUP COUNT XECORE4\0"
   /* 126760 */ "TASK THREADGROUP COUNT XECORE5\0"
   /* 126791 */ "TASK THREADGROUP COUNT XECORE6\0"
   /* 126822 */ "TASK THREADGROUP COUNT XECORE7\0"
   /* 126853 */ "TASK THREADGROUP COUNT XECORE8\0"
   /* 126884 */ "TASK THREADGROUP COUNT XECORE9\0"
   /* 126915 */ "TCS AVG Active per Thread\0"
   /* 126941 */ "TCS AVG Stall per Thread\0"
   /* 126966 */ "TCS Duration\0"
   /* 126979 */ "TCS EU Active\0"
   /* 126993 */ "TCS EU Stall\0"
   /* 127006 */ "TCS Threads Dispatched\0"
   /* 127029 */ "TE Bottleneck\0"
   /* 127043 */ "TES AVG Active per Thread\0"
   /* 127069 */ "TES AVG Stall per Thread\0"
   /* 127094 */ "TES Duration\0"
   /* 127107 */ "TES EU Active\0"
   /* 127121 */ "TES EU Stall\0"
   /* 127134 */ "TES Threads Dispatched\0"
   /* 127157 */ "THREAD DISPATCH INPUT AVAILABLE XECORE0\0"
   /* 127197 */ "THREAD DISPATCH INPUT AVAILABLE XECORE1\0"
   /* 127237 */ "THREAD DISPATCH INPUT AVAILABLE XECORE10\0"
   /* 127278 */ "THREAD DISPATCH INPUT AVAILABLE XECORE11\0"
   /* 127319 */ "THREAD DISPATCH INPUT AVAILABLE XECORE12\0"
   /* 127360 */ "THREAD DISPATCH INPUT AVAILABLE XECORE13\0"
   /* 127401 */ "THREAD DISPATCH INPUT AVAILABLE XECORE14\0"
   /* 127442 */ "THREAD DISPATCH INPUT AVAILABLE XECORE15\0"
   /* 127483 */ "THREAD DISPATCH INPUT AVAILABLE XECORE16\0"
   /* 127524 */ "THREAD DISPATCH INPUT AVAILABLE XECORE17\0"
   /* 127565 */ "THREAD DISPATCH INPUT AVAILABLE XECORE18\0"
   /* 127606 */ "THREAD DISPATCH INPUT AVAILABLE XECORE19\0"
   /* 127647 */ "THREAD DISPATCH INPUT AVAILABLE XECORE2\0"
   /* 127687 */ "THREAD DISPATCH INPUT AVAILABLE XECORE20\0"
   /* 127728 */ "THREAD DISPATCH INPUT AVAILABLE XECORE21\0"
   /* 127769 */ "THREAD DISPATCH INPUT AVAILABLE XECORE22\0"
   /* 127810 */ "THREAD DISPATCH INPUT AVAILABLE XECORE23\0"
   /* 127851 */ "THREAD DISPATCH INPUT AVAILABLE XECORE24\0"
   /* 127892 */ "THREAD DISPATCH INPUT AVAILABLE XECORE25\0"
   /* 127933 */ "THREAD DISPATCH INPUT AVAILABLE XECORE26\0"
   /* 127974 */ "THREAD DISPATCH INPUT AVAILABLE XECORE27\0"
   /* 128015 */ "THREAD DISPATCH INPUT AVAILABLE XECORE28\0"
   /* 128056 */ "THREAD DISPATCH INPUT AVAILABLE XECORE29\0"
   /* 128097 */ "THREAD DISPATCH INPUT AVAILABLE XECORE3\0"
   /* 128137 */ "THREAD DISPATCH INPUT AVAILABLE XECORE30\0"
   /* 128178 */ "THREAD DISPATCH INPUT AVAILABLE XECORE31\0"
   /* 128219 */ "THREAD DISPATCH INPUT AVAILABLE XECORE4\0"
   /* 128259 */ "THREAD DISPATCH INPUT AVAILABLE XECORE5\0"
   /* 128299 */ "THREAD DISPATCH INPUT AVAILABLE XECORE6\0"
   /* 128339 */ "THREAD DISPATCH INPUT AVAILABLE XECORE7\0"
   /* 128379 */ "THREAD DISPATCH INPUT AVAILABLE XECORE8\0"
   /* 128419 */ "THREAD DISPATCH INPUT AVAILABLE XECORE9\0"
   /* 128459 */ "THREAD DISPATCH PS ACTIVE CYCLES XECORE0\0"
   /* 128500 */ "THREAD DISPATCH PS ACTIVE CYCLES XECORE1\0"
   /* 128541 */ "THREAD DISPATCH PS ACTIVE CYCLES XECORE2\0"
   /* 128582 */ "THREAD DISPATCH PS ACTIVE CYCLES XECORE3\0"
   /* 128623 */ "THREAD DISPATCH PS ACTIVE CYCLES XECORE4\0"
   /* 128664 */ "THREAD DISPATCH PS ACTIVE CYCLES XECORE5\0"
   /* 128705 */ "THREAD DISPATCH PS ACTIVE CYCLES XECORE6\0"
   /* 128746 */ "THREAD DISPATCH PS ACTIVE CYCLES XECORE7\0"
   /* 128787 */ "THREAD DISPATCH PS ACTIVE XECORE0\0"
   /* 128821 */ "THREAD DISPATCH PS ACTIVE XECORE1\0"
   /* 128855 */ "THREAD DISPATCH PS ACTIVE XECORE10\0"
   /* 128890 */ "THREAD DISPATCH PS ACTIVE XECORE11\0"
   /* 128925 */ "THREAD DISPATCH PS ACTIVE XECORE12\0"
   /* 128960 */ "THREAD DISPATCH PS ACTIVE XECORE13\0"
   /* 128995 */ "THREAD DISPATCH PS ACTIVE XECORE14\0"
   /* 129030 */ "THREAD DISPATCH PS ACTIVE XECORE15\0"
   /* 129065 */ "THREAD DISPATCH PS ACTIVE XECORE16\0"
   /* 129100 */ "THREAD DISPATCH PS ACTIVE XECORE17\0"
   /* 129135 */ "THREAD DISPATCH PS ACTIVE XECORE18\0"
   /* 129170 */ "THREAD DISPATCH PS ACTIVE XECORE19\0"
   /* 129205 */ "THREAD DISPATCH PS ACTIVE XECORE2\0"
   /* 129239 */ "THREAD DISPATCH PS ACTIVE XECORE20\0"
   /* 129274 */ "THREAD DISPATCH PS ACTIVE XECORE21\0"
   /* 129309 */ "THREAD DISPATCH PS ACTIVE XECORE22\0"
   /* 129344 */ "THREAD DISPATCH PS ACTIVE XECORE23\0"
   /* 129379 */ "THREAD DISPATCH PS ACTIVE XECORE24\0"
   /* 129414 */ "THREAD DISPATCH PS ACTIVE XECORE25\0"
   /* 129449 */ "THREAD DISPATCH PS ACTIVE XECORE26\0"
   /* 129484 */ "THREAD DISPATCH PS ACTIVE XECORE27\0"
   /* 129519 */ "THREAD DISPATCH PS ACTIVE XECORE28\0"
   /* 129554 */ "THREAD DISPATCH PS ACTIVE XECORE29\0"
   /* 129589 */ "THREAD DISPATCH PS ACTIVE XECORE3\0"
   /* 129623 */ "THREAD DISPATCH PS ACTIVE XECORE30\0"
   /* 129658 */ "THREAD DISPATCH PS ACTIVE XECORE31\0"
   /* 129693 */ "THREAD DISPATCH PS ACTIVE XECORE4\0"
   /* 129727 */ "THREAD DISPATCH PS ACTIVE XECORE5\0"
   /* 129761 */ "THREAD DISPATCH PS ACTIVE XECORE6\0"
   /* 129795 */ "THREAD DISPATCH PS ACTIVE XECORE7\0"
   /* 129829 */ "THREAD DISPATCH PS ACTIVE XECORE8\0"
   /* 129863 */ "THREAD DISPATCH PS ACTIVE XECORE9\0"
   /* 129897 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE0\0"
   /* 129935 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE1\0"
   /* 129973 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE10\0"
   /* 130012 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE11\0"
   /* 130051 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE12\0"
   /* 130090 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE13\0"
   /* 130129 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE14\0"
   /* 130168 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE15\0"
   /* 130207 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE16\0"
   /* 130246 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE17\0"
   /* 130285 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE18\0"
   /* 130324 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE19\0"
   /* 130363 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE2\0"
   /* 130401 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE20\0"
   /* 130440 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE21\0"
   /* 130479 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE22\0"
   /* 130518 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE23\0"
   /* 130557 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE24\0"
   /* 130596 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE25\0"
   /* 130635 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE26\0"
   /* 130674 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE27\0"
   /* 130713 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE28\0"
   /* 130752 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE29\0"
   /* 130791 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE3\0"
   /* 130829 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE30\0"
   /* 130868 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE31\0"
   /* 130907 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE4\0"
   /* 130945 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE5\0"
   /* 130983 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE6\0"
   /* 131021 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE7\0"
   /* 131059 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE8\0"
   /* 131097 */ "THREAD DISPATCH QUEUE0 ACTIVE XECORE9\0"
   /* 131135 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE0\0"
   /* 131173 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE1\0"
   /* 131211 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE10\0"
   /* 131250 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE11\0"
   /* 131289 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE12\0"
   /* 131328 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE13\0"
   /* 131367 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE14\0"
   /* 131406 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE15\0"
   /* 131445 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE16\0"
   /* 131484 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE17\0"
   /* 131523 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE18\0"
   /* 131562 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE19\0"
   /* 131601 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE2\0"
   /* 131639 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE20\0"
   /* 131678 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE21\0"
   /* 131717 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE22\0"
   /* 131756 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE23\0"
   /* 131795 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE24\0"
   /* 131834 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE25\0"
   /* 131873 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE26\0"
   /* 131912 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE27\0"
   /* 131951 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE28\0"
   /* 131990 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE29\0"
   /* 132029 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE3\0"
   /* 132067 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE30\0"
   /* 132106 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE31\0"
   /* 132145 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE4\0"
   /* 132183 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE5\0"
   /* 132221 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE6\0"
   /* 132259 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE7\0"
   /* 132297 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE8\0"
   /* 132335 */ "THREAD DISPATCH QUEUE1 ACTIVE XECORE9\0"
   /* 132373 */ "THREAD DISPATCH STALL XECORE0\0"
   /* 132403 */ "THREAD DISPATCH STALL XECORE1\0"
   /* 132433 */ "THREAD DISPATCH STALL XECORE10\0"
   /* 132464 */ "THREAD DISPATCH STALL XECORE11\0"
   /* 132495 */ "THREAD DISPATCH STALL XECORE12\0"
   /* 132526 */ "THREAD DISPATCH STALL XECORE13\0"
   /* 132557 */ "THREAD DISPATCH STALL XECORE14\0"
   /* 132588 */ "THREAD DISPATCH STALL XECORE15\0"
   /* 132619 */ "THREAD DISPATCH STALL XECORE16\0"
   /* 132650 */ "THREAD DISPATCH STALL XECORE17\0"
   /* 132681 */ "THREAD DISPATCH STALL XECORE18\0"
   /* 132712 */ "THREAD DISPATCH STALL XECORE19\0"
   /* 132743 */ "THREAD DISPATCH STALL XECORE2\0"
   /* 132773 */ "THREAD DISPATCH STALL XECORE20\0"
   /* 132804 */ "THREAD DISPATCH STALL XECORE21\0"
   /* 132835 */ "THREAD DISPATCH STALL XECORE22\0"
   /* 132866 */ "THREAD DISPATCH STALL XECORE23\0"
   /* 132897 */ "THREAD DISPATCH STALL XECORE24\0"
   /* 132928 */ "THREAD DISPATCH STALL XECORE25\0"
   /* 132959 */ "THREAD DISPATCH STALL XECORE26\0"
   /* 132990 */ "THREAD DISPATCH STALL XECORE27\0"
   /* 133021 */ "THREAD DISPATCH STALL XECORE28\0"
   /* 133052 */ "THREAD DISPATCH STALL XECORE29\0"
   /* 133083 */ "THREAD DISPATCH STALL XECORE3\0"
   /* 133113 */ "THREAD DISPATCH STALL XECORE30\0"
   /* 133144 */ "THREAD DISPATCH STALL XECORE31\0"
   /* 133175 */ "THREAD DISPATCH STALL XECORE4\0"
   /* 133205 */ "THREAD DISPATCH STALL XECORE5\0"
   /* 133235 */ "THREAD DISPATCH STALL XECORE6\0"
   /* 133265 */ "THREAD DISPATCH STALL XECORE7\0"
   /* 133295 */ "THREAD DISPATCH STALL XECORE8\0"
   /* 133325 */ "THREAD DISPATCH STALL XECORE9\0"
   /* 133355 */ "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE0\0"
   /* 133405 */ "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE1\0"
   /* 133455 */ "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE2\0"
   /* 133505 */ "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE3\0"
   /* 133555 */ "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE4\0"
   /* 133605 */ "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE5\0"
   /* 133655 */ "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE6\0"
   /* 133705 */ "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE7\0"
   /* 133755 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE0\0"
   /* 133807 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE1\0"
   /* 133859 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE10\0"
   /* 133912 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE11\0"
   /* 133965 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE12\0"
   /* 134018 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE13\0"
   /* 134071 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE14\0"
   /* 134124 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE15\0"
   /* 134177 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE16\0"
   /* 134230 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE17\0"
   /* 134283 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE18\0"
   /* 134336 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE19\0"
   /* 134389 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE2\0"
   /* 134441 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE20\0"
   /* 134494 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE21\0"
   /* 134547 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE22\0"
   /* 134600 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE23\0"
   /* 134653 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE24\0"
   /* 134706 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE25\0"
   /* 134759 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE26\0"
   /* 134812 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE27\0"
   /* 134865 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE28\0"
   /* 134918 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE29\0"
   /* 134971 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE3\0"
   /* 135023 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE30\0"
   /* 135076 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE31\0"
   /* 135129 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE4\0"
   /* 135181 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE5\0"
   /* 135233 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE6\0"
   /* 135285 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE7\0"
   /* 135337 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE8\0"
   /* 135389 */ "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE9\0"
   /* 135441 */ "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE0\0"
   /* 135491 */ "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE1\0"
   /* 135541 */ "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE2\0"
   /* 135591 */ "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE3\0"
   /* 135641 */ "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE4\0"
   /* 135691 */ "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE5\0"
   /* 135741 */ "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE6\0"
   /* 135791 */ "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE7\0"
   /* 135841 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE0\0"
   /* 135893 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE1\0"
   /* 135945 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE10\0"
   /* 135998 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE11\0"
   /* 136051 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE12\0"
   /* 136104 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE13\0"
   /* 136157 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE14\0"
   /* 136210 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE15\0"
   /* 136263 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE16\0"
   /* 136316 */ "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE17\0"
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   /* 151681 */ "Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 2\0"
   /* 151745 */ "Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 3\0"
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   /* 151994 */ "Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 2\0"
   /* 152058 */ "Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 3\0"
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   /* 152179 */ "Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 0\0"
   /* 152243 */ "Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 1\0"
   /* 152307 */ "Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 2\0"
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   /* 152795 */ "Typed Atomics Accesses\0"
   /* 152818 */ "Typed Bytes Read\0"
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   /* 153458 */ "URB WRITE SLICE7\0"
   /* 153475 */ "Untyped Bytes Read\0"
   /* 153494 */ "Untyped Reads 0\0"
   /* 153510 */ "Untyped Reads 00\0"
   /* 153527 */ "Untyped Writes\0"
   /* 153542 */ "Untyped Writes 0\0"
   /* 153559 */ "Untyped Writes 00\0"
   /* 153577 */ "UntypedReadsPerCacheLine\0"
   /* 153602 */ "UntypedWritesPerCacheLine\0"
   /* 153628 */ "VERTEX FETCH INPUT AVAILABLE SLICE0\0"
   /* 153664 */ "VERTEX FETCH INPUT AVAILABLE SLICE1\0"
   /* 153700 */ "VERTEX FETCH INPUT AVAILABLE SLICE2\0"
   /* 153736 */ "VERTEX FETCH INPUT AVAILABLE SLICE3\0"
   /* 153772 */ "VERTEX FETCH INPUT AVAILABLE SLICE4\0"
   /* 153808 */ "VERTEX FETCH INPUT AVAILABLE SLICE5\0"
   /* 153844 */ "VERTEX FETCH INPUT AVAILABLE SLICE6\0"
   /* 153880 */ "VERTEX FETCH INPUT AVAILABLE SLICE7\0"
   /* 153916 */ "VERTEX FETCH OUTPUT READY SLICE0\0"
   /* 153949 */ "VERTEX FETCH OUTPUT READY SLICE1\0"
   /* 153982 */ "VERTEX FETCH OUTPUT READY SLICE2\0"
   /* 154015 */ "VERTEX FETCH OUTPUT READY SLICE3\0"
   /* 154048 */ "VERTEX FETCH OUTPUT READY SLICE4\0"
   /* 154081 */ "VERTEX FETCH OUTPUT READY SLICE5\0"
   /* 154114 */ "VERTEX FETCH OUTPUT READY SLICE6\0"
   /* 154147 */ "VERTEX FETCH OUTPUT READY SLICE7\0"
   /* 154180 */ "VF Bottleneck\0"
   /* 154194 */ "VF0 Bottleneck\0"
   /* 154209 */ "VF1 Bottleneck\0"
   /* 154224 */ "VF2 Bottleneck\0"
   /* 154239 */ "VF3 Bottleneck\0"
   /* 154254 */ "VF4 Bottleneck\0"
   /* 154269 */ "VF5 Bottleneck\0"
   /* 154284 */ "VF6 Bottleneck\0"
   /* 154299 */ "VF7 Bottleneck\0"
   /* 154314 */ "VME Busy\0"
   /* 154323 */ "VS AVG Active per Thread\0"
   /* 154348 */ "VS AVG Stall per Thread\0"
   /* 154372 */ "VS Bottleneck\0"
   /* 154386 */ "VS Duration\0"
   /* 154398 */ "VS EM Pipe Active\0"
   /* 154416 */ "VS EU Active\0"
   /* 154429 */ "VS EU Stall\0"
   /* 154441 */ "VS FPU Pipe Active\0"
   /* 154460 */ "VS FPU0 Pipe Active\0"
   /* 154480 */ "VS FPU1 Pipe Active\0"
   /* 154500 */ "VS OUTPUT READY SLICE0\0"
   /* 154523 */ "VS OUTPUT READY SLICE1\0"
   /* 154546 */ "VS OUTPUT READY SLICE2\0"
   /* 154569 */ "VS OUTPUT READY SLICE3\0"
   /* 154592 */ "VS OUTPUT READY SLICE4\0"
   /* 154615 */ "VS OUTPUT READY SLICE5\0"
   /* 154638 */ "VS OUTPUT READY SLICE6\0"
   /* 154661 */ "VS OUTPUT READY SLICE7\0"
   /* 154684 */ "VS Send Pipe Active\0"
   /* 154704 */ "VS Threads Dispatched\0"
   /* 154726 */ "VS is sending vertices to CL\0"
   /* 154755 */ "VS0 Bottleneck\0"
   /* 154770 */ "VS1 Bottleneck\0"
   /* 154785 */ "VS2 Bottleneck\0"
   /* 154800 */ "VS3 Bottleneck\0"
   /* 154815 */ "VS4 Bottleneck\0"
   /* 154830 */ "VS5 Bottleneck\0"
   /* 154845 */ "VS6 Bottleneck\0"
   /* 154860 */ "VS7 Bottleneck\0"
   /* 154875 */ "Vdbox0 Ring Busy\0"
   /* 154892 */ "Vdbox00 Ring Busy\0"
   /* 154910 */ "Vdbox1 Ring Busy\0"
   /* 154927 */ "Vdbox10 Ring Busy\0"
   /* 154945 */ "Vebox Ring Busy\0"
   /* 154961 */ "Vebox0 Ring Busy\0"
   /* 154978 */ "Vebox1 Ring Busy\0"
   /* 154995 */ "XMX And FPU Pipes Active\0"
   /* 155020 */ "XMX Pipe Active\0"
   /* 155036 */ "XVE ACTIVE\0"
   /* 155047 */ "XVE ACTIVE ASYNC CS\0"
   /* 155067 */ "XVE ACTIVE CS\0"
   /* 155081 */ "XVE ACTIVE CYCLES\0"
   /* 155099 */ "XVE ACTIVE CYCLES ASYNC CS\0"
   /* 155126 */ "XVE ACTIVE CYCLES CS\0"
   /* 155147 */ "XVE ACTIVE CYCLES DS\0"
   /* 155168 */ "XVE ACTIVE CYCLES FS\0"
   /* 155189 */ "XVE ACTIVE CYCLES GS\0"
   /* 155210 */ "XVE ACTIVE CYCLES HS\0"
   /* 155231 */ "XVE ACTIVE CYCLES MS\0"
   /* 155252 */ "XVE ACTIVE CYCLES RT\0"
   /* 155273 */ "XVE ACTIVE CYCLES TS\0"
   /* 155294 */ "XVE ACTIVE CYCLES VS\0"
   /* 155315 */ "XVE ACTIVE DS\0"
   /* 155329 */ "XVE ACTIVE FS\0"
   /* 155343 */ "XVE ACTIVE GS\0"
   /* 155357 */ "XVE ACTIVE HS\0"
   /* 155371 */ "XVE ACTIVE MS\0"
   /* 155385 */ "XVE ACTIVE RT\0"
   /* 155399 */ "XVE ACTIVE TS\0"
   /* 155413 */ "XVE ACTIVE VS\0"
   /* 155427 */ "XVE ATOMIC ACCESS COUNT\0"
   /* 155451 */ "XVE AVG IPC Rate\0"
   /* 155468 */ "XVE Active\0"
   /* 155479 */ "XVE BARRIER MESSAGE COUNT\0"
   /* 155505 */ "XVE BUSY\0"
   /* 155514 */ "XVE COMPUTE THREAD COUNT\0"
   /* 155539 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0\0"
   /* 155581 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1\0"
   /* 155623 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE10\0"
   /* 155666 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE11\0"
   /* 155709 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE12\0"
   /* 155752 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE13\0"
   /* 155795 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE14\0"
   /* 155838 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE15\0"
   /* 155881 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE16\0"
   /* 155924 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE17\0"
   /* 155967 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE18\0"
   /* 156010 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE19\0"
   /* 156053 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2\0"
   /* 156095 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE20\0"
   /* 156138 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE21\0"
   /* 156181 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE22\0"
   /* 156224 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE23\0"
   /* 156267 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE24\0"
   /* 156310 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE25\0"
   /* 156353 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE26\0"
   /* 156396 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE27\0"
   /* 156439 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE28\0"
   /* 156482 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE29\0"
   /* 156525 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3\0"
   /* 156567 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE30\0"
   /* 156610 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE31\0"
   /* 156653 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4\0"
   /* 156695 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5\0"
   /* 156737 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6\0"
   /* 156779 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7\0"
   /* 156821 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE8\0"
   /* 156863 */ "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE9\0"
   /* 156905 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE0\0"
   /* 156946 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE1\0"
   /* 156987 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE10\0"
   /* 157029 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE11\0"
   /* 157071 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE12\0"
   /* 157113 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE13\0"
   /* 157155 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE14\0"
   /* 157197 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE15\0"
   /* 157239 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE16\0"
   /* 157281 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE17\0"
   /* 157323 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE18\0"
   /* 157365 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE19\0"
   /* 157407 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE2\0"
   /* 157448 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE20\0"
   /* 157490 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE21\0"
   /* 157532 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE22\0"
   /* 157574 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE23\0"
   /* 157616 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE24\0"
   /* 157658 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE25\0"
   /* 157700 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE26\0"
   /* 157742 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE27\0"
   /* 157784 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE28\0"
   /* 157826 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE29\0"
   /* 157868 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE3\0"
   /* 157909 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE30\0"
   /* 157951 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE31\0"
   /* 157993 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE4\0"
   /* 158034 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE5\0"
   /* 158075 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE6\0"
   /* 158116 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE7\0"
   /* 158157 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE8\0"
   /* 158198 */ "XVE DATAPORT FENCE MESSAGE COUNT XECORE9\0"
   /* 158239 */ "XVE DATAPORT READ MESSAGE COUNT XECORE0\0"
   /* 158279 */ "XVE DATAPORT READ MESSAGE COUNT XECORE1\0"
   /* 158319 */ "XVE DATAPORT READ MESSAGE COUNT XECORE10\0"
   /* 158360 */ "XVE DATAPORT READ MESSAGE COUNT XECORE11\0"
   /* 158401 */ "XVE DATAPORT READ MESSAGE COUNT XECORE12\0"
   /* 158442 */ "XVE DATAPORT READ MESSAGE COUNT XECORE13\0"
   /* 158483 */ "XVE DATAPORT READ MESSAGE COUNT XECORE14\0"
   /* 158524 */ "XVE DATAPORT READ MESSAGE COUNT XECORE15\0"
   /* 158565 */ "XVE DATAPORT READ MESSAGE COUNT XECORE16\0"
   /* 158606 */ "XVE DATAPORT READ MESSAGE COUNT XECORE17\0"
   /* 158647 */ "XVE DATAPORT READ MESSAGE COUNT XECORE18\0"
   /* 158688 */ "XVE DATAPORT READ MESSAGE COUNT XECORE19\0"
   /* 158729 */ "XVE DATAPORT READ MESSAGE COUNT XECORE2\0"
   /* 158769 */ "XVE DATAPORT READ MESSAGE COUNT XECORE20\0"
   /* 158810 */ "XVE DATAPORT READ MESSAGE COUNT XECORE21\0"
   /* 158851 */ "XVE DATAPORT READ MESSAGE COUNT XECORE22\0"
   /* 158892 */ "XVE DATAPORT READ MESSAGE COUNT XECORE23\0"
   /* 158933 */ "XVE DATAPORT READ MESSAGE COUNT XECORE24\0"
   /* 158974 */ "XVE DATAPORT READ MESSAGE COUNT XECORE25\0"
   /* 159015 */ "XVE DATAPORT READ MESSAGE COUNT XECORE26\0"
   /* 159056 */ "XVE DATAPORT READ MESSAGE COUNT XECORE27\0"
   /* 159097 */ "XVE DATAPORT READ MESSAGE COUNT XECORE28\0"
   /* 159138 */ "XVE DATAPORT READ MESSAGE COUNT XECORE29\0"
   /* 159179 */ "XVE DATAPORT READ MESSAGE COUNT XECORE3\0"
   /* 159219 */ "XVE DATAPORT READ MESSAGE COUNT XECORE30\0"
   /* 159260 */ "XVE DATAPORT READ MESSAGE COUNT XECORE31\0"
   /* 159301 */ "XVE DATAPORT READ MESSAGE COUNT XECORE4\0"
   /* 159341 */ "XVE DATAPORT READ MESSAGE COUNT XECORE5\0"
   /* 159381 */ "XVE DATAPORT READ MESSAGE COUNT XECORE6\0"
   /* 159421 */ "XVE DATAPORT READ MESSAGE COUNT XECORE7\0"
   /* 159461 */ "XVE DATAPORT READ MESSAGE COUNT XECORE8\0"
   /* 159501 */ "XVE DATAPORT READ MESSAGE COUNT XECORE9\0"
   /* 159541 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE0\0"
   /* 159585 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE1\0"
   /* 159629 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE10\0"
   /* 159674 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE11\0"
   /* 159719 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE12\0"
   /* 159764 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE13\0"
   /* 159809 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE14\0"
   /* 159854 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE15\0"
   /* 159899 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE16\0"
   /* 159944 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE17\0"
   /* 159989 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE18\0"
   /* 160034 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE19\0"
   /* 160079 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE2\0"
   /* 160123 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE20\0"
   /* 160168 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE21\0"
   /* 160213 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE22\0"
   /* 160258 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE23\0"
   /* 160303 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE24\0"
   /* 160348 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE25\0"
   /* 160393 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE26\0"
   /* 160438 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE27\0"
   /* 160483 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE28\0"
   /* 160528 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE29\0"
   /* 160573 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE3\0"
   /* 160617 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE30\0"
   /* 160662 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE31\0"
   /* 160707 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE4\0"
   /* 160751 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE5\0"
   /* 160795 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE6\0"
   /* 160839 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE7\0"
   /* 160883 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE8\0"
   /* 160927 */ "XVE DATAPORT REGISTER REQUEST COUNT XECORE9\0"
   /* 160971 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE0\0"
   /* 161016 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE1\0"
   /* 161061 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE10\0"
   /* 161107 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE11\0"
   /* 161153 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE12\0"
   /* 161199 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE13\0"
   /* 161245 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE14\0"
   /* 161291 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE15\0"
   /* 161337 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE16\0"
   /* 161383 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE17\0"
   /* 161429 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE18\0"
   /* 161475 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE19\0"
   /* 161521 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE2\0"
   /* 161566 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE20\0"
   /* 161612 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE21\0"
   /* 161658 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE22\0"
   /* 161704 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE23\0"
   /* 161750 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE24\0"
   /* 161796 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE25\0"
   /* 161842 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE26\0"
   /* 161888 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE27\0"
   /* 161934 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE28\0"
   /* 161980 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE29\0"
   /* 162026 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE3\0"
   /* 162071 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE30\0"
   /* 162117 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE31\0"
   /* 162163 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE4\0"
   /* 162208 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE5\0"
   /* 162253 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE6\0"
   /* 162298 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE7\0"
   /* 162343 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE8\0"
   /* 162388 */ "XVE DATAPORT REGISTER RESPONSE COUNT XECORE9\0"
   /* 162433 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE0\0"
   /* 162474 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE1\0"
   /* 162515 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE10\0"
   /* 162557 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE11\0"
   /* 162599 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE12\0"
   /* 162641 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE13\0"
   /* 162683 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE14\0"
   /* 162725 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE15\0"
   /* 162767 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE16\0"
   /* 162809 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE17\0"
   /* 162851 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE18\0"
   /* 162893 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE19\0"
   /* 162935 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE2\0"
   /* 162976 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE20\0"
   /* 163018 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE21\0"
   /* 163060 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE22\0"
   /* 163102 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE23\0"
   /* 163144 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE24\0"
   /* 163186 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE25\0"
   /* 163228 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE26\0"
   /* 163270 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE27\0"
   /* 163312 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE28\0"
   /* 163354 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE29\0"
   /* 163396 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE3\0"
   /* 163437 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE30\0"
   /* 163479 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE31\0"
   /* 163521 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE4\0"
   /* 163562 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE5\0"
   /* 163603 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE6\0"
   /* 163644 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE7\0"
   /* 163685 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE8\0"
   /* 163726 */ "XVE DATAPORT WRITE MESSAGE COUNT XECORE9\0"
   /* 163767 */ "XVE FPU Pipe Active\0"
   /* 163787 */ "XVE INST EXECUTED ALU0 ALL\0"
   /* 163814 */ "XVE INST EXECUTED ALU0 ALL UTILIZATION\0"
   /* 163853 */ "XVE INST EXECUTED ALU0 ASYNC CS\0"
   /* 163885 */ "XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION\0"
   /* 163929 */ "XVE INST EXECUTED ALU0 CS\0"
   /* 163955 */ "XVE INST EXECUTED ALU0 CS UTILIZATION\0"
   /* 163993 */ "XVE INST EXECUTED ALU0 DS\0"
   /* 164019 */ "XVE INST EXECUTED ALU0 DS UTILIZATION\0"
   /* 164057 */ "XVE INST EXECUTED ALU0 FS\0"
   /* 164083 */ "XVE INST EXECUTED ALU0 FS UTILIZATION\0"
   /* 164121 */ "XVE INST EXECUTED ALU0 GS\0"
   /* 164147 */ "XVE INST EXECUTED ALU0 GS UTILIZATION\0"
   /* 164185 */ "XVE INST EXECUTED ALU0 HS\0"
   /* 164211 */ "XVE INST EXECUTED ALU0 HS UTILIZATION\0"
   /* 164249 */ "XVE INST EXECUTED ALU0 MS\0"
   /* 164275 */ "XVE INST EXECUTED ALU0 MS UTILIZATION\0"
   /* 164313 */ "XVE INST EXECUTED ALU0 RT AHS\0"
   /* 164343 */ "XVE INST EXECUTED ALU0 RT AHS UTILIZATION\0"
   /* 164385 */ "XVE INST EXECUTED ALU0 RT CHS\0"
   /* 164415 */ "XVE INST EXECUTED ALU0 RT CHS UTILIZATION\0"
   /* 164457 */ "XVE INST EXECUTED ALU0 RT MS\0"
   /* 164486 */ "XVE INST EXECUTED ALU0 RT MS UTILIZATION\0"
   /* 164527 */ "XVE INST EXECUTED ALU0 TS\0"
   /* 164553 */ "XVE INST EXECUTED ALU0 TS UTILIZATION\0"
   /* 164591 */ "XVE INST EXECUTED ALU0 VS\0"
   /* 164617 */ "XVE INST EXECUTED ALU0 VS UTILIZATION\0"
   /* 164655 */ "XVE INST EXECUTED ALU1 ALL\0"
   /* 164682 */ "XVE INST EXECUTED ALU1 ALL UTILIZATION\0"
   /* 164721 */ "XVE INST EXECUTED ALU1 ASYNC CS\0"
   /* 164753 */ "XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION\0"
   /* 164797 */ "XVE INST EXECUTED ALU1 CS\0"
   /* 164823 */ "XVE INST EXECUTED ALU1 CS UTILIZATION\0"
   /* 164861 */ "XVE INST EXECUTED ALU1 DS\0"
   /* 164887 */ "XVE INST EXECUTED ALU1 DS UTILIZATION\0"
   /* 164925 */ "XVE INST EXECUTED ALU1 FS\0"
   /* 164951 */ "XVE INST EXECUTED ALU1 FS UTILIZATION\0"
   /* 164989 */ "XVE INST EXECUTED ALU1 GS\0"
   /* 165015 */ "XVE INST EXECUTED ALU1 GS UTILIZATION\0"
   /* 165053 */ "XVE INST EXECUTED ALU1 HS\0"
   /* 165079 */ "XVE INST EXECUTED ALU1 HS UTILIZATION\0"
   /* 165117 */ "XVE INST EXECUTED ALU1 MS\0"
   /* 165143 */ "XVE INST EXECUTED ALU1 MS UTILIZATION\0"
   /* 165181 */ "XVE INST EXECUTED ALU1 RT AHS\0"
   /* 165211 */ "XVE INST EXECUTED ALU1 RT AHS UTILIZATION\0"
   /* 165253 */ "XVE INST EXECUTED ALU1 RT CHS\0"
   /* 165283 */ "XVE INST EXECUTED ALU1 RT CHS UTILIZATION\0"
   /* 165325 */ "XVE INST EXECUTED ALU1 RT MS\0"
   /* 165354 */ "XVE INST EXECUTED ALU1 RT MS UTILIZATION\0"
   /* 165395 */ "XVE INST EXECUTED ALU1 TS\0"
   /* 165421 */ "XVE INST EXECUTED ALU1 TS UTILIZATION\0"
   /* 165459 */ "XVE INST EXECUTED ALU1 VS\0"
   /* 165485 */ "XVE INST EXECUTED ALU1 VS UTILIZATION\0"
   /* 165523 */ "XVE INST EXECUTED CONTROL ALL\0"
   /* 165553 */ "XVE INST EXECUTED CONTROL ALL UTILIZATION\0"
   /* 165595 */ "XVE INST EXECUTED FP16\0"
   /* 165618 */ "XVE INST EXECUTED FP16 UTILIZATION\0"
   /* 165653 */ "XVE INST EXECUTED FP32\0"
   /* 165676 */ "XVE INST EXECUTED FP32 UTILIZATION\0"
   /* 165711 */ "XVE INST EXECUTED FP64\0"
   /* 165734 */ "XVE INST EXECUTED FP64 UTILIZATION\0"
   /* 165769 */ "XVE INST EXECUTED INT16\0"
   /* 165793 */ "XVE INST EXECUTED INT16 UTILIZATION\0"
   /* 165829 */ "XVE INST EXECUTED INT32\0"
   /* 165853 */ "XVE INST EXECUTED INT32 UTILIZATION\0"
   /* 165889 */ "XVE INST EXECUTED MATH\0"
   /* 165912 */ "XVE INST EXECUTED MATH UTILIZATION\0"
   /* 165947 */ "XVE INST EXECUTED SEND ALL\0"
   /* 165974 */ "XVE INST EXECUTED SEND ALL UTILIZATION\0"
   /* 166013 */ "XVE INST EXECUTED SEND ASYNC CS\0"
   /* 166045 */ "XVE INST EXECUTED SEND ASYNC CS UTILIZATION\0"
   /* 166089 */ "XVE INST EXECUTED SEND CS\0"
   /* 166115 */ "XVE INST EXECUTED SEND CS UTILIZATION\0"
   /* 166153 */ "XVE INST EXECUTED SEND DS\0"
   /* 166179 */ "XVE INST EXECUTED SEND DS UTILIZATION\0"
   /* 166217 */ "XVE INST EXECUTED SEND FS\0"
   /* 166243 */ "XVE INST EXECUTED SEND FS UTILIZATION\0"
   /* 166281 */ "XVE INST EXECUTED SEND GS\0"
   /* 166307 */ "XVE INST EXECUTED SEND GS UTILIZATION\0"
   /* 166345 */ "XVE INST EXECUTED SEND HS\0"
   /* 166371 */ "XVE INST EXECUTED SEND HS UTILIZATION\0"
   /* 166409 */ "XVE INST EXECUTED SEND MS\0"
   /* 166435 */ "XVE INST EXECUTED SEND MS UTILIZATION\0"
   /* 166473 */ "XVE INST EXECUTED SEND RT AHS\0"
   /* 166503 */ "XVE INST EXECUTED SEND RT AHS UTILIZATION\0"
   /* 166545 */ "XVE INST EXECUTED SEND RT CHS\0"
   /* 166575 */ "XVE INST EXECUTED SEND RT CHS UTILIZATION\0"
   /* 166617 */ "XVE INST EXECUTED SEND RT MS\0"
   /* 166646 */ "XVE INST EXECUTED SEND RT MS UTILIZATION\0"
   /* 166687 */ "XVE INST EXECUTED SEND TS\0"
   /* 166713 */ "XVE INST EXECUTED SEND TS UTILIZATION\0"
   /* 166751 */ "XVE INST EXECUTED SEND VS\0"
   /* 166777 */ "XVE INST EXECUTED SEND VS UTILIZATION\0"
   /* 166815 */ "XVE INST EXECUTED XMX ALL\0"
   /* 166841 */ "XVE INST EXECUTED XMX ALL UTILIZATION\0"
   /* 166879 */ "XVE INST EXECUTED XMX BF16\0"
   /* 166906 */ "XVE INST EXECUTED XMX BF16 UTILIZATION\0"
   /* 166945 */ "XVE INST EXECUTED XMX FP16\0"
   /* 166972 */ "XVE INST EXECUTED XMX FP16 UTILIZATION\0"
   /* 167011 */ "XVE INST EXECUTED XMX INT8\0"
   /* 167038 */ "XVE INST EXECUTED XMX INT8 UTILIZATION\0"
   /* 167077 */ "XVE INST ISSUED ALL XECORE0 XVE0\0"
   /* 167110 */ "XVE INST ISSUED ALL XECORE1 XVE0\0"
   /* 167143 */ "XVE INST ISSUED ALL XECORE10 XVE0\0"
   /* 167177 */ "XVE INST ISSUED ALL XECORE11 XVE0\0"
   /* 167211 */ "XVE INST ISSUED ALL XECORE12 XVE0\0"
   /* 167245 */ "XVE INST ISSUED ALL XECORE13 XVE0\0"
   /* 167279 */ "XVE INST ISSUED ALL XECORE14 XVE0\0"
   /* 167313 */ "XVE INST ISSUED ALL XECORE15 XVE0\0"
   /* 167347 */ "XVE INST ISSUED ALL XECORE16 XVE0\0"
   /* 167381 */ "XVE INST ISSUED ALL XECORE17 XVE0\0"
   /* 167415 */ "XVE INST ISSUED ALL XECORE18 XVE0\0"
   /* 167449 */ "XVE INST ISSUED ALL XECORE19 XVE0\0"
   /* 167483 */ "XVE INST ISSUED ALL XECORE2 XVE0\0"
   /* 167516 */ "XVE INST ISSUED ALL XECORE20 XVE0\0"
   /* 167550 */ "XVE INST ISSUED ALL XECORE21 XVE0\0"
   /* 167584 */ "XVE INST ISSUED ALL XECORE22 XVE0\0"
   /* 167618 */ "XVE INST ISSUED ALL XECORE23 XVE0\0"
   /* 167652 */ "XVE INST ISSUED ALL XECORE24 XVE0\0"
   /* 167686 */ "XVE INST ISSUED ALL XECORE25 XVE0\0"
   /* 167720 */ "XVE INST ISSUED ALL XECORE26 XVE0\0"
   /* 167754 */ "XVE INST ISSUED ALL XECORE27 XVE0\0"
   /* 167788 */ "XVE INST ISSUED ALL XECORE28 XVE0\0"
   /* 167822 */ "XVE INST ISSUED ALL XECORE29 XVE0\0"
   /* 167856 */ "XVE INST ISSUED ALL XECORE3 XVE0\0"
   /* 167889 */ "XVE INST ISSUED ALL XECORE30 XVE0\0"
   /* 167923 */ "XVE INST ISSUED ALL XECORE31 XVE0\0"
   /* 167957 */ "XVE INST ISSUED ALL XECORE4 XVE0\0"
   /* 167990 */ "XVE INST ISSUED ALL XECORE5 XVE0\0"
   /* 168023 */ "XVE INST ISSUED ALL XECORE6 XVE0\0"
   /* 168056 */ "XVE INST ISSUED ALL XECORE7 XVE0\0"
   /* 168089 */ "XVE INST ISSUED ALL XECORE8 XVE0\0"
   /* 168122 */ "XVE INST ISSUED ALL XECORE9 XVE0\0"
   /* 168155 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0\0"
   /* 168205 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1\0"
   /* 168255 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE10\0"
   /* 168306 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE11\0"
   /* 168357 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE12\0"
   /* 168408 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE13\0"
   /* 168459 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE14\0"
   /* 168510 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE15\0"
   /* 168561 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE16\0"
   /* 168612 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE17\0"
   /* 168663 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE18\0"
   /* 168714 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE19\0"
   /* 168765 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2\0"
   /* 168815 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE20\0"
   /* 168866 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE21\0"
   /* 168917 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE22\0"
   /* 168968 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE23\0"
   /* 169019 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE24\0"
   /* 169070 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE25\0"
   /* 169121 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE26\0"
   /* 169172 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE27\0"
   /* 169223 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE28\0"
   /* 169274 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE29\0"
   /* 169325 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3\0"
   /* 169375 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE30\0"
   /* 169426 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE31\0"
   /* 169477 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4\0"
   /* 169527 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5\0"
   /* 169577 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6\0"
   /* 169627 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7\0"
   /* 169677 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE8\0"
   /* 169727 */ "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE9\0"
   /* 169777 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0\0"
   /* 169826 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1\0"
   /* 169875 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE10\0"
   /* 169925 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE11\0"
   /* 169975 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE12\0"
   /* 170025 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE13\0"
   /* 170075 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE14\0"
   /* 170125 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE15\0"
   /* 170175 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE16\0"
   /* 170225 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE17\0"
   /* 170275 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE18\0"
   /* 170325 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE19\0"
   /* 170375 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2\0"
   /* 170424 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE20\0"
   /* 170474 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE21\0"
   /* 170524 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE22\0"
   /* 170574 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE23\0"
   /* 170624 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE24\0"
   /* 170674 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE25\0"
   /* 170724 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE26\0"
   /* 170774 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE27\0"
   /* 170824 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE28\0"
   /* 170874 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE29\0"
   /* 170924 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3\0"
   /* 170973 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE30\0"
   /* 171023 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE31\0"
   /* 171073 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4\0"
   /* 171122 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5\0"
   /* 171171 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6\0"
   /* 171220 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7\0"
   /* 171269 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE8\0"
   /* 171318 */ "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE9\0"
   /* 171367 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0\0"
   /* 171415 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1\0"
   /* 171463 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE10\0"
   /* 171512 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE11\0"
   /* 171561 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE12\0"
   /* 171610 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE13\0"
   /* 171659 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE14\0"
   /* 171708 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE15\0"
   /* 171757 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE16\0"
   /* 171806 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE17\0"
   /* 171855 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE18\0"
   /* 171904 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE19\0"
   /* 171953 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2\0"
   /* 172001 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE20\0"
   /* 172050 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE21\0"
   /* 172099 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE22\0"
   /* 172148 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE23\0"
   /* 172197 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE24\0"
   /* 172246 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE25\0"
   /* 172295 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE26\0"
   /* 172344 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE27\0"
   /* 172393 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE28\0"
   /* 172442 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE29\0"
   /* 172491 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3\0"
   /* 172539 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE30\0"
   /* 172588 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE31\0"
   /* 172637 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4\0"
   /* 172685 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5\0"
   /* 172733 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6\0"
   /* 172781 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7\0"
   /* 172829 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE8\0"
   /* 172877 */ "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE9\0"
   /* 172925 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0\0"
   /* 172977 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1\0"
   /* 173029 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE10\0"
   /* 173082 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE11\0"
   /* 173135 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE12\0"
   /* 173188 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE13\0"
   /* 173241 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE14\0"
   /* 173294 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE15\0"
   /* 173347 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE16\0"
   /* 173400 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE17\0"
   /* 173453 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE18\0"
   /* 173506 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE19\0"
   /* 173559 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2\0"
   /* 173611 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE20\0"
   /* 173664 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE21\0"
   /* 173717 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE22\0"
   /* 173770 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE23\0"
   /* 173823 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE24\0"
   /* 173876 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE25\0"
   /* 173929 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE26\0"
   /* 173982 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE27\0"
   /* 174035 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE28\0"
   /* 174088 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE29\0"
   /* 174141 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3\0"
   /* 174193 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE30\0"
   /* 174246 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE31\0"
   /* 174299 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4\0"
   /* 174351 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5\0"
   /* 174403 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6\0"
   /* 174455 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7\0"
   /* 174507 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE8\0"
   /* 174559 */ "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE9\0"
   /* 174611 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0\0"
   /* 174664 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1\0"
   /* 174717 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE10\0"
   /* 174771 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE11\0"
   /* 174825 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE12\0"
   /* 174879 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE13\0"
   /* 174933 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE14\0"
   /* 174987 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE15\0"
   /* 175041 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE16\0"
   /* 175095 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE17\0"
   /* 175149 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE18\0"
   /* 175203 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE19\0"
   /* 175257 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2\0"
   /* 175310 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE20\0"
   /* 175364 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE21\0"
   /* 175418 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE22\0"
   /* 175472 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE23\0"
   /* 175526 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE24\0"
   /* 175580 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE25\0"
   /* 175634 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE26\0"
   /* 175688 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE27\0"
   /* 175742 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE28\0"
   /* 175796 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE29\0"
   /* 175850 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3\0"
   /* 175903 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE30\0"
   /* 175957 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE31\0"
   /* 176011 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4\0"
   /* 176064 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5\0"
   /* 176117 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6\0"
   /* 176170 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7\0"
   /* 176223 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE8\0"
   /* 176276 */ "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE9\0"
   /* 176329 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0\0"
   /* 176378 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1\0"
   /* 176427 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE10\0"
   /* 176477 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE11\0"
   /* 176527 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE12\0"
   /* 176577 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE13\0"
   /* 176627 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE14\0"
   /* 176677 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE15\0"
   /* 176727 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE16\0"
   /* 176777 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE17\0"
   /* 176827 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE18\0"
   /* 176877 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE19\0"
   /* 176927 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2\0"
   /* 176976 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE20\0"
   /* 177026 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE21\0"
   /* 177076 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE22\0"
   /* 177126 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE23\0"
   /* 177176 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE24\0"
   /* 177226 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE25\0"
   /* 177276 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE26\0"
   /* 177326 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE27\0"
   /* 177376 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE28\0"
   /* 177426 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE29\0"
   /* 177476 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3\0"
   /* 177525 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE30\0"
   /* 177575 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE31\0"
   /* 177625 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4\0"
   /* 177674 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5\0"
   /* 177723 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6\0"
   /* 177772 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7\0"
   /* 177821 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE8\0"
   /* 177870 */ "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE9\0"
   /* 177919 */ "XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0\0"
   /* 177957 */ "XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0\0"
   /* 177995 */ "XVE MULTIPLE PIPE ACTIVE XECORE10 XVE0\0"
   /* 178034 */ "XVE MULTIPLE PIPE ACTIVE XECORE11 XVE0\0"
   /* 178073 */ "XVE MULTIPLE PIPE ACTIVE XECORE12 XVE0\0"
   /* 178112 */ "XVE MULTIPLE PIPE ACTIVE XECORE13 XVE0\0"
   /* 178151 */ "XVE MULTIPLE PIPE ACTIVE XECORE14 XVE0\0"
   /* 178190 */ "XVE MULTIPLE PIPE ACTIVE XECORE15 XVE0\0"
   /* 178229 */ "XVE MULTIPLE PIPE ACTIVE XECORE16 XVE0\0"
   /* 178268 */ "XVE MULTIPLE PIPE ACTIVE XECORE17 XVE0\0"
   /* 178307 */ "XVE MULTIPLE PIPE ACTIVE XECORE18 XVE0\0"
   /* 178346 */ "XVE MULTIPLE PIPE ACTIVE XECORE19 XVE0\0"
   /* 178385 */ "XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0\0"
   /* 178423 */ "XVE MULTIPLE PIPE ACTIVE XECORE20 XVE0\0"
   /* 178462 */ "XVE MULTIPLE PIPE ACTIVE XECORE21 XVE0\0"
   /* 178501 */ "XVE MULTIPLE PIPE ACTIVE XECORE22 XVE0\0"
   /* 178540 */ "XVE MULTIPLE PIPE ACTIVE XECORE23 XVE0\0"
   /* 178579 */ "XVE MULTIPLE PIPE ACTIVE XECORE24 XVE0\0"
   /* 178618 */ "XVE MULTIPLE PIPE ACTIVE XECORE25 XVE0\0"
   /* 178657 */ "XVE MULTIPLE PIPE ACTIVE XECORE26 XVE0\0"
   /* 178696 */ "XVE MULTIPLE PIPE ACTIVE XECORE27 XVE0\0"
   /* 178735 */ "XVE MULTIPLE PIPE ACTIVE XECORE28 XVE0\0"
   /* 178774 */ "XVE MULTIPLE PIPE ACTIVE XECORE29 XVE0\0"
   /* 178813 */ "XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0\0"
   /* 178851 */ "XVE MULTIPLE PIPE ACTIVE XECORE30 XVE0\0"
   /* 178890 */ "XVE MULTIPLE PIPE ACTIVE XECORE31 XVE0\0"
   /* 178929 */ "XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0\0"
   /* 178967 */ "XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0\0"
   /* 179005 */ "XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0\0"
   /* 179043 */ "XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0\0"
   /* 179081 */ "XVE MULTIPLE PIPE ACTIVE XECORE8 XVE0\0"
   /* 179119 */ "XVE MULTIPLE PIPE ACTIVE XECORE9 XVE0\0"
   /* 179157 */ "XVE PIPE ALU0 AND ALU1 ACTIVE\0"
   /* 179187 */ "XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES\0"
   /* 179224 */ "XVE PIPE ALU0 AND XMX ACTIVE\0"
   /* 179253 */ "XVE PIPE ALU0 AND XMX ACTIVE CYCLES\0"
   /* 179289 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0\0"
   /* 179342 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0\0"
   /* 179395 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE10 XVE0 THREAD0\0"
   /* 179449 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE11 XVE0 THREAD0\0"
   /* 179503 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE12 XVE0 THREAD0\0"
   /* 179557 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE13 XVE0 THREAD0\0"
   /* 179611 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE14 XVE0 THREAD0\0"
   /* 179665 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE15 XVE0 THREAD0\0"
   /* 179719 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE16 XVE0 THREAD0\0"
   /* 179773 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE17 XVE0 THREAD0\0"
   /* 179827 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE18 XVE0 THREAD0\0"
   /* 179881 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE19 XVE0 THREAD0\0"
   /* 179935 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0\0"
   /* 179988 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE20 XVE0 THREAD0\0"
   /* 180042 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE21 XVE0 THREAD0\0"
   /* 180096 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE22 XVE0 THREAD0\0"
   /* 180150 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE23 XVE0 THREAD0\0"
   /* 180204 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE24 XVE0 THREAD0\0"
   /* 180258 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE25 XVE0 THREAD0\0"
   /* 180312 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE26 XVE0 THREAD0\0"
   /* 180366 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE27 XVE0 THREAD0\0"
   /* 180420 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE28 XVE0 THREAD0\0"
   /* 180474 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE29 XVE0 THREAD0\0"
   /* 180528 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0\0"
   /* 180581 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE30 XVE0 THREAD0\0"
   /* 180635 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE31 XVE0 THREAD0\0"
   /* 180689 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0\0"
   /* 180742 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0\0"
   /* 180795 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0\0"
   /* 180848 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0\0"
   /* 180901 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE8 XVE0 THREAD0\0"
   /* 180954 */ "XVE SHARED FUNCTION ACCESS HOLD XECORE9 XVE0 THREAD0\0"
   /* 181007 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE0\0"
   /* 181044 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE1\0"
   /* 181081 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE10\0"
   /* 181119 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE11\0"
   /* 181157 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE12\0"
   /* 181195 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE13\0"
   /* 181233 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE14\0"
   /* 181271 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE15\0"
   /* 181309 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE16\0"
   /* 181347 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE17\0"
   /* 181385 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE18\0"
   /* 181423 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE19\0"
   /* 181461 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE2\0"
   /* 181498 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE20\0"
   /* 181536 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE21\0"
   /* 181574 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE22\0"
   /* 181612 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE23\0"
   /* 181650 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE24\0"
   /* 181688 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE25\0"
   /* 181726 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE26\0"
   /* 181764 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE27\0"
   /* 181802 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE28\0"
   /* 181840 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE29\0"
   /* 181878 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE3\0"
   /* 181915 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE30\0"
   /* 181953 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE31\0"
   /* 181991 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE4\0"
   /* 182028 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE5\0"
   /* 182065 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE6\0"
   /* 182102 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE7\0"
   /* 182139 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE8\0"
   /* 182176 */ "XVE SLM ATOMIC MESSAGE COUNT XECORE9\0"
   /* 182213 */ "XVE SLM FENCE MESSAGE COUNT XECORE0\0"
   /* 182249 */ "XVE SLM FENCE MESSAGE COUNT XECORE1\0"
   /* 182285 */ "XVE SLM FENCE MESSAGE COUNT XECORE10\0"
   /* 182322 */ "XVE SLM FENCE MESSAGE COUNT XECORE11\0"
   /* 182359 */ "XVE SLM FENCE MESSAGE COUNT XECORE12\0"
   /* 182396 */ "XVE SLM FENCE MESSAGE COUNT XECORE13\0"
   /* 182433 */ "XVE SLM FENCE MESSAGE COUNT XECORE14\0"
   /* 182470 */ "XVE SLM FENCE MESSAGE COUNT XECORE15\0"
   /* 182507 */ "XVE SLM FENCE MESSAGE COUNT XECORE16\0"
   /* 182544 */ "XVE SLM FENCE MESSAGE COUNT XECORE17\0"
   /* 182581 */ "XVE SLM FENCE MESSAGE COUNT XECORE18\0"
   /* 182618 */ "XVE SLM FENCE MESSAGE COUNT XECORE19\0"
   /* 182655 */ "XVE SLM FENCE MESSAGE COUNT XECORE2\0"
   /* 182691 */ "XVE SLM FENCE MESSAGE COUNT XECORE20\0"
   /* 182728 */ "XVE SLM FENCE MESSAGE COUNT XECORE21\0"
   /* 182765 */ "XVE SLM FENCE MESSAGE COUNT XECORE22\0"
   /* 182802 */ "XVE SLM FENCE MESSAGE COUNT XECORE23\0"
   /* 182839 */ "XVE SLM FENCE MESSAGE COUNT XECORE24\0"
   /* 182876 */ "XVE SLM FENCE MESSAGE COUNT XECORE25\0"
   /* 182913 */ "XVE SLM FENCE MESSAGE COUNT XECORE26\0"
   /* 182950 */ "XVE SLM FENCE MESSAGE COUNT XECORE27\0"
   /* 182987 */ "XVE SLM FENCE MESSAGE COUNT XECORE28\0"
   /* 183024 */ "XVE SLM FENCE MESSAGE COUNT XECORE29\0"
   /* 183061 */ "XVE SLM FENCE MESSAGE COUNT XECORE3\0"
   /* 183097 */ "XVE SLM FENCE MESSAGE COUNT XECORE30\0"
   /* 183134 */ "XVE SLM FENCE MESSAGE COUNT XECORE31\0"
   /* 183171 */ "XVE SLM FENCE MESSAGE COUNT XECORE4\0"
   /* 183207 */ "XVE SLM FENCE MESSAGE COUNT XECORE5\0"
   /* 183243 */ "XVE SLM FENCE MESSAGE COUNT XECORE6\0"
   /* 183279 */ "XVE SLM FENCE MESSAGE COUNT XECORE7\0"
   /* 183315 */ "XVE SLM FENCE MESSAGE COUNT XECORE8\0"
   /* 183351 */ "XVE SLM FENCE MESSAGE COUNT XECORE9\0"
   /* 183387 */ "XVE SLM READ MESSAGE COUNT XECORE0\0"
   /* 183422 */ "XVE SLM READ MESSAGE COUNT XECORE1\0"
   /* 183457 */ "XVE SLM READ MESSAGE COUNT XECORE10\0"
   /* 183493 */ "XVE SLM READ MESSAGE COUNT XECORE11\0"
   /* 183529 */ "XVE SLM READ MESSAGE COUNT XECORE12\0"
   /* 183565 */ "XVE SLM READ MESSAGE COUNT XECORE13\0"
   /* 183601 */ "XVE SLM READ MESSAGE COUNT XECORE14\0"
   /* 183637 */ "XVE SLM READ MESSAGE COUNT XECORE15\0"
   /* 183673 */ "XVE SLM READ MESSAGE COUNT XECORE16\0"
   /* 183709 */ "XVE SLM READ MESSAGE COUNT XECORE17\0"
   /* 183745 */ "XVE SLM READ MESSAGE COUNT XECORE18\0"
   /* 183781 */ "XVE SLM READ MESSAGE COUNT XECORE19\0"
   /* 183817 */ "XVE SLM READ MESSAGE COUNT XECORE2\0"
   /* 183852 */ "XVE SLM READ MESSAGE COUNT XECORE20\0"
   /* 183888 */ "XVE SLM READ MESSAGE COUNT XECORE21\0"
   /* 183924 */ "XVE SLM READ MESSAGE COUNT XECORE22\0"
   /* 183960 */ "XVE SLM READ MESSAGE COUNT XECORE23\0"
   /* 183996 */ "XVE SLM READ MESSAGE COUNT XECORE24\0"
   /* 184032 */ "XVE SLM READ MESSAGE COUNT XECORE25\0"
   /* 184068 */ "XVE SLM READ MESSAGE COUNT XECORE26\0"
   /* 184104 */ "XVE SLM READ MESSAGE COUNT XECORE27\0"
   /* 184140 */ "XVE SLM READ MESSAGE COUNT XECORE28\0"
   /* 184176 */ "XVE SLM READ MESSAGE COUNT XECORE29\0"
   /* 184212 */ "XVE SLM READ MESSAGE COUNT XECORE3\0"
   /* 184247 */ "XVE SLM READ MESSAGE COUNT XECORE30\0"
   /* 184283 */ "XVE SLM READ MESSAGE COUNT XECORE31\0"
   /* 184319 */ "XVE SLM READ MESSAGE COUNT XECORE4\0"
   /* 184354 */ "XVE SLM READ MESSAGE COUNT XECORE5\0"
   /* 184389 */ "XVE SLM READ MESSAGE COUNT XECORE6\0"
   /* 184424 */ "XVE SLM READ MESSAGE COUNT XECORE7\0"
   /* 184459 */ "XVE SLM READ MESSAGE COUNT XECORE8\0"
   /* 184494 */ "XVE SLM READ MESSAGE COUNT XECORE9\0"
   /* 184529 */ "XVE SLM WRITE MESSAGE COUNT XECORE0\0"
   /* 184565 */ "XVE SLM WRITE MESSAGE COUNT XECORE1\0"
   /* 184601 */ "XVE SLM WRITE MESSAGE COUNT XECORE10\0"
   /* 184638 */ "XVE SLM WRITE MESSAGE COUNT XECORE11\0"
   /* 184675 */ "XVE SLM WRITE MESSAGE COUNT XECORE12\0"
   /* 184712 */ "XVE SLM WRITE MESSAGE COUNT XECORE13\0"
   /* 184749 */ "XVE SLM WRITE MESSAGE COUNT XECORE14\0"
   /* 184786 */ "XVE SLM WRITE MESSAGE COUNT XECORE15\0"
   /* 184823 */ "XVE SLM WRITE MESSAGE COUNT XECORE16\0"
   /* 184860 */ "XVE SLM WRITE MESSAGE COUNT XECORE17\0"
   /* 184897 */ "XVE SLM WRITE MESSAGE COUNT XECORE18\0"
   /* 184934 */ "XVE SLM WRITE MESSAGE COUNT XECORE19\0"
   /* 184971 */ "XVE SLM WRITE MESSAGE COUNT XECORE2\0"
   /* 185007 */ "XVE SLM WRITE MESSAGE COUNT XECORE20\0"
   /* 185044 */ "XVE SLM WRITE MESSAGE COUNT XECORE21\0"
   /* 185081 */ "XVE SLM WRITE MESSAGE COUNT XECORE22\0"
   /* 185118 */ "XVE SLM WRITE MESSAGE COUNT XECORE23\0"
   /* 185155 */ "XVE SLM WRITE MESSAGE COUNT XECORE24\0"
   /* 185192 */ "XVE SLM WRITE MESSAGE COUNT XECORE25\0"
   /* 185229 */ "XVE SLM WRITE MESSAGE COUNT XECORE26\0"
   /* 185266 */ "XVE SLM WRITE MESSAGE COUNT XECORE27\0"
   /* 185303 */ "XVE SLM WRITE MESSAGE COUNT XECORE28\0"
   /* 185340 */ "XVE SLM WRITE MESSAGE COUNT XECORE29\0"
   /* 185377 */ "XVE SLM WRITE MESSAGE COUNT XECORE3\0"
   /* 185413 */ "XVE SLM WRITE MESSAGE COUNT XECORE30\0"
   /* 185450 */ "XVE SLM WRITE MESSAGE COUNT XECORE31\0"
   /* 185487 */ "XVE SLM WRITE MESSAGE COUNT XECORE4\0"
   /* 185523 */ "XVE SLM WRITE MESSAGE COUNT XECORE5\0"
   /* 185559 */ "XVE SLM WRITE MESSAGE COUNT XECORE6\0"
   /* 185595 */ "XVE SLM WRITE MESSAGE COUNT XECORE7\0"
   /* 185631 */ "XVE SLM WRITE MESSAGE COUNT XECORE8\0"
   /* 185667 */ "XVE SLM WRITE MESSAGE COUNT XECORE9\0"
   /* 185703 */ "XVE STALL\0"
   /* 185713 */ "XVE STALL ALUWR XECORE0 XVE0 THREAD0\0"
   /* 185750 */ "XVE STALL ALUWR XECORE1 XVE0 THREAD0\0"
   /* 185787 */ "XVE STALL ALUWR XECORE10 XVE0 THREAD0\0"
   /* 185825 */ "XVE STALL ALUWR XECORE11 XVE0 THREAD0\0"
   /* 185863 */ "XVE STALL ALUWR XECORE12 XVE0 THREAD0\0"
   /* 185901 */ "XVE STALL ALUWR XECORE13 XVE0 THREAD0\0"
   /* 185939 */ "XVE STALL ALUWR XECORE14 XVE0 THREAD0\0"
   /* 185977 */ "XVE STALL ALUWR XECORE15 XVE0 THREAD0\0"
   /* 186015 */ "XVE STALL ALUWR XECORE16 XVE0 THREAD0\0"
   /* 186053 */ "XVE STALL ALUWR XECORE17 XVE0 THREAD0\0"
   /* 186091 */ "XVE STALL ALUWR XECORE18 XVE0 THREAD0\0"
   /* 186129 */ "XVE STALL ALUWR XECORE19 XVE0 THREAD0\0"
   /* 186167 */ "XVE STALL ALUWR XECORE2 XVE0 THREAD0\0"
   /* 186204 */ "XVE STALL ALUWR XECORE20 XVE0 THREAD0\0"
   /* 186242 */ "XVE STALL ALUWR XECORE21 XVE0 THREAD0\0"
   /* 186280 */ "XVE STALL ALUWR XECORE22 XVE0 THREAD0\0"
   /* 186318 */ "XVE STALL ALUWR XECORE23 XVE0 THREAD0\0"
   /* 186356 */ "XVE STALL ALUWR XECORE24 XVE0 THREAD0\0"
   /* 186394 */ "XVE STALL ALUWR XECORE25 XVE0 THREAD0\0"
   /* 186432 */ "XVE STALL ALUWR XECORE26 XVE0 THREAD0\0"
   /* 186470 */ "XVE STALL ALUWR XECORE27 XVE0 THREAD0\0"
   /* 186508 */ "XVE STALL ALUWR XECORE28 XVE0 THREAD0\0"
   /* 186546 */ "XVE STALL ALUWR XECORE29 XVE0 THREAD0\0"
   /* 186584 */ "XVE STALL ALUWR XECORE3 XVE0 THREAD0\0"
   /* 186621 */ "XVE STALL ALUWR XECORE30 XVE0 THREAD0\0"
   /* 186659 */ "XVE STALL ALUWR XECORE31 XVE0 THREAD0\0"
   /* 186697 */ "XVE STALL ALUWR XECORE4 XVE0 THREAD0\0"
   /* 186734 */ "XVE STALL ALUWR XECORE5 XVE0 THREAD0\0"
   /* 186771 */ "XVE STALL ALUWR XECORE6 XVE0 THREAD0\0"
   /* 186808 */ "XVE STALL ALUWR XECORE7 XVE0 THREAD0\0"
   /* 186845 */ "XVE STALL ALUWR XECORE8 XVE0 THREAD0\0"
   /* 186882 */ "XVE STALL ALUWR XECORE9 XVE0 THREAD0\0"
   /* 186919 */ "XVE STALL ASYNC CS\0"
   /* 186938 */ "XVE STALL BARRIER XECORE0 XVE0 THREAD0\0"
   /* 186977 */ "XVE STALL BARRIER XECORE1 XVE0 THREAD0\0"
   /* 187016 */ "XVE STALL BARRIER XECORE10 XVE0 THREAD0\0"
   /* 187056 */ "XVE STALL BARRIER XECORE11 XVE0 THREAD0\0"
   /* 187096 */ "XVE STALL BARRIER XECORE12 XVE0 THREAD0\0"
   /* 187136 */ "XVE STALL BARRIER XECORE13 XVE0 THREAD0\0"
   /* 187176 */ "XVE STALL BARRIER XECORE14 XVE0 THREAD0\0"
   /* 187216 */ "XVE STALL BARRIER XECORE15 XVE0 THREAD0\0"
   /* 187256 */ "XVE STALL BARRIER XECORE16 XVE0 THREAD0\0"
   /* 187296 */ "XVE STALL BARRIER XECORE17 XVE0 THREAD0\0"
   /* 187336 */ "XVE STALL BARRIER XECORE18 XVE0 THREAD0\0"
   /* 187376 */ "XVE STALL BARRIER XECORE19 XVE0 THREAD0\0"
   /* 187416 */ "XVE STALL BARRIER XECORE2 XVE0 THREAD0\0"
   /* 187455 */ "XVE STALL BARRIER XECORE20 XVE0 THREAD0\0"
   /* 187495 */ "XVE STALL BARRIER XECORE21 XVE0 THREAD0\0"
   /* 187535 */ "XVE STALL BARRIER XECORE22 XVE0 THREAD0\0"
   /* 187575 */ "XVE STALL BARRIER XECORE23 XVE0 THREAD0\0"
   /* 187615 */ "XVE STALL BARRIER XECORE24 XVE0 THREAD0\0"
   /* 187655 */ "XVE STALL BARRIER XECORE25 XVE0 THREAD0\0"
   /* 187695 */ "XVE STALL BARRIER XECORE26 XVE0 THREAD0\0"
   /* 187735 */ "XVE STALL BARRIER XECORE27 XVE0 THREAD0\0"
   /* 187775 */ "XVE STALL BARRIER XECORE28 XVE0 THREAD0\0"
   /* 187815 */ "XVE STALL BARRIER XECORE29 XVE0 THREAD0\0"
   /* 187855 */ "XVE STALL BARRIER XECORE3 XVE0 THREAD0\0"
   /* 187894 */ "XVE STALL BARRIER XECORE30 XVE0 THREAD0\0"
   /* 187934 */ "XVE STALL BARRIER XECORE31 XVE0 THREAD0\0"
   /* 187974 */ "XVE STALL BARRIER XECORE4 XVE0 THREAD0\0"
   /* 188013 */ "XVE STALL BARRIER XECORE5 XVE0 THREAD0\0"
   /* 188052 */ "XVE STALL BARRIER XECORE6 XVE0 THREAD0\0"
   /* 188091 */ "XVE STALL BARRIER XECORE7 XVE0 THREAD0\0"
   /* 188130 */ "XVE STALL BARRIER XECORE8 XVE0 THREAD0\0"
   /* 188169 */ "XVE STALL BARRIER XECORE9 XVE0 THREAD0\0"
   /* 188208 */ "XVE STALL CONTROL XECORE0 XVE0 THREAD0\0"
   /* 188247 */ "XVE STALL CONTROL XECORE1 XVE0 THREAD0\0"
   /* 188286 */ "XVE STALL CONTROL XECORE2 XVE0 THREAD0\0"
   /* 188325 */ "XVE STALL CONTROL XECORE3 XVE0 THREAD0\0"
   /* 188364 */ "XVE STALL CONTROL XECORE4 XVE0 THREAD0\0"
   /* 188403 */ "XVE STALL CONTROL XECORE5 XVE0 THREAD0\0"
   /* 188442 */ "XVE STALL CONTROL XECORE6 XVE0 THREAD0\0"
   /* 188481 */ "XVE STALL CONTROL XECORE7 XVE0 THREAD0\0"
   /* 188520 */ "XVE STALL CS\0"
   /* 188533 */ "XVE STALL CYCLES\0"
   /* 188550 */ "XVE STALL CYCLES ASYNC CS\0"
   /* 188576 */ "XVE STALL CYCLES CS\0"
   /* 188596 */ "XVE STALL CYCLES DS\0"
   /* 188616 */ "XVE STALL CYCLES FS\0"
   /* 188636 */ "XVE STALL CYCLES GS\0"
   /* 188656 */ "XVE STALL CYCLES HS\0"
   /* 188676 */ "XVE STALL CYCLES MS\0"
   /* 188696 */ "XVE STALL CYCLES RT\0"
   /* 188716 */ "XVE STALL CYCLES TS\0"
   /* 188736 */ "XVE STALL CYCLES VS\0"
   /* 188756 */ "XVE STALL DS\0"
   /* 188769 */ "XVE STALL FS\0"
   /* 188782 */ "XVE STALL GS\0"
   /* 188795 */ "XVE STALL HS\0"
   /* 188808 */ "XVE STALL INSTFETCH XECORE0 XVE0 THREAD0\0"
   /* 188849 */ "XVE STALL INSTFETCH XECORE1 XVE0 THREAD0\0"
   /* 188890 */ "XVE STALL INSTFETCH XECORE10 XVE0 THREAD0\0"
   /* 188932 */ "XVE STALL INSTFETCH XECORE11 XVE0 THREAD0\0"
   /* 188974 */ "XVE STALL INSTFETCH XECORE12 XVE0 THREAD0\0"
   /* 189016 */ "XVE STALL INSTFETCH XECORE13 XVE0 THREAD0\0"
   /* 189058 */ "XVE STALL INSTFETCH XECORE14 XVE0 THREAD0\0"
   /* 189100 */ "XVE STALL INSTFETCH XECORE15 XVE0 THREAD0\0"
   /* 189142 */ "XVE STALL INSTFETCH XECORE16 XVE0 THREAD0\0"
   /* 189184 */ "XVE STALL INSTFETCH XECORE17 XVE0 THREAD0\0"
   /* 189226 */ "XVE STALL INSTFETCH XECORE18 XVE0 THREAD0\0"
   /* 189268 */ "XVE STALL INSTFETCH XECORE19 XVE0 THREAD0\0"
   /* 189310 */ "XVE STALL INSTFETCH XECORE2 XVE0 THREAD0\0"
   /* 189351 */ "XVE STALL INSTFETCH XECORE20 XVE0 THREAD0\0"
   /* 189393 */ "XVE STALL INSTFETCH XECORE21 XVE0 THREAD0\0"
   /* 189435 */ "XVE STALL INSTFETCH XECORE22 XVE0 THREAD0\0"
   /* 189477 */ "XVE STALL INSTFETCH XECORE23 XVE0 THREAD0\0"
   /* 189519 */ "XVE STALL INSTFETCH XECORE24 XVE0 THREAD0\0"
   /* 189561 */ "XVE STALL INSTFETCH XECORE25 XVE0 THREAD0\0"
   /* 189603 */ "XVE STALL INSTFETCH XECORE26 XVE0 THREAD0\0"
   /* 189645 */ "XVE STALL INSTFETCH XECORE27 XVE0 THREAD0\0"
   /* 189687 */ "XVE STALL INSTFETCH XECORE28 XVE0 THREAD0\0"
   /* 189729 */ "XVE STALL INSTFETCH XECORE29 XVE0 THREAD0\0"
   /* 189771 */ "XVE STALL INSTFETCH XECORE3 XVE0 THREAD0\0"
   /* 189812 */ "XVE STALL INSTFETCH XECORE30 XVE0 THREAD0\0"
   /* 189854 */ "XVE STALL INSTFETCH XECORE31 XVE0 THREAD0\0"
   /* 189896 */ "XVE STALL INSTFETCH XECORE4 XVE0 THREAD0\0"
   /* 189937 */ "XVE STALL INSTFETCH XECORE5 XVE0 THREAD0\0"
   /* 189978 */ "XVE STALL INSTFETCH XECORE6 XVE0 THREAD0\0"
   /* 190019 */ "XVE STALL INSTFETCH XECORE7 XVE0 THREAD0\0"
   /* 190060 */ "XVE STALL INSTFETCH XECORE8 XVE0 THREAD0\0"
   /* 190101 */ "XVE STALL INSTFETCH XECORE9 XVE0 THREAD0\0"
   /* 190142 */ "XVE STALL MS\0"
   /* 190155 */ "XVE STALL OTHER XECORE0 XVE0 THREAD0\0"
   /* 190192 */ "XVE STALL OTHER XECORE1 XVE0 THREAD0\0"
   /* 190229 */ "XVE STALL OTHER XECORE10 XVE0 THREAD0\0"
   /* 190267 */ "XVE STALL OTHER XECORE11 XVE0 THREAD0\0"
   /* 190305 */ "XVE STALL OTHER XECORE12 XVE0 THREAD0\0"
   /* 190343 */ "XVE STALL OTHER XECORE13 XVE0 THREAD0\0"
   /* 190381 */ "XVE STALL OTHER XECORE14 XVE0 THREAD0\0"
   /* 190419 */ "XVE STALL OTHER XECORE15 XVE0 THREAD0\0"
   /* 190457 */ "XVE STALL OTHER XECORE16 XVE0 THREAD0\0"
   /* 190495 */ "XVE STALL OTHER XECORE17 XVE0 THREAD0\0"
   /* 190533 */ "XVE STALL OTHER XECORE18 XVE0 THREAD0\0"
   /* 190571 */ "XVE STALL OTHER XECORE19 XVE0 THREAD0\0"
   /* 190609 */ "XVE STALL OTHER XECORE2 XVE0 THREAD0\0"
   /* 190646 */ "XVE STALL OTHER XECORE20 XVE0 THREAD0\0"
   /* 190684 */ "XVE STALL OTHER XECORE21 XVE0 THREAD0\0"
   /* 190722 */ "XVE STALL OTHER XECORE22 XVE0 THREAD0\0"
   /* 190760 */ "XVE STALL OTHER XECORE23 XVE0 THREAD0\0"
   /* 190798 */ "XVE STALL OTHER XECORE24 XVE0 THREAD0\0"
   /* 190836 */ "XVE STALL OTHER XECORE25 XVE0 THREAD0\0"
   /* 190874 */ "XVE STALL OTHER XECORE26 XVE0 THREAD0\0"
   /* 190912 */ "XVE STALL OTHER XECORE27 XVE0 THREAD0\0"
   /* 190950 */ "XVE STALL OTHER XECORE28 XVE0 THREAD0\0"
   /* 190988 */ "XVE STALL OTHER XECORE29 XVE0 THREAD0\0"
   /* 191026 */ "XVE STALL OTHER XECORE3 XVE0 THREAD0\0"
   /* 191063 */ "XVE STALL OTHER XECORE30 XVE0 THREAD0\0"
   /* 191101 */ "XVE STALL OTHER XECORE31 XVE0 THREAD0\0"
   /* 191139 */ "XVE STALL OTHER XECORE4 XVE0 THREAD0\0"
   /* 191176 */ "XVE STALL OTHER XECORE5 XVE0 THREAD0\0"
   /* 191213 */ "XVE STALL OTHER XECORE6 XVE0 THREAD0\0"
   /* 191250 */ "XVE STALL OTHER XECORE7 XVE0 THREAD0\0"
   /* 191287 */ "XVE STALL OTHER XECORE8 XVE0 THREAD0\0"
   /* 191324 */ "XVE STALL OTHER XECORE9 XVE0 THREAD0\0"
   /* 191361 */ "XVE STALL PIPESTALL XECORE0 XVE0\0"
   /* 191394 */ "XVE STALL PIPESTALL XECORE1 XVE0\0"
   /* 191427 */ "XVE STALL PIPESTALL XECORE2 XVE0\0"
   /* 191460 */ "XVE STALL PIPESTALL XECORE3 XVE0\0"
   /* 191493 */ "XVE STALL PIPESTALL XECORE4 XVE0\0"
   /* 191526 */ "XVE STALL PIPESTALL XECORE5 XVE0\0"
   /* 191559 */ "XVE STALL PIPESTALL XECORE6 XVE0\0"
   /* 191592 */ "XVE STALL PIPESTALL XECORE7 XVE0\0"
   /* 191625 */ "XVE STALL RT\0"
   /* 191638 */ "XVE STALL SBID XECORE0 XVE0 THREAD0\0"
   /* 191674 */ "XVE STALL SBID XECORE1 XVE0 THREAD0\0"
   /* 191710 */ "XVE STALL SBID XECORE10 XVE0 THREAD0\0"
   /* 191747 */ "XVE STALL SBID XECORE11 XVE0 THREAD0\0"
   /* 191784 */ "XVE STALL SBID XECORE12 XVE0 THREAD0\0"
   /* 191821 */ "XVE STALL SBID XECORE13 XVE0 THREAD0\0"
   /* 191858 */ "XVE STALL SBID XECORE14 XVE0 THREAD0\0"
   /* 191895 */ "XVE STALL SBID XECORE15 XVE0 THREAD0\0"
   /* 191932 */ "XVE STALL SBID XECORE16 XVE0 THREAD0\0"
   /* 191969 */ "XVE STALL SBID XECORE17 XVE0 THREAD0\0"
   /* 192006 */ "XVE STALL SBID XECORE18 XVE0 THREAD0\0"
   /* 192043 */ "XVE STALL SBID XECORE19 XVE0 THREAD0\0"
   /* 192080 */ "XVE STALL SBID XECORE2 XVE0 THREAD0\0"
   /* 192116 */ "XVE STALL SBID XECORE20 XVE0 THREAD0\0"
   /* 192153 */ "XVE STALL SBID XECORE21 XVE0 THREAD0\0"
   /* 192190 */ "XVE STALL SBID XECORE22 XVE0 THREAD0\0"
   /* 192227 */ "XVE STALL SBID XECORE23 XVE0 THREAD0\0"
   /* 192264 */ "XVE STALL SBID XECORE24 XVE0 THREAD0\0"
   /* 192301 */ "XVE STALL SBID XECORE25 XVE0 THREAD0\0"
   /* 192338 */ "XVE STALL SBID XECORE26 XVE0 THREAD0\0"
   /* 192375 */ "XVE STALL SBID XECORE27 XVE0 THREAD0\0"
   /* 192412 */ "XVE STALL SBID XECORE28 XVE0 THREAD0\0"
   /* 192449 */ "XVE STALL SBID XECORE29 XVE0 THREAD0\0"
   /* 192486 */ "XVE STALL SBID XECORE3 XVE0 THREAD0\0"
   /* 192522 */ "XVE STALL SBID XECORE30 XVE0 THREAD0\0"
   /* 192559 */ "XVE STALL SBID XECORE31 XVE0 THREAD0\0"
   /* 192596 */ "XVE STALL SBID XECORE4 XVE0 THREAD0\0"
   /* 192632 */ "XVE STALL SBID XECORE5 XVE0 THREAD0\0"
   /* 192668 */ "XVE STALL SBID XECORE6 XVE0 THREAD0\0"
   /* 192704 */ "XVE STALL SBID XECORE7 XVE0 THREAD0\0"
   /* 192740 */ "XVE STALL SBID XECORE8 XVE0 THREAD0\0"
   /* 192776 */ "XVE STALL SBID XECORE9 XVE0 THREAD0\0"
   /* 192812 */ "XVE STALL SENDWR XECORE0 XVE0 THREAD0\0"
   /* 192850 */ "XVE STALL SENDWR XECORE1 XVE0 THREAD0\0"
   /* 192888 */ "XVE STALL SENDWR XECORE10 XVE0 THREAD0\0"
   /* 192927 */ "XVE STALL SENDWR XECORE11 XVE0 THREAD0\0"
   /* 192966 */ "XVE STALL SENDWR XECORE12 XVE0 THREAD0\0"
   /* 193005 */ "XVE STALL SENDWR XECORE13 XVE0 THREAD0\0"
   /* 193044 */ "XVE STALL SENDWR XECORE14 XVE0 THREAD0\0"
   /* 193083 */ "XVE STALL SENDWR XECORE15 XVE0 THREAD0\0"
   /* 193122 */ "XVE STALL SENDWR XECORE16 XVE0 THREAD0\0"
   /* 193161 */ "XVE STALL SENDWR XECORE17 XVE0 THREAD0\0"
   /* 193200 */ "XVE STALL SENDWR XECORE18 XVE0 THREAD0\0"
   /* 193239 */ "XVE STALL SENDWR XECORE19 XVE0 THREAD0\0"
   /* 193278 */ "XVE STALL SENDWR XECORE2 XVE0 THREAD0\0"
   /* 193316 */ "XVE STALL SENDWR XECORE20 XVE0 THREAD0\0"
   /* 193355 */ "XVE STALL SENDWR XECORE21 XVE0 THREAD0\0"
   /* 193394 */ "XVE STALL SENDWR XECORE22 XVE0 THREAD0\0"
   /* 193433 */ "XVE STALL SENDWR XECORE23 XVE0 THREAD0\0"
   /* 193472 */ "XVE STALL SENDWR XECORE24 XVE0 THREAD0\0"
   /* 193511 */ "XVE STALL SENDWR XECORE25 XVE0 THREAD0\0"
   /* 193550 */ "XVE STALL SENDWR XECORE26 XVE0 THREAD0\0"
   /* 193589 */ "XVE STALL SENDWR XECORE27 XVE0 THREAD0\0"
   /* 193628 */ "XVE STALL SENDWR XECORE28 XVE0 THREAD0\0"
   /* 193667 */ "XVE STALL SENDWR XECORE29 XVE0 THREAD0\0"
   /* 193706 */ "XVE STALL SENDWR XECORE3 XVE0 THREAD0\0"
   /* 193744 */ "XVE STALL SENDWR XECORE30 XVE0 THREAD0\0"
   /* 193783 */ "XVE STALL SENDWR XECORE31 XVE0 THREAD0\0"
   /* 193822 */ "XVE STALL SENDWR XECORE4 XVE0 THREAD0\0"
   /* 193860 */ "XVE STALL SENDWR XECORE5 XVE0 THREAD0\0"
   /* 193898 */ "XVE STALL SENDWR XECORE6 XVE0 THREAD0\0"
   /* 193936 */ "XVE STALL SENDWR XECORE7 XVE0 THREAD0\0"
   /* 193974 */ "XVE STALL SENDWR XECORE8 XVE0 THREAD0\0"
   /* 194012 */ "XVE STALL SENDWR XECORE9 XVE0 THREAD0\0"
   /* 194050 */ "XVE STALL TS\0"
   /* 194063 */ "XVE STALL VS\0"
   /* 194076 */ "XVE Stall\0"
   /* 194086 */ "XVE THREADS OCCUPANCY ALL\0"
   /* 194112 */ "XVE THREADS OCCUPANCY CYCLES ALL\0"
   /* 194145 */ "XVE Thread Occupancy\0"
   /* 194166 */ "Z L3 ACCESS L3BANK0\0"
   /* 194186 */ "Z L3 ACCESS L3BANK1\0"
   /* 194206 */ "Z L3 ACCESS L3BANK2\0"
   /* 194226 */ "Z L3 ACCESS L3BANK3\0"
   /* 194246 */ "Z L3 ACCESS L3BANK4\0"
   /* 194266 */ "Z L3 ACCESS L3BANK5\0"
   /* 194286 */ "Z L3 ACCESS L3BANK6\0"
   /* 194306 */ "Z L3 ACCESS L3BANK7\0"
   /* 194326 */ "Z L3 HIT L3BANK0\0"
   /* 194343 */ "Z L3 HIT L3BANK1\0"
   /* 194360 */ "Z L3 HIT L3BANK10\0"
   /* 194378 */ "Z L3 HIT L3BANK11\0"
   /* 194396 */ "Z L3 HIT L3BANK12\0"
   /* 194414 */ "Z L3 HIT L3BANK13\0"
   /* 194432 */ "Z L3 HIT L3BANK14\0"
   /* 194450 */ "Z L3 HIT L3BANK15\0"
   /* 194468 */ "Z L3 HIT L3BANK16\0"
   /* 194486 */ "Z L3 HIT L3BANK17\0"
   /* 194504 */ "Z L3 HIT L3BANK18\0"
   /* 194522 */ "Z L3 HIT L3BANK19\0"
   /* 194540 */ "Z L3 HIT L3BANK2\0"
   /* 194557 */ "Z L3 HIT L3BANK20\0"
   /* 194575 */ "Z L3 HIT L3BANK21\0"
   /* 194593 */ "Z L3 HIT L3BANK22\0"
   /* 194611 */ "Z L3 HIT L3BANK23\0"
   /* 194629 */ "Z L3 HIT L3BANK24\0"
   /* 194647 */ "Z L3 HIT L3BANK25\0"
   /* 194665 */ "Z L3 HIT L3BANK26\0"
   /* 194683 */ "Z L3 HIT L3BANK27\0"
   /* 194701 */ "Z L3 HIT L3BANK28\0"
   /* 194719 */ "Z L3 HIT L3BANK29\0"
   /* 194737 */ "Z L3 HIT L3BANK3\0"
   /* 194754 */ "Z L3 HIT L3BANK30\0"
   /* 194772 */ "Z L3 HIT L3BANK31\0"
   /* 194790 */ "Z L3 HIT L3BANK4\0"
   /* 194807 */ "Z L3 HIT L3BANK5\0"
   /* 194824 */ "Z L3 HIT L3BANK6\0"
   /* 194841 */ "Z L3 HIT L3BANK7\0"
   /* 194858 */ "Z L3 HIT L3BANK8\0"
   /* 194875 */ "Z L3 HIT L3BANK9\0"
};

static const char desc[] = {
   /* 0 */ "Any XVE thread loaded. Unit: events.\0"
   /* 37 */ "Average EU bytes read per L3 cache line. \0"
   /* 79 */ "Average EU bytes written per L3 cache line. \0"
   /* 124 */ "Average GPU Core Frequency in the measurement. Unit: Hz.\0"
   /* 181 */ "Coalescing ratio of EU read requests to L3 cache lines. \0"
   /* 238 */ "Coalescing ratio of EU write requests to L3 cache lines. \0"
   /* 296 */ "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth Unit: gbps.\0"
   /* 368 */ "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth Unit: gbps.\0"
   /* 441 */ "HW test counter 0. Factor: 0.0 Unit: events.\0"
   /* 486 */ "HW test counter 1. Factor: 1.0 Unit: events.\0"
   /* 531 */ "HW test counter 2. Factor: 1.0 Unit: events.\0"
   /* 576 */ "HW test counter 3. Factor: 0.5 Unit: events.\0"
   /* 621 */ "HW test counter 4. Factor: 0.333 Unit: events.\0"
   /* 668 */ "HW test counter 4. Factor: 0.3333 Unit: events.\0"
   /* 716 */ "HW test counter 5. Factor: 0.333 Unit: events.\0"
   /* 763 */ "HW test counter 5. Factor: 0.3333 Unit: events.\0"
   /* 811 */ "HW test counter 6. Factor: 0.166 Unit: events.\0"
   /* 858 */ "HW test counter 6. Factor: 0.16666 Unit: events.\0"
   /* 907 */ "HW test counter 7. Factor: 0.666 Unit: events.\0"
   /* 954 */ "HW test counter 7. Factor: 0.6666 Unit: events.\0"
   /* 1002 */ "HW test counter 8. Should be equal to 1 in IOStream or in OAG query mode Unit: events.\0"
   /* 1089 */ "HW test counter 8. Should be equal to 1. Unit: events.\0"
   /* 1144 */ "HW test counter 9. Should be equal to 1 in query. Unit: events.\0"
   /* 1208 */ "Number of 2x2 pixels written to all render targets Unit: pixels.\0"
   /* 1273 */ "Number of 2x2 texel block requested from Sampler Unit: texels.\0"
   /* 1336 */ "Number of 2x2 that were lit from Rasterizer but failed the depth stencil test or alpha test Unit: pixels.\0"
   /* 1442 */ "Number of AMFS accesses to L3 Unit: events.\0"
   /* 1486 */ "Number of AMFS atomics to L3 Unit: events.\0"
   /* 1529 */ "Number of AMFS writes to L3 Unit: events.\0"
   /* 1571 */ "Number of Async GPGPU EOT messages received Unit: events.\0"
   /* 1629 */ "Number of Async GPGPU threadgroups dispatched Unit: events.\0"
   /* 1689 */ "Number of BVH cache misses for RayQuery only Unit: events.\0"
   /* 1748 */ "Number of BVH nodes processed Unit: events.\0"
   /* 1792 */ "Number of Clipper early cull primitives Unit: events.\0"
   /* 1846 */ "Number of Clipper input vertices Unit: events.\0"
   /* 1893 */ "Number of DRAW and MESH commands parsed on the 3D engine Unit: events.\0"
   /* 1964 */ "Number of DS thread dispatches Unit: events.\0"
   /* 2009 */ "Number of GPGPU threadgroups dispatched Unit: events.\0"
   /* 2063 */ "Number of GS thread dispatches Unit: events.\0"
   /* 2108 */ "Number of GTI memory reads Unit: events.\0"
   /* 2149 */ "Number of GTI memory reads from L3 caused by L3 Cache misses Unit: events.\0"
   /* 2224 */ "Number of GTI memory writes Unit: events.\0"
   /* 2266 */ "Number of GTI memory writes from L3 caused by L3 invalidations Unit: events.\0"
   /* 2343 */ "Number of HS thread dispatches Unit: events.\0"
   /* 2388 */ "Number of Instruction Cache Hits Unit: events.\0"
   /* 2435 */ "Number of Instruction Cache Misses Unit: events.\0"
   /* 2484 */ "Number of L3 accesses which hits in the L3 cache Unit: events.\0"
   /* 2547 */ "Number of L3 accesses which miss in the L3 cache Unit: events.\0"
   /* 2610 */ "Number of L3 hit requests resulting from Sampler local cache miss which hits in L3 Unit: events.\0"
   /* 2707 */ "Number of L3 hit requests resulting from sampler local cache miss which hits in L3 Unit: events.\0"
   /* 2804 */ "Number of L3 hits for requests coming from the Dataport Unit: events.\0"
   /* 2874 */ "Number of L3 read requests Unit: events.\0"
   /* 2915 */ "Number of L3 read requests coming from XVE Instruction Cache Unit: events.\0"
   /* 2990 */ "Number of L3 read requests coming from XVE via Dataport Unit: events.\0"
   /* 3060 */ "Number of L3 read requests resulting from Sampler local cache miss Unit: events.\0"
   /* 3141 */ "Number of L3 read requests resulting from Z local cache miss Unit: events.\0"
   /* 3216 */ "Number of L3 read requests resulting from Z local cache miss which hits in L3 Unit: events.\0"
   /* 3308 */ "Number of L3 read requests resulting from color local cache miss which hits in L3 Unit: events.\0"
   /* 3404 */ "Number of L3 read requests resulting from sampler local cache miss Unit: events.\0"
   /* 3485 */ "Number of L3 request resulting from color local cache miss Unit: events.\0"
   /* 3558 */ "Number of L3 write requests Unit: events.\0"
   /* 3600 */ "Number of L3 write requests coming from XVE via Dataport Unit: events.\0"
   /* 3671 */ "Number of Load Store Cache accesses Unit: events.\0"
   /* 3721 */ "Number of Load Store Cache accesses. Unit: events.\0"
   /* 3772 */ "Number of Load Store Cache banks accessed in a clock. Unit: events.\0"
   /* 3840 */ "Number of Load Store Cache hits Unit: events.\0"
   /* 3886 */ "Number of Load Store Cache hits. Unit: events.\0"
   /* 3933 */ "Number of PS thread dispatches Unit: events.\0"
   /* 3978 */ "Number of Ray Tracing Traversal input rays Unit: events.\0"
   /* 4035 */ "Number of Ray Tracing Traversal output rays Unit: events.\0"
   /* 4093 */ "Number of Render Cache allocations - cache miss signal for new allocation Unit: events.\0"
   /* 4181 */ "Number of Render Cache allocations Unit: events.\0"
   /* 4230 */ "Number of Render Cache hits Unit: events.\0"
   /* 4272 */ "Number of Render Cache reads Unit: events.\0"
   /* 4315 */ "Number of Render Cache writes Unit: events.\0"
   /* 4359 */ "Number of SLM accesses Unit: events.\0"
   /* 4396 */ "Number of SLM accesses resulting in a bank conflict Unit: events.\0"
   /* 4462 */ "Number of SLM accesses resulting in a bank conflict. Unit: events.\0"
   /* 4529 */ "Number of SLM accesses. Unit: events.\0"
   /* 4567 */ "Number of SLM atomic operations sent by XVEs Unit: events.\0"
   /* 4626 */ "Number of SLM fence operations sent by XVEs Unit: events.\0"
   /* 4684 */ "Number of SLM read messages sent by XVEs Unit: events.\0"
   /* 4739 */ "Number of SLM write messages sent by XVEs Unit: events.\0"
   /* 4795 */ "Number of Sampler L1 misses Unit: events.\0"
   /* 4837 */ "Number of Sampler L1 requests Unit: events.\0"
   /* 4881 */ "Number of Shading Request (evaluate) messages processed by AMFS Unit: events.\0"
   /* 4959 */ "Number of Stalling flushes at the top of the pipe Unit: events.\0"
   /* 5023 */ "Number of Task Shader EOT messages received Unit: events.\0"
   /* 5081 */ "Number of Task Shader threadgroups dispatched Unit: events.\0"
   /* 5141 */ "Number of URB reads Unit: events.\0"
   /* 5175 */ "Number of URB reads occurred from cross slices Unit: events.\0"
   /* 5236 */ "Number of URB writes Unit: events.\0"
   /* 5271 */ "Number of VS thread dispatches Unit: events.\0"
   /* 5316 */ "Number of XVE instruction cache requests that hit the L3 Unit: events.\0"
   /* 5387 */ "Number of any hit threads dispatched for RayQuery only Unit: events.\0"
   /* 5456 */ "Number of atomic accesses to L3 Bank Unit: events.\0"
   /* 5507 */ "Number of atomic accesses to L3 bank Unit: events.\0"
   /* 5558 */ "Number of atomic messages sent by XVEs to the Dataport Unit: events.\0"
   /* 5627 */ "Number of atomic operations sent by XVEs to the Load Store Cache Unit: events.\0"
   /* 5706 */ "Number of blended 2x2 pixels written to all render targets Unit: pixels.\0"
   /* 5779 */ "Number of bytes read by host from GPU local (HBM) memory (downstream) Unit: bytes.\0"
   /* 5862 */ "Number of bytes read from L3 Unit: bytes.\0"
   /* 5904 */ "Number of bytes read from SLM Unit: bytes.\0"
   /* 5947 */ "Number of bytes read out of the Load Store Cache, excluding SLM accesses. Unit: bytes.\0"
   /* 6034 */ "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES Unit: bytes.\0"
   /* 6144 */ "Number of bytes read through the Dataport Unit: bytes.\0"
   /* 6199 */ "Number of bytes read through the Dataport Unit: events.\0"
   /* 6255 */ "Number of bytes written by host to GPU local (HBM) memory (downstream) Unit: bytes.\0"
   /* 6339 */ "Number of bytes written through the Dataport Unit: bytes.\0"
   /* 6397 */ "Number of bytes written to L3 Unit: bytes.\0"
   /* 6440 */ "Number of bytes written to SLM Unit: bytes.\0"
   /* 6484 */ "Number of bytes written to the Load Store Cache, excluding SLM accesses. Unit: bytes.\0"
   /* 6570 */ "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES Unit: bytes.\0"
   /* 6679 */ "Number of cache misses in AMFS Unit: events.\0"
   /* 6724 */ "Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit Unit: events.\0"
   /* 6830 */ "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit Unit: events.\0"
   /* 6937 */ "Number of cacheline read requests from the Load Store Cache to L3 Unit: events.\0"
   /* 7017 */ "Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses Unit: events.\0"
   /* 7130 */ "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses Unit: events.\0"
   /* 7244 */ "Number of cacheline write requests from the Load Store Cache to L3 Unit: events.\0"
   /* 7325 */ "Number of callable threads dispatched for RayQuery only Unit: events.\0"
   /* 7395 */ "Number of clocks spent dispatching GPGPU threads to XVEs Unit: events.\0"
   /* 7466 */ "Number of closest hit threads dispatched for RayQuery only Unit: events.\0"
   /* 7539 */ "Number of compute shader hardware threads dispatched Unit: threads.\0"
   /* 7607 */ "Number of compute walker commands parsed on the 3D engine Unit: events.\0"
   /* 7679 */ "Number of compute walker commands parsed on the compute engine Unit: events.\0"
   /* 7756 */ "Number of cycles ALU0 and XMX pipes are both actively executing a Gen ISA instruction Unit: events.\0"
   /* 7856 */ "Number of cycles any threads are loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 7954 */ "Number of cycles at least one pipe is active in XVE Unit: events.\0"
   /* 8020 */ "Number of cycles at least one pipe is active in XVE and there are Async Compute Shader threads loaded Unit: events.\0"
   /* 8136 */ "Number of cycles at least one pipe is active in XVE and there are Compute Shader (from Render Engine) threads loaded Unit: events.\0"
   /* 8267 */ "Number of cycles at least one pipe is active in XVE and there are Domain Shader threads loaded Unit: events.\0"
   /* 8376 */ "Number of cycles at least one pipe is active in XVE and there are Fragment Shader threads loaded Unit: events.\0"
   /* 8487 */ "Number of cycles at least one pipe is active in XVE and there are Geometry Shader threads loaded Unit: events.\0"
   /* 8598 */ "Number of cycles at least one pipe is active in XVE and there are Hull Shader threads loaded Unit: events.\0"
   /* 8705 */ "Number of cycles at least one pipe is active in XVE and there are Mesh Shader threads loaded Unit: events.\0"
   /* 8812 */ "Number of cycles at least one pipe is active in XVE and there are Ray Tracing Shader threads loaded Unit: events.\0"
   /* 8926 */ "Number of cycles at least one pipe is active in XVE and there are Task Shader threads loaded Unit: events.\0"
   /* 9033 */ "Number of cycles at least one pipe is active in XVE and there are Vertex Shader threads loaded Unit: events.\0"
   /* 9142 */ "Number of cycles in ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction Unit: events.\0"
   /* 9246 */ "Number of cycles there are Async Compute Shader threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 9367 */ "Number of cycles there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 9503 */ "Number of cycles there are Domain Shader threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 9617 */ "Number of cycles there are Fragment Shader threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 9733 */ "Number of cycles there are Geometry Shader threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 9849 */ "Number of cycles there are Hull Shader threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 9961 */ "Number of cycles there are Mesh Shader threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 10073 */ "Number of cycles there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 10192 */ "Number of cycles there are Task Shader threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 10304 */ "Number of cycles there are Vertex Shader threads loaded but not even a single pipe is active in XVE Unit: events.\0"
   /* 10418 */ "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes Unit: bytes.\0"
   /* 10497 */ "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes Unit: events.\0"
   /* 10577 */ "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B) Unit: events.\0"
   /* 10658 */ "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B) Unit: events.\0"
   /* 10739 */ "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes Unit: bytes.\0"
   /* 10819 */ "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes Unit: events.\0"
   /* 10900 */ "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B) Unit: events.\0"
   /* 10982 */ "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B) Unit: events.\0"
   /* 11064 */ "Number of elements pushed by Clipper into Stripsfan stage Unit: events.\0"
   /* 11136 */ "Number of execution slots taken by BF16 XMX instructions Unit: events.\0"
   /* 11207 */ "Number of execution slots taken by FP16 ALU instructions Unit: events.\0"
   /* 11278 */ "Number of execution slots taken by FP16 XMX instructions Unit: events.\0"
   /* 11349 */ "Number of execution slots taken by FP32 ALU instructions Unit: events.\0"
   /* 11420 */ "Number of execution slots taken by INT16 ALU instructions Unit: events.\0"
   /* 11492 */ "Number of execution slots taken by INT32 ALU instructions Unit: events.\0"
   /* 11564 */ "Number of execution slots taken by INT8 XMX instructions Unit: events.\0"
   /* 11635 */ "Number of execution slots taken by extended math instructions Unit: events.\0"
   /* 11711 */ "Number of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe Unit: events.\0"
   /* 11819 */ "Number of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe Unit: events.\0"
   /* 11927 */ "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe Unit: events.\0"
   /* 12033 */ "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe Unit: events.\0"
   /* 12139 */ "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe Unit: events.\0"
   /* 12249 */ "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe Unit: events.\0"
   /* 12359 */ "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe Unit: events.\0"
   /* 12462 */ "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe Unit: events.\0"
   /* 12565 */ "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe Unit: events.\0"
   /* 12688 */ "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe Unit: events.\0"
   /* 12811 */ "Number of execution slots taken by instructions executed by Domain Shader on ALU0 pipe Unit: events.\0"
   /* 12912 */ "Number of execution slots taken by instructions executed by Domain Shader on ALU1 pipe Unit: events.\0"
   /* 13013 */ "Number of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe Unit: events.\0"
   /* 13116 */ "Number of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe Unit: events.\0"
   /* 13219 */ "Number of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe Unit: events.\0"
   /* 13322 */ "Number of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe Unit: events.\0"
   /* 13425 */ "Number of execution slots taken by instructions executed by Hull Shader on ALU0 pipe Unit: events.\0"
   /* 13524 */ "Number of execution slots taken by instructions executed by Hull Shader on ALU1 pipe Unit: events.\0"
   /* 13623 */ "Number of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe Unit: events.\0"
   /* 13722 */ "Number of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe Unit: events.\0"
   /* 13821 */ "Number of execution slots taken by instructions executed by Task Shader on ALU0 pipe Unit: events.\0"
   /* 13920 */ "Number of execution slots taken by instructions executed by Task Shader on ALU1 pipe Unit: events.\0"
   /* 14019 */ "Number of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe Unit: events.\0"
   /* 14120 */ "Number of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe Unit: events.\0"
   /* 14221 */ "Number of execution slots taken by instructions executed in XMX pipe Unit: events.\0"
   /* 14304 */ "Number of execution slots taken by instructions executed on ALU0 pipe Unit: events.\0"
   /* 14388 */ "Number of execution slots taken by instructions executed on ALU1 pipe Unit: events.\0"
   /* 14472 */ "Number of fence messages sent by XVEs to the Dataport Unit: events.\0"
   /* 14540 */ "Number of fence messages sent by XVEs to the Load Store Cache Unit: events.\0"
   /* 14616 */ "Number of hits in the AMFS cache Unit: events.\0"
   /* 14663 */ "Number of host reads to GPU local (HBM) memory (downstream) Unit: events.\0"
   /* 14737 */ "Number of host writes to GPU local (HBM) memory (downstream) Unit: events.\0"
   /* 14812 */ "Number of instance BVH nodes processed by the traversal function Unit: events.\0"
   /* 14891 */ "Number of instructions executed by Async Compute Shader threads on SEND pipe Unit: events.\0"
   /* 14982 */ "Number of instructions executed by BTD Any Hit Shader threads on SEND pipe Unit: events.\0"
   /* 15071 */ "Number of instructions executed by BTD Closest Hit Shader threads on SEND pipe Unit: events.\0"
   /* 15164 */ "Number of instructions executed by BTD Miss Shader threads on SEND pipe Unit: events.\0"
   /* 15250 */ "Number of instructions executed by Compute Shader (from Render Engine) threads on SEND pipe Unit: events.\0"
   /* 15356 */ "Number of instructions executed by Domain Shader threads on SEND pipe Unit: events.\0"
   /* 15440 */ "Number of instructions executed by Fragment Shader threads on SEND pipe Unit: events.\0"
   /* 15526 */ "Number of instructions executed by Geometry Shader threads on SEND pipe Unit: events.\0"
   /* 15612 */ "Number of instructions executed by Hull Shader threads on SEND pipe Unit: events.\0"
   /* 15694 */ "Number of instructions executed by Mesh Shader threads on SEND pipe Unit: events.\0"
   /* 15776 */ "Number of instructions executed by Task Shader threads on SEND pipe Unit: events.\0"
   /* 15858 */ "Number of instructions executed by Vertex Shader threads on SEND pipe Unit: events.\0"
   /* 15942 */ "Number of instructions executed on Jump Pipe Unit: events.\0"
   /* 16001 */ "Number of instructions executed on SEND pipe Unit: events.\0"
   /* 16060 */ "Number of instructions issued (decoded) to any pipe Unit: events.\0"
   /* 16126 */ "Number of internal BVH nodes processed by the traversal function Unit: events.\0"
   /* 16205 */ "Number of intersection threads dispatched for RayQuery only Unit: events.\0"
   /* 16279 */ "Number of lit samples emitted by Rasterizer Unit: pixels.\0"
   /* 16337 */ "Number of message payload transactions sent by XVEs to the Load Store Cache Unit: events.\0"
   /* 16427 */ "Number of message payload transactions sent from XVEs to the Dataport Unit: events.\0"
   /* 16511 */ "Number of message payload transactions sent from the Load Store Cache back to XVEs Unit: events.\0"
   /* 16608 */ "Number of miss threads dispatched for RayQuery only Unit: events.\0"
   /* 16674 */ "Number of nodes processed that use ray-quad intersection pipeline Unit: events.\0"
   /* 16754 */ "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test Unit: bytes.\0"
   /* 16840 */ "Number of non-promoted 2x2 that are lit from Rasterizer Unit: events.\0"
   /* 16910 */ "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ Unit: events.\0"
   /* 17041 */ "Number of non-promoted 2x2 that failed the hierarchical depth test Unit: bytes.\0"
   /* 17121 */ "Number of objects exiting Stripsfan stage Unit: events.\0"
   /* 17177 */ "Number of only HW transform accesses Unit: events.\0"
   /* 17228 */ "Number of primitives clipped by Clipper due to near/far planes Unit: events.\0"
   /* 17305 */ "Number of primitives going out of Clipper, must clip plus the trivial accept Unit: events.\0"
   /* 17396 */ "Number of procedural BVH nodes processed by the traversal function Unit: events.\0"
   /* 17477 */ "Number of promoted 2x2 passed by hierarchical depth test Unit: bytes.\0"
   /* 17547 */ "Number of promoted 2x2 that are ambiguous by hierarchical depth test Unit: bytes.\0"
   /* 17629 */ "Number of promoted 2x2 that are lit from Rasterizer Unit: events.\0"
   /* 17695 */ "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ Unit: events.\0"
   /* 17798 */ "Number of promoted 2x2 that failed the hierarchical depth test Unit: bytes.\0"
   /* 17874 */ "Number of read messages sent by XVEs to the Dataport Unit: events.\0"
   /* 17941 */ "Number of read messages sent by XVEs to the Load Store Cache Unit: events.\0"
   /* 18016 */ "Number of read messages sent from Ray Tracing unit to the Load Store Cache Unit: events.\0"
   /* 18105 */ "Number of return message payload transactions sent from the Dataport to XVEs Unit: events.\0"
   /* 18196 */ "Number of sampler L2 cache misses (ss0) Unit: messages.\0"
   /* 18252 */ "Number of sampler L2 cache misses (ss1) Unit: messages.\0"
   /* 18308 */ "Number of sampler L2 cache misses (ss2) Unit: messages.\0"
   /* 18364 */ "Number of sampler L2 cache misses (ss3) Unit: messages.\0"
   /* 18420 */ "Number of sampler L2 cache misses Unit: messages.\0"
   /* 18470 */ "Number of shader atomic memory accesses Unit: messages.\0"
   /* 18526 */ "Number of shader barrier messages Unit: messages.\0"
   /* 18576 */ "Number of simple culled objects in Stripsfan stage Unit: events.\0"
   /* 18641 */ "Number of system memory bytes read (upstream) Unit: bytes.\0"
   /* 18700 */ "Number of system memory bytes written (upstream) Unit: bytes.\0"
   /* 18762 */ "Number of system memory reads (upstream) Unit: events.\0"
   /* 18817 */ "Number of system memory writes (upstream) Unit: events.\0"
   /* 18873 */ "Number of thread slots occupied Unit: events.\0"
   /* 18919 */ "Number of transactions pushed from Rasterizer to the Z pipe Unit: events.\0"
   /* 18993 */ "Number of triangle BVH nodes processed by the traversal function Unit: events.\0"
   /* 19072 */ "Number of valid SIMD lanes in the TraceRay message Unit: events.\0"
   /* 19137 */ "Number of vertices written by SOL Unit: events.\0"
   /* 19185 */ "Number of write messages sent by XVEs to the Dataport Unit: events.\0"
   /* 19253 */ "Number of write messages sent by XVEs to the Load Store Cache Unit: events.\0"
   /* 19329 */ "Number of write messages sent from Ray Tracing unit to the Load Store Cache Unit: events.\0"
   /* 19419 */ "Number of writes to the Load Store Cache that don't fill a subsector Unit: events.\0"
   /* 19502 */ "Percentage of execution slots taken by BF16 XMX instructions Unit: percent.\0"
   /* 19578 */ "Percentage of execution slots taken by FP16 ALU instructions Unit: percent.\0"
   /* 19654 */ "Percentage of execution slots taken by FP16 XMX instructions Unit: percent.\0"
   /* 19730 */ "Percentage of execution slots taken by FP32 ALU instructions Unit: percent.\0"
   /* 19806 */ "Percentage of execution slots taken by INT16 ALU instructions Unit: percent.\0"
   /* 19883 */ "Percentage of execution slots taken by INT32 ALU instructions Unit: percent.\0"
   /* 19960 */ "Percentage of execution slots taken by INT8 XMX instructions Unit: percent.\0"
   /* 20036 */ "Percentage of execution slots taken by extended math instructions Unit: percent.\0"
   /* 20117 */ "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe Unit: percent.\0"
   /* 20230 */ "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe Unit: percent.\0"
   /* 20343 */ "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe Unit: percent.\0"
   /* 20454 */ "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe Unit: percent.\0"
   /* 20565 */ "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe Unit: percent.\0"
   /* 20680 */ "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe Unit: percent.\0"
   /* 20795 */ "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe Unit: percent.\0"
   /* 20903 */ "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe Unit: percent.\0"
   /* 21011 */ "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe Unit: percent.\0"
   /* 21139 */ "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe Unit: percent.\0"
   /* 21267 */ "Percentage of execution slots taken by instructions executed by Domain Shader on ALU0 pipe Unit: percent.\0"
   /* 21373 */ "Percentage of execution slots taken by instructions executed by Domain Shader on ALU1 pipe Unit: percent.\0"
   /* 21479 */ "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe Unit: percent.\0"
   /* 21587 */ "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe Unit: percent.\0"
   /* 21695 */ "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe Unit: percent.\0"
   /* 21803 */ "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe Unit: percent.\0"
   /* 21911 */ "Percentage of execution slots taken by instructions executed by Hull Shader on ALU0 pipe Unit: percent.\0"
   /* 22015 */ "Percentage of execution slots taken by instructions executed by Hull Shader on ALU1 pipe Unit: percent.\0"
   /* 22119 */ "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe Unit: percent.\0"
   /* 22223 */ "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe Unit: percent.\0"
   /* 22327 */ "Percentage of execution slots taken by instructions executed by Task Shader on ALU0 pipe Unit: percent.\0"
   /* 22431 */ "Percentage of execution slots taken by instructions executed by Task Shader on ALU1 pipe Unit: percent.\0"
   /* 22535 */ "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe Unit: percent.\0"
   /* 22641 */ "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe Unit: percent.\0"
   /* 22747 */ "Percentage of execution slots taken by instructions executed in XMX pipe Unit: percent.\0"
   /* 22835 */ "Percentage of execution slots taken by instructions executed on ALU0 pipe Unit: percent.\0"
   /* 22924 */ "Percentage of execution slots taken by instructions executed on ALU1 pipe Unit: percent.\0"
   /* 23013 */ "Percentage of thread slots occupied Unit: percent.\0"
   /* 23064 */ "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid Unit: events.\0"
   /* 23155 */ "Percentage of time in which ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction Unit: percent.\0"
   /* 23268 */ "Percentage of time in which ALU0 and XMX pipes are both actively executing a Gen ISA instruction Unit: percent.\0"
   /* 23380 */ "Percentage of time in which AMFS stalls at any of the color pipe inputs Unit: percent.\0"
   /* 23467 */ "Percentage of time in which AMFS stalls at both of the color pipe inputs Unit: percent.\0"
   /* 23555 */ "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core Unit: percent.\0"
   /* 23665 */ "Percentage of time in which Clipper has input available (from Vertex Shader or SOL) Unit: percent.\0"
   /* 23764 */ "Percentage of time in which Clipper output ready Unit: percent.\0"
   /* 23828 */ "Percentage of time in which Color Pipeline input ready Unit: percent.\0"
   /* 23898 */ "Percentage of time in which Color Pipeline pixel output ready Unit: percent.\0"
   /* 23975 */ "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full Unit: percent.\0"
   /* 24098 */ "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full Unit: percent.\0"
   /* 24214 */ "Percentage of time in which HiZ latency hiding structure full Unit: percent.\0"
   /* 24291 */ "Percentage of time in which IZ has requests to different clients Unit: percent.\0"
   /* 24371 */ "Percentage of time in which IZ latency hiding structure full Unit: percent.\0"
   /* 24447 */ "Percentage of time in which L3 Bank Stalled Unit: percent.\0"
   /* 24506 */ "Percentage of time in which L3 Bank has input requests Unit: percent.\0"
   /* 24576 */ "Percentage of time in which L3 Bank has output ready Unit: percent.\0"
   /* 24644 */ "Percentage of time in which L3 bank has input requests Unit: percent.\0"
   /* 24714 */ "Percentage of time in which L3 bank has output ready Unit: percent.\0"
   /* 24782 */ "Percentage of time in which L3 bank stalled Unit: percent.\0"
   /* 24841 */ "Percentage of time in which L3 request queue has one or more requests pending Unit: percent.\0"
   /* 24934 */ "Percentage of time in which Pixel Shader data is available Unit: percent.\0"
   /* 25008 */ "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core Unit: percent.\0"
   /* 25119 */ "Percentage of time in which Rasterizer input is available Unit: percent.\0"
   /* 25192 */ "Percentage of time in which Rasterizer output is ready Unit: percent.\0"
   /* 25262 */ "Percentage of time in which Ray Tracing message input is stalled while accepting input Unit: percent.\0"
   /* 25364 */ "Percentage of time in which RayTracing Leaf has two Traversal inputs valid Unit: events.\0"
   /* 25453 */ "Percentage of time in which SQ is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 25548 */ "Percentage of time in which Sampler input is available Unit: percent.\0"
   /* 25618 */ "Percentage of time in which Sampler output is ready Unit: percent.\0"
   /* 25685 */ "Percentage of time in which Sampler pipeline active Unit: percent.\0"
   /* 25752 */ "Percentage of time in which Sampler stalled due to latency hiding structure full Unit: percent.\0"
   /* 25848 */ "Percentage of time in which Thread Dispatch input is available Unit: percent.\0"
   /* 25926 */ "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available Unit: percent.\0"
   /* 26032 */ "Percentage of time in which Thread Spawner has input available on queue 0 Unit: percent.\0"
   /* 26121 */ "Percentage of time in which Thread Spawner has input available on queue 1 Unit: percent.\0"
   /* 26210 */ "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack) Unit: percent.\0"
   /* 26343 */ "Percentage of time in which Vertex Fetch input is available Unit: percent.\0"
   /* 26418 */ "Percentage of time in which Vertex Fetch output is ready Unit: percent.\0"
   /* 26490 */ "Percentage of time in which Vertex Shader output is ready Unit: percent.\0"
   /* 26563 */ "Percentage of time in which XVE requests stalled by Shared Function units Unit: percent.\0"
   /* 26652 */ "Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled Unit: percent.\0"
   /* 26758 */ "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register Unit: percent.\0"
   /* 26881 */ "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register Unit: percent.\0"
   /* 27007 */ "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch Unit: percent.\0"
   /* 27118 */ "Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction Unit: percent.\0"
   /* 27246 */ "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register Unit: percent.\0"
   /* 27366 */ "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available Unit: percent.\0"
   /* 27492 */ "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc) Unit: percent.\0"
   /* 27620 */ "Percentage of time in which XVEs have requests to the Dataport Unit: percent.\0"
   /* 27698 */ "Percentage of time in which all slots in L3 request queue are waiting for data return / response Unit: percent.\0"
   /* 27810 */ "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 27920 */ "Percentage of time in which at least one pipe is active in XVE Unit: percent.\0"
   /* 27998 */ "Percentage of time in which at least one pipe is active in XVE and there are Async Compute Shader threads loaded Unit: percent.\0"
   /* 28126 */ "Percentage of time in which at least one pipe is active in XVE and there are Compute Shader (from Render Engine) threads loaded Unit: percent.\0"
   /* 28269 */ "Percentage of time in which at least one pipe is active in XVE and there are Domain Shader threads loaded Unit: percent.\0"
   /* 28390 */ "Percentage of time in which at least one pipe is active in XVE and there are Fragment Shader threads loaded Unit: percent.\0"
   /* 28513 */ "Percentage of time in which at least one pipe is active in XVE and there are Geometry Shader threads loaded Unit: percent.\0"
   /* 28636 */ "Percentage of time in which at least one pipe is active in XVE and there are Hull Shader threads loaded Unit: percent.\0"
   /* 28755 */ "Percentage of time in which at least one pipe is active in XVE and there are Mesh Shader threads loaded Unit: percent.\0"
   /* 28874 */ "Percentage of time in which at least one pipe is active in XVE and there are Ray Tracing Shader threads loaded Unit: percent.\0"
   /* 29000 */ "Percentage of time in which at least one pipe is active in XVE and there are Task Shader threads loaded Unit: percent.\0"
   /* 29119 */ "Percentage of time in which at least one pipe is active in XVE and there are Vertex Shader threads loaded Unit: percent.\0"
   /* 29240 */ "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes Unit: percent.\0"
   /* 29378 */ "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active Unit: percent.\0"
   /* 29476 */ "Percentage of time in which in which geometry pipeline output is ready Unit: percent.\0"
   /* 29562 */ "Percentage of time in which new message is accepted by Ray Tracing Frontend Unit: percent.\0"
   /* 29653 */ "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher Unit: percent.\0"
   /* 29753 */ "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core Unit: percent.\0"
   /* 29868 */ "Percentage of time in which the Dataport has data to return to XVEs Unit: percent.\0"
   /* 29951 */ "Percentage of time in which the Load Store Cache has input available Unit: percent.\0"
   /* 30035 */ "Percentage of time in which the Load Store Cache has output ready Unit: percent.\0"
   /* 30116 */ "Percentage of time in which there are Async Compute Shader threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 30249 */ "Percentage of time in which there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 30397 */ "Percentage of time in which there are Domain Shader threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 30523 */ "Percentage of time in which there are Fragment Shader threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 30651 */ "Percentage of time in which there are Geometry Shader threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 30779 */ "Percentage of time in which there are Hull Shader threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 30903 */ "Percentage of time in which there are Mesh Shader threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 31027 */ "Percentage of time in which there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 31158 */ "Percentage of time in which there are Task Shader threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 31282 */ "Percentage of time in which there are Vertex Shader threads loaded but not even a single pipe is active in XVE Unit: percent.\0"
   /* 31408 */ "Percentage of time in which there is a context loaded and active on the 3D queue Unit: percent.\0"
   /* 31504 */ "Percentage of time in which there is a context loaded and active on the compute queue Unit: percent.\0"
   /* 31605 */ "Percentage of time in which there is a context loaded and active on the copy queue Unit: percent.\0"
   /* 31703 */ "Percentage of time in which there is a context loaded and active on the copy queue. Unit: percent.\0"
   /* 31802 */ "Percentage of time in which there is a context loaded and active on the media queue Unit: percent.\0"
   /* 31901 */ "Percentage of time in which there is a context loaded and active on the video enhancement queue Unit: percent.\0"
   /* 32012 */ "Percentage of time spent dispatching GPGPU threads to XVEs Unit: events.\0"
   /* 32085 */ "Percentage of time taken by instructions executed by Async Compute Shader threads on SEND pipe Unit: percent.\0"
   /* 32195 */ "Percentage of time taken by instructions executed by BTD Any Hit Shader threads on SEND pipe Unit: percent.\0"
   /* 32303 */ "Percentage of time taken by instructions executed by BTD Closest Hit Shader threads on SEND pipe Unit: percent.\0"
   /* 32415 */ "Percentage of time taken by instructions executed by BTD Miss Shader threads on SEND pipe Unit: percent.\0"
   /* 32520 */ "Percentage of time taken by instructions executed by Compute Shader (from Render Engine) threads on SEND pipe Unit: percent.\0"
   /* 32645 */ "Percentage of time taken by instructions executed by Domain Shader threads on SEND pipe Unit: percent.\0"
   /* 32748 */ "Percentage of time taken by instructions executed by Fragment Shader threads on SEND pipe Unit: percent.\0"
   /* 32853 */ "Percentage of time taken by instructions executed by Geometry Shader threads on SEND pipe Unit: percent.\0"
   /* 32958 */ "Percentage of time taken by instructions executed by Hull Shader threads on SEND pipe Unit: percent.\0"
   /* 33059 */ "Percentage of time taken by instructions executed by Mesh Shader threads on SEND pipe Unit: percent.\0"
   /* 33160 */ "Percentage of time taken by instructions executed by Task Shader threads on SEND pipe Unit: percent.\0"
   /* 33261 */ "Percentage of time taken by instructions executed by Vertex Shader threads on SEND pipe Unit: percent.\0"
   /* 33364 */ "Percentage of time taken by instructions executed on Jump Pipe Unit: percent.\0"
   /* 33442 */ "Percentage of time taken by instructions executed on SEND pipe Unit: percent.\0"
   /* 33520 */ "Percentage of time when  the data at Pixel Backend output is ready Unit: percent.\0"
   /* 33602 */ "Percentage of time when  the data is available at input of Pixel Backend Unit: percent.\0"
   /* 33690 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice0) Unit: percent.\0"
   /* 33816 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice1) Unit: percent.\0"
   /* 33942 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice2) Unit: percent.\0"
   /* 34068 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice3) Unit: percent.\0"
   /* 34194 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice4) Unit: percent.\0"
   /* 34320 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice5) Unit: percent.\0"
   /* 34446 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice group 0) Unit: percent.\0"
   /* 34575 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice group 1) Unit: percent.\0"
   /* 34704 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice group 2) Unit: percent.\0"
   /* 34833 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice group 3) Unit: percent.\0"
   /* 34962 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core0) Unit: percent.\0"
   /* 35083 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core1) Unit: percent.\0"
   /* 35204 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core2) Unit: percent.\0"
   /* 35325 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core3) Unit: percent.\0"
   /* 35446 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core0) Unit: percent.\0"
   /* 35567 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core1) Unit: percent.\0"
   /* 35688 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core2) Unit: percent.\0"
   /* 35809 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core3) Unit: percent.\0"
   /* 35930 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core0) Unit: percent.\0"
   /* 36051 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core1) Unit: percent.\0"
   /* 36172 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core2) Unit: percent.\0"
   /* 36293 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core3) Unit: percent.\0"
   /* 36414 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core0) Unit: percent.\0"
   /* 36535 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core1) Unit: percent.\0"
   /* 36656 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core2) Unit: percent.\0"
   /* 36777 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core3) Unit: percent.\0"
   /* 36898 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core0) Unit: percent.\0"
   /* 37019 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core1) Unit: percent.\0"
   /* 37140 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core2) Unit: percent.\0"
   /* 37261 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core3) Unit: percent.\0"
   /* 37382 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core0) Unit: percent.\0"
   /* 37503 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core1) Unit: percent.\0"
   /* 37624 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core2) Unit: percent.\0"
   /* 37745 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core3) Unit: percent.\0"
   /* 37866 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core0) Unit: percent.\0"
   /* 37987 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core1) Unit: percent.\0"
   /* 38108 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core2) Unit: percent.\0"
   /* 38229 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core3) Unit: percent.\0"
   /* 38350 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core0) Unit: percent.\0"
   /* 38471 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core1) Unit: percent.\0"
   /* 38592 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core2) Unit: percent.\0"
   /* 38713 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core3) Unit: percent.\0"
   /* 38834 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (s0.ss0) Unit: percent.\0"
   /* 38946 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (s0.ss1) Unit: percent.\0"
   /* 39058 */ "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (s0.ss2) Unit: percent.\0"
   /* 39170 */ "Percentage of time when Render Cache input is available Unit: percent.\0"
   /* 39241 */ "Percentage of time when Render Cache output is ready Unit: percent.\0"
   /* 39309 */ "Percentage of time when render cache input is available Unit: percent.\0"
   /* 39380 */ "Percentage of time when render cache output is ready Unit: percent.\0"
   /* 39448 */ "Percentage of time when stencil cache line and an overlapping pixel are causing stalls Unit: percent.\0"
   /* 39550 */ "Ratio of EU typed atomics requests to L3 cache line writes. \0"
   /* 39611 */ "Ratio of EU typed read requests to L3 cache line reads. \0"
   /* 39668 */ "Ratio of EU typed write requests to L3 cache line writes. \0"
   /* 39727 */ "Ratio of EU untyped read requests to L3 cache line reads. \0"
   /* 39786 */ "Ratio of EU untyped write requests to L3 cache line writes. \0"
   /* 39847 */ "Slice 0 Dualsubslice 0 typed atomics. Unit: messages.\0"
   /* 39901 */ "Slice 0 Dualsubslice 0 typed reads. Unit: messages.\0"
   /* 39953 */ "Slice 0 Dualsubslice 0 typed writes. Unit: messages.\0"
   /* 40006 */ "Slice 0 Dualsubslice 0 untyped reads (including SLM reads). Unit: messages.\0"
   /* 40082 */ "Slice 0 Dualsubslice 0 untyped writes (including SLM writes). Unit: messages.\0"
   /* 40160 */ "Slice 0 Subslice group 0 typed atomics. Unit: messages.\0"
   /* 40216 */ "Slice 0 Subslice group 0 typed reads. Unit: messages.\0"
   /* 40270 */ "Slice 0 Subslice group 0 typed writes. Unit: messages.\0"
   /* 40325 */ "Slice 0 Subslice group 0 untyped reads (including SLM reads). Unit: messages.\0"
   /* 40403 */ "Slice 0 Subslice group 0 untyped writes (including SLM writes). Unit: messages.\0"
   /* 40483 */ "Slice0 Dualsubslice 0 Eu 64 Untyped Reads Unit: messages.\0"
   /* 40541 */ "Slice0 Dualsubslice 0 Eu A32 Untyped Reads Unit: messages.\0"
   /* 40600 */ "Slice0 Dualsubslice 0 Eu A32 Untyped Writes Unit: messages.\0"
   /* 40660 */ "Slice0 Dualsubslice 0 Eu A64 Untyped Writes Unit: messages.\0"
   /* 40720 */ "Slice0 Dualsubslice 0 Eu Typed Atomics Unit: messages.\0"
   /* 40775 */ "Slice0 Dualsubslice 0 Eu Typed Reads Unit: messages.\0"
   /* 40828 */ "Slice0 Dualsubslice 0 Eu Typed Writes Unit: messages.\0"
   /* 40882 */ "Slice0 Subslice group 0 Eu 64 Untyped Reads Unit: messages.\0"
   /* 40942 */ "Slice0 Subslice group 0 Eu A32 Untyped Reads Unit: messages.\0"
   /* 41003 */ "Slice0 Subslice group 0 Eu A32 Untyped Writes Unit: messages.\0"
   /* 41065 */ "Slice0 Subslice group 0 Eu A64 Untyped Writes Unit: messages.\0"
   /* 41127 */ "Slice0 Subslice group 0 Eu Typed Atomics Unit: messages.\0"
   /* 41184 */ "Slice0 Subslice group 0 Eu Typed Reads Unit: messages.\0"
   /* 41239 */ "Slice0 Subslice group 0 Eu Typed Writes Unit: messages.\0"
   /* 41295 */ "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs. Unit: cycles.\0"
   /* 41423 */ "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs. Unit: cycles.\0"
   /* 41540 */ "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs. Unit: cycles.\0"
   /* 41668 */ "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs. Unit: cycles.\0"
   /* 41785 */ "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs. Unit: cycles.\0"
   /* 41916 */ "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs. Unit: cycles.\0"
   /* 42036 */ "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs. Unit: cycles.\0"
   /* 42165 */ "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs. Unit: cycles.\0"
   /* 42283 */ "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs. Unit: cycles.\0"
   /* 42412 */ "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs. Unit: cycles.\0"
   /* 42530 */ "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs. Unit: cycles.\0"
   /* 42657 */ "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs. Unit: cycles.\0"
   /* 42773 */ "The average rate of IPC calculated for 2 FPU pipelines. \0"
   /* 42830 */ "The number of FLT64 instructions executed in ALU0 INT64 pipeline. Unit: events.\0"
   /* 42910 */ "The percentage of time in which EU EM pipeline was actively processing a domain shader instructions. Unit: percent.\0"
   /* 43026 */ "The percentage of time in which EU EM pipeline was actively processing a geometry shader instructions. Unit: percent.\0"
   /* 43144 */ "The percentage of time in which EU EM pipeline was actively processing a hull shader instructions. Unit: percent.\0"
   /* 43258 */ "The percentage of time in which EU EM pipeline was actively processing a pixel shader instruction. Unit: percent.\0"
   /* 43372 */ "The percentage of time in which EU EM pipeline was actively processing a vertex shader instruction. Unit: percent.\0"
   /* 43487 */ "The percentage of time in which EU EM pipeline was actively processing. Unit: percent.\0"
   /* 43574 */ "The percentage of time in which EU FPU and EM pipelines were actively processing. Unit: percent.\0"
   /* 43671 */ "The percentage of time in which EU FPU pipeline was actively processing a compute shader instruction. Unit: percent.\0"
   /* 43788 */ "The percentage of time in which EU FPU pipeline was actively processing a domain shader instructions. Unit: percent.\0"
   /* 43905 */ "The percentage of time in which EU FPU pipeline was actively processing a geometry shader instructions. Unit: percent.\0"
   /* 44024 */ "The percentage of time in which EU FPU pipeline was actively processing a hull shader instruction. Unit: percent.\0"
   /* 44138 */ "The percentage of time in which EU FPU pipeline was actively processing a pixel shader instruction. Unit: percent.\0"
   /* 44253 */ "The percentage of time in which EU FPU pipeline was actively processing a vertex shader instruction. Unit: percent.\0"
   /* 44369 */ "The percentage of time in which EU FPU pipeline was actively processing. Unit: percent.\0"
   /* 44457 */ "The percentage of time in which EU FPU0 pipeline was actively processing a compute shader instruction. Unit: percent.\0"
   /* 44575 */ "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction. Unit: percent.\0"
   /* 44691 */ "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction. Unit: percent.\0"
   /* 44808 */ "The percentage of time in which EU FPU0 pipeline was actively processing. Unit: percent.\0"
   /* 44897 */ "The percentage of time in which EU FPU1 pipeline was actively processing a compute shader instruction. Unit: percent.\0"
   /* 45015 */ "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction. Unit: percent.\0"
   /* 45131 */ "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction. Unit: percent.\0"
   /* 45248 */ "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing Unit: percent.\0"
   /* 45371 */ "The percentage of time in which EU FPU1 pipeline was actively processing. Unit: percent.\0"
   /* 45460 */ "The percentage of time in which EU send pipeline was actively processing a compute shader instruction. Unit: percent.\0"
   /* 45578 */ "The percentage of time in which EU send pipeline was actively processing a domain shader instruction. Unit: percent.\0"
   /* 45695 */ "The percentage of time in which EU send pipeline was actively processing a geometry shader instruction. Unit: percent.\0"
   /* 45814 */ "The percentage of time in which EU send pipeline was actively processing a hull shader instruction. Unit: percent.\0"
   /* 45929 */ "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction. Unit: percent.\0"
   /* 46045 */ "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction. Unit: percent.\0"
   /* 46162 */ "The percentage of time in which EU send pipeline was actively processing. Unit: percent.\0"
   /* 46251 */ "The percentage of time in which FLT16 instruction were processed actively on FPU INT64 pipeline. Unit: percent.\0"
   /* 46363 */ "The percentage of time in which FLT32 instruction were processed actively on FPU INT64 pipeline. Unit: percent.\0"
   /* 46475 */ "The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline. Unit: percent.\0"
   /* 46587 */ "The percentage of time in which GTI Read-Only port has been stalled. Unit: percent.\0"
   /* 46671 */ "The percentage of time in which GTI Read-Write port has been stalled. Unit: percent.\0"
   /* 46756 */ "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core0 thread dispatcher Unit: percent.\0"
   /* 46872 */ "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core1 thread dispatcher Unit: percent.\0"
   /* 46988 */ "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core2 thread dispatcher Unit: percent.\0"
   /* 47104 */ "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core3 thread dispatcher Unit: percent.\0"
   /* 47220 */ "The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice0 thread dispatcher Unit: percent.\0"
   /* 47341 */ "The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice1 thread dispatcher Unit: percent.\0"
   /* 47462 */ "The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice2 thread dispatcher Unit: percent.\0"
   /* 47583 */ "The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice3 thread dispatcher Unit: percent.\0"
   /* 47704 */ "The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice4 thread dispatcher Unit: percent.\0"
   /* 47825 */ "The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice5 thread dispatcher Unit: percent.\0"
   /* 47946 */ "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher Unit: percent.\0"
   /* 48063 */ "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher Unit: percent.\0"
   /* 48180 */ "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher Unit: percent.\0"
   /* 48297 */ "The percentage of time in which PS thread is ready for dispatch on slice0 subslice3 thread dispatcher Unit: percent.\0"
   /* 48414 */ "The percentage of time in which PS thread is ready for dispatch on slice0 subslice4 thread dispatcher Unit: percent.\0"
   /* 48531 */ "The percentage of time in which PS thread is ready for dispatch on slice0 subslice5 thread dispatcher Unit: percent.\0"
   /* 48648 */ "The percentage of time in which PS thread is ready for dispatch on slice0 subslice6 thread dispatcher Unit: percent.\0"
   /* 48765 */ "The percentage of time in which PS thread is ready for dispatch on slice0 subslice7 thread dispatcher Unit: percent.\0"
   /* 48882 */ "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core0 thread dispatcher Unit: percent.\0"
   /* 48998 */ "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core1 thread dispatcher Unit: percent.\0"
   /* 49114 */ "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core2 thread dispatcher Unit: percent.\0"
   /* 49230 */ "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core3 thread dispatcher Unit: percent.\0"
   /* 49346 */ "The percentage of time in which PS thread is ready for dispatch on slice1 subslice0 thread dispatcher Unit: percent.\0"
   /* 49463 */ "The percentage of time in which PS thread is ready for dispatch on slice1 subslice1 thread dispatcher Unit: percent.\0"
   /* 49580 */ "The percentage of time in which PS thread is ready for dispatch on slice1 subslice2 thread dispatcher Unit: percent.\0"
   /* 49697 */ "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher Unit: percent.\0"
   /* 49813 */ "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher Unit: percent.\0"
   /* 49929 */ "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher Unit: percent.\0"
   /* 50045 */ "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher Unit: percent.\0"
   /* 50161 */ "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher Unit: percent.\0"
   /* 50277 */ "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher Unit: percent.\0"
   /* 50393 */ "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher Unit: percent.\0"
   /* 50509 */ "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher Unit: percent.\0"
   /* 50625 */ "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core0 thread dispatcher Unit: percent.\0"
   /* 50741 */ "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core1 thread dispatcher Unit: percent.\0"
   /* 50857 */ "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core2 thread dispatcher Unit: percent.\0"
   /* 50973 */ "The percentage of time in which PS thread is ready for dispatch on slice4 Xe core3 thread dispatcher Unit: percent.\0"
   /* 51089 */ "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core0 thread dispatcher Unit: percent.\0"
   /* 51205 */ "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core1 thread dispatcher Unit: percent.\0"
   /* 51321 */ "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core2 thread dispatcher Unit: percent.\0"
   /* 51437 */ "The percentage of time in which PS thread is ready for dispatch on slice5 Xe core3 thread dispatcher Unit: percent.\0"
   /* 51553 */ "The percentage of time in which PS thread is ready for dispatch on slice6 Xe core0 thread dispatcher Unit: percent.\0"
   /* 51669 */ "The percentage of time in which PS thread is ready for dispatch on slice6 Xe core1 thread dispatcher Unit: percent.\0"
   /* 51785 */ "The percentage of time in which PS thread is ready for dispatch on slice6 Xe core2 thread dispatcher Unit: percent.\0"
   /* 51901 */ "The percentage of time in which PS thread is ready for dispatch on slice6 Xe core3 thread dispatcher Unit: percent.\0"
   /* 52017 */ "The percentage of time in which PS thread is ready for dispatch on slice7 Xe core0 thread dispatcher Unit: percent.\0"
   /* 52133 */ "The percentage of time in which PS thread is ready for dispatch on slice7 Xe core1 thread dispatcher Unit: percent.\0"
   /* 52249 */ "The percentage of time in which PS thread is ready for dispatch on slice7 Xe core2 thread dispatcher Unit: percent.\0"
   /* 52365 */ "The percentage of time in which PS thread is ready for dispatch on slice7 Xe core3 thread dispatcher Unit: percent.\0"
   /* 52481 */ "The percentage of time in which PS00 output is available Unit: percent.\0"
   /* 52553 */ "The percentage of time in which PS01 output is available Unit: percent.\0"
   /* 52625 */ "The percentage of time in which PS10 output is available Unit: percent.\0"
   /* 52697 */ "The percentage of time in which PS11 output is available Unit: percent.\0"
   /* 52769 */ "The percentage of time in which PS20 output is available Unit: percent.\0"
   /* 52841 */ "The percentage of time in which PS21 output is available Unit: percent.\0"
   /* 52913 */ "The percentage of time in which PS30 output is available Unit: percent.\0"
   /* 52985 */ "The percentage of time in which PS31 output is available Unit: percent.\0"
   /* 53057 */ "The percentage of time in which Quad0 L3 bank0 has input available Unit: percent.\0"
   /* 53139 */ "The percentage of time in which Quad0 L3 bank1 has input available Unit: percent.\0"
   /* 53221 */ "The percentage of time in which Quad0 L3 bank2 has input available Unit: percent.\0"
   /* 53303 */ "The percentage of time in which Quad0 L3 bank3 has input available Unit: percent.\0"
   /* 53385 */ "The percentage of time in which Quad0 L3 bank4 has input available Unit: percent.\0"
   /* 53467 */ "The percentage of time in which Quad0 L3 bank5 has input available Unit: percent.\0"
   /* 53549 */ "The percentage of time in which Quad0 L3 bank6 has input available Unit: percent.\0"
   /* 53631 */ "The percentage of time in which Quad0 L3 bank7 has input available Unit: percent.\0"
   /* 53713 */ "The percentage of time in which Quad1 L3 bank0 has input available Unit: percent.\0"
   /* 53795 */ "The percentage of time in which Quad1 L3 bank1 has input available Unit: percent.\0"
   /* 53877 */ "The percentage of time in which Quad1 L3 bank2 has input available Unit: percent.\0"
   /* 53959 */ "The percentage of time in which Quad1 L3 bank3 has input available Unit: percent.\0"
   /* 54041 */ "The percentage of time in which Quad1 L3 bank4 has input available Unit: percent.\0"
   /* 54123 */ "The percentage of time in which Quad1 L3 bank5 has input available Unit: percent.\0"
   /* 54205 */ "The percentage of time in which Quad1 L3 bank6 has input available Unit: percent.\0"
   /* 54287 */ "The percentage of time in which Quad1 L3 bank7 has input available Unit: percent.\0"
   /* 54369 */ "The percentage of time in which Quad2 L3 bank0 has input available Unit: percent.\0"
   /* 54451 */ "The percentage of time in which Quad2 L3 bank1 has input available Unit: percent.\0"
   /* 54533 */ "The percentage of time in which Quad2 L3 bank2 has input available Unit: percent.\0"
   /* 54615 */ "The percentage of time in which Quad2 L3 bank3 has input available Unit: percent.\0"
   /* 54697 */ "The percentage of time in which Quad2 L3 bank4 has input available Unit: percent.\0"
   /* 54779 */ "The percentage of time in which Quad2 L3 bank5 has input available Unit: percent.\0"
   /* 54861 */ "The percentage of time in which Quad2 L3 bank6 has input available Unit: percent.\0"
   /* 54943 */ "The percentage of time in which Quad2 L3 bank7 has input available Unit: percent.\0"
   /* 55025 */ "The percentage of time in which Quad3 L3 bank0 has input available Unit: percent.\0"
   /* 55107 */ "The percentage of time in which Quad3 L3 bank1 has input available Unit: percent.\0"
   /* 55189 */ "The percentage of time in which Quad3 L3 bank2 has input available Unit: percent.\0"
   /* 55271 */ "The percentage of time in which Quad3 L3 bank3 has input available Unit: percent.\0"
   /* 55353 */ "The percentage of time in which Quad3 L3 bank4 has input available Unit: percent.\0"
   /* 55435 */ "The percentage of time in which Quad3 L3 bank5 has input available Unit: percent.\0"
   /* 55517 */ "The percentage of time in which Quad3 L3 bank6 has input available Unit: percent.\0"
   /* 55599 */ "The percentage of time in which Quad3 L3 bank7 has input available Unit: percent.\0"
   /* 55681 */ "The percentage of time in which Sampler 0 has been processing EU requests. Unit: percent.\0"
   /* 55771 */ "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests. Unit: percent.\0"
   /* 55888 */ "The percentage of time in which Sampler 1 has been processing EU requests. Unit: percent.\0"
   /* 55978 */ "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests. Unit: percent.\0"
   /* 56095 */ "The percentage of time in which Slice0 Sampler0 has been processing EU requests. Unit: percent.\0"
   /* 56191 */ "The percentage of time in which Slice0 Sampler0 has been slowing down the pipe when processing EU requests. Unit: percent.\0"
   /* 56314 */ "The percentage of time in which Slice0 Sampler0 has been slowing down the pipe when processing XVE requests. Unit: percent.\0"
   /* 56438 */ "The percentage of time in which Slice2 Sampler0 has been slowing down the pipe when processing XVE requests. Unit: percent.\0"
   /* 56562 */ "The percentage of time in which VME (IME or CRE) was actively processing data. Unit: percent.\0"
   /* 56656 */ "The percentage of time in which VS is sending vertices to CL bypassing other pipeline stages. Unit: percent.\0"
   /* 56765 */ "The percentage of time in which VS0 pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 56865 */ "The percentage of time in which VS1 pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 56965 */ "The percentage of time in which VS2 pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 57065 */ "The percentage of time in which VS3 pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 57165 */ "The percentage of time in which VS4 pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 57265 */ "The percentage of time in which VS5 pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 57365 */ "The percentage of time in which VS6 pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 57465 */ "The percentage of time in which VS7 pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 57565 */ "The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing. Unit: percent.\0"
   /* 57673 */ "The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction. Unit: percent.\0"
   /* 57794 */ "The percentage of time in which XVE EM INT pipeline was actively processing a domain shader instruction. Unit: percent.\0"
   /* 57914 */ "The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction. Unit: percent.\0"
   /* 58036 */ "The percentage of time in which XVE EM INT pipeline was actively processing a geometry shader instruction. Unit: percent.\0"
   /* 58158 */ "The percentage of time in which XVE EM INT pipeline was actively processing a hull shader instruction. Unit: percent.\0"
   /* 58276 */ "The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction. Unit: percent.\0"
   /* 58396 */ "The percentage of time in which XVE EM INT pipeline was actively processing. Unit: percent.\0"
   /* 58488 */ "The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction. Unit: percent.\0"
   /* 58612 */ "The percentage of time in which XVE FPU INT64 pipeline was actively processing a domain shader instruction. Unit: percent.\0"
   /* 58735 */ "The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction. Unit: percent.\0"
   /* 58860 */ "The percentage of time in which XVE FPU INT64 pipeline was actively processing a geometry shader instruction. Unit: percent.\0"
   /* 58985 */ "The percentage of time in which XVE FPU INT64 pipeline was actively processing a hull shader instruction. Unit: percent.\0"
   /* 59106 */ "The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction. Unit: percent.\0"
   /* 59229 */ "The percentage of time in which XVE FPU INT64 pipeline was actively processing. Unit: percent.\0"
   /* 59324 */ "The percentage of time in which XVE XMX and FPU INT64 pipelines were actively processing. Unit: percent.\0"
   /* 59429 */ "The percentage of time in which XVE XMX pipeline was actively processing. Unit: percent.\0"
   /* 59518 */ "The percentage of time in which XVE send pipeline was actively processing a compute shader instruction. Unit: percent.\0"
   /* 59637 */ "The percentage of time in which XVE send pipeline was actively processing a domain shader instruction. Unit: percent.\0"
   /* 59755 */ "The percentage of time in which XVE send pipeline was actively processing a fragment shader instruction. Unit: percent.\0"
   /* 59875 */ "The percentage of time in which XVE send pipeline was actively processing a geometry shader instruction. Unit: percent.\0"
   /* 59995 */ "The percentage of time in which XVE send pipeline was actively processing a hull shader instruction. Unit: percent.\0"
   /* 60111 */ "The percentage of time in which XVE send pipeline was actively processing a vertex shader instruction. Unit: percent.\0"
   /* 60229 */ "The percentage of time in which XVE send pipeline was actively processing. Unit: percent.\0"
   /* 60319 */ "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 60451 */ "The percentage of time in which both EU FPU pipelines were actively processing. Unit: percent.\0"
   /* 60546 */ "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 60650 */ "The percentage of time in which clipper pipeline stage was stalled. Unit: percent.\0"
   /* 60733 */ "The percentage of time in which compute shaders were processed actively on the EUs. Unit: percent.\0"
   /* 60832 */ "The percentage of time in which compute shaders were stalled on the EUs. Unit: percent.\0"
   /* 60920 */ "The percentage of time in which control shaders were processed actively on the EUs. Unit: percent.\0"
   /* 61019 */ "The percentage of time in which control shaders were stalled on the EUs. Unit: percent.\0"
   /* 61107 */ "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 61217 */ "The percentage of time in which domain shader pipeline stage was stalled. Unit: percent.\0"
   /* 61306 */ "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 61419 */ "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 61545 */ "The percentage of time in which evaluation shaders were processed actively on the EUs. Unit: percent.\0"
   /* 61647 */ "The percentage of time in which evaluation shaders were stalled on the EUs. Unit: percent.\0"
   /* 61738 */ "The percentage of time in which execution units were actively processing binary instructions on FPU0. Unit: percent.\0"
   /* 61855 */ "The percentage of time in which execution units were actively processing binary instructions on FPU1. Unit: percent.\0"
   /* 61972 */ "The percentage of time in which execution units were actively processing hybrid instructions on FPU0. Unit: percent.\0"
   /* 62089 */ "The percentage of time in which execution units were actively processing hybrid instructions on FPU1. Unit: percent.\0"
   /* 62206 */ "The percentage of time in which execution units were actively processing move instructions on FPU0. Unit: percent.\0"
   /* 62321 */ "The percentage of time in which execution units were actively processing move instructions on FPU1. Unit: percent.\0"
   /* 62436 */ "The percentage of time in which execution units were actively processing ternary instructions on FPU0. Unit: percent.\0"
   /* 62554 */ "The percentage of time in which execution units were actively processing ternary instructions on FPU1. Unit: percent.\0"
   /* 62672 */ "The percentage of time in which fragment shaders were processed actively on the EUs. Unit: percent.\0"
   /* 62772 */ "The percentage of time in which fragment shaders were processed actively on the both FPUs. Unit: percent.\0"
   /* 62878 */ "The percentage of time in which fragment shaders were stalled on the EUs. Unit: percent.\0"
   /* 62967 */ "The percentage of time in which geometry pipeline output is ready Unit: percent.\0"
   /* 63048 */ "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 63160 */ "The percentage of time in which geometry shaders were processed actively on the EUs. Unit: percent.\0"
   /* 63260 */ "The percentage of time in which geometry shaders were stalled on the EUs. Unit: percent.\0"
   /* 63349 */ "The percentage of time in which hardware threads occupied EUs. Unit: percent.\0"
   /* 63427 */ "The percentage of time in which hardware threads occupied XVEs. Unit: percent.\0"
   /* 63506 */ "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 63614 */ "The percentage of time in which hull stall pipeline stage was stalled. Unit: percent.\0"
   /* 63700 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core0 thread dispatcher Unit: percent.\0"
   /* 63820 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core1 thread dispatcher Unit: percent.\0"
   /* 63940 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core2 thread dispatcher Unit: percent.\0"
   /* 64060 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core3 thread dispatcher Unit: percent.\0"
   /* 64180 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice0 thread dispatcher Unit: percent.\0"
   /* 64305 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice1 thread dispatcher Unit: percent.\0"
   /* 64430 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice2 thread dispatcher Unit: percent.\0"
   /* 64555 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice3 thread dispatcher Unit: percent.\0"
   /* 64680 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice4 thread dispatcher Unit: percent.\0"
   /* 64805 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice5 thread dispatcher Unit: percent.\0"
   /* 64930 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher Unit: percent.\0"
   /* 65051 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher Unit: percent.\0"
   /* 65172 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher Unit: percent.\0"
   /* 65293 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice3 thread dispatcher Unit: percent.\0"
   /* 65414 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice4 thread dispatcher Unit: percent.\0"
   /* 65535 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice5 thread dispatcher Unit: percent.\0"
   /* 65656 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice6 thread dispatcher Unit: percent.\0"
   /* 65777 */ "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice7 thread dispatcher Unit: percent.\0"
   /* 65898 */ "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core0 thread dispatcher Unit: percent.\0"
   /* 66018 */ "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core1 thread dispatcher Unit: percent.\0"
   /* 66138 */ "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core2 thread dispatcher Unit: percent.\0"
   /* 66258 */ "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core3 thread dispatcher Unit: percent.\0"
   /* 66378 */ "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice0 thread dispatcher Unit: percent.\0"
   /* 66499 */ "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice1 thread dispatcher Unit: percent.\0"
   /* 66620 */ "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice2 thread dispatcher Unit: percent.\0"
   /* 66741 */ "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher Unit: percent.\0"
   /* 66861 */ "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher Unit: percent.\0"
   /* 66981 */ "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher Unit: percent.\0"
   /* 67101 */ "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher Unit: percent.\0"
   /* 67221 */ "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher Unit: percent.\0"
   /* 67341 */ "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher Unit: percent.\0"
   /* 67461 */ "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher Unit: percent.\0"
   /* 67581 */ "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher Unit: percent.\0"
   /* 67701 */ "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core0 thread dispatcher Unit: percent.\0"
   /* 67821 */ "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core1 thread dispatcher Unit: percent.\0"
   /* 67941 */ "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core2 thread dispatcher Unit: percent.\0"
   /* 68061 */ "The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core3 thread dispatcher Unit: percent.\0"
   /* 68181 */ "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core0 thread dispatcher Unit: percent.\0"
   /* 68301 */ "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core1 thread dispatcher Unit: percent.\0"
   /* 68421 */ "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core2 thread dispatcher Unit: percent.\0"
   /* 68541 */ "The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core3 thread dispatcher Unit: percent.\0"
   /* 68661 */ "The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core0 thread dispatcher Unit: percent.\0"
   /* 68781 */ "The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core1 thread dispatcher Unit: percent.\0"
   /* 68901 */ "The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core2 thread dispatcher Unit: percent.\0"
   /* 69021 */ "The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core3 thread dispatcher Unit: percent.\0"
   /* 69141 */ "The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core0 thread dispatcher Unit: percent.\0"
   /* 69261 */ "The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core1 thread dispatcher Unit: percent.\0"
   /* 69381 */ "The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core2 thread dispatcher Unit: percent.\0"
   /* 69501 */ "The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core3 thread dispatcher Unit: percent.\0"
   /* 69621 */ "The percentage of time in which pixel values 00 are ready Unit: percent.\0"
   /* 69694 */ "The percentage of time in which pixel values 01 are ready Unit: percent.\0"
   /* 69767 */ "The percentage of time in which pixel values 10 are ready Unit: percent.\0"
   /* 69840 */ "The percentage of time in which pixel values 11 are ready Unit: percent.\0"
   /* 69913 */ "The percentage of time in which pixel values 20 are ready Unit: percent.\0"
   /* 69986 */ "The percentage of time in which pixel values 21 are ready Unit: percent.\0"
   /* 70059 */ "The percentage of time in which pixel values 30 are ready Unit: percent.\0"
   /* 70132 */ "The percentage of time in which pixel values 31 are ready Unit: percent.\0"
   /* 70205 */ "The percentage of time in which quad0 L3 bank0 output is ready Unit: percent.\0"
   /* 70283 */ "The percentage of time in which quad0 L3 bank1 output is ready Unit: percent.\0"
   /* 70361 */ "The percentage of time in which quad0 L3 bank2 output is ready Unit: percent.\0"
   /* 70439 */ "The percentage of time in which quad0 L3 bank3 output is ready Unit: percent.\0"
   /* 70517 */ "The percentage of time in which quad0 L3 bank4 output is ready Unit: percent.\0"
   /* 70595 */ "The percentage of time in which quad0 L3 bank5 output is ready Unit: percent.\0"
   /* 70673 */ "The percentage of time in which quad0 L3 bank6 output is ready Unit: percent.\0"
   /* 70751 */ "The percentage of time in which quad0 L3 bank7 output is ready Unit: percent.\0"
   /* 70829 */ "The percentage of time in which quad1 L3 bank0 output is ready Unit: percent.\0"
   /* 70907 */ "The percentage of time in which quad1 L3 bank1 output is ready Unit: percent.\0"
   /* 70985 */ "The percentage of time in which quad1 L3 bank2 output is ready Unit: percent.\0"
   /* 71063 */ "The percentage of time in which quad1 L3 bank3 output is ready Unit: percent.\0"
   /* 71141 */ "The percentage of time in which quad1 L3 bank4 output is ready Unit: percent.\0"
   /* 71219 */ "The percentage of time in which quad1 L3 bank5 output is ready Unit: percent.\0"
   /* 71297 */ "The percentage of time in which quad1 L3 bank6 output is ready Unit: percent.\0"
   /* 71375 */ "The percentage of time in which quad1 L3 bank7 output is ready Unit: percent.\0"
   /* 71453 */ "The percentage of time in which quad2 L3 bank0 output is ready Unit: percent.\0"
   /* 71531 */ "The percentage of time in which quad2 L3 bank1 output is ready Unit: percent.\0"
   /* 71609 */ "The percentage of time in which quad2 L3 bank2 output is ready Unit: percent.\0"
   /* 71687 */ "The percentage of time in which quad2 L3 bank3 output is ready Unit: percent.\0"
   /* 71765 */ "The percentage of time in which quad2 L3 bank4 output is ready Unit: percent.\0"
   /* 71843 */ "The percentage of time in which quad2 L3 bank5 output is ready Unit: percent.\0"
   /* 71921 */ "The percentage of time in which quad2 L3 bank6 output is ready Unit: percent.\0"
   /* 71999 */ "The percentage of time in which quad2 L3 bank7 output is ready Unit: percent.\0"
   /* 72077 */ "The percentage of time in which quad3 L3 bank0 output is ready Unit: percent.\0"
   /* 72155 */ "The percentage of time in which quad3 L3 bank1 output is ready Unit: percent.\0"
   /* 72233 */ "The percentage of time in which quad3 L3 bank2 output is ready Unit: percent.\0"
   /* 72311 */ "The percentage of time in which quad3 L3 bank3 output is ready Unit: percent.\0"
   /* 72389 */ "The percentage of time in which quad3 L3 bank4 output is ready Unit: percent.\0"
   /* 72467 */ "The percentage of time in which quad3 L3 bank5 output is ready Unit: percent.\0"
   /* 72545 */ "The percentage of time in which quad3 L3 bank6 output is ready Unit: percent.\0"
   /* 72623 */ "The percentage of time in which quad3 L3 bank7 output is ready Unit: percent.\0"
   /* 72701 */ "The percentage of time in which sampler 0 was bottlenecks. Unit: percent.\0"
   /* 72775 */ "The percentage of time in which sampler 0 was busy. Unit: percent.\0"
   /* 72842 */ "The percentage of time in which sampler 1 was bottlenecks. Unit: percent.\0"
   /* 72916 */ "The percentage of time in which sampler 1 was busy. Unit: percent.\0"
   /* 72983 */ "The percentage of time in which samplers have been processing EU requests. Unit: percent.\0"
   /* 73073 */ "The percentage of time in which samplers have been slowing down the pipe when processing EU requests. Unit: percent.\0"
   /* 73190 */ "The percentage of time in which samplers have been slowing down the pipe when processing XVE requests. Unit: percent.\0"
   /* 73308 */ "The percentage of time in which samplers or L1 cache are not idle. Unit: percent.\0"
   /* 73390 */ "The percentage of time in which samplers were bottlenecks. Unit: percent.\0"
   /* 73464 */ "The percentage of time in which samplers were busy. Unit: percent.\0"
   /* 73531 */ "The percentage of time in which slice0  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 73664 */ "The percentage of time in which slice0  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 73797 */ "The percentage of time in which slice0  pipe2 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 73930 */ "The percentage of time in which slice0 L3 bank0 has input available Unit: percent.\0"
   /* 74013 */ "The percentage of time in which slice0 L3 bank0 is active Unit: percent.\0"
   /* 74086 */ "The percentage of time in which slice0 L3 bank0 is stalled Unit: percent.\0"
   /* 74160 */ "The percentage of time in which slice0 L3 bank0 output is ready Unit: percent.\0"
   /* 74239 */ "The percentage of time in which slice0 L3 bank1 has input available Unit: percent.\0"
   /* 74322 */ "The percentage of time in which slice0 L3 bank1 is active Unit: percent.\0"
   /* 74395 */ "The percentage of time in which slice0 L3 bank1 is stalled Unit: percent.\0"
   /* 74469 */ "The percentage of time in which slice0 L3 bank1 output is ready Unit: percent.\0"
   /* 74548 */ "The percentage of time in which slice0 L3 bank2 has input available Unit: percent.\0"
   /* 74631 */ "The percentage of time in which slice0 L3 bank2 is active Unit: percent.\0"
   /* 74704 */ "The percentage of time in which slice0 L3 bank2 is stalled Unit: percent.\0"
   /* 74778 */ "The percentage of time in which slice0 L3 bank2 output is ready Unit: percent.\0"
   /* 74857 */ "The percentage of time in which slice0 L3 bank3 has input available Unit: percent.\0"
   /* 74940 */ "The percentage of time in which slice0 L3 bank3 is active Unit: percent.\0"
   /* 75013 */ "The percentage of time in which slice0 L3 bank3 is stalled Unit: percent.\0"
   /* 75087 */ "The percentage of time in which slice0 L3 bank3 output is ready Unit: percent.\0"
   /* 75166 */ "The percentage of time in which slice0 L3 bank4 has input available Unit: percent.\0"
   /* 75249 */ "The percentage of time in which slice0 L3 bank4 is active Unit: percent.\0"
   /* 75322 */ "The percentage of time in which slice0 L3 bank4 is stalled Unit: percent.\0"
   /* 75396 */ "The percentage of time in which slice0 L3 bank4 output is ready Unit: percent.\0"
   /* 75475 */ "The percentage of time in which slice0 L3 bank5 has input available Unit: percent.\0"
   /* 75558 */ "The percentage of time in which slice0 L3 bank5 is active Unit: percent.\0"
   /* 75631 */ "The percentage of time in which slice0 L3 bank5 is stalled Unit: percent.\0"
   /* 75705 */ "The percentage of time in which slice0 L3 bank5 output is ready Unit: percent.\0"
   /* 75784 */ "The percentage of time in which slice0 L3 bank6 has input available Unit: percent.\0"
   /* 75867 */ "The percentage of time in which slice0 L3 bank6 is active Unit: percent.\0"
   /* 75940 */ "The percentage of time in which slice0 L3 bank6 output is ready Unit: percent.\0"
   /* 76019 */ "The percentage of time in which slice0 L3 bank7 has input available Unit: percent.\0"
   /* 76102 */ "The percentage of time in which slice0 L3 bank7 is active Unit: percent.\0"
   /* 76175 */ "The percentage of time in which slice0 L3 bank7 output is ready Unit: percent.\0"
   /* 76254 */ "The percentage of time in which slice0 PS output is available Unit: percent.\0"
   /* 76331 */ "The percentage of time in which slice0 Xe core0 sampler input is available Unit: percent.\0"
   /* 76421 */ "The percentage of time in which slice0 Xe core0 sampler output is ready Unit: percent.\0"
   /* 76508 */ "The percentage of time in which slice0 Xe core1 sampler input is available Unit: percent.\0"
   /* 76598 */ "The percentage of time in which slice0 Xe core1 sampler output is ready Unit: percent.\0"
   /* 76685 */ "The percentage of time in which slice0 Xe core2 sampler input is available Unit: percent.\0"
   /* 76775 */ "The percentage of time in which slice0 Xe core2 sampler output is ready Unit: percent.\0"
   /* 76862 */ "The percentage of time in which slice0 Xe core3 sampler input is available Unit: percent.\0"
   /* 76952 */ "The percentage of time in which slice0 Xe core3 sampler output is ready Unit: percent.\0"
   /* 77039 */ "The percentage of time in which slice0 dualsubslice0 sampler input is available Unit: percent.\0"
   /* 77134 */ "The percentage of time in which slice0 dualsubslice0 sampler output is ready Unit: percent.\0"
   /* 77226 */ "The percentage of time in which slice0 dualsubslice1 sampler input is available Unit: percent.\0"
   /* 77321 */ "The percentage of time in which slice0 dualsubslice1 sampler output is ready Unit: percent.\0"
   /* 77413 */ "The percentage of time in which slice0 dualsubslice2 sampler input is available Unit: percent.\0"
   /* 77508 */ "The percentage of time in which slice0 dualsubslice2 sampler output is ready Unit: percent.\0"
   /* 77600 */ "The percentage of time in which slice0 dualsubslice3 sampler input is available Unit: percent.\0"
   /* 77695 */ "The percentage of time in which slice0 dualsubslice3 sampler output is ready Unit: percent.\0"
   /* 77787 */ "The percentage of time in which slice0 dualsubslice4 sampler input is available Unit: percent.\0"
   /* 77882 */ "The percentage of time in which slice0 dualsubslice4 sampler output is ready Unit: percent.\0"
   /* 77974 */ "The percentage of time in which slice0 dualsubslice5 sampler input is available Unit: percent.\0"
   /* 78069 */ "The percentage of time in which slice0 dualsubslice5 sampler output is ready Unit: percent.\0"
   /* 78161 */ "The percentage of time in which slice0 pipe0 PS output is available Unit: percent.\0"
   /* 78244 */ "The percentage of time in which slice0 pipe0 pixel values are ready Unit: percent.\0"
   /* 78327 */ "The percentage of time in which slice0 pipe1 PS output is available Unit: percent.\0"
   /* 78410 */ "The percentage of time in which slice0 pipe1 pixel values are ready Unit: percent.\0"
   /* 78493 */ "The percentage of time in which slice0 pipe2 PS output is available Unit: percent.\0"
   /* 78576 */ "The percentage of time in which slice0 pipe2 pixel values are ready Unit: percent.\0"
   /* 78659 */ "The percentage of time in which slice0 pixel values are ready Unit: percent.\0"
   /* 78736 */ "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 78862 */ "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)) Unit: percent.\0"
   /* 78989 */ "The percentage of time in which slice0 rasterizer input is available Unit: percent.\0"
   /* 79073 */ "The percentage of time in which slice0 rasterizer output is ready Unit: percent.\0"
   /* 79154 */ "The percentage of time in which slice0 subslice0 sampler input is available Unit: percent.\0"
   /* 79245 */ "The percentage of time in which slice0 subslice0 sampler output is ready Unit: percent.\0"
   /* 79333 */ "The percentage of time in which slice0 subslice1 sampler input is available Unit: percent.\0"
   /* 79424 */ "The percentage of time in which slice0 subslice1 sampler output is ready Unit: percent.\0"
   /* 79512 */ "The percentage of time in which slice0 subslice2 sampler input is available Unit: percent.\0"
   /* 79603 */ "The percentage of time in which slice0 subslice2 sampler output is ready Unit: percent.\0"
   /* 79691 */ "The percentage of time in which slice0 subslice3 sampler input is available Unit: percent.\0"
   /* 79782 */ "The percentage of time in which slice0 subslice3 sampler output is ready Unit: percent.\0"
   /* 79870 */ "The percentage of time in which slice0 subslice4 sampler input is available Unit: percent.\0"
   /* 79961 */ "The percentage of time in which slice0 subslice4 sampler output is ready Unit: percent.\0"
   /* 80049 */ "The percentage of time in which slice0 subslice5 sampler input is available Unit: percent.\0"
   /* 80140 */ "The percentage of time in which slice0 subslice5 sampler output is ready Unit: percent.\0"
   /* 80228 */ "The percentage of time in which slice0 subslice6 sampler input is available Unit: percent.\0"
   /* 80319 */ "The percentage of time in which slice0 subslice6 sampler output is ready Unit: percent.\0"
   /* 80407 */ "The percentage of time in which slice0 subslice7 sampler input is available Unit: percent.\0"
   /* 80498 */ "The percentage of time in which slice0 subslice7 sampler output is ready Unit: percent.\0"
   /* 80586 */ "The percentage of time in which slice1  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 80719 */ "The percentage of time in which slice1  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 80852 */ "The percentage of time in which slice1 L3 bank0 is active Unit: percent.\0"
   /* 80925 */ "The percentage of time in which slice1 L3 bank0 is stalled Unit: percent.\0"
   /* 80999 */ "The percentage of time in which slice1 L3 bank1 is active Unit: percent.\0"
   /* 81072 */ "The percentage of time in which slice1 L3 bank1 is stalled Unit: percent.\0"
   /* 81146 */ "The percentage of time in which slice1 L3 bank2 is active Unit: percent.\0"
   /* 81219 */ "The percentage of time in which slice1 L3 bank2 is stalled Unit: percent.\0"
   /* 81293 */ "The percentage of time in which slice1 L3 bank3 is active Unit: percent.\0"
   /* 81366 */ "The percentage of time in which slice1 L3 bank3 is stalled Unit: percent.\0"
   /* 81440 */ "The percentage of time in which slice1 PS output is available Unit: percent.\0"
   /* 81517 */ "The percentage of time in which slice1 Xe core0 sampler input is available Unit: percent.\0"
   /* 81607 */ "The percentage of time in which slice1 Xe core0 sampler output is ready Unit: percent.\0"
   /* 81694 */ "The percentage of time in which slice1 Xe core1 sampler input is available Unit: percent.\0"
   /* 81784 */ "The percentage of time in which slice1 Xe core1 sampler output is ready Unit: percent.\0"
   /* 81871 */ "The percentage of time in which slice1 Xe core2 sampler input is available Unit: percent.\0"
   /* 81961 */ "The percentage of time in which slice1 Xe core2 sampler output is ready Unit: percent.\0"
   /* 82048 */ "The percentage of time in which slice1 Xe core3 sampler input is available Unit: percent.\0"
   /* 82138 */ "The percentage of time in which slice1 Xe core3 sampler output is ready Unit: percent.\0"
   /* 82225 */ "The percentage of time in which slice1 pixel values are ready Unit: percent.\0"
   /* 82302 */ "The percentage of time in which slice1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 82428 */ "The percentage of time in which slice1 rasterizer input is available Unit: percent.\0"
   /* 82512 */ "The percentage of time in which slice1 rasterizer output is ready Unit: percent.\0"
   /* 82593 */ "The percentage of time in which slice1 subslice0 sampler input is available Unit: percent.\0"
   /* 82684 */ "The percentage of time in which slice1 subslice0 sampler output is ready Unit: percent.\0"
   /* 82772 */ "The percentage of time in which slice1 subslice1 sampler input is available Unit: percent.\0"
   /* 82863 */ "The percentage of time in which slice1 subslice1 sampler output is ready Unit: percent.\0"
   /* 82951 */ "The percentage of time in which slice1 subslice2 sampler input is available Unit: percent.\0"
   /* 83042 */ "The percentage of time in which slice1 subslice2 sampler output is ready Unit: percent.\0"
   /* 83130 */ "The percentage of time in which slice2  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 83263 */ "The percentage of time in which slice2  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 83396 */ "The percentage of time in which slice2 Xe core0 sampler input is available Unit: percent.\0"
   /* 83486 */ "The percentage of time in which slice2 Xe core0 sampler output is ready Unit: percent.\0"
   /* 83573 */ "The percentage of time in which slice2 Xe core1 sampler input is available Unit: percent.\0"
   /* 83663 */ "The percentage of time in which slice2 Xe core1 sampler output is ready Unit: percent.\0"
   /* 83750 */ "The percentage of time in which slice2 Xe core2 sampler input is available Unit: percent.\0"
   /* 83840 */ "The percentage of time in which slice2 Xe core2 sampler output is ready Unit: percent.\0"
   /* 83927 */ "The percentage of time in which slice2 Xe core3 sampler input is available Unit: percent.\0"
   /* 84017 */ "The percentage of time in which slice2 Xe core3 sampler output is ready Unit: percent.\0"
   /* 84104 */ "The percentage of time in which slice2 rasterizer input is available Unit: percent.\0"
   /* 84188 */ "The percentage of time in which slice2 rasterizer output is ready Unit: percent.\0"
   /* 84269 */ "The percentage of time in which slice3  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 84402 */ "The percentage of time in which slice3  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 84535 */ "The percentage of time in which slice3 Xe core0 sampler input is available Unit: percent.\0"
   /* 84625 */ "The percentage of time in which slice3 Xe core0 sampler output is ready Unit: percent.\0"
   /* 84712 */ "The percentage of time in which slice3 Xe core1 sampler input is available Unit: percent.\0"
   /* 84802 */ "The percentage of time in which slice3 Xe core1 sampler output is ready Unit: percent.\0"
   /* 84889 */ "The percentage of time in which slice3 Xe core2 sampler input is available Unit: percent.\0"
   /* 84979 */ "The percentage of time in which slice3 Xe core2 sampler output is ready Unit: percent.\0"
   /* 85066 */ "The percentage of time in which slice3 Xe core3 sampler input is available Unit: percent.\0"
   /* 85156 */ "The percentage of time in which slice3 Xe core3 sampler output is ready Unit: percent.\0"
   /* 85243 */ "The percentage of time in which slice3 rasterizer input is available Unit: percent.\0"
   /* 85327 */ "The percentage of time in which slice3 rasterizer output is ready Unit: percent.\0"
   /* 85408 */ "The percentage of time in which slice4  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 85541 */ "The percentage of time in which slice4  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 85674 */ "The percentage of time in which slice4 Xe core0 sampler input is available Unit: percent.\0"
   /* 85764 */ "The percentage of time in which slice4 Xe core0 sampler output is ready Unit: percent.\0"
   /* 85851 */ "The percentage of time in which slice4 Xe core1 sampler input is available Unit: percent.\0"
   /* 85941 */ "The percentage of time in which slice4 Xe core1 sampler output is ready Unit: percent.\0"
   /* 86028 */ "The percentage of time in which slice4 Xe core2 sampler input is available Unit: percent.\0"
   /* 86118 */ "The percentage of time in which slice4 Xe core2 sampler output is ready Unit: percent.\0"
   /* 86205 */ "The percentage of time in which slice4 Xe core3 sampler input is available Unit: percent.\0"
   /* 86295 */ "The percentage of time in which slice4 Xe core3 sampler output is ready Unit: percent.\0"
   /* 86382 */ "The percentage of time in which slice4 rasterizer input is available Unit: percent.\0"
   /* 86466 */ "The percentage of time in which slice4 rasterizer output is ready Unit: percent.\0"
   /* 86547 */ "The percentage of time in which slice5  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 86680 */ "The percentage of time in which slice5  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 86813 */ "The percentage of time in which slice5 Xe core0 sampler input is available Unit: percent.\0"
   /* 86903 */ "The percentage of time in which slice5 Xe core0 sampler output is ready Unit: percent.\0"
   /* 86990 */ "The percentage of time in which slice5 Xe core1 sampler input is available Unit: percent.\0"
   /* 87080 */ "The percentage of time in which slice5 Xe core1 sampler output is ready Unit: percent.\0"
   /* 87167 */ "The percentage of time in which slice5 Xe core2 sampler input is available Unit: percent.\0"
   /* 87257 */ "The percentage of time in which slice5 Xe core2 sampler output is ready Unit: percent.\0"
   /* 87344 */ "The percentage of time in which slice5 Xe core3 sampler input is available Unit: percent.\0"
   /* 87434 */ "The percentage of time in which slice5 Xe core3 sampler output is ready Unit: percent.\0"
   /* 87521 */ "The percentage of time in which slice5 rasterizer input is available Unit: percent.\0"
   /* 87605 */ "The percentage of time in which slice5 rasterizer output is ready Unit: percent.\0"
   /* 87686 */ "The percentage of time in which slice6  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 87819 */ "The percentage of time in which slice6  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 87952 */ "The percentage of time in which slice6 Xe core0 sampler input is available Unit: percent.\0"
   /* 88042 */ "The percentage of time in which slice6 Xe core0 sampler output is ready Unit: percent.\0"
   /* 88129 */ "The percentage of time in which slice6 Xe core1 sampler input is available Unit: percent.\0"
   /* 88219 */ "The percentage of time in which slice6 Xe core1 sampler output is ready Unit: percent.\0"
   /* 88306 */ "The percentage of time in which slice6 Xe core2 sampler input is available Unit: percent.\0"
   /* 88396 */ "The percentage of time in which slice6 Xe core2 sampler output is ready Unit: percent.\0"
   /* 88483 */ "The percentage of time in which slice6 Xe core3 sampler input is available Unit: percent.\0"
   /* 88573 */ "The percentage of time in which slice6 Xe core3 sampler output is ready Unit: percent.\0"
   /* 88660 */ "The percentage of time in which slice6 rasterizer input is available Unit: percent.\0"
   /* 88744 */ "The percentage of time in which slice6 rasterizer output is ready Unit: percent.\0"
   /* 88825 */ "The percentage of time in which slice7  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 88958 */ "The percentage of time in which slice7  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.\0"
   /* 89091 */ "The percentage of time in which slice7 Xe core0 sampler input is available Unit: percent.\0"
   /* 89181 */ "The percentage of time in which slice7 Xe core0 sampler output is ready Unit: percent.\0"
   /* 89268 */ "The percentage of time in which slice7 Xe core1 sampler input is available Unit: percent.\0"
   /* 89358 */ "The percentage of time in which slice7 Xe core1 sampler output is ready Unit: percent.\0"
   /* 89445 */ "The percentage of time in which slice7 Xe core2 sampler input is available Unit: percent.\0"
   /* 89535 */ "The percentage of time in which slice7 Xe core2 sampler output is ready Unit: percent.\0"
   /* 89622 */ "The percentage of time in which slice7 Xe core3 sampler input is available Unit: percent.\0"
   /* 89712 */ "The percentage of time in which slice7 Xe core3 sampler output is ready Unit: percent.\0"
   /* 89799 */ "The percentage of time in which slice7 rasterizer input is available Unit: percent.\0"
   /* 89883 */ "The percentage of time in which slice7 rasterizer output is ready Unit: percent.\0"
   /* 89964 */ "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 90074 */ "The percentage of time in which stream-output pipeline stage was stalled. Unit: percent.\0"
   /* 90163 */ "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 90270 */ "The percentage of time in which strip-fans pipeline stage was stalled. Unit: percent.\0"
   /* 90356 */ "The percentage of time in which tessellation pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 90465 */ "The percentage of time in which the Execution Units were actively processing. Unit: percent.\0"
   /* 90558 */ "The percentage of time in which the Execution Units were idle. Unit: percent.\0"
   /* 90636 */ "The percentage of time in which the Execution Units were stalled. Unit: percent.\0"
   /* 90717 */ "The percentage of time in which the GPU has been processing GPU commands. Unit: percent.\0"
   /* 90806 */ "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher Unit: percent.\0"
   /* 90913 */ "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 0 Unit: percent.\0"
   /* 91027 */ "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 1 Unit: percent.\0"
   /* 91141 */ "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 2 Unit: percent.\0"
   /* 91255 */ "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 3 Unit: percent.\0"
   /* 91369 */ "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher Unit: percent.\0"
   /* 91476 */ "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 0 Unit: percent.\0"
   /* 91590 */ "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 1 Unit: percent.\0"
   /* 91704 */ "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 2 Unit: percent.\0"
   /* 91818 */ "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 3 Unit: percent.\0"
   /* 91932 */ "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher Unit: percent.\0"
   /* 92039 */ "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 0 Unit: percent.\0"
   /* 92153 */ "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 1 Unit: percent.\0"
   /* 92267 */ "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 2 Unit: percent.\0"
   /* 92381 */ "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 3 Unit: percent.\0"
   /* 92495 */ "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher Unit: percent.\0"
   /* 92602 */ "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 0 Unit: percent.\0"
   /* 92716 */ "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 1 Unit: percent.\0"
   /* 92830 */ "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 2 Unit: percent.\0"
   /* 92944 */ "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 3 Unit: percent.\0"
   /* 93058 */ "The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher Unit: percent.\0"
   /* 93170 */ "The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher port 0 Unit: percent.\0"
   /* 93289 */ "The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher port 1 Unit: percent.\0"
   /* 93408 */ "The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher port 2 Unit: percent.\0"
   /* 93527 */ "The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher port 3 Unit: percent.\0"
   /* 93646 */ "The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher Unit: percent.\0"
   /* 93758 */ "The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher port 0 Unit: percent.\0"
   /* 93877 */ "The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher port 1 Unit: percent.\0"
   /* 93996 */ "The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher port 2 Unit: percent.\0"
   /* 94115 */ "The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher port 3 Unit: percent.\0"
   /* 94234 */ "The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher Unit: percent.\0"
   /* 94346 */ "The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher port 0 Unit: percent.\0"
   /* 94465 */ "The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher port 1 Unit: percent.\0"
   /* 94584 */ "The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher port 2 Unit: percent.\0"
   /* 94703 */ "The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher port 3 Unit: percent.\0"
   /* 94822 */ "The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher Unit: percent.\0"
   /* 94934 */ "The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher port 0 Unit: percent.\0"
   /* 95053 */ "The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher port 1 Unit: percent.\0"
   /* 95172 */ "The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher port 2 Unit: percent.\0"
   /* 95291 */ "The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher port 3 Unit: percent.\0"
   /* 95410 */ "The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher Unit: percent.\0"
   /* 95522 */ "The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher port 0 Unit: percent.\0"
   /* 95641 */ "The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher port 1 Unit: percent.\0"
   /* 95760 */ "The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher port 2 Unit: percent.\0"
   /* 95879 */ "The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher port 3 Unit: percent.\0"
   /* 95998 */ "The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher Unit: percent.\0"
   /* 96110 */ "The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher port 0 Unit: percent.\0"
   /* 96229 */ "The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher port 1 Unit: percent.\0"
   /* 96348 */ "The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher port 2 Unit: percent.\0"
   /* 96467 */ "The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher port 3 Unit: percent.\0"
   /* 96586 */ "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0 Unit: percent.\0"
   /* 96701 */ "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1 Unit: percent.\0"
   /* 96816 */ "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0 Unit: percent.\0"
   /* 96931 */ "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1 Unit: percent.\0"
   /* 97046 */ "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0 Unit: percent.\0"
   /* 97161 */ "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1 Unit: percent.\0"
   /* 97276 */ "The percentage of time in which thread header is ready on slice0 subslice3 thread dispatcher port 0 Unit: percent.\0"
   /* 97391 */ "The percentage of time in which thread header is ready on slice0 subslice3 thread dispatcher port 1 Unit: percent.\0"
   /* 97506 */ "The percentage of time in which thread header is ready on slice0 subslice4 thread dispatcher port 0 Unit: percent.\0"
   /* 97621 */ "The percentage of time in which thread header is ready on slice0 subslice4 thread dispatcher port 1 Unit: percent.\0"
   /* 97736 */ "The percentage of time in which thread header is ready on slice0 subslice5 thread dispatcher port 0 Unit: percent.\0"
   /* 97851 */ "The percentage of time in which thread header is ready on slice0 subslice5 thread dispatcher port 1 Unit: percent.\0"
   /* 97966 */ "The percentage of time in which thread header is ready on slice0 subslice6 thread dispatcher port 0 Unit: percent.\0"
   /* 98081 */ "The percentage of time in which thread header is ready on slice0 subslice6 thread dispatcher port 1 Unit: percent.\0"
   /* 98196 */ "The percentage of time in which thread header is ready on slice0 subslice7 thread dispatcher port 0 Unit: percent.\0"
   /* 98311 */ "The percentage of time in which thread header is ready on slice0 subslice7 thread dispatcher port 1 Unit: percent.\0"
   /* 98426 */ "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher Unit: percent.\0"
   /* 98533 */ "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 0 Unit: percent.\0"
   /* 98647 */ "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 1 Unit: percent.\0"
   /* 98761 */ "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 2 Unit: percent.\0"
   /* 98875 */ "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 3 Unit: percent.\0"
   /* 98989 */ "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher Unit: percent.\0"
   /* 99096 */ "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 0 Unit: percent.\0"
   /* 99210 */ "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 1 Unit: percent.\0"
   /* 99324 */ "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 2 Unit: percent.\0"
   /* 99438 */ "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 3 Unit: percent.\0"
   /* 99552 */ "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher Unit: percent.\0"
   /* 99659 */ "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 0 Unit: percent.\0"
   /* 99773 */ "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 1 Unit: percent.\0"
   /* 99887 */ "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 2 Unit: percent.\0"
   /* 100001 */ "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 3 Unit: percent.\0"
   /* 100115 */ "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher Unit: percent.\0"
   /* 100222 */ "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 0 Unit: percent.\0"
   /* 100336 */ "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 1 Unit: percent.\0"
   /* 100450 */ "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 2 Unit: percent.\0"
   /* 100564 */ "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 3 Unit: percent.\0"
   /* 100678 */ "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 0 Unit: percent.\0"
   /* 100793 */ "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 1 Unit: percent.\0"
   /* 100908 */ "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 0 Unit: percent.\0"
   /* 101023 */ "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 1 Unit: percent.\0"
   /* 101138 */ "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 0 Unit: percent.\0"
   /* 101253 */ "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 1 Unit: percent.\0"
   /* 101368 */ "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher Unit: percent.\0"
   /* 101475 */ "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 0 Unit: percent.\0"
   /* 101589 */ "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 1 Unit: percent.\0"
   /* 101703 */ "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 2 Unit: percent.\0"
   /* 101817 */ "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 3 Unit: percent.\0"
   /* 101931 */ "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher Unit: percent.\0"
   /* 102038 */ "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 0 Unit: percent.\0"
   /* 102152 */ "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 1 Unit: percent.\0"
   /* 102266 */ "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 2 Unit: percent.\0"
   /* 102380 */ "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 3 Unit: percent.\0"
   /* 102494 */ "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher Unit: percent.\0"
   /* 102601 */ "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 0 Unit: percent.\0"
   /* 102715 */ "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 1 Unit: percent.\0"
   /* 102829 */ "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 2 Unit: percent.\0"
   /* 102943 */ "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 3 Unit: percent.\0"
   /* 103057 */ "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher Unit: percent.\0"
   /* 103164 */ "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 0 Unit: percent.\0"
   /* 103278 */ "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 1 Unit: percent.\0"
   /* 103392 */ "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 2 Unit: percent.\0"
   /* 103506 */ "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 3 Unit: percent.\0"
   /* 103620 */ "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher Unit: percent.\0"
   /* 103727 */ "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 0 Unit: percent.\0"
   /* 103841 */ "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 1 Unit: percent.\0"
   /* 103955 */ "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 2 Unit: percent.\0"
   /* 104069 */ "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 3 Unit: percent.\0"
   /* 104183 */ "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher Unit: percent.\0"
   /* 104290 */ "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 0 Unit: percent.\0"
   /* 104404 */ "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 1 Unit: percent.\0"
   /* 104518 */ "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 2 Unit: percent.\0"
   /* 104632 */ "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 3 Unit: percent.\0"
   /* 104746 */ "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher Unit: percent.\0"
   /* 104853 */ "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 0 Unit: percent.\0"
   /* 104967 */ "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 1 Unit: percent.\0"
   /* 105081 */ "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 2 Unit: percent.\0"
   /* 105195 */ "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 3 Unit: percent.\0"
   /* 105309 */ "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher Unit: percent.\0"
   /* 105416 */ "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 0 Unit: percent.\0"
   /* 105530 */ "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 1 Unit: percent.\0"
   /* 105644 */ "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 2 Unit: percent.\0"
   /* 105758 */ "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 3 Unit: percent.\0"
   /* 105872 */ "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher Unit: percent.\0"
   /* 105979 */ "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 0 Unit: percent.\0"
   /* 106093 */ "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 1 Unit: percent.\0"
   /* 106207 */ "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 2 Unit: percent.\0"
   /* 106321 */ "The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 3 Unit: percent.\0"
   /* 106435 */ "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher Unit: percent.\0"
   /* 106542 */ "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 0 Unit: percent.\0"
   /* 106656 */ "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 1 Unit: percent.\0"
   /* 106770 */ "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 2 Unit: percent.\0"
   /* 106884 */ "The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 3 Unit: percent.\0"
   /* 106998 */ "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher Unit: percent.\0"
   /* 107105 */ "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 0 Unit: percent.\0"
   /* 107219 */ "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 1 Unit: percent.\0"
   /* 107333 */ "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 2 Unit: percent.\0"
   /* 107447 */ "The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 3 Unit: percent.\0"
   /* 107561 */ "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher Unit: percent.\0"
   /* 107668 */ "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 0 Unit: percent.\0"
   /* 107782 */ "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 1 Unit: percent.\0"
   /* 107896 */ "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 2 Unit: percent.\0"
   /* 108010 */ "The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 3 Unit: percent.\0"
   /* 108124 */ "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher Unit: percent.\0"
   /* 108231 */ "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 0 Unit: percent.\0"
   /* 108345 */ "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 1 Unit: percent.\0"
   /* 108459 */ "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 2 Unit: percent.\0"
   /* 108573 */ "The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 3 Unit: percent.\0"
   /* 108687 */ "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher Unit: percent.\0"
   /* 108794 */ "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 0 Unit: percent.\0"
   /* 108908 */ "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 1 Unit: percent.\0"
   /* 109022 */ "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 2 Unit: percent.\0"
   /* 109136 */ "The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 3 Unit: percent.\0"
   /* 109250 */ "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher Unit: percent.\0"
   /* 109357 */ "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 0 Unit: percent.\0"
   /* 109471 */ "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 1 Unit: percent.\0"
   /* 109585 */ "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 2 Unit: percent.\0"
   /* 109699 */ "The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 3 Unit: percent.\0"
   /* 109813 */ "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher Unit: percent.\0"
   /* 109920 */ "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 0 Unit: percent.\0"
   /* 110034 */ "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 1 Unit: percent.\0"
   /* 110148 */ "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 2 Unit: percent.\0"
   /* 110262 */ "The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 3 Unit: percent.\0"
   /* 110376 */ "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher Unit: percent.\0"
   /* 110483 */ "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 0 Unit: percent.\0"
   /* 110597 */ "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 1 Unit: percent.\0"
   /* 110711 */ "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 2 Unit: percent.\0"
   /* 110825 */ "The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 3 Unit: percent.\0"
   /* 110939 */ "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher Unit: percent.\0"
   /* 111046 */ "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 0 Unit: percent.\0"
   /* 111160 */ "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 1 Unit: percent.\0"
   /* 111274 */ "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 2 Unit: percent.\0"
   /* 111388 */ "The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 3 Unit: percent.\0"
   /* 111502 */ "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher Unit: percent.\0"
   /* 111609 */ "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 0 Unit: percent.\0"
   /* 111723 */ "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 1 Unit: percent.\0"
   /* 111837 */ "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 2 Unit: percent.\0"
   /* 111951 */ "The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 3 Unit: percent.\0"
   /* 112065 */ "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher Unit: percent.\0"
   /* 112172 */ "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 0 Unit: percent.\0"
   /* 112286 */ "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 1 Unit: percent.\0"
   /* 112400 */ "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 2 Unit: percent.\0"
   /* 112514 */ "The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 3 Unit: percent.\0"
   /* 112628 */ "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher Unit: percent.\0"
   /* 112735 */ "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 0 Unit: percent.\0"
   /* 112849 */ "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 1 Unit: percent.\0"
   /* 112963 */ "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 2 Unit: percent.\0"
   /* 113077 */ "The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 3 Unit: percent.\0"
   /* 113191 */ "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher Unit: percent.\0"
   /* 113298 */ "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 0 Unit: percent.\0"
   /* 113412 */ "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 1 Unit: percent.\0"
   /* 113526 */ "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 2 Unit: percent.\0"
   /* 113640 */ "The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 3 Unit: percent.\0"
   /* 113754 */ "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher Unit: percent.\0"
   /* 113861 */ "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 0 Unit: percent.\0"
   /* 113975 */ "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 1 Unit: percent.\0"
   /* 114089 */ "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 2 Unit: percent.\0"
   /* 114203 */ "The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 3 Unit: percent.\0"
   /* 114317 */ "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher Unit: percent.\0"
   /* 114424 */ "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 0 Unit: percent.\0"
   /* 114538 */ "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 1 Unit: percent.\0"
   /* 114652 */ "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 2 Unit: percent.\0"
   /* 114766 */ "The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 3 Unit: percent.\0"
   /* 114880 */ "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 114989 */ "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline. Unit: percent.\0"
   /* 115099 */ "The percentage of time in which vertex shaders were processed actively on the EUs. Unit: percent.\0"
   /* 115197 */ "The percentage of time in which vertex shaders were stalled on the EUs. Unit: percent.\0"
   /* 115284 */ "The percentage of time when IDI0 SQ0 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 115385 */ "The percentage of time when IDI0 SQ00 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 115487 */ "The percentage of time when IDI0 SQ01 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 115589 */ "The percentage of time when IDI0 SQ1 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 115690 */ "The percentage of time when IDI0 SQ10 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 115792 */ "The percentage of time when IDI0 SQ11 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 115894 */ "The percentage of time when IDI0 SQ20 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 115996 */ "The percentage of time when IDI0 SQ30 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 116098 */ "The percentage of time when IDI0 SQ40 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 116200 */ "The percentage of time when IDI0 SQ50 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 116302 */ "The percentage of time when IDI0 SQ60 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 116404 */ "The percentage of time when IDI0 SQ70 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 116506 */ "The percentage of time when IDI1 SQ0 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 116607 */ "The percentage of time when IDI1 SQ1 is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 116708 */ "The percentage of time when SQ is filled above a threshold (usually 48 entries) Unit: percent.\0"
   /* 116803 */ "The percentage of time when Vdbox0 command streamer was busy. Unit: percent.\0"
   /* 116880 */ "The percentage of time when Vdbox1 command streamer was busy. Unit: percent.\0"
   /* 116957 */ "The percentage of time when any command streamer was busy. Unit: percent.\0"
   /* 117031 */ "The percentage of time when any compute engine is busy Unit: percent.\0"
   /* 117101 */ "The percentage of time when blitter command streamer was busy. Unit: percent.\0"
   /* 117179 */ "The percentage of time when compute command streamer 0 was busy. Unit: percent.\0"
   /* 117259 */ "The percentage of time when compute command streamer 1 was busy. Unit: percent.\0"
   /* 117339 */ "The percentage of time when compute command streamer 2 was busy. Unit: percent.\0"
   /* 117419 */ "The percentage of time when compute command streamer 3 was busy. Unit: percent.\0"
   /* 117499 */ "The percentage of time when posh command streamer was busy. Unit: percent.\0"
   /* 117574 */ "The percentage of time when render and any compute engines are simultaneously busy Unit: percent.\0"
   /* 117672 */ "The percentage of time when render and compute engines are simultaneously busy Unit: percent.\0"
   /* 117766 */ "The percentage of time when render command streamer was busy. Unit: percent.\0"
   /* 117843 */ "The percentage of time when sampler slice0 Xe core0 is busy Unit: percent.\0"
   /* 117918 */ "The percentage of time when sampler slice0 dualsubslice0 is bottleneck Unit: percent.\0"
   /* 118004 */ "The percentage of time when sampler slice2 Xe core0 is busy Unit: percent.\0"
   /* 118079 */ "The percentage of time when vdbox00 command streamer was busy. Unit: percent.\0"
   /* 118157 */ "The percentage of time when vdbox10 command streamer was busy. Unit: percent.\0"
   /* 118235 */ "The percentage of time when vebox command streamer was busy. Unit: percent.\0"
   /* 118311 */ "The percentage of time when vebox0 command streamer was busy. Unit: percent.\0"
   /* 118388 */ "The percentage of time when vebox1 command streamer was busy. Unit: percent.\0"
   /* 118465 */ "The ratio of EU typed atomics requests to L3 cache line writes. \0"
   /* 118530 */ "The ratio of EU typed read requests to L3 cache line reads. \0"
   /* 118591 */ "The ratio of EU typed write requests to L3 cache line writes. \0"
   /* 118654 */ "The ratio of EU untyped read requests to L3 cache line reads. \0"
   /* 118717 */ "The ratio of EU untyped write requests to L3 cache line writes. \0"
   /* 118782 */ "The subslice 0 Data Port data and constant reads from L3 cache. Unit: messages.\0"
   /* 118862 */ "The subslice 0 Data Port data writes to L3 cache. Unit: messages.\0"
   /* 118928 */ "The subslice 0 Data Port reads from L3 cache. Unit: messages.\0"
   /* 118990 */ "The subslice 0 Data Port writes to L3 cache. Unit: messages.\0"
   /* 119051 */ "The subslice 0 EU A64 Untyped Reads subslice 0. Unit: messages.\0"
   /* 119115 */ "The subslice 0 EU A64 Untyped Writes subslice 0. Unit: messages.\0"
   /* 119180 */ "The subslice 0 EU Typed Atomics subslice 0. Unit: messages.\0"
   /* 119240 */ "The subslice 0 EU Typed Reads subslice 0. Unit: messages.\0"
   /* 119298 */ "The subslice 0 EU Typed Writes subslice 0. Unit: messages.\0"
   /* 119357 */ "The subslice 0 EU URB Atomics subslice 0. Unit: messages.\0"
   /* 119415 */ "The subslice 0 EU Untyped Atomics subslice 0. Unit: messages.\0"
   /* 119477 */ "The subslice 0 EU Untyped Reads subslice 0. Unit: messages.\0"
   /* 119537 */ "The subslice 0 EU Untyped Writes subslice 0. Unit: messages.\0"
   /* 119598 */ "The subslice 0 EU data reads from Data Port with 128B per message. Unit: messages.\0"
   /* 119681 */ "The subslice 0 EU data reads from Data Port with 256B per message. Unit: messages.\0"
   /* 119764 */ "The subslice 0 EU data reads from Data Port with 32B per message. Unit: messages.\0"
   /* 119846 */ "The subslice 0 EU data reads from Data Port with 64B per message. Unit: messages.\0"
   /* 119928 */ "The subslice 0 EU data simd16 writes to Data Port with 128B per message. Unit: messages.\0"
   /* 120017 */ "The subslice 0 EU data simd16 writes to Data Port with 192B per message. Unit: messages.\0"
   /* 120106 */ "The subslice 0 EU data simd16 writes to Data Port with 256B per message. Unit: messages.\0"
   /* 120195 */ "The subslice 0 EU data writes to Data Port with 128B per message. Unit: messages.\0"
   /* 120277 */ "The subslice 0 EU data writes to Data Port with 32B per message. Unit: messages.\0"
   /* 120358 */ "The subslice 0 EU data writes to Data Port with 64B per message. Unit: messages.\0"
   /* 120439 */ "The subslice 0 typed atomics. Unit: messages.\0"
   /* 120485 */ "The subslice 0 typed reads. Unit: messages.\0"
   /* 120529 */ "The subslice 0 typed writes. Unit: messages.\0"
   /* 120574 */ "The subslice 0 untyped reads (including SLM reads). Unit: messages.\0"
   /* 120642 */ "The subslice 0 untyped writes (including SLM writes). Unit: messages.\0"
   /* 120712 */ "The total number of GPU core clocks elapsed during the measurement. Unit: cycles.\0"
   /* 120794 */ "The total number of GPU memory bytes read from GTI. Unit: bytes.\0"
   /* 120859 */ "The total number of GPU memory bytes read from shared local memory. Unit: bytes.\0"
   /* 120940 */ "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI. Unit: bytes.\0"
   /* 121084 */ "The total number of GPU memory bytes transferred between GPU and LLC. Unit: bytes.\0"
   /* 121167 */ "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups. Unit: bytes.\0"
   /* 121281 */ "The total number of GPU memory bytes transferred between GTI and Uncore ring. Unit: bytes.\0"
   /* 121372 */ "The total number of GPU memory bytes transferred between L3 caches and GTI. Unit: bytes.\0"
   /* 121461 */ "The total number of GPU memory bytes transferred between depth caches and GTI. Unit: bytes.\0"
   /* 121553 */ "The total number of GPU memory bytes transferred between render color caches and GTI. Unit: bytes.\0"
   /* 121652 */ "The total number of GPU memory bytes transferred between samplers and L3 caches. Unit: bytes.\0"
   /* 121746 */ "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB. Unit: bytes.\0"
   /* 121847 */ "The total number of GPU memory bytes transferred via L3. Unit: bytes.\0"
   /* 121917 */ "The total number of GPU memory bytes written into shared local memory. Unit: bytes.\0"
   /* 122001 */ "The total number of GPU memory bytes written to GTI. Unit: bytes.\0"
   /* 122067 */ "The total number of GTI memory reads (64B each). Unit: messages.\0"
   /* 122132 */ "The total number of GTI memory reads from Command Streamer. Unit: messages.\0"
   /* 122208 */ "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses). Unit: messages.\0"
   /* 122316 */ "The total number of GTI memory reads from Hierarchical Depth Cache. Unit: messages.\0"
   /* 122400 */ "The total number of GTI memory reads from L3 (L3 Cache misses). Unit: messages.\0"
   /* 122480 */ "The total number of GTI memory reads from L3 (L3 misses). Unit: messages.\0"
   /* 122554 */ "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses). Unit: messages.\0"
   /* 122641 */ "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses). Unit: messages.\0"
   /* 122728 */ "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses). Unit: messages.\0"
   /* 122815 */ "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses). Unit: messages.\0"
   /* 122902 */ "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses). Unit: messages.\0"
   /* 123022 */ "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses). Unit: messages.\0"
   /* 123128 */ "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses). Unit: messages.\0"
   /* 123234 */ "The total number of GTI memory reads from Render Depth Cache. Unit: messages.\0"
   /* 123312 */ "The total number of GTI memory reads from Resource Streamer. Unit: messages.\0"
   /* 123389 */ "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses). Unit: messages.\0"
   /* 123485 */ "The total number of GTI memory reads from Stencil Cache. Unit: messages.\0"
   /* 123558 */ "The total number of GTI memory reads from Vertex Fetch. Unit: messages.\0"
   /* 123630 */ "The total number of GTI memory reads. Unit: messages.\0"
   /* 123684 */ "The total number of GTI memory writes (64B each). Unit: messages.\0"
   /* 123750 */ "The total number of GTI memory writes from Command Streamer. Unit: messages.\0"
   /* 123827 */ "The total number of GTI memory writes from Hierarchical Depth Cache. Unit: messages.\0"
   /* 123912 */ "The total number of GTI memory writes from L3 (L3 invalidations). Unit: messages.\0"
   /* 123994 */ "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations). Unit: messages.\0"
   /* 124090 */ "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations). Unit: messages.\0"
   /* 124186 */ "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations). Unit: messages.\0"
   /* 124282 */ "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations). Unit: messages.\0"
   /* 124378 */ "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations). Unit: messages.\0"
   /* 124506 */ "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations). Unit: messages.\0"
   /* 124620 */ "The total number of GTI memory writes from Render Depth Cache. Unit: messages.\0"
   /* 124699 */ "The total number of GTI memory writes from Stencil Cache. Unit: messages.\0"
   /* 124773 */ "The total number of GTI memory writes from Stream Output. Unit: messages.\0"
   /* 124847 */ "The total number of GTI memory writes. Unit: messages.\0"
   /* 124902 */ "The total number of L3 accesses from all entities. Unit: messages.\0"
   /* 124969 */ "The total number of L3 cache lookup accesses w/o IC. Unit: messages.\0"
   /* 125038 */ "The total number of L3 misses. Unit: messages.\0"
   /* 125085 */ "The total number of LLC cache lookups done from the GPU (64b reads, 32B writes). Unit: messages.\0"
   /* 125182 */ "The total number of LLC cache lookups for reads done from the GPU. Unit: messages.\0"
   /* 125265 */ "The total number of LLC cache lookups for write done from the GPU (32B writes). Unit: messages.\0"
   /* 125361 */ "The total number of accesses to L3 Bank 00 from IC cache. Unit: messages.\0"
   /* 125435 */ "The total number of accesses to L3 Bank 00. Unit: messages.\0"
   /* 125495 */ "The total number of accesses to L3 Bank 01. Unit: messages.\0"
   /* 125555 */ "The total number of accesses to L3 Bank 02. Unit: messages.\0"
   /* 125615 */ "The total number of accesses to L3 Bank 03. Unit: messages.\0"
   /* 125675 */ "The total number of accesses to L3 Bank 10 from IC cache. Unit: messages.\0"
   /* 125749 */ "The total number of accesses to L3 Bank 10. Unit: messages.\0"
   /* 125809 */ "The total number of accesses to L3 Bank 11. Unit: messages.\0"
   /* 125869 */ "The total number of accesses to L3 Bank 12. Unit: messages.\0"
   /* 125929 */ "The total number of accesses to L3 Bank 13. Unit: messages.\0"
   /* 125989 */ "The total number of accesses to Slice0 L3 Bank0. Unit: messages.\0"
   /* 126054 */ "The total number of accesses to Slice0 L3 Bank1. Unit: messages.\0"
   /* 126119 */ "The total number of accesses to Slice0 L3 Bank2. Unit: messages.\0"
   /* 126184 */ "The total number of accesses to Slice0 L3 Bank3. Unit: messages.\0"
   /* 126249 */ "The total number of accesses to Slice0 L3 Bank4. Unit: messages.\0"
   /* 126314 */ "The total number of accesses to Slice0 L3 Bank5. Unit: messages.\0"
   /* 126379 */ "The total number of accesses to Slice0 L3 Bank6. Unit: messages.\0"
   /* 126444 */ "The total number of accesses to Slice0 L3 Bank7. Unit: messages.\0"
   /* 126509 */ "The total number of all GTI accesses to the ring. Unit: messages.\0"
   /* 126575 */ "The total number of all accesses from GTI to the ring. Unit: messages.\0"
   /* 126646 */ "The total number of blended samples or pixels written to all render targets. Unit: pixels.\0"
   /* 126737 */ "The total number of byten written into shared local memory. Unit: bytes.\0"
   /* 126810 */ "The total number of compute shader hardware threads dispatched. Unit: threads.\0"
   /* 126889 */ "The total number of control shader hardware threads dispatched. Unit: threads.\0"
   /* 126968 */ "The total number of domain shader hardware threads dispatched. Unit: threads.\0"
   /* 127046 */ "The total number of evaluation shader hardware threads dispatched. Unit: threads.\0"
   /* 127128 */ "The total number of fragment shader hardware threads dispatched. Unit: threads.\0"
   /* 127208 */ "The total number of geometry shader hardware threads dispatched. Unit: threads.\0"
   /* 127288 */ "The total number of hits in L3 Bank 00 from IC cache. Unit: messages.\0"
   /* 127358 */ "The total number of hits in L3 Bank 10 from IC cache. Unit: messages.\0"
   /* 127428 */ "The total number of hull shader hardware threads dispatched. Unit: threads.\0"
   /* 127504 */ "The total number of messages send to samplers. Unit: messages.\0"
   /* 127567 */ "The total number of pixels dropped on early depth test. Unit: events.\0"
   /* 127637 */ "The total number of pixels dropped on early depth test. Unit: pixels.\0"
   /* 127707 */ "The total number of pixels dropped on early hierarchical depth test. Unit: pixels.\0"
   /* 127790 */ "The total number of pixels dropped on post-FS alpha test. Unit: pixels.\0"
   /* 127862 */ "The total number of pixels dropped on post-FS alpha, stencil, or depth tests. Unit: pixels.\0"
   /* 127954 */ "The total number of pixels dropped on post-FS depth test. Unit: pixels.\0"
   /* 128026 */ "The total number of pixels dropped on post-FS stencil test. Unit: pixels.\0"
   /* 128100 */ "The total number of rasterized pixels. Unit: pixels.\0"
   /* 128153 */ "The total number of reads from shared local memory. Unit: messages.\0"
   /* 128221 */ "The total number of sampler cache misses in all LODs in all sampler units. Unit: messages.\0"
   /* 128312 */ "The total number of samples or pixels dropped in fragment shaders. Unit: pixels.\0"
   /* 128393 */ "The total number of samples or pixels written to all render targets. Unit: pixels.\0"
   /* 128476 */ "The total number of shader atomic memory accesses. Unit: messages.\0"
   /* 128543 */ "The total number of shader barrier messages. Unit: messages.\0"
   /* 128604 */ "The total number of shader memory accesses to L3. Unit: messages.\0"
   /* 128670 */ "The total number of successful LLC cache lookups done from the GPU. Unit: messages.\0"
   /* 128754 */ "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache. Unit: texels.\0"
   /* 128853 */ "The total number of texels lookups in LOD0 in all sampler units. Unit: texels.\0"
   /* 128932 */ "The total number of texels lookups in LOD0 in sampler 0 unit. Unit: texels.\0"
   /* 129008 */ "The total number of texels lookups in LOD0 in sampler 1 unit. Unit: texels.\0"
   /* 129084 */ "The total number of texels seen on input (with 2x2 accuracy) in all sampler units. Unit: texels.\0"
   /* 129181 */ "The total number of typed atomic accesses via Data Port. Unit: events.\0"
   /* 129252 */ "The total number of typed atomics. Unit: messages.\0"
   /* 129303 */ "The total number of typed memory bytes read via Data Port. Unit: bytes.\0"
   /* 129375 */ "The total number of typed memory bytes written via Data Port. Unit: bytes.\0"
   /* 129450 */ "The total number of untyped memory bytes written via Data Port. Unit: bytes.\0"
   /* 129527 */ "The total number of vertex shader hardware threads dispatched. Unit: threads.\0"
   /* 129605 */ "The total number of writes into shared local memory. Unit: messages.\0"
   /* 129674 */ "Time elapsed on the GPU during the measurement. Unit: ns.\0"
   /* 129732 */ "Total Compute Shader GPU duration. Unit: us.\0"
   /* 129777 */ "Total Control Shader GPU duration. Unit: us.\0"
   /* 129822 */ "Total Evaluation Shader GPU duration. Unit: us.\0"
   /* 129870 */ "Total Fragment Shader GPU duration. Unit: us.\0"
   /* 129916 */ "Total Geometry Shader GPU duration. Unit: us.\0"
   /* 129962 */ "Total Vertex Shader GPU duration. Unit: us.\0"
};

static const char symbol_name[] = {
   /* 0 */ "AMFS_4X4_SHADING_REQUEST_SLICE0\0"
   /* 32 */ "AMFS_4X4_SHADING_REQUEST_SLICE1\0"
   /* 64 */ "AMFS_4X4_SHADING_REQUEST_SLICE2\0"
   /* 96 */ "AMFS_4X4_SHADING_REQUEST_SLICE3\0"
   /* 128 */ "AMFS_4X4_SHADING_REQUEST_SLICE4\0"
   /* 160 */ "AMFS_4X4_SHADING_REQUEST_SLICE5\0"
   /* 192 */ "AMFS_4X4_SHADING_REQUEST_SLICE6\0"
   /* 224 */ "AMFS_4X4_SHADING_REQUEST_SLICE7\0"
   /* 256 */ "AMFS_CACHE_HIT_SLICE0\0"
   /* 278 */ "AMFS_CACHE_HIT_SLICE1\0"
   /* 300 */ "AMFS_CACHE_HIT_SLICE2\0"
   /* 322 */ "AMFS_CACHE_HIT_SLICE3\0"
   /* 344 */ "AMFS_CACHE_HIT_SLICE4\0"
   /* 366 */ "AMFS_CACHE_HIT_SLICE5\0"
   /* 388 */ "AMFS_CACHE_HIT_SLICE6\0"
   /* 410 */ "AMFS_CACHE_HIT_SLICE7\0"
   /* 432 */ "AMFS_CACHE_MISS_SLICE0\0"
   /* 455 */ "AMFS_CACHE_MISS_SLICE1\0"
   /* 478 */ "AMFS_CACHE_MISS_SLICE2\0"
   /* 501 */ "AMFS_CACHE_MISS_SLICE3\0"
   /* 524 */ "AMFS_CACHE_MISS_SLICE4\0"
   /* 547 */ "AMFS_CACHE_MISS_SLICE5\0"
   /* 570 */ "AMFS_CACHE_MISS_SLICE6\0"
   /* 593 */ "AMFS_CACHE_MISS_SLICE7\0"
   /* 616 */ "AMFS_L3_ACCESS_SLICE0\0"
   /* 638 */ "AMFS_L3_ACCESS_SLICE1\0"
   /* 660 */ "AMFS_L3_ACCESS_SLICE2\0"
   /* 682 */ "AMFS_L3_ACCESS_SLICE3\0"
   /* 704 */ "AMFS_L3_ACCESS_SLICE4\0"
   /* 726 */ "AMFS_L3_ACCESS_SLICE5\0"
   /* 748 */ "AMFS_L3_ACCESS_SLICE6\0"
   /* 770 */ "AMFS_L3_ACCESS_SLICE7\0"
   /* 792 */ "AMFS_L3_ATOMIC_SLICE0\0"
   /* 814 */ "AMFS_L3_ATOMIC_SLICE1\0"
   /* 836 */ "AMFS_L3_ATOMIC_SLICE2\0"
   /* 858 */ "AMFS_L3_ATOMIC_SLICE3\0"
   /* 880 */ "AMFS_L3_ATOMIC_SLICE4\0"
   /* 902 */ "AMFS_L3_ATOMIC_SLICE5\0"
   /* 924 */ "AMFS_L3_ATOMIC_SLICE6\0"
   /* 946 */ "AMFS_L3_ATOMIC_SLICE7\0"
   /* 968 */ "AMFS_L3_WRITE_SLICE0\0"
   /* 989 */ "AMFS_L3_WRITE_SLICE1\0"
   /* 1010 */ "AMFS_L3_WRITE_SLICE2\0"
   /* 1031 */ "AMFS_L3_WRITE_SLICE3\0"
   /* 1052 */ "AMFS_L3_WRITE_SLICE4\0"
   /* 1073 */ "AMFS_L3_WRITE_SLICE5\0"
   /* 1094 */ "AMFS_L3_WRITE_SLICE6\0"
   /* 1115 */ "AMFS_L3_WRITE_SLICE7\0"
   /* 1136 */ "AMFS_STALL_ALL_INPUT_SLICE0\0"
   /* 1164 */ "AMFS_STALL_ALL_INPUT_SLICE1\0"
   /* 1192 */ "AMFS_STALL_ALL_INPUT_SLICE2\0"
   /* 1220 */ "AMFS_STALL_ALL_INPUT_SLICE3\0"
   /* 1248 */ "AMFS_STALL_ALL_INPUT_SLICE4\0"
   /* 1276 */ "AMFS_STALL_ALL_INPUT_SLICE5\0"
   /* 1304 */ "AMFS_STALL_ALL_INPUT_SLICE6\0"
   /* 1332 */ "AMFS_STALL_ALL_INPUT_SLICE7\0"
   /* 1360 */ "AMFS_STALL_ANY_INPUT_SLICE0\0"
   /* 1388 */ "AMFS_STALL_ANY_INPUT_SLICE1\0"
   /* 1416 */ "AMFS_STALL_ANY_INPUT_SLICE2\0"
   /* 1444 */ "AMFS_STALL_ANY_INPUT_SLICE3\0"
   /* 1472 */ "AMFS_STALL_ANY_INPUT_SLICE4\0"
   /* 1500 */ "AMFS_STALL_ANY_INPUT_SLICE5\0"
   /* 1528 */ "AMFS_STALL_ANY_INPUT_SLICE6\0"
   /* 1556 */ "AMFS_STALL_ANY_INPUT_SLICE7\0"
   /* 1584 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0\0"
   /* 1622 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1\0"
   /* 1660 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE10\0"
   /* 1699 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE11\0"
   /* 1738 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE12\0"
   /* 1777 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE13\0"
   /* 1816 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE14\0"
   /* 1855 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE15\0"
   /* 1894 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE16\0"
   /* 1933 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE17\0"
   /* 1972 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE18\0"
   /* 2011 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE19\0"
   /* 2050 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2\0"
   /* 2088 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE20\0"
   /* 2127 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE21\0"
   /* 2166 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE22\0"
   /* 2205 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE23\0"
   /* 2244 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE24\0"
   /* 2283 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE25\0"
   /* 2322 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE26\0"
   /* 2361 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE27\0"
   /* 2400 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE28\0"
   /* 2439 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE29\0"
   /* 2478 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3\0"
   /* 2516 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE30\0"
   /* 2555 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE31\0"
   /* 2594 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4\0"
   /* 2632 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5\0"
   /* 2670 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6\0"
   /* 2708 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7\0"
   /* 2746 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE8\0"
   /* 2784 */ "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE9\0"
   /* 2822 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0\0"
   /* 2860 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1\0"
   /* 2898 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE10\0"
   /* 2937 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE11\0"
   /* 2976 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE12\0"
   /* 3015 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE13\0"
   /* 3054 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE14\0"
   /* 3093 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE15\0"
   /* 3132 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE16\0"
   /* 3171 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE17\0"
   /* 3210 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE18\0"
   /* 3249 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE19\0"
   /* 3288 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2\0"
   /* 3326 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE20\0"
   /* 3365 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE21\0"
   /* 3404 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE22\0"
   /* 3443 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE23\0"
   /* 3482 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE24\0"
   /* 3521 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE25\0"
   /* 3560 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE26\0"
   /* 3599 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE27\0"
   /* 3638 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE28\0"
   /* 3677 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE29\0"
   /* 3716 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3\0"
   /* 3754 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE30\0"
   /* 3793 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE31\0"
   /* 3832 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4\0"
   /* 3870 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5\0"
   /* 3908 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6\0"
   /* 3946 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7\0"
   /* 3984 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE8\0"
   /* 4022 */ "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE9\0"
   /* 4060 */ "AlphaTestFails\0"
   /* 4075 */ "AnyComputeEngineBusy\0"
   /* 4096 */ "AnyEngineBusy\0"
   /* 4110 */ "AnyRingBusy\0"
   /* 4122 */ "AsyncCsEmActive\0"
   /* 4138 */ "AsyncCsFpuActive\0"
   /* 4155 */ "AvgGpuCoreFrequency\0"
   /* 4175 */ "Bc00Bottleneck\0"
   /* 4190 */ "Bc10Bottleneck\0"
   /* 4205 */ "Bc20Bottleneck\0"
   /* 4220 */ "Bc30Bottleneck\0"
   /* 4235 */ "Bc40Bottleneck\0"
   /* 4250 */ "Bc50Bottleneck\0"
   /* 4265 */ "Bc60Bottleneck\0"
   /* 4280 */ "Bc70Bottleneck\0"
   /* 4295 */ "BcBottleneck\0"
   /* 4308 */ "BlitterBusy\0"
   /* 4320 */ "CLIPPER_INPUT_AVAILABLE_SLICE0\0"
   /* 4351 */ "CLIPPER_INPUT_AVAILABLE_SLICE1\0"
   /* 4382 */ "CLIPPER_INPUT_AVAILABLE_SLICE2\0"
   /* 4413 */ "CLIPPER_INPUT_AVAILABLE_SLICE3\0"
   /* 4444 */ "CLIPPER_INPUT_AVAILABLE_SLICE4\0"
   /* 4475 */ "CLIPPER_INPUT_AVAILABLE_SLICE5\0"
   /* 4506 */ "CLIPPER_INPUT_AVAILABLE_SLICE6\0"
   /* 4537 */ "CLIPPER_INPUT_AVAILABLE_SLICE7\0"
   /* 4568 */ "CLIPPER_INPUT_VERTEX_SLICE0\0"
   /* 4596 */ "CLIPPER_INPUT_VERTEX_SLICE1\0"
   /* 4624 */ "CLIPPER_INPUT_VERTEX_SLICE2\0"
   /* 4652 */ "CLIPPER_INPUT_VERTEX_SLICE3\0"
   /* 4680 */ "CLIPPER_INPUT_VERTEX_SLICE4\0"
   /* 4708 */ "CLIPPER_INPUT_VERTEX_SLICE5\0"
   /* 4736 */ "CLIPPER_INPUT_VERTEX_SLICE6\0"
   /* 4764 */ "CLIPPER_INPUT_VERTEX_SLICE7\0"
   /* 4792 */ "CLIPPER_OUTPUT_READY_SLICE0\0"
   /* 4820 */ "CLIPPER_OUTPUT_READY_SLICE1\0"
   /* 4848 */ "CLIPPER_OUTPUT_READY_SLICE2\0"
   /* 4876 */ "CLIPPER_OUTPUT_READY_SLICE3\0"
   /* 4904 */ "CLIPPER_OUTPUT_READY_SLICE4\0"
   /* 4932 */ "CLIPPER_OUTPUT_READY_SLICE5\0"
   /* 4960 */ "CLIPPER_OUTPUT_READY_SLICE6\0"
   /* 4988 */ "CLIPPER_OUTPUT_READY_SLICE7\0"
   /* 5016 */ "CLIPPER_PRIMITIVE_CULL_SLICE0\0"
   /* 5046 */ "CLIPPER_PRIMITIVE_CULL_SLICE1\0"
   /* 5076 */ "CLIPPER_PRIMITIVE_CULL_SLICE2\0"
   /* 5106 */ "CLIPPER_PRIMITIVE_CULL_SLICE3\0"
   /* 5136 */ "CLIPPER_PRIMITIVE_CULL_SLICE4\0"
   /* 5166 */ "CLIPPER_PRIMITIVE_CULL_SLICE5\0"
   /* 5196 */ "CLIPPER_PRIMITIVE_CULL_SLICE6\0"
   /* 5226 */ "CLIPPER_PRIMITIVE_CULL_SLICE7\0"
   /* 5256 */ "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0\0"
   /* 5295 */ "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1\0"
   /* 5334 */ "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE2\0"
   /* 5373 */ "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE3\0"
   /* 5412 */ "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE4\0"
   /* 5451 */ "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE5\0"
   /* 5490 */ "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE6\0"
   /* 5529 */ "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE7\0"
   /* 5568 */ "CLIPPER_PRIMITIVE_OUTPUT_SLICE0\0"
   /* 5600 */ "CLIPPER_PRIMITIVE_OUTPUT_SLICE1\0"
   /* 5632 */ "CLIPPER_PRIMITIVE_OUTPUT_SLICE2\0"
   /* 5664 */ "CLIPPER_PRIMITIVE_OUTPUT_SLICE3\0"
   /* 5696 */ "CLIPPER_PRIMITIVE_OUTPUT_SLICE4\0"
   /* 5728 */ "CLIPPER_PRIMITIVE_OUTPUT_SLICE5\0"
   /* 5760 */ "CLIPPER_PRIMITIVE_OUTPUT_SLICE6\0"
   /* 5792 */ "CLIPPER_PRIMITIVE_OUTPUT_SLICE7\0"
   /* 5824 */ "CLIPPER_TRANSACTION_OUTPUT_SLICE0\0"
   /* 5858 */ "CLIPPER_TRANSACTION_OUTPUT_SLICE1\0"
   /* 5892 */ "CLIPPER_TRANSACTION_OUTPUT_SLICE2\0"
   /* 5926 */ "CLIPPER_TRANSACTION_OUTPUT_SLICE3\0"
   /* 5960 */ "CLIPPER_TRANSACTION_OUTPUT_SLICE4\0"
   /* 5994 */ "CLIPPER_TRANSACTION_OUTPUT_SLICE5\0"
   /* 6028 */ "CLIPPER_TRANSACTION_OUTPUT_SLICE6\0"
   /* 6062 */ "CLIPPER_TRANSACTION_OUTPUT_SLICE7\0"
   /* 6096 */ "COLOR_L3_ACCESS_L3BANK0\0"
   /* 6120 */ "COLOR_L3_ACCESS_L3BANK1\0"
   /* 6144 */ "COLOR_L3_ACCESS_L3BANK2\0"
   /* 6168 */ "COLOR_L3_ACCESS_L3BANK3\0"
   /* 6192 */ "COLOR_L3_ACCESS_L3BANK4\0"
   /* 6216 */ "COLOR_L3_ACCESS_L3BANK5\0"
   /* 6240 */ "COLOR_L3_ACCESS_L3BANK6\0"
   /* 6264 */ "COLOR_L3_ACCESS_L3BANK7\0"
   /* 6288 */ "COLOR_L3_HIT_L3BANK0\0"
   /* 6309 */ "COLOR_L3_HIT_L3BANK1\0"
   /* 6330 */ "COLOR_L3_HIT_L3BANK10\0"
   /* 6352 */ "COLOR_L3_HIT_L3BANK11\0"
   /* 6374 */ "COLOR_L3_HIT_L3BANK12\0"
   /* 6396 */ "COLOR_L3_HIT_L3BANK13\0"
   /* 6418 */ "COLOR_L3_HIT_L3BANK14\0"
   /* 6440 */ "COLOR_L3_HIT_L3BANK15\0"
   /* 6462 */ "COLOR_L3_HIT_L3BANK16\0"
   /* 6484 */ "COLOR_L3_HIT_L3BANK17\0"
   /* 6506 */ "COLOR_L3_HIT_L3BANK18\0"
   /* 6528 */ "COLOR_L3_HIT_L3BANK19\0"
   /* 6550 */ "COLOR_L3_HIT_L3BANK2\0"
   /* 6571 */ "COLOR_L3_HIT_L3BANK20\0"
   /* 6593 */ "COLOR_L3_HIT_L3BANK21\0"
   /* 6615 */ "COLOR_L3_HIT_L3BANK22\0"
   /* 6637 */ "COLOR_L3_HIT_L3BANK23\0"
   /* 6659 */ "COLOR_L3_HIT_L3BANK24\0"
   /* 6681 */ "COLOR_L3_HIT_L3BANK25\0"
   /* 6703 */ "COLOR_L3_HIT_L3BANK26\0"
   /* 6725 */ "COLOR_L3_HIT_L3BANK27\0"
   /* 6747 */ "COLOR_L3_HIT_L3BANK28\0"
   /* 6769 */ "COLOR_L3_HIT_L3BANK29\0"
   /* 6791 */ "COLOR_L3_HIT_L3BANK3\0"
   /* 6812 */ "COLOR_L3_HIT_L3BANK30\0"
   /* 6834 */ "COLOR_L3_HIT_L3BANK31\0"
   /* 6856 */ "COLOR_L3_HIT_L3BANK4\0"
   /* 6877 */ "COLOR_L3_HIT_L3BANK5\0"
   /* 6898 */ "COLOR_L3_HIT_L3BANK6\0"
   /* 6919 */ "COLOR_L3_HIT_L3BANK7\0"
   /* 6940 */ "COLOR_L3_HIT_L3BANK8\0"
   /* 6961 */ "COLOR_L3_HIT_L3BANK9\0"
   /* 6982 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0\0"
   /* 7021 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1\0"
   /* 7060 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE10\0"
   /* 7100 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE11\0"
   /* 7140 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE12\0"
   /* 7180 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE13\0"
   /* 7220 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE14\0"
   /* 7260 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE15\0"
   /* 7300 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2\0"
   /* 7339 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3\0"
   /* 7378 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE4\0"
   /* 7417 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE5\0"
   /* 7456 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE6\0"
   /* 7495 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE7\0"
   /* 7534 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE8\0"
   /* 7573 */ "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE9\0"
   /* 7612 */ "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0\0"
   /* 7652 */ "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1\0"
   /* 7692 */ "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE2\0"
   /* 7732 */ "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE3\0"
   /* 7772 */ "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE4\0"
   /* 7812 */ "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE5\0"
   /* 7852 */ "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE6\0"
   /* 7892 */ "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE7\0"
   /* 7932 */ "COMMAND_PARSER_COMPUTE_ENGINE_BUSY\0"
   /* 7967 */ "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS0\0"
   /* 8007 */ "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS1\0"
   /* 8047 */ "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS2\0"
   /* 8087 */ "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS3\0"
   /* 8127 */ "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT\0"
   /* 8179 */ "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS0\0"
   /* 8236 */ "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS1\0"
   /* 8293 */ "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS2\0"
   /* 8350 */ "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS3\0"
   /* 8407 */ "COMMAND_PARSER_COPY_ENGINE_BUSY\0"
   /* 8439 */ "COMMAND_PARSER_FLUSH_COUNT\0"
   /* 8466 */ "COMMAND_PARSER_RENDER_ENGINE_BUSY\0"
   /* 8500 */ "COMMAND_PARSER_RENDER_ENGINE_DISPATCH_KERNEL_COUNT\0"
   /* 8551 */ "COMMAND_PARSER_RENDER_ENGINE_DRAW_COUNT\0"
   /* 8591 */ "COMMAND_PARSER_VIDEO_ENGINE_BUSY\0"
   /* 8624 */ "COMMAND_PARSER_VIDEO_ENGINE_BUSY_VDBOX0\0"
   /* 8664 */ "COMMAND_PARSER_VIDEO_ENGINE_BUSY_VDBOX1\0"
   /* 8704 */ "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY\0"
   /* 8749 */ "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY_VEBOX0\0"
   /* 8801 */ "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY_VEBOX1\0"
   /* 8853 */ "Cl0Bottleneck\0"
   /* 8867 */ "Cl0Stall\0"
   /* 8876 */ "Cl1Bottleneck\0"
   /* 8890 */ "Cl1Stall\0"
   /* 8899 */ "Cl2Bottleneck\0"
   /* 8913 */ "Cl2Stall\0"
   /* 8922 */ "Cl3Bottleneck\0"
   /* 8936 */ "Cl3Stall\0"
   /* 8945 */ "Cl4Bottleneck\0"
   /* 8959 */ "Cl4Stall\0"
   /* 8968 */ "Cl5Bottleneck\0"
   /* 8982 */ "Cl5Stall\0"
   /* 8991 */ "Cl6Bottleneck\0"
   /* 9005 */ "Cl6Stall\0"
   /* 9014 */ "Cl7Bottleneck\0"
   /* 9028 */ "Cl7Stall\0"
   /* 9037 */ "ClBottleneck\0"
   /* 9050 */ "ClStall\0"
   /* 9058 */ "ComputeBusy\0"
   /* 9070 */ "ComputeEngine0Busy\0"
   /* 9089 */ "ComputeEngine1Busy\0"
   /* 9108 */ "ComputeEngine2Busy\0"
   /* 9127 */ "ComputeEngine3Busy\0"
   /* 9146 */ "Counter0\0"
   /* 9155 */ "Counter1\0"
   /* 9164 */ "Counter2\0"
   /* 9173 */ "Counter3\0"
   /* 9182 */ "Counter4\0"
   /* 9191 */ "Counter5\0"
   /* 9200 */ "Counter6\0"
   /* 9209 */ "Counter7\0"
   /* 9218 */ "Counter8\0"
   /* 9227 */ "Counter9\0"
   /* 9236 */ "CsDuration\0"
   /* 9247 */ "CsEmActive\0"
   /* 9258 */ "CsEuActive\0"
   /* 9269 */ "CsEuActivePerThread\0"
   /* 9289 */ "CsEuStall\0"
   /* 9299 */ "CsEuStallPerThread\0"
   /* 9318 */ "CsFpu0Active\0"
   /* 9331 */ "CsFpu1Active\0"
   /* 9344 */ "CsFpuActive\0"
   /* 9356 */ "CsSendActive\0"
   /* 9369 */ "CsThreads\0"
   /* 9379 */ "DATAPORT_BYTE_READ\0"
   /* 9398 */ "DATAPORT_BYTE_READ_XECORE0\0"
   /* 9425 */ "DATAPORT_BYTE_READ_XECORE1\0"
   /* 9452 */ "DATAPORT_BYTE_READ_XECORE10\0"
   /* 9480 */ "DATAPORT_BYTE_READ_XECORE11\0"
   /* 9508 */ "DATAPORT_BYTE_READ_XECORE12\0"
   /* 9536 */ "DATAPORT_BYTE_READ_XECORE13\0"
   /* 9564 */ "DATAPORT_BYTE_READ_XECORE14\0"
   /* 9592 */ "DATAPORT_BYTE_READ_XECORE15\0"
   /* 9620 */ "DATAPORT_BYTE_READ_XECORE16\0"
   /* 9648 */ "DATAPORT_BYTE_READ_XECORE17\0"
   /* 9676 */ "DATAPORT_BYTE_READ_XECORE18\0"
   /* 9704 */ "DATAPORT_BYTE_READ_XECORE19\0"
   /* 9732 */ "DATAPORT_BYTE_READ_XECORE2\0"
   /* 9759 */ "DATAPORT_BYTE_READ_XECORE20\0"
   /* 9787 */ "DATAPORT_BYTE_READ_XECORE21\0"
   /* 9815 */ "DATAPORT_BYTE_READ_XECORE22\0"
   /* 9843 */ "DATAPORT_BYTE_READ_XECORE23\0"
   /* 9871 */ "DATAPORT_BYTE_READ_XECORE24\0"
   /* 9899 */ "DATAPORT_BYTE_READ_XECORE25\0"
   /* 9927 */ "DATAPORT_BYTE_READ_XECORE26\0"
   /* 9955 */ "DATAPORT_BYTE_READ_XECORE27\0"
   /* 9983 */ "DATAPORT_BYTE_READ_XECORE28\0"
   /* 10011 */ "DATAPORT_BYTE_READ_XECORE29\0"
   /* 10039 */ "DATAPORT_BYTE_READ_XECORE3\0"
   /* 10066 */ "DATAPORT_BYTE_READ_XECORE30\0"
   /* 10094 */ "DATAPORT_BYTE_READ_XECORE31\0"
   /* 10122 */ "DATAPORT_BYTE_READ_XECORE4\0"
   /* 10149 */ "DATAPORT_BYTE_READ_XECORE5\0"
   /* 10176 */ "DATAPORT_BYTE_READ_XECORE6\0"
   /* 10203 */ "DATAPORT_BYTE_READ_XECORE7\0"
   /* 10230 */ "DATAPORT_BYTE_READ_XECORE8\0"
   /* 10257 */ "DATAPORT_BYTE_READ_XECORE9\0"
   /* 10284 */ "DATAPORT_BYTE_WRITE\0"
   /* 10304 */ "DATAPORT_BYTE_WRITE_XECORE0\0"
   /* 10332 */ "DATAPORT_BYTE_WRITE_XECORE1\0"
   /* 10360 */ "DATAPORT_BYTE_WRITE_XECORE10\0"
   /* 10389 */ "DATAPORT_BYTE_WRITE_XECORE11\0"
   /* 10418 */ "DATAPORT_BYTE_WRITE_XECORE12\0"
   /* 10447 */ "DATAPORT_BYTE_WRITE_XECORE13\0"
   /* 10476 */ "DATAPORT_BYTE_WRITE_XECORE14\0"
   /* 10505 */ "DATAPORT_BYTE_WRITE_XECORE15\0"
   /* 10534 */ "DATAPORT_BYTE_WRITE_XECORE16\0"
   /* 10563 */ "DATAPORT_BYTE_WRITE_XECORE17\0"
   /* 10592 */ "DATAPORT_BYTE_WRITE_XECORE18\0"
   /* 10621 */ "DATAPORT_BYTE_WRITE_XECORE19\0"
   /* 10650 */ "DATAPORT_BYTE_WRITE_XECORE2\0"
   /* 10678 */ "DATAPORT_BYTE_WRITE_XECORE20\0"
   /* 10707 */ "DATAPORT_BYTE_WRITE_XECORE21\0"
   /* 10736 */ "DATAPORT_BYTE_WRITE_XECORE22\0"
   /* 10765 */ "DATAPORT_BYTE_WRITE_XECORE23\0"
   /* 10794 */ "DATAPORT_BYTE_WRITE_XECORE24\0"
   /* 10823 */ "DATAPORT_BYTE_WRITE_XECORE25\0"
   /* 10852 */ "DATAPORT_BYTE_WRITE_XECORE26\0"
   /* 10881 */ "DATAPORT_BYTE_WRITE_XECORE27\0"
   /* 10910 */ "DATAPORT_BYTE_WRITE_XECORE28\0"
   /* 10939 */ "DATAPORT_BYTE_WRITE_XECORE29\0"
   /* 10968 */ "DATAPORT_BYTE_WRITE_XECORE3\0"
   /* 10996 */ "DATAPORT_BYTE_WRITE_XECORE30\0"
   /* 11025 */ "DATAPORT_BYTE_WRITE_XECORE31\0"
   /* 11054 */ "DATAPORT_BYTE_WRITE_XECORE4\0"
   /* 11082 */ "DATAPORT_BYTE_WRITE_XECORE5\0"
   /* 11110 */ "DATAPORT_BYTE_WRITE_XECORE6\0"
   /* 11138 */ "DATAPORT_BYTE_WRITE_XECORE7\0"
   /* 11166 */ "DATAPORT_BYTE_WRITE_XECORE8\0"
   /* 11194 */ "DATAPORT_BYTE_WRITE_XECORE9\0"
   /* 11222 */ "DATAPORT_INPUT_AVAILABLE_XECORE0\0"
   /* 11255 */ "DATAPORT_INPUT_AVAILABLE_XECORE1\0"
   /* 11288 */ "DATAPORT_INPUT_AVAILABLE_XECORE10\0"
   /* 11322 */ "DATAPORT_INPUT_AVAILABLE_XECORE11\0"
   /* 11356 */ "DATAPORT_INPUT_AVAILABLE_XECORE12\0"
   /* 11390 */ "DATAPORT_INPUT_AVAILABLE_XECORE13\0"
   /* 11424 */ "DATAPORT_INPUT_AVAILABLE_XECORE14\0"
   /* 11458 */ "DATAPORT_INPUT_AVAILABLE_XECORE15\0"
   /* 11492 */ "DATAPORT_INPUT_AVAILABLE_XECORE16\0"
   /* 11526 */ "DATAPORT_INPUT_AVAILABLE_XECORE17\0"
   /* 11560 */ "DATAPORT_INPUT_AVAILABLE_XECORE18\0"
   /* 11594 */ "DATAPORT_INPUT_AVAILABLE_XECORE19\0"
   /* 11628 */ "DATAPORT_INPUT_AVAILABLE_XECORE2\0"
   /* 11661 */ "DATAPORT_INPUT_AVAILABLE_XECORE20\0"
   /* 11695 */ "DATAPORT_INPUT_AVAILABLE_XECORE21\0"
   /* 11729 */ "DATAPORT_INPUT_AVAILABLE_XECORE22\0"
   /* 11763 */ "DATAPORT_INPUT_AVAILABLE_XECORE23\0"
   /* 11797 */ "DATAPORT_INPUT_AVAILABLE_XECORE24\0"
   /* 11831 */ "DATAPORT_INPUT_AVAILABLE_XECORE25\0"
   /* 11865 */ "DATAPORT_INPUT_AVAILABLE_XECORE26\0"
   /* 11899 */ "DATAPORT_INPUT_AVAILABLE_XECORE27\0"
   /* 11933 */ "DATAPORT_INPUT_AVAILABLE_XECORE28\0"
   /* 11967 */ "DATAPORT_INPUT_AVAILABLE_XECORE29\0"
   /* 12001 */ "DATAPORT_INPUT_AVAILABLE_XECORE3\0"
   /* 12034 */ "DATAPORT_INPUT_AVAILABLE_XECORE30\0"
   /* 12068 */ "DATAPORT_INPUT_AVAILABLE_XECORE31\0"
   /* 12102 */ "DATAPORT_INPUT_AVAILABLE_XECORE4\0"
   /* 12135 */ "DATAPORT_INPUT_AVAILABLE_XECORE5\0"
   /* 12168 */ "DATAPORT_INPUT_AVAILABLE_XECORE6\0"
   /* 12201 */ "DATAPORT_INPUT_AVAILABLE_XECORE7\0"
   /* 12234 */ "DATAPORT_INPUT_AVAILABLE_XECORE8\0"
   /* 12267 */ "DATAPORT_INPUT_AVAILABLE_XECORE9\0"
   /* 12300 */ "DATAPORT_L3_HIT_L3BANK0\0"
   /* 12324 */ "DATAPORT_L3_HIT_L3BANK1\0"
   /* 12348 */ "DATAPORT_L3_HIT_L3BANK10\0"
   /* 12373 */ "DATAPORT_L3_HIT_L3BANK11\0"
   /* 12398 */ "DATAPORT_L3_HIT_L3BANK12\0"
   /* 12423 */ "DATAPORT_L3_HIT_L3BANK13\0"
   /* 12448 */ "DATAPORT_L3_HIT_L3BANK14\0"
   /* 12473 */ "DATAPORT_L3_HIT_L3BANK15\0"
   /* 12498 */ "DATAPORT_L3_HIT_L3BANK16\0"
   /* 12523 */ "DATAPORT_L3_HIT_L3BANK17\0"
   /* 12548 */ "DATAPORT_L3_HIT_L3BANK18\0"
   /* 12573 */ "DATAPORT_L3_HIT_L3BANK19\0"
   /* 12598 */ "DATAPORT_L3_HIT_L3BANK2\0"
   /* 12622 */ "DATAPORT_L3_HIT_L3BANK20\0"
   /* 12647 */ "DATAPORT_L3_HIT_L3BANK21\0"
   /* 12672 */ "DATAPORT_L3_HIT_L3BANK22\0"
   /* 12697 */ "DATAPORT_L3_HIT_L3BANK23\0"
   /* 12722 */ "DATAPORT_L3_HIT_L3BANK24\0"
   /* 12747 */ "DATAPORT_L3_HIT_L3BANK25\0"
   /* 12772 */ "DATAPORT_L3_HIT_L3BANK26\0"
   /* 12797 */ "DATAPORT_L3_HIT_L3BANK27\0"
   /* 12822 */ "DATAPORT_L3_HIT_L3BANK28\0"
   /* 12847 */ "DATAPORT_L3_HIT_L3BANK29\0"
   /* 12872 */ "DATAPORT_L3_HIT_L3BANK3\0"
   /* 12896 */ "DATAPORT_L3_HIT_L3BANK30\0"
   /* 12921 */ "DATAPORT_L3_HIT_L3BANK31\0"
   /* 12946 */ "DATAPORT_L3_HIT_L3BANK4\0"
   /* 12970 */ "DATAPORT_L3_HIT_L3BANK5\0"
   /* 12994 */ "DATAPORT_L3_HIT_L3BANK6\0"
   /* 13018 */ "DATAPORT_L3_HIT_L3BANK7\0"
   /* 13042 */ "DATAPORT_L3_HIT_L3BANK8\0"
   /* 13066 */ "DATAPORT_L3_HIT_L3BANK9\0"
   /* 13090 */ "DATAPORT_L3_READ_L3BANK0\0"
   /* 13115 */ "DATAPORT_L3_READ_L3BANK1\0"
   /* 13140 */ "DATAPORT_L3_READ_L3BANK10\0"
   /* 13166 */ "DATAPORT_L3_READ_L3BANK11\0"
   /* 13192 */ "DATAPORT_L3_READ_L3BANK12\0"
   /* 13218 */ "DATAPORT_L3_READ_L3BANK13\0"
   /* 13244 */ "DATAPORT_L3_READ_L3BANK14\0"
   /* 13270 */ "DATAPORT_L3_READ_L3BANK15\0"
   /* 13296 */ "DATAPORT_L3_READ_L3BANK16\0"
   /* 13322 */ "DATAPORT_L3_READ_L3BANK17\0"
   /* 13348 */ "DATAPORT_L3_READ_L3BANK18\0"
   /* 13374 */ "DATAPORT_L3_READ_L3BANK19\0"
   /* 13400 */ "DATAPORT_L3_READ_L3BANK2\0"
   /* 13425 */ "DATAPORT_L3_READ_L3BANK20\0"
   /* 13451 */ "DATAPORT_L3_READ_L3BANK21\0"
   /* 13477 */ "DATAPORT_L3_READ_L3BANK22\0"
   /* 13503 */ "DATAPORT_L3_READ_L3BANK23\0"
   /* 13529 */ "DATAPORT_L3_READ_L3BANK24\0"
   /* 13555 */ "DATAPORT_L3_READ_L3BANK25\0"
   /* 13581 */ "DATAPORT_L3_READ_L3BANK26\0"
   /* 13607 */ "DATAPORT_L3_READ_L3BANK27\0"
   /* 13633 */ "DATAPORT_L3_READ_L3BANK28\0"
   /* 13659 */ "DATAPORT_L3_READ_L3BANK29\0"
   /* 13685 */ "DATAPORT_L3_READ_L3BANK3\0"
   /* 13710 */ "DATAPORT_L3_READ_L3BANK30\0"
   /* 13736 */ "DATAPORT_L3_READ_L3BANK31\0"
   /* 13762 */ "DATAPORT_L3_READ_L3BANK4\0"
   /* 13787 */ "DATAPORT_L3_READ_L3BANK5\0"
   /* 13812 */ "DATAPORT_L3_READ_L3BANK6\0"
   /* 13837 */ "DATAPORT_L3_READ_L3BANK7\0"
   /* 13862 */ "DATAPORT_L3_READ_L3BANK8\0"
   /* 13887 */ "DATAPORT_L3_READ_L3BANK9\0"
   /* 13912 */ "DATAPORT_L3_WRITE_L3BANK0\0"
   /* 13938 */ "DATAPORT_L3_WRITE_L3BANK1\0"
   /* 13964 */ "DATAPORT_L3_WRITE_L3BANK10\0"
   /* 13991 */ "DATAPORT_L3_WRITE_L3BANK11\0"
   /* 14018 */ "DATAPORT_L3_WRITE_L3BANK12\0"
   /* 14045 */ "DATAPORT_L3_WRITE_L3BANK13\0"
   /* 14072 */ "DATAPORT_L3_WRITE_L3BANK14\0"
   /* 14099 */ "DATAPORT_L3_WRITE_L3BANK15\0"
   /* 14126 */ "DATAPORT_L3_WRITE_L3BANK16\0"
   /* 14153 */ "DATAPORT_L3_WRITE_L3BANK17\0"
   /* 14180 */ "DATAPORT_L3_WRITE_L3BANK18\0"
   /* 14207 */ "DATAPORT_L3_WRITE_L3BANK19\0"
   /* 14234 */ "DATAPORT_L3_WRITE_L3BANK2\0"
   /* 14260 */ "DATAPORT_L3_WRITE_L3BANK20\0"
   /* 14287 */ "DATAPORT_L3_WRITE_L3BANK21\0"
   /* 14314 */ "DATAPORT_L3_WRITE_L3BANK22\0"
   /* 14341 */ "DATAPORT_L3_WRITE_L3BANK23\0"
   /* 14368 */ "DATAPORT_L3_WRITE_L3BANK24\0"
   /* 14395 */ "DATAPORT_L3_WRITE_L3BANK25\0"
   /* 14422 */ "DATAPORT_L3_WRITE_L3BANK26\0"
   /* 14449 */ "DATAPORT_L3_WRITE_L3BANK27\0"
   /* 14476 */ "DATAPORT_L3_WRITE_L3BANK28\0"
   /* 14503 */ "DATAPORT_L3_WRITE_L3BANK29\0"
   /* 14530 */ "DATAPORT_L3_WRITE_L3BANK3\0"
   /* 14556 */ "DATAPORT_L3_WRITE_L3BANK30\0"
   /* 14583 */ "DATAPORT_L3_WRITE_L3BANK31\0"
   /* 14610 */ "DATAPORT_L3_WRITE_L3BANK4\0"
   /* 14636 */ "DATAPORT_L3_WRITE_L3BANK5\0"
   /* 14662 */ "DATAPORT_L3_WRITE_L3BANK6\0"
   /* 14688 */ "DATAPORT_L3_WRITE_L3BANK7\0"
   /* 14714 */ "DATAPORT_L3_WRITE_L3BANK8\0"
   /* 14740 */ "DATAPORT_L3_WRITE_L3BANK9\0"
   /* 14766 */ "DATAPORT_OUTPUT_READY_XECORE0\0"
   /* 14796 */ "DATAPORT_OUTPUT_READY_XECORE1\0"
   /* 14826 */ "DATAPORT_OUTPUT_READY_XECORE10\0"
   /* 14857 */ "DATAPORT_OUTPUT_READY_XECORE11\0"
   /* 14888 */ "DATAPORT_OUTPUT_READY_XECORE12\0"
   /* 14919 */ "DATAPORT_OUTPUT_READY_XECORE13\0"
   /* 14950 */ "DATAPORT_OUTPUT_READY_XECORE14\0"
   /* 14981 */ "DATAPORT_OUTPUT_READY_XECORE15\0"
   /* 15012 */ "DATAPORT_OUTPUT_READY_XECORE16\0"
   /* 15043 */ "DATAPORT_OUTPUT_READY_XECORE17\0"
   /* 15074 */ "DATAPORT_OUTPUT_READY_XECORE18\0"
   /* 15105 */ "DATAPORT_OUTPUT_READY_XECORE19\0"
   /* 15136 */ "DATAPORT_OUTPUT_READY_XECORE2\0"
   /* 15166 */ "DATAPORT_OUTPUT_READY_XECORE20\0"
   /* 15197 */ "DATAPORT_OUTPUT_READY_XECORE21\0"
   /* 15228 */ "DATAPORT_OUTPUT_READY_XECORE22\0"
   /* 15259 */ "DATAPORT_OUTPUT_READY_XECORE23\0"
   /* 15290 */ "DATAPORT_OUTPUT_READY_XECORE24\0"
   /* 15321 */ "DATAPORT_OUTPUT_READY_XECORE25\0"
   /* 15352 */ "DATAPORT_OUTPUT_READY_XECORE26\0"
   /* 15383 */ "DATAPORT_OUTPUT_READY_XECORE27\0"
   /* 15414 */ "DATAPORT_OUTPUT_READY_XECORE28\0"
   /* 15445 */ "DATAPORT_OUTPUT_READY_XECORE29\0"
   /* 15476 */ "DATAPORT_OUTPUT_READY_XECORE3\0"
   /* 15506 */ "DATAPORT_OUTPUT_READY_XECORE30\0"
   /* 15537 */ "DATAPORT_OUTPUT_READY_XECORE31\0"
   /* 15568 */ "DATAPORT_OUTPUT_READY_XECORE4\0"
   /* 15598 */ "DATAPORT_OUTPUT_READY_XECORE5\0"
   /* 15628 */ "DATAPORT_OUTPUT_READY_XECORE6\0"
   /* 15658 */ "DATAPORT_OUTPUT_READY_XECORE7\0"
   /* 15688 */ "DATAPORT_OUTPUT_READY_XECORE8\0"
   /* 15718 */ "DATAPORT_OUTPUT_READY_XECORE9\0"
   /* 15748 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0\0"
   /* 15786 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1\0"
   /* 15824 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE10\0"
   /* 15863 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE11\0"
   /* 15902 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE12\0"
   /* 15941 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE13\0"
   /* 15980 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE14\0"
   /* 16019 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE15\0"
   /* 16058 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE16\0"
   /* 16097 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE17\0"
   /* 16136 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE18\0"
   /* 16175 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE19\0"
   /* 16214 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2\0"
   /* 16252 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE20\0"
   /* 16291 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE21\0"
   /* 16330 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE22\0"
   /* 16369 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE23\0"
   /* 16408 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE24\0"
   /* 16447 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE25\0"
   /* 16486 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE26\0"
   /* 16525 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE27\0"
   /* 16564 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE28\0"
   /* 16603 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE29\0"
   /* 16642 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3\0"
   /* 16680 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE30\0"
   /* 16719 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE31\0"
   /* 16758 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4\0"
   /* 16796 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5\0"
   /* 16834 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6\0"
   /* 16872 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7\0"
   /* 16910 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE8\0"
   /* 16948 */ "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE9\0"
   /* 16986 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE0\0"
   /* 17021 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE1\0"
   /* 17056 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE10\0"
   /* 17092 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE11\0"
   /* 17128 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE12\0"
   /* 17164 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE13\0"
   /* 17200 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE14\0"
   /* 17236 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE15\0"
   /* 17272 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE16\0"
   /* 17308 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE17\0"
   /* 17344 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE18\0"
   /* 17380 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE19\0"
   /* 17416 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE2\0"
   /* 17451 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE20\0"
   /* 17487 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE21\0"
   /* 17523 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE22\0"
   /* 17559 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE23\0"
   /* 17595 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE24\0"
   /* 17631 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE25\0"
   /* 17667 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE26\0"
   /* 17703 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE27\0"
   /* 17739 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE28\0"
   /* 17775 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE29\0"
   /* 17811 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE3\0"
   /* 17846 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE30\0"
   /* 17882 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE31\0"
   /* 17918 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE4\0"
   /* 17953 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE5\0"
   /* 17988 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE6\0"
   /* 18023 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE7\0"
   /* 18058 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE8\0"
   /* 18093 */ "DATAPORT_TEXTURE_CACHE_HIT_XECORE9\0"
   /* 18128 */ "Ds0Bottleneck\0"
   /* 18142 */ "Ds0Stall\0"
   /* 18151 */ "Ds1Bottleneck\0"
   /* 18165 */ "Ds1Stall\0"
   /* 18174 */ "Ds2Bottleneck\0"
   /* 18188 */ "Ds2Stall\0"
   /* 18197 */ "Ds3Bottleneck\0"
   /* 18211 */ "Ds3Stall\0"
   /* 18220 */ "Ds4Bottleneck\0"
   /* 18234 */ "Ds4Stall\0"
   /* 18243 */ "Ds5Bottleneck\0"
   /* 18257 */ "Ds5Stall\0"
   /* 18266 */ "Ds6Bottleneck\0"
   /* 18280 */ "Ds6Stall\0"
   /* 18289 */ "Ds7Bottleneck\0"
   /* 18303 */ "Ds7Stall\0"
   /* 18312 */ "DsBottleneck\0"
   /* 18325 */ "DsDuration\0"
   /* 18336 */ "DsEmActive\0"
   /* 18347 */ "DsEuActive\0"
   /* 18358 */ "DsEuActivePerThread\0"
   /* 18378 */ "DsEuStall\0"
   /* 18388 */ "DsEuStallPerThread\0"
   /* 18407 */ "DsFpuActive\0"
   /* 18419 */ "DsSendActive\0"
   /* 18432 */ "DsStall\0"
   /* 18440 */ "DsThreads\0"
   /* 18450 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0\0"
   /* 18490 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1\0"
   /* 18530 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE10\0"
   /* 18571 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE11\0"
   /* 18612 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE12\0"
   /* 18653 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE13\0"
   /* 18694 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE14\0"
   /* 18735 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE15\0"
   /* 18776 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2\0"
   /* 18816 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3\0"
   /* 18856 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE4\0"
   /* 18896 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE5\0"
   /* 18936 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE6\0"
   /* 18976 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE7\0"
   /* 19016 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE8\0"
   /* 19056 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE9\0"
   /* 19096 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0\0"
   /* 19135 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1\0"
   /* 19174 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE10\0"
   /* 19214 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE11\0"
   /* 19254 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE12\0"
   /* 19294 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE13\0"
   /* 19334 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE14\0"
   /* 19374 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE15\0"
   /* 19414 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2\0"
   /* 19453 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3\0"
   /* 19492 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE4\0"
   /* 19531 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE5\0"
   /* 19570 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE6\0"
   /* 19609 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE7\0"
   /* 19648 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE8\0"
   /* 19687 */ "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE9\0"
   /* 19726 */ "EarlyDepthBottleneck\0"
   /* 19747 */ "EarlyDepthTestFails\0"
   /* 19767 */ "EmActive\0"
   /* 19776 */ "EuA32UntypedReads00\0"
   /* 19796 */ "EuA32UntypedWrites00\0"
   /* 19817 */ "EuA64UntypedReads0\0"
   /* 19836 */ "EuA64UntypedReads00\0"
   /* 19856 */ "EuA64UntypedWrites0\0"
   /* 19876 */ "EuA64UntypedWrites00\0"
   /* 19897 */ "EuActive\0"
   /* 19906 */ "EuAvgIpcRate\0"
   /* 19919 */ "EuBinaryFpu0Instruction\0"
   /* 19943 */ "EuBinaryFpu1Instruction\0"
   /* 19967 */ "EuBytesReadPerCacheLine\0"
   /* 19991 */ "EuBytesWrittenPerCacheLine\0"
   /* 20018 */ "EuDataReadsPerCacheLine\0"
   /* 20042 */ "EuDataWritesPerCacheLine\0"
   /* 20067 */ "EuFpuBothActive\0"
   /* 20083 */ "EuFpuEmActive\0"
   /* 20097 */ "EuHdc0Reads128B\0"
   /* 20113 */ "EuHdc0Reads256B\0"
   /* 20129 */ "EuHdc0Reads32B\0"
   /* 20144 */ "EuHdc0Reads64B\0"
   /* 20159 */ "EuHdc0Writes128B\0"
   /* 20176 */ "EuHdc0Writes128BSimd16\0"
   /* 20199 */ "EuHdc0Writes192B\0"
   /* 20216 */ "EuHdc0Writes256BSimd16\0"
   /* 20239 */ "EuHdc0Writes32B\0"
   /* 20255 */ "EuHdc0Writes64B\0"
   /* 20271 */ "EuHdc0Writes96B\0"
   /* 20287 */ "EuHybridFpu0Instruction\0"
   /* 20311 */ "EuHybridFpu1Instruction\0"
   /* 20335 */ "EuIdle\0"
   /* 20342 */ "EuMoveFpu0Instruction\0"
   /* 20364 */ "EuMoveFpu1Instruction\0"
   /* 20386 */ "EuSendActive\0"
   /* 20399 */ "EuStall\0"
   /* 20407 */ "EuTernaryFpu0Instruction\0"
   /* 20432 */ "EuTernaryFpu1Instruction\0"
   /* 20457 */ "EuThreadOccupancy\0"
   /* 20475 */ "EuTypedAtomics0\0"
   /* 20491 */ "EuTypedAtomics00\0"
   /* 20508 */ "EuTypedReads0\0"
   /* 20522 */ "EuTypedReads00\0"
   /* 20537 */ "EuTypedWrites0\0"
   /* 20552 */ "EuTypedWrites00\0"
   /* 20568 */ "EuUntypedAtomics0\0"
   /* 20586 */ "EuUntypedReads0\0"
   /* 20602 */ "EuUntypedWrites0\0"
   /* 20619 */ "EuUrbAtomics0\0"
   /* 20633 */ "Fpu0Active\0"
   /* 20644 */ "Fpu1Active\0"
   /* 20655 */ "Fpu1ActiveAdjusted\0"
   /* 20674 */ "FpuActive\0"
   /* 20684 */ "GPGPU_DISPATCH_XECORE0\0"
   /* 20707 */ "GPGPU_DISPATCH_XECORE1\0"
   /* 20730 */ "GPGPU_DISPATCH_XECORE10\0"
   /* 20754 */ "GPGPU_DISPATCH_XECORE11\0"
   /* 20778 */ "GPGPU_DISPATCH_XECORE12\0"
   /* 20802 */ "GPGPU_DISPATCH_XECORE13\0"
   /* 20826 */ "GPGPU_DISPATCH_XECORE14\0"
   /* 20850 */ "GPGPU_DISPATCH_XECORE15\0"
   /* 20874 */ "GPGPU_DISPATCH_XECORE16\0"
   /* 20898 */ "GPGPU_DISPATCH_XECORE17\0"
   /* 20922 */ "GPGPU_DISPATCH_XECORE18\0"
   /* 20946 */ "GPGPU_DISPATCH_XECORE19\0"
   /* 20970 */ "GPGPU_DISPATCH_XECORE2\0"
   /* 20993 */ "GPGPU_DISPATCH_XECORE20\0"
   /* 21017 */ "GPGPU_DISPATCH_XECORE21\0"
   /* 21041 */ "GPGPU_DISPATCH_XECORE22\0"
   /* 21065 */ "GPGPU_DISPATCH_XECORE23\0"
   /* 21089 */ "GPGPU_DISPATCH_XECORE24\0"
   /* 21113 */ "GPGPU_DISPATCH_XECORE25\0"
   /* 21137 */ "GPGPU_DISPATCH_XECORE26\0"
   /* 21161 */ "GPGPU_DISPATCH_XECORE27\0"
   /* 21185 */ "GPGPU_DISPATCH_XECORE28\0"
   /* 21209 */ "GPGPU_DISPATCH_XECORE29\0"
   /* 21233 */ "GPGPU_DISPATCH_XECORE3\0"
   /* 21256 */ "GPGPU_DISPATCH_XECORE30\0"
   /* 21280 */ "GPGPU_DISPATCH_XECORE31\0"
   /* 21304 */ "GPGPU_DISPATCH_XECORE4\0"
   /* 21327 */ "GPGPU_DISPATCH_XECORE5\0"
   /* 21350 */ "GPGPU_DISPATCH_XECORE6\0"
   /* 21373 */ "GPGPU_DISPATCH_XECORE7\0"
   /* 21396 */ "GPGPU_DISPATCH_XECORE8\0"
   /* 21419 */ "GPGPU_DISPATCH_XECORE9\0"
   /* 21442 */ "GPGPU_THREADGROUP_COUNT_XECORE0\0"
   /* 21474 */ "GPGPU_THREADGROUP_COUNT_XECORE1\0"
   /* 21506 */ "GPGPU_THREADGROUP_COUNT_XECORE10\0"
   /* 21539 */ "GPGPU_THREADGROUP_COUNT_XECORE11\0"
   /* 21572 */ "GPGPU_THREADGROUP_COUNT_XECORE12\0"
   /* 21605 */ "GPGPU_THREADGROUP_COUNT_XECORE13\0"
   /* 21638 */ "GPGPU_THREADGROUP_COUNT_XECORE14\0"
   /* 21671 */ "GPGPU_THREADGROUP_COUNT_XECORE15\0"
   /* 21704 */ "GPGPU_THREADGROUP_COUNT_XECORE16\0"
   /* 21737 */ "GPGPU_THREADGROUP_COUNT_XECORE17\0"
   /* 21770 */ "GPGPU_THREADGROUP_COUNT_XECORE18\0"
   /* 21803 */ "GPGPU_THREADGROUP_COUNT_XECORE19\0"
   /* 21836 */ "GPGPU_THREADGROUP_COUNT_XECORE2\0"
   /* 21868 */ "GPGPU_THREADGROUP_COUNT_XECORE20\0"
   /* 21901 */ "GPGPU_THREADGROUP_COUNT_XECORE21\0"
   /* 21934 */ "GPGPU_THREADGROUP_COUNT_XECORE22\0"
   /* 21967 */ "GPGPU_THREADGROUP_COUNT_XECORE23\0"
   /* 22000 */ "GPGPU_THREADGROUP_COUNT_XECORE24\0"
   /* 22033 */ "GPGPU_THREADGROUP_COUNT_XECORE25\0"
   /* 22066 */ "GPGPU_THREADGROUP_COUNT_XECORE26\0"
   /* 22099 */ "GPGPU_THREADGROUP_COUNT_XECORE27\0"
   /* 22132 */ "GPGPU_THREADGROUP_COUNT_XECORE28\0"
   /* 22165 */ "GPGPU_THREADGROUP_COUNT_XECORE29\0"
   /* 22198 */ "GPGPU_THREADGROUP_COUNT_XECORE3\0"
   /* 22230 */ "GPGPU_THREADGROUP_COUNT_XECORE30\0"
   /* 22263 */ "GPGPU_THREADGROUP_COUNT_XECORE31\0"
   /* 22296 */ "GPGPU_THREADGROUP_COUNT_XECORE4\0"
   /* 22328 */ "GPGPU_THREADGROUP_COUNT_XECORE5\0"
   /* 22360 */ "GPGPU_THREADGROUP_COUNT_XECORE6\0"
   /* 22392 */ "GPGPU_THREADGROUP_COUNT_XECORE7\0"
   /* 22424 */ "GPGPU_THREADGROUP_COUNT_XECORE8\0"
   /* 22456 */ "GPGPU_THREADGROUP_COUNT_XECORE9\0"
   /* 22488 */ "GPU_MEMORY_32B_TRANSACTION_READ\0"
   /* 22520 */ "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI0\0"
   /* 22559 */ "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI1\0"
   /* 22598 */ "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI2\0"
   /* 22637 */ "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI3\0"
   /* 22676 */ "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI4\0"
   /* 22715 */ "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI5\0"
   /* 22754 */ "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI6\0"
   /* 22793 */ "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI7\0"
   /* 22832 */ "GPU_MEMORY_32B_TRANSACTION_WRITE\0"
   /* 22865 */ "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI0\0"
   /* 22905 */ "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI1\0"
   /* 22945 */ "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI2\0"
   /* 22985 */ "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI3\0"
   /* 23025 */ "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI4\0"
   /* 23065 */ "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI5\0"
   /* 23105 */ "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI6\0"
   /* 23145 */ "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI7\0"
   /* 23185 */ "GPU_MEMORY_64B_TRANSACTION_READ\0"
   /* 23217 */ "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI0\0"
   /* 23256 */ "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI1\0"
   /* 23295 */ "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI2\0"
   /* 23334 */ "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI3\0"
   /* 23373 */ "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI4\0"
   /* 23412 */ "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI5\0"
   /* 23451 */ "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI6\0"
   /* 23490 */ "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI7\0"
   /* 23529 */ "GPU_MEMORY_64B_TRANSACTION_WRITE\0"
   /* 23562 */ "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI0\0"
   /* 23602 */ "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI1\0"
   /* 23642 */ "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI2\0"
   /* 23682 */ "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI3\0"
   /* 23722 */ "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI4\0"
   /* 23762 */ "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI5\0"
   /* 23802 */ "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI6\0"
   /* 23842 */ "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI7\0"
   /* 23882 */ "GPU_MEMORY_ACTIVE\0"
   /* 23900 */ "GPU_MEMORY_ACTIVE_SQIDI0\0"
   /* 23925 */ "GPU_MEMORY_ACTIVE_SQIDI1\0"
   /* 23950 */ "GPU_MEMORY_ACTIVE_SQIDI2\0"
   /* 23975 */ "GPU_MEMORY_ACTIVE_SQIDI3\0"
   /* 24000 */ "GPU_MEMORY_ACTIVE_SQIDI4\0"
   /* 24025 */ "GPU_MEMORY_ACTIVE_SQIDI5\0"
   /* 24050 */ "GPU_MEMORY_ACTIVE_SQIDI6\0"
   /* 24075 */ "GPU_MEMORY_ACTIVE_SQIDI7\0"
   /* 24100 */ "GPU_MEMORY_BYTE_READ\0"
   /* 24121 */ "GPU_MEMORY_BYTE_READ_BW\0"
   /* 24145 */ "GPU_MEMORY_BYTE_READ_BW_SQIDI0\0"
   /* 24176 */ "GPU_MEMORY_BYTE_READ_BW_SQIDI1\0"
   /* 24207 */ "GPU_MEMORY_BYTE_READ_BW_SQIDI2\0"
   /* 24238 */ "GPU_MEMORY_BYTE_READ_BW_SQIDI3\0"
   /* 24269 */ "GPU_MEMORY_BYTE_READ_BW_SQIDI4\0"
   /* 24300 */ "GPU_MEMORY_BYTE_READ_BW_SQIDI5\0"
   /* 24331 */ "GPU_MEMORY_BYTE_READ_BW_SQIDI6\0"
   /* 24362 */ "GPU_MEMORY_BYTE_READ_BW_SQIDI7\0"
   /* 24393 */ "GPU_MEMORY_BYTE_READ_SQIDI0\0"
   /* 24421 */ "GPU_MEMORY_BYTE_READ_SQIDI1\0"
   /* 24449 */ "GPU_MEMORY_BYTE_READ_SQIDI2\0"
   /* 24477 */ "GPU_MEMORY_BYTE_READ_SQIDI3\0"
   /* 24505 */ "GPU_MEMORY_BYTE_READ_SQIDI4\0"
   /* 24533 */ "GPU_MEMORY_BYTE_READ_SQIDI5\0"
   /* 24561 */ "GPU_MEMORY_BYTE_READ_SQIDI6\0"
   /* 24589 */ "GPU_MEMORY_BYTE_READ_SQIDI7\0"
   /* 24617 */ "GPU_MEMORY_BYTE_WRITE\0"
   /* 24639 */ "GPU_MEMORY_BYTE_WRITE_BW\0"
   /* 24664 */ "GPU_MEMORY_BYTE_WRITE_BW_SQIDI0\0"
   /* 24696 */ "GPU_MEMORY_BYTE_WRITE_BW_SQIDI1\0"
   /* 24728 */ "GPU_MEMORY_BYTE_WRITE_BW_SQIDI2\0"
   /* 24760 */ "GPU_MEMORY_BYTE_WRITE_BW_SQIDI3\0"
   /* 24792 */ "GPU_MEMORY_BYTE_WRITE_BW_SQIDI4\0"
   /* 24824 */ "GPU_MEMORY_BYTE_WRITE_BW_SQIDI5\0"
   /* 24856 */ "GPU_MEMORY_BYTE_WRITE_BW_SQIDI6\0"
   /* 24888 */ "GPU_MEMORY_BYTE_WRITE_BW_SQIDI7\0"
   /* 24920 */ "GPU_MEMORY_BYTE_WRITE_SQIDI0\0"
   /* 24949 */ "GPU_MEMORY_BYTE_WRITE_SQIDI1\0"
   /* 24978 */ "GPU_MEMORY_BYTE_WRITE_SQIDI2\0"
   /* 25007 */ "GPU_MEMORY_BYTE_WRITE_SQIDI3\0"
   /* 25036 */ "GPU_MEMORY_BYTE_WRITE_SQIDI4\0"
   /* 25065 */ "GPU_MEMORY_BYTE_WRITE_SQIDI5\0"
   /* 25094 */ "GPU_MEMORY_BYTE_WRITE_SQIDI6\0"
   /* 25123 */ "GPU_MEMORY_BYTE_WRITE_SQIDI7\0"
   /* 25152 */ "GPU_MEMORY_L3_READ_SQIDI0\0"
   /* 25178 */ "GPU_MEMORY_L3_READ_SQIDI1\0"
   /* 25204 */ "GPU_MEMORY_L3_READ_SQIDI2\0"
   /* 25230 */ "GPU_MEMORY_L3_READ_SQIDI3\0"
   /* 25256 */ "GPU_MEMORY_L3_READ_SQIDI4\0"
   /* 25282 */ "GPU_MEMORY_L3_READ_SQIDI5\0"
   /* 25308 */ "GPU_MEMORY_L3_READ_SQIDI6\0"
   /* 25334 */ "GPU_MEMORY_L3_READ_SQIDI7\0"
   /* 25360 */ "GPU_MEMORY_L3_WRITE_SQIDI0\0"
   /* 25387 */ "GPU_MEMORY_L3_WRITE_SQIDI1\0"
   /* 25414 */ "GPU_MEMORY_L3_WRITE_SQIDI2\0"
   /* 25441 */ "GPU_MEMORY_L3_WRITE_SQIDI3\0"
   /* 25468 */ "GPU_MEMORY_L3_WRITE_SQIDI4\0"
   /* 25495 */ "GPU_MEMORY_L3_WRITE_SQIDI5\0"
   /* 25522 */ "GPU_MEMORY_L3_WRITE_SQIDI6\0"
   /* 25549 */ "GPU_MEMORY_L3_WRITE_SQIDI7\0"
   /* 25576 */ "GPU_MEMORY_READ\0"
   /* 25592 */ "GPU_MEMORY_READ_SQIDI0\0"
   /* 25615 */ "GPU_MEMORY_READ_SQIDI1\0"
   /* 25638 */ "GPU_MEMORY_READ_SQIDI2\0"
   /* 25661 */ "GPU_MEMORY_READ_SQIDI3\0"
   /* 25684 */ "GPU_MEMORY_READ_SQIDI4\0"
   /* 25707 */ "GPU_MEMORY_READ_SQIDI5\0"
   /* 25730 */ "GPU_MEMORY_READ_SQIDI6\0"
   /* 25753 */ "GPU_MEMORY_READ_SQIDI7\0"
   /* 25776 */ "GPU_MEMORY_REQUEST_QUEUE_FULL\0"
   /* 25806 */ "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI0\0"
   /* 25843 */ "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI1\0"
   /* 25880 */ "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI2\0"
   /* 25917 */ "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI3\0"
   /* 25954 */ "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI4\0"
   /* 25991 */ "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI5\0"
   /* 26028 */ "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI6\0"
   /* 26065 */ "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI7\0"
   /* 26102 */ "GPU_MEMORY_WRITE\0"
   /* 26119 */ "GPU_MEMORY_WRITE_SQIDI0\0"
   /* 26143 */ "GPU_MEMORY_WRITE_SQIDI1\0"
   /* 26167 */ "GPU_MEMORY_WRITE_SQIDI2\0"
   /* 26191 */ "GPU_MEMORY_WRITE_SQIDI3\0"
   /* 26215 */ "GPU_MEMORY_WRITE_SQIDI4\0"
   /* 26239 */ "GPU_MEMORY_WRITE_SQIDI5\0"
   /* 26263 */ "GPU_MEMORY_WRITE_SQIDI6\0"
   /* 26287 */ "GPU_MEMORY_WRITE_SQIDI7\0"
   /* 26311 */ "GTRequestQueue00Full\0"
   /* 26332 */ "GTRequestQueue01Full\0"
   /* 26353 */ "GTRequestQueue10Full\0"
   /* 26374 */ "GTRequestQueue11Full\0"
   /* 26395 */ "GTRequestQueue20Full\0"
   /* 26416 */ "GTRequestQueue30Full\0"
   /* 26437 */ "GTRequestQueue40Full\0"
   /* 26458 */ "GTRequestQueue50Full\0"
   /* 26479 */ "GTRequestQueue60Full\0"
   /* 26500 */ "GTRequestQueue70Full\0"
   /* 26521 */ "GTRequestQueueFull\0"
   /* 26540 */ "GpuBusy\0"
   /* 26548 */ "GpuClocks\0"
   /* 26558 */ "GpuCoreClocks\0"
   /* 26572 */ "GpuTime\0"
   /* 26580 */ "Gs0Bottleneck\0"
   /* 26594 */ "Gs1Bottleneck\0"
   /* 26608 */ "Gs2Bottleneck\0"
   /* 26622 */ "Gs3Bottleneck\0"
   /* 26636 */ "Gs4Bottleneck\0"
   /* 26650 */ "Gs5Bottleneck\0"
   /* 26664 */ "Gs6Bottleneck\0"
   /* 26678 */ "Gs7Bottleneck\0"
   /* 26692 */ "GsBottleneck\0"
   /* 26705 */ "GsDuration\0"
   /* 26716 */ "GsEmActive\0"
   /* 26727 */ "GsEuActive\0"
   /* 26738 */ "GsEuActivePerThread\0"
   /* 26758 */ "GsEuStall\0"
   /* 26768 */ "GsEuStallPerThread\0"
   /* 26787 */ "GsFpuActive\0"
   /* 26799 */ "GsSendActive\0"
   /* 26812 */ "GsThreads\0"
   /* 26822 */ "GtiCmdStreamerMemoryReads\0"
   /* 26848 */ "GtiCmdStreamerMemoryWrites\0"
   /* 26875 */ "GtiDepthThroughput\0"
   /* 26894 */ "GtiHdcLookupsThroughput\0"
   /* 26918 */ "GtiHiDepthMemoryReads\0"
   /* 26940 */ "GtiHizMemoryReads\0"
   /* 26958 */ "GtiHizMemoryWrites\0"
   /* 26977 */ "GtiL3Bank0Reads\0"
   /* 26993 */ "GtiL3Bank0Writes\0"
   /* 27010 */ "GtiL3Bank1Reads\0"
   /* 27026 */ "GtiL3Bank1Writes\0"
   /* 27043 */ "GtiL3Bank2Reads\0"
   /* 27059 */ "GtiL3Bank2Writes\0"
   /* 27076 */ "GtiL3Bank3Reads\0"
   /* 27092 */ "GtiL3Bank3Writes\0"
   /* 27109 */ "GtiL3Reads\0"
   /* 27120 */ "GtiL3Throughput\0"
   /* 27136 */ "GtiL3Writes\0"
   /* 27148 */ "GtiMemoryReads\0"
   /* 27163 */ "GtiMemoryWrites\0"
   /* 27179 */ "GtiMscMemoryReads\0"
   /* 27197 */ "GtiMscMemoryWrites\0"
   /* 27216 */ "GtiRccMemoryReads\0"
   /* 27234 */ "GtiRccMemoryWrites\0"
   /* 27253 */ "GtiRccThroughput\0"
   /* 27270 */ "GtiRczMemoryReads\0"
   /* 27288 */ "GtiRczMemoryWrites\0"
   /* 27307 */ "GtiReadThroughput\0"
   /* 27325 */ "GtiRingAccesses\0"
   /* 27341 */ "GtiRingThroughput\0"
   /* 27359 */ "GtiRoStall\0"
   /* 27370 */ "GtiRsMemoryReads\0"
   /* 27387 */ "GtiRwStall\0"
   /* 27398 */ "GtiSoMemoryWrites\0"
   /* 27416 */ "GtiStcMemoryReads\0"
   /* 27434 */ "GtiStcMemoryWrites\0"
   /* 27453 */ "GtiVfMemoryReads\0"
   /* 27470 */ "GtiVfThroughput\0"
   /* 27486 */ "GtiWriteThroughput\0"
   /* 27505 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0\0"
   /* 27536 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1\0"
   /* 27567 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE10\0"
   /* 27599 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE11\0"
   /* 27631 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE12\0"
   /* 27663 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE13\0"
   /* 27695 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE14\0"
   /* 27727 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE15\0"
   /* 27759 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2\0"
   /* 27790 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3\0"
   /* 27821 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE4\0"
   /* 27852 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE5\0"
   /* 27883 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE6\0"
   /* 27914 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE7\0"
   /* 27945 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE8\0"
   /* 27976 */ "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE9\0"
   /* 28007 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0\0"
   /* 28037 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1\0"
   /* 28067 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE10\0"
   /* 28098 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE11\0"
   /* 28129 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE12\0"
   /* 28160 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE13\0"
   /* 28191 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE14\0"
   /* 28222 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE15\0"
   /* 28253 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2\0"
   /* 28283 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3\0"
   /* 28313 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE4\0"
   /* 28343 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE5\0"
   /* 28373 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE6\0"
   /* 28403 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE7\0"
   /* 28433 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE8\0"
   /* 28463 */ "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE9\0"
   /* 28493 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0\0"
   /* 28523 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1\0"
   /* 28553 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE10\0"
   /* 28584 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE11\0"
   /* 28615 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE12\0"
   /* 28646 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE13\0"
   /* 28677 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE14\0"
   /* 28708 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE15\0"
   /* 28739 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2\0"
   /* 28769 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3\0"
   /* 28799 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE4\0"
   /* 28829 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE5\0"
   /* 28859 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE6\0"
   /* 28889 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE7\0"
   /* 28919 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE8\0"
   /* 28949 */ "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE9\0"
   /* 28979 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE0\0"
   /* 29008 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE1\0"
   /* 29037 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE10\0"
   /* 29067 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE11\0"
   /* 29097 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE12\0"
   /* 29127 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE13\0"
   /* 29157 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE14\0"
   /* 29187 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE15\0"
   /* 29217 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE2\0"
   /* 29246 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE3\0"
   /* 29275 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE4\0"
   /* 29304 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE5\0"
   /* 29333 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE6\0"
   /* 29362 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE7\0"
   /* 29391 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE8\0"
   /* 29420 */ "HIZ_DEPTH_TEST_FAIL_P_ZPIPE9\0"
   /* 29449 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE0\0"
   /* 29478 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE1\0"
   /* 29507 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE10\0"
   /* 29537 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE11\0"
   /* 29567 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE12\0"
   /* 29597 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE13\0"
   /* 29627 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE14\0"
   /* 29657 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE15\0"
   /* 29687 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE2\0"
   /* 29716 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE3\0"
   /* 29745 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE4\0"
   /* 29774 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE5\0"
   /* 29803 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE6\0"
   /* 29832 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE7\0"
   /* 29861 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE8\0"
   /* 29890 */ "HIZ_DEPTH_TEST_PASS_P_ZPIPE9\0"
   /* 29919 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0\0"
   /* 29955 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1\0"
   /* 29991 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE10\0"
   /* 30028 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE11\0"
   /* 30065 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE12\0"
   /* 30102 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE13\0"
   /* 30139 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE14\0"
   /* 30176 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE15\0"
   /* 30213 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2\0"
   /* 30249 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3\0"
   /* 30285 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4\0"
   /* 30321 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5\0"
   /* 30357 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6\0"
   /* 30393 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7\0"
   /* 30429 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE8\0"
   /* 30465 */ "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE9\0"
   /* 30501 */ "HOST_TO_GPUMEM_BYTE_READ\0"
   /* 30526 */ "HOST_TO_GPUMEM_BYTE_WRITE\0"
   /* 30552 */ "HOST_TO_GPUMEM_TRANSACTION_READ\0"
   /* 30584 */ "HOST_TO_GPUMEM_TRANSACTION_WRITE\0"
   /* 30617 */ "Hdc0L3DataReads\0"
   /* 30633 */ "Hdc0L3DataWrites\0"
   /* 30650 */ "Hdc0L3Reads\0"
   /* 30662 */ "Hdc0L3Writes\0"
   /* 30675 */ "HiDepth00Bottleneck\0"
   /* 30695 */ "HiDepth01Bottleneck\0"
   /* 30715 */ "HiDepth10Bottleneck\0"
   /* 30735 */ "HiDepth11Bottleneck\0"
   /* 30755 */ "HiDepth20Bottleneck\0"
   /* 30775 */ "HiDepth30Bottleneck\0"
   /* 30795 */ "HiDepth40Bottleneck\0"
   /* 30815 */ "HiDepth50Bottleneck\0"
   /* 30835 */ "HiDepth60Bottleneck\0"
   /* 30855 */ "HiDepth70Bottleneck\0"
   /* 30875 */ "HiDepthBottleneck\0"
   /* 30893 */ "HiDepthTestFails\0"
   /* 30910 */ "Hs0Bottleneck\0"
   /* 30924 */ "Hs0Stall\0"
   /* 30933 */ "Hs1Bottleneck\0"
   /* 30947 */ "Hs1Stall\0"
   /* 30956 */ "Hs2Bottleneck\0"
   /* 30970 */ "Hs2Stall\0"
   /* 30979 */ "Hs3Bottleneck\0"
   /* 30993 */ "Hs3Stall\0"
   /* 31002 */ "Hs4Bottleneck\0"
   /* 31016 */ "Hs4Stall\0"
   /* 31025 */ "Hs5Bottleneck\0"
   /* 31039 */ "Hs5Stall\0"
   /* 31048 */ "Hs6Bottleneck\0"
   /* 31062 */ "Hs6Stall\0"
   /* 31071 */ "Hs7Bottleneck\0"
   /* 31085 */ "Hs7Stall\0"
   /* 31094 */ "HsBottleneck\0"
   /* 31107 */ "HsDuration\0"
   /* 31118 */ "HsEmActive\0"
   /* 31129 */ "HsEuActive\0"
   /* 31140 */ "HsEuActivePerThread\0"
   /* 31160 */ "HsEuStall\0"
   /* 31170 */ "HsEuStallPerThread\0"
   /* 31189 */ "HsFpuActive\0"
   /* 31201 */ "HsSendActive\0"
   /* 31214 */ "HsStall\0"
   /* 31222 */ "HsThreads\0"
   /* 31232 */ "ICACHE_HIT_BANK0_XECORE0\0"
   /* 31257 */ "ICACHE_HIT_BANK0_XECORE1\0"
   /* 31282 */ "ICACHE_HIT_BANK0_XECORE10\0"
   /* 31308 */ "ICACHE_HIT_BANK0_XECORE11\0"
   /* 31334 */ "ICACHE_HIT_BANK0_XECORE12\0"
   /* 31360 */ "ICACHE_HIT_BANK0_XECORE13\0"
   /* 31386 */ "ICACHE_HIT_BANK0_XECORE14\0"
   /* 31412 */ "ICACHE_HIT_BANK0_XECORE15\0"
   /* 31438 */ "ICACHE_HIT_BANK0_XECORE16\0"
   /* 31464 */ "ICACHE_HIT_BANK0_XECORE17\0"
   /* 31490 */ "ICACHE_HIT_BANK0_XECORE18\0"
   /* 31516 */ "ICACHE_HIT_BANK0_XECORE19\0"
   /* 31542 */ "ICACHE_HIT_BANK0_XECORE2\0"
   /* 31567 */ "ICACHE_HIT_BANK0_XECORE20\0"
   /* 31593 */ "ICACHE_HIT_BANK0_XECORE21\0"
   /* 31619 */ "ICACHE_HIT_BANK0_XECORE22\0"
   /* 31645 */ "ICACHE_HIT_BANK0_XECORE23\0"
   /* 31671 */ "ICACHE_HIT_BANK0_XECORE24\0"
   /* 31697 */ "ICACHE_HIT_BANK0_XECORE25\0"
   /* 31723 */ "ICACHE_HIT_BANK0_XECORE26\0"
   /* 31749 */ "ICACHE_HIT_BANK0_XECORE27\0"
   /* 31775 */ "ICACHE_HIT_BANK0_XECORE28\0"
   /* 31801 */ "ICACHE_HIT_BANK0_XECORE29\0"
   /* 31827 */ "ICACHE_HIT_BANK0_XECORE3\0"
   /* 31852 */ "ICACHE_HIT_BANK0_XECORE30\0"
   /* 31878 */ "ICACHE_HIT_BANK0_XECORE31\0"
   /* 31904 */ "ICACHE_HIT_BANK0_XECORE4\0"
   /* 31929 */ "ICACHE_HIT_BANK0_XECORE5\0"
   /* 31954 */ "ICACHE_HIT_BANK0_XECORE6\0"
   /* 31979 */ "ICACHE_HIT_BANK0_XECORE7\0"
   /* 32004 */ "ICACHE_HIT_BANK0_XECORE8\0"
   /* 32029 */ "ICACHE_HIT_BANK0_XECORE9\0"
   /* 32054 */ "ICACHE_HIT_BANK1_XECORE0\0"
   /* 32079 */ "ICACHE_HIT_BANK1_XECORE1\0"
   /* 32104 */ "ICACHE_HIT_BANK1_XECORE10\0"
   /* 32130 */ "ICACHE_HIT_BANK1_XECORE11\0"
   /* 32156 */ "ICACHE_HIT_BANK1_XECORE12\0"
   /* 32182 */ "ICACHE_HIT_BANK1_XECORE13\0"
   /* 32208 */ "ICACHE_HIT_BANK1_XECORE14\0"
   /* 32234 */ "ICACHE_HIT_BANK1_XECORE15\0"
   /* 32260 */ "ICACHE_HIT_BANK1_XECORE16\0"
   /* 32286 */ "ICACHE_HIT_BANK1_XECORE17\0"
   /* 32312 */ "ICACHE_HIT_BANK1_XECORE18\0"
   /* 32338 */ "ICACHE_HIT_BANK1_XECORE19\0"
   /* 32364 */ "ICACHE_HIT_BANK1_XECORE2\0"
   /* 32389 */ "ICACHE_HIT_BANK1_XECORE20\0"
   /* 32415 */ "ICACHE_HIT_BANK1_XECORE21\0"
   /* 32441 */ "ICACHE_HIT_BANK1_XECORE22\0"
   /* 32467 */ "ICACHE_HIT_BANK1_XECORE23\0"
   /* 32493 */ "ICACHE_HIT_BANK1_XECORE24\0"
   /* 32519 */ "ICACHE_HIT_BANK1_XECORE25\0"
   /* 32545 */ "ICACHE_HIT_BANK1_XECORE26\0"
   /* 32571 */ "ICACHE_HIT_BANK1_XECORE27\0"
   /* 32597 */ "ICACHE_HIT_BANK1_XECORE28\0"
   /* 32623 */ "ICACHE_HIT_BANK1_XECORE29\0"
   /* 32649 */ "ICACHE_HIT_BANK1_XECORE3\0"
   /* 32674 */ "ICACHE_HIT_BANK1_XECORE30\0"
   /* 32700 */ "ICACHE_HIT_BANK1_XECORE31\0"
   /* 32726 */ "ICACHE_HIT_BANK1_XECORE4\0"
   /* 32751 */ "ICACHE_HIT_BANK1_XECORE5\0"
   /* 32776 */ "ICACHE_HIT_BANK1_XECORE6\0"
   /* 32801 */ "ICACHE_HIT_BANK1_XECORE7\0"
   /* 32826 */ "ICACHE_HIT_BANK1_XECORE8\0"
   /* 32851 */ "ICACHE_HIT_BANK1_XECORE9\0"
   /* 32876 */ "ICACHE_HIT_BANK2_XECORE0\0"
   /* 32901 */ "ICACHE_HIT_BANK2_XECORE1\0"
   /* 32926 */ "ICACHE_HIT_BANK2_XECORE10\0"
   /* 32952 */ "ICACHE_HIT_BANK2_XECORE11\0"
   /* 32978 */ "ICACHE_HIT_BANK2_XECORE12\0"
   /* 33004 */ "ICACHE_HIT_BANK2_XECORE13\0"
   /* 33030 */ "ICACHE_HIT_BANK2_XECORE14\0"
   /* 33056 */ "ICACHE_HIT_BANK2_XECORE15\0"
   /* 33082 */ "ICACHE_HIT_BANK2_XECORE16\0"
   /* 33108 */ "ICACHE_HIT_BANK2_XECORE17\0"
   /* 33134 */ "ICACHE_HIT_BANK2_XECORE18\0"
   /* 33160 */ "ICACHE_HIT_BANK2_XECORE19\0"
   /* 33186 */ "ICACHE_HIT_BANK2_XECORE2\0"
   /* 33211 */ "ICACHE_HIT_BANK2_XECORE20\0"
   /* 33237 */ "ICACHE_HIT_BANK2_XECORE21\0"
   /* 33263 */ "ICACHE_HIT_BANK2_XECORE22\0"
   /* 33289 */ "ICACHE_HIT_BANK2_XECORE23\0"
   /* 33315 */ "ICACHE_HIT_BANK2_XECORE24\0"
   /* 33341 */ "ICACHE_HIT_BANK2_XECORE25\0"
   /* 33367 */ "ICACHE_HIT_BANK2_XECORE26\0"
   /* 33393 */ "ICACHE_HIT_BANK2_XECORE27\0"
   /* 33419 */ "ICACHE_HIT_BANK2_XECORE28\0"
   /* 33445 */ "ICACHE_HIT_BANK2_XECORE29\0"
   /* 33471 */ "ICACHE_HIT_BANK2_XECORE3\0"
   /* 33496 */ "ICACHE_HIT_BANK2_XECORE30\0"
   /* 33522 */ "ICACHE_HIT_BANK2_XECORE31\0"
   /* 33548 */ "ICACHE_HIT_BANK2_XECORE4\0"
   /* 33573 */ "ICACHE_HIT_BANK2_XECORE5\0"
   /* 33598 */ "ICACHE_HIT_BANK2_XECORE6\0"
   /* 33623 */ "ICACHE_HIT_BANK2_XECORE7\0"
   /* 33648 */ "ICACHE_HIT_BANK2_XECORE8\0"
   /* 33673 */ "ICACHE_HIT_BANK2_XECORE9\0"
   /* 33698 */ "ICACHE_HIT_BANK3_XECORE0\0"
   /* 33723 */ "ICACHE_HIT_BANK3_XECORE1\0"
   /* 33748 */ "ICACHE_HIT_BANK3_XECORE10\0"
   /* 33774 */ "ICACHE_HIT_BANK3_XECORE11\0"
   /* 33800 */ "ICACHE_HIT_BANK3_XECORE12\0"
   /* 33826 */ "ICACHE_HIT_BANK3_XECORE13\0"
   /* 33852 */ "ICACHE_HIT_BANK3_XECORE14\0"
   /* 33878 */ "ICACHE_HIT_BANK3_XECORE15\0"
   /* 33904 */ "ICACHE_HIT_BANK3_XECORE16\0"
   /* 33930 */ "ICACHE_HIT_BANK3_XECORE17\0"
   /* 33956 */ "ICACHE_HIT_BANK3_XECORE18\0"
   /* 33982 */ "ICACHE_HIT_BANK3_XECORE19\0"
   /* 34008 */ "ICACHE_HIT_BANK3_XECORE2\0"
   /* 34033 */ "ICACHE_HIT_BANK3_XECORE20\0"
   /* 34059 */ "ICACHE_HIT_BANK3_XECORE21\0"
   /* 34085 */ "ICACHE_HIT_BANK3_XECORE22\0"
   /* 34111 */ "ICACHE_HIT_BANK3_XECORE23\0"
   /* 34137 */ "ICACHE_HIT_BANK3_XECORE24\0"
   /* 34163 */ "ICACHE_HIT_BANK3_XECORE25\0"
   /* 34189 */ "ICACHE_HIT_BANK3_XECORE26\0"
   /* 34215 */ "ICACHE_HIT_BANK3_XECORE27\0"
   /* 34241 */ "ICACHE_HIT_BANK3_XECORE28\0"
   /* 34267 */ "ICACHE_HIT_BANK3_XECORE29\0"
   /* 34293 */ "ICACHE_HIT_BANK3_XECORE3\0"
   /* 34318 */ "ICACHE_HIT_BANK3_XECORE30\0"
   /* 34344 */ "ICACHE_HIT_BANK3_XECORE31\0"
   /* 34370 */ "ICACHE_HIT_BANK3_XECORE4\0"
   /* 34395 */ "ICACHE_HIT_BANK3_XECORE5\0"
   /* 34420 */ "ICACHE_HIT_BANK3_XECORE6\0"
   /* 34445 */ "ICACHE_HIT_BANK3_XECORE7\0"
   /* 34470 */ "ICACHE_HIT_BANK3_XECORE8\0"
   /* 34495 */ "ICACHE_HIT_BANK3_XECORE9\0"
   /* 34520 */ "ICACHE_L3_HIT_L3BANK0\0"
   /* 34542 */ "ICACHE_L3_HIT_L3BANK1\0"
   /* 34564 */ "ICACHE_L3_HIT_L3BANK10\0"
   /* 34587 */ "ICACHE_L3_HIT_L3BANK11\0"
   /* 34610 */ "ICACHE_L3_HIT_L3BANK12\0"
   /* 34633 */ "ICACHE_L3_HIT_L3BANK13\0"
   /* 34656 */ "ICACHE_L3_HIT_L3BANK14\0"
   /* 34679 */ "ICACHE_L3_HIT_L3BANK15\0"
   /* 34702 */ "ICACHE_L3_HIT_L3BANK16\0"
   /* 34725 */ "ICACHE_L3_HIT_L3BANK17\0"
   /* 34748 */ "ICACHE_L3_HIT_L3BANK18\0"
   /* 34771 */ "ICACHE_L3_HIT_L3BANK19\0"
   /* 34794 */ "ICACHE_L3_HIT_L3BANK2\0"
   /* 34816 */ "ICACHE_L3_HIT_L3BANK20\0"
   /* 34839 */ "ICACHE_L3_HIT_L3BANK21\0"
   /* 34862 */ "ICACHE_L3_HIT_L3BANK22\0"
   /* 34885 */ "ICACHE_L3_HIT_L3BANK23\0"
   /* 34908 */ "ICACHE_L3_HIT_L3BANK24\0"
   /* 34931 */ "ICACHE_L3_HIT_L3BANK25\0"
   /* 34954 */ "ICACHE_L3_HIT_L3BANK26\0"
   /* 34977 */ "ICACHE_L3_HIT_L3BANK27\0"
   /* 35000 */ "ICACHE_L3_HIT_L3BANK28\0"
   /* 35023 */ "ICACHE_L3_HIT_L3BANK29\0"
   /* 35046 */ "ICACHE_L3_HIT_L3BANK3\0"
   /* 35068 */ "ICACHE_L3_HIT_L3BANK30\0"
   /* 35091 */ "ICACHE_L3_HIT_L3BANK31\0"
   /* 35114 */ "ICACHE_L3_HIT_L3BANK4\0"
   /* 35136 */ "ICACHE_L3_HIT_L3BANK5\0"
   /* 35158 */ "ICACHE_L3_HIT_L3BANK6\0"
   /* 35180 */ "ICACHE_L3_HIT_L3BANK7\0"
   /* 35202 */ "ICACHE_L3_HIT_L3BANK8\0"
   /* 35224 */ "ICACHE_L3_HIT_L3BANK9\0"
   /* 35246 */ "ICACHE_L3_READ_L3BANK0\0"
   /* 35269 */ "ICACHE_L3_READ_L3BANK1\0"
   /* 35292 */ "ICACHE_L3_READ_L3BANK10\0"
   /* 35316 */ "ICACHE_L3_READ_L3BANK11\0"
   /* 35340 */ "ICACHE_L3_READ_L3BANK12\0"
   /* 35364 */ "ICACHE_L3_READ_L3BANK13\0"
   /* 35388 */ "ICACHE_L3_READ_L3BANK14\0"
   /* 35412 */ "ICACHE_L3_READ_L3BANK15\0"
   /* 35436 */ "ICACHE_L3_READ_L3BANK16\0"
   /* 35460 */ "ICACHE_L3_READ_L3BANK17\0"
   /* 35484 */ "ICACHE_L3_READ_L3BANK18\0"
   /* 35508 */ "ICACHE_L3_READ_L3BANK19\0"
   /* 35532 */ "ICACHE_L3_READ_L3BANK2\0"
   /* 35555 */ "ICACHE_L3_READ_L3BANK20\0"
   /* 35579 */ "ICACHE_L3_READ_L3BANK21\0"
   /* 35603 */ "ICACHE_L3_READ_L3BANK22\0"
   /* 35627 */ "ICACHE_L3_READ_L3BANK23\0"
   /* 35651 */ "ICACHE_L3_READ_L3BANK24\0"
   /* 35675 */ "ICACHE_L3_READ_L3BANK25\0"
   /* 35699 */ "ICACHE_L3_READ_L3BANK26\0"
   /* 35723 */ "ICACHE_L3_READ_L3BANK27\0"
   /* 35747 */ "ICACHE_L3_READ_L3BANK28\0"
   /* 35771 */ "ICACHE_L3_READ_L3BANK29\0"
   /* 35795 */ "ICACHE_L3_READ_L3BANK3\0"
   /* 35818 */ "ICACHE_L3_READ_L3BANK30\0"
   /* 35842 */ "ICACHE_L3_READ_L3BANK31\0"
   /* 35866 */ "ICACHE_L3_READ_L3BANK4\0"
   /* 35889 */ "ICACHE_L3_READ_L3BANK5\0"
   /* 35912 */ "ICACHE_L3_READ_L3BANK6\0"
   /* 35935 */ "ICACHE_L3_READ_L3BANK7\0"
   /* 35958 */ "ICACHE_L3_READ_L3BANK8\0"
   /* 35981 */ "ICACHE_L3_READ_L3BANK9\0"
   /* 36004 */ "ICACHE_MISS_BANK0_XECORE0\0"
   /* 36030 */ "ICACHE_MISS_BANK0_XECORE1\0"
   /* 36056 */ "ICACHE_MISS_BANK0_XECORE10\0"
   /* 36083 */ "ICACHE_MISS_BANK0_XECORE11\0"
   /* 36110 */ "ICACHE_MISS_BANK0_XECORE12\0"
   /* 36137 */ "ICACHE_MISS_BANK0_XECORE13\0"
   /* 36164 */ "ICACHE_MISS_BANK0_XECORE14\0"
   /* 36191 */ "ICACHE_MISS_BANK0_XECORE15\0"
   /* 36218 */ "ICACHE_MISS_BANK0_XECORE16\0"
   /* 36245 */ "ICACHE_MISS_BANK0_XECORE17\0"
   /* 36272 */ "ICACHE_MISS_BANK0_XECORE18\0"
   /* 36299 */ "ICACHE_MISS_BANK0_XECORE19\0"
   /* 36326 */ "ICACHE_MISS_BANK0_XECORE2\0"
   /* 36352 */ "ICACHE_MISS_BANK0_XECORE20\0"
   /* 36379 */ "ICACHE_MISS_BANK0_XECORE21\0"
   /* 36406 */ "ICACHE_MISS_BANK0_XECORE22\0"
   /* 36433 */ "ICACHE_MISS_BANK0_XECORE23\0"
   /* 36460 */ "ICACHE_MISS_BANK0_XECORE24\0"
   /* 36487 */ "ICACHE_MISS_BANK0_XECORE25\0"
   /* 36514 */ "ICACHE_MISS_BANK0_XECORE26\0"
   /* 36541 */ "ICACHE_MISS_BANK0_XECORE27\0"
   /* 36568 */ "ICACHE_MISS_BANK0_XECORE28\0"
   /* 36595 */ "ICACHE_MISS_BANK0_XECORE29\0"
   /* 36622 */ "ICACHE_MISS_BANK0_XECORE3\0"
   /* 36648 */ "ICACHE_MISS_BANK0_XECORE30\0"
   /* 36675 */ "ICACHE_MISS_BANK0_XECORE31\0"
   /* 36702 */ "ICACHE_MISS_BANK0_XECORE4\0"
   /* 36728 */ "ICACHE_MISS_BANK0_XECORE5\0"
   /* 36754 */ "ICACHE_MISS_BANK0_XECORE6\0"
   /* 36780 */ "ICACHE_MISS_BANK0_XECORE7\0"
   /* 36806 */ "ICACHE_MISS_BANK0_XECORE8\0"
   /* 36832 */ "ICACHE_MISS_BANK0_XECORE9\0"
   /* 36858 */ "ICACHE_MISS_BANK1_XECORE0\0"
   /* 36884 */ "ICACHE_MISS_BANK1_XECORE1\0"
   /* 36910 */ "ICACHE_MISS_BANK1_XECORE10\0"
   /* 36937 */ "ICACHE_MISS_BANK1_XECORE11\0"
   /* 36964 */ "ICACHE_MISS_BANK1_XECORE12\0"
   /* 36991 */ "ICACHE_MISS_BANK1_XECORE13\0"
   /* 37018 */ "ICACHE_MISS_BANK1_XECORE14\0"
   /* 37045 */ "ICACHE_MISS_BANK1_XECORE15\0"
   /* 37072 */ "ICACHE_MISS_BANK1_XECORE16\0"
   /* 37099 */ "ICACHE_MISS_BANK1_XECORE17\0"
   /* 37126 */ "ICACHE_MISS_BANK1_XECORE18\0"
   /* 37153 */ "ICACHE_MISS_BANK1_XECORE19\0"
   /* 37180 */ "ICACHE_MISS_BANK1_XECORE2\0"
   /* 37206 */ "ICACHE_MISS_BANK1_XECORE20\0"
   /* 37233 */ "ICACHE_MISS_BANK1_XECORE21\0"
   /* 37260 */ "ICACHE_MISS_BANK1_XECORE22\0"
   /* 37287 */ "ICACHE_MISS_BANK1_XECORE23\0"
   /* 37314 */ "ICACHE_MISS_BANK1_XECORE24\0"
   /* 37341 */ "ICACHE_MISS_BANK1_XECORE25\0"
   /* 37368 */ "ICACHE_MISS_BANK1_XECORE26\0"
   /* 37395 */ "ICACHE_MISS_BANK1_XECORE27\0"
   /* 37422 */ "ICACHE_MISS_BANK1_XECORE28\0"
   /* 37449 */ "ICACHE_MISS_BANK1_XECORE29\0"
   /* 37476 */ "ICACHE_MISS_BANK1_XECORE3\0"
   /* 37502 */ "ICACHE_MISS_BANK1_XECORE30\0"
   /* 37529 */ "ICACHE_MISS_BANK1_XECORE31\0"
   /* 37556 */ "ICACHE_MISS_BANK1_XECORE4\0"
   /* 37582 */ "ICACHE_MISS_BANK1_XECORE5\0"
   /* 37608 */ "ICACHE_MISS_BANK1_XECORE6\0"
   /* 37634 */ "ICACHE_MISS_BANK1_XECORE7\0"
   /* 37660 */ "ICACHE_MISS_BANK1_XECORE8\0"
   /* 37686 */ "ICACHE_MISS_BANK1_XECORE9\0"
   /* 37712 */ "ICACHE_MISS_BANK2_XECORE0\0"
   /* 37738 */ "ICACHE_MISS_BANK2_XECORE1\0"
   /* 37764 */ "ICACHE_MISS_BANK2_XECORE10\0"
   /* 37791 */ "ICACHE_MISS_BANK2_XECORE11\0"
   /* 37818 */ "ICACHE_MISS_BANK2_XECORE12\0"
   /* 37845 */ "ICACHE_MISS_BANK2_XECORE13\0"
   /* 37872 */ "ICACHE_MISS_BANK2_XECORE14\0"
   /* 37899 */ "ICACHE_MISS_BANK2_XECORE15\0"
   /* 37926 */ "ICACHE_MISS_BANK2_XECORE16\0"
   /* 37953 */ "ICACHE_MISS_BANK2_XECORE17\0"
   /* 37980 */ "ICACHE_MISS_BANK2_XECORE18\0"
   /* 38007 */ "ICACHE_MISS_BANK2_XECORE19\0"
   /* 38034 */ "ICACHE_MISS_BANK2_XECORE2\0"
   /* 38060 */ "ICACHE_MISS_BANK2_XECORE20\0"
   /* 38087 */ "ICACHE_MISS_BANK2_XECORE21\0"
   /* 38114 */ "ICACHE_MISS_BANK2_XECORE22\0"
   /* 38141 */ "ICACHE_MISS_BANK2_XECORE23\0"
   /* 38168 */ "ICACHE_MISS_BANK2_XECORE24\0"
   /* 38195 */ "ICACHE_MISS_BANK2_XECORE25\0"
   /* 38222 */ "ICACHE_MISS_BANK2_XECORE26\0"
   /* 38249 */ "ICACHE_MISS_BANK2_XECORE27\0"
   /* 38276 */ "ICACHE_MISS_BANK2_XECORE28\0"
   /* 38303 */ "ICACHE_MISS_BANK2_XECORE29\0"
   /* 38330 */ "ICACHE_MISS_BANK2_XECORE3\0"
   /* 38356 */ "ICACHE_MISS_BANK2_XECORE30\0"
   /* 38383 */ "ICACHE_MISS_BANK2_XECORE31\0"
   /* 38410 */ "ICACHE_MISS_BANK2_XECORE4\0"
   /* 38436 */ "ICACHE_MISS_BANK2_XECORE5\0"
   /* 38462 */ "ICACHE_MISS_BANK2_XECORE6\0"
   /* 38488 */ "ICACHE_MISS_BANK2_XECORE7\0"
   /* 38514 */ "ICACHE_MISS_BANK2_XECORE8\0"
   /* 38540 */ "ICACHE_MISS_BANK2_XECORE9\0"
   /* 38566 */ "ICACHE_MISS_BANK3_XECORE0\0"
   /* 38592 */ "ICACHE_MISS_BANK3_XECORE1\0"
   /* 38618 */ "ICACHE_MISS_BANK3_XECORE10\0"
   /* 38645 */ "ICACHE_MISS_BANK3_XECORE11\0"
   /* 38672 */ "ICACHE_MISS_BANK3_XECORE12\0"
   /* 38699 */ "ICACHE_MISS_BANK3_XECORE13\0"
   /* 38726 */ "ICACHE_MISS_BANK3_XECORE14\0"
   /* 38753 */ "ICACHE_MISS_BANK3_XECORE15\0"
   /* 38780 */ "ICACHE_MISS_BANK3_XECORE16\0"
   /* 38807 */ "ICACHE_MISS_BANK3_XECORE17\0"
   /* 38834 */ "ICACHE_MISS_BANK3_XECORE18\0"
   /* 38861 */ "ICACHE_MISS_BANK3_XECORE19\0"
   /* 38888 */ "ICACHE_MISS_BANK3_XECORE2\0"
   /* 38914 */ "ICACHE_MISS_BANK3_XECORE20\0"
   /* 38941 */ "ICACHE_MISS_BANK3_XECORE21\0"
   /* 38968 */ "ICACHE_MISS_BANK3_XECORE22\0"
   /* 38995 */ "ICACHE_MISS_BANK3_XECORE23\0"
   /* 39022 */ "ICACHE_MISS_BANK3_XECORE24\0"
   /* 39049 */ "ICACHE_MISS_BANK3_XECORE25\0"
   /* 39076 */ "ICACHE_MISS_BANK3_XECORE26\0"
   /* 39103 */ "ICACHE_MISS_BANK3_XECORE27\0"
   /* 39130 */ "ICACHE_MISS_BANK3_XECORE28\0"
   /* 39157 */ "ICACHE_MISS_BANK3_XECORE29\0"
   /* 39184 */ "ICACHE_MISS_BANK3_XECORE3\0"
   /* 39210 */ "ICACHE_MISS_BANK3_XECORE30\0"
   /* 39237 */ "ICACHE_MISS_BANK3_XECORE31\0"
   /* 39264 */ "ICACHE_MISS_BANK3_XECORE4\0"
   /* 39290 */ "ICACHE_MISS_BANK3_XECORE5\0"
   /* 39316 */ "ICACHE_MISS_BANK3_XECORE6\0"
   /* 39342 */ "ICACHE_MISS_BANK3_XECORE7\0"
   /* 39368 */ "ICACHE_MISS_BANK3_XECORE8\0"
   /* 39394 */ "ICACHE_MISS_BANK3_XECORE9\0"
   /* 39420 */ "IZ_OUTPUT_READY_ZPIPE0\0"
   /* 39443 */ "IZ_OUTPUT_READY_ZPIPE1\0"
   /* 39466 */ "IZ_OUTPUT_READY_ZPIPE10\0"
   /* 39490 */ "IZ_OUTPUT_READY_ZPIPE11\0"
   /* 39514 */ "IZ_OUTPUT_READY_ZPIPE12\0"
   /* 39538 */ "IZ_OUTPUT_READY_ZPIPE13\0"
   /* 39562 */ "IZ_OUTPUT_READY_ZPIPE14\0"
   /* 39586 */ "IZ_OUTPUT_READY_ZPIPE15\0"
   /* 39610 */ "IZ_OUTPUT_READY_ZPIPE2\0"
   /* 39633 */ "IZ_OUTPUT_READY_ZPIPE3\0"
   /* 39656 */ "IZ_OUTPUT_READY_ZPIPE4\0"
   /* 39679 */ "IZ_OUTPUT_READY_ZPIPE5\0"
   /* 39702 */ "IZ_OUTPUT_READY_ZPIPE6\0"
   /* 39725 */ "IZ_OUTPUT_READY_ZPIPE7\0"
   /* 39748 */ "IZ_OUTPUT_READY_ZPIPE8\0"
   /* 39771 */ "IZ_OUTPUT_READY_ZPIPE9\0"
   /* 39794 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0\0"
   /* 39829 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1\0"
   /* 39864 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE10\0"
   /* 39900 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE11\0"
   /* 39936 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE12\0"
   /* 39972 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE13\0"
   /* 40008 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE14\0"
   /* 40044 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE15\0"
   /* 40080 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2\0"
   /* 40115 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3\0"
   /* 40150 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4\0"
   /* 40185 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5\0"
   /* 40220 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6\0"
   /* 40255 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7\0"
   /* 40290 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE8\0"
   /* 40325 */ "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE9\0"
   /* 40360 */ "L30Bank0Active\0"
   /* 40375 */ "L30Bank0InputAvailable\0"
   /* 40398 */ "L30Bank0OutputReady\0"
   /* 40418 */ "L30Bank0Stalled\0"
   /* 40434 */ "L30Bank1Active\0"
   /* 40449 */ "L30Bank1InputAvailable\0"
   /* 40472 */ "L30Bank1OutputReady\0"
   /* 40492 */ "L30Bank1Stalled\0"
   /* 40508 */ "L30Bank2Active\0"
   /* 40523 */ "L30Bank2InputAvailable\0"
   /* 40546 */ "L30Bank2OutputReady\0"
   /* 40566 */ "L30Bank2Stalled\0"
   /* 40582 */ "L30Bank3Active\0"
   /* 40597 */ "L30Bank3InputAvailable\0"
   /* 40620 */ "L30Bank3OutputReady\0"
   /* 40640 */ "L30Bank3Stalled\0"
   /* 40656 */ "L30Bank4Active\0"
   /* 40671 */ "L30Bank4InputAvailable\0"
   /* 40694 */ "L30Bank4OutputReady\0"
   /* 40714 */ "L30Bank4Stalled\0"
   /* 40730 */ "L30Bank5Active\0"
   /* 40745 */ "L30Bank5InputAvailable\0"
   /* 40768 */ "L30Bank5OutputReady\0"
   /* 40788 */ "L30Bank5Stalled\0"
   /* 40804 */ "L30Bank6Active\0"
   /* 40819 */ "L30Bank6InputAvailable\0"
   /* 40842 */ "L30Bank6OutputReady\0"
   /* 40862 */ "L30Bank7Active\0"
   /* 40877 */ "L30Bank7InputAvailable\0"
   /* 40900 */ "L30Bank7OutputReady\0"
   /* 40920 */ "L31Bank0Active\0"
   /* 40935 */ "L31Bank0InputAvailable\0"
   /* 40958 */ "L31Bank0OutputReady\0"
   /* 40978 */ "L31Bank0Stalled\0"
   /* 40994 */ "L31Bank1Active\0"
   /* 41009 */ "L31Bank1InputAvailable\0"
   /* 41032 */ "L31Bank1OutputReady\0"
   /* 41052 */ "L31Bank1Stalled\0"
   /* 41068 */ "L31Bank2Active\0"
   /* 41083 */ "L31Bank2InputAvailable\0"
   /* 41106 */ "L31Bank2OutputReady\0"
   /* 41126 */ "L31Bank2Stalled\0"
   /* 41142 */ "L31Bank3Active\0"
   /* 41157 */ "L31Bank3InputAvailable\0"
   /* 41180 */ "L31Bank3OutputReady\0"
   /* 41200 */ "L31Bank3Stalled\0"
   /* 41216 */ "L31Bank4InputAvailable\0"
   /* 41239 */ "L31Bank4OutputReady\0"
   /* 41259 */ "L31Bank5InputAvailable\0"
   /* 41282 */ "L31Bank5OutputReady\0"
   /* 41302 */ "L31Bank6InputAvailable\0"
   /* 41325 */ "L31Bank6OutputReady\0"
   /* 41345 */ "L31Bank7InputAvailable\0"
   /* 41368 */ "L31Bank7OutputReady\0"
   /* 41388 */ "L32Bank0InputAvailable\0"
   /* 41411 */ "L32Bank0OutputReady\0"
   /* 41431 */ "L32Bank1InputAvailable\0"
   /* 41454 */ "L32Bank1OutputReady\0"
   /* 41474 */ "L32Bank2InputAvailable\0"
   /* 41497 */ "L32Bank2OutputReady\0"
   /* 41517 */ "L32Bank3InputAvailable\0"
   /* 41540 */ "L32Bank3OutputReady\0"
   /* 41560 */ "L32Bank4InputAvailable\0"
   /* 41583 */ "L32Bank4OutputReady\0"
   /* 41603 */ "L32Bank5InputAvailable\0"
   /* 41626 */ "L32Bank5OutputReady\0"
   /* 41646 */ "L32Bank6InputAvailable\0"
   /* 41669 */ "L32Bank6OutputReady\0"
   /* 41689 */ "L32Bank7InputAvailable\0"
   /* 41712 */ "L32Bank7OutputReady\0"
   /* 41732 */ "L33Bank0InputAvailable\0"
   /* 41755 */ "L33Bank0OutputReady\0"
   /* 41775 */ "L33Bank1InputAvailable\0"
   /* 41798 */ "L33Bank1OutputReady\0"
   /* 41818 */ "L33Bank2InputAvailable\0"
   /* 41841 */ "L33Bank2OutputReady\0"
   /* 41861 */ "L33Bank3InputAvailable\0"
   /* 41884 */ "L33Bank3OutputReady\0"
   /* 41904 */ "L33Bank4InputAvailable\0"
   /* 41927 */ "L33Bank4OutputReady\0"
   /* 41947 */ "L33Bank5InputAvailable\0"
   /* 41970 */ "L33Bank5OutputReady\0"
   /* 41990 */ "L33Bank6InputAvailable\0"
   /* 42013 */ "L33Bank6OutputReady\0"
   /* 42033 */ "L33Bank7InputAvailable\0"
   /* 42056 */ "L33Bank7OutputReady\0"
   /* 42076 */ "L3Accesses\0"
   /* 42087 */ "L3Bank00Accesses\0"
   /* 42104 */ "L3Bank00IcAccesses\0"
   /* 42123 */ "L3Bank00IcHits\0"
   /* 42138 */ "L3Bank01Accesses\0"
   /* 42155 */ "L3Bank02Accesses\0"
   /* 42172 */ "L3Bank03Accesses\0"
   /* 42189 */ "L3Bank04Accesses\0"
   /* 42206 */ "L3Bank05Accesses\0"
   /* 42223 */ "L3Bank06Accesses\0"
   /* 42240 */ "L3Bank07Accesses\0"
   /* 42257 */ "L3Bank10Accesses\0"
   /* 42274 */ "L3Bank10IcAccesses\0"
   /* 42293 */ "L3Bank10IcHits\0"
   /* 42308 */ "L3Bank11Accesses\0"
   /* 42325 */ "L3Bank12Accesses\0"
   /* 42342 */ "L3Bank13Accesses\0"
   /* 42359 */ "L3Lookups\0"
   /* 42369 */ "L3Misses\0"
   /* 42378 */ "L3SamplerThroughput\0"
   /* 42398 */ "L3ShaderThroughput\0"
   /* 42417 */ "L3TotalThroughput\0"
   /* 42435 */ "L3_ATOMIC_ACCESS_L3BANK0\0"
   /* 42460 */ "L3_ATOMIC_ACCESS_L3BANK1\0"
   /* 42485 */ "L3_ATOMIC_ACCESS_L3BANK10\0"
   /* 42511 */ "L3_ATOMIC_ACCESS_L3BANK11\0"
   /* 42537 */ "L3_ATOMIC_ACCESS_L3BANK12\0"
   /* 42563 */ "L3_ATOMIC_ACCESS_L3BANK13\0"
   /* 42589 */ "L3_ATOMIC_ACCESS_L3BANK14\0"
   /* 42615 */ "L3_ATOMIC_ACCESS_L3BANK15\0"
   /* 42641 */ "L3_ATOMIC_ACCESS_L3BANK16\0"
   /* 42667 */ "L3_ATOMIC_ACCESS_L3BANK17\0"
   /* 42693 */ "L3_ATOMIC_ACCESS_L3BANK18\0"
   /* 42719 */ "L3_ATOMIC_ACCESS_L3BANK19\0"
   /* 42745 */ "L3_ATOMIC_ACCESS_L3BANK2\0"
   /* 42770 */ "L3_ATOMIC_ACCESS_L3BANK20\0"
   /* 42796 */ "L3_ATOMIC_ACCESS_L3BANK21\0"
   /* 42822 */ "L3_ATOMIC_ACCESS_L3BANK22\0"
   /* 42848 */ "L3_ATOMIC_ACCESS_L3BANK23\0"
   /* 42874 */ "L3_ATOMIC_ACCESS_L3BANK24\0"
   /* 42900 */ "L3_ATOMIC_ACCESS_L3BANK25\0"
   /* 42926 */ "L3_ATOMIC_ACCESS_L3BANK26\0"
   /* 42952 */ "L3_ATOMIC_ACCESS_L3BANK27\0"
   /* 42978 */ "L3_ATOMIC_ACCESS_L3BANK28\0"
   /* 43004 */ "L3_ATOMIC_ACCESS_L3BANK29\0"
   /* 43030 */ "L3_ATOMIC_ACCESS_L3BANK3\0"
   /* 43055 */ "L3_ATOMIC_ACCESS_L3BANK30\0"
   /* 43081 */ "L3_ATOMIC_ACCESS_L3BANK31\0"
   /* 43107 */ "L3_ATOMIC_ACCESS_L3BANK4\0"
   /* 43132 */ "L3_ATOMIC_ACCESS_L3BANK5\0"
   /* 43157 */ "L3_ATOMIC_ACCESS_L3BANK6\0"
   /* 43182 */ "L3_ATOMIC_ACCESS_L3BANK7\0"
   /* 43207 */ "L3_ATOMIC_ACCESS_L3BANK8\0"
   /* 43232 */ "L3_ATOMIC_ACCESS_L3BANK9\0"
   /* 43257 */ "L3_BUSY_L3BANK0\0"
   /* 43273 */ "L3_BUSY_L3BANK1\0"
   /* 43289 */ "L3_BUSY_L3BANK10\0"
   /* 43306 */ "L3_BUSY_L3BANK11\0"
   /* 43323 */ "L3_BUSY_L3BANK12\0"
   /* 43340 */ "L3_BUSY_L3BANK13\0"
   /* 43357 */ "L3_BUSY_L3BANK14\0"
   /* 43374 */ "L3_BUSY_L3BANK15\0"
   /* 43391 */ "L3_BUSY_L3BANK16\0"
   /* 43408 */ "L3_BUSY_L3BANK17\0"
   /* 43425 */ "L3_BUSY_L3BANK18\0"
   /* 43442 */ "L3_BUSY_L3BANK19\0"
   /* 43459 */ "L3_BUSY_L3BANK2\0"
   /* 43475 */ "L3_BUSY_L3BANK20\0"
   /* 43492 */ "L3_BUSY_L3BANK21\0"
   /* 43509 */ "L3_BUSY_L3BANK22\0"
   /* 43526 */ "L3_BUSY_L3BANK23\0"
   /* 43543 */ "L3_BUSY_L3BANK24\0"
   /* 43560 */ "L3_BUSY_L3BANK25\0"
   /* 43577 */ "L3_BUSY_L3BANK26\0"
   /* 43594 */ "L3_BUSY_L3BANK27\0"
   /* 43611 */ "L3_BUSY_L3BANK28\0"
   /* 43628 */ "L3_BUSY_L3BANK29\0"
   /* 43645 */ "L3_BUSY_L3BANK3\0"
   /* 43661 */ "L3_BUSY_L3BANK30\0"
   /* 43678 */ "L3_BUSY_L3BANK31\0"
   /* 43695 */ "L3_BUSY_L3BANK4\0"
   /* 43711 */ "L3_BUSY_L3BANK5\0"
   /* 43727 */ "L3_BUSY_L3BANK6\0"
   /* 43743 */ "L3_BUSY_L3BANK7\0"
   /* 43759 */ "L3_BUSY_L3BANK8\0"
   /* 43775 */ "L3_BUSY_L3BANK9\0"
   /* 43791 */ "L3_BYTE_READ\0"
   /* 43804 */ "L3_BYTE_WRITE\0"
   /* 43818 */ "L3_HIT_L3BANK0\0"
   /* 43833 */ "L3_HIT_L3BANK1\0"
   /* 43848 */ "L3_HIT_L3BANK10\0"
   /* 43864 */ "L3_HIT_L3BANK11\0"
   /* 43880 */ "L3_HIT_L3BANK12\0"
   /* 43896 */ "L3_HIT_L3BANK13\0"
   /* 43912 */ "L3_HIT_L3BANK14\0"
   /* 43928 */ "L3_HIT_L3BANK15\0"
   /* 43944 */ "L3_HIT_L3BANK16\0"
   /* 43960 */ "L3_HIT_L3BANK17\0"
   /* 43976 */ "L3_HIT_L3BANK18\0"
   /* 43992 */ "L3_HIT_L3BANK19\0"
   /* 44008 */ "L3_HIT_L3BANK2\0"
   /* 44023 */ "L3_HIT_L3BANK20\0"
   /* 44039 */ "L3_HIT_L3BANK21\0"
   /* 44055 */ "L3_HIT_L3BANK22\0"
   /* 44071 */ "L3_HIT_L3BANK23\0"
   /* 44087 */ "L3_HIT_L3BANK24\0"
   /* 44103 */ "L3_HIT_L3BANK25\0"
   /* 44119 */ "L3_HIT_L3BANK26\0"
   /* 44135 */ "L3_HIT_L3BANK27\0"
   /* 44151 */ "L3_HIT_L3BANK28\0"
   /* 44167 */ "L3_HIT_L3BANK29\0"
   /* 44183 */ "L3_HIT_L3BANK3\0"
   /* 44198 */ "L3_HIT_L3BANK30\0"
   /* 44214 */ "L3_HIT_L3BANK31\0"
   /* 44230 */ "L3_HIT_L3BANK4\0"
   /* 44245 */ "L3_HIT_L3BANK5\0"
   /* 44260 */ "L3_HIT_L3BANK6\0"
   /* 44275 */ "L3_HIT_L3BANK7\0"
   /* 44290 */ "L3_HIT_L3BANK8\0"
   /* 44305 */ "L3_HIT_L3BANK9\0"
   /* 44320 */ "L3_INPUT_AVAILABLE_L3BANK0\0"
   /* 44347 */ "L3_INPUT_AVAILABLE_L3BANK1\0"
   /* 44374 */ "L3_INPUT_AVAILABLE_L3BANK10\0"
   /* 44402 */ "L3_INPUT_AVAILABLE_L3BANK11\0"
   /* 44430 */ "L3_INPUT_AVAILABLE_L3BANK12\0"
   /* 44458 */ "L3_INPUT_AVAILABLE_L3BANK13\0"
   /* 44486 */ "L3_INPUT_AVAILABLE_L3BANK14\0"
   /* 44514 */ "L3_INPUT_AVAILABLE_L3BANK15\0"
   /* 44542 */ "L3_INPUT_AVAILABLE_L3BANK16\0"
   /* 44570 */ "L3_INPUT_AVAILABLE_L3BANK17\0"
   /* 44598 */ "L3_INPUT_AVAILABLE_L3BANK18\0"
   /* 44626 */ "L3_INPUT_AVAILABLE_L3BANK19\0"
   /* 44654 */ "L3_INPUT_AVAILABLE_L3BANK2\0"
   /* 44681 */ "L3_INPUT_AVAILABLE_L3BANK20\0"
   /* 44709 */ "L3_INPUT_AVAILABLE_L3BANK21\0"
   /* 44737 */ "L3_INPUT_AVAILABLE_L3BANK22\0"
   /* 44765 */ "L3_INPUT_AVAILABLE_L3BANK23\0"
   /* 44793 */ "L3_INPUT_AVAILABLE_L3BANK24\0"
   /* 44821 */ "L3_INPUT_AVAILABLE_L3BANK25\0"
   /* 44849 */ "L3_INPUT_AVAILABLE_L3BANK26\0"
   /* 44877 */ "L3_INPUT_AVAILABLE_L3BANK27\0"
   /* 44905 */ "L3_INPUT_AVAILABLE_L3BANK28\0"
   /* 44933 */ "L3_INPUT_AVAILABLE_L3BANK29\0"
   /* 44961 */ "L3_INPUT_AVAILABLE_L3BANK3\0"
   /* 44988 */ "L3_INPUT_AVAILABLE_L3BANK30\0"
   /* 45016 */ "L3_INPUT_AVAILABLE_L3BANK31\0"
   /* 45044 */ "L3_INPUT_AVAILABLE_L3BANK4\0"
   /* 45071 */ "L3_INPUT_AVAILABLE_L3BANK5\0"
   /* 45098 */ "L3_INPUT_AVAILABLE_L3BANK6\0"
   /* 45125 */ "L3_INPUT_AVAILABLE_L3BANK7\0"
   /* 45152 */ "L3_INPUT_AVAILABLE_L3BANK8\0"
   /* 45179 */ "L3_INPUT_AVAILABLE_L3BANK9\0"
   /* 45206 */ "L3_MISS_L3BANK0\0"
   /* 45222 */ "L3_MISS_L3BANK1\0"
   /* 45238 */ "L3_MISS_L3BANK10\0"
   /* 45255 */ "L3_MISS_L3BANK11\0"
   /* 45272 */ "L3_MISS_L3BANK12\0"
   /* 45289 */ "L3_MISS_L3BANK13\0"
   /* 45306 */ "L3_MISS_L3BANK14\0"
   /* 45323 */ "L3_MISS_L3BANK15\0"
   /* 45340 */ "L3_MISS_L3BANK16\0"
   /* 45357 */ "L3_MISS_L3BANK17\0"
   /* 45374 */ "L3_MISS_L3BANK18\0"
   /* 45391 */ "L3_MISS_L3BANK19\0"
   /* 45408 */ "L3_MISS_L3BANK2\0"
   /* 45424 */ "L3_MISS_L3BANK20\0"
   /* 45441 */ "L3_MISS_L3BANK21\0"
   /* 45458 */ "L3_MISS_L3BANK22\0"
   /* 45475 */ "L3_MISS_L3BANK23\0"
   /* 45492 */ "L3_MISS_L3BANK24\0"
   /* 45509 */ "L3_MISS_L3BANK25\0"
   /* 45526 */ "L3_MISS_L3BANK26\0"
   /* 45543 */ "L3_MISS_L3BANK27\0"
   /* 45560 */ "L3_MISS_L3BANK28\0"
   /* 45577 */ "L3_MISS_L3BANK29\0"
   /* 45594 */ "L3_MISS_L3BANK3\0"
   /* 45610 */ "L3_MISS_L3BANK30\0"
   /* 45627 */ "L3_MISS_L3BANK31\0"
   /* 45644 */ "L3_MISS_L3BANK4\0"
   /* 45660 */ "L3_MISS_L3BANK5\0"
   /* 45676 */ "L3_MISS_L3BANK6\0"
   /* 45692 */ "L3_MISS_L3BANK7\0"
   /* 45708 */ "L3_MISS_L3BANK8\0"
   /* 45724 */ "L3_MISS_L3BANK9\0"
   /* 45740 */ "L3_OUTPUT_READY_L3BANK0\0"
   /* 45764 */ "L3_OUTPUT_READY_L3BANK1\0"
   /* 45788 */ "L3_OUTPUT_READY_L3BANK10\0"
   /* 45813 */ "L3_OUTPUT_READY_L3BANK11\0"
   /* 45838 */ "L3_OUTPUT_READY_L3BANK12\0"
   /* 45863 */ "L3_OUTPUT_READY_L3BANK13\0"
   /* 45888 */ "L3_OUTPUT_READY_L3BANK14\0"
   /* 45913 */ "L3_OUTPUT_READY_L3BANK15\0"
   /* 45938 */ "L3_OUTPUT_READY_L3BANK16\0"
   /* 45963 */ "L3_OUTPUT_READY_L3BANK17\0"
   /* 45988 */ "L3_OUTPUT_READY_L3BANK18\0"
   /* 46013 */ "L3_OUTPUT_READY_L3BANK19\0"
   /* 46038 */ "L3_OUTPUT_READY_L3BANK2\0"
   /* 46062 */ "L3_OUTPUT_READY_L3BANK20\0"
   /* 46087 */ "L3_OUTPUT_READY_L3BANK21\0"
   /* 46112 */ "L3_OUTPUT_READY_L3BANK22\0"
   /* 46137 */ "L3_OUTPUT_READY_L3BANK23\0"
   /* 46162 */ "L3_OUTPUT_READY_L3BANK24\0"
   /* 46187 */ "L3_OUTPUT_READY_L3BANK25\0"
   /* 46212 */ "L3_OUTPUT_READY_L3BANK26\0"
   /* 46237 */ "L3_OUTPUT_READY_L3BANK27\0"
   /* 46262 */ "L3_OUTPUT_READY_L3BANK28\0"
   /* 46287 */ "L3_OUTPUT_READY_L3BANK29\0"
   /* 46312 */ "L3_OUTPUT_READY_L3BANK3\0"
   /* 46336 */ "L3_OUTPUT_READY_L3BANK30\0"
   /* 46361 */ "L3_OUTPUT_READY_L3BANK31\0"
   /* 46386 */ "L3_OUTPUT_READY_L3BANK4\0"
   /* 46410 */ "L3_OUTPUT_READY_L3BANK5\0"
   /* 46434 */ "L3_OUTPUT_READY_L3BANK6\0"
   /* 46458 */ "L3_OUTPUT_READY_L3BANK7\0"
   /* 46482 */ "L3_OUTPUT_READY_L3BANK8\0"
   /* 46506 */ "L3_OUTPUT_READY_L3BANK9\0"
   /* 46530 */ "L3_READ_L3BANK0\0"
   /* 46546 */ "L3_READ_L3BANK1\0"
   /* 46562 */ "L3_READ_L3BANK10\0"
   /* 46579 */ "L3_READ_L3BANK11\0"
   /* 46596 */ "L3_READ_L3BANK12\0"
   /* 46613 */ "L3_READ_L3BANK13\0"
   /* 46630 */ "L3_READ_L3BANK14\0"
   /* 46647 */ "L3_READ_L3BANK15\0"
   /* 46664 */ "L3_READ_L3BANK16\0"
   /* 46681 */ "L3_READ_L3BANK17\0"
   /* 46698 */ "L3_READ_L3BANK18\0"
   /* 46715 */ "L3_READ_L3BANK19\0"
   /* 46732 */ "L3_READ_L3BANK2\0"
   /* 46748 */ "L3_READ_L3BANK20\0"
   /* 46765 */ "L3_READ_L3BANK21\0"
   /* 46782 */ "L3_READ_L3BANK22\0"
   /* 46799 */ "L3_READ_L3BANK23\0"
   /* 46816 */ "L3_READ_L3BANK24\0"
   /* 46833 */ "L3_READ_L3BANK25\0"
   /* 46850 */ "L3_READ_L3BANK26\0"
   /* 46867 */ "L3_READ_L3BANK27\0"
   /* 46884 */ "L3_READ_L3BANK28\0"
   /* 46901 */ "L3_READ_L3BANK29\0"
   /* 46918 */ "L3_READ_L3BANK3\0"
   /* 46934 */ "L3_READ_L3BANK30\0"
   /* 46951 */ "L3_READ_L3BANK31\0"
   /* 46968 */ "L3_READ_L3BANK4\0"
   /* 46984 */ "L3_READ_L3BANK5\0"
   /* 47000 */ "L3_READ_L3BANK6\0"
   /* 47016 */ "L3_READ_L3BANK7\0"
   /* 47032 */ "L3_READ_L3BANK8\0"
   /* 47048 */ "L3_READ_L3BANK9\0"
   /* 47064 */ "L3_STALL_L3BANK0\0"
   /* 47081 */ "L3_STALL_L3BANK1\0"
   /* 47098 */ "L3_STALL_L3BANK10\0"
   /* 47116 */ "L3_STALL_L3BANK11\0"
   /* 47134 */ "L3_STALL_L3BANK12\0"
   /* 47152 */ "L3_STALL_L3BANK13\0"
   /* 47170 */ "L3_STALL_L3BANK14\0"
   /* 47188 */ "L3_STALL_L3BANK15\0"
   /* 47206 */ "L3_STALL_L3BANK16\0"
   /* 47224 */ "L3_STALL_L3BANK17\0"
   /* 47242 */ "L3_STALL_L3BANK18\0"
   /* 47260 */ "L3_STALL_L3BANK19\0"
   /* 47278 */ "L3_STALL_L3BANK2\0"
   /* 47295 */ "L3_STALL_L3BANK20\0"
   /* 47313 */ "L3_STALL_L3BANK21\0"
   /* 47331 */ "L3_STALL_L3BANK22\0"
   /* 47349 */ "L3_STALL_L3BANK23\0"
   /* 47367 */ "L3_STALL_L3BANK24\0"
   /* 47385 */ "L3_STALL_L3BANK25\0"
   /* 47403 */ "L3_STALL_L3BANK26\0"
   /* 47421 */ "L3_STALL_L3BANK27\0"
   /* 47439 */ "L3_STALL_L3BANK28\0"
   /* 47457 */ "L3_STALL_L3BANK29\0"
   /* 47475 */ "L3_STALL_L3BANK3\0"
   /* 47492 */ "L3_STALL_L3BANK30\0"
   /* 47510 */ "L3_STALL_L3BANK31\0"
   /* 47528 */ "L3_STALL_L3BANK4\0"
   /* 47545 */ "L3_STALL_L3BANK5\0"
   /* 47562 */ "L3_STALL_L3BANK6\0"
   /* 47579 */ "L3_STALL_L3BANK7\0"
   /* 47596 */ "L3_STALL_L3BANK8\0"
   /* 47613 */ "L3_STALL_L3BANK9\0"
   /* 47630 */ "L3_SUPERQ_FULL_L3BANK0\0"
   /* 47653 */ "L3_SUPERQ_FULL_L3BANK1\0"
   /* 47676 */ "L3_SUPERQ_FULL_L3BANK10\0"
   /* 47700 */ "L3_SUPERQ_FULL_L3BANK11\0"
   /* 47724 */ "L3_SUPERQ_FULL_L3BANK12\0"
   /* 47748 */ "L3_SUPERQ_FULL_L3BANK13\0"
   /* 47772 */ "L3_SUPERQ_FULL_L3BANK14\0"
   /* 47796 */ "L3_SUPERQ_FULL_L3BANK15\0"
   /* 47820 */ "L3_SUPERQ_FULL_L3BANK16\0"
   /* 47844 */ "L3_SUPERQ_FULL_L3BANK17\0"
   /* 47868 */ "L3_SUPERQ_FULL_L3BANK18\0"
   /* 47892 */ "L3_SUPERQ_FULL_L3BANK19\0"
   /* 47916 */ "L3_SUPERQ_FULL_L3BANK2\0"
   /* 47939 */ "L3_SUPERQ_FULL_L3BANK20\0"
   /* 47963 */ "L3_SUPERQ_FULL_L3BANK21\0"
   /* 47987 */ "L3_SUPERQ_FULL_L3BANK22\0"
   /* 48011 */ "L3_SUPERQ_FULL_L3BANK23\0"
   /* 48035 */ "L3_SUPERQ_FULL_L3BANK24\0"
   /* 48059 */ "L3_SUPERQ_FULL_L3BANK25\0"
   /* 48083 */ "L3_SUPERQ_FULL_L3BANK26\0"
   /* 48107 */ "L3_SUPERQ_FULL_L3BANK27\0"
   /* 48131 */ "L3_SUPERQ_FULL_L3BANK28\0"
   /* 48155 */ "L3_SUPERQ_FULL_L3BANK29\0"
   /* 48179 */ "L3_SUPERQ_FULL_L3BANK3\0"
   /* 48202 */ "L3_SUPERQ_FULL_L3BANK30\0"
   /* 48226 */ "L3_SUPERQ_FULL_L3BANK31\0"
   /* 48250 */ "L3_SUPERQ_FULL_L3BANK4\0"
   /* 48273 */ "L3_SUPERQ_FULL_L3BANK5\0"
   /* 48296 */ "L3_SUPERQ_FULL_L3BANK6\0"
   /* 48319 */ "L3_SUPERQ_FULL_L3BANK7\0"
   /* 48342 */ "L3_SUPERQ_FULL_L3BANK8\0"
   /* 48365 */ "L3_SUPERQ_FULL_L3BANK9\0"
   /* 48388 */ "L3_WRITE_L3BANK0\0"
   /* 48405 */ "L3_WRITE_L3BANK1\0"
   /* 48422 */ "L3_WRITE_L3BANK10\0"
   /* 48440 */ "L3_WRITE_L3BANK11\0"
   /* 48458 */ "L3_WRITE_L3BANK12\0"
   /* 48476 */ "L3_WRITE_L3BANK13\0"
   /* 48494 */ "L3_WRITE_L3BANK14\0"
   /* 48512 */ "L3_WRITE_L3BANK15\0"
   /* 48530 */ "L3_WRITE_L3BANK16\0"
   /* 48548 */ "L3_WRITE_L3BANK17\0"
   /* 48566 */ "L3_WRITE_L3BANK18\0"
   /* 48584 */ "L3_WRITE_L3BANK19\0"
   /* 48602 */ "L3_WRITE_L3BANK2\0"
   /* 48619 */ "L3_WRITE_L3BANK20\0"
   /* 48637 */ "L3_WRITE_L3BANK21\0"
   /* 48655 */ "L3_WRITE_L3BANK22\0"
   /* 48673 */ "L3_WRITE_L3BANK23\0"
   /* 48691 */ "L3_WRITE_L3BANK24\0"
   /* 48709 */ "L3_WRITE_L3BANK25\0"
   /* 48727 */ "L3_WRITE_L3BANK26\0"
   /* 48745 */ "L3_WRITE_L3BANK27\0"
   /* 48763 */ "L3_WRITE_L3BANK28\0"
   /* 48781 */ "L3_WRITE_L3BANK29\0"
   /* 48799 */ "L3_WRITE_L3BANK3\0"
   /* 48816 */ "L3_WRITE_L3BANK30\0"
   /* 48834 */ "L3_WRITE_L3BANK31\0"
   /* 48852 */ "L3_WRITE_L3BANK4\0"
   /* 48869 */ "L3_WRITE_L3BANK5\0"
   /* 48886 */ "L3_WRITE_L3BANK6\0"
   /* 48903 */ "L3_WRITE_L3BANK7\0"
   /* 48920 */ "L3_WRITE_L3BANK8\0"
   /* 48937 */ "L3_WRITE_L3BANK9\0"
   /* 48954 */ "LOAD_STORE_CACHE_ACCESS_XECORE0\0"
   /* 48986 */ "LOAD_STORE_CACHE_ACCESS_XECORE1\0"
   /* 49018 */ "LOAD_STORE_CACHE_ACCESS_XECORE10\0"
   /* 49051 */ "LOAD_STORE_CACHE_ACCESS_XECORE11\0"
   /* 49084 */ "LOAD_STORE_CACHE_ACCESS_XECORE12\0"
   /* 49117 */ "LOAD_STORE_CACHE_ACCESS_XECORE13\0"
   /* 49150 */ "LOAD_STORE_CACHE_ACCESS_XECORE14\0"
   /* 49183 */ "LOAD_STORE_CACHE_ACCESS_XECORE15\0"
   /* 49216 */ "LOAD_STORE_CACHE_ACCESS_XECORE16\0"
   /* 49249 */ "LOAD_STORE_CACHE_ACCESS_XECORE17\0"
   /* 49282 */ "LOAD_STORE_CACHE_ACCESS_XECORE18\0"
   /* 49315 */ "LOAD_STORE_CACHE_ACCESS_XECORE19\0"
   /* 49348 */ "LOAD_STORE_CACHE_ACCESS_XECORE2\0"
   /* 49380 */ "LOAD_STORE_CACHE_ACCESS_XECORE20\0"
   /* 49413 */ "LOAD_STORE_CACHE_ACCESS_XECORE21\0"
   /* 49446 */ "LOAD_STORE_CACHE_ACCESS_XECORE22\0"
   /* 49479 */ "LOAD_STORE_CACHE_ACCESS_XECORE23\0"
   /* 49512 */ "LOAD_STORE_CACHE_ACCESS_XECORE24\0"
   /* 49545 */ "LOAD_STORE_CACHE_ACCESS_XECORE25\0"
   /* 49578 */ "LOAD_STORE_CACHE_ACCESS_XECORE26\0"
   /* 49611 */ "LOAD_STORE_CACHE_ACCESS_XECORE27\0"
   /* 49644 */ "LOAD_STORE_CACHE_ACCESS_XECORE28\0"
   /* 49677 */ "LOAD_STORE_CACHE_ACCESS_XECORE29\0"
   /* 49710 */ "LOAD_STORE_CACHE_ACCESS_XECORE3\0"
   /* 49742 */ "LOAD_STORE_CACHE_ACCESS_XECORE30\0"
   /* 49775 */ "LOAD_STORE_CACHE_ACCESS_XECORE31\0"
   /* 49808 */ "LOAD_STORE_CACHE_ACCESS_XECORE4\0"
   /* 49840 */ "LOAD_STORE_CACHE_ACCESS_XECORE5\0"
   /* 49872 */ "LOAD_STORE_CACHE_ACCESS_XECORE6\0"
   /* 49904 */ "LOAD_STORE_CACHE_ACCESS_XECORE7\0"
   /* 49936 */ "LOAD_STORE_CACHE_ACCESS_XECORE8\0"
   /* 49968 */ "LOAD_STORE_CACHE_ACCESS_XECORE9\0"
   /* 50000 */ "LOAD_STORE_CACHE_BYTE_READ\0"
   /* 50027 */ "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0\0"
   /* 50068 */ "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1\0"
   /* 50109 */ "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2\0"
   /* 50150 */ "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3\0"
   /* 50191 */ "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE4\0"
   /* 50232 */ "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE5\0"
   /* 50273 */ "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE6\0"
   /* 50314 */ "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE7\0"
   /* 50355 */ "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0\0"
   /* 50396 */ "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1\0"
   /* 50437 */ "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2\0"
   /* 50478 */ "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3\0"
   /* 50519 */ "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE4\0"
   /* 50560 */ "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE5\0"
   /* 50601 */ "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE6\0"
   /* 50642 */ "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE7\0"
   /* 50683 */ "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0\0"
   /* 50724 */ "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1\0"
   /* 50765 */ "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2\0"
   /* 50806 */ "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3\0"
   /* 50847 */ "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE4\0"
   /* 50888 */ "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE5\0"
   /* 50929 */ "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE6\0"
   /* 50970 */ "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE7\0"
   /* 51011 */ "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0\0"
   /* 51052 */ "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1\0"
   /* 51093 */ "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2\0"
   /* 51134 */ "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3\0"
   /* 51175 */ "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE4\0"
   /* 51216 */ "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE5\0"
   /* 51257 */ "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE6\0"
   /* 51298 */ "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE7\0"
   /* 51339 */ "LOAD_STORE_CACHE_BYTE_WRITE\0"
   /* 51367 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0\0"
   /* 51409 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1\0"
   /* 51451 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2\0"
   /* 51493 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3\0"
   /* 51535 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE4\0"
   /* 51577 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE5\0"
   /* 51619 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE6\0"
   /* 51661 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE7\0"
   /* 51703 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0\0"
   /* 51745 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1\0"
   /* 51787 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2\0"
   /* 51829 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3\0"
   /* 51871 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE4\0"
   /* 51913 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE5\0"
   /* 51955 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE6\0"
   /* 51997 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE7\0"
   /* 52039 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0\0"
   /* 52081 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1\0"
   /* 52123 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2\0"
   /* 52165 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3\0"
   /* 52207 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE4\0"
   /* 52249 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE5\0"
   /* 52291 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE6\0"
   /* 52333 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE7\0"
   /* 52375 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0\0"
   /* 52417 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1\0"
   /* 52459 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2\0"
   /* 52501 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3\0"
   /* 52543 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE4\0"
   /* 52585 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE5\0"
   /* 52627 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE6\0"
   /* 52669 */ "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE7\0"
   /* 52711 */ "LOAD_STORE_CACHE_HIT_XECORE0\0"
   /* 52740 */ "LOAD_STORE_CACHE_HIT_XECORE1\0"
   /* 52769 */ "LOAD_STORE_CACHE_HIT_XECORE10\0"
   /* 52799 */ "LOAD_STORE_CACHE_HIT_XECORE11\0"
   /* 52829 */ "LOAD_STORE_CACHE_HIT_XECORE12\0"
   /* 52859 */ "LOAD_STORE_CACHE_HIT_XECORE13\0"
   /* 52889 */ "LOAD_STORE_CACHE_HIT_XECORE14\0"
   /* 52919 */ "LOAD_STORE_CACHE_HIT_XECORE15\0"
   /* 52949 */ "LOAD_STORE_CACHE_HIT_XECORE16\0"
   /* 52979 */ "LOAD_STORE_CACHE_HIT_XECORE17\0"
   /* 53009 */ "LOAD_STORE_CACHE_HIT_XECORE18\0"
   /* 53039 */ "LOAD_STORE_CACHE_HIT_XECORE19\0"
   /* 53069 */ "LOAD_STORE_CACHE_HIT_XECORE2\0"
   /* 53098 */ "LOAD_STORE_CACHE_HIT_XECORE20\0"
   /* 53128 */ "LOAD_STORE_CACHE_HIT_XECORE21\0"
   /* 53158 */ "LOAD_STORE_CACHE_HIT_XECORE22\0"
   /* 53188 */ "LOAD_STORE_CACHE_HIT_XECORE23\0"
   /* 53218 */ "LOAD_STORE_CACHE_HIT_XECORE24\0"
   /* 53248 */ "LOAD_STORE_CACHE_HIT_XECORE25\0"
   /* 53278 */ "LOAD_STORE_CACHE_HIT_XECORE26\0"
   /* 53308 */ "LOAD_STORE_CACHE_HIT_XECORE27\0"
   /* 53338 */ "LOAD_STORE_CACHE_HIT_XECORE28\0"
   /* 53368 */ "LOAD_STORE_CACHE_HIT_XECORE29\0"
   /* 53398 */ "LOAD_STORE_CACHE_HIT_XECORE3\0"
   /* 53427 */ "LOAD_STORE_CACHE_HIT_XECORE30\0"
   /* 53457 */ "LOAD_STORE_CACHE_HIT_XECORE31\0"
   /* 53487 */ "LOAD_STORE_CACHE_HIT_XECORE4\0"
   /* 53516 */ "LOAD_STORE_CACHE_HIT_XECORE5\0"
   /* 53545 */ "LOAD_STORE_CACHE_HIT_XECORE6\0"
   /* 53574 */ "LOAD_STORE_CACHE_HIT_XECORE7\0"
   /* 53603 */ "LOAD_STORE_CACHE_HIT_XECORE8\0"
   /* 53632 */ "LOAD_STORE_CACHE_HIT_XECORE9\0"
   /* 53661 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0\0"
   /* 53702 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1\0"
   /* 53743 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE10\0"
   /* 53785 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE11\0"
   /* 53827 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE12\0"
   /* 53869 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE13\0"
   /* 53911 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE14\0"
   /* 53953 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE15\0"
   /* 53995 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE16\0"
   /* 54037 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE17\0"
   /* 54079 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE18\0"
   /* 54121 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE19\0"
   /* 54163 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2\0"
   /* 54204 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE20\0"
   /* 54246 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE21\0"
   /* 54288 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE22\0"
   /* 54330 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE23\0"
   /* 54372 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE24\0"
   /* 54414 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE25\0"
   /* 54456 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE26\0"
   /* 54498 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE27\0"
   /* 54540 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE28\0"
   /* 54582 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE29\0"
   /* 54624 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3\0"
   /* 54665 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE30\0"
   /* 54707 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE31\0"
   /* 54749 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4\0"
   /* 54790 */ "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5\0"
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   /* 58636 */ "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5\0"
   /* 58689 */ "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6\0"
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   /* 58795 */ "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE8\0"
   /* 58848 */ "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE9\0"
   /* 58901 */ "LOAD_STORE_CACHE_OUTPUT_READY_XECORE0\0"
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   /* 59561 */ "LOAD_STORE_CACHE_OUTPUT_READY_XECORE24\0"
   /* 59600 */ "LOAD_STORE_CACHE_OUTPUT_READY_XECORE25\0"
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   /* 59756 */ "LOAD_STORE_CACHE_OUTPUT_READY_XECORE29\0"
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   /* 59949 */ "LOAD_STORE_CACHE_OUTPUT_READY_XECORE5\0"
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   /* 60025 */ "LOAD_STORE_CACHE_OUTPUT_READY_XECORE7\0"
   /* 60063 */ "LOAD_STORE_CACHE_OUTPUT_READY_XECORE8\0"
   /* 60101 */ "LOAD_STORE_CACHE_OUTPUT_READY_XECORE9\0"
   /* 60139 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0\0"
   /* 60184 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1\0"
   /* 60229 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE10\0"
   /* 60275 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE11\0"
   /* 60321 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE12\0"
   /* 60367 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE13\0"
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   /* 60459 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE15\0"
   /* 60505 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE16\0"
   /* 60551 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE17\0"
   /* 60597 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE18\0"
   /* 60643 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE19\0"
   /* 60689 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2\0"
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   /* 60780 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE21\0"
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   /* 60918 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE24\0"
   /* 60964 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE25\0"
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   /* 61466 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7\0"
   /* 61511 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE8\0"
   /* 61556 */ "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE9\0"
   /* 61601 */ "LlcAccesses\0"
   /* 61613 */ "LlcGpuThroughput\0"
   /* 61630 */ "LlcHits\0"
   /* 61638 */ "LlcReadAccesses\0"
   /* 61654 */ "LlcWrAccesses\0"
   /* 61668 */ "NonPSThread00ReadyForDispatch\0"
   /* 61698 */ "NonPSThread01ReadyForDispatch\0"
   /* 61728 */ "NonPSThread02ReadyForDispatch\0"
   /* 61758 */ "NonPSThread03ReadyForDispatch\0"
   /* 61788 */ "NonPSThread04ReadyForDispatch\0"
   /* 61818 */ "NonPSThread05ReadyForDispatch\0"
   /* 61848 */ "NonPSThread06ReadyForDispatch\0"
   /* 61878 */ "NonPSThread07ReadyForDispatch\0"
   /* 61908 */ "NonPSThread10ReadyForDispatch\0"
   /* 61938 */ "NonPSThread11ReadyForDispatch\0"
   /* 61968 */ "NonPSThread12ReadyForDispatch\0"
   /* 61998 */ "NonPSThread13ReadyForDispatch\0"
   /* 62028 */ "NonPSThread20ReadyForDispatch\0"
   /* 62058 */ "NonPSThread21ReadyForDispatch\0"
   /* 62088 */ "NonPSThread22ReadyForDispatch\0"
   /* 62118 */ "NonPSThread23ReadyForDispatch\0"
   /* 62148 */ "NonPSThread30ReadyForDispatch\0"
   /* 62178 */ "NonPSThread31ReadyForDispatch\0"
   /* 62208 */ "NonPSThread32ReadyForDispatch\0"
   /* 62238 */ "NonPSThread33ReadyForDispatch\0"
   /* 62268 */ "NonPSThread40ReadyForDispatch\0"
   /* 62298 */ "NonPSThread41ReadyForDispatch\0"
   /* 62328 */ "NonPSThread42ReadyForDispatch\0"
   /* 62358 */ "NonPSThread43ReadyForDispatch\0"
   /* 62388 */ "NonPSThread50ReadyForDispatch\0"
   /* 62418 */ "NonPSThread51ReadyForDispatch\0"
   /* 62448 */ "NonPSThread52ReadyForDispatch\0"
   /* 62478 */ "NonPSThread53ReadyForDispatch\0"
   /* 62508 */ "NonPSThread60ReadyForDispatch\0"
   /* 62538 */ "NonPSThread61ReadyForDispatch\0"
   /* 62568 */ "NonPSThread62ReadyForDispatch\0"
   /* 62598 */ "NonPSThread63ReadyForDispatch\0"
   /* 62628 */ "NonPSThread70ReadyForDispatch\0"
   /* 62658 */ "NonPSThread71ReadyForDispatch\0"
   /* 62688 */ "NonPSThread72ReadyForDispatch\0"
   /* 62718 */ "NonPSThread73ReadyForDispatch\0"
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   /* 62784 */ "NonSamplerShader01AccessStalledOnL3\0"
   /* 62820 */ "NonSamplerShader02AccessStalledOnL3\0"
   /* 62856 */ "NonSamplerShader03AccessStalledOnL3\0"
   /* 62892 */ "NonSamplerShader04AccessStalledOnL3\0"
   /* 62928 */ "NonSamplerShader05AccessStalledOnL3\0"
   /* 62964 */ "NonSamplerShader10AccessStalledOnL3\0"
   /* 63000 */ "NonSamplerShader11AccessStalledOnL3\0"
   /* 63036 */ "NonSamplerShader12AccessStalledOnL3\0"
   /* 63072 */ "NonSamplerShader13AccessStalledOnL3\0"
   /* 63108 */ "NonSamplerShader20AccessStalledOnL3\0"
   /* 63144 */ "NonSamplerShader21AccessStalledOnL3\0"
   /* 63180 */ "NonSamplerShader22AccessStalledOnL3\0"
   /* 63216 */ "NonSamplerShader23AccessStalledOnL3\0"
   /* 63252 */ "NonSamplerShader30AccessStalledOnL3\0"
   /* 63288 */ "NonSamplerShader31AccessStalledOnL3\0"
   /* 63324 */ "NonSamplerShader32AccessStalledOnL3\0"
   /* 63360 */ "NonSamplerShader33AccessStalledOnL3\0"
   /* 63396 */ "NonSamplerShader40AccessStalledOnL3\0"
   /* 63432 */ "NonSamplerShader41AccessStalledOnL3\0"
   /* 63468 */ "NonSamplerShader42AccessStalledOnL3\0"
   /* 63504 */ "NonSamplerShader43AccessStalledOnL3\0"
   /* 63540 */ "NonSamplerShader50AccessStalledOnL3\0"
   /* 63576 */ "NonSamplerShader51AccessStalledOnL3\0"
   /* 63612 */ "NonSamplerShader52AccessStalledOnL3\0"
   /* 63648 */ "NonSamplerShader53AccessStalledOnL3\0"
   /* 63684 */ "NonSamplerShader60AccessStalledOnL3\0"
   /* 63720 */ "NonSamplerShader61AccessStalledOnL3\0"
   /* 63756 */ "NonSamplerShader62AccessStalledOnL3\0"
   /* 63792 */ "NonSamplerShader63AccessStalledOnL3\0"
   /* 63828 */ "NonSamplerShader70AccessStalledOnL3\0"
   /* 63864 */ "NonSamplerShader71AccessStalledOnL3\0"
   /* 63900 */ "NonSamplerShader72AccessStalledOnL3\0"
   /* 63936 */ "NonSamplerShader73AccessStalledOnL3\0"
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   /* 64021 */ "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1\0"
   /* 64070 */ "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE2\0"
   /* 64119 */ "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE3\0"
   /* 64168 */ "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE4\0"
   /* 64217 */ "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE5\0"
   /* 64266 */ "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE6\0"
   /* 64315 */ "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE7\0"
   /* 64364 */ "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0\0"
   /* 64412 */ "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1\0"
   /* 64460 */ "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE2\0"
   /* 64508 */ "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE3\0"
   /* 64556 */ "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE4\0"
   /* 64604 */ "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE5\0"
   /* 64652 */ "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE6\0"
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   /* 64748 */ "PIXEL_BACKEND_INPUT_AVAILABLE_L3NODE0\0"
   /* 64786 */ "PIXEL_BACKEND_INPUT_AVAILABLE_L3NODE1\0"
   /* 64824 */ "PIXEL_BACKEND_OUTPUT_READY_L3NODE0\0"
   /* 64859 */ "PIXEL_BACKEND_OUTPUT_READY_L3NODE1\0"
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   /* 66480 */ "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE8\0"
   /* 66519 */ "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE9\0"
   /* 66558 */ "PIXEL_WRITE\0"
   /* 66570 */ "POSTPS_DEPTH_STENCIL_ALPHA_TEST_FAIL\0"
   /* 66607 */ "PSOutput00Available\0"
   /* 66627 */ "PSOutput01Available\0"
   /* 66647 */ "PSOutput02Available\0"
   /* 66667 */ "PSOutput0Available\0"
   /* 66686 */ "PSOutput10Available\0"
   /* 66706 */ "PSOutput11Available\0"
   /* 66726 */ "PSOutput1Available\0"
   /* 66745 */ "PSOutput20Available\0"
   /* 66765 */ "PSOutput21Available\0"
   /* 66785 */ "PSOutput30Available\0"
   /* 66805 */ "PSOutput31Available\0"
   /* 66825 */ "PSThread00ReadyForDispatch\0"
   /* 66852 */ "PSThread01ReadyForDispatch\0"
   /* 66879 */ "PSThread02ReadyForDispatch\0"
   /* 66906 */ "PSThread03ReadyForDispatch\0"
   /* 66933 */ "PSThread04ReadyForDispatch\0"
   /* 66960 */ "PSThread05ReadyForDispatch\0"
   /* 66987 */ "PSThread06ReadyForDispatch\0"
   /* 67014 */ "PSThread07ReadyForDispatch\0"
   /* 67041 */ "PSThread10ReadyForDispatch\0"
   /* 67068 */ "PSThread11ReadyForDispatch\0"
   /* 67095 */ "PSThread12ReadyForDispatch\0"
   /* 67122 */ "PSThread13ReadyForDispatch\0"
   /* 67149 */ "PSThread20ReadyForDispatch\0"
   /* 67176 */ "PSThread21ReadyForDispatch\0"
   /* 67203 */ "PSThread22ReadyForDispatch\0"
   /* 67230 */ "PSThread23ReadyForDispatch\0"
   /* 67257 */ "PSThread30ReadyForDispatch\0"
   /* 67284 */ "PSThread31ReadyForDispatch\0"
   /* 67311 */ "PSThread32ReadyForDispatch\0"
   /* 67338 */ "PSThread33ReadyForDispatch\0"
   /* 67365 */ "PSThread40ReadyForDispatch\0"
   /* 67392 */ "PSThread41ReadyForDispatch\0"
   /* 67419 */ "PSThread42ReadyForDispatch\0"
   /* 67446 */ "PSThread43ReadyForDispatch\0"
   /* 67473 */ "PSThread50ReadyForDispatch\0"
   /* 67500 */ "PSThread51ReadyForDispatch\0"
   /* 67527 */ "PSThread52ReadyForDispatch\0"
   /* 67554 */ "PSThread53ReadyForDispatch\0"
   /* 67581 */ "PSThread60ReadyForDispatch\0"
   /* 67608 */ "PSThread61ReadyForDispatch\0"
   /* 67635 */ "PSThread62ReadyForDispatch\0"
   /* 67662 */ "PSThread63ReadyForDispatch\0"
   /* 67689 */ "PSThread70ReadyForDispatch\0"
   /* 67716 */ "PSThread71ReadyForDispatch\0"
   /* 67743 */ "PSThread72ReadyForDispatch\0"
   /* 67770 */ "PSThread73ReadyForDispatch\0"
   /* 67797 */ "PS_OUTPUT_AVAILABLE_CPIPE0\0"
   /* 67824 */ "PS_OUTPUT_AVAILABLE_CPIPE1\0"
   /* 67851 */ "PS_OUTPUT_AVAILABLE_CPIPE10\0"
   /* 67879 */ "PS_OUTPUT_AVAILABLE_CPIPE11\0"
   /* 67907 */ "PS_OUTPUT_AVAILABLE_CPIPE12\0"
   /* 67935 */ "PS_OUTPUT_AVAILABLE_CPIPE13\0"
   /* 67963 */ "PS_OUTPUT_AVAILABLE_CPIPE14\0"
   /* 67991 */ "PS_OUTPUT_AVAILABLE_CPIPE15\0"
   /* 68019 */ "PS_OUTPUT_AVAILABLE_CPIPE2\0"
   /* 68046 */ "PS_OUTPUT_AVAILABLE_CPIPE3\0"
   /* 68073 */ "PS_OUTPUT_AVAILABLE_CPIPE4\0"
   /* 68100 */ "PS_OUTPUT_AVAILABLE_CPIPE5\0"
   /* 68127 */ "PS_OUTPUT_AVAILABLE_CPIPE6\0"
   /* 68154 */ "PS_OUTPUT_AVAILABLE_CPIPE7\0"
   /* 68181 */ "PS_OUTPUT_AVAILABLE_CPIPE8\0"
   /* 68208 */ "PS_OUTPUT_AVAILABLE_CPIPE9\0"
   /* 68235 */ "PixelData00Ready\0"
   /* 68252 */ "PixelData01Ready\0"
   /* 68269 */ "PixelData02Ready\0"
   /* 68286 */ "PixelData0Ready\0"
   /* 68302 */ "PixelData10Ready\0"
   /* 68319 */ "PixelData11Ready\0"
   /* 68336 */ "PixelData1Ready\0"
   /* 68352 */ "PixelData20Ready\0"
   /* 68369 */ "PixelData21Ready\0"
   /* 68386 */ "PixelData30Ready\0"
   /* 68403 */ "PixelData31Ready\0"
   /* 68420 */ "PixelData40Ready\0"
   /* 68437 */ "PixelData41Ready\0"
   /* 68454 */ "PixelData50Ready\0"
   /* 68471 */ "PixelData51Ready\0"
   /* 68488 */ "PixelData60Ready\0"
   /* 68505 */ "PixelData61Ready\0"
   /* 68522 */ "PixelData70Ready\0"
   /* 68539 */ "PixelData71Ready\0"
   /* 68556 */ "PixelValues00Ready\0"
   /* 68575 */ "PixelValues01Ready\0"
   /* 68594 */ "PixelValues02Ready\0"
   /* 68613 */ "PixelValues0Ready\0"
   /* 68631 */ "PixelValues10Ready\0"
   /* 68650 */ "PixelValues11Ready\0"
   /* 68669 */ "PixelValues1Ready\0"
   /* 68687 */ "PixelValues20Ready\0"
   /* 68706 */ "PixelValues21Ready\0"
   /* 68725 */ "PixelValues30Ready\0"
   /* 68744 */ "PixelValues31Ready\0"
   /* 68763 */ "PixelsFailingPostPsTests\0"
   /* 68788 */ "Poly0DataReady\0"
   /* 68803 */ "Poly1DataReady\0"
   /* 68818 */ "Poly2DataReady\0"
   /* 68833 */ "Poly3DataReady\0"
   /* 68848 */ "Poly4DataReady\0"
   /* 68863 */ "Poly5DataReady\0"
   /* 68878 */ "Poly6DataReady\0"
   /* 68893 */ "Poly7DataReady\0"
   /* 68908 */ "PolyDataReady\0"
   /* 68922 */ "PoshEngineBusy\0"
   /* 68937 */ "PostPsDepthTestFails\0"
   /* 68958 */ "PostPsStencilTestFails\0"
   /* 68981 */ "PsDuration\0"
   /* 68992 */ "PsEmActive\0"
   /* 69003 */ "PsEuActive\0"
   /* 69014 */ "PsEuActivePerThread\0"
   /* 69034 */ "PsEuBothFpuActive\0"
   /* 69052 */ "PsEuStall\0"
   /* 69062 */ "PsEuStallPerThread\0"
   /* 69081 */ "PsFpu0Active\0"
   /* 69094 */ "PsFpu1Active\0"
   /* 69107 */ "PsFpuActive\0"
   /* 69119 */ "PsSendActive\0"
   /* 69132 */ "PsThreads\0"
   /* 69142 */ "RASTERIZER_INPUT_AVAILABLE_SLICE0\0"
   /* 69176 */ "RASTERIZER_INPUT_AVAILABLE_SLICE1\0"
   /* 69210 */ "RASTERIZER_INPUT_AVAILABLE_SLICE2\0"
   /* 69244 */ "RASTERIZER_INPUT_AVAILABLE_SLICE3\0"
   /* 69278 */ "RASTERIZER_INPUT_AVAILABLE_SLICE4\0"
   /* 69312 */ "RASTERIZER_INPUT_AVAILABLE_SLICE5\0"
   /* 69346 */ "RASTERIZER_INPUT_AVAILABLE_SLICE6\0"
   /* 69380 */ "RASTERIZER_INPUT_AVAILABLE_SLICE7\0"
   /* 69414 */ "RASTERIZER_OUTPUT_READY_SLICE0\0"
   /* 69445 */ "RASTERIZER_OUTPUT_READY_SLICE1\0"
   /* 69476 */ "RASTERIZER_OUTPUT_READY_SLICE2\0"
   /* 69507 */ "RASTERIZER_OUTPUT_READY_SLICE3\0"
   /* 69538 */ "RASTERIZER_OUTPUT_READY_SLICE4\0"
   /* 69569 */ "RASTERIZER_OUTPUT_READY_SLICE5\0"
   /* 69600 */ "RASTERIZER_OUTPUT_READY_SLICE6\0"
   /* 69631 */ "RASTERIZER_OUTPUT_READY_SLICE7\0"
   /* 69662 */ "RASTERIZER_SAMPLE_OUTPUT\0"
   /* 69687 */ "RASTERIZER_TRANSACTION_OUTPUT_SLICE0\0"
   /* 69724 */ "RASTERIZER_TRANSACTION_OUTPUT_SLICE1\0"
   /* 69761 */ "RASTERIZER_TRANSACTION_OUTPUT_SLICE2\0"
   /* 69798 */ "RASTERIZER_TRANSACTION_OUTPUT_SLICE3\0"
   /* 69835 */ "RASTERIZER_TRANSACTION_OUTPUT_SLICE4\0"
   /* 69872 */ "RASTERIZER_TRANSACTION_OUTPUT_SLICE5\0"
   /* 69909 */ "RASTERIZER_TRANSACTION_OUTPUT_SLICE6\0"
   /* 69946 */ "RASTERIZER_TRANSACTION_OUTPUT_SLICE7\0"
   /* 69983 */ "RENDER_CACHE_ALLOC_L3NODE0\0"
   /* 70010 */ "RENDER_CACHE_ALLOC_L3NODE1\0"
   /* 70037 */ "RENDER_CACHE_ALLOC_L3NODE2\0"
   /* 70064 */ "RENDER_CACHE_ALLOC_L3NODE3\0"
   /* 70091 */ "RENDER_CACHE_ALLOC_L3NODE4\0"
   /* 70118 */ "RENDER_CACHE_ALLOC_L3NODE5\0"
   /* 70145 */ "RENDER_CACHE_ALLOC_L3NODE6\0"
   /* 70172 */ "RENDER_CACHE_ALLOC_L3NODE7\0"
   /* 70199 */ "RENDER_CACHE_HIT_L3NODE0\0"
   /* 70224 */ "RENDER_CACHE_HIT_L3NODE1\0"
   /* 70249 */ "RENDER_CACHE_HIT_L3NODE2\0"
   /* 70274 */ "RENDER_CACHE_HIT_L3NODE3\0"
   /* 70299 */ "RENDER_CACHE_HIT_L3NODE4\0"
   /* 70324 */ "RENDER_CACHE_HIT_L3NODE5\0"
   /* 70349 */ "RENDER_CACHE_HIT_L3NODE6\0"
   /* 70374 */ "RENDER_CACHE_HIT_L3NODE7\0"
   /* 70399 */ "RENDER_CACHE_INPUT_AVAILABLE_L3NODE0\0"
   /* 70436 */ "RENDER_CACHE_INPUT_AVAILABLE_L3NODE1\0"
   /* 70473 */ "RENDER_CACHE_INPUT_AVAILABLE_L3NODE2\0"
   /* 70510 */ "RENDER_CACHE_INPUT_AVAILABLE_L3NODE3\0"
   /* 70547 */ "RENDER_CACHE_INPUT_AVAILABLE_L3NODE4\0"
   /* 70584 */ "RENDER_CACHE_INPUT_AVAILABLE_L3NODE5\0"
   /* 70621 */ "RENDER_CACHE_INPUT_AVAILABLE_L3NODE6\0"
   /* 70658 */ "RENDER_CACHE_INPUT_AVAILABLE_L3NODE7\0"
   /* 70695 */ "RENDER_CACHE_OUTPUT_READY_L3NODE0\0"
   /* 70729 */ "RENDER_CACHE_OUTPUT_READY_L3NODE1\0"
   /* 70763 */ "RENDER_CACHE_OUTPUT_READY_L3NODE2\0"
   /* 70797 */ "RENDER_CACHE_OUTPUT_READY_L3NODE3\0"
   /* 70831 */ "RENDER_CACHE_OUTPUT_READY_L3NODE4\0"
   /* 70865 */ "RENDER_CACHE_OUTPUT_READY_L3NODE5\0"
   /* 70899 */ "RENDER_CACHE_OUTPUT_READY_L3NODE6\0"
   /* 70933 */ "RENDER_CACHE_OUTPUT_READY_L3NODE7\0"
   /* 70967 */ "RENDER_CACHE_READ_L3NODE0\0"
   /* 70993 */ "RENDER_CACHE_READ_L3NODE1\0"
   /* 71019 */ "RENDER_CACHE_READ_L3NODE2\0"
   /* 71045 */ "RENDER_CACHE_READ_L3NODE3\0"
   /* 71071 */ "RENDER_CACHE_READ_L3NODE4\0"
   /* 71097 */ "RENDER_CACHE_READ_L3NODE5\0"
   /* 71123 */ "RENDER_CACHE_READ_L3NODE6\0"
   /* 71149 */ "RENDER_CACHE_READ_L3NODE7\0"
   /* 71175 */ "RENDER_CACHE_WRITE_L3NODE0\0"
   /* 71202 */ "RENDER_CACHE_WRITE_L3NODE1\0"
   /* 71229 */ "RENDER_CACHE_WRITE_L3NODE2\0"
   /* 71256 */ "RENDER_CACHE_WRITE_L3NODE3\0"
   /* 71283 */ "RENDER_CACHE_WRITE_L3NODE4\0"
   /* 71310 */ "RENDER_CACHE_WRITE_L3NODE5\0"
   /* 71337 */ "RENDER_CACHE_WRITE_L3NODE6\0"
   /* 71364 */ "RENDER_CACHE_WRITE_L3NODE7\0"
   /* 71391 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0\0"
   /* 71430 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1\0"
   /* 71469 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE10\0"
   /* 71509 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE11\0"
   /* 71549 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE12\0"
   /* 71589 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE13\0"
   /* 71629 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE14\0"
   /* 71669 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE15\0"
   /* 71709 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE16\0"
   /* 71749 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE17\0"
   /* 71789 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE18\0"
   /* 71829 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE19\0"
   /* 71869 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2\0"
   /* 71908 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE20\0"
   /* 71948 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE21\0"
   /* 71988 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE22\0"
   /* 72028 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE23\0"
   /* 72068 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE24\0"
   /* 72108 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE25\0"
   /* 72148 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE26\0"
   /* 72188 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE27\0"
   /* 72228 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE28\0"
   /* 72268 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE29\0"
   /* 72308 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3\0"
   /* 72347 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE30\0"
   /* 72387 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE31\0"
   /* 72427 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4\0"
   /* 72466 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5\0"
   /* 72505 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6\0"
   /* 72544 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7\0"
   /* 72583 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE8\0"
   /* 72622 */ "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE9\0"
   /* 72661 */ "RT_BVH_CACHE_MISS_XECORE0\0"
   /* 72687 */ "RT_BVH_CACHE_MISS_XECORE1\0"
   /* 72713 */ "RT_BVH_CACHE_MISS_XECORE10\0"
   /* 72740 */ "RT_BVH_CACHE_MISS_XECORE11\0"
   /* 72767 */ "RT_BVH_CACHE_MISS_XECORE12\0"
   /* 72794 */ "RT_BVH_CACHE_MISS_XECORE13\0"
   /* 72821 */ "RT_BVH_CACHE_MISS_XECORE14\0"
   /* 72848 */ "RT_BVH_CACHE_MISS_XECORE15\0"
   /* 72875 */ "RT_BVH_CACHE_MISS_XECORE16\0"
   /* 72902 */ "RT_BVH_CACHE_MISS_XECORE17\0"
   /* 72929 */ "RT_BVH_CACHE_MISS_XECORE18\0"
   /* 72956 */ "RT_BVH_CACHE_MISS_XECORE19\0"
   /* 72983 */ "RT_BVH_CACHE_MISS_XECORE2\0"
   /* 73009 */ "RT_BVH_CACHE_MISS_XECORE20\0"
   /* 73036 */ "RT_BVH_CACHE_MISS_XECORE21\0"
   /* 73063 */ "RT_BVH_CACHE_MISS_XECORE22\0"
   /* 73090 */ "RT_BVH_CACHE_MISS_XECORE23\0"
   /* 73117 */ "RT_BVH_CACHE_MISS_XECORE24\0"
   /* 73144 */ "RT_BVH_CACHE_MISS_XECORE25\0"
   /* 73171 */ "RT_BVH_CACHE_MISS_XECORE26\0"
   /* 73198 */ "RT_BVH_CACHE_MISS_XECORE27\0"
   /* 73225 */ "RT_BVH_CACHE_MISS_XECORE28\0"
   /* 73252 */ "RT_BVH_CACHE_MISS_XECORE29\0"
   /* 73279 */ "RT_BVH_CACHE_MISS_XECORE3\0"
   /* 73305 */ "RT_BVH_CACHE_MISS_XECORE30\0"
   /* 73332 */ "RT_BVH_CACHE_MISS_XECORE31\0"
   /* 73359 */ "RT_BVH_CACHE_MISS_XECORE4\0"
   /* 73385 */ "RT_BVH_CACHE_MISS_XECORE5\0"
   /* 73411 */ "RT_BVH_CACHE_MISS_XECORE6\0"
   /* 73437 */ "RT_BVH_CACHE_MISS_XECORE7\0"
   /* 73463 */ "RT_BVH_CACHE_MISS_XECORE8\0"
   /* 73489 */ "RT_BVH_CACHE_MISS_XECORE9\0"
   /* 73515 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0\0"
   /* 73555 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1\0"
   /* 73595 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE10\0"
   /* 73636 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE11\0"
   /* 73677 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE12\0"
   /* 73718 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE13\0"
   /* 73759 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE14\0"
   /* 73800 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE15\0"
   /* 73841 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE16\0"
   /* 73882 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE17\0"
   /* 73923 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE18\0"
   /* 73964 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE19\0"
   /* 74005 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2\0"
   /* 74045 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE20\0"
   /* 74086 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE21\0"
   /* 74127 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE22\0"
   /* 74168 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE23\0"
   /* 74209 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE24\0"
   /* 74250 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE25\0"
   /* 74291 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE26\0"
   /* 74332 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE27\0"
   /* 74373 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE28\0"
   /* 74414 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE29\0"
   /* 74455 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3\0"
   /* 74495 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE30\0"
   /* 74536 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE31\0"
   /* 74577 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4\0"
   /* 74617 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5\0"
   /* 74657 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6\0"
   /* 74697 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7\0"
   /* 74737 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE8\0"
   /* 74777 */ "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE9\0"
   /* 74817 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0\0"
   /* 74860 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1\0"
   /* 74903 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE10\0"
   /* 74947 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE11\0"
   /* 74991 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE12\0"
   /* 75035 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE13\0"
   /* 75079 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE14\0"
   /* 75123 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE15\0"
   /* 75167 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE16\0"
   /* 75211 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE17\0"
   /* 75255 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE18\0"
   /* 75299 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE19\0"
   /* 75343 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2\0"
   /* 75386 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE20\0"
   /* 75430 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE21\0"
   /* 75474 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE22\0"
   /* 75518 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE23\0"
   /* 75562 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE24\0"
   /* 75606 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE25\0"
   /* 75650 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE26\0"
   /* 75694 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE27\0"
   /* 75738 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE28\0"
   /* 75782 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE29\0"
   /* 75826 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3\0"
   /* 75869 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE30\0"
   /* 75913 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE31\0"
   /* 75957 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4\0"
   /* 76000 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5\0"
   /* 76043 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6\0"
   /* 76086 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7\0"
   /* 76129 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE8\0"
   /* 76172 */ "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE9\0"
   /* 76215 */ "RT_INPUT_AVAILABLE_XECORE0\0"
   /* 76242 */ "RT_INPUT_AVAILABLE_XECORE1\0"
   /* 76269 */ "RT_INPUT_AVAILABLE_XECORE10\0"
   /* 76297 */ "RT_INPUT_AVAILABLE_XECORE11\0"
   /* 76325 */ "RT_INPUT_AVAILABLE_XECORE12\0"
   /* 76353 */ "RT_INPUT_AVAILABLE_XECORE13\0"
   /* 76381 */ "RT_INPUT_AVAILABLE_XECORE14\0"
   /* 76409 */ "RT_INPUT_AVAILABLE_XECORE15\0"
   /* 76437 */ "RT_INPUT_AVAILABLE_XECORE16\0"
   /* 76465 */ "RT_INPUT_AVAILABLE_XECORE17\0"
   /* 76493 */ "RT_INPUT_AVAILABLE_XECORE18\0"
   /* 76521 */ "RT_INPUT_AVAILABLE_XECORE19\0"
   /* 76549 */ "RT_INPUT_AVAILABLE_XECORE2\0"
   /* 76576 */ "RT_INPUT_AVAILABLE_XECORE20\0"
   /* 76604 */ "RT_INPUT_AVAILABLE_XECORE21\0"
   /* 76632 */ "RT_INPUT_AVAILABLE_XECORE22\0"
   /* 76660 */ "RT_INPUT_AVAILABLE_XECORE23\0"
   /* 76688 */ "RT_INPUT_AVAILABLE_XECORE24\0"
   /* 76716 */ "RT_INPUT_AVAILABLE_XECORE25\0"
   /* 76744 */ "RT_INPUT_AVAILABLE_XECORE26\0"
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   /* 98433 */ "SAMPLER_L3_HIT_L3BANK0\0"
   /* 98456 */ "SAMPLER_L3_HIT_L3BANK1\0"
   /* 98479 */ "SAMPLER_L3_HIT_L3BANK10\0"
   /* 98503 */ "SAMPLER_L3_HIT_L3BANK11\0"
   /* 98527 */ "SAMPLER_L3_HIT_L3BANK12\0"
   /* 98551 */ "SAMPLER_L3_HIT_L3BANK13\0"
   /* 98575 */ "SAMPLER_L3_HIT_L3BANK14\0"
   /* 98599 */ "SAMPLER_L3_HIT_L3BANK15\0"
   /* 98623 */ "SAMPLER_L3_HIT_L3BANK16\0"
   /* 98647 */ "SAMPLER_L3_HIT_L3BANK17\0"
   /* 98671 */ "SAMPLER_L3_HIT_L3BANK18\0"
   /* 98695 */ "SAMPLER_L3_HIT_L3BANK19\0"
   /* 98719 */ "SAMPLER_L3_HIT_L3BANK2\0"
   /* 98742 */ "SAMPLER_L3_HIT_L3BANK20\0"
   /* 98766 */ "SAMPLER_L3_HIT_L3BANK21\0"
   /* 98790 */ "SAMPLER_L3_HIT_L3BANK22\0"
   /* 98814 */ "SAMPLER_L3_HIT_L3BANK23\0"
   /* 98838 */ "SAMPLER_L3_HIT_L3BANK24\0"
   /* 98862 */ "SAMPLER_L3_HIT_L3BANK25\0"
   /* 98886 */ "SAMPLER_L3_HIT_L3BANK26\0"
   /* 98910 */ "SAMPLER_L3_HIT_L3BANK27\0"
   /* 98934 */ "SAMPLER_L3_HIT_L3BANK28\0"
   /* 98958 */ "SAMPLER_L3_HIT_L3BANK29\0"
   /* 98982 */ "SAMPLER_L3_HIT_L3BANK3\0"
   /* 99005 */ "SAMPLER_L3_HIT_L3BANK30\0"
   /* 99029 */ "SAMPLER_L3_HIT_L3BANK31\0"
   /* 99053 */ "SAMPLER_L3_HIT_L3BANK4\0"
   /* 99076 */ "SAMPLER_L3_HIT_L3BANK5\0"
   /* 99099 */ "SAMPLER_L3_HIT_L3BANK6\0"
   /* 99122 */ "SAMPLER_L3_HIT_L3BANK7\0"
   /* 99145 */ "SAMPLER_L3_HIT_L3BANK8\0"
   /* 99168 */ "SAMPLER_L3_HIT_L3BANK9\0"
   /* 99191 */ "SAMPLER_L3_READ\0"
   /* 99207 */ "SAMPLER_L3_READ_L3BANK0\0"
   /* 99231 */ "SAMPLER_L3_READ_L3BANK1\0"
   /* 99255 */ "SAMPLER_L3_READ_L3BANK10\0"
   /* 99280 */ "SAMPLER_L3_READ_L3BANK11\0"
   /* 99305 */ "SAMPLER_L3_READ_L3BANK12\0"
   /* 99330 */ "SAMPLER_L3_READ_L3BANK13\0"
   /* 99355 */ "SAMPLER_L3_READ_L3BANK14\0"
   /* 99380 */ "SAMPLER_L3_READ_L3BANK15\0"
   /* 99405 */ "SAMPLER_L3_READ_L3BANK16\0"
   /* 99430 */ "SAMPLER_L3_READ_L3BANK17\0"
   /* 99455 */ "SAMPLER_L3_READ_L3BANK18\0"
   /* 99480 */ "SAMPLER_L3_READ_L3BANK19\0"
   /* 99505 */ "SAMPLER_L3_READ_L3BANK2\0"
   /* 99529 */ "SAMPLER_L3_READ_L3BANK20\0"
   /* 99554 */ "SAMPLER_L3_READ_L3BANK21\0"
   /* 99579 */ "SAMPLER_L3_READ_L3BANK22\0"
   /* 99604 */ "SAMPLER_L3_READ_L3BANK23\0"
   /* 99629 */ "SAMPLER_L3_READ_L3BANK24\0"
   /* 99654 */ "SAMPLER_L3_READ_L3BANK25\0"
   /* 99679 */ "SAMPLER_L3_READ_L3BANK26\0"
   /* 99704 */ "SAMPLER_L3_READ_L3BANK27\0"
   /* 99729 */ "SAMPLER_L3_READ_L3BANK28\0"
   /* 99754 */ "SAMPLER_L3_READ_L3BANK29\0"
   /* 99779 */ "SAMPLER_L3_READ_L3BANK3\0"
   /* 99803 */ "SAMPLER_L3_READ_L3BANK30\0"
   /* 99828 */ "SAMPLER_L3_READ_L3BANK31\0"
   /* 99853 */ "SAMPLER_L3_READ_L3BANK4\0"
   /* 99877 */ "SAMPLER_L3_READ_L3BANK5\0"
   /* 99901 */ "SAMPLER_L3_READ_L3BANK6\0"
   /* 99925 */ "SAMPLER_L3_READ_L3BANK7\0"
   /* 99949 */ "SAMPLER_L3_READ_L3BANK8\0"
   /* 99973 */ "SAMPLER_L3_READ_L3BANK9\0"
   /* 99997 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE0\0"
   /* 100034 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE1\0"
   /* 100071 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE10\0"
   /* 100109 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE11\0"
   /* 100147 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE12\0"
   /* 100185 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE13\0"
   /* 100223 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE14\0"
   /* 100261 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE15\0"
   /* 100299 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE16\0"
   /* 100337 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE17\0"
   /* 100375 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE18\0"
   /* 100413 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE19\0"
   /* 100451 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE2\0"
   /* 100488 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE20\0"
   /* 100526 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE21\0"
   /* 100564 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE22\0"
   /* 100602 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE23\0"
   /* 100640 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE24\0"
   /* 100678 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE25\0"
   /* 100716 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE26\0"
   /* 100754 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE27\0"
   /* 100792 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE28\0"
   /* 100830 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE29\0"
   /* 100868 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE3\0"
   /* 100905 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE30\0"
   /* 100943 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE31\0"
   /* 100981 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE4\0"
   /* 101018 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE5\0"
   /* 101055 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE6\0"
   /* 101092 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE7\0"
   /* 101129 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE8\0"
   /* 101166 */ "SAMPLER_MEMORY_LATENCY_STALL_XECORE9\0"
   /* 101203 */ "SAMPLER_OUTPUT_READY_XECORE0\0"
   /* 101232 */ "SAMPLER_OUTPUT_READY_XECORE1\0"
   /* 101261 */ "SAMPLER_OUTPUT_READY_XECORE10\0"
   /* 101291 */ "SAMPLER_OUTPUT_READY_XECORE11\0"
   /* 101321 */ "SAMPLER_OUTPUT_READY_XECORE12\0"
   /* 101351 */ "SAMPLER_OUTPUT_READY_XECORE13\0"
   /* 101381 */ "SAMPLER_OUTPUT_READY_XECORE14\0"
   /* 101411 */ "SAMPLER_OUTPUT_READY_XECORE15\0"
   /* 101441 */ "SAMPLER_OUTPUT_READY_XECORE16\0"
   /* 101471 */ "SAMPLER_OUTPUT_READY_XECORE17\0"
   /* 101501 */ "SAMPLER_OUTPUT_READY_XECORE18\0"
   /* 101531 */ "SAMPLER_OUTPUT_READY_XECORE19\0"
   /* 101561 */ "SAMPLER_OUTPUT_READY_XECORE2\0"
   /* 101590 */ "SAMPLER_OUTPUT_READY_XECORE20\0"
   /* 101620 */ "SAMPLER_OUTPUT_READY_XECORE21\0"
   /* 101650 */ "SAMPLER_OUTPUT_READY_XECORE22\0"
   /* 101680 */ "SAMPLER_OUTPUT_READY_XECORE23\0"
   /* 101710 */ "SAMPLER_OUTPUT_READY_XECORE24\0"
   /* 101740 */ "SAMPLER_OUTPUT_READY_XECORE25\0"
   /* 101770 */ "SAMPLER_OUTPUT_READY_XECORE26\0"
   /* 101800 */ "SAMPLER_OUTPUT_READY_XECORE27\0"
   /* 101830 */ "SAMPLER_OUTPUT_READY_XECORE28\0"
   /* 101860 */ "SAMPLER_OUTPUT_READY_XECORE29\0"
   /* 101890 */ "SAMPLER_OUTPUT_READY_XECORE3\0"
   /* 101919 */ "SAMPLER_OUTPUT_READY_XECORE30\0"
   /* 101949 */ "SAMPLER_OUTPUT_READY_XECORE31\0"
   /* 101979 */ "SAMPLER_OUTPUT_READY_XECORE4\0"
   /* 102008 */ "SAMPLER_OUTPUT_READY_XECORE5\0"
   /* 102037 */ "SAMPLER_OUTPUT_READY_XECORE6\0"
   /* 102066 */ "SAMPLER_OUTPUT_READY_XECORE7\0"
   /* 102095 */ "SAMPLER_OUTPUT_READY_XECORE8\0"
   /* 102124 */ "SAMPLER_OUTPUT_READY_XECORE9\0"
   /* 102153 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0\0"
   /* 102190 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1\0"
   /* 102227 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE10\0"
   /* 102265 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE11\0"
   /* 102303 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE12\0"
   /* 102341 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE13\0"
   /* 102379 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE14\0"
   /* 102417 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE15\0"
   /* 102455 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE16\0"
   /* 102493 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE17\0"
   /* 102531 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE18\0"
   /* 102569 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE19\0"
   /* 102607 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2\0"
   /* 102644 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE20\0"
   /* 102682 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE21\0"
   /* 102720 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE22\0"
   /* 102758 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE23\0"
   /* 102796 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE24\0"
   /* 102834 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE25\0"
   /* 102872 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE26\0"
   /* 102910 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE27\0"
   /* 102948 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE28\0"
   /* 102986 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE29\0"
   /* 103024 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3\0"
   /* 103061 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE30\0"
   /* 103099 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE31\0"
   /* 103137 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4\0"
   /* 103174 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5\0"
   /* 103211 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6\0"
   /* 103248 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7\0"
   /* 103285 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE8\0"
   /* 103322 */ "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE9\0"
   /* 103359 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE0\0"
   /* 103394 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE1\0"
   /* 103429 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE10\0"
   /* 103465 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE11\0"
   /* 103501 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE12\0"
   /* 103537 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE13\0"
   /* 103573 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE14\0"
   /* 103609 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE15\0"
   /* 103645 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE16\0"
   /* 103681 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE17\0"
   /* 103717 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE18\0"
   /* 103753 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE19\0"
   /* 103789 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE2\0"
   /* 103824 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE20\0"
   /* 103860 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE21\0"
   /* 103896 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE22\0"
   /* 103932 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE23\0"
   /* 103968 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE24\0"
   /* 104004 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE25\0"
   /* 104040 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE26\0"
   /* 104076 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE27\0"
   /* 104112 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE28\0"
   /* 104148 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE29\0"
   /* 104184 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE3\0"
   /* 104219 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE30\0"
   /* 104255 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE31\0"
   /* 104291 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE4\0"
   /* 104326 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE5\0"
   /* 104361 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE6\0"
   /* 104396 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE7\0"
   /* 104431 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE8\0"
   /* 104466 */ "SAMPLER_TEXTURE_CACHE_MISS_XECORE9\0"
   /* 104501 */ "SLM_ACCESS_COUNT_BANK0_XECORE0\0"
   /* 104532 */ "SLM_ACCESS_COUNT_BANK0_XECORE1\0"
   /* 104563 */ "SLM_ACCESS_COUNT_BANK0_XECORE2\0"
   /* 104594 */ "SLM_ACCESS_COUNT_BANK0_XECORE3\0"
   /* 104625 */ "SLM_ACCESS_COUNT_BANK0_XECORE4\0"
   /* 104656 */ "SLM_ACCESS_COUNT_BANK0_XECORE5\0"
   /* 104687 */ "SLM_ACCESS_COUNT_BANK0_XECORE6\0"
   /* 104718 */ "SLM_ACCESS_COUNT_BANK0_XECORE7\0"
   /* 104749 */ "SLM_ACCESS_COUNT_BANK1_XECORE0\0"
   /* 104780 */ "SLM_ACCESS_COUNT_BANK1_XECORE1\0"
   /* 104811 */ "SLM_ACCESS_COUNT_BANK1_XECORE2\0"
   /* 104842 */ "SLM_ACCESS_COUNT_BANK1_XECORE3\0"
   /* 104873 */ "SLM_ACCESS_COUNT_BANK1_XECORE4\0"
   /* 104904 */ "SLM_ACCESS_COUNT_BANK1_XECORE5\0"
   /* 104935 */ "SLM_ACCESS_COUNT_BANK1_XECORE6\0"
   /* 104966 */ "SLM_ACCESS_COUNT_BANK1_XECORE7\0"
   /* 104997 */ "SLM_ACCESS_COUNT_XECORE0\0"
   /* 105022 */ "SLM_ACCESS_COUNT_XECORE1\0"
   /* 105047 */ "SLM_ACCESS_COUNT_XECORE10\0"
   /* 105073 */ "SLM_ACCESS_COUNT_XECORE11\0"
   /* 105099 */ "SLM_ACCESS_COUNT_XECORE12\0"
   /* 105125 */ "SLM_ACCESS_COUNT_XECORE13\0"
   /* 105151 */ "SLM_ACCESS_COUNT_XECORE14\0"
   /* 105177 */ "SLM_ACCESS_COUNT_XECORE15\0"
   /* 105203 */ "SLM_ACCESS_COUNT_XECORE16\0"
   /* 105229 */ "SLM_ACCESS_COUNT_XECORE17\0"
   /* 105255 */ "SLM_ACCESS_COUNT_XECORE18\0"
   /* 105281 */ "SLM_ACCESS_COUNT_XECORE19\0"
   /* 105307 */ "SLM_ACCESS_COUNT_XECORE2\0"
   /* 105332 */ "SLM_ACCESS_COUNT_XECORE20\0"
   /* 105358 */ "SLM_ACCESS_COUNT_XECORE21\0"
   /* 105384 */ "SLM_ACCESS_COUNT_XECORE22\0"
   /* 105410 */ "SLM_ACCESS_COUNT_XECORE23\0"
   /* 105436 */ "SLM_ACCESS_COUNT_XECORE24\0"
   /* 105462 */ "SLM_ACCESS_COUNT_XECORE25\0"
   /* 105488 */ "SLM_ACCESS_COUNT_XECORE26\0"
   /* 105514 */ "SLM_ACCESS_COUNT_XECORE27\0"
   /* 105540 */ "SLM_ACCESS_COUNT_XECORE28\0"
   /* 105566 */ "SLM_ACCESS_COUNT_XECORE29\0"
   /* 105592 */ "SLM_ACCESS_COUNT_XECORE3\0"
   /* 105617 */ "SLM_ACCESS_COUNT_XECORE30\0"
   /* 105643 */ "SLM_ACCESS_COUNT_XECORE31\0"
   /* 105669 */ "SLM_ACCESS_COUNT_XECORE4\0"
   /* 105694 */ "SLM_ACCESS_COUNT_XECORE5\0"
   /* 105719 */ "SLM_ACCESS_COUNT_XECORE6\0"
   /* 105744 */ "SLM_ACCESS_COUNT_XECORE7\0"
   /* 105769 */ "SLM_ACCESS_COUNT_XECORE8\0"
   /* 105794 */ "SLM_ACCESS_COUNT_XECORE9\0"
   /* 105819 */ "SLM_BANK_CONFLICT_COUNT\0"
   /* 105843 */ "SLM_BANK_CONFLICT_COUNT_XECORE0\0"
   /* 105875 */ "SLM_BANK_CONFLICT_COUNT_XECORE1\0"
   /* 105907 */ "SLM_BANK_CONFLICT_COUNT_XECORE10\0"
   /* 105940 */ "SLM_BANK_CONFLICT_COUNT_XECORE11\0"
   /* 105973 */ "SLM_BANK_CONFLICT_COUNT_XECORE12\0"
   /* 106006 */ "SLM_BANK_CONFLICT_COUNT_XECORE13\0"
   /* 106039 */ "SLM_BANK_CONFLICT_COUNT_XECORE14\0"
   /* 106072 */ "SLM_BANK_CONFLICT_COUNT_XECORE15\0"
   /* 106105 */ "SLM_BANK_CONFLICT_COUNT_XECORE16\0"
   /* 106138 */ "SLM_BANK_CONFLICT_COUNT_XECORE17\0"
   /* 106171 */ "SLM_BANK_CONFLICT_COUNT_XECORE18\0"
   /* 106204 */ "SLM_BANK_CONFLICT_COUNT_XECORE19\0"
   /* 106237 */ "SLM_BANK_CONFLICT_COUNT_XECORE2\0"
   /* 106269 */ "SLM_BANK_CONFLICT_COUNT_XECORE20\0"
   /* 106302 */ "SLM_BANK_CONFLICT_COUNT_XECORE21\0"
   /* 106335 */ "SLM_BANK_CONFLICT_COUNT_XECORE22\0"
   /* 106368 */ "SLM_BANK_CONFLICT_COUNT_XECORE23\0"
   /* 106401 */ "SLM_BANK_CONFLICT_COUNT_XECORE24\0"
   /* 106434 */ "SLM_BANK_CONFLICT_COUNT_XECORE25\0"
   /* 106467 */ "SLM_BANK_CONFLICT_COUNT_XECORE26\0"
   /* 106500 */ "SLM_BANK_CONFLICT_COUNT_XECORE27\0"
   /* 106533 */ "SLM_BANK_CONFLICT_COUNT_XECORE28\0"
   /* 106566 */ "SLM_BANK_CONFLICT_COUNT_XECORE29\0"
   /* 106599 */ "SLM_BANK_CONFLICT_COUNT_XECORE3\0"
   /* 106631 */ "SLM_BANK_CONFLICT_COUNT_XECORE30\0"
   /* 106664 */ "SLM_BANK_CONFLICT_COUNT_XECORE31\0"
   /* 106697 */ "SLM_BANK_CONFLICT_COUNT_XECORE4\0"
   /* 106729 */ "SLM_BANK_CONFLICT_COUNT_XECORE5\0"
   /* 106761 */ "SLM_BANK_CONFLICT_COUNT_XECORE6\0"
   /* 106793 */ "SLM_BANK_CONFLICT_COUNT_XECORE7\0"
   /* 106825 */ "SLM_BANK_CONFLICT_COUNT_XECORE8\0"
   /* 106857 */ "SLM_BANK_CONFLICT_COUNT_XECORE9\0"
   /* 106889 */ "SLM_BYTE_READ\0"
   /* 106903 */ "SLM_BYTE_READ_BANK0_XECORE0\0"
   /* 106931 */ "SLM_BYTE_READ_BANK0_XECORE1\0"
   /* 106959 */ "SLM_BYTE_READ_BANK0_XECORE2\0"
   /* 106987 */ "SLM_BYTE_READ_BANK0_XECORE3\0"
   /* 107015 */ "SLM_BYTE_READ_BANK0_XECORE4\0"
   /* 107043 */ "SLM_BYTE_READ_BANK0_XECORE5\0"
   /* 107071 */ "SLM_BYTE_READ_BANK0_XECORE6\0"
   /* 107099 */ "SLM_BYTE_READ_BANK0_XECORE7\0"
   /* 107127 */ "SLM_BYTE_READ_BANK1_XECORE0\0"
   /* 107155 */ "SLM_BYTE_READ_BANK1_XECORE1\0"
   /* 107183 */ "SLM_BYTE_READ_BANK1_XECORE2\0"
   /* 107211 */ "SLM_BYTE_READ_BANK1_XECORE3\0"
   /* 107239 */ "SLM_BYTE_READ_BANK1_XECORE4\0"
   /* 107267 */ "SLM_BYTE_READ_BANK1_XECORE5\0"
   /* 107295 */ "SLM_BYTE_READ_BANK1_XECORE6\0"
   /* 107323 */ "SLM_BYTE_READ_BANK1_XECORE7\0"
   /* 107351 */ "SLM_BYTE_READ_BANK2_XECORE0\0"
   /* 107379 */ "SLM_BYTE_READ_BANK2_XECORE1\0"
   /* 107407 */ "SLM_BYTE_READ_BANK2_XECORE2\0"
   /* 107435 */ "SLM_BYTE_READ_BANK2_XECORE3\0"
   /* 107463 */ "SLM_BYTE_READ_BANK2_XECORE4\0"
   /* 107491 */ "SLM_BYTE_READ_BANK2_XECORE5\0"
   /* 107519 */ "SLM_BYTE_READ_BANK2_XECORE6\0"
   /* 107547 */ "SLM_BYTE_READ_BANK2_XECORE7\0"
   /* 107575 */ "SLM_BYTE_READ_BANK3_XECORE0\0"
   /* 107603 */ "SLM_BYTE_READ_BANK3_XECORE1\0"
   /* 107631 */ "SLM_BYTE_READ_BANK3_XECORE2\0"
   /* 107659 */ "SLM_BYTE_READ_BANK3_XECORE3\0"
   /* 107687 */ "SLM_BYTE_READ_BANK3_XECORE4\0"
   /* 107715 */ "SLM_BYTE_READ_BANK3_XECORE5\0"
   /* 107743 */ "SLM_BYTE_READ_BANK3_XECORE6\0"
   /* 107771 */ "SLM_BYTE_READ_BANK3_XECORE7\0"
   /* 107799 */ "SLM_BYTE_WRITE\0"
   /* 107814 */ "SLM_BYTE_WRITE_BANK0_XECORE0\0"
   /* 107843 */ "SLM_BYTE_WRITE_BANK0_XECORE1\0"
   /* 107872 */ "SLM_BYTE_WRITE_BANK0_XECORE2\0"
   /* 107901 */ "SLM_BYTE_WRITE_BANK0_XECORE3\0"
   /* 107930 */ "SLM_BYTE_WRITE_BANK0_XECORE4\0"
   /* 107959 */ "SLM_BYTE_WRITE_BANK0_XECORE5\0"
   /* 107988 */ "SLM_BYTE_WRITE_BANK0_XECORE6\0"
   /* 108017 */ "SLM_BYTE_WRITE_BANK0_XECORE7\0"
   /* 108046 */ "SLM_BYTE_WRITE_BANK1_XECORE0\0"
   /* 108075 */ "SLM_BYTE_WRITE_BANK1_XECORE1\0"
   /* 108104 */ "SLM_BYTE_WRITE_BANK1_XECORE2\0"
   /* 108133 */ "SLM_BYTE_WRITE_BANK1_XECORE3\0"
   /* 108162 */ "SLM_BYTE_WRITE_BANK1_XECORE4\0"
   /* 108191 */ "SLM_BYTE_WRITE_BANK1_XECORE5\0"
   /* 108220 */ "SLM_BYTE_WRITE_BANK1_XECORE6\0"
   /* 108249 */ "SLM_BYTE_WRITE_BANK1_XECORE7\0"
   /* 108278 */ "SLM_BYTE_WRITE_BANK2_XECORE0\0"
   /* 108307 */ "SLM_BYTE_WRITE_BANK2_XECORE1\0"
   /* 108336 */ "SLM_BYTE_WRITE_BANK2_XECORE2\0"
   /* 108365 */ "SLM_BYTE_WRITE_BANK2_XECORE3\0"
   /* 108394 */ "SLM_BYTE_WRITE_BANK2_XECORE4\0"
   /* 108423 */ "SLM_BYTE_WRITE_BANK2_XECORE5\0"
   /* 108452 */ "SLM_BYTE_WRITE_BANK2_XECORE6\0"
   /* 108481 */ "SLM_BYTE_WRITE_BANK2_XECORE7\0"
   /* 108510 */ "SLM_BYTE_WRITE_BANK3_XECORE0\0"
   /* 108539 */ "SLM_BYTE_WRITE_BANK3_XECORE1\0"
   /* 108568 */ "SLM_BYTE_WRITE_BANK3_XECORE2\0"
   /* 108597 */ "SLM_BYTE_WRITE_BANK3_XECORE3\0"
   /* 108626 */ "SLM_BYTE_WRITE_BANK3_XECORE4\0"
   /* 108655 */ "SLM_BYTE_WRITE_BANK3_XECORE5\0"
   /* 108684 */ "SLM_BYTE_WRITE_BANK3_XECORE6\0"
   /* 108713 */ "SLM_BYTE_WRITE_BANK3_XECORE7\0"
   /* 108742 */ "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0\0"
   /* 108779 */ "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1\0"
   /* 108816 */ "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE2\0"
   /* 108853 */ "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE3\0"
   /* 108890 */ "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE4\0"
   /* 108927 */ "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE5\0"
   /* 108964 */ "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE6\0"
   /* 109001 */ "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE7\0"
   /* 109038 */ "STRIPSFAN_OBJECTS_CULL_SLICE0\0"
   /* 109068 */ "STRIPSFAN_OBJECTS_CULL_SLICE1\0"
   /* 109098 */ "STRIPSFAN_OBJECTS_CULL_SLICE2\0"
   /* 109128 */ "STRIPSFAN_OBJECTS_CULL_SLICE3\0"
   /* 109158 */ "STRIPSFAN_OBJECTS_CULL_SLICE4\0"
   /* 109188 */ "STRIPSFAN_OBJECTS_CULL_SLICE5\0"
   /* 109218 */ "STRIPSFAN_OBJECTS_CULL_SLICE6\0"
   /* 109248 */ "STRIPSFAN_OBJECTS_CULL_SLICE7\0"
   /* 109278 */ "STRIPSFAN_OBJECT_COUNT_SLICE0\0"
   /* 109308 */ "STRIPSFAN_OBJECT_COUNT_SLICE1\0"
   /* 109338 */ "STRIPSFAN_OBJECT_COUNT_SLICE2\0"
   /* 109368 */ "STRIPSFAN_OBJECT_COUNT_SLICE3\0"
   /* 109398 */ "STRIPSFAN_OBJECT_COUNT_SLICE4\0"
   /* 109428 */ "STRIPSFAN_OBJECT_COUNT_SLICE5\0"
   /* 109458 */ "STRIPSFAN_OBJECT_COUNT_SLICE6\0"
   /* 109488 */ "STRIPSFAN_OBJECT_COUNT_SLICE7\0"
   /* 109518 */ "STRIPSFAN_OUTPUT_READY_SLICE0\0"
   /* 109548 */ "STRIPSFAN_OUTPUT_READY_SLICE1\0"
   /* 109578 */ "STRIPSFAN_OUTPUT_READY_SLICE2\0"
   /* 109608 */ "STRIPSFAN_OUTPUT_READY_SLICE3\0"
   /* 109638 */ "STRIPSFAN_OUTPUT_READY_SLICE4\0"
   /* 109668 */ "STRIPSFAN_OUTPUT_READY_SLICE5\0"
   /* 109698 */ "STRIPSFAN_OUTPUT_READY_SLICE6\0"
   /* 109728 */ "STRIPSFAN_OUTPUT_READY_SLICE7\0"
   /* 109758 */ "SYSMEM_BYTE_READ\0"
   /* 109775 */ "SYSMEM_BYTE_WRITE\0"
   /* 109793 */ "SYSMEM_TRANSACTION_READ\0"
   /* 109817 */ "SYSMEM_TRANSACTION_WRITE\0"
   /* 109842 */ "Sampler00Bottleneck\0"
   /* 109862 */ "Sampler00Busy\0"
   /* 109876 */ "Sampler00InputAvailable\0"
   /* 109900 */ "Sampler00OutputReady\0"
   /* 109921 */ "Sampler01InputAvailable\0"
   /* 109945 */ "Sampler01OutputReady\0"
   /* 109966 */ "Sampler02InputAvailable\0"
   /* 109990 */ "Sampler02OutputReady\0"
   /* 110011 */ "Sampler03InputAvailable\0"
   /* 110035 */ "Sampler03OutputReady\0"
   /* 110056 */ "Sampler04InputAvailable\0"
   /* 110080 */ "Sampler04OutputReady\0"
   /* 110101 */ "Sampler05InputAvailable\0"
   /* 110125 */ "Sampler05OutputReady\0"
   /* 110146 */ "Sampler06InputAvailable\0"
   /* 110170 */ "Sampler06OutputReady\0"
   /* 110191 */ "Sampler07InputAvailable\0"
   /* 110215 */ "Sampler07OutputReady\0"
   /* 110236 */ "Sampler0Bottleneck\0"
   /* 110255 */ "Sampler0Busy\0"
   /* 110268 */ "Sampler0L2CacheMisses\0"
   /* 110290 */ "Sampler0Texels\0"
   /* 110305 */ "Sampler10InputAvailable\0"
   /* 110329 */ "Sampler10OutputReady\0"
   /* 110350 */ "Sampler11InputAvailable\0"
   /* 110374 */ "Sampler11OutputReady\0"
   /* 110395 */ "Sampler12InputAvailable\0"
   /* 110419 */ "Sampler12OutputReady\0"
   /* 110440 */ "Sampler13InputAvailable\0"
   /* 110464 */ "Sampler13OutputReady\0"
   /* 110485 */ "Sampler1Bottleneck\0"
   /* 110504 */ "Sampler1Busy\0"
   /* 110517 */ "Sampler1L2CacheMisses\0"
   /* 110539 */ "Sampler1Texels\0"
   /* 110554 */ "Sampler20Bottleneck\0"
   /* 110574 */ "Sampler20Busy\0"
   /* 110588 */ "Sampler20InputAvailable\0"
   /* 110612 */ "Sampler20OutputReady\0"
   /* 110633 */ "Sampler21InputAvailable\0"
   /* 110657 */ "Sampler21OutputReady\0"
   /* 110678 */ "Sampler22InputAvailable\0"
   /* 110702 */ "Sampler22OutputReady\0"
   /* 110723 */ "Sampler23InputAvailable\0"
   /* 110747 */ "Sampler23OutputReady\0"
   /* 110768 */ "Sampler2L2CacheMisses\0"
   /* 110790 */ "Sampler30InputAvailable\0"
   /* 110814 */ "Sampler30OutputReady\0"
   /* 110835 */ "Sampler31InputAvailable\0"
   /* 110859 */ "Sampler31OutputReady\0"
   /* 110880 */ "Sampler32InputAvailable\0"
   /* 110904 */ "Sampler32OutputReady\0"
   /* 110925 */ "Sampler33InputAvailable\0"
   /* 110949 */ "Sampler33OutputReady\0"
   /* 110970 */ "Sampler3L2CacheMisses\0"
   /* 110992 */ "Sampler40InputAvailable\0"
   /* 111016 */ "Sampler40OutputReady\0"
   /* 111037 */ "Sampler41InputAvailable\0"
   /* 111061 */ "Sampler41OutputReady\0"
   /* 111082 */ "Sampler42InputAvailable\0"
   /* 111106 */ "Sampler42OutputReady\0"
   /* 111127 */ "Sampler43InputAvailable\0"
   /* 111151 */ "Sampler43OutputReady\0"
   /* 111172 */ "Sampler50InputAvailable\0"
   /* 111196 */ "Sampler50OutputReady\0"
   /* 111217 */ "Sampler51InputAvailable\0"
   /* 111241 */ "Sampler51OutputReady\0"
   /* 111262 */ "Sampler52InputAvailable\0"
   /* 111286 */ "Sampler52OutputReady\0"
   /* 111307 */ "Sampler53InputAvailable\0"
   /* 111331 */ "Sampler53OutputReady\0"
   /* 111352 */ "Sampler60InputAvailable\0"
   /* 111376 */ "Sampler60OutputReady\0"
   /* 111397 */ "Sampler61InputAvailable\0"
   /* 111421 */ "Sampler61OutputReady\0"
   /* 111442 */ "Sampler62InputAvailable\0"
   /* 111466 */ "Sampler62OutputReady\0"
   /* 111487 */ "Sampler63InputAvailable\0"
   /* 111511 */ "Sampler63OutputReady\0"
   /* 111532 */ "Sampler70InputAvailable\0"
   /* 111556 */ "Sampler70OutputReady\0"
   /* 111577 */ "Sampler71InputAvailable\0"
   /* 111601 */ "Sampler71OutputReady\0"
   /* 111622 */ "Sampler72InputAvailable\0"
   /* 111646 */ "Sampler72OutputReady\0"
   /* 111667 */ "Sampler73InputAvailable\0"
   /* 111691 */ "Sampler73OutputReady\0"
   /* 111712 */ "SamplerAccesses\0"
   /* 111728 */ "SamplerBottleneck\0"
   /* 111746 */ "SamplerL1Misses\0"
   /* 111762 */ "SamplerL2CacheMisses\0"
   /* 111783 */ "SamplerTexelMisses\0"
   /* 111802 */ "SamplerTexels\0"
   /* 111816 */ "SamplersBusy\0"
   /* 111829 */ "SamplesBlended\0"
   /* 111844 */ "SamplesKilledInPs\0"
   /* 111862 */ "SamplesWritten\0"
   /* 111877 */ "SendActive\0"
   /* 111888 */ "Sf0Bottleneck\0"
   /* 111902 */ "Sf0Stall\0"
   /* 111911 */ "Sf1Bottleneck\0"
   /* 111925 */ "Sf1Stall\0"
   /* 111934 */ "Sf2Bottleneck\0"
   /* 111948 */ "Sf2Stall\0"
   /* 111957 */ "Sf3Bottleneck\0"
   /* 111971 */ "Sf3Stall\0"
   /* 111980 */ "Sf4Bottleneck\0"
   /* 111994 */ "Sf4Stall\0"
   /* 112003 */ "Sf5Bottleneck\0"
   /* 112017 */ "Sf5Stall\0"
   /* 112026 */ "Sf6Bottleneck\0"
   /* 112040 */ "Sf6Stall\0"
   /* 112049 */ "Sf7Bottleneck\0"
   /* 112063 */ "Sf7Stall\0"
   /* 112072 */ "SfBottleneck\0"
   /* 112085 */ "SfStall\0"
   /* 112093 */ "ShaderAtomics\0"
   /* 112107 */ "ShaderBarriers\0"
   /* 112122 */ "ShaderMemoryAccesses\0"
   /* 112143 */ "SlmBytesRead\0"
   /* 112156 */ "SlmBytesWritten\0"
   /* 112172 */ "SlmReads\0"
   /* 112181 */ "SlmWrites\0"
   /* 112191 */ "So0Bottleneck\0"
   /* 112205 */ "So0Stall\0"
   /* 112214 */ "So1Bottleneck\0"
   /* 112228 */ "So1Stall\0"
   /* 112237 */ "So2Bottleneck\0"
   /* 112251 */ "So2Stall\0"
   /* 112260 */ "So3Bottleneck\0"
   /* 112274 */ "So3Stall\0"
   /* 112283 */ "So4Bottleneck\0"
   /* 112297 */ "So4Stall\0"
   /* 112306 */ "So5Bottleneck\0"
   /* 112320 */ "So5Stall\0"
   /* 112329 */ "So6Bottleneck\0"
   /* 112343 */ "So6Stall\0"
   /* 112352 */ "So7Bottleneck\0"
   /* 112366 */ "So7Stall\0"
   /* 112375 */ "SoBottleneck\0"
   /* 112388 */ "SoStall\0"
   /* 112396 */ "StcPMAStall\0"
   /* 112408 */ "TASK_THREADGROUP_COUNT_XECORE0\0"
   /* 112439 */ "TASK_THREADGROUP_COUNT_XECORE1\0"
   /* 112470 */ "TASK_THREADGROUP_COUNT_XECORE10\0"
   /* 112502 */ "TASK_THREADGROUP_COUNT_XECORE11\0"
   /* 112534 */ "TASK_THREADGROUP_COUNT_XECORE12\0"
   /* 112566 */ "TASK_THREADGROUP_COUNT_XECORE13\0"
   /* 112598 */ "TASK_THREADGROUP_COUNT_XECORE14\0"
   /* 112630 */ "TASK_THREADGROUP_COUNT_XECORE15\0"
   /* 112662 */ "TASK_THREADGROUP_COUNT_XECORE16\0"
   /* 112694 */ "TASK_THREADGROUP_COUNT_XECORE17\0"
   /* 112726 */ "TASK_THREADGROUP_COUNT_XECORE18\0"
   /* 112758 */ "TASK_THREADGROUP_COUNT_XECORE19\0"
   /* 112790 */ "TASK_THREADGROUP_COUNT_XECORE2\0"
   /* 112821 */ "TASK_THREADGROUP_COUNT_XECORE20\0"
   /* 112853 */ "TASK_THREADGROUP_COUNT_XECORE21\0"
   /* 112885 */ "TASK_THREADGROUP_COUNT_XECORE22\0"
   /* 112917 */ "TASK_THREADGROUP_COUNT_XECORE23\0"
   /* 112949 */ "TASK_THREADGROUP_COUNT_XECORE24\0"
   /* 112981 */ "TASK_THREADGROUP_COUNT_XECORE25\0"
   /* 113013 */ "TASK_THREADGROUP_COUNT_XECORE26\0"
   /* 113045 */ "TASK_THREADGROUP_COUNT_XECORE27\0"
   /* 113077 */ "TASK_THREADGROUP_COUNT_XECORE28\0"
   /* 113109 */ "TASK_THREADGROUP_COUNT_XECORE29\0"
   /* 113141 */ "TASK_THREADGROUP_COUNT_XECORE3\0"
   /* 113172 */ "TASK_THREADGROUP_COUNT_XECORE30\0"
   /* 113204 */ "TASK_THREADGROUP_COUNT_XECORE31\0"
   /* 113236 */ "TASK_THREADGROUP_COUNT_XECORE4\0"
   /* 113267 */ "TASK_THREADGROUP_COUNT_XECORE5\0"
   /* 113298 */ "TASK_THREADGROUP_COUNT_XECORE6\0"
   /* 113329 */ "TASK_THREADGROUP_COUNT_XECORE7\0"
   /* 113360 */ "TASK_THREADGROUP_COUNT_XECORE8\0"
   /* 113391 */ "TASK_THREADGROUP_COUNT_XECORE9\0"
   /* 113422 */ "TASK_THREAD_EXIT_COUNT_XECORE0\0"
   /* 113453 */ "TASK_THREAD_EXIT_COUNT_XECORE1\0"
   /* 113484 */ "TASK_THREAD_EXIT_COUNT_XECORE10\0"
   /* 113516 */ "TASK_THREAD_EXIT_COUNT_XECORE11\0"
   /* 113548 */ "TASK_THREAD_EXIT_COUNT_XECORE12\0"
   /* 113580 */ "TASK_THREAD_EXIT_COUNT_XECORE13\0"
   /* 113612 */ "TASK_THREAD_EXIT_COUNT_XECORE14\0"
   /* 113644 */ "TASK_THREAD_EXIT_COUNT_XECORE15\0"
   /* 113676 */ "TASK_THREAD_EXIT_COUNT_XECORE16\0"
   /* 113708 */ "TASK_THREAD_EXIT_COUNT_XECORE17\0"
   /* 113740 */ "TASK_THREAD_EXIT_COUNT_XECORE18\0"
   /* 113772 */ "TASK_THREAD_EXIT_COUNT_XECORE19\0"
   /* 113804 */ "TASK_THREAD_EXIT_COUNT_XECORE2\0"
   /* 113835 */ "TASK_THREAD_EXIT_COUNT_XECORE20\0"
   /* 113867 */ "TASK_THREAD_EXIT_COUNT_XECORE21\0"
   /* 113899 */ "TASK_THREAD_EXIT_COUNT_XECORE22\0"
   /* 113931 */ "TASK_THREAD_EXIT_COUNT_XECORE23\0"
   /* 113963 */ "TASK_THREAD_EXIT_COUNT_XECORE24\0"
   /* 113995 */ "TASK_THREAD_EXIT_COUNT_XECORE25\0"
   /* 114027 */ "TASK_THREAD_EXIT_COUNT_XECORE26\0"
   /* 114059 */ "TASK_THREAD_EXIT_COUNT_XECORE27\0"
   /* 114091 */ "TASK_THREAD_EXIT_COUNT_XECORE28\0"
   /* 114123 */ "TASK_THREAD_EXIT_COUNT_XECORE29\0"
   /* 114155 */ "TASK_THREAD_EXIT_COUNT_XECORE3\0"
   /* 114186 */ "TASK_THREAD_EXIT_COUNT_XECORE30\0"
   /* 114218 */ "TASK_THREAD_EXIT_COUNT_XECORE31\0"
   /* 114250 */ "TASK_THREAD_EXIT_COUNT_XECORE4\0"
   /* 114281 */ "TASK_THREAD_EXIT_COUNT_XECORE5\0"
   /* 114312 */ "TASK_THREAD_EXIT_COUNT_XECORE6\0"
   /* 114343 */ "TASK_THREAD_EXIT_COUNT_XECORE7\0"
   /* 114374 */ "TASK_THREAD_EXIT_COUNT_XECORE8\0"
   /* 114405 */ "TASK_THREAD_EXIT_COUNT_XECORE9\0"
   /* 114436 */ "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE0\0"
   /* 114486 */ "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE1\0"
   /* 114536 */ "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE2\0"
   /* 114586 */ "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE3\0"
   /* 114636 */ "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE4\0"
   /* 114686 */ "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE5\0"
   /* 114736 */ "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE6\0"
   /* 114786 */ "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE7\0"
   /* 114836 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0\0"
   /* 114888 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1\0"
   /* 114940 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE10\0"
   /* 114993 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE11\0"
   /* 115046 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE12\0"
   /* 115099 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE13\0"
   /* 115152 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE14\0"
   /* 115205 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE15\0"
   /* 115258 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE16\0"
   /* 115311 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE17\0"
   /* 115364 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE18\0"
   /* 115417 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE19\0"
   /* 115470 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2\0"
   /* 115522 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE20\0"
   /* 115575 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE21\0"
   /* 115628 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE22\0"
   /* 115681 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE23\0"
   /* 115734 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE24\0"
   /* 115787 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE25\0"
   /* 115840 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE26\0"
   /* 115893 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE27\0"
   /* 115946 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE28\0"
   /* 115999 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE29\0"
   /* 116052 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3\0"
   /* 116104 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE30\0"
   /* 116157 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE31\0"
   /* 116210 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4\0"
   /* 116262 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5\0"
   /* 116314 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6\0"
   /* 116366 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7\0"
   /* 116418 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE8\0"
   /* 116470 */ "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE9\0"
   /* 116522 */ "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE0\0"
   /* 116572 */ "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE1\0"
   /* 116622 */ "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE2\0"
   /* 116672 */ "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE3\0"
   /* 116722 */ "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE4\0"
   /* 116772 */ "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE5\0"
   /* 116822 */ "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE6\0"
   /* 116872 */ "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE7\0"
   /* 116922 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0\0"
   /* 116974 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1\0"
   /* 117026 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE10\0"
   /* 117079 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE11\0"
   /* 117132 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE12\0"
   /* 117185 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE13\0"
   /* 117238 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE14\0"
   /* 117291 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE15\0"
   /* 117344 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE16\0"
   /* 117397 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE17\0"
   /* 117450 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE18\0"
   /* 117503 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE19\0"
   /* 117556 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2\0"
   /* 117608 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE20\0"
   /* 117661 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE21\0"
   /* 117714 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE22\0"
   /* 117767 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE23\0"
   /* 117820 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE24\0"
   /* 117873 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE25\0"
   /* 117926 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE26\0"
   /* 117979 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE27\0"
   /* 118032 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE28\0"
   /* 118085 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE29\0"
   /* 118138 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3\0"
   /* 118190 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE30\0"
   /* 118243 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE31\0"
   /* 118296 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4\0"
   /* 118348 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5\0"
   /* 118400 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6\0"
   /* 118452 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7\0"
   /* 118504 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE8\0"
   /* 118556 */ "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE9\0"
   /* 118608 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0\0"
   /* 118652 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1\0"
   /* 118696 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE10\0"
   /* 118741 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE11\0"
   /* 118786 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE12\0"
   /* 118831 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE13\0"
   /* 118876 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE14\0"
   /* 118921 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE15\0"
   /* 118966 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE16\0"
   /* 119011 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE17\0"
   /* 119056 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE18\0"
   /* 119101 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE19\0"
   /* 119146 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2\0"
   /* 119190 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE20\0"
   /* 119235 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE21\0"
   /* 119280 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE22\0"
   /* 119325 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE23\0"
   /* 119370 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE24\0"
   /* 119415 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE25\0"
   /* 119460 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE26\0"
   /* 119505 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE27\0"
   /* 119550 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE28\0"
   /* 119595 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE29\0"
   /* 119640 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3\0"
   /* 119684 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE30\0"
   /* 119729 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE31\0"
   /* 119774 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4\0"
   /* 119818 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5\0"
   /* 119862 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6\0"
   /* 119906 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7\0"
   /* 119950 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE8\0"
   /* 119994 */ "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE9\0"
   /* 120038 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0\0"
   /* 120078 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1\0"
   /* 120118 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE10\0"
   /* 120159 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE11\0"
   /* 120200 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE12\0"
   /* 120241 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE13\0"
   /* 120282 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE14\0"
   /* 120323 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE15\0"
   /* 120364 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE16\0"
   /* 120405 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE17\0"
   /* 120446 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE18\0"
   /* 120487 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE19\0"
   /* 120528 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2\0"
   /* 120568 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE20\0"
   /* 120609 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE21\0"
   /* 120650 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE22\0"
   /* 120691 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE23\0"
   /* 120732 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE24\0"
   /* 120773 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE25\0"
   /* 120814 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE26\0"
   /* 120855 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE27\0"
   /* 120896 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE28\0"
   /* 120937 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE29\0"
   /* 120978 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3\0"
   /* 121018 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE30\0"
   /* 121059 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE31\0"
   /* 121100 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4\0"
   /* 121140 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5\0"
   /* 121180 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6\0"
   /* 121220 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7\0"
   /* 121260 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE8\0"
   /* 121300 */ "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE9\0"
   /* 121340 */ "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE0\0"
   /* 121381 */ "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE1\0"
   /* 121422 */ "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE2\0"
   /* 121463 */ "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE3\0"
   /* 121504 */ "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE4\0"
   /* 121545 */ "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE5\0"
   /* 121586 */ "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE6\0"
   /* 121627 */ "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE7\0"
   /* 121668 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE0\0"
   /* 121702 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE1\0"
   /* 121736 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE10\0"
   /* 121771 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE11\0"
   /* 121806 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE12\0"
   /* 121841 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE13\0"
   /* 121876 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE14\0"
   /* 121911 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE15\0"
   /* 121946 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE16\0"
   /* 121981 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE17\0"
   /* 122016 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE18\0"
   /* 122051 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE19\0"
   /* 122086 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE2\0"
   /* 122120 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE20\0"
   /* 122155 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE21\0"
   /* 122190 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE22\0"
   /* 122225 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE23\0"
   /* 122260 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE24\0"
   /* 122295 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE25\0"
   /* 122330 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE26\0"
   /* 122365 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE27\0"
   /* 122400 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE28\0"
   /* 122435 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE29\0"
   /* 122470 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE3\0"
   /* 122504 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE30\0"
   /* 122539 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE31\0"
   /* 122574 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE4\0"
   /* 122608 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE5\0"
   /* 122642 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE6\0"
   /* 122676 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE7\0"
   /* 122710 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE8\0"
   /* 122744 */ "THREAD_DISPATCH_PS_ACTIVE_XECORE9\0"
   /* 122778 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0\0"
   /* 122816 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1\0"
   /* 122854 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE10\0"
   /* 122893 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE11\0"
   /* 122932 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE12\0"
   /* 122971 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE13\0"
   /* 123010 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE14\0"
   /* 123049 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE15\0"
   /* 123088 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE16\0"
   /* 123127 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE17\0"
   /* 123166 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE18\0"
   /* 123205 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE19\0"
   /* 123244 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2\0"
   /* 123282 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE20\0"
   /* 123321 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE21\0"
   /* 123360 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE22\0"
   /* 123399 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE23\0"
   /* 123438 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE24\0"
   /* 123477 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE25\0"
   /* 123516 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE26\0"
   /* 123555 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE27\0"
   /* 123594 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE28\0"
   /* 123633 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE29\0"
   /* 123672 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3\0"
   /* 123710 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE30\0"
   /* 123749 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE31\0"
   /* 123788 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4\0"
   /* 123826 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5\0"
   /* 123864 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6\0"
   /* 123902 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7\0"
   /* 123940 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE8\0"
   /* 123978 */ "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE9\0"
   /* 124016 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0\0"
   /* 124054 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1\0"
   /* 124092 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE10\0"
   /* 124131 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE11\0"
   /* 124170 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE12\0"
   /* 124209 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE13\0"
   /* 124248 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE14\0"
   /* 124287 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE15\0"
   /* 124326 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE16\0"
   /* 124365 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE17\0"
   /* 124404 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE18\0"
   /* 124443 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE19\0"
   /* 124482 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2\0"
   /* 124520 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE20\0"
   /* 124559 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE21\0"
   /* 124598 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE22\0"
   /* 124637 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE23\0"
   /* 124676 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE24\0"
   /* 124715 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE25\0"
   /* 124754 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE26\0"
   /* 124793 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE27\0"
   /* 124832 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE28\0"
   /* 124871 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE29\0"
   /* 124910 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3\0"
   /* 124948 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE30\0"
   /* 124987 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE31\0"
   /* 125026 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4\0"
   /* 125064 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5\0"
   /* 125102 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6\0"
   /* 125140 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7\0"
   /* 125178 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE8\0"
   /* 125216 */ "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE9\0"
   /* 125254 */ "THREAD_DISPATCH_STALL_XECORE0\0"
   /* 125284 */ "THREAD_DISPATCH_STALL_XECORE1\0"
   /* 125314 */ "THREAD_DISPATCH_STALL_XECORE10\0"
   /* 125345 */ "THREAD_DISPATCH_STALL_XECORE11\0"
   /* 125376 */ "THREAD_DISPATCH_STALL_XECORE12\0"
   /* 125407 */ "THREAD_DISPATCH_STALL_XECORE13\0"
   /* 125438 */ "THREAD_DISPATCH_STALL_XECORE14\0"
   /* 125469 */ "THREAD_DISPATCH_STALL_XECORE15\0"
   /* 125500 */ "THREAD_DISPATCH_STALL_XECORE16\0"
   /* 125531 */ "THREAD_DISPATCH_STALL_XECORE17\0"
   /* 125562 */ "THREAD_DISPATCH_STALL_XECORE18\0"
   /* 125593 */ "THREAD_DISPATCH_STALL_XECORE19\0"
   /* 125624 */ "THREAD_DISPATCH_STALL_XECORE2\0"
   /* 125654 */ "THREAD_DISPATCH_STALL_XECORE20\0"
   /* 125685 */ "THREAD_DISPATCH_STALL_XECORE21\0"
   /* 125716 */ "THREAD_DISPATCH_STALL_XECORE22\0"
   /* 125747 */ "THREAD_DISPATCH_STALL_XECORE23\0"
   /* 125778 */ "THREAD_DISPATCH_STALL_XECORE24\0"
   /* 125809 */ "THREAD_DISPATCH_STALL_XECORE25\0"
   /* 125840 */ "THREAD_DISPATCH_STALL_XECORE26\0"
   /* 125871 */ "THREAD_DISPATCH_STALL_XECORE27\0"
   /* 125902 */ "THREAD_DISPATCH_STALL_XECORE28\0"
   /* 125933 */ "THREAD_DISPATCH_STALL_XECORE29\0"
   /* 125964 */ "THREAD_DISPATCH_STALL_XECORE3\0"
   /* 125994 */ "THREAD_DISPATCH_STALL_XECORE30\0"
   /* 126025 */ "THREAD_DISPATCH_STALL_XECORE31\0"
   /* 126056 */ "THREAD_DISPATCH_STALL_XECORE4\0"
   /* 126086 */ "THREAD_DISPATCH_STALL_XECORE5\0"
   /* 126116 */ "THREAD_DISPATCH_STALL_XECORE6\0"
   /* 126146 */ "THREAD_DISPATCH_STALL_XECORE7\0"
   /* 126176 */ "THREAD_DISPATCH_STALL_XECORE8\0"
   /* 126206 */ "THREAD_DISPATCH_STALL_XECORE9\0"
   /* 126236 */ "TeBottleneck\0"
   /* 126249 */ "ThreadHeader00Ready\0"
   /* 126269 */ "ThreadHeader00ReadyPort0\0"
   /* 126294 */ "ThreadHeader00ReadyPort1\0"
   /* 126319 */ "ThreadHeader00ReadyPort2\0"
   /* 126344 */ "ThreadHeader00ReadyPort3\0"
   /* 126369 */ "ThreadHeader01Ready\0"
   /* 126389 */ "ThreadHeader01ReadyPort0\0"
   /* 126414 */ "ThreadHeader01ReadyPort1\0"
   /* 126439 */ "ThreadHeader01ReadyPort2\0"
   /* 126464 */ "ThreadHeader01ReadyPort3\0"
   /* 126489 */ "ThreadHeader02Ready\0"
   /* 126509 */ "ThreadHeader02ReadyPort0\0"
   /* 126534 */ "ThreadHeader02ReadyPort1\0"
   /* 126559 */ "ThreadHeader02ReadyPort2\0"
   /* 126584 */ "ThreadHeader02ReadyPort3\0"
   /* 126609 */ "ThreadHeader03Ready\0"
   /* 126629 */ "ThreadHeader03ReadyPort0\0"
   /* 126654 */ "ThreadHeader03ReadyPort1\0"
   /* 126679 */ "ThreadHeader03ReadyPort2\0"
   /* 126704 */ "ThreadHeader03ReadyPort3\0"
   /* 126729 */ "ThreadHeader04Ready\0"
   /* 126749 */ "ThreadHeader04ReadyPort0\0"
   /* 126774 */ "ThreadHeader04ReadyPort1\0"
   /* 126799 */ "ThreadHeader04ReadyPort2\0"
   /* 126824 */ "ThreadHeader04ReadyPort3\0"
   /* 126849 */ "ThreadHeader05Ready\0"
   /* 126869 */ "ThreadHeader05ReadyPort0\0"
   /* 126894 */ "ThreadHeader05ReadyPort1\0"
   /* 126919 */ "ThreadHeader05ReadyPort2\0"
   /* 126944 */ "ThreadHeader05ReadyPort3\0"
   /* 126969 */ "ThreadHeader06ReadyPort0\0"
   /* 126994 */ "ThreadHeader06ReadyPort1\0"
   /* 127019 */ "ThreadHeader07ReadyPort0\0"
   /* 127044 */ "ThreadHeader07ReadyPort1\0"
   /* 127069 */ "ThreadHeader10Ready\0"
   /* 127089 */ "ThreadHeader10ReadyPort0\0"
   /* 127114 */ "ThreadHeader10ReadyPort1\0"
   /* 127139 */ "ThreadHeader10ReadyPort2\0"
   /* 127164 */ "ThreadHeader10ReadyPort3\0"
   /* 127189 */ "ThreadHeader11Ready\0"
   /* 127209 */ "ThreadHeader11ReadyPort0\0"
   /* 127234 */ "ThreadHeader11ReadyPort1\0"
   /* 127259 */ "ThreadHeader11ReadyPort2\0"
   /* 127284 */ "ThreadHeader11ReadyPort3\0"
   /* 127309 */ "ThreadHeader12Ready\0"
   /* 127329 */ "ThreadHeader12ReadyPort0\0"
   /* 127354 */ "ThreadHeader12ReadyPort1\0"
   /* 127379 */ "ThreadHeader12ReadyPort2\0"
   /* 127404 */ "ThreadHeader12ReadyPort3\0"
   /* 127429 */ "ThreadHeader13Ready\0"
   /* 127449 */ "ThreadHeader13ReadyPort0\0"
   /* 127474 */ "ThreadHeader13ReadyPort1\0"
   /* 127499 */ "ThreadHeader13ReadyPort2\0"
   /* 127524 */ "ThreadHeader13ReadyPort3\0"
   /* 127549 */ "ThreadHeader20Ready\0"
   /* 127569 */ "ThreadHeader20ReadyPort0\0"
   /* 127594 */ "ThreadHeader20ReadyPort1\0"
   /* 127619 */ "ThreadHeader20ReadyPort2\0"
   /* 127644 */ "ThreadHeader20ReadyPort3\0"
   /* 127669 */ "ThreadHeader21Ready\0"
   /* 127689 */ "ThreadHeader21ReadyPort0\0"
   /* 127714 */ "ThreadHeader21ReadyPort1\0"
   /* 127739 */ "ThreadHeader21ReadyPort2\0"
   /* 127764 */ "ThreadHeader21ReadyPort3\0"
   /* 127789 */ "ThreadHeader22Ready\0"
   /* 127809 */ "ThreadHeader22ReadyPort0\0"
   /* 127834 */ "ThreadHeader22ReadyPort1\0"
   /* 127859 */ "ThreadHeader22ReadyPort2\0"
   /* 127884 */ "ThreadHeader22ReadyPort3\0"
   /* 127909 */ "ThreadHeader23Ready\0"
   /* 127929 */ "ThreadHeader23ReadyPort0\0"
   /* 127954 */ "ThreadHeader23ReadyPort1\0"
   /* 127979 */ "ThreadHeader23ReadyPort2\0"
   /* 128004 */ "ThreadHeader23ReadyPort3\0"
   /* 128029 */ "ThreadHeader30Ready\0"
   /* 128049 */ "ThreadHeader30ReadyPort0\0"
   /* 128074 */ "ThreadHeader30ReadyPort1\0"
   /* 128099 */ "ThreadHeader30ReadyPort2\0"
   /* 128124 */ "ThreadHeader30ReadyPort3\0"
   /* 128149 */ "ThreadHeader31Ready\0"
   /* 128169 */ "ThreadHeader31ReadyPort0\0"
   /* 128194 */ "ThreadHeader31ReadyPort1\0"
   /* 128219 */ "ThreadHeader31ReadyPort2\0"
   /* 128244 */ "ThreadHeader31ReadyPort3\0"
   /* 128269 */ "ThreadHeader32Ready\0"
   /* 128289 */ "ThreadHeader32ReadyPort0\0"
   /* 128314 */ "ThreadHeader32ReadyPort1\0"
   /* 128339 */ "ThreadHeader32ReadyPort2\0"
   /* 128364 */ "ThreadHeader32ReadyPort3\0"
   /* 128389 */ "ThreadHeader33Ready\0"
   /* 128409 */ "ThreadHeader33ReadyPort0\0"
   /* 128434 */ "ThreadHeader33ReadyPort1\0"
   /* 128459 */ "ThreadHeader33ReadyPort2\0"
   /* 128484 */ "ThreadHeader33ReadyPort3\0"
   /* 128509 */ "ThreadHeader40Ready\0"
   /* 128529 */ "ThreadHeader40ReadyPort0\0"
   /* 128554 */ "ThreadHeader40ReadyPort1\0"
   /* 128579 */ "ThreadHeader40ReadyPort2\0"
   /* 128604 */ "ThreadHeader40ReadyPort3\0"
   /* 128629 */ "ThreadHeader41Ready\0"
   /* 128649 */ "ThreadHeader41ReadyPort0\0"
   /* 128674 */ "ThreadHeader41ReadyPort1\0"
   /* 128699 */ "ThreadHeader41ReadyPort2\0"
   /* 128724 */ "ThreadHeader41ReadyPort3\0"
   /* 128749 */ "ThreadHeader42Ready\0"
   /* 128769 */ "ThreadHeader42ReadyPort0\0"
   /* 128794 */ "ThreadHeader42ReadyPort1\0"
   /* 128819 */ "ThreadHeader42ReadyPort2\0"
   /* 128844 */ "ThreadHeader42ReadyPort3\0"
   /* 128869 */ "ThreadHeader43Ready\0"
   /* 128889 */ "ThreadHeader43ReadyPort0\0"
   /* 128914 */ "ThreadHeader43ReadyPort1\0"
   /* 128939 */ "ThreadHeader43ReadyPort2\0"
   /* 128964 */ "ThreadHeader43ReadyPort3\0"
   /* 128989 */ "ThreadHeader50Ready\0"
   /* 129009 */ "ThreadHeader50ReadyPort0\0"
   /* 129034 */ "ThreadHeader50ReadyPort1\0"
   /* 129059 */ "ThreadHeader50ReadyPort2\0"
   /* 129084 */ "ThreadHeader50ReadyPort3\0"
   /* 129109 */ "ThreadHeader51Ready\0"
   /* 129129 */ "ThreadHeader51ReadyPort0\0"
   /* 129154 */ "ThreadHeader51ReadyPort1\0"
   /* 129179 */ "ThreadHeader51ReadyPort2\0"
   /* 129204 */ "ThreadHeader51ReadyPort3\0"
   /* 129229 */ "ThreadHeader52Ready\0"
   /* 129249 */ "ThreadHeader52ReadyPort0\0"
   /* 129274 */ "ThreadHeader52ReadyPort1\0"
   /* 129299 */ "ThreadHeader52ReadyPort2\0"
   /* 129324 */ "ThreadHeader52ReadyPort3\0"
   /* 129349 */ "ThreadHeader53Ready\0"
   /* 129369 */ "ThreadHeader53ReadyPort0\0"
   /* 129394 */ "ThreadHeader53ReadyPort1\0"
   /* 129419 */ "ThreadHeader53ReadyPort2\0"
   /* 129444 */ "ThreadHeader53ReadyPort3\0"
   /* 129469 */ "ThreadHeader60Ready\0"
   /* 129489 */ "ThreadHeader60ReadyPort0\0"
   /* 129514 */ "ThreadHeader60ReadyPort1\0"
   /* 129539 */ "ThreadHeader60ReadyPort2\0"
   /* 129564 */ "ThreadHeader60ReadyPort3\0"
   /* 129589 */ "ThreadHeader61Ready\0"
   /* 129609 */ "ThreadHeader61ReadyPort0\0"
   /* 129634 */ "ThreadHeader61ReadyPort1\0"
   /* 129659 */ "ThreadHeader61ReadyPort2\0"
   /* 129684 */ "ThreadHeader61ReadyPort3\0"
   /* 129709 */ "ThreadHeader62Ready\0"
   /* 129729 */ "ThreadHeader62ReadyPort0\0"
   /* 129754 */ "ThreadHeader62ReadyPort1\0"
   /* 129779 */ "ThreadHeader62ReadyPort2\0"
   /* 129804 */ "ThreadHeader62ReadyPort3\0"
   /* 129829 */ "ThreadHeader63Ready\0"
   /* 129849 */ "ThreadHeader63ReadyPort0\0"
   /* 129874 */ "ThreadHeader63ReadyPort1\0"
   /* 129899 */ "ThreadHeader63ReadyPort2\0"
   /* 129924 */ "ThreadHeader63ReadyPort3\0"
   /* 129949 */ "ThreadHeader70Ready\0"
   /* 129969 */ "ThreadHeader70ReadyPort0\0"
   /* 129994 */ "ThreadHeader70ReadyPort1\0"
   /* 130019 */ "ThreadHeader70ReadyPort2\0"
   /* 130044 */ "ThreadHeader70ReadyPort3\0"
   /* 130069 */ "ThreadHeader71Ready\0"
   /* 130089 */ "ThreadHeader71ReadyPort0\0"
   /* 130114 */ "ThreadHeader71ReadyPort1\0"
   /* 130139 */ "ThreadHeader71ReadyPort2\0"
   /* 130164 */ "ThreadHeader71ReadyPort3\0"
   /* 130189 */ "ThreadHeader72Ready\0"
   /* 130209 */ "ThreadHeader72ReadyPort0\0"
   /* 130234 */ "ThreadHeader72ReadyPort1\0"
   /* 130259 */ "ThreadHeader72ReadyPort2\0"
   /* 130284 */ "ThreadHeader72ReadyPort3\0"
   /* 130309 */ "ThreadHeader73Ready\0"
   /* 130329 */ "ThreadHeader73ReadyPort0\0"
   /* 130354 */ "ThreadHeader73ReadyPort1\0"
   /* 130379 */ "ThreadHeader73ReadyPort2\0"
   /* 130404 */ "ThreadHeader73ReadyPort3\0"
   /* 130429 */ "TypedAtomics\0"
   /* 130442 */ "TypedAtomics0\0"
   /* 130456 */ "TypedAtomics00\0"
   /* 130471 */ "TypedAtomicsPerCacheLine\0"
   /* 130496 */ "TypedBytesRead\0"
   /* 130511 */ "TypedBytesWritten\0"
   /* 130529 */ "TypedReads0\0"
   /* 130541 */ "TypedReads00\0"
   /* 130554 */ "TypedReadsPerCacheLine\0"
   /* 130577 */ "TypedWrites0\0"
   /* 130590 */ "TypedWrites00\0"
   /* 130604 */ "TypedWritesPerCacheLine\0"
   /* 130628 */ "URB_CROSS_SLICE_READ_SLICE0\0"
   /* 130656 */ "URB_CROSS_SLICE_READ_SLICE1\0"
   /* 130684 */ "URB_CROSS_SLICE_READ_SLICE2\0"
   /* 130712 */ "URB_CROSS_SLICE_READ_SLICE3\0"
   /* 130740 */ "URB_CROSS_SLICE_READ_SLICE4\0"
   /* 130768 */ "URB_CROSS_SLICE_READ_SLICE5\0"
   /* 130796 */ "URB_CROSS_SLICE_READ_SLICE6\0"
   /* 130824 */ "URB_CROSS_SLICE_READ_SLICE7\0"
   /* 130852 */ "URB_READ_SLICE0\0"
   /* 130868 */ "URB_READ_SLICE1\0"
   /* 130884 */ "URB_READ_SLICE2\0"
   /* 130900 */ "URB_READ_SLICE3\0"
   /* 130916 */ "URB_READ_SLICE4\0"
   /* 130932 */ "URB_READ_SLICE5\0"
   /* 130948 */ "URB_READ_SLICE6\0"
   /* 130964 */ "URB_READ_SLICE7\0"
   /* 130980 */ "URB_WRITE_SLICE0\0"
   /* 130997 */ "URB_WRITE_SLICE1\0"
   /* 131014 */ "URB_WRITE_SLICE2\0"
   /* 131031 */ "URB_WRITE_SLICE3\0"
   /* 131048 */ "URB_WRITE_SLICE4\0"
   /* 131065 */ "URB_WRITE_SLICE5\0"
   /* 131082 */ "URB_WRITE_SLICE6\0"
   /* 131099 */ "URB_WRITE_SLICE7\0"
   /* 131116 */ "UntypedBytesRead\0"
   /* 131133 */ "UntypedBytesWritten\0"
   /* 131153 */ "UntypedReads0\0"
   /* 131167 */ "UntypedReads00\0"
   /* 131182 */ "UntypedReadsPerCacheLine\0"
   /* 131207 */ "UntypedWrites0\0"
   /* 131222 */ "UntypedWrites00\0"
   /* 131238 */ "UntypedWritesPerCacheLine\0"
   /* 131264 */ "VERTEX_FETCH_INPUT_AVAILABLE_SLICE0\0"
   /* 131300 */ "VERTEX_FETCH_INPUT_AVAILABLE_SLICE1\0"
   /* 131336 */ "VERTEX_FETCH_INPUT_AVAILABLE_SLICE2\0"
   /* 131372 */ "VERTEX_FETCH_INPUT_AVAILABLE_SLICE3\0"
   /* 131408 */ "VERTEX_FETCH_INPUT_AVAILABLE_SLICE4\0"
   /* 131444 */ "VERTEX_FETCH_INPUT_AVAILABLE_SLICE5\0"
   /* 131480 */ "VERTEX_FETCH_INPUT_AVAILABLE_SLICE6\0"
   /* 131516 */ "VERTEX_FETCH_INPUT_AVAILABLE_SLICE7\0"
   /* 131552 */ "VERTEX_FETCH_OUTPUT_READY_SLICE0\0"
   /* 131585 */ "VERTEX_FETCH_OUTPUT_READY_SLICE1\0"
   /* 131618 */ "VERTEX_FETCH_OUTPUT_READY_SLICE2\0"
   /* 131651 */ "VERTEX_FETCH_OUTPUT_READY_SLICE3\0"
   /* 131684 */ "VERTEX_FETCH_OUTPUT_READY_SLICE4\0"
   /* 131717 */ "VERTEX_FETCH_OUTPUT_READY_SLICE5\0"
   /* 131750 */ "VERTEX_FETCH_OUTPUT_READY_SLICE6\0"
   /* 131783 */ "VERTEX_FETCH_OUTPUT_READY_SLICE7\0"
   /* 131816 */ "VMEBusy\0"
   /* 131824 */ "VS_OUTPUT_READY_SLICE0\0"
   /* 131847 */ "VS_OUTPUT_READY_SLICE1\0"
   /* 131870 */ "VS_OUTPUT_READY_SLICE2\0"
   /* 131893 */ "VS_OUTPUT_READY_SLICE3\0"
   /* 131916 */ "VS_OUTPUT_READY_SLICE4\0"
   /* 131939 */ "VS_OUTPUT_READY_SLICE5\0"
   /* 131962 */ "VS_OUTPUT_READY_SLICE6\0"
   /* 131985 */ "VS_OUTPUT_READY_SLICE7\0"
   /* 132008 */ "Vdbox00Busy\0"
   /* 132020 */ "Vdbox0Busy\0"
   /* 132031 */ "Vdbox10Busy\0"
   /* 132043 */ "Vdbox1Busy\0"
   /* 132054 */ "Vebox0Busy\0"
   /* 132065 */ "Vebox1Busy\0"
   /* 132076 */ "VeboxBusy\0"
   /* 132086 */ "Vf0Bottleneck\0"
   /* 132100 */ "Vf1Bottleneck\0"
   /* 132114 */ "Vf2Bottleneck\0"
   /* 132128 */ "Vf3Bottleneck\0"
   /* 132142 */ "Vf4Bottleneck\0"
   /* 132156 */ "Vf5Bottleneck\0"
   /* 132170 */ "Vf6Bottleneck\0"
   /* 132184 */ "Vf7Bottleneck\0"
   /* 132198 */ "VfBottleneck\0"
   /* 132211 */ "Vs0Bottleneck\0"
   /* 132225 */ "Vs1Bottleneck\0"
   /* 132239 */ "Vs2Bottleneck\0"
   /* 132253 */ "Vs3Bottleneck\0"
   /* 132267 */ "Vs4Bottleneck\0"
   /* 132281 */ "Vs5Bottleneck\0"
   /* 132295 */ "Vs6Bottleneck\0"
   /* 132309 */ "Vs7Bottleneck\0"
   /* 132323 */ "VsBottleneck\0"
   /* 132336 */ "VsClBypass\0"
   /* 132347 */ "VsDuration\0"
   /* 132358 */ "VsEmActive\0"
   /* 132369 */ "VsEuActive\0"
   /* 132380 */ "VsEuActivePerThread\0"
   /* 132400 */ "VsEuStall\0"
   /* 132410 */ "VsEuStallPerThread\0"
   /* 132429 */ "VsFpu0Active\0"
   /* 132442 */ "VsFpu1Active\0"
   /* 132455 */ "VsFpuActive\0"
   /* 132467 */ "VsSendActive\0"
   /* 132480 */ "VsThreads\0"
   /* 132490 */ "XVE_ACTIVE\0"
   /* 132501 */ "XVE_ACTIVE_ASYNC_CS\0"
   /* 132521 */ "XVE_ACTIVE_CS\0"
   /* 132535 */ "XVE_ACTIVE_CYCLES\0"
   /* 132553 */ "XVE_ACTIVE_CYCLES_ASYNC_CS\0"
   /* 132580 */ "XVE_ACTIVE_CYCLES_CS\0"
   /* 132601 */ "XVE_ACTIVE_CYCLES_DS\0"
   /* 132622 */ "XVE_ACTIVE_CYCLES_GS\0"
   /* 132643 */ "XVE_ACTIVE_CYCLES_HS\0"
   /* 132664 */ "XVE_ACTIVE_CYCLES_MS\0"
   /* 132685 */ "XVE_ACTIVE_CYCLES_PS\0"
   /* 132706 */ "XVE_ACTIVE_CYCLES_RT\0"
   /* 132727 */ "XVE_ACTIVE_CYCLES_TS\0"
   /* 132748 */ "XVE_ACTIVE_CYCLES_VS\0"
   /* 132769 */ "XVE_ACTIVE_DS\0"
   /* 132783 */ "XVE_ACTIVE_GS\0"
   /* 132797 */ "XVE_ACTIVE_HS\0"
   /* 132811 */ "XVE_ACTIVE_MS\0"
   /* 132825 */ "XVE_ACTIVE_PS\0"
   /* 132839 */ "XVE_ACTIVE_RT\0"
   /* 132853 */ "XVE_ACTIVE_TS\0"
   /* 132867 */ "XVE_ACTIVE_VS\0"
   /* 132881 */ "XVE_ATOMIC_ACCESS_COUNT\0"
   /* 132905 */ "XVE_BARRIER_MESSAGE_COUNT\0"
   /* 132931 */ "XVE_BUSY\0"
   /* 132940 */ "XVE_COMPUTE_THREAD_COUNT\0"
   /* 132965 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0\0"
   /* 133007 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1\0"
   /* 133049 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE10\0"
   /* 133092 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE11\0"
   /* 133135 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE12\0"
   /* 133178 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE13\0"
   /* 133221 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE14\0"
   /* 133264 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE15\0"
   /* 133307 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE16\0"
   /* 133350 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE17\0"
   /* 133393 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE18\0"
   /* 133436 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE19\0"
   /* 133479 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2\0"
   /* 133521 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE20\0"
   /* 133564 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE21\0"
   /* 133607 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE22\0"
   /* 133650 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE23\0"
   /* 133693 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE24\0"
   /* 133736 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE25\0"
   /* 133779 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE26\0"
   /* 133822 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE27\0"
   /* 133865 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE28\0"
   /* 133908 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE29\0"
   /* 133951 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3\0"
   /* 133993 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE30\0"
   /* 134036 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE31\0"
   /* 134079 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4\0"
   /* 134121 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5\0"
   /* 134163 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6\0"
   /* 134205 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7\0"
   /* 134247 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE8\0"
   /* 134289 */ "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE9\0"
   /* 134331 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0\0"
   /* 134372 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1\0"
   /* 134413 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE10\0"
   /* 134455 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE11\0"
   /* 134497 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE12\0"
   /* 134539 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE13\0"
   /* 134581 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE14\0"
   /* 134623 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE15\0"
   /* 134665 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE16\0"
   /* 134707 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE17\0"
   /* 134749 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE18\0"
   /* 134791 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE19\0"
   /* 134833 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2\0"
   /* 134874 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE20\0"
   /* 134916 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE21\0"
   /* 134958 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE22\0"
   /* 135000 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE23\0"
   /* 135042 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE24\0"
   /* 135084 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE25\0"
   /* 135126 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE26\0"
   /* 135168 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE27\0"
   /* 135210 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE28\0"
   /* 135252 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE29\0"
   /* 135294 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3\0"
   /* 135335 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE30\0"
   /* 135377 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE31\0"
   /* 135419 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4\0"
   /* 135460 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5\0"
   /* 135501 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6\0"
   /* 135542 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7\0"
   /* 135583 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE8\0"
   /* 135624 */ "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE9\0"
   /* 135665 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0\0"
   /* 135705 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1\0"
   /* 135745 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE10\0"
   /* 135786 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE11\0"
   /* 135827 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE12\0"
   /* 135868 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE13\0"
   /* 135909 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE14\0"
   /* 135950 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE15\0"
   /* 135991 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE16\0"
   /* 136032 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE17\0"
   /* 136073 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE18\0"
   /* 136114 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE19\0"
   /* 136155 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2\0"
   /* 136195 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE20\0"
   /* 136236 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE21\0"
   /* 136277 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE22\0"
   /* 136318 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE23\0"
   /* 136359 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE24\0"
   /* 136400 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE25\0"
   /* 136441 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE26\0"
   /* 136482 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE27\0"
   /* 136523 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE28\0"
   /* 136564 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE29\0"
   /* 136605 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3\0"
   /* 136645 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE30\0"
   /* 136686 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE31\0"
   /* 136727 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4\0"
   /* 136767 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5\0"
   /* 136807 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6\0"
   /* 136847 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7\0"
   /* 136887 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE8\0"
   /* 136927 */ "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE9\0"
   /* 136967 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0\0"
   /* 137011 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1\0"
   /* 137055 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE10\0"
   /* 137100 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE11\0"
   /* 137145 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE12\0"
   /* 137190 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE13\0"
   /* 137235 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE14\0"
   /* 137280 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE15\0"
   /* 137325 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE16\0"
   /* 137370 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE17\0"
   /* 137415 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE18\0"
   /* 137460 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE19\0"
   /* 137505 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2\0"
   /* 137549 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE20\0"
   /* 137594 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE21\0"
   /* 137639 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE22\0"
   /* 137684 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE23\0"
   /* 137729 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE24\0"
   /* 137774 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE25\0"
   /* 137819 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE26\0"
   /* 137864 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE27\0"
   /* 137909 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE28\0"
   /* 137954 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE29\0"
   /* 137999 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3\0"
   /* 138043 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE30\0"
   /* 138088 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE31\0"
   /* 138133 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4\0"
   /* 138177 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5\0"
   /* 138221 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6\0"
   /* 138265 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7\0"
   /* 138309 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE8\0"
   /* 138353 */ "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE9\0"
   /* 138397 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0\0"
   /* 138442 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1\0"
   /* 138487 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE10\0"
   /* 138533 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE11\0"
   /* 138579 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE12\0"
   /* 138625 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE13\0"
   /* 138671 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE14\0"
   /* 138717 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE15\0"
   /* 138763 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE16\0"
   /* 138809 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE17\0"
   /* 138855 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE18\0"
   /* 138901 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE19\0"
   /* 138947 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2\0"
   /* 138992 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE20\0"
   /* 139038 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE21\0"
   /* 139084 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE22\0"
   /* 139130 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE23\0"
   /* 139176 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE24\0"
   /* 139222 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE25\0"
   /* 139268 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE26\0"
   /* 139314 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE27\0"
   /* 139360 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE28\0"
   /* 139406 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE29\0"
   /* 139452 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3\0"
   /* 139497 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE30\0"
   /* 139543 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE31\0"
   /* 139589 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4\0"
   /* 139634 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5\0"
   /* 139679 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6\0"
   /* 139724 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7\0"
   /* 139769 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE8\0"
   /* 139814 */ "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE9\0"
   /* 139859 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0\0"
   /* 139900 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1\0"
   /* 139941 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE10\0"
   /* 139983 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE11\0"
   /* 140025 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE12\0"
   /* 140067 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE13\0"
   /* 140109 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE14\0"
   /* 140151 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE15\0"
   /* 140193 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE16\0"
   /* 140235 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE17\0"
   /* 140277 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE18\0"
   /* 140319 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE19\0"
   /* 140361 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2\0"
   /* 140402 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE20\0"
   /* 140444 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE21\0"
   /* 140486 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE22\0"
   /* 140528 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE23\0"
   /* 140570 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE24\0"
   /* 140612 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE25\0"
   /* 140654 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE26\0"
   /* 140696 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE27\0"
   /* 140738 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE28\0"
   /* 140780 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE29\0"
   /* 140822 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3\0"
   /* 140863 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE30\0"
   /* 140905 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE31\0"
   /* 140947 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4\0"
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   /* 141029 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6\0"
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   /* 141152 */ "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE9\0"
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   /* 141220 */ "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION\0"
   /* 141259 */ "XVE_INST_EXECUTED_ALU0_ASYNC_CS\0"
   /* 141291 */ "XVE_INST_EXECUTED_ALU0_ASYNC_CS_UTILIZATION\0"
   /* 141335 */ "XVE_INST_EXECUTED_ALU0_CS\0"
   /* 141361 */ "XVE_INST_EXECUTED_ALU0_CS_UTILIZATION\0"
   /* 141399 */ "XVE_INST_EXECUTED_ALU0_DS\0"
   /* 141425 */ "XVE_INST_EXECUTED_ALU0_DS_UTILIZATION\0"
   /* 141463 */ "XVE_INST_EXECUTED_ALU0_GS\0"
   /* 141489 */ "XVE_INST_EXECUTED_ALU0_GS_UTILIZATION\0"
   /* 141527 */ "XVE_INST_EXECUTED_ALU0_HS\0"
   /* 141553 */ "XVE_INST_EXECUTED_ALU0_HS_UTILIZATION\0"
   /* 141591 */ "XVE_INST_EXECUTED_ALU0_MS\0"
   /* 141617 */ "XVE_INST_EXECUTED_ALU0_MS_UTILIZATION\0"
   /* 141655 */ "XVE_INST_EXECUTED_ALU0_PS\0"
   /* 141681 */ "XVE_INST_EXECUTED_ALU0_PS_UTILIZATION\0"
   /* 141719 */ "XVE_INST_EXECUTED_ALU0_RT_AHS\0"
   /* 141749 */ "XVE_INST_EXECUTED_ALU0_RT_AHS_UTILIZATION\0"
   /* 141791 */ "XVE_INST_EXECUTED_ALU0_RT_CHS\0"
   /* 141821 */ "XVE_INST_EXECUTED_ALU0_RT_CHS_UTILIZATION\0"
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   /* 141933 */ "XVE_INST_EXECUTED_ALU0_TS\0"
   /* 141959 */ "XVE_INST_EXECUTED_ALU0_TS_UTILIZATION\0"
   /* 141997 */ "XVE_INST_EXECUTED_ALU0_VS\0"
   /* 142023 */ "XVE_INST_EXECUTED_ALU0_VS_UTILIZATION\0"
   /* 142061 */ "XVE_INST_EXECUTED_ALU1_ALL\0"
   /* 142088 */ "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION\0"
   /* 142127 */ "XVE_INST_EXECUTED_ALU1_ASYNC_CS\0"
   /* 142159 */ "XVE_INST_EXECUTED_ALU1_ASYNC_CS_UTILIZATION\0"
   /* 142203 */ "XVE_INST_EXECUTED_ALU1_CS\0"
   /* 142229 */ "XVE_INST_EXECUTED_ALU1_CS_UTILIZATION\0"
   /* 142267 */ "XVE_INST_EXECUTED_ALU1_DS\0"
   /* 142293 */ "XVE_INST_EXECUTED_ALU1_DS_UTILIZATION\0"
   /* 142331 */ "XVE_INST_EXECUTED_ALU1_GS\0"
   /* 142357 */ "XVE_INST_EXECUTED_ALU1_GS_UTILIZATION\0"
   /* 142395 */ "XVE_INST_EXECUTED_ALU1_HS\0"
   /* 142421 */ "XVE_INST_EXECUTED_ALU1_HS_UTILIZATION\0"
   /* 142459 */ "XVE_INST_EXECUTED_ALU1_MS\0"
   /* 142485 */ "XVE_INST_EXECUTED_ALU1_MS_UTILIZATION\0"
   /* 142523 */ "XVE_INST_EXECUTED_ALU1_PS\0"
   /* 142549 */ "XVE_INST_EXECUTED_ALU1_PS_UTILIZATION\0"
   /* 142587 */ "XVE_INST_EXECUTED_ALU1_RT_AHS\0"
   /* 142617 */ "XVE_INST_EXECUTED_ALU1_RT_AHS_UTILIZATION\0"
   /* 142659 */ "XVE_INST_EXECUTED_ALU1_RT_CHS\0"
   /* 142689 */ "XVE_INST_EXECUTED_ALU1_RT_CHS_UTILIZATION\0"
   /* 142731 */ "XVE_INST_EXECUTED_ALU1_RT_MS\0"
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   /* 142801 */ "XVE_INST_EXECUTED_ALU1_TS\0"
   /* 142827 */ "XVE_INST_EXECUTED_ALU1_TS_UTILIZATION\0"
   /* 142865 */ "XVE_INST_EXECUTED_ALU1_VS\0"
   /* 142891 */ "XVE_INST_EXECUTED_ALU1_VS_UTILIZATION\0"
   /* 142929 */ "XVE_INST_EXECUTED_CONTROL_ALL\0"
   /* 142959 */ "XVE_INST_EXECUTED_CONTROL_ALL_UTILIZATION\0"
   /* 143001 */ "XVE_INST_EXECUTED_FP16\0"
   /* 143024 */ "XVE_INST_EXECUTED_FP16_UTILIZATION\0"
   /* 143059 */ "XVE_INST_EXECUTED_FP32\0"
   /* 143082 */ "XVE_INST_EXECUTED_FP32_UTILIZATION\0"
   /* 143117 */ "XVE_INST_EXECUTED_FP64\0"
   /* 143140 */ "XVE_INST_EXECUTED_FP64_UTILIZATION\0"
   /* 143175 */ "XVE_INST_EXECUTED_INT16\0"
   /* 143199 */ "XVE_INST_EXECUTED_INT16_UTILIZATION\0"
   /* 143235 */ "XVE_INST_EXECUTED_INT32\0"
   /* 143259 */ "XVE_INST_EXECUTED_INT32_UTILIZATION\0"
   /* 143295 */ "XVE_INST_EXECUTED_MATH\0"
   /* 143318 */ "XVE_INST_EXECUTED_MATH_UTILIZATION\0"
   /* 143353 */ "XVE_INST_EXECUTED_SEND_ALL\0"
   /* 143380 */ "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION\0"
   /* 143419 */ "XVE_INST_EXECUTED_SEND_ASYNC_CS\0"
   /* 143451 */ "XVE_INST_EXECUTED_SEND_ASYNC_CS_UTILIZATION\0"
   /* 143495 */ "XVE_INST_EXECUTED_SEND_CS\0"
   /* 143521 */ "XVE_INST_EXECUTED_SEND_CS_UTILIZATION\0"
   /* 143559 */ "XVE_INST_EXECUTED_SEND_DS\0"
   /* 143585 */ "XVE_INST_EXECUTED_SEND_DS_UTILIZATION\0"
   /* 143623 */ "XVE_INST_EXECUTED_SEND_GS\0"
   /* 143649 */ "XVE_INST_EXECUTED_SEND_GS_UTILIZATION\0"
   /* 143687 */ "XVE_INST_EXECUTED_SEND_HS\0"
   /* 143713 */ "XVE_INST_EXECUTED_SEND_HS_UTILIZATION\0"
   /* 143751 */ "XVE_INST_EXECUTED_SEND_MS\0"
   /* 143777 */ "XVE_INST_EXECUTED_SEND_MS_UTILIZATION\0"
   /* 143815 */ "XVE_INST_EXECUTED_SEND_PS\0"
   /* 143841 */ "XVE_INST_EXECUTED_SEND_PS_UTILIZATION\0"
   /* 143879 */ "XVE_INST_EXECUTED_SEND_RT_AHS\0"
   /* 143909 */ "XVE_INST_EXECUTED_SEND_RT_AHS_UTILIZATION\0"
   /* 143951 */ "XVE_INST_EXECUTED_SEND_RT_CHS\0"
   /* 143981 */ "XVE_INST_EXECUTED_SEND_RT_CHS_UTILIZATION\0"
   /* 144023 */ "XVE_INST_EXECUTED_SEND_RT_MS\0"
   /* 144052 */ "XVE_INST_EXECUTED_SEND_RT_MS_UTILIZATION\0"
   /* 144093 */ "XVE_INST_EXECUTED_SEND_TS\0"
   /* 144119 */ "XVE_INST_EXECUTED_SEND_TS_UTILIZATION\0"
   /* 144157 */ "XVE_INST_EXECUTED_SEND_VS\0"
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   /* 144221 */ "XVE_INST_EXECUTED_XMX_ALL\0"
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   /* 144285 */ "XVE_INST_EXECUTED_XMX_BF16\0"
   /* 144312 */ "XVE_INST_EXECUTED_XMX_BF16_UTILIZATION\0"
   /* 144351 */ "XVE_INST_EXECUTED_XMX_FP16\0"
   /* 144378 */ "XVE_INST_EXECUTED_XMX_FP16_UTILIZATION\0"
   /* 144417 */ "XVE_INST_EXECUTED_XMX_INT8\0"
   /* 144444 */ "XVE_INST_EXECUTED_XMX_INT8_UTILIZATION\0"
   /* 144483 */ "XVE_INST_ISSUED_ALL_XECORE0_XVE0\0"
   /* 144516 */ "XVE_INST_ISSUED_ALL_XECORE10_XVE0\0"
   /* 144550 */ "XVE_INST_ISSUED_ALL_XECORE11_XVE0\0"
   /* 144584 */ "XVE_INST_ISSUED_ALL_XECORE12_XVE0\0"
   /* 144618 */ "XVE_INST_ISSUED_ALL_XECORE13_XVE0\0"
   /* 144652 */ "XVE_INST_ISSUED_ALL_XECORE14_XVE0\0"
   /* 144686 */ "XVE_INST_ISSUED_ALL_XECORE15_XVE0\0"
   /* 144720 */ "XVE_INST_ISSUED_ALL_XECORE16_XVE0\0"
   /* 144754 */ "XVE_INST_ISSUED_ALL_XECORE17_XVE0\0"
   /* 144788 */ "XVE_INST_ISSUED_ALL_XECORE18_XVE0\0"
   /* 144822 */ "XVE_INST_ISSUED_ALL_XECORE19_XVE0\0"
   /* 144856 */ "XVE_INST_ISSUED_ALL_XECORE1_XVE0\0"
   /* 144889 */ "XVE_INST_ISSUED_ALL_XECORE20_XVE0\0"
   /* 144923 */ "XVE_INST_ISSUED_ALL_XECORE21_XVE0\0"
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   /* 144991 */ "XVE_INST_ISSUED_ALL_XECORE23_XVE0\0"
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   /* 145059 */ "XVE_INST_ISSUED_ALL_XECORE25_XVE0\0"
   /* 145093 */ "XVE_INST_ISSUED_ALL_XECORE26_XVE0\0"
   /* 145127 */ "XVE_INST_ISSUED_ALL_XECORE27_XVE0\0"
   /* 145161 */ "XVE_INST_ISSUED_ALL_XECORE28_XVE0\0"
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   /* 145229 */ "XVE_INST_ISSUED_ALL_XECORE2_XVE0\0"
   /* 145262 */ "XVE_INST_ISSUED_ALL_XECORE30_XVE0\0"
   /* 145296 */ "XVE_INST_ISSUED_ALL_XECORE31_XVE0\0"
   /* 145330 */ "XVE_INST_ISSUED_ALL_XECORE3_XVE0\0"
   /* 145363 */ "XVE_INST_ISSUED_ALL_XECORE4_XVE0\0"
   /* 145396 */ "XVE_INST_ISSUED_ALL_XECORE5_XVE0\0"
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   /* 145462 */ "XVE_INST_ISSUED_ALL_XECORE7_XVE0\0"
   /* 145495 */ "XVE_INST_ISSUED_ALL_XECORE8_XVE0\0"
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   /* 145661 */ "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE10\0"
   /* 145712 */ "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE11\0"
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   /* 146680 */ "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE29\0"
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   /* 147183 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0\0"
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   /* 147281 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE10\0"
   /* 147331 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE11\0"
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   /* 148080 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE25\0"
   /* 148130 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE26\0"
   /* 148180 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE27\0"
   /* 148230 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE28\0"
   /* 148280 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE29\0"
   /* 148330 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3\0"
   /* 148379 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE30\0"
   /* 148429 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE31\0"
   /* 148479 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4\0"
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   /* 148675 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE8\0"
   /* 148724 */ "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE9\0"
   /* 148773 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0\0"
   /* 148821 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1\0"
   /* 148869 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE10\0"
   /* 148918 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE11\0"
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   /* 149016 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE13\0"
   /* 149065 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE14\0"
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   /* 149163 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE16\0"
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   /* 149261 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE18\0"
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   /* 149359 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2\0"
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   /* 149652 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE25\0"
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   /* 149750 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE27\0"
   /* 149799 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE28\0"
   /* 149848 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE29\0"
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   /* 149945 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE30\0"
   /* 149994 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE31\0"
   /* 150043 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4\0"
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   /* 150139 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6\0"
   /* 150187 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7\0"
   /* 150235 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE8\0"
   /* 150283 */ "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE9\0"
   /* 150331 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0\0"
   /* 150383 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1\0"
   /* 150435 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE10\0"
   /* 150488 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE11\0"
   /* 150541 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE12\0"
   /* 150594 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE13\0"
   /* 150647 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE14\0"
   /* 150700 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE15\0"
   /* 150753 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE16\0"
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   /* 150912 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE19\0"
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   /* 151123 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE22\0"
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   /* 151229 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE24\0"
   /* 151282 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE25\0"
   /* 151335 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE26\0"
   /* 151388 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE27\0"
   /* 151441 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE28\0"
   /* 151494 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE29\0"
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   /* 151599 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE30\0"
   /* 151652 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE31\0"
   /* 151705 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4\0"
   /* 151757 */ "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5\0"
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   /* 155402 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE11_XVE0\0"
   /* 155441 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE12_XVE0\0"
   /* 155480 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE13_XVE0\0"
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   /* 155947 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE24_XVE0\0"
   /* 155986 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE25_XVE0\0"
   /* 156025 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE26_XVE0\0"
   /* 156064 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE27_XVE0\0"
   /* 156103 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE28_XVE0\0"
   /* 156142 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE29_XVE0\0"
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   /* 156219 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE30_XVE0\0"
   /* 156258 */ "XVE_MULTIPLE_PIPE_ACTIVE_XECORE31_XVE0\0"
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   /* 160757 */ "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE9\0"
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   /* 160863 */ "XVE_SLM_READ_MESSAGE_COUNT_XECORE10\0"
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   /* 162709 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE28\0"
   /* 162746 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE29\0"
   /* 162783 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3\0"
   /* 162819 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE30\0"
   /* 162856 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE31\0"
   /* 162893 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4\0"
   /* 162929 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5\0"
   /* 162965 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6\0"
   /* 163001 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7\0"
   /* 163037 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE8\0"
   /* 163073 */ "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE9\0"
   /* 163109 */ "XVE_STALL\0"
   /* 163119 */ "XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0\0"
   /* 163156 */ "XVE_STALL_ALUWR_XECORE10_XVE0_THREAD0\0"
   /* 163194 */ "XVE_STALL_ALUWR_XECORE11_XVE0_THREAD0\0"
   /* 163232 */ "XVE_STALL_ALUWR_XECORE12_XVE0_THREAD0\0"
   /* 163270 */ "XVE_STALL_ALUWR_XECORE13_XVE0_THREAD0\0"
   /* 163308 */ "XVE_STALL_ALUWR_XECORE14_XVE0_THREAD0\0"
   /* 163346 */ "XVE_STALL_ALUWR_XECORE15_XVE0_THREAD0\0"
   /* 163384 */ "XVE_STALL_ALUWR_XECORE16_XVE0_THREAD0\0"
   /* 163422 */ "XVE_STALL_ALUWR_XECORE17_XVE0_THREAD0\0"
   /* 163460 */ "XVE_STALL_ALUWR_XECORE18_XVE0_THREAD0\0"
   /* 163498 */ "XVE_STALL_ALUWR_XECORE19_XVE0_THREAD0\0"
   /* 163536 */ "XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0\0"
   /* 163573 */ "XVE_STALL_ALUWR_XECORE20_XVE0_THREAD0\0"
   /* 163611 */ "XVE_STALL_ALUWR_XECORE21_XVE0_THREAD0\0"
   /* 163649 */ "XVE_STALL_ALUWR_XECORE22_XVE0_THREAD0\0"
   /* 163687 */ "XVE_STALL_ALUWR_XECORE23_XVE0_THREAD0\0"
   /* 163725 */ "XVE_STALL_ALUWR_XECORE24_XVE0_THREAD0\0"
   /* 163763 */ "XVE_STALL_ALUWR_XECORE25_XVE0_THREAD0\0"
   /* 163801 */ "XVE_STALL_ALUWR_XECORE26_XVE0_THREAD0\0"
   /* 163839 */ "XVE_STALL_ALUWR_XECORE27_XVE0_THREAD0\0"
   /* 163877 */ "XVE_STALL_ALUWR_XECORE28_XVE0_THREAD0\0"
   /* 163915 */ "XVE_STALL_ALUWR_XECORE29_XVE0_THREAD0\0"
   /* 163953 */ "XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0\0"
   /* 163990 */ "XVE_STALL_ALUWR_XECORE30_XVE0_THREAD0\0"
   /* 164028 */ "XVE_STALL_ALUWR_XECORE31_XVE0_THREAD0\0"
   /* 164066 */ "XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0\0"
   /* 164103 */ "XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0\0"
   /* 164140 */ "XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0\0"
   /* 164177 */ "XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0\0"
   /* 164214 */ "XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0\0"
   /* 164251 */ "XVE_STALL_ALUWR_XECORE8_XVE0_THREAD0\0"
   /* 164288 */ "XVE_STALL_ALUWR_XECORE9_XVE0_THREAD0\0"
   /* 164325 */ "XVE_STALL_ASYNC_CS\0"
   /* 164344 */ "XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0\0"
   /* 164383 */ "XVE_STALL_BARRIER_XECORE10_XVE0_THREAD0\0"
   /* 164423 */ "XVE_STALL_BARRIER_XECORE11_XVE0_THREAD0\0"
   /* 164463 */ "XVE_STALL_BARRIER_XECORE12_XVE0_THREAD0\0"
   /* 164503 */ "XVE_STALL_BARRIER_XECORE13_XVE0_THREAD0\0"
   /* 164543 */ "XVE_STALL_BARRIER_XECORE14_XVE0_THREAD0\0"
   /* 164583 */ "XVE_STALL_BARRIER_XECORE15_XVE0_THREAD0\0"
   /* 164623 */ "XVE_STALL_BARRIER_XECORE16_XVE0_THREAD0\0"
   /* 164663 */ "XVE_STALL_BARRIER_XECORE17_XVE0_THREAD0\0"
   /* 164703 */ "XVE_STALL_BARRIER_XECORE18_XVE0_THREAD0\0"
   /* 164743 */ "XVE_STALL_BARRIER_XECORE19_XVE0_THREAD0\0"
   /* 164783 */ "XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0\0"
   /* 164822 */ "XVE_STALL_BARRIER_XECORE20_XVE0_THREAD0\0"
   /* 164862 */ "XVE_STALL_BARRIER_XECORE21_XVE0_THREAD0\0"
   /* 164902 */ "XVE_STALL_BARRIER_XECORE22_XVE0_THREAD0\0"
   /* 164942 */ "XVE_STALL_BARRIER_XECORE23_XVE0_THREAD0\0"
   /* 164982 */ "XVE_STALL_BARRIER_XECORE24_XVE0_THREAD0\0"
   /* 165022 */ "XVE_STALL_BARRIER_XECORE25_XVE0_THREAD0\0"
   /* 165062 */ "XVE_STALL_BARRIER_XECORE26_XVE0_THREAD0\0"
   /* 165102 */ "XVE_STALL_BARRIER_XECORE27_XVE0_THREAD0\0"
   /* 165142 */ "XVE_STALL_BARRIER_XECORE28_XVE0_THREAD0\0"
   /* 165182 */ "XVE_STALL_BARRIER_XECORE29_XVE0_THREAD0\0"
   /* 165222 */ "XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0\0"
   /* 165261 */ "XVE_STALL_BARRIER_XECORE30_XVE0_THREAD0\0"
   /* 165301 */ "XVE_STALL_BARRIER_XECORE31_XVE0_THREAD0\0"
   /* 165341 */ "XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0\0"
   /* 165380 */ "XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0\0"
   /* 165419 */ "XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0\0"
   /* 165458 */ "XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0\0"
   /* 165497 */ "XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0\0"
   /* 165536 */ "XVE_STALL_BARRIER_XECORE8_XVE0_THREAD0\0"
   /* 165575 */ "XVE_STALL_BARRIER_XECORE9_XVE0_THREAD0\0"
   /* 165614 */ "XVE_STALL_CONTROL_XECORE0_XVE0_THREAD0\0"
   /* 165653 */ "XVE_STALL_CONTROL_XECORE1_XVE0_THREAD0\0"
   /* 165692 */ "XVE_STALL_CONTROL_XECORE2_XVE0_THREAD0\0"
   /* 165731 */ "XVE_STALL_CONTROL_XECORE3_XVE0_THREAD0\0"
   /* 165770 */ "XVE_STALL_CONTROL_XECORE4_XVE0_THREAD0\0"
   /* 165809 */ "XVE_STALL_CONTROL_XECORE5_XVE0_THREAD0\0"
   /* 165848 */ "XVE_STALL_CONTROL_XECORE6_XVE0_THREAD0\0"
   /* 165887 */ "XVE_STALL_CONTROL_XECORE7_XVE0_THREAD0\0"
   /* 165926 */ "XVE_STALL_CS\0"
   /* 165939 */ "XVE_STALL_CYCLES\0"
   /* 165956 */ "XVE_STALL_CYCLES_ASYNC_CS\0"
   /* 165982 */ "XVE_STALL_CYCLES_CS\0"
   /* 166002 */ "XVE_STALL_CYCLES_DS\0"
   /* 166022 */ "XVE_STALL_CYCLES_GS\0"
   /* 166042 */ "XVE_STALL_CYCLES_HS\0"
   /* 166062 */ "XVE_STALL_CYCLES_MS\0"
   /* 166082 */ "XVE_STALL_CYCLES_PS\0"
   /* 166102 */ "XVE_STALL_CYCLES_RT\0"
   /* 166122 */ "XVE_STALL_CYCLES_TS\0"
   /* 166142 */ "XVE_STALL_CYCLES_VS\0"
   /* 166162 */ "XVE_STALL_DS\0"
   /* 166175 */ "XVE_STALL_GS\0"
   /* 166188 */ "XVE_STALL_HS\0"
   /* 166201 */ "XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0\0"
   /* 166242 */ "XVE_STALL_INSTFETCH_XECORE10_XVE0_THREAD0\0"
   /* 166284 */ "XVE_STALL_INSTFETCH_XECORE11_XVE0_THREAD0\0"
   /* 166326 */ "XVE_STALL_INSTFETCH_XECORE12_XVE0_THREAD0\0"
   /* 166368 */ "XVE_STALL_INSTFETCH_XECORE13_XVE0_THREAD0\0"
   /* 166410 */ "XVE_STALL_INSTFETCH_XECORE14_XVE0_THREAD0\0"
   /* 166452 */ "XVE_STALL_INSTFETCH_XECORE15_XVE0_THREAD0\0"
   /* 166494 */ "XVE_STALL_INSTFETCH_XECORE16_XVE0_THREAD0\0"
   /* 166536 */ "XVE_STALL_INSTFETCH_XECORE17_XVE0_THREAD0\0"
   /* 166578 */ "XVE_STALL_INSTFETCH_XECORE18_XVE0_THREAD0\0"
   /* 166620 */ "XVE_STALL_INSTFETCH_XECORE19_XVE0_THREAD0\0"
   /* 166662 */ "XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0\0"
   /* 166703 */ "XVE_STALL_INSTFETCH_XECORE20_XVE0_THREAD0\0"
   /* 166745 */ "XVE_STALL_INSTFETCH_XECORE21_XVE0_THREAD0\0"
   /* 166787 */ "XVE_STALL_INSTFETCH_XECORE22_XVE0_THREAD0\0"
   /* 166829 */ "XVE_STALL_INSTFETCH_XECORE23_XVE0_THREAD0\0"
   /* 166871 */ "XVE_STALL_INSTFETCH_XECORE24_XVE0_THREAD0\0"
   /* 166913 */ "XVE_STALL_INSTFETCH_XECORE25_XVE0_THREAD0\0"
   /* 166955 */ "XVE_STALL_INSTFETCH_XECORE26_XVE0_THREAD0\0"
   /* 166997 */ "XVE_STALL_INSTFETCH_XECORE27_XVE0_THREAD0\0"
   /* 167039 */ "XVE_STALL_INSTFETCH_XECORE28_XVE0_THREAD0\0"
   /* 167081 */ "XVE_STALL_INSTFETCH_XECORE29_XVE0_THREAD0\0"
   /* 167123 */ "XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0\0"
   /* 167164 */ "XVE_STALL_INSTFETCH_XECORE30_XVE0_THREAD0\0"
   /* 167206 */ "XVE_STALL_INSTFETCH_XECORE31_XVE0_THREAD0\0"
   /* 167248 */ "XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0\0"
   /* 167289 */ "XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0\0"
   /* 167330 */ "XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0\0"
   /* 167371 */ "XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0\0"
   /* 167412 */ "XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0\0"
   /* 167453 */ "XVE_STALL_INSTFETCH_XECORE8_XVE0_THREAD0\0"
   /* 167494 */ "XVE_STALL_INSTFETCH_XECORE9_XVE0_THREAD0\0"
   /* 167535 */ "XVE_STALL_MS\0"
   /* 167548 */ "XVE_STALL_OTHER_XECORE0_XVE0_THREAD0\0"
   /* 167585 */ "XVE_STALL_OTHER_XECORE10_XVE0_THREAD0\0"
   /* 167623 */ "XVE_STALL_OTHER_XECORE11_XVE0_THREAD0\0"
   /* 167661 */ "XVE_STALL_OTHER_XECORE12_XVE0_THREAD0\0"
   /* 167699 */ "XVE_STALL_OTHER_XECORE13_XVE0_THREAD0\0"
   /* 167737 */ "XVE_STALL_OTHER_XECORE14_XVE0_THREAD0\0"
   /* 167775 */ "XVE_STALL_OTHER_XECORE15_XVE0_THREAD0\0"
   /* 167813 */ "XVE_STALL_OTHER_XECORE16_XVE0_THREAD0\0"
   /* 167851 */ "XVE_STALL_OTHER_XECORE17_XVE0_THREAD0\0"
   /* 167889 */ "XVE_STALL_OTHER_XECORE18_XVE0_THREAD0\0"
   /* 167927 */ "XVE_STALL_OTHER_XECORE19_XVE0_THREAD0\0"
   /* 167965 */ "XVE_STALL_OTHER_XECORE1_XVE0_THREAD0\0"
   /* 168002 */ "XVE_STALL_OTHER_XECORE20_XVE0_THREAD0\0"
   /* 168040 */ "XVE_STALL_OTHER_XECORE21_XVE0_THREAD0\0"
   /* 168078 */ "XVE_STALL_OTHER_XECORE22_XVE0_THREAD0\0"
   /* 168116 */ "XVE_STALL_OTHER_XECORE23_XVE0_THREAD0\0"
   /* 168154 */ "XVE_STALL_OTHER_XECORE24_XVE0_THREAD0\0"
   /* 168192 */ "XVE_STALL_OTHER_XECORE25_XVE0_THREAD0\0"
   /* 168230 */ "XVE_STALL_OTHER_XECORE26_XVE0_THREAD0\0"
   /* 168268 */ "XVE_STALL_OTHER_XECORE27_XVE0_THREAD0\0"
   /* 168306 */ "XVE_STALL_OTHER_XECORE28_XVE0_THREAD0\0"
   /* 168344 */ "XVE_STALL_OTHER_XECORE29_XVE0_THREAD0\0"
   /* 168382 */ "XVE_STALL_OTHER_XECORE2_XVE0_THREAD0\0"
   /* 168419 */ "XVE_STALL_OTHER_XECORE30_XVE0_THREAD0\0"
   /* 168457 */ "XVE_STALL_OTHER_XECORE31_XVE0_THREAD0\0"
   /* 168495 */ "XVE_STALL_OTHER_XECORE3_XVE0_THREAD0\0"
   /* 168532 */ "XVE_STALL_OTHER_XECORE4_XVE0_THREAD0\0"
   /* 168569 */ "XVE_STALL_OTHER_XECORE5_XVE0_THREAD0\0"
   /* 168606 */ "XVE_STALL_OTHER_XECORE6_XVE0_THREAD0\0"
   /* 168643 */ "XVE_STALL_OTHER_XECORE7_XVE0_THREAD0\0"
   /* 168680 */ "XVE_STALL_OTHER_XECORE8_XVE0_THREAD0\0"
   /* 168717 */ "XVE_STALL_OTHER_XECORE9_XVE0_THREAD0\0"
   /* 168754 */ "XVE_STALL_PIPESTALL_XECORE0_XVE0\0"
   /* 168787 */ "XVE_STALL_PIPESTALL_XECORE1_XVE0\0"
   /* 168820 */ "XVE_STALL_PIPESTALL_XECORE2_XVE0\0"
   /* 168853 */ "XVE_STALL_PIPESTALL_XECORE3_XVE0\0"
   /* 168886 */ "XVE_STALL_PIPESTALL_XECORE4_XVE0\0"
   /* 168919 */ "XVE_STALL_PIPESTALL_XECORE5_XVE0\0"
   /* 168952 */ "XVE_STALL_PIPESTALL_XECORE6_XVE0\0"
   /* 168985 */ "XVE_STALL_PIPESTALL_XECORE7_XVE0\0"
   /* 169018 */ "XVE_STALL_PS\0"
   /* 169031 */ "XVE_STALL_RT\0"
   /* 169044 */ "XVE_STALL_SBID_XECORE0_XVE0_THREAD0\0"
   /* 169080 */ "XVE_STALL_SBID_XECORE10_XVE0_THREAD0\0"
   /* 169117 */ "XVE_STALL_SBID_XECORE11_XVE0_THREAD0\0"
   /* 169154 */ "XVE_STALL_SBID_XECORE12_XVE0_THREAD0\0"
   /* 169191 */ "XVE_STALL_SBID_XECORE13_XVE0_THREAD0\0"
   /* 169228 */ "XVE_STALL_SBID_XECORE14_XVE0_THREAD0\0"
   /* 169265 */ "XVE_STALL_SBID_XECORE15_XVE0_THREAD0\0"
   /* 169302 */ "XVE_STALL_SBID_XECORE16_XVE0_THREAD0\0"
   /* 169339 */ "XVE_STALL_SBID_XECORE17_XVE0_THREAD0\0"
   /* 169376 */ "XVE_STALL_SBID_XECORE18_XVE0_THREAD0\0"
   /* 169413 */ "XVE_STALL_SBID_XECORE19_XVE0_THREAD0\0"
   /* 169450 */ "XVE_STALL_SBID_XECORE1_XVE0_THREAD0\0"
   /* 169486 */ "XVE_STALL_SBID_XECORE20_XVE0_THREAD0\0"
   /* 169523 */ "XVE_STALL_SBID_XECORE21_XVE0_THREAD0\0"
   /* 169560 */ "XVE_STALL_SBID_XECORE22_XVE0_THREAD0\0"
   /* 169597 */ "XVE_STALL_SBID_XECORE23_XVE0_THREAD0\0"
   /* 169634 */ "XVE_STALL_SBID_XECORE24_XVE0_THREAD0\0"
   /* 169671 */ "XVE_STALL_SBID_XECORE25_XVE0_THREAD0\0"
   /* 169708 */ "XVE_STALL_SBID_XECORE26_XVE0_THREAD0\0"
   /* 169745 */ "XVE_STALL_SBID_XECORE27_XVE0_THREAD0\0"
   /* 169782 */ "XVE_STALL_SBID_XECORE28_XVE0_THREAD0\0"
   /* 169819 */ "XVE_STALL_SBID_XECORE29_XVE0_THREAD0\0"
   /* 169856 */ "XVE_STALL_SBID_XECORE2_XVE0_THREAD0\0"
   /* 169892 */ "XVE_STALL_SBID_XECORE30_XVE0_THREAD0\0"
   /* 169929 */ "XVE_STALL_SBID_XECORE31_XVE0_THREAD0\0"
   /* 169966 */ "XVE_STALL_SBID_XECORE3_XVE0_THREAD0\0"
   /* 170002 */ "XVE_STALL_SBID_XECORE4_XVE0_THREAD0\0"
   /* 170038 */ "XVE_STALL_SBID_XECORE5_XVE0_THREAD0\0"
   /* 170074 */ "XVE_STALL_SBID_XECORE6_XVE0_THREAD0\0"
   /* 170110 */ "XVE_STALL_SBID_XECORE7_XVE0_THREAD0\0"
   /* 170146 */ "XVE_STALL_SBID_XECORE8_XVE0_THREAD0\0"
   /* 170182 */ "XVE_STALL_SBID_XECORE9_XVE0_THREAD0\0"
   /* 170218 */ "XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0\0"
   /* 170256 */ "XVE_STALL_SENDWR_XECORE10_XVE0_THREAD0\0"
   /* 170295 */ "XVE_STALL_SENDWR_XECORE11_XVE0_THREAD0\0"
   /* 170334 */ "XVE_STALL_SENDWR_XECORE12_XVE0_THREAD0\0"
   /* 170373 */ "XVE_STALL_SENDWR_XECORE13_XVE0_THREAD0\0"
   /* 170412 */ "XVE_STALL_SENDWR_XECORE14_XVE0_THREAD0\0"
   /* 170451 */ "XVE_STALL_SENDWR_XECORE15_XVE0_THREAD0\0"
   /* 170490 */ "XVE_STALL_SENDWR_XECORE16_XVE0_THREAD0\0"
   /* 170529 */ "XVE_STALL_SENDWR_XECORE17_XVE0_THREAD0\0"
   /* 170568 */ "XVE_STALL_SENDWR_XECORE18_XVE0_THREAD0\0"
   /* 170607 */ "XVE_STALL_SENDWR_XECORE19_XVE0_THREAD0\0"
   /* 170646 */ "XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0\0"
   /* 170684 */ "XVE_STALL_SENDWR_XECORE20_XVE0_THREAD0\0"
   /* 170723 */ "XVE_STALL_SENDWR_XECORE21_XVE0_THREAD0\0"
   /* 170762 */ "XVE_STALL_SENDWR_XECORE22_XVE0_THREAD0\0"
   /* 170801 */ "XVE_STALL_SENDWR_XECORE23_XVE0_THREAD0\0"
   /* 170840 */ "XVE_STALL_SENDWR_XECORE24_XVE0_THREAD0\0"
   /* 170879 */ "XVE_STALL_SENDWR_XECORE25_XVE0_THREAD0\0"
   /* 170918 */ "XVE_STALL_SENDWR_XECORE26_XVE0_THREAD0\0"
   /* 170957 */ "XVE_STALL_SENDWR_XECORE27_XVE0_THREAD0\0"
   /* 170996 */ "XVE_STALL_SENDWR_XECORE28_XVE0_THREAD0\0"
   /* 171035 */ "XVE_STALL_SENDWR_XECORE29_XVE0_THREAD0\0"
   /* 171074 */ "XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0\0"
   /* 171112 */ "XVE_STALL_SENDWR_XECORE30_XVE0_THREAD0\0"
   /* 171151 */ "XVE_STALL_SENDWR_XECORE31_XVE0_THREAD0\0"
   /* 171190 */ "XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0\0"
   /* 171228 */ "XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0\0"
   /* 171266 */ "XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0\0"
   /* 171304 */ "XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0\0"
   /* 171342 */ "XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0\0"
   /* 171380 */ "XVE_STALL_SENDWR_XECORE8_XVE0_THREAD0\0"
   /* 171418 */ "XVE_STALL_SENDWR_XECORE9_XVE0_THREAD0\0"
   /* 171456 */ "XVE_STALL_TS\0"
   /* 171469 */ "XVE_STALL_VS\0"
   /* 171482 */ "XVE_THREADS_OCCUPANCY_ALL\0"
   /* 171508 */ "XVE_THREADS_OCCUPANCY_CYCLES_ALL\0"
   /* 171541 */ "XmxActive\0"
   /* 171551 */ "XveActive\0"
   /* 171561 */ "XveAvgIpcRate\0"
   /* 171575 */ "XveFpuEmActive\0"
   /* 171590 */ "XveFpuFlt16\0"
   /* 171602 */ "XveFpuFlt32\0"
   /* 171614 */ "XveFpuFlt64\0"
   /* 171626 */ "XveFpuXmxActive\0"
   /* 171642 */ "XveStall\0"
   /* 171651 */ "XveThreadOccupancy\0"
   /* 171670 */ "Z_L3_ACCESS_L3BANK0\0"
   /* 171690 */ "Z_L3_ACCESS_L3BANK1\0"
   /* 171710 */ "Z_L3_ACCESS_L3BANK2\0"
   /* 171730 */ "Z_L3_ACCESS_L3BANK3\0"
   /* 171750 */ "Z_L3_ACCESS_L3BANK4\0"
   /* 171770 */ "Z_L3_ACCESS_L3BANK5\0"
   /* 171790 */ "Z_L3_ACCESS_L3BANK6\0"
   /* 171810 */ "Z_L3_ACCESS_L3BANK7\0"
   /* 171830 */ "Z_L3_HIT_L3BANK0\0"
   /* 171847 */ "Z_L3_HIT_L3BANK1\0"
   /* 171864 */ "Z_L3_HIT_L3BANK10\0"
   /* 171882 */ "Z_L3_HIT_L3BANK11\0"
   /* 171900 */ "Z_L3_HIT_L3BANK12\0"
   /* 171918 */ "Z_L3_HIT_L3BANK13\0"
   /* 171936 */ "Z_L3_HIT_L3BANK14\0"
   /* 171954 */ "Z_L3_HIT_L3BANK15\0"
   /* 171972 */ "Z_L3_HIT_L3BANK16\0"
   /* 171990 */ "Z_L3_HIT_L3BANK17\0"
   /* 172008 */ "Z_L3_HIT_L3BANK18\0"
   /* 172026 */ "Z_L3_HIT_L3BANK19\0"
   /* 172044 */ "Z_L3_HIT_L3BANK2\0"
   /* 172061 */ "Z_L3_HIT_L3BANK20\0"
   /* 172079 */ "Z_L3_HIT_L3BANK21\0"
   /* 172097 */ "Z_L3_HIT_L3BANK22\0"
   /* 172115 */ "Z_L3_HIT_L3BANK23\0"
   /* 172133 */ "Z_L3_HIT_L3BANK24\0"
   /* 172151 */ "Z_L3_HIT_L3BANK25\0"
   /* 172169 */ "Z_L3_HIT_L3BANK26\0"
   /* 172187 */ "Z_L3_HIT_L3BANK27\0"
   /* 172205 */ "Z_L3_HIT_L3BANK28\0"
   /* 172223 */ "Z_L3_HIT_L3BANK29\0"
   /* 172241 */ "Z_L3_HIT_L3BANK3\0"
   /* 172258 */ "Z_L3_HIT_L3BANK30\0"
   /* 172276 */ "Z_L3_HIT_L3BANK31\0"
   /* 172294 */ "Z_L3_HIT_L3BANK4\0"
   /* 172311 */ "Z_L3_HIT_L3BANK5\0"
   /* 172328 */ "Z_L3_HIT_L3BANK6\0"
   /* 172345 */ "Z_L3_HIT_L3BANK7\0"
   /* 172362 */ "Z_L3_HIT_L3BANK8\0"
   /* 172379 */ "Z_L3_HIT_L3BANK9\0"
};

static const char category[] = {
   /* 0 */ "3D Pipe/Clipper\0"
   /* 16 */ "3D Pipe/Domain Shader\0"
   /* 38 */ "3D Pipe/Fragment Shader\0"
   /* 62 */ "3D Pipe/Geometry Shader\0"
   /* 86 */ "3D Pipe/Hull Shader\0"
   /* 106 */ "3D Pipe/Input Assembler\0"
   /* 130 */ "3D Pipe/Output Merger\0"
   /* 152 */ "3D Pipe/Rasterizer\0"
   /* 171 */ "3D Pipe/Rasterizer/Barycentric Calc\0"
   /* 207 */ "3D Pipe/Rasterizer/Early Depth Test\0"
   /* 243 */ "3D Pipe/Rasterizer/Hi-Depth Test\0"
   /* 276 */ "3D Pipe/Rasterizer/Strip-Fans\0"
   /* 306 */ "3D Pipe/Stream Output\0"
   /* 328 */ "3D Pipe/Vertex Shader\0"
   /* 350 */ "AMFS\0"
   /* 355 */ "ColorPipe\0"
   /* 365 */ "Dataport\0"
   /* 374 */ "DepthPipe\0"
   /* 384 */ "EU Array\0"
   /* 393 */ "EU Array/Barrier\0"
   /* 410 */ "EU Array/Compute Shader\0"
   /* 434 */ "EU Array/Control Shader\0"
   /* 458 */ "EU Array/Domain Shader\0"
   /* 481 */ "EU Array/Evaluation Shader\0"
   /* 508 */ "EU Array/Fragment Shader\0"
   /* 533 */ "EU Array/Geometry Shader\0"
   /* 558 */ "EU Array/Hull Shader\0"
   /* 579 */ "EU Array/Pipes\0"
   /* 594 */ "EU Array/Pipes/Instructions\0"
   /* 622 */ "EU Array/Pixel Shader\0"
   /* 644 */ "EU Array/Vertex Shader\0"
   /* 667 */ "FrontEnd\0"
   /* 676 */ "GPU\0"
   /* 680 */ "GPU/3D Pipe\0"
   /* 692 */ "GPU/3D Pipe/Strip-Fans\0"
   /* 715 */ "GPU/Data Port\0"
   /* 729 */ "GPU/Rasterizer\0"
   /* 744 */ "GPU/Rasterizer/Early Depth Test\0"
   /* 776 */ "GPU/Sampler\0"
   /* 788 */ "GPU/Stencil Cache\0"
   /* 806 */ "GPU/Thread Dispatcher\0"
   /* 828 */ "GTI\0"
   /* 832 */ "GTI/3D Pipe\0"
   /* 844 */ "GTI/3D Pipe/Command Streamer\0"
   /* 873 */ "GTI/3D Pipe/Resource Streamer\0"
   /* 903 */ "GTI/3D Pipe/Stream Output\0"
   /* 929 */ "GTI/3D Pipe/Vertex Fetch\0"
   /* 954 */ "GTI/Color Cache\0"
   /* 970 */ "GTI/Depth Cache\0"
   /* 986 */ "GTI/L3\0"
   /* 993 */ "Geometry\0"
   /* 1002 */ "L1Cache\0"
   /* 1010 */ "L3\0"
   /* 1013 */ "L3/Data Port\0"
   /* 1026 */ "L3/Data Port/Atomics\0"
   /* 1047 */ "L3/Data Port/SLM\0"
   /* 1064 */ "L3/IC\0"
   /* 1070 */ "L3/Sampler\0"
   /* 1081 */ "L3/TAG\0"
   /* 1088 */ "L3Cache\0"
   /* 1096 */ "LLC\0"
   /* 1100 */ "Media\0"
   /* 1106 */ "Memory\0"
   /* 1113 */ "Rasterizer\0"
   /* 1124 */ "RayTracing\0"
   /* 1135 */ "Sampler\0"
   /* 1143 */ "Sampler/Sampler Cache\0"
   /* 1165 */ "Sampler/Sampler Input\0"
   /* 1187 */ "Test\0"
   /* 1192 */ "ThreadDispatcher\0"
   /* 1209 */ "URB\0"
   /* 1213 */ "VME Pipe\0"
   /* 1222 */ "VectorEngine\0"
};

/* Render Metrics Basic set :: GPU Time Elapsed */
static uint64_t
hsw__render_basic__gpu_time__read(UNUSED struct intel_perf_config *perf,
                                  const struct intel_perf_query_info *query,
                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_TIME 0 READ 1000000000 UMUL $GpuTimestampFrequency UDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_time_offset + 0];
   uint64_t tmp1 = tmp0 * 1000000000;
   uint64_t tmp2 = tmp1;
   uint64_t tmp3 = perf->devinfo.timestamp_frequency;
   uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: GPU Core Clocks */
static uint64_t
hsw__render_basic__gpu_core_clocks__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 2 READ */
   uint64_t tmp0 = results->accumulator[query->c_offset + 2];

   return tmp0;
}

/* Render Metrics Basic set :: AVG GPU Core Frequency */
static uint64_t
hsw__render_basic__avg_gpu_core_frequency__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */
   uint64_t tmp0 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * 1000000000;
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__gpu_time__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: AVG GPU Core Frequency */
static uint64_t
hsw__render_basic__avg_gpu_core_frequency__max(struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuMaxFrequency */

   return perf->sys_vars.gt_max_freq;
}

/* Render Metrics Basic set :: VS Threads Dispatched */
static uint64_t
hsw__render_basic__vs_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 5 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 5];

   return tmp0;
}

/* Render Metrics Basic set :: TCS Threads Dispatched */
static uint64_t
hsw__render_basic__hs_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 10 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 10];

   return tmp0;
}

/* Render Metrics Basic set :: TES Threads Dispatched */
static uint64_t
hsw__render_basic__ds_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 15 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 15];

   return tmp0;
}

/* Render Metrics Basic set :: GS Threads Dispatched */
static uint64_t
hsw__render_basic__gs_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 25 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 25];

   return tmp0;
}

/* Render Metrics Basic set :: FS Threads Dispatched */
static uint64_t
hsw__render_basic__ps_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 30 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 30];

   return tmp0;
}

/* Render Metrics Basic set :: CS Threads Dispatched */
static uint64_t
hsw__render_basic__cs_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 20 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 20];

   return tmp0;
}

/* Render Metrics Basic set :: GPU Busy */
static float
hsw__render_basic__gpu_busy__read(UNUSED struct intel_perf_config *perf,
                                  const struct intel_perf_query_info *query,
                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: A 41 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 41];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: EU Active */
static float
hsw__render_basic__eu_active__read(UNUSED struct intel_perf_config *perf,
                                   const struct intel_perf_query_info *query,
                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: A 0 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 0];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: EU Stall */
static float
hsw__render_basic__eu_stall__read(UNUSED struct intel_perf_config *perf,
                                  const struct intel_perf_query_info *query,
                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: A 1 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 1];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: VS EU Active */
static float
hsw__render_basic__vs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 2 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 2];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: VS AVG Active per Thread */
static uint64_t
hsw__render_basic__vs_eu_active_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: A 2 READ $VsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 2];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__vs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: VS AVG Stall per Thread */
static uint64_t
hsw__render_basic__vs_eu_stall_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: A 3 READ $VsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 3];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__vs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: VS EU Stall */
static float
hsw__render_basic__vs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 3 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 3];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: TCS EU Active */
static float
hsw__render_basic__hs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: TCS AVG Active per Thread */
static uint64_t
hsw__render_basic__hs_eu_active_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ $HsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__hs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: TCS AVG Stall per Thread */
static uint64_t
hsw__render_basic__hs_eu_stall_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: A 8 READ $HsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 8];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__hs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: TCS EU Stall */
static float
hsw__render_basic__hs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 8];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: TES EU Active */
static float
hsw__render_basic__ds_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 12];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: TES AVG Active per Thread */
static uint64_t
hsw__render_basic__ds_eu_active_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: A 12 READ $DsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 12];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__ds_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: TES AVG Stall per Thread */
static uint64_t
hsw__render_basic__ds_eu_stall_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: A 13 READ $DsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 13];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__ds_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: TES EU Stall */
static float
hsw__render_basic__ds_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 13];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: GS EU Active */
static float
hsw__render_basic__gs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 22 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 22];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: GS AVG Active per Thread */
static uint64_t
hsw__render_basic__gs_eu_active_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: A 22 READ $GsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 22];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__gs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: GS AVG Stall per Thread */
static uint64_t
hsw__render_basic__gs_eu_stall_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: A 23 READ $GsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 23];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__gs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: GS EU Stall */
static float
hsw__render_basic__gs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 23 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 23];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: CS EU Active */
static float
hsw__render_basic__cs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: CS AVG Active per Thread */
static uint64_t
hsw__render_basic__cs_eu_active_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: A 17 READ $CsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__cs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: CS AVG Stall per Thread */
static uint64_t
hsw__render_basic__cs_eu_stall_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: A 18 READ $CsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 18];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__cs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: CS EU Stall */
static float
hsw__render_basic__cs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 18];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: FS EU Active */
static float
hsw__render_basic__ps_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 27 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 27];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: FS AVG Active per Thread */
static uint64_t
hsw__render_basic__ps_eu_active_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: A 27 READ $PsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 27];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__ps_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: FS AVG Stall per Thread */
static uint64_t
hsw__render_basic__ps_eu_stall_per_thread__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: A 28 READ $PsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 28];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__render_basic__ps_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: FS EU Stall */
static float
hsw__render_basic__ps_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 28 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 28];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: Sampler 0 Busy */
static float
hsw__render_basic__sampler0_busy__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: Sampler 1 Busy */
static float
hsw__render_basic__sampler1_busy__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: Samplers Busy */
static float
hsw__render_basic__samplers_busy__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ  B 1 READ UADD $GpuCoreClocks FDIV 2 FDIV 100 FMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   double tmp6 = tmp5;
   double tmp7 = 2;
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;
   double tmp9 = tmp8 * 100;

   return tmp9;
}

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
static float
hsw__render_basic__sampler0_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
static float
hsw__render_basic__sampler1_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: Sampler 0 Texels LOD0 */
static uint64_t
hsw__render_basic__sampler0_texels__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Sampler 1 Texels LOD0 */
static uint64_t
hsw__render_basic__sampler1_texels__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Sampler Texels LOD0 */
static uint64_t
hsw__render_basic__sampler_texels__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: $Sampler0Texels $Sampler1Texels UADD $EuSlicesTotalCount UMUL */
   uint64_t tmp0 = hsw__render_basic__sampler0_texels__read(perf, query, results) + hsw__render_basic__sampler1_texels__read(perf, query, results);
   uint64_t tmp1 = tmp0 * perf->sys_vars.n_eu_slices;

   return tmp1;
}

/* Render Metrics Basic set :: L3 Sampler Throughput */
static uint64_t
hsw__render_basic__l3_sampler_throughput__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ B 7 READ UADD 2 UMUL $EuSlicesTotalCount UMUL 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 2;
   uint64_t tmp4 = tmp3 * perf->sys_vars.n_eu_slices;
   uint64_t tmp5 = tmp4 * 64;

   return tmp5;
}

/* Render Metrics Basic set :: L3 Sampler Throughput */
static uint64_t
hsw__render_basic__l3_sampler_throughput__max(struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 64 UMUL $EuSlicesTotalCount UMUL */
   uint64_t tmp0 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * 64;
   uint64_t tmp1 = tmp0 * perf->sys_vars.n_eu_slices;

   return tmp1;
}

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
static uint64_t
hsw__render_basic__hi_depth_test_fails__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: A 33 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 33];

   return tmp0;
}

/* Render Metrics Basic set :: Early Depth Test Fails */
static uint64_t
hsw__render_basic__early_depth_test_fails__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: A 35 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 35];

   return tmp0;
}

/* Render Metrics Basic set :: Samples Killed in FS */
static uint64_t
hsw__render_basic__samples_killed_in_ps__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: A 36 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 36];

   return tmp0;
}

/* Render Metrics Basic set :: Alpha Test Fails */
static uint64_t
hsw__render_basic__alpha_test_fails__read(UNUSED struct intel_perf_config *perf,
                                          const struct intel_perf_query_info *query,
                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: A 37 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 37];

   return tmp0;
}

/* Render Metrics Basic set :: Late Stencil Test Fails */
static uint64_t
hsw__render_basic__post_ps_stencil_test_fails__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 38 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 38];

   return tmp0;
}

/* Render Metrics Basic set :: Late Depth Test Fails */
static uint64_t
hsw__render_basic__post_ps_depth_test_fails__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: A 39 READ $SamplesKilledInPs USUB */
   uint64_t tmp0 = results->accumulator[query->a_offset + 39];
   uint64_t tmp1 = tmp0 - hsw__render_basic__samples_killed_in_ps__read(perf, query, results);

   return tmp1;
}

/* Render Metrics Basic set :: Samples Written */
static uint64_t
hsw__render_basic__samples_written__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 40 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 40];

   return tmp0;
}

/* Render Metrics Basic set :: Samples Blended */
static uint64_t
hsw__render_basic__samples_blended__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ $EuSlicesTotalCount 4 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = perf->sys_vars.n_eu_slices * 4;
   uint64_t tmp2 = tmp0 * tmp1;

   return tmp2;
}

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
static uint64_t
hsw__render_basic__gti_vf_throughput__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
static uint64_t
hsw__render_basic__gti_vf_throughput__max(struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 64 UMUL */
   uint64_t tmp0 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * 64;

   return tmp0;
}

/* Render Metrics Basic set :: GTI Depth Throughput */
static uint64_t
hsw__render_basic__gti_depth_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: GTI Depth Throughput */
#define hsw__render_basic__gti_depth_throughput__max \
   hsw__render_basic__l3_sampler_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
static uint64_t
hsw__render_basic__gti_rcc_throughput__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: GTI RCC Throughput */
#define hsw__render_basic__gti_rcc_throughput__max \
   hsw__render_basic__l3_sampler_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
static uint64_t
hsw__render_basic__gti_l3_throughput__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: GTI L3 Throughput */
#define hsw__render_basic__gti_l3_throughput__max \
   hsw__render_basic__l3_sampler_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
static uint64_t
hsw__render_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Render Metrics Basic set :: GTI Read Throughput */
#define hsw__render_basic__gti_read_throughput__max \
   hsw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
static uint64_t
hsw__render_basic__gti_write_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: GTI Write Throughput */
static uint64_t
hsw__render_basic__gti_write_throughput__max(struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 32 UMUL */
   uint64_t tmp0 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * 32;

   return tmp0;
}

/* Render Metrics Basic set :: LLC GPU Accesses */
static uint64_t
hsw__render_basic__llc_accesses__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: PERFCNT 0 READ */
   uint64_t tmp0 = results->accumulator[query->perfcnt_offset + 0];

   return tmp0;
}

/* Render Metrics Basic set :: LLC GPU Hits */
static uint64_t
hsw__render_basic__llc_hits__read(UNUSED struct intel_perf_config *perf,
                                  const struct intel_perf_query_info *query,
                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: PERFCNT 1 READ */
   uint64_t tmp0 = results->accumulator[query->perfcnt_offset + 1];

   return tmp0;
}

/* Render Metrics Basic set :: LLC GPU Throughput */
static uint64_t
hsw__render_basic__llc_gpu_throughput__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: PERFCNT 0 READ C 7 READ USUB 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->perfcnt_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 64;

   return tmp3;
}

/* Render Metrics Basic set :: LLC GPU Throughput */
#define hsw__render_basic__llc_gpu_throughput__max \
   hsw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: FS Duration */
static uint64_t
hsw__render_basic__ps_duration__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 27 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 28 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 27];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 28];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Render Metrics Basic set :: VS Duration */
static uint64_t
hsw__render_basic__vs_duration__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 2 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 3 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 2];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 3];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Render Metrics Basic set :: GS Duration */
static uint64_t
hsw__render_basic__gs_duration__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 22 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 23 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 22];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 23];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Render Metrics Basic set :: TES Duration */
static uint64_t
hsw__render_basic__ds_duration__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 12 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 13 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 12];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 13];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Render Metrics Basic set :: TCS Duration */
static uint64_t
hsw__render_basic__hs_duration__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 8 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 8];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Render Metrics Basic set :: CS Duration */
static uint64_t
hsw__render_basic__cs_duration__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 17 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 18 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 18];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Render Metrics Basic set :: Sampler Bottleneck */
static float
hsw__render_basic__sampler_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: $Sampler0Bottleneck $Sampler1Bottleneck FMAX */
   double tmp0 = hsw__render_basic__sampler0_bottleneck__read(perf, query, results);
   double tmp1 = hsw__render_basic__sampler1_bottleneck__read(perf, query, results);
   double tmp2 = MAX(tmp0, tmp1);

   return tmp2;
}

/* Render Metrics Basic set :: EU Idle */
static float
hsw__render_basic__eu_idle__read(UNUSED struct intel_perf_config *perf,
                                 const struct intel_perf_query_info *query,
                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 100 $EuActive $EuStall FADD FSUB */
   double tmp0 = hsw__render_basic__eu_active__read(perf, query, results) + hsw__render_basic__eu_stall__read(perf, query, results);
   double tmp1 = 100 - tmp0;

   return tmp1;
}

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define hsw__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define hsw__compute_basic__gpu_core_clocks__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define hsw__compute_basic__avg_gpu_core_frequency__read \
   hsw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define hsw__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define hsw__compute_basic__gpu_busy__read \
   hsw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define hsw__compute_basic__vs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: TCS Threads Dispatched */
#define hsw__compute_basic__hs_threads__read \
   hsw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: TES Threads Dispatched */
#define hsw__compute_basic__ds_threads__read \
   hsw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define hsw__compute_basic__gs_threads__read \
   hsw__render_basic__gs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define hsw__compute_basic__ps_threads__read \
   hsw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define hsw__compute_basic__cs_threads__read \
   hsw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define hsw__compute_basic__eu_active__read \
   hsw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define hsw__compute_basic__eu_stall__read \
   hsw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: VS EU Active */
#define hsw__compute_basic__vs_eu_active__read \
   hsw__render_basic__vs_eu_active__read

/* Compute Metrics Basic set :: VS AVG Active per Thread */
#define hsw__compute_basic__vs_eu_active_per_thread__read \
   hsw__render_basic__vs_eu_active_per_thread__read

/* Compute Metrics Basic set :: VS EU Stall */
#define hsw__compute_basic__vs_eu_stall__read \
   hsw__render_basic__vs_eu_stall__read

/* Compute Metrics Basic set :: VS AVG Stall per Thread */
#define hsw__compute_basic__vs_eu_stall_per_thread__read \
   hsw__render_basic__vs_eu_stall_per_thread__read

/* Compute Metrics Basic set :: FS EU Active */
#define hsw__compute_basic__ps_eu_active__read \
   hsw__render_basic__ps_eu_active__read

/* Compute Metrics Basic set :: TCS EU Active */
#define hsw__compute_basic__hs_eu_active__read \
   hsw__render_basic__hs_eu_active__read

/* Compute Metrics Basic set :: TCS AVG Active per Thread */
#define hsw__compute_basic__hs_eu_active_per_thread__read \
   hsw__render_basic__hs_eu_active_per_thread__read

/* Compute Metrics Basic set :: TCS EU Stall */
#define hsw__compute_basic__hs_eu_stall__read \
   hsw__render_basic__hs_eu_stall__read

/* Compute Metrics Basic set :: TCS AVG Stall per Thread */
#define hsw__compute_basic__hs_eu_stall_per_thread__read \
   hsw__render_basic__hs_eu_stall_per_thread__read

/* Compute Metrics Basic set :: TES EU Active */
#define hsw__compute_basic__ds_eu_active__read \
   hsw__render_basic__ds_eu_active__read

/* Compute Metrics Basic set :: TES AVG Active per Thread */
#define hsw__compute_basic__ds_eu_active_per_thread__read \
   hsw__render_basic__ds_eu_active_per_thread__read

/* Compute Metrics Basic set :: TES EU Stall */
#define hsw__compute_basic__ds_eu_stall__read \
   hsw__render_basic__ds_eu_stall__read

/* Compute Metrics Basic set :: TES AVG Stall per Thread */
#define hsw__compute_basic__ds_eu_stall_per_thread__read \
   hsw__render_basic__ds_eu_stall_per_thread__read

/* Compute Metrics Basic set :: GS EU Active */
#define hsw__compute_basic__gs_eu_active__read \
   hsw__render_basic__gs_eu_active__read

/* Compute Metrics Basic set :: GS AVG Active per Thread */
#define hsw__compute_basic__gs_eu_active_per_thread__read \
   hsw__render_basic__gs_eu_active_per_thread__read

/* Compute Metrics Basic set :: GS EU Stall */
#define hsw__compute_basic__gs_eu_stall__read \
   hsw__render_basic__gs_eu_stall__read

/* Compute Metrics Basic set :: GS AVG Stall per Thread */
#define hsw__compute_basic__gs_eu_stall_per_thread__read \
   hsw__render_basic__gs_eu_stall_per_thread__read

/* Compute Metrics Basic set :: CS EU Active */
#define hsw__compute_basic__cs_eu_active__read \
   hsw__render_basic__cs_eu_active__read

/* Compute Metrics Basic set :: CS AVG Active per Thread */
#define hsw__compute_basic__cs_eu_active_per_thread__read \
   hsw__render_basic__cs_eu_active_per_thread__read

/* Compute Metrics Basic set :: CS EU Stall */
#define hsw__compute_basic__cs_eu_stall__read \
   hsw__render_basic__cs_eu_stall__read

/* Compute Metrics Basic set :: CS AVG Stall per Thread */
#define hsw__compute_basic__cs_eu_stall_per_thread__read \
   hsw__render_basic__cs_eu_stall_per_thread__read

/* Compute Metrics Basic set :: FS AVG Active per Thread */
#define hsw__compute_basic__ps_eu_active_per_thread__read \
   hsw__render_basic__ps_eu_active_per_thread__read

/* Compute Metrics Basic set :: FS EU Stall */
#define hsw__compute_basic__ps_eu_stall__read \
   hsw__render_basic__ps_eu_stall__read

/* Compute Metrics Basic set :: FS AVG Stall per Thread */
#define hsw__compute_basic__ps_eu_stall_per_thread__read \
   hsw__render_basic__ps_eu_stall_per_thread__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define hsw__compute_basic__hi_depth_test_fails__read \
   hsw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define hsw__compute_basic__early_depth_test_fails__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define hsw__compute_basic__samples_killed_in_ps__read \
   hsw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Alpha Test Fails */
#define hsw__compute_basic__alpha_test_fails__read \
   hsw__render_basic__alpha_test_fails__read

/* Compute Metrics Basic set :: Late Stencil Test Fails */
#define hsw__compute_basic__post_ps_stencil_test_fails__read \
   hsw__render_basic__post_ps_stencil_test_fails__read

/* Compute Metrics Basic set :: Late Depth Test Fails */
#define hsw__compute_basic__post_ps_depth_test_fails__read \
   hsw__render_basic__post_ps_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Written */
#define hsw__compute_basic__samples_written__read \
   hsw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Typed Bytes Read */
static uint64_t
hsw__compute_basic__typed_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp4 = tmp2 * tmp3;

   return tmp4;
}

/* Compute Metrics Basic set :: Typed Bytes Read */
#define hsw__compute_basic__typed_bytes_read__max \
   hsw__render_basic__l3_sampler_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
static uint64_t
hsw__compute_basic__typed_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ B 7 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp4 = tmp2 * tmp3;

   return tmp4;
}

/* Compute Metrics Basic set :: Typed Bytes Written */
#define hsw__compute_basic__typed_bytes_written__max \
   hsw__render_basic__l3_sampler_throughput__max

/* Compute Metrics Basic set :: Typed Atomics */
static uint64_t
hsw__compute_basic__typed_atomics__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ C 1 READ UADD $EuSlicesTotalCount UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_slices;

   return tmp3;
}

/* Compute Metrics Basic set :: Untyped Bytes Read */
static uint64_t
hsw__compute_basic__untyped_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp4 = tmp2 * tmp3;

   return tmp4;
}

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define hsw__compute_basic__untyped_bytes_read__max \
   hsw__render_basic__l3_sampler_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
static uint64_t
hsw__compute_basic__untyped_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ B 3 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->b_offset + 3];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp4 = tmp2 * tmp3;

   return tmp4;
}

/* Compute Metrics Basic set :: Untyped Writes */
#define hsw__compute_basic__untyped_bytes_written__max \
   hsw__render_basic__l3_sampler_throughput__max

/* Compute Metrics Basic set :: SLM Bytes Read */
static uint64_t
hsw__compute_basic__slm_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ C 7 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp4 = tmp2 * tmp3;

   return tmp4;
}

/* Compute Metrics Basic set :: SLM Bytes Read */
#define hsw__compute_basic__slm_bytes_read__max \
   hsw__render_basic__l3_sampler_throughput__max

/* Compute Metrics Basic set :: SLM Bytes Written */
static uint64_t
hsw__compute_basic__slm_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ C 5 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp4 = tmp2 * tmp3;

   return tmp4;
}

/* Compute Metrics Basic set :: SLM Bytes Written */
#define hsw__compute_basic__slm_bytes_written__max \
   hsw__render_basic__l3_sampler_throughput__max

/* Compute Metrics Basic set :: LLC GPU Accesses */
#define hsw__compute_basic__llc_accesses__read \
   hsw__render_basic__llc_accesses__read

/* Compute Metrics Basic set :: LLC GPU Hits */
#define hsw__compute_basic__llc_hits__read \
   hsw__render_basic__llc_hits__read

/* Compute Metrics Extended set :: GPU Time Elapsed */
#define hsw__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended set :: GPU Core Clocks */
static uint64_t
hsw__compute_extended__gpu_clocks__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];

   return tmp0;
}

/* Compute Metrics Extended set :: CS Threads Dispatched */
#define hsw__compute_extended__cs_threads__read \
   hsw__render_basic__cs_threads__read

/* Compute Metrics Extended set :: EuUntypedReads0 */
static uint64_t
hsw__compute_extended__eu_untyped_reads0__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];

   return tmp0;
}

/* Compute Metrics Extended set :: EuTypedReads0 */
static uint64_t
hsw__compute_extended__eu_typed_reads0__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];

   return tmp0;
}

/* Compute Metrics Extended set :: EuUntypedWrites0 */
static uint64_t
hsw__compute_extended__eu_untyped_writes0__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];

   return tmp0;
}

/* Compute Metrics Extended set :: EuTypedWrites0 */
static uint64_t
hsw__compute_extended__eu_typed_writes0__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];

   return tmp0;
}

/* Compute Metrics Extended set :: EuUntypedAtomics0 */
static uint64_t
hsw__compute_extended__eu_untyped_atomics0__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];

   return tmp0;
}

/* Compute Metrics Extended set :: EuTypedAtomics0 */
static uint64_t
hsw__compute_extended__eu_typed_atomics0__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];

   return tmp0;
}

/* Compute Metrics Extended set :: EuUrbAtomics0 */
static uint64_t
hsw__compute_extended__eu_urb_atomics0__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];

   return tmp0;
}

/* Compute Metrics Extended set :: Typed Reads 0 */
#define hsw__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: Typed Writes 0 */
static uint64_t
hsw__compute_extended__typed_writes0__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];

   return tmp0;
}

/* Compute Metrics Extended set :: Untyped Reads 0 */
static uint64_t
hsw__compute_extended__untyped_reads0__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];

   return tmp0;
}

/* Compute Metrics Extended set :: Untyped Writes 0 */
static uint64_t
hsw__compute_extended__untyped_writes0__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];

   return tmp0;
}

/* Compute Metrics Extended set :: Typed Atomics 0 */
static uint64_t
hsw__compute_extended__typed_atomics0__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];

   return tmp0;
}

/* Compute Metrics Extended set :: TypedReadsPerCacheLine */
static float
hsw__compute_extended__typed_reads_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuTypedReads0 $TypedReads0 FDIV */
   double tmp0 = hsw__compute_extended__eu_typed_reads0__read(perf, query, results);
   double tmp1 = hsw__compute_extended__typed_reads0__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Compute Metrics Extended set :: TypedWritesPerCacheLine */
static float
hsw__compute_extended__typed_writes_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                         const struct intel_perf_query_info *query,
                                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuTypedWrites0 $TypedWrites0 FDIV */
   double tmp0 = hsw__compute_extended__eu_typed_writes0__read(perf, query, results);
   double tmp1 = hsw__compute_extended__typed_writes0__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Compute Metrics Extended set :: UntypedReadsPerCacheLine */
static float
hsw__compute_extended__untyped_reads_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                          const struct intel_perf_query_info *query,
                                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuUntypedReads0 $UntypedReads0 FDIV */
   double tmp0 = hsw__compute_extended__eu_untyped_reads0__read(perf, query, results);
   double tmp1 = hsw__compute_extended__untyped_reads0__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Compute Metrics Extended set :: UntypedWritesPerCacheLine */
static float
hsw__compute_extended__untyped_writes_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuUntypedWrites0 $UntypedWrites0 FDIV */
   double tmp0 = hsw__compute_extended__eu_untyped_writes0__read(perf, query, results);
   double tmp1 = hsw__compute_extended__untyped_writes0__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Compute Metrics Extended set :: TypedAtomicsPerCacheLine */
static float
hsw__compute_extended__typed_atomics_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                          const struct intel_perf_query_info *query,
                                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuTypedAtomics0 $TypedAtomics0 FDIV */
   double tmp0 = hsw__compute_extended__eu_typed_atomics0__read(perf, query, results);
   double tmp1 = hsw__compute_extended__typed_atomics0__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Compute Metrics Extended set :: LLC GPU Accesses */
#define hsw__compute_extended__llc_accesses__read \
   hsw__render_basic__llc_accesses__read

/* Compute Metrics Extended set :: LLC GPU Hits */
#define hsw__compute_extended__llc_hits__read \
   hsw__render_basic__llc_hits__read

/* Memory Reads Distribution set :: GPU Time Elapsed */
#define hsw__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution set :: GPU Core Clocks */
static uint64_t
hsw__memory_reads__gpu_core_clocks__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];

   return tmp0;
}

/* Memory Reads Distribution set :: AVG GPU Core Frequency */
static uint64_t
hsw__memory_reads__avg_gpu_core_frequency__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */
   uint64_t tmp0 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results) * 1000000000;
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__memory_reads__gpu_time__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Memory Reads Distribution set :: AVG GPU Core Frequency */
#define hsw__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution set :: GPU Busy */
static float
hsw__memory_reads__gpu_busy__read(UNUSED struct intel_perf_config *perf,
                                  const struct intel_perf_query_info *query,
                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: A 41 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 41];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Memory Reads Distribution set :: VS Threads Dispatched */
#define hsw__memory_reads__vs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution set :: TCS Threads Dispatched */
#define hsw__memory_reads__hs_threads__read \
   hsw__render_basic__hs_threads__read

/* Memory Reads Distribution set :: TES Threads Dispatched */
#define hsw__memory_reads__ds_threads__read \
   hsw__render_basic__ds_threads__read

/* Memory Reads Distribution set :: GS Threads Dispatched */
#define hsw__memory_reads__gs_threads__read \
   hsw__render_basic__gs_threads__read

/* Memory Reads Distribution set :: FS Threads Dispatched */
#define hsw__memory_reads__ps_threads__read \
   hsw__render_basic__ps_threads__read

/* Memory Reads Distribution set :: CS Threads Dispatched */
#define hsw__memory_reads__cs_threads__read \
   hsw__render_basic__cs_threads__read

/* Memory Reads Distribution set :: EU Active */
static float
hsw__memory_reads__eu_active__read(UNUSED struct intel_perf_config *perf,
                                   const struct intel_perf_query_info *query,
                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: A 0 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 0];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: EU Stall */
static float
hsw__memory_reads__eu_stall__read(UNUSED struct intel_perf_config *perf,
                                  const struct intel_perf_query_info *query,
                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: A 1 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 1];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: VS EU Active */
static float
hsw__memory_reads__vs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 2 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 2];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: VS AVG Active per Thread */
#define hsw__memory_reads__vs_eu_active_per_thread__read \
   hsw__render_basic__vs_eu_active_per_thread__read

/* Memory Reads Distribution set :: VS EU Stall */
static float
hsw__memory_reads__vs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 3 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 3];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: VS AVG Stall per Thread */
#define hsw__memory_reads__vs_eu_stall_per_thread__read \
   hsw__render_basic__vs_eu_stall_per_thread__read

/* Memory Reads Distribution set :: TCS EU Active */
static float
hsw__memory_reads__hs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: TCS AVG Active per Thread */
#define hsw__memory_reads__hs_eu_active_per_thread__read \
   hsw__render_basic__hs_eu_active_per_thread__read

/* Memory Reads Distribution set :: TCS EU Stall */
static float
hsw__memory_reads__hs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 8];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: TCS AVG Stall per Thread */
#define hsw__memory_reads__hs_eu_stall_per_thread__read \
   hsw__render_basic__hs_eu_stall_per_thread__read

/* Memory Reads Distribution set :: TES EU Active */
static float
hsw__memory_reads__ds_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 12];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: TES AVG Active per Thread */
#define hsw__memory_reads__ds_eu_active_per_thread__read \
   hsw__render_basic__ds_eu_active_per_thread__read

/* Memory Reads Distribution set :: TES EU Stall */
static float
hsw__memory_reads__ds_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 13];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: TES AVG Stall per Thread */
#define hsw__memory_reads__ds_eu_stall_per_thread__read \
   hsw__render_basic__ds_eu_stall_per_thread__read

/* Memory Reads Distribution set :: GS EU Active */
static float
hsw__memory_reads__gs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 22 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 22];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: GS AVG Active per Thread */
#define hsw__memory_reads__gs_eu_active_per_thread__read \
   hsw__render_basic__gs_eu_active_per_thread__read

/* Memory Reads Distribution set :: GS EU Stall */
static float
hsw__memory_reads__gs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 23 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 23];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: GS AVG Stall per Thread */
#define hsw__memory_reads__gs_eu_stall_per_thread__read \
   hsw__render_basic__gs_eu_stall_per_thread__read

/* Memory Reads Distribution set :: CS EU Active */
static float
hsw__memory_reads__cs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: CS AVG Active per Thread */
#define hsw__memory_reads__cs_eu_active_per_thread__read \
   hsw__render_basic__cs_eu_active_per_thread__read

/* Memory Reads Distribution set :: CS EU Stall */
static float
hsw__memory_reads__cs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 18];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: CS AVG Stall per Thread */
#define hsw__memory_reads__cs_eu_stall_per_thread__read \
   hsw__render_basic__cs_eu_stall_per_thread__read

/* Memory Reads Distribution set :: FS EU Active */
static float
hsw__memory_reads__ps_eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 27 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 27];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: FS AVG Active per Thread */
#define hsw__memory_reads__ps_eu_active_per_thread__read \
   hsw__render_basic__ps_eu_active_per_thread__read

/* Memory Reads Distribution set :: FS EU Stall */
static float
hsw__memory_reads__ps_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 28 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 28];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Memory Reads Distribution set :: FS AVG Stall per Thread */
#define hsw__memory_reads__ps_eu_stall_per_thread__read \
   hsw__render_basic__ps_eu_stall_per_thread__read

/* Memory Reads Distribution set :: Early Hi-Depth Test Fails */
#define hsw__memory_reads__hi_depth_test_fails__read \
   hsw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution set :: Early Depth Test Fails */
#define hsw__memory_reads__early_depth_test_fails__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution set :: Samples Killed in FS */
#define hsw__memory_reads__samples_killed_in_ps__read \
   hsw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution set :: Alpha Test Fails */
#define hsw__memory_reads__alpha_test_fails__read \
   hsw__render_basic__alpha_test_fails__read

/* Memory Reads Distribution set :: Late Stencil Test Fails */
#define hsw__memory_reads__post_ps_stencil_test_fails__read \
   hsw__render_basic__post_ps_stencil_test_fails__read

/* Memory Reads Distribution set :: Late Depth Test Fails */
#define hsw__memory_reads__post_ps_depth_test_fails__read \
   hsw__render_basic__post_ps_depth_test_fails__read

/* Memory Reads Distribution set :: Samples Written */
#define hsw__memory_reads__samples_written__read \
   hsw__render_basic__samples_written__read

/* Memory Reads Distribution set :: GtiCmdStreamerMemoryReads */
#define hsw__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution set :: GtiRsMemoryReads */
#define hsw__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution set :: GtiVfMemoryReads */
#define hsw__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution set :: GtiRccMemoryReads */
#define hsw__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution set :: GtiMscMemoryReads */
#define hsw__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution set :: GtiHiDepthMemoryReads */
#define hsw__memory_reads__gti_hi_depth_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution set :: GtiStcMemoryReads */
#define hsw__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution set :: GtiRczMemoryReads */
#define hsw__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution set :: GtiL3Reads */
#define hsw__memory_reads__gti_l3_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution set :: GtiMemoryReads */
static uint64_t
hsw__memory_reads__gti_memory_reads__read(UNUSED struct intel_perf_config *perf,
                                          const struct intel_perf_query_info *query,
                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];

   return tmp0;
}

/* Memory Reads Distribution set :: LLC GPU Read Accesses */
static uint64_t
hsw__memory_reads__llc_read_accesses__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];

   return tmp0;
}

/* Memory Reads Distribution set :: LLC GPU Accesses */
#define hsw__memory_reads__llc_accesses__read \
   hsw__render_basic__llc_accesses__read

/* Memory Reads Distribution set :: LLC GPU Hits */
#define hsw__memory_reads__llc_hits__read \
   hsw__render_basic__llc_hits__read

/* Memory Writes Distribution set :: GPU Time Elapsed */
#define hsw__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution set :: GPU Core Clocks */
#define hsw__memory_writes__gpu_core_clocks__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution set :: AVG GPU Core Frequency */
#define hsw__memory_writes__avg_gpu_core_frequency__read \
   hsw__memory_reads__avg_gpu_core_frequency__read

/* Memory Writes Distribution set :: AVG GPU Core Frequency */
#define hsw__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution set :: GPU Busy */
#define hsw__memory_writes__gpu_busy__read \
   hsw__memory_reads__gpu_busy__read

/* Memory Writes Distribution set :: VS Threads Dispatched */
#define hsw__memory_writes__vs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution set :: TCS Threads Dispatched */
#define hsw__memory_writes__hs_threads__read \
   hsw__render_basic__hs_threads__read

/* Memory Writes Distribution set :: TES Threads Dispatched */
#define hsw__memory_writes__ds_threads__read \
   hsw__render_basic__ds_threads__read

/* Memory Writes Distribution set :: GS Threads Dispatched */
#define hsw__memory_writes__gs_threads__read \
   hsw__render_basic__gs_threads__read

/* Memory Writes Distribution set :: FS Threads Dispatched */
#define hsw__memory_writes__ps_threads__read \
   hsw__render_basic__ps_threads__read

/* Memory Writes Distribution set :: CS Threads Dispatched */
#define hsw__memory_writes__cs_threads__read \
   hsw__render_basic__cs_threads__read

/* Memory Writes Distribution set :: EU Active */
#define hsw__memory_writes__eu_active__read \
   hsw__memory_reads__eu_active__read

/* Memory Writes Distribution set :: EU Stall */
#define hsw__memory_writes__eu_stall__read \
   hsw__memory_reads__eu_stall__read

/* Memory Writes Distribution set :: VS EU Active */
#define hsw__memory_writes__vs_eu_active__read \
   hsw__memory_reads__vs_eu_active__read

/* Memory Writes Distribution set :: VS AVG Active per Thread */
#define hsw__memory_writes__vs_eu_active_per_thread__read \
   hsw__render_basic__vs_eu_active_per_thread__read

/* Memory Writes Distribution set :: VS EU Stall */
#define hsw__memory_writes__vs_eu_stall__read \
   hsw__memory_reads__vs_eu_stall__read

/* Memory Writes Distribution set :: VS AVG Stall per Thread */
#define hsw__memory_writes__vs_eu_stall_per_thread__read \
   hsw__render_basic__vs_eu_stall_per_thread__read

/* Memory Writes Distribution set :: TCS EU Active */
#define hsw__memory_writes__hs_eu_active__read \
   hsw__memory_reads__hs_eu_active__read

/* Memory Writes Distribution set :: TCS AVG Active per Thread */
#define hsw__memory_writes__hs_eu_active_per_thread__read \
   hsw__render_basic__hs_eu_active_per_thread__read

/* Memory Writes Distribution set :: TCS EU Stall */
#define hsw__memory_writes__hs_eu_stall__read \
   hsw__memory_reads__hs_eu_stall__read

/* Memory Writes Distribution set :: TCS AVG Stall per Thread */
#define hsw__memory_writes__hs_eu_stall_per_thread__read \
   hsw__render_basic__hs_eu_stall_per_thread__read

/* Memory Writes Distribution set :: TES EU Active */
#define hsw__memory_writes__ds_eu_active__read \
   hsw__memory_reads__ds_eu_active__read

/* Memory Writes Distribution set :: TES AVG Active per Thread */
#define hsw__memory_writes__ds_eu_active_per_thread__read \
   hsw__render_basic__ds_eu_active_per_thread__read

/* Memory Writes Distribution set :: TES EU Stall */
#define hsw__memory_writes__ds_eu_stall__read \
   hsw__memory_reads__ds_eu_stall__read

/* Memory Writes Distribution set :: TES AVG Stall per Thread */
#define hsw__memory_writes__ds_eu_stall_per_thread__read \
   hsw__render_basic__ds_eu_stall_per_thread__read

/* Memory Writes Distribution set :: GS EU Active */
#define hsw__memory_writes__gs_eu_active__read \
   hsw__memory_reads__gs_eu_active__read

/* Memory Writes Distribution set :: GS AVG Active per Thread */
#define hsw__memory_writes__gs_eu_active_per_thread__read \
   hsw__render_basic__gs_eu_active_per_thread__read

/* Memory Writes Distribution set :: GS EU Stall */
#define hsw__memory_writes__gs_eu_stall__read \
   hsw__memory_reads__gs_eu_stall__read

/* Memory Writes Distribution set :: GS AVG Stall per Thread */
#define hsw__memory_writes__gs_eu_stall_per_thread__read \
   hsw__render_basic__gs_eu_stall_per_thread__read

/* Memory Writes Distribution set :: CS EU Active */
#define hsw__memory_writes__cs_eu_active__read \
   hsw__memory_reads__cs_eu_active__read

/* Memory Writes Distribution set :: CS AVG Active per Thread */
#define hsw__memory_writes__cs_eu_active_per_thread__read \
   hsw__render_basic__cs_eu_active_per_thread__read

/* Memory Writes Distribution set :: CS EU Stall */
#define hsw__memory_writes__cs_eu_stall__read \
   hsw__memory_reads__cs_eu_stall__read

/* Memory Writes Distribution set :: CS AVG Stall per Thread */
#define hsw__memory_writes__cs_eu_stall_per_thread__read \
   hsw__render_basic__cs_eu_stall_per_thread__read

/* Memory Writes Distribution set :: FS EU Active */
#define hsw__memory_writes__ps_eu_active__read \
   hsw__memory_reads__ps_eu_active__read

/* Memory Writes Distribution set :: FS AVG Active per Thread */
#define hsw__memory_writes__ps_eu_active_per_thread__read \
   hsw__render_basic__ps_eu_active_per_thread__read

/* Memory Writes Distribution set :: FS EU Stall */
#define hsw__memory_writes__ps_eu_stall__read \
   hsw__memory_reads__ps_eu_stall__read

/* Memory Writes Distribution set :: FS AVG Stall per Thread */
#define hsw__memory_writes__ps_eu_stall_per_thread__read \
   hsw__render_basic__ps_eu_stall_per_thread__read

/* Memory Writes Distribution set :: Early Hi-Depth Test Fails */
#define hsw__memory_writes__hi_depth_test_fails__read \
   hsw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution set :: Early Depth Test Fails */
#define hsw__memory_writes__early_depth_test_fails__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution set :: Samples Killed in FS */
#define hsw__memory_writes__samples_killed_in_ps__read \
   hsw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution set :: Alpha Test Fails */
#define hsw__memory_writes__alpha_test_fails__read \
   hsw__render_basic__alpha_test_fails__read

/* Memory Writes Distribution set :: Late Stencil Test Fails */
#define hsw__memory_writes__post_ps_stencil_test_fails__read \
   hsw__render_basic__post_ps_stencil_test_fails__read

/* Memory Writes Distribution set :: Late Depth Test Fails */
#define hsw__memory_writes__post_ps_depth_test_fails__read \
   hsw__render_basic__post_ps_depth_test_fails__read

/* Memory Writes Distribution set :: Samples Written */
#define hsw__memory_writes__samples_written__read \
   hsw__render_basic__samples_written__read

/* Memory Writes Distribution set :: GtiCmdStreamerMemoryWrites */
#define hsw__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution set :: GtiSoMemoryWrites */
#define hsw__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution set :: GtiRccMemoryWrites */
#define hsw__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution set :: GtiMscMemoryWrites */
#define hsw__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution set :: GtiHizMemoryWrites */
#define hsw__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution set :: GtiStcMemoryWrites */
#define hsw__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution set :: GtiRczMemoryWrites */
#define hsw__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution set :: GtiL3Writes */
#define hsw__memory_writes__gti_l3_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution set :: GtiMemoryWrites */
#define hsw__memory_writes__gti_memory_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution set :: LLC GPU Write Accesses */
static uint64_t
hsw__memory_writes__llc_wr_accesses__read(UNUSED struct intel_perf_config *perf,
                                          const struct intel_perf_query_info *query,
                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Memory Writes Distribution set :: LLC GPU Accesses */
#define hsw__memory_writes__llc_accesses__read \
   hsw__render_basic__llc_accesses__read

/* Memory Writes Distribution set :: LLC GPU Hits */
#define hsw__memory_writes__llc_hits__read \
   hsw__render_basic__llc_hits__read

/* Memory Writes Distribution set :: LLC GPU Throughput */
static uint64_t
hsw__memory_writes__llc_gpu_throughput__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: PERFCNT 0 READ $LlcWrAccesses USUB 64 UMUL $LlcWrAccesses 32 UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->perfcnt_offset + 0];
   uint64_t tmp1 = tmp0 - hsw__memory_writes__llc_wr_accesses__read(perf, query, results);
   uint64_t tmp2 = tmp1 * 64;
   uint64_t tmp3 = hsw__memory_writes__llc_wr_accesses__read(perf, query, results) * 32;
   uint64_t tmp4 = tmp2 + tmp3;

   return tmp4;
}

/* Memory Writes Distribution set :: LLC GPU Throughput */
#define hsw__memory_writes__llc_gpu_throughput__max \
   hsw__render_basic__gti_write_throughput__read

/* Metric set SamplerBalance :: GPU Time Elapsed */
#define hsw__sampler_balance__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set SamplerBalance :: GPU Core Clocks */
#define hsw__sampler_balance__gpu_core_clocks__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set SamplerBalance :: AVG GPU Core Frequency */
static uint64_t
hsw__sampler_balance__avg_gpu_core_frequency__read(UNUSED struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */
   uint64_t tmp0 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results) * 1000000000;
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = hsw__sampler_balance__gpu_time__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Metric set SamplerBalance :: AVG GPU Core Frequency */
#define hsw__sampler_balance__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set SamplerBalance :: GPU Busy */
static float
hsw__sampler_balance__gpu_busy__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 41 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 41];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Metric set SamplerBalance :: VS Threads Dispatched */
#define hsw__sampler_balance__vs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set SamplerBalance :: TCS Threads Dispatched */
#define hsw__sampler_balance__hs_threads__read \
   hsw__render_basic__hs_threads__read

/* Metric set SamplerBalance :: TES Threads Dispatched */
#define hsw__sampler_balance__ds_threads__read \
   hsw__render_basic__ds_threads__read

/* Metric set SamplerBalance :: GS Threads Dispatched */
#define hsw__sampler_balance__gs_threads__read \
   hsw__render_basic__gs_threads__read

/* Metric set SamplerBalance :: FS Threads Dispatched */
#define hsw__sampler_balance__ps_threads__read \
   hsw__render_basic__ps_threads__read

/* Metric set SamplerBalance :: CS Threads Dispatched */
#define hsw__sampler_balance__cs_threads__read \
   hsw__render_basic__cs_threads__read

/* Metric set SamplerBalance :: EU Active */
static float
hsw__sampler_balance__eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 0 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 0];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: EU Stall */
static float
hsw__sampler_balance__eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 1 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 1];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: VS EU Active */
static float
hsw__sampler_balance__vs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 2 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 2];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: VS AVG Active per Thread */
#define hsw__sampler_balance__vs_eu_active_per_thread__read \
   hsw__render_basic__vs_eu_active_per_thread__read

/* Metric set SamplerBalance :: VS EU Stall */
static float
hsw__sampler_balance__vs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 3 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 3];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: VS AVG Stall per Thread */
#define hsw__sampler_balance__vs_eu_stall_per_thread__read \
   hsw__render_basic__vs_eu_stall_per_thread__read

/* Metric set SamplerBalance :: TCS EU Active */
static float
hsw__sampler_balance__hs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: TCS AVG Active per Thread */
#define hsw__sampler_balance__hs_eu_active_per_thread__read \
   hsw__render_basic__hs_eu_active_per_thread__read

/* Metric set SamplerBalance :: TCS EU Stall */
static float
hsw__sampler_balance__hs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 8];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: TCS AVG Stall per Thread */
#define hsw__sampler_balance__hs_eu_stall_per_thread__read \
   hsw__render_basic__hs_eu_stall_per_thread__read

/* Metric set SamplerBalance :: TES EU Active */
static float
hsw__sampler_balance__ds_eu_active__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 12];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: TES AVG Active per Thread */
#define hsw__sampler_balance__ds_eu_active_per_thread__read \
   hsw__render_basic__ds_eu_active_per_thread__read

/* Metric set SamplerBalance :: TES EU Stall */
static float
hsw__sampler_balance__ds_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 13];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: TES AVG Stall per Thread */
#define hsw__sampler_balance__ds_eu_stall_per_thread__read \
   hsw__render_basic__ds_eu_stall_per_thread__read

/* Metric set SamplerBalance :: GS EU Active */
static float
hsw__sampler_balance__gs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 22 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 22];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: GS AVG Active per Thread */
#define hsw__sampler_balance__gs_eu_active_per_thread__read \
   hsw__render_basic__gs_eu_active_per_thread__read

/* Metric set SamplerBalance :: GS EU Stall */
static float
hsw__sampler_balance__gs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 23 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 23];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: GS AVG Stall per Thread */
#define hsw__sampler_balance__gs_eu_stall_per_thread__read \
   hsw__render_basic__gs_eu_stall_per_thread__read

/* Metric set SamplerBalance :: CS EU Active */
static float
hsw__sampler_balance__cs_eu_active__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: CS AVG Active per Thread */
#define hsw__sampler_balance__cs_eu_active_per_thread__read \
   hsw__render_basic__cs_eu_active_per_thread__read

/* Metric set SamplerBalance :: CS EU Stall */
static float
hsw__sampler_balance__cs_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 18];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: CS AVG Stall per Thread */
#define hsw__sampler_balance__cs_eu_stall_per_thread__read \
   hsw__render_basic__cs_eu_stall_per_thread__read

/* Metric set SamplerBalance :: FS EU Active */
static float
hsw__sampler_balance__ps_eu_active__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 27 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 27];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: FS AVG Active per Thread */
#define hsw__sampler_balance__ps_eu_active_per_thread__read \
   hsw__render_basic__ps_eu_active_per_thread__read

/* Metric set SamplerBalance :: FS EU Stall */
static float
hsw__sampler_balance__ps_eu_stall__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 28 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 28];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Metric set SamplerBalance :: FS AVG Stall per Thread */
#define hsw__sampler_balance__ps_eu_stall_per_thread__read \
   hsw__render_basic__ps_eu_stall_per_thread__read

/* Metric set SamplerBalance :: Early Hi-Depth Test Fails */
#define hsw__sampler_balance__hi_depth_test_fails__read \
   hsw__render_basic__hi_depth_test_fails__read

/* Metric set SamplerBalance :: Early Depth Test Fails */
#define hsw__sampler_balance__early_depth_test_fails__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set SamplerBalance :: Samples Killed in FS */
#define hsw__sampler_balance__samples_killed_in_ps__read \
   hsw__render_basic__samples_killed_in_ps__read

/* Metric set SamplerBalance :: Alpha Test Fails */
#define hsw__sampler_balance__alpha_test_fails__read \
   hsw__render_basic__alpha_test_fails__read

/* Metric set SamplerBalance :: Late Stencil Test Fails */
#define hsw__sampler_balance__post_ps_stencil_test_fails__read \
   hsw__render_basic__post_ps_stencil_test_fails__read

/* Metric set SamplerBalance :: Late Depth Test Fails */
#define hsw__sampler_balance__post_ps_depth_test_fails__read \
   hsw__render_basic__post_ps_depth_test_fails__read

/* Metric set SamplerBalance :: Samples Written */
#define hsw__sampler_balance__samples_written__read \
   hsw__render_basic__samples_written__read

/* Metric set SamplerBalance :: FS Duration */
static uint64_t
hsw__sampler_balance__ps_duration__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 27 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 28 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 27];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 28];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Metric set SamplerBalance :: VS Duration */
static uint64_t
hsw__sampler_balance__vs_duration__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 2 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 3 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 2];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 3];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Metric set SamplerBalance :: GS Duration */
static uint64_t
hsw__sampler_balance__gs_duration__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 22 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 23 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 22];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 23];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Metric set SamplerBalance :: TES Duration */
static uint64_t
hsw__sampler_balance__ds_duration__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 12 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 13 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 12];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 13];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Metric set SamplerBalance :: TCS Duration */
static uint64_t
hsw__sampler_balance__hs_duration__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 8 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 8];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Metric set SamplerBalance :: CS Duration */
static uint64_t
hsw__sampler_balance__cs_duration__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 17 READ  A 0 READ UMUL  A 2 READ  A 7 READ UADD  A 12 READ UADD  A 17 READ UADD  A 22 READ UADD  A 27 READ UADD UDIV  A 18 READ  A 1 READ UMUL  A 3 READ  A 8 READ UADD  A 13 READ UADD  A 18 READ UADD  A 23 READ UADD  A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];
   uint64_t tmp1 = results->accumulator[query->a_offset + 0];
   uint64_t tmp2 = tmp0 * tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 2];
   uint64_t tmp4 = results->accumulator[query->a_offset + 7];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->a_offset + 12];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->a_offset + 17];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 22];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 27];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = tmp2;
   uint64_t tmp15 = tmp13;
   uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0;
   uint64_t tmp17 = results->accumulator[query->a_offset + 18];
   uint64_t tmp18 = results->accumulator[query->a_offset + 1];
   uint64_t tmp19 = tmp17 * tmp18;
   uint64_t tmp20 = results->accumulator[query->a_offset + 3];
   uint64_t tmp21 = results->accumulator[query->a_offset + 8];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->a_offset + 13];
   uint64_t tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 18];
   uint64_t tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 23];
   uint64_t tmp28 = tmp26 + tmp27;
   uint64_t tmp29 = results->accumulator[query->a_offset + 28];
   uint64_t tmp30 = tmp28 + tmp29;
   uint64_t tmp31 = tmp19;
   uint64_t tmp32 = tmp30;
   uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0;
   uint64_t tmp34 = tmp16 + tmp33;
   uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, results);
   uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;
   uint64_t tmp37 = tmp36 * 1000;
   uint64_t tmp38 = tmp35;
   uint64_t tmp39 = tmp37;
   uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0;

   return tmp40;
}

/* Metric set SamplerBalance :: EU Idle */
static float
hsw__sampler_balance__eu_idle__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: 100 $EuActive $EuStall FADD FSUB */
   double tmp0 = hsw__sampler_balance__eu_active__read(perf, query, results) + hsw__sampler_balance__eu_stall__read(perf, query, results);
   double tmp1 = 100 - tmp0;

   return tmp1;
}

/* Metric set SamplerBalance :: Sampler L2 cache misses */
static uint64_t
hsw__sampler_balance__sampler_l2_cache_misses__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ UADD C 5 READ UADD C 4 READ UADD C 3 READ UADD C 2 READ UADD C 1 READ UADD C 0 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 3];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->c_offset + 2];
   uint64_t tmp10 = tmp8 + tmp9;
   uint64_t tmp11 = results->accumulator[query->c_offset + 1];
   uint64_t tmp12 = tmp10 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 0];
   uint64_t tmp14 = tmp12 + tmp13;

   return tmp14;
}

/* Metric set SamplerBalance :: Sampler L2 cache misses (ss0) */
static uint64_t
hsw__sampler_balance__sampler0_l2_cache_misses__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Metric set SamplerBalance :: Sampler L2 cache misses (ss1) */
static uint64_t
hsw__sampler_balance__sampler1_l2_cache_misses__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ C 4 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = results->accumulator[query->c_offset + 4];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Metric set SamplerBalance :: Sampler L2 cache misses (ss2) */
static uint64_t
hsw__sampler_balance__sampler2_l2_cache_misses__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ C 2 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Metric set SamplerBalance :: Sampler L2 cache misses (ss3) */
static uint64_t
hsw__sampler_balance__sampler3_l2_cache_misses__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ C 0 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 0];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Metric set SamplerBalance :: LLC GPU Accesses */
#define hsw__sampler_balance__llc_accesses__read \
   hsw__render_basic__llc_accesses__read

/* Metric set SamplerBalance :: LLC GPU Hits */
#define hsw__sampler_balance__llc_hits__read \
   hsw__render_basic__llc_hits__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define bdw__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
static uint64_t
bdw__render_basic__gpu_core_clocks__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];

   return tmp0;
}

/* Render Metrics Basic set :: AVG GPU Core Frequency */
static uint64_t
bdw__render_basic__avg_gpu_core_frequency__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */
   uint64_t tmp0 = bdw__render_basic__gpu_core_clocks__read(perf, query, results) * 1000000000;
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = bdw__render_basic__gpu_time__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define bdw__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
static uint64_t
bdw__render_basic__vs_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 1 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 1];

   return tmp0;
}

/* Render Metrics Basic set :: HS Threads Dispatched */
static uint64_t
bdw__render_basic__hs_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 2 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 2];

   return tmp0;
}

/* Render Metrics Basic set :: DS Threads Dispatched */
static uint64_t
bdw__render_basic__ds_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 3 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 3];

   return tmp0;
}

/* Render Metrics Basic set :: GS Threads Dispatched */
#define bdw__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
static uint64_t
bdw__render_basic__ps_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 6 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 6];

   return tmp0;
}

/* Render Metrics Basic set :: CS Threads Dispatched */
static uint64_t
bdw__render_basic__cs_threads__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: A 4 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 4];

   return tmp0;
}

/* Render Metrics Basic set :: GPU Busy */
static float
bdw__render_basic__gpu_busy__read(UNUSED struct intel_perf_config *perf,
                                  const struct intel_perf_query_info *query,
                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: A 0 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 0];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: EU Active */
static float
bdw__render_basic__eu_active__read(UNUSED struct intel_perf_config *perf,
                                   const struct intel_perf_query_info *query,
                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: EU Stall */
static float
bdw__render_basic__eu_stall__read(UNUSED struct intel_perf_config *perf,
                                  const struct intel_perf_query_info *query,
                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 8];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
static float
bdw__render_basic__eu_fpu_both_active__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: A 9 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 9];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
static float
bdw__render_basic__vs_fpu0_active__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 10 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 10];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
static float
bdw__render_basic__vs_fpu1_active__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 11 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 11];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: VS Send Pipe Active */
static float
bdw__render_basic__vs_send_active__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 12];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
static float
bdw__render_basic__ps_fpu0_active__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 15 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 15];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
static float
bdw__render_basic__ps_fpu1_active__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 16 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 16];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: PS Send Pipeline Active */
static float
bdw__render_basic__ps_send_active__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: FS Both FPU Active */
static float
bdw__render_basic__ps_eu_both_fpu_active__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 18];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Render Metrics Basic set :: Sampler 0 Busy */
static float
bdw__render_basic__sampler0_busy__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: Sampler 1 Busy */
static float
bdw__render_basic__sampler1_busy__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: Samplers Busy */
static float
bdw__render_basic__samplers_busy__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: $Sampler0Busy $Sampler1Busy FMAX */
   double tmp0 = bdw__render_basic__sampler0_busy__read(perf, query, results);
   double tmp1 = bdw__render_basic__sampler1_busy__read(perf, query, results);
   double tmp2 = MAX(tmp0, tmp1);

   return tmp2;
}

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
static float
bdw__render_basic__sampler0_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
static float
bdw__render_basic__sampler1_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics Basic set :: Samples Written */
static uint64_t
bdw__render_basic__samples_written__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 26 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 26];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Samples Blended */
static uint64_t
bdw__render_basic__samples_blended__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 27 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 27];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Sampler Texels */
static uint64_t
bdw__render_basic__sampler_texels__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 28 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 28];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Sampler Texels Misses */
static uint64_t
bdw__render_basic__sampler_texel_misses__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: A 29 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 29];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Sampler Cache Misses */
static uint64_t
bdw__render_basic__sampler_l1_misses__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ UADD 8 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 8;

   return tmp3;
}

/* Render Metrics Basic set :: Rasterized Pixels */
static uint64_t
bdw__render_basic__rasterized_pixels__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: A 21 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 21];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
static uint64_t
bdw__render_basic__hi_depth_test_fails__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: A 22 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 22];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Early Depth Test Fails */
static uint64_t
bdw__render_basic__early_depth_test_fails__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: A 23 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 23];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Samples Killed in FS */
static uint64_t
bdw__render_basic__samples_killed_in_ps__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: A 24 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 24];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: Pixels Failing Tests */
static uint64_t
bdw__render_basic__pixels_failing_post_ps_tests__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 25 READ 4 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 25];
   uint64_t tmp1 = tmp0 * 4;

   return tmp1;
}

/* Render Metrics Basic set :: SLM Bytes Read */
static uint64_t
bdw__render_basic__slm_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 30 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 30];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: SLM Bytes Read */
static uint64_t
bdw__render_basic__slm_bytes_read__max(struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 64 UMUL $EuSubslicesTotalCount UMUL */
   uint64_t tmp0 = bdw__render_basic__gpu_core_clocks__read(perf, query, results) * 64;
   uint64_t tmp1 = tmp0 * perf->sys_vars.n_eu_sub_slices;

   return tmp1;
}

/* Render Metrics Basic set :: SLM Bytes Written */
static uint64_t
bdw__render_basic__slm_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: A 31 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 31];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: SLM Bytes Written */
#define bdw__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
static uint64_t
bdw__render_basic__shader_memory_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: A 32 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 32];

   return tmp0;
}

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
static uint64_t
bdw__render_basic__shader_atomics__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 34 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 34];

   return tmp0;
}

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
static uint64_t
bdw__render_basic__l3_lookups__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */
   uint64_t tmp0 = bdw__render_basic__sampler_l1_misses__read(perf, query, results) + bdw__render_basic__shader_memory_accesses__read(perf, query, results);

   return tmp0;
}

/* Render Metrics Basic set :: L3 Misses */
#define bdw__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
static uint64_t
bdw__render_basic__l3_sampler_throughput__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: $SamplerL1Misses 64 UMUL */
   uint64_t tmp0 = bdw__render_basic__sampler_l1_misses__read(perf, query, results) * 64;

   return tmp0;
}

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define bdw__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: L3 Shader Throughput */
static uint64_t
bdw__render_basic__l3_shader_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: A 30 READ  A 31 READ $ShaderMemoryAccesses UADD UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 30];
   uint64_t tmp1 = results->accumulator[query->a_offset + 31];
   uint64_t tmp2 = tmp1 + bdw__render_basic__shader_memory_accesses__read(perf, query, results);
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = tmp3 * 64;

   return tmp4;
}

/* Render Metrics Basic set :: L3 Shader Throughput */
static uint64_t
bdw__render_basic__l3_shader_throughput__max(struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 64 UMUL 2 UMUL $EuSubslicesTotalCount UMUL */
   uint64_t tmp0 = bdw__render_basic__gpu_core_clocks__read(perf, query, results) * 64;
   uint64_t tmp1 = tmp0 * 2;
   uint64_t tmp2 = tmp1 * perf->sys_vars.n_eu_sub_slices;

   return tmp2;
}

/* Render Metrics Basic set :: Shader Barrier Messages */
#define bdw__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
static uint64_t
bdw__render_basic__gti_vf_throughput__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ B 7 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 64;

   return tmp3;
}

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
static uint64_t
bdw__render_basic__gti_vf_throughput__max(struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 64 UMUL */
   uint64_t tmp0 = bdw__render_basic__gpu_core_clocks__read(perf, query, results) * 64;

   return tmp0;
}

/* Render Metrics Basic set :: GTI Depth Throughput */
static uint64_t
bdw__render_basic__gti_depth_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ C 1 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 64;

   return tmp3;
}

/* Render Metrics Basic set :: GTI Depth Throughput */
static uint64_t
bdw__render_basic__gti_depth_throughput__max(struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 64 UMUL $EuSlicesTotalCount UMUL */
   uint64_t tmp0 = bdw__render_basic__gpu_core_clocks__read(perf, query, results) * 64;
   uint64_t tmp1 = tmp0 * perf->sys_vars.n_eu_slices;

   return tmp1;
}

/* Render Metrics Basic set :: GTI RCC Throughput */
static uint64_t
bdw__render_basic__gti_rcc_throughput__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: C 2 READ C 3 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 2];
   uint64_t tmp1 = results->accumulator[query->c_offset + 3];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 64;

   return tmp3;
}

/* Render Metrics Basic set :: GTI RCC Throughput */
#define bdw__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define bdw__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define bdw__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
static uint64_t
bdw__render_basic__gti_hdc_lookups_throughput__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define bdw__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
static uint64_t
bdw__render_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: GTI Read Throughput */
#define bdw__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define bdw__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
static uint64_t
bdw__render_basic__gti_write_throughput__max(struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 32 UMUL */
   uint64_t tmp0 = bdw__render_basic__gpu_core_clocks__read(perf, query, results) * 32;

   return tmp0;
}

/* Render Metrics Basic set :: Samplers Bottleneck */
static float
bdw__render_basic__sampler_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: $Sampler0Bottleneck $Sampler1Bottleneck FMAX */
   double tmp0 = bdw__render_basic__sampler0_bottleneck__read(perf, query, results);
   double tmp1 = bdw__render_basic__sampler1_bottleneck__read(perf, query, results);
   double tmp2 = MAX(tmp0, tmp1);

   return tmp2;
}

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define bdw__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define bdw__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define bdw__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define bdw__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define bdw__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define bdw__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define bdw__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define bdw__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define bdw__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define bdw__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define bdw__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define bdw__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define bdw__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define bdw__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define bdw__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define bdw__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
static float
bdw__compute_basic__eu_avg_ipc_rate__read(UNUSED struct intel_perf_config *perf,
                                          const struct intel_perf_query_info *query,
                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: A 9 READ  A 10 READ  A 11 READ UADD  A 9 READ USUB FDIV 1 FADD */
   uint64_t tmp0 = results->accumulator[query->a_offset + 9];
   uint64_t tmp1 = results->accumulator[query->a_offset + 10];
   uint64_t tmp2 = results->accumulator[query->a_offset + 11];
   uint64_t tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = results->accumulator[query->a_offset + 9];
   uint64_t tmp5 = tmp3 - tmp4;
   double tmp6 = tmp0;
   double tmp7 = tmp5;
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;
   double tmp9 = tmp8 + 1;

   return tmp9;
}

/* Compute Metrics Basic set :: EU AVG IPC Rate */
static float
bdw__compute_basic__eu_avg_ipc_rate__max(struct intel_perf_config *perf,
                                          const struct intel_perf_query_info *query,
                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 */

   return 2;
}

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define bdw__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
static float
bdw__compute_basic__eu_thread_occupancy__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: A 13 READ 8 UMUL $EuCoresTotalCount UDIV $EuThreadsCount UDIV 100 UMUL  $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 13];
   uint64_t tmp1 = tmp0 * 8;
   uint64_t tmp2 = tmp1;
   uint64_t tmp3 = perf->sys_vars.n_eus;
   uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0;
   uint64_t tmp5 = tmp4;
   uint64_t tmp6 = perf->devinfo.num_thread_per_eu;
   uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0;
   uint64_t tmp8 = tmp7 * 100;
   double tmp9 = tmp8;
   double tmp10 = bdw__compute_basic__gpu_core_clocks__read(perf, query, results);
   double tmp11 = tmp10 ? tmp9 / tmp10 : 0;

   return tmp11;
}

/* Compute Metrics Basic set :: Rasterized Pixels */
#define bdw__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define bdw__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define bdw__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define bdw__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define bdw__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define bdw__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define bdw__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define bdw__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define bdw__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define bdw__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define bdw__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define bdw__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define bdw__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define bdw__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define bdw__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define bdw__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define bdw__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__l3_shader_throughput__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define bdw__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
static uint64_t
bdw__compute_basic__typed_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ B 2 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = results->accumulator[query->b_offset + 2];
   uint64_t tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = tmp0 + tmp3;
   uint64_t tmp5 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp6 = tmp4 * tmp5;

   return tmp6;
}

/* Compute Metrics Basic set :: Typed Bytes Read */
#define bdw__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
static uint64_t
bdw__compute_basic__typed_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ B 4 READ B 5 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = results->accumulator[query->b_offset + 5];
   uint64_t tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = tmp0 + tmp3;
   uint64_t tmp5 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp6 = tmp4 * tmp5;

   return tmp6;
}

/* Compute Metrics Basic set :: Typed Bytes Written */
#define bdw__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
static uint64_t
bdw__compute_basic__untyped_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ B 7 READ C 0 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = results->accumulator[query->c_offset + 0];
   uint64_t tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = tmp0 + tmp3;
   uint64_t tmp5 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp6 = tmp4 * tmp5;

   return tmp6;
}

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define bdw__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
static uint64_t
bdw__compute_basic__untyped_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ C 2 READ C 3 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = results->accumulator[query->c_offset + 3];
   uint64_t tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = tmp0 + tmp3;
   uint64_t tmp5 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp6 = tmp4 * tmp5;

   return tmp6;
}

/* Compute Metrics Basic set :: Untyped Writes */
#define bdw__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define bdw__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define bdw__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define bdw__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define bdw__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define bdw__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define bdw__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define bdw__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define bdw__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define bdw__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VS Threads Dispatched */
#define bdw__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics for 3D Pipeline Profile :: HS Threads Dispatched */
#define bdw__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics for 3D Pipeline Profile :: DS Threads Dispatched */
#define bdw__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics for 3D Pipeline Profile :: GS Threads Dispatched */
#define bdw__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics for 3D Pipeline Profile :: FS Threads Dispatched */
#define bdw__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics for 3D Pipeline Profile :: CS Threads Dispatched */
#define bdw__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics for 3D Pipeline Profile :: EU Active */
#define bdw__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics for 3D Pipeline Profile :: EU Stall */
#define bdw__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics for 3D Pipeline Profile :: Rasterized Pixels */
#define bdw__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define bdw__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics for 3D Pipeline Profile :: Early Depth Test Fails */
#define bdw__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics for 3D Pipeline Profile :: Samples Killed in FS */
#define bdw__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics for 3D Pipeline Profile :: Pixels Failing Tests */
#define bdw__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics for 3D Pipeline Profile :: Samples Written */
#define bdw__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics for 3D Pipeline Profile :: Samples Blended */
#define bdw__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics for 3D Pipeline Profile :: Sampler Accesses */
static uint64_t
bdw__render_pipe_profile__sampler_accesses__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: A 28 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 28];

   return tmp0;
}

/* Render Metrics for 3D Pipeline Profile :: Sampler Texels */
#define bdw__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics for 3D Pipeline Profile :: Sampler Texels Misses */
#define bdw__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */
#define bdw__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */
#define bdw__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */
#define bdw__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */
#define bdw__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics for 3D Pipeline Profile :: Shader Memory Accesses */
#define bdw__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define bdw__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */
#define bdw__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */
#define bdw__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__l3_shader_throughput__max

/* Render Metrics for 3D Pipeline Profile :: Shader Barrier Messages */
#define bdw__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics for 3D Pipeline Profile :: VF Bottleneck */
static float
bdw__render_pipe_profile__vf_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: VS Bottleneck */
#define bdw__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: HS Bottleneck */
#define bdw__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics for 3D Pipeline Profile :: DS Bottleneck */
#define bdw__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: GS Bottleneck */
#define bdw__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO Bottleneck */
static float
bdw__render_pipe_profile__so_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: Clipper Bottleneck */
static float
bdw__render_pipe_profile__cl_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: Strip-Fans Bottleneck */
static float
bdw__render_pipe_profile__sf_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth Bottleneck */
static float
bdw__render_pipe_profile__hi_depth_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: Early Depth Bottleneck */
static float
bdw__render_pipe_profile__early_depth_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: BC Bottleneck */
static float
bdw__render_pipe_profile__bc_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: HS Stall */
static float
bdw__render_pipe_profile__hs_stall__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: DS Stall */
static float
bdw__render_pipe_profile__ds_stall__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 2 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 2];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: SO Stall */
static float
bdw__render_pipe_profile__so_stall__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: CL Stall */
static float
bdw__render_pipe_profile__cl_stall__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Render Metrics for 3D Pipeline Profile :: SF Stall */
static float
bdw__render_pipe_profile__sf_stall__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Memory Reads Distribution metric set :: GPU Time Elapsed */
#define bdw__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metric set :: GPU Core Clocks */
#define bdw__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metric set :: AVG GPU Core Frequency */
#define bdw__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metric set :: AVG GPU Core Frequency */
#define bdw__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metric set :: GPU Busy */
#define bdw__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metric set :: VS Threads Dispatched */
#define bdw__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metric set :: HS Threads Dispatched */
#define bdw__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metric set :: DS Threads Dispatched */
#define bdw__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metric set :: GS Threads Dispatched */
#define bdw__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metric set :: FS Threads Dispatched */
#define bdw__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metric set :: CS Threads Dispatched */
#define bdw__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metric set :: EU Active */
#define bdw__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metric set :: EU Stall */
#define bdw__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metric set :: Rasterized Pixels */
#define bdw__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metric set :: Early Hi-Depth Test Fails */
#define bdw__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metric set :: Early Depth Test Fails */
#define bdw__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metric set :: Samples Killed in FS */
#define bdw__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metric set :: Pixels Failing Tests */
#define bdw__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metric set :: Samples Written */
#define bdw__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metric set :: Samples Blended */
#define bdw__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metric set :: Sampler Texels */
#define bdw__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metric set :: Sampler Texels Misses */
#define bdw__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metric set :: SLM Bytes Read */
#define bdw__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metric set :: SLM Bytes Read */
#define bdw__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metric set :: SLM Bytes Written */
#define bdw__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metric set :: SLM Bytes Written */
#define bdw__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metric set :: Shader Memory Accesses */
#define bdw__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metric set :: Shader Atomic Memory Accesses */
#define bdw__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metric set :: Shader Barrier Messages */
#define bdw__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metric set :: L3 Shader Throughput */
#define bdw__memory_reads__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Reads Distribution metric set :: L3 Shader Throughput */
#define bdw__memory_reads__l3_shader_throughput__max \
   bdw__render_basic__l3_shader_throughput__max

/* Memory Reads Distribution metric set :: GtiCmdStreamerMemoryReads */
#define bdw__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metric set :: GtiRsMemoryReads */
#define bdw__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metric set :: GtiVfMemoryReads */
#define bdw__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metric set :: GtiRccMemoryReads */
#define bdw__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metric set :: GtiMscMemoryReads */
#define bdw__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metric set :: GtiHizMemoryReads */
#define bdw__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metric set :: GtiStcMemoryReads */
#define bdw__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metric set :: GtiRczMemoryReads */
#define bdw__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metric set :: GtiMemoryReads */
#define bdw__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metric set :: GtiL3Bank0Reads */
#define bdw__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metric set :: GtiL3Bank1Reads */
#define bdw__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metric set :: GtiL3Bank2Reads */
#define bdw__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metric set :: GtiL3Bank3Reads */
#define bdw__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metric set :: GtiL3Reads */
static uint64_t
bdw__memory_reads__gti_l3_reads__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: $GtiL3Bank0Reads $GtiL3Bank1Reads $GtiL3Bank2Reads $GtiL3Bank3Reads UADD UADD UADD */
   uint64_t tmp0 = bdw__memory_reads__gti_l3_bank2_reads__read(perf, query, results) + bdw__memory_reads__gti_l3_bank3_reads__read(perf, query, results);
   uint64_t tmp1 = bdw__memory_reads__gti_l3_bank1_reads__read(perf, query, results) + tmp0;
   uint64_t tmp2 = bdw__memory_reads__gti_l3_bank0_reads__read(perf, query, results) + tmp1;

   return tmp2;
}

/* Memory Reads Distribution metric set :: GtiRingAccesses */
static uint64_t
bdw__memory_reads__gti_ring_accesses__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Memory Writes Distribution metric set :: GPU Time Elapsed */
#define bdw__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metric set :: GPU Core Clocks */
#define bdw__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metric set :: AVG GPU Core Frequency */
#define bdw__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metric set :: AVG GPU Core Frequency */
#define bdw__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metric set :: GPU Busy */
#define bdw__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metric set :: VS Threads Dispatched */
#define bdw__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metric set :: HS Threads Dispatched */
#define bdw__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metric set :: DS Threads Dispatched */
#define bdw__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metric set :: GS Threads Dispatched */
#define bdw__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metric set :: FS Threads Dispatched */
#define bdw__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metric set :: CS Threads Dispatched */
#define bdw__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metric set :: EU Active */
#define bdw__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metric set :: EU Stall */
#define bdw__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metric set :: Rasterized Pixels */
#define bdw__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metric set :: Early Hi-Depth Test Fails */
#define bdw__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metric set :: Early Depth Test Fails */
#define bdw__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metric set :: Samples Killed in FS */
#define bdw__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metric set :: Pixels Failing Tests */
#define bdw__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metric set :: Samples Written */
#define bdw__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metric set :: Samples Blended */
#define bdw__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metric set :: Sampler Texels */
#define bdw__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metric set :: Sampler Texels Misses */
#define bdw__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metric set :: SLM Bytes Read */
#define bdw__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metric set :: SLM Bytes Read */
#define bdw__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metric set :: SLM Bytes Written */
#define bdw__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metric set :: SLM Bytes Written */
#define bdw__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metric set :: Shader Memory Accesses */
#define bdw__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metric set :: Shader Atomic Memory Accesses */
#define bdw__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metric set :: L3 Shader Throughput */
#define bdw__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metric set :: L3 Shader Throughput */
#define bdw__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__l3_shader_throughput__max

/* Memory Writes Distribution metric set :: Shader Barrier Messages */
#define bdw__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metric set :: GtiCmdStreamerMemoryWrites */
#define bdw__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metric set :: GtiSoMemoryWrites */
#define bdw__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metric set :: GtiRccMemoryWrites */
#define bdw__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metric set :: GtiMscMemoryWrites */
#define bdw__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metric set :: GtiHizMemoryWrites */
#define bdw__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metric set :: GtiStcMemoryWrites */
#define bdw__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metric set :: GtiRczMemoryWrites */
#define bdw__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metric set :: GtiMemoryWrites */
#define bdw__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metric set :: GtiL3Bank0Writes */
#define bdw__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metric set :: GtiL3Bank1Writes */
#define bdw__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metric set :: GtiL3Bank2Writes */
#define bdw__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metric set :: GtiL3Bank3Writes */
#define bdw__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metric set :: GtiL3Writes */
#define bdw__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metric set :: GtiRingAccesses */
#define bdw__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended metric set :: GPU Time Elapsed */
#define bdw__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended metric set :: GPU Core Clocks */
#define bdw__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended metric set :: AVG GPU Core Frequency */
#define bdw__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended metric set :: AVG GPU Core Frequency */
#define bdw__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended metric set :: CS Threads Dispatched */
#define bdw__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended metric set :: EU Active */
#define bdw__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended metric set :: EU Stall */
#define bdw__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended metric set :: EU Both FPU Pipes Active */
#define bdw__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended metric set :: EU FPU0 Pipe Active */
#define bdw__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended metric set :: EU FPU1 Pipe Active */
#define bdw__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended metric set :: EU AVG IPC Rate */
#define bdw__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended metric set :: EU AVG IPC Rate */
#define bdw__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended metric set :: EU Send Pipe Active */
#define bdw__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended metric set :: EU Thread Occupancy */
#define bdw__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended metric set :: Sampler Texels */
#define bdw__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended metric set :: Sampler Texels Misses */
#define bdw__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended metric set :: SLM Bytes Read */
#define bdw__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended metric set :: SLM Bytes Read */
#define bdw__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended metric set :: SLM Bytes Written */
#define bdw__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended metric set :: SLM Bytes Written */
#define bdw__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended metric set :: Shader Memory Accesses */
#define bdw__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended metric set :: Shader Atomic Memory Accesses */
#define bdw__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended metric set :: L3 Shader Throughput */
#define bdw__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended metric set :: L3 Shader Throughput */
#define bdw__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__l3_shader_throughput__max

/* Compute Metrics Extended metric set :: Shader Barrier Messages */
#define bdw__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended metric set :: EuUntypedReads0 */
#define bdw__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended metric set :: EuTypedReads0 */
#define bdw__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended metric set :: EuUntypedWrites0 */
#define bdw__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended metric set :: EuTypedWrites0 */
#define bdw__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended metric set :: EuUntypedAtomics0 */
#define bdw__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended metric set :: EuTypedAtomics0 */
#define bdw__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended metric set :: EuA64UntypedReads0 */
#define bdw__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended metric set :: EuA64UntypedWrites0 */
#define bdw__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended metric set :: Typed Reads 0 */
#define bdw__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended metric set :: Typed Writes 0 */
#define bdw__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended metric set :: Untyped Reads 0 */
#define bdw__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended metric set :: Untyped Writes 0 */
#define bdw__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended metric set :: Typed Atomics 0 */
#define bdw__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended metric set :: TypedReadsPerCacheLine */
#define bdw__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended metric set :: TypedWritesPerCacheLine */
#define bdw__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended metric set :: UntypedReadsPerCacheLine */
static float
bdw__compute_extended__untyped_reads_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                          const struct intel_perf_query_info *query,
                                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuUntypedReads0 $EuA64UntypedReads0 UADD $UntypedReads0 FDIV */
   uint64_t tmp0 = bdw__compute_extended__eu_untyped_reads0__read(perf, query, results) + bdw__compute_extended__eu_a64_untyped_reads0__read(perf, query, results);
   double tmp1 = tmp0;
   double tmp2 = bdw__compute_extended__untyped_reads0__read(perf, query, results);
   double tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Compute Metrics Extended metric set :: UntypedWritesPerCacheLine */
static float
bdw__compute_extended__untyped_writes_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuUntypedWrites0 $EuA64UntypedWrites0 UADD $UntypedWrites0 FDIV */
   uint64_t tmp0 = bdw__compute_extended__eu_untyped_writes0__read(perf, query, results) + bdw__compute_extended__eu_a64_untyped_writes0__read(perf, query, results);
   double tmp1 = tmp0;
   double tmp2 = bdw__compute_extended__untyped_writes0__read(perf, query, results);
   double tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Compute Metrics Extended metric set :: TypedAtomicsPerCacheLine */
#define bdw__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache metric set :: GPU Time Elapsed */
#define bdw__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache metric set :: GPU Core Clocks */
#define bdw__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache metric set :: AVG GPU Core Frequency */
#define bdw__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache metric set :: AVG GPU Core Frequency */
#define bdw__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache metric set :: GPU Busy */
#define bdw__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache metric set :: VS Threads Dispatched */
#define bdw__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metric set :: HS Threads Dispatched */
#define bdw__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache metric set :: DS Threads Dispatched */
#define bdw__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache metric set :: GS Threads Dispatched */
#define bdw__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metric set :: FS Threads Dispatched */
#define bdw__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache metric set :: CS Threads Dispatched */
#define bdw__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache metric set :: EU Active */
#define bdw__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache metric set :: EU Stall */
#define bdw__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache metric set :: EU Both FPU Pipes Active */
#define bdw__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU0 Pipe Active */
#define bdw__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU1 Pipe Active */
#define bdw__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache metric set :: EU AVG IPC Rate */
#define bdw__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache metric set :: EU AVG IPC Rate */
#define bdw__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache metric set :: EU Send Pipe Active */
#define bdw__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU0 Hybrid Instruction */
static float
bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read(UNUSED struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 13];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Compute Metrics L3 Cache metric set :: EU FPU1 Hybrid Instruction */
static float
bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read(UNUSED struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 14 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 14];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Compute Metrics L3 Cache metric set :: EU FPU0 Ternary Instruction */
#define bdw__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU1 Ternary Instruction */
#define bdw__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU0 Binary Instruction */
#define bdw__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU1 Binary Instruction */
#define bdw__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU0 Move Instruction */
static float
bdw__compute_l3_cache__eu_move_fpu0_instruction__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 19 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 19];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Compute Metrics L3 Cache metric set :: EU FPU1 Move Instruction */
static float
bdw__compute_l3_cache__eu_move_fpu1_instruction__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 20 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 20];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = perf->sys_vars.n_eus;
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;
   uint64_t tmp4 = tmp3 * 100;
   double tmp5 = tmp4;
   double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(perf, query, results);
   double tmp7 = tmp6 ? tmp5 / tmp6 : 0;

   return tmp7;
}

/* Compute Metrics L3 Cache metric set :: Rasterized Pixels */
#define bdw__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache metric set :: Early Hi-Depth Test Fails */
#define bdw__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache metric set :: Early Depth Test Fails */
#define bdw__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metric set :: Samples Killed in FS */
#define bdw__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache metric set :: Pixels Failing Tests */
#define bdw__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache metric set :: Samples Written */
#define bdw__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache metric set :: Samples Blended */
#define bdw__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache metric set :: Sampler Texels */
#define bdw__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache metric set :: Sampler Texels Misses */
#define bdw__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache metric set :: SLM Bytes Read */
#define bdw__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache metric set :: SLM Bytes Read */
#define bdw__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metric set :: SLM Bytes Written */
#define bdw__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache metric set :: SLM Bytes Written */
#define bdw__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metric set :: Shader Memory Accesses */
#define bdw__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache metric set :: Shader Atomic Memory Accesses */
#define bdw__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache metric set :: L3 Accesses */
static uint64_t
bdw__compute_l3_cache__l3_accesses__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ C 1 READ B 2 READ B 3 READ C 2 READ C 3 READ B 6 READ B 7 READ UADD UADD UADD UADD UADD UADD UADD 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   uint64_t tmp2 = results->accumulator[query->b_offset + 2];
   uint64_t tmp3 = results->accumulator[query->b_offset + 3];
   uint64_t tmp4 = results->accumulator[query->c_offset + 2];
   uint64_t tmp5 = results->accumulator[query->c_offset + 3];
   uint64_t tmp6 = results->accumulator[query->b_offset + 6];
   uint64_t tmp7 = results->accumulator[query->b_offset + 7];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = tmp5 + tmp8;
   uint64_t tmp10 = tmp4 + tmp9;
   uint64_t tmp11 = tmp3 + tmp10;
   uint64_t tmp12 = tmp2 + tmp11;
   uint64_t tmp13 = tmp1 + tmp12;
   uint64_t tmp14 = tmp0 + tmp13;
   uint64_t tmp15 = tmp14 * 2;

   return tmp15;
}

/* Compute Metrics L3 Cache metric set :: L3 Misses */
static uint64_t
bdw__compute_l3_cache__l3_misses__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ C 5 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Compute Metrics L3 Cache metric set :: L3 Shader Throughput */
#define bdw__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache metric set :: L3 Shader Throughput */
#define bdw__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__l3_shader_throughput__max

/* Compute Metrics L3 Cache metric set :: L3 Total Throughput */
static uint64_t
bdw__compute_l3_cache__l3_total_throughput__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: $L3Accesses 64 UMUL */
   uint64_t tmp0 = bdw__compute_l3_cache__l3_accesses__read(perf, query, results) * 64;

   return tmp0;
}

/* Compute Metrics L3 Cache metric set :: L3 Total Throughput */
#define bdw__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metric set :: Shader Barrier Messages */
#define bdw__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metric set :: L3 Bank 00 Accesses */
static uint64_t
bdw__compute_l3_cache__l3_bank00_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 01 Accesses */
static uint64_t
bdw__compute_l3_cache__l3_bank01_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 02 Accesses */
static uint64_t
bdw__compute_l3_cache__l3_bank02_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 03 Accesses */
static uint64_t
bdw__compute_l3_cache__l3_bank03_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 10 Accesses */
static uint64_t
bdw__compute_l3_cache__l3_bank10_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 2 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 2];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 11 Accesses */
#define bdw__compute_l3_cache__l3_bank11_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics L3 Cache metric set :: L3 Bank 12 Accesses */
static uint64_t
bdw__compute_l3_cache__l3_bank12_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 13 Accesses */
static uint64_t
bdw__compute_l3_cache__l3_bank13_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 00 IC Accesses */
static uint64_t
bdw__compute_l3_cache__l3_bank00_ic_accesses__read(UNUSED struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ UADD 2 UMUL $L3Bank00Accesses UMIN */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 2;
   uint64_t tmp4 = MIN(tmp3, bdw__compute_l3_cache__l3_bank00_accesses__read(perf, query, results));

   return tmp4;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 00 IC Hits */
static uint64_t
bdw__compute_l3_cache__l3_bank00_ic_hits__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ 2 UMUL $L3Bank00IcAccesses UMIN */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = tmp0 * 2;
   uint64_t tmp2 = MIN(tmp1, bdw__compute_l3_cache__l3_bank00_ic_accesses__read(perf, query, results));

   return tmp2;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 10 IC Accesses */
static uint64_t
bdw__compute_l3_cache__l3_bank10_ic_accesses__read(UNUSED struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ UADD 2 UMUL $L3Bank10Accesses UMIN */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 2;
   uint64_t tmp4 = MIN(tmp3, bdw__compute_l3_cache__l3_bank10_accesses__read(perf, query, results));

   return tmp4;
}

/* Compute Metrics L3 Cache metric set :: L3 Bank 10 IC Hits */
static uint64_t
bdw__compute_l3_cache__l3_bank10_ic_hits__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ 2 UMUL $L3Bank10IcAccesses UMIN */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = tmp0 * 2;
   uint64_t tmp2 = MIN(tmp1, bdw__compute_l3_cache__l3_bank10_ic_accesses__read(perf, query, results));

   return tmp2;
}

/* Compute Metrics L3 Cache metric set :: GTI L3 Throughput */
static uint64_t
bdw__compute_l3_cache__gti_l3_throughput__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ C 5 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 64;

   return tmp3;
}

/* Compute Metrics L3 Cache metric set :: GTI L3 Throughput */
#define bdw__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metric set :: GTI Read Throughput */
#define bdw__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache metric set :: GTI Read Throughput */
#define bdw__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache metric set :: GTI Write Throughput */
#define bdw__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache metric set :: GTI Write Throughput */
#define bdw__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Data Port Reads Coalescing metric set :: GPU Time Elapsed */
#define bdw__data_port_reads_coalescing__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Data Port Reads Coalescing metric set :: GPU Core Clocks */
#define bdw__data_port_reads_coalescing__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Data Port Reads Coalescing metric set :: AVG GPU Core Frequency */
#define bdw__data_port_reads_coalescing__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Data Port Reads Coalescing metric set :: AVG GPU Core Frequency */
#define bdw__data_port_reads_coalescing__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Data Port Reads Coalescing metric set :: VS Threads Dispatched */
#define bdw__data_port_reads_coalescing__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Data Port Reads Coalescing metric set :: HS Threads Dispatched */
#define bdw__data_port_reads_coalescing__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Data Port Reads Coalescing metric set :: DS Threads Dispatched */
#define bdw__data_port_reads_coalescing__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Data Port Reads Coalescing metric set :: GS Threads Dispatched */
#define bdw__data_port_reads_coalescing__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Data Port Reads Coalescing metric set :: FS Threads Dispatched */
#define bdw__data_port_reads_coalescing__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Data Port Reads Coalescing metric set :: CS Threads Dispatched */
#define bdw__data_port_reads_coalescing__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Data Port Reads Coalescing metric set :: EU Active */
#define bdw__data_port_reads_coalescing__eu_active__read \
   bdw__render_basic__eu_active__read

/* Data Port Reads Coalescing metric set :: EU Stall */
#define bdw__data_port_reads_coalescing__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Data Port Reads Coalescing metric set :: EU Both FPU Pipes Active */
#define bdw__data_port_reads_coalescing__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Data Port Reads Coalescing metric set :: EU FPU0 Pipe Active */
#define bdw__data_port_reads_coalescing__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Data Port Reads Coalescing metric set :: EU FPU1 Pipe Active */
#define bdw__data_port_reads_coalescing__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Data Port Reads Coalescing metric set :: EU AVG IPC Rate */
#define bdw__data_port_reads_coalescing__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Data Port Reads Coalescing metric set :: EU AVG IPC Rate */
#define bdw__data_port_reads_coalescing__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Data Port Reads Coalescing metric set :: EU Send Pipe Active */
#define bdw__data_port_reads_coalescing__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Data Port Reads Coalescing metric set :: EU Thread Occupancy */
#define bdw__data_port_reads_coalescing__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Data Port Reads Coalescing metric set :: Sampler Texels */
#define bdw__data_port_reads_coalescing__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Data Port Reads Coalescing metric set :: Sampler Texels Misses */
#define bdw__data_port_reads_coalescing__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Data Port Reads Coalescing metric set :: SLM Bytes Read */
#define bdw__data_port_reads_coalescing__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Data Port Reads Coalescing metric set :: SLM Bytes Read */
#define bdw__data_port_reads_coalescing__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Data Port Reads Coalescing metric set :: SLM Bytes Written */
#define bdw__data_port_reads_coalescing__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Data Port Reads Coalescing metric set :: SLM Bytes Written */
#define bdw__data_port_reads_coalescing__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Data Port Reads Coalescing metric set :: Shader Memory Accesses */
#define bdw__data_port_reads_coalescing__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Data Port Reads Coalescing metric set :: Shader Atomic Memory Accesses */
#define bdw__data_port_reads_coalescing__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Data Port Reads Coalescing metric set :: L3 Shader Throughput */
#define bdw__data_port_reads_coalescing__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Data Port Reads Coalescing metric set :: L3 Shader Throughput */
#define bdw__data_port_reads_coalescing__l3_shader_throughput__max \
   bdw__render_basic__l3_shader_throughput__max

/* Data Port Reads Coalescing metric set :: Shader Barrier Messages */
#define bdw__data_port_reads_coalescing__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Data Port Reads Coalescing metric set :: EU to Data Port 0 Reads 32 */
#define bdw__data_port_reads_coalescing__eu_hdc0_reads32_b__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Data Port Reads Coalescing metric set :: EU to Data Port 0 Reads 64 */
#define bdw__data_port_reads_coalescing__eu_hdc0_reads64_b__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Data Port Reads Coalescing metric set :: EU to Data Port 0 Reads 128 */
#define bdw__data_port_reads_coalescing__eu_hdc0_reads128_b__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Data Port Reads Coalescing metric set :: EU to Data Port 0 Reads 256 */
#define bdw__data_port_reads_coalescing__eu_hdc0_reads256_b__read \
   hsw__compute_extended__gpu_clocks__read

/* Data Port Reads Coalescing metric set :: Data Port 0 to L3 Data Reads */
#define bdw__data_port_reads_coalescing__hdc0_l3_data_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Data Port Reads Coalescing metric set :: Data Port 0 to L3 Data Writes */
#define bdw__data_port_reads_coalescing__hdc0_l3_data_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Data Port Reads Coalescing metric set :: All Data Port 0 Reads from L3 */
static uint64_t
bdw__data_port_reads_coalescing__hdc0_l3_reads__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ C 2 READ USUB */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = tmp0 - tmp1;

   return tmp2;
}

/* Data Port Reads Coalescing metric set :: All Data Port 0 Writes to L3 */
#define bdw__data_port_reads_coalescing__hdc0_l3_writes__read \
   hsw__render_basic__gpu_core_clocks__read

/* Data Port Reads Coalescing metric set :: EuBytesReadPerCacheLine */
static float
bdw__data_port_reads_coalescing__eu_bytes_read_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                                    const struct intel_perf_query_info *query,
                                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuHdc0Reads32B 32 UMUL $EuHdc0Reads64B 64 UMUL $EuHdc0Reads128B 128 UMUL $EuHdc0Reads256B 256 UMUL UADD UADD UADD $Hdc0L3DataReads FDIV */
   uint64_t tmp0 = bdw__data_port_reads_coalescing__eu_hdc0_reads32_b__read(perf, query, results) * 32;
   uint64_t tmp1 = bdw__data_port_reads_coalescing__eu_hdc0_reads64_b__read(perf, query, results) * 64;
   uint64_t tmp2 = bdw__data_port_reads_coalescing__eu_hdc0_reads128_b__read(perf, query, results) * 128;
   uint64_t tmp3 = bdw__data_port_reads_coalescing__eu_hdc0_reads256_b__read(perf, query, results) * 256;
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = tmp1 + tmp4;
   uint64_t tmp6 = tmp0 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = bdw__data_port_reads_coalescing__hdc0_l3_data_reads__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Data Port Reads Coalescing metric set :: EuDataReadsPerCacheLine */
static float
bdw__data_port_reads_coalescing__eu_data_reads_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                                    const struct intel_perf_query_info *query,
                                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuBytesReadPerCacheLine 64 FDIV */
   double tmp0 = bdw__data_port_reads_coalescing__eu_bytes_read_per_cache_line__read(perf, query, results);
   double tmp1 = 64;
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Data Port Writes Coalescing metric set :: GPU Time Elapsed */
#define bdw__data_port_writes_coalescing__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Data Port Writes Coalescing metric set :: GPU Core Clocks */
#define bdw__data_port_writes_coalescing__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Data Port Writes Coalescing metric set :: AVG GPU Core Frequency */
#define bdw__data_port_writes_coalescing__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Data Port Writes Coalescing metric set :: AVG GPU Core Frequency */
#define bdw__data_port_writes_coalescing__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Data Port Writes Coalescing metric set :: VS Threads Dispatched */
#define bdw__data_port_writes_coalescing__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Data Port Writes Coalescing metric set :: HS Threads Dispatched */
#define bdw__data_port_writes_coalescing__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Data Port Writes Coalescing metric set :: DS Threads Dispatched */
#define bdw__data_port_writes_coalescing__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Data Port Writes Coalescing metric set :: GS Threads Dispatched */
#define bdw__data_port_writes_coalescing__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Data Port Writes Coalescing metric set :: FS Threads Dispatched */
#define bdw__data_port_writes_coalescing__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Data Port Writes Coalescing metric set :: CS Threads Dispatched */
#define bdw__data_port_writes_coalescing__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Data Port Writes Coalescing metric set :: EU Active */
#define bdw__data_port_writes_coalescing__eu_active__read \
   bdw__render_basic__eu_active__read

/* Data Port Writes Coalescing metric set :: EU Stall */
#define bdw__data_port_writes_coalescing__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Data Port Writes Coalescing metric set :: EU Both FPU Pipes Active */
#define bdw__data_port_writes_coalescing__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Data Port Writes Coalescing metric set :: EU FPU0 Pipe Active */
#define bdw__data_port_writes_coalescing__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Data Port Writes Coalescing metric set :: EU FPU1 Pipe Active */
#define bdw__data_port_writes_coalescing__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Data Port Writes Coalescing metric set :: EU AVG IPC Rate */
#define bdw__data_port_writes_coalescing__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Data Port Writes Coalescing metric set :: EU AVG IPC Rate */
#define bdw__data_port_writes_coalescing__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Data Port Writes Coalescing metric set :: EU Send Pipe Active */
#define bdw__data_port_writes_coalescing__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Data Port Writes Coalescing metric set :: EU Thread Occupancy */
#define bdw__data_port_writes_coalescing__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Data Port Writes Coalescing metric set :: Sampler Texels */
#define bdw__data_port_writes_coalescing__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Data Port Writes Coalescing metric set :: Sampler Texels Misses */
#define bdw__data_port_writes_coalescing__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Data Port Writes Coalescing metric set :: SLM Bytes Read */
#define bdw__data_port_writes_coalescing__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Data Port Writes Coalescing metric set :: SLM Bytes Read */
#define bdw__data_port_writes_coalescing__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Data Port Writes Coalescing metric set :: SLM Bytes Written */
#define bdw__data_port_writes_coalescing__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Data Port Writes Coalescing metric set :: SLM Bytes Written */
#define bdw__data_port_writes_coalescing__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Data Port Writes Coalescing metric set :: Shader Memory Accesses */
#define bdw__data_port_writes_coalescing__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Data Port Writes Coalescing metric set :: Shader Atomic Memory Accesses */
#define bdw__data_port_writes_coalescing__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Data Port Writes Coalescing metric set :: L3 Shader Throughput */
#define bdw__data_port_writes_coalescing__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Data Port Writes Coalescing metric set :: L3 Shader Throughput */
#define bdw__data_port_writes_coalescing__l3_shader_throughput__max \
   bdw__render_basic__l3_shader_throughput__max

/* Data Port Writes Coalescing metric set :: Shader Barrier Messages */
#define bdw__data_port_writes_coalescing__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Data Port Writes Coalescing metric set :: EU to Data Port 0 Writes 32B */
#define bdw__data_port_writes_coalescing__eu_hdc0_writes32_b__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Data Port Writes Coalescing metric set :: EU to Data Port 0 Writes 64B */
static uint64_t
bdw__data_port_writes_coalescing__eu_hdc0_writes64_b__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ B 4 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Data Port Writes Coalescing metric set :: EU to Data Port 0 Writes 64B */
static uint64_t
bdw__data_port_writes_coalescing__eu_hdc0_writes96_b__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ 2 UDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = 2;
   uint64_t tmp3 = tmp1 / tmp2;

   return tmp3;
}

/* Data Port Writes Coalescing metric set :: EU to Data Port 0 Writes 128 */
static uint64_t
bdw__data_port_writes_coalescing__eu_hdc0_writes128_b__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ 2 UDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = 2;
   uint64_t tmp3 = tmp1 / tmp2;

   return tmp3;
}

/* Data Port Writes Coalescing metric set :: EU to Data Port 0 Writes 128 */
static uint64_t
bdw__data_port_writes_coalescing__eu_hdc0_writes192_b__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ 2 UDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = 2;
   uint64_t tmp3 = tmp1 / tmp2;

   return tmp3;
}

/* Data Port Writes Coalescing metric set :: EU to Data Port 0 Writes 64B */
#define bdw__data_port_writes_coalescing__eu_hdc0_writes128_b_simd16__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Data Port Writes Coalescing metric set :: EU to Data Port 0 Writes 256B */
static uint64_t
bdw__data_port_writes_coalescing__eu_hdc0_writes256_b_simd16__read(UNUSED struct intel_perf_config *perf,
                                                                   const struct intel_perf_query_info *query,
                                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ 2 UDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = 2;
   uint64_t tmp3 = tmp1 / tmp2;

   return tmp3;
}

/* Data Port Writes Coalescing metric set :: Data Port 0 to L3 Data Reads */
#define bdw__data_port_writes_coalescing__hdc0_l3_data_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Data Port Writes Coalescing metric set :: Data Port 0 to L3 Data Writes */
#define bdw__data_port_writes_coalescing__hdc0_l3_data_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Data Port Writes Coalescing metric set :: All Data Port 0 Reads from L3 */
#define bdw__data_port_writes_coalescing__hdc0_l3_reads__read \
   bdw__data_port_reads_coalescing__hdc0_l3_reads__read

/* Data Port Writes Coalescing metric set :: All Data Port 0 Writes to L3 */
#define bdw__data_port_writes_coalescing__hdc0_l3_writes__read \
   hsw__render_basic__gpu_core_clocks__read

/* Data Port Writes Coalescing metric set :: EuBytesWrittenPerCacheLine */
static float
bdw__data_port_writes_coalescing__eu_bytes_written_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                                        const struct intel_perf_query_info *query,
                                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuHdc0Writes32B 32 UMUL $EuHdc0Writes64B 64 UMUL $EuHdc0Writes96B 96 UMUL $EuHdc0Writes128B 128 UMUL $EuHdc0Writes128BSimd16 128 UMUL $EuHdc0Writes256BSimd16 256 UMUL $EuHdc0Writes192B 192 UMUL UADD UADD UADD UADD UADD UADD $Hdc0L3DataWrites FDIV */
   uint64_t tmp0 = bdw__data_port_writes_coalescing__eu_hdc0_writes32_b__read(perf, query, results) * 32;
   uint64_t tmp1 = bdw__data_port_writes_coalescing__eu_hdc0_writes64_b__read(perf, query, results) * 64;
   uint64_t tmp2 = bdw__data_port_writes_coalescing__eu_hdc0_writes96_b__read(perf, query, results) * 96;
   uint64_t tmp3 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b__read(perf, query, results) * 128;
   uint64_t tmp4 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b_simd16__read(perf, query, results) * 128;
   uint64_t tmp5 = bdw__data_port_writes_coalescing__eu_hdc0_writes256_b_simd16__read(perf, query, results) * 256;
   uint64_t tmp6 = bdw__data_port_writes_coalescing__eu_hdc0_writes192_b__read(perf, query, results) * 192;
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = tmp4 + tmp7;
   uint64_t tmp9 = tmp3 + tmp8;
   uint64_t tmp10 = tmp2 + tmp9;
   uint64_t tmp11 = tmp1 + tmp10;
   uint64_t tmp12 = tmp0 + tmp11;
   double tmp13 = tmp12;
   double tmp14 = bdw__data_port_writes_coalescing__hdc0_l3_data_writes__read(perf, query, results);
   double tmp15 = tmp14 ? tmp13 / tmp14 : 0;

   return tmp15;
}

/* Data Port Writes Coalescing metric set :: EuDataWritesPerCacheLine */
static float
bdw__data_port_writes_coalescing__eu_data_writes_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                                      const struct intel_perf_query_info *query,
                                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuBytesWrittenPerCacheLine 64 FDIV */
   double tmp0 = bdw__data_port_writes_coalescing__eu_bytes_written_per_cache_line__read(perf, query, results);
   double tmp1 = 64;
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define bdw__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define bdw__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define bdw__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define bdw__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define bdw__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define bdw__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define bdw__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define bdw__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define bdw__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define bdw__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define bdw__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define bdw__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define bdw__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define bdw__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define bdw__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define bdw__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define bdw__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define bdw__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define bdw__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define bdw__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define bdw__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define bdw__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define bdw__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define bdw__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define bdw__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define bdw__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define bdw__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define bdw__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define bdw__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define bdw__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define bdw__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define bdw__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define bdw__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define bdw__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define bdw__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define bdw__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define bdw__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
static uint64_t
bdw__hdc_and_sf__l3_shader_throughput__max(struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 64 UMUL $EuSubslicesTotalCount UMUL 2 UMUL */
   uint64_t tmp0 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, results) * 64;
   uint64_t tmp1 = tmp0 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp2 = tmp1 * 2;

   return tmp2;
}

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define bdw__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define bdw__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
static float
bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
static float
bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ C 4 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = results->accumulator[query->c_offset + 4];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
static float
bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ C 2 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
static float
bdw__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ C 0 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 0];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
static float
bdw__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 6 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
static float
bdw__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ B 4 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: SQ is full */
static float
bdw__hdc_and_sf__gt_request_queue_full__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: PERFCNT 0 READ 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->perfcnt_offset + 0];
   uint64_t tmp1 = tmp0 * 100;
   double tmp2 = tmp1;
   double tmp3 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;

   return tmp4;
}

/* Metric set L3_1 :: GPU Time Elapsed */
#define bdw__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define bdw__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define bdw__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define bdw__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define bdw__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define bdw__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define bdw__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define bdw__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define bdw__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define bdw__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define bdw__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define bdw__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define bdw__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define bdw__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define bdw__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define bdw__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define bdw__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define bdw__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define bdw__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define bdw__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define bdw__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define bdw__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define bdw__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define bdw__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define bdw__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define bdw__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define bdw__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define bdw__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define bdw__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define bdw__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define bdw__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define bdw__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define bdw__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define bdw__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define bdw__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define bdw__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define bdw__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define bdw__l3_1__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define bdw__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice1 L3 Bank0 Stalled */
#define bdw__l3_1__l31_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice1 L3 Bank1 Stalled */
#define bdw__l3_1__l31_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice1 L3 Bank1 Active */
#define bdw__l3_1__l31_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice1 L3 Bank0 Active */
#define bdw__l3_1__l31_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define bdw__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_2 :: GPU Time Elapsed */
#define bdw__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_2 :: GPU Core Clocks */
#define bdw__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define bdw__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define bdw__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_2 :: GPU Busy */
#define bdw__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_2 :: VS Threads Dispatched */
#define bdw__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_2 :: HS Threads Dispatched */
#define bdw__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_2 :: DS Threads Dispatched */
#define bdw__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_2 :: GS Threads Dispatched */
#define bdw__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_2 :: FS Threads Dispatched */
#define bdw__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_2 :: CS Threads Dispatched */
#define bdw__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_2 :: EU Active */
#define bdw__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_2 :: EU Stall */
#define bdw__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_2 :: EU Both FPU Pipes Active */
#define bdw__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_2 :: VS FPU0 Pipe Active */
#define bdw__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_2 :: VS FPU1 Pipe Active */
#define bdw__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_2 :: VS Send Pipe Active */
#define bdw__l3_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_2 :: PS FPU0 Pipe Active */
#define bdw__l3_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_2 :: PS FPU1 Pipe Active */
#define bdw__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_2 :: PS Send Pipeline Active */
#define bdw__l3_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_2 :: FS Both FPU Active */
#define bdw__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_2 :: Rasterized Pixels */
#define bdw__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_2 :: Early Hi-Depth Test Fails */
#define bdw__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_2 :: Early Depth Test Fails */
#define bdw__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Samples Killed in FS */
#define bdw__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_2 :: Pixels Failing Tests */
#define bdw__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_2 :: Samples Written */
#define bdw__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_2 :: Samples Blended */
#define bdw__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_2 :: Sampler Texels */
#define bdw__l3_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_2 :: Sampler Texels Misses */
#define bdw__l3_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_2 :: SLM Bytes Read */
#define bdw__l3_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_2 :: SLM Bytes Read */
#define bdw__l3_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: SLM Bytes Written */
#define bdw__l3_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_2 :: SLM Bytes Written */
#define bdw__l3_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Memory Accesses */
#define bdw__l3_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_2 :: Shader Atomic Memory Accesses */
#define bdw__l3_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define bdw__l3_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define bdw__l3_2__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set L3_2 :: Shader Barrier Messages */
#define bdw__l3_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Slice0 L3 Bank0 Stalled */
#define bdw__l3_2__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_2 :: Slice0 L3 Bank1 Stalled */
#define bdw__l3_2__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_2 :: Slice0 L3 Bank1 Active */
#define bdw__l3_2__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_2 :: Slice0 L3 Bank0 Active */
#define bdw__l3_2__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_2 :: SQ is full */
#define bdw__l3_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_3 :: GPU Time Elapsed */
#define bdw__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_3 :: GPU Core Clocks */
#define bdw__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define bdw__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define bdw__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_3 :: GPU Busy */
#define bdw__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_3 :: VS Threads Dispatched */
#define bdw__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_3 :: HS Threads Dispatched */
#define bdw__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_3 :: DS Threads Dispatched */
#define bdw__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_3 :: GS Threads Dispatched */
#define bdw__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_3 :: FS Threads Dispatched */
#define bdw__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_3 :: CS Threads Dispatched */
#define bdw__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_3 :: EU Active */
#define bdw__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_3 :: EU Stall */
#define bdw__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_3 :: EU Both FPU Pipes Active */
#define bdw__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_3 :: VS FPU0 Pipe Active */
#define bdw__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_3 :: VS FPU1 Pipe Active */
#define bdw__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_3 :: VS Send Pipe Active */
#define bdw__l3_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_3 :: PS FPU0 Pipe Active */
#define bdw__l3_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_3 :: PS FPU1 Pipe Active */
#define bdw__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_3 :: PS Send Pipeline Active */
#define bdw__l3_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_3 :: FS Both FPU Active */
#define bdw__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_3 :: Rasterized Pixels */
#define bdw__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_3 :: Early Hi-Depth Test Fails */
#define bdw__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_3 :: Early Depth Test Fails */
#define bdw__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Samples Killed in FS */
#define bdw__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_3 :: Pixels Failing Tests */
#define bdw__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_3 :: Samples Written */
#define bdw__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_3 :: Samples Blended */
#define bdw__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_3 :: Sampler Texels */
#define bdw__l3_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_3 :: Sampler Texels Misses */
#define bdw__l3_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_3 :: SLM Bytes Read */
#define bdw__l3_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_3 :: SLM Bytes Read */
#define bdw__l3_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: SLM Bytes Written */
#define bdw__l3_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_3 :: SLM Bytes Written */
#define bdw__l3_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Memory Accesses */
#define bdw__l3_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_3 :: Shader Atomic Memory Accesses */
#define bdw__l3_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define bdw__l3_3__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define bdw__l3_3__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set L3_3 :: Shader Barrier Messages */
#define bdw__l3_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */
#define bdw__l3_3__l30_bank3_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_3 :: Slice1 L3 Bank3 Stalled */
#define bdw__l3_3__l31_bank3_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_3 :: Slice1 L3 Bank3 Active */
#define bdw__l3_3__l31_bank3_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Active */
#define bdw__l3_3__l30_bank3_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_3 :: SQ is full */
#define bdw__l3_3__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_4 :: GPU Time Elapsed */
#define bdw__l3_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_4 :: GPU Core Clocks */
#define bdw__l3_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_4 :: AVG GPU Core Frequency */
#define bdw__l3_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_4 :: AVG GPU Core Frequency */
#define bdw__l3_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_4 :: GPU Busy */
#define bdw__l3_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_4 :: VS Threads Dispatched */
#define bdw__l3_4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_4 :: HS Threads Dispatched */
#define bdw__l3_4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_4 :: DS Threads Dispatched */
#define bdw__l3_4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_4 :: GS Threads Dispatched */
#define bdw__l3_4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_4 :: FS Threads Dispatched */
#define bdw__l3_4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_4 :: CS Threads Dispatched */
#define bdw__l3_4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_4 :: EU Active */
#define bdw__l3_4__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_4 :: EU Stall */
#define bdw__l3_4__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_4 :: EU Both FPU Pipes Active */
#define bdw__l3_4__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_4 :: VS FPU0 Pipe Active */
#define bdw__l3_4__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_4 :: VS FPU1 Pipe Active */
#define bdw__l3_4__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_4 :: VS Send Pipe Active */
#define bdw__l3_4__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_4 :: PS FPU0 Pipe Active */
#define bdw__l3_4__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_4 :: PS FPU1 Pipe Active */
#define bdw__l3_4__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_4 :: PS Send Pipeline Active */
#define bdw__l3_4__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_4 :: FS Both FPU Active */
#define bdw__l3_4__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_4 :: Rasterized Pixels */
#define bdw__l3_4__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_4 :: Early Hi-Depth Test Fails */
#define bdw__l3_4__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_4 :: Early Depth Test Fails */
#define bdw__l3_4__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_4 :: Samples Killed in FS */
#define bdw__l3_4__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_4 :: Pixels Failing Tests */
#define bdw__l3_4__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_4 :: Samples Written */
#define bdw__l3_4__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_4 :: Samples Blended */
#define bdw__l3_4__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_4 :: Sampler Texels */
#define bdw__l3_4__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_4 :: Sampler Texels Misses */
#define bdw__l3_4__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_4 :: SLM Bytes Read */
#define bdw__l3_4__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_4 :: SLM Bytes Read */
#define bdw__l3_4__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_4 :: SLM Bytes Written */
#define bdw__l3_4__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_4 :: SLM Bytes Written */
#define bdw__l3_4__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_4 :: Shader Memory Accesses */
#define bdw__l3_4__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_4 :: Shader Atomic Memory Accesses */
#define bdw__l3_4__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_4 :: L3 Shader Throughput */
#define bdw__l3_4__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_4 :: L3 Shader Throughput */
#define bdw__l3_4__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set L3_4 :: Shader Barrier Messages */
#define bdw__l3_4__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_4 :: Slice0 L3 Bank2 Stalled */
#define bdw__l3_4__l30_bank2_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_4 :: Slice1 L3 Bank2 Stalled */
#define bdw__l3_4__l31_bank2_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_4 :: Slice1 L3 Bank2 Active */
#define bdw__l3_4__l31_bank2_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_4 :: Slice0 L3 Bank2 Active */
#define bdw__l3_4__l30_bank2_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_4 :: SQ is full */
#define bdw__l3_4__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define bdw__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define bdw__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define bdw__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define bdw__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define bdw__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define bdw__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define bdw__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define bdw__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define bdw__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define bdw__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define bdw__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define bdw__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define bdw__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define bdw__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define bdw__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define bdw__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define bdw__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define bdw__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define bdw__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define bdw__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define bdw__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define bdw__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define bdw__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define bdw__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define bdw__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define bdw__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define bdw__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define bdw__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define bdw__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define bdw__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define bdw__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define bdw__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define bdw__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define bdw__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define bdw__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define bdw__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define bdw__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define bdw__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice1 Post-EarlyZ Pixel Data Ready */
#define bdw__rasterizer_and_pixel_backend__pixel_data1_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define bdw__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Input Available */
#define bdw__rasterizer_and_pixel_backend__rasterizer1_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Output Ready */
#define bdw__rasterizer_and_pixel_backend__rasterizer1_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define bdw__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define bdw__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define bdw__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice1 Pixel Values Ready */
#define bdw__rasterizer_and_pixel_backend__pixel_values1_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice1 PS Output Available */
#define bdw__rasterizer_and_pixel_backend__ps_output1_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define bdw__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler_1 :: GPU Time Elapsed */
#define bdw__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler_1 :: GPU Core Clocks */
#define bdw__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler_1 :: AVG GPU Core Frequency */
#define bdw__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler_1 :: AVG GPU Core Frequency */
#define bdw__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler_1 :: GPU Busy */
#define bdw__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler_1 :: VS Threads Dispatched */
#define bdw__sampler_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler_1 :: HS Threads Dispatched */
#define bdw__sampler_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler_1 :: DS Threads Dispatched */
#define bdw__sampler_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler_1 :: GS Threads Dispatched */
#define bdw__sampler_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler_1 :: FS Threads Dispatched */
#define bdw__sampler_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler_1 :: CS Threads Dispatched */
#define bdw__sampler_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler_1 :: EU Active */
#define bdw__sampler_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler_1 :: EU Stall */
#define bdw__sampler_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler_1 :: EU Both FPU Pipes Active */
#define bdw__sampler_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler_1 :: VS FPU0 Pipe Active */
#define bdw__sampler_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler_1 :: VS FPU1 Pipe Active */
#define bdw__sampler_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler_1 :: VS Send Pipe Active */
#define bdw__sampler_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler_1 :: PS FPU0 Pipe Active */
#define bdw__sampler_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler_1 :: PS FPU1 Pipe Active */
#define bdw__sampler_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler_1 :: PS Send Pipeline Active */
#define bdw__sampler_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler_1 :: FS Both FPU Active */
#define bdw__sampler_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler_1 :: Rasterized Pixels */
#define bdw__sampler_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler_1 :: Early Hi-Depth Test Fails */
#define bdw__sampler_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler_1 :: Early Depth Test Fails */
#define bdw__sampler_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler_1 :: Samples Killed in FS */
#define bdw__sampler_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler_1 :: Pixels Failing Tests */
#define bdw__sampler_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler_1 :: Samples Written */
#define bdw__sampler_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler_1 :: Samples Blended */
#define bdw__sampler_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler_1 :: Sampler Texels */
#define bdw__sampler_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler_1 :: Sampler Texels Misses */
#define bdw__sampler_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler_1 :: SLM Bytes Read */
#define bdw__sampler_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler_1 :: SLM Bytes Read */
#define bdw__sampler_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler_1 :: SLM Bytes Written */
#define bdw__sampler_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler_1 :: SLM Bytes Written */
#define bdw__sampler_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler_1 :: Shader Memory Accesses */
#define bdw__sampler_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler_1 :: Shader Atomic Memory Accesses */
#define bdw__sampler_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler_1 :: L3 Shader Throughput */
#define bdw__sampler_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler_1 :: L3 Shader Throughput */
#define bdw__sampler_1__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set Sampler_1 :: Shader Barrier Messages */
#define bdw__sampler_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler_1 :: Slice1 Subslice1 Input Available */
#define bdw__sampler_1__sampler11_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler_1 :: Slice1 Subslice2 Input Available */
#define bdw__sampler_1__sampler12_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler_1 :: Slice1 Subslice0 Input Available */
#define bdw__sampler_1__sampler10_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler_1 :: Slice1 Subslice2 Sampler Output Ready */
#define bdw__sampler_1__sampler12_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler_1 :: Slice1 Subslice0 Sampler Output Ready */
#define bdw__sampler_1__sampler10_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler_1 :: Slice1 Subslice1 Sampler Output Ready */
#define bdw__sampler_1__sampler11_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler_1 :: SQ is full */
#define bdw__sampler_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler_2 :: GPU Time Elapsed */
#define bdw__sampler_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler_2 :: GPU Core Clocks */
#define bdw__sampler_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler_2 :: AVG GPU Core Frequency */
#define bdw__sampler_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler_2 :: AVG GPU Core Frequency */
#define bdw__sampler_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler_2 :: GPU Busy */
#define bdw__sampler_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler_2 :: VS Threads Dispatched */
#define bdw__sampler_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler_2 :: HS Threads Dispatched */
#define bdw__sampler_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler_2 :: DS Threads Dispatched */
#define bdw__sampler_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler_2 :: GS Threads Dispatched */
#define bdw__sampler_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler_2 :: FS Threads Dispatched */
#define bdw__sampler_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler_2 :: CS Threads Dispatched */
#define bdw__sampler_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler_2 :: EU Active */
#define bdw__sampler_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler_2 :: EU Stall */
#define bdw__sampler_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler_2 :: EU Both FPU Pipes Active */
#define bdw__sampler_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler_2 :: VS FPU0 Pipe Active */
#define bdw__sampler_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler_2 :: VS FPU1 Pipe Active */
#define bdw__sampler_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler_2 :: VS Send Pipe Active */
#define bdw__sampler_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler_2 :: PS FPU0 Pipe Active */
#define bdw__sampler_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler_2 :: PS FPU1 Pipe Active */
#define bdw__sampler_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler_2 :: PS Send Pipeline Active */
#define bdw__sampler_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler_2 :: FS Both FPU Active */
#define bdw__sampler_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler_2 :: Rasterized Pixels */
#define bdw__sampler_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler_2 :: Early Hi-Depth Test Fails */
#define bdw__sampler_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler_2 :: Early Depth Test Fails */
#define bdw__sampler_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler_2 :: Samples Killed in FS */
#define bdw__sampler_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler_2 :: Pixels Failing Tests */
#define bdw__sampler_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler_2 :: Samples Written */
#define bdw__sampler_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler_2 :: Samples Blended */
#define bdw__sampler_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler_2 :: Sampler Texels */
#define bdw__sampler_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler_2 :: Sampler Texels Misses */
#define bdw__sampler_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler_2 :: SLM Bytes Read */
#define bdw__sampler_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler_2 :: SLM Bytes Read */
#define bdw__sampler_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler_2 :: SLM Bytes Written */
#define bdw__sampler_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler_2 :: SLM Bytes Written */
#define bdw__sampler_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler_2 :: Shader Memory Accesses */
#define bdw__sampler_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler_2 :: Shader Atomic Memory Accesses */
#define bdw__sampler_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler_2 :: L3 Shader Throughput */
#define bdw__sampler_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler_2 :: L3 Shader Throughput */
#define bdw__sampler_2__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set Sampler_2 :: Shader Barrier Messages */
#define bdw__sampler_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler_2 :: Slice0 Subslice1 Input Available */
#define bdw__sampler_2__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler_2 :: Slice0 Subslice2 Input Available */
#define bdw__sampler_2__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler_2 :: Slice0 Subslice0 Input Available */
#define bdw__sampler_2__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler_2 :: Slice0 Subslice2 Sampler Output Ready */
#define bdw__sampler_2__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler_2 :: Slice0 Subslice0 Sampler Output Ready */
#define bdw__sampler_2__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler_2 :: Slice0 Subslice1 Sampler Output Ready */
#define bdw__sampler_2__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler_2 :: SQ is full */
#define bdw__sampler_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define bdw__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define bdw__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define bdw__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define bdw__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define bdw__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define bdw__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define bdw__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define bdw__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define bdw__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define bdw__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define bdw__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define bdw__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define bdw__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define bdw__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define bdw__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define bdw__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define bdw__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define bdw__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define bdw__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define bdw__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define bdw__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define bdw__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define bdw__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define bdw__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define bdw__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define bdw__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define bdw__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define bdw__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define bdw__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define bdw__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define bdw__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define bdw__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define bdw__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define bdw__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define bdw__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define bdw__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define bdw__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define bdw__tdl_1__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define bdw__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice1 */
#define bdw__tdl_1__non_ps_thread11_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice0 */
#define bdw__tdl_1__ps_thread10_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice0 */
#define bdw__tdl_1__non_ps_thread10_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice2 */
#define bdw__tdl_1__ps_thread12_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice2 */
#define bdw__tdl_1__non_ps_thread12_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice1 */
#define bdw__tdl_1__ps_thread11_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define bdw__tdl_1__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define bdw__tdl_1__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define bdw__tdl_1__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define bdw__tdl_1__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define bdw__tdl_1__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define bdw__tdl_1__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_1 :: SQ is full */
#define bdw__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define bdw__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define bdw__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define bdw__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define bdw__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define bdw__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define bdw__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define bdw__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define bdw__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define bdw__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define bdw__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define bdw__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define bdw__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define bdw__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define bdw__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define bdw__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define bdw__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define bdw__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define bdw__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define bdw__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define bdw__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define bdw__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define bdw__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define bdw__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define bdw__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define bdw__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define bdw__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define bdw__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define bdw__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define bdw__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define bdw__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define bdw__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define bdw__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define bdw__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define bdw__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define bdw__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define bdw__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define bdw__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define bdw__tdl_2__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define bdw__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define bdw__tdl_2__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define bdw__tdl_2__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define bdw__tdl_2__ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define bdw__tdl_2__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define bdw__tdl_2__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define bdw__tdl_2__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 0 */
#define bdw__tdl_2__thread_header12_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 1 */
#define bdw__tdl_2__thread_header12_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 1 */
#define bdw__tdl_2__thread_header11_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 0 */
#define bdw__tdl_2__thread_header10_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 1 */
#define bdw__tdl_2__thread_header10_ready_port1__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 0 */
#define bdw__tdl_2__thread_header11_ready_port0__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define bdw__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define bdw__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define bdw__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define bdw__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define bdw__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define bdw__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extra set :: EU FPU1 Pipe Active including Ext Math */
static float
bdw__compute_extra__fpu1_active_adjusted__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: A 8 READ  C 5 READ C 6 READ FADD C 7 READ FADD C 2 READ FADD C 3 READ FADD C 4 READ FADD 8 FMUL FADD 100 FMUL $EuCoresTotalCount FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 8];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   uint64_t tmp2 = results->accumulator[query->c_offset + 6];
   double tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 7];
   double tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->c_offset + 2];
   double tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->c_offset + 3];
   double tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 4];
   double tmp11 = tmp9 + tmp10;
   double tmp12 = tmp11 * 8;
   double tmp13 = tmp0 + tmp12;
   double tmp14 = tmp13 * 100;
   double tmp15 = tmp14;
   double tmp16 = perf->sys_vars.n_eus;
   double tmp17 = tmp16 ? tmp15 / tmp16 : 0;
   double tmp18 = tmp17;
   double tmp19 = bdw__compute_extra__gpu_core_clocks__read(perf, query, results);
   double tmp20 = tmp19 ? tmp18 / tmp19 : 0;

   return tmp20;
}

/* Media Vme Pipe metric set :: GPU Time Elapsed */
#define bdw__vme_pipe__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Media Vme Pipe metric set :: GPU Core Clocks */
#define bdw__vme_pipe__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Media Vme Pipe metric set :: AVG GPU Core Frequency */
#define bdw__vme_pipe__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Media Vme Pipe metric set :: AVG GPU Core Frequency */
#define bdw__vme_pipe__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Media Vme Pipe metric set :: GPU Busy */
#define bdw__vme_pipe__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Media Vme Pipe metric set :: CS Threads Dispatched */
#define bdw__vme_pipe__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Media Vme Pipe metric set :: EU Active */
#define bdw__vme_pipe__eu_active__read \
   bdw__render_basic__eu_active__read

/* Media Vme Pipe metric set :: EU Stall */
#define bdw__vme_pipe__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Media Vme Pipe metric set :: EU Both FPU Pipes Active */
#define bdw__vme_pipe__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Media Vme Pipe metric set :: EU Thread Occupancy */
static float
bdw__vme_pipe__eu_thread_occupancy__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: 8 A 10 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 10];
   double tmp1 = 8 * tmp0;
   double tmp2 = tmp1;
   double tmp3 = perf->devinfo.num_thread_per_eu;
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;
   uint64_t tmp5 = tmp4;
   uint64_t tmp6 = perf->sys_vars.n_eus;
   uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0;
   uint64_t tmp8 = tmp7 * 100;
   double tmp9 = tmp8;
   double tmp10 = bdw__vme_pipe__gpu_core_clocks__read(perf, query, results);
   double tmp11 = tmp10 ? tmp9 / tmp10 : 0;

   return tmp11;
}

/* Media Vme Pipe metric set :: VME Busy */
static float
bdw__vme_pipe__vme_busy__read(UNUSED struct intel_perf_config *perf,
                              const struct intel_perf_query_info *query,
                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 3 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 3];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = bdw__vme_pipe__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Gpu Rings Busyness :: GPU Time Elapsed */
#define bdw__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness :: GPU Core Clocks */
#define bdw__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define bdw__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define bdw__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness :: Render Ring Busy */
#define bdw__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: Vdbox0 Ring Busy */
#define bdw__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness :: Vdbox1 Ring Busy */
#define bdw__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* Gpu Rings Busyness :: Vebox Ring Busy */
#define bdw__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness :: Blitter Ring Busy */
#define bdw__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness :: AnyRingBusy */
#define bdw__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* MDAPI testing set :: GPU Time Elapsed */
#define bdw__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define bdw__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define bdw__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define bdw__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define bdw__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define bdw__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define bdw__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define bdw__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define bdw__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define bdw__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define bdw__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define bdw__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define bdw__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define bdw__stc__pma_stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define bdw__stc__pma_stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define bdw__stc__pma_stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define bdw__stc__pma_stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: GPU Busy */
#define bdw__stc__pma_stall__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set PMA Stall :: VS Threads Dispatched */
#define bdw__stc__pma_stall__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set PMA Stall :: HS Threads Dispatched */
#define bdw__stc__pma_stall__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set PMA Stall :: DS Threads Dispatched */
#define bdw__stc__pma_stall__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set PMA Stall :: GS Threads Dispatched */
#define bdw__stc__pma_stall__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set PMA Stall :: FS Threads Dispatched */
#define bdw__stc__pma_stall__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set PMA Stall :: CS Threads Dispatched */
#define bdw__stc__pma_stall__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set PMA Stall :: STC PMA stall */
#define bdw__stc__pma_stall__stc_pma_stall__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define chv__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define chv__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define chv__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define chv__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define chv__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define chv__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define chv__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define chv__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define chv__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define chv__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define chv__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define chv__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define chv__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define chv__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define chv__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define chv__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define chv__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define chv__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define chv__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define chv__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define chv__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define chv__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define chv__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
static float
chv__render_basic__samplers_busy__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ  B 1 READ UADD $GpuCoreClocks FDIV 2 FDIV 100 FMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = chv__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   double tmp6 = tmp5;
   double tmp7 = 2;
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;
   double tmp9 = tmp8 * 100;

   return tmp9;
}

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define chv__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
#define chv__render_basic__sampler1_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics Basic set :: Samples Written */
#define chv__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define chv__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define chv__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define chv__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define chv__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define chv__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define chv__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define chv__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define chv__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define chv__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define chv__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define chv__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define chv__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define chv__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define chv__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Misses */
#define chv__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
static uint64_t
chv__render_basic__l3_sampler_throughput__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: A 29 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 29];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define chv__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define chv__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
static uint64_t
chv__render_basic__l3_shader_throughput__max(struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 64 UMUL $EuSlicesTotalCount UMUL 2 UMUL */
   uint64_t tmp0 = chv__render_basic__gpu_core_clocks__read(perf, query, results) * 64;
   uint64_t tmp1 = tmp0 * perf->sys_vars.n_eu_slices;
   uint64_t tmp2 = tmp1 * 2;

   return tmp2;
}

/* Render Metrics Basic set :: Shader Barrier Messages */
#define chv__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define chv__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define chv__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define chv__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define chv__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define chv__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define chv__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define chv__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define chv__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define chv__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define chv__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define chv__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define chv__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define chv__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define chv__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define chv__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define chv__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define chv__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define chv__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define chv__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define chv__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define chv__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define chv__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define chv__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define chv__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define chv__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define chv__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define chv__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define chv__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define chv__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define chv__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define chv__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define chv__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define chv__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define chv__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define chv__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define chv__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define chv__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define chv__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define chv__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define chv__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define chv__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define chv__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define chv__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define chv__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define chv__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define chv__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define chv__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define chv__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define chv__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define chv__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define chv__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define chv__compute_basic__l3_shader_throughput__max \
   chv__render_basic__l3_shader_throughput__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define chv__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
static uint64_t
chv__compute_basic__typed_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 64;

   return tmp3;
}

/* Compute Metrics Basic set :: Typed Bytes Read */
#define chv__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
static uint64_t
chv__compute_basic__typed_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ B 3 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->b_offset + 3];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 64;

   return tmp3;
}

/* Compute Metrics Basic set :: Typed Bytes Written */
#define chv__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
static uint64_t
chv__compute_basic__untyped_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 64;

   return tmp3;
}

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define chv__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define chv__compute_basic__untyped_bytes_written__read \
   hsw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define chv__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define chv__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_depth_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define chv__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define chv__compute_basic__gti_write_throughput__read \
   hsw__render_basic__gti_vf_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define chv__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Compute Metrics Basic set :: GTI Ring Throughput */
static uint64_t
chv__compute_basic__gti_ring_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 2 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 2];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Compute Metrics Basic set :: GTI Ring Throughput */
static uint64_t
chv__compute_basic__gti_ring_throughput__max(struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 128 UMUL */
   uint64_t tmp0 = chv__compute_basic__gpu_core_clocks__read(perf, query, results) * 128;

   return tmp0;
}

/* Compute Metrics Basic set :: GTI Read-Only Stall */
#define chv__compute_basic__gti_ro_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Compute Metrics Basic set :: GTI Read-Write Stall */
#define chv__compute_basic__gti_rw_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define chv__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define chv__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define chv__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define chv__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define chv__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VS Threads Dispatched */
#define chv__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics for 3D Pipeline Profile :: HS Threads Dispatched */
#define chv__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics for 3D Pipeline Profile :: DS Threads Dispatched */
#define chv__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics for 3D Pipeline Profile :: GS Threads Dispatched */
#define chv__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics for 3D Pipeline Profile :: FS Threads Dispatched */
#define chv__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics for 3D Pipeline Profile :: CS Threads Dispatched */
#define chv__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics for 3D Pipeline Profile :: EU Active */
#define chv__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics for 3D Pipeline Profile :: EU Stall */
#define chv__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics for 3D Pipeline Profile :: Rasterized Pixels */
#define chv__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define chv__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics for 3D Pipeline Profile :: Early Depth Test Fails */
#define chv__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics for 3D Pipeline Profile :: Samples Killed in FS */
#define chv__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics for 3D Pipeline Profile :: Pixels Failing Tests */
#define chv__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics for 3D Pipeline Profile :: Samples Written */
#define chv__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics for 3D Pipeline Profile :: Samples Blended */
#define chv__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics for 3D Pipeline Profile :: Sampler Accesses */
#define chv__render_pipe_profile__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Render Metrics for 3D Pipeline Profile :: Sampler Texels */
#define chv__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics for 3D Pipeline Profile :: Sampler Texels Misses */
#define chv__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */
#define chv__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */
#define chv__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */
#define chv__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */
#define chv__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics for 3D Pipeline Profile :: Shader Memory Accesses */
#define chv__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define chv__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */
#define chv__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */
#define chv__render_pipe_profile__l3_shader_throughput__max \
   chv__render_basic__l3_shader_throughput__max

/* Render Metrics for 3D Pipeline Profile :: Shader Barrier Messages */
#define chv__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics for 3D Pipeline Profile :: VF Bottleneck */
#define chv__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS Bottleneck */
#define chv__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: HS Bottleneck */
#define chv__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics for 3D Pipeline Profile :: DS Bottleneck */
#define chv__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: GS Bottleneck */
#define chv__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO Bottleneck */
#define chv__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper Bottleneck */
#define chv__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define chv__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define chv__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Early Depth Bottleneck */
#define chv__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC Bottleneck */
#define chv__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS Stall */
#define chv__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS Stall */
#define chv__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO Stall */
#define chv__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: CL Stall */
#define chv__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF Stall */
#define chv__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define chv__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define chv__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define chv__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define chv__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define chv__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define chv__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define chv__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define chv__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define chv__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define chv__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define chv__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define chv__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define chv__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define chv__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define chv__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define chv__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define chv__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define chv__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define chv__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define chv__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define chv__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define chv__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define chv__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define chv__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define chv__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define chv__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define chv__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define chv__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define chv__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define chv__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define chv__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define chv__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define chv__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define chv__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define chv__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define chv__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define chv__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define chv__hdc_and_sf__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define chv__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define chv__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
#define chv__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define chv__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define chv__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
#define chv__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define chv__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define chv__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define chv__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define chv__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define chv__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define chv__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define chv__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define chv__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define chv__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define chv__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define chv__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define chv__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define chv__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define chv__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define chv__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define chv__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define chv__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define chv__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define chv__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define chv__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define chv__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define chv__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define chv__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define chv__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define chv__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define chv__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define chv__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define chv__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define chv__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define chv__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define chv__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define chv__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define chv__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define chv__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define chv__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define chv__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define chv__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define chv__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define chv__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define chv__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define chv__l3_1__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define chv__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice1 L3 Bank0 Stalled */
#define chv__l3_1__l31_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice1 L3 Bank1 Stalled */
#define chv__l3_1__l31_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice1 L3 Bank1 Active */
#define chv__l3_1__l31_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice1 L3 Bank0 Active */
#define chv__l3_1__l31_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define chv__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_2 :: GPU Time Elapsed */
#define chv__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_2 :: GPU Core Clocks */
#define chv__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define chv__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define chv__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_2 :: GPU Busy */
#define chv__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_2 :: VS Threads Dispatched */
#define chv__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_2 :: HS Threads Dispatched */
#define chv__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_2 :: DS Threads Dispatched */
#define chv__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_2 :: GS Threads Dispatched */
#define chv__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_2 :: FS Threads Dispatched */
#define chv__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_2 :: CS Threads Dispatched */
#define chv__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_2 :: EU Active */
#define chv__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_2 :: EU Stall */
#define chv__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_2 :: EU Both FPU Pipes Active */
#define chv__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_2 :: VS FPU0 Pipe Active */
#define chv__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_2 :: VS FPU1 Pipe Active */
#define chv__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_2 :: VS Send Pipe Active */
#define chv__l3_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_2 :: PS FPU0 Pipe Active */
#define chv__l3_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_2 :: PS FPU1 Pipe Active */
#define chv__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_2 :: PS Send Pipeline Active */
#define chv__l3_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_2 :: FS Both FPU Active */
#define chv__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_2 :: Rasterized Pixels */
#define chv__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_2 :: Early Hi-Depth Test Fails */
#define chv__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_2 :: Early Depth Test Fails */
#define chv__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Samples Killed in FS */
#define chv__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_2 :: Pixels Failing Tests */
#define chv__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_2 :: Samples Written */
#define chv__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_2 :: Samples Blended */
#define chv__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_2 :: Sampler Texels */
#define chv__l3_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_2 :: Sampler Texels Misses */
#define chv__l3_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_2 :: SLM Bytes Read */
#define chv__l3_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_2 :: SLM Bytes Read */
#define chv__l3_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: SLM Bytes Written */
#define chv__l3_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_2 :: SLM Bytes Written */
#define chv__l3_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Memory Accesses */
#define chv__l3_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_2 :: Shader Atomic Memory Accesses */
#define chv__l3_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define chv__l3_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define chv__l3_2__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set L3_2 :: Shader Barrier Messages */
#define chv__l3_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Slice0 L3 Bank0 Stalled */
#define chv__l3_2__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_2 :: Slice0 L3 Bank1 Stalled */
#define chv__l3_2__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_2 :: Slice0 L3 Bank1 Active */
#define chv__l3_2__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_2 :: Slice0 L3 Bank0 Active */
#define chv__l3_2__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_2 :: SQ is full */
#define chv__l3_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_3 :: GPU Time Elapsed */
#define chv__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_3 :: GPU Core Clocks */
#define chv__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define chv__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define chv__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_3 :: GPU Busy */
#define chv__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_3 :: VS Threads Dispatched */
#define chv__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_3 :: HS Threads Dispatched */
#define chv__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_3 :: DS Threads Dispatched */
#define chv__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_3 :: GS Threads Dispatched */
#define chv__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_3 :: FS Threads Dispatched */
#define chv__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_3 :: CS Threads Dispatched */
#define chv__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_3 :: EU Active */
#define chv__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_3 :: EU Stall */
#define chv__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_3 :: EU Both FPU Pipes Active */
#define chv__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_3 :: VS FPU0 Pipe Active */
#define chv__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_3 :: VS FPU1 Pipe Active */
#define chv__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_3 :: VS Send Pipe Active */
#define chv__l3_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_3 :: PS FPU0 Pipe Active */
#define chv__l3_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_3 :: PS FPU1 Pipe Active */
#define chv__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_3 :: PS Send Pipeline Active */
#define chv__l3_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_3 :: FS Both FPU Active */
#define chv__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_3 :: Rasterized Pixels */
#define chv__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_3 :: Early Hi-Depth Test Fails */
#define chv__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_3 :: Early Depth Test Fails */
#define chv__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Samples Killed in FS */
#define chv__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_3 :: Pixels Failing Tests */
#define chv__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_3 :: Samples Written */
#define chv__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_3 :: Samples Blended */
#define chv__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_3 :: Sampler Texels */
#define chv__l3_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_3 :: Sampler Texels Misses */
#define chv__l3_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_3 :: SLM Bytes Read */
#define chv__l3_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_3 :: SLM Bytes Read */
#define chv__l3_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: SLM Bytes Written */
#define chv__l3_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_3 :: SLM Bytes Written */
#define chv__l3_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Memory Accesses */
#define chv__l3_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_3 :: Shader Atomic Memory Accesses */
#define chv__l3_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define chv__l3_3__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define chv__l3_3__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set L3_3 :: Shader Barrier Messages */
#define chv__l3_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */
#define chv__l3_3__l30_bank3_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_3 :: Slice1 L3 Bank3 Stalled */
#define chv__l3_3__l31_bank3_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_3 :: Slice1 L3 Bank3 Active */
#define chv__l3_3__l31_bank3_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Active */
#define chv__l3_3__l30_bank3_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_3 :: SQ is full */
#define chv__l3_3__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_4 :: GPU Time Elapsed */
#define chv__l3_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_4 :: GPU Core Clocks */
#define chv__l3_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_4 :: AVG GPU Core Frequency */
#define chv__l3_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_4 :: AVG GPU Core Frequency */
#define chv__l3_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_4 :: GPU Busy */
#define chv__l3_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_4 :: VS Threads Dispatched */
#define chv__l3_4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_4 :: HS Threads Dispatched */
#define chv__l3_4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_4 :: DS Threads Dispatched */
#define chv__l3_4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_4 :: GS Threads Dispatched */
#define chv__l3_4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_4 :: FS Threads Dispatched */
#define chv__l3_4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_4 :: CS Threads Dispatched */
#define chv__l3_4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_4 :: EU Active */
#define chv__l3_4__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_4 :: EU Stall */
#define chv__l3_4__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_4 :: EU Both FPU Pipes Active */
#define chv__l3_4__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_4 :: VS FPU0 Pipe Active */
#define chv__l3_4__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_4 :: VS FPU1 Pipe Active */
#define chv__l3_4__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_4 :: VS Send Pipe Active */
#define chv__l3_4__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_4 :: PS FPU0 Pipe Active */
#define chv__l3_4__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_4 :: PS FPU1 Pipe Active */
#define chv__l3_4__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_4 :: PS Send Pipeline Active */
#define chv__l3_4__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_4 :: FS Both FPU Active */
#define chv__l3_4__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_4 :: Rasterized Pixels */
#define chv__l3_4__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_4 :: Early Hi-Depth Test Fails */
#define chv__l3_4__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_4 :: Early Depth Test Fails */
#define chv__l3_4__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_4 :: Samples Killed in FS */
#define chv__l3_4__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_4 :: Pixels Failing Tests */
#define chv__l3_4__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_4 :: Samples Written */
#define chv__l3_4__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_4 :: Samples Blended */
#define chv__l3_4__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_4 :: Sampler Texels */
#define chv__l3_4__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_4 :: Sampler Texels Misses */
#define chv__l3_4__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_4 :: SLM Bytes Read */
#define chv__l3_4__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_4 :: SLM Bytes Read */
#define chv__l3_4__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_4 :: SLM Bytes Written */
#define chv__l3_4__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_4 :: SLM Bytes Written */
#define chv__l3_4__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_4 :: Shader Memory Accesses */
#define chv__l3_4__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_4 :: Shader Atomic Memory Accesses */
#define chv__l3_4__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_4 :: L3 Shader Throughput */
#define chv__l3_4__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_4 :: L3 Shader Throughput */
#define chv__l3_4__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set L3_4 :: Shader Barrier Messages */
#define chv__l3_4__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_4 :: Slice0 L3 Bank2 Stalled */
#define chv__l3_4__l30_bank2_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_4 :: Slice1 L3 Bank2 Stalled */
#define chv__l3_4__l31_bank2_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_4 :: Slice1 L3 Bank2 Active */
#define chv__l3_4__l31_bank2_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_4 :: Slice0 L3 Bank2 Active */
#define chv__l3_4__l30_bank2_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_4 :: SQ is full */
#define chv__l3_4__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define chv__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define chv__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define chv__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define chv__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define chv__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define chv__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define chv__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define chv__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define chv__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define chv__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define chv__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define chv__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define chv__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define chv__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define chv__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define chv__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define chv__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define chv__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define chv__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define chv__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define chv__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define chv__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define chv__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define chv__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define chv__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define chv__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define chv__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define chv__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define chv__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define chv__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define chv__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define chv__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define chv__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define chv__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define chv__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define chv__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define chv__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define chv__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice1 Post-EarlyZ Pixel Data Ready */
#define chv__rasterizer_and_pixel_backend__pixel_data1_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define chv__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Input Available */
#define chv__rasterizer_and_pixel_backend__rasterizer1_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Output Ready */
#define chv__rasterizer_and_pixel_backend__rasterizer1_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define chv__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define chv__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define chv__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice1 Pixel Values Ready */
#define chv__rasterizer_and_pixel_backend__pixel_values1_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice1 PS Output Available */
#define chv__rasterizer_and_pixel_backend__ps_output1_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define chv__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler_1 :: GPU Time Elapsed */
#define chv__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler_1 :: GPU Core Clocks */
#define chv__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler_1 :: AVG GPU Core Frequency */
#define chv__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler_1 :: AVG GPU Core Frequency */
#define chv__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler_1 :: GPU Busy */
#define chv__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler_1 :: VS Threads Dispatched */
#define chv__sampler_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler_1 :: HS Threads Dispatched */
#define chv__sampler_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler_1 :: DS Threads Dispatched */
#define chv__sampler_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler_1 :: GS Threads Dispatched */
#define chv__sampler_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler_1 :: FS Threads Dispatched */
#define chv__sampler_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler_1 :: CS Threads Dispatched */
#define chv__sampler_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler_1 :: EU Active */
#define chv__sampler_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler_1 :: EU Stall */
#define chv__sampler_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler_1 :: EU Both FPU Pipes Active */
#define chv__sampler_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler_1 :: VS FPU0 Pipe Active */
#define chv__sampler_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler_1 :: VS FPU1 Pipe Active */
#define chv__sampler_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler_1 :: VS Send Pipe Active */
#define chv__sampler_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler_1 :: PS FPU0 Pipe Active */
#define chv__sampler_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler_1 :: PS FPU1 Pipe Active */
#define chv__sampler_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler_1 :: PS Send Pipeline Active */
#define chv__sampler_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler_1 :: FS Both FPU Active */
#define chv__sampler_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler_1 :: Rasterized Pixels */
#define chv__sampler_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler_1 :: Early Hi-Depth Test Fails */
#define chv__sampler_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler_1 :: Early Depth Test Fails */
#define chv__sampler_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler_1 :: Samples Killed in FS */
#define chv__sampler_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler_1 :: Pixels Failing Tests */
#define chv__sampler_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler_1 :: Samples Written */
#define chv__sampler_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler_1 :: Samples Blended */
#define chv__sampler_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler_1 :: Sampler Texels */
#define chv__sampler_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler_1 :: Sampler Texels Misses */
#define chv__sampler_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler_1 :: SLM Bytes Read */
#define chv__sampler_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler_1 :: SLM Bytes Read */
#define chv__sampler_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler_1 :: SLM Bytes Written */
#define chv__sampler_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler_1 :: SLM Bytes Written */
#define chv__sampler_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler_1 :: Shader Memory Accesses */
#define chv__sampler_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler_1 :: Shader Atomic Memory Accesses */
#define chv__sampler_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler_1 :: L3 Shader Throughput */
#define chv__sampler_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler_1 :: L3 Shader Throughput */
#define chv__sampler_1__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set Sampler_1 :: Shader Barrier Messages */
#define chv__sampler_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler_1 :: Slice1 Subslice1 Input Available */
#define chv__sampler_1__sampler11_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler_1 :: Slice1 Subslice2 Input Available */
#define chv__sampler_1__sampler12_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler_1 :: Slice1 Subslice0 Input Available */
#define chv__sampler_1__sampler10_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler_1 :: Slice1 Subslice2 Sampler Output Ready */
#define chv__sampler_1__sampler12_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler_1 :: Slice1 Subslice0 Sampler Output Ready */
#define chv__sampler_1__sampler10_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler_1 :: Slice1 Subslice1 Sampler Output Ready */
#define chv__sampler_1__sampler11_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler_1 :: SQ is full */
#define chv__sampler_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler_2 :: GPU Time Elapsed */
#define chv__sampler_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler_2 :: GPU Core Clocks */
#define chv__sampler_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler_2 :: AVG GPU Core Frequency */
#define chv__sampler_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler_2 :: AVG GPU Core Frequency */
#define chv__sampler_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler_2 :: GPU Busy */
#define chv__sampler_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler_2 :: VS Threads Dispatched */
#define chv__sampler_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler_2 :: HS Threads Dispatched */
#define chv__sampler_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler_2 :: DS Threads Dispatched */
#define chv__sampler_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler_2 :: GS Threads Dispatched */
#define chv__sampler_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler_2 :: FS Threads Dispatched */
#define chv__sampler_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler_2 :: CS Threads Dispatched */
#define chv__sampler_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler_2 :: EU Active */
#define chv__sampler_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler_2 :: EU Stall */
#define chv__sampler_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler_2 :: EU Both FPU Pipes Active */
#define chv__sampler_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler_2 :: VS FPU0 Pipe Active */
#define chv__sampler_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler_2 :: VS FPU1 Pipe Active */
#define chv__sampler_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler_2 :: VS Send Pipe Active */
#define chv__sampler_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler_2 :: PS FPU0 Pipe Active */
#define chv__sampler_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler_2 :: PS FPU1 Pipe Active */
#define chv__sampler_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler_2 :: PS Send Pipeline Active */
#define chv__sampler_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler_2 :: FS Both FPU Active */
#define chv__sampler_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler_2 :: Rasterized Pixels */
#define chv__sampler_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler_2 :: Early Hi-Depth Test Fails */
#define chv__sampler_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler_2 :: Early Depth Test Fails */
#define chv__sampler_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler_2 :: Samples Killed in FS */
#define chv__sampler_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler_2 :: Pixels Failing Tests */
#define chv__sampler_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler_2 :: Samples Written */
#define chv__sampler_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler_2 :: Samples Blended */
#define chv__sampler_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler_2 :: Sampler Texels */
#define chv__sampler_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler_2 :: Sampler Texels Misses */
#define chv__sampler_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler_2 :: SLM Bytes Read */
#define chv__sampler_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler_2 :: SLM Bytes Read */
#define chv__sampler_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler_2 :: SLM Bytes Written */
#define chv__sampler_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler_2 :: SLM Bytes Written */
#define chv__sampler_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler_2 :: Shader Memory Accesses */
#define chv__sampler_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler_2 :: Shader Atomic Memory Accesses */
#define chv__sampler_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler_2 :: L3 Shader Throughput */
#define chv__sampler_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler_2 :: L3 Shader Throughput */
#define chv__sampler_2__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set Sampler_2 :: Shader Barrier Messages */
#define chv__sampler_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler_2 :: Slice0 Subslice1 Input Available */
#define chv__sampler_2__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler_2 :: Slice0 Subslice2 Input Available */
#define chv__sampler_2__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler_2 :: Slice0 Subslice0 Input Available */
#define chv__sampler_2__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler_2 :: Slice0 Subslice2 Sampler Output Ready */
#define chv__sampler_2__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler_2 :: Slice0 Subslice0 Sampler Output Ready */
#define chv__sampler_2__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler_2 :: Slice0 Subslice1 Sampler Output Ready */
#define chv__sampler_2__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler_2 :: SQ is full */
#define chv__sampler_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define chv__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define chv__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define chv__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define chv__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define chv__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define chv__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define chv__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define chv__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define chv__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define chv__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define chv__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define chv__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define chv__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define chv__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define chv__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define chv__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define chv__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define chv__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define chv__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define chv__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define chv__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define chv__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define chv__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define chv__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define chv__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define chv__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define chv__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define chv__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define chv__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define chv__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define chv__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define chv__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define chv__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define chv__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define chv__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define chv__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define chv__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define chv__tdl_1__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define chv__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice1 */
#define chv__tdl_1__non_ps_thread11_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice0 */
#define chv__tdl_1__ps_thread10_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice0 */
#define chv__tdl_1__non_ps_thread10_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice2 */
#define chv__tdl_1__ps_thread12_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice2 */
#define chv__tdl_1__non_ps_thread12_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice1 */
#define chv__tdl_1__ps_thread11_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define chv__tdl_1__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define chv__tdl_1__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define chv__tdl_1__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define chv__tdl_1__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define chv__tdl_1__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define chv__tdl_1__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_1 :: SQ is full */
#define chv__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define chv__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define chv__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define chv__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define chv__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define chv__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define chv__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define chv__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define chv__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define chv__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define chv__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define chv__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define chv__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define chv__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define chv__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define chv__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define chv__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define chv__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define chv__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define chv__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define chv__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define chv__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define chv__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define chv__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define chv__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define chv__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define chv__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define chv__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define chv__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define chv__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define chv__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define chv__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define chv__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define chv__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define chv__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define chv__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define chv__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define chv__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define chv__tdl_2__l3_shader_throughput__max \
   bdw__hdc_and_sf__l3_shader_throughput__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define chv__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define chv__tdl_2__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define chv__tdl_2__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define chv__tdl_2__ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define chv__tdl_2__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define chv__tdl_2__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define chv__tdl_2__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 0 */
#define chv__tdl_2__thread_header12_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 1 */
#define chv__tdl_2__thread_header12_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 1 */
#define chv__tdl_2__thread_header11_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 0 */
#define chv__tdl_2__thread_header10_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 1 */
#define chv__tdl_2__thread_header10_ready_port1__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 0 */
#define chv__tdl_2__thread_header11_ready_port0__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define chv__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* MDAPI testing set :: GPU Time Elapsed */
#define chv__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define chv__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define chv__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define chv__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define chv__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define chv__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define chv__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define chv__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define chv__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define chv__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define chv__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define chv__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define chv__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define sklgt2__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define sklgt2__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt2__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt2__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define sklgt2__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define sklgt2__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define sklgt2__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define sklgt2__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define sklgt2__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define sklgt2__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define sklgt2__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define sklgt2__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define sklgt2__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define sklgt2__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define sklgt2__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define sklgt2__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define sklgt2__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define sklgt2__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define sklgt2__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define sklgt2__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define sklgt2__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define sklgt2__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define sklgt2__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define sklgt2__render_basic__samplers_busy__read \
   bdw__render_basic__samplers_busy__read

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define sklgt2__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
#define sklgt2__render_basic__sampler1_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define sklgt2__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define sklgt2__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define sklgt2__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define sklgt2__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define sklgt2__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define sklgt2__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define sklgt2__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define sklgt2__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define sklgt2__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
static uint64_t
sklgt2__render_basic__sampler_l1_misses__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ 8 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = tmp0 * 8;

   return tmp1;
}

/* Render Metrics Basic set :: SLM Bytes Read */
#define sklgt2__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define sklgt2__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define sklgt2__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define sklgt2__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define sklgt2__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define sklgt2__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
static uint64_t
sklgt2__render_basic__l3_lookups__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */
   uint64_t tmp0 = sklgt2__render_basic__sampler_l1_misses__read(perf, query, results) + sklgt2__render_basic__shader_memory_accesses__read(perf, query, results);

   return tmp0;
}

/* Render Metrics Basic set :: L3 Misses */
#define sklgt2__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
static uint64_t
sklgt2__render_basic__l3_sampler_throughput__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: $SamplerL1Misses 64 UMUL */
   uint64_t tmp0 = sklgt2__render_basic__sampler_l1_misses__read(perf, query, results) * 64;

   return tmp0;
}

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define sklgt2__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define sklgt2__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define sklgt2__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define sklgt2__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define sklgt2__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define sklgt2__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define sklgt2__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define sklgt2__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define sklgt2__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define sklgt2__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define sklgt2__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define sklgt2__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define sklgt2__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define sklgt2__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define sklgt2__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define sklgt2__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define sklgt2__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define sklgt2__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define sklgt2__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define sklgt2__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define sklgt2__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt2__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt2__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define sklgt2__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define sklgt2__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define sklgt2__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define sklgt2__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define sklgt2__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define sklgt2__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define sklgt2__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define sklgt2__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define sklgt2__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define sklgt2__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define sklgt2__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define sklgt2__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define sklgt2__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define sklgt2__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define sklgt2__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define sklgt2__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define sklgt2__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define sklgt2__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define sklgt2__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define sklgt2__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define sklgt2__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define sklgt2__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define sklgt2__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define sklgt2__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define sklgt2__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define sklgt2__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define sklgt2__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define sklgt2__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define sklgt2__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define sklgt2__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define sklgt2__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define sklgt2__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define sklgt2__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define sklgt2__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define sklgt2__compute_basic__typed_bytes_read__read \
   bdw__compute_basic__typed_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define sklgt2__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
#define sklgt2__compute_basic__typed_bytes_written__read \
   bdw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Typed Bytes Written */
#define sklgt2__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define sklgt2__compute_basic__untyped_bytes_read__read \
   bdw__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define sklgt2__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define sklgt2__compute_basic__untyped_bytes_written__read \
   bdw__compute_basic__untyped_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define sklgt2__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define sklgt2__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define sklgt2__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define sklgt2__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define sklgt2__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define sklgt2__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define sklgt2__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define sklgt2__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define sklgt2__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define sklgt2__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define sklgt2__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define sklgt2__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define sklgt2__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define sklgt2__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define sklgt2__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define sklgt2__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define sklgt2__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define sklgt2__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define sklgt2__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define sklgt2__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define sklgt2__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define sklgt2__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define sklgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define sklgt2__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define sklgt2__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define sklgt2__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define sklgt2__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define sklgt2__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define sklgt2__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define sklgt2__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define sklgt2__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define sklgt2__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define sklgt2__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define sklgt2__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define sklgt2__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define sklgt2__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define sklgt2__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define sklgt2__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define sklgt2__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define sklgt2__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define sklgt2__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define sklgt2__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define sklgt2__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define sklgt2__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define sklgt2__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define sklgt2__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define sklgt2__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define sklgt2__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define sklgt2__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define sklgt2__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define sklgt2__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define sklgt2__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory Reads Distribution metrics set :: GPU Time Elapsed */
#define sklgt2__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metrics set :: GPU Core Clocks */
#define sklgt2__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt2__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt2__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metrics set :: GPU Busy */
#define sklgt2__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metrics set :: VS Threads Dispatched */
#define sklgt2__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: HS Threads Dispatched */
#define sklgt2__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metrics set :: DS Threads Dispatched */
#define sklgt2__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metrics set :: GS Threads Dispatched */
#define sklgt2__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: FS Threads Dispatched */
#define sklgt2__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metrics set :: CS Threads Dispatched */
#define sklgt2__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metrics set :: EU Active */
#define sklgt2__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metrics set :: EU Stall */
#define sklgt2__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metrics set :: Rasterized Pixels */
#define sklgt2__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metrics set :: Early Hi-Depth Test Fails */
#define sklgt2__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Early Depth Test Fails */
#define sklgt2__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Samples Killed in FS */
#define sklgt2__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metrics set :: Pixels Failing Tests */
#define sklgt2__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metrics set :: Samples Written */
#define sklgt2__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metrics set :: Samples Blended */
#define sklgt2__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metrics set :: Sampler Texels */
#define sklgt2__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metrics set :: Sampler Texels Misses */
#define sklgt2__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define sklgt2__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define sklgt2__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define sklgt2__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define sklgt2__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: Shader Memory Accesses */
#define sklgt2__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metrics set :: Shader Atomic Memory Accesses */
#define sklgt2__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metrics set :: Shader Barrier Messages */
#define sklgt2__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: GtiCmdStreamerMemoryReads */
#define sklgt2__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metrics set :: GtiRsMemoryReads */
#define sklgt2__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metrics set :: GtiVfMemoryReads */
#define sklgt2__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metrics set :: GtiRccMemoryReads */
#define sklgt2__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiMscMemoryReads */
#define sklgt2__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metrics set :: GtiHizMemoryReads */
#define sklgt2__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiStcMemoryReads */
#define sklgt2__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metrics set :: GtiRczMemoryReads */
#define sklgt2__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metrics set :: GtiMemoryReads */
#define sklgt2__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank0Reads */
#define sklgt2__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank1Reads */
#define sklgt2__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metrics set :: GtiL3Bank2Reads */
#define sklgt2__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metrics set :: GtiL3Bank3Reads */
#define sklgt2__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: GtiL3Reads */
#define sklgt2__memory_reads__gti_l3_reads__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Reads Distribution metrics set :: GtiRingAccesses */
#define sklgt2__memory_reads__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Memory Writes Distribution metrics set :: GPU Time Elapsed */
#define sklgt2__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metrics set :: GPU Core Clocks */
#define sklgt2__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt2__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt2__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metrics set :: GPU Busy */
#define sklgt2__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metrics set :: VS Threads Dispatched */
#define sklgt2__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: HS Threads Dispatched */
#define sklgt2__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metrics set :: DS Threads Dispatched */
#define sklgt2__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metrics set :: GS Threads Dispatched */
#define sklgt2__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: FS Threads Dispatched */
#define sklgt2__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metrics set :: CS Threads Dispatched */
#define sklgt2__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metrics set :: EU Active */
#define sklgt2__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metrics set :: EU Stall */
#define sklgt2__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metrics set :: Rasterized Pixels */
#define sklgt2__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metrics set :: Early Hi-Depth Test Fails */
#define sklgt2__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Early Depth Test Fails */
#define sklgt2__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Samples Killed in FS */
#define sklgt2__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metrics set :: Pixels Failing Tests */
#define sklgt2__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metrics set :: Samples Written */
#define sklgt2__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metrics set :: Samples Blended */
#define sklgt2__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metrics set :: Sampler Texels */
#define sklgt2__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metrics set :: Sampler Texels Misses */
#define sklgt2__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define sklgt2__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define sklgt2__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define sklgt2__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define sklgt2__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Memory Accesses */
#define sklgt2__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metrics set :: Shader Atomic Memory Accesses */
#define sklgt2__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define sklgt2__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define sklgt2__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Barrier Messages */
#define sklgt2__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: GtiCmdStreamerMemoryWrites */
#define sklgt2__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metrics set :: GtiSoMemoryWrites */
#define sklgt2__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metrics set :: GtiRccMemoryWrites */
#define sklgt2__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiMscMemoryWrites */
#define sklgt2__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metrics set :: GtiHizMemoryWrites */
#define sklgt2__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiStcMemoryWrites */
#define sklgt2__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metrics set :: GtiRczMemoryWrites */
#define sklgt2__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metrics set :: GtiMemoryWrites */
#define sklgt2__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank0Writes */
#define sklgt2__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank1Writes */
#define sklgt2__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metrics set :: GtiL3Bank2Writes */
#define sklgt2__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metrics set :: GtiL3Bank3Writes */
#define sklgt2__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: GtiL3Writes */
#define sklgt2__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metrics set :: GtiRingAccesses */
#define sklgt2__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended metrics set :: GPU Time Elapsed */
#define sklgt2__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended metrics set :: GPU Core Clocks */
#define sklgt2__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended metrics set :: AVG GPU Core Frequency */
#define sklgt2__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended metrics set :: AVG GPU Core Frequency */
#define sklgt2__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended metrics set :: CS Threads Dispatched */
#define sklgt2__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended metrics set :: EU Active */
#define sklgt2__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended metrics set :: EU Stall */
#define sklgt2__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended metrics set :: EU Both FPU Pipes Active */
#define sklgt2__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended metrics set :: EU FPU0 Pipe Active */
#define sklgt2__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended metrics set :: EU FPU1 Pipe Active */
#define sklgt2__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended metrics set :: EU AVG IPC Rate */
#define sklgt2__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended metrics set :: EU AVG IPC Rate */
#define sklgt2__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended metrics set :: EU Send Pipe Active */
#define sklgt2__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended metrics set :: EU Thread Occupancy */
#define sklgt2__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended metrics set :: Sampler Texels */
#define sklgt2__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended metrics set :: Sampler Texels Misses */
#define sklgt2__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended metrics set :: SLM Bytes Read */
#define sklgt2__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended metrics set :: SLM Bytes Read */
#define sklgt2__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended metrics set :: SLM Bytes Written */
#define sklgt2__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended metrics set :: SLM Bytes Written */
#define sklgt2__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended metrics set :: Shader Memory Accesses */
#define sklgt2__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended metrics set :: Shader Atomic Memory Accesses */
#define sklgt2__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended metrics set :: L3 Shader Throughput */
#define sklgt2__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended metrics set :: L3 Shader Throughput */
#define sklgt2__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended metrics set :: Shader Barrier Messages */
#define sklgt2__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended metrics set :: EuUntypedReads0 */
#define sklgt2__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended metrics set :: EuTypedReads0 */
#define sklgt2__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended metrics set :: EuUntypedWrites0 */
#define sklgt2__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended metrics set :: EuTypedWrites0 */
#define sklgt2__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended metrics set :: EuUntypedAtomics0 */
#define sklgt2__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended metrics set :: EuTypedAtomics0 */
#define sklgt2__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended metrics set :: EuA64UntypedReads0 */
#define sklgt2__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended metrics set :: EuA64UntypedWrites0 */
#define sklgt2__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended metrics set :: Typed Reads 0 */
#define sklgt2__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended metrics set :: Typed Writes 0 */
#define sklgt2__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended metrics set :: Untyped Reads 0 */
#define sklgt2__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended metrics set :: Untyped Writes 0 */
#define sklgt2__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended metrics set :: Typed Atomics 0 */
#define sklgt2__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended metrics set :: TypedReadsPerCacheLine */
#define sklgt2__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended metrics set :: TypedWritesPerCacheLine */
#define sklgt2__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended metrics set :: UntypedReadsPerCacheLine */
#define sklgt2__compute_extended__untyped_reads_per_cache_line__read \
   bdw__compute_extended__untyped_reads_per_cache_line__read

/* Compute Metrics Extended metrics set :: UntypedWritesPerCacheLine */
#define sklgt2__compute_extended__untyped_writes_per_cache_line__read \
   bdw__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics Extended metrics set :: TypedAtomicsPerCacheLine */
#define sklgt2__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache metrics set :: GPU Time Elapsed */
#define sklgt2__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache metrics set :: GPU Core Clocks */
#define sklgt2__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache metrics set :: AVG GPU Core Frequency */
#define sklgt2__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache metrics set :: AVG GPU Core Frequency */
#define sklgt2__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache metrics set :: GPU Busy */
#define sklgt2__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache metrics set :: VS Threads Dispatched */
#define sklgt2__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metrics set :: HS Threads Dispatched */
#define sklgt2__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache metrics set :: DS Threads Dispatched */
#define sklgt2__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache metrics set :: GS Threads Dispatched */
#define sklgt2__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metrics set :: FS Threads Dispatched */
#define sklgt2__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache metrics set :: CS Threads Dispatched */
#define sklgt2__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache metrics set :: EU Active */
#define sklgt2__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache metrics set :: EU Stall */
#define sklgt2__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache metrics set :: EU Both FPU Pipes Active */
#define sklgt2__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Pipe Active */
#define sklgt2__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Pipe Active */
#define sklgt2__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache metrics set :: EU AVG IPC Rate */
#define sklgt2__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache metrics set :: EU AVG IPC Rate */
#define sklgt2__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache metrics set :: EU Send Pipe Active */
#define sklgt2__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Hybrid Instruction */
#define sklgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Hybrid Instruction */
#define sklgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Ternary Instruction */
#define sklgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Ternary Instruction */
#define sklgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Binary Instruction */
#define sklgt2__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Binary Instruction */
#define sklgt2__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Move Instruction */
#define sklgt2__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Move Instruction */
#define sklgt2__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache metrics set :: Rasterized Pixels */
#define sklgt2__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache metrics set :: Early Hi-Depth Test Fails */
#define sklgt2__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache metrics set :: Early Depth Test Fails */
#define sklgt2__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metrics set :: Samples Killed in FS */
#define sklgt2__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache metrics set :: Pixels Failing Tests */
#define sklgt2__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache metrics set :: Samples Written */
#define sklgt2__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache metrics set :: Samples Blended */
#define sklgt2__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache metrics set :: Sampler Accesses */
#define sklgt2__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache metrics set :: Sampler Texels */
#define sklgt2__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache metrics set :: Sampler Texels Misses */
#define sklgt2__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Read */
#define sklgt2__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Read */
#define sklgt2__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Written */
#define sklgt2__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Written */
#define sklgt2__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metrics set :: Shader Memory Accesses */
#define sklgt2__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache metrics set :: Shader Atomic Memory Accesses */
#define sklgt2__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache metrics set :: L3 Accesses */
static uint64_t
sklgt2__compute_l3_cache__l3_accesses__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ C 1 READ B 2 READ B 3 READ UADD UADD UADD 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   uint64_t tmp2 = results->accumulator[query->b_offset + 2];
   uint64_t tmp3 = results->accumulator[query->b_offset + 3];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = tmp1 + tmp4;
   uint64_t tmp6 = tmp0 + tmp5;
   uint64_t tmp7 = tmp6 * 2;

   return tmp7;
}

/* Compute Metrics L3 Cache metrics set :: L3 Misses */
#define sklgt2__compute_l3_cache__l3_misses__read \
   bdw__compute_l3_cache__l3_misses__read

/* Compute Metrics L3 Cache metrics set :: L3 Sampler Throughput */
#define sklgt2__compute_l3_cache__l3_sampler_throughput__read \
   chv__render_basic__l3_sampler_throughput__read

/* Compute Metrics L3 Cache metrics set :: L3 Sampler Throughput */
#define sklgt2__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metrics set :: L3 Shader Throughput */
#define sklgt2__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache metrics set :: L3 Shader Throughput */
#define sklgt2__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metrics set :: L3 Total Throughput */
static uint64_t
sklgt2__compute_l3_cache__l3_total_throughput__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $L3Accesses 64 UMUL */
   uint64_t tmp0 = sklgt2__compute_l3_cache__l3_accesses__read(perf, query, results) * 64;

   return tmp0;
}

/* Compute Metrics L3 Cache metrics set :: L3 Total Throughput */
#define sklgt2__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metrics set :: Shader Barrier Messages */
#define sklgt2__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 00 Accesses */
#define sklgt2__compute_l3_cache__l3_bank00_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 01 Accesses */
#define sklgt2__compute_l3_cache__l3_bank01_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 02 Accesses */
#define sklgt2__compute_l3_cache__l3_bank02_accesses__read \
   bdw__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 03 Accesses */
#define sklgt2__compute_l3_cache__l3_bank03_accesses__read \
   bdw__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 00 IC Accesses */
#define sklgt2__compute_l3_cache__l3_bank00_ic_accesses__read \
   bdw__compute_l3_cache__l3_bank00_ic_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 00 IC Hits */
#define sklgt2__compute_l3_cache__l3_bank00_ic_hits__read \
   bdw__compute_l3_cache__l3_bank00_ic_hits__read

/* Compute Metrics L3 Cache metrics set :: GTI L3 Throughput */
#define sklgt2__compute_l3_cache__gti_l3_throughput__read \
   bdw__compute_l3_cache__gti_l3_throughput__read

/* Compute Metrics L3 Cache metrics set :: GTI L3 Throughput */
#define sklgt2__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metrics set :: GTI Read Throughput */
#define sklgt2__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache metrics set :: GTI Read Throughput */
#define sklgt2__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache metrics set :: GTI Write Throughput */
#define sklgt2__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache metrics set :: GTI Write Throughput */
#define sklgt2__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define sklgt2__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define sklgt2__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define sklgt2__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define sklgt2__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define sklgt2__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define sklgt2__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define sklgt2__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define sklgt2__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define sklgt2__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define sklgt2__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define sklgt2__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define sklgt2__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define sklgt2__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define sklgt2__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define sklgt2__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define sklgt2__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define sklgt2__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define sklgt2__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define sklgt2__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define sklgt2__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define sklgt2__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define sklgt2__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define sklgt2__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define sklgt2__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define sklgt2__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define sklgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define sklgt2__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define sklgt2__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define sklgt2__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define sklgt2__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define sklgt2__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define sklgt2__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define sklgt2__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define sklgt2__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define sklgt2__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define sklgt2__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define sklgt2__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define sklgt2__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define sklgt2__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define sklgt2__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define sklgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define sklgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
#define sklgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define sklgt2__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define sklgt2__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define sklgt2__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define sklgt2__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define sklgt2__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define sklgt2__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define sklgt2__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define sklgt2__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define sklgt2__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define sklgt2__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define sklgt2__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define sklgt2__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define sklgt2__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define sklgt2__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define sklgt2__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define sklgt2__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define sklgt2__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define sklgt2__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define sklgt2__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define sklgt2__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define sklgt2__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define sklgt2__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define sklgt2__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define sklgt2__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define sklgt2__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define sklgt2__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define sklgt2__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define sklgt2__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define sklgt2__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define sklgt2__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define sklgt2__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define sklgt2__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define sklgt2__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define sklgt2__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define sklgt2__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define sklgt2__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define sklgt2__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define sklgt2__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define sklgt2__l3_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define sklgt2__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */
#define sklgt2__l3_1__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */
#define sklgt2__l3_1__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define sklgt2__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define sklgt2__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define sklgt2__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_2 :: GPU Time Elapsed */
#define sklgt2__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_2 :: GPU Core Clocks */
#define sklgt2__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define sklgt2__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define sklgt2__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_2 :: GPU Busy */
#define sklgt2__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_2 :: VS Threads Dispatched */
#define sklgt2__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_2 :: HS Threads Dispatched */
#define sklgt2__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_2 :: DS Threads Dispatched */
#define sklgt2__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_2 :: GS Threads Dispatched */
#define sklgt2__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_2 :: FS Threads Dispatched */
#define sklgt2__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_2 :: CS Threads Dispatched */
#define sklgt2__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_2 :: EU Active */
#define sklgt2__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_2 :: EU Stall */
#define sklgt2__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_2 :: EU Both FPU Pipes Active */
#define sklgt2__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_2 :: VS FPU0 Pipe Active */
#define sklgt2__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_2 :: VS FPU1 Pipe Active */
#define sklgt2__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_2 :: VS Send Pipe Active */
#define sklgt2__l3_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_2 :: PS FPU0 Pipe Active */
#define sklgt2__l3_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_2 :: PS FPU1 Pipe Active */
#define sklgt2__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_2 :: PS Send Pipeline Active */
#define sklgt2__l3_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_2 :: FS Both FPU Active */
#define sklgt2__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_2 :: Rasterized Pixels */
#define sklgt2__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_2 :: Early Hi-Depth Test Fails */
#define sklgt2__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_2 :: Early Depth Test Fails */
#define sklgt2__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Samples Killed in FS */
#define sklgt2__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_2 :: Pixels Failing Tests */
#define sklgt2__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_2 :: Samples Written */
#define sklgt2__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_2 :: Samples Blended */
#define sklgt2__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_2 :: Sampler Texels */
#define sklgt2__l3_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_2 :: Sampler Texels Misses */
#define sklgt2__l3_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_2 :: SLM Bytes Read */
#define sklgt2__l3_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_2 :: SLM Bytes Read */
#define sklgt2__l3_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: SLM Bytes Written */
#define sklgt2__l3_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_2 :: SLM Bytes Written */
#define sklgt2__l3_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Memory Accesses */
#define sklgt2__l3_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_2 :: Shader Atomic Memory Accesses */
#define sklgt2__l3_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define sklgt2__l3_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define sklgt2__l3_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Barrier Messages */
#define sklgt2__l3_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */
#define sklgt2__l3_2__l30_bank2_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Active */
#define sklgt2__l3_2__l30_bank2_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_2 :: SQ is full */
#define sklgt2__l3_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_3 :: GPU Time Elapsed */
#define sklgt2__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_3 :: GPU Core Clocks */
#define sklgt2__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define sklgt2__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define sklgt2__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_3 :: GPU Busy */
#define sklgt2__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_3 :: VS Threads Dispatched */
#define sklgt2__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_3 :: HS Threads Dispatched */
#define sklgt2__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_3 :: DS Threads Dispatched */
#define sklgt2__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_3 :: GS Threads Dispatched */
#define sklgt2__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_3 :: FS Threads Dispatched */
#define sklgt2__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_3 :: CS Threads Dispatched */
#define sklgt2__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_3 :: EU Active */
#define sklgt2__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_3 :: EU Stall */
#define sklgt2__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_3 :: EU Both FPU Pipes Active */
#define sklgt2__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_3 :: VS FPU0 Pipe Active */
#define sklgt2__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_3 :: VS FPU1 Pipe Active */
#define sklgt2__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_3 :: VS Send Pipe Active */
#define sklgt2__l3_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_3 :: PS FPU0 Pipe Active */
#define sklgt2__l3_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_3 :: PS FPU1 Pipe Active */
#define sklgt2__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_3 :: PS Send Pipeline Active */
#define sklgt2__l3_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_3 :: FS Both FPU Active */
#define sklgt2__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_3 :: Rasterized Pixels */
#define sklgt2__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_3 :: Early Hi-Depth Test Fails */
#define sklgt2__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_3 :: Early Depth Test Fails */
#define sklgt2__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Samples Killed in FS */
#define sklgt2__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_3 :: Pixels Failing Tests */
#define sklgt2__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_3 :: Samples Written */
#define sklgt2__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_3 :: Samples Blended */
#define sklgt2__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_3 :: Sampler Texels */
#define sklgt2__l3_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_3 :: Sampler Texels Misses */
#define sklgt2__l3_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_3 :: SLM Bytes Read */
#define sklgt2__l3_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_3 :: SLM Bytes Read */
#define sklgt2__l3_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: SLM Bytes Written */
#define sklgt2__l3_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_3 :: SLM Bytes Written */
#define sklgt2__l3_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Memory Accesses */
#define sklgt2__l3_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_3 :: Shader Atomic Memory Accesses */
#define sklgt2__l3_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define sklgt2__l3_3__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define sklgt2__l3_3__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Barrier Messages */
#define sklgt2__l3_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */
#define sklgt2__l3_3__l30_bank3_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Active */
#define sklgt2__l3_3__l30_bank3_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_3 :: SQ is full */
#define sklgt2__l3_3__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define sklgt2__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define sklgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define sklgt2__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define sklgt2__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define sklgt2__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define sklgt2__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define sklgt2__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define sklgt2__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define sklgt2__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define sklgt2__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define sklgt2__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define sklgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define sklgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define sklgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define sklgt2__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define sklgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define sklgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define sklgt2__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define sklgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define sklgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define sklgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define sklgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define sklgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define sklgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define sklgt2__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define sklgt2__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define sklgt2__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define sklgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define sklgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define sklgt2__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define sklgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define sklgt2__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define sklgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define sklgt2__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define sklgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define sklgt2__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define sklgt2__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define sklgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define sklgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define sklgt2__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define sklgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define sklgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define sklgt2__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler :: GPU Time Elapsed */
#define sklgt2__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler :: GPU Core Clocks */
#define sklgt2__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define sklgt2__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define sklgt2__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler :: GPU Busy */
#define sklgt2__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler :: VS Threads Dispatched */
#define sklgt2__sampler__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler :: HS Threads Dispatched */
#define sklgt2__sampler__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler :: DS Threads Dispatched */
#define sklgt2__sampler__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler :: GS Threads Dispatched */
#define sklgt2__sampler__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler :: FS Threads Dispatched */
#define sklgt2__sampler__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler :: CS Threads Dispatched */
#define sklgt2__sampler__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler :: EU Active */
#define sklgt2__sampler__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler :: EU Stall */
#define sklgt2__sampler__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler :: EU Both FPU Pipes Active */
#define sklgt2__sampler__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler :: VS FPU0 Pipe Active */
#define sklgt2__sampler__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler :: VS FPU1 Pipe Active */
#define sklgt2__sampler__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler :: VS Send Pipe Active */
#define sklgt2__sampler__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler :: PS FPU0 Pipe Active */
#define sklgt2__sampler__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler :: PS FPU1 Pipe Active */
#define sklgt2__sampler__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler :: PS Send Pipeline Active */
#define sklgt2__sampler__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler :: FS Both FPU Active */
#define sklgt2__sampler__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler :: Rasterized Pixels */
#define sklgt2__sampler__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler :: Early Hi-Depth Test Fails */
#define sklgt2__sampler__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler :: Early Depth Test Fails */
#define sklgt2__sampler__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Samples Killed in FS */
#define sklgt2__sampler__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler :: Pixels Failing Tests */
#define sklgt2__sampler__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler :: Samples Written */
#define sklgt2__sampler__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler :: Samples Blended */
#define sklgt2__sampler__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler :: Sampler Texels */
#define sklgt2__sampler__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler :: Sampler Texels Misses */
#define sklgt2__sampler__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler :: SLM Bytes Read */
#define sklgt2__sampler__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler :: SLM Bytes Read */
#define sklgt2__sampler__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: SLM Bytes Written */
#define sklgt2__sampler__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler :: SLM Bytes Written */
#define sklgt2__sampler__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Memory Accesses */
#define sklgt2__sampler__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler :: Shader Atomic Memory Accesses */
#define sklgt2__sampler__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler :: L3 Shader Throughput */
#define sklgt2__sampler__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler :: L3 Shader Throughput */
#define sklgt2__sampler__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Barrier Messages */
#define sklgt2__sampler__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Slice0 Subslice1 Input Available */
#define sklgt2__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler :: Slice0 Subslice2 Input Available */
#define sklgt2__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler :: Slice0 Subslice0 Input Available */
#define sklgt2__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */
#define sklgt2__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */
#define sklgt2__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */
#define sklgt2__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler :: SQ is full */
#define sklgt2__sampler__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define sklgt2__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define sklgt2__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define sklgt2__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define sklgt2__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define sklgt2__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define sklgt2__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define sklgt2__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define sklgt2__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define sklgt2__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define sklgt2__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define sklgt2__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define sklgt2__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define sklgt2__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define sklgt2__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define sklgt2__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define sklgt2__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define sklgt2__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define sklgt2__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define sklgt2__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define sklgt2__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define sklgt2__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define sklgt2__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define sklgt2__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define sklgt2__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define sklgt2__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define sklgt2__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define sklgt2__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define sklgt2__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define sklgt2__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define sklgt2__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define sklgt2__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define sklgt2__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define sklgt2__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define sklgt2__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define sklgt2__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define sklgt2__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define sklgt2__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define sklgt2__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define sklgt2__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define sklgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define sklgt2__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define sklgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define sklgt2__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define sklgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define sklgt2__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: SQ is full */
#define sklgt2__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define sklgt2__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define sklgt2__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define sklgt2__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define sklgt2__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define sklgt2__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define sklgt2__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define sklgt2__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define sklgt2__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define sklgt2__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define sklgt2__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define sklgt2__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define sklgt2__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define sklgt2__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define sklgt2__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define sklgt2__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define sklgt2__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define sklgt2__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define sklgt2__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define sklgt2__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define sklgt2__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define sklgt2__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define sklgt2__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define sklgt2__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define sklgt2__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define sklgt2__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define sklgt2__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define sklgt2__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define sklgt2__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define sklgt2__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define sklgt2__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define sklgt2__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define sklgt2__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define sklgt2__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define sklgt2__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define sklgt2__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define sklgt2__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define sklgt2__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define sklgt2__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define sklgt2__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define sklgt2__tdl_2__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define sklgt2__tdl_2__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define sklgt2__tdl_2__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define sklgt2__tdl_2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define sklgt2__tdl_2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define sklgt2__tdl_2__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define sklgt2__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define sklgt2__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define sklgt2__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define sklgt2__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define sklgt2__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define sklgt2__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extra set :: EU FPU1 Pipe Active including Ext Math */
static float
sklgt2__compute_extra__fpu1_active_adjusted__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: A 8 READ  C 7 READ C 6 READ FADD C 5 READ FADD 8 FMUL FADD 100 FMUL $EuCoresTotalCount FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 8];
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   uint64_t tmp2 = results->accumulator[query->c_offset + 6];
   double tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   double tmp5 = tmp3 + tmp4;
   double tmp6 = tmp5 * 8;
   double tmp7 = tmp0 + tmp6;
   double tmp8 = tmp7 * 100;
   double tmp9 = tmp8;
   double tmp10 = perf->sys_vars.n_eus;
   double tmp11 = tmp10 ? tmp9 / tmp10 : 0;
   double tmp12 = tmp11;
   double tmp13 = sklgt2__compute_extra__gpu_core_clocks__read(perf, query, results);
   double tmp14 = tmp13 ? tmp12 / tmp13 : 0;

   return tmp14;
}

/* Media Vme Pipe metrics set :: GPU Time Elapsed */
#define sklgt2__vme_pipe__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Media Vme Pipe metrics set :: GPU Core Clocks */
#define sklgt2__vme_pipe__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define sklgt2__vme_pipe__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define sklgt2__vme_pipe__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Media Vme Pipe metrics set :: GPU Busy */
#define sklgt2__vme_pipe__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Media Vme Pipe metrics set :: CS Threads Dispatched */
#define sklgt2__vme_pipe__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Media Vme Pipe metrics set :: EU Active */
#define sklgt2__vme_pipe__eu_active__read \
   bdw__render_basic__eu_active__read

/* Media Vme Pipe metrics set :: EU Stall */
#define sklgt2__vme_pipe__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Media Vme Pipe metrics set :: EU Both FPU Pipes Active */
#define sklgt2__vme_pipe__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Media Vme Pipe metrics set :: EU Thread Occupancy */
#define sklgt2__vme_pipe__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* Media Vme Pipe metrics set :: VME Busy */
#define sklgt2__vme_pipe__vme_busy__read \
   bdw__vme_pipe__vme_busy__read

/* Gpu Rings Busyness :: GPU Time Elapsed */
#define sklgt2__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness :: GPU Core Clocks */
#define sklgt2__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define sklgt2__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define sklgt2__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness :: Render Ring Busy */
#define sklgt2__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: Vdbox0 Ring Busy */
#define sklgt2__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness :: Vebox Ring Busy */
#define sklgt2__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness :: Blitter Ring Busy */
#define sklgt2__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness :: AnyRingBusy */
#define sklgt2__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* FF Bottlenecks :: GPU Time Elapsed */
#define sklgt2__ff_bottlenecks__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* FF Bottlenecks :: GPU Core Clocks */
#define sklgt2__ff_bottlenecks__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* FF Bottlenecks :: AVG GPU Core Frequency */
#define sklgt2__ff_bottlenecks__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* FF Bottlenecks :: AVG GPU Core Frequency */
#define sklgt2__ff_bottlenecks__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* FF Bottlenecks :: GPU Busy */
#define sklgt2__ff_bottlenecks__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* FF Bottlenecks :: VS Threads Dispatched */
#define sklgt2__ff_bottlenecks__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* FF Bottlenecks :: HS Threads Dispatched */
#define sklgt2__ff_bottlenecks__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* FF Bottlenecks :: DS Threads Dispatched */
#define sklgt2__ff_bottlenecks__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* FF Bottlenecks :: GS Threads Dispatched */
#define sklgt2__ff_bottlenecks__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* FF Bottlenecks :: FS Threads Dispatched */
#define sklgt2__ff_bottlenecks__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* FF Bottlenecks :: CS Threads Dispatched */
#define sklgt2__ff_bottlenecks__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* FF Bottlenecks :: Rasterized Pixels */
#define sklgt2__ff_bottlenecks__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* FF Bottlenecks :: Early Hi-Depth Test Fails */
#define sklgt2__ff_bottlenecks__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* FF Bottlenecks :: Early Depth Test Fails */
#define sklgt2__ff_bottlenecks__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* FF Bottlenecks :: Samples Killed in FS */
#define sklgt2__ff_bottlenecks__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* FF Bottlenecks :: Pixels Failing Tests */
#define sklgt2__ff_bottlenecks__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* FF Bottlenecks :: Samples Written */
#define sklgt2__ff_bottlenecks__samples_written__read \
   bdw__render_basic__samples_written__read

/* FF Bottlenecks :: Samples Blended */
#define sklgt2__ff_bottlenecks__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* FF Bottlenecks :: EU Active */
#define sklgt2__ff_bottlenecks__eu_active__read \
   bdw__render_basic__eu_active__read

/* FF Bottlenecks :: EU Stall */
#define sklgt2__ff_bottlenecks__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* FF Bottlenecks :: EU Both FPU Pipes Active */
#define sklgt2__ff_bottlenecks__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* FF Bottlenecks :: EU Thread Occupancy */
static float
sklgt2__ff_bottlenecks__eu_thread_occupancy__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: 8 A 17 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];
   double tmp1 = 8 * tmp0;
   double tmp2 = tmp1;
   double tmp3 = perf->devinfo.num_thread_per_eu;
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;
   uint64_t tmp5 = tmp4;
   uint64_t tmp6 = perf->sys_vars.n_eus;
   uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0;
   uint64_t tmp8 = tmp7 * 100;
   double tmp9 = tmp8;
   double tmp10 = sklgt2__ff_bottlenecks__gpu_core_clocks__read(perf, query, results);
   double tmp11 = tmp10 ? tmp9 / tmp10 : 0;

   return tmp11;
}

/* FF Bottlenecks :: VS FPU0 Pipe Active */
#define sklgt2__ff_bottlenecks__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* FF Bottlenecks :: VS FPU1 Pipe Active */
#define sklgt2__ff_bottlenecks__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* FF Bottlenecks :: PS FPU0 Pipe Active */
#define sklgt2__ff_bottlenecks__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* FF Bottlenecks :: PS FPU1 Pipe Active */
#define sklgt2__ff_bottlenecks__ps_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* FF Bottlenecks :: VS is sending vertices to CL */
static float
sklgt2__ff_bottlenecks__vs_cl_bypass__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 4 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = sklgt2__ff_bottlenecks__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* FF Bottlenecks :: HS Bottleneck */
#define sklgt2__ff_bottlenecks__hs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* FF Bottlenecks :: DS Bottleneck */
static float
sklgt2__ff_bottlenecks__ds_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ B 5 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = sklgt2__ff_bottlenecks__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* FF Bottlenecks :: TE Bottleneck */
static float
sklgt2__ff_bottlenecks__te_bottleneck__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ B 6 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = sklgt2__ff_bottlenecks__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* FF Bottlenecks :: GS Bottleneck */
#define sklgt2__ff_bottlenecks__gs_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* MDAPI testing set :: GPU Time Elapsed */
#define sklgt2__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define sklgt2__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define sklgt2__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define sklgt2__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define sklgt2__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define sklgt2__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define sklgt2__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define sklgt2__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define sklgt2__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define sklgt2__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define sklgt2__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define sklgt2__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define sklgt2__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define sklgt2__pma__stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define sklgt2__pma__stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define sklgt2__pma__stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define sklgt2__pma__stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: STC PMA stall */
static float
sklgt2__pma__stall__stc_pma_stall__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = sklgt2__pma__stall__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* AsyncCompute :: GPU Time Elapsed */
#define sklgt2__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define sklgt2__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define sklgt2__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define sklgt2__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define sklgt2__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define sklgt2__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define sklgt2__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define sklgt2__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define sklgt2__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define sklgt2__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define sklgt2__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: EU FPU0 Pipe Active */
#define sklgt2__async_compute__fpu0_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: VS FPU0 Pipe Active */
#define sklgt2__async_compute__vs_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: PS FPU0 Pipe Active */
#define sklgt2__async_compute__ps_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: CS FPU0 Pipe Active */
#define sklgt2__async_compute__cs_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: EU FPU1 Pipe Active */
#define sklgt2__async_compute__fpu1_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: VS FPU1 Pipe Active */
#define sklgt2__async_compute__vs_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: PS FPU1 Pipe Active */
#define sklgt2__async_compute__ps_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: CS FPU1 Pipe Active */
#define sklgt2__async_compute__cs_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: EU Thread Occupancy */
#define sklgt2__async_compute__eu_thread_occupancy__read \
   sklgt2__ff_bottlenecks__eu_thread_occupancy__read

/* AsyncCompute :: EU Active */
#define sklgt2__async_compute__eu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: EU Stall */
#define sklgt2__async_compute__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define sklgt3__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define sklgt3__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt3__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt3__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define sklgt3__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define sklgt3__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define sklgt3__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define sklgt3__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define sklgt3__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define sklgt3__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define sklgt3__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define sklgt3__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define sklgt3__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define sklgt3__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define sklgt3__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define sklgt3__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define sklgt3__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define sklgt3__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define sklgt3__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define sklgt3__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define sklgt3__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define sklgt3__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define sklgt3__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define sklgt3__render_basic__samplers_busy__read \
   bdw__render_basic__samplers_busy__read

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define sklgt3__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
#define sklgt3__render_basic__sampler1_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define sklgt3__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define sklgt3__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define sklgt3__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define sklgt3__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define sklgt3__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define sklgt3__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define sklgt3__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define sklgt3__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define sklgt3__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
#define sklgt3__render_basic__sampler_l1_misses__read \
   bdw__render_basic__sampler_l1_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define sklgt3__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define sklgt3__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define sklgt3__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define sklgt3__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define sklgt3__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define sklgt3__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
#define sklgt3__render_basic__l3_lookups__read \
   bdw__render_basic__l3_lookups__read

/* Render Metrics Basic set :: L3 Misses */
#define sklgt3__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define sklgt3__render_basic__l3_sampler_throughput__read \
   bdw__render_basic__l3_sampler_throughput__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define sklgt3__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define sklgt3__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define sklgt3__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define sklgt3__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define sklgt3__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define sklgt3__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define sklgt3__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define sklgt3__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define sklgt3__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define sklgt3__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define sklgt3__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define sklgt3__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define sklgt3__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define sklgt3__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define sklgt3__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define sklgt3__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define sklgt3__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define sklgt3__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define sklgt3__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define sklgt3__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define sklgt3__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt3__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt3__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define sklgt3__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define sklgt3__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define sklgt3__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define sklgt3__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define sklgt3__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define sklgt3__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define sklgt3__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define sklgt3__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define sklgt3__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define sklgt3__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define sklgt3__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define sklgt3__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define sklgt3__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define sklgt3__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define sklgt3__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define sklgt3__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define sklgt3__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define sklgt3__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define sklgt3__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define sklgt3__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define sklgt3__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define sklgt3__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define sklgt3__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define sklgt3__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define sklgt3__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define sklgt3__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define sklgt3__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define sklgt3__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define sklgt3__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define sklgt3__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define sklgt3__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define sklgt3__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define sklgt3__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define sklgt3__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define sklgt3__compute_basic__typed_bytes_read__read \
   bdw__compute_basic__typed_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define sklgt3__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
#define sklgt3__compute_basic__typed_bytes_written__read \
   bdw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Typed Bytes Written */
#define sklgt3__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define sklgt3__compute_basic__untyped_bytes_read__read \
   bdw__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define sklgt3__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define sklgt3__compute_basic__untyped_bytes_written__read \
   bdw__compute_basic__untyped_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define sklgt3__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define sklgt3__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define sklgt3__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define sklgt3__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define sklgt3__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define sklgt3__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define sklgt3__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define sklgt3__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define sklgt3__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define sklgt3__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define sklgt3__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define sklgt3__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define sklgt3__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define sklgt3__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define sklgt3__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define sklgt3__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define sklgt3__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define sklgt3__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define sklgt3__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define sklgt3__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define sklgt3__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define sklgt3__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define sklgt3__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define sklgt3__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define sklgt3__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define sklgt3__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define sklgt3__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define sklgt3__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define sklgt3__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define sklgt3__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define sklgt3__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define sklgt3__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define sklgt3__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define sklgt3__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define sklgt3__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define sklgt3__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define sklgt3__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define sklgt3__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define sklgt3__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define sklgt3__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define sklgt3__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define sklgt3__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define sklgt3__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define sklgt3__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define sklgt3__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define sklgt3__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define sklgt3__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define sklgt3__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define sklgt3__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define sklgt3__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define sklgt3__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define sklgt3__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory Reads Distribution metrics set :: GPU Time Elapsed */
#define sklgt3__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metrics set :: GPU Core Clocks */
#define sklgt3__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt3__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt3__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metrics set :: GPU Busy */
#define sklgt3__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metrics set :: VS Threads Dispatched */
#define sklgt3__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: HS Threads Dispatched */
#define sklgt3__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metrics set :: DS Threads Dispatched */
#define sklgt3__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metrics set :: GS Threads Dispatched */
#define sklgt3__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: FS Threads Dispatched */
#define sklgt3__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metrics set :: CS Threads Dispatched */
#define sklgt3__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metrics set :: EU Active */
#define sklgt3__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metrics set :: EU Stall */
#define sklgt3__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metrics set :: Rasterized Pixels */
#define sklgt3__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metrics set :: Early Hi-Depth Test Fails */
#define sklgt3__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Early Depth Test Fails */
#define sklgt3__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Samples Killed in FS */
#define sklgt3__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metrics set :: Pixels Failing Tests */
#define sklgt3__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metrics set :: Samples Written */
#define sklgt3__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metrics set :: Samples Blended */
#define sklgt3__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metrics set :: Sampler Texels */
#define sklgt3__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metrics set :: Sampler Texels Misses */
#define sklgt3__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define sklgt3__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define sklgt3__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define sklgt3__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define sklgt3__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: Shader Memory Accesses */
#define sklgt3__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metrics set :: Shader Atomic Memory Accesses */
#define sklgt3__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metrics set :: Shader Barrier Messages */
#define sklgt3__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: GtiCmdStreamerMemoryReads */
#define sklgt3__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metrics set :: GtiRsMemoryReads */
#define sklgt3__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metrics set :: GtiVfMemoryReads */
#define sklgt3__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metrics set :: GtiRccMemoryReads */
#define sklgt3__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiMscMemoryReads */
#define sklgt3__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metrics set :: GtiHizMemoryReads */
#define sklgt3__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiStcMemoryReads */
#define sklgt3__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metrics set :: GtiRczMemoryReads */
#define sklgt3__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metrics set :: GtiMemoryReads */
#define sklgt3__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank0Reads */
#define sklgt3__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank1Reads */
#define sklgt3__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metrics set :: GtiL3Bank2Reads */
#define sklgt3__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metrics set :: GtiL3Bank3Reads */
#define sklgt3__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: GtiL3Reads */
#define sklgt3__memory_reads__gti_l3_reads__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Reads Distribution metrics set :: GtiRingAccesses */
#define sklgt3__memory_reads__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Memory Writes Distribution metrics set :: GPU Time Elapsed */
#define sklgt3__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metrics set :: GPU Core Clocks */
#define sklgt3__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt3__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt3__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metrics set :: GPU Busy */
#define sklgt3__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metrics set :: VS Threads Dispatched */
#define sklgt3__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: HS Threads Dispatched */
#define sklgt3__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metrics set :: DS Threads Dispatched */
#define sklgt3__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metrics set :: GS Threads Dispatched */
#define sklgt3__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: FS Threads Dispatched */
#define sklgt3__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metrics set :: CS Threads Dispatched */
#define sklgt3__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metrics set :: EU Active */
#define sklgt3__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metrics set :: EU Stall */
#define sklgt3__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metrics set :: Rasterized Pixels */
#define sklgt3__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metrics set :: Early Hi-Depth Test Fails */
#define sklgt3__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Early Depth Test Fails */
#define sklgt3__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Samples Killed in FS */
#define sklgt3__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metrics set :: Pixels Failing Tests */
#define sklgt3__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metrics set :: Samples Written */
#define sklgt3__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metrics set :: Samples Blended */
#define sklgt3__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metrics set :: Sampler Texels */
#define sklgt3__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metrics set :: Sampler Texels Misses */
#define sklgt3__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define sklgt3__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define sklgt3__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define sklgt3__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define sklgt3__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Memory Accesses */
#define sklgt3__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metrics set :: Shader Atomic Memory Accesses */
#define sklgt3__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define sklgt3__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define sklgt3__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Barrier Messages */
#define sklgt3__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: GtiCmdStreamerMemoryWrites */
#define sklgt3__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metrics set :: GtiSoMemoryWrites */
#define sklgt3__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metrics set :: GtiRccMemoryWrites */
#define sklgt3__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiMscMemoryWrites */
#define sklgt3__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metrics set :: GtiHizMemoryWrites */
#define sklgt3__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiStcMemoryWrites */
#define sklgt3__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metrics set :: GtiRczMemoryWrites */
#define sklgt3__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metrics set :: GtiMemoryWrites */
#define sklgt3__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank0Writes */
#define sklgt3__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank1Writes */
#define sklgt3__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metrics set :: GtiL3Bank2Writes */
#define sklgt3__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metrics set :: GtiL3Bank3Writes */
#define sklgt3__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: GtiL3Writes */
#define sklgt3__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metrics set :: GtiRingAccesses */
#define sklgt3__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended set :: GPU Time Elapsed */
#define sklgt3__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended set :: GPU Core Clocks */
#define sklgt3__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define sklgt3__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define sklgt3__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended set :: CS Threads Dispatched */
#define sklgt3__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended set :: EU Active */
#define sklgt3__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended set :: EU Stall */
#define sklgt3__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended set :: EU Both FPU Pipes Active */
#define sklgt3__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended set :: EU FPU0 Pipe Active */
#define sklgt3__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended set :: EU FPU1 Pipe Active */
#define sklgt3__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define sklgt3__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define sklgt3__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended set :: EU Send Pipe Active */
#define sklgt3__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended set :: EU Thread Occupancy */
#define sklgt3__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended set :: Sampler Texels */
#define sklgt3__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended set :: Sampler Texels Misses */
#define sklgt3__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define sklgt3__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define sklgt3__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: SLM Bytes Written */
#define sklgt3__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended set :: SLM Bytes Written */
#define sklgt3__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Memory Accesses */
#define sklgt3__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended set :: Shader Atomic Memory Accesses */
#define sklgt3__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define sklgt3__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define sklgt3__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Barrier Messages */
#define sklgt3__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended set :: EuUntypedReads0 */
#define sklgt3__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended set :: EuTypedReads0 */
#define sklgt3__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended set :: EuUntypedWrites0 */
#define sklgt3__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended set :: EuTypedWrites0 */
#define sklgt3__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended set :: EuUntypedAtomics0 */
#define sklgt3__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended set :: EuTypedAtomics0 */
#define sklgt3__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedReads0 */
#define sklgt3__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedWrites0 */
#define sklgt3__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended set :: Typed Reads 0 */
#define sklgt3__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: Typed Writes 0 */
#define sklgt3__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended set :: Untyped Reads 0 */
#define sklgt3__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended set :: Untyped Writes 0 */
#define sklgt3__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended set :: Typed Atomics 0 */
#define sklgt3__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended set :: TypedReadsPerCacheLine */
#define sklgt3__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended set :: TypedWritesPerCacheLine */
#define sklgt3__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended set :: UntypedReadsPerCacheLine */
#define sklgt3__compute_extended__untyped_reads_per_cache_line__read \
   bdw__compute_extended__untyped_reads_per_cache_line__read

/* Compute Metrics Extended set :: UntypedWritesPerCacheLine */
#define sklgt3__compute_extended__untyped_writes_per_cache_line__read \
   bdw__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics Extended set :: TypedAtomicsPerCacheLine */
#define sklgt3__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache set :: GPU Time Elapsed */
#define sklgt3__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache set :: GPU Core Clocks */
#define sklgt3__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define sklgt3__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define sklgt3__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache set :: GPU Busy */
#define sklgt3__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache set :: VS Threads Dispatched */
#define sklgt3__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: HS Threads Dispatched */
#define sklgt3__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache set :: DS Threads Dispatched */
#define sklgt3__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache set :: GS Threads Dispatched */
#define sklgt3__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: FS Threads Dispatched */
#define sklgt3__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache set :: CS Threads Dispatched */
#define sklgt3__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache set :: EU Active */
#define sklgt3__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache set :: EU Stall */
#define sklgt3__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache set :: EU Both FPU Pipes Active */
#define sklgt3__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Pipe Active */
#define sklgt3__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Pipe Active */
#define sklgt3__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define sklgt3__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define sklgt3__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache set :: EU Send Pipe Active */
#define sklgt3__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Hybrid Instruction */
#define sklgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Hybrid Instruction */
#define sklgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU0 Ternary Instruction */
#define sklgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Ternary Instruction */
#define sklgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Binary Instruction */
#define sklgt3__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Binary Instruction */
#define sklgt3__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Move Instruction */
#define sklgt3__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Move Instruction */
#define sklgt3__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: Rasterized Pixels */
#define sklgt3__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache set :: Early Hi-Depth Test Fails */
#define sklgt3__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Early Depth Test Fails */
#define sklgt3__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Samples Killed in FS */
#define sklgt3__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache set :: Pixels Failing Tests */
#define sklgt3__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache set :: Samples Written */
#define sklgt3__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache set :: Samples Blended */
#define sklgt3__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache set :: Sampler Accesses */
#define sklgt3__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache set :: Sampler Texels */
#define sklgt3__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache set :: Sampler Texels Misses */
#define sklgt3__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define sklgt3__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define sklgt3__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define sklgt3__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define sklgt3__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: Shader Memory Accesses */
#define sklgt3__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache set :: Shader Atomic Memory Accesses */
#define sklgt3__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache set :: L3 Accesses */
#define sklgt3__compute_l3_cache__l3_accesses__read \
   sklgt2__compute_l3_cache__l3_accesses__read

/* Compute Metrics L3 Cache set :: L3 Misses */
#define sklgt3__compute_l3_cache__l3_misses__read \
   bdw__compute_l3_cache__l3_misses__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define sklgt3__compute_l3_cache__l3_sampler_throughput__read \
   chv__render_basic__l3_sampler_throughput__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define sklgt3__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define sklgt3__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define sklgt3__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define sklgt3__compute_l3_cache__l3_total_throughput__read \
   sklgt2__compute_l3_cache__l3_total_throughput__read

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define sklgt3__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: Shader Barrier Messages */
#define sklgt3__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 Accesses */
#define sklgt3__compute_l3_cache__l3_bank00_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 01 Accesses */
#define sklgt3__compute_l3_cache__l3_bank01_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 02 Accesses */
#define sklgt3__compute_l3_cache__l3_bank02_accesses__read \
   bdw__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 03 Accesses */
#define sklgt3__compute_l3_cache__l3_bank03_accesses__read \
   bdw__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Accesses */
#define sklgt3__compute_l3_cache__l3_bank00_ic_accesses__read \
   bdw__compute_l3_cache__l3_bank00_ic_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Hits */
#define sklgt3__compute_l3_cache__l3_bank00_ic_hits__read \
   bdw__compute_l3_cache__l3_bank00_ic_hits__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define sklgt3__compute_l3_cache__gti_l3_throughput__read \
   bdw__compute_l3_cache__gti_l3_throughput__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define sklgt3__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define sklgt3__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define sklgt3__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define sklgt3__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define sklgt3__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define sklgt3__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define sklgt3__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define sklgt3__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define sklgt3__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define sklgt3__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define sklgt3__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define sklgt3__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define sklgt3__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define sklgt3__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define sklgt3__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define sklgt3__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define sklgt3__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define sklgt3__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define sklgt3__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define sklgt3__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define sklgt3__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define sklgt3__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define sklgt3__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define sklgt3__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define sklgt3__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define sklgt3__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define sklgt3__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define sklgt3__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define sklgt3__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define sklgt3__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define sklgt3__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define sklgt3__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define sklgt3__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define sklgt3__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define sklgt3__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define sklgt3__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define sklgt3__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define sklgt3__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define sklgt3__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define sklgt3__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define sklgt3__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define sklgt3__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define sklgt3__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define sklgt3__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define sklgt3__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define sklgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define sklgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
#define sklgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define sklgt3__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define sklgt3__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define sklgt3__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define sklgt3__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define sklgt3__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define sklgt3__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define sklgt3__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define sklgt3__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define sklgt3__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define sklgt3__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define sklgt3__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define sklgt3__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define sklgt3__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define sklgt3__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define sklgt3__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define sklgt3__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define sklgt3__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define sklgt3__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define sklgt3__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define sklgt3__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define sklgt3__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define sklgt3__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define sklgt3__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define sklgt3__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define sklgt3__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define sklgt3__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define sklgt3__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define sklgt3__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define sklgt3__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define sklgt3__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define sklgt3__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define sklgt3__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define sklgt3__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define sklgt3__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define sklgt3__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define sklgt3__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define sklgt3__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define sklgt3__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define sklgt3__l3_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define sklgt3__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */
#define sklgt3__l3_1__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */
#define sklgt3__l3_1__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define sklgt3__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define sklgt3__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define sklgt3__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_2 :: GPU Time Elapsed */
#define sklgt3__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_2 :: GPU Core Clocks */
#define sklgt3__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define sklgt3__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define sklgt3__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_2 :: GPU Busy */
#define sklgt3__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_2 :: VS Threads Dispatched */
#define sklgt3__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_2 :: HS Threads Dispatched */
#define sklgt3__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_2 :: DS Threads Dispatched */
#define sklgt3__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_2 :: GS Threads Dispatched */
#define sklgt3__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_2 :: FS Threads Dispatched */
#define sklgt3__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_2 :: CS Threads Dispatched */
#define sklgt3__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_2 :: EU Active */
#define sklgt3__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_2 :: EU Stall */
#define sklgt3__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_2 :: EU Both FPU Pipes Active */
#define sklgt3__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_2 :: VS FPU0 Pipe Active */
#define sklgt3__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_2 :: VS FPU1 Pipe Active */
#define sklgt3__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_2 :: VS Send Pipe Active */
#define sklgt3__l3_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_2 :: PS FPU0 Pipe Active */
#define sklgt3__l3_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_2 :: PS FPU1 Pipe Active */
#define sklgt3__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_2 :: PS Send Pipeline Active */
#define sklgt3__l3_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_2 :: FS Both FPU Active */
#define sklgt3__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_2 :: Rasterized Pixels */
#define sklgt3__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_2 :: Early Hi-Depth Test Fails */
#define sklgt3__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_2 :: Early Depth Test Fails */
#define sklgt3__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Samples Killed in FS */
#define sklgt3__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_2 :: Pixels Failing Tests */
#define sklgt3__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_2 :: Samples Written */
#define sklgt3__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_2 :: Samples Blended */
#define sklgt3__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_2 :: Sampler Texels */
#define sklgt3__l3_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_2 :: Sampler Texels Misses */
#define sklgt3__l3_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_2 :: SLM Bytes Read */
#define sklgt3__l3_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_2 :: SLM Bytes Read */
#define sklgt3__l3_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: SLM Bytes Written */
#define sklgt3__l3_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_2 :: SLM Bytes Written */
#define sklgt3__l3_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Memory Accesses */
#define sklgt3__l3_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_2 :: Shader Atomic Memory Accesses */
#define sklgt3__l3_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define sklgt3__l3_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define sklgt3__l3_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Barrier Messages */
#define sklgt3__l3_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */
#define sklgt3__l3_2__l30_bank2_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Active */
#define sklgt3__l3_2__l30_bank2_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_2 :: SQ is full */
#define sklgt3__l3_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_3 :: GPU Time Elapsed */
#define sklgt3__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_3 :: GPU Core Clocks */
#define sklgt3__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define sklgt3__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define sklgt3__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_3 :: GPU Busy */
#define sklgt3__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_3 :: VS Threads Dispatched */
#define sklgt3__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_3 :: HS Threads Dispatched */
#define sklgt3__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_3 :: DS Threads Dispatched */
#define sklgt3__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_3 :: GS Threads Dispatched */
#define sklgt3__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_3 :: FS Threads Dispatched */
#define sklgt3__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_3 :: CS Threads Dispatched */
#define sklgt3__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_3 :: EU Active */
#define sklgt3__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_3 :: EU Stall */
#define sklgt3__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_3 :: EU Both FPU Pipes Active */
#define sklgt3__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_3 :: VS FPU0 Pipe Active */
#define sklgt3__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_3 :: VS FPU1 Pipe Active */
#define sklgt3__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_3 :: VS Send Pipe Active */
#define sklgt3__l3_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_3 :: PS FPU0 Pipe Active */
#define sklgt3__l3_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_3 :: PS FPU1 Pipe Active */
#define sklgt3__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_3 :: PS Send Pipeline Active */
#define sklgt3__l3_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_3 :: FS Both FPU Active */
#define sklgt3__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_3 :: Rasterized Pixels */
#define sklgt3__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_3 :: Early Hi-Depth Test Fails */
#define sklgt3__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_3 :: Early Depth Test Fails */
#define sklgt3__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Samples Killed in FS */
#define sklgt3__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_3 :: Pixels Failing Tests */
#define sklgt3__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_3 :: Samples Written */
#define sklgt3__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_3 :: Samples Blended */
#define sklgt3__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_3 :: Sampler Texels */
#define sklgt3__l3_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_3 :: Sampler Texels Misses */
#define sklgt3__l3_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_3 :: SLM Bytes Read */
#define sklgt3__l3_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_3 :: SLM Bytes Read */
#define sklgt3__l3_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: SLM Bytes Written */
#define sklgt3__l3_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_3 :: SLM Bytes Written */
#define sklgt3__l3_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Memory Accesses */
#define sklgt3__l3_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_3 :: Shader Atomic Memory Accesses */
#define sklgt3__l3_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define sklgt3__l3_3__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define sklgt3__l3_3__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Barrier Messages */
#define sklgt3__l3_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */
#define sklgt3__l3_3__l30_bank3_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Active */
#define sklgt3__l3_3__l30_bank3_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_3 :: SQ is full */
#define sklgt3__l3_3__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define sklgt3__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define sklgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define sklgt3__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define sklgt3__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define sklgt3__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define sklgt3__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define sklgt3__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define sklgt3__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define sklgt3__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define sklgt3__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define sklgt3__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define sklgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define sklgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define sklgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define sklgt3__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define sklgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define sklgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define sklgt3__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define sklgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define sklgt3__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define sklgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define sklgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define sklgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define sklgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define sklgt3__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define sklgt3__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define sklgt3__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define sklgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define sklgt3__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define sklgt3__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define sklgt3__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define sklgt3__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define sklgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define sklgt3__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define sklgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define sklgt3__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define sklgt3__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define sklgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define sklgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define sklgt3__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define sklgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define sklgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define sklgt3__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler :: GPU Time Elapsed */
#define sklgt3__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler :: GPU Core Clocks */
#define sklgt3__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define sklgt3__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define sklgt3__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler :: GPU Busy */
#define sklgt3__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler :: VS Threads Dispatched */
#define sklgt3__sampler__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler :: HS Threads Dispatched */
#define sklgt3__sampler__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler :: DS Threads Dispatched */
#define sklgt3__sampler__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler :: GS Threads Dispatched */
#define sklgt3__sampler__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler :: FS Threads Dispatched */
#define sklgt3__sampler__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler :: CS Threads Dispatched */
#define sklgt3__sampler__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler :: EU Active */
#define sklgt3__sampler__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler :: EU Stall */
#define sklgt3__sampler__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler :: EU Both FPU Pipes Active */
#define sklgt3__sampler__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler :: VS FPU0 Pipe Active */
#define sklgt3__sampler__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler :: VS FPU1 Pipe Active */
#define sklgt3__sampler__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler :: VS Send Pipe Active */
#define sklgt3__sampler__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler :: PS FPU0 Pipe Active */
#define sklgt3__sampler__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler :: PS FPU1 Pipe Active */
#define sklgt3__sampler__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler :: PS Send Pipeline Active */
#define sklgt3__sampler__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler :: FS Both FPU Active */
#define sklgt3__sampler__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler :: Rasterized Pixels */
#define sklgt3__sampler__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler :: Early Hi-Depth Test Fails */
#define sklgt3__sampler__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler :: Early Depth Test Fails */
#define sklgt3__sampler__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Samples Killed in FS */
#define sklgt3__sampler__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler :: Pixels Failing Tests */
#define sklgt3__sampler__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler :: Samples Written */
#define sklgt3__sampler__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler :: Samples Blended */
#define sklgt3__sampler__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler :: Sampler Texels */
#define sklgt3__sampler__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler :: Sampler Texels Misses */
#define sklgt3__sampler__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler :: SLM Bytes Read */
#define sklgt3__sampler__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler :: SLM Bytes Read */
#define sklgt3__sampler__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: SLM Bytes Written */
#define sklgt3__sampler__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler :: SLM Bytes Written */
#define sklgt3__sampler__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Memory Accesses */
#define sklgt3__sampler__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler :: Shader Atomic Memory Accesses */
#define sklgt3__sampler__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler :: L3 Shader Throughput */
#define sklgt3__sampler__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler :: L3 Shader Throughput */
#define sklgt3__sampler__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Barrier Messages */
#define sklgt3__sampler__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Slice0 Subslice1 Input Available */
#define sklgt3__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler :: Slice0 Subslice2 Input Available */
#define sklgt3__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler :: Slice0 Subslice0 Input Available */
#define sklgt3__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */
#define sklgt3__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */
#define sklgt3__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */
#define sklgt3__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler :: SQ is full */
#define sklgt3__sampler__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define sklgt3__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define sklgt3__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define sklgt3__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define sklgt3__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define sklgt3__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define sklgt3__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define sklgt3__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define sklgt3__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define sklgt3__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define sklgt3__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define sklgt3__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define sklgt3__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define sklgt3__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define sklgt3__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define sklgt3__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define sklgt3__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define sklgt3__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define sklgt3__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define sklgt3__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define sklgt3__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define sklgt3__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define sklgt3__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define sklgt3__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define sklgt3__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define sklgt3__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define sklgt3__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define sklgt3__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define sklgt3__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define sklgt3__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define sklgt3__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define sklgt3__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define sklgt3__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define sklgt3__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define sklgt3__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define sklgt3__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define sklgt3__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define sklgt3__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define sklgt3__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define sklgt3__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define sklgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define sklgt3__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define sklgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define sklgt3__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define sklgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define sklgt3__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: SQ is full */
#define sklgt3__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define sklgt3__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define sklgt3__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define sklgt3__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define sklgt3__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define sklgt3__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define sklgt3__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define sklgt3__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define sklgt3__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define sklgt3__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define sklgt3__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define sklgt3__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define sklgt3__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define sklgt3__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define sklgt3__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define sklgt3__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define sklgt3__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define sklgt3__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define sklgt3__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define sklgt3__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define sklgt3__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define sklgt3__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define sklgt3__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define sklgt3__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define sklgt3__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define sklgt3__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define sklgt3__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define sklgt3__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define sklgt3__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define sklgt3__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define sklgt3__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define sklgt3__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define sklgt3__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define sklgt3__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define sklgt3__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define sklgt3__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define sklgt3__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define sklgt3__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define sklgt3__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define sklgt3__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define sklgt3__tdl_2__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define sklgt3__tdl_2__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define sklgt3__tdl_2__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define sklgt3__tdl_2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define sklgt3__tdl_2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define sklgt3__tdl_2__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define sklgt3__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define sklgt3__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define sklgt3__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define sklgt3__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define sklgt3__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define sklgt3__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extra set :: EU FPU1 Pipe Active including Ext Math */
#define sklgt3__compute_extra__fpu1_active_adjusted__read \
   bdw__compute_extra__fpu1_active_adjusted__read

/* Media Vme Pipe metrics set :: GPU Time Elapsed */
#define sklgt3__vme_pipe__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Media Vme Pipe metrics set :: GPU Core Clocks */
#define sklgt3__vme_pipe__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define sklgt3__vme_pipe__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define sklgt3__vme_pipe__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Media Vme Pipe metrics set :: GPU Busy */
#define sklgt3__vme_pipe__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Media Vme Pipe metrics set :: CS Threads Dispatched */
#define sklgt3__vme_pipe__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Media Vme Pipe metrics set :: EU Active */
#define sklgt3__vme_pipe__eu_active__read \
   bdw__render_basic__eu_active__read

/* Media Vme Pipe metrics set :: EU Stall */
#define sklgt3__vme_pipe__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Media Vme Pipe metrics set :: EU Both FPU Pipes Active */
#define sklgt3__vme_pipe__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Media Vme Pipe metrics set :: EU Thread Occupancy */
#define sklgt3__vme_pipe__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* Media Vme Pipe metrics set :: VME Busy */
#define sklgt3__vme_pipe__vme_busy__read \
   bdw__vme_pipe__vme_busy__read

/* Gpu Rings Busyness :: GPU Time Elapsed */
#define sklgt3__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness :: GPU Core Clocks */
#define sklgt3__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define sklgt3__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define sklgt3__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness :: Render Ring Busy */
#define sklgt3__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: Vdbox0 Ring Busy */
#define sklgt3__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness :: Vdbox1 Ring Busy */
#define sklgt3__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness :: Vebox Ring Busy */
#define sklgt3__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness :: Blitter Ring Busy */
#define sklgt3__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* Gpu Rings Busyness :: AnyRingBusy */
#define sklgt3__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* MDAPI testing set :: GPU Time Elapsed */
#define sklgt3__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define sklgt3__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define sklgt3__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define sklgt3__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define sklgt3__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define sklgt3__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define sklgt3__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define sklgt3__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define sklgt3__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define sklgt3__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define sklgt3__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define sklgt3__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define sklgt3__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define sklgt3__pma__stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define sklgt3__pma__stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define sklgt3__pma__stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define sklgt3__pma__stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: STC PMA stall */
#define sklgt3__pma__stall__stc_pma_stall__read \
   sklgt2__pma__stall__stc_pma_stall__read

/* AsyncCompute :: GPU Time Elapsed */
#define sklgt3__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define sklgt3__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define sklgt3__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define sklgt3__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define sklgt3__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define sklgt3__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define sklgt3__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define sklgt3__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define sklgt3__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define sklgt3__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define sklgt3__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: EU FPU0 Pipe Active */
#define sklgt3__async_compute__fpu0_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: VS FPU0 Pipe Active */
#define sklgt3__async_compute__vs_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: PS FPU0 Pipe Active */
#define sklgt3__async_compute__ps_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: CS FPU0 Pipe Active */
#define sklgt3__async_compute__cs_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: EU FPU1 Pipe Active */
#define sklgt3__async_compute__fpu1_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: VS FPU1 Pipe Active */
#define sklgt3__async_compute__vs_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: PS FPU1 Pipe Active */
#define sklgt3__async_compute__ps_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: CS FPU1 Pipe Active */
#define sklgt3__async_compute__cs_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: EU Thread Occupancy */
#define sklgt3__async_compute__eu_thread_occupancy__read \
   sklgt2__ff_bottlenecks__eu_thread_occupancy__read

/* AsyncCompute :: EU Active */
#define sklgt3__async_compute__eu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: EU Stall */
#define sklgt3__async_compute__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define sklgt4__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define sklgt4__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt4__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt4__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define sklgt4__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define sklgt4__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define sklgt4__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define sklgt4__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define sklgt4__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define sklgt4__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define sklgt4__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define sklgt4__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define sklgt4__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define sklgt4__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define sklgt4__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define sklgt4__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define sklgt4__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define sklgt4__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define sklgt4__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define sklgt4__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define sklgt4__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define sklgt4__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define sklgt4__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define sklgt4__render_basic__samplers_busy__read \
   bdw__render_basic__samplers_busy__read

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define sklgt4__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define sklgt4__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define sklgt4__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define sklgt4__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define sklgt4__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define sklgt4__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define sklgt4__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define sklgt4__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define sklgt4__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define sklgt4__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
static uint64_t
sklgt4__render_basic__sampler_l1_misses__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ UADD B 3 READ UADD 8 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 3];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = tmp4 * 8;

   return tmp5;
}

/* Render Metrics Basic set :: SLM Bytes Read */
#define sklgt4__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define sklgt4__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define sklgt4__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define sklgt4__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define sklgt4__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define sklgt4__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
static uint64_t
sklgt4__render_basic__l3_lookups__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */
   uint64_t tmp0 = sklgt4__render_basic__sampler_l1_misses__read(perf, query, results) + sklgt4__render_basic__shader_memory_accesses__read(perf, query, results);

   return tmp0;
}

/* Render Metrics Basic set :: L3 Misses */
#define sklgt4__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
static uint64_t
sklgt4__render_basic__l3_sampler_throughput__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: $SamplerL1Misses 64 UMUL */
   uint64_t tmp0 = sklgt4__render_basic__sampler_l1_misses__read(perf, query, results) * 64;

   return tmp0;
}

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define sklgt4__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define sklgt4__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define sklgt4__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define sklgt4__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define sklgt4__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define sklgt4__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define sklgt4__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define sklgt4__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define sklgt4__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define sklgt4__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define sklgt4__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define sklgt4__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define sklgt4__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define sklgt4__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define sklgt4__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define sklgt4__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define sklgt4__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define sklgt4__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define sklgt4__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define sklgt4__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define sklgt4__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt4__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define sklgt4__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define sklgt4__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define sklgt4__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define sklgt4__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define sklgt4__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define sklgt4__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define sklgt4__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define sklgt4__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define sklgt4__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define sklgt4__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define sklgt4__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define sklgt4__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define sklgt4__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define sklgt4__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define sklgt4__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define sklgt4__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define sklgt4__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define sklgt4__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define sklgt4__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define sklgt4__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define sklgt4__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define sklgt4__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define sklgt4__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define sklgt4__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define sklgt4__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define sklgt4__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define sklgt4__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define sklgt4__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define sklgt4__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define sklgt4__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define sklgt4__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define sklgt4__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define sklgt4__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define sklgt4__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define sklgt4__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define sklgt4__compute_basic__typed_bytes_read__read \
   bdw__compute_basic__typed_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define sklgt4__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
#define sklgt4__compute_basic__typed_bytes_written__read \
   bdw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Typed Bytes Written */
#define sklgt4__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define sklgt4__compute_basic__untyped_bytes_read__read \
   bdw__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define sklgt4__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define sklgt4__compute_basic__untyped_bytes_written__read \
   bdw__compute_basic__untyped_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define sklgt4__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define sklgt4__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define sklgt4__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define sklgt4__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define sklgt4__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define sklgt4__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define sklgt4__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define sklgt4__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define sklgt4__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define sklgt4__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define sklgt4__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define sklgt4__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define sklgt4__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define sklgt4__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define sklgt4__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define sklgt4__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define sklgt4__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define sklgt4__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define sklgt4__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define sklgt4__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define sklgt4__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define sklgt4__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define sklgt4__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define sklgt4__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define sklgt4__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define sklgt4__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define sklgt4__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define sklgt4__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define sklgt4__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define sklgt4__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define sklgt4__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define sklgt4__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define sklgt4__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define sklgt4__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define sklgt4__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define sklgt4__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define sklgt4__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define sklgt4__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define sklgt4__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define sklgt4__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define sklgt4__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define sklgt4__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define sklgt4__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define sklgt4__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define sklgt4__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define sklgt4__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define sklgt4__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define sklgt4__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define sklgt4__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define sklgt4__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define sklgt4__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define sklgt4__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory Reads Distribution metrics set :: GPU Time Elapsed */
#define sklgt4__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metrics set :: GPU Core Clocks */
#define sklgt4__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt4__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt4__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metrics set :: GPU Busy */
#define sklgt4__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metrics set :: VS Threads Dispatched */
#define sklgt4__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: HS Threads Dispatched */
#define sklgt4__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metrics set :: DS Threads Dispatched */
#define sklgt4__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metrics set :: GS Threads Dispatched */
#define sklgt4__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: FS Threads Dispatched */
#define sklgt4__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metrics set :: CS Threads Dispatched */
#define sklgt4__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metrics set :: EU Active */
#define sklgt4__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metrics set :: EU Stall */
#define sklgt4__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metrics set :: Rasterized Pixels */
#define sklgt4__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metrics set :: Early Hi-Depth Test Fails */
#define sklgt4__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Early Depth Test Fails */
#define sklgt4__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Samples Killed in FS */
#define sklgt4__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metrics set :: Pixels Failing Tests */
#define sklgt4__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metrics set :: Samples Written */
#define sklgt4__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metrics set :: Samples Blended */
#define sklgt4__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metrics set :: Sampler Texels */
#define sklgt4__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metrics set :: Sampler Texels Misses */
#define sklgt4__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define sklgt4__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define sklgt4__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define sklgt4__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define sklgt4__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: Shader Memory Accesses */
#define sklgt4__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metrics set :: Shader Atomic Memory Accesses */
#define sklgt4__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metrics set :: Shader Barrier Messages */
#define sklgt4__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: GtiCmdStreamerMemoryReads */
#define sklgt4__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metrics set :: GtiRsMemoryReads */
#define sklgt4__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metrics set :: GtiVfMemoryReads */
#define sklgt4__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metrics set :: GtiRccMemoryReads */
#define sklgt4__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiMscMemoryReads */
#define sklgt4__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metrics set :: GtiHizMemoryReads */
#define sklgt4__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiStcMemoryReads */
#define sklgt4__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metrics set :: GtiRczMemoryReads */
#define sklgt4__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metrics set :: GtiMemoryReads */
#define sklgt4__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank0Reads */
#define sklgt4__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank1Reads */
#define sklgt4__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metrics set :: GtiL3Bank2Reads */
#define sklgt4__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metrics set :: GtiL3Bank3Reads */
#define sklgt4__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: GtiL3Reads */
#define sklgt4__memory_reads__gti_l3_reads__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Reads Distribution metrics set :: GtiRingAccesses */
#define sklgt4__memory_reads__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Memory Writes Distribution metrics set :: GPU Time Elapsed */
#define sklgt4__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metrics set :: GPU Core Clocks */
#define sklgt4__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt4__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define sklgt4__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metrics set :: GPU Busy */
#define sklgt4__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metrics set :: VS Threads Dispatched */
#define sklgt4__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: HS Threads Dispatched */
#define sklgt4__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metrics set :: DS Threads Dispatched */
#define sklgt4__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metrics set :: GS Threads Dispatched */
#define sklgt4__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: FS Threads Dispatched */
#define sklgt4__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metrics set :: CS Threads Dispatched */
#define sklgt4__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metrics set :: EU Active */
#define sklgt4__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metrics set :: EU Stall */
#define sklgt4__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metrics set :: Rasterized Pixels */
#define sklgt4__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metrics set :: Early Hi-Depth Test Fails */
#define sklgt4__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Early Depth Test Fails */
#define sklgt4__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Samples Killed in FS */
#define sklgt4__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metrics set :: Pixels Failing Tests */
#define sklgt4__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metrics set :: Samples Written */
#define sklgt4__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metrics set :: Samples Blended */
#define sklgt4__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metrics set :: Sampler Texels */
#define sklgt4__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metrics set :: Sampler Texels Misses */
#define sklgt4__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define sklgt4__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define sklgt4__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define sklgt4__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define sklgt4__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Memory Accesses */
#define sklgt4__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metrics set :: Shader Atomic Memory Accesses */
#define sklgt4__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define sklgt4__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define sklgt4__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Barrier Messages */
#define sklgt4__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: GtiCmdStreamerMemoryWrites */
#define sklgt4__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metrics set :: GtiSoMemoryWrites */
#define sklgt4__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metrics set :: GtiRccMemoryWrites */
#define sklgt4__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiMscMemoryWrites */
#define sklgt4__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metrics set :: GtiHizMemoryWrites */
#define sklgt4__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiStcMemoryWrites */
#define sklgt4__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metrics set :: GtiRczMemoryWrites */
#define sklgt4__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metrics set :: GtiMemoryWrites */
#define sklgt4__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank0Writes */
#define sklgt4__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank1Writes */
#define sklgt4__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metrics set :: GtiL3Bank2Writes */
#define sklgt4__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metrics set :: GtiL3Bank3Writes */
#define sklgt4__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: GtiL3Writes */
#define sklgt4__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metrics set :: GtiRingAccesses */
#define sklgt4__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended set :: GPU Time Elapsed */
#define sklgt4__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended set :: GPU Core Clocks */
#define sklgt4__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define sklgt4__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define sklgt4__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended set :: CS Threads Dispatched */
#define sklgt4__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended set :: EU Active */
#define sklgt4__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended set :: EU Stall */
#define sklgt4__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended set :: EU Both FPU Pipes Active */
#define sklgt4__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended set :: EU FPU0 Pipe Active */
#define sklgt4__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended set :: EU FPU1 Pipe Active */
#define sklgt4__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define sklgt4__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define sklgt4__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended set :: EU Send Pipe Active */
#define sklgt4__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended set :: EU Thread Occupancy */
#define sklgt4__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended set :: Sampler Texels */
#define sklgt4__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended set :: Sampler Texels Misses */
#define sklgt4__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define sklgt4__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define sklgt4__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: SLM Bytes Written */
#define sklgt4__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended set :: SLM Bytes Written */
#define sklgt4__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Memory Accesses */
#define sklgt4__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended set :: Shader Atomic Memory Accesses */
#define sklgt4__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define sklgt4__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define sklgt4__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Barrier Messages */
#define sklgt4__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended set :: EuUntypedReads0 */
#define sklgt4__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended set :: EuTypedReads0 */
#define sklgt4__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended set :: EuUntypedWrites0 */
#define sklgt4__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended set :: EuTypedWrites0 */
#define sklgt4__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended set :: EuUntypedAtomics0 */
#define sklgt4__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended set :: EuTypedAtomics0 */
#define sklgt4__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedReads0 */
#define sklgt4__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedWrites0 */
#define sklgt4__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended set :: Typed Reads 0 */
#define sklgt4__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: Typed Writes 0 */
#define sklgt4__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended set :: Untyped Reads 0 */
#define sklgt4__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended set :: Untyped Writes 0 */
#define sklgt4__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended set :: Typed Atomics 0 */
#define sklgt4__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended set :: TypedReadsPerCacheLine */
#define sklgt4__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended set :: TypedWritesPerCacheLine */
#define sklgt4__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended set :: UntypedReadsPerCacheLine */
#define sklgt4__compute_extended__untyped_reads_per_cache_line__read \
   bdw__compute_extended__untyped_reads_per_cache_line__read

/* Compute Metrics Extended set :: UntypedWritesPerCacheLine */
#define sklgt4__compute_extended__untyped_writes_per_cache_line__read \
   bdw__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics Extended set :: TypedAtomicsPerCacheLine */
#define sklgt4__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache set :: GPU Time Elapsed */
#define sklgt4__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache set :: GPU Core Clocks */
#define sklgt4__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define sklgt4__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define sklgt4__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache set :: GPU Busy */
#define sklgt4__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache set :: VS Threads Dispatched */
#define sklgt4__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: HS Threads Dispatched */
#define sklgt4__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache set :: DS Threads Dispatched */
#define sklgt4__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache set :: GS Threads Dispatched */
#define sklgt4__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: FS Threads Dispatched */
#define sklgt4__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache set :: CS Threads Dispatched */
#define sklgt4__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache set :: EU Active */
#define sklgt4__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache set :: EU Stall */
#define sklgt4__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache set :: EU Both FPU Pipes Active */
#define sklgt4__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Pipe Active */
#define sklgt4__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Pipe Active */
#define sklgt4__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define sklgt4__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define sklgt4__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache set :: EU Send Pipe Active */
#define sklgt4__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Hybrid Instruction */
#define sklgt4__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Hybrid Instruction */
#define sklgt4__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU0 Ternary Instruction */
#define sklgt4__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Ternary Instruction */
#define sklgt4__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Binary Instruction */
#define sklgt4__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Binary Instruction */
#define sklgt4__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Move Instruction */
#define sklgt4__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Move Instruction */
#define sklgt4__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: Rasterized Pixels */
#define sklgt4__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache set :: Early Hi-Depth Test Fails */
#define sklgt4__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Early Depth Test Fails */
#define sklgt4__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Samples Killed in FS */
#define sklgt4__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache set :: Pixels Failing Tests */
#define sklgt4__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache set :: Samples Written */
#define sklgt4__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache set :: Samples Blended */
#define sklgt4__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache set :: Sampler Accesses */
#define sklgt4__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache set :: Sampler Texels */
#define sklgt4__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache set :: Sampler Texels Misses */
#define sklgt4__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define sklgt4__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define sklgt4__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define sklgt4__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define sklgt4__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: Shader Memory Accesses */
#define sklgt4__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache set :: Shader Atomic Memory Accesses */
#define sklgt4__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache set :: L3 Accesses */
#define sklgt4__compute_l3_cache__l3_accesses__read \
   sklgt2__compute_l3_cache__l3_accesses__read

/* Compute Metrics L3 Cache set :: L3 Misses */
#define sklgt4__compute_l3_cache__l3_misses__read \
   bdw__compute_l3_cache__l3_misses__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define sklgt4__compute_l3_cache__l3_sampler_throughput__read \
   chv__render_basic__l3_sampler_throughput__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define sklgt4__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define sklgt4__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define sklgt4__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define sklgt4__compute_l3_cache__l3_total_throughput__read \
   sklgt2__compute_l3_cache__l3_total_throughput__read

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define sklgt4__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: Shader Barrier Messages */
#define sklgt4__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 Accesses */
#define sklgt4__compute_l3_cache__l3_bank00_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 01 Accesses */
#define sklgt4__compute_l3_cache__l3_bank01_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 02 Accesses */
#define sklgt4__compute_l3_cache__l3_bank02_accesses__read \
   bdw__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 03 Accesses */
#define sklgt4__compute_l3_cache__l3_bank03_accesses__read \
   bdw__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Accesses */
#define sklgt4__compute_l3_cache__l3_bank00_ic_accesses__read \
   bdw__compute_l3_cache__l3_bank00_ic_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Hits */
#define sklgt4__compute_l3_cache__l3_bank00_ic_hits__read \
   bdw__compute_l3_cache__l3_bank00_ic_hits__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define sklgt4__compute_l3_cache__gti_l3_throughput__read \
   bdw__compute_l3_cache__gti_l3_throughput__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define sklgt4__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define sklgt4__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define sklgt4__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define sklgt4__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define sklgt4__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define sklgt4__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define sklgt4__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define sklgt4__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define sklgt4__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define sklgt4__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define sklgt4__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define sklgt4__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define sklgt4__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define sklgt4__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define sklgt4__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define sklgt4__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define sklgt4__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define sklgt4__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define sklgt4__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define sklgt4__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define sklgt4__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define sklgt4__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define sklgt4__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define sklgt4__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define sklgt4__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define sklgt4__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define sklgt4__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define sklgt4__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define sklgt4__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define sklgt4__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define sklgt4__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define sklgt4__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define sklgt4__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define sklgt4__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define sklgt4__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define sklgt4__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define sklgt4__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define sklgt4__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define sklgt4__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define sklgt4__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define sklgt4__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define sklgt4__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define sklgt4__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define sklgt4__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define sklgt4__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define sklgt4__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define sklgt4__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
#define sklgt4__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define sklgt4__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define sklgt4__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define sklgt4__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define sklgt4__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define sklgt4__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define sklgt4__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define sklgt4__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define sklgt4__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define sklgt4__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define sklgt4__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define sklgt4__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define sklgt4__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define sklgt4__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define sklgt4__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define sklgt4__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define sklgt4__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define sklgt4__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define sklgt4__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define sklgt4__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define sklgt4__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define sklgt4__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define sklgt4__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define sklgt4__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define sklgt4__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define sklgt4__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define sklgt4__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define sklgt4__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define sklgt4__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define sklgt4__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define sklgt4__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define sklgt4__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define sklgt4__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define sklgt4__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define sklgt4__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define sklgt4__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define sklgt4__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define sklgt4__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define sklgt4__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define sklgt4__l3_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define sklgt4__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */
#define sklgt4__l3_1__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */
#define sklgt4__l3_1__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define sklgt4__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define sklgt4__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define sklgt4__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_2 :: GPU Time Elapsed */
#define sklgt4__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_2 :: GPU Core Clocks */
#define sklgt4__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define sklgt4__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define sklgt4__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_2 :: GPU Busy */
#define sklgt4__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_2 :: VS Threads Dispatched */
#define sklgt4__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_2 :: HS Threads Dispatched */
#define sklgt4__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_2 :: DS Threads Dispatched */
#define sklgt4__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_2 :: GS Threads Dispatched */
#define sklgt4__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_2 :: FS Threads Dispatched */
#define sklgt4__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_2 :: CS Threads Dispatched */
#define sklgt4__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_2 :: EU Active */
#define sklgt4__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_2 :: EU Stall */
#define sklgt4__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_2 :: EU Both FPU Pipes Active */
#define sklgt4__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_2 :: VS FPU0 Pipe Active */
#define sklgt4__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_2 :: VS FPU1 Pipe Active */
#define sklgt4__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_2 :: VS Send Pipe Active */
#define sklgt4__l3_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_2 :: PS FPU0 Pipe Active */
#define sklgt4__l3_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_2 :: PS FPU1 Pipe Active */
#define sklgt4__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_2 :: PS Send Pipeline Active */
#define sklgt4__l3_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_2 :: FS Both FPU Active */
#define sklgt4__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_2 :: Rasterized Pixels */
#define sklgt4__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_2 :: Early Hi-Depth Test Fails */
#define sklgt4__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_2 :: Early Depth Test Fails */
#define sklgt4__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Samples Killed in FS */
#define sklgt4__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_2 :: Pixels Failing Tests */
#define sklgt4__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_2 :: Samples Written */
#define sklgt4__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_2 :: Samples Blended */
#define sklgt4__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_2 :: Sampler Texels */
#define sklgt4__l3_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_2 :: Sampler Texels Misses */
#define sklgt4__l3_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_2 :: SLM Bytes Read */
#define sklgt4__l3_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_2 :: SLM Bytes Read */
#define sklgt4__l3_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: SLM Bytes Written */
#define sklgt4__l3_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_2 :: SLM Bytes Written */
#define sklgt4__l3_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Memory Accesses */
#define sklgt4__l3_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_2 :: Shader Atomic Memory Accesses */
#define sklgt4__l3_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define sklgt4__l3_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define sklgt4__l3_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Barrier Messages */
#define sklgt4__l3_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */
#define sklgt4__l3_2__l30_bank2_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Active */
#define sklgt4__l3_2__l30_bank2_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_2 :: SQ is full */
#define sklgt4__l3_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_3 :: GPU Time Elapsed */
#define sklgt4__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_3 :: GPU Core Clocks */
#define sklgt4__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define sklgt4__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define sklgt4__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_3 :: GPU Busy */
#define sklgt4__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_3 :: VS Threads Dispatched */
#define sklgt4__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_3 :: HS Threads Dispatched */
#define sklgt4__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_3 :: DS Threads Dispatched */
#define sklgt4__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_3 :: GS Threads Dispatched */
#define sklgt4__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_3 :: FS Threads Dispatched */
#define sklgt4__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_3 :: CS Threads Dispatched */
#define sklgt4__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_3 :: EU Active */
#define sklgt4__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_3 :: EU Stall */
#define sklgt4__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_3 :: EU Both FPU Pipes Active */
#define sklgt4__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_3 :: VS FPU0 Pipe Active */
#define sklgt4__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_3 :: VS FPU1 Pipe Active */
#define sklgt4__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_3 :: VS Send Pipe Active */
#define sklgt4__l3_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_3 :: PS FPU0 Pipe Active */
#define sklgt4__l3_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_3 :: PS FPU1 Pipe Active */
#define sklgt4__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_3 :: PS Send Pipeline Active */
#define sklgt4__l3_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_3 :: FS Both FPU Active */
#define sklgt4__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_3 :: Rasterized Pixels */
#define sklgt4__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_3 :: Early Hi-Depth Test Fails */
#define sklgt4__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_3 :: Early Depth Test Fails */
#define sklgt4__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Samples Killed in FS */
#define sklgt4__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_3 :: Pixels Failing Tests */
#define sklgt4__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_3 :: Samples Written */
#define sklgt4__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_3 :: Samples Blended */
#define sklgt4__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_3 :: Sampler Texels */
#define sklgt4__l3_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_3 :: Sampler Texels Misses */
#define sklgt4__l3_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_3 :: SLM Bytes Read */
#define sklgt4__l3_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_3 :: SLM Bytes Read */
#define sklgt4__l3_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: SLM Bytes Written */
#define sklgt4__l3_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_3 :: SLM Bytes Written */
#define sklgt4__l3_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Memory Accesses */
#define sklgt4__l3_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_3 :: Shader Atomic Memory Accesses */
#define sklgt4__l3_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define sklgt4__l3_3__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define sklgt4__l3_3__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Barrier Messages */
#define sklgt4__l3_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */
#define sklgt4__l3_3__l30_bank3_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Active */
#define sklgt4__l3_3__l30_bank3_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_3 :: SQ is full */
#define sklgt4__l3_3__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define sklgt4__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define sklgt4__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define sklgt4__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define sklgt4__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define sklgt4__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define sklgt4__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define sklgt4__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define sklgt4__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define sklgt4__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define sklgt4__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define sklgt4__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define sklgt4__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define sklgt4__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define sklgt4__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define sklgt4__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define sklgt4__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define sklgt4__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define sklgt4__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define sklgt4__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define sklgt4__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define sklgt4__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define sklgt4__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define sklgt4__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define sklgt4__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define sklgt4__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define sklgt4__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define sklgt4__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define sklgt4__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define sklgt4__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define sklgt4__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define sklgt4__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define sklgt4__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define sklgt4__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define sklgt4__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define sklgt4__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define sklgt4__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define sklgt4__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define sklgt4__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define sklgt4__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define sklgt4__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define sklgt4__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define sklgt4__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define sklgt4__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler :: GPU Time Elapsed */
#define sklgt4__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler :: GPU Core Clocks */
#define sklgt4__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define sklgt4__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define sklgt4__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler :: GPU Busy */
#define sklgt4__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler :: VS Threads Dispatched */
#define sklgt4__sampler__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler :: HS Threads Dispatched */
#define sklgt4__sampler__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler :: DS Threads Dispatched */
#define sklgt4__sampler__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler :: GS Threads Dispatched */
#define sklgt4__sampler__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler :: FS Threads Dispatched */
#define sklgt4__sampler__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler :: CS Threads Dispatched */
#define sklgt4__sampler__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler :: EU Active */
#define sklgt4__sampler__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler :: EU Stall */
#define sklgt4__sampler__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler :: EU Both FPU Pipes Active */
#define sklgt4__sampler__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler :: VS FPU0 Pipe Active */
#define sklgt4__sampler__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler :: VS FPU1 Pipe Active */
#define sklgt4__sampler__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler :: VS Send Pipe Active */
#define sklgt4__sampler__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler :: PS FPU0 Pipe Active */
#define sklgt4__sampler__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler :: PS FPU1 Pipe Active */
#define sklgt4__sampler__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler :: PS Send Pipeline Active */
#define sklgt4__sampler__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler :: FS Both FPU Active */
#define sklgt4__sampler__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler :: Rasterized Pixels */
#define sklgt4__sampler__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler :: Early Hi-Depth Test Fails */
#define sklgt4__sampler__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler :: Early Depth Test Fails */
#define sklgt4__sampler__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Samples Killed in FS */
#define sklgt4__sampler__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler :: Pixels Failing Tests */
#define sklgt4__sampler__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler :: Samples Written */
#define sklgt4__sampler__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler :: Samples Blended */
#define sklgt4__sampler__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler :: Sampler Texels */
#define sklgt4__sampler__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler :: Sampler Texels Misses */
#define sklgt4__sampler__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler :: SLM Bytes Read */
#define sklgt4__sampler__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler :: SLM Bytes Read */
#define sklgt4__sampler__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: SLM Bytes Written */
#define sklgt4__sampler__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler :: SLM Bytes Written */
#define sklgt4__sampler__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Memory Accesses */
#define sklgt4__sampler__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler :: Shader Atomic Memory Accesses */
#define sklgt4__sampler__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler :: L3 Shader Throughput */
#define sklgt4__sampler__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler :: L3 Shader Throughput */
#define sklgt4__sampler__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Barrier Messages */
#define sklgt4__sampler__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Slice0 Subslice1 Input Available */
#define sklgt4__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler :: Slice0 Subslice2 Input Available */
#define sklgt4__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler :: Slice0 Subslice0 Input Available */
#define sklgt4__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */
#define sklgt4__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */
#define sklgt4__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */
#define sklgt4__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler :: SQ is full */
#define sklgt4__sampler__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define sklgt4__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define sklgt4__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define sklgt4__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define sklgt4__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define sklgt4__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define sklgt4__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define sklgt4__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define sklgt4__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define sklgt4__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define sklgt4__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define sklgt4__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define sklgt4__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define sklgt4__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define sklgt4__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define sklgt4__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define sklgt4__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define sklgt4__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define sklgt4__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define sklgt4__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define sklgt4__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define sklgt4__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define sklgt4__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define sklgt4__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define sklgt4__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define sklgt4__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define sklgt4__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define sklgt4__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define sklgt4__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define sklgt4__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define sklgt4__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define sklgt4__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define sklgt4__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define sklgt4__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define sklgt4__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define sklgt4__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define sklgt4__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define sklgt4__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define sklgt4__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define sklgt4__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define sklgt4__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define sklgt4__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define sklgt4__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define sklgt4__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define sklgt4__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define sklgt4__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: SQ is full */
#define sklgt4__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define sklgt4__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define sklgt4__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define sklgt4__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define sklgt4__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define sklgt4__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define sklgt4__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define sklgt4__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define sklgt4__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define sklgt4__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define sklgt4__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define sklgt4__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define sklgt4__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define sklgt4__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define sklgt4__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define sklgt4__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define sklgt4__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define sklgt4__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define sklgt4__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define sklgt4__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define sklgt4__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define sklgt4__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define sklgt4__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define sklgt4__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define sklgt4__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define sklgt4__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define sklgt4__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define sklgt4__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define sklgt4__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define sklgt4__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define sklgt4__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define sklgt4__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define sklgt4__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define sklgt4__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define sklgt4__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define sklgt4__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define sklgt4__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define sklgt4__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define sklgt4__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define sklgt4__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define sklgt4__tdl_2__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define sklgt4__tdl_2__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define sklgt4__tdl_2__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define sklgt4__tdl_2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define sklgt4__tdl_2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define sklgt4__tdl_2__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define sklgt4__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define sklgt4__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define sklgt4__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define sklgt4__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define sklgt4__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define sklgt4__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Media Vme Pipe metrics set :: GPU Time Elapsed */
#define sklgt4__vme_pipe__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Media Vme Pipe metrics set :: GPU Core Clocks */
#define sklgt4__vme_pipe__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define sklgt4__vme_pipe__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define sklgt4__vme_pipe__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Media Vme Pipe metrics set :: GPU Busy */
#define sklgt4__vme_pipe__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Media Vme Pipe metrics set :: CS Threads Dispatched */
#define sklgt4__vme_pipe__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Media Vme Pipe metrics set :: EU Active */
#define sklgt4__vme_pipe__eu_active__read \
   bdw__render_basic__eu_active__read

/* Media Vme Pipe metrics set :: EU Stall */
#define sklgt4__vme_pipe__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Media Vme Pipe metrics set :: EU Both FPU Pipes Active */
#define sklgt4__vme_pipe__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Media Vme Pipe metrics set :: EU Thread Occupancy */
#define sklgt4__vme_pipe__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* Media Vme Pipe metrics set :: VME Busy */
#define sklgt4__vme_pipe__vme_busy__read \
   bdw__vme_pipe__vme_busy__read

/* Gpu Rings Busyness :: GPU Time Elapsed */
#define sklgt4__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness :: GPU Core Clocks */
#define sklgt4__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define sklgt4__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define sklgt4__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness :: Render Ring Busy */
#define sklgt4__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: Vdbox0 Ring Busy */
#define sklgt4__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness :: Vdbox1 Ring Busy */
#define sklgt4__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness :: Vebox Ring Busy */
#define sklgt4__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness :: Blitter Ring Busy */
#define sklgt4__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* Gpu Rings Busyness :: AnyRingBusy */
#define sklgt4__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* MDAPI testing set :: GPU Time Elapsed */
#define sklgt4__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define sklgt4__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define sklgt4__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define sklgt4__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define sklgt4__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define sklgt4__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define sklgt4__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define sklgt4__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define sklgt4__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define sklgt4__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define sklgt4__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define sklgt4__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define sklgt4__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define sklgt4__pma__stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define sklgt4__pma__stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define sklgt4__pma__stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define sklgt4__pma__stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: STC PMA stall */
#define sklgt4__pma__stall__stc_pma_stall__read \
   sklgt2__pma__stall__stc_pma_stall__read

/* AsyncCompute :: GPU Time Elapsed */
#define sklgt4__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define sklgt4__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define sklgt4__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define sklgt4__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define sklgt4__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define sklgt4__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define sklgt4__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define sklgt4__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define sklgt4__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define sklgt4__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define sklgt4__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: EU FPU0 Pipe Active */
#define sklgt4__async_compute__fpu0_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: VS FPU0 Pipe Active */
#define sklgt4__async_compute__vs_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: PS FPU0 Pipe Active */
#define sklgt4__async_compute__ps_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: CS FPU0 Pipe Active */
#define sklgt4__async_compute__cs_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: EU FPU1 Pipe Active */
#define sklgt4__async_compute__fpu1_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: VS FPU1 Pipe Active */
#define sklgt4__async_compute__vs_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: PS FPU1 Pipe Active */
#define sklgt4__async_compute__ps_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: CS FPU1 Pipe Active */
#define sklgt4__async_compute__cs_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: EU Thread Occupancy */
#define sklgt4__async_compute__eu_thread_occupancy__read \
   sklgt2__ff_bottlenecks__eu_thread_occupancy__read

/* AsyncCompute :: EU Active */
#define sklgt4__async_compute__eu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: EU Stall */
#define sklgt4__async_compute__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define kblgt2__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define kblgt2__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define kblgt2__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define kblgt2__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define kblgt2__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define kblgt2__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define kblgt2__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define kblgt2__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define kblgt2__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define kblgt2__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define kblgt2__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define kblgt2__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define kblgt2__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define kblgt2__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define kblgt2__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define kblgt2__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define kblgt2__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define kblgt2__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define kblgt2__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define kblgt2__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define kblgt2__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define kblgt2__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define kblgt2__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define kblgt2__render_basic__samplers_busy__read \
   bdw__render_basic__samplers_busy__read

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define kblgt2__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
#define kblgt2__render_basic__sampler1_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define kblgt2__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define kblgt2__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define kblgt2__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define kblgt2__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define kblgt2__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define kblgt2__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define kblgt2__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define kblgt2__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define kblgt2__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
#define kblgt2__render_basic__sampler_l1_misses__read \
   sklgt2__render_basic__sampler_l1_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define kblgt2__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define kblgt2__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define kblgt2__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define kblgt2__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define kblgt2__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define kblgt2__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
#define kblgt2__render_basic__l3_lookups__read \
   sklgt2__render_basic__l3_lookups__read

/* Render Metrics Basic set :: L3 Misses */
#define kblgt2__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define kblgt2__render_basic__l3_sampler_throughput__read \
   sklgt2__render_basic__l3_sampler_throughput__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define kblgt2__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define kblgt2__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define kblgt2__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define kblgt2__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define kblgt2__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define kblgt2__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define kblgt2__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define kblgt2__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define kblgt2__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define kblgt2__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define kblgt2__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define kblgt2__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define kblgt2__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define kblgt2__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define kblgt2__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define kblgt2__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define kblgt2__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define kblgt2__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define kblgt2__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define kblgt2__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define kblgt2__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define kblgt2__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define kblgt2__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define kblgt2__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define kblgt2__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define kblgt2__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define kblgt2__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define kblgt2__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define kblgt2__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define kblgt2__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define kblgt2__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define kblgt2__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define kblgt2__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define kblgt2__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define kblgt2__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define kblgt2__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define kblgt2__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define kblgt2__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define kblgt2__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define kblgt2__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define kblgt2__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define kblgt2__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define kblgt2__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define kblgt2__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define kblgt2__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define kblgt2__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define kblgt2__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define kblgt2__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define kblgt2__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define kblgt2__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define kblgt2__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define kblgt2__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define kblgt2__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define kblgt2__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define kblgt2__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define kblgt2__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define kblgt2__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define kblgt2__compute_basic__typed_bytes_read__read \
   bdw__compute_basic__typed_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define kblgt2__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
#define kblgt2__compute_basic__typed_bytes_written__read \
   bdw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Typed Bytes Written */
#define kblgt2__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define kblgt2__compute_basic__untyped_bytes_read__read \
   bdw__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define kblgt2__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define kblgt2__compute_basic__untyped_bytes_written__read \
   bdw__compute_basic__untyped_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define kblgt2__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define kblgt2__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define kblgt2__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define kblgt2__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define kblgt2__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define kblgt2__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define kblgt2__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define kblgt2__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define kblgt2__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define kblgt2__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define kblgt2__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define kblgt2__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define kblgt2__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define kblgt2__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define kblgt2__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define kblgt2__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define kblgt2__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define kblgt2__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define kblgt2__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define kblgt2__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define kblgt2__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define kblgt2__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define kblgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define kblgt2__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define kblgt2__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define kblgt2__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define kblgt2__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define kblgt2__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define kblgt2__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define kblgt2__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define kblgt2__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define kblgt2__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define kblgt2__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define kblgt2__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define kblgt2__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define kblgt2__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define kblgt2__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define kblgt2__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define kblgt2__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define kblgt2__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define kblgt2__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define kblgt2__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define kblgt2__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define kblgt2__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define kblgt2__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define kblgt2__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define kblgt2__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define kblgt2__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define kblgt2__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define kblgt2__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define kblgt2__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define kblgt2__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory Reads Distribution metrics set :: GPU Time Elapsed */
#define kblgt2__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metrics set :: GPU Core Clocks */
#define kblgt2__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define kblgt2__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define kblgt2__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metrics set :: GPU Busy */
#define kblgt2__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metrics set :: VS Threads Dispatched */
#define kblgt2__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: HS Threads Dispatched */
#define kblgt2__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metrics set :: DS Threads Dispatched */
#define kblgt2__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metrics set :: GS Threads Dispatched */
#define kblgt2__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: FS Threads Dispatched */
#define kblgt2__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metrics set :: CS Threads Dispatched */
#define kblgt2__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metrics set :: EU Active */
#define kblgt2__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metrics set :: EU Stall */
#define kblgt2__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metrics set :: Rasterized Pixels */
#define kblgt2__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metrics set :: Early Hi-Depth Test Fails */
#define kblgt2__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Early Depth Test Fails */
#define kblgt2__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Samples Killed in FS */
#define kblgt2__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metrics set :: Pixels Failing Tests */
#define kblgt2__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metrics set :: Samples Written */
#define kblgt2__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metrics set :: Samples Blended */
#define kblgt2__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metrics set :: Sampler Texels */
#define kblgt2__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metrics set :: Sampler Texels Misses */
#define kblgt2__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define kblgt2__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define kblgt2__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define kblgt2__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define kblgt2__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: Shader Memory Accesses */
#define kblgt2__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metrics set :: Shader Atomic Memory Accesses */
#define kblgt2__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metrics set :: Shader Barrier Messages */
#define kblgt2__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: GtiCmdStreamerMemoryReads */
#define kblgt2__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metrics set :: GtiRsMemoryReads */
#define kblgt2__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metrics set :: GtiVfMemoryReads */
#define kblgt2__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metrics set :: GtiRccMemoryReads */
#define kblgt2__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiMscMemoryReads */
#define kblgt2__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metrics set :: GtiHizMemoryReads */
#define kblgt2__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiStcMemoryReads */
#define kblgt2__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metrics set :: GtiRczMemoryReads */
#define kblgt2__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metrics set :: GtiMemoryReads */
#define kblgt2__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank0Reads */
#define kblgt2__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank1Reads */
#define kblgt2__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metrics set :: GtiL3Bank2Reads */
#define kblgt2__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metrics set :: GtiL3Bank3Reads */
#define kblgt2__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: GtiL3Reads */
#define kblgt2__memory_reads__gti_l3_reads__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Reads Distribution metrics set :: GtiRingAccesses */
#define kblgt2__memory_reads__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Memory Writes Distribution metrics set :: GPU Time Elapsed */
#define kblgt2__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metrics set :: GPU Core Clocks */
#define kblgt2__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define kblgt2__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define kblgt2__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metrics set :: GPU Busy */
#define kblgt2__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metrics set :: VS Threads Dispatched */
#define kblgt2__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: HS Threads Dispatched */
#define kblgt2__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metrics set :: DS Threads Dispatched */
#define kblgt2__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metrics set :: GS Threads Dispatched */
#define kblgt2__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: FS Threads Dispatched */
#define kblgt2__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metrics set :: CS Threads Dispatched */
#define kblgt2__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metrics set :: EU Active */
#define kblgt2__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metrics set :: EU Stall */
#define kblgt2__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metrics set :: Rasterized Pixels */
#define kblgt2__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metrics set :: Early Hi-Depth Test Fails */
#define kblgt2__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Early Depth Test Fails */
#define kblgt2__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Samples Killed in FS */
#define kblgt2__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metrics set :: Pixels Failing Tests */
#define kblgt2__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metrics set :: Samples Written */
#define kblgt2__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metrics set :: Samples Blended */
#define kblgt2__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metrics set :: Sampler Texels */
#define kblgt2__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metrics set :: Sampler Texels Misses */
#define kblgt2__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define kblgt2__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define kblgt2__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define kblgt2__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define kblgt2__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Memory Accesses */
#define kblgt2__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metrics set :: Shader Atomic Memory Accesses */
#define kblgt2__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define kblgt2__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define kblgt2__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Barrier Messages */
#define kblgt2__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: GtiCmdStreamerMemoryWrites */
#define kblgt2__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metrics set :: GtiSoMemoryWrites */
#define kblgt2__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metrics set :: GtiRccMemoryWrites */
#define kblgt2__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiMscMemoryWrites */
#define kblgt2__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metrics set :: GtiHizMemoryWrites */
#define kblgt2__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiStcMemoryWrites */
#define kblgt2__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metrics set :: GtiRczMemoryWrites */
#define kblgt2__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metrics set :: GtiMemoryWrites */
#define kblgt2__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank0Writes */
#define kblgt2__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank1Writes */
#define kblgt2__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metrics set :: GtiL3Bank2Writes */
#define kblgt2__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metrics set :: GtiL3Bank3Writes */
#define kblgt2__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: GtiL3Writes */
#define kblgt2__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metrics set :: GtiRingAccesses */
#define kblgt2__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended set :: GPU Time Elapsed */
#define kblgt2__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended set :: GPU Core Clocks */
#define kblgt2__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define kblgt2__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define kblgt2__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended set :: CS Threads Dispatched */
#define kblgt2__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended set :: EU Active */
#define kblgt2__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended set :: EU Stall */
#define kblgt2__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended set :: EU Both FPU Pipes Active */
#define kblgt2__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended set :: EU FPU0 Pipe Active */
#define kblgt2__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended set :: EU FPU1 Pipe Active */
#define kblgt2__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define kblgt2__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define kblgt2__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended set :: EU Send Pipe Active */
#define kblgt2__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended set :: EU Thread Occupancy */
#define kblgt2__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended set :: Sampler Texels */
#define kblgt2__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended set :: Sampler Texels Misses */
#define kblgt2__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define kblgt2__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define kblgt2__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: SLM Bytes Written */
#define kblgt2__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended set :: SLM Bytes Written */
#define kblgt2__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Memory Accesses */
#define kblgt2__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended set :: Shader Atomic Memory Accesses */
#define kblgt2__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define kblgt2__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define kblgt2__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Barrier Messages */
#define kblgt2__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended set :: EuUntypedReads0 */
#define kblgt2__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended set :: EuTypedReads0 */
#define kblgt2__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended set :: EuUntypedWrites0 */
#define kblgt2__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended set :: EuTypedWrites0 */
#define kblgt2__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended set :: EuUntypedAtomics0 */
#define kblgt2__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended set :: EuTypedAtomics0 */
#define kblgt2__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedReads0 */
#define kblgt2__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedWrites0 */
#define kblgt2__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended set :: Typed Reads 0 */
#define kblgt2__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: Typed Writes 0 */
#define kblgt2__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended set :: Untyped Reads 0 */
#define kblgt2__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended set :: Untyped Writes 0 */
#define kblgt2__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended set :: Typed Atomics 0 */
#define kblgt2__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended set :: TypedReadsPerCacheLine */
#define kblgt2__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended set :: TypedWritesPerCacheLine */
#define kblgt2__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended set :: UntypedReadsPerCacheLine */
#define kblgt2__compute_extended__untyped_reads_per_cache_line__read \
   bdw__compute_extended__untyped_reads_per_cache_line__read

/* Compute Metrics Extended set :: UntypedWritesPerCacheLine */
#define kblgt2__compute_extended__untyped_writes_per_cache_line__read \
   bdw__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics Extended set :: TypedAtomicsPerCacheLine */
#define kblgt2__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache set :: GPU Time Elapsed */
#define kblgt2__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache set :: GPU Core Clocks */
#define kblgt2__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define kblgt2__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define kblgt2__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache set :: GPU Busy */
#define kblgt2__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache set :: VS Threads Dispatched */
#define kblgt2__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: HS Threads Dispatched */
#define kblgt2__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache set :: DS Threads Dispatched */
#define kblgt2__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache set :: GS Threads Dispatched */
#define kblgt2__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: FS Threads Dispatched */
#define kblgt2__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache set :: CS Threads Dispatched */
#define kblgt2__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache set :: EU Active */
#define kblgt2__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache set :: EU Stall */
#define kblgt2__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache set :: EU Both FPU Pipes Active */
#define kblgt2__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Pipe Active */
#define kblgt2__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Pipe Active */
#define kblgt2__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define kblgt2__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define kblgt2__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache set :: EU Send Pipe Active */
#define kblgt2__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Hybrid Instruction */
#define kblgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Hybrid Instruction */
#define kblgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU0 Ternary Instruction */
#define kblgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Ternary Instruction */
#define kblgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Binary Instruction */
#define kblgt2__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Binary Instruction */
#define kblgt2__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Move Instruction */
#define kblgt2__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Move Instruction */
#define kblgt2__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: Rasterized Pixels */
#define kblgt2__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache set :: Early Hi-Depth Test Fails */
#define kblgt2__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Early Depth Test Fails */
#define kblgt2__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Samples Killed in FS */
#define kblgt2__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache set :: Pixels Failing Tests */
#define kblgt2__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache set :: Samples Written */
#define kblgt2__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache set :: Samples Blended */
#define kblgt2__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache set :: Sampler Accesses */
#define kblgt2__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache set :: Sampler Texels */
#define kblgt2__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache set :: Sampler Texels Misses */
#define kblgt2__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define kblgt2__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define kblgt2__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define kblgt2__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define kblgt2__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: Shader Memory Accesses */
#define kblgt2__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache set :: Shader Atomic Memory Accesses */
#define kblgt2__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache set :: L3 Accesses */
#define kblgt2__compute_l3_cache__l3_accesses__read \
   sklgt2__compute_l3_cache__l3_accesses__read

/* Compute Metrics L3 Cache set :: L3 Misses */
#define kblgt2__compute_l3_cache__l3_misses__read \
   bdw__compute_l3_cache__l3_misses__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define kblgt2__compute_l3_cache__l3_sampler_throughput__read \
   chv__render_basic__l3_sampler_throughput__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define kblgt2__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define kblgt2__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define kblgt2__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define kblgt2__compute_l3_cache__l3_total_throughput__read \
   sklgt2__compute_l3_cache__l3_total_throughput__read

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define kblgt2__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: Shader Barrier Messages */
#define kblgt2__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 Accesses */
#define kblgt2__compute_l3_cache__l3_bank00_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 01 Accesses */
#define kblgt2__compute_l3_cache__l3_bank01_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 02 Accesses */
#define kblgt2__compute_l3_cache__l3_bank02_accesses__read \
   bdw__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 03 Accesses */
#define kblgt2__compute_l3_cache__l3_bank03_accesses__read \
   bdw__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Accesses */
#define kblgt2__compute_l3_cache__l3_bank00_ic_accesses__read \
   bdw__compute_l3_cache__l3_bank00_ic_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Hits */
#define kblgt2__compute_l3_cache__l3_bank00_ic_hits__read \
   bdw__compute_l3_cache__l3_bank00_ic_hits__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define kblgt2__compute_l3_cache__gti_l3_throughput__read \
   bdw__compute_l3_cache__gti_l3_throughput__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define kblgt2__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define kblgt2__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define kblgt2__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define kblgt2__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define kblgt2__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define kblgt2__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define kblgt2__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define kblgt2__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define kblgt2__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define kblgt2__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define kblgt2__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define kblgt2__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define kblgt2__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define kblgt2__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define kblgt2__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define kblgt2__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define kblgt2__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define kblgt2__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define kblgt2__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define kblgt2__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define kblgt2__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define kblgt2__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define kblgt2__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define kblgt2__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define kblgt2__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define kblgt2__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define kblgt2__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define kblgt2__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define kblgt2__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define kblgt2__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define kblgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define kblgt2__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define kblgt2__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define kblgt2__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define kblgt2__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define kblgt2__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define kblgt2__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define kblgt2__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define kblgt2__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define kblgt2__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define kblgt2__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define kblgt2__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define kblgt2__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define kblgt2__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define kblgt2__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define kblgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define kblgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
#define kblgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define kblgt2__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define kblgt2__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define kblgt2__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define kblgt2__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define kblgt2__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define kblgt2__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define kblgt2__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define kblgt2__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define kblgt2__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define kblgt2__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define kblgt2__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define kblgt2__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define kblgt2__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define kblgt2__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define kblgt2__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define kblgt2__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define kblgt2__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define kblgt2__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define kblgt2__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define kblgt2__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define kblgt2__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define kblgt2__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define kblgt2__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define kblgt2__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define kblgt2__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define kblgt2__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define kblgt2__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define kblgt2__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define kblgt2__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define kblgt2__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define kblgt2__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define kblgt2__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define kblgt2__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define kblgt2__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define kblgt2__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define kblgt2__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define kblgt2__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define kblgt2__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define kblgt2__l3_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define kblgt2__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */
#define kblgt2__l3_1__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */
#define kblgt2__l3_1__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define kblgt2__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define kblgt2__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define kblgt2__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_2 :: GPU Time Elapsed */
#define kblgt2__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_2 :: GPU Core Clocks */
#define kblgt2__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define kblgt2__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define kblgt2__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_2 :: GPU Busy */
#define kblgt2__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_2 :: VS Threads Dispatched */
#define kblgt2__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_2 :: HS Threads Dispatched */
#define kblgt2__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_2 :: DS Threads Dispatched */
#define kblgt2__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_2 :: GS Threads Dispatched */
#define kblgt2__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_2 :: FS Threads Dispatched */
#define kblgt2__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_2 :: CS Threads Dispatched */
#define kblgt2__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_2 :: EU Active */
#define kblgt2__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_2 :: EU Stall */
#define kblgt2__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_2 :: EU Both FPU Pipes Active */
#define kblgt2__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_2 :: VS FPU0 Pipe Active */
#define kblgt2__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_2 :: VS FPU1 Pipe Active */
#define kblgt2__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_2 :: VS Send Pipe Active */
#define kblgt2__l3_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_2 :: PS FPU0 Pipe Active */
#define kblgt2__l3_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_2 :: PS FPU1 Pipe Active */
#define kblgt2__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_2 :: PS Send Pipeline Active */
#define kblgt2__l3_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_2 :: FS Both FPU Active */
#define kblgt2__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_2 :: Rasterized Pixels */
#define kblgt2__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_2 :: Early Hi-Depth Test Fails */
#define kblgt2__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_2 :: Early Depth Test Fails */
#define kblgt2__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Samples Killed in FS */
#define kblgt2__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_2 :: Pixels Failing Tests */
#define kblgt2__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_2 :: Samples Written */
#define kblgt2__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_2 :: Samples Blended */
#define kblgt2__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_2 :: Sampler Texels */
#define kblgt2__l3_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_2 :: Sampler Texels Misses */
#define kblgt2__l3_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_2 :: SLM Bytes Read */
#define kblgt2__l3_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_2 :: SLM Bytes Read */
#define kblgt2__l3_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: SLM Bytes Written */
#define kblgt2__l3_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_2 :: SLM Bytes Written */
#define kblgt2__l3_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Memory Accesses */
#define kblgt2__l3_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_2 :: Shader Atomic Memory Accesses */
#define kblgt2__l3_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define kblgt2__l3_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define kblgt2__l3_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Barrier Messages */
#define kblgt2__l3_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */
#define kblgt2__l3_2__l30_bank2_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Active */
#define kblgt2__l3_2__l30_bank2_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_2 :: SQ is full */
#define kblgt2__l3_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_3 :: GPU Time Elapsed */
#define kblgt2__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_3 :: GPU Core Clocks */
#define kblgt2__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define kblgt2__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define kblgt2__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_3 :: GPU Busy */
#define kblgt2__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_3 :: VS Threads Dispatched */
#define kblgt2__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_3 :: HS Threads Dispatched */
#define kblgt2__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_3 :: DS Threads Dispatched */
#define kblgt2__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_3 :: GS Threads Dispatched */
#define kblgt2__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_3 :: FS Threads Dispatched */
#define kblgt2__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_3 :: CS Threads Dispatched */
#define kblgt2__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_3 :: EU Active */
#define kblgt2__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_3 :: EU Stall */
#define kblgt2__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_3 :: EU Both FPU Pipes Active */
#define kblgt2__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_3 :: VS FPU0 Pipe Active */
#define kblgt2__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_3 :: VS FPU1 Pipe Active */
#define kblgt2__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_3 :: VS Send Pipe Active */
#define kblgt2__l3_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_3 :: PS FPU0 Pipe Active */
#define kblgt2__l3_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_3 :: PS FPU1 Pipe Active */
#define kblgt2__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_3 :: PS Send Pipeline Active */
#define kblgt2__l3_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_3 :: FS Both FPU Active */
#define kblgt2__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_3 :: Rasterized Pixels */
#define kblgt2__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_3 :: Early Hi-Depth Test Fails */
#define kblgt2__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_3 :: Early Depth Test Fails */
#define kblgt2__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Samples Killed in FS */
#define kblgt2__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_3 :: Pixels Failing Tests */
#define kblgt2__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_3 :: Samples Written */
#define kblgt2__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_3 :: Samples Blended */
#define kblgt2__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_3 :: Sampler Texels */
#define kblgt2__l3_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_3 :: Sampler Texels Misses */
#define kblgt2__l3_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_3 :: SLM Bytes Read */
#define kblgt2__l3_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_3 :: SLM Bytes Read */
#define kblgt2__l3_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: SLM Bytes Written */
#define kblgt2__l3_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_3 :: SLM Bytes Written */
#define kblgt2__l3_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Memory Accesses */
#define kblgt2__l3_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_3 :: Shader Atomic Memory Accesses */
#define kblgt2__l3_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define kblgt2__l3_3__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define kblgt2__l3_3__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Barrier Messages */
#define kblgt2__l3_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */
#define kblgt2__l3_3__l30_bank3_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Active */
#define kblgt2__l3_3__l30_bank3_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_3 :: SQ is full */
#define kblgt2__l3_3__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define kblgt2__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define kblgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define kblgt2__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define kblgt2__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define kblgt2__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define kblgt2__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define kblgt2__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define kblgt2__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define kblgt2__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define kblgt2__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define kblgt2__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define kblgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define kblgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define kblgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define kblgt2__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define kblgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define kblgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define kblgt2__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define kblgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define kblgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define kblgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define kblgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define kblgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define kblgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define kblgt2__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define kblgt2__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define kblgt2__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define kblgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define kblgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define kblgt2__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define kblgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define kblgt2__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define kblgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define kblgt2__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define kblgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define kblgt2__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define kblgt2__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define kblgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define kblgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define kblgt2__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define kblgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define kblgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define kblgt2__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler :: GPU Time Elapsed */
#define kblgt2__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler :: GPU Core Clocks */
#define kblgt2__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define kblgt2__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define kblgt2__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler :: GPU Busy */
#define kblgt2__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler :: VS Threads Dispatched */
#define kblgt2__sampler__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler :: HS Threads Dispatched */
#define kblgt2__sampler__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler :: DS Threads Dispatched */
#define kblgt2__sampler__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler :: GS Threads Dispatched */
#define kblgt2__sampler__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler :: FS Threads Dispatched */
#define kblgt2__sampler__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler :: CS Threads Dispatched */
#define kblgt2__sampler__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler :: EU Active */
#define kblgt2__sampler__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler :: EU Stall */
#define kblgt2__sampler__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler :: EU Both FPU Pipes Active */
#define kblgt2__sampler__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler :: VS FPU0 Pipe Active */
#define kblgt2__sampler__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler :: VS FPU1 Pipe Active */
#define kblgt2__sampler__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler :: VS Send Pipe Active */
#define kblgt2__sampler__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler :: PS FPU0 Pipe Active */
#define kblgt2__sampler__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler :: PS FPU1 Pipe Active */
#define kblgt2__sampler__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler :: PS Send Pipeline Active */
#define kblgt2__sampler__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler :: FS Both FPU Active */
#define kblgt2__sampler__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler :: Rasterized Pixels */
#define kblgt2__sampler__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler :: Early Hi-Depth Test Fails */
#define kblgt2__sampler__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler :: Early Depth Test Fails */
#define kblgt2__sampler__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Samples Killed in FS */
#define kblgt2__sampler__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler :: Pixels Failing Tests */
#define kblgt2__sampler__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler :: Samples Written */
#define kblgt2__sampler__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler :: Samples Blended */
#define kblgt2__sampler__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler :: Sampler Texels */
#define kblgt2__sampler__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler :: Sampler Texels Misses */
#define kblgt2__sampler__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler :: SLM Bytes Read */
#define kblgt2__sampler__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler :: SLM Bytes Read */
#define kblgt2__sampler__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: SLM Bytes Written */
#define kblgt2__sampler__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler :: SLM Bytes Written */
#define kblgt2__sampler__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Memory Accesses */
#define kblgt2__sampler__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler :: Shader Atomic Memory Accesses */
#define kblgt2__sampler__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler :: L3 Shader Throughput */
#define kblgt2__sampler__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler :: L3 Shader Throughput */
#define kblgt2__sampler__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Barrier Messages */
#define kblgt2__sampler__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Slice0 Subslice1 Input Available */
#define kblgt2__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler :: Slice0 Subslice2 Input Available */
#define kblgt2__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler :: Slice0 Subslice0 Input Available */
#define kblgt2__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */
#define kblgt2__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */
#define kblgt2__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */
#define kblgt2__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler :: SQ is full */
#define kblgt2__sampler__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define kblgt2__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define kblgt2__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define kblgt2__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define kblgt2__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define kblgt2__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define kblgt2__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define kblgt2__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define kblgt2__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define kblgt2__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define kblgt2__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define kblgt2__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define kblgt2__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define kblgt2__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define kblgt2__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define kblgt2__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define kblgt2__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define kblgt2__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define kblgt2__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define kblgt2__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define kblgt2__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define kblgt2__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define kblgt2__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define kblgt2__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define kblgt2__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define kblgt2__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define kblgt2__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define kblgt2__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define kblgt2__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define kblgt2__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define kblgt2__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define kblgt2__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define kblgt2__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define kblgt2__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define kblgt2__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define kblgt2__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define kblgt2__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define kblgt2__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define kblgt2__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define kblgt2__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define kblgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define kblgt2__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define kblgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define kblgt2__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define kblgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define kblgt2__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: SQ is full */
#define kblgt2__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define kblgt2__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define kblgt2__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define kblgt2__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define kblgt2__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define kblgt2__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define kblgt2__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define kblgt2__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define kblgt2__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define kblgt2__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define kblgt2__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define kblgt2__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define kblgt2__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define kblgt2__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define kblgt2__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define kblgt2__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define kblgt2__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define kblgt2__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define kblgt2__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define kblgt2__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define kblgt2__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define kblgt2__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define kblgt2__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define kblgt2__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define kblgt2__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define kblgt2__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define kblgt2__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define kblgt2__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define kblgt2__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define kblgt2__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define kblgt2__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define kblgt2__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define kblgt2__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define kblgt2__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define kblgt2__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define kblgt2__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define kblgt2__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define kblgt2__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define kblgt2__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define kblgt2__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define kblgt2__tdl_2__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define kblgt2__tdl_2__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define kblgt2__tdl_2__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define kblgt2__tdl_2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define kblgt2__tdl_2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define kblgt2__tdl_2__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define kblgt2__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define kblgt2__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define kblgt2__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define kblgt2__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define kblgt2__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define kblgt2__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extra set :: EU FPU1 Pipe Active including Ext Math */
#define kblgt2__compute_extra__fpu1_active_adjusted__read \
   sklgt2__compute_extra__fpu1_active_adjusted__read

/* Media Vme Pipe metrics set :: GPU Time Elapsed */
#define kblgt2__vme_pipe__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Media Vme Pipe metrics set :: GPU Core Clocks */
#define kblgt2__vme_pipe__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define kblgt2__vme_pipe__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define kblgt2__vme_pipe__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Media Vme Pipe metrics set :: GPU Busy */
#define kblgt2__vme_pipe__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Media Vme Pipe metrics set :: CS Threads Dispatched */
#define kblgt2__vme_pipe__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Media Vme Pipe metrics set :: EU Active */
#define kblgt2__vme_pipe__eu_active__read \
   bdw__render_basic__eu_active__read

/* Media Vme Pipe metrics set :: EU Stall */
#define kblgt2__vme_pipe__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Media Vme Pipe metrics set :: EU Both FPU Pipes Active */
#define kblgt2__vme_pipe__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Media Vme Pipe metrics set :: EU Thread Occupancy */
#define kblgt2__vme_pipe__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* Media Vme Pipe metrics set :: VME Busy */
#define kblgt2__vme_pipe__vme_busy__read \
   bdw__vme_pipe__vme_busy__read

/* Gpu Rings Busyness :: GPU Time Elapsed */
#define kblgt2__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness :: GPU Core Clocks */
#define kblgt2__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define kblgt2__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define kblgt2__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness :: Render Ring Busy */
#define kblgt2__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: Vdbox0 Ring Busy */
#define kblgt2__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness :: Vebox Ring Busy */
#define kblgt2__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness :: Blitter Ring Busy */
#define kblgt2__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness :: AnyRingBusy */
#define kblgt2__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* MDAPI testing set :: GPU Time Elapsed */
#define kblgt2__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define kblgt2__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define kblgt2__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define kblgt2__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define kblgt2__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define kblgt2__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define kblgt2__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define kblgt2__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define kblgt2__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define kblgt2__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define kblgt2__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define kblgt2__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define kblgt2__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define kblgt2__pma__stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define kblgt2__pma__stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define kblgt2__pma__stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define kblgt2__pma__stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: STC PMA stall */
#define kblgt2__pma__stall__stc_pma_stall__read \
   sklgt2__pma__stall__stc_pma_stall__read

/* AsyncCompute :: GPU Time Elapsed */
#define kblgt2__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define kblgt2__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define kblgt2__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define kblgt2__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define kblgt2__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define kblgt2__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define kblgt2__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define kblgt2__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define kblgt2__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define kblgt2__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define kblgt2__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: EU FPU0 Pipe Active */
#define kblgt2__async_compute__fpu0_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: VS FPU0 Pipe Active */
#define kblgt2__async_compute__vs_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: PS FPU0 Pipe Active */
#define kblgt2__async_compute__ps_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: CS FPU0 Pipe Active */
#define kblgt2__async_compute__cs_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: EU FPU1 Pipe Active */
#define kblgt2__async_compute__fpu1_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: VS FPU1 Pipe Active */
#define kblgt2__async_compute__vs_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: PS FPU1 Pipe Active */
#define kblgt2__async_compute__ps_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: CS FPU1 Pipe Active */
#define kblgt2__async_compute__cs_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: EU Thread Occupancy */
#define kblgt2__async_compute__eu_thread_occupancy__read \
   sklgt2__ff_bottlenecks__eu_thread_occupancy__read

/* AsyncCompute :: EU Active */
#define kblgt2__async_compute__eu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: EU Stall */
#define kblgt2__async_compute__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define kblgt3__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define kblgt3__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define kblgt3__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define kblgt3__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define kblgt3__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define kblgt3__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define kblgt3__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define kblgt3__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define kblgt3__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define kblgt3__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define kblgt3__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define kblgt3__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define kblgt3__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define kblgt3__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define kblgt3__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define kblgt3__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define kblgt3__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define kblgt3__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define kblgt3__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define kblgt3__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define kblgt3__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define kblgt3__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define kblgt3__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define kblgt3__render_basic__samplers_busy__read \
   bdw__render_basic__samplers_busy__read

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define kblgt3__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
#define kblgt3__render_basic__sampler1_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define kblgt3__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define kblgt3__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define kblgt3__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define kblgt3__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define kblgt3__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define kblgt3__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define kblgt3__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define kblgt3__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define kblgt3__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
#define kblgt3__render_basic__sampler_l1_misses__read \
   bdw__render_basic__sampler_l1_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define kblgt3__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define kblgt3__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define kblgt3__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define kblgt3__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define kblgt3__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define kblgt3__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
#define kblgt3__render_basic__l3_lookups__read \
   bdw__render_basic__l3_lookups__read

/* Render Metrics Basic set :: L3 Misses */
#define kblgt3__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define kblgt3__render_basic__l3_sampler_throughput__read \
   bdw__render_basic__l3_sampler_throughput__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define kblgt3__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define kblgt3__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define kblgt3__render_basic__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define kblgt3__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define kblgt3__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define kblgt3__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define kblgt3__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define kblgt3__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define kblgt3__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define kblgt3__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define kblgt3__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define kblgt3__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define kblgt3__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define kblgt3__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define kblgt3__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define kblgt3__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define kblgt3__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define kblgt3__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define kblgt3__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define kblgt3__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define kblgt3__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define kblgt3__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define kblgt3__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define kblgt3__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define kblgt3__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define kblgt3__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define kblgt3__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define kblgt3__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define kblgt3__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define kblgt3__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define kblgt3__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define kblgt3__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define kblgt3__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define kblgt3__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define kblgt3__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define kblgt3__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define kblgt3__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define kblgt3__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define kblgt3__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define kblgt3__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define kblgt3__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define kblgt3__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define kblgt3__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define kblgt3__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define kblgt3__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define kblgt3__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define kblgt3__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define kblgt3__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define kblgt3__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define kblgt3__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define kblgt3__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define kblgt3__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define kblgt3__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define kblgt3__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define kblgt3__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define kblgt3__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define kblgt3__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define kblgt3__compute_basic__typed_bytes_read__read \
   bdw__compute_basic__typed_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define kblgt3__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
#define kblgt3__compute_basic__typed_bytes_written__read \
   bdw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Typed Bytes Written */
#define kblgt3__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define kblgt3__compute_basic__untyped_bytes_read__read \
   bdw__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define kblgt3__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define kblgt3__compute_basic__untyped_bytes_written__read \
   bdw__compute_basic__untyped_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define kblgt3__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define kblgt3__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define kblgt3__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define kblgt3__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define kblgt3__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define kblgt3__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define kblgt3__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define kblgt3__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define kblgt3__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define kblgt3__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define kblgt3__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define kblgt3__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define kblgt3__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define kblgt3__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define kblgt3__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define kblgt3__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define kblgt3__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define kblgt3__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define kblgt3__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define kblgt3__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define kblgt3__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define kblgt3__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define kblgt3__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define kblgt3__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define kblgt3__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define kblgt3__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define kblgt3__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define kblgt3__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define kblgt3__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define kblgt3__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define kblgt3__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define kblgt3__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define kblgt3__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define kblgt3__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define kblgt3__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define kblgt3__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define kblgt3__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define kblgt3__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define kblgt3__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define kblgt3__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define kblgt3__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define kblgt3__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define kblgt3__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define kblgt3__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define kblgt3__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define kblgt3__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define kblgt3__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define kblgt3__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define kblgt3__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define kblgt3__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define kblgt3__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define kblgt3__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory Reads Distribution metrics set :: GPU Time Elapsed */
#define kblgt3__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metrics set :: GPU Core Clocks */
#define kblgt3__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define kblgt3__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define kblgt3__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metrics set :: GPU Busy */
#define kblgt3__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metrics set :: VS Threads Dispatched */
#define kblgt3__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: HS Threads Dispatched */
#define kblgt3__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metrics set :: DS Threads Dispatched */
#define kblgt3__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metrics set :: GS Threads Dispatched */
#define kblgt3__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: FS Threads Dispatched */
#define kblgt3__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metrics set :: CS Threads Dispatched */
#define kblgt3__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metrics set :: EU Active */
#define kblgt3__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metrics set :: EU Stall */
#define kblgt3__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metrics set :: Rasterized Pixels */
#define kblgt3__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metrics set :: Early Hi-Depth Test Fails */
#define kblgt3__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Early Depth Test Fails */
#define kblgt3__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Samples Killed in FS */
#define kblgt3__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metrics set :: Pixels Failing Tests */
#define kblgt3__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metrics set :: Samples Written */
#define kblgt3__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metrics set :: Samples Blended */
#define kblgt3__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metrics set :: Sampler Texels */
#define kblgt3__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metrics set :: Sampler Texels Misses */
#define kblgt3__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define kblgt3__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define kblgt3__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define kblgt3__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define kblgt3__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: Shader Memory Accesses */
#define kblgt3__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metrics set :: Shader Atomic Memory Accesses */
#define kblgt3__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metrics set :: Shader Barrier Messages */
#define kblgt3__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: GtiCmdStreamerMemoryReads */
#define kblgt3__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metrics set :: GtiRsMemoryReads */
#define kblgt3__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metrics set :: GtiVfMemoryReads */
#define kblgt3__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metrics set :: GtiRccMemoryReads */
#define kblgt3__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiMscMemoryReads */
#define kblgt3__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metrics set :: GtiHizMemoryReads */
#define kblgt3__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiStcMemoryReads */
#define kblgt3__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metrics set :: GtiRczMemoryReads */
#define kblgt3__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metrics set :: GtiMemoryReads */
#define kblgt3__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank0Reads */
#define kblgt3__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank1Reads */
#define kblgt3__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metrics set :: GtiL3Bank2Reads */
#define kblgt3__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metrics set :: GtiL3Bank3Reads */
#define kblgt3__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: GtiL3Reads */
#define kblgt3__memory_reads__gti_l3_reads__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Reads Distribution metrics set :: GtiRingAccesses */
#define kblgt3__memory_reads__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Memory Writes Distribution metrics set :: GPU Time Elapsed */
#define kblgt3__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metrics set :: GPU Core Clocks */
#define kblgt3__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define kblgt3__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define kblgt3__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metrics set :: GPU Busy */
#define kblgt3__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metrics set :: VS Threads Dispatched */
#define kblgt3__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: HS Threads Dispatched */
#define kblgt3__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metrics set :: DS Threads Dispatched */
#define kblgt3__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metrics set :: GS Threads Dispatched */
#define kblgt3__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: FS Threads Dispatched */
#define kblgt3__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metrics set :: CS Threads Dispatched */
#define kblgt3__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metrics set :: EU Active */
#define kblgt3__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metrics set :: EU Stall */
#define kblgt3__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metrics set :: Rasterized Pixels */
#define kblgt3__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metrics set :: Early Hi-Depth Test Fails */
#define kblgt3__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Early Depth Test Fails */
#define kblgt3__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Samples Killed in FS */
#define kblgt3__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metrics set :: Pixels Failing Tests */
#define kblgt3__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metrics set :: Samples Written */
#define kblgt3__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metrics set :: Samples Blended */
#define kblgt3__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metrics set :: Sampler Texels */
#define kblgt3__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metrics set :: Sampler Texels Misses */
#define kblgt3__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define kblgt3__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define kblgt3__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define kblgt3__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define kblgt3__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Memory Accesses */
#define kblgt3__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metrics set :: Shader Atomic Memory Accesses */
#define kblgt3__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define kblgt3__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define kblgt3__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Memory Writes Distribution metrics set :: Shader Barrier Messages */
#define kblgt3__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: GtiCmdStreamerMemoryWrites */
#define kblgt3__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metrics set :: GtiSoMemoryWrites */
#define kblgt3__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metrics set :: GtiRccMemoryWrites */
#define kblgt3__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiMscMemoryWrites */
#define kblgt3__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metrics set :: GtiHizMemoryWrites */
#define kblgt3__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiStcMemoryWrites */
#define kblgt3__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metrics set :: GtiRczMemoryWrites */
#define kblgt3__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metrics set :: GtiMemoryWrites */
#define kblgt3__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank0Writes */
#define kblgt3__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank1Writes */
#define kblgt3__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metrics set :: GtiL3Bank2Writes */
#define kblgt3__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metrics set :: GtiL3Bank3Writes */
#define kblgt3__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: GtiL3Writes */
#define kblgt3__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metrics set :: GtiRingAccesses */
#define kblgt3__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended set :: GPU Time Elapsed */
#define kblgt3__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended set :: GPU Core Clocks */
#define kblgt3__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define kblgt3__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define kblgt3__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended set :: CS Threads Dispatched */
#define kblgt3__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended set :: EU Active */
#define kblgt3__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended set :: EU Stall */
#define kblgt3__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended set :: EU Both FPU Pipes Active */
#define kblgt3__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended set :: EU FPU0 Pipe Active */
#define kblgt3__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended set :: EU FPU1 Pipe Active */
#define kblgt3__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define kblgt3__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define kblgt3__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended set :: EU Send Pipe Active */
#define kblgt3__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended set :: EU Thread Occupancy */
#define kblgt3__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended set :: Sampler Texels */
#define kblgt3__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended set :: Sampler Texels Misses */
#define kblgt3__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define kblgt3__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define kblgt3__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: SLM Bytes Written */
#define kblgt3__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended set :: SLM Bytes Written */
#define kblgt3__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Memory Accesses */
#define kblgt3__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended set :: Shader Atomic Memory Accesses */
#define kblgt3__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define kblgt3__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define kblgt3__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Extended set :: Shader Barrier Messages */
#define kblgt3__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended set :: EuUntypedReads0 */
#define kblgt3__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended set :: EuTypedReads0 */
#define kblgt3__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended set :: EuUntypedWrites0 */
#define kblgt3__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended set :: EuTypedWrites0 */
#define kblgt3__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended set :: EuUntypedAtomics0 */
#define kblgt3__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended set :: EuTypedAtomics0 */
#define kblgt3__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedReads0 */
#define kblgt3__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedWrites0 */
#define kblgt3__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended set :: Typed Reads 0 */
#define kblgt3__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: Typed Writes 0 */
#define kblgt3__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended set :: Untyped Reads 0 */
#define kblgt3__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended set :: Untyped Writes 0 */
#define kblgt3__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended set :: Typed Atomics 0 */
#define kblgt3__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended set :: TypedReadsPerCacheLine */
#define kblgt3__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended set :: TypedWritesPerCacheLine */
#define kblgt3__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended set :: UntypedReadsPerCacheLine */
#define kblgt3__compute_extended__untyped_reads_per_cache_line__read \
   bdw__compute_extended__untyped_reads_per_cache_line__read

/* Compute Metrics Extended set :: UntypedWritesPerCacheLine */
#define kblgt3__compute_extended__untyped_writes_per_cache_line__read \
   bdw__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics Extended set :: TypedAtomicsPerCacheLine */
#define kblgt3__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache set :: GPU Time Elapsed */
#define kblgt3__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache set :: GPU Core Clocks */
#define kblgt3__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define kblgt3__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define kblgt3__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache set :: GPU Busy */
#define kblgt3__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache set :: VS Threads Dispatched */
#define kblgt3__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: HS Threads Dispatched */
#define kblgt3__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache set :: DS Threads Dispatched */
#define kblgt3__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache set :: GS Threads Dispatched */
#define kblgt3__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: FS Threads Dispatched */
#define kblgt3__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache set :: CS Threads Dispatched */
#define kblgt3__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache set :: EU Active */
#define kblgt3__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache set :: EU Stall */
#define kblgt3__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache set :: EU Both FPU Pipes Active */
#define kblgt3__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Pipe Active */
#define kblgt3__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Pipe Active */
#define kblgt3__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define kblgt3__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define kblgt3__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache set :: EU Send Pipe Active */
#define kblgt3__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Hybrid Instruction */
#define kblgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Hybrid Instruction */
#define kblgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU0 Ternary Instruction */
#define kblgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Ternary Instruction */
#define kblgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Binary Instruction */
#define kblgt3__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Binary Instruction */
#define kblgt3__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Move Instruction */
#define kblgt3__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Move Instruction */
#define kblgt3__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: Rasterized Pixels */
#define kblgt3__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache set :: Early Hi-Depth Test Fails */
#define kblgt3__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Early Depth Test Fails */
#define kblgt3__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Samples Killed in FS */
#define kblgt3__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache set :: Pixels Failing Tests */
#define kblgt3__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache set :: Samples Written */
#define kblgt3__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache set :: Samples Blended */
#define kblgt3__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache set :: Sampler Accesses */
#define kblgt3__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache set :: Sampler Texels */
#define kblgt3__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache set :: Sampler Texels Misses */
#define kblgt3__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define kblgt3__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define kblgt3__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define kblgt3__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define kblgt3__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: Shader Memory Accesses */
#define kblgt3__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache set :: Shader Atomic Memory Accesses */
#define kblgt3__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache set :: L3 Accesses */
#define kblgt3__compute_l3_cache__l3_accesses__read \
   sklgt2__compute_l3_cache__l3_accesses__read

/* Compute Metrics L3 Cache set :: L3 Misses */
#define kblgt3__compute_l3_cache__l3_misses__read \
   bdw__compute_l3_cache__l3_misses__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define kblgt3__compute_l3_cache__l3_sampler_throughput__read \
   chv__render_basic__l3_sampler_throughput__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define kblgt3__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define kblgt3__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define kblgt3__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define kblgt3__compute_l3_cache__l3_total_throughput__read \
   sklgt2__compute_l3_cache__l3_total_throughput__read

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define kblgt3__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: Shader Barrier Messages */
#define kblgt3__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 Accesses */
#define kblgt3__compute_l3_cache__l3_bank00_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 01 Accesses */
#define kblgt3__compute_l3_cache__l3_bank01_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 02 Accesses */
#define kblgt3__compute_l3_cache__l3_bank02_accesses__read \
   bdw__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 03 Accesses */
#define kblgt3__compute_l3_cache__l3_bank03_accesses__read \
   bdw__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Accesses */
#define kblgt3__compute_l3_cache__l3_bank00_ic_accesses__read \
   bdw__compute_l3_cache__l3_bank00_ic_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Hits */
#define kblgt3__compute_l3_cache__l3_bank00_ic_hits__read \
   bdw__compute_l3_cache__l3_bank00_ic_hits__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define kblgt3__compute_l3_cache__gti_l3_throughput__read \
   bdw__compute_l3_cache__gti_l3_throughput__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define kblgt3__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define kblgt3__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define kblgt3__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define kblgt3__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define kblgt3__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define kblgt3__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define kblgt3__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define kblgt3__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define kblgt3__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define kblgt3__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define kblgt3__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define kblgt3__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define kblgt3__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define kblgt3__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define kblgt3__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define kblgt3__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define kblgt3__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define kblgt3__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define kblgt3__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define kblgt3__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define kblgt3__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define kblgt3__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define kblgt3__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define kblgt3__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define kblgt3__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define kblgt3__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define kblgt3__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define kblgt3__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define kblgt3__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define kblgt3__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define kblgt3__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define kblgt3__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define kblgt3__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define kblgt3__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define kblgt3__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define kblgt3__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define kblgt3__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define kblgt3__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define kblgt3__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define kblgt3__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define kblgt3__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define kblgt3__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define kblgt3__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define kblgt3__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define kblgt3__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define kblgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define kblgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
#define kblgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define kblgt3__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define kblgt3__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define kblgt3__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define kblgt3__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define kblgt3__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define kblgt3__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define kblgt3__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define kblgt3__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define kblgt3__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define kblgt3__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define kblgt3__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define kblgt3__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define kblgt3__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define kblgt3__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define kblgt3__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define kblgt3__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define kblgt3__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define kblgt3__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define kblgt3__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define kblgt3__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define kblgt3__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define kblgt3__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define kblgt3__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define kblgt3__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define kblgt3__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define kblgt3__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define kblgt3__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define kblgt3__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define kblgt3__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define kblgt3__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define kblgt3__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define kblgt3__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define kblgt3__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define kblgt3__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define kblgt3__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define kblgt3__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define kblgt3__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define kblgt3__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define kblgt3__l3_1__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define kblgt3__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */
#define kblgt3__l3_1__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */
#define kblgt3__l3_1__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define kblgt3__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define kblgt3__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define kblgt3__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_2 :: GPU Time Elapsed */
#define kblgt3__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_2 :: GPU Core Clocks */
#define kblgt3__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define kblgt3__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define kblgt3__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_2 :: GPU Busy */
#define kblgt3__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_2 :: VS Threads Dispatched */
#define kblgt3__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_2 :: HS Threads Dispatched */
#define kblgt3__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_2 :: DS Threads Dispatched */
#define kblgt3__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_2 :: GS Threads Dispatched */
#define kblgt3__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_2 :: FS Threads Dispatched */
#define kblgt3__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_2 :: CS Threads Dispatched */
#define kblgt3__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_2 :: EU Active */
#define kblgt3__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_2 :: EU Stall */
#define kblgt3__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_2 :: EU Both FPU Pipes Active */
#define kblgt3__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_2 :: VS FPU0 Pipe Active */
#define kblgt3__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_2 :: VS FPU1 Pipe Active */
#define kblgt3__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_2 :: VS Send Pipe Active */
#define kblgt3__l3_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_2 :: PS FPU0 Pipe Active */
#define kblgt3__l3_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_2 :: PS FPU1 Pipe Active */
#define kblgt3__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_2 :: PS Send Pipeline Active */
#define kblgt3__l3_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_2 :: FS Both FPU Active */
#define kblgt3__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_2 :: Rasterized Pixels */
#define kblgt3__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_2 :: Early Hi-Depth Test Fails */
#define kblgt3__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_2 :: Early Depth Test Fails */
#define kblgt3__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Samples Killed in FS */
#define kblgt3__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_2 :: Pixels Failing Tests */
#define kblgt3__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_2 :: Samples Written */
#define kblgt3__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_2 :: Samples Blended */
#define kblgt3__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_2 :: Sampler Texels */
#define kblgt3__l3_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_2 :: Sampler Texels Misses */
#define kblgt3__l3_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_2 :: SLM Bytes Read */
#define kblgt3__l3_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_2 :: SLM Bytes Read */
#define kblgt3__l3_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: SLM Bytes Written */
#define kblgt3__l3_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_2 :: SLM Bytes Written */
#define kblgt3__l3_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Memory Accesses */
#define kblgt3__l3_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_2 :: Shader Atomic Memory Accesses */
#define kblgt3__l3_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define kblgt3__l3_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define kblgt3__l3_2__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set L3_2 :: Shader Barrier Messages */
#define kblgt3__l3_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */
#define kblgt3__l3_2__l30_bank2_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Active */
#define kblgt3__l3_2__l30_bank2_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_2 :: SQ is full */
#define kblgt3__l3_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_3 :: GPU Time Elapsed */
#define kblgt3__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_3 :: GPU Core Clocks */
#define kblgt3__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define kblgt3__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define kblgt3__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_3 :: GPU Busy */
#define kblgt3__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_3 :: VS Threads Dispatched */
#define kblgt3__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_3 :: HS Threads Dispatched */
#define kblgt3__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_3 :: DS Threads Dispatched */
#define kblgt3__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_3 :: GS Threads Dispatched */
#define kblgt3__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_3 :: FS Threads Dispatched */
#define kblgt3__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_3 :: CS Threads Dispatched */
#define kblgt3__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_3 :: EU Active */
#define kblgt3__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_3 :: EU Stall */
#define kblgt3__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_3 :: EU Both FPU Pipes Active */
#define kblgt3__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_3 :: VS FPU0 Pipe Active */
#define kblgt3__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_3 :: VS FPU1 Pipe Active */
#define kblgt3__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_3 :: VS Send Pipe Active */
#define kblgt3__l3_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_3 :: PS FPU0 Pipe Active */
#define kblgt3__l3_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_3 :: PS FPU1 Pipe Active */
#define kblgt3__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_3 :: PS Send Pipeline Active */
#define kblgt3__l3_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_3 :: FS Both FPU Active */
#define kblgt3__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_3 :: Rasterized Pixels */
#define kblgt3__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_3 :: Early Hi-Depth Test Fails */
#define kblgt3__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_3 :: Early Depth Test Fails */
#define kblgt3__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Samples Killed in FS */
#define kblgt3__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_3 :: Pixels Failing Tests */
#define kblgt3__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_3 :: Samples Written */
#define kblgt3__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_3 :: Samples Blended */
#define kblgt3__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_3 :: Sampler Texels */
#define kblgt3__l3_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_3 :: Sampler Texels Misses */
#define kblgt3__l3_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_3 :: SLM Bytes Read */
#define kblgt3__l3_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_3 :: SLM Bytes Read */
#define kblgt3__l3_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: SLM Bytes Written */
#define kblgt3__l3_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_3 :: SLM Bytes Written */
#define kblgt3__l3_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Memory Accesses */
#define kblgt3__l3_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_3 :: Shader Atomic Memory Accesses */
#define kblgt3__l3_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define kblgt3__l3_3__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define kblgt3__l3_3__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set L3_3 :: Shader Barrier Messages */
#define kblgt3__l3_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */
#define kblgt3__l3_3__l30_bank3_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Active */
#define kblgt3__l3_3__l30_bank3_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_3 :: SQ is full */
#define kblgt3__l3_3__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define kblgt3__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define kblgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define kblgt3__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define kblgt3__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define kblgt3__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define kblgt3__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define kblgt3__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define kblgt3__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define kblgt3__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define kblgt3__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define kblgt3__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define kblgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define kblgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define kblgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define kblgt3__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define kblgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define kblgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define kblgt3__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define kblgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define kblgt3__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define kblgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define kblgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define kblgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define kblgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define kblgt3__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define kblgt3__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define kblgt3__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define kblgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define kblgt3__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define kblgt3__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define kblgt3__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define kblgt3__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define kblgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define kblgt3__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define kblgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define kblgt3__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define kblgt3__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define kblgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define kblgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define kblgt3__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define kblgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define kblgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define kblgt3__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler :: GPU Time Elapsed */
#define kblgt3__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler :: GPU Core Clocks */
#define kblgt3__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define kblgt3__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define kblgt3__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler :: GPU Busy */
#define kblgt3__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler :: VS Threads Dispatched */
#define kblgt3__sampler__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler :: HS Threads Dispatched */
#define kblgt3__sampler__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler :: DS Threads Dispatched */
#define kblgt3__sampler__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler :: GS Threads Dispatched */
#define kblgt3__sampler__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler :: FS Threads Dispatched */
#define kblgt3__sampler__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler :: CS Threads Dispatched */
#define kblgt3__sampler__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler :: EU Active */
#define kblgt3__sampler__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler :: EU Stall */
#define kblgt3__sampler__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler :: EU Both FPU Pipes Active */
#define kblgt3__sampler__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler :: VS FPU0 Pipe Active */
#define kblgt3__sampler__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler :: VS FPU1 Pipe Active */
#define kblgt3__sampler__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler :: VS Send Pipe Active */
#define kblgt3__sampler__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler :: PS FPU0 Pipe Active */
#define kblgt3__sampler__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler :: PS FPU1 Pipe Active */
#define kblgt3__sampler__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler :: PS Send Pipeline Active */
#define kblgt3__sampler__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler :: FS Both FPU Active */
#define kblgt3__sampler__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler :: Rasterized Pixels */
#define kblgt3__sampler__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler :: Early Hi-Depth Test Fails */
#define kblgt3__sampler__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler :: Early Depth Test Fails */
#define kblgt3__sampler__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Samples Killed in FS */
#define kblgt3__sampler__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler :: Pixels Failing Tests */
#define kblgt3__sampler__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler :: Samples Written */
#define kblgt3__sampler__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler :: Samples Blended */
#define kblgt3__sampler__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler :: Sampler Texels */
#define kblgt3__sampler__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler :: Sampler Texels Misses */
#define kblgt3__sampler__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler :: SLM Bytes Read */
#define kblgt3__sampler__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler :: SLM Bytes Read */
#define kblgt3__sampler__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: SLM Bytes Written */
#define kblgt3__sampler__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler :: SLM Bytes Written */
#define kblgt3__sampler__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Memory Accesses */
#define kblgt3__sampler__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler :: Shader Atomic Memory Accesses */
#define kblgt3__sampler__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler :: L3 Shader Throughput */
#define kblgt3__sampler__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler :: L3 Shader Throughput */
#define kblgt3__sampler__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set Sampler :: Shader Barrier Messages */
#define kblgt3__sampler__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Slice0 Subslice1 Input Available */
#define kblgt3__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler :: Slice0 Subslice2 Input Available */
#define kblgt3__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler :: Slice0 Subslice0 Input Available */
#define kblgt3__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */
#define kblgt3__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */
#define kblgt3__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */
#define kblgt3__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler :: SQ is full */
#define kblgt3__sampler__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define kblgt3__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define kblgt3__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define kblgt3__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define kblgt3__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define kblgt3__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define kblgt3__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define kblgt3__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define kblgt3__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define kblgt3__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define kblgt3__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define kblgt3__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define kblgt3__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define kblgt3__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define kblgt3__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define kblgt3__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define kblgt3__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define kblgt3__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define kblgt3__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define kblgt3__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define kblgt3__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define kblgt3__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define kblgt3__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define kblgt3__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define kblgt3__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define kblgt3__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define kblgt3__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define kblgt3__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define kblgt3__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define kblgt3__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define kblgt3__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define kblgt3__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define kblgt3__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define kblgt3__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define kblgt3__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define kblgt3__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define kblgt3__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define kblgt3__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define kblgt3__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define kblgt3__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define kblgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define kblgt3__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define kblgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define kblgt3__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define kblgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define kblgt3__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: SQ is full */
#define kblgt3__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define kblgt3__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define kblgt3__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define kblgt3__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define kblgt3__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define kblgt3__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define kblgt3__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define kblgt3__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define kblgt3__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define kblgt3__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define kblgt3__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define kblgt3__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define kblgt3__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define kblgt3__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define kblgt3__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define kblgt3__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define kblgt3__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define kblgt3__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define kblgt3__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define kblgt3__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define kblgt3__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define kblgt3__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define kblgt3__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define kblgt3__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define kblgt3__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define kblgt3__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define kblgt3__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define kblgt3__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define kblgt3__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define kblgt3__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define kblgt3__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define kblgt3__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define kblgt3__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define kblgt3__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define kblgt3__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define kblgt3__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define kblgt3__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define kblgt3__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define kblgt3__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define kblgt3__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define kblgt3__tdl_2__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define kblgt3__tdl_2__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define kblgt3__tdl_2__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define kblgt3__tdl_2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define kblgt3__tdl_2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define kblgt3__tdl_2__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define kblgt3__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define kblgt3__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define kblgt3__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define kblgt3__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define kblgt3__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define kblgt3__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extra set :: EU FPU1 Pipe Active including Ext Math */
#define kblgt3__compute_extra__fpu1_active_adjusted__read \
   bdw__compute_extra__fpu1_active_adjusted__read

/* Media Vme Pipe metrics set :: GPU Time Elapsed */
#define kblgt3__vme_pipe__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Media Vme Pipe metrics set :: GPU Core Clocks */
#define kblgt3__vme_pipe__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define kblgt3__vme_pipe__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define kblgt3__vme_pipe__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Media Vme Pipe metrics set :: GPU Busy */
#define kblgt3__vme_pipe__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Media Vme Pipe metrics set :: CS Threads Dispatched */
#define kblgt3__vme_pipe__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Media Vme Pipe metrics set :: EU Active */
#define kblgt3__vme_pipe__eu_active__read \
   bdw__render_basic__eu_active__read

/* Media Vme Pipe metrics set :: EU Stall */
#define kblgt3__vme_pipe__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Media Vme Pipe metrics set :: EU Both FPU Pipes Active */
#define kblgt3__vme_pipe__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Media Vme Pipe metrics set :: EU Thread Occupancy */
#define kblgt3__vme_pipe__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* Media Vme Pipe metrics set :: VME Busy */
#define kblgt3__vme_pipe__vme_busy__read \
   bdw__vme_pipe__vme_busy__read

/* Gpu Rings Busyness :: GPU Time Elapsed */
#define kblgt3__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness :: GPU Core Clocks */
#define kblgt3__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define kblgt3__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define kblgt3__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness :: Render Ring Busy */
#define kblgt3__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: Vdbox0 Ring Busy */
#define kblgt3__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness :: Vdbox1 Ring Busy */
#define kblgt3__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness :: Vebox Ring Busy */
#define kblgt3__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness :: Blitter Ring Busy */
#define kblgt3__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* Gpu Rings Busyness :: AnyRingBusy */
#define kblgt3__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* MDAPI testing set :: GPU Time Elapsed */
#define kblgt3__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define kblgt3__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define kblgt3__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define kblgt3__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define kblgt3__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define kblgt3__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define kblgt3__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define kblgt3__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define kblgt3__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define kblgt3__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define kblgt3__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define kblgt3__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define kblgt3__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define kblgt3__pma__stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define kblgt3__pma__stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define kblgt3__pma__stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define kblgt3__pma__stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: STC PMA stall */
#define kblgt3__pma__stall__stc_pma_stall__read \
   sklgt2__pma__stall__stc_pma_stall__read

/* AsyncCompute :: GPU Time Elapsed */
#define kblgt3__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define kblgt3__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define kblgt3__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define kblgt3__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define kblgt3__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define kblgt3__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define kblgt3__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define kblgt3__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define kblgt3__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define kblgt3__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define kblgt3__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: EU FPU0 Pipe Active */
#define kblgt3__async_compute__fpu0_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: VS FPU0 Pipe Active */
#define kblgt3__async_compute__vs_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: PS FPU0 Pipe Active */
#define kblgt3__async_compute__ps_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: CS FPU0 Pipe Active */
#define kblgt3__async_compute__cs_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: EU FPU1 Pipe Active */
#define kblgt3__async_compute__fpu1_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: VS FPU1 Pipe Active */
#define kblgt3__async_compute__vs_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: PS FPU1 Pipe Active */
#define kblgt3__async_compute__ps_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: CS FPU1 Pipe Active */
#define kblgt3__async_compute__cs_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: EU Thread Occupancy */
#define kblgt3__async_compute__eu_thread_occupancy__read \
   sklgt2__ff_bottlenecks__eu_thread_occupancy__read

/* AsyncCompute :: EU Active */
#define kblgt3__async_compute__eu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: EU Stall */
#define kblgt3__async_compute__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define cflgt2__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define cflgt2__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define cflgt2__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define cflgt2__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define cflgt2__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define cflgt2__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define cflgt2__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define cflgt2__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define cflgt2__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define cflgt2__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define cflgt2__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define cflgt2__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define cflgt2__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define cflgt2__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define cflgt2__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define cflgt2__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define cflgt2__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define cflgt2__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define cflgt2__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define cflgt2__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define cflgt2__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define cflgt2__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define cflgt2__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define cflgt2__render_basic__samplers_busy__read \
   bdw__render_basic__samplers_busy__read

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define cflgt2__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
#define cflgt2__render_basic__sampler1_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define cflgt2__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define cflgt2__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define cflgt2__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define cflgt2__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define cflgt2__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define cflgt2__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define cflgt2__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define cflgt2__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define cflgt2__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
#define cflgt2__render_basic__sampler_l1_misses__read \
   sklgt2__render_basic__sampler_l1_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define cflgt2__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define cflgt2__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define cflgt2__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define cflgt2__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define cflgt2__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define cflgt2__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
#define cflgt2__render_basic__l3_lookups__read \
   sklgt2__render_basic__l3_lookups__read

/* Render Metrics Basic set :: L3 Misses */
#define cflgt2__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define cflgt2__render_basic__l3_sampler_throughput__read \
   sklgt2__render_basic__l3_sampler_throughput__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define cflgt2__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define cflgt2__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define cflgt2__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define cflgt2__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define cflgt2__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define cflgt2__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define cflgt2__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define cflgt2__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define cflgt2__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define cflgt2__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define cflgt2__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define cflgt2__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define cflgt2__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define cflgt2__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define cflgt2__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define cflgt2__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define cflgt2__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define cflgt2__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define cflgt2__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define cflgt2__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define cflgt2__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define cflgt2__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define cflgt2__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define cflgt2__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define cflgt2__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define cflgt2__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define cflgt2__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define cflgt2__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define cflgt2__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define cflgt2__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define cflgt2__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define cflgt2__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define cflgt2__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define cflgt2__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define cflgt2__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define cflgt2__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define cflgt2__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define cflgt2__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define cflgt2__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define cflgt2__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define cflgt2__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define cflgt2__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define cflgt2__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define cflgt2__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define cflgt2__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define cflgt2__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define cflgt2__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define cflgt2__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define cflgt2__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define cflgt2__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define cflgt2__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define cflgt2__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define cflgt2__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define cflgt2__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define cflgt2__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define cflgt2__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define cflgt2__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define cflgt2__compute_basic__typed_bytes_read__read \
   bdw__compute_basic__typed_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define cflgt2__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
#define cflgt2__compute_basic__typed_bytes_written__read \
   bdw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Typed Bytes Written */
#define cflgt2__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define cflgt2__compute_basic__untyped_bytes_read__read \
   bdw__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define cflgt2__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define cflgt2__compute_basic__untyped_bytes_written__read \
   bdw__compute_basic__untyped_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define cflgt2__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define cflgt2__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define cflgt2__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define cflgt2__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define cflgt2__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define cflgt2__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define cflgt2__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define cflgt2__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define cflgt2__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define cflgt2__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define cflgt2__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define cflgt2__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define cflgt2__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define cflgt2__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define cflgt2__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define cflgt2__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define cflgt2__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define cflgt2__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define cflgt2__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define cflgt2__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define cflgt2__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define cflgt2__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define cflgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define cflgt2__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define cflgt2__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define cflgt2__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define cflgt2__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define cflgt2__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define cflgt2__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define cflgt2__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define cflgt2__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define cflgt2__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define cflgt2__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define cflgt2__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define cflgt2__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define cflgt2__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define cflgt2__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define cflgt2__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define cflgt2__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define cflgt2__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define cflgt2__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define cflgt2__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define cflgt2__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define cflgt2__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define cflgt2__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define cflgt2__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define cflgt2__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define cflgt2__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define cflgt2__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define cflgt2__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define cflgt2__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define cflgt2__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory Reads Distribution metrics set :: GPU Time Elapsed */
#define cflgt2__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metrics set :: GPU Core Clocks */
#define cflgt2__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define cflgt2__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define cflgt2__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metrics set :: GPU Busy */
#define cflgt2__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metrics set :: VS Threads Dispatched */
#define cflgt2__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: HS Threads Dispatched */
#define cflgt2__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metrics set :: DS Threads Dispatched */
#define cflgt2__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metrics set :: GS Threads Dispatched */
#define cflgt2__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: FS Threads Dispatched */
#define cflgt2__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metrics set :: CS Threads Dispatched */
#define cflgt2__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metrics set :: EU Active */
#define cflgt2__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metrics set :: EU Stall */
#define cflgt2__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metrics set :: Rasterized Pixels */
#define cflgt2__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metrics set :: Early Hi-Depth Test Fails */
#define cflgt2__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Early Depth Test Fails */
#define cflgt2__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Samples Killed in FS */
#define cflgt2__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metrics set :: Pixels Failing Tests */
#define cflgt2__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metrics set :: Samples Written */
#define cflgt2__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metrics set :: Samples Blended */
#define cflgt2__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metrics set :: Sampler Texels */
#define cflgt2__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metrics set :: Sampler Texels Misses */
#define cflgt2__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define cflgt2__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define cflgt2__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define cflgt2__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define cflgt2__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: Shader Memory Accesses */
#define cflgt2__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metrics set :: Shader Atomic Memory Accesses */
#define cflgt2__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metrics set :: Shader Barrier Messages */
#define cflgt2__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: GtiCmdStreamerMemoryReads */
#define cflgt2__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metrics set :: GtiRsMemoryReads */
#define cflgt2__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metrics set :: GtiVfMemoryReads */
#define cflgt2__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metrics set :: GtiRccMemoryReads */
#define cflgt2__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiMscMemoryReads */
#define cflgt2__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metrics set :: GtiHizMemoryReads */
#define cflgt2__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiStcMemoryReads */
#define cflgt2__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metrics set :: GtiRczMemoryReads */
#define cflgt2__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metrics set :: GtiMemoryReads */
#define cflgt2__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank0Reads */
#define cflgt2__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank1Reads */
#define cflgt2__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metrics set :: GtiL3Bank2Reads */
#define cflgt2__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metrics set :: GtiL3Bank3Reads */
#define cflgt2__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: GtiL3Reads */
#define cflgt2__memory_reads__gti_l3_reads__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Reads Distribution metrics set :: GtiRingAccesses */
#define cflgt2__memory_reads__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Memory Writes Distribution metrics set :: GPU Time Elapsed */
#define cflgt2__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metrics set :: GPU Core Clocks */
#define cflgt2__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define cflgt2__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define cflgt2__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metrics set :: GPU Busy */
#define cflgt2__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metrics set :: VS Threads Dispatched */
#define cflgt2__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: HS Threads Dispatched */
#define cflgt2__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metrics set :: DS Threads Dispatched */
#define cflgt2__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metrics set :: GS Threads Dispatched */
#define cflgt2__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: FS Threads Dispatched */
#define cflgt2__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metrics set :: CS Threads Dispatched */
#define cflgt2__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metrics set :: EU Active */
#define cflgt2__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metrics set :: EU Stall */
#define cflgt2__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metrics set :: Rasterized Pixels */
#define cflgt2__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metrics set :: Early Hi-Depth Test Fails */
#define cflgt2__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Early Depth Test Fails */
#define cflgt2__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Samples Killed in FS */
#define cflgt2__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metrics set :: Pixels Failing Tests */
#define cflgt2__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metrics set :: Samples Written */
#define cflgt2__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metrics set :: Samples Blended */
#define cflgt2__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metrics set :: Sampler Texels */
#define cflgt2__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metrics set :: Sampler Texels Misses */
#define cflgt2__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define cflgt2__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define cflgt2__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define cflgt2__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define cflgt2__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Memory Accesses */
#define cflgt2__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metrics set :: Shader Atomic Memory Accesses */
#define cflgt2__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define cflgt2__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define cflgt2__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Barrier Messages */
#define cflgt2__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: GtiCmdStreamerMemoryWrites */
#define cflgt2__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metrics set :: GtiSoMemoryWrites */
#define cflgt2__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metrics set :: GtiRccMemoryWrites */
#define cflgt2__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiMscMemoryWrites */
#define cflgt2__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metrics set :: GtiHizMemoryWrites */
#define cflgt2__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiStcMemoryWrites */
#define cflgt2__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metrics set :: GtiRczMemoryWrites */
#define cflgt2__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metrics set :: GtiMemoryWrites */
#define cflgt2__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank0Writes */
#define cflgt2__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank1Writes */
#define cflgt2__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metrics set :: GtiL3Bank2Writes */
#define cflgt2__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metrics set :: GtiL3Bank3Writes */
#define cflgt2__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: GtiL3Writes */
#define cflgt2__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metrics set :: GtiRingAccesses */
#define cflgt2__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended set :: GPU Time Elapsed */
#define cflgt2__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended set :: GPU Core Clocks */
#define cflgt2__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define cflgt2__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define cflgt2__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended set :: CS Threads Dispatched */
#define cflgt2__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended set :: EU Active */
#define cflgt2__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended set :: EU Stall */
#define cflgt2__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended set :: EU Both FPU Pipes Active */
#define cflgt2__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended set :: EU FPU0 Pipe Active */
#define cflgt2__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended set :: EU FPU1 Pipe Active */
#define cflgt2__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define cflgt2__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define cflgt2__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended set :: EU Send Pipe Active */
#define cflgt2__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended set :: EU Thread Occupancy */
#define cflgt2__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended set :: Sampler Texels */
#define cflgt2__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended set :: Sampler Texels Misses */
#define cflgt2__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define cflgt2__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define cflgt2__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: SLM Bytes Written */
#define cflgt2__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended set :: SLM Bytes Written */
#define cflgt2__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Memory Accesses */
#define cflgt2__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended set :: Shader Atomic Memory Accesses */
#define cflgt2__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define cflgt2__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define cflgt2__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Barrier Messages */
#define cflgt2__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended set :: EuUntypedReads0 */
#define cflgt2__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended set :: EuTypedReads0 */
#define cflgt2__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended set :: EuUntypedWrites0 */
#define cflgt2__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended set :: EuTypedWrites0 */
#define cflgt2__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended set :: EuUntypedAtomics0 */
#define cflgt2__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended set :: EuTypedAtomics0 */
#define cflgt2__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedReads0 */
#define cflgt2__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedWrites0 */
#define cflgt2__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended set :: Typed Reads 0 */
#define cflgt2__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: Typed Writes 0 */
#define cflgt2__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended set :: Untyped Reads 0 */
#define cflgt2__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended set :: Untyped Writes 0 */
#define cflgt2__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended set :: Typed Atomics 0 */
#define cflgt2__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended set :: TypedReadsPerCacheLine */
#define cflgt2__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended set :: TypedWritesPerCacheLine */
#define cflgt2__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended set :: UntypedReadsPerCacheLine */
#define cflgt2__compute_extended__untyped_reads_per_cache_line__read \
   bdw__compute_extended__untyped_reads_per_cache_line__read

/* Compute Metrics Extended set :: UntypedWritesPerCacheLine */
#define cflgt2__compute_extended__untyped_writes_per_cache_line__read \
   bdw__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics Extended set :: TypedAtomicsPerCacheLine */
#define cflgt2__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache set :: GPU Time Elapsed */
#define cflgt2__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache set :: GPU Core Clocks */
#define cflgt2__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define cflgt2__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define cflgt2__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache set :: GPU Busy */
#define cflgt2__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache set :: VS Threads Dispatched */
#define cflgt2__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: HS Threads Dispatched */
#define cflgt2__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache set :: DS Threads Dispatched */
#define cflgt2__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache set :: GS Threads Dispatched */
#define cflgt2__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: FS Threads Dispatched */
#define cflgt2__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache set :: CS Threads Dispatched */
#define cflgt2__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache set :: EU Active */
#define cflgt2__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache set :: EU Stall */
#define cflgt2__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache set :: EU Both FPU Pipes Active */
#define cflgt2__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Pipe Active */
#define cflgt2__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Pipe Active */
#define cflgt2__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define cflgt2__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define cflgt2__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache set :: EU Send Pipe Active */
#define cflgt2__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Hybrid Instruction */
#define cflgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Hybrid Instruction */
#define cflgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU0 Ternary Instruction */
#define cflgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Ternary Instruction */
#define cflgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Binary Instruction */
#define cflgt2__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Binary Instruction */
#define cflgt2__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Move Instruction */
#define cflgt2__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Move Instruction */
#define cflgt2__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: Rasterized Pixels */
#define cflgt2__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache set :: Early Hi-Depth Test Fails */
#define cflgt2__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Early Depth Test Fails */
#define cflgt2__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Samples Killed in FS */
#define cflgt2__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache set :: Pixels Failing Tests */
#define cflgt2__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache set :: Samples Written */
#define cflgt2__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache set :: Samples Blended */
#define cflgt2__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache set :: Sampler Accesses */
#define cflgt2__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache set :: Sampler Texels */
#define cflgt2__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache set :: Sampler Texels Misses */
#define cflgt2__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define cflgt2__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define cflgt2__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define cflgt2__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define cflgt2__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: Shader Memory Accesses */
#define cflgt2__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache set :: Shader Atomic Memory Accesses */
#define cflgt2__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache set :: L3 Accesses */
#define cflgt2__compute_l3_cache__l3_accesses__read \
   sklgt2__compute_l3_cache__l3_accesses__read

/* Compute Metrics L3 Cache set :: L3 Misses */
#define cflgt2__compute_l3_cache__l3_misses__read \
   bdw__compute_l3_cache__l3_misses__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define cflgt2__compute_l3_cache__l3_sampler_throughput__read \
   chv__render_basic__l3_sampler_throughput__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define cflgt2__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define cflgt2__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define cflgt2__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define cflgt2__compute_l3_cache__l3_total_throughput__read \
   sklgt2__compute_l3_cache__l3_total_throughput__read

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define cflgt2__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: Shader Barrier Messages */
#define cflgt2__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 Accesses */
#define cflgt2__compute_l3_cache__l3_bank00_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 01 Accesses */
#define cflgt2__compute_l3_cache__l3_bank01_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 02 Accesses */
#define cflgt2__compute_l3_cache__l3_bank02_accesses__read \
   bdw__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 03 Accesses */
#define cflgt2__compute_l3_cache__l3_bank03_accesses__read \
   bdw__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Accesses */
#define cflgt2__compute_l3_cache__l3_bank00_ic_accesses__read \
   bdw__compute_l3_cache__l3_bank00_ic_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Hits */
#define cflgt2__compute_l3_cache__l3_bank00_ic_hits__read \
   bdw__compute_l3_cache__l3_bank00_ic_hits__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define cflgt2__compute_l3_cache__gti_l3_throughput__read \
   bdw__compute_l3_cache__gti_l3_throughput__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define cflgt2__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define cflgt2__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define cflgt2__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define cflgt2__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define cflgt2__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define cflgt2__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define cflgt2__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define cflgt2__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define cflgt2__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define cflgt2__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define cflgt2__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define cflgt2__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define cflgt2__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define cflgt2__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define cflgt2__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define cflgt2__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define cflgt2__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define cflgt2__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define cflgt2__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define cflgt2__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define cflgt2__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define cflgt2__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define cflgt2__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define cflgt2__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define cflgt2__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define cflgt2__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define cflgt2__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define cflgt2__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define cflgt2__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define cflgt2__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define cflgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define cflgt2__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define cflgt2__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define cflgt2__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define cflgt2__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define cflgt2__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define cflgt2__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define cflgt2__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define cflgt2__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define cflgt2__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define cflgt2__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define cflgt2__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define cflgt2__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define cflgt2__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define cflgt2__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define cflgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define cflgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
#define cflgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define cflgt2__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define cflgt2__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define cflgt2__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define cflgt2__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define cflgt2__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define cflgt2__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define cflgt2__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define cflgt2__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define cflgt2__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define cflgt2__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define cflgt2__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define cflgt2__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define cflgt2__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define cflgt2__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define cflgt2__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define cflgt2__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define cflgt2__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define cflgt2__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define cflgt2__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define cflgt2__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define cflgt2__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define cflgt2__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define cflgt2__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define cflgt2__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define cflgt2__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define cflgt2__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define cflgt2__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define cflgt2__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define cflgt2__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define cflgt2__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define cflgt2__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define cflgt2__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define cflgt2__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define cflgt2__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define cflgt2__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define cflgt2__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define cflgt2__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define cflgt2__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define cflgt2__l3_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define cflgt2__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */
#define cflgt2__l3_1__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */
#define cflgt2__l3_1__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define cflgt2__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define cflgt2__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define cflgt2__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_2 :: GPU Time Elapsed */
#define cflgt2__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_2 :: GPU Core Clocks */
#define cflgt2__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define cflgt2__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define cflgt2__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_2 :: GPU Busy */
#define cflgt2__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_2 :: VS Threads Dispatched */
#define cflgt2__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_2 :: HS Threads Dispatched */
#define cflgt2__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_2 :: DS Threads Dispatched */
#define cflgt2__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_2 :: GS Threads Dispatched */
#define cflgt2__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_2 :: FS Threads Dispatched */
#define cflgt2__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_2 :: CS Threads Dispatched */
#define cflgt2__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_2 :: EU Active */
#define cflgt2__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_2 :: EU Stall */
#define cflgt2__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_2 :: EU Both FPU Pipes Active */
#define cflgt2__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_2 :: VS FPU0 Pipe Active */
#define cflgt2__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_2 :: VS FPU1 Pipe Active */
#define cflgt2__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_2 :: VS Send Pipe Active */
#define cflgt2__l3_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_2 :: PS FPU0 Pipe Active */
#define cflgt2__l3_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_2 :: PS FPU1 Pipe Active */
#define cflgt2__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_2 :: PS Send Pipeline Active */
#define cflgt2__l3_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_2 :: FS Both FPU Active */
#define cflgt2__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_2 :: Rasterized Pixels */
#define cflgt2__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_2 :: Early Hi-Depth Test Fails */
#define cflgt2__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_2 :: Early Depth Test Fails */
#define cflgt2__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Samples Killed in FS */
#define cflgt2__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_2 :: Pixels Failing Tests */
#define cflgt2__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_2 :: Samples Written */
#define cflgt2__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_2 :: Samples Blended */
#define cflgt2__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_2 :: Sampler Texels */
#define cflgt2__l3_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_2 :: Sampler Texels Misses */
#define cflgt2__l3_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_2 :: SLM Bytes Read */
#define cflgt2__l3_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_2 :: SLM Bytes Read */
#define cflgt2__l3_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: SLM Bytes Written */
#define cflgt2__l3_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_2 :: SLM Bytes Written */
#define cflgt2__l3_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Memory Accesses */
#define cflgt2__l3_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_2 :: Shader Atomic Memory Accesses */
#define cflgt2__l3_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define cflgt2__l3_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define cflgt2__l3_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Barrier Messages */
#define cflgt2__l3_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */
#define cflgt2__l3_2__l30_bank2_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Active */
#define cflgt2__l3_2__l30_bank2_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_2 :: SQ is full */
#define cflgt2__l3_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_3 :: GPU Time Elapsed */
#define cflgt2__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_3 :: GPU Core Clocks */
#define cflgt2__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define cflgt2__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define cflgt2__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_3 :: GPU Busy */
#define cflgt2__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_3 :: VS Threads Dispatched */
#define cflgt2__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_3 :: HS Threads Dispatched */
#define cflgt2__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_3 :: DS Threads Dispatched */
#define cflgt2__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_3 :: GS Threads Dispatched */
#define cflgt2__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_3 :: FS Threads Dispatched */
#define cflgt2__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_3 :: CS Threads Dispatched */
#define cflgt2__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_3 :: EU Active */
#define cflgt2__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_3 :: EU Stall */
#define cflgt2__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_3 :: EU Both FPU Pipes Active */
#define cflgt2__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_3 :: VS FPU0 Pipe Active */
#define cflgt2__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_3 :: VS FPU1 Pipe Active */
#define cflgt2__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_3 :: VS Send Pipe Active */
#define cflgt2__l3_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_3 :: PS FPU0 Pipe Active */
#define cflgt2__l3_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_3 :: PS FPU1 Pipe Active */
#define cflgt2__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_3 :: PS Send Pipeline Active */
#define cflgt2__l3_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_3 :: FS Both FPU Active */
#define cflgt2__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_3 :: Rasterized Pixels */
#define cflgt2__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_3 :: Early Hi-Depth Test Fails */
#define cflgt2__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_3 :: Early Depth Test Fails */
#define cflgt2__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Samples Killed in FS */
#define cflgt2__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_3 :: Pixels Failing Tests */
#define cflgt2__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_3 :: Samples Written */
#define cflgt2__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_3 :: Samples Blended */
#define cflgt2__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_3 :: Sampler Texels */
#define cflgt2__l3_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_3 :: Sampler Texels Misses */
#define cflgt2__l3_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_3 :: SLM Bytes Read */
#define cflgt2__l3_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_3 :: SLM Bytes Read */
#define cflgt2__l3_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: SLM Bytes Written */
#define cflgt2__l3_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_3 :: SLM Bytes Written */
#define cflgt2__l3_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Memory Accesses */
#define cflgt2__l3_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_3 :: Shader Atomic Memory Accesses */
#define cflgt2__l3_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define cflgt2__l3_3__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define cflgt2__l3_3__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Barrier Messages */
#define cflgt2__l3_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */
#define cflgt2__l3_3__l30_bank3_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Active */
#define cflgt2__l3_3__l30_bank3_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_3 :: SQ is full */
#define cflgt2__l3_3__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define cflgt2__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define cflgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define cflgt2__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define cflgt2__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define cflgt2__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define cflgt2__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define cflgt2__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define cflgt2__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define cflgt2__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define cflgt2__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define cflgt2__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define cflgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define cflgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define cflgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define cflgt2__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define cflgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define cflgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define cflgt2__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define cflgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define cflgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define cflgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define cflgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define cflgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define cflgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define cflgt2__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define cflgt2__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define cflgt2__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define cflgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define cflgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define cflgt2__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define cflgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define cflgt2__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define cflgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define cflgt2__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define cflgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define cflgt2__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define cflgt2__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define cflgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define cflgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define cflgt2__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define cflgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define cflgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define cflgt2__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler :: GPU Time Elapsed */
#define cflgt2__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler :: GPU Core Clocks */
#define cflgt2__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define cflgt2__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define cflgt2__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler :: GPU Busy */
#define cflgt2__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler :: VS Threads Dispatched */
#define cflgt2__sampler__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler :: HS Threads Dispatched */
#define cflgt2__sampler__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler :: DS Threads Dispatched */
#define cflgt2__sampler__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler :: GS Threads Dispatched */
#define cflgt2__sampler__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler :: FS Threads Dispatched */
#define cflgt2__sampler__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler :: CS Threads Dispatched */
#define cflgt2__sampler__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler :: EU Active */
#define cflgt2__sampler__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler :: EU Stall */
#define cflgt2__sampler__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler :: EU Both FPU Pipes Active */
#define cflgt2__sampler__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler :: VS FPU0 Pipe Active */
#define cflgt2__sampler__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler :: VS FPU1 Pipe Active */
#define cflgt2__sampler__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler :: VS Send Pipe Active */
#define cflgt2__sampler__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler :: PS FPU0 Pipe Active */
#define cflgt2__sampler__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler :: PS FPU1 Pipe Active */
#define cflgt2__sampler__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler :: PS Send Pipeline Active */
#define cflgt2__sampler__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler :: FS Both FPU Active */
#define cflgt2__sampler__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler :: Rasterized Pixels */
#define cflgt2__sampler__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler :: Early Hi-Depth Test Fails */
#define cflgt2__sampler__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler :: Early Depth Test Fails */
#define cflgt2__sampler__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Samples Killed in FS */
#define cflgt2__sampler__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler :: Pixels Failing Tests */
#define cflgt2__sampler__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler :: Samples Written */
#define cflgt2__sampler__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler :: Samples Blended */
#define cflgt2__sampler__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler :: Sampler Texels */
#define cflgt2__sampler__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler :: Sampler Texels Misses */
#define cflgt2__sampler__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler :: SLM Bytes Read */
#define cflgt2__sampler__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler :: SLM Bytes Read */
#define cflgt2__sampler__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: SLM Bytes Written */
#define cflgt2__sampler__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler :: SLM Bytes Written */
#define cflgt2__sampler__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Memory Accesses */
#define cflgt2__sampler__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler :: Shader Atomic Memory Accesses */
#define cflgt2__sampler__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler :: L3 Shader Throughput */
#define cflgt2__sampler__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler :: L3 Shader Throughput */
#define cflgt2__sampler__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Barrier Messages */
#define cflgt2__sampler__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Slice0 Subslice1 Input Available */
#define cflgt2__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler :: Slice0 Subslice2 Input Available */
#define cflgt2__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler :: Slice0 Subslice0 Input Available */
#define cflgt2__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */
#define cflgt2__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */
#define cflgt2__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */
#define cflgt2__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler :: SQ is full */
#define cflgt2__sampler__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define cflgt2__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define cflgt2__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define cflgt2__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define cflgt2__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define cflgt2__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define cflgt2__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define cflgt2__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define cflgt2__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define cflgt2__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define cflgt2__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define cflgt2__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define cflgt2__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define cflgt2__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define cflgt2__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define cflgt2__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define cflgt2__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define cflgt2__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define cflgt2__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define cflgt2__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define cflgt2__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define cflgt2__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define cflgt2__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define cflgt2__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define cflgt2__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define cflgt2__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define cflgt2__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define cflgt2__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define cflgt2__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define cflgt2__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define cflgt2__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define cflgt2__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define cflgt2__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define cflgt2__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define cflgt2__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define cflgt2__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define cflgt2__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define cflgt2__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define cflgt2__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define cflgt2__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define cflgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define cflgt2__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define cflgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define cflgt2__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define cflgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define cflgt2__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: SQ is full */
#define cflgt2__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define cflgt2__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define cflgt2__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define cflgt2__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define cflgt2__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define cflgt2__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define cflgt2__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define cflgt2__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define cflgt2__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define cflgt2__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define cflgt2__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define cflgt2__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define cflgt2__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define cflgt2__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define cflgt2__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define cflgt2__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define cflgt2__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define cflgt2__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define cflgt2__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define cflgt2__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define cflgt2__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define cflgt2__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define cflgt2__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define cflgt2__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define cflgt2__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define cflgt2__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define cflgt2__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define cflgt2__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define cflgt2__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define cflgt2__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define cflgt2__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define cflgt2__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define cflgt2__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define cflgt2__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define cflgt2__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define cflgt2__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define cflgt2__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define cflgt2__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define cflgt2__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define cflgt2__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define cflgt2__tdl_2__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define cflgt2__tdl_2__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define cflgt2__tdl_2__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define cflgt2__tdl_2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define cflgt2__tdl_2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define cflgt2__tdl_2__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define cflgt2__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define cflgt2__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define cflgt2__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define cflgt2__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define cflgt2__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define cflgt2__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extra set :: EU FPU1 Pipe Active including Ext Math */
#define cflgt2__compute_extra__fpu1_active_adjusted__read \
   sklgt2__compute_extra__fpu1_active_adjusted__read

/* Media Vme Pipe metrics set :: GPU Time Elapsed */
#define cflgt2__vme_pipe__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Media Vme Pipe metrics set :: GPU Core Clocks */
#define cflgt2__vme_pipe__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define cflgt2__vme_pipe__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define cflgt2__vme_pipe__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Media Vme Pipe metrics set :: GPU Busy */
#define cflgt2__vme_pipe__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Media Vme Pipe metrics set :: CS Threads Dispatched */
#define cflgt2__vme_pipe__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Media Vme Pipe metrics set :: EU Active */
#define cflgt2__vme_pipe__eu_active__read \
   bdw__render_basic__eu_active__read

/* Media Vme Pipe metrics set :: EU Stall */
#define cflgt2__vme_pipe__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Media Vme Pipe metrics set :: EU Both FPU Pipes Active */
#define cflgt2__vme_pipe__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Media Vme Pipe metrics set :: EU Thread Occupancy */
#define cflgt2__vme_pipe__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* Media Vme Pipe metrics set :: VME Busy */
#define cflgt2__vme_pipe__vme_busy__read \
   bdw__vme_pipe__vme_busy__read

/* Gpu Rings Busyness metrics set :: GPU Time Elapsed */
#define cflgt2__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness metrics set :: GPU Core Clocks */
#define cflgt2__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness metrics set :: AVG GPU Core Frequency */
#define cflgt2__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness metrics set :: AVG GPU Core Frequency */
#define cflgt2__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness metrics set :: Render Ring Busy */
#define cflgt2__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness metrics set :: Vdbox0 Ring Busy */
#define cflgt2__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness metrics set :: Vebox Ring Busy */
#define cflgt2__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness metrics set :: Blitter Ring Busy */
#define cflgt2__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness metrics set :: AnyRingBusy */
#define cflgt2__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* MDAPI testing set :: GPU Time Elapsed */
#define cflgt2__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define cflgt2__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define cflgt2__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define cflgt2__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define cflgt2__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define cflgt2__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define cflgt2__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define cflgt2__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define cflgt2__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define cflgt2__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define cflgt2__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define cflgt2__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define cflgt2__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define cflgt2__pma__stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define cflgt2__pma__stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define cflgt2__pma__stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define cflgt2__pma__stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: STC PMA stall */
#define cflgt2__pma__stall__stc_pma_stall__read \
   sklgt2__pma__stall__stc_pma_stall__read

/* AsyncCompute metrics set :: GPU Time Elapsed */
#define cflgt2__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute metrics set :: GPU Core Clocks */
#define cflgt2__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute metrics set :: AVG GPU Core Frequency */
#define cflgt2__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute metrics set :: AVG GPU Core Frequency */
#define cflgt2__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute metrics set :: GPU Busy */
#define cflgt2__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute metrics set :: VS Threads Dispatched */
#define cflgt2__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute metrics set :: HS Threads Dispatched */
#define cflgt2__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute metrics set :: DS Threads Dispatched */
#define cflgt2__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute metrics set :: GS Threads Dispatched */
#define cflgt2__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute metrics set :: FS Threads Dispatched */
#define cflgt2__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute metrics set :: CS Threads Dispatched */
#define cflgt2__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute metrics set :: EU FPU0 Pipe Active */
#define cflgt2__async_compute__fpu0_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute metrics set :: VS FPU0 Pipe Active */
#define cflgt2__async_compute__vs_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute metrics set :: PS FPU0 Pipe Active */
#define cflgt2__async_compute__ps_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute metrics set :: CS FPU0 Pipe Active */
#define cflgt2__async_compute__cs_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute metrics set :: EU FPU1 Pipe Active */
#define cflgt2__async_compute__fpu1_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute metrics set :: VS FPU1 Pipe Active */
#define cflgt2__async_compute__vs_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute metrics set :: PS FPU1 Pipe Active */
#define cflgt2__async_compute__ps_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute metrics set :: CS FPU1 Pipe Active */
#define cflgt2__async_compute__cs_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute metrics set :: EU Thread Occupancy */
#define cflgt2__async_compute__eu_thread_occupancy__read \
   sklgt2__ff_bottlenecks__eu_thread_occupancy__read

/* AsyncCompute metrics set :: EU Active */
#define cflgt2__async_compute__eu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute metrics set :: EU Stall */
#define cflgt2__async_compute__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define cflgt3__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define cflgt3__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define cflgt3__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define cflgt3__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define cflgt3__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define cflgt3__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define cflgt3__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define cflgt3__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define cflgt3__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define cflgt3__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define cflgt3__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define cflgt3__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define cflgt3__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define cflgt3__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define cflgt3__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define cflgt3__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define cflgt3__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define cflgt3__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define cflgt3__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define cflgt3__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define cflgt3__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define cflgt3__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define cflgt3__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define cflgt3__render_basic__samplers_busy__read \
   bdw__render_basic__samplers_busy__read

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define cflgt3__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
#define cflgt3__render_basic__sampler1_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define cflgt3__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define cflgt3__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define cflgt3__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define cflgt3__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define cflgt3__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define cflgt3__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define cflgt3__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define cflgt3__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define cflgt3__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
#define cflgt3__render_basic__sampler_l1_misses__read \
   bdw__render_basic__sampler_l1_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define cflgt3__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define cflgt3__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define cflgt3__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define cflgt3__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define cflgt3__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define cflgt3__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
#define cflgt3__render_basic__l3_lookups__read \
   bdw__render_basic__l3_lookups__read

/* Render Metrics Basic set :: L3 Misses */
#define cflgt3__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define cflgt3__render_basic__l3_sampler_throughput__read \
   bdw__render_basic__l3_sampler_throughput__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define cflgt3__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define cflgt3__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define cflgt3__render_basic__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define cflgt3__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define cflgt3__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define cflgt3__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define cflgt3__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define cflgt3__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define cflgt3__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define cflgt3__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define cflgt3__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define cflgt3__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define cflgt3__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define cflgt3__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define cflgt3__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define cflgt3__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define cflgt3__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define cflgt3__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define cflgt3__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define cflgt3__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define cflgt3__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define cflgt3__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define cflgt3__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define cflgt3__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define cflgt3__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define cflgt3__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define cflgt3__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define cflgt3__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define cflgt3__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define cflgt3__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define cflgt3__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define cflgt3__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define cflgt3__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define cflgt3__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define cflgt3__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define cflgt3__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define cflgt3__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define cflgt3__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define cflgt3__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define cflgt3__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define cflgt3__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define cflgt3__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define cflgt3__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define cflgt3__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define cflgt3__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define cflgt3__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define cflgt3__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define cflgt3__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define cflgt3__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define cflgt3__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define cflgt3__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define cflgt3__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define cflgt3__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define cflgt3__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define cflgt3__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define cflgt3__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define cflgt3__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define cflgt3__compute_basic__typed_bytes_read__read \
   bdw__compute_basic__typed_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define cflgt3__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
#define cflgt3__compute_basic__typed_bytes_written__read \
   bdw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Typed Bytes Written */
#define cflgt3__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define cflgt3__compute_basic__untyped_bytes_read__read \
   bdw__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define cflgt3__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define cflgt3__compute_basic__untyped_bytes_written__read \
   bdw__compute_basic__untyped_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define cflgt3__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define cflgt3__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define cflgt3__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define cflgt3__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define cflgt3__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define cflgt3__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define cflgt3__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define cflgt3__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define cflgt3__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define cflgt3__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define cflgt3__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define cflgt3__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define cflgt3__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define cflgt3__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define cflgt3__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define cflgt3__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define cflgt3__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define cflgt3__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define cflgt3__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define cflgt3__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define cflgt3__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define cflgt3__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define cflgt3__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define cflgt3__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define cflgt3__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define cflgt3__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define cflgt3__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define cflgt3__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define cflgt3__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define cflgt3__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define cflgt3__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define cflgt3__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define cflgt3__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define cflgt3__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define cflgt3__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define cflgt3__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define cflgt3__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define cflgt3__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define cflgt3__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define cflgt3__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define cflgt3__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define cflgt3__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define cflgt3__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define cflgt3__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define cflgt3__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define cflgt3__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define cflgt3__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define cflgt3__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define cflgt3__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define cflgt3__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define cflgt3__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define cflgt3__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory Reads Distribution metrics set :: GPU Time Elapsed */
#define cflgt3__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metrics set :: GPU Core Clocks */
#define cflgt3__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define cflgt3__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define cflgt3__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metrics set :: GPU Busy */
#define cflgt3__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metrics set :: VS Threads Dispatched */
#define cflgt3__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: HS Threads Dispatched */
#define cflgt3__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metrics set :: DS Threads Dispatched */
#define cflgt3__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metrics set :: GS Threads Dispatched */
#define cflgt3__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: FS Threads Dispatched */
#define cflgt3__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metrics set :: CS Threads Dispatched */
#define cflgt3__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metrics set :: EU Active */
#define cflgt3__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metrics set :: EU Stall */
#define cflgt3__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metrics set :: Rasterized Pixels */
#define cflgt3__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metrics set :: Early Hi-Depth Test Fails */
#define cflgt3__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Early Depth Test Fails */
#define cflgt3__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Samples Killed in FS */
#define cflgt3__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metrics set :: Pixels Failing Tests */
#define cflgt3__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metrics set :: Samples Written */
#define cflgt3__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metrics set :: Samples Blended */
#define cflgt3__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metrics set :: Sampler Texels */
#define cflgt3__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metrics set :: Sampler Texels Misses */
#define cflgt3__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define cflgt3__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define cflgt3__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define cflgt3__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define cflgt3__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: Shader Memory Accesses */
#define cflgt3__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metrics set :: Shader Atomic Memory Accesses */
#define cflgt3__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metrics set :: Shader Barrier Messages */
#define cflgt3__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: GtiCmdStreamerMemoryReads */
#define cflgt3__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metrics set :: GtiRsMemoryReads */
#define cflgt3__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metrics set :: GtiVfMemoryReads */
#define cflgt3__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metrics set :: GtiRccMemoryReads */
#define cflgt3__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiMscMemoryReads */
#define cflgt3__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metrics set :: GtiHizMemoryReads */
#define cflgt3__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiStcMemoryReads */
#define cflgt3__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metrics set :: GtiRczMemoryReads */
#define cflgt3__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metrics set :: GtiMemoryReads */
#define cflgt3__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank0Reads */
#define cflgt3__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank1Reads */
#define cflgt3__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metrics set :: GtiL3Bank2Reads */
#define cflgt3__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metrics set :: GtiL3Bank3Reads */
#define cflgt3__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: GtiL3Reads */
#define cflgt3__memory_reads__gti_l3_reads__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Reads Distribution metrics set :: GtiRingAccesses */
#define cflgt3__memory_reads__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Memory Writes Distribution metrics set :: GPU Time Elapsed */
#define cflgt3__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metrics set :: GPU Core Clocks */
#define cflgt3__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define cflgt3__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define cflgt3__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metrics set :: GPU Busy */
#define cflgt3__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metrics set :: VS Threads Dispatched */
#define cflgt3__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: HS Threads Dispatched */
#define cflgt3__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metrics set :: DS Threads Dispatched */
#define cflgt3__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metrics set :: GS Threads Dispatched */
#define cflgt3__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: FS Threads Dispatched */
#define cflgt3__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metrics set :: CS Threads Dispatched */
#define cflgt3__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metrics set :: EU Active */
#define cflgt3__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metrics set :: EU Stall */
#define cflgt3__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metrics set :: Rasterized Pixels */
#define cflgt3__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metrics set :: Early Hi-Depth Test Fails */
#define cflgt3__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Early Depth Test Fails */
#define cflgt3__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Samples Killed in FS */
#define cflgt3__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metrics set :: Pixels Failing Tests */
#define cflgt3__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metrics set :: Samples Written */
#define cflgt3__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metrics set :: Samples Blended */
#define cflgt3__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metrics set :: Sampler Texels */
#define cflgt3__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metrics set :: Sampler Texels Misses */
#define cflgt3__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define cflgt3__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define cflgt3__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define cflgt3__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define cflgt3__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Memory Accesses */
#define cflgt3__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metrics set :: Shader Atomic Memory Accesses */
#define cflgt3__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define cflgt3__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define cflgt3__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Memory Writes Distribution metrics set :: Shader Barrier Messages */
#define cflgt3__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: GtiCmdStreamerMemoryWrites */
#define cflgt3__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metrics set :: GtiSoMemoryWrites */
#define cflgt3__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metrics set :: GtiRccMemoryWrites */
#define cflgt3__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiMscMemoryWrites */
#define cflgt3__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metrics set :: GtiHizMemoryWrites */
#define cflgt3__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiStcMemoryWrites */
#define cflgt3__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metrics set :: GtiRczMemoryWrites */
#define cflgt3__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metrics set :: GtiMemoryWrites */
#define cflgt3__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank0Writes */
#define cflgt3__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank1Writes */
#define cflgt3__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metrics set :: GtiL3Bank2Writes */
#define cflgt3__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metrics set :: GtiL3Bank3Writes */
#define cflgt3__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: GtiL3Writes */
#define cflgt3__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metrics set :: GtiRingAccesses */
#define cflgt3__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended metrics set :: GPU Time Elapsed */
#define cflgt3__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended metrics set :: GPU Core Clocks */
#define cflgt3__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended metrics set :: AVG GPU Core Frequency */
#define cflgt3__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended metrics set :: AVG GPU Core Frequency */
#define cflgt3__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended metrics set :: CS Threads Dispatched */
#define cflgt3__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended metrics set :: EU Active */
#define cflgt3__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended metrics set :: EU Stall */
#define cflgt3__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended metrics set :: EU Both FPU Pipes Active */
#define cflgt3__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended metrics set :: EU FPU0 Pipe Active */
#define cflgt3__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended metrics set :: EU FPU1 Pipe Active */
#define cflgt3__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended metrics set :: EU AVG IPC Rate */
#define cflgt3__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended metrics set :: EU AVG IPC Rate */
#define cflgt3__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended metrics set :: EU Send Pipe Active */
#define cflgt3__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended metrics set :: EU Thread Occupancy */
#define cflgt3__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended metrics set :: Sampler Texels */
#define cflgt3__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended metrics set :: Sampler Texels Misses */
#define cflgt3__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended metrics set :: SLM Bytes Read */
#define cflgt3__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended metrics set :: SLM Bytes Read */
#define cflgt3__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended metrics set :: SLM Bytes Written */
#define cflgt3__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended metrics set :: SLM Bytes Written */
#define cflgt3__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended metrics set :: Shader Memory Accesses */
#define cflgt3__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended metrics set :: Shader Atomic Memory Accesses */
#define cflgt3__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended metrics set :: L3 Shader Throughput */
#define cflgt3__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended metrics set :: L3 Shader Throughput */
#define cflgt3__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Extended metrics set :: Shader Barrier Messages */
#define cflgt3__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended metrics set :: EuUntypedReads0 */
#define cflgt3__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended metrics set :: EuTypedReads0 */
#define cflgt3__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended metrics set :: EuUntypedWrites0 */
#define cflgt3__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended metrics set :: EuTypedWrites0 */
#define cflgt3__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended metrics set :: EuUntypedAtomics0 */
#define cflgt3__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended metrics set :: EuTypedAtomics0 */
#define cflgt3__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended metrics set :: EuA64UntypedReads0 */
#define cflgt3__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended metrics set :: EuA64UntypedWrites0 */
#define cflgt3__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended metrics set :: Typed Reads 0 */
#define cflgt3__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended metrics set :: Typed Writes 0 */
#define cflgt3__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended metrics set :: Untyped Reads 0 */
#define cflgt3__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended metrics set :: Untyped Writes 0 */
#define cflgt3__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended metrics set :: Typed Atomics 0 */
#define cflgt3__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended metrics set :: TypedReadsPerCacheLine */
#define cflgt3__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended metrics set :: TypedWritesPerCacheLine */
#define cflgt3__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended metrics set :: UntypedReadsPerCacheLine */
#define cflgt3__compute_extended__untyped_reads_per_cache_line__read \
   bdw__compute_extended__untyped_reads_per_cache_line__read

/* Compute Metrics Extended metrics set :: UntypedWritesPerCacheLine */
#define cflgt3__compute_extended__untyped_writes_per_cache_line__read \
   bdw__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics Extended metrics set :: TypedAtomicsPerCacheLine */
#define cflgt3__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache metrics set :: GPU Time Elapsed */
#define cflgt3__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache metrics set :: GPU Core Clocks */
#define cflgt3__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache metrics set :: AVG GPU Core Frequency */
#define cflgt3__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache metrics set :: AVG GPU Core Frequency */
#define cflgt3__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache metrics set :: GPU Busy */
#define cflgt3__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache metrics set :: VS Threads Dispatched */
#define cflgt3__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metrics set :: HS Threads Dispatched */
#define cflgt3__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache metrics set :: DS Threads Dispatched */
#define cflgt3__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache metrics set :: GS Threads Dispatched */
#define cflgt3__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metrics set :: FS Threads Dispatched */
#define cflgt3__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache metrics set :: CS Threads Dispatched */
#define cflgt3__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache metrics set :: EU Active */
#define cflgt3__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache metrics set :: EU Stall */
#define cflgt3__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache metrics set :: EU Both FPU Pipes Active */
#define cflgt3__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Pipe Active */
#define cflgt3__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Pipe Active */
#define cflgt3__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache metrics set :: EU AVG IPC Rate */
#define cflgt3__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache metrics set :: EU AVG IPC Rate */
#define cflgt3__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache metrics set :: EU Send Pipe Active */
#define cflgt3__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Hybrid Instruction */
#define cflgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Hybrid Instruction */
#define cflgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Ternary Instruction */
#define cflgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Ternary Instruction */
#define cflgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Binary Instruction */
#define cflgt3__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Binary Instruction */
#define cflgt3__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Move Instruction */
#define cflgt3__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Move Instruction */
#define cflgt3__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache metrics set :: Rasterized Pixels */
#define cflgt3__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache metrics set :: Early Hi-Depth Test Fails */
#define cflgt3__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache metrics set :: Early Depth Test Fails */
#define cflgt3__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metrics set :: Samples Killed in FS */
#define cflgt3__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache metrics set :: Pixels Failing Tests */
#define cflgt3__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache metrics set :: Samples Written */
#define cflgt3__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache metrics set :: Samples Blended */
#define cflgt3__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache metrics set :: Sampler Accesses */
#define cflgt3__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache metrics set :: Sampler Texels */
#define cflgt3__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache metrics set :: Sampler Texels Misses */
#define cflgt3__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Read */
#define cflgt3__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Read */
#define cflgt3__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Written */
#define cflgt3__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Written */
#define cflgt3__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metrics set :: Shader Memory Accesses */
#define cflgt3__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache metrics set :: Shader Atomic Memory Accesses */
#define cflgt3__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache metrics set :: L3 Accesses */
#define cflgt3__compute_l3_cache__l3_accesses__read \
   sklgt2__compute_l3_cache__l3_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Misses */
#define cflgt3__compute_l3_cache__l3_misses__read \
   bdw__compute_l3_cache__l3_misses__read

/* Compute Metrics L3 Cache metrics set :: L3 Sampler Throughput */
#define cflgt3__compute_l3_cache__l3_sampler_throughput__read \
   chv__render_basic__l3_sampler_throughput__read

/* Compute Metrics L3 Cache metrics set :: L3 Sampler Throughput */
#define cflgt3__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metrics set :: L3 Shader Throughput */
#define cflgt3__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache metrics set :: L3 Shader Throughput */
#define cflgt3__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metrics set :: L3 Total Throughput */
#define cflgt3__compute_l3_cache__l3_total_throughput__read \
   sklgt2__compute_l3_cache__l3_total_throughput__read

/* Compute Metrics L3 Cache metrics set :: L3 Total Throughput */
#define cflgt3__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metrics set :: Shader Barrier Messages */
#define cflgt3__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 00 Accesses */
#define cflgt3__compute_l3_cache__l3_bank00_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 01 Accesses */
#define cflgt3__compute_l3_cache__l3_bank01_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 02 Accesses */
#define cflgt3__compute_l3_cache__l3_bank02_accesses__read \
   bdw__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 03 Accesses */
#define cflgt3__compute_l3_cache__l3_bank03_accesses__read \
   bdw__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 00 IC Accesses */
#define cflgt3__compute_l3_cache__l3_bank00_ic_accesses__read \
   bdw__compute_l3_cache__l3_bank00_ic_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Bank 00 IC Hits */
#define cflgt3__compute_l3_cache__l3_bank00_ic_hits__read \
   bdw__compute_l3_cache__l3_bank00_ic_hits__read

/* Compute Metrics L3 Cache metrics set :: GTI L3 Throughput */
#define cflgt3__compute_l3_cache__gti_l3_throughput__read \
   bdw__compute_l3_cache__gti_l3_throughput__read

/* Compute Metrics L3 Cache metrics set :: GTI L3 Throughput */
#define cflgt3__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metrics set :: GTI Read Throughput */
#define cflgt3__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache metrics set :: GTI Read Throughput */
#define cflgt3__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache metrics set :: GTI Write Throughput */
#define cflgt3__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache metrics set :: GTI Write Throughput */
#define cflgt3__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define cflgt3__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define cflgt3__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define cflgt3__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define cflgt3__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define cflgt3__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define cflgt3__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define cflgt3__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define cflgt3__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define cflgt3__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define cflgt3__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define cflgt3__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define cflgt3__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define cflgt3__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define cflgt3__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define cflgt3__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define cflgt3__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define cflgt3__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define cflgt3__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define cflgt3__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define cflgt3__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define cflgt3__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define cflgt3__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define cflgt3__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define cflgt3__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define cflgt3__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define cflgt3__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define cflgt3__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define cflgt3__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define cflgt3__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define cflgt3__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define cflgt3__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define cflgt3__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define cflgt3__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define cflgt3__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define cflgt3__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define cflgt3__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define cflgt3__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define cflgt3__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define cflgt3__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define cflgt3__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define cflgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define cflgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */
#define cflgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define cflgt3__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define cflgt3__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define cflgt3__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define cflgt3__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define cflgt3__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define cflgt3__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define cflgt3__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define cflgt3__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define cflgt3__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define cflgt3__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define cflgt3__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define cflgt3__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define cflgt3__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define cflgt3__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define cflgt3__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define cflgt3__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define cflgt3__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define cflgt3__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define cflgt3__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define cflgt3__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define cflgt3__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define cflgt3__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define cflgt3__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define cflgt3__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define cflgt3__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define cflgt3__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define cflgt3__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define cflgt3__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define cflgt3__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define cflgt3__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define cflgt3__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define cflgt3__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define cflgt3__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define cflgt3__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define cflgt3__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define cflgt3__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define cflgt3__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define cflgt3__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define cflgt3__l3_1__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define cflgt3__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */
#define cflgt3__l3_1__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */
#define cflgt3__l3_1__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define cflgt3__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define cflgt3__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define cflgt3__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_2 :: GPU Time Elapsed */
#define cflgt3__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_2 :: GPU Core Clocks */
#define cflgt3__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define cflgt3__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_2 :: AVG GPU Core Frequency */
#define cflgt3__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_2 :: GPU Busy */
#define cflgt3__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_2 :: VS Threads Dispatched */
#define cflgt3__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_2 :: HS Threads Dispatched */
#define cflgt3__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_2 :: DS Threads Dispatched */
#define cflgt3__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_2 :: GS Threads Dispatched */
#define cflgt3__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_2 :: FS Threads Dispatched */
#define cflgt3__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_2 :: CS Threads Dispatched */
#define cflgt3__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_2 :: EU Active */
#define cflgt3__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_2 :: EU Stall */
#define cflgt3__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_2 :: EU Both FPU Pipes Active */
#define cflgt3__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_2 :: VS FPU0 Pipe Active */
#define cflgt3__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_2 :: VS FPU1 Pipe Active */
#define cflgt3__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_2 :: VS Send Pipe Active */
#define cflgt3__l3_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_2 :: PS FPU0 Pipe Active */
#define cflgt3__l3_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_2 :: PS FPU1 Pipe Active */
#define cflgt3__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_2 :: PS Send Pipeline Active */
#define cflgt3__l3_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_2 :: FS Both FPU Active */
#define cflgt3__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_2 :: Rasterized Pixels */
#define cflgt3__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_2 :: Early Hi-Depth Test Fails */
#define cflgt3__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_2 :: Early Depth Test Fails */
#define cflgt3__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Samples Killed in FS */
#define cflgt3__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_2 :: Pixels Failing Tests */
#define cflgt3__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_2 :: Samples Written */
#define cflgt3__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_2 :: Samples Blended */
#define cflgt3__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_2 :: Sampler Texels */
#define cflgt3__l3_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_2 :: Sampler Texels Misses */
#define cflgt3__l3_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_2 :: SLM Bytes Read */
#define cflgt3__l3_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_2 :: SLM Bytes Read */
#define cflgt3__l3_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: SLM Bytes Written */
#define cflgt3__l3_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_2 :: SLM Bytes Written */
#define cflgt3__l3_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_2 :: Shader Memory Accesses */
#define cflgt3__l3_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_2 :: Shader Atomic Memory Accesses */
#define cflgt3__l3_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define cflgt3__l3_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_2 :: L3 Shader Throughput */
#define cflgt3__l3_2__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set L3_2 :: Shader Barrier Messages */
#define cflgt3__l3_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */
#define cflgt3__l3_2__l30_bank2_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_2 :: Slice0 L3 Bank2 Active */
#define cflgt3__l3_2__l30_bank2_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_2 :: SQ is full */
#define cflgt3__l3_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_3 :: GPU Time Elapsed */
#define cflgt3__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_3 :: GPU Core Clocks */
#define cflgt3__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define cflgt3__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_3 :: AVG GPU Core Frequency */
#define cflgt3__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_3 :: GPU Busy */
#define cflgt3__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_3 :: VS Threads Dispatched */
#define cflgt3__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_3 :: HS Threads Dispatched */
#define cflgt3__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_3 :: DS Threads Dispatched */
#define cflgt3__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_3 :: GS Threads Dispatched */
#define cflgt3__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_3 :: FS Threads Dispatched */
#define cflgt3__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_3 :: CS Threads Dispatched */
#define cflgt3__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_3 :: EU Active */
#define cflgt3__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_3 :: EU Stall */
#define cflgt3__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_3 :: EU Both FPU Pipes Active */
#define cflgt3__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_3 :: VS FPU0 Pipe Active */
#define cflgt3__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_3 :: VS FPU1 Pipe Active */
#define cflgt3__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_3 :: VS Send Pipe Active */
#define cflgt3__l3_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_3 :: PS FPU0 Pipe Active */
#define cflgt3__l3_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_3 :: PS FPU1 Pipe Active */
#define cflgt3__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_3 :: PS Send Pipeline Active */
#define cflgt3__l3_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_3 :: FS Both FPU Active */
#define cflgt3__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_3 :: Rasterized Pixels */
#define cflgt3__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_3 :: Early Hi-Depth Test Fails */
#define cflgt3__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_3 :: Early Depth Test Fails */
#define cflgt3__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Samples Killed in FS */
#define cflgt3__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_3 :: Pixels Failing Tests */
#define cflgt3__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_3 :: Samples Written */
#define cflgt3__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_3 :: Samples Blended */
#define cflgt3__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_3 :: Sampler Texels */
#define cflgt3__l3_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_3 :: Sampler Texels Misses */
#define cflgt3__l3_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_3 :: SLM Bytes Read */
#define cflgt3__l3_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_3 :: SLM Bytes Read */
#define cflgt3__l3_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: SLM Bytes Written */
#define cflgt3__l3_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_3 :: SLM Bytes Written */
#define cflgt3__l3_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_3 :: Shader Memory Accesses */
#define cflgt3__l3_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_3 :: Shader Atomic Memory Accesses */
#define cflgt3__l3_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define cflgt3__l3_3__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_3 :: L3 Shader Throughput */
#define cflgt3__l3_3__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set L3_3 :: Shader Barrier Messages */
#define cflgt3__l3_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */
#define cflgt3__l3_3__l30_bank3_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_3 :: Slice0 L3 Bank3 Active */
#define cflgt3__l3_3__l30_bank3_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_3 :: SQ is full */
#define cflgt3__l3_3__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define cflgt3__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define cflgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define cflgt3__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define cflgt3__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define cflgt3__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define cflgt3__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define cflgt3__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define cflgt3__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define cflgt3__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define cflgt3__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define cflgt3__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define cflgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define cflgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define cflgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define cflgt3__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define cflgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define cflgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define cflgt3__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define cflgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define cflgt3__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define cflgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define cflgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define cflgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define cflgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define cflgt3__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define cflgt3__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define cflgt3__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define cflgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define cflgt3__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define cflgt3__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define cflgt3__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define cflgt3__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define cflgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define cflgt3__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define cflgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define cflgt3__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define cflgt3__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define cflgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define cflgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define cflgt3__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define cflgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define cflgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define cflgt3__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler :: GPU Time Elapsed */
#define cflgt3__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler :: GPU Core Clocks */
#define cflgt3__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define cflgt3__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define cflgt3__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler :: GPU Busy */
#define cflgt3__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler :: VS Threads Dispatched */
#define cflgt3__sampler__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler :: HS Threads Dispatched */
#define cflgt3__sampler__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler :: DS Threads Dispatched */
#define cflgt3__sampler__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler :: GS Threads Dispatched */
#define cflgt3__sampler__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler :: FS Threads Dispatched */
#define cflgt3__sampler__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler :: CS Threads Dispatched */
#define cflgt3__sampler__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler :: EU Active */
#define cflgt3__sampler__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler :: EU Stall */
#define cflgt3__sampler__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler :: EU Both FPU Pipes Active */
#define cflgt3__sampler__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler :: VS FPU0 Pipe Active */
#define cflgt3__sampler__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler :: VS FPU1 Pipe Active */
#define cflgt3__sampler__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler :: VS Send Pipe Active */
#define cflgt3__sampler__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler :: PS FPU0 Pipe Active */
#define cflgt3__sampler__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler :: PS FPU1 Pipe Active */
#define cflgt3__sampler__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler :: PS Send Pipeline Active */
#define cflgt3__sampler__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler :: FS Both FPU Active */
#define cflgt3__sampler__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler :: Rasterized Pixels */
#define cflgt3__sampler__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler :: Early Hi-Depth Test Fails */
#define cflgt3__sampler__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler :: Early Depth Test Fails */
#define cflgt3__sampler__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Samples Killed in FS */
#define cflgt3__sampler__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler :: Pixels Failing Tests */
#define cflgt3__sampler__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler :: Samples Written */
#define cflgt3__sampler__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler :: Samples Blended */
#define cflgt3__sampler__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler :: Sampler Texels */
#define cflgt3__sampler__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler :: Sampler Texels Misses */
#define cflgt3__sampler__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler :: SLM Bytes Read */
#define cflgt3__sampler__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler :: SLM Bytes Read */
#define cflgt3__sampler__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: SLM Bytes Written */
#define cflgt3__sampler__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler :: SLM Bytes Written */
#define cflgt3__sampler__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Memory Accesses */
#define cflgt3__sampler__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler :: Shader Atomic Memory Accesses */
#define cflgt3__sampler__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler :: L3 Shader Throughput */
#define cflgt3__sampler__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler :: L3 Shader Throughput */
#define cflgt3__sampler__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set Sampler :: Shader Barrier Messages */
#define cflgt3__sampler__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Slice0 Subslice1 Input Available */
#define cflgt3__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler :: Slice0 Subslice2 Input Available */
#define cflgt3__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler :: Slice0 Subslice0 Input Available */
#define cflgt3__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */
#define cflgt3__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */
#define cflgt3__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */
#define cflgt3__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler :: SQ is full */
#define cflgt3__sampler__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define cflgt3__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define cflgt3__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define cflgt3__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define cflgt3__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define cflgt3__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define cflgt3__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define cflgt3__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define cflgt3__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define cflgt3__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define cflgt3__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define cflgt3__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define cflgt3__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define cflgt3__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define cflgt3__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define cflgt3__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define cflgt3__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define cflgt3__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define cflgt3__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define cflgt3__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define cflgt3__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define cflgt3__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define cflgt3__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define cflgt3__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define cflgt3__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define cflgt3__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define cflgt3__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define cflgt3__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define cflgt3__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define cflgt3__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define cflgt3__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define cflgt3__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define cflgt3__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define cflgt3__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define cflgt3__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define cflgt3__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define cflgt3__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define cflgt3__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define cflgt3__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define cflgt3__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define cflgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define cflgt3__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define cflgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define cflgt3__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define cflgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define cflgt3__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: SQ is full */
#define cflgt3__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define cflgt3__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define cflgt3__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define cflgt3__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define cflgt3__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define cflgt3__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define cflgt3__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define cflgt3__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define cflgt3__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define cflgt3__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define cflgt3__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define cflgt3__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define cflgt3__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define cflgt3__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define cflgt3__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define cflgt3__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define cflgt3__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define cflgt3__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define cflgt3__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define cflgt3__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define cflgt3__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define cflgt3__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define cflgt3__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define cflgt3__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define cflgt3__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define cflgt3__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define cflgt3__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define cflgt3__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define cflgt3__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define cflgt3__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define cflgt3__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define cflgt3__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define cflgt3__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define cflgt3__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define cflgt3__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define cflgt3__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define cflgt3__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define cflgt3__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define cflgt3__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define cflgt3__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define cflgt3__tdl_2__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define cflgt3__tdl_2__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define cflgt3__tdl_2__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define cflgt3__tdl_2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define cflgt3__tdl_2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define cflgt3__tdl_2__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define cflgt3__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define cflgt3__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define cflgt3__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define cflgt3__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define cflgt3__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define cflgt3__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extra set :: EU FPU1 Pipe Active including Ext Math */
#define cflgt3__compute_extra__fpu1_active_adjusted__read \
   bdw__compute_extra__fpu1_active_adjusted__read

/* Media Vme Pipe metrics set :: GPU Time Elapsed */
#define cflgt3__vme_pipe__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Media Vme Pipe metrics set :: GPU Core Clocks */
#define cflgt3__vme_pipe__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define cflgt3__vme_pipe__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Media Vme Pipe metrics set :: AVG GPU Core Frequency */
#define cflgt3__vme_pipe__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Media Vme Pipe metrics set :: GPU Busy */
#define cflgt3__vme_pipe__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Media Vme Pipe metrics set :: CS Threads Dispatched */
#define cflgt3__vme_pipe__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Media Vme Pipe metrics set :: EU Active */
#define cflgt3__vme_pipe__eu_active__read \
   bdw__render_basic__eu_active__read

/* Media Vme Pipe metrics set :: EU Stall */
#define cflgt3__vme_pipe__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Media Vme Pipe metrics set :: EU Both FPU Pipes Active */
#define cflgt3__vme_pipe__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Media Vme Pipe metrics set :: EU Thread Occupancy */
#define cflgt3__vme_pipe__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* Media Vme Pipe metrics set :: VME Busy */
#define cflgt3__vme_pipe__vme_busy__read \
   bdw__vme_pipe__vme_busy__read

/* Gpu Rings Busyness metrics set :: GPU Time Elapsed */
#define cflgt3__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness metrics set :: GPU Core Clocks */
#define cflgt3__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness metrics set :: AVG GPU Core Frequency */
#define cflgt3__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness metrics set :: AVG GPU Core Frequency */
#define cflgt3__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness metrics set :: Render Ring Busy */
#define cflgt3__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness metrics set :: Vdbox0 Ring Busy */
#define cflgt3__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness metrics set :: Vdbox1 Ring Busy */
#define cflgt3__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness metrics set :: Vebox Ring Busy */
#define cflgt3__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness metrics set :: Blitter Ring Busy */
#define cflgt3__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* Gpu Rings Busyness metrics set :: AnyRingBusy */
#define cflgt3__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* MDAPI testing set :: GPU Time Elapsed */
#define cflgt3__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define cflgt3__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define cflgt3__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define cflgt3__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define cflgt3__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define cflgt3__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define cflgt3__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define cflgt3__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define cflgt3__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define cflgt3__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define cflgt3__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define cflgt3__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define cflgt3__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define cflgt3__pma__stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define cflgt3__pma__stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define cflgt3__pma__stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define cflgt3__pma__stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: STC PMA stall */
#define cflgt3__pma__stall__stc_pma_stall__read \
   sklgt2__pma__stall__stc_pma_stall__read

/* AsyncCompute metrics set :: GPU Time Elapsed */
#define cflgt3__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute metrics set :: GPU Core Clocks */
#define cflgt3__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute metrics set :: AVG GPU Core Frequency */
#define cflgt3__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute metrics set :: AVG GPU Core Frequency */
#define cflgt3__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute metrics set :: GPU Busy */
#define cflgt3__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute metrics set :: VS Threads Dispatched */
#define cflgt3__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute metrics set :: HS Threads Dispatched */
#define cflgt3__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute metrics set :: DS Threads Dispatched */
#define cflgt3__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute metrics set :: GS Threads Dispatched */
#define cflgt3__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute metrics set :: FS Threads Dispatched */
#define cflgt3__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute metrics set :: CS Threads Dispatched */
#define cflgt3__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute metrics set :: EU FPU0 Pipe Active */
#define cflgt3__async_compute__fpu0_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute metrics set :: VS FPU0 Pipe Active */
#define cflgt3__async_compute__vs_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute metrics set :: PS FPU0 Pipe Active */
#define cflgt3__async_compute__ps_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute metrics set :: CS FPU0 Pipe Active */
#define cflgt3__async_compute__cs_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute metrics set :: EU FPU1 Pipe Active */
#define cflgt3__async_compute__fpu1_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute metrics set :: VS FPU1 Pipe Active */
#define cflgt3__async_compute__vs_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute metrics set :: PS FPU1 Pipe Active */
#define cflgt3__async_compute__ps_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute metrics set :: CS FPU1 Pipe Active */
#define cflgt3__async_compute__cs_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute metrics set :: EU Thread Occupancy */
#define cflgt3__async_compute__eu_thread_occupancy__read \
   sklgt2__ff_bottlenecks__eu_thread_occupancy__read

/* AsyncCompute metrics set :: EU Active */
#define cflgt3__async_compute__eu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute metrics set :: EU Stall */
#define cflgt3__async_compute__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define bxt__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define bxt__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define bxt__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define bxt__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define bxt__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define bxt__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define bxt__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define bxt__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define bxt__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define bxt__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define bxt__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define bxt__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define bxt__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define bxt__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define bxt__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define bxt__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define bxt__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define bxt__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define bxt__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define bxt__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define bxt__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define bxt__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define bxt__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define bxt__render_basic__samplers_busy__read \
   bdw__render_basic__samplers_busy__read

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define bxt__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
#define bxt__render_basic__sampler1_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define bxt__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define bxt__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define bxt__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define bxt__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define bxt__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define bxt__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define bxt__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define bxt__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define bxt__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
#define bxt__render_basic__sampler_l1_misses__read \
   sklgt2__render_basic__sampler_l1_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define bxt__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define bxt__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define bxt__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define bxt__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define bxt__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define bxt__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
#define bxt__render_basic__l3_lookups__read \
   sklgt2__render_basic__l3_lookups__read

/* Render Metrics Basic set :: L3 Misses */
#define bxt__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define bxt__render_basic__l3_sampler_throughput__read \
   sklgt2__render_basic__l3_sampler_throughput__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define bxt__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define bxt__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define bxt__render_basic__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define bxt__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define bxt__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define bxt__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define bxt__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define bxt__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define bxt__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define bxt__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define bxt__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define bxt__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define bxt__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define bxt__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define bxt__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define bxt__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define bxt__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define bxt__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define bxt__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define bxt__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define bxt__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define bxt__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define bxt__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define bxt__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define bxt__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define bxt__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define bxt__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define bxt__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define bxt__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define bxt__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define bxt__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define bxt__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define bxt__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define bxt__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define bxt__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define bxt__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define bxt__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define bxt__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define bxt__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define bxt__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define bxt__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define bxt__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define bxt__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define bxt__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define bxt__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define bxt__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define bxt__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define bxt__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define bxt__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define bxt__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define bxt__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define bxt__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define bxt__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define bxt__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define bxt__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define bxt__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define bxt__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define bxt__compute_basic__typed_bytes_read__read \
   hsw__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define bxt__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
static uint64_t
bxt__compute_basic__typed_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ B 4 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp4 = tmp2 * tmp3;

   return tmp4;
}

/* Compute Metrics Basic set :: Typed Bytes Written */
#define bxt__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define bxt__compute_basic__untyped_bytes_read__read \
   hsw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define bxt__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
static uint64_t
bxt__compute_basic__untyped_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ C 2 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64;
   uint64_t tmp4 = tmp2 * tmp3;

   return tmp4;
}

/* Compute Metrics Basic set :: Untyped Writes */
#define bxt__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define bxt__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define bxt__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define bxt__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define bxt__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define bxt__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define bxt__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define bxt__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define bxt__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define bxt__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define bxt__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define bxt__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define bxt__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define bxt__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define bxt__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define bxt__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define bxt__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define bxt__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define bxt__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define bxt__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define bxt__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define bxt__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define bxt__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define bxt__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define bxt__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define bxt__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define bxt__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define bxt__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define bxt__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define bxt__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define bxt__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define bxt__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define bxt__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define bxt__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define bxt__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define bxt__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define bxt__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define bxt__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define bxt__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define bxt__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define bxt__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define bxt__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define bxt__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define bxt__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define bxt__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define bxt__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define bxt__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define bxt__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define bxt__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define bxt__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define bxt__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define bxt__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory Reads Distribution metric set :: GPU Time Elapsed */
#define bxt__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metric set :: GPU Core Clocks */
#define bxt__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metric set :: AVG GPU Core Frequency */
#define bxt__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metric set :: AVG GPU Core Frequency */
#define bxt__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metric set :: GPU Busy */
#define bxt__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metric set :: VS Threads Dispatched */
#define bxt__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metric set :: HS Threads Dispatched */
#define bxt__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metric set :: DS Threads Dispatched */
#define bxt__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metric set :: GS Threads Dispatched */
#define bxt__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metric set :: FS Threads Dispatched */
#define bxt__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metric set :: CS Threads Dispatched */
#define bxt__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metric set :: EU Active */
#define bxt__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metric set :: EU Stall */
#define bxt__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metric set :: Rasterized Pixels */
#define bxt__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metric set :: Early Hi-Depth Test Fails */
#define bxt__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metric set :: Early Depth Test Fails */
#define bxt__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metric set :: Samples Killed in FS */
#define bxt__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metric set :: Pixels Failing Tests */
#define bxt__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metric set :: Samples Written */
#define bxt__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metric set :: Samples Blended */
#define bxt__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metric set :: Sampler Texels */
#define bxt__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metric set :: Sampler Texels Misses */
#define bxt__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metric set :: SLM Bytes Read */
#define bxt__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metric set :: SLM Bytes Read */
#define bxt__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metric set :: SLM Bytes Written */
#define bxt__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metric set :: SLM Bytes Written */
#define bxt__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metric set :: Shader Memory Accesses */
#define bxt__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metric set :: Shader Atomic Memory Accesses */
#define bxt__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metric set :: Shader Barrier Messages */
#define bxt__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metric set :: GtiCmdStreamerMemoryReads */
#define bxt__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metric set :: GtiRsMemoryReads */
#define bxt__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metric set :: GtiVfMemoryReads */
#define bxt__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metric set :: GtiRccMemoryReads */
#define bxt__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metric set :: GtiMscMemoryReads */
#define bxt__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metric set :: GtiHizMemoryReads */
#define bxt__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metric set :: GtiStcMemoryReads */
#define bxt__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metric set :: GtiRczMemoryReads */
#define bxt__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metric set :: GtiMemoryReads */
#define bxt__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metric set :: GtiL3Bank0Reads */
#define bxt__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metric set :: GtiL3Bank1Reads */
#define bxt__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metric set :: GtiL3Bank2Reads */
#define bxt__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metric set :: GtiL3Bank3Reads */
#define bxt__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metric set :: GtiL3Reads */
#define bxt__memory_reads__gti_l3_reads__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Reads Distribution metric set :: GtiRingAccesses */
#define bxt__memory_reads__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Memory Writes Distribution metric set :: GPU Time Elapsed */
#define bxt__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metric set :: GPU Core Clocks */
#define bxt__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metric set :: AVG GPU Core Frequency */
#define bxt__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metric set :: AVG GPU Core Frequency */
#define bxt__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metric set :: GPU Busy */
#define bxt__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metric set :: VS Threads Dispatched */
#define bxt__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metric set :: HS Threads Dispatched */
#define bxt__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metric set :: DS Threads Dispatched */
#define bxt__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metric set :: GS Threads Dispatched */
#define bxt__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metric set :: FS Threads Dispatched */
#define bxt__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metric set :: CS Threads Dispatched */
#define bxt__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metric set :: EU Active */
#define bxt__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metric set :: EU Stall */
#define bxt__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metric set :: Rasterized Pixels */
#define bxt__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metric set :: Early Hi-Depth Test Fails */
#define bxt__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metric set :: Early Depth Test Fails */
#define bxt__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metric set :: Samples Killed in FS */
#define bxt__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metric set :: Pixels Failing Tests */
#define bxt__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metric set :: Samples Written */
#define bxt__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metric set :: Samples Blended */
#define bxt__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metric set :: Sampler Texels */
#define bxt__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metric set :: Sampler Texels Misses */
#define bxt__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metric set :: SLM Bytes Read */
#define bxt__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metric set :: SLM Bytes Read */
#define bxt__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metric set :: SLM Bytes Written */
#define bxt__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metric set :: SLM Bytes Written */
#define bxt__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metric set :: Shader Memory Accesses */
#define bxt__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metric set :: Shader Atomic Memory Accesses */
#define bxt__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metric set :: L3 Shader Throughput */
#define bxt__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metric set :: L3 Shader Throughput */
#define bxt__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Memory Writes Distribution metric set :: Shader Barrier Messages */
#define bxt__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metric set :: GtiCmdStreamerMemoryWrites */
#define bxt__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metric set :: GtiSoMemoryWrites */
#define bxt__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metric set :: GtiRccMemoryWrites */
#define bxt__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metric set :: GtiMscMemoryWrites */
#define bxt__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metric set :: GtiHizMemoryWrites */
#define bxt__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metric set :: GtiStcMemoryWrites */
#define bxt__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metric set :: GtiRczMemoryWrites */
#define bxt__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metric set :: GtiMemoryWrites */
#define bxt__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metric set :: GtiL3Bank0Writes */
#define bxt__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metric set :: GtiL3Bank1Writes */
#define bxt__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metric set :: GtiL3Bank2Writes */
#define bxt__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metric set :: GtiL3Bank3Writes */
#define bxt__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metric set :: GtiL3Writes */
#define bxt__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metric set :: GtiRingAccesses */
#define bxt__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended metric set :: GPU Time Elapsed */
#define bxt__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended metric set :: GPU Core Clocks */
#define bxt__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended metric set :: AVG GPU Core Frequency */
#define bxt__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended metric set :: AVG GPU Core Frequency */
#define bxt__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended metric set :: CS Threads Dispatched */
#define bxt__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended metric set :: EU Active */
#define bxt__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended metric set :: EU Stall */
#define bxt__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended metric set :: EU Both FPU Pipes Active */
#define bxt__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended metric set :: EU FPU0 Pipe Active */
#define bxt__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended metric set :: EU FPU1 Pipe Active */
#define bxt__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended metric set :: EU AVG IPC Rate */
#define bxt__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended metric set :: EU AVG IPC Rate */
#define bxt__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended metric set :: EU Send Pipe Active */
#define bxt__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended metric set :: EU Thread Occupancy */
#define bxt__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended metric set :: Sampler Texels */
#define bxt__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended metric set :: Sampler Texels Misses */
#define bxt__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended metric set :: SLM Bytes Read */
#define bxt__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended metric set :: SLM Bytes Read */
#define bxt__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended metric set :: SLM Bytes Written */
#define bxt__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended metric set :: SLM Bytes Written */
#define bxt__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended metric set :: Shader Memory Accesses */
#define bxt__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended metric set :: Shader Atomic Memory Accesses */
#define bxt__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended metric set :: L3 Shader Throughput */
#define bxt__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended metric set :: L3 Shader Throughput */
#define bxt__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Extended metric set :: Shader Barrier Messages */
#define bxt__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended metric set :: EuUntypedReads0 */
#define bxt__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended metric set :: EuTypedReads0 */
#define bxt__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended metric set :: EuUntypedWrites0 */
#define bxt__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended metric set :: EuTypedWrites0 */
#define bxt__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended metric set :: EuUntypedAtomics0 */
#define bxt__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended metric set :: EuTypedAtomics0 */
#define bxt__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended metric set :: EuA64UntypedReads0 */
#define bxt__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended metric set :: EuA64UntypedWrites0 */
#define bxt__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended metric set :: Typed Reads 0 */
#define bxt__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended metric set :: Typed Writes 0 */
#define bxt__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended metric set :: Untyped Reads 0 */
#define bxt__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended metric set :: Untyped Writes 0 */
#define bxt__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended metric set :: Typed Atomics 0 */
#define bxt__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended metric set :: TypedReadsPerCacheLine */
#define bxt__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended metric set :: TypedWritesPerCacheLine */
#define bxt__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended metric set :: UntypedReadsPerCacheLine */
#define bxt__compute_extended__untyped_reads_per_cache_line__read \
   bdw__compute_extended__untyped_reads_per_cache_line__read

/* Compute Metrics Extended metric set :: UntypedWritesPerCacheLine */
#define bxt__compute_extended__untyped_writes_per_cache_line__read \
   bdw__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics Extended metric set :: TypedAtomicsPerCacheLine */
#define bxt__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache metric set :: GPU Time Elapsed */
#define bxt__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache metric set :: GPU Core Clocks */
#define bxt__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache metric set :: AVG GPU Core Frequency */
#define bxt__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache metric set :: AVG GPU Core Frequency */
#define bxt__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache metric set :: GPU Busy */
#define bxt__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache metric set :: VS Threads Dispatched */
#define bxt__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metric set :: HS Threads Dispatched */
#define bxt__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache metric set :: DS Threads Dispatched */
#define bxt__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache metric set :: GS Threads Dispatched */
#define bxt__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metric set :: FS Threads Dispatched */
#define bxt__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache metric set :: CS Threads Dispatched */
#define bxt__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache metric set :: EU Active */
#define bxt__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache metric set :: EU Stall */
#define bxt__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache metric set :: EU Both FPU Pipes Active */
#define bxt__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU0 Pipe Active */
#define bxt__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU1 Pipe Active */
#define bxt__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache metric set :: EU AVG IPC Rate */
#define bxt__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache metric set :: EU AVG IPC Rate */
#define bxt__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache metric set :: EU Send Pipe Active */
#define bxt__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU0 Hybrid Instruction */
#define bxt__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache metric set :: EU FPU1 Hybrid Instruction */
#define bxt__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache metric set :: EU FPU0 Ternary Instruction */
#define bxt__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU1 Ternary Instruction */
#define bxt__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU0 Binary Instruction */
#define bxt__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU1 Binary Instruction */
#define bxt__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache metric set :: EU FPU0 Move Instruction */
#define bxt__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache metric set :: EU FPU1 Move Instruction */
#define bxt__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache metric set :: Rasterized Pixels */
#define bxt__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache metric set :: Early Hi-Depth Test Fails */
#define bxt__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache metric set :: Early Depth Test Fails */
#define bxt__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metric set :: Samples Killed in FS */
#define bxt__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache metric set :: Pixels Failing Tests */
#define bxt__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache metric set :: Samples Written */
#define bxt__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache metric set :: Samples Blended */
#define bxt__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache metric set :: Sampler Accesses */
#define bxt__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache metric set :: Sampler Texels */
#define bxt__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache metric set :: Sampler Texels Misses */
#define bxt__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache metric set :: SLM Bytes Read */
#define bxt__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache metric set :: SLM Bytes Read */
#define bxt__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metric set :: SLM Bytes Written */
#define bxt__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache metric set :: SLM Bytes Written */
#define bxt__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metric set :: Shader Memory Accesses */
#define bxt__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache metric set :: Shader Atomic Memory Accesses */
#define bxt__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache metric set :: L3 Accesses */
#define bxt__compute_l3_cache__l3_accesses__read \
   sklgt2__compute_l3_cache__l3_accesses__read

/* Compute Metrics L3 Cache metric set :: L3 Misses */
#define bxt__compute_l3_cache__l3_misses__read \
   bdw__compute_l3_cache__l3_misses__read

/* Compute Metrics L3 Cache metric set :: L3 Sampler Throughput */
#define bxt__compute_l3_cache__l3_sampler_throughput__read \
   chv__render_basic__l3_sampler_throughput__read

/* Compute Metrics L3 Cache metric set :: L3 Sampler Throughput */
#define bxt__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metric set :: L3 Shader Throughput */
#define bxt__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache metric set :: L3 Shader Throughput */
#define bxt__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metric set :: L3 Total Throughput */
#define bxt__compute_l3_cache__l3_total_throughput__read \
   sklgt2__compute_l3_cache__l3_total_throughput__read

/* Compute Metrics L3 Cache metric set :: L3 Total Throughput */
#define bxt__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metric set :: Shader Barrier Messages */
#define bxt__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metric set :: L3 Bank 00 Accesses */
#define bxt__compute_l3_cache__l3_bank00_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache metric set :: L3 Bank 01 Accesses */
#define bxt__compute_l3_cache__l3_bank01_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache metric set :: L3 Bank 02 Accesses */
#define bxt__compute_l3_cache__l3_bank02_accesses__read \
   bdw__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache metric set :: L3 Bank 03 Accesses */
#define bxt__compute_l3_cache__l3_bank03_accesses__read \
   bdw__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache metric set :: L3 Bank 00 IC Accesses */
#define bxt__compute_l3_cache__l3_bank00_ic_accesses__read \
   bdw__compute_l3_cache__l3_bank00_ic_accesses__read

/* Compute Metrics L3 Cache metric set :: L3 Bank 00 IC Hits */
#define bxt__compute_l3_cache__l3_bank00_ic_hits__read \
   bdw__compute_l3_cache__l3_bank00_ic_hits__read

/* Compute Metrics L3 Cache metric set :: GTI L3 Throughput */
#define bxt__compute_l3_cache__gti_l3_throughput__read \
   bdw__compute_l3_cache__gti_l3_throughput__read

/* Compute Metrics L3 Cache metric set :: GTI L3 Throughput */
#define bxt__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metric set :: GTI Read Throughput */
#define bxt__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache metric set :: GTI Read Throughput */
#define bxt__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache metric set :: GTI Write Throughput */
#define bxt__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache metric set :: GTI Write Throughput */
#define bxt__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define bxt__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define bxt__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define bxt__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define bxt__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define bxt__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define bxt__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define bxt__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define bxt__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define bxt__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define bxt__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define bxt__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define bxt__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define bxt__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define bxt__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define bxt__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define bxt__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define bxt__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define bxt__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define bxt__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define bxt__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define bxt__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define bxt__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define bxt__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define bxt__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define bxt__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define bxt__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define bxt__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define bxt__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define bxt__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define bxt__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define bxt__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define bxt__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define bxt__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define bxt__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define bxt__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define bxt__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define bxt__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define bxt__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define bxt__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define bxt__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define bxt__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define bxt__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define bxt__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define bxt__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define bxt__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define bxt__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define bxt__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define bxt__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define bxt__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define bxt__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define bxt__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define bxt__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define bxt__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define bxt__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define bxt__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define bxt__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define bxt__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define bxt__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define bxt__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define bxt__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define bxt__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define bxt__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define bxt__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define bxt__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define bxt__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define bxt__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define bxt__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define bxt__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define bxt__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define bxt__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define bxt__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define bxt__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define bxt__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define bxt__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define bxt__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define bxt__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define bxt__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define bxt__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define bxt__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define bxt__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define bxt__l3_1__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define bxt__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */
#define bxt__l3_1__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */
#define bxt__l3_1__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define bxt__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define bxt__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define bxt__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define bxt__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define bxt__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define bxt__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define bxt__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define bxt__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define bxt__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define bxt__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define bxt__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define bxt__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define bxt__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define bxt__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define bxt__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define bxt__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define bxt__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define bxt__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define bxt__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define bxt__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define bxt__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define bxt__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define bxt__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define bxt__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define bxt__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define bxt__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define bxt__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define bxt__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define bxt__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define bxt__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define bxt__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define bxt__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define bxt__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define bxt__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define bxt__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define bxt__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define bxt__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define bxt__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define bxt__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define bxt__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define bxt__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define bxt__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define bxt__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define bxt__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define bxt__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define bxt__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler :: GPU Time Elapsed */
#define bxt__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler :: GPU Core Clocks */
#define bxt__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define bxt__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define bxt__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler :: GPU Busy */
#define bxt__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler :: VS Threads Dispatched */
#define bxt__sampler__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler :: HS Threads Dispatched */
#define bxt__sampler__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler :: DS Threads Dispatched */
#define bxt__sampler__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler :: GS Threads Dispatched */
#define bxt__sampler__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler :: FS Threads Dispatched */
#define bxt__sampler__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler :: CS Threads Dispatched */
#define bxt__sampler__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler :: EU Active */
#define bxt__sampler__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler :: EU Stall */
#define bxt__sampler__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler :: EU Both FPU Pipes Active */
#define bxt__sampler__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler :: VS FPU0 Pipe Active */
#define bxt__sampler__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler :: VS FPU1 Pipe Active */
#define bxt__sampler__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler :: VS Send Pipe Active */
#define bxt__sampler__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler :: PS FPU0 Pipe Active */
#define bxt__sampler__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler :: PS FPU1 Pipe Active */
#define bxt__sampler__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler :: PS Send Pipeline Active */
#define bxt__sampler__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler :: FS Both FPU Active */
#define bxt__sampler__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler :: Rasterized Pixels */
#define bxt__sampler__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler :: Early Hi-Depth Test Fails */
#define bxt__sampler__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler :: Early Depth Test Fails */
#define bxt__sampler__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Samples Killed in FS */
#define bxt__sampler__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler :: Pixels Failing Tests */
#define bxt__sampler__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler :: Samples Written */
#define bxt__sampler__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler :: Samples Blended */
#define bxt__sampler__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler :: Sampler Texels */
#define bxt__sampler__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler :: Sampler Texels Misses */
#define bxt__sampler__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler :: SLM Bytes Read */
#define bxt__sampler__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler :: SLM Bytes Read */
#define bxt__sampler__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: SLM Bytes Written */
#define bxt__sampler__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler :: SLM Bytes Written */
#define bxt__sampler__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Memory Accesses */
#define bxt__sampler__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler :: Shader Atomic Memory Accesses */
#define bxt__sampler__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler :: L3 Shader Throughput */
#define bxt__sampler__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler :: L3 Shader Throughput */
#define bxt__sampler__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set Sampler :: Shader Barrier Messages */
#define bxt__sampler__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Slice0 Subslice1 Input Available */
#define bxt__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler :: Slice0 Subslice2 Input Available */
#define bxt__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler :: Slice0 Subslice0 Input Available */
#define bxt__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */
#define bxt__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */
#define bxt__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */
#define bxt__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler :: SQ is full */
#define bxt__sampler__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define bxt__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define bxt__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define bxt__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define bxt__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define bxt__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define bxt__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define bxt__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define bxt__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define bxt__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define bxt__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define bxt__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define bxt__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define bxt__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define bxt__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define bxt__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define bxt__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define bxt__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define bxt__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define bxt__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define bxt__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define bxt__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define bxt__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define bxt__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define bxt__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define bxt__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define bxt__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define bxt__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define bxt__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define bxt__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define bxt__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define bxt__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define bxt__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define bxt__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define bxt__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define bxt__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define bxt__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define bxt__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define bxt__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define bxt__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define bxt__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define bxt__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define bxt__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define bxt__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define bxt__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define bxt__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: SQ is full */
#define bxt__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define bxt__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define bxt__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define bxt__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define bxt__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define bxt__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define bxt__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define bxt__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define bxt__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define bxt__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define bxt__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define bxt__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define bxt__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define bxt__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define bxt__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define bxt__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define bxt__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define bxt__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define bxt__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define bxt__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define bxt__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define bxt__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define bxt__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define bxt__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define bxt__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define bxt__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define bxt__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define bxt__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define bxt__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define bxt__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define bxt__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define bxt__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define bxt__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define bxt__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define bxt__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define bxt__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define bxt__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define bxt__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define bxt__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define bxt__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define bxt__tdl_2__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define bxt__tdl_2__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define bxt__tdl_2__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define bxt__tdl_2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define bxt__tdl_2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define bxt__tdl_2__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define bxt__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define bxt__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define bxt__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define bxt__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define bxt__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define bxt__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extra set :: EU FPU1 Pipe Active including Ext Math */
#define bxt__compute_extra__fpu1_active_adjusted__read \
   sklgt2__compute_extra__fpu1_active_adjusted__read

/* Gpu Rings Busyness metrics set :: GPU Time Elapsed */
#define bxt__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness metrics set :: GPU Core Clocks */
#define bxt__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness metrics set :: AVG GPU Core Frequency */
#define bxt__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness metrics set :: AVG GPU Core Frequency */
#define bxt__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness metrics set :: Render Ring Busy */
#define bxt__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness metrics set :: Vdbox0 Ring Busy */
#define bxt__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness metrics set :: Vebox Ring Busy */
#define bxt__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness metrics set :: Blitter Ring Busy */
#define bxt__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness metrics set :: AnyRingBusy */
#define bxt__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* MDAPI testing set :: GPU Time Elapsed */
#define bxt__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define bxt__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define bxt__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define bxt__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define bxt__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define bxt__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define bxt__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define bxt__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define bxt__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define bxt__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define bxt__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define bxt__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define bxt__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define bxt__pma__stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define bxt__pma__stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define bxt__pma__stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define bxt__pma__stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: STC PMA stall */
#define bxt__pma__stall__stc_pma_stall__read \
   sklgt2__pma__stall__stc_pma_stall__read

/* AsyncCompute metrics set :: GPU Time Elapsed */
#define bxt__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute metrics set :: GPU Core Clocks */
#define bxt__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute metrics set :: AVG GPU Core Frequency */
#define bxt__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute metrics set :: AVG GPU Core Frequency */
#define bxt__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute metrics set :: GPU Busy */
#define bxt__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute metrics set :: VS Threads Dispatched */
#define bxt__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute metrics set :: HS Threads Dispatched */
#define bxt__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute metrics set :: DS Threads Dispatched */
#define bxt__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute metrics set :: GS Threads Dispatched */
#define bxt__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute metrics set :: FS Threads Dispatched */
#define bxt__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute metrics set :: CS Threads Dispatched */
#define bxt__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute metrics set :: EU FPU0 Pipe Active */
#define bxt__async_compute__fpu0_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute metrics set :: VS FPU0 Pipe Active */
#define bxt__async_compute__vs_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute metrics set :: PS FPU0 Pipe Active */
#define bxt__async_compute__ps_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute metrics set :: CS FPU0 Pipe Active */
#define bxt__async_compute__cs_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute metrics set :: EU FPU1 Pipe Active */
#define bxt__async_compute__fpu1_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute metrics set :: VS FPU1 Pipe Active */
#define bxt__async_compute__vs_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute metrics set :: PS FPU1 Pipe Active */
#define bxt__async_compute__ps_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute metrics set :: CS FPU1 Pipe Active */
#define bxt__async_compute__cs_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute metrics set :: EU Thread Occupancy */
#define bxt__async_compute__eu_thread_occupancy__read \
   sklgt2__ff_bottlenecks__eu_thread_occupancy__read

/* AsyncCompute metrics set :: EU Active */
#define bxt__async_compute__eu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute metrics set :: EU Stall */
#define bxt__async_compute__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define glk__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define glk__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define glk__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define glk__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define glk__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define glk__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define glk__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define glk__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define glk__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define glk__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define glk__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define glk__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define glk__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define glk__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define glk__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define glk__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define glk__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define glk__render_basic__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define glk__render_basic__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define glk__render_basic__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Render Metrics Basic set :: FS Both FPU Active */
#define glk__render_basic__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Render Metrics Basic set :: Sampler 0 Busy */
#define glk__render_basic__sampler0_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler 1 Busy */
#define glk__render_basic__sampler1_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define glk__render_basic__samplers_busy__read \
   bdw__render_basic__samplers_busy__read

/* Render Metrics Basic set :: Sampler 0 Bottleneck */
#define glk__render_basic__sampler0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics Basic set :: Sampler 1 Bottleneck */
#define glk__render_basic__sampler1_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define glk__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define glk__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define glk__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define glk__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define glk__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define glk__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define glk__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define glk__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define glk__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
#define glk__render_basic__sampler_l1_misses__read \
   sklgt2__render_basic__sampler_l1_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define glk__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define glk__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define glk__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define glk__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define glk__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define glk__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Lookup Accesses w/o IC */
#define glk__render_basic__l3_lookups__read \
   sklgt2__render_basic__l3_lookups__read

/* Render Metrics Basic set :: L3 Misses */
#define glk__render_basic__l3_misses__read \
   hsw__compute_extended__typed_atomics0__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define glk__render_basic__l3_sampler_throughput__read \
   sklgt2__render_basic__l3_sampler_throughput__read

/* Render Metrics Basic set :: L3 Sampler Throughput */
#define glk__render_basic__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: L3 Shader Throughput */
#define glk__render_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define glk__render_basic__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define glk__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define glk__render_basic__gti_vf_throughput__read \
   bdw__render_basic__gti_vf_throughput__read

/* Render Metrics Basic set :: GTI Fixed Pipe Throughput */
#define glk__render_basic__gti_vf_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Depth Throughput */
#define glk__render_basic__gti_depth_throughput__read \
   bdw__render_basic__gti_depth_throughput__read

/* Render Metrics Basic set :: GTI Depth Throughput */
#define glk__render_basic__gti_depth_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI RCC Throughput */
#define glk__render_basic__gti_rcc_throughput__read \
   bdw__render_basic__gti_rcc_throughput__read

/* Render Metrics Basic set :: GTI RCC Throughput */
#define glk__render_basic__gti_rcc_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI L3 Throughput */
#define glk__render_basic__gti_l3_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Render Metrics Basic set :: GTI L3 Throughput */
#define glk__render_basic__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define glk__render_basic__gti_hdc_lookups_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Render Metrics Basic set :: GTI HDC TLB Lookup Throughput */
#define glk__render_basic__gti_hdc_lookups_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics Basic set :: GTI Read Throughput */
#define glk__render_basic__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define glk__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define glk__render_basic__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define glk__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define glk__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define glk__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define glk__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define glk__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define glk__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define glk__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define glk__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define glk__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define glk__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define glk__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define glk__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define glk__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define glk__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define glk__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define glk__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define glk__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define glk__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define glk__compute_basic__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define glk__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define glk__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define glk__compute_basic__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define glk__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define glk__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define glk__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define glk__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define glk__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define glk__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define glk__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define glk__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define glk__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define glk__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define glk__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define glk__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define glk__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define glk__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define glk__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define glk__compute_basic__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define glk__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define glk__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define glk__compute_basic__typed_bytes_read__read \
   hsw__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define glk__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
#define glk__compute_basic__typed_bytes_written__read \
   bxt__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Typed Bytes Written */
#define glk__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define glk__compute_basic__untyped_bytes_read__read \
   hsw__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define glk__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define glk__compute_basic__untyped_bytes_written__read \
   bxt__compute_basic__untyped_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define glk__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
#define glk__compute_basic__gti_read_throughput__read \
   hsw__render_basic__gti_l3_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define glk__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define glk__compute_basic__gti_write_throughput__read \
   bdw__render_basic__gti_hdc_lookups_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define glk__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define glk__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define glk__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define glk__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define glk__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define glk__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define glk__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define glk__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define glk__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define glk__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define glk__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define glk__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define glk__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define glk__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define glk__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define glk__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define glk__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define glk__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define glk__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define glk__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define glk__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define glk__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define glk__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define glk__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define glk__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define glk__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define glk__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define glk__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define glk__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define glk__render_pipe_profile__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define glk__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define glk__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define glk__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define glk__render_pipe_profile__vs_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define glk__render_pipe_profile__hs_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define glk__render_pipe_profile__ds_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define glk__render_pipe_profile__gs_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define glk__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define glk__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define glk__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define glk__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define glk__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define glk__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define glk__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define glk__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define glk__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define glk__render_pipe_profile__cl_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define glk__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory Reads Distribution metrics set :: GPU Time Elapsed */
#define glk__memory_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Reads Distribution metrics set :: GPU Core Clocks */
#define glk__memory_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define glk__memory_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Reads Distribution metrics set :: AVG GPU Core Frequency */
#define glk__memory_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Reads Distribution metrics set :: GPU Busy */
#define glk__memory_reads__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Reads Distribution metrics set :: VS Threads Dispatched */
#define glk__memory_reads__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: HS Threads Dispatched */
#define glk__memory_reads__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Reads Distribution metrics set :: DS Threads Dispatched */
#define glk__memory_reads__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Reads Distribution metrics set :: GS Threads Dispatched */
#define glk__memory_reads__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Reads Distribution metrics set :: FS Threads Dispatched */
#define glk__memory_reads__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Reads Distribution metrics set :: CS Threads Dispatched */
#define glk__memory_reads__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Reads Distribution metrics set :: EU Active */
#define glk__memory_reads__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Reads Distribution metrics set :: EU Stall */
#define glk__memory_reads__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Reads Distribution metrics set :: Rasterized Pixels */
#define glk__memory_reads__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Reads Distribution metrics set :: Early Hi-Depth Test Fails */
#define glk__memory_reads__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Early Depth Test Fails */
#define glk__memory_reads__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: Samples Killed in FS */
#define glk__memory_reads__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Reads Distribution metrics set :: Pixels Failing Tests */
#define glk__memory_reads__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Reads Distribution metrics set :: Samples Written */
#define glk__memory_reads__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Reads Distribution metrics set :: Samples Blended */
#define glk__memory_reads__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Reads Distribution metrics set :: Sampler Texels */
#define glk__memory_reads__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Reads Distribution metrics set :: Sampler Texels Misses */
#define glk__memory_reads__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define glk__memory_reads__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Reads Distribution metrics set :: SLM Bytes Read */
#define glk__memory_reads__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define glk__memory_reads__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Reads Distribution metrics set :: SLM Bytes Written */
#define glk__memory_reads__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Reads Distribution metrics set :: Shader Memory Accesses */
#define glk__memory_reads__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Reads Distribution metrics set :: Shader Atomic Memory Accesses */
#define glk__memory_reads__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Reads Distribution metrics set :: Shader Barrier Messages */
#define glk__memory_reads__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Reads Distribution metrics set :: GtiCmdStreamerMemoryReads */
#define glk__memory_reads__gti_cmd_streamer_memory_reads__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Reads Distribution metrics set :: GtiRsMemoryReads */
#define glk__memory_reads__gti_rs_memory_reads__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Reads Distribution metrics set :: GtiVfMemoryReads */
#define glk__memory_reads__gti_vf_memory_reads__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Memory Reads Distribution metrics set :: GtiRccMemoryReads */
#define glk__memory_reads__gti_rcc_memory_reads__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiMscMemoryReads */
#define glk__memory_reads__gti_msc_memory_reads__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Reads Distribution metrics set :: GtiHizMemoryReads */
#define glk__memory_reads__gti_hiz_memory_reads__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiStcMemoryReads */
#define glk__memory_reads__gti_stc_memory_reads__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Reads Distribution metrics set :: GtiRczMemoryReads */
#define glk__memory_reads__gti_rcz_memory_reads__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Reads Distribution metrics set :: GtiMemoryReads */
#define glk__memory_reads__gti_memory_reads__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank0Reads */
#define glk__memory_reads__gti_l3_bank0_reads__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Reads Distribution metrics set :: GtiL3Bank1Reads */
#define glk__memory_reads__gti_l3_bank1_reads__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Reads Distribution metrics set :: GtiL3Bank2Reads */
#define glk__memory_reads__gti_l3_bank2_reads__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Reads Distribution metrics set :: GtiL3Bank3Reads */
#define glk__memory_reads__gti_l3_bank3_reads__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Reads Distribution metrics set :: GtiL3Reads */
#define glk__memory_reads__gti_l3_reads__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Reads Distribution metrics set :: GtiRingAccesses */
#define glk__memory_reads__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Memory Writes Distribution metrics set :: GPU Time Elapsed */
#define glk__memory_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory Writes Distribution metrics set :: GPU Core Clocks */
#define glk__memory_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define glk__memory_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory Writes Distribution metrics set :: AVG GPU Core Frequency */
#define glk__memory_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory Writes Distribution metrics set :: GPU Busy */
#define glk__memory_writes__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Memory Writes Distribution metrics set :: VS Threads Dispatched */
#define glk__memory_writes__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: HS Threads Dispatched */
#define glk__memory_writes__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Memory Writes Distribution metrics set :: DS Threads Dispatched */
#define glk__memory_writes__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Memory Writes Distribution metrics set :: GS Threads Dispatched */
#define glk__memory_writes__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Memory Writes Distribution metrics set :: FS Threads Dispatched */
#define glk__memory_writes__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Memory Writes Distribution metrics set :: CS Threads Dispatched */
#define glk__memory_writes__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Memory Writes Distribution metrics set :: EU Active */
#define glk__memory_writes__eu_active__read \
   bdw__render_basic__eu_active__read

/* Memory Writes Distribution metrics set :: EU Stall */
#define glk__memory_writes__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Memory Writes Distribution metrics set :: Rasterized Pixels */
#define glk__memory_writes__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Memory Writes Distribution metrics set :: Early Hi-Depth Test Fails */
#define glk__memory_writes__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Early Depth Test Fails */
#define glk__memory_writes__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: Samples Killed in FS */
#define glk__memory_writes__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Memory Writes Distribution metrics set :: Pixels Failing Tests */
#define glk__memory_writes__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Memory Writes Distribution metrics set :: Samples Written */
#define glk__memory_writes__samples_written__read \
   bdw__render_basic__samples_written__read

/* Memory Writes Distribution metrics set :: Samples Blended */
#define glk__memory_writes__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Memory Writes Distribution metrics set :: Sampler Texels */
#define glk__memory_writes__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Memory Writes Distribution metrics set :: Sampler Texels Misses */
#define glk__memory_writes__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define glk__memory_writes__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Memory Writes Distribution metrics set :: SLM Bytes Read */
#define glk__memory_writes__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define glk__memory_writes__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Memory Writes Distribution metrics set :: SLM Bytes Written */
#define glk__memory_writes__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Memory Writes Distribution metrics set :: Shader Memory Accesses */
#define glk__memory_writes__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Memory Writes Distribution metrics set :: Shader Atomic Memory Accesses */
#define glk__memory_writes__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define glk__memory_writes__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Memory Writes Distribution metrics set :: L3 Shader Throughput */
#define glk__memory_writes__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Memory Writes Distribution metrics set :: Shader Barrier Messages */
#define glk__memory_writes__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Memory Writes Distribution metrics set :: GtiCmdStreamerMemoryWrites */
#define glk__memory_writes__gti_cmd_streamer_memory_writes__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory Writes Distribution metrics set :: GtiSoMemoryWrites */
#define glk__memory_writes__gti_so_memory_writes__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Memory Writes Distribution metrics set :: GtiRccMemoryWrites */
#define glk__memory_writes__gti_rcc_memory_writes__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiMscMemoryWrites */
#define glk__memory_writes__gti_msc_memory_writes__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Memory Writes Distribution metrics set :: GtiHizMemoryWrites */
#define glk__memory_writes__gti_hiz_memory_writes__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiStcMemoryWrites */
#define glk__memory_writes__gti_stc_memory_writes__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Memory Writes Distribution metrics set :: GtiRczMemoryWrites */
#define glk__memory_writes__gti_rcz_memory_writes__read \
   hsw__compute_extended__gpu_clocks__read

/* Memory Writes Distribution metrics set :: GtiMemoryWrites */
#define glk__memory_writes__gti_memory_writes__read \
   hsw__compute_extended__typed_writes0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank0Writes */
#define glk__memory_writes__gti_l3_bank0_writes__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory Writes Distribution metrics set :: GtiL3Bank1Writes */
#define glk__memory_writes__gti_l3_bank1_writes__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory Writes Distribution metrics set :: GtiL3Bank2Writes */
#define glk__memory_writes__gti_l3_bank2_writes__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory Writes Distribution metrics set :: GtiL3Bank3Writes */
#define glk__memory_writes__gti_l3_bank3_writes__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory Writes Distribution metrics set :: GtiL3Writes */
#define glk__memory_writes__gti_l3_writes__read \
   bdw__memory_reads__gti_l3_reads__read

/* Memory Writes Distribution metrics set :: GtiRingAccesses */
#define glk__memory_writes__gti_ring_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics Extended set :: GPU Time Elapsed */
#define glk__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extended set :: GPU Core Clocks */
#define glk__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define glk__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extended set :: AVG GPU Core Frequency */
#define glk__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extended set :: CS Threads Dispatched */
#define glk__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Extended set :: EU Active */
#define glk__compute_extended__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Extended set :: EU Stall */
#define glk__compute_extended__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extended set :: EU Both FPU Pipes Active */
#define glk__compute_extended__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Extended set :: EU FPU0 Pipe Active */
#define glk__compute_extended__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Extended set :: EU FPU1 Pipe Active */
#define glk__compute_extended__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define glk__compute_extended__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Extended set :: EU AVG IPC Rate */
#define glk__compute_extended__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Extended set :: EU Send Pipe Active */
#define glk__compute_extended__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Extended set :: EU Thread Occupancy */
#define glk__compute_extended__eu_thread_occupancy__read \
   bdw__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Extended set :: Sampler Texels */
#define glk__compute_extended__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Extended set :: Sampler Texels Misses */
#define glk__compute_extended__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define glk__compute_extended__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Extended set :: SLM Bytes Read */
#define glk__compute_extended__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: SLM Bytes Written */
#define glk__compute_extended__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Extended set :: SLM Bytes Written */
#define glk__compute_extended__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Extended set :: Shader Memory Accesses */
#define glk__compute_extended__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Extended set :: Shader Atomic Memory Accesses */
#define glk__compute_extended__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define glk__compute_extended__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics Extended set :: L3 Shader Throughput */
#define glk__compute_extended__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Extended set :: Shader Barrier Messages */
#define glk__compute_extended__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Extended set :: EuUntypedReads0 */
#define glk__compute_extended__eu_untyped_reads0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Metrics Extended set :: EuTypedReads0 */
#define glk__compute_extended__eu_typed_reads0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Metrics Extended set :: EuUntypedWrites0 */
#define glk__compute_extended__eu_untyped_writes0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Compute Metrics Extended set :: EuTypedWrites0 */
#define glk__compute_extended__eu_typed_writes0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Metrics Extended set :: EuUntypedAtomics0 */
#define glk__compute_extended__eu_untyped_atomics0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Metrics Extended set :: EuTypedAtomics0 */
#define glk__compute_extended__eu_typed_atomics0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedReads0 */
#define glk__compute_extended__eu_a64_untyped_reads0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Compute Metrics Extended set :: EuA64UntypedWrites0 */
#define glk__compute_extended__eu_a64_untyped_writes0__read \
   hsw__compute_extended__gpu_clocks__read

/* Compute Metrics Extended set :: Typed Reads 0 */
#define glk__compute_extended__typed_reads0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extended set :: Typed Writes 0 */
#define glk__compute_extended__typed_writes0__read \
   hsw__compute_extended__typed_writes0__read

/* Compute Metrics Extended set :: Untyped Reads 0 */
#define glk__compute_extended__untyped_reads0__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Metrics Extended set :: Untyped Writes 0 */
#define glk__compute_extended__untyped_writes0__read \
   hsw__compute_extended__untyped_writes0__read

/* Compute Metrics Extended set :: Typed Atomics 0 */
#define glk__compute_extended__typed_atomics0__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Metrics Extended set :: TypedReadsPerCacheLine */
#define glk__compute_extended__typed_reads_per_cache_line__read \
   hsw__compute_extended__typed_reads_per_cache_line__read

/* Compute Metrics Extended set :: TypedWritesPerCacheLine */
#define glk__compute_extended__typed_writes_per_cache_line__read \
   hsw__compute_extended__typed_writes_per_cache_line__read

/* Compute Metrics Extended set :: UntypedReadsPerCacheLine */
#define glk__compute_extended__untyped_reads_per_cache_line__read \
   bdw__compute_extended__untyped_reads_per_cache_line__read

/* Compute Metrics Extended set :: UntypedWritesPerCacheLine */
#define glk__compute_extended__untyped_writes_per_cache_line__read \
   bdw__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics Extended set :: TypedAtomicsPerCacheLine */
#define glk__compute_extended__typed_atomics_per_cache_line__read \
   hsw__compute_extended__typed_atomics_per_cache_line__read

/* Compute Metrics L3 Cache set :: GPU Time Elapsed */
#define glk__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache set :: GPU Core Clocks */
#define glk__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define glk__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define glk__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache set :: GPU Busy */
#define glk__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache set :: VS Threads Dispatched */
#define glk__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: HS Threads Dispatched */
#define glk__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache set :: DS Threads Dispatched */
#define glk__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache set :: GS Threads Dispatched */
#define glk__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: FS Threads Dispatched */
#define glk__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache set :: CS Threads Dispatched */
#define glk__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache set :: EU Active */
#define glk__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache set :: EU Stall */
#define glk__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache set :: EU Both FPU Pipes Active */
#define glk__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Pipe Active */
#define glk__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Pipe Active */
#define glk__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define glk__compute_l3_cache__eu_avg_ipc_rate__read \
   bdw__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define glk__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache set :: EU Send Pipe Active */
#define glk__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Hybrid Instruction */
#define glk__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Hybrid Instruction */
#define glk__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU0 Ternary Instruction */
#define glk__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Ternary Instruction */
#define glk__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Binary Instruction */
#define glk__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Binary Instruction */
#define glk__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Move Instruction */
#define glk__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Move Instruction */
#define glk__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: Rasterized Pixels */
#define glk__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache set :: Early Hi-Depth Test Fails */
#define glk__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Early Depth Test Fails */
#define glk__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Samples Killed in FS */
#define glk__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache set :: Pixels Failing Tests */
#define glk__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache set :: Samples Written */
#define glk__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache set :: Samples Blended */
#define glk__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache set :: Sampler Accesses */
#define glk__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache set :: Sampler Texels */
#define glk__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache set :: Sampler Texels Misses */
#define glk__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define glk__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define glk__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define glk__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define glk__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: Shader Memory Accesses */
#define glk__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache set :: Shader Atomic Memory Accesses */
#define glk__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache set :: L3 Accesses */
#define glk__compute_l3_cache__l3_accesses__read \
   sklgt2__compute_l3_cache__l3_accesses__read

/* Compute Metrics L3 Cache set :: L3 Misses */
#define glk__compute_l3_cache__l3_misses__read \
   bdw__compute_l3_cache__l3_misses__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define glk__compute_l3_cache__l3_sampler_throughput__read \
   chv__render_basic__l3_sampler_throughput__read

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define glk__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define glk__compute_l3_cache__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define glk__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define glk__compute_l3_cache__l3_total_throughput__read \
   sklgt2__compute_l3_cache__l3_total_throughput__read

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define glk__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: Shader Barrier Messages */
#define glk__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 Accesses */
#define glk__compute_l3_cache__l3_bank00_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 01 Accesses */
#define glk__compute_l3_cache__l3_bank01_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 02 Accesses */
#define glk__compute_l3_cache__l3_bank02_accesses__read \
   bdw__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 03 Accesses */
#define glk__compute_l3_cache__l3_bank03_accesses__read \
   bdw__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Accesses */
#define glk__compute_l3_cache__l3_bank00_ic_accesses__read \
   bdw__compute_l3_cache__l3_bank00_ic_accesses__read

/* Compute Metrics L3 Cache set :: L3 Bank 00 IC Hits */
#define glk__compute_l3_cache__l3_bank00_ic_hits__read \
   bdw__compute_l3_cache__l3_bank00_ic_hits__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define glk__compute_l3_cache__gti_l3_throughput__read \
   bdw__compute_l3_cache__gti_l3_throughput__read

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define glk__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define glk__compute_l3_cache__gti_read_throughput__read \
   bdw__render_basic__gti_read_throughput__read

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define glk__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define glk__compute_l3_cache__gti_write_throughput__read \
   hsw__render_basic__gti_write_throughput__read

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define glk__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_write_throughput__max

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define glk__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define glk__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define glk__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define glk__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define glk__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define glk__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define glk__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define glk__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define glk__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define glk__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define glk__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define glk__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define glk__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define glk__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define glk__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define glk__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define glk__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define glk__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define glk__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define glk__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define glk__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define glk__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define glk__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define glk__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define glk__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define glk__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define glk__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define glk__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define glk__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define glk__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define glk__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define glk__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define glk__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define glk__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define glk__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define glk__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define glk__hdc_and_sf__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define glk__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define glk__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define glk__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */
#define glk__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */
#define glk__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: SQ is full */
#define glk__hdc_and_sf__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define glk__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define glk__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define glk__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define glk__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define glk__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define glk__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define glk__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define glk__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define glk__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define glk__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define glk__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define glk__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define glk__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define glk__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define glk__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define glk__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define glk__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define glk__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define glk__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define glk__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define glk__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define glk__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define glk__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define glk__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define glk__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define glk__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define glk__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define glk__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define glk__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define glk__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define glk__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define glk__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define glk__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define glk__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define glk__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define glk__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define glk__l3_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define glk__l3_1__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define glk__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */
#define glk__l3_1__l30_bank0_stalled__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */
#define glk__l3_1__l30_bank1_stalled__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define glk__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define glk__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define glk__l3_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define glk__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define glk__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define glk__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define glk__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define glk__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define glk__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define glk__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define glk__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define glk__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define glk__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define glk__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define glk__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define glk__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define glk__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define glk__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define glk__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define glk__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define glk__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define glk__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define glk__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define glk__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define glk__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define glk__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define glk__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define glk__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define glk__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define glk__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define glk__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define glk__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define glk__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define glk__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define glk__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define glk__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define glk__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define glk__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define glk__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define glk__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */
#define glk__rasterizer_and_pixel_backend__pixel_data0_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define glk__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */
#define glk__rasterizer_and_pixel_backend__ps_output0_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */
#define glk__rasterizer_and_pixel_backend__pixel_values0_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define glk__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define glk__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set Sampler :: GPU Time Elapsed */
#define glk__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler :: GPU Core Clocks */
#define glk__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define glk__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler :: AVG GPU Core Frequency */
#define glk__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler :: GPU Busy */
#define glk__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler :: VS Threads Dispatched */
#define glk__sampler__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler :: HS Threads Dispatched */
#define glk__sampler__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler :: DS Threads Dispatched */
#define glk__sampler__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler :: GS Threads Dispatched */
#define glk__sampler__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler :: FS Threads Dispatched */
#define glk__sampler__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler :: CS Threads Dispatched */
#define glk__sampler__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler :: EU Active */
#define glk__sampler__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler :: EU Stall */
#define glk__sampler__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler :: EU Both FPU Pipes Active */
#define glk__sampler__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler :: VS FPU0 Pipe Active */
#define glk__sampler__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler :: VS FPU1 Pipe Active */
#define glk__sampler__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler :: VS Send Pipe Active */
#define glk__sampler__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler :: PS FPU0 Pipe Active */
#define glk__sampler__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler :: PS FPU1 Pipe Active */
#define glk__sampler__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler :: PS Send Pipeline Active */
#define glk__sampler__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler :: FS Both FPU Active */
#define glk__sampler__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler :: Rasterized Pixels */
#define glk__sampler__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler :: Early Hi-Depth Test Fails */
#define glk__sampler__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler :: Early Depth Test Fails */
#define glk__sampler__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Samples Killed in FS */
#define glk__sampler__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler :: Pixels Failing Tests */
#define glk__sampler__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler :: Samples Written */
#define glk__sampler__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler :: Samples Blended */
#define glk__sampler__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler :: Sampler Texels */
#define glk__sampler__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler :: Sampler Texels Misses */
#define glk__sampler__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler :: SLM Bytes Read */
#define glk__sampler__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler :: SLM Bytes Read */
#define glk__sampler__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: SLM Bytes Written */
#define glk__sampler__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler :: SLM Bytes Written */
#define glk__sampler__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler :: Shader Memory Accesses */
#define glk__sampler__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler :: Shader Atomic Memory Accesses */
#define glk__sampler__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler :: L3 Shader Throughput */
#define glk__sampler__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set Sampler :: L3 Shader Throughput */
#define glk__sampler__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set Sampler :: Shader Barrier Messages */
#define glk__sampler__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler :: Slice0 Subslice1 Input Available */
#define glk__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler :: Slice0 Subslice2 Input Available */
#define glk__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler :: Slice0 Subslice0 Input Available */
#define glk__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */
#define glk__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */
#define glk__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */
#define glk__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler :: SQ is full */
#define glk__sampler__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define glk__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define glk__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define glk__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define glk__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define glk__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define glk__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define glk__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define glk__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define glk__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define glk__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define glk__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define glk__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define glk__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define glk__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define glk__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define glk__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define glk__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define glk__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define glk__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define glk__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define glk__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define glk__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define glk__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define glk__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define glk__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define glk__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define glk__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define glk__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define glk__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define glk__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define glk__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define glk__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define glk__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define glk__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define glk__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define glk__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define glk__tdl_1__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define glk__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define glk__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */
#define glk__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */
#define glk__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */
#define glk__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */
#define glk__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */
#define glk__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */
#define glk__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: SQ is full */
#define glk__tdl_1__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define glk__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define glk__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define glk__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define glk__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define glk__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define glk__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define glk__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define glk__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define glk__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define glk__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define glk__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define glk__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define glk__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define glk__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define glk__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define glk__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define glk__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define glk__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define glk__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define glk__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define glk__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define glk__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define glk__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define glk__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define glk__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define glk__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define glk__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define glk__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define glk__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define glk__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define glk__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define glk__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define glk__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define glk__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define glk__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define glk__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define glk__tdl_2__l3_shader_throughput__read \
   bdw__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define glk__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define glk__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */
#define glk__tdl_2__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */
#define glk__tdl_2__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */
#define glk__tdl_2__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */
#define glk__tdl_2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */
#define glk__tdl_2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */
#define glk__tdl_2__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_2 :: SQ is full */
#define glk__tdl_2__gt_request_queue_full__read \
   bdw__hdc_and_sf__gt_request_queue_full__read

/* Compute Metrics Extra set :: GPU Time Elapsed */
#define glk__compute_extra__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Extra set :: GPU Core Clocks */
#define glk__compute_extra__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define glk__compute_extra__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Extra set :: AVG GPU Core Frequency */
#define glk__compute_extra__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Extra set :: EU FPU1 Pipe Active */
#define glk__compute_extra__fpu1_active__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Extra set :: EU FPU1 Pipe Active including Ext Math */
#define glk__compute_extra__fpu1_active_adjusted__read \
   sklgt2__compute_extra__fpu1_active_adjusted__read

/* MDAPI testing set :: GPU Time Elapsed */
#define glk__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* MDAPI testing set :: GPU Core Clocks */
#define glk__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define glk__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* MDAPI testing set :: AVG GPU Core Frequency */
#define glk__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* MDAPI testing set :: TestCounter0 */
#define glk__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* MDAPI testing set :: TestCounter1 */
#define glk__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* MDAPI testing set :: TestCounter2 */
#define glk__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* MDAPI testing set :: TestCounter3 */
#define glk__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* MDAPI testing set :: TestCounter4 */
#define glk__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* MDAPI testing set :: TestCounter5 */
#define glk__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* MDAPI testing set :: TestCounter6 */
#define glk__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* MDAPI testing set :: TestCounter7 */
#define glk__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* MDAPI testing set :: TestCounter8 */
#define glk__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set PMA Stall :: GPU Time Elapsed */
#define glk__pma__stall__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set PMA Stall :: GPU Core Clocks */
#define glk__pma__stall__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define glk__pma__stall__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set PMA Stall :: AVG GPU Core Frequency */
#define glk__pma__stall__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set PMA Stall :: STC PMA stall */
#define glk__pma__stall__stc_pma_stall__read \
   sklgt2__pma__stall__stc_pma_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define icl__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define icl__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define icl__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define icl__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define icl__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define icl__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define icl__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define icl__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define icl__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define icl__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define icl__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define icl__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define icl__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define icl__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define icl__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define icl__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define icl__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define icl__render_basic__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define icl__render_basic__ps_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define icl__render_basic__ps_send_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: Sampler00 Busy */
#define icl__render_basic__sampler00_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics Basic set :: Samplers Busy */
#define icl__render_basic__samplers_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics Basic set :: Sampler00 Bottleneck */
#define icl__render_basic__sampler00_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define icl__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define icl__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define icl__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define icl__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define icl__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define icl__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define icl__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define icl__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define icl__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
static uint64_t
icl__render_basic__sampler_l1_misses__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ C 5 READ UADD 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 2;

   return tmp3;
}

/* Render Metrics Basic set :: SLM Bytes Read */
#define icl__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define icl__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define icl__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define icl__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define icl__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define icl__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Shader Throughput */
static uint64_t
icl__render_basic__l3_shader_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: $ShaderMemoryAccesses 64 UMUL */
   uint64_t tmp0 = icl__render_basic__shader_memory_accesses__read(perf, query, results) * 64;

   return tmp0;
}

/* Render Metrics Basic set :: L3 Shader Throughput */
#define icl__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define icl__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Read Throughput */
static uint64_t
icl__render_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  B 1 READ B 3 READ UADD B 4 READ UADD B 5 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 3];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 4];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 5];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = 64 * tmp6;

   return tmp7;
}

/* Render Metrics Basic set :: GTI Read Throughput */
#define icl__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
static uint64_t
icl__render_basic__gti_write_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  B 0 READ B 2 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 2];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = 64 * tmp2;

   return tmp3;
}

/* Render Metrics Basic set :: GTI Write Throughput */
#define icl__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define icl__render_basic__sampler_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define icl__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define icl__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define icl__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define icl__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define icl__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define icl__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define icl__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define icl__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define icl__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define icl__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define icl__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define icl__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define icl__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define icl__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define icl__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define icl__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
static float
icl__compute_basic__eu_avg_ipc_rate__read(UNUSED struct intel_perf_config *perf,
                                          const struct intel_perf_query_info *query,
                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: A 9 READ  A 10 READ  A 11 READ FADD  A 9 READ FSUB FDIV 1 FADD */
   uint64_t tmp0 = results->accumulator[query->a_offset + 9];
   uint64_t tmp1 = results->accumulator[query->a_offset + 10];
   uint64_t tmp2 = results->accumulator[query->a_offset + 11];
   double tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = results->accumulator[query->a_offset + 9];
   double tmp5 = tmp3 - tmp4;
   double tmp6 = tmp0;
   double tmp7 = tmp5;
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;
   double tmp9 = tmp8 + 1;

   return tmp9;
}

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define icl__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define icl__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
static float
icl__compute_basic__eu_thread_occupancy__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: 8 A 13 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 13];
   double tmp1 = 8 * tmp0;
   double tmp2 = tmp1;
   double tmp3 = perf->devinfo.num_thread_per_eu;
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;
   uint64_t tmp5 = tmp4;
   uint64_t tmp6 = perf->sys_vars.n_eus;
   uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0;
   uint64_t tmp8 = tmp7 * 100;
   double tmp9 = tmp8;
   double tmp10 = icl__compute_basic__gpu_core_clocks__read(perf, query, results);
   double tmp11 = tmp10 ? tmp9 / tmp10 : 0;

   return tmp11;
}

/* Compute Metrics Basic set :: Rasterized Pixels */
#define icl__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define icl__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define icl__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define icl__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define icl__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define icl__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define icl__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define icl__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define icl__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define icl__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define icl__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define icl__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define icl__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define icl__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define icl__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define icl__compute_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define icl__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define icl__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
static uint64_t
icl__compute_basic__typed_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ UADD $EuSubslicesTotalCount UMUL 32 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp4 = tmp3 * 32;

   return tmp4;
}

/* Compute Metrics Basic set :: Typed Bytes Read */
#define icl__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
static uint64_t
icl__compute_basic__typed_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ C 4 READ UADD $EuSubslicesTotalCount UMUL 32 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = results->accumulator[query->c_offset + 4];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp4 = tmp3 * 32;

   return tmp4;
}

/* Compute Metrics Basic set :: Typed Bytes Written */
#define icl__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
static uint64_t
icl__compute_basic__untyped_bytes_read__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ C 2 READ UADD $EuSubslicesTotalCount UMUL 32 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp4 = tmp3 * 32;

   return tmp4;
}

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define icl__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
static uint64_t
icl__compute_basic__untyped_bytes_written__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ C 0 READ UADD $EuSubslicesTotalCount UMUL 32 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 0];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp4 = tmp3 * 32;

   return tmp4;
}

/* Compute Metrics Basic set :: Untyped Writes */
#define icl__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Atomics Accesses */
static uint64_t
icl__compute_basic__typed_atomics__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ FADD 2 FDIV $EuSubslicesTotalCount FMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   double tmp6 = tmp5 * perf->sys_vars.n_eu_sub_slices;

   return tmp6;
}

/* Compute Metrics Basic set :: Typed Atomics Accesses */
#define icl__compute_basic__typed_atomics__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
static uint64_t
icl__compute_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  B 1 READ B 3 READ UADD B 6 READ UADD B 7 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 3];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 6];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 7];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = 64 * tmp6;

   return tmp7;
}

/* Compute Metrics Basic set :: GTI Read Throughput */
#define icl__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define icl__compute_basic__gti_write_throughput__read \
   icl__render_basic__gti_write_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define icl__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Extended metrics set :: GPU Time Elapsed */
#define icl__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Extended metrics set :: GPU Core Clocks */
#define icl__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Extended metrics set :: AVG GPU Core Frequency */
#define icl__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Extended metrics set :: AVG GPU Core Frequency */
#define icl__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Extended metrics set :: GPU Busy */
#define icl__compute_extended__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Extended metrics set :: CS Threads Dispatched */
#define icl__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Extended metrics set :: Typed Atomics 00 */
#define icl__compute_extended__typed_atomics00__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Compute Extended metrics set :: Typed Reads 00 */
#define icl__compute_extended__typed_reads00__read \
   hsw__memory_reads__llc_read_accesses__read

/* Compute Extended metrics set :: Typed Writes 00 */
#define icl__compute_extended__typed_writes00__read \
   hsw__memory_reads__gti_memory_reads__read

/* Compute Extended metrics set :: Untyped Reads 00 */
#define icl__compute_extended__untyped_reads00__read \
   hsw__compute_extended__typed_atomics0__read

/* Compute Extended metrics set :: Untyped Writes 00 */
#define icl__compute_extended__untyped_writes00__read \
   hsw__compute_extended__untyped_reads0__read

/* Compute Extended metrics set :: Eu Typed Reads 00 */
#define icl__compute_extended__eu_typed_reads00__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Compute Extended metrics set :: Eu Typed Writes 00 */
#define icl__compute_extended__eu_typed_writes00__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Compute Extended metrics set :: Eu Typed Atomics 00 */
#define icl__compute_extended__eu_typed_atomics00__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Compute Extended metrics set :: Eu A32 Untyped Reads 00 */
#define icl__compute_extended__eu_a32_untyped_reads00__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Compute Extended metrics set :: Eu A32 Untyped Writes 00 */
static uint64_t
icl__compute_extended__eu_a32_untyped_writes00__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 1 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Compute Extended metrics set :: Eu 64 Untyped Reads 00 */
static float
icl__compute_extended__eu_a64_untyped_reads00__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ C 1 READ FADD B 6 READ FADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 6];
   double tmp4 = tmp2 + tmp3;

   return tmp4;
}

/* Compute Extended metrics set :: Eu A64 Untyped Writes 00 */
#define icl__compute_extended__eu_a64_untyped_writes00__read \
   hsw__render_basic__gpu_core_clocks__read

/* Compute Extended metrics set :: TypedAtomicsPerCacheLine */
static float
icl__compute_extended__typed_atomics_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                          const struct intel_perf_query_info *query,
                                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuTypedAtomics00 $TypedAtomics00 FDIV */
   double tmp0 = icl__compute_extended__eu_typed_atomics00__read(perf, query, results);
   double tmp1 = icl__compute_extended__typed_atomics00__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Compute Extended metrics set :: TypedReadsPerCacheLine */
static float
icl__compute_extended__typed_reads_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuTypedReads00 $TypedReads00 FDIV */
   double tmp0 = icl__compute_extended__eu_typed_reads00__read(perf, query, results);
   double tmp1 = icl__compute_extended__typed_reads00__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Compute Extended metrics set :: TypedWritesPerCacheLine */
static float
icl__compute_extended__typed_writes_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                         const struct intel_perf_query_info *query,
                                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: $EuTypedWrites00 $TypedWrites00 FDIV */
   double tmp0 = icl__compute_extended__eu_typed_writes00__read(perf, query, results);
   double tmp1 = icl__compute_extended__typed_writes00__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Compute Extended metrics set :: UntypedReadsPerCacheLine */
static float
icl__compute_extended__untyped_reads_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                          const struct intel_perf_query_info *query,
                                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 5 READ C 1 READ FADD B 6 READ FADD FADD C 4 READ FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = results->accumulator[query->c_offset + 1];
   double tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 6];
   double tmp5 = tmp3 + tmp4;
   double tmp6 = tmp0 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   double tmp8 = tmp6;
   double tmp9 = tmp7;
   double tmp10 = tmp9 ? tmp8 / tmp9 : 0;

   return tmp10;
}

/* Compute Extended metrics set :: UntypedWritesPerCacheLine */
static float
icl__compute_extended__untyped_writes_per_cache_line__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 1 READ FADD C 2 READ FADD C 3 READ FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 2];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 3];
   double tmp6 = tmp4;
   double tmp7 = tmp5;
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;

   return tmp8;
}

/* Compute Metrics L3 Cache metrics set :: GPU Time Elapsed */
#define icl__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache metrics set :: GPU Core Clocks */
#define icl__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache metrics set :: AVG GPU Core Frequency */
#define icl__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache metrics set :: AVG GPU Core Frequency */
#define icl__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache metrics set :: GPU Busy */
#define icl__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache metrics set :: VS Threads Dispatched */
#define icl__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metrics set :: HS Threads Dispatched */
#define icl__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache metrics set :: DS Threads Dispatched */
#define icl__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache metrics set :: GS Threads Dispatched */
#define icl__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache metrics set :: FS Threads Dispatched */
#define icl__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache metrics set :: CS Threads Dispatched */
#define icl__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache metrics set :: EU Active */
#define icl__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache metrics set :: EU Stall */
#define icl__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache metrics set :: EU AVG IPC Rate */
#define icl__compute_l3_cache__eu_avg_ipc_rate__read \
   icl__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache metrics set :: EU AVG IPC Rate */
#define icl__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache metrics set :: EU Both FPU Pipes Active */
#define icl__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Pipe Active */
#define icl__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Pipe Active */
#define icl__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache metrics set :: EU Send Pipe Active */
#define icl__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Hybrid Instruction */
#define icl__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Hybrid Instruction */
#define icl__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Ternary Instruction */
#define icl__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Ternary Instruction */
#define icl__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Binary Instruction */
#define icl__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Binary Instruction */
#define icl__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache metrics set :: EU FPU0 Move Instruction */
#define icl__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache metrics set :: EU FPU1 Move Instruction */
#define icl__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache metrics set :: Rasterized Pixels */
#define icl__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache metrics set :: Early Hi-Depth Test Fails */
#define icl__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache metrics set :: Early Depth Test Fails */
#define icl__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metrics set :: Samples Killed in FS */
#define icl__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache metrics set :: Pixels Failing Tests */
#define icl__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache metrics set :: Samples Written */
#define icl__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache metrics set :: Samples Blended */
#define icl__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache metrics set :: Sampler Accesses */
#define icl__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache metrics set :: Sampler Texels */
#define icl__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache metrics set :: Sampler Texels Misses */
#define icl__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Read */
#define icl__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Read */
#define icl__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Written */
#define icl__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache metrics set :: SLM Bytes Written */
#define icl__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metrics set :: Shader Memory Accesses */
#define icl__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache metrics set :: Shader Atomic Memory Accesses */
#define icl__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache metrics set :: Shader Barrier Messages */
#define icl__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache metrics set :: Slice0 L3 Bank0 Accesses */
static uint64_t
icl__compute_l3_cache__l3_bank00_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metrics set :: Slice0 L3 Bank1 Accesses */
#define icl__compute_l3_cache__l3_bank01_accesses__read \
   hsw__memory_writes__llc_wr_accesses__read

/* Compute Metrics L3 Cache metrics set :: Slice0 L3 Bank2 Accesses */
static uint64_t
icl__compute_l3_cache__l3_bank02_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metrics set :: Slice0 L3 Bank3 Accesses */
static uint64_t
icl__compute_l3_cache__l3_bank03_accesses__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ 2 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = tmp0 * 2;

   return tmp1;
}

/* Compute Metrics L3 Cache metrics set :: Slice0 L3 Bank4 Accesses */
#define icl__compute_l3_cache__l3_bank04_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics L3 Cache metrics set :: Slice0 L3 Bank5 Accesses */
#define icl__compute_l3_cache__l3_bank05_accesses__read \
   bdw__compute_l3_cache__l3_bank10_accesses__read

/* Compute Metrics L3 Cache metrics set :: Slice0 L3 Bank6 Accesses */
#define icl__compute_l3_cache__l3_bank06_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache metrics set :: Slice0 L3 Bank7 Accesses */
#define icl__compute_l3_cache__l3_bank07_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache metrics set :: L3 Accesses */
static uint64_t
icl__compute_l3_cache__l3_accesses__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: $L3Bank00Accesses $L3Bank01Accesses UADD $L3Bank02Accesses UADD $L3Bank03Accesses UADD $L3Bank04Accesses UADD $L3Bank05Accesses UADD $L3Bank06Accesses UADD $L3Bank07Accesses UADD */
   uint64_t tmp0 = icl__compute_l3_cache__l3_bank00_accesses__read(perf, query, results) + icl__compute_l3_cache__l3_bank01_accesses__read(perf, query, results);
   uint64_t tmp1 = tmp0 + icl__compute_l3_cache__l3_bank02_accesses__read(perf, query, results);
   uint64_t tmp2 = tmp1 + icl__compute_l3_cache__l3_bank03_accesses__read(perf, query, results);
   uint64_t tmp3 = tmp2 + icl__compute_l3_cache__l3_bank04_accesses__read(perf, query, results);
   uint64_t tmp4 = tmp3 + icl__compute_l3_cache__l3_bank05_accesses__read(perf, query, results);
   uint64_t tmp5 = tmp4 + icl__compute_l3_cache__l3_bank06_accesses__read(perf, query, results);
   uint64_t tmp6 = tmp5 + icl__compute_l3_cache__l3_bank07_accesses__read(perf, query, results);

   return tmp6;
}

/* Compute Metrics L3 Cache metrics set :: L3 Lookup Accesses w/o IC */
static uint64_t
icl__compute_l3_cache__l3_lookups__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 6 READ UADD 2 UMUL A 32 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 2;
   uint64_t tmp4 = results->accumulator[query->a_offset + 32];
   uint64_t tmp5 = tmp3 + tmp4;

   return tmp5;
}

/* Compute Metrics L3 Cache metrics set :: L3 Sampler Throughput */
static uint64_t
icl__compute_l3_cache__l3_sampler_throughput__read(UNUSED struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  B 7 READ B 6 READ UADD 2 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 2;
   uint64_t tmp4 = 64 * tmp3;

   return tmp4;
}

/* Compute Metrics L3 Cache metrics set :: L3 Sampler Throughput */
#define icl__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metrics set :: L3 Shader Throughput */
#define icl__compute_l3_cache__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache metrics set :: L3 Shader Throughput */
#define icl__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache metrics set :: L3 Total Throughput */
static uint64_t
icl__compute_l3_cache__l3_total_throughput__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: $L3Accesses 64 UMUL */
   uint64_t tmp0 = icl__compute_l3_cache__l3_accesses__read(perf, query, results) * 64;

   return tmp0;
}

/* Compute Metrics L3 Cache metrics set :: L3 Total Throughput */
#define icl__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache metrics set :: GTI Read Throughput */
static uint64_t
icl__compute_l3_cache__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Compute Metrics L3 Cache metrics set :: GTI Read Throughput */
#define icl__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache metrics set :: GTI Write Throughput */
static uint64_t
icl__compute_l3_cache__gti_write_throughput__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = tmp0 * 64;

   return tmp1;
}

/* Compute Metrics L3 Cache metrics set :: GTI Write Throughput */
#define icl__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define icl__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define icl__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define icl__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define icl__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define icl__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define icl__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define icl__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define icl__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define icl__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define icl__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define icl__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define icl__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define icl__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define icl__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define icl__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define icl__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define icl__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define icl__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define icl__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define icl__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define icl__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define icl__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define icl__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define icl__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define icl__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define icl__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define icl__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define icl__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define icl__render_pipe_profile__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define icl__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define icl__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define icl__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define icl__render_pipe_profile__vs_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define icl__render_pipe_profile__hs_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define icl__render_pipe_profile__ds_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define icl__render_pipe_profile__gs_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define icl__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define icl__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define icl__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define icl__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define icl__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define icl__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define icl__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define icl__render_pipe_profile__ds_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define icl__render_pipe_profile__so_stall__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define icl__render_pipe_profile__cl_stall__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define icl__render_pipe_profile__sf_stall__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define icl__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define icl__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define icl__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define icl__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define icl__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define icl__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define icl__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define icl__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define icl__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define icl__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define icl__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define icl__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define icl__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define icl__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define icl__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define icl__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define icl__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define icl__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define icl__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define icl__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define icl__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define icl__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define icl__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define icl__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define icl__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define icl__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define icl__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define icl__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define icl__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define icl__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define icl__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define icl__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define icl__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define icl__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define icl__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define icl__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define icl__hdc_and_sf__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define icl__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define icl__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3 */
static float
icl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ B 7 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3 */
static float
icl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 2 READ C 1 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 2];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: Slice0 Dualsubslice2 Non-sampler Shader Access Stalled On L3 */
static float
icl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ C 3 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = results->accumulator[query->c_offset + 3];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: Slice0 Dualsubslice3 Non-sampler Shader Access Stalled On L3 */
static float
icl__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ C 5 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF :: Polygon Data Ready */
#define icl__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: SQ is full */
#define icl__hdc_and_sf__gt_request_queue_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define icl__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define icl__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define icl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define icl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define icl__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define icl__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define icl__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define icl__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define icl__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define icl__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define icl__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define icl__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define icl__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define icl__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define icl__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define icl__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define icl__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define icl__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define icl__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define icl__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define icl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define icl__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define icl__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define icl__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define icl__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define icl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define icl__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define icl__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define icl__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define icl__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define icl__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define icl__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define icl__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define icl__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define icl__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define icl__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define icl__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define icl__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define icl__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define icl__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define icl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define icl__rasterizer_and_pixel_backend__pixel_data00_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 Post-EarlyZ Pixel Data Ready */
#define icl__rasterizer_and_pixel_backend__pixel_data01_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 PS Output Available */
#define icl__rasterizer_and_pixel_backend__ps_output00_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 PS Output Available */
#define icl__rasterizer_and_pixel_backend__ps_output01_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Pixel Values Ready */
#define icl__rasterizer_and_pixel_backend__pixel_values00_ready__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 Pixel Values Ready */
#define icl__rasterizer_and_pixel_backend__pixel_values01_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define icl__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define icl__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define icl__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define icl__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define icl__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define icl__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define icl__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define icl__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define icl__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define icl__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define icl__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define icl__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define icl__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define icl__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define icl__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define icl__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define icl__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define icl__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define icl__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define icl__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define icl__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define icl__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define icl__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define icl__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define icl__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define icl__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define icl__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define icl__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define icl__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define icl__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define icl__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define icl__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define icl__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define icl__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define icl__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define icl__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define icl__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define icl__l3_1__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define icl__l3_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define icl__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define icl__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define icl__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank2 Active */
#define icl__l3_1__l30_bank2_active__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank3 Active */
#define icl__l3_1__l30_bank3_active__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank4 Active */
#define icl__l3_1__l30_bank4_active__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank5 Active */
#define icl__l3_1__l30_bank5_active__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank6 Active */
#define icl__l3_1__l30_bank6_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank7 Active */
#define icl__l3_1__l30_bank7_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define icl__l3_1__gt_request_queue_full__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L2Bank0 stalled metric set :: GPU Time Elapsed */
#define icl__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L2Bank0 stalled metric set :: GPU Core Clocks */
#define icl__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L2Bank0 stalled metric set :: AVG GPU Core Frequency */
#define icl__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L2Bank0 stalled metric set :: AVG GPU Core Frequency */
#define icl__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L2Bank0 stalled metric set :: GPU Busy */
#define icl__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L2Bank0 stalled metric set :: VS Threads Dispatched */
#define icl__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L2Bank0 stalled metric set :: HS Threads Dispatched */
#define icl__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L2Bank0 stalled metric set :: DS Threads Dispatched */
#define icl__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L2Bank0 stalled metric set :: GS Threads Dispatched */
#define icl__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L2Bank0 stalled metric set :: FS Threads Dispatched */
#define icl__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L2Bank0 stalled metric set :: CS Threads Dispatched */
#define icl__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L2Bank0 stalled metric set :: Rasterized Pixels */
#define icl__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* L2Bank0 stalled metric set :: Early Hi-Depth Test Fails */
#define icl__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* L2Bank0 stalled metric set :: Early Depth Test Fails */
#define icl__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* L2Bank0 stalled metric set :: Samples Killed in FS */
#define icl__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* L2Bank0 stalled metric set :: Pixels Failing Tests */
#define icl__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* L2Bank0 stalled metric set :: Samples Written */
#define icl__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* L2Bank0 stalled metric set :: Samples Blended */
#define icl__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* L2Bank0 stalled metric set :: EU Active */
#define icl__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* L2Bank0 stalled metric set :: EU Stall */
#define icl__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* L2Bank0 stalled metric set :: EU Both FPU Pipes Active */
#define icl__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* L2Bank0 stalled metric set :: EU Thread Occupancy */
#define icl__l3_2__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* L2Bank0 stalled metric set :: VS FPU0 Pipe Active */
#define icl__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* L2Bank0 stalled metric set :: VS FPU1 Pipe Active */
#define icl__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* L2Bank0 stalled metric set :: VS Send Pipe Active */
#define icl__l3_2__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* L2Bank0 stalled metric set :: PS FPU0 Pipe Active */
#define icl__l3_2__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* L2Bank0 stalled metric set :: PS FPU1 Pipe Active */
#define icl__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* L2Bank0 stalled metric set :: PS Send Pipeline Active */
#define icl__l3_2__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* L2Bank0 stalled metric set :: FS Both FPU Active */
#define icl__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_send_active__read

/* L2Bank0 stalled metric set :: Slice0 L3 Bank0 Stalled */
static float
icl__l3_2__l30_bank0_stalled__read(UNUSED struct intel_perf_config *perf,
                                   const struct intel_perf_query_info *query,
                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ FADD B 2 READ FADD B 3 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 2];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 3];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = icl__l3_2__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* L2Bank1 stalled metric set :: GPU Time Elapsed */
#define icl__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L2Bank1 stalled metric set :: GPU Core Clocks */
#define icl__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L2Bank1 stalled metric set :: AVG GPU Core Frequency */
#define icl__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L2Bank1 stalled metric set :: AVG GPU Core Frequency */
#define icl__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L2Bank1 stalled metric set :: GPU Busy */
#define icl__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L2Bank1 stalled metric set :: VS Threads Dispatched */
#define icl__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L2Bank1 stalled metric set :: HS Threads Dispatched */
#define icl__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L2Bank1 stalled metric set :: DS Threads Dispatched */
#define icl__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L2Bank1 stalled metric set :: GS Threads Dispatched */
#define icl__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L2Bank1 stalled metric set :: FS Threads Dispatched */
#define icl__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L2Bank1 stalled metric set :: CS Threads Dispatched */
#define icl__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L2Bank1 stalled metric set :: Rasterized Pixels */
#define icl__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* L2Bank1 stalled metric set :: Early Hi-Depth Test Fails */
#define icl__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* L2Bank1 stalled metric set :: Early Depth Test Fails */
#define icl__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* L2Bank1 stalled metric set :: Samples Killed in FS */
#define icl__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* L2Bank1 stalled metric set :: Pixels Failing Tests */
#define icl__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* L2Bank1 stalled metric set :: Samples Written */
#define icl__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* L2Bank1 stalled metric set :: Samples Blended */
#define icl__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* L2Bank1 stalled metric set :: EU Active */
#define icl__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* L2Bank1 stalled metric set :: EU Stall */
#define icl__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* L2Bank1 stalled metric set :: EU Both FPU Pipes Active */
#define icl__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* L2Bank1 stalled metric set :: EU Thread Occupancy */
#define icl__l3_3__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* L2Bank1 stalled metric set :: VS FPU0 Pipe Active */
#define icl__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* L2Bank1 stalled metric set :: VS FPU1 Pipe Active */
#define icl__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* L2Bank1 stalled metric set :: VS Send Pipe Active */
#define icl__l3_3__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* L2Bank1 stalled metric set :: PS FPU0 Pipe Active */
#define icl__l3_3__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* L2Bank1 stalled metric set :: PS FPU1 Pipe Active */
#define icl__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* L2Bank1 stalled metric set :: PS Send Pipeline Active */
#define icl__l3_3__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* L2Bank1 stalled metric set :: FS Both FPU Active */
#define icl__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_send_active__read

/* L2Bank1 stalled metric set :: Slice0 L3 Bank1 Stalled */
#define icl__l3_3__l30_bank1_stalled__read \
   icl__l3_2__l30_bank0_stalled__read

/* L2Bank4 stalled metric set :: GPU Time Elapsed */
#define icl__l3_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L2Bank4 stalled metric set :: GPU Core Clocks */
#define icl__l3_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L2Bank4 stalled metric set :: AVG GPU Core Frequency */
#define icl__l3_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L2Bank4 stalled metric set :: AVG GPU Core Frequency */
#define icl__l3_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L2Bank4 stalled metric set :: GPU Busy */
#define icl__l3_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L2Bank4 stalled metric set :: VS Threads Dispatched */
#define icl__l3_4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L2Bank4 stalled metric set :: HS Threads Dispatched */
#define icl__l3_4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L2Bank4 stalled metric set :: DS Threads Dispatched */
#define icl__l3_4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L2Bank4 stalled metric set :: GS Threads Dispatched */
#define icl__l3_4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L2Bank4 stalled metric set :: FS Threads Dispatched */
#define icl__l3_4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L2Bank4 stalled metric set :: CS Threads Dispatched */
#define icl__l3_4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L2Bank4 stalled metric set :: Rasterized Pixels */
#define icl__l3_4__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* L2Bank4 stalled metric set :: Early Hi-Depth Test Fails */
#define icl__l3_4__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* L2Bank4 stalled metric set :: Early Depth Test Fails */
#define icl__l3_4__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* L2Bank4 stalled metric set :: Samples Killed in FS */
#define icl__l3_4__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* L2Bank4 stalled metric set :: Pixels Failing Tests */
#define icl__l3_4__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* L2Bank4 stalled metric set :: Samples Written */
#define icl__l3_4__samples_written__read \
   bdw__render_basic__samples_written__read

/* L2Bank4 stalled metric set :: Samples Blended */
#define icl__l3_4__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* L2Bank4 stalled metric set :: EU Active */
#define icl__l3_4__eu_active__read \
   bdw__render_basic__eu_active__read

/* L2Bank4 stalled metric set :: EU Stall */
#define icl__l3_4__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* L2Bank4 stalled metric set :: EU Both FPU Pipes Active */
#define icl__l3_4__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* L2Bank4 stalled metric set :: EU Thread Occupancy */
#define icl__l3_4__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* L2Bank4 stalled metric set :: VS FPU0 Pipe Active */
#define icl__l3_4__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* L2Bank4 stalled metric set :: VS FPU1 Pipe Active */
#define icl__l3_4__vs_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* L2Bank4 stalled metric set :: VS Send Pipe Active */
#define icl__l3_4__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* L2Bank4 stalled metric set :: PS FPU0 Pipe Active */
#define icl__l3_4__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* L2Bank4 stalled metric set :: PS FPU1 Pipe Active */
#define icl__l3_4__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* L2Bank4 stalled metric set :: PS Send Pipeline Active */
#define icl__l3_4__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* L2Bank4 stalled metric set :: FS Both FPU Active */
#define icl__l3_4__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_send_active__read

/* L2Bank4 stalled metric set :: Slice0 L3 Bank4 Stalled */
#define icl__l3_4__l30_bank4_stalled__read \
   icl__l3_2__l30_bank0_stalled__read

/* L2Bank5 stalled metric set :: GPU Time Elapsed */
#define icl__l3_5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L2Bank5 stalled metric set :: GPU Core Clocks */
#define icl__l3_5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L2Bank5 stalled metric set :: AVG GPU Core Frequency */
#define icl__l3_5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L2Bank5 stalled metric set :: AVG GPU Core Frequency */
#define icl__l3_5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L2Bank5 stalled metric set :: GPU Busy */
#define icl__l3_5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L2Bank5 stalled metric set :: VS Threads Dispatched */
#define icl__l3_5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L2Bank5 stalled metric set :: HS Threads Dispatched */
#define icl__l3_5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L2Bank5 stalled metric set :: DS Threads Dispatched */
#define icl__l3_5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L2Bank5 stalled metric set :: GS Threads Dispatched */
#define icl__l3_5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L2Bank5 stalled metric set :: FS Threads Dispatched */
#define icl__l3_5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L2Bank5 stalled metric set :: CS Threads Dispatched */
#define icl__l3_5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L2Bank5 stalled metric set :: Rasterized Pixels */
#define icl__l3_5__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* L2Bank5 stalled metric set :: Early Hi-Depth Test Fails */
#define icl__l3_5__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* L2Bank5 stalled metric set :: Early Depth Test Fails */
#define icl__l3_5__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* L2Bank5 stalled metric set :: Samples Killed in FS */
#define icl__l3_5__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* L2Bank5 stalled metric set :: Pixels Failing Tests */
#define icl__l3_5__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* L2Bank5 stalled metric set :: Samples Written */
#define icl__l3_5__samples_written__read \
   bdw__render_basic__samples_written__read

/* L2Bank5 stalled metric set :: Samples Blended */
#define icl__l3_5__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* L2Bank5 stalled metric set :: EU Active */
#define icl__l3_5__eu_active__read \
   bdw__render_basic__eu_active__read

/* L2Bank5 stalled metric set :: EU Stall */
#define icl__l3_5__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* L2Bank5 stalled metric set :: EU Both FPU Pipes Active */
#define icl__l3_5__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* L2Bank5 stalled metric set :: EU Thread Occupancy */
#define icl__l3_5__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* L2Bank5 stalled metric set :: VS FPU0 Pipe Active */
#define icl__l3_5__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* L2Bank5 stalled metric set :: VS FPU1 Pipe Active */
#define icl__l3_5__vs_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* L2Bank5 stalled metric set :: VS Send Pipe Active */
#define icl__l3_5__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* L2Bank5 stalled metric set :: PS FPU0 Pipe Active */
#define icl__l3_5__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* L2Bank5 stalled metric set :: PS FPU1 Pipe Active */
#define icl__l3_5__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* L2Bank5 stalled metric set :: PS Send Pipeline Active */
#define icl__l3_5__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* L2Bank5 stalled metric set :: FS Both FPU Active */
#define icl__l3_5__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_send_active__read

/* L2Bank5 stalled metric set :: Slice0 L3 Bank5 Stalled */
static float
icl__l3_5__l30_bank5_stalled__read(UNUSED struct intel_perf_config *perf,
                                   const struct intel_perf_query_info *query,
                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ B 3 READ FADD B 0 READ FADD B 1 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->b_offset + 3];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 0];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 1];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = icl__l3_5__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* Metric set Sampler 1 :: GPU Time Elapsed */
#define icl__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler 1 :: GPU Core Clocks */
#define icl__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler 1 :: AVG GPU Core Frequency */
#define icl__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler 1 :: AVG GPU Core Frequency */
#define icl__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler 1 :: GPU Busy */
#define icl__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler 1 :: VS Threads Dispatched */
#define icl__sampler_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler 1 :: HS Threads Dispatched */
#define icl__sampler_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler 1 :: DS Threads Dispatched */
#define icl__sampler_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler 1 :: GS Threads Dispatched */
#define icl__sampler_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler 1 :: FS Threads Dispatched */
#define icl__sampler_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler 1 :: CS Threads Dispatched */
#define icl__sampler_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler 1 :: EU Active */
#define icl__sampler_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler 1 :: EU Stall */
#define icl__sampler_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler 1 :: EU Both FPU Pipes Active */
#define icl__sampler_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler 1 :: VS FPU0 Pipe Active */
#define icl__sampler_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler 1 :: VS FPU1 Pipe Active */
#define icl__sampler_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler 1 :: VS Send Pipe Active */
#define icl__sampler_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler 1 :: PS FPU0 Pipe Active */
#define icl__sampler_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler 1 :: PS FPU1 Pipe Active */
#define icl__sampler_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler 1 :: PS Send Pipeline Active */
#define icl__sampler_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler 1 :: FS Both FPU Active */
#define icl__sampler_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler 1 :: Rasterized Pixels */
#define icl__sampler_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler 1 :: Early Hi-Depth Test Fails */
#define icl__sampler_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler 1 :: Early Depth Test Fails */
#define icl__sampler_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler 1 :: Samples Killed in FS */
#define icl__sampler_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler 1 :: Pixels Failing Tests */
#define icl__sampler_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler 1 :: Samples Written */
#define icl__sampler_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler 1 :: Samples Blended */
#define icl__sampler_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler 1 :: Sampler Texels */
#define icl__sampler_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler 1 :: Sampler Texels Misses */
#define icl__sampler_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler 1 :: SLM Bytes Read */
#define icl__sampler_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler 1 :: SLM Bytes Read */
#define icl__sampler_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 1 :: SLM Bytes Written */
#define icl__sampler_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler 1 :: SLM Bytes Written */
#define icl__sampler_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 1 :: Shader Memory Accesses */
#define icl__sampler_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler 1 :: Shader Atomic Memory Accesses */
#define icl__sampler_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler 1 :: L3 Shader Throughput */
#define icl__sampler_1__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set Sampler 1 :: L3 Shader Throughput */
#define icl__sampler_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 1 :: Shader Barrier Messages */
#define icl__sampler_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler 1 :: Slice0 Subslice0 Input Available */
#define icl__sampler_1__sampler00_input_available__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice1 Input Available */
#define icl__sampler_1__sampler01_input_available__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice2 Input Available */
#define icl__sampler_1__sampler02_input_available__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice3 Input Available */
#define icl__sampler_1__sampler03_input_available__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice4 Input Available */
#define icl__sampler_1__sampler04_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice5 Input Available */
#define icl__sampler_1__sampler05_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice6 Input Available */
#define icl__sampler_1__sampler06_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler 1 :: Slice0 Subslice7 Input Available */
#define icl__sampler_1__sampler07_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler 2 :: GPU Time Elapsed */
#define icl__sampler_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler 2 :: GPU Core Clocks */
#define icl__sampler_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler 2 :: AVG GPU Core Frequency */
#define icl__sampler_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler 2 :: AVG GPU Core Frequency */
#define icl__sampler_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler 2 :: GPU Busy */
#define icl__sampler_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler 2 :: VS Threads Dispatched */
#define icl__sampler_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler 2 :: HS Threads Dispatched */
#define icl__sampler_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler 2 :: DS Threads Dispatched */
#define icl__sampler_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler 2 :: GS Threads Dispatched */
#define icl__sampler_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler 2 :: FS Threads Dispatched */
#define icl__sampler_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler 2 :: CS Threads Dispatched */
#define icl__sampler_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler 2 :: EU Active */
#define icl__sampler_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler 2 :: EU Stall */
#define icl__sampler_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler 2 :: EU Both FPU Pipes Active */
#define icl__sampler_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler 2 :: VS FPU0 Pipe Active */
#define icl__sampler_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler 2 :: VS FPU1 Pipe Active */
#define icl__sampler_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler 2 :: VS Send Pipe Active */
#define icl__sampler_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler 2 :: PS FPU0 Pipe Active */
#define icl__sampler_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler 2 :: PS FPU1 Pipe Active */
#define icl__sampler_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler 2 :: PS Send Pipeline Active */
#define icl__sampler_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler 2 :: FS Both FPU Active */
#define icl__sampler_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler 2 :: Rasterized Pixels */
#define icl__sampler_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler 2 :: Early Hi-Depth Test Fails */
#define icl__sampler_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler 2 :: Early Depth Test Fails */
#define icl__sampler_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler 2 :: Samples Killed in FS */
#define icl__sampler_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler 2 :: Pixels Failing Tests */
#define icl__sampler_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler 2 :: Samples Written */
#define icl__sampler_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler 2 :: Samples Blended */
#define icl__sampler_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler 2 :: Sampler Texels */
#define icl__sampler_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler 2 :: Sampler Texels Misses */
#define icl__sampler_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler 2 :: SLM Bytes Read */
#define icl__sampler_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler 2 :: SLM Bytes Read */
#define icl__sampler_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 2 :: SLM Bytes Written */
#define icl__sampler_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler 2 :: SLM Bytes Written */
#define icl__sampler_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 2 :: Shader Memory Accesses */
#define icl__sampler_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler 2 :: Shader Atomic Memory Accesses */
#define icl__sampler_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler 2 :: L3 Shader Throughput */
#define icl__sampler_2__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set Sampler 2 :: L3 Shader Throughput */
#define icl__sampler_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 2 :: Shader Barrier Messages */
#define icl__sampler_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler 2 :: Slice0 Subslice0 Sampler Output Ready */
#define icl__sampler_2__sampler00_output_ready__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set Sampler 2 :: Slice0 Subslice1 Sampler Output Ready */
#define icl__sampler_2__sampler01_output_ready__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice2 Sampler Output Ready */
#define icl__sampler_2__sampler02_output_ready__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice3 Sampler Output Ready */
#define icl__sampler_2__sampler03_output_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice4 Sampler Output Ready */
#define icl__sampler_2__sampler04_output_ready__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice5 Sampler Output Ready */
#define icl__sampler_2__sampler05_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice6 Sampler Output Ready */
#define icl__sampler_2__sampler06_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler 2 :: Slice0 Subslice7 Sampler Output Ready */
#define icl__sampler_2__sampler07_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler 2 :: SQ is full */
#define icl__sampler_2__gt_request_queue_full__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define icl__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define icl__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define icl__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define icl__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define icl__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define icl__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define icl__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define icl__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define icl__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define icl__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define icl__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define icl__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define icl__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define icl__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define icl__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define icl__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define icl__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: VS EU Active */
#define icl__tdl_1__vs_eu_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Metric set TDL_1 :: VS AVG Active per Thread */
static uint64_t
icl__tdl_1__vs_eu_active_per_thread__read(UNUSED struct intel_perf_config *perf,
                                          const struct intel_perf_query_info *query,
                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: A 13 READ $VsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 13];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = icl__tdl_1__vs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Metric set TDL_1 :: VS EU Stall */
#define icl__tdl_1__vs_eu_stall__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Metric set TDL_1 :: VS AVG Stall per Thread */
static uint64_t
icl__tdl_1__vs_eu_stall_per_thread__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 14 READ $VsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 14];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = icl__tdl_1__vs_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define icl__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define icl__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define icl__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define icl__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: FS EU Active */
#define icl__tdl_1__ps_eu_active__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Metric set TDL_1 :: FS AVG Active per Thread */
static uint64_t
icl__tdl_1__ps_eu_active_per_thread__read(UNUSED struct intel_perf_config *perf,
                                          const struct intel_perf_query_info *query,
                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: A 19 READ $PsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 19];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = icl__tdl_1__ps_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Metric set TDL_1 :: FS EU Stall */
#define icl__tdl_1__ps_eu_stall__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Metric set TDL_1 :: FS AVG Stall per Thread */
static uint64_t
icl__tdl_1__ps_eu_stall_per_thread__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 20 READ $PsThreads UDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 20];
   uint64_t tmp1 = tmp0;
   uint64_t tmp2 = icl__tdl_1__ps_threads__read(perf, query, results);
   uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0;

   return tmp3;
}

/* Metric set TDL_1 :: Rasterized Pixels */
#define icl__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define icl__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define icl__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define icl__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define icl__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define icl__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define icl__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define icl__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define icl__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define icl__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define icl__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define icl__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define icl__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define icl__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define icl__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define icl__tdl_1__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define icl__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define icl__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher */
#define icl__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher */
#define icl__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher */
#define icl__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher */
#define icl__tdl_1__ps_thread03_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher */
#define icl__tdl_1__ps_thread04_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher */
#define icl__tdl_1__ps_thread05_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher */
#define icl__tdl_1__ps_thread06_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher */
#define icl__tdl_1__ps_thread07_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define icl__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define icl__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define icl__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define icl__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define icl__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define icl__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define icl__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define icl__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define icl__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define icl__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define icl__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define icl__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define icl__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define icl__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define icl__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define icl__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define icl__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define icl__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define icl__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define icl__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define icl__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define icl__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define icl__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define icl__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define icl__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define icl__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define icl__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define icl__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define icl__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define icl__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define icl__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define icl__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define icl__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define icl__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define icl__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define icl__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define icl__tdl_2__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define icl__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define icl__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher */
static float
icl__tdl_2__non_ps_thread00_ready_for_dispatch__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ B 7 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher */
static float
icl__tdl_2__non_ps_thread01_ready_for_dispatch__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ C 0 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 0];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher */
static float
icl__tdl_2__non_ps_thread02_ready_for_dispatch__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ C 1 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher */
static float
icl__tdl_2__non_ps_thread03_ready_for_dispatch__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ C 2 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher */
static float
icl__tdl_2__non_ps_thread04_ready_for_dispatch__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ C 3 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 3];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher */
static float
icl__tdl_2__non_ps_thread05_ready_for_dispatch__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ C 4 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 4];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher */
static float
icl__tdl_2__non_ps_thread06_ready_for_dispatch__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ C 5 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher */
static float
icl__tdl_2__non_ps_thread07_ready_for_dispatch__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ C 6 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set TDL_2 :: SQ is full */
#define icl__tdl_2__gt_request_queue_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_3 :: GPU Time Elapsed */
#define icl__tdl_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_3 :: GPU Core Clocks */
#define icl__tdl_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_3 :: AVG GPU Core Frequency */
#define icl__tdl_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_3 :: AVG GPU Core Frequency */
#define icl__tdl_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_3 :: GPU Busy */
#define icl__tdl_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_3 :: VS Threads Dispatched */
#define icl__tdl_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_3 :: HS Threads Dispatched */
#define icl__tdl_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_3 :: DS Threads Dispatched */
#define icl__tdl_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_3 :: GS Threads Dispatched */
#define icl__tdl_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_3 :: FS Threads Dispatched */
#define icl__tdl_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_3 :: CS Threads Dispatched */
#define icl__tdl_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_3 :: EU Active */
#define icl__tdl_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_3 :: EU Stall */
#define icl__tdl_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_3 :: EU Both FPU Pipes Active */
#define icl__tdl_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_3 :: VS FPU0 Pipe Active */
#define icl__tdl_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_3 :: VS FPU1 Pipe Active */
#define icl__tdl_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_3 :: VS Send Pipe Active */
#define icl__tdl_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_3 :: PS FPU0 Pipe Active */
#define icl__tdl_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_3 :: PS FPU1 Pipe Active */
#define icl__tdl_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_3 :: PS Send Pipeline Active */
#define icl__tdl_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_3 :: FS Both FPU Active */
#define icl__tdl_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_3 :: Rasterized Pixels */
#define icl__tdl_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_3 :: Early Hi-Depth Test Fails */
#define icl__tdl_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_3 :: Early Depth Test Fails */
#define icl__tdl_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_3 :: Samples Killed in FS */
#define icl__tdl_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_3 :: Pixels Failing Tests */
#define icl__tdl_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_3 :: Samples Written */
#define icl__tdl_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_3 :: Samples Blended */
#define icl__tdl_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_3 :: Sampler Texels */
#define icl__tdl_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_3 :: Sampler Texels Misses */
#define icl__tdl_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_3 :: SLM Bytes Read */
#define icl__tdl_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_3 :: SLM Bytes Read */
#define icl__tdl_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_3 :: SLM Bytes Written */
#define icl__tdl_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_3 :: SLM Bytes Written */
#define icl__tdl_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_3 :: Shader Memory Accesses */
#define icl__tdl_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_3 :: Shader Atomic Memory Accesses */
#define icl__tdl_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_3 :: L3 Shader Throughput */
#define icl__tdl_3__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set TDL_3 :: L3 Shader Throughput */
#define icl__tdl_3__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_3 :: Shader Barrier Messages */
#define icl__tdl_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 0 */
#define icl__tdl_3__thread_header00_ready_port0__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 1 */
#define icl__tdl_3__thread_header00_ready_port1__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 0 */
#define icl__tdl_3__thread_header01_ready_port0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 1 */
#define icl__tdl_3__thread_header01_ready_port1__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 0 */
#define icl__tdl_3__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 1 */
#define icl__tdl_3__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 0 */
#define icl__tdl_3__thread_header03_ready_port0__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 1 */
#define icl__tdl_3__thread_header03_ready_port1__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 0 */
#define icl__tdl_3__thread_header04_ready_port0__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 1 */
#define icl__tdl_3__thread_header04_ready_port1__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 0 */
#define icl__tdl_3__thread_header05_ready_port0__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 1 */
#define icl__tdl_3__thread_header05_ready_port1__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 0 */
#define icl__tdl_3__thread_header06_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 1 */
#define icl__tdl_3__thread_header06_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 0 */
#define icl__tdl_3__thread_header07_ready_port0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 1 */
#define icl__tdl_3__thread_header07_ready_port1__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: GPU Time Elapsed */
#define icl__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness :: GPU Core Clocks */
#define icl__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define icl__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define icl__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness :: GPU Busy */
#define icl__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Gpu Rings Busyness :: Render Ring Busy */
#define icl__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: Vdbox0 Ring Busy */
#define icl__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness :: Vdbox1 Ring Busy */
#define icl__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness :: Vebox Ring Busy */
#define icl__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness :: Blitter Ring Busy */
#define icl__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* Gpu Rings Busyness :: Posh Ring Busy */
#define icl__gpu_busyness__posh_engine_busy__read \
   bdw__render_pipe_profile__ds_stall__read

/* Gpu Rings Busyness :: AnyRingBusy */
#define icl__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TestOa :: GPU Time Elapsed */
#define icl__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define icl__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define icl__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define icl__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define icl__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define icl__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define icl__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define icl__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define icl__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define icl__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define icl__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define icl__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define icl__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* AsyncCompute :: GPU Time Elapsed */
#define icl__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define icl__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define icl__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define icl__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define icl__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define icl__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define icl__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define icl__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define icl__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define icl__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define icl__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: EU FPU0 Pipe Active */
#define icl__async_compute__fpu0_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: VS FPU0 Pipe Active */
#define icl__async_compute__vs_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: PS FPU0 Pipe Active */
#define icl__async_compute__ps_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: CS FPU0 Pipe Active */
#define icl__async_compute__cs_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: EU FPU1 Pipe Active */
#define icl__async_compute__fpu1_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: VS FPU1 Pipe Active */
#define icl__async_compute__vs_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: PS FPU1 Pipe Active */
#define icl__async_compute__ps_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: CS FPU1 Pipe Active */
#define icl__async_compute__cs_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: EU Thread Occupancy */
#define icl__async_compute__eu_thread_occupancy__read \
   sklgt2__ff_bottlenecks__eu_thread_occupancy__read

/* AsyncCompute :: EU Active */
#define icl__async_compute__eu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: EU Stall */
#define icl__async_compute__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define ehl__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define ehl__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define ehl__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define ehl__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define ehl__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define ehl__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define ehl__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define ehl__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define ehl__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define ehl__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define ehl__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define ehl__render_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define ehl__render_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Both FPU Pipes Active */
#define ehl__render_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Render Metrics Basic set :: VS FPU0 Pipe Active */
#define ehl__render_basic__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic set :: VS FPU1 Pipe Active */
#define ehl__render_basic__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic set :: VS Send Pipe Active */
#define ehl__render_basic__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic set :: PS FPU0 Pipe Active */
#define ehl__render_basic__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Render Metrics Basic set :: PS FPU1 Pipe Active */
#define ehl__render_basic__ps_fpu1_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Render Metrics Basic set :: PS Send Pipeline Active */
#define ehl__render_basic__ps_send_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic set :: Sampler00 Busy */
#define ehl__render_basic__sampler00_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics Basic set :: Samplers Busy */
#define ehl__render_basic__samplers_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics Basic set :: Sampler00 Bottleneck */
#define ehl__render_basic__sampler00_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define ehl__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define ehl__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define ehl__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define ehl__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define ehl__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define ehl__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define ehl__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define ehl__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define ehl__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: Sampler Cache Misses */
static uint64_t
ehl__render_basic__sampler_l1_misses__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ C 5 READ UADD 8 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 8;

   return tmp3;
}

/* Render Metrics Basic set :: SLM Bytes Read */
#define ehl__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define ehl__render_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define ehl__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define ehl__render_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define ehl__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define ehl__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Shader Throughput */
static uint64_t
ehl__render_basic__l3_shader_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: A 30 READ A 31 READ UADD A 32 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 30];
   uint64_t tmp1 = results->accumulator[query->a_offset + 31];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 32];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = tmp4 * 64;

   return tmp5;
}

/* Render Metrics Basic set :: L3 Shader Throughput */
#define ehl__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define ehl__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Read Throughput */
static uint64_t
ehl__render_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  B 5 READ B 4 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = 64 * tmp2;

   return tmp3;
}

/* Render Metrics Basic set :: GTI Read Throughput */
#define ehl__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define ehl__render_basic__gti_write_throughput__read \
   icl__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define ehl__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: Samplers Bottleneck */
#define ehl__render_basic__sampler_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define ehl__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define ehl__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define ehl__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define ehl__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define ehl__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define ehl__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define ehl__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define ehl__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define ehl__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define ehl__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define ehl__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define ehl__compute_basic__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define ehl__compute_basic__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define ehl__compute_basic__eu_avg_ipc_rate__read \
   icl__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics Basic set :: EU AVG IPC Rate */
#define ehl__compute_basic__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic set :: EU Both FPU Pipes Active */
#define ehl__compute_basic__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic set :: EU FPU0 Pipe Active */
#define ehl__compute_basic__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic set :: EU FPU1 Pipe Active */
#define ehl__compute_basic__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic set :: EU Send Pipe Active */
#define ehl__compute_basic__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define ehl__compute_basic__eu_thread_occupancy__read \
   icl__compute_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define ehl__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define ehl__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define ehl__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define ehl__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define ehl__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define ehl__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define ehl__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define ehl__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define ehl__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define ehl__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define ehl__compute_basic__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define ehl__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define ehl__compute_basic__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define ehl__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define ehl__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define ehl__compute_basic__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define ehl__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define ehl__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define ehl__compute_basic__typed_bytes_read__read \
   icl__compute_basic__typed_bytes_read__read

/* Compute Metrics Basic set :: Typed Bytes Read */
#define ehl__compute_basic__typed_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Bytes Written */
#define ehl__compute_basic__typed_bytes_written__read \
   icl__compute_basic__typed_bytes_written__read

/* Compute Metrics Basic set :: Typed Bytes Written */
#define ehl__compute_basic__typed_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define ehl__compute_basic__untyped_bytes_read__read \
   icl__compute_basic__untyped_bytes_read__read

/* Compute Metrics Basic set :: Untyped Bytes Read */
#define ehl__compute_basic__untyped_bytes_read__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Untyped Writes */
#define ehl__compute_basic__untyped_bytes_written__read \
   icl__compute_basic__untyped_bytes_written__read

/* Compute Metrics Basic set :: Untyped Writes */
#define ehl__compute_basic__untyped_bytes_written__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: Typed Atomics Accesses */
#define ehl__compute_basic__typed_atomics__read \
   icl__compute_basic__typed_atomics__read

/* Compute Metrics Basic set :: Typed Atomics Accesses */
#define ehl__compute_basic__typed_atomics__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics Basic set :: GTI Read Throughput */
static uint64_t
ehl__compute_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  B 7 READ B 6 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = 64 * tmp2;

   return tmp3;
}

/* Compute Metrics Basic set :: GTI Read Throughput */
#define ehl__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define ehl__compute_basic__gti_write_throughput__read \
   icl__render_basic__gti_write_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define ehl__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* ComputeExtended metrics set :: GPU Time Elapsed */
#define ehl__compute_extended__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ComputeExtended metrics set :: GPU Core Clocks */
#define ehl__compute_extended__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ComputeExtended metrics set :: AVG GPU Core Frequency */
#define ehl__compute_extended__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ComputeExtended metrics set :: AVG GPU Core Frequency */
#define ehl__compute_extended__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ComputeExtended metrics set :: GPU Busy */
#define ehl__compute_extended__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* ComputeExtended metrics set :: CS Threads Dispatched */
#define ehl__compute_extended__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* ComputeExtended metrics set :: Typed Atomics 00 */
#define ehl__compute_extended__typed_atomics00__read \
   hsw__memory_reads__gpu_core_clocks__read

/* ComputeExtended metrics set :: Typed Reads 00 */
#define ehl__compute_extended__typed_reads00__read \
   hsw__memory_reads__llc_read_accesses__read

/* ComputeExtended metrics set :: Typed Writes 00 */
#define ehl__compute_extended__typed_writes00__read \
   hsw__memory_reads__gti_memory_reads__read

/* ComputeExtended metrics set :: Untyped Reads 00 */
#define ehl__compute_extended__untyped_reads00__read \
   hsw__compute_extended__typed_atomics0__read

/* ComputeExtended metrics set :: Untyped Writes 00 */
#define ehl__compute_extended__untyped_writes00__read \
   hsw__compute_extended__untyped_reads0__read

/* ComputeExtended metrics set :: Eu Typed Reads 00 */
#define ehl__compute_extended__eu_typed_reads00__read \
   hsw__compute_extended__eu_typed_writes0__read

/* ComputeExtended metrics set :: Eu Typed Writes 00 */
#define ehl__compute_extended__eu_typed_writes00__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* ComputeExtended metrics set :: Eu Typed Atomics 00 */
#define ehl__compute_extended__eu_typed_atomics00__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ComputeExtended metrics set :: Eu A32 Untyped Reads 00 */
#define ehl__compute_extended__eu_a32_untyped_reads00__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ComputeExtended metrics set :: Eu A32 Untyped Writes 00 */
#define ehl__compute_extended__eu_a32_untyped_writes00__read \
   icl__compute_extended__eu_a32_untyped_writes00__read

/* ComputeExtended metrics set :: Eu 64 Untyped Reads 00 */
#define ehl__compute_extended__eu_a64_untyped_reads00__read \
   icl__compute_extended__eu_a64_untyped_reads00__read

/* ComputeExtended metrics set :: Eu A64 Untyped Writes 00 */
#define ehl__compute_extended__eu_a64_untyped_writes00__read \
   hsw__render_basic__gpu_core_clocks__read

/* ComputeExtended metrics set :: TypedAtomicsPerCacheLine */
#define ehl__compute_extended__typed_atomics_per_cache_line__read \
   icl__compute_extended__typed_atomics_per_cache_line__read

/* ComputeExtended metrics set :: TypedReadsPerCacheLine */
#define ehl__compute_extended__typed_reads_per_cache_line__read \
   icl__compute_extended__typed_reads_per_cache_line__read

/* ComputeExtended metrics set :: TypedWritesPerCacheLine */
#define ehl__compute_extended__typed_writes_per_cache_line__read \
   icl__compute_extended__typed_writes_per_cache_line__read

/* ComputeExtended metrics set :: UntypedReadsPerCacheLine */
#define ehl__compute_extended__untyped_reads_per_cache_line__read \
   icl__compute_extended__untyped_reads_per_cache_line__read

/* ComputeExtended metrics set :: UntypedWritesPerCacheLine */
#define ehl__compute_extended__untyped_writes_per_cache_line__read \
   icl__compute_extended__untyped_writes_per_cache_line__read

/* Compute Metrics L3 Cache set :: GPU Time Elapsed */
#define ehl__compute_l3_cache__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics L3 Cache set :: GPU Core Clocks */
#define ehl__compute_l3_cache__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define ehl__compute_l3_cache__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics L3 Cache set :: AVG GPU Core Frequency */
#define ehl__compute_l3_cache__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics L3 Cache set :: GPU Busy */
#define ehl__compute_l3_cache__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics L3 Cache set :: VS Threads Dispatched */
#define ehl__compute_l3_cache__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: HS Threads Dispatched */
#define ehl__compute_l3_cache__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics L3 Cache set :: DS Threads Dispatched */
#define ehl__compute_l3_cache__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics L3 Cache set :: GS Threads Dispatched */
#define ehl__compute_l3_cache__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics L3 Cache set :: FS Threads Dispatched */
#define ehl__compute_l3_cache__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics L3 Cache set :: CS Threads Dispatched */
#define ehl__compute_l3_cache__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics L3 Cache set :: EU Active */
#define ehl__compute_l3_cache__eu_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics L3 Cache set :: EU Stall */
#define ehl__compute_l3_cache__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define ehl__compute_l3_cache__eu_avg_ipc_rate__read \
   icl__compute_basic__eu_avg_ipc_rate__read

/* Compute Metrics L3 Cache set :: EU AVG IPC Rate */
#define ehl__compute_l3_cache__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics L3 Cache set :: EU Both FPU Pipes Active */
#define ehl__compute_l3_cache__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Pipe Active */
#define ehl__compute_l3_cache__fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Pipe Active */
#define ehl__compute_l3_cache__fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU Send Pipe Active */
#define ehl__compute_l3_cache__eu_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Hybrid Instruction */
#define ehl__compute_l3_cache__eu_hybrid_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Hybrid Instruction */
#define ehl__compute_l3_cache__eu_hybrid_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU0 Ternary Instruction */
#define ehl__compute_l3_cache__eu_ternary_fpu0_instruction__read \
   bdw__render_basic__ps_fpu0_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Ternary Instruction */
#define ehl__compute_l3_cache__eu_ternary_fpu1_instruction__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Binary Instruction */
#define ehl__compute_l3_cache__eu_binary_fpu0_instruction__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics L3 Cache set :: EU FPU1 Binary Instruction */
#define ehl__compute_l3_cache__eu_binary_fpu1_instruction__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics L3 Cache set :: EU FPU0 Move Instruction */
#define ehl__compute_l3_cache__eu_move_fpu0_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Compute Metrics L3 Cache set :: EU FPU1 Move Instruction */
#define ehl__compute_l3_cache__eu_move_fpu1_instruction__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Compute Metrics L3 Cache set :: Rasterized Pixels */
#define ehl__compute_l3_cache__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics L3 Cache set :: Early Hi-Depth Test Fails */
#define ehl__compute_l3_cache__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Early Depth Test Fails */
#define ehl__compute_l3_cache__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Samples Killed in FS */
#define ehl__compute_l3_cache__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics L3 Cache set :: Pixels Failing Tests */
#define ehl__compute_l3_cache__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics L3 Cache set :: Samples Written */
#define ehl__compute_l3_cache__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics L3 Cache set :: Samples Blended */
#define ehl__compute_l3_cache__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics L3 Cache set :: Sampler Accesses */
#define ehl__compute_l3_cache__sampler_accesses__read \
   bdw__render_pipe_profile__sampler_accesses__read

/* Compute Metrics L3 Cache set :: Sampler Texels */
#define ehl__compute_l3_cache__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics L3 Cache set :: Sampler Texels Misses */
#define ehl__compute_l3_cache__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define ehl__compute_l3_cache__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics L3 Cache set :: SLM Bytes Read */
#define ehl__compute_l3_cache__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define ehl__compute_l3_cache__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics L3 Cache set :: SLM Bytes Written */
#define ehl__compute_l3_cache__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: Shader Memory Accesses */
#define ehl__compute_l3_cache__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics L3 Cache set :: Shader Atomic Memory Accesses */
#define ehl__compute_l3_cache__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics L3 Cache set :: Shader Barrier Messages */
#define ehl__compute_l3_cache__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics L3 Cache set :: Slice0 L3 Bank0 Accesses */
#define ehl__compute_l3_cache__l3_bank00_accesses__read \
   icl__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache set :: Slice0 L3 Bank1 Accesses */
#define ehl__compute_l3_cache__l3_bank01_accesses__read \
   hsw__memory_writes__llc_wr_accesses__read

/* Compute Metrics L3 Cache set :: Slice0 L3 Bank2 Accesses */
#define ehl__compute_l3_cache__l3_bank02_accesses__read \
   icl__compute_l3_cache__l3_bank02_accesses__read

/* Compute Metrics L3 Cache set :: Slice0 L3 Bank3 Accesses */
#define ehl__compute_l3_cache__l3_bank03_accesses__read \
   icl__compute_l3_cache__l3_bank03_accesses__read

/* Compute Metrics L3 Cache set :: Slice0 L3 Bank4 Accesses */
#define ehl__compute_l3_cache__l3_bank04_accesses__read \
   bdw__memory_reads__gti_ring_accesses__read

/* Compute Metrics L3 Cache set :: Slice0 L3 Bank5 Accesses */
#define ehl__compute_l3_cache__l3_bank05_accesses__read \
   bdw__compute_l3_cache__l3_bank10_accesses__read

/* Compute Metrics L3 Cache set :: Slice0 L3 Bank6 Accesses */
#define ehl__compute_l3_cache__l3_bank06_accesses__read \
   bdw__compute_l3_cache__l3_bank01_accesses__read

/* Compute Metrics L3 Cache set :: Slice0 L3 Bank7 Accesses */
#define ehl__compute_l3_cache__l3_bank07_accesses__read \
   bdw__compute_l3_cache__l3_bank00_accesses__read

/* Compute Metrics L3 Cache set :: L3 Accesses */
#define ehl__compute_l3_cache__l3_accesses__read \
   icl__compute_l3_cache__l3_accesses__read

/* Compute Metrics L3 Cache set :: L3 Lookup Accesses w/o IC */
static uint64_t
ehl__compute_l3_cache__l3_lookups__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 6 READ UADD 8 UMUL A 32 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 8;
   uint64_t tmp4 = results->accumulator[query->a_offset + 32];
   uint64_t tmp5 = tmp3 + tmp4;

   return tmp5;
}

/* Compute Metrics L3 Cache set :: L3 Misses */
static uint64_t
ehl__compute_l3_cache__l3_misses__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 B 5 READ B 4 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = 2 * tmp2;

   return tmp3;
}

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
static uint64_t
ehl__compute_l3_cache__l3_sampler_throughput__read(UNUSED struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  B 7 READ B 6 READ UADD 8 UMUL UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 8;
   uint64_t tmp4 = 64 * tmp3;

   return tmp4;
}

/* Compute Metrics L3 Cache set :: L3 Sampler Throughput */
#define ehl__compute_l3_cache__l3_sampler_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define ehl__compute_l3_cache__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Compute Metrics L3 Cache set :: L3 Shader Throughput */
#define ehl__compute_l3_cache__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define ehl__compute_l3_cache__l3_total_throughput__read \
   icl__compute_l3_cache__l3_total_throughput__read

/* Compute Metrics L3 Cache set :: L3 Total Throughput */
#define ehl__compute_l3_cache__l3_total_throughput__max \
   bdw__render_basic__gti_depth_throughput__max

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
static uint64_t
ehl__compute_l3_cache__gti_l3_throughput__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: $L3Misses 64 UMUL */
   uint64_t tmp0 = ehl__compute_l3_cache__l3_misses__read(perf, query, results) * 64;

   return tmp0;
}

/* Compute Metrics L3 Cache set :: GTI L3 Throughput */
#define ehl__compute_l3_cache__gti_l3_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define ehl__compute_l3_cache__gti_read_throughput__read \
   icl__compute_l3_cache__gti_read_throughput__read

/* Compute Metrics L3 Cache set :: GTI Read Throughput */
#define ehl__compute_l3_cache__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define ehl__compute_l3_cache__gti_write_throughput__read \
   icl__compute_l3_cache__gti_write_throughput__read

/* Compute Metrics L3 Cache set :: GTI Write Throughput */
#define ehl__compute_l3_cache__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define ehl__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define ehl__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define ehl__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define ehl__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define ehl__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define ehl__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define ehl__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define ehl__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define ehl__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define ehl__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define ehl__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define ehl__render_pipe_profile__eu_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define ehl__render_pipe_profile__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define ehl__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define ehl__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define ehl__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define ehl__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define ehl__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define ehl__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define ehl__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define ehl__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define ehl__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define ehl__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define ehl__render_pipe_profile__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define ehl__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define ehl__render_pipe_profile__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define ehl__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define ehl__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define ehl__render_pipe_profile__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define ehl__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define ehl__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define ehl__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define ehl__render_pipe_profile__vs_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define ehl__render_pipe_profile__hs_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define ehl__render_pipe_profile__ds_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define ehl__render_pipe_profile__gs_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define ehl__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define ehl__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define ehl__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define ehl__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Bottleneck */
#define ehl__render_pipe_profile__early_depth_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define ehl__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define ehl__render_pipe_profile__hs_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define ehl__render_pipe_profile__ds_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define ehl__render_pipe_profile__so_stall__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define ehl__render_pipe_profile__cl_stall__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define ehl__render_pipe_profile__sf_stall__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define ehl__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define ehl__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define ehl__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define ehl__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define ehl__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define ehl__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define ehl__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define ehl__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define ehl__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define ehl__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define ehl__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define ehl__hdc_and_sf__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define ehl__hdc_and_sf__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Both FPU Pipes Active */
#define ehl__hdc_and_sf__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set HDCAndSF :: VS FPU0 Pipe Active */
#define ehl__hdc_and_sf__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set HDCAndSF :: VS FPU1 Pipe Active */
#define ehl__hdc_and_sf__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set HDCAndSF :: VS Send Pipe Active */
#define ehl__hdc_and_sf__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set HDCAndSF :: PS FPU0 Pipe Active */
#define ehl__hdc_and_sf__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set HDCAndSF :: PS FPU1 Pipe Active */
#define ehl__hdc_and_sf__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set HDCAndSF :: PS Send Pipeline Active */
#define ehl__hdc_and_sf__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set HDCAndSF :: FS Both FPU Active */
#define ehl__hdc_and_sf__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define ehl__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define ehl__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define ehl__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define ehl__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define ehl__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define ehl__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define ehl__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define ehl__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define ehl__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define ehl__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define ehl__hdc_and_sf__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define ehl__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define ehl__hdc_and_sf__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define ehl__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define ehl__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define ehl__hdc_and_sf__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define ehl__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define ehl__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Slice0 Subslice group 0 Non-sampler Shader Access Stalled On L3 */
#define ehl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   icl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read

/* Metric set HDCAndSF :: Slice0 Subslice group 1 Non-sampler Shader Access Stalled On L3 */
#define ehl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   icl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read

/* Metric set HDCAndSF :: Slice0 Subslice group 2 Non-sampler Shader Access Stalled On L3 */
#define ehl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   icl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read

/* Metric set HDCAndSF :: Slice0 Subslice group 3 Non-sampler Shader Access Stalled On L3 */
#define ehl__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read \
   icl__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define ehl__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: SQ is full */
#define ehl__hdc_and_sf__gt_request_queue_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define ehl__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define ehl__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define ehl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define ehl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define ehl__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define ehl__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define ehl__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define ehl__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define ehl__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define ehl__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define ehl__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define ehl__rasterizer_and_pixel_backend__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define ehl__rasterizer_and_pixel_backend__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */
#define ehl__rasterizer_and_pixel_backend__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */
#define ehl__rasterizer_and_pixel_backend__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */
#define ehl__rasterizer_and_pixel_backend__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */
#define ehl__rasterizer_and_pixel_backend__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */
#define ehl__rasterizer_and_pixel_backend__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */
#define ehl__rasterizer_and_pixel_backend__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */
#define ehl__rasterizer_and_pixel_backend__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */
#define ehl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define ehl__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define ehl__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define ehl__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define ehl__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define ehl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define ehl__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define ehl__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define ehl__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define ehl__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define ehl__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define ehl__rasterizer_and_pixel_backend__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define ehl__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define ehl__rasterizer_and_pixel_backend__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define ehl__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define ehl__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define ehl__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define ehl__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define ehl__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define ehl__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define ehl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define ehl__rasterizer_and_pixel_backend__pixel_data00_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 Post-EarlyZ Pixel Data Ready */
#define ehl__rasterizer_and_pixel_backend__pixel_data01_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 PS Output Available */
#define ehl__rasterizer_and_pixel_backend__ps_output00_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 PS Output Available */
#define ehl__rasterizer_and_pixel_backend__ps_output01_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Pixel Values Ready */
#define ehl__rasterizer_and_pixel_backend__pixel_values00_ready__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 Pixel Values Ready */
#define ehl__rasterizer_and_pixel_backend__pixel_values01_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ is full */
#define ehl__rasterizer_and_pixel_backend__gt_request_queue_full__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: GPU Time Elapsed */
#define ehl__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set L3_1 :: GPU Core Clocks */
#define ehl__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define ehl__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set L3_1 :: AVG GPU Core Frequency */
#define ehl__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set L3_1 :: GPU Busy */
#define ehl__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set L3_1 :: VS Threads Dispatched */
#define ehl__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set L3_1 :: HS Threads Dispatched */
#define ehl__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set L3_1 :: DS Threads Dispatched */
#define ehl__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set L3_1 :: GS Threads Dispatched */
#define ehl__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set L3_1 :: FS Threads Dispatched */
#define ehl__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set L3_1 :: CS Threads Dispatched */
#define ehl__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set L3_1 :: EU Active */
#define ehl__l3_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set L3_1 :: EU Stall */
#define ehl__l3_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set L3_1 :: EU Both FPU Pipes Active */
#define ehl__l3_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set L3_1 :: VS FPU0 Pipe Active */
#define ehl__l3_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set L3_1 :: VS FPU1 Pipe Active */
#define ehl__l3_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set L3_1 :: VS Send Pipe Active */
#define ehl__l3_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set L3_1 :: PS FPU0 Pipe Active */
#define ehl__l3_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set L3_1 :: PS FPU1 Pipe Active */
#define ehl__l3_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set L3_1 :: PS Send Pipeline Active */
#define ehl__l3_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set L3_1 :: FS Both FPU Active */
#define ehl__l3_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set L3_1 :: Rasterized Pixels */
#define ehl__l3_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set L3_1 :: Early Hi-Depth Test Fails */
#define ehl__l3_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set L3_1 :: Early Depth Test Fails */
#define ehl__l3_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Samples Killed in FS */
#define ehl__l3_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set L3_1 :: Pixels Failing Tests */
#define ehl__l3_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set L3_1 :: Samples Written */
#define ehl__l3_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set L3_1 :: Samples Blended */
#define ehl__l3_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set L3_1 :: Sampler Texels */
#define ehl__l3_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set L3_1 :: Sampler Texels Misses */
#define ehl__l3_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set L3_1 :: SLM Bytes Read */
#define ehl__l3_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set L3_1 :: SLM Bytes Read */
#define ehl__l3_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: SLM Bytes Written */
#define ehl__l3_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set L3_1 :: SLM Bytes Written */
#define ehl__l3_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Memory Accesses */
#define ehl__l3_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set L3_1 :: Shader Atomic Memory Accesses */
#define ehl__l3_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define ehl__l3_1__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Metric set L3_1 :: L3 Shader Throughput */
#define ehl__l3_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set L3_1 :: Shader Barrier Messages */
#define ehl__l3_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set L3_1 :: Slice0 L3 Bank0 Active */
#define ehl__l3_1__l30_bank0_active__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank1 Active */
#define ehl__l3_1__l30_bank1_active__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank2 Active */
#define ehl__l3_1__l30_bank2_active__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank3 Active */
#define ehl__l3_1__l30_bank3_active__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank4 Active */
#define ehl__l3_1__l30_bank4_active__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank5 Active */
#define ehl__l3_1__l30_bank5_active__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set L3_1 :: Slice0 L3 Bank6 Active */
#define ehl__l3_1__l30_bank6_active__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set L3_1 :: Slice0 L3 Bank7 Active */
#define ehl__l3_1__l30_bank7_active__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set L3_1 :: SQ is full */
#define ehl__l3_1__gt_request_queue_full__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L2Bank0 stalled metric set :: GPU Time Elapsed */
#define ehl__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L2Bank0 stalled metric set :: GPU Core Clocks */
#define ehl__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L2Bank0 stalled metric set :: AVG GPU Core Frequency */
#define ehl__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L2Bank0 stalled metric set :: AVG GPU Core Frequency */
#define ehl__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L2Bank0 stalled metric set :: GPU Busy */
#define ehl__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L2Bank0 stalled metric set :: VS Threads Dispatched */
#define ehl__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L2Bank0 stalled metric set :: HS Threads Dispatched */
#define ehl__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L2Bank0 stalled metric set :: DS Threads Dispatched */
#define ehl__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L2Bank0 stalled metric set :: GS Threads Dispatched */
#define ehl__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L2Bank0 stalled metric set :: FS Threads Dispatched */
#define ehl__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L2Bank0 stalled metric set :: CS Threads Dispatched */
#define ehl__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L2Bank0 stalled metric set :: Rasterized Pixels */
#define ehl__l3_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* L2Bank0 stalled metric set :: Early Hi-Depth Test Fails */
#define ehl__l3_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* L2Bank0 stalled metric set :: Early Depth Test Fails */
#define ehl__l3_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* L2Bank0 stalled metric set :: Samples Killed in FS */
#define ehl__l3_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* L2Bank0 stalled metric set :: Pixels Failing Tests */
#define ehl__l3_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* L2Bank0 stalled metric set :: Samples Written */
#define ehl__l3_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* L2Bank0 stalled metric set :: Samples Blended */
#define ehl__l3_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* L2Bank0 stalled metric set :: EU Active */
#define ehl__l3_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* L2Bank0 stalled metric set :: EU Stall */
#define ehl__l3_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* L2Bank0 stalled metric set :: EU Both FPU Pipes Active */
#define ehl__l3_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* L2Bank0 stalled metric set :: EU Thread Occupancy */
#define ehl__l3_2__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* L2Bank0 stalled metric set :: VS FPU0 Pipe Active */
#define ehl__l3_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* L2Bank0 stalled metric set :: VS FPU1 Pipe Active */
#define ehl__l3_2__vs_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* L2Bank0 stalled metric set :: VS Send Pipe Active */
#define ehl__l3_2__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* L2Bank0 stalled metric set :: PS FPU0 Pipe Active */
#define ehl__l3_2__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* L2Bank0 stalled metric set :: PS FPU1 Pipe Active */
#define ehl__l3_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* L2Bank0 stalled metric set :: PS Send Pipeline Active */
#define ehl__l3_2__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* L2Bank0 stalled metric set :: FS Both FPU Active */
#define ehl__l3_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_send_active__read

/* L2Bank0 stalled metric set :: Slice0 L3 Bank0 Stalled */
#define ehl__l3_2__l30_bank0_stalled__read \
   icl__l3_2__l30_bank0_stalled__read

/* L2Bank1 stalled metric set :: GPU Time Elapsed */
#define ehl__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L2Bank1 stalled metric set :: GPU Core Clocks */
#define ehl__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L2Bank1 stalled metric set :: AVG GPU Core Frequency */
#define ehl__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L2Bank1 stalled metric set :: AVG GPU Core Frequency */
#define ehl__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L2Bank1 stalled metric set :: GPU Busy */
#define ehl__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L2Bank1 stalled metric set :: VS Threads Dispatched */
#define ehl__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L2Bank1 stalled metric set :: HS Threads Dispatched */
#define ehl__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L2Bank1 stalled metric set :: DS Threads Dispatched */
#define ehl__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L2Bank1 stalled metric set :: GS Threads Dispatched */
#define ehl__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L2Bank1 stalled metric set :: FS Threads Dispatched */
#define ehl__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L2Bank1 stalled metric set :: CS Threads Dispatched */
#define ehl__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L2Bank1 stalled metric set :: Rasterized Pixels */
#define ehl__l3_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* L2Bank1 stalled metric set :: Early Hi-Depth Test Fails */
#define ehl__l3_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* L2Bank1 stalled metric set :: Early Depth Test Fails */
#define ehl__l3_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* L2Bank1 stalled metric set :: Samples Killed in FS */
#define ehl__l3_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* L2Bank1 stalled metric set :: Pixels Failing Tests */
#define ehl__l3_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* L2Bank1 stalled metric set :: Samples Written */
#define ehl__l3_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* L2Bank1 stalled metric set :: Samples Blended */
#define ehl__l3_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* L2Bank1 stalled metric set :: EU Active */
#define ehl__l3_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* L2Bank1 stalled metric set :: EU Stall */
#define ehl__l3_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* L2Bank1 stalled metric set :: EU Both FPU Pipes Active */
#define ehl__l3_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* L2Bank1 stalled metric set :: EU Thread Occupancy */
#define ehl__l3_3__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* L2Bank1 stalled metric set :: VS FPU0 Pipe Active */
#define ehl__l3_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* L2Bank1 stalled metric set :: VS FPU1 Pipe Active */
#define ehl__l3_3__vs_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* L2Bank1 stalled metric set :: VS Send Pipe Active */
#define ehl__l3_3__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* L2Bank1 stalled metric set :: PS FPU0 Pipe Active */
#define ehl__l3_3__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* L2Bank1 stalled metric set :: PS FPU1 Pipe Active */
#define ehl__l3_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* L2Bank1 stalled metric set :: PS Send Pipeline Active */
#define ehl__l3_3__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* L2Bank1 stalled metric set :: FS Both FPU Active */
#define ehl__l3_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_send_active__read

/* L2Bank1 stalled metric set :: Slice0 L3 Bank1 Stalled */
#define ehl__l3_3__l30_bank1_stalled__read \
   icl__l3_2__l30_bank0_stalled__read

/* L2Bank4 stalled metric set :: GPU Time Elapsed */
#define ehl__l3_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L2Bank4 stalled metric set :: GPU Core Clocks */
#define ehl__l3_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L2Bank4 stalled metric set :: AVG GPU Core Frequency */
#define ehl__l3_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L2Bank4 stalled metric set :: AVG GPU Core Frequency */
#define ehl__l3_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L2Bank4 stalled metric set :: GPU Busy */
#define ehl__l3_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L2Bank4 stalled metric set :: VS Threads Dispatched */
#define ehl__l3_4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L2Bank4 stalled metric set :: HS Threads Dispatched */
#define ehl__l3_4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L2Bank4 stalled metric set :: DS Threads Dispatched */
#define ehl__l3_4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L2Bank4 stalled metric set :: GS Threads Dispatched */
#define ehl__l3_4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L2Bank4 stalled metric set :: FS Threads Dispatched */
#define ehl__l3_4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L2Bank4 stalled metric set :: CS Threads Dispatched */
#define ehl__l3_4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L2Bank4 stalled metric set :: Rasterized Pixels */
#define ehl__l3_4__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* L2Bank4 stalled metric set :: Early Hi-Depth Test Fails */
#define ehl__l3_4__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* L2Bank4 stalled metric set :: Early Depth Test Fails */
#define ehl__l3_4__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* L2Bank4 stalled metric set :: Samples Killed in FS */
#define ehl__l3_4__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* L2Bank4 stalled metric set :: Pixels Failing Tests */
#define ehl__l3_4__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* L2Bank4 stalled metric set :: Samples Written */
#define ehl__l3_4__samples_written__read \
   bdw__render_basic__samples_written__read

/* L2Bank4 stalled metric set :: Samples Blended */
#define ehl__l3_4__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* L2Bank4 stalled metric set :: EU Active */
#define ehl__l3_4__eu_active__read \
   bdw__render_basic__eu_active__read

/* L2Bank4 stalled metric set :: EU Stall */
#define ehl__l3_4__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* L2Bank4 stalled metric set :: EU Both FPU Pipes Active */
#define ehl__l3_4__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* L2Bank4 stalled metric set :: EU Thread Occupancy */
#define ehl__l3_4__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* L2Bank4 stalled metric set :: VS FPU0 Pipe Active */
#define ehl__l3_4__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* L2Bank4 stalled metric set :: VS FPU1 Pipe Active */
#define ehl__l3_4__vs_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* L2Bank4 stalled metric set :: VS Send Pipe Active */
#define ehl__l3_4__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* L2Bank4 stalled metric set :: PS FPU0 Pipe Active */
#define ehl__l3_4__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* L2Bank4 stalled metric set :: PS FPU1 Pipe Active */
#define ehl__l3_4__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* L2Bank4 stalled metric set :: PS Send Pipeline Active */
#define ehl__l3_4__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* L2Bank4 stalled metric set :: FS Both FPU Active */
#define ehl__l3_4__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_send_active__read

/* L2Bank4 stalled metric set :: Slice0 L3 Bank4 Stalled */
#define ehl__l3_4__l30_bank4_stalled__read \
   icl__l3_2__l30_bank0_stalled__read

/* L2Bank5 stalled metric set :: GPU Time Elapsed */
#define ehl__l3_5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L2Bank5 stalled metric set :: GPU Core Clocks */
#define ehl__l3_5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L2Bank5 stalled metric set :: AVG GPU Core Frequency */
#define ehl__l3_5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L2Bank5 stalled metric set :: AVG GPU Core Frequency */
#define ehl__l3_5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L2Bank5 stalled metric set :: GPU Busy */
#define ehl__l3_5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L2Bank5 stalled metric set :: VS Threads Dispatched */
#define ehl__l3_5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L2Bank5 stalled metric set :: HS Threads Dispatched */
#define ehl__l3_5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L2Bank5 stalled metric set :: DS Threads Dispatched */
#define ehl__l3_5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L2Bank5 stalled metric set :: GS Threads Dispatched */
#define ehl__l3_5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L2Bank5 stalled metric set :: FS Threads Dispatched */
#define ehl__l3_5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L2Bank5 stalled metric set :: CS Threads Dispatched */
#define ehl__l3_5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L2Bank5 stalled metric set :: Rasterized Pixels */
#define ehl__l3_5__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* L2Bank5 stalled metric set :: Early Hi-Depth Test Fails */
#define ehl__l3_5__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* L2Bank5 stalled metric set :: Early Depth Test Fails */
#define ehl__l3_5__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* L2Bank5 stalled metric set :: Samples Killed in FS */
#define ehl__l3_5__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* L2Bank5 stalled metric set :: Pixels Failing Tests */
#define ehl__l3_5__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* L2Bank5 stalled metric set :: Samples Written */
#define ehl__l3_5__samples_written__read \
   bdw__render_basic__samples_written__read

/* L2Bank5 stalled metric set :: Samples Blended */
#define ehl__l3_5__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* L2Bank5 stalled metric set :: EU Active */
#define ehl__l3_5__eu_active__read \
   bdw__render_basic__eu_active__read

/* L2Bank5 stalled metric set :: EU Stall */
#define ehl__l3_5__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* L2Bank5 stalled metric set :: EU Both FPU Pipes Active */
#define ehl__l3_5__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* L2Bank5 stalled metric set :: EU Thread Occupancy */
#define ehl__l3_5__eu_thread_occupancy__read \
   bdw__vme_pipe__eu_thread_occupancy__read

/* L2Bank5 stalled metric set :: VS FPU0 Pipe Active */
#define ehl__l3_5__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* L2Bank5 stalled metric set :: VS FPU1 Pipe Active */
#define ehl__l3_5__vs_fpu1_active__read \
   bdw__render_basic__vs_send_active__read

/* L2Bank5 stalled metric set :: VS Send Pipe Active */
#define ehl__l3_5__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* L2Bank5 stalled metric set :: PS FPU0 Pipe Active */
#define ehl__l3_5__ps_fpu0_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* L2Bank5 stalled metric set :: PS FPU1 Pipe Active */
#define ehl__l3_5__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* L2Bank5 stalled metric set :: PS Send Pipeline Active */
#define ehl__l3_5__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* L2Bank5 stalled metric set :: FS Both FPU Active */
#define ehl__l3_5__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_send_active__read

/* L2Bank5 stalled metric set :: Slice0 L3 Bank5 Stalled */
#define ehl__l3_5__l30_bank5_stalled__read \
   icl__l3_5__l30_bank5_stalled__read

/* Metric set Sampler 1 :: GPU Time Elapsed */
#define ehl__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler 1 :: GPU Core Clocks */
#define ehl__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler 1 :: AVG GPU Core Frequency */
#define ehl__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler 1 :: AVG GPU Core Frequency */
#define ehl__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler 1 :: GPU Busy */
#define ehl__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler 1 :: VS Threads Dispatched */
#define ehl__sampler_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler 1 :: HS Threads Dispatched */
#define ehl__sampler_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler 1 :: DS Threads Dispatched */
#define ehl__sampler_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler 1 :: GS Threads Dispatched */
#define ehl__sampler_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler 1 :: FS Threads Dispatched */
#define ehl__sampler_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler 1 :: CS Threads Dispatched */
#define ehl__sampler_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler 1 :: EU Active */
#define ehl__sampler_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler 1 :: EU Stall */
#define ehl__sampler_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler 1 :: EU Both FPU Pipes Active */
#define ehl__sampler_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler 1 :: VS FPU0 Pipe Active */
#define ehl__sampler_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler 1 :: VS FPU1 Pipe Active */
#define ehl__sampler_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler 1 :: VS Send Pipe Active */
#define ehl__sampler_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler 1 :: PS FPU0 Pipe Active */
#define ehl__sampler_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler 1 :: PS FPU1 Pipe Active */
#define ehl__sampler_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler 1 :: PS Send Pipeline Active */
#define ehl__sampler_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler 1 :: FS Both FPU Active */
#define ehl__sampler_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler 1 :: Rasterized Pixels */
#define ehl__sampler_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler 1 :: Early Hi-Depth Test Fails */
#define ehl__sampler_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler 1 :: Early Depth Test Fails */
#define ehl__sampler_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler 1 :: Samples Killed in FS */
#define ehl__sampler_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler 1 :: Pixels Failing Tests */
#define ehl__sampler_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler 1 :: Samples Written */
#define ehl__sampler_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler 1 :: Samples Blended */
#define ehl__sampler_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler 1 :: Sampler Texels */
#define ehl__sampler_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler 1 :: Sampler Texels Misses */
#define ehl__sampler_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler 1 :: SLM Bytes Read */
#define ehl__sampler_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler 1 :: SLM Bytes Read */
#define ehl__sampler_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 1 :: SLM Bytes Written */
#define ehl__sampler_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler 1 :: SLM Bytes Written */
#define ehl__sampler_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 1 :: Shader Memory Accesses */
#define ehl__sampler_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler 1 :: Shader Atomic Memory Accesses */
#define ehl__sampler_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler 1 :: L3 Shader Throughput */
#define ehl__sampler_1__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Metric set Sampler 1 :: L3 Shader Throughput */
#define ehl__sampler_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 1 :: Shader Barrier Messages */
#define ehl__sampler_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler 1 :: Slice0 Subslice0 Input Available */
#define ehl__sampler_1__sampler00_input_available__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice1 Input Available */
#define ehl__sampler_1__sampler01_input_available__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice2 Input Available */
#define ehl__sampler_1__sampler02_input_available__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice3 Input Available */
#define ehl__sampler_1__sampler03_input_available__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice4 Input Available */
#define ehl__sampler_1__sampler04_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice5 Input Available */
#define ehl__sampler_1__sampler05_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set Sampler 1 :: Slice0 Subslice6 Input Available */
#define ehl__sampler_1__sampler06_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set Sampler 1 :: Slice0 Subslice7 Input Available */
#define ehl__sampler_1__sampler07_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set Sampler 2 :: GPU Time Elapsed */
#define ehl__sampler_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set Sampler 2 :: GPU Core Clocks */
#define ehl__sampler_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set Sampler 2 :: AVG GPU Core Frequency */
#define ehl__sampler_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set Sampler 2 :: AVG GPU Core Frequency */
#define ehl__sampler_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set Sampler 2 :: GPU Busy */
#define ehl__sampler_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set Sampler 2 :: VS Threads Dispatched */
#define ehl__sampler_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set Sampler 2 :: HS Threads Dispatched */
#define ehl__sampler_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set Sampler 2 :: DS Threads Dispatched */
#define ehl__sampler_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set Sampler 2 :: GS Threads Dispatched */
#define ehl__sampler_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set Sampler 2 :: FS Threads Dispatched */
#define ehl__sampler_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set Sampler 2 :: CS Threads Dispatched */
#define ehl__sampler_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set Sampler 2 :: EU Active */
#define ehl__sampler_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set Sampler 2 :: EU Stall */
#define ehl__sampler_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set Sampler 2 :: EU Both FPU Pipes Active */
#define ehl__sampler_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set Sampler 2 :: VS FPU0 Pipe Active */
#define ehl__sampler_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set Sampler 2 :: VS FPU1 Pipe Active */
#define ehl__sampler_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set Sampler 2 :: VS Send Pipe Active */
#define ehl__sampler_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set Sampler 2 :: PS FPU0 Pipe Active */
#define ehl__sampler_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set Sampler 2 :: PS FPU1 Pipe Active */
#define ehl__sampler_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set Sampler 2 :: PS Send Pipeline Active */
#define ehl__sampler_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set Sampler 2 :: FS Both FPU Active */
#define ehl__sampler_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set Sampler 2 :: Rasterized Pixels */
#define ehl__sampler_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set Sampler 2 :: Early Hi-Depth Test Fails */
#define ehl__sampler_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set Sampler 2 :: Early Depth Test Fails */
#define ehl__sampler_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set Sampler 2 :: Samples Killed in FS */
#define ehl__sampler_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set Sampler 2 :: Pixels Failing Tests */
#define ehl__sampler_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set Sampler 2 :: Samples Written */
#define ehl__sampler_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set Sampler 2 :: Samples Blended */
#define ehl__sampler_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set Sampler 2 :: Sampler Texels */
#define ehl__sampler_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set Sampler 2 :: Sampler Texels Misses */
#define ehl__sampler_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set Sampler 2 :: SLM Bytes Read */
#define ehl__sampler_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set Sampler 2 :: SLM Bytes Read */
#define ehl__sampler_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 2 :: SLM Bytes Written */
#define ehl__sampler_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set Sampler 2 :: SLM Bytes Written */
#define ehl__sampler_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 2 :: Shader Memory Accesses */
#define ehl__sampler_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set Sampler 2 :: Shader Atomic Memory Accesses */
#define ehl__sampler_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set Sampler 2 :: L3 Shader Throughput */
#define ehl__sampler_2__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Metric set Sampler 2 :: L3 Shader Throughput */
#define ehl__sampler_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set Sampler 2 :: Shader Barrier Messages */
#define ehl__sampler_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set Sampler 2 :: Slice0 Subslice0 Sampler Output Ready */
#define ehl__sampler_2__sampler00_output_ready__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set Sampler 2 :: Slice0 Subslice1 Sampler Output Ready */
#define ehl__sampler_2__sampler01_output_ready__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice2 Sampler Output Ready */
#define ehl__sampler_2__sampler02_output_ready__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice3 Sampler Output Ready */
#define ehl__sampler_2__sampler03_output_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice4 Sampler Output Ready */
#define ehl__sampler_2__sampler04_output_ready__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice5 Sampler Output Ready */
#define ehl__sampler_2__sampler05_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set Sampler 2 :: Slice0 Subslice6 Sampler Output Ready */
#define ehl__sampler_2__sampler06_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set Sampler 2 :: Slice0 Subslice7 Sampler Output Ready */
#define ehl__sampler_2__sampler07_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set Sampler 2 :: SQ is full */
#define ehl__sampler_2__gt_request_queue_full__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set TDL_1 :: GPU Time Elapsed */
#define ehl__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_1 :: GPU Core Clocks */
#define ehl__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define ehl__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_1 :: AVG GPU Core Frequency */
#define ehl__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_1 :: GPU Busy */
#define ehl__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_1 :: VS Threads Dispatched */
#define ehl__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_1 :: HS Threads Dispatched */
#define ehl__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_1 :: DS Threads Dispatched */
#define ehl__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_1 :: GS Threads Dispatched */
#define ehl__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_1 :: FS Threads Dispatched */
#define ehl__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_1 :: CS Threads Dispatched */
#define ehl__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_1 :: EU Active */
#define ehl__tdl_1__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_1 :: EU Stall */
#define ehl__tdl_1__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_1 :: EU Both FPU Pipes Active */
#define ehl__tdl_1__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_1 :: VS FPU0 Pipe Active */
#define ehl__tdl_1__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_1 :: VS FPU1 Pipe Active */
#define ehl__tdl_1__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_1 :: VS Send Pipe Active */
#define ehl__tdl_1__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_1 :: VS EU Active */
#define ehl__tdl_1__vs_eu_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Metric set TDL_1 :: VS AVG Active per Thread */
#define ehl__tdl_1__vs_eu_active_per_thread__read \
   icl__tdl_1__vs_eu_active_per_thread__read

/* Metric set TDL_1 :: VS EU Stall */
#define ehl__tdl_1__vs_eu_stall__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Metric set TDL_1 :: VS AVG Stall per Thread */
#define ehl__tdl_1__vs_eu_stall_per_thread__read \
   icl__tdl_1__vs_eu_stall_per_thread__read

/* Metric set TDL_1 :: PS FPU0 Pipe Active */
#define ehl__tdl_1__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_1 :: PS FPU1 Pipe Active */
#define ehl__tdl_1__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_1 :: PS Send Pipeline Active */
#define ehl__tdl_1__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_1 :: FS Both FPU Active */
#define ehl__tdl_1__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_1 :: FS EU Active */
#define ehl__tdl_1__ps_eu_active__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* Metric set TDL_1 :: FS AVG Active per Thread */
#define ehl__tdl_1__ps_eu_active_per_thread__read \
   icl__tdl_1__ps_eu_active_per_thread__read

/* Metric set TDL_1 :: FS EU Stall */
#define ehl__tdl_1__ps_eu_stall__read \
   bdw__compute_l3_cache__eu_move_fpu1_instruction__read

/* Metric set TDL_1 :: FS AVG Stall per Thread */
#define ehl__tdl_1__ps_eu_stall_per_thread__read \
   icl__tdl_1__ps_eu_stall_per_thread__read

/* Metric set TDL_1 :: Rasterized Pixels */
#define ehl__tdl_1__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_1 :: Early Hi-Depth Test Fails */
#define ehl__tdl_1__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_1 :: Early Depth Test Fails */
#define ehl__tdl_1__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: Samples Killed in FS */
#define ehl__tdl_1__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_1 :: Pixels Failing Tests */
#define ehl__tdl_1__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_1 :: Samples Written */
#define ehl__tdl_1__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_1 :: Samples Blended */
#define ehl__tdl_1__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_1 :: Sampler Texels */
#define ehl__tdl_1__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_1 :: Sampler Texels Misses */
#define ehl__tdl_1__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define ehl__tdl_1__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_1 :: SLM Bytes Read */
#define ehl__tdl_1__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: SLM Bytes Written */
#define ehl__tdl_1__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_1 :: SLM Bytes Written */
#define ehl__tdl_1__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Memory Accesses */
#define ehl__tdl_1__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_1 :: Shader Atomic Memory Accesses */
#define ehl__tdl_1__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define ehl__tdl_1__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Metric set TDL_1 :: L3 Shader Throughput */
#define ehl__tdl_1__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_1 :: Shader Barrier Messages */
#define ehl__tdl_1__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher */
#define ehl__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher */
#define ehl__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher */
#define ehl__tdl_1__ps_thread02_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher */
#define ehl__tdl_1__ps_thread03_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher */
#define ehl__tdl_1__ps_thread04_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher */
#define ehl__tdl_1__ps_thread05_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher */
#define ehl__tdl_1__ps_thread06_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher */
#define ehl__tdl_1__ps_thread07_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_2 :: GPU Time Elapsed */
#define ehl__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_2 :: GPU Core Clocks */
#define ehl__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define ehl__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_2 :: AVG GPU Core Frequency */
#define ehl__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_2 :: GPU Busy */
#define ehl__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_2 :: VS Threads Dispatched */
#define ehl__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_2 :: HS Threads Dispatched */
#define ehl__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_2 :: DS Threads Dispatched */
#define ehl__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_2 :: GS Threads Dispatched */
#define ehl__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_2 :: FS Threads Dispatched */
#define ehl__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_2 :: CS Threads Dispatched */
#define ehl__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_2 :: EU Active */
#define ehl__tdl_2__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_2 :: EU Stall */
#define ehl__tdl_2__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_2 :: EU Both FPU Pipes Active */
#define ehl__tdl_2__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_2 :: VS FPU0 Pipe Active */
#define ehl__tdl_2__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_2 :: VS FPU1 Pipe Active */
#define ehl__tdl_2__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_2 :: VS Send Pipe Active */
#define ehl__tdl_2__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_2 :: PS FPU0 Pipe Active */
#define ehl__tdl_2__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_2 :: PS FPU1 Pipe Active */
#define ehl__tdl_2__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_2 :: PS Send Pipeline Active */
#define ehl__tdl_2__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_2 :: FS Both FPU Active */
#define ehl__tdl_2__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_2 :: Rasterized Pixels */
#define ehl__tdl_2__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_2 :: Early Hi-Depth Test Fails */
#define ehl__tdl_2__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_2 :: Early Depth Test Fails */
#define ehl__tdl_2__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Samples Killed in FS */
#define ehl__tdl_2__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_2 :: Pixels Failing Tests */
#define ehl__tdl_2__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_2 :: Samples Written */
#define ehl__tdl_2__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_2 :: Samples Blended */
#define ehl__tdl_2__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_2 :: Sampler Texels */
#define ehl__tdl_2__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_2 :: Sampler Texels Misses */
#define ehl__tdl_2__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define ehl__tdl_2__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_2 :: SLM Bytes Read */
#define ehl__tdl_2__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: SLM Bytes Written */
#define ehl__tdl_2__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_2 :: SLM Bytes Written */
#define ehl__tdl_2__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Memory Accesses */
#define ehl__tdl_2__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_2 :: Shader Atomic Memory Accesses */
#define ehl__tdl_2__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define ehl__tdl_2__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Metric set TDL_2 :: L3 Shader Throughput */
#define ehl__tdl_2__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_2 :: Shader Barrier Messages */
#define ehl__tdl_2__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher */
#define ehl__tdl_2__non_ps_thread00_ready_for_dispatch__read \
   icl__tdl_2__non_ps_thread00_ready_for_dispatch__read

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher */
#define ehl__tdl_2__non_ps_thread01_ready_for_dispatch__read \
   icl__tdl_2__non_ps_thread01_ready_for_dispatch__read

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher */
#define ehl__tdl_2__non_ps_thread02_ready_for_dispatch__read \
   icl__tdl_2__non_ps_thread02_ready_for_dispatch__read

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher */
#define ehl__tdl_2__non_ps_thread03_ready_for_dispatch__read \
   icl__tdl_2__non_ps_thread03_ready_for_dispatch__read

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher */
#define ehl__tdl_2__non_ps_thread04_ready_for_dispatch__read \
   icl__tdl_2__non_ps_thread04_ready_for_dispatch__read

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher */
#define ehl__tdl_2__non_ps_thread05_ready_for_dispatch__read \
   icl__tdl_2__non_ps_thread05_ready_for_dispatch__read

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher */
#define ehl__tdl_2__non_ps_thread06_ready_for_dispatch__read \
   icl__tdl_2__non_ps_thread06_ready_for_dispatch__read

/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher */
#define ehl__tdl_2__non_ps_thread07_ready_for_dispatch__read \
   icl__tdl_2__non_ps_thread07_ready_for_dispatch__read

/* Metric set TDL_2 :: SQ is full */
#define ehl__tdl_2__gt_request_queue_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set TDL_3 :: GPU Time Elapsed */
#define ehl__tdl_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TDL_3 :: GPU Core Clocks */
#define ehl__tdl_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TDL_3 :: AVG GPU Core Frequency */
#define ehl__tdl_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TDL_3 :: AVG GPU Core Frequency */
#define ehl__tdl_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TDL_3 :: GPU Busy */
#define ehl__tdl_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set TDL_3 :: VS Threads Dispatched */
#define ehl__tdl_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set TDL_3 :: HS Threads Dispatched */
#define ehl__tdl_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set TDL_3 :: DS Threads Dispatched */
#define ehl__tdl_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set TDL_3 :: GS Threads Dispatched */
#define ehl__tdl_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set TDL_3 :: FS Threads Dispatched */
#define ehl__tdl_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set TDL_3 :: CS Threads Dispatched */
#define ehl__tdl_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set TDL_3 :: EU Active */
#define ehl__tdl_3__eu_active__read \
   bdw__render_basic__eu_active__read

/* Metric set TDL_3 :: EU Stall */
#define ehl__tdl_3__eu_stall__read \
   bdw__render_basic__eu_stall__read

/* Metric set TDL_3 :: EU Both FPU Pipes Active */
#define ehl__tdl_3__eu_fpu_both_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Metric set TDL_3 :: VS FPU0 Pipe Active */
#define ehl__tdl_3__vs_fpu0_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Metric set TDL_3 :: VS FPU1 Pipe Active */
#define ehl__tdl_3__vs_fpu1_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Metric set TDL_3 :: VS Send Pipe Active */
#define ehl__tdl_3__vs_send_active__read \
   bdw__render_basic__vs_send_active__read

/* Metric set TDL_3 :: PS FPU0 Pipe Active */
#define ehl__tdl_3__ps_fpu0_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Metric set TDL_3 :: PS FPU1 Pipe Active */
#define ehl__tdl_3__ps_fpu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Metric set TDL_3 :: PS Send Pipeline Active */
#define ehl__tdl_3__ps_send_active__read \
   bdw__render_basic__ps_send_active__read

/* Metric set TDL_3 :: FS Both FPU Active */
#define ehl__tdl_3__ps_eu_both_fpu_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Metric set TDL_3 :: Rasterized Pixels */
#define ehl__tdl_3__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set TDL_3 :: Early Hi-Depth Test Fails */
#define ehl__tdl_3__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set TDL_3 :: Early Depth Test Fails */
#define ehl__tdl_3__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set TDL_3 :: Samples Killed in FS */
#define ehl__tdl_3__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set TDL_3 :: Pixels Failing Tests */
#define ehl__tdl_3__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set TDL_3 :: Samples Written */
#define ehl__tdl_3__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set TDL_3 :: Samples Blended */
#define ehl__tdl_3__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set TDL_3 :: Sampler Texels */
#define ehl__tdl_3__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set TDL_3 :: Sampler Texels Misses */
#define ehl__tdl_3__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set TDL_3 :: SLM Bytes Read */
#define ehl__tdl_3__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set TDL_3 :: SLM Bytes Read */
#define ehl__tdl_3__slm_bytes_read__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_3 :: SLM Bytes Written */
#define ehl__tdl_3__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set TDL_3 :: SLM Bytes Written */
#define ehl__tdl_3__slm_bytes_written__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_3 :: Shader Memory Accesses */
#define ehl__tdl_3__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set TDL_3 :: Shader Atomic Memory Accesses */
#define ehl__tdl_3__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set TDL_3 :: L3 Shader Throughput */
#define ehl__tdl_3__l3_shader_throughput__read \
   ehl__render_basic__l3_shader_throughput__read

/* Metric set TDL_3 :: L3 Shader Throughput */
#define ehl__tdl_3__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set TDL_3 :: Shader Barrier Messages */
#define ehl__tdl_3__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 0 */
#define ehl__tdl_3__thread_header00_ready_port0__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 1 */
#define ehl__tdl_3__thread_header00_ready_port1__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 0 */
#define ehl__tdl_3__thread_header01_ready_port0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 1 */
#define ehl__tdl_3__thread_header01_ready_port1__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 0 */
#define ehl__tdl_3__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 1 */
#define ehl__tdl_3__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 0 */
#define ehl__tdl_3__thread_header03_ready_port0__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 1 */
#define ehl__tdl_3__thread_header03_ready_port1__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 0 */
#define ehl__tdl_3__thread_header04_ready_port0__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 1 */
#define ehl__tdl_3__thread_header04_ready_port1__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 0 */
#define ehl__tdl_3__thread_header05_ready_port0__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 1 */
#define ehl__tdl_3__thread_header05_ready_port1__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 0 */
#define ehl__tdl_3__thread_header06_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 1 */
#define ehl__tdl_3__thread_header06_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 0 */
#define ehl__tdl_3__thread_header07_ready_port0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 1 */
#define ehl__tdl_3__thread_header07_ready_port1__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: GPU Time Elapsed */
#define ehl__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Gpu Rings Busyness :: GPU Core Clocks */
#define ehl__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define ehl__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Gpu Rings Busyness :: AVG GPU Core Frequency */
#define ehl__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Gpu Rings Busyness :: GPU Busy */
#define ehl__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Gpu Rings Busyness :: Render Ring Busy */
#define ehl__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Gpu Rings Busyness :: Vdbox0 Ring Busy */
#define ehl__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Gpu Rings Busyness :: Vdbox1 Ring Busy */
#define ehl__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Gpu Rings Busyness :: Vebox Ring Busy */
#define ehl__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* Gpu Rings Busyness :: Blitter Ring Busy */
#define ehl__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* Gpu Rings Busyness :: AnyRingBusy */
#define ehl__gpu_busyness__any_ring_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TestOa :: GPU Time Elapsed */
#define ehl__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define ehl__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define ehl__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define ehl__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define ehl__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define ehl__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define ehl__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define ehl__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define ehl__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define ehl__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define ehl__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define ehl__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define ehl__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define tglgt1__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define tglgt1__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define tglgt1__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define tglgt1__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define tglgt1__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define tglgt1__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define tglgt1__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define tglgt1__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define tglgt1__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define tglgt1__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define tglgt1__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
static float
tglgt1__render_basic__eu_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ A 8 READ FADD A 9 READ FADD A 10 READ FADD $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];
   uint64_t tmp1 = results->accumulator[query->a_offset + 8];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 9];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->a_offset + 10];
   double tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = tmp6;
   uint64_t tmp8 = perf->sys_vars.n_eus;
   uint64_t tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = tglgt1__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* Render Metrics Basic set :: EU Stall */
static float
tglgt1__render_basic__eu_stall__read(UNUSED struct intel_perf_config *perf,
                                     const struct intel_perf_query_info *query,
                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 11 READ A 12 READ FADD A 13 READ FADD A 14 READ FADD $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 11];
   uint64_t tmp1 = results->accumulator[query->a_offset + 12];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 13];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->a_offset + 14];
   double tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = tmp6;
   uint64_t tmp8 = perf->sys_vars.n_eus;
   uint64_t tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = tglgt1__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* Render Metrics Basic set :: EU Thread Occupancy */
static float
tglgt1__render_basic__eu_thread_occupancy__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: 8 A 15 READ A 16 READ FADD A 17 READ FADD A 18 READ FADD FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 15];
   uint64_t tmp1 = results->accumulator[query->a_offset + 16];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 17];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->a_offset + 18];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = 8 * tmp6;
   double tmp8 = tmp7;
   double tmp9 = perf->devinfo.num_thread_per_eu;
   double tmp10 = tmp9 ? tmp8 / tmp9 : 0;
   uint64_t tmp11 = tmp10;
   uint64_t tmp12 = perf->sys_vars.n_eus;
   uint64_t tmp13 = tmp12 ? tmp11 / tmp12 : 0;
   uint64_t tmp14 = tmp13 * 100;
   double tmp15 = tmp14;
   double tmp16 = tglgt1__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp17 = tmp16 ? tmp15 / tmp16 : 0;

   return tmp17;
}

/* Render Metrics Basic set :: Sampler00 Busy */
#define tglgt1__render_basic__sampler00_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler Slice0 Dualsubslice0 is bottleneck */
#define tglgt1__render_basic__sampler00_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define tglgt1__render_basic__samplers_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Samplers Bottleneck */
#define tglgt1__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define tglgt1__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define tglgt1__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define tglgt1__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define tglgt1__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define tglgt1__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define tglgt1__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define tglgt1__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define tglgt1__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define tglgt1__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define tglgt1__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
static uint64_t
tglgt1__render_basic__slm_bytes_read__max(struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 128 UMUL $EuSubslicesTotalCount UMUL */
   uint64_t tmp0 = tglgt1__render_basic__gpu_core_clocks__read(perf, query, results) * 128;
   uint64_t tmp1 = tmp0 * perf->sys_vars.n_eu_sub_slices;

   return tmp1;
}

/* Render Metrics Basic set :: SLM Bytes Written */
#define tglgt1__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define tglgt1__render_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define tglgt1__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define tglgt1__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define tglgt1__render_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define tglgt1__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define tglgt1__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Read Throughput */
static uint64_t
tglgt1__render_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  C 5 READ C 4 READ UADD C 3 READ UADD C 2 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = results->accumulator[query->c_offset + 4];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 3];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 2];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = 64 * tmp6;

   return tmp7;
}

/* Render Metrics Basic set :: GTI Read Throughput */
#define tglgt1__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
static uint64_t
tglgt1__render_basic__gti_write_throughput__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  C 1 READ C 0 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 0];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = 64 * tmp2;

   return tmp3;
}

/* Render Metrics Basic set :: GTI Write Throughput */
#define tglgt1__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define tglgt1__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define tglgt1__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define tglgt1__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define tglgt1__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define tglgt1__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define tglgt1__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define tglgt1__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define tglgt1__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define tglgt1__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define tglgt1__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define tglgt1__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define tglgt1__compute_basic__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define tglgt1__compute_basic__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define tglgt1__compute_basic__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define tglgt1__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define tglgt1__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define tglgt1__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define tglgt1__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define tglgt1__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define tglgt1__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define tglgt1__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define tglgt1__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define tglgt1__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define tglgt1__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define tglgt1__compute_basic__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define tglgt1__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define tglgt1__compute_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define tglgt1__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define tglgt1__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define tglgt1__compute_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define tglgt1__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define tglgt1__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: GTI Read Throughput */
static uint64_t
tglgt1__compute_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  C 7 READ C 6 READ UADD C 5 READ UADD C 4 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = 64 * tmp6;

   return tmp7;
}

/* Compute Metrics Basic set :: GTI Read Throughput */
#define tglgt1__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
static uint64_t
tglgt1__compute_basic__gti_write_throughput__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  C 3 READ C 2 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = 64 * tmp2;

   return tmp3;
}

/* Compute Metrics Basic set :: GTI Write Throughput */
#define tglgt1__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define tglgt1__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define tglgt1__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define tglgt1__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define tglgt1__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define tglgt1__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define tglgt1__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define tglgt1__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define tglgt1__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define tglgt1__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define tglgt1__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define tglgt1__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define tglgt1__render_pipe_profile__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define tglgt1__render_pipe_profile__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: EU Thread Occupancy */
#define tglgt1__render_pipe_profile__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define tglgt1__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define tglgt1__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define tglgt1__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define tglgt1__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define tglgt1__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define tglgt1__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define tglgt1__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define tglgt1__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define tglgt1__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define tglgt1__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define tglgt1__render_pipe_profile__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define tglgt1__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define tglgt1__render_pipe_profile__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define tglgt1__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define tglgt1__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define tglgt1__render_pipe_profile__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define tglgt1__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define tglgt1__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define tglgt1__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define tglgt1__render_pipe_profile__vs_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define tglgt1__render_pipe_profile__hs_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define tglgt1__render_pipe_profile__ds_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define tglgt1__render_pipe_profile__gs_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define tglgt1__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define tglgt1__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define tglgt1__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define tglgt1__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define tglgt1__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define tglgt1__render_pipe_profile__hs_stall__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define tglgt1__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define tglgt1__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define tglgt1__render_pipe_profile__cl_stall__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define tglgt1__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define tglgt1__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define tglgt1__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define tglgt1__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define tglgt1__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define tglgt1__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define tglgt1__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define tglgt1__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define tglgt1__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define tglgt1__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define tglgt1__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define tglgt1__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define tglgt1__hdc_and_sf__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define tglgt1__hdc_and_sf__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Thread Occupancy */
#define tglgt1__hdc_and_sf__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define tglgt1__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define tglgt1__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define tglgt1__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define tglgt1__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define tglgt1__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define tglgt1__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define tglgt1__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define tglgt1__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define tglgt1__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define tglgt1__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define tglgt1__hdc_and_sf__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define tglgt1__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define tglgt1__hdc_and_sf__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define tglgt1__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define tglgt1__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define tglgt1__hdc_and_sf__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define tglgt1__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define tglgt1__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3 */
#define tglgt1__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3 */
#define tglgt1__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define tglgt1__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define tglgt1__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define tglgt1__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define tglgt1__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define tglgt1__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define tglgt1__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define tglgt1__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define tglgt1__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define tglgt1__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define tglgt1__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define tglgt1__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define tglgt1__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define tglgt1__rasterizer_and_pixel_backend__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define tglgt1__rasterizer_and_pixel_backend__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Thread Occupancy */
#define tglgt1__rasterizer_and_pixel_backend__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define tglgt1__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define tglgt1__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define tglgt1__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define tglgt1__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define tglgt1__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define tglgt1__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define tglgt1__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define tglgt1__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define tglgt1__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define tglgt1__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define tglgt1__rasterizer_and_pixel_backend__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define tglgt1__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define tglgt1__rasterizer_and_pixel_backend__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define tglgt1__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define tglgt1__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define tglgt1__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define tglgt1__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define tglgt1__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define tglgt1__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define tglgt1__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define tglgt1__rasterizer_and_pixel_backend__pixel_data00_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 PS Output Available */
#define tglgt1__rasterizer_and_pixel_backend__ps_output00_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Pixel Values Ready */
#define tglgt1__rasterizer_and_pixel_backend__pixel_values00_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: SQ00 is full */
#define tglgt1__rasterizer_and_pixel_backend__gt_request_queue00_full__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ01 is full */
#define tglgt1__rasterizer_and_pixel_backend__gt_request_queue01_full__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ10 is full */
#define tglgt1__rasterizer_and_pixel_backend__gt_request_queue10_full__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ11 is full */
#define tglgt1__rasterizer_and_pixel_backend__gt_request_queue11_full__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3_1 :: GPU Time Elapsed */
#define tglgt1__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_1 :: GPU Core Clocks */
#define tglgt1__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_1 :: AVG GPU Core Frequency */
#define tglgt1__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_1 :: AVG GPU Core Frequency */
#define tglgt1__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_1 :: GPU Busy */
#define tglgt1__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_1 :: EU Active */
#define tglgt1__l3_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_1 :: EU Stall */
#define tglgt1__l3_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_1 :: EU Thread Occupancy */
#define tglgt1__l3_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_1 :: VS Threads Dispatched */
#define tglgt1__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_1 :: HS Threads Dispatched */
#define tglgt1__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_1 :: DS Threads Dispatched */
#define tglgt1__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_1 :: GS Threads Dispatched */
#define tglgt1__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_1 :: FS Threads Dispatched */
#define tglgt1__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_1 :: CS Threads Dispatched */
#define tglgt1__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_1 :: Slice0 L3 Bank0 Input Available */
static float
tglgt1__l3_1__l30_bank0_input_available__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ C 1 READ FADD C 2 READ FADD C 3 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 2];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 3];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = tglgt1__l3_1__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* L3_1 :: Slice0 L3 Bank1 Input Available */
static float
tglgt1__l3_1__l30_bank1_input_available__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ C 5 READ FADD C 6 READ FADD C 7 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 6];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 7];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = tglgt1__l3_1__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* L3_2 :: GPU Time Elapsed */
#define tglgt1__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_2 :: GPU Core Clocks */
#define tglgt1__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_2 :: AVG GPU Core Frequency */
#define tglgt1__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_2 :: AVG GPU Core Frequency */
#define tglgt1__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_2 :: GPU Busy */
#define tglgt1__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_2 :: VS Threads Dispatched */
#define tglgt1__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_2 :: HS Threads Dispatched */
#define tglgt1__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_2 :: DS Threads Dispatched */
#define tglgt1__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_2 :: GS Threads Dispatched */
#define tglgt1__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_2 :: FS Threads Dispatched */
#define tglgt1__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_2 :: CS Threads Dispatched */
#define tglgt1__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_2 :: EU Active */
#define tglgt1__l3_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_2 :: EU Stall */
#define tglgt1__l3_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_2 :: EU Thread Occupancy */
#define tglgt1__l3_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_2 :: Slice0 L3 Bank2 Input Available */
static float
tglgt1__l3_2__l30_bank2_input_available__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ B 2 READ FADD B 1 READ FADD B 0 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = results->accumulator[query->b_offset + 2];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 1];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 0];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = tglgt1__l3_2__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* L3_2 :: Slice0 L3 Bank3 Input Available */
static float
tglgt1__l3_2__l30_bank3_input_available__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 6 READ FADD B 5 READ FADD B 4 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 5];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 4];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = tglgt1__l3_2__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* L3_3 :: GPU Time Elapsed */
#define tglgt1__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_3 :: GPU Core Clocks */
#define tglgt1__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_3 :: AVG GPU Core Frequency */
#define tglgt1__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_3 :: AVG GPU Core Frequency */
#define tglgt1__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_3 :: GPU Busy */
#define tglgt1__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_3 :: VS Threads Dispatched */
#define tglgt1__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_3 :: HS Threads Dispatched */
#define tglgt1__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_3 :: DS Threads Dispatched */
#define tglgt1__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_3 :: GS Threads Dispatched */
#define tglgt1__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_3 :: FS Threads Dispatched */
#define tglgt1__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_3 :: CS Threads Dispatched */
#define tglgt1__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_3 :: EU Active */
#define tglgt1__l3_3__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_3 :: EU Stall */
#define tglgt1__l3_3__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_3 :: EU Thread Occupancy */
#define tglgt1__l3_3__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_3 :: Slice0 L3 Bank0 Output Ready */
static float
tglgt1__l3_3__l30_bank0_output_ready__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 4;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = tglgt1__l3_3__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* L3_4 :: GPU Time Elapsed */
#define tglgt1__l3_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_4 :: GPU Core Clocks */
#define tglgt1__l3_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_4 :: AVG GPU Core Frequency */
#define tglgt1__l3_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_4 :: AVG GPU Core Frequency */
#define tglgt1__l3_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_4 :: GPU Busy */
#define tglgt1__l3_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_4 :: VS Threads Dispatched */
#define tglgt1__l3_4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_4 :: HS Threads Dispatched */
#define tglgt1__l3_4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_4 :: DS Threads Dispatched */
#define tglgt1__l3_4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_4 :: GS Threads Dispatched */
#define tglgt1__l3_4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_4 :: FS Threads Dispatched */
#define tglgt1__l3_4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_4 :: CS Threads Dispatched */
#define tglgt1__l3_4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_4 :: EU Active */
#define tglgt1__l3_4__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_4 :: EU Stall */
#define tglgt1__l3_4__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_4 :: EU Thread Occupancy */
#define tglgt1__l3_4__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_4 :: Slice0 L3 Bank1 Output Ready */
static float
tglgt1__l3_4__l30_bank1_output_ready__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ C 4 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = results->accumulator[query->c_offset + 4];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 4;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = tglgt1__l3_4__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* L3_5 :: GPU Time Elapsed */
#define tglgt1__l3_5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_5 :: GPU Core Clocks */
#define tglgt1__l3_5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_5 :: AVG GPU Core Frequency */
#define tglgt1__l3_5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_5 :: AVG GPU Core Frequency */
#define tglgt1__l3_5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_5 :: GPU Busy */
#define tglgt1__l3_5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_5 :: VS Threads Dispatched */
#define tglgt1__l3_5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_5 :: HS Threads Dispatched */
#define tglgt1__l3_5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_5 :: DS Threads Dispatched */
#define tglgt1__l3_5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_5 :: GS Threads Dispatched */
#define tglgt1__l3_5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_5 :: FS Threads Dispatched */
#define tglgt1__l3_5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_5 :: CS Threads Dispatched */
#define tglgt1__l3_5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_5 :: EU Active */
#define tglgt1__l3_5__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_5 :: EU Stall */
#define tglgt1__l3_5__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_5 :: EU Thread Occupancy */
#define tglgt1__l3_5__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_5 :: Slice0 L3 Bank2 Output Ready */
#define tglgt1__l3_5__l30_bank2_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_6 :: GPU Time Elapsed */
#define tglgt1__l3_6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_6 :: GPU Core Clocks */
#define tglgt1__l3_6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_6 :: AVG GPU Core Frequency */
#define tglgt1__l3_6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_6 :: AVG GPU Core Frequency */
#define tglgt1__l3_6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_6 :: GPU Busy */
#define tglgt1__l3_6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_6 :: VS Threads Dispatched */
#define tglgt1__l3_6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_6 :: HS Threads Dispatched */
#define tglgt1__l3_6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_6 :: DS Threads Dispatched */
#define tglgt1__l3_6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_6 :: GS Threads Dispatched */
#define tglgt1__l3_6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_6 :: FS Threads Dispatched */
#define tglgt1__l3_6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_6 :: CS Threads Dispatched */
#define tglgt1__l3_6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_6 :: EU Active */
#define tglgt1__l3_6__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_6 :: EU Stall */
#define tglgt1__l3_6__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_6 :: EU Thread Occupancy */
#define tglgt1__l3_6__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_6 :: Slice0 L3 Bank3 Output Ready */
#define tglgt1__l3_6__l30_bank3_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* Sampler_1 :: GPU Time Elapsed */
#define tglgt1__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_1 :: GPU Core Clocks */
#define tglgt1__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define tglgt1__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define tglgt1__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_1 :: GPU Busy */
#define tglgt1__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_1 :: VS Threads Dispatched */
#define tglgt1__sampler_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Sampler_1 :: HS Threads Dispatched */
#define tglgt1__sampler_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Sampler_1 :: DS Threads Dispatched */
#define tglgt1__sampler_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Sampler_1 :: GS Threads Dispatched */
#define tglgt1__sampler_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Sampler_1 :: FS Threads Dispatched */
#define tglgt1__sampler_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Sampler_1 :: CS Threads Dispatched */
#define tglgt1__sampler_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Sampler_1 :: EU Active */
#define tglgt1__sampler_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Sampler_1 :: EU Stall */
#define tglgt1__sampler_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Sampler_1 :: EU Thread Occupancy */
#define tglgt1__sampler_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Sampler_1 :: Slice0 DualSubslice0 Input Available */
#define tglgt1__sampler_1__sampler00_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_1 :: Slice0 DualSubslice1 Input Available */
#define tglgt1__sampler_1__sampler01_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_1 :: Slice0 DualSubslice0 Sampler Output Ready */
#define tglgt1__sampler_1__sampler00_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice1 Sampler Output Ready */
#define tglgt1__sampler_1__sampler01_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_1 :: GPU Time Elapsed */
#define tglgt1__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_1 :: GPU Core Clocks */
#define tglgt1__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_1 :: AVG GPU Core Frequency */
#define tglgt1__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_1 :: AVG GPU Core Frequency */
#define tglgt1__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_1 :: GPU Busy */
#define tglgt1__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_1 :: VS Threads Dispatched */
#define tglgt1__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_1 :: HS Threads Dispatched */
#define tglgt1__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_1 :: DS Threads Dispatched */
#define tglgt1__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_1 :: GS Threads Dispatched */
#define tglgt1__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_1 :: FS Threads Dispatched */
#define tglgt1__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_1 :: CS Threads Dispatched */
#define tglgt1__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_1 :: EU Active */
#define tglgt1__tdl_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_1 :: EU Stall */
#define tglgt1__tdl_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_1 :: EU Thread Occupancy */
#define tglgt1__tdl_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice0 Thread Dispatcher */
#define tglgt1__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice1 Thread Dispatcher */
#define tglgt1__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_1 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice0 Thread Dispatcher */
#define tglgt1__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_1 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice1 Thread Dispatcher */
#define tglgt1__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 0 */
#define tglgt1__tdl_1__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 1 */
#define tglgt1__tdl_1__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 2 */
#define tglgt1__tdl_1__thread_header00_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 3 */
#define tglgt1__tdl_1__thread_header00_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 0 */
#define tglgt1__tdl_1__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 1 */
#define tglgt1__tdl_1__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 2 */
#define tglgt1__tdl_1__thread_header01_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 3 */
#define tglgt1__tdl_1__thread_header01_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher */
#define tglgt1__tdl_1__thread_header00_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher */
#define tglgt1__tdl_1__thread_header01_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* GpuBusyness :: GPU Time Elapsed */
#define tglgt1__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define tglgt1__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define tglgt1__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define tglgt1__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define tglgt1__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: EU Active */
#define tglgt1__gpu_busyness__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* GpuBusyness :: EU Stall */
#define tglgt1__gpu_busyness__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* GpuBusyness :: EU Thread Occupancy */
#define tglgt1__gpu_busyness__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* GpuBusyness :: VS Threads Dispatched */
#define tglgt1__gpu_busyness__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* GpuBusyness :: HS Threads Dispatched */
#define tglgt1__gpu_busyness__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* GpuBusyness :: DS Threads Dispatched */
#define tglgt1__gpu_busyness__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* GpuBusyness :: GS Threads Dispatched */
#define tglgt1__gpu_busyness__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* GpuBusyness :: FS Threads Dispatched */
#define tglgt1__gpu_busyness__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* GpuBusyness :: CS Threads Dispatched */
#define tglgt1__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define tglgt1__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* GpuBusyness :: Compute Ring Busy */
#define tglgt1__gpu_busyness__compute_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* GpuBusyness :: Posh Ring Busy */
#define tglgt1__gpu_busyness__posh_engine_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* GpuBusyness :: Blitter Ring Busy */
#define tglgt1__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* GpuBusyness :: Vebox Ring Busy */
#define tglgt1__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: Vdbox0 Ring Busy */
#define tglgt1__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* GpuBusyness :: Vdbox1 Ring Busy */
#define tglgt1__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__ds_stall__read

/* GpuBusyness :: Render and compute engines are simultaneously busy */
#define tglgt1__gpu_busyness__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* GpuBusyness :: Any Engine Busy */
#define tglgt1__gpu_busyness__any_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* EuActivity1 :: GPU Time Elapsed */
#define tglgt1__eu_activity1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity1 :: GPU Core Clocks */
#define tglgt1__eu_activity1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity1 :: GPU Busy */
#define tglgt1__eu_activity1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity1 :: VS Threads Dispatched */
#define tglgt1__eu_activity1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity1 :: HS Threads Dispatched */
#define tglgt1__eu_activity1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity1 :: DS Threads Dispatched */
#define tglgt1__eu_activity1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity1 :: GS Threads Dispatched */
#define tglgt1__eu_activity1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity1 :: FS Threads Dispatched */
#define tglgt1__eu_activity1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity1 :: CS Threads Dispatched */
#define tglgt1__eu_activity1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity1 :: Render Ring Busy */
#define tglgt1__eu_activity1__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity1 :: Compute Ring Busy */
#define tglgt1__eu_activity1__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity1 :: Render and compute engines are simultaneously busy */
#define tglgt1__eu_activity1__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity1 :: GTI Read Throughput */
#define tglgt1__eu_activity1__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity1 :: GTI Read Throughput */
#define tglgt1__eu_activity1__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity1 :: GTI Write Throughput */
#define tglgt1__eu_activity1__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity1 :: GTI Write Throughput */
#define tglgt1__eu_activity1__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity1 :: VS FPU Pipe Active */
#define tglgt1__eu_activity1__vs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity1 :: PS FPU Pipe Active */
#define tglgt1__eu_activity1__ps_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity1 :: EU Send Pipe Active */
static float
tglgt1__eu_activity1__eu_send_active__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: A 15 READ A 16 READ FADD A 17 READ FADD A 18 READ FADD $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 15];
   uint64_t tmp1 = results->accumulator[query->a_offset + 16];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 17];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->a_offset + 18];
   double tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = tmp6;
   uint64_t tmp8 = perf->sys_vars.n_eus;
   uint64_t tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = tglgt1__eu_activity1__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* EuActivity2 :: GPU Time Elapsed */
#define tglgt1__eu_activity2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity2 :: GPU Core Clocks */
#define tglgt1__eu_activity2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity2 :: GPU Busy */
#define tglgt1__eu_activity2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity2 :: VS Threads Dispatched */
#define tglgt1__eu_activity2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity2 :: HS Threads Dispatched */
#define tglgt1__eu_activity2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity2 :: DS Threads Dispatched */
#define tglgt1__eu_activity2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity2 :: GS Threads Dispatched */
#define tglgt1__eu_activity2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity2 :: FS Threads Dispatched */
#define tglgt1__eu_activity2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity2 :: CS Threads Dispatched */
#define tglgt1__eu_activity2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity2 :: Render Ring Busy */
#define tglgt1__eu_activity2__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity2 :: Compute Ring Busy */
#define tglgt1__eu_activity2__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity2 :: Render and compute engines are simultaneously busy */
#define tglgt1__eu_activity2__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity2 :: GTI Read Throughput */
#define tglgt1__eu_activity2__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity2 :: GTI Read Throughput */
#define tglgt1__eu_activity2__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity2 :: GTI Write Throughput */
#define tglgt1__eu_activity2__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity2 :: GTI Write Throughput */
#define tglgt1__eu_activity2__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity2 :: CS EM Pipe Active */
#define tglgt1__eu_activity2__cs_em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity2 :: CS FPU Pipe Active */
#define tglgt1__eu_activity2__cs_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity2 :: CS Send Pipeline Active */
#define tglgt1__eu_activity2__cs_send_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: GPU Time Elapsed */
#define tglgt1__eu_activity3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity3 :: GPU Core Clocks */
#define tglgt1__eu_activity3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity3 :: GPU Busy */
#define tglgt1__eu_activity3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity3 :: VS Threads Dispatched */
#define tglgt1__eu_activity3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity3 :: HS Threads Dispatched */
#define tglgt1__eu_activity3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity3 :: DS Threads Dispatched */
#define tglgt1__eu_activity3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity3 :: GS Threads Dispatched */
#define tglgt1__eu_activity3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity3 :: FS Threads Dispatched */
#define tglgt1__eu_activity3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity3 :: CS Threads Dispatched */
#define tglgt1__eu_activity3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity3 :: Render Ring Busy */
#define tglgt1__eu_activity3__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity3 :: Compute Ring Busy */
#define tglgt1__eu_activity3__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity3 :: Render and compute engines are simultaneously busy */
#define tglgt1__eu_activity3__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity3 :: GTI Read Throughput */
#define tglgt1__eu_activity3__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity3 :: GTI Read Throughput */
#define tglgt1__eu_activity3__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity3 :: GTI Write Throughput */
#define tglgt1__eu_activity3__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity3 :: GTI Write Throughput */
#define tglgt1__eu_activity3__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity3 :: VS EM Pipe Active */
#define tglgt1__eu_activity3__vs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: PS EM Pipe Active */
#define tglgt1__eu_activity3__ps_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity3 :: PS Send Pipeline Active */
#define tglgt1__eu_activity3__ps_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity4 :: GPU Time Elapsed */
#define tglgt1__eu_activity4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity4 :: GPU Core Clocks */
#define tglgt1__eu_activity4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity4 :: GPU Busy */
#define tglgt1__eu_activity4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity4 :: VS Threads Dispatched */
#define tglgt1__eu_activity4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity4 :: HS Threads Dispatched */
#define tglgt1__eu_activity4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity4 :: DS Threads Dispatched */
#define tglgt1__eu_activity4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity4 :: GS Threads Dispatched */
#define tglgt1__eu_activity4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity4 :: FS Threads Dispatched */
#define tglgt1__eu_activity4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity4 :: CS Threads Dispatched */
#define tglgt1__eu_activity4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity4 :: Render Ring Busy */
#define tglgt1__eu_activity4__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity4 :: Compute Ring Busy */
#define tglgt1__eu_activity4__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity4 :: Render and compute engines are simultaneously busy */
#define tglgt1__eu_activity4__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity4 :: GTI Read Throughput */
#define tglgt1__eu_activity4__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity4 :: GTI Read Throughput */
#define tglgt1__eu_activity4__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity4 :: GTI Write Throughput */
#define tglgt1__eu_activity4__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity4 :: GTI Write Throughput */
#define tglgt1__eu_activity4__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity4 :: HS FPU Pipe Active */
#define tglgt1__eu_activity4__hs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity4 :: DS FPU Pipe Active */
#define tglgt1__eu_activity4__ds_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity4 :: VS Send Pipe Active */
#define tglgt1__eu_activity4__vs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity5 :: GPU Time Elapsed */
#define tglgt1__eu_activity5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity5 :: GPU Core Clocks */
#define tglgt1__eu_activity5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity5 :: GPU Busy */
#define tglgt1__eu_activity5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity5 :: VS Threads Dispatched */
#define tglgt1__eu_activity5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity5 :: HS Threads Dispatched */
#define tglgt1__eu_activity5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity5 :: DS Threads Dispatched */
#define tglgt1__eu_activity5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity5 :: GS Threads Dispatched */
#define tglgt1__eu_activity5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity5 :: FS Threads Dispatched */
#define tglgt1__eu_activity5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity5 :: CS Threads Dispatched */
#define tglgt1__eu_activity5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity5 :: Render Ring Busy */
#define tglgt1__eu_activity5__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity5 :: Compute Ring Busy */
#define tglgt1__eu_activity5__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity5 :: Render and compute engines are simultaneously busy */
#define tglgt1__eu_activity5__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity5 :: GTI Read Throughput */
#define tglgt1__eu_activity5__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity5 :: GTI Read Throughput */
#define tglgt1__eu_activity5__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity5 :: GTI Write Throughput */
#define tglgt1__eu_activity5__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity5 :: GTI Write Throughput */
#define tglgt1__eu_activity5__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity5 :: HS EM Pipe Active */
#define tglgt1__eu_activity5__hs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity5 :: DS EM Pipe Active */
#define tglgt1__eu_activity5__ds_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity5 :: HS Send Pipe Active */
#define tglgt1__eu_activity5__hs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity6 :: GPU Time Elapsed */
#define tglgt1__eu_activity6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity6 :: GPU Core Clocks */
#define tglgt1__eu_activity6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity6 :: GPU Busy */
#define tglgt1__eu_activity6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity6 :: VS Threads Dispatched */
#define tglgt1__eu_activity6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity6 :: HS Threads Dispatched */
#define tglgt1__eu_activity6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity6 :: DS Threads Dispatched */
#define tglgt1__eu_activity6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity6 :: GS Threads Dispatched */
#define tglgt1__eu_activity6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity6 :: FS Threads Dispatched */
#define tglgt1__eu_activity6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity6 :: CS Threads Dispatched */
#define tglgt1__eu_activity6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity6 :: Render Ring Busy */
#define tglgt1__eu_activity6__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity6 :: Compute Ring Busy */
#define tglgt1__eu_activity6__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity6 :: Render and compute engines are simultaneously busy */
#define tglgt1__eu_activity6__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity6 :: GTI Read Throughput */
#define tglgt1__eu_activity6__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity6 :: GTI Read Throughput */
#define tglgt1__eu_activity6__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity6 :: GTI Write Throughput */
#define tglgt1__eu_activity6__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity6 :: GTI Write Throughput */
#define tglgt1__eu_activity6__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity6 :: GS FPU Pipe Active */
#define tglgt1__eu_activity6__gs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity6 :: GS EM Pipe Active */
#define tglgt1__eu_activity6__gs_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity6 :: GS Send Pipe Active */
#define tglgt1__eu_activity6__gs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: GPU Time Elapsed */
#define tglgt1__eu_activity7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity7 :: GPU Core Clocks */
#define tglgt1__eu_activity7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity7 :: GPU Busy */
#define tglgt1__eu_activity7__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity7 :: VS Threads Dispatched */
#define tglgt1__eu_activity7__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity7 :: HS Threads Dispatched */
#define tglgt1__eu_activity7__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity7 :: DS Threads Dispatched */
#define tglgt1__eu_activity7__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity7 :: GS Threads Dispatched */
#define tglgt1__eu_activity7__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity7 :: FS Threads Dispatched */
#define tglgt1__eu_activity7__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity7 :: CS Threads Dispatched */
#define tglgt1__eu_activity7__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity7 :: EU FPU Pipe Active */
#define tglgt1__eu_activity7__fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity7 :: EM Pipe Active */
#define tglgt1__eu_activity7__em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: EU FPU And EM Pipes Active */
#define tglgt1__eu_activity7__eu_fpu_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity7 :: EU AVG IPC Rate */
static float
tglgt1__eu_activity7__eu_avg_ipc_rate__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ A 8 READ FADD A 9 READ FADD A 10 READ FADD  A 11 READ A 12 READ FADD A 13 READ FADD A 14 READ FADD  A 15 READ A 16 READ FADD A 17 READ FADD A 18 READ FADD FADD  A 7 READ A 8 READ FADD A 9 READ FADD A 10 READ FADD FSUB FDIV 1 FADD */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];
   uint64_t tmp1 = results->accumulator[query->a_offset + 8];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->a_offset + 9];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->a_offset + 10];
   double tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->a_offset + 11];
   uint64_t tmp8 = results->accumulator[query->a_offset + 12];
   double tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->a_offset + 13];
   double tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->a_offset + 14];
   double tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = results->accumulator[query->a_offset + 15];
   uint64_t tmp15 = results->accumulator[query->a_offset + 16];
   double tmp16 = tmp14 + tmp15;
   uint64_t tmp17 = results->accumulator[query->a_offset + 17];
   double tmp18 = tmp16 + tmp17;
   uint64_t tmp19 = results->accumulator[query->a_offset + 18];
   double tmp20 = tmp18 + tmp19;
   double tmp21 = tmp13 + tmp20;
   uint64_t tmp22 = results->accumulator[query->a_offset + 7];
   uint64_t tmp23 = results->accumulator[query->a_offset + 8];
   double tmp24 = tmp22 + tmp23;
   uint64_t tmp25 = results->accumulator[query->a_offset + 9];
   double tmp26 = tmp24 + tmp25;
   uint64_t tmp27 = results->accumulator[query->a_offset + 10];
   double tmp28 = tmp26 + tmp27;
   double tmp29 = tmp21 - tmp28;
   double tmp30 = tmp6;
   double tmp31 = tmp29;
   double tmp32 = tmp31 ? tmp30 / tmp31 : 0;
   double tmp33 = tmp32 + 1;

   return tmp33;
}

/* EuActivity7 :: EU AVG IPC Rate */
#define tglgt1__eu_activity7__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* EuActivity7 :: Render Ring Busy */
#define tglgt1__eu_activity7__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity7 :: Compute Ring Busy */
#define tglgt1__eu_activity7__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity7 :: Render and compute engines are simultaneously busy */
#define tglgt1__eu_activity7__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity7 :: GTI Read Throughput */
#define tglgt1__eu_activity7__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity7 :: GTI Read Throughput */
#define tglgt1__eu_activity7__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity7 :: GTI Write Throughput */
#define tglgt1__eu_activity7__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity7 :: GTI Write Throughput */
#define tglgt1__eu_activity7__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: GPU Time Elapsed */
#define tglgt1__eu_activity8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity8 :: GPU Core Clocks */
#define tglgt1__eu_activity8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define tglgt1__eu_activity8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity8 :: GPU Busy */
#define tglgt1__eu_activity8__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity8 :: VS Threads Dispatched */
#define tglgt1__eu_activity8__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity8 :: HS Threads Dispatched */
#define tglgt1__eu_activity8__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity8 :: DS Threads Dispatched */
#define tglgt1__eu_activity8__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity8 :: GS Threads Dispatched */
#define tglgt1__eu_activity8__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity8 :: FS Threads Dispatched */
#define tglgt1__eu_activity8__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity8 :: CS Threads Dispatched */
#define tglgt1__eu_activity8__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity8 :: Render Ring Busy */
#define tglgt1__eu_activity8__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity8 :: Compute Ring Busy */
#define tglgt1__eu_activity8__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity8 :: Render and compute engines are simultaneously busy */
#define tglgt1__eu_activity8__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity8 :: GTI Read Throughput */
#define tglgt1__eu_activity8__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity8 :: GTI Read Throughput */
#define tglgt1__eu_activity8__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: GTI Write Throughput */
#define tglgt1__eu_activity8__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity8 :: GTI Write Throughput */
#define tglgt1__eu_activity8__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: DS Send Pipe Active */
#define tglgt1__eu_activity8__ds_send_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set TestOa :: GPU Time Elapsed */
#define tglgt1__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define tglgt1__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define tglgt1__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define tglgt1__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define tglgt1__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define tglgt1__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define tglgt1__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define tglgt1__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define tglgt1__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define tglgt1__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define tglgt1__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define tglgt1__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define tglgt1__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define tglgt1__test_oa__counter9__read \
   hsw__compute_extended__untyped_writes0__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define tglgt2__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define tglgt2__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define tglgt2__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define tglgt2__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define tglgt2__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define tglgt2__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define tglgt2__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define tglgt2__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define tglgt2__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define tglgt2__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define tglgt2__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define tglgt2__render_basic__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define tglgt2__render_basic__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Thread Occupancy */
#define tglgt2__render_basic__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Render Metrics Basic set :: Sampler00 Busy */
#define tglgt2__render_basic__sampler00_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler Slice0 Dualsubslice0 is bottleneck */
#define tglgt2__render_basic__sampler00_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define tglgt2__render_basic__samplers_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Samplers Bottleneck */
#define tglgt2__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define tglgt2__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define tglgt2__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define tglgt2__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define tglgt2__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define tglgt2__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define tglgt2__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define tglgt2__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define tglgt2__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define tglgt2__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define tglgt2__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define tglgt2__render_basic__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define tglgt2__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define tglgt2__render_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define tglgt2__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define tglgt2__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define tglgt2__render_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define tglgt2__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define tglgt2__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define tglgt2__render_basic__gti_read_throughput__read \
   tglgt1__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define tglgt2__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define tglgt2__render_basic__gti_write_throughput__read \
   tglgt1__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define tglgt2__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define tglgt2__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define tglgt2__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define tglgt2__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define tglgt2__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define tglgt2__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define tglgt2__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define tglgt2__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define tglgt2__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define tglgt2__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define tglgt2__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define tglgt2__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define tglgt2__compute_basic__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define tglgt2__compute_basic__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define tglgt2__compute_basic__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define tglgt2__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define tglgt2__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define tglgt2__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define tglgt2__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define tglgt2__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define tglgt2__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define tglgt2__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define tglgt2__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define tglgt2__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define tglgt2__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define tglgt2__compute_basic__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define tglgt2__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define tglgt2__compute_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define tglgt2__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define tglgt2__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define tglgt2__compute_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define tglgt2__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define tglgt2__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define tglgt2__compute_basic__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define tglgt2__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define tglgt2__compute_basic__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define tglgt2__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define tglgt2__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define tglgt2__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define tglgt2__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define tglgt2__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define tglgt2__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define tglgt2__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define tglgt2__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define tglgt2__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define tglgt2__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define tglgt2__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define tglgt2__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define tglgt2__render_pipe_profile__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define tglgt2__render_pipe_profile__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: EU Thread Occupancy */
#define tglgt2__render_pipe_profile__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define tglgt2__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define tglgt2__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define tglgt2__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define tglgt2__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define tglgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define tglgt2__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define tglgt2__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define tglgt2__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define tglgt2__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define tglgt2__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define tglgt2__render_pipe_profile__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define tglgt2__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define tglgt2__render_pipe_profile__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define tglgt2__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define tglgt2__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define tglgt2__render_pipe_profile__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define tglgt2__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define tglgt2__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define tglgt2__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define tglgt2__render_pipe_profile__vs_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define tglgt2__render_pipe_profile__hs_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define tglgt2__render_pipe_profile__ds_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define tglgt2__render_pipe_profile__gs_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define tglgt2__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define tglgt2__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define tglgt2__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define tglgt2__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define tglgt2__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define tglgt2__render_pipe_profile__hs_stall__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define tglgt2__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define tglgt2__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define tglgt2__render_pipe_profile__cl_stall__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define tglgt2__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define tglgt2__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define tglgt2__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define tglgt2__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define tglgt2__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define tglgt2__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define tglgt2__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define tglgt2__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define tglgt2__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define tglgt2__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define tglgt2__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define tglgt2__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define tglgt2__hdc_and_sf__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define tglgt2__hdc_and_sf__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Thread Occupancy */
#define tglgt2__hdc_and_sf__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define tglgt2__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define tglgt2__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define tglgt2__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define tglgt2__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define tglgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define tglgt2__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define tglgt2__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define tglgt2__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define tglgt2__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define tglgt2__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define tglgt2__hdc_and_sf__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define tglgt2__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define tglgt2__hdc_and_sf__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define tglgt2__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define tglgt2__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define tglgt2__hdc_and_sf__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define tglgt2__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define tglgt2__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3 */
#define tglgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3 */
#define tglgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice2 Non-sampler Shader Access Stalled On L3 */
#define tglgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice3 Non-sampler Shader Access Stalled On L3 */
#define tglgt2__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice4 Non-sampler Shader Access Stalled On L3 */
#define tglgt2__hdc_and_sf__non_sampler_shader04_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice5 Non-sampler Shader Access Stalled On L3 */
#define tglgt2__hdc_and_sf__non_sampler_shader05_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define tglgt2__hdc_and_sf__poly_data_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define tglgt2__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define tglgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define tglgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define tglgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define tglgt2__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define tglgt2__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define tglgt2__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define tglgt2__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define tglgt2__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define tglgt2__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define tglgt2__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define tglgt2__rasterizer_and_pixel_backend__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define tglgt2__rasterizer_and_pixel_backend__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Thread Occupancy */
#define tglgt2__rasterizer_and_pixel_backend__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define tglgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define tglgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define tglgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define tglgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define tglgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define tglgt2__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define tglgt2__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define tglgt2__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define tglgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define tglgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define tglgt2__rasterizer_and_pixel_backend__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define tglgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define tglgt2__rasterizer_and_pixel_backend__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define tglgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define tglgt2__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define tglgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define tglgt2__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define tglgt2__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define tglgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define tglgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define tglgt2__rasterizer_and_pixel_backend__pixel_data00_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 PS Output Available */
#define tglgt2__rasterizer_and_pixel_backend__ps_output00_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 PS Output Available */
#define tglgt2__rasterizer_and_pixel_backend__ps_output01_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe2 PS Output Available */
#define tglgt2__rasterizer_and_pixel_backend__ps_output02_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Pixel Values Ready */
#define tglgt2__rasterizer_and_pixel_backend__pixel_values00_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 Pixel Values Ready */
#define tglgt2__rasterizer_and_pixel_backend__pixel_values01_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe2 Pixel Values Ready */
#define tglgt2__rasterizer_and_pixel_backend__pixel_values02_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: SQ00 is full */
#define tglgt2__rasterizer_and_pixel_backend__gt_request_queue00_full__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ01 is full */
#define tglgt2__rasterizer_and_pixel_backend__gt_request_queue01_full__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ10 is full */
#define tglgt2__rasterizer_and_pixel_backend__gt_request_queue10_full__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: SQ11 is full */
#define tglgt2__rasterizer_and_pixel_backend__gt_request_queue11_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3_1 :: GPU Time Elapsed */
#define tglgt2__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_1 :: GPU Core Clocks */
#define tglgt2__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_1 :: AVG GPU Core Frequency */
#define tglgt2__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_1 :: AVG GPU Core Frequency */
#define tglgt2__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_1 :: GPU Busy */
#define tglgt2__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_1 :: EU Active */
#define tglgt2__l3_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_1 :: EU Stall */
#define tglgt2__l3_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_1 :: EU Thread Occupancy */
#define tglgt2__l3_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_1 :: VS Threads Dispatched */
#define tglgt2__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_1 :: HS Threads Dispatched */
#define tglgt2__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_1 :: DS Threads Dispatched */
#define tglgt2__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_1 :: GS Threads Dispatched */
#define tglgt2__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_1 :: FS Threads Dispatched */
#define tglgt2__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_1 :: CS Threads Dispatched */
#define tglgt2__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_1 :: Slice0 L3 Bank0 Input Available */
static float
tglgt2__l3_1__l30_bank0_input_available__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ FADD C 5 READ FADD C 4 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = tglgt2__l3_1__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* L3_1 :: Slice0 L3 Bank1 Input Available */
static float
tglgt2__l3_1__l30_bank1_input_available__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ C 2 READ FADD C 1 READ FADD C 0 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 1];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 0];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   uint64_t tmp10 = tmp9 * 100;
   double tmp11 = tmp10;
   double tmp12 = tglgt2__l3_1__gpu_core_clocks__read(perf, query, results);
   double tmp13 = tmp12 ? tmp11 / tmp12 : 0;

   return tmp13;
}

/* L3_1 :: Slice0 L3 Bank4 Input Available */
#define tglgt2__l3_1__l30_bank4_input_available__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L3_1 :: Slice0 L3 Bank5 Input Available */
#define tglgt2__l3_1__l30_bank5_input_available__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L3_2 :: GPU Time Elapsed */
#define tglgt2__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_2 :: GPU Core Clocks */
#define tglgt2__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_2 :: AVG GPU Core Frequency */
#define tglgt2__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_2 :: AVG GPU Core Frequency */
#define tglgt2__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_2 :: GPU Busy */
#define tglgt2__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_2 :: VS Threads Dispatched */
#define tglgt2__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_2 :: HS Threads Dispatched */
#define tglgt2__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_2 :: DS Threads Dispatched */
#define tglgt2__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_2 :: GS Threads Dispatched */
#define tglgt2__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_2 :: FS Threads Dispatched */
#define tglgt2__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_2 :: CS Threads Dispatched */
#define tglgt2__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_2 :: EU Active */
#define tglgt2__l3_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_2 :: EU Stall */
#define tglgt2__l3_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_2 :: EU Thread Occupancy */
#define tglgt2__l3_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_2 :: Slice0 L3 Bank2 Input Available */
#define tglgt2__l3_2__l30_bank2_input_available__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L3_2 :: Slice0 L3 Bank3 Input Available */
#define tglgt2__l3_2__l30_bank3_input_available__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L3_2 :: Slice0 L3 Bank6 Input Available */
#define tglgt2__l3_2__l30_bank6_input_available__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L3_2 :: Slice0 L3 Bank7 Input Available */
#define tglgt2__l3_2__l30_bank7_input_available__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L3_3 :: GPU Time Elapsed */
#define tglgt2__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_3 :: GPU Core Clocks */
#define tglgt2__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_3 :: AVG GPU Core Frequency */
#define tglgt2__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_3 :: AVG GPU Core Frequency */
#define tglgt2__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_3 :: GPU Busy */
#define tglgt2__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_3 :: VS Threads Dispatched */
#define tglgt2__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_3 :: HS Threads Dispatched */
#define tglgt2__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_3 :: DS Threads Dispatched */
#define tglgt2__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_3 :: GS Threads Dispatched */
#define tglgt2__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_3 :: FS Threads Dispatched */
#define tglgt2__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_3 :: CS Threads Dispatched */
#define tglgt2__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_3 :: EU Active */
#define tglgt2__l3_3__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_3 :: EU Stall */
#define tglgt2__l3_3__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_3 :: EU Thread Occupancy */
#define tglgt2__l3_3__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_3 :: Slice0 L3 Bank0 Output Ready */
#define tglgt2__l3_3__l30_bank0_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_3 :: Slice0 L3 Bank4 Output Ready */
#define tglgt2__l3_3__l30_bank4_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_4 :: GPU Time Elapsed */
#define tglgt2__l3_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_4 :: GPU Core Clocks */
#define tglgt2__l3_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_4 :: AVG GPU Core Frequency */
#define tglgt2__l3_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_4 :: AVG GPU Core Frequency */
#define tglgt2__l3_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_4 :: GPU Busy */
#define tglgt2__l3_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_4 :: VS Threads Dispatched */
#define tglgt2__l3_4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_4 :: HS Threads Dispatched */
#define tglgt2__l3_4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_4 :: DS Threads Dispatched */
#define tglgt2__l3_4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_4 :: GS Threads Dispatched */
#define tglgt2__l3_4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_4 :: FS Threads Dispatched */
#define tglgt2__l3_4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_4 :: CS Threads Dispatched */
#define tglgt2__l3_4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_4 :: EU Active */
#define tglgt2__l3_4__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_4 :: EU Stall */
#define tglgt2__l3_4__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_4 :: EU Thread Occupancy */
#define tglgt2__l3_4__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_4 :: Slice0 L3 Bank1 Output Ready */
#define tglgt2__l3_4__l30_bank1_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_4 :: Slice0 L3 Bank5 Output Ready */
#define tglgt2__l3_4__l30_bank5_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_5 :: GPU Time Elapsed */
#define tglgt2__l3_5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_5 :: GPU Core Clocks */
#define tglgt2__l3_5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_5 :: AVG GPU Core Frequency */
#define tglgt2__l3_5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_5 :: AVG GPU Core Frequency */
#define tglgt2__l3_5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_5 :: GPU Busy */
#define tglgt2__l3_5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_5 :: VS Threads Dispatched */
#define tglgt2__l3_5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_5 :: HS Threads Dispatched */
#define tglgt2__l3_5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_5 :: DS Threads Dispatched */
#define tglgt2__l3_5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_5 :: GS Threads Dispatched */
#define tglgt2__l3_5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_5 :: FS Threads Dispatched */
#define tglgt2__l3_5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_5 :: CS Threads Dispatched */
#define tglgt2__l3_5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_5 :: EU Active */
#define tglgt2__l3_5__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_5 :: EU Stall */
#define tglgt2__l3_5__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_5 :: EU Thread Occupancy */
#define tglgt2__l3_5__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_5 :: Slice0 L3 Bank2 Output Ready */
#define tglgt2__l3_5__l30_bank2_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_5 :: Slice0 L3 Bank6 Output Ready */
#define tglgt2__l3_5__l30_bank6_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_6 :: GPU Time Elapsed */
#define tglgt2__l3_6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_6 :: GPU Core Clocks */
#define tglgt2__l3_6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_6 :: AVG GPU Core Frequency */
#define tglgt2__l3_6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_6 :: AVG GPU Core Frequency */
#define tglgt2__l3_6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_6 :: GPU Busy */
#define tglgt2__l3_6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_6 :: VS Threads Dispatched */
#define tglgt2__l3_6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_6 :: HS Threads Dispatched */
#define tglgt2__l3_6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_6 :: DS Threads Dispatched */
#define tglgt2__l3_6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_6 :: GS Threads Dispatched */
#define tglgt2__l3_6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_6 :: FS Threads Dispatched */
#define tglgt2__l3_6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_6 :: CS Threads Dispatched */
#define tglgt2__l3_6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_6 :: EU Active */
#define tglgt2__l3_6__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_6 :: EU Stall */
#define tglgt2__l3_6__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_6 :: EU Thread Occupancy */
#define tglgt2__l3_6__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_6 :: Slice0 L3 Bank3 Output Ready */
#define tglgt2__l3_6__l30_bank3_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_6 :: Slice0 L3 Bank7 Output Ready */
#define tglgt2__l3_6__l30_bank7_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* Sampler_1 :: GPU Time Elapsed */
#define tglgt2__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_1 :: GPU Core Clocks */
#define tglgt2__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define tglgt2__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define tglgt2__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_1 :: GPU Busy */
#define tglgt2__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_1 :: VS Threads Dispatched */
#define tglgt2__sampler_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Sampler_1 :: HS Threads Dispatched */
#define tglgt2__sampler_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Sampler_1 :: DS Threads Dispatched */
#define tglgt2__sampler_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Sampler_1 :: GS Threads Dispatched */
#define tglgt2__sampler_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Sampler_1 :: FS Threads Dispatched */
#define tglgt2__sampler_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Sampler_1 :: CS Threads Dispatched */
#define tglgt2__sampler_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Sampler_1 :: EU Active */
#define tglgt2__sampler_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Sampler_1 :: EU Stall */
#define tglgt2__sampler_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Sampler_1 :: EU Thread Occupancy */
#define tglgt2__sampler_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Sampler_1 :: Slice0 DualSubslice0 Input Available */
#define tglgt2__sampler_1__sampler00_input_available__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice1 Input Available */
#define tglgt2__sampler_1__sampler01_input_available__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice2 Input Available */
#define tglgt2__sampler_1__sampler02_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice3 Input Available */
#define tglgt2__sampler_1__sampler03_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice4 Input Available */
#define tglgt2__sampler_1__sampler04_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_1 :: Slice0 DualSubslice5 Input Available */
#define tglgt2__sampler_1__sampler05_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_2 :: GPU Time Elapsed */
#define tglgt2__sampler_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_2 :: GPU Core Clocks */
#define tglgt2__sampler_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_2 :: AVG GPU Core Frequency */
#define tglgt2__sampler_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_2 :: AVG GPU Core Frequency */
#define tglgt2__sampler_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_2 :: GPU Busy */
#define tglgt2__sampler_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_2 :: VS Threads Dispatched */
#define tglgt2__sampler_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Sampler_2 :: HS Threads Dispatched */
#define tglgt2__sampler_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Sampler_2 :: DS Threads Dispatched */
#define tglgt2__sampler_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Sampler_2 :: GS Threads Dispatched */
#define tglgt2__sampler_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Sampler_2 :: FS Threads Dispatched */
#define tglgt2__sampler_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Sampler_2 :: CS Threads Dispatched */
#define tglgt2__sampler_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Sampler_2 :: EU Active */
#define tglgt2__sampler_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Sampler_2 :: EU Stall */
#define tglgt2__sampler_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Sampler_2 :: EU Thread Occupancy */
#define tglgt2__sampler_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Sampler_2 :: Slice0 DualSubslice0 Sampler Output Ready */
#define tglgt2__sampler_2__sampler00_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice1 Sampler Output Ready */
#define tglgt2__sampler_2__sampler01_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice2 Sampler Output Ready */
#define tglgt2__sampler_2__sampler02_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice3 Sampler Output Ready */
#define tglgt2__sampler_2__sampler03_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice4 Sampler Output Ready */
#define tglgt2__sampler_2__sampler04_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_2 :: Slice0 DualSubslice5 Sampler Output Ready */
#define tglgt2__sampler_2__sampler05_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_1 :: GPU Time Elapsed */
#define tglgt2__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_1 :: GPU Core Clocks */
#define tglgt2__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_1 :: AVG GPU Core Frequency */
#define tglgt2__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_1 :: AVG GPU Core Frequency */
#define tglgt2__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_1 :: GPU Busy */
#define tglgt2__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_1 :: VS Threads Dispatched */
#define tglgt2__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_1 :: HS Threads Dispatched */
#define tglgt2__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_1 :: DS Threads Dispatched */
#define tglgt2__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_1 :: GS Threads Dispatched */
#define tglgt2__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_1 :: FS Threads Dispatched */
#define tglgt2__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_1 :: CS Threads Dispatched */
#define tglgt2__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_1 :: EU Active */
#define tglgt2__tdl_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_1 :: EU Stall */
#define tglgt2__tdl_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_1 :: EU Thread Occupancy */
#define tglgt2__tdl_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice0 Thread Dispatcher */
#define tglgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice1 Thread Dispatcher */
#define tglgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice2 Thread Dispatcher */
#define tglgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice3 Thread Dispatcher */
#define tglgt2__tdl_1__non_ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice4 Thread Dispatcher */
#define tglgt2__tdl_1__non_ps_thread04_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice5 Thread Dispatcher */
#define tglgt2__tdl_1__non_ps_thread05_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 0 */
#define tglgt2__tdl_1__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 1 */
#define tglgt2__tdl_1__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 2 */
#define tglgt2__tdl_1__thread_header00_ready_port2__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 3 */
#define tglgt2__tdl_1__thread_header00_ready_port3__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 0 */
#define tglgt2__tdl_1__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 1 */
#define tglgt2__tdl_1__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 2 */
#define tglgt2__tdl_1__thread_header01_ready_port2__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 3 */
#define tglgt2__tdl_1__thread_header01_ready_port3__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher */
#define tglgt2__tdl_1__thread_header00_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher */
#define tglgt2__tdl_1__thread_header01_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_2 :: GPU Time Elapsed */
#define tglgt2__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_2 :: GPU Core Clocks */
#define tglgt2__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_2 :: AVG GPU Core Frequency */
#define tglgt2__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_2 :: AVG GPU Core Frequency */
#define tglgt2__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_2 :: GPU Busy */
#define tglgt2__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_2 :: VS Threads Dispatched */
#define tglgt2__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_2 :: HS Threads Dispatched */
#define tglgt2__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_2 :: DS Threads Dispatched */
#define tglgt2__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_2 :: GS Threads Dispatched */
#define tglgt2__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_2 :: FS Threads Dispatched */
#define tglgt2__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_2 :: CS Threads Dispatched */
#define tglgt2__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_2 :: EU Active */
#define tglgt2__tdl_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_2 :: EU Stall */
#define tglgt2__tdl_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_2 :: EU Thread Occupancy */
#define tglgt2__tdl_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice0 Thread Dispatcher */
#define tglgt2__tdl_2__ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice1 Thread Dispatcher */
#define tglgt2__tdl_2__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice2 Thread Dispatcher */
#define tglgt2__tdl_2__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice3 Thread Dispatcher */
#define tglgt2__tdl_2__ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice4 Thread Dispatcher */
#define tglgt2__tdl_2__ps_thread04_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice5 Thread Dispatcher */
#define tglgt2__tdl_2__ps_thread05_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher */
#define tglgt2__tdl_2__thread_header05_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 0 */
#define tglgt2__tdl_2__thread_header05_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 1 */
#define tglgt2__tdl_2__thread_header05_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 2 */
#define tglgt2__tdl_2__thread_header05_ready_port2__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 3 */
#define tglgt2__tdl_2__thread_header05_ready_port3__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_3 :: GPU Time Elapsed */
#define tglgt2__tdl_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_3 :: GPU Core Clocks */
#define tglgt2__tdl_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_3 :: AVG GPU Core Frequency */
#define tglgt2__tdl_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_3 :: AVG GPU Core Frequency */
#define tglgt2__tdl_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_3 :: GPU Busy */
#define tglgt2__tdl_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_3 :: VS Threads Dispatched */
#define tglgt2__tdl_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_3 :: HS Threads Dispatched */
#define tglgt2__tdl_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_3 :: DS Threads Dispatched */
#define tglgt2__tdl_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_3 :: GS Threads Dispatched */
#define tglgt2__tdl_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_3 :: FS Threads Dispatched */
#define tglgt2__tdl_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_3 :: CS Threads Dispatched */
#define tglgt2__tdl_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_3 :: EU Active */
#define tglgt2__tdl_3__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_3 :: EU Stall */
#define tglgt2__tdl_3__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_3 :: EU Thread Occupancy */
#define tglgt2__tdl_3__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher */
#define tglgt2__tdl_3__thread_header02_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher */
#define tglgt2__tdl_3__thread_header03_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher */
#define tglgt2__tdl_3__thread_header04_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 0 */
#define tglgt2__tdl_3__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 1 */
#define tglgt2__tdl_3__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 2 */
#define tglgt2__tdl_3__thread_header02_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 3 */
#define tglgt2__tdl_3__thread_header02_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 0 */
#define tglgt2__tdl_3__thread_header03_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 1 */
#define tglgt2__tdl_3__thread_header03_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 2 */
#define tglgt2__tdl_3__thread_header03_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 3 */
#define tglgt2__tdl_3__thread_header03_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 0 */
#define tglgt2__tdl_3__thread_header04_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 1 */
#define tglgt2__tdl_3__thread_header04_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 2 */
#define tglgt2__tdl_3__thread_header04_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 3 */
#define tglgt2__tdl_3__thread_header04_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* GpuBusyness :: GPU Time Elapsed */
#define tglgt2__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define tglgt2__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define tglgt2__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define tglgt2__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define tglgt2__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: EU Active */
#define tglgt2__gpu_busyness__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* GpuBusyness :: EU Stall */
#define tglgt2__gpu_busyness__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* GpuBusyness :: EU Thread Occupancy */
#define tglgt2__gpu_busyness__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* GpuBusyness :: VS Threads Dispatched */
#define tglgt2__gpu_busyness__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* GpuBusyness :: HS Threads Dispatched */
#define tglgt2__gpu_busyness__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* GpuBusyness :: DS Threads Dispatched */
#define tglgt2__gpu_busyness__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* GpuBusyness :: GS Threads Dispatched */
#define tglgt2__gpu_busyness__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* GpuBusyness :: FS Threads Dispatched */
#define tglgt2__gpu_busyness__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* GpuBusyness :: CS Threads Dispatched */
#define tglgt2__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define tglgt2__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* GpuBusyness :: Compute Ring Busy */
#define tglgt2__gpu_busyness__compute_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* GpuBusyness :: Posh Ring Busy */
#define tglgt2__gpu_busyness__posh_engine_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* GpuBusyness :: Blitter Ring Busy */
#define tglgt2__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* GpuBusyness :: Vebox Ring Busy */
#define tglgt2__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: Vdbox0 Ring Busy */
#define tglgt2__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* GpuBusyness :: Vdbox1 Ring Busy */
#define tglgt2__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__ds_stall__read

/* GpuBusyness :: Render and compute engines are simultaneously busy */
#define tglgt2__gpu_busyness__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* GpuBusyness :: Any Engine Busy */
#define tglgt2__gpu_busyness__any_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* EuActivity1 :: GPU Time Elapsed */
#define tglgt2__eu_activity1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity1 :: GPU Core Clocks */
#define tglgt2__eu_activity1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity1 :: GPU Busy */
#define tglgt2__eu_activity1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity1 :: VS Threads Dispatched */
#define tglgt2__eu_activity1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity1 :: HS Threads Dispatched */
#define tglgt2__eu_activity1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity1 :: DS Threads Dispatched */
#define tglgt2__eu_activity1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity1 :: GS Threads Dispatched */
#define tglgt2__eu_activity1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity1 :: FS Threads Dispatched */
#define tglgt2__eu_activity1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity1 :: CS Threads Dispatched */
#define tglgt2__eu_activity1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity1 :: Render Ring Busy */
#define tglgt2__eu_activity1__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity1 :: Compute Ring Busy */
#define tglgt2__eu_activity1__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity1 :: Render and compute engines are simultaneously busy */
#define tglgt2__eu_activity1__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity1 :: GTI Read Throughput */
#define tglgt2__eu_activity1__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity1 :: GTI Read Throughput */
#define tglgt2__eu_activity1__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity1 :: GTI Write Throughput */
#define tglgt2__eu_activity1__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity1 :: GTI Write Throughput */
#define tglgt2__eu_activity1__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity1 :: VS FPU Pipe Active */
#define tglgt2__eu_activity1__vs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity1 :: PS FPU Pipe Active */
#define tglgt2__eu_activity1__ps_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity1 :: EU Send Pipe Active */
#define tglgt2__eu_activity1__eu_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity2 :: GPU Time Elapsed */
#define tglgt2__eu_activity2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity2 :: GPU Core Clocks */
#define tglgt2__eu_activity2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity2 :: GPU Busy */
#define tglgt2__eu_activity2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity2 :: VS Threads Dispatched */
#define tglgt2__eu_activity2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity2 :: HS Threads Dispatched */
#define tglgt2__eu_activity2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity2 :: DS Threads Dispatched */
#define tglgt2__eu_activity2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity2 :: GS Threads Dispatched */
#define tglgt2__eu_activity2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity2 :: FS Threads Dispatched */
#define tglgt2__eu_activity2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity2 :: CS Threads Dispatched */
#define tglgt2__eu_activity2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity2 :: Render Ring Busy */
#define tglgt2__eu_activity2__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity2 :: Compute Ring Busy */
#define tglgt2__eu_activity2__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity2 :: Render and compute engines are simultaneously busy */
#define tglgt2__eu_activity2__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity2 :: GTI Read Throughput */
#define tglgt2__eu_activity2__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity2 :: GTI Read Throughput */
#define tglgt2__eu_activity2__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity2 :: GTI Write Throughput */
#define tglgt2__eu_activity2__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity2 :: GTI Write Throughput */
#define tglgt2__eu_activity2__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity2 :: CS EM Pipe Active */
#define tglgt2__eu_activity2__cs_em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity2 :: CS FPU Pipe Active */
#define tglgt2__eu_activity2__cs_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity2 :: CS Send Pipeline Active */
#define tglgt2__eu_activity2__cs_send_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: GPU Time Elapsed */
#define tglgt2__eu_activity3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity3 :: GPU Core Clocks */
#define tglgt2__eu_activity3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity3 :: GPU Busy */
#define tglgt2__eu_activity3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity3 :: VS Threads Dispatched */
#define tglgt2__eu_activity3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity3 :: HS Threads Dispatched */
#define tglgt2__eu_activity3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity3 :: DS Threads Dispatched */
#define tglgt2__eu_activity3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity3 :: GS Threads Dispatched */
#define tglgt2__eu_activity3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity3 :: FS Threads Dispatched */
#define tglgt2__eu_activity3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity3 :: CS Threads Dispatched */
#define tglgt2__eu_activity3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity3 :: Render Ring Busy */
#define tglgt2__eu_activity3__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity3 :: Compute Ring Busy */
#define tglgt2__eu_activity3__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity3 :: Render and compute engines are simultaneously busy */
#define tglgt2__eu_activity3__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity3 :: GTI Read Throughput */
#define tglgt2__eu_activity3__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity3 :: GTI Read Throughput */
#define tglgt2__eu_activity3__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity3 :: GTI Write Throughput */
#define tglgt2__eu_activity3__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity3 :: GTI Write Throughput */
#define tglgt2__eu_activity3__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity3 :: VS EM Pipe Active */
#define tglgt2__eu_activity3__vs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: PS EM Pipe Active */
#define tglgt2__eu_activity3__ps_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity3 :: PS Send Pipeline Active */
#define tglgt2__eu_activity3__ps_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity4 :: GPU Time Elapsed */
#define tglgt2__eu_activity4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity4 :: GPU Core Clocks */
#define tglgt2__eu_activity4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity4 :: GPU Busy */
#define tglgt2__eu_activity4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity4 :: VS Threads Dispatched */
#define tglgt2__eu_activity4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity4 :: HS Threads Dispatched */
#define tglgt2__eu_activity4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity4 :: DS Threads Dispatched */
#define tglgt2__eu_activity4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity4 :: GS Threads Dispatched */
#define tglgt2__eu_activity4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity4 :: FS Threads Dispatched */
#define tglgt2__eu_activity4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity4 :: CS Threads Dispatched */
#define tglgt2__eu_activity4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity4 :: Render Ring Busy */
#define tglgt2__eu_activity4__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity4 :: Compute Ring Busy */
#define tglgt2__eu_activity4__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity4 :: Render and compute engines are simultaneously busy */
#define tglgt2__eu_activity4__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity4 :: GTI Read Throughput */
#define tglgt2__eu_activity4__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity4 :: GTI Read Throughput */
#define tglgt2__eu_activity4__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity4 :: GTI Write Throughput */
#define tglgt2__eu_activity4__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity4 :: GTI Write Throughput */
#define tglgt2__eu_activity4__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity4 :: HS FPU Pipe Active */
#define tglgt2__eu_activity4__hs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity4 :: DS FPU Pipe Active */
#define tglgt2__eu_activity4__ds_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity4 :: VS Send Pipe Active */
#define tglgt2__eu_activity4__vs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity5 :: GPU Time Elapsed */
#define tglgt2__eu_activity5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity5 :: GPU Core Clocks */
#define tglgt2__eu_activity5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity5 :: GPU Busy */
#define tglgt2__eu_activity5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity5 :: VS Threads Dispatched */
#define tglgt2__eu_activity5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity5 :: HS Threads Dispatched */
#define tglgt2__eu_activity5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity5 :: DS Threads Dispatched */
#define tglgt2__eu_activity5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity5 :: GS Threads Dispatched */
#define tglgt2__eu_activity5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity5 :: FS Threads Dispatched */
#define tglgt2__eu_activity5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity5 :: CS Threads Dispatched */
#define tglgt2__eu_activity5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity5 :: Render Ring Busy */
#define tglgt2__eu_activity5__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity5 :: Compute Ring Busy */
#define tglgt2__eu_activity5__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity5 :: Render and compute engines are simultaneously busy */
#define tglgt2__eu_activity5__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity5 :: GTI Read Throughput */
#define tglgt2__eu_activity5__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity5 :: GTI Read Throughput */
#define tglgt2__eu_activity5__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity5 :: GTI Write Throughput */
#define tglgt2__eu_activity5__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity5 :: GTI Write Throughput */
#define tglgt2__eu_activity5__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity5 :: HS EM Pipe Active */
#define tglgt2__eu_activity5__hs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity5 :: DS EM Pipe Active */
#define tglgt2__eu_activity5__ds_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity5 :: HS Send Pipe Active */
#define tglgt2__eu_activity5__hs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity6 :: GPU Time Elapsed */
#define tglgt2__eu_activity6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity6 :: GPU Core Clocks */
#define tglgt2__eu_activity6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity6 :: GPU Busy */
#define tglgt2__eu_activity6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity6 :: VS Threads Dispatched */
#define tglgt2__eu_activity6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity6 :: HS Threads Dispatched */
#define tglgt2__eu_activity6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity6 :: DS Threads Dispatched */
#define tglgt2__eu_activity6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity6 :: GS Threads Dispatched */
#define tglgt2__eu_activity6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity6 :: FS Threads Dispatched */
#define tglgt2__eu_activity6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity6 :: CS Threads Dispatched */
#define tglgt2__eu_activity6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity6 :: Render Ring Busy */
#define tglgt2__eu_activity6__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity6 :: Compute Ring Busy */
#define tglgt2__eu_activity6__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity6 :: Render and compute engines are simultaneously busy */
#define tglgt2__eu_activity6__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity6 :: GTI Read Throughput */
#define tglgt2__eu_activity6__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity6 :: GTI Read Throughput */
#define tglgt2__eu_activity6__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity6 :: GTI Write Throughput */
#define tglgt2__eu_activity6__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity6 :: GTI Write Throughput */
#define tglgt2__eu_activity6__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity6 :: GS FPU Pipe Active */
#define tglgt2__eu_activity6__gs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity6 :: GS EM Pipe Active */
#define tglgt2__eu_activity6__gs_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity6 :: GS Send Pipe Active */
#define tglgt2__eu_activity6__gs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: GPU Time Elapsed */
#define tglgt2__eu_activity7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity7 :: GPU Core Clocks */
#define tglgt2__eu_activity7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity7 :: GPU Busy */
#define tglgt2__eu_activity7__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity7 :: VS Threads Dispatched */
#define tglgt2__eu_activity7__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity7 :: HS Threads Dispatched */
#define tglgt2__eu_activity7__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity7 :: DS Threads Dispatched */
#define tglgt2__eu_activity7__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity7 :: GS Threads Dispatched */
#define tglgt2__eu_activity7__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity7 :: FS Threads Dispatched */
#define tglgt2__eu_activity7__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity7 :: CS Threads Dispatched */
#define tglgt2__eu_activity7__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity7 :: EU FPU Pipe Active */
#define tglgt2__eu_activity7__fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity7 :: EM Pipe Active */
#define tglgt2__eu_activity7__em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: EU FPU And EM Pipes Active */
#define tglgt2__eu_activity7__eu_fpu_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity7 :: EU AVG IPC Rate */
#define tglgt2__eu_activity7__eu_avg_ipc_rate__read \
   tglgt1__eu_activity7__eu_avg_ipc_rate__read

/* EuActivity7 :: EU AVG IPC Rate */
#define tglgt2__eu_activity7__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* EuActivity7 :: Render Ring Busy */
#define tglgt2__eu_activity7__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity7 :: Compute Ring Busy */
#define tglgt2__eu_activity7__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity7 :: Render and compute engines are simultaneously busy */
#define tglgt2__eu_activity7__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity7 :: GTI Read Throughput */
#define tglgt2__eu_activity7__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity7 :: GTI Read Throughput */
#define tglgt2__eu_activity7__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity7 :: GTI Write Throughput */
#define tglgt2__eu_activity7__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity7 :: GTI Write Throughput */
#define tglgt2__eu_activity7__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: GPU Time Elapsed */
#define tglgt2__eu_activity8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity8 :: GPU Core Clocks */
#define tglgt2__eu_activity8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define tglgt2__eu_activity8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity8 :: GPU Busy */
#define tglgt2__eu_activity8__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity8 :: VS Threads Dispatched */
#define tglgt2__eu_activity8__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity8 :: HS Threads Dispatched */
#define tglgt2__eu_activity8__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity8 :: DS Threads Dispatched */
#define tglgt2__eu_activity8__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity8 :: GS Threads Dispatched */
#define tglgt2__eu_activity8__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity8 :: FS Threads Dispatched */
#define tglgt2__eu_activity8__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity8 :: CS Threads Dispatched */
#define tglgt2__eu_activity8__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity8 :: Render Ring Busy */
#define tglgt2__eu_activity8__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity8 :: Compute Ring Busy */
#define tglgt2__eu_activity8__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity8 :: Render and compute engines are simultaneously busy */
#define tglgt2__eu_activity8__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity8 :: GTI Read Throughput */
#define tglgt2__eu_activity8__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity8 :: GTI Read Throughput */
#define tglgt2__eu_activity8__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: GTI Write Throughput */
#define tglgt2__eu_activity8__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity8 :: GTI Write Throughput */
#define tglgt2__eu_activity8__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: DS Send Pipe Active */
#define tglgt2__eu_activity8__ds_send_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set TestOa :: GPU Time Elapsed */
#define tglgt2__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define tglgt2__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define tglgt2__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define tglgt2__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define tglgt2__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define tglgt2__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define tglgt2__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define tglgt2__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define tglgt2__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define tglgt2__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define tglgt2__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define tglgt2__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define tglgt2__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define tglgt2__test_oa__counter9__read \
   hsw__compute_extended__untyped_writes0__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define rkl__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define rkl__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define rkl__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define rkl__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define rkl__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define rkl__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define rkl__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define rkl__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define rkl__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define rkl__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define rkl__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define rkl__render_basic__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define rkl__render_basic__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Thread Occupancy */
#define rkl__render_basic__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Render Metrics Basic set :: Sampler00 Busy */
#define rkl__render_basic__sampler00_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler Slice0 Dualsubslice0 is bottleneck */
#define rkl__render_basic__sampler00_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define rkl__render_basic__samplers_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Samplers Bottleneck */
#define rkl__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define rkl__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define rkl__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define rkl__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define rkl__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define rkl__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define rkl__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define rkl__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define rkl__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define rkl__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define rkl__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define rkl__render_basic__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define rkl__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define rkl__render_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define rkl__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define rkl__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define rkl__render_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define rkl__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define rkl__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define rkl__render_basic__gti_read_throughput__read \
   tglgt1__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define rkl__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define rkl__render_basic__gti_write_throughput__read \
   tglgt1__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define rkl__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define rkl__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define rkl__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define rkl__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define rkl__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define rkl__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define rkl__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define rkl__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define rkl__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define rkl__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define rkl__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define rkl__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define rkl__compute_basic__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define rkl__compute_basic__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define rkl__compute_basic__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define rkl__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define rkl__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define rkl__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define rkl__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define rkl__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define rkl__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define rkl__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define rkl__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define rkl__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define rkl__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define rkl__compute_basic__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define rkl__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define rkl__compute_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define rkl__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define rkl__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define rkl__compute_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define rkl__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define rkl__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define rkl__compute_basic__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define rkl__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define rkl__compute_basic__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define rkl__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define rkl__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define rkl__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define rkl__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define rkl__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define rkl__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define rkl__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define rkl__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define rkl__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define rkl__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define rkl__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define rkl__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define rkl__render_pipe_profile__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define rkl__render_pipe_profile__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: EU Thread Occupancy */
#define rkl__render_pipe_profile__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define rkl__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define rkl__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define rkl__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define rkl__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define rkl__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define rkl__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define rkl__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define rkl__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define rkl__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define rkl__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define rkl__render_pipe_profile__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define rkl__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define rkl__render_pipe_profile__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define rkl__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define rkl__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define rkl__render_pipe_profile__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define rkl__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define rkl__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define rkl__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define rkl__render_pipe_profile__vs_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define rkl__render_pipe_profile__hs_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define rkl__render_pipe_profile__ds_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define rkl__render_pipe_profile__gs_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define rkl__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define rkl__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define rkl__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define rkl__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define rkl__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define rkl__render_pipe_profile__hs_stall__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define rkl__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define rkl__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define rkl__render_pipe_profile__cl_stall__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define rkl__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define rkl__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define rkl__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define rkl__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define rkl__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define rkl__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define rkl__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define rkl__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define rkl__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define rkl__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define rkl__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define rkl__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define rkl__hdc_and_sf__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define rkl__hdc_and_sf__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Thread Occupancy */
#define rkl__hdc_and_sf__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define rkl__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define rkl__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define rkl__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define rkl__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define rkl__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define rkl__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define rkl__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define rkl__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define rkl__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define rkl__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define rkl__hdc_and_sf__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define rkl__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define rkl__hdc_and_sf__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define rkl__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define rkl__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define rkl__hdc_and_sf__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define rkl__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define rkl__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3 */
#define rkl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3 */
#define rkl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define rkl__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define rkl__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define rkl__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define rkl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define rkl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define rkl__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define rkl__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define rkl__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define rkl__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define rkl__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define rkl__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define rkl__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define rkl__rasterizer_and_pixel_backend__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define rkl__rasterizer_and_pixel_backend__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Thread Occupancy */
#define rkl__rasterizer_and_pixel_backend__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define rkl__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define rkl__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define rkl__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define rkl__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define rkl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define rkl__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define rkl__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define rkl__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define rkl__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define rkl__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define rkl__rasterizer_and_pixel_backend__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define rkl__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define rkl__rasterizer_and_pixel_backend__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define rkl__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define rkl__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define rkl__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define rkl__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define rkl__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define rkl__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define rkl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define rkl__rasterizer_and_pixel_backend__pixel_data00_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 PS Output Available */
#define rkl__rasterizer_and_pixel_backend__ps_output00_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Pixel Values Ready */
#define rkl__rasterizer_and_pixel_backend__pixel_values00_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: SQ00 is full */
#define rkl__rasterizer_and_pixel_backend__gt_request_queue00_full__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ01 is full */
#define rkl__rasterizer_and_pixel_backend__gt_request_queue01_full__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ10 is full */
#define rkl__rasterizer_and_pixel_backend__gt_request_queue10_full__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ11 is full */
#define rkl__rasterizer_and_pixel_backend__gt_request_queue11_full__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3_1 :: GPU Time Elapsed */
#define rkl__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_1 :: GPU Core Clocks */
#define rkl__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_1 :: AVG GPU Core Frequency */
#define rkl__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_1 :: AVG GPU Core Frequency */
#define rkl__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_1 :: GPU Busy */
#define rkl__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_1 :: EU Active */
#define rkl__l3_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_1 :: EU Stall */
#define rkl__l3_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_1 :: EU Thread Occupancy */
#define rkl__l3_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_1 :: VS Threads Dispatched */
#define rkl__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_1 :: HS Threads Dispatched */
#define rkl__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_1 :: DS Threads Dispatched */
#define rkl__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_1 :: GS Threads Dispatched */
#define rkl__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_1 :: FS Threads Dispatched */
#define rkl__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_1 :: CS Threads Dispatched */
#define rkl__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_1 :: Slice0 L3 Bank0 Input Available */
#define rkl__l3_1__l30_bank0_input_available__read \
   tglgt1__l3_1__l30_bank0_input_available__read

/* L3_1 :: Slice0 L3 Bank1 Input Available */
#define rkl__l3_1__l30_bank1_input_available__read \
   tglgt1__l3_1__l30_bank1_input_available__read

/* L3_2 :: GPU Time Elapsed */
#define rkl__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_2 :: GPU Core Clocks */
#define rkl__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_2 :: AVG GPU Core Frequency */
#define rkl__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_2 :: AVG GPU Core Frequency */
#define rkl__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_2 :: GPU Busy */
#define rkl__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_2 :: VS Threads Dispatched */
#define rkl__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_2 :: HS Threads Dispatched */
#define rkl__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_2 :: DS Threads Dispatched */
#define rkl__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_2 :: GS Threads Dispatched */
#define rkl__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_2 :: FS Threads Dispatched */
#define rkl__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_2 :: CS Threads Dispatched */
#define rkl__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_2 :: EU Active */
#define rkl__l3_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_2 :: EU Stall */
#define rkl__l3_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_2 :: EU Thread Occupancy */
#define rkl__l3_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_2 :: Slice0 L3 Bank2 Input Available */
#define rkl__l3_2__l30_bank2_input_available__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L3_2 :: Slice0 L3 Bank3 Input Available */
#define rkl__l3_2__l30_bank3_input_available__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L3_3 :: GPU Time Elapsed */
#define rkl__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_3 :: GPU Core Clocks */
#define rkl__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_3 :: AVG GPU Core Frequency */
#define rkl__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_3 :: AVG GPU Core Frequency */
#define rkl__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_3 :: GPU Busy */
#define rkl__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_3 :: VS Threads Dispatched */
#define rkl__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_3 :: HS Threads Dispatched */
#define rkl__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_3 :: DS Threads Dispatched */
#define rkl__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_3 :: GS Threads Dispatched */
#define rkl__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_3 :: FS Threads Dispatched */
#define rkl__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_3 :: CS Threads Dispatched */
#define rkl__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_3 :: EU Active */
#define rkl__l3_3__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_3 :: EU Stall */
#define rkl__l3_3__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_3 :: EU Thread Occupancy */
#define rkl__l3_3__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_3 :: Slice0 L3 Bank0 Output Ready */
#define rkl__l3_3__l30_bank0_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_4 :: GPU Time Elapsed */
#define rkl__l3_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_4 :: GPU Core Clocks */
#define rkl__l3_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_4 :: AVG GPU Core Frequency */
#define rkl__l3_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_4 :: AVG GPU Core Frequency */
#define rkl__l3_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_4 :: GPU Busy */
#define rkl__l3_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_4 :: VS Threads Dispatched */
#define rkl__l3_4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_4 :: HS Threads Dispatched */
#define rkl__l3_4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_4 :: DS Threads Dispatched */
#define rkl__l3_4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_4 :: GS Threads Dispatched */
#define rkl__l3_4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_4 :: FS Threads Dispatched */
#define rkl__l3_4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_4 :: CS Threads Dispatched */
#define rkl__l3_4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_4 :: EU Active */
#define rkl__l3_4__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_4 :: EU Stall */
#define rkl__l3_4__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_4 :: EU Thread Occupancy */
#define rkl__l3_4__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_4 :: Slice0 L3 Bank1 Output Ready */
#define rkl__l3_4__l30_bank1_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_5 :: GPU Time Elapsed */
#define rkl__l3_5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_5 :: GPU Core Clocks */
#define rkl__l3_5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_5 :: AVG GPU Core Frequency */
#define rkl__l3_5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_5 :: AVG GPU Core Frequency */
#define rkl__l3_5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_5 :: GPU Busy */
#define rkl__l3_5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_5 :: VS Threads Dispatched */
#define rkl__l3_5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_5 :: HS Threads Dispatched */
#define rkl__l3_5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_5 :: DS Threads Dispatched */
#define rkl__l3_5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_5 :: GS Threads Dispatched */
#define rkl__l3_5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_5 :: FS Threads Dispatched */
#define rkl__l3_5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_5 :: CS Threads Dispatched */
#define rkl__l3_5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_5 :: EU Active */
#define rkl__l3_5__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_5 :: EU Stall */
#define rkl__l3_5__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_5 :: EU Thread Occupancy */
#define rkl__l3_5__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_5 :: Slice0 L3 Bank2 Output Ready */
#define rkl__l3_5__l30_bank2_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_6 :: GPU Time Elapsed */
#define rkl__l3_6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_6 :: GPU Core Clocks */
#define rkl__l3_6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_6 :: AVG GPU Core Frequency */
#define rkl__l3_6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_6 :: AVG GPU Core Frequency */
#define rkl__l3_6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_6 :: GPU Busy */
#define rkl__l3_6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_6 :: VS Threads Dispatched */
#define rkl__l3_6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_6 :: HS Threads Dispatched */
#define rkl__l3_6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_6 :: DS Threads Dispatched */
#define rkl__l3_6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_6 :: GS Threads Dispatched */
#define rkl__l3_6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_6 :: FS Threads Dispatched */
#define rkl__l3_6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_6 :: CS Threads Dispatched */
#define rkl__l3_6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_6 :: EU Active */
#define rkl__l3_6__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_6 :: EU Stall */
#define rkl__l3_6__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_6 :: EU Thread Occupancy */
#define rkl__l3_6__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_6 :: Slice0 L3 Bank3 Output Ready */
#define rkl__l3_6__l30_bank3_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* Sampler_1 :: GPU Time Elapsed */
#define rkl__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_1 :: GPU Core Clocks */
#define rkl__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define rkl__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define rkl__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_1 :: GPU Busy */
#define rkl__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_1 :: VS Threads Dispatched */
#define rkl__sampler_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Sampler_1 :: HS Threads Dispatched */
#define rkl__sampler_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Sampler_1 :: DS Threads Dispatched */
#define rkl__sampler_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Sampler_1 :: GS Threads Dispatched */
#define rkl__sampler_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Sampler_1 :: FS Threads Dispatched */
#define rkl__sampler_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Sampler_1 :: CS Threads Dispatched */
#define rkl__sampler_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Sampler_1 :: EU Active */
#define rkl__sampler_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Sampler_1 :: EU Stall */
#define rkl__sampler_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Sampler_1 :: EU Thread Occupancy */
#define rkl__sampler_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Sampler_1 :: Slice0 DualSubslice0 Input Available */
#define rkl__sampler_1__sampler00_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_1 :: Slice0 DualSubslice1 Input Available */
#define rkl__sampler_1__sampler01_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_1 :: Slice0 DualSubslice0 Sampler Output Ready */
#define rkl__sampler_1__sampler00_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice1 Sampler Output Ready */
#define rkl__sampler_1__sampler01_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_1 :: GPU Time Elapsed */
#define rkl__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_1 :: GPU Core Clocks */
#define rkl__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_1 :: AVG GPU Core Frequency */
#define rkl__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_1 :: AVG GPU Core Frequency */
#define rkl__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_1 :: GPU Busy */
#define rkl__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_1 :: VS Threads Dispatched */
#define rkl__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_1 :: HS Threads Dispatched */
#define rkl__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_1 :: DS Threads Dispatched */
#define rkl__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_1 :: GS Threads Dispatched */
#define rkl__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_1 :: FS Threads Dispatched */
#define rkl__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_1 :: CS Threads Dispatched */
#define rkl__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_1 :: EU Active */
#define rkl__tdl_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_1 :: EU Stall */
#define rkl__tdl_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_1 :: EU Thread Occupancy */
#define rkl__tdl_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice0 Thread Dispatcher */
#define rkl__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice1 Thread Dispatcher */
#define rkl__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_1 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice0 Thread Dispatcher */
#define rkl__tdl_1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_1 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice1 Thread Dispatcher */
#define rkl__tdl_1__ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 0 */
#define rkl__tdl_1__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 1 */
#define rkl__tdl_1__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 2 */
#define rkl__tdl_1__thread_header00_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 3 */
#define rkl__tdl_1__thread_header00_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 0 */
#define rkl__tdl_1__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 1 */
#define rkl__tdl_1__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 2 */
#define rkl__tdl_1__thread_header01_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 3 */
#define rkl__tdl_1__thread_header01_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher */
#define rkl__tdl_1__thread_header00_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher */
#define rkl__tdl_1__thread_header01_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* GpuBusyness :: GPU Time Elapsed */
#define rkl__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define rkl__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define rkl__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define rkl__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define rkl__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: EU Active */
#define rkl__gpu_busyness__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* GpuBusyness :: EU Stall */
#define rkl__gpu_busyness__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* GpuBusyness :: EU Thread Occupancy */
#define rkl__gpu_busyness__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* GpuBusyness :: VS Threads Dispatched */
#define rkl__gpu_busyness__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* GpuBusyness :: HS Threads Dispatched */
#define rkl__gpu_busyness__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* GpuBusyness :: DS Threads Dispatched */
#define rkl__gpu_busyness__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* GpuBusyness :: GS Threads Dispatched */
#define rkl__gpu_busyness__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* GpuBusyness :: FS Threads Dispatched */
#define rkl__gpu_busyness__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* GpuBusyness :: CS Threads Dispatched */
#define rkl__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define rkl__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* GpuBusyness :: Compute Ring Busy */
#define rkl__gpu_busyness__compute_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* GpuBusyness :: Posh Ring Busy */
#define rkl__gpu_busyness__posh_engine_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* GpuBusyness :: Blitter Ring Busy */
#define rkl__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* GpuBusyness :: Vebox Ring Busy */
#define rkl__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: Vdbox0 Ring Busy */
#define rkl__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* GpuBusyness :: Render and compute engines are simultaneously busy */
#define rkl__gpu_busyness__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* GpuBusyness :: Any Engine Busy */
#define rkl__gpu_busyness__any_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* EuActivity1 :: GPU Time Elapsed */
#define rkl__eu_activity1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity1 :: GPU Core Clocks */
#define rkl__eu_activity1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define rkl__eu_activity1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define rkl__eu_activity1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity1 :: GPU Busy */
#define rkl__eu_activity1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity1 :: VS Threads Dispatched */
#define rkl__eu_activity1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity1 :: HS Threads Dispatched */
#define rkl__eu_activity1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity1 :: DS Threads Dispatched */
#define rkl__eu_activity1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity1 :: GS Threads Dispatched */
#define rkl__eu_activity1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity1 :: FS Threads Dispatched */
#define rkl__eu_activity1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity1 :: CS Threads Dispatched */
#define rkl__eu_activity1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity1 :: Render Ring Busy */
#define rkl__eu_activity1__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity1 :: Compute Ring Busy */
#define rkl__eu_activity1__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity1 :: Render and compute engines are simultaneously busy */
#define rkl__eu_activity1__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity1 :: GTI Read Throughput */
#define rkl__eu_activity1__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity1 :: GTI Read Throughput */
#define rkl__eu_activity1__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity1 :: GTI Write Throughput */
#define rkl__eu_activity1__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity1 :: GTI Write Throughput */
#define rkl__eu_activity1__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity1 :: VS FPU Pipe Active */
#define rkl__eu_activity1__vs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity1 :: PS FPU Pipe Active */
#define rkl__eu_activity1__ps_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity1 :: EU Send Pipe Active */
#define rkl__eu_activity1__eu_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity2 :: GPU Time Elapsed */
#define rkl__eu_activity2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity2 :: GPU Core Clocks */
#define rkl__eu_activity2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define rkl__eu_activity2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define rkl__eu_activity2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity2 :: GPU Busy */
#define rkl__eu_activity2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity2 :: VS Threads Dispatched */
#define rkl__eu_activity2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity2 :: HS Threads Dispatched */
#define rkl__eu_activity2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity2 :: DS Threads Dispatched */
#define rkl__eu_activity2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity2 :: GS Threads Dispatched */
#define rkl__eu_activity2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity2 :: FS Threads Dispatched */
#define rkl__eu_activity2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity2 :: CS Threads Dispatched */
#define rkl__eu_activity2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity2 :: Render Ring Busy */
#define rkl__eu_activity2__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity2 :: Compute Ring Busy */
#define rkl__eu_activity2__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity2 :: Render and compute engines are simultaneously busy */
#define rkl__eu_activity2__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity2 :: GTI Read Throughput */
#define rkl__eu_activity2__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity2 :: GTI Read Throughput */
#define rkl__eu_activity2__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity2 :: GTI Write Throughput */
#define rkl__eu_activity2__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity2 :: GTI Write Throughput */
#define rkl__eu_activity2__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity2 :: CS EM Pipe Active */
#define rkl__eu_activity2__cs_em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity2 :: CS FPU Pipe Active */
#define rkl__eu_activity2__cs_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity2 :: CS Send Pipeline Active */
#define rkl__eu_activity2__cs_send_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: GPU Time Elapsed */
#define rkl__eu_activity3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity3 :: GPU Core Clocks */
#define rkl__eu_activity3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define rkl__eu_activity3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define rkl__eu_activity3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity3 :: GPU Busy */
#define rkl__eu_activity3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity3 :: VS Threads Dispatched */
#define rkl__eu_activity3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity3 :: HS Threads Dispatched */
#define rkl__eu_activity3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity3 :: DS Threads Dispatched */
#define rkl__eu_activity3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity3 :: GS Threads Dispatched */
#define rkl__eu_activity3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity3 :: FS Threads Dispatched */
#define rkl__eu_activity3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity3 :: CS Threads Dispatched */
#define rkl__eu_activity3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity3 :: Render Ring Busy */
#define rkl__eu_activity3__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity3 :: Compute Ring Busy */
#define rkl__eu_activity3__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity3 :: Render and compute engines are simultaneously busy */
#define rkl__eu_activity3__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity3 :: GTI Read Throughput */
#define rkl__eu_activity3__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity3 :: GTI Read Throughput */
#define rkl__eu_activity3__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity3 :: GTI Write Throughput */
#define rkl__eu_activity3__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity3 :: GTI Write Throughput */
#define rkl__eu_activity3__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity3 :: VS EM Pipe Active */
#define rkl__eu_activity3__vs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: PS EM Pipe Active */
#define rkl__eu_activity3__ps_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity3 :: PS Send Pipeline Active */
#define rkl__eu_activity3__ps_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity4 :: GPU Time Elapsed */
#define rkl__eu_activity4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity4 :: GPU Core Clocks */
#define rkl__eu_activity4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define rkl__eu_activity4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define rkl__eu_activity4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity4 :: GPU Busy */
#define rkl__eu_activity4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity4 :: VS Threads Dispatched */
#define rkl__eu_activity4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity4 :: HS Threads Dispatched */
#define rkl__eu_activity4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity4 :: DS Threads Dispatched */
#define rkl__eu_activity4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity4 :: GS Threads Dispatched */
#define rkl__eu_activity4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity4 :: FS Threads Dispatched */
#define rkl__eu_activity4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity4 :: CS Threads Dispatched */
#define rkl__eu_activity4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity4 :: Render Ring Busy */
#define rkl__eu_activity4__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity4 :: Compute Ring Busy */
#define rkl__eu_activity4__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity4 :: Render and compute engines are simultaneously busy */
#define rkl__eu_activity4__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity4 :: GTI Read Throughput */
#define rkl__eu_activity4__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity4 :: GTI Read Throughput */
#define rkl__eu_activity4__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity4 :: GTI Write Throughput */
#define rkl__eu_activity4__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity4 :: GTI Write Throughput */
#define rkl__eu_activity4__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity4 :: HS FPU Pipe Active */
#define rkl__eu_activity4__hs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity4 :: DS FPU Pipe Active */
#define rkl__eu_activity4__ds_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity4 :: VS Send Pipe Active */
#define rkl__eu_activity4__vs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity5 :: GPU Time Elapsed */
#define rkl__eu_activity5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity5 :: GPU Core Clocks */
#define rkl__eu_activity5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define rkl__eu_activity5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define rkl__eu_activity5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity5 :: GPU Busy */
#define rkl__eu_activity5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity5 :: VS Threads Dispatched */
#define rkl__eu_activity5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity5 :: HS Threads Dispatched */
#define rkl__eu_activity5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity5 :: DS Threads Dispatched */
#define rkl__eu_activity5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity5 :: GS Threads Dispatched */
#define rkl__eu_activity5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity5 :: FS Threads Dispatched */
#define rkl__eu_activity5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity5 :: CS Threads Dispatched */
#define rkl__eu_activity5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity5 :: Render Ring Busy */
#define rkl__eu_activity5__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity5 :: Compute Ring Busy */
#define rkl__eu_activity5__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity5 :: Render and compute engines are simultaneously busy */
#define rkl__eu_activity5__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity5 :: GTI Read Throughput */
#define rkl__eu_activity5__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity5 :: GTI Read Throughput */
#define rkl__eu_activity5__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity5 :: GTI Write Throughput */
#define rkl__eu_activity5__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity5 :: GTI Write Throughput */
#define rkl__eu_activity5__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity5 :: HS EM Pipe Active */
#define rkl__eu_activity5__hs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity5 :: DS EM Pipe Active */
#define rkl__eu_activity5__ds_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity5 :: HS Send Pipe Active */
#define rkl__eu_activity5__hs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity6 :: GPU Time Elapsed */
#define rkl__eu_activity6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity6 :: GPU Core Clocks */
#define rkl__eu_activity6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define rkl__eu_activity6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define rkl__eu_activity6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity6 :: GPU Busy */
#define rkl__eu_activity6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity6 :: VS Threads Dispatched */
#define rkl__eu_activity6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity6 :: HS Threads Dispatched */
#define rkl__eu_activity6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity6 :: DS Threads Dispatched */
#define rkl__eu_activity6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity6 :: GS Threads Dispatched */
#define rkl__eu_activity6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity6 :: FS Threads Dispatched */
#define rkl__eu_activity6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity6 :: CS Threads Dispatched */
#define rkl__eu_activity6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity6 :: Render Ring Busy */
#define rkl__eu_activity6__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity6 :: Compute Ring Busy */
#define rkl__eu_activity6__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity6 :: Render and compute engines are simultaneously busy */
#define rkl__eu_activity6__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity6 :: GTI Read Throughput */
#define rkl__eu_activity6__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity6 :: GTI Read Throughput */
#define rkl__eu_activity6__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity6 :: GTI Write Throughput */
#define rkl__eu_activity6__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity6 :: GTI Write Throughput */
#define rkl__eu_activity6__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity6 :: GS FPU Pipe Active */
#define rkl__eu_activity6__gs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity6 :: GS EM Pipe Active */
#define rkl__eu_activity6__gs_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity6 :: GS Send Pipe Active */
#define rkl__eu_activity6__gs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: GPU Time Elapsed */
#define rkl__eu_activity7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity7 :: GPU Core Clocks */
#define rkl__eu_activity7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define rkl__eu_activity7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define rkl__eu_activity7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity7 :: GPU Busy */
#define rkl__eu_activity7__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity7 :: VS Threads Dispatched */
#define rkl__eu_activity7__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity7 :: HS Threads Dispatched */
#define rkl__eu_activity7__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity7 :: DS Threads Dispatched */
#define rkl__eu_activity7__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity7 :: GS Threads Dispatched */
#define rkl__eu_activity7__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity7 :: FS Threads Dispatched */
#define rkl__eu_activity7__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity7 :: CS Threads Dispatched */
#define rkl__eu_activity7__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity7 :: EU FPU Pipe Active */
#define rkl__eu_activity7__fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity7 :: EM Pipe Active */
#define rkl__eu_activity7__em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: EU FPU And EM Pipes Active */
#define rkl__eu_activity7__eu_fpu_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity7 :: EU AVG IPC Rate */
#define rkl__eu_activity7__eu_avg_ipc_rate__read \
   tglgt1__eu_activity7__eu_avg_ipc_rate__read

/* EuActivity7 :: EU AVG IPC Rate */
#define rkl__eu_activity7__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* EuActivity7 :: Render Ring Busy */
#define rkl__eu_activity7__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity7 :: Compute Ring Busy */
#define rkl__eu_activity7__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity7 :: Render and compute engines are simultaneously busy */
#define rkl__eu_activity7__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity7 :: GTI Read Throughput */
#define rkl__eu_activity7__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity7 :: GTI Read Throughput */
#define rkl__eu_activity7__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity7 :: GTI Write Throughput */
#define rkl__eu_activity7__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity7 :: GTI Write Throughput */
#define rkl__eu_activity7__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: GPU Time Elapsed */
#define rkl__eu_activity8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity8 :: GPU Core Clocks */
#define rkl__eu_activity8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define rkl__eu_activity8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define rkl__eu_activity8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity8 :: GPU Busy */
#define rkl__eu_activity8__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity8 :: VS Threads Dispatched */
#define rkl__eu_activity8__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity8 :: HS Threads Dispatched */
#define rkl__eu_activity8__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity8 :: DS Threads Dispatched */
#define rkl__eu_activity8__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity8 :: GS Threads Dispatched */
#define rkl__eu_activity8__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity8 :: FS Threads Dispatched */
#define rkl__eu_activity8__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity8 :: CS Threads Dispatched */
#define rkl__eu_activity8__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity8 :: Render Ring Busy */
#define rkl__eu_activity8__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity8 :: Compute Ring Busy */
#define rkl__eu_activity8__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity8 :: Render and compute engines are simultaneously busy */
#define rkl__eu_activity8__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity8 :: GTI Read Throughput */
#define rkl__eu_activity8__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity8 :: GTI Read Throughput */
#define rkl__eu_activity8__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: GTI Write Throughput */
#define rkl__eu_activity8__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity8 :: GTI Write Throughput */
#define rkl__eu_activity8__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: DS Send Pipe Active */
#define rkl__eu_activity8__ds_send_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set TestOa :: GPU Time Elapsed */
#define rkl__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define rkl__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define rkl__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define rkl__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define rkl__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define rkl__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define rkl__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define rkl__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define rkl__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define rkl__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define rkl__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define rkl__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define rkl__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define rkl__test_oa__counter9__read \
   hsw__compute_extended__untyped_writes0__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define dg1__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define dg1__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define dg1__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define dg1__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define dg1__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define dg1__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define dg1__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define dg1__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define dg1__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define dg1__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define dg1__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define dg1__render_basic__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define dg1__render_basic__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Thread Occupancy */
#define dg1__render_basic__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Render Metrics Basic set :: Sampler00 Busy */
#define dg1__render_basic__sampler00_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler Slice0 Dualsubslice0 is bottleneck */
#define dg1__render_basic__sampler00_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define dg1__render_basic__samplers_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Samplers Bottleneck */
#define dg1__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define dg1__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define dg1__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define dg1__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define dg1__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define dg1__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define dg1__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define dg1__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define dg1__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define dg1__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define dg1__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define dg1__render_basic__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define dg1__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define dg1__render_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define dg1__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define dg1__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define dg1__render_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define dg1__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define dg1__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define dg1__render_basic__gti_read_throughput__read \
   tglgt1__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define dg1__render_basic__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define dg1__render_basic__gti_write_throughput__read \
   tglgt1__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define dg1__render_basic__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* Compute Metrics Basic set :: GPU Time Elapsed */
#define dg1__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic set :: GPU Core Clocks */
#define dg1__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define dg1__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic set :: AVG GPU Core Frequency */
#define dg1__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic set :: GPU Busy */
#define dg1__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic set :: VS Threads Dispatched */
#define dg1__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: HS Threads Dispatched */
#define dg1__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic set :: DS Threads Dispatched */
#define dg1__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic set :: GS Threads Dispatched */
#define dg1__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic set :: FS Threads Dispatched */
#define dg1__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic set :: CS Threads Dispatched */
#define dg1__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic set :: EU Active */
#define dg1__compute_basic__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Compute Metrics Basic set :: EU Stall */
#define dg1__compute_basic__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Compute Metrics Basic set :: EU Thread Occupancy */
#define dg1__compute_basic__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Compute Metrics Basic set :: Rasterized Pixels */
#define dg1__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic set :: Early Hi-Depth Test Fails */
#define dg1__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic set :: Early Depth Test Fails */
#define dg1__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: Samples Killed in FS */
#define dg1__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic set :: Pixels Failing Tests */
#define dg1__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic set :: Samples Written */
#define dg1__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic set :: Samples Blended */
#define dg1__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic set :: Sampler Texels */
#define dg1__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic set :: Sampler Texels Misses */
#define dg1__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define dg1__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic set :: SLM Bytes Read */
#define dg1__compute_basic__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: SLM Bytes Written */
#define dg1__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic set :: SLM Bytes Written */
#define dg1__compute_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Memory Accesses */
#define dg1__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic set :: Shader Atomic Memory Accesses */
#define dg1__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define dg1__compute_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic set :: L3 Shader Throughput */
#define dg1__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic set :: Shader Barrier Messages */
#define dg1__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define dg1__compute_basic__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* Compute Metrics Basic set :: GTI Read Throughput */
#define dg1__compute_basic__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* Compute Metrics Basic set :: GTI Write Throughput */
#define dg1__compute_basic__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* Compute Metrics Basic set :: GTI Write Throughput */
#define dg1__compute_basic__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define dg1__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define dg1__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define dg1__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define dg1__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define dg1__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VS Threads Dispatched */
#define dg1__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics for 3D Pipeline Profile :: HS Threads Dispatched */
#define dg1__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics for 3D Pipeline Profile :: DS Threads Dispatched */
#define dg1__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics for 3D Pipeline Profile :: GS Threads Dispatched */
#define dg1__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics for 3D Pipeline Profile :: FS Threads Dispatched */
#define dg1__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics for 3D Pipeline Profile :: CS Threads Dispatched */
#define dg1__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics for 3D Pipeline Profile :: EU Active */
#define dg1__render_pipe_profile__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Render Metrics for 3D Pipeline Profile :: EU Stall */
#define dg1__render_pipe_profile__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Render Metrics for 3D Pipeline Profile :: EU Thread Occupancy */
#define dg1__render_pipe_profile__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Render Metrics for 3D Pipeline Profile :: Rasterized Pixels */
#define dg1__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define dg1__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics for 3D Pipeline Profile :: Early Depth Test Fails */
#define dg1__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics for 3D Pipeline Profile :: Samples Killed in FS */
#define dg1__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics for 3D Pipeline Profile :: Pixels Failing Tests */
#define dg1__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics for 3D Pipeline Profile :: Samples Written */
#define dg1__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics for 3D Pipeline Profile :: Samples Blended */
#define dg1__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics for 3D Pipeline Profile :: Sampler Texels */
#define dg1__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics for 3D Pipeline Profile :: Sampler Texels Misses */
#define dg1__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */
#define dg1__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */
#define dg1__render_pipe_profile__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */
#define dg1__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */
#define dg1__render_pipe_profile__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics for 3D Pipeline Profile :: Shader Memory Accesses */
#define dg1__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define dg1__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */
#define dg1__render_pipe_profile__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */
#define dg1__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics for 3D Pipeline Profile :: Shader Barrier Messages */
#define dg1__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics for 3D Pipeline Profile :: VF Bottleneck */
#define dg1__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS Bottleneck */
#define dg1__render_pipe_profile__vs_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS Bottleneck */
#define dg1__render_pipe_profile__hs_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS Bottleneck */
#define dg1__render_pipe_profile__ds_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS Bottleneck */
#define dg1__render_pipe_profile__gs_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO Bottleneck */
#define dg1__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: Clipper Bottleneck */
#define dg1__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define dg1__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define dg1__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC Bottleneck */
#define dg1__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS Stall */
#define dg1__render_pipe_profile__hs_stall__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS Stall */
#define dg1__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO Stall */
#define dg1__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL Stall */
#define dg1__render_pipe_profile__cl_stall__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics for 3D Pipeline Profile :: SF Stall */
#define dg1__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF (DG1) :: GPU Time Elapsed */
#define dg1__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF (DG1) :: GPU Core Clocks */
#define dg1__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF (DG1) :: AVG GPU Core Frequency */
#define dg1__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF (DG1) :: AVG GPU Core Frequency */
#define dg1__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF (DG1) :: GPU Busy */
#define dg1__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF (DG1) :: VS Threads Dispatched */
#define dg1__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF (DG1) :: HS Threads Dispatched */
#define dg1__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF (DG1) :: DS Threads Dispatched */
#define dg1__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF (DG1) :: GS Threads Dispatched */
#define dg1__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF (DG1) :: FS Threads Dispatched */
#define dg1__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF (DG1) :: CS Threads Dispatched */
#define dg1__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF (DG1) :: EU Active */
#define dg1__hdc_and_sf__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set HDCAndSF (DG1) :: EU Stall */
#define dg1__hdc_and_sf__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set HDCAndSF (DG1) :: EU Thread Occupancy */
#define dg1__hdc_and_sf__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set HDCAndSF (DG1) :: Rasterized Pixels */
#define dg1__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF (DG1) :: Early Hi-Depth Test Fails */
#define dg1__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF (DG1) :: Early Depth Test Fails */
#define dg1__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF (DG1) :: Samples Killed in FS */
#define dg1__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF (DG1) :: Pixels Failing Tests */
#define dg1__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF (DG1) :: Samples Written */
#define dg1__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF (DG1) :: Samples Blended */
#define dg1__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF (DG1) :: Sampler Texels */
#define dg1__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF (DG1) :: Sampler Texels Misses */
#define dg1__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF (DG1) :: SLM Bytes Read */
#define dg1__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF (DG1) :: SLM Bytes Read */
#define dg1__hdc_and_sf__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF (DG1) :: SLM Bytes Written */
#define dg1__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF (DG1) :: SLM Bytes Written */
#define dg1__hdc_and_sf__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF (DG1) :: Shader Memory Accesses */
#define dg1__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF (DG1) :: Shader Atomic Memory Accesses */
#define dg1__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF (DG1) :: L3 Shader Throughput */
#define dg1__hdc_and_sf__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF (DG1) :: L3 Shader Throughput */
#define dg1__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF (DG1) :: Shader Barrier Messages */
#define dg1__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF (DG1) :: Slice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3 */
#define dg1__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   icl__tdl_2__non_ps_thread03_ready_for_dispatch__read

/* Metric set HDCAndSF (DG1) :: Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3 */
#define dg1__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   icl__tdl_2__non_ps_thread04_ready_for_dispatch__read

/* Metric set HDCAndSF (DG1) :: Slice0 Dualsubslice2 Non-sampler Shader Access Stalled On L3 */
#define dg1__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   icl__tdl_2__non_ps_thread05_ready_for_dispatch__read

/* Metric set HDCAndSF (DG1) :: Slice0 Dualsubslice3 Non-sampler Shader Access Stalled On L3 */
#define dg1__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read \
   icl__tdl_2__non_ps_thread06_ready_for_dispatch__read

/* Metric set HDCAndSF (DG1) :: Slice0 Dualsubslice4 Non-sampler Shader Access Stalled On L3 */
#define dg1__hdc_and_sf__non_sampler_shader04_access_stalled_on_l3__read \
   icl__tdl_2__non_ps_thread07_ready_for_dispatch__read

/* Metric set HDCAndSF (DG1) :: Slice0 Dualsubslice5 Non-sampler Shader Access Stalled On L3 */
static float
dg1__hdc_and_sf__non_sampler_shader05_access_stalled_on_l3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: GPU_CLOCK 0 READ C 7 READ FSUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->gpu_clock_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   double tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = dg1__hdc_and_sf__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Metric set HDCAndSF (DG1) :: Polygon Data Ready */
#define dg1__hdc_and_sf__poly_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF (DG1) :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define dg1__hdc_and_sf__pixel_data00_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF (DG1) :: Slice0 Pipe1 Post-EarlyZ Pixel Data Ready */
#define dg1__hdc_and_sf__pixel_data01_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF (DG1) :: Slice0 Pipe2 Post-EarlyZ Pixel Data Ready */
#define dg1__hdc_and_sf__pixel_data02_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define dg1__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define dg1__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define dg1__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define dg1__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define dg1__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define dg1__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define dg1__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define dg1__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define dg1__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define dg1__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define dg1__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define dg1__rasterizer_and_pixel_backend__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define dg1__rasterizer_and_pixel_backend__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Thread Occupancy */
#define dg1__rasterizer_and_pixel_backend__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define dg1__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define dg1__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define dg1__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define dg1__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define dg1__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define dg1__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define dg1__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define dg1__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define dg1__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define dg1__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define dg1__rasterizer_and_pixel_backend__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define dg1__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define dg1__rasterizer_and_pixel_backend__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define dg1__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define dg1__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define dg1__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define dg1__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define dg1__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define dg1__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define dg1__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 PS Output Available */
#define dg1__rasterizer_and_pixel_backend__ps_output00_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 PS Output Available */
#define dg1__rasterizer_and_pixel_backend__ps_output01_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe2 PS Output Available */
#define dg1__rasterizer_and_pixel_backend__ps_output02_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Pixel Values Ready */
#define dg1__rasterizer_and_pixel_backend__pixel_values00_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 Pixel Values Ready */
#define dg1__rasterizer_and_pixel_backend__pixel_values01_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe2 Pixel Values Ready */
#define dg1__rasterizer_and_pixel_backend__pixel_values02_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: SQ00 is full */
#define dg1__rasterizer_and_pixel_backend__gt_request_queue00_full__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ01 is full */
#define dg1__rasterizer_and_pixel_backend__gt_request_queue01_full__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ10 is full */
#define dg1__rasterizer_and_pixel_backend__gt_request_queue10_full__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: SQ11 is full */
#define dg1__rasterizer_and_pixel_backend__gt_request_queue11_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3_1 :: GPU Time Elapsed */
#define dg1__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_1 :: GPU Core Clocks */
#define dg1__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_1 :: AVG GPU Core Frequency */
#define dg1__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_1 :: AVG GPU Core Frequency */
#define dg1__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_1 :: GPU Busy */
#define dg1__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_1 :: EU Active */
#define dg1__l3_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_1 :: EU Stall */
#define dg1__l3_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_1 :: EU Thread Occupancy */
#define dg1__l3_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_1 :: VS Threads Dispatched */
#define dg1__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_1 :: HS Threads Dispatched */
#define dg1__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_1 :: DS Threads Dispatched */
#define dg1__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_1 :: GS Threads Dispatched */
#define dg1__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_1 :: FS Threads Dispatched */
#define dg1__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_1 :: CS Threads Dispatched */
#define dg1__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_1 :: Slice0 L3 Bank0 Input Available */
#define dg1__l3_1__l30_bank0_input_available__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L3_1 :: Slice0 L3 Bank1 Input Available */
#define dg1__l3_1__l30_bank1_input_available__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L3_1 :: Slice0 L3 Bank4 Input Available */
#define dg1__l3_1__l30_bank4_input_available__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L3_1 :: Slice0 L3 Bank5 Input Available */
#define dg1__l3_1__l30_bank5_input_available__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L3_2 :: GPU Time Elapsed */
#define dg1__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_2 :: GPU Core Clocks */
#define dg1__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_2 :: AVG GPU Core Frequency */
#define dg1__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_2 :: AVG GPU Core Frequency */
#define dg1__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_2 :: GPU Busy */
#define dg1__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_2 :: VS Threads Dispatched */
#define dg1__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_2 :: HS Threads Dispatched */
#define dg1__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_2 :: DS Threads Dispatched */
#define dg1__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_2 :: GS Threads Dispatched */
#define dg1__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_2 :: FS Threads Dispatched */
#define dg1__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_2 :: CS Threads Dispatched */
#define dg1__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_2 :: EU Active */
#define dg1__l3_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_2 :: EU Stall */
#define dg1__l3_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_2 :: EU Thread Occupancy */
#define dg1__l3_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_2 :: Slice0 L3 Bank2 Input Available */
#define dg1__l3_2__l30_bank2_input_available__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L3_2 :: Slice0 L3 Bank3 Input Available */
#define dg1__l3_2__l30_bank3_input_available__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L3_2 :: Slice0 L3 Bank6 Input Available */
#define dg1__l3_2__l30_bank6_input_available__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L3_2 :: Slice0 L3 Bank7 Input Available */
#define dg1__l3_2__l30_bank7_input_available__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L3_3 :: GPU Time Elapsed */
#define dg1__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_3 :: GPU Core Clocks */
#define dg1__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_3 :: AVG GPU Core Frequency */
#define dg1__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_3 :: AVG GPU Core Frequency */
#define dg1__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_3 :: GPU Busy */
#define dg1__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_3 :: VS Threads Dispatched */
#define dg1__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_3 :: HS Threads Dispatched */
#define dg1__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_3 :: DS Threads Dispatched */
#define dg1__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_3 :: GS Threads Dispatched */
#define dg1__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_3 :: FS Threads Dispatched */
#define dg1__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_3 :: CS Threads Dispatched */
#define dg1__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_3 :: EU Active */
#define dg1__l3_3__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_3 :: EU Stall */
#define dg1__l3_3__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_3 :: EU Thread Occupancy */
#define dg1__l3_3__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_3 :: Slice0 L3 Bank0 Output Ready */
#define dg1__l3_3__l30_bank0_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_3 :: Slice0 L3 Bank4 Output Ready */
#define dg1__l3_3__l30_bank4_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_4 :: GPU Time Elapsed */
#define dg1__l3_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_4 :: GPU Core Clocks */
#define dg1__l3_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_4 :: AVG GPU Core Frequency */
#define dg1__l3_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_4 :: AVG GPU Core Frequency */
#define dg1__l3_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_4 :: GPU Busy */
#define dg1__l3_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_4 :: VS Threads Dispatched */
#define dg1__l3_4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_4 :: HS Threads Dispatched */
#define dg1__l3_4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_4 :: DS Threads Dispatched */
#define dg1__l3_4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_4 :: GS Threads Dispatched */
#define dg1__l3_4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_4 :: FS Threads Dispatched */
#define dg1__l3_4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_4 :: CS Threads Dispatched */
#define dg1__l3_4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_4 :: EU Active */
#define dg1__l3_4__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_4 :: EU Stall */
#define dg1__l3_4__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_4 :: EU Thread Occupancy */
#define dg1__l3_4__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_4 :: Slice0 L3 Bank1 Output Ready */
#define dg1__l3_4__l30_bank1_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_4 :: Slice0 L3 Bank5 Output Ready */
#define dg1__l3_4__l30_bank5_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_5 :: GPU Time Elapsed */
#define dg1__l3_5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_5 :: GPU Core Clocks */
#define dg1__l3_5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_5 :: AVG GPU Core Frequency */
#define dg1__l3_5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_5 :: AVG GPU Core Frequency */
#define dg1__l3_5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_5 :: GPU Busy */
#define dg1__l3_5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_5 :: VS Threads Dispatched */
#define dg1__l3_5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_5 :: HS Threads Dispatched */
#define dg1__l3_5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_5 :: DS Threads Dispatched */
#define dg1__l3_5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_5 :: GS Threads Dispatched */
#define dg1__l3_5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_5 :: FS Threads Dispatched */
#define dg1__l3_5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_5 :: CS Threads Dispatched */
#define dg1__l3_5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_5 :: EU Active */
#define dg1__l3_5__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_5 :: EU Stall */
#define dg1__l3_5__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_5 :: EU Thread Occupancy */
#define dg1__l3_5__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_5 :: Slice0 L3 Bank2 Output Ready */
#define dg1__l3_5__l30_bank2_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_5 :: Slice0 L3 Bank6 Output Ready */
#define dg1__l3_5__l30_bank6_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_6 :: GPU Time Elapsed */
#define dg1__l3_6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_6 :: GPU Core Clocks */
#define dg1__l3_6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_6 :: AVG GPU Core Frequency */
#define dg1__l3_6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_6 :: AVG GPU Core Frequency */
#define dg1__l3_6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_6 :: GPU Busy */
#define dg1__l3_6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_6 :: VS Threads Dispatched */
#define dg1__l3_6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_6 :: HS Threads Dispatched */
#define dg1__l3_6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_6 :: DS Threads Dispatched */
#define dg1__l3_6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_6 :: GS Threads Dispatched */
#define dg1__l3_6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_6 :: FS Threads Dispatched */
#define dg1__l3_6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_6 :: CS Threads Dispatched */
#define dg1__l3_6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_6 :: EU Active */
#define dg1__l3_6__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_6 :: EU Stall */
#define dg1__l3_6__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_6 :: EU Thread Occupancy */
#define dg1__l3_6__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_6 :: Slice0 L3 Bank3 Output Ready */
#define dg1__l3_6__l30_bank3_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_6 :: Slice0 L3 Bank7 Output Ready */
#define dg1__l3_6__l30_bank7_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* Sampler_1 :: GPU Time Elapsed */
#define dg1__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_1 :: GPU Core Clocks */
#define dg1__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define dg1__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define dg1__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_1 :: GPU Busy */
#define dg1__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_1 :: VS Threads Dispatched */
#define dg1__sampler_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Sampler_1 :: HS Threads Dispatched */
#define dg1__sampler_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Sampler_1 :: DS Threads Dispatched */
#define dg1__sampler_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Sampler_1 :: GS Threads Dispatched */
#define dg1__sampler_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Sampler_1 :: FS Threads Dispatched */
#define dg1__sampler_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Sampler_1 :: CS Threads Dispatched */
#define dg1__sampler_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Sampler_1 :: EU Active */
#define dg1__sampler_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Sampler_1 :: EU Stall */
#define dg1__sampler_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Sampler_1 :: EU Thread Occupancy */
#define dg1__sampler_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Sampler_1 :: Slice0 DualSubslice0 Input Available */
#define dg1__sampler_1__sampler00_input_available__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice1 Input Available */
#define dg1__sampler_1__sampler01_input_available__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice2 Input Available */
#define dg1__sampler_1__sampler02_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice3 Input Available */
#define dg1__sampler_1__sampler03_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice4 Input Available */
#define dg1__sampler_1__sampler04_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_1 :: Slice0 DualSubslice5 Input Available */
#define dg1__sampler_1__sampler05_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_2 :: GPU Time Elapsed */
#define dg1__sampler_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_2 :: GPU Core Clocks */
#define dg1__sampler_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_2 :: AVG GPU Core Frequency */
#define dg1__sampler_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_2 :: AVG GPU Core Frequency */
#define dg1__sampler_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_2 :: GPU Busy */
#define dg1__sampler_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_2 :: VS Threads Dispatched */
#define dg1__sampler_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Sampler_2 :: HS Threads Dispatched */
#define dg1__sampler_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Sampler_2 :: DS Threads Dispatched */
#define dg1__sampler_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Sampler_2 :: GS Threads Dispatched */
#define dg1__sampler_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Sampler_2 :: FS Threads Dispatched */
#define dg1__sampler_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Sampler_2 :: CS Threads Dispatched */
#define dg1__sampler_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Sampler_2 :: EU Active */
#define dg1__sampler_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Sampler_2 :: EU Stall */
#define dg1__sampler_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Sampler_2 :: EU Thread Occupancy */
#define dg1__sampler_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Sampler_2 :: Slice0 DualSubslice0 Sampler Output Ready */
#define dg1__sampler_2__sampler00_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice1 Sampler Output Ready */
#define dg1__sampler_2__sampler01_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice2 Sampler Output Ready */
#define dg1__sampler_2__sampler02_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice3 Sampler Output Ready */
#define dg1__sampler_2__sampler03_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice4 Sampler Output Ready */
#define dg1__sampler_2__sampler04_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_2 :: Slice0 DualSubslice5 Sampler Output Ready */
#define dg1__sampler_2__sampler05_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_1 :: GPU Time Elapsed */
#define dg1__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_1 :: GPU Core Clocks */
#define dg1__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_1 :: AVG GPU Core Frequency */
#define dg1__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_1 :: AVG GPU Core Frequency */
#define dg1__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_1 :: GPU Busy */
#define dg1__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_1 :: VS Threads Dispatched */
#define dg1__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_1 :: HS Threads Dispatched */
#define dg1__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_1 :: DS Threads Dispatched */
#define dg1__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_1 :: GS Threads Dispatched */
#define dg1__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_1 :: FS Threads Dispatched */
#define dg1__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_1 :: CS Threads Dispatched */
#define dg1__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_1 :: EU Active */
#define dg1__tdl_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_1 :: EU Stall */
#define dg1__tdl_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_1 :: EU Thread Occupancy */
#define dg1__tdl_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice0 Thread Dispatcher */
#define dg1__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice1 Thread Dispatcher */
#define dg1__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice2 Thread Dispatcher */
#define dg1__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice3 Thread Dispatcher */
#define dg1__tdl_1__non_ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice4 Thread Dispatcher */
#define dg1__tdl_1__non_ps_thread04_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice5 Thread Dispatcher */
#define dg1__tdl_1__non_ps_thread05_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 0 */
#define dg1__tdl_1__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 1 */
#define dg1__tdl_1__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 2 */
#define dg1__tdl_1__thread_header00_ready_port2__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 3 */
#define dg1__tdl_1__thread_header00_ready_port3__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 0 */
#define dg1__tdl_1__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 1 */
#define dg1__tdl_1__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 2 */
#define dg1__tdl_1__thread_header01_ready_port2__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 3 */
#define dg1__tdl_1__thread_header01_ready_port3__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher */
#define dg1__tdl_1__thread_header00_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher */
#define dg1__tdl_1__thread_header01_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_2 :: GPU Time Elapsed */
#define dg1__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_2 :: GPU Core Clocks */
#define dg1__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_2 :: AVG GPU Core Frequency */
#define dg1__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_2 :: AVG GPU Core Frequency */
#define dg1__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_2 :: GPU Busy */
#define dg1__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_2 :: VS Threads Dispatched */
#define dg1__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_2 :: HS Threads Dispatched */
#define dg1__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_2 :: DS Threads Dispatched */
#define dg1__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_2 :: GS Threads Dispatched */
#define dg1__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_2 :: FS Threads Dispatched */
#define dg1__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_2 :: CS Threads Dispatched */
#define dg1__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_2 :: EU Active */
#define dg1__tdl_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_2 :: EU Stall */
#define dg1__tdl_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_2 :: EU Thread Occupancy */
#define dg1__tdl_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice0 Thread Dispatcher */
#define dg1__tdl_2__ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice1 Thread Dispatcher */
#define dg1__tdl_2__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice2 Thread Dispatcher */
#define dg1__tdl_2__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice3 Thread Dispatcher */
#define dg1__tdl_2__ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice4 Thread Dispatcher */
#define dg1__tdl_2__ps_thread04_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice5 Thread Dispatcher */
#define dg1__tdl_2__ps_thread05_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher */
#define dg1__tdl_2__thread_header05_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 0 */
#define dg1__tdl_2__thread_header05_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 1 */
#define dg1__tdl_2__thread_header05_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 2 */
#define dg1__tdl_2__thread_header05_ready_port2__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 3 */
#define dg1__tdl_2__thread_header05_ready_port3__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_3 :: GPU Time Elapsed */
#define dg1__tdl_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_3 :: GPU Core Clocks */
#define dg1__tdl_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_3 :: AVG GPU Core Frequency */
#define dg1__tdl_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_3 :: AVG GPU Core Frequency */
#define dg1__tdl_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_3 :: GPU Busy */
#define dg1__tdl_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_3 :: VS Threads Dispatched */
#define dg1__tdl_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_3 :: HS Threads Dispatched */
#define dg1__tdl_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_3 :: DS Threads Dispatched */
#define dg1__tdl_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_3 :: GS Threads Dispatched */
#define dg1__tdl_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_3 :: FS Threads Dispatched */
#define dg1__tdl_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_3 :: CS Threads Dispatched */
#define dg1__tdl_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_3 :: EU Active */
#define dg1__tdl_3__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_3 :: EU Stall */
#define dg1__tdl_3__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_3 :: EU Thread Occupancy */
#define dg1__tdl_3__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher */
#define dg1__tdl_3__thread_header02_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher */
#define dg1__tdl_3__thread_header03_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher */
#define dg1__tdl_3__thread_header04_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 0 */
#define dg1__tdl_3__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 1 */
#define dg1__tdl_3__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 2 */
#define dg1__tdl_3__thread_header02_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 3 */
#define dg1__tdl_3__thread_header02_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 0 */
#define dg1__tdl_3__thread_header03_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 1 */
#define dg1__tdl_3__thread_header03_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 2 */
#define dg1__tdl_3__thread_header03_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 3 */
#define dg1__tdl_3__thread_header03_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 0 */
#define dg1__tdl_3__thread_header04_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 1 */
#define dg1__tdl_3__thread_header04_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 2 */
#define dg1__tdl_3__thread_header04_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 3 */
#define dg1__tdl_3__thread_header04_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* GpuBusyness :: GPU Time Elapsed */
#define dg1__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define dg1__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define dg1__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define dg1__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define dg1__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: EU Active */
#define dg1__gpu_busyness__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* GpuBusyness :: EU Stall */
#define dg1__gpu_busyness__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* GpuBusyness :: EU Thread Occupancy */
#define dg1__gpu_busyness__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* GpuBusyness :: VS Threads Dispatched */
#define dg1__gpu_busyness__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* GpuBusyness :: HS Threads Dispatched */
#define dg1__gpu_busyness__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* GpuBusyness :: DS Threads Dispatched */
#define dg1__gpu_busyness__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* GpuBusyness :: GS Threads Dispatched */
#define dg1__gpu_busyness__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* GpuBusyness :: FS Threads Dispatched */
#define dg1__gpu_busyness__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* GpuBusyness :: CS Threads Dispatched */
#define dg1__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define dg1__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* GpuBusyness :: Compute Ring Busy */
#define dg1__gpu_busyness__compute_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* GpuBusyness :: Posh Ring Busy */
#define dg1__gpu_busyness__posh_engine_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* GpuBusyness :: Blitter Ring Busy */
#define dg1__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* GpuBusyness :: Vebox Ring Busy */
#define dg1__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: Vdbox0 Ring Busy */
#define dg1__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* GpuBusyness :: Vdbox1 Ring Busy */
#define dg1__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__ds_stall__read

/* GpuBusyness :: Render and compute engines are simultaneously busy */
#define dg1__gpu_busyness__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* GpuBusyness :: Any Engine Busy */
#define dg1__gpu_busyness__any_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* EuActivity1 :: GPU Time Elapsed */
#define dg1__eu_activity1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity1 :: GPU Core Clocks */
#define dg1__eu_activity1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define dg1__eu_activity1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define dg1__eu_activity1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity1 :: GPU Busy */
#define dg1__eu_activity1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity1 :: VS Threads Dispatched */
#define dg1__eu_activity1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity1 :: HS Threads Dispatched */
#define dg1__eu_activity1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity1 :: DS Threads Dispatched */
#define dg1__eu_activity1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity1 :: GS Threads Dispatched */
#define dg1__eu_activity1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity1 :: FS Threads Dispatched */
#define dg1__eu_activity1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity1 :: CS Threads Dispatched */
#define dg1__eu_activity1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity1 :: Render Ring Busy */
#define dg1__eu_activity1__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity1 :: Compute Ring Busy */
#define dg1__eu_activity1__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity1 :: Render and compute engines are simultaneously busy */
#define dg1__eu_activity1__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity1 :: GTI Read Throughput */
#define dg1__eu_activity1__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity1 :: GTI Read Throughput */
#define dg1__eu_activity1__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity1 :: GTI Write Throughput */
#define dg1__eu_activity1__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity1 :: GTI Write Throughput */
#define dg1__eu_activity1__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity1 :: VS FPU Pipe Active */
#define dg1__eu_activity1__vs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity1 :: PS FPU Pipe Active */
#define dg1__eu_activity1__ps_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity1 :: EU Send Pipe Active */
#define dg1__eu_activity1__eu_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity2 :: GPU Time Elapsed */
#define dg1__eu_activity2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity2 :: GPU Core Clocks */
#define dg1__eu_activity2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define dg1__eu_activity2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define dg1__eu_activity2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity2 :: GPU Busy */
#define dg1__eu_activity2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity2 :: VS Threads Dispatched */
#define dg1__eu_activity2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity2 :: HS Threads Dispatched */
#define dg1__eu_activity2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity2 :: DS Threads Dispatched */
#define dg1__eu_activity2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity2 :: GS Threads Dispatched */
#define dg1__eu_activity2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity2 :: FS Threads Dispatched */
#define dg1__eu_activity2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity2 :: CS Threads Dispatched */
#define dg1__eu_activity2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity2 :: Render Ring Busy */
#define dg1__eu_activity2__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity2 :: Compute Ring Busy */
#define dg1__eu_activity2__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity2 :: Render and compute engines are simultaneously busy */
#define dg1__eu_activity2__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity2 :: GTI Read Throughput */
#define dg1__eu_activity2__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity2 :: GTI Read Throughput */
#define dg1__eu_activity2__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity2 :: GTI Write Throughput */
#define dg1__eu_activity2__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity2 :: GTI Write Throughput */
#define dg1__eu_activity2__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity2 :: CS EM Pipe Active */
#define dg1__eu_activity2__cs_em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity2 :: CS FPU Pipe Active */
#define dg1__eu_activity2__cs_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity2 :: CS Send Pipeline Active */
#define dg1__eu_activity2__cs_send_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: GPU Time Elapsed */
#define dg1__eu_activity3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity3 :: GPU Core Clocks */
#define dg1__eu_activity3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define dg1__eu_activity3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define dg1__eu_activity3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity3 :: GPU Busy */
#define dg1__eu_activity3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity3 :: VS Threads Dispatched */
#define dg1__eu_activity3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity3 :: HS Threads Dispatched */
#define dg1__eu_activity3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity3 :: DS Threads Dispatched */
#define dg1__eu_activity3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity3 :: GS Threads Dispatched */
#define dg1__eu_activity3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity3 :: FS Threads Dispatched */
#define dg1__eu_activity3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity3 :: CS Threads Dispatched */
#define dg1__eu_activity3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity3 :: Render Ring Busy */
#define dg1__eu_activity3__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity3 :: Compute Ring Busy */
#define dg1__eu_activity3__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity3 :: Render and compute engines are simultaneously busy */
#define dg1__eu_activity3__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity3 :: GTI Read Throughput */
#define dg1__eu_activity3__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity3 :: GTI Read Throughput */
#define dg1__eu_activity3__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity3 :: GTI Write Throughput */
#define dg1__eu_activity3__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity3 :: GTI Write Throughput */
#define dg1__eu_activity3__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity3 :: VS EM Pipe Active */
#define dg1__eu_activity3__vs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: PS EM Pipe Active */
#define dg1__eu_activity3__ps_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity3 :: PS Send Pipeline Active */
#define dg1__eu_activity3__ps_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity4 :: GPU Time Elapsed */
#define dg1__eu_activity4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity4 :: GPU Core Clocks */
#define dg1__eu_activity4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define dg1__eu_activity4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define dg1__eu_activity4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity4 :: GPU Busy */
#define dg1__eu_activity4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity4 :: VS Threads Dispatched */
#define dg1__eu_activity4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity4 :: HS Threads Dispatched */
#define dg1__eu_activity4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity4 :: DS Threads Dispatched */
#define dg1__eu_activity4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity4 :: GS Threads Dispatched */
#define dg1__eu_activity4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity4 :: FS Threads Dispatched */
#define dg1__eu_activity4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity4 :: CS Threads Dispatched */
#define dg1__eu_activity4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity4 :: Render Ring Busy */
#define dg1__eu_activity4__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity4 :: Compute Ring Busy */
#define dg1__eu_activity4__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity4 :: Render and compute engines are simultaneously busy */
#define dg1__eu_activity4__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity4 :: GTI Read Throughput */
#define dg1__eu_activity4__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity4 :: GTI Read Throughput */
#define dg1__eu_activity4__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity4 :: GTI Write Throughput */
#define dg1__eu_activity4__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity4 :: GTI Write Throughput */
#define dg1__eu_activity4__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity4 :: HS FPU Pipe Active */
#define dg1__eu_activity4__hs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity4 :: DS FPU Pipe Active */
#define dg1__eu_activity4__ds_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity4 :: VS Send Pipe Active */
#define dg1__eu_activity4__vs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity5 :: GPU Time Elapsed */
#define dg1__eu_activity5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity5 :: GPU Core Clocks */
#define dg1__eu_activity5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define dg1__eu_activity5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define dg1__eu_activity5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity5 :: GPU Busy */
#define dg1__eu_activity5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity5 :: VS Threads Dispatched */
#define dg1__eu_activity5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity5 :: HS Threads Dispatched */
#define dg1__eu_activity5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity5 :: DS Threads Dispatched */
#define dg1__eu_activity5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity5 :: GS Threads Dispatched */
#define dg1__eu_activity5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity5 :: FS Threads Dispatched */
#define dg1__eu_activity5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity5 :: CS Threads Dispatched */
#define dg1__eu_activity5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity5 :: Render Ring Busy */
#define dg1__eu_activity5__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity5 :: Compute Ring Busy */
#define dg1__eu_activity5__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity5 :: Render and compute engines are simultaneously busy */
#define dg1__eu_activity5__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity5 :: GTI Read Throughput */
#define dg1__eu_activity5__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity5 :: GTI Read Throughput */
#define dg1__eu_activity5__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity5 :: GTI Write Throughput */
#define dg1__eu_activity5__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity5 :: GTI Write Throughput */
#define dg1__eu_activity5__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity5 :: HS EM Pipe Active */
#define dg1__eu_activity5__hs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity5 :: DS EM Pipe Active */
#define dg1__eu_activity5__ds_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity5 :: HS Send Pipe Active */
#define dg1__eu_activity5__hs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity6 :: GPU Time Elapsed */
#define dg1__eu_activity6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity6 :: GPU Core Clocks */
#define dg1__eu_activity6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define dg1__eu_activity6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define dg1__eu_activity6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity6 :: GPU Busy */
#define dg1__eu_activity6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity6 :: VS Threads Dispatched */
#define dg1__eu_activity6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity6 :: HS Threads Dispatched */
#define dg1__eu_activity6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity6 :: DS Threads Dispatched */
#define dg1__eu_activity6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity6 :: GS Threads Dispatched */
#define dg1__eu_activity6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity6 :: FS Threads Dispatched */
#define dg1__eu_activity6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity6 :: CS Threads Dispatched */
#define dg1__eu_activity6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity6 :: Render Ring Busy */
#define dg1__eu_activity6__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity6 :: Compute Ring Busy */
#define dg1__eu_activity6__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity6 :: Render and compute engines are simultaneously busy */
#define dg1__eu_activity6__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity6 :: GTI Read Throughput */
#define dg1__eu_activity6__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity6 :: GTI Read Throughput */
#define dg1__eu_activity6__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity6 :: GTI Write Throughput */
#define dg1__eu_activity6__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity6 :: GTI Write Throughput */
#define dg1__eu_activity6__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity6 :: GS FPU Pipe Active */
#define dg1__eu_activity6__gs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity6 :: GS EM Pipe Active */
#define dg1__eu_activity6__gs_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity6 :: GS Send Pipe Active */
#define dg1__eu_activity6__gs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: GPU Time Elapsed */
#define dg1__eu_activity7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity7 :: GPU Core Clocks */
#define dg1__eu_activity7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define dg1__eu_activity7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define dg1__eu_activity7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity7 :: GPU Busy */
#define dg1__eu_activity7__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity7 :: VS Threads Dispatched */
#define dg1__eu_activity7__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity7 :: HS Threads Dispatched */
#define dg1__eu_activity7__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity7 :: DS Threads Dispatched */
#define dg1__eu_activity7__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity7 :: GS Threads Dispatched */
#define dg1__eu_activity7__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity7 :: FS Threads Dispatched */
#define dg1__eu_activity7__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity7 :: CS Threads Dispatched */
#define dg1__eu_activity7__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity7 :: EU FPU Pipe Active */
#define dg1__eu_activity7__fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity7 :: EM Pipe Active */
#define dg1__eu_activity7__em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: EU FPU And EM Pipes Active */
#define dg1__eu_activity7__eu_fpu_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity7 :: EU AVG IPC Rate */
#define dg1__eu_activity7__eu_avg_ipc_rate__read \
   tglgt1__eu_activity7__eu_avg_ipc_rate__read

/* EuActivity7 :: EU AVG IPC Rate */
#define dg1__eu_activity7__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* EuActivity7 :: Render Ring Busy */
#define dg1__eu_activity7__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity7 :: Compute Ring Busy */
#define dg1__eu_activity7__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity7 :: Render and compute engines are simultaneously busy */
#define dg1__eu_activity7__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity7 :: GTI Read Throughput */
#define dg1__eu_activity7__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity7 :: GTI Read Throughput */
#define dg1__eu_activity7__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity7 :: GTI Write Throughput */
#define dg1__eu_activity7__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity7 :: GTI Write Throughput */
#define dg1__eu_activity7__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity8 :: GPU Time Elapsed */
#define dg1__eu_activity8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity8 :: GPU Core Clocks */
#define dg1__eu_activity8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define dg1__eu_activity8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define dg1__eu_activity8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity8 :: GPU Busy */
#define dg1__eu_activity8__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity8 :: VS Threads Dispatched */
#define dg1__eu_activity8__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity8 :: HS Threads Dispatched */
#define dg1__eu_activity8__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity8 :: DS Threads Dispatched */
#define dg1__eu_activity8__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity8 :: GS Threads Dispatched */
#define dg1__eu_activity8__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity8 :: FS Threads Dispatched */
#define dg1__eu_activity8__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity8 :: CS Threads Dispatched */
#define dg1__eu_activity8__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity8 :: Render Ring Busy */
#define dg1__eu_activity8__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity8 :: Compute Ring Busy */
#define dg1__eu_activity8__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity8 :: Render and compute engines are simultaneously busy */
#define dg1__eu_activity8__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity8 :: GTI Read Throughput */
#define dg1__eu_activity8__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity8 :: GTI Read Throughput */
#define dg1__eu_activity8__gti_read_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity8 :: GTI Write Throughput */
#define dg1__eu_activity8__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity8 :: GTI Write Throughput */
#define dg1__eu_activity8__gti_write_throughput__max \
   chv__compute_basic__gti_ring_throughput__max

/* EuActivity8 :: DS Send Pipe Active */
#define dg1__eu_activity8__ds_send_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set TestOa :: GPU Time Elapsed */
#define dg1__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define dg1__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define dg1__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define dg1__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define dg1__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define dg1__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define dg1__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define dg1__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define dg1__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define dg1__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define dg1__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define dg1__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define dg1__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define dg1__test_oa__counter9__read \
   hsw__compute_extended__untyped_writes0__read

/* Render Metrics Basic set :: GPU Time Elapsed */
#define adl__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic set :: GPU Core Clocks */
#define adl__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define adl__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic set :: AVG GPU Core Frequency */
#define adl__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic set :: VS Threads Dispatched */
#define adl__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic set :: HS Threads Dispatched */
#define adl__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic set :: DS Threads Dispatched */
#define adl__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic set :: GS Threads Dispatched */
#define adl__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic set :: FS Threads Dispatched */
#define adl__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic set :: CS Threads Dispatched */
#define adl__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic set :: GPU Busy */
#define adl__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic set :: EU Active */
#define adl__render_basic__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Render Metrics Basic set :: EU Stall */
#define adl__render_basic__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Render Metrics Basic set :: EU Thread Occupancy */
#define adl__render_basic__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Render Metrics Basic set :: Sampler00 Busy */
#define adl__render_basic__sampler00_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Sampler Slice0 Dualsubslice0 is bottleneck */
#define adl__render_basic__sampler00_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Samplers Busy */
#define adl__render_basic__samplers_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics Basic set :: Samplers Bottleneck */
#define adl__render_basic__sampler_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics Basic set :: Rasterized Pixels */
#define adl__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic set :: Early Hi-Depth Test Fails */
#define adl__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic set :: Early Depth Test Fails */
#define adl__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: Samples Killed in FS */
#define adl__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic set :: Pixels Failing Tests */
#define adl__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic set :: Samples Written */
#define adl__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic set :: Samples Blended */
#define adl__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic set :: Sampler Texels */
#define adl__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic set :: Sampler Texels Misses */
#define adl__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define adl__render_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics Basic set :: SLM Bytes Read */
#define adl__render_basic__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: SLM Bytes Written */
#define adl__render_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics Basic set :: SLM Bytes Written */
#define adl__render_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Memory Accesses */
#define adl__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic set :: Shader Atomic Memory Accesses */
#define adl__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define adl__render_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics Basic set :: L3 Shader Throughput */
#define adl__render_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics Basic set :: Shader Barrier Messages */
#define adl__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define adl__render_basic__gti_read_throughput__read \
   tglgt1__render_basic__gti_read_throughput__read

/* Render Metrics Basic set :: GTI Read Throughput */
#define adl__render_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics Basic set :: GTI Write Throughput */
#define adl__render_basic__gti_write_throughput__read \
   tglgt1__render_basic__gti_write_throughput__read

/* Render Metrics Basic set :: GTI Write Throughput */
#define adl__render_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic :: GPU Time Elapsed */
#define adl__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic :: GPU Core Clocks */
#define adl__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define adl__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define adl__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic :: GPU Busy */
#define adl__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic :: VS Threads Dispatched */
#define adl__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic :: HS Threads Dispatched */
#define adl__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic :: DS Threads Dispatched */
#define adl__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic :: GS Threads Dispatched */
#define adl__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic :: FS Threads Dispatched */
#define adl__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic :: CS Threads Dispatched */
#define adl__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic :: EU Active */
#define adl__compute_basic__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Compute Metrics Basic :: EU Stall */
#define adl__compute_basic__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Compute Metrics Basic :: EU Thread Occupancy */
#define adl__compute_basic__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Compute Metrics Basic :: Rasterized Pixels */
#define adl__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic :: Early Hi-Depth Test Fails */
#define adl__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic :: Early Depth Test Fails */
#define adl__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic :: Samples Killed in FS */
#define adl__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic :: Pixels Failing Tests */
#define adl__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic :: Samples Written */
#define adl__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic :: Samples Blended */
#define adl__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic :: Sampler Texels */
#define adl__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic :: Sampler Texels Misses */
#define adl__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define adl__compute_basic__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define adl__compute_basic__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic :: SLM Bytes Written */
#define adl__compute_basic__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Compute Metrics Basic :: SLM Bytes Written */
#define adl__compute_basic__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Compute Metrics Basic :: Shader Memory Accesses */
#define adl__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic :: Shader Atomic Memory Accesses */
#define adl__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic :: L3 Shader Throughput */
#define adl__compute_basic__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Compute Metrics Basic :: L3 Shader Throughput */
#define adl__compute_basic__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Compute Metrics Basic :: Shader Barrier Messages */
#define adl__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define adl__compute_basic__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define adl__compute_basic__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Compute Metrics Basic :: GTI Write Throughput */
#define adl__compute_basic__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* Compute Metrics Basic :: GTI Write Throughput */
#define adl__compute_basic__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Time Elapsed */
#define adl__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics set for 3D Pipeline Profile :: GPU Core Clocks */
#define adl__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define adl__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics set for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define adl__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics set for 3D Pipeline Profile :: GPU Busy */
#define adl__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics set for 3D Pipeline Profile :: VS Threads Dispatched */
#define adl__render_pipe_profile__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: HS Threads Dispatched */
#define adl__render_pipe_profile__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: DS Threads Dispatched */
#define adl__render_pipe_profile__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics set for 3D Pipeline Profile :: GS Threads Dispatched */
#define adl__render_pipe_profile__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: FS Threads Dispatched */
#define adl__render_pipe_profile__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics set for 3D Pipeline Profile :: CS Threads Dispatched */
#define adl__render_pipe_profile__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics set for 3D Pipeline Profile :: EU Active */
#define adl__render_pipe_profile__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Render Metrics set for 3D Pipeline Profile :: EU Stall */
#define adl__render_pipe_profile__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Render Metrics set for 3D Pipeline Profile :: EU Thread Occupancy */
#define adl__render_pipe_profile__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Render Metrics set for 3D Pipeline Profile :: Rasterized Pixels */
#define adl__render_pipe_profile__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics set for 3D Pipeline Profile :: Early Hi-Depth Test Fails */
#define adl__render_pipe_profile__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Early Depth Test Fails */
#define adl__render_pipe_profile__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Killed in FS */
#define adl__render_pipe_profile__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics set for 3D Pipeline Profile :: Pixels Failing Tests */
#define adl__render_pipe_profile__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Written */
#define adl__render_pipe_profile__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics set for 3D Pipeline Profile :: Samples Blended */
#define adl__render_pipe_profile__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels */
#define adl__render_pipe_profile__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics set for 3D Pipeline Profile :: Sampler Texels Misses */
#define adl__render_pipe_profile__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define adl__render_pipe_profile__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Read */
#define adl__render_pipe_profile__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define adl__render_pipe_profile__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Render Metrics set for 3D Pipeline Profile :: SLM Bytes Written */
#define adl__render_pipe_profile__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Memory Accesses */
#define adl__render_pipe_profile__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics set for 3D Pipeline Profile :: Shader Atomic Memory Accesses */
#define adl__render_pipe_profile__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define adl__render_pipe_profile__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Render Metrics set for 3D Pipeline Profile :: L3 Shader Throughput */
#define adl__render_pipe_profile__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Render Metrics set for 3D Pipeline Profile :: Shader Barrier Messages */
#define adl__render_pipe_profile__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics set for 3D Pipeline Profile :: VF Bottleneck */
#define adl__render_pipe_profile__vf_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: VS Bottleneck */
#define adl__render_pipe_profile__vs_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: HS Bottleneck */
#define adl__render_pipe_profile__hs_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Bottleneck */
#define adl__render_pipe_profile__ds_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics set for 3D Pipeline Profile :: GS Bottleneck */
#define adl__render_pipe_profile__gs_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Bottleneck */
#define adl__render_pipe_profile__so_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Clipper Bottleneck */
#define adl__render_pipe_profile__cl_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Strip-Fans Bottleneck */
#define adl__render_pipe_profile__sf_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics set for 3D Pipeline Profile :: Hi-Depth Bottleneck */
#define adl__render_pipe_profile__hi_depth_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: BC Bottleneck */
#define adl__render_pipe_profile__bc_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics set for 3D Pipeline Profile :: HS Stall */
#define adl__render_pipe_profile__hs_stall__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: DS Stall */
#define adl__render_pipe_profile__ds_stall__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: SO Stall */
#define adl__render_pipe_profile__so_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics set for 3D Pipeline Profile :: CL Stall */
#define adl__render_pipe_profile__cl_stall__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics set for 3D Pipeline Profile :: SF Stall */
#define adl__render_pipe_profile__sf_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define adl__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define adl__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define adl__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define adl__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define adl__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: VS Threads Dispatched */
#define adl__hdc_and_sf__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: HS Threads Dispatched */
#define adl__hdc_and_sf__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set HDCAndSF :: DS Threads Dispatched */
#define adl__hdc_and_sf__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set HDCAndSF :: GS Threads Dispatched */
#define adl__hdc_and_sf__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set HDCAndSF :: FS Threads Dispatched */
#define adl__hdc_and_sf__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set HDCAndSF :: CS Threads Dispatched */
#define adl__hdc_and_sf__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set HDCAndSF :: EU Active */
#define adl__hdc_and_sf__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set HDCAndSF :: EU Stall */
#define adl__hdc_and_sf__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set HDCAndSF :: EU Thread Occupancy */
#define adl__hdc_and_sf__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set HDCAndSF :: Rasterized Pixels */
#define adl__hdc_and_sf__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */
#define adl__hdc_and_sf__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set HDCAndSF :: Early Depth Test Fails */
#define adl__hdc_and_sf__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Samples Killed in FS */
#define adl__hdc_and_sf__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set HDCAndSF :: Pixels Failing Tests */
#define adl__hdc_and_sf__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set HDCAndSF :: Samples Written */
#define adl__hdc_and_sf__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set HDCAndSF :: Samples Blended */
#define adl__hdc_and_sf__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set HDCAndSF :: Sampler Texels */
#define adl__hdc_and_sf__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set HDCAndSF :: Sampler Texels Misses */
#define adl__hdc_and_sf__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define adl__hdc_and_sf__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set HDCAndSF :: SLM Bytes Read */
#define adl__hdc_and_sf__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: SLM Bytes Written */
#define adl__hdc_and_sf__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set HDCAndSF :: SLM Bytes Written */
#define adl__hdc_and_sf__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Memory Accesses */
#define adl__hdc_and_sf__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */
#define adl__hdc_and_sf__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define adl__hdc_and_sf__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set HDCAndSF :: L3 Shader Throughput */
#define adl__hdc_and_sf__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set HDCAndSF :: Shader Barrier Messages */
#define adl__hdc_and_sf__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3 */
#define adl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3 */
#define adl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice2 Non-sampler Shader Access Stalled On L3 */
#define adl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice3 Non-sampler Shader Access Stalled On L3 */
#define adl__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice4 Non-sampler Shader Access Stalled On L3 */
#define adl__hdc_and_sf__non_sampler_shader04_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF :: Slice0 Dualsubslice5 Non-sampler Shader Access Stalled On L3 */
#define adl__hdc_and_sf__non_sampler_shader05_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: Polygon Data Ready */
#define adl__hdc_and_sf__poly_data_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */
#define adl__rasterizer_and_pixel_backend__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */
#define adl__rasterizer_and_pixel_backend__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define adl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */
#define adl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend :: GPU Busy */
#define adl__rasterizer_and_pixel_backend__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */
#define adl__rasterizer_and_pixel_backend__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */
#define adl__rasterizer_and_pixel_backend__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */
#define adl__rasterizer_and_pixel_backend__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */
#define adl__rasterizer_and_pixel_backend__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */
#define adl__rasterizer_and_pixel_backend__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */
#define adl__rasterizer_and_pixel_backend__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Metric set RasterizerAndPixelBackend :: EU Active */
#define adl__rasterizer_and_pixel_backend__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set RasterizerAndPixelBackend :: EU Stall */
#define adl__rasterizer_and_pixel_backend__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Metric set RasterizerAndPixelBackend :: EU Thread Occupancy */
#define adl__rasterizer_and_pixel_backend__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */
#define adl__rasterizer_and_pixel_backend__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */
#define adl__rasterizer_and_pixel_backend__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */
#define adl__rasterizer_and_pixel_backend__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */
#define adl__rasterizer_and_pixel_backend__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */
#define adl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Metric set RasterizerAndPixelBackend :: Samples Written */
#define adl__rasterizer_and_pixel_backend__samples_written__read \
   bdw__render_basic__samples_written__read

/* Metric set RasterizerAndPixelBackend :: Samples Blended */
#define adl__rasterizer_and_pixel_backend__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels */
#define adl__rasterizer_and_pixel_backend__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */
#define adl__rasterizer_and_pixel_backend__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define adl__rasterizer_and_pixel_backend__slm_bytes_read__read \
   bdw__render_basic__slm_bytes_read__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */
#define adl__rasterizer_and_pixel_backend__slm_bytes_read__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define adl__rasterizer_and_pixel_backend__slm_bytes_written__read \
   bdw__render_basic__slm_bytes_written__read

/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */
#define adl__rasterizer_and_pixel_backend__slm_bytes_written__max \
   tglgt1__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */
#define adl__rasterizer_and_pixel_backend__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */
#define adl__rasterizer_and_pixel_backend__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define adl__rasterizer_and_pixel_backend__l3_shader_throughput__read \
   icl__render_basic__l3_shader_throughput__read

/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */
#define adl__rasterizer_and_pixel_backend__l3_shader_throughput__max \
   bdw__render_basic__slm_bytes_read__max

/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */
#define adl__rasterizer_and_pixel_backend__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */
#define adl__rasterizer_and_pixel_backend__rasterizer0_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */
#define adl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define adl__rasterizer_and_pixel_backend__pixel_data00_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 PS Output Available */
#define adl__rasterizer_and_pixel_backend__ps_output00_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 PS Output Available */
#define adl__rasterizer_and_pixel_backend__ps_output01_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe2 PS Output Available */
#define adl__rasterizer_and_pixel_backend__ps_output02_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Pixel Values Ready */
#define adl__rasterizer_and_pixel_backend__pixel_values00_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 Pixel Values Ready */
#define adl__rasterizer_and_pixel_backend__pixel_values01_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: Slice0 Pipe2 Pixel Values Ready */
#define adl__rasterizer_and_pixel_backend__pixel_values02_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: SQ00 is full */
#define adl__rasterizer_and_pixel_backend__gt_request_queue00_full__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ01 is full */
#define adl__rasterizer_and_pixel_backend__gt_request_queue01_full__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend :: SQ10 is full */
#define adl__rasterizer_and_pixel_backend__gt_request_queue10_full__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend :: SQ11 is full */
#define adl__rasterizer_and_pixel_backend__gt_request_queue11_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3_1 :: GPU Time Elapsed */
#define adl__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_1 :: GPU Core Clocks */
#define adl__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_1 :: AVG GPU Core Frequency */
#define adl__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_1 :: AVG GPU Core Frequency */
#define adl__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_1 :: GPU Busy */
#define adl__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_1 :: EU Active */
#define adl__l3_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_1 :: EU Stall */
#define adl__l3_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_1 :: EU Thread Occupancy */
#define adl__l3_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_1 :: VS Threads Dispatched */
#define adl__l3_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_1 :: HS Threads Dispatched */
#define adl__l3_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_1 :: DS Threads Dispatched */
#define adl__l3_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_1 :: GS Threads Dispatched */
#define adl__l3_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_1 :: FS Threads Dispatched */
#define adl__l3_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_1 :: CS Threads Dispatched */
#define adl__l3_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_1 :: Slice0 L3 Bank0 Input Available */
#define adl__l3_1__l30_bank0_input_available__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L3_1 :: Slice0 L3 Bank1 Input Available */
#define adl__l3_1__l30_bank1_input_available__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L3_1 :: Slice0 L3 Bank4 Input Available */
#define adl__l3_1__l30_bank4_input_available__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L3_1 :: Slice0 L3 Bank5 Input Available */
#define adl__l3_1__l30_bank5_input_available__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L3_2 :: GPU Time Elapsed */
#define adl__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_2 :: GPU Core Clocks */
#define adl__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_2 :: AVG GPU Core Frequency */
#define adl__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_2 :: AVG GPU Core Frequency */
#define adl__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_2 :: GPU Busy */
#define adl__l3_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_2 :: VS Threads Dispatched */
#define adl__l3_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_2 :: HS Threads Dispatched */
#define adl__l3_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_2 :: DS Threads Dispatched */
#define adl__l3_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_2 :: GS Threads Dispatched */
#define adl__l3_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_2 :: FS Threads Dispatched */
#define adl__l3_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_2 :: CS Threads Dispatched */
#define adl__l3_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_2 :: EU Active */
#define adl__l3_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_2 :: EU Stall */
#define adl__l3_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_2 :: EU Thread Occupancy */
#define adl__l3_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_2 :: Slice0 L3 Bank2 Input Available */
#define adl__l3_2__l30_bank2_input_available__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L3_2 :: Slice0 L3 Bank3 Input Available */
#define adl__l3_2__l30_bank3_input_available__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L3_2 :: Slice0 L3 Bank6 Input Available */
#define adl__l3_2__l30_bank6_input_available__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L3_2 :: Slice0 L3 Bank7 Input Available */
#define adl__l3_2__l30_bank7_input_available__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L3_3 :: GPU Time Elapsed */
#define adl__l3_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_3 :: GPU Core Clocks */
#define adl__l3_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_3 :: AVG GPU Core Frequency */
#define adl__l3_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_3 :: AVG GPU Core Frequency */
#define adl__l3_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_3 :: GPU Busy */
#define adl__l3_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_3 :: VS Threads Dispatched */
#define adl__l3_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_3 :: HS Threads Dispatched */
#define adl__l3_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_3 :: DS Threads Dispatched */
#define adl__l3_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_3 :: GS Threads Dispatched */
#define adl__l3_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_3 :: FS Threads Dispatched */
#define adl__l3_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_3 :: CS Threads Dispatched */
#define adl__l3_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_3 :: EU Active */
#define adl__l3_3__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_3 :: EU Stall */
#define adl__l3_3__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_3 :: EU Thread Occupancy */
#define adl__l3_3__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_3 :: Slice0 L3 Bank0 Output Ready */
#define adl__l3_3__l30_bank0_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_3 :: Slice0 L3 Bank4 Output Ready */
#define adl__l3_3__l30_bank4_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_4 :: GPU Time Elapsed */
#define adl__l3_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_4 :: GPU Core Clocks */
#define adl__l3_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_4 :: AVG GPU Core Frequency */
#define adl__l3_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_4 :: AVG GPU Core Frequency */
#define adl__l3_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_4 :: GPU Busy */
#define adl__l3_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_4 :: VS Threads Dispatched */
#define adl__l3_4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_4 :: HS Threads Dispatched */
#define adl__l3_4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_4 :: DS Threads Dispatched */
#define adl__l3_4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_4 :: GS Threads Dispatched */
#define adl__l3_4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_4 :: FS Threads Dispatched */
#define adl__l3_4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_4 :: CS Threads Dispatched */
#define adl__l3_4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_4 :: EU Active */
#define adl__l3_4__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_4 :: EU Stall */
#define adl__l3_4__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_4 :: EU Thread Occupancy */
#define adl__l3_4__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_4 :: Slice0 L3 Bank1 Output Ready */
#define adl__l3_4__l30_bank1_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_4 :: Slice0 L3 Bank5 Output Ready */
#define adl__l3_4__l30_bank5_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_5 :: GPU Time Elapsed */
#define adl__l3_5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_5 :: GPU Core Clocks */
#define adl__l3_5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_5 :: AVG GPU Core Frequency */
#define adl__l3_5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_5 :: AVG GPU Core Frequency */
#define adl__l3_5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_5 :: GPU Busy */
#define adl__l3_5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_5 :: VS Threads Dispatched */
#define adl__l3_5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_5 :: HS Threads Dispatched */
#define adl__l3_5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_5 :: DS Threads Dispatched */
#define adl__l3_5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_5 :: GS Threads Dispatched */
#define adl__l3_5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_5 :: FS Threads Dispatched */
#define adl__l3_5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_5 :: CS Threads Dispatched */
#define adl__l3_5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_5 :: EU Active */
#define adl__l3_5__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_5 :: EU Stall */
#define adl__l3_5__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_5 :: EU Thread Occupancy */
#define adl__l3_5__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_5 :: Slice0 L3 Bank2 Output Ready */
#define adl__l3_5__l30_bank2_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_5 :: Slice0 L3 Bank6 Output Ready */
#define adl__l3_5__l30_bank6_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* L3_6 :: GPU Time Elapsed */
#define adl__l3_6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_6 :: GPU Core Clocks */
#define adl__l3_6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_6 :: AVG GPU Core Frequency */
#define adl__l3_6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_6 :: AVG GPU Core Frequency */
#define adl__l3_6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_6 :: GPU Busy */
#define adl__l3_6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_6 :: VS Threads Dispatched */
#define adl__l3_6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* L3_6 :: HS Threads Dispatched */
#define adl__l3_6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* L3_6 :: DS Threads Dispatched */
#define adl__l3_6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* L3_6 :: GS Threads Dispatched */
#define adl__l3_6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* L3_6 :: FS Threads Dispatched */
#define adl__l3_6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* L3_6 :: CS Threads Dispatched */
#define adl__l3_6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* L3_6 :: EU Active */
#define adl__l3_6__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* L3_6 :: EU Stall */
#define adl__l3_6__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* L3_6 :: EU Thread Occupancy */
#define adl__l3_6__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* L3_6 :: Slice0 L3 Bank3 Output Ready */
#define adl__l3_6__l30_bank3_output_ready__read \
   tglgt1__l3_4__l30_bank1_output_ready__read

/* L3_6 :: Slice0 L3 Bank7 Output Ready */
#define adl__l3_6__l30_bank7_output_ready__read \
   tglgt1__l3_3__l30_bank0_output_ready__read

/* Sampler_1 :: GPU Time Elapsed */
#define adl__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_1 :: GPU Core Clocks */
#define adl__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define adl__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define adl__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_1 :: GPU Busy */
#define adl__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_1 :: VS Threads Dispatched */
#define adl__sampler_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Sampler_1 :: HS Threads Dispatched */
#define adl__sampler_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Sampler_1 :: DS Threads Dispatched */
#define adl__sampler_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Sampler_1 :: GS Threads Dispatched */
#define adl__sampler_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Sampler_1 :: FS Threads Dispatched */
#define adl__sampler_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Sampler_1 :: CS Threads Dispatched */
#define adl__sampler_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Sampler_1 :: EU Active */
#define adl__sampler_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Sampler_1 :: EU Stall */
#define adl__sampler_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Sampler_1 :: EU Thread Occupancy */
#define adl__sampler_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Sampler_1 :: Slice0 DualSubslice0 Input Available */
#define adl__sampler_1__sampler00_input_available__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice1 Input Available */
#define adl__sampler_1__sampler01_input_available__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice2 Input Available */
#define adl__sampler_1__sampler02_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice3 Input Available */
#define adl__sampler_1__sampler03_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_1 :: Slice0 DualSubslice4 Input Available */
#define adl__sampler_1__sampler04_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_1 :: Slice0 DualSubslice5 Input Available */
#define adl__sampler_1__sampler05_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_2 :: GPU Time Elapsed */
#define adl__sampler_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_2 :: GPU Core Clocks */
#define adl__sampler_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_2 :: AVG GPU Core Frequency */
#define adl__sampler_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_2 :: AVG GPU Core Frequency */
#define adl__sampler_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_2 :: GPU Busy */
#define adl__sampler_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_2 :: VS Threads Dispatched */
#define adl__sampler_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Sampler_2 :: HS Threads Dispatched */
#define adl__sampler_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Sampler_2 :: DS Threads Dispatched */
#define adl__sampler_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Sampler_2 :: GS Threads Dispatched */
#define adl__sampler_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Sampler_2 :: FS Threads Dispatched */
#define adl__sampler_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Sampler_2 :: CS Threads Dispatched */
#define adl__sampler_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Sampler_2 :: EU Active */
#define adl__sampler_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* Sampler_2 :: EU Stall */
#define adl__sampler_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* Sampler_2 :: EU Thread Occupancy */
#define adl__sampler_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* Sampler_2 :: Slice0 DualSubslice0 Sampler Output Ready */
#define adl__sampler_2__sampler00_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice1 Sampler Output Ready */
#define adl__sampler_2__sampler01_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice2 Sampler Output Ready */
#define adl__sampler_2__sampler02_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice3 Sampler Output Ready */
#define adl__sampler_2__sampler03_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_2 :: Slice0 DualSubslice4 Sampler Output Ready */
#define adl__sampler_2__sampler04_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_2 :: Slice0 DualSubslice5 Sampler Output Ready */
#define adl__sampler_2__sampler05_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_1 :: GPU Time Elapsed */
#define adl__tdl_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_1 :: GPU Core Clocks */
#define adl__tdl_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_1 :: AVG GPU Core Frequency */
#define adl__tdl_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_1 :: AVG GPU Core Frequency */
#define adl__tdl_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_1 :: GPU Busy */
#define adl__tdl_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_1 :: VS Threads Dispatched */
#define adl__tdl_1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_1 :: HS Threads Dispatched */
#define adl__tdl_1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_1 :: DS Threads Dispatched */
#define adl__tdl_1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_1 :: GS Threads Dispatched */
#define adl__tdl_1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_1 :: FS Threads Dispatched */
#define adl__tdl_1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_1 :: CS Threads Dispatched */
#define adl__tdl_1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_1 :: EU Active */
#define adl__tdl_1__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_1 :: EU Stall */
#define adl__tdl_1__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_1 :: EU Thread Occupancy */
#define adl__tdl_1__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice0 Thread Dispatcher */
#define adl__tdl_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice1 Thread Dispatcher */
#define adl__tdl_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice2 Thread Dispatcher */
#define adl__tdl_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice3 Thread Dispatcher */
#define adl__tdl_1__non_ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice4 Thread Dispatcher */
#define adl__tdl_1__non_ps_thread04_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_1 :: Non-PS Thread Ready For Dispatch on Slice0 DualSubslice5 Thread Dispatcher */
#define adl__tdl_1__non_ps_thread05_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 0 */
#define adl__tdl_1__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 1 */
#define adl__tdl_1__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 2 */
#define adl__tdl_1__thread_header00_ready_port2__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 3 */
#define adl__tdl_1__thread_header00_ready_port3__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 0 */
#define adl__tdl_1__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 1 */
#define adl__tdl_1__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 2 */
#define adl__tdl_1__thread_header01_ready_port2__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 3 */
#define adl__tdl_1__thread_header01_ready_port3__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher */
#define adl__tdl_1__thread_header00_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_1 :: Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher */
#define adl__tdl_1__thread_header01_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_2 :: GPU Time Elapsed */
#define adl__tdl_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_2 :: GPU Core Clocks */
#define adl__tdl_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_2 :: AVG GPU Core Frequency */
#define adl__tdl_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_2 :: AVG GPU Core Frequency */
#define adl__tdl_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_2 :: GPU Busy */
#define adl__tdl_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_2 :: VS Threads Dispatched */
#define adl__tdl_2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_2 :: HS Threads Dispatched */
#define adl__tdl_2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_2 :: DS Threads Dispatched */
#define adl__tdl_2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_2 :: GS Threads Dispatched */
#define adl__tdl_2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_2 :: FS Threads Dispatched */
#define adl__tdl_2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_2 :: CS Threads Dispatched */
#define adl__tdl_2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_2 :: EU Active */
#define adl__tdl_2__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_2 :: EU Stall */
#define adl__tdl_2__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_2 :: EU Thread Occupancy */
#define adl__tdl_2__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice0 Thread Dispatcher */
#define adl__tdl_2__ps_thread00_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice1 Thread Dispatcher */
#define adl__tdl_2__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice2 Thread Dispatcher */
#define adl__tdl_2__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice3 Thread Dispatcher */
#define adl__tdl_2__ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice4 Thread Dispatcher */
#define adl__tdl_2__ps_thread04_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_2 :: PS Thread Ready For Dispatch on Slice0 Dualsubslice5 Thread Dispatcher */
#define adl__tdl_2__ps_thread05_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher */
#define adl__tdl_2__thread_header05_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 0 */
#define adl__tdl_2__thread_header05_ready_port0__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 1 */
#define adl__tdl_2__thread_header05_ready_port1__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 2 */
#define adl__tdl_2__thread_header05_ready_port2__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_2 :: Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 3 */
#define adl__tdl_2__thread_header05_ready_port3__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_3 :: GPU Time Elapsed */
#define adl__tdl_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_3 :: GPU Core Clocks */
#define adl__tdl_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_3 :: AVG GPU Core Frequency */
#define adl__tdl_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_3 :: AVG GPU Core Frequency */
#define adl__tdl_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_3 :: GPU Busy */
#define adl__tdl_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_3 :: VS Threads Dispatched */
#define adl__tdl_3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* TDL_3 :: HS Threads Dispatched */
#define adl__tdl_3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* TDL_3 :: DS Threads Dispatched */
#define adl__tdl_3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* TDL_3 :: GS Threads Dispatched */
#define adl__tdl_3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* TDL_3 :: FS Threads Dispatched */
#define adl__tdl_3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* TDL_3 :: CS Threads Dispatched */
#define adl__tdl_3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* TDL_3 :: EU Active */
#define adl__tdl_3__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* TDL_3 :: EU Stall */
#define adl__tdl_3__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* TDL_3 :: EU Thread Occupancy */
#define adl__tdl_3__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher */
#define adl__tdl_3__thread_header02_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher */
#define adl__tdl_3__thread_header03_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher */
#define adl__tdl_3__thread_header04_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 0 */
#define adl__tdl_3__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 1 */
#define adl__tdl_3__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 2 */
#define adl__tdl_3__thread_header02_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 3 */
#define adl__tdl_3__thread_header02_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 0 */
#define adl__tdl_3__thread_header03_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 1 */
#define adl__tdl_3__thread_header03_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 2 */
#define adl__tdl_3__thread_header03_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 3 */
#define adl__tdl_3__thread_header03_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 0 */
#define adl__tdl_3__thread_header04_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 1 */
#define adl__tdl_3__thread_header04_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 2 */
#define adl__tdl_3__thread_header04_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_3 :: Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 3 */
#define adl__tdl_3__thread_header04_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* GpuBusyness :: GPU Time Elapsed */
#define adl__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define adl__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define adl__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define adl__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define adl__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: EU Active */
#define adl__gpu_busyness__eu_active__read \
   tglgt1__render_basic__eu_active__read

/* GpuBusyness :: EU Stall */
#define adl__gpu_busyness__eu_stall__read \
   tglgt1__render_basic__eu_stall__read

/* GpuBusyness :: EU Thread Occupancy */
#define adl__gpu_busyness__eu_thread_occupancy__read \
   tglgt1__render_basic__eu_thread_occupancy__read

/* GpuBusyness :: VS Threads Dispatched */
#define adl__gpu_busyness__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* GpuBusyness :: HS Threads Dispatched */
#define adl__gpu_busyness__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* GpuBusyness :: DS Threads Dispatched */
#define adl__gpu_busyness__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* GpuBusyness :: GS Threads Dispatched */
#define adl__gpu_busyness__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* GpuBusyness :: FS Threads Dispatched */
#define adl__gpu_busyness__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* GpuBusyness :: CS Threads Dispatched */
#define adl__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define adl__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* GpuBusyness :: Compute Ring Busy */
#define adl__gpu_busyness__compute_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* GpuBusyness :: Posh Ring Busy */
#define adl__gpu_busyness__posh_engine_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* GpuBusyness :: Blitter Ring Busy */
#define adl__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* GpuBusyness :: Vebox Ring Busy */
#define adl__gpu_busyness__vebox_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: Vdbox0 Ring Busy */
#define adl__gpu_busyness__vdbox0_busy__read \
   bdw__render_pipe_profile__ds_stall__read

/* GpuBusyness :: Vdbox1 Ring Busy */
#define adl__gpu_busyness__vdbox1_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* GpuBusyness :: Render and compute engines are simultaneously busy */
#define adl__gpu_busyness__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* GpuBusyness :: Any Engine Busy */
#define adl__gpu_busyness__any_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* EuActivity1 :: GPU Time Elapsed */
#define adl__eu_activity1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity1 :: GPU Core Clocks */
#define adl__eu_activity1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define adl__eu_activity1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity1 :: AVG GPU Core Frequency */
#define adl__eu_activity1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity1 :: GPU Busy */
#define adl__eu_activity1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity1 :: VS Threads Dispatched */
#define adl__eu_activity1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity1 :: HS Threads Dispatched */
#define adl__eu_activity1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity1 :: DS Threads Dispatched */
#define adl__eu_activity1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity1 :: GS Threads Dispatched */
#define adl__eu_activity1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity1 :: FS Threads Dispatched */
#define adl__eu_activity1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity1 :: CS Threads Dispatched */
#define adl__eu_activity1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity1 :: Render Ring Busy */
#define adl__eu_activity1__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity1 :: Compute Ring Busy */
#define adl__eu_activity1__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity1 :: Render and compute engines are simultaneously busy */
#define adl__eu_activity1__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity1 :: GTI Read Throughput */
#define adl__eu_activity1__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity1 :: GTI Read Throughput */
#define adl__eu_activity1__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity1 :: GTI Write Throughput */
#define adl__eu_activity1__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity1 :: GTI Write Throughput */
#define adl__eu_activity1__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity1 :: VS FPU Pipe Active */
#define adl__eu_activity1__vs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity1 :: PS FPU Pipe Active */
#define adl__eu_activity1__ps_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity1 :: EU Send Pipe Active */
#define adl__eu_activity1__eu_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity2 :: GPU Time Elapsed */
#define adl__eu_activity2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity2 :: GPU Core Clocks */
#define adl__eu_activity2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define adl__eu_activity2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity2 :: AVG GPU Core Frequency */
#define adl__eu_activity2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity2 :: GPU Busy */
#define adl__eu_activity2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity2 :: VS Threads Dispatched */
#define adl__eu_activity2__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity2 :: HS Threads Dispatched */
#define adl__eu_activity2__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity2 :: DS Threads Dispatched */
#define adl__eu_activity2__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity2 :: GS Threads Dispatched */
#define adl__eu_activity2__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity2 :: FS Threads Dispatched */
#define adl__eu_activity2__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity2 :: CS Threads Dispatched */
#define adl__eu_activity2__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity2 :: Render Ring Busy */
#define adl__eu_activity2__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity2 :: Compute Ring Busy */
#define adl__eu_activity2__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity2 :: Render and compute engines are simultaneously busy */
#define adl__eu_activity2__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity2 :: GTI Read Throughput */
#define adl__eu_activity2__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity2 :: GTI Read Throughput */
#define adl__eu_activity2__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity2 :: GTI Write Throughput */
#define adl__eu_activity2__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity2 :: GTI Write Throughput */
#define adl__eu_activity2__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity2 :: CS EM Pipe Active */
#define adl__eu_activity2__cs_em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity2 :: CS FPU Pipe Active */
#define adl__eu_activity2__cs_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity2 :: CS Send Pipeline Active */
#define adl__eu_activity2__cs_send_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: GPU Time Elapsed */
#define adl__eu_activity3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity3 :: GPU Core Clocks */
#define adl__eu_activity3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define adl__eu_activity3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity3 :: AVG GPU Core Frequency */
#define adl__eu_activity3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity3 :: GPU Busy */
#define adl__eu_activity3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity3 :: VS Threads Dispatched */
#define adl__eu_activity3__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity3 :: HS Threads Dispatched */
#define adl__eu_activity3__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity3 :: DS Threads Dispatched */
#define adl__eu_activity3__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity3 :: GS Threads Dispatched */
#define adl__eu_activity3__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity3 :: FS Threads Dispatched */
#define adl__eu_activity3__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity3 :: CS Threads Dispatched */
#define adl__eu_activity3__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity3 :: Render Ring Busy */
#define adl__eu_activity3__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity3 :: Compute Ring Busy */
#define adl__eu_activity3__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity3 :: Render and compute engines are simultaneously busy */
#define adl__eu_activity3__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity3 :: GTI Read Throughput */
#define adl__eu_activity3__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity3 :: GTI Read Throughput */
#define adl__eu_activity3__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity3 :: GTI Write Throughput */
#define adl__eu_activity3__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity3 :: GTI Write Throughput */
#define adl__eu_activity3__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity3 :: VS EM Pipe Active */
#define adl__eu_activity3__vs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity3 :: PS EM Pipe Active */
#define adl__eu_activity3__ps_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity3 :: PS Send Pipeline Active */
#define adl__eu_activity3__ps_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity4 :: GPU Time Elapsed */
#define adl__eu_activity4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity4 :: GPU Core Clocks */
#define adl__eu_activity4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define adl__eu_activity4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity4 :: AVG GPU Core Frequency */
#define adl__eu_activity4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity4 :: GPU Busy */
#define adl__eu_activity4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity4 :: VS Threads Dispatched */
#define adl__eu_activity4__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity4 :: HS Threads Dispatched */
#define adl__eu_activity4__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity4 :: DS Threads Dispatched */
#define adl__eu_activity4__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity4 :: GS Threads Dispatched */
#define adl__eu_activity4__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity4 :: FS Threads Dispatched */
#define adl__eu_activity4__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity4 :: CS Threads Dispatched */
#define adl__eu_activity4__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity4 :: Render Ring Busy */
#define adl__eu_activity4__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity4 :: Compute Ring Busy */
#define adl__eu_activity4__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity4 :: Render and compute engines are simultaneously busy */
#define adl__eu_activity4__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity4 :: GTI Read Throughput */
#define adl__eu_activity4__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity4 :: GTI Read Throughput */
#define adl__eu_activity4__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity4 :: GTI Write Throughput */
#define adl__eu_activity4__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity4 :: GTI Write Throughput */
#define adl__eu_activity4__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity4 :: HS FPU Pipe Active */
#define adl__eu_activity4__hs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity4 :: DS FPU Pipe Active */
#define adl__eu_activity4__ds_fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity4 :: VS Send Pipe Active */
#define adl__eu_activity4__vs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity5 :: GPU Time Elapsed */
#define adl__eu_activity5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity5 :: GPU Core Clocks */
#define adl__eu_activity5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define adl__eu_activity5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity5 :: AVG GPU Core Frequency */
#define adl__eu_activity5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity5 :: GPU Busy */
#define adl__eu_activity5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity5 :: VS Threads Dispatched */
#define adl__eu_activity5__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity5 :: HS Threads Dispatched */
#define adl__eu_activity5__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity5 :: DS Threads Dispatched */
#define adl__eu_activity5__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity5 :: GS Threads Dispatched */
#define adl__eu_activity5__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity5 :: FS Threads Dispatched */
#define adl__eu_activity5__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity5 :: CS Threads Dispatched */
#define adl__eu_activity5__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity5 :: Render Ring Busy */
#define adl__eu_activity5__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity5 :: Compute Ring Busy */
#define adl__eu_activity5__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity5 :: Render and compute engines are simultaneously busy */
#define adl__eu_activity5__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity5 :: GTI Read Throughput */
#define adl__eu_activity5__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity5 :: GTI Read Throughput */
#define adl__eu_activity5__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity5 :: GTI Write Throughput */
#define adl__eu_activity5__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity5 :: GTI Write Throughput */
#define adl__eu_activity5__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity5 :: HS EM Pipe Active */
#define adl__eu_activity5__hs_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity5 :: DS EM Pipe Active */
#define adl__eu_activity5__ds_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity5 :: HS Send Pipe Active */
#define adl__eu_activity5__hs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity6 :: GPU Time Elapsed */
#define adl__eu_activity6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity6 :: GPU Core Clocks */
#define adl__eu_activity6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define adl__eu_activity6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity6 :: AVG GPU Core Frequency */
#define adl__eu_activity6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity6 :: GPU Busy */
#define adl__eu_activity6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity6 :: VS Threads Dispatched */
#define adl__eu_activity6__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity6 :: HS Threads Dispatched */
#define adl__eu_activity6__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity6 :: DS Threads Dispatched */
#define adl__eu_activity6__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity6 :: GS Threads Dispatched */
#define adl__eu_activity6__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity6 :: FS Threads Dispatched */
#define adl__eu_activity6__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity6 :: CS Threads Dispatched */
#define adl__eu_activity6__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity6 :: Render Ring Busy */
#define adl__eu_activity6__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity6 :: Compute Ring Busy */
#define adl__eu_activity6__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity6 :: Render and compute engines are simultaneously busy */
#define adl__eu_activity6__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity6 :: GTI Read Throughput */
#define adl__eu_activity6__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity6 :: GTI Read Throughput */
#define adl__eu_activity6__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity6 :: GTI Write Throughput */
#define adl__eu_activity6__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity6 :: GTI Write Throughput */
#define adl__eu_activity6__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity6 :: GS FPU Pipe Active */
#define adl__eu_activity6__gs_fpu_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity6 :: GS EM Pipe Active */
#define adl__eu_activity6__gs_em_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity6 :: GS Send Pipe Active */
#define adl__eu_activity6__gs_send_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: GPU Time Elapsed */
#define adl__eu_activity7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity7 :: GPU Core Clocks */
#define adl__eu_activity7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define adl__eu_activity7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity7 :: AVG GPU Core Frequency */
#define adl__eu_activity7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity7 :: GPU Busy */
#define adl__eu_activity7__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity7 :: VS Threads Dispatched */
#define adl__eu_activity7__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity7 :: HS Threads Dispatched */
#define adl__eu_activity7__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity7 :: DS Threads Dispatched */
#define adl__eu_activity7__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity7 :: GS Threads Dispatched */
#define adl__eu_activity7__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity7 :: FS Threads Dispatched */
#define adl__eu_activity7__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity7 :: CS Threads Dispatched */
#define adl__eu_activity7__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity7 :: EU FPU Pipe Active */
#define adl__eu_activity7__fpu_active__read \
   tglgt1__render_basic__eu_stall__read

/* EuActivity7 :: EM Pipe Active */
#define adl__eu_activity7__em_active__read \
   tglgt1__eu_activity1__eu_send_active__read

/* EuActivity7 :: EU FPU And EM Pipes Active */
#define adl__eu_activity7__eu_fpu_em_active__read \
   tglgt1__render_basic__eu_active__read

/* EuActivity7 :: EU AVG IPC Rate */
#define adl__eu_activity7__eu_avg_ipc_rate__read \
   tglgt1__eu_activity7__eu_avg_ipc_rate__read

/* EuActivity7 :: EU AVG IPC Rate */
#define adl__eu_activity7__eu_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* EuActivity7 :: Render Ring Busy */
#define adl__eu_activity7__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity7 :: Compute Ring Busy */
#define adl__eu_activity7__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity7 :: Render and compute engines are simultaneously busy */
#define adl__eu_activity7__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity7 :: GTI Read Throughput */
#define adl__eu_activity7__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity7 :: GTI Read Throughput */
#define adl__eu_activity7__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity7 :: GTI Write Throughput */
#define adl__eu_activity7__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity7 :: GTI Write Throughput */
#define adl__eu_activity7__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: GPU Time Elapsed */
#define adl__eu_activity8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* EuActivity8 :: GPU Core Clocks */
#define adl__eu_activity8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define adl__eu_activity8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* EuActivity8 :: AVG GPU Core Frequency */
#define adl__eu_activity8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* EuActivity8 :: GPU Busy */
#define adl__eu_activity8__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* EuActivity8 :: VS Threads Dispatched */
#define adl__eu_activity8__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* EuActivity8 :: HS Threads Dispatched */
#define adl__eu_activity8__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* EuActivity8 :: DS Threads Dispatched */
#define adl__eu_activity8__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* EuActivity8 :: GS Threads Dispatched */
#define adl__eu_activity8__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* EuActivity8 :: FS Threads Dispatched */
#define adl__eu_activity8__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* EuActivity8 :: CS Threads Dispatched */
#define adl__eu_activity8__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* EuActivity8 :: Render Ring Busy */
#define adl__eu_activity8__render_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* EuActivity8 :: Compute Ring Busy */
#define adl__eu_activity8__compute_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* EuActivity8 :: Render and compute engines are simultaneously busy */
#define adl__eu_activity8__render_and_compute_busy__read \
   bdw__render_basic__sampler0_busy__read

/* EuActivity8 :: GTI Read Throughput */
#define adl__eu_activity8__gti_read_throughput__read \
   tglgt1__compute_basic__gti_read_throughput__read

/* EuActivity8 :: GTI Read Throughput */
#define adl__eu_activity8__gti_read_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: GTI Write Throughput */
#define adl__eu_activity8__gti_write_throughput__read \
   tglgt1__compute_basic__gti_write_throughput__read

/* EuActivity8 :: GTI Write Throughput */
#define adl__eu_activity8__gti_write_throughput__max \
   bdw__render_basic__gti_vf_throughput__max

/* EuActivity8 :: DS Send Pipe Active */
#define adl__eu_activity8__ds_send_active__read \
   tglgt1__render_basic__eu_active__read

/* Metric set TestOa :: GPU Time Elapsed */
#define adl__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define adl__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define adl__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define adl__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define adl__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define adl__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define adl__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define adl__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define adl__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define adl__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define adl__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define adl__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define adl__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define adl__test_oa__counter9__read \
   hsw__compute_extended__untyped_writes0__read

/* Render Metrics Basic - aggregation approximation :: GPU Time Elapsed */
#define acmgt1__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic - aggregation approximation :: GPU Core Clocks */
#define acmgt1__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic - aggregation approximation :: AVG GPU Core Frequency */
#define acmgt1__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic - aggregation approximation :: AVG GPU Core Frequency */
#define acmgt1__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic - aggregation approximation :: CS Threads Dispatched */
#define acmgt1__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic - aggregation approximation :: GPU Busy */
#define acmgt1__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic - aggregation approximation :: XVE Active */
#define acmgt1__render_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic - aggregation approximation :: XVE Stall */
#define acmgt1__render_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic - aggregation approximation :: XVE Thread Occupancy */
static float
acmgt1__render_basic__xve_thread_occupancy__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 8 A 9 READ FMUL $VectorEngineThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 9];
   double tmp1 = 8 * tmp0;
   double tmp2 = tmp1;
   double tmp3 = perf->devinfo.num_thread_per_eu;
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;
   uint64_t tmp5 = tmp4;
   uint64_t tmp6 = perf->sys_vars.n_eus;
   uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0;
   uint64_t tmp8 = tmp7 * 100;
   double tmp9 = tmp8;
   double tmp10 = acmgt1__render_basic__gpu_core_clocks__read(perf, query, results);
   double tmp11 = tmp10 ? tmp9 / tmp10 : 0;

   return tmp11;
}

/* Render Metrics Basic - aggregation approximation :: EM And FPU Pipes Active */
#define acmgt1__render_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic - aggregation approximation :: VS FPU Pipe Active */
#define acmgt1__render_basic__vs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic - aggregation approximation :: VS EM Pipe Active */
#define acmgt1__render_basic__vs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic - aggregation approximation :: VS Send Pipe Active */
#define acmgt1__render_basic__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Render Metrics Basic - aggregation approximation :: FS FPU Pipe Active */
#define acmgt1__render_basic__ps_fpu_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Render Metrics Basic - aggregation approximation :: FS EM Pipe Active */
#define acmgt1__render_basic__ps_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic - aggregation approximation :: FS Send Pipe Active */
#define acmgt1__render_basic__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic - aggregation approximation :: Samples Written */
#define acmgt1__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic - aggregation approximation :: Samples Blended */
#define acmgt1__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic - aggregation approximation :: Sampler Texels */
#define acmgt1__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic - aggregation approximation :: Sampler Texels Misses */
#define acmgt1__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic - aggregation approximation :: SLM Bytes Read */
#define acmgt1__render_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Render Metrics Basic - aggregation approximation :: SLM Bytes Read */
static uint64_t
acmgt1__render_basic__slm_reads__max(struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks $XeCoreTotalCount UMUL */
   uint64_t tmp0 = acmgt1__render_basic__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eu_sub_slices;

   return tmp0;
}

/* Render Metrics Basic - aggregation approximation :: SLM Writes */
static uint64_t
acmgt1__render_basic__slm_writes__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: A 31 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 31];

   return tmp0;
}

/* Render Metrics Basic - aggregation approximation :: SLM Writes */
#define acmgt1__render_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Render Metrics Basic - aggregation approximation :: Shader Memory Accesses */
#define acmgt1__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic - aggregation approximation :: Shader Atomic Memory Accesses */
#define acmgt1__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic - aggregation approximation :: Shader Barrier Messages */
#define acmgt1__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic - aggregation approximation :: GTI Read Throughput */
static uint64_t
acmgt1__render_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: 128  A 36 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 36];
   uint64_t tmp1 = 128 * tmp0;

   return tmp1;
}

/* Render Metrics Basic - aggregation approximation :: GTI Read Throughput */
static uint64_t
acmgt1__render_basic__gti_read_throughput__max(struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks 512 UMUL */
   uint64_t tmp0 = acmgt1__render_basic__gpu_core_clocks__read(perf, query, results) * 512;

   return tmp0;
}

/* Render Metrics Basic - aggregation approximation :: GTI Write Throughput */
static uint64_t
acmgt1__render_basic__gti_write_throughput__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ C 7 READ UADD 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 128;

   return tmp3;
}

/* Render Metrics Basic - aggregation approximation :: GTI Write Throughput */
#define acmgt1__render_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Render Metrics Basic - aggregation approximation :: Sampler Slice2 Xe Core0 is busy */
#define acmgt1__render_basic__sampler20_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics Basic - aggregation approximation :: Samplers Busy */
#define acmgt1__render_basic__samplers_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics Basic - aggregation approximation :: Sampler20 Bottleneck */
#define acmgt1__render_basic__sampler20_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics Basic - aggregation approximation :: Samplers Bottleneck */
#define acmgt1__render_basic__sampler_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Compute Metrics Basic :: GPU Time Elapsed */
#define acmgt1__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic :: GPU Core Clocks */
#define acmgt1__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define acmgt1__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define acmgt1__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic :: GPU Busy */
#define acmgt1__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic :: CS Threads Dispatched */
#define acmgt1__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic :: XVE Active */
#define acmgt1__compute_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic :: XVE Stall */
#define acmgt1__compute_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic :: XVE FPU Pipe Active */
#define acmgt1__compute_basic__fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic :: EM Pipe Active */
#define acmgt1__compute_basic__em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic :: XMX Pipe Active */
#define acmgt1__compute_basic__xmx_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic :: EM And FPU Pipes Active */
#define acmgt1__compute_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic :: XMX And FPU Pipes Active */
#define acmgt1__compute_basic__xve_fpu_xmx_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics Basic :: XVE AVG IPC Rate */
static float
acmgt1__compute_basic__xve_avg_ipc_rate__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: A 12 READ  A 9 READ  A 10 READ FADD  A 10 READ FSUB FDIV 1 FADD */
   uint64_t tmp0 = results->accumulator[query->a_offset + 12];
   uint64_t tmp1 = results->accumulator[query->a_offset + 9];
   uint64_t tmp2 = results->accumulator[query->a_offset + 10];
   double tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = results->accumulator[query->a_offset + 10];
   double tmp5 = tmp3 - tmp4;
   double tmp6 = tmp0;
   double tmp7 = tmp5;
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;
   double tmp9 = tmp8 + 1;

   return tmp9;
}

/* Compute Metrics Basic :: XVE AVG IPC Rate */
#define acmgt1__compute_basic__xve_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic :: Send Pipe Active */
#define acmgt1__compute_basic__send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics Basic :: XVE Thread Occupancy */
static float
acmgt1__compute_basic__xve_thread_occupancy__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: 8 A 15 READ FMUL $VectorEngineThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 15];
   double tmp1 = 8 * tmp0;
   double tmp2 = tmp1;
   double tmp3 = perf->devinfo.num_thread_per_eu;
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;
   uint64_t tmp5 = tmp4;
   uint64_t tmp6 = perf->sys_vars.n_eus;
   uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0;
   uint64_t tmp8 = tmp7 * 100;
   double tmp9 = tmp8;
   double tmp10 = acmgt1__compute_basic__gpu_core_clocks__read(perf, query, results);
   double tmp11 = tmp10 ? tmp9 / tmp10 : 0;

   return tmp11;
}

/* Compute Metrics Basic :: FPU FLT16 Instruction */
#define acmgt1__compute_basic__xve_fpu_flt16__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics Basic :: FPU FLT32 Instruction */
#define acmgt1__compute_basic__xve_fpu_flt32__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics Basic :: FPU FLT64 Instruction */
#define acmgt1__compute_basic__xve_fpu_flt64__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define acmgt1__compute_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define acmgt1__compute_basic__slm_reads__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: SLM Writes */
#define acmgt1__compute_basic__slm_writes__read \
   acmgt1__render_basic__slm_writes__read

/* Compute Metrics Basic :: SLM Writes */
#define acmgt1__compute_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: Shader Memory Accesses */
#define acmgt1__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic :: Shader Atomic Memory Accesses */
#define acmgt1__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic :: Shader Barrier Messages */
#define acmgt1__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define acmgt1__compute_basic__gti_read_throughput__read \
   acmgt1__render_basic__gti_read_throughput__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define acmgt1__compute_basic__gti_read_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Compute Metrics Basic :: GTI Write Throughput */
static uint64_t
acmgt1__compute_basic__gti_write_throughput__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ UADD 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 128;

   return tmp3;
}

/* Compute Metrics Basic :: GTI Write Throughput */
#define acmgt1__compute_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* ThreadsAndRast1 :: GPU Time Elapsed */
#define acmgt1__threads_and_rast1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadsAndRast1 :: GPU Core Clocks */
#define acmgt1__threads_and_rast1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadsAndRast1 :: AVG GPU Core Frequency */
#define acmgt1__threads_and_rast1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadsAndRast1 :: AVG GPU Core Frequency */
#define acmgt1__threads_and_rast1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadsAndRast1 :: VS Threads Dispatched */
#define acmgt1__threads_and_rast1__vs_threads__read \
   hsw__sampler_balance__sampler_l2_cache_misses__read

/* ThreadsAndRast1 :: HS Threads Dispatched */
static uint64_t
acmgt1__threads_and_rast1__hs_threads__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 6 READ UADD B 5 READ UADD B 4 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;

   return tmp6;
}

/* ThreadsAndRast1 :: DS Threads Dispatched */
static uint64_t
acmgt1__threads_and_rast1__ds_threads__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ B 2 READ UADD B 1 READ UADD B 0 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = results->accumulator[query->b_offset + 2];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 1];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 0];
   uint64_t tmp6 = tmp4 + tmp5;

   return tmp6;
}

/* ThreadsAndRast2 :: GPU Time Elapsed */
#define acmgt1__threads_and_rast2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadsAndRast2 :: GPU Core Clocks */
#define acmgt1__threads_and_rast2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadsAndRast2 :: AVG GPU Core Frequency */
#define acmgt1__threads_and_rast2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadsAndRast2 :: AVG GPU Core Frequency */
#define acmgt1__threads_and_rast2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadsAndRast2 :: PS Threads Dispatched */
static uint64_t
acmgt1__threads_and_rast2__ps_threads__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ UADD B 2 READ UADD B 3 READ UADD B 4 READ UADD B 5 READ UADD B 6 READ UADD B 7 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 2];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 3];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 4];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->b_offset + 5];
   uint64_t tmp10 = tmp8 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 6];
   uint64_t tmp12 = tmp10 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 7];
   uint64_t tmp14 = tmp12 + tmp13;

   return tmp14;
}

/* ThreadsAndRast3 :: GPU Time Elapsed */
#define acmgt1__threads_and_rast3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadsAndRast3 :: GPU Core Clocks */
#define acmgt1__threads_and_rast3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadsAndRast3 :: AVG GPU Core Frequency */
#define acmgt1__threads_and_rast3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadsAndRast3 :: AVG GPU Core Frequency */
#define acmgt1__threads_and_rast3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadsAndRast3 :: GS Threads Dispatched */
static uint64_t
acmgt1__threads_and_rast3__gs_threads__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ UADD C 5 READ UADD C 4 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;

   return tmp6;
}

/* ThreadsAndRast3 :: Early Hi-Depth Test Fails */
static uint64_t
acmgt1__threads_and_rast3__hi_depth_test_fails__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: 4 2 UMUL C 3 READ 2 C 2 READ UMUL UADD 4 C 1 READ UMUL UADD 8 C 0 READ UMUL UADD 16 B 7 READ UMUL UADD 32 B 6 READ UMUL UADD 64 B 5 READ UMUL UADD 128 B 4 READ UMUL UADD 256 B 3 READ UMUL UADD 512 B 2 READ UMUL UADD 1024 B 1 READ UMUL UADD UMUL */
   uint64_t tmp0 = 4 * 2;
   uint64_t tmp1 = results->accumulator[query->c_offset + 3];
   uint64_t tmp2 = results->accumulator[query->c_offset + 2];
   uint64_t tmp3 = 2 * tmp2;
   uint64_t tmp4 = tmp1 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 1];
   uint64_t tmp6 = 4 * tmp5;
   uint64_t tmp7 = tmp4 + tmp6;
   uint64_t tmp8 = results->accumulator[query->c_offset + 0];
   uint64_t tmp9 = 8 * tmp8;
   uint64_t tmp10 = tmp7 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 7];
   uint64_t tmp12 = 16 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->b_offset + 6];
   uint64_t tmp15 = 32 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->b_offset + 5];
   uint64_t tmp18 = 64 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = results->accumulator[query->b_offset + 4];
   uint64_t tmp21 = 128 * tmp20;
   uint64_t tmp22 = tmp19 + tmp21;
   uint64_t tmp23 = results->accumulator[query->b_offset + 3];
   uint64_t tmp24 = 256 * tmp23;
   uint64_t tmp25 = tmp22 + tmp24;
   uint64_t tmp26 = results->accumulator[query->b_offset + 2];
   uint64_t tmp27 = 512 * tmp26;
   uint64_t tmp28 = tmp25 + tmp27;
   uint64_t tmp29 = results->accumulator[query->b_offset + 1];
   uint64_t tmp30 = 1024 * tmp29;
   uint64_t tmp31 = tmp28 + tmp30;
   uint64_t tmp32 = tmp0 * tmp31;

   return tmp32;
}

/* ThreadsAndRast4 :: GPU Time Elapsed */
#define acmgt1__threads_and_rast4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadsAndRast4 :: GPU Core Clocks */
#define acmgt1__threads_and_rast4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadsAndRast4 :: AVG GPU Core Frequency */
#define acmgt1__threads_and_rast4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadsAndRast4 :: AVG GPU Core Frequency */
#define acmgt1__threads_and_rast4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadsAndRast4 :: Early Depth Test Fails */
static uint64_t
acmgt1__threads_and_rast4__early_depth_test_fails__read(UNUSED struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: 4 C 7 READ C 6 READ UADD 2 C 5 READ C 4 READ UADD UMUL UADD 4 C 3 READ C 2 READ UADD UMUL UADD 8 C 1 READ C 0 READ UADD UMUL UADD 16 B 7 READ B 6 READ UADD UMUL UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   uint64_t tmp4 = results->accumulator[query->c_offset + 4];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = 2 * tmp5;
   uint64_t tmp7 = tmp2 + tmp6;
   uint64_t tmp8 = results->accumulator[query->c_offset + 3];
   uint64_t tmp9 = results->accumulator[query->c_offset + 2];
   uint64_t tmp10 = tmp8 + tmp9;
   uint64_t tmp11 = 4 * tmp10;
   uint64_t tmp12 = tmp7 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 1];
   uint64_t tmp14 = results->accumulator[query->c_offset + 0];
   uint64_t tmp15 = tmp13 + tmp14;
   uint64_t tmp16 = 8 * tmp15;
   uint64_t tmp17 = tmp12 + tmp16;
   uint64_t tmp18 = results->accumulator[query->b_offset + 7];
   uint64_t tmp19 = results->accumulator[query->b_offset + 6];
   uint64_t tmp20 = tmp18 + tmp19;
   uint64_t tmp21 = 16 * tmp20;
   uint64_t tmp22 = tmp17 + tmp21;
   uint64_t tmp23 = 4 * tmp22;

   return tmp23;
}

/* AsyncCompute :: GPU Time Elapsed */
#define acmgt1__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define acmgt1__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define acmgt1__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define acmgt1__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define acmgt1__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: CS Threads Dispatched */
#define acmgt1__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: XVE FPU Pipe Active */
#define acmgt1__async_compute__fpu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: VS FPU Pipe Active */
#define acmgt1__async_compute__vs_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* AsyncCompute :: FS FPU Pipe Active */
#define acmgt1__async_compute__ps_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: CS FPU Pipe Active */
#define acmgt1__async_compute__cs_fpu_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: ASYNC CS FPU Pipe Active */
#define acmgt1__async_compute__async_cs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: EM Pipe Active */
#define acmgt1__async_compute__em_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: VS EM Pipe Active */
#define acmgt1__async_compute__vs_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: FS EM Pipe Active */
#define acmgt1__async_compute__ps_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: CS EM Pipe Active */
#define acmgt1__async_compute__cs_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: ASYNC CS EM Pipe Active */
#define acmgt1__async_compute__async_cs_em_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: XVE Thread Occupancy */
static float
acmgt1__async_compute__xve_thread_occupancy__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: 8 A 17 READ FMUL $VectorEngineThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];
   double tmp1 = 8 * tmp0;
   double tmp2 = tmp1;
   double tmp3 = perf->devinfo.num_thread_per_eu;
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;
   uint64_t tmp5 = tmp4;
   uint64_t tmp6 = perf->sys_vars.n_eus;
   uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0;
   uint64_t tmp8 = tmp7 * 100;
   double tmp9 = tmp8;
   double tmp10 = acmgt1__async_compute__gpu_core_clocks__read(perf, query, results);
   double tmp11 = tmp10 ? tmp9 / tmp10 : 0;

   return tmp11;
}

/* AsyncCompute :: XVE Active */
#define acmgt1__async_compute__xve_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* AsyncCompute :: XVE Stall */
#define acmgt1__async_compute__xve_stall__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* XveActivity1 :: GPU Time Elapsed */
#define acmgt1__xve_activity1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* XveActivity1 :: GPU Core Clocks */
#define acmgt1__xve_activity1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* XveActivity1 :: AVG GPU Core Frequency */
#define acmgt1__xve_activity1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* XveActivity1 :: AVG GPU Core Frequency */
#define acmgt1__xve_activity1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* XveActivity1 :: GPU Busy */
#define acmgt1__xve_activity1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* XveActivity1 :: CS Threads Dispatched */
#define acmgt1__xve_activity1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* XveActivity1 :: HS FPU Pipe Active */
#define acmgt1__xve_activity1__hs_fpu_active__read \
   bdw__render_basic__eu_active__read

/* XveActivity1 :: DS FPU Pipe Active */
#define acmgt1__xve_activity1__ds_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* XveActivity1 :: GS FPU Pipe Active */
#define acmgt1__xve_activity1__gs_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* XveActivity1 :: HS EM Pipe Active */
#define acmgt1__xve_activity1__hs_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* XveActivity1 :: DS EM Pipe Active */
#define acmgt1__xve_activity1__ds_em_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* XveActivity1 :: GS EM Pipe Active */
#define acmgt1__xve_activity1__gs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* XveActivity1 :: HS Send Pipe Active */
#define acmgt1__xve_activity1__hs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* XveActivity1 :: DS Send Pipe Active */
#define acmgt1__xve_activity1__ds_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* XveActivity1 :: GS Send Pipe Active */
#define acmgt1__xve_activity1__gs_send_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* XveActivity1 :: CS Send Pipe Active */
#define acmgt1__xve_activity1__cs_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* GpuBusyness :: GPU Time Elapsed */
#define acmgt1__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define acmgt1__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define acmgt1__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define acmgt1__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define acmgt1__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: XVE Active */
#define acmgt1__gpu_busyness__xve_active__read \
   bdw__render_basic__eu_active__read

/* GpuBusyness :: XVE Stall */
#define acmgt1__gpu_busyness__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* GpuBusyness :: XVE Thread Occupancy */
#define acmgt1__gpu_busyness__xve_thread_occupancy__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* GpuBusyness :: CS Threads Dispatched */
#define acmgt1__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define acmgt1__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: ComputeEngine0 Ring Busy */
#define acmgt1__gpu_busyness__compute_engine0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* GpuBusyness :: ComputeEngine1 Ring Busy */
#define acmgt1__gpu_busyness__compute_engine1_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* GpuBusyness :: ComputeEngine2 Ring Busy */
#define acmgt1__gpu_busyness__compute_engine2_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* GpuBusyness :: ComputeEngine3 Ring Busy */
#define acmgt1__gpu_busyness__compute_engine3_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* GpuBusyness :: Blitter Ring Busy */
#define acmgt1__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* GpuBusyness :: Vdbox00 Ring Busy */
#define acmgt1__gpu_busyness__vdbox00_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* GpuBusyness :: Vebox0 Ring Busy */
#define acmgt1__gpu_busyness__vebox0_busy__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* GpuBusyness :: Vdbox10 Ring Busy */
#define acmgt1__gpu_busyness__vdbox10_busy__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* GpuBusyness :: Vebox1 Ring Busy */
#define acmgt1__gpu_busyness__vebox1_busy__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* GpuBusyness :: Any compute engine busy */
#define acmgt1__gpu_busyness__any_compute_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* GpuBusyness :: Render and any compute engines are simultaneously busy */
#define acmgt1__gpu_busyness__render_and_any_compute_engine_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt1__render_pipe_profile1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt1__render_pipe_profile1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt1__render_pipe_profile1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt1__render_pipe_profile1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt1__render_pipe_profile1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF2 Bottleneck */
#define acmgt1__render_pipe_profile1__vf2_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS2 Bottleneck */
#define acmgt1__render_pipe_profile1__vs2_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper2 Bottleneck */
#define acmgt1__render_pipe_profile1__cl2_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS2 Bottleneck */
#define acmgt1__render_pipe_profile1__hs2_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS2 Bottleneck */
#define acmgt1__render_pipe_profile1__ds2_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS2 Bottleneck */
#define acmgt1__render_pipe_profile1__gs2_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF2 Bottleneck */
#define acmgt1__render_pipe_profile1__sf2_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO2 Bottleneck */
#define acmgt1__render_pipe_profile1__so2_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL2 Stall */
#define acmgt1__render_pipe_profile1__cl2_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS2 Stall */
#define acmgt1__render_pipe_profile1__hs2_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS2 Stall */
#define acmgt1__render_pipe_profile1__ds2_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF2 Stall */
#define acmgt1__render_pipe_profile1__sf2_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO2 Stall */
#define acmgt1__render_pipe_profile1__so2_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth20 Bottleneck */
#define acmgt1__render_pipe_profile1__hi_depth20_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC20 Bottleneck */
#define acmgt1__render_pipe_profile1__bc20_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt1__render_pipe_profile2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt1__render_pipe_profile2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt1__render_pipe_profile2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt1__render_pipe_profile2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt1__render_pipe_profile2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF3 Bottleneck */
#define acmgt1__render_pipe_profile2__vf3_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS3 Bottleneck */
#define acmgt1__render_pipe_profile2__vs3_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper3 Bottleneck */
#define acmgt1__render_pipe_profile2__cl3_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS3 Bottleneck */
#define acmgt1__render_pipe_profile2__hs3_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS3 Bottleneck */
#define acmgt1__render_pipe_profile2__ds3_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS3 Bottleneck */
#define acmgt1__render_pipe_profile2__gs3_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF3 Bottleneck */
#define acmgt1__render_pipe_profile2__sf3_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO3 Bottleneck */
#define acmgt1__render_pipe_profile2__so3_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL3 Stall */
#define acmgt1__render_pipe_profile2__cl3_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS3 Stall */
#define acmgt1__render_pipe_profile2__hs3_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS3 Stall */
#define acmgt1__render_pipe_profile2__ds3_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF3 Stall */
#define acmgt1__render_pipe_profile2__sf3_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO3 Stall */
#define acmgt1__render_pipe_profile2__so3_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth30 Bottleneck */
#define acmgt1__render_pipe_profile2__hi_depth30_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC30 Bottleneck */
#define acmgt1__render_pipe_profile2__bc30_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* L3 :: GPU Time Elapsed */
#define acmgt1__l3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3 :: GPU Core Clocks */
#define acmgt1__l3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3 :: AVG GPU Core Frequency */
#define acmgt1__l3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3 :: AVG GPU Core Frequency */
#define acmgt1__l3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3 :: GPU Busy */
#define acmgt1__l3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3 :: Quad1 L3 Bank0 Input Available */
#define acmgt1__l3__l31_bank0_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3 :: Quad1 L3 Bank1 Input Available */
#define acmgt1__l3__l31_bank1_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3 :: Quad1 L3 Bank2 Input Available */
#define acmgt1__l3__l31_bank2_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3 :: Quad1 L3 Bank3 Input Available */
#define acmgt1__l3__l31_bank3_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3 :: Quad1 L3 Bank4 Input Available */
#define acmgt1__l3__l31_bank4_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* L3 :: Quad1 L3 Bank5 Input Available */
#define acmgt1__l3__l31_bank5_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3 :: Quad1 L3 Bank6 Input Available */
#define acmgt1__l3__l31_bank6_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3 :: Quad1 L3 Bank7 Input Available */
#define acmgt1__l3__l31_bank7_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3 :: Quad1 L3 Bank0 Output Ready */
#define acmgt1__l3__l31_bank0_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3 :: Quad1 L3 Bank1 Output Ready */
#define acmgt1__l3__l31_bank1_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3 :: Quad1 L3 Bank2 Output Ready */
#define acmgt1__l3__l31_bank2_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3 :: Quad1 L3 Bank3 Output Ready */
#define acmgt1__l3__l31_bank3_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3 :: Quad1 L3 Bank4 Output Ready */
#define acmgt1__l3__l31_bank4_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3 :: Quad1 L3 Bank5 Output Ready */
#define acmgt1__l3__l31_bank5_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3 :: Quad1 L3 Bank6 Output Ready */
#define acmgt1__l3__l31_bank6_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* L3 :: Quad1 L3 Bank7 Output Ready */
#define acmgt1__l3__l31_bank7_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_Slice23 :: GPU Time Elapsed */
#define acmgt1__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_Slice23 :: GPU Core Clocks */
#define acmgt1__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_Slice23 :: AVG GPU Core Frequency */
#define acmgt1__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_Slice23 :: AVG GPU Core Frequency */
#define acmgt1__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_Slice23 :: GPU Busy */
#define acmgt1__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_Slice23 :: Slice2 Xe Core0 Input Available */
#define acmgt1__sampler__sampler20_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core1 Input Available */
#define acmgt1__sampler__sampler21_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core2 Input Available */
#define acmgt1__sampler__sampler22_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler_Slice23 :: Slice2 Xe Core3 Input Available */
#define acmgt1__sampler__sampler23_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler_Slice23 :: Slice3 Xe Core0 Input Available */
#define acmgt1__sampler__sampler30_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler_Slice23 :: Slice3 Xe Core1 Input Available */
#define acmgt1__sampler__sampler31_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler_Slice23 :: Slice3 Xe Core2 Input Available */
#define acmgt1__sampler__sampler32_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler_Slice23 :: Slice3 Xe Core3 Input Available */
#define acmgt1__sampler__sampler33_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core0 Sampler Output Ready */
#define acmgt1__sampler__sampler20_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core1 Sampler Output Ready */
#define acmgt1__sampler__sampler21_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core2 Sampler Output Ready */
#define acmgt1__sampler__sampler22_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core3 Sampler Output Ready */
#define acmgt1__sampler__sampler23_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_Slice23 :: Slice3 Xe Core0 Sampler Output Ready */
#define acmgt1__sampler__sampler30_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_Slice23 :: Slice3 Xe Core1 Sampler Output Ready */
#define acmgt1__sampler__sampler31_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_Slice23 :: Slice3 Xe Core2 Sampler Output Ready */
#define acmgt1__sampler__sampler32_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_Slice23 :: Slice3 Xe Core3 Sampler Output Ready */
#define acmgt1__sampler__sampler33_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF1 :: GPU Time Elapsed */
#define acmgt1__hdc_and_sf1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF1 :: GPU Core Clocks */
#define acmgt1__hdc_and_sf1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF1 :: AVG GPU Core Frequency */
#define acmgt1__hdc_and_sf1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF1 :: AVG GPU Core Frequency */
#define acmgt1__hdc_and_sf1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF1 :: GPU Busy */
#define acmgt1__hdc_and_sf1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF1 :: Slice2 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt1__hdc_and_sf1__non_sampler_shader20_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF1 :: Slice2 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt1__hdc_and_sf1__non_sampler_shader21_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF1 :: Slice2 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt1__hdc_and_sf1__non_sampler_shader22_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF1 :: Slice2 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt1__hdc_and_sf1__non_sampler_shader23_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF1 :: Slice3 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt1__hdc_and_sf1__non_sampler_shader30_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF1 :: Slice3 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt1__hdc_and_sf1__non_sampler_shader31_access_stalled_on_l3__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set HDCAndSF1 :: Slice3 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt1__hdc_and_sf1__non_sampler_shader32_access_stalled_on_l3__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF1 :: Slice3 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt1__hdc_and_sf1__non_sampler_shader33_access_stalled_on_l3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set HDCAndSF2 :: GPU Time Elapsed */
#define acmgt1__hdc_and_sf2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF2 :: GPU Core Clocks */
#define acmgt1__hdc_and_sf2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF2 :: AVG GPU Core Frequency */
#define acmgt1__hdc_and_sf2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF2 :: AVG GPU Core Frequency */
#define acmgt1__hdc_and_sf2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF2 :: GPU Busy */
#define acmgt1__hdc_and_sf2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF2 :: Polygon (Slice2) Data Ready */
#define acmgt1__hdc_and_sf2__poly2_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF2 :: Polygon (Slice3) Data Ready */
#define acmgt1__hdc_and_sf2__poly3_data_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF2 :: SQ20 is full */
#define acmgt1__hdc_and_sf2__gt_request_queue20_full__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set HDCAndSF2 :: SQ30 is full */
#define acmgt1__hdc_and_sf2__gt_request_queue30_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Time Elapsed */
#define acmgt1__rasterizer_and_pixel_backend1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Core Clocks */
#define acmgt1__rasterizer_and_pixel_backend1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define acmgt1__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define acmgt1__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend1 :: GPU Busy */
#define acmgt1__rasterizer_and_pixel_backend1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice2 Rasterizer Input Available */
#define acmgt1__rasterizer_and_pixel_backend1__rasterizer2_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice3 Rasterizer Output Ready */
#define acmgt1__rasterizer_and_pixel_backend1__rasterizer3_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice2 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt1__rasterizer_and_pixel_backend1__pixel_data20_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice2 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt1__rasterizer_and_pixel_backend1__pixel_data21_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: PS10 Output Available */
#define acmgt1__rasterizer_and_pixel_backend1__ps_output10_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: PS11 Output Available */
#define acmgt1__rasterizer_and_pixel_backend1__ps_output11_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend1 :: Pixel Values 10 Ready */
#define acmgt1__rasterizer_and_pixel_backend1__pixel_values10_ready__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend1 :: Pixel Values 11 Ready */
#define acmgt1__rasterizer_and_pixel_backend1__pixel_values11_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Time Elapsed */
#define acmgt1__rasterizer_and_pixel_backend2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Core Clocks */
#define acmgt1__rasterizer_and_pixel_backend2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define acmgt1__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define acmgt1__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend2 :: GPU Busy */
#define acmgt1__rasterizer_and_pixel_backend2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice3 Rasterizer Input Available */
#define acmgt1__rasterizer_and_pixel_backend2__rasterizer3_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice2 Rasterizer Output Ready */
#define acmgt1__rasterizer_and_pixel_backend2__rasterizer2_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice3 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt1__rasterizer_and_pixel_backend2__pixel_data30_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice3 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt1__rasterizer_and_pixel_backend2__pixel_data31_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL1 :: GPU Time Elapsed */
#define acmgt1__tdl1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL1 :: GPU Core Clocks */
#define acmgt1__tdl1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL1 :: AVG GPU Core Frequency */
#define acmgt1__tdl1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL1 :: AVG GPU Core Frequency */
#define acmgt1__tdl1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL1 :: GPU Busy */
#define acmgt1__tdl1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher */
#define acmgt1__tdl1__non_ps_thread20_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher */
#define acmgt1__tdl1__non_ps_thread21_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher */
#define acmgt1__tdl1__non_ps_thread22_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher */
#define acmgt1__tdl1__non_ps_thread23_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher */
#define acmgt1__tdl1__non_ps_thread30_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher */
#define acmgt1__tdl1__non_ps_thread31_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher */
#define acmgt1__tdl1__non_ps_thread32_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher */
#define acmgt1__tdl1__non_ps_thread33_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt1__tdl1__thread_header23_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt1__tdl1__thread_header23_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt1__tdl1__thread_header23_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt1__tdl1__thread_header23_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt1__tdl1__thread_header33_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt1__tdl1__thread_header33_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt1__tdl1__thread_header33_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt1__tdl1__thread_header33_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL2 :: GPU Time Elapsed */
#define acmgt1__tdl2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL2 :: GPU Core Clocks */
#define acmgt1__tdl2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL2 :: AVG GPU Core Frequency */
#define acmgt1__tdl2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL2 :: AVG GPU Core Frequency */
#define acmgt1__tdl2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL2 :: GPU Busy */
#define acmgt1__tdl2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher */
#define acmgt1__tdl2__ps_thread20_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher */
#define acmgt1__tdl2__ps_thread21_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher */
#define acmgt1__tdl2__ps_thread22_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher */
#define acmgt1__tdl2__ps_thread23_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher */
#define acmgt1__tdl2__ps_thread30_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher */
#define acmgt1__tdl2__ps_thread31_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher */
#define acmgt1__tdl2__ps_thread32_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher */
#define acmgt1__tdl2__ps_thread33_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL3 :: GPU Time Elapsed */
#define acmgt1__tdl3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL3 :: GPU Core Clocks */
#define acmgt1__tdl3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL3 :: AVG GPU Core Frequency */
#define acmgt1__tdl3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL3 :: AVG GPU Core Frequency */
#define acmgt1__tdl3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL3 :: GPU Busy */
#define acmgt1__tdl3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher */
#define acmgt1__tdl3__thread_header20_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt1__tdl3__thread_header20_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt1__tdl3__thread_header20_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt1__tdl3__thread_header20_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt1__tdl3__thread_header20_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher */
#define acmgt1__tdl3__thread_header21_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt1__tdl3__thread_header21_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt1__tdl3__thread_header21_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt1__tdl3__thread_header21_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt1__tdl3__thread_header21_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher */
#define acmgt1__tdl3__thread_header22_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt1__tdl3__thread_header22_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt1__tdl3__thread_header22_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt1__tdl3__thread_header22_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt1__tdl3__thread_header22_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher */
#define acmgt1__tdl3__thread_header23_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL4 :: GPU Time Elapsed */
#define acmgt1__tdl4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL4 :: GPU Core Clocks */
#define acmgt1__tdl4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL4 :: AVG GPU Core Frequency */
#define acmgt1__tdl4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL4 :: AVG GPU Core Frequency */
#define acmgt1__tdl4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL4 :: GPU Busy */
#define acmgt1__tdl4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher */
#define acmgt1__tdl4__thread_header30_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt1__tdl4__thread_header30_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt1__tdl4__thread_header30_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt1__tdl4__thread_header30_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt1__tdl4__thread_header30_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher */
#define acmgt1__tdl4__thread_header31_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt1__tdl4__thread_header31_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt1__tdl4__thread_header31_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt1__tdl4__thread_header31_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt1__tdl4__thread_header31_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher */
#define acmgt1__tdl4__thread_header32_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt1__tdl4__thread_header32_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt1__tdl4__thread_header32_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt1__tdl4__thread_header32_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt1__tdl4__thread_header32_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher */
#define acmgt1__tdl4__thread_header33_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TestOa :: GPU Time Elapsed */
#define acmgt1__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define acmgt1__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define acmgt1__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define acmgt1__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define acmgt1__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define acmgt1__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define acmgt1__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define acmgt1__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define acmgt1__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define acmgt1__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define acmgt1__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define acmgt1__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define acmgt1__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define acmgt1__test_oa__counter9__read \
   hsw__compute_extended__untyped_writes0__read

/* ComputeOverview :: GPU Time Elapsed */
#define acmgt1__compute_overview__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ComputeOverview :: GPU Core Clocks */
#define acmgt1__compute_overview__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ComputeOverview :: AVG GPU Core Frequency */
#define acmgt1__compute_overview__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ComputeOverview :: AVG GPU Core Frequency */
#define acmgt1__compute_overview__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ComputeOverview :: L3 BYTE READ */
static uint64_t
acmgt1__compute_overview__l3_byte_read__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 6 READ UADD B 5 READ UADD B 4 READ UADD B 3 READ UADD B 2 READ UADD B 1 READ UADD B 0 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 3];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->b_offset + 2];
   uint64_t tmp10 = tmp8 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 1];
   uint64_t tmp12 = tmp10 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 0];
   uint64_t tmp14 = tmp12 + tmp13;
   uint64_t tmp15 = tmp14 * 64;

   return tmp15;
}

/* ComputeOverview :: L3 BYTE READ */
static uint64_t
acmgt1__compute_overview__l3_byte_read__max(struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: 256 $SliceTotalCount UMUL $GpuCoreClocks UMUL */
   uint64_t tmp0 = 256 * perf->sys_vars.n_eu_slices;
   uint64_t tmp1 = tmp0 * acmgt1__compute_overview__gpu_core_clocks__read(perf, query, results);

   return tmp1;
}

/* ComputeOverview :: L3 BYTE WRITE */
static uint64_t
acmgt1__compute_overview__l3_byte_write__read(UNUSED struct intel_perf_config *perf,
                                              const struct intel_perf_query_info *query,
                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ UADD C 5 READ UADD C 4 READ UADD C 3 READ UADD C 2 READ UADD C 1 READ UADD C 0 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 3];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->c_offset + 2];
   uint64_t tmp10 = tmp8 + tmp9;
   uint64_t tmp11 = results->accumulator[query->c_offset + 1];
   uint64_t tmp12 = tmp10 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 0];
   uint64_t tmp14 = tmp12 + tmp13;
   uint64_t tmp15 = tmp14 * 64;

   return tmp15;
}

/* ComputeOverview :: L3 BYTE WRITE */
#define acmgt1__compute_overview__l3_byte_write__max \
   acmgt1__compute_overview__l3_byte_read__max

/* ComputeOverview :: GPU MEMORY BYTE READ */
static uint64_t
acmgt1__compute_overview__gpu_memory_byte_read__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: A 36 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 36];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* ComputeOverview :: GPU MEMORY BYTE READ */
static uint64_t
acmgt1__compute_overview__gpu_memory_byte_read__max(struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: 64 $SliceTotalCount UMUL $GpuCoreClocks UMUL */
   uint64_t tmp0 = 64 * perf->sys_vars.n_eu_slices;
   uint64_t tmp1 = tmp0 * acmgt1__compute_overview__gpu_core_clocks__read(perf, query, results);

   return tmp1;
}

/* ComputeOverview :: GPU MEMORY BYTE WRITE */
static uint64_t
acmgt1__compute_overview__gpu_memory_byte_write__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: A 37 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 37];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* ComputeOverview :: GPU MEMORY BYTE WRITE */
#define acmgt1__compute_overview__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* ComputeOverview :: XVE ACTIVE */
#define acmgt1__compute_overview__xve_active__read \
   bdw__render_basic__eu_active__read

/* ComputeOverview :: XVE STALL */
#define acmgt1__compute_overview__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* ComputeOverview :: XVE BUSY */
static uint64_t
acmgt1__compute_overview__xve_busy__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 9 READ 0 UGT */
   uint64_t tmp0 = results->accumulator[query->a_offset + 9];
   uint64_t tmp1 = tmp0 > 0;

   return tmp1;
}

/* ComputeOverview :: XVE BUSY */
static uint64_t
acmgt1__compute_overview__xve_busy__max(struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: 1 */

   return 1;
}

/* ComputeOverview :: XVE THREADS OCCUPANCY ALL */
#define acmgt1__compute_overview__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* ComputeOverview :: XVE COMPUTE THREAD COUNT */
#define acmgt1__compute_overview__xve_compute_thread_count__read \
   bdw__render_basic__cs_threads__read

/* ComputeOverview :: XVE ATOMIC ACCESS COUNT */
#define acmgt1__compute_overview__xve_atomic_access_count__read \
   bdw__render_basic__shader_atomics__read

/* ComputeOverview :: XVE BARRIER MESSAGE COUNT */
#define acmgt1__compute_overview__xve_barrier_message_count__read \
   hsw__render_basic__early_depth_test_fails__read

/* ComputeOverview :: XVE INST EXECUTED ALU0 ALL */
#define acmgt1__compute_overview__xve_inst_executed_alu0_all__read \
   hsw__render_basic__hs_threads__read

/* ComputeOverview :: XVE INST EXECUTED ALU0 ALL */
static uint64_t
acmgt1__compute_overview__xve_inst_executed_alu0_all__max(struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks $VectorEngineTotalCount UMUL */
   uint64_t tmp0 = acmgt1__compute_overview__gpu_core_clocks__read(perf, query, results) * perf->sys_vars.n_eus;

   return tmp0;
}

/* ComputeOverview :: XVE INST EXECUTED ALU1 ALL */
static uint64_t
acmgt1__compute_overview__xve_inst_executed_alu1_all__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: A 11 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 11];

   return tmp0;
}

/* ComputeOverview :: XVE INST EXECUTED ALU1 ALL */
#define acmgt1__compute_overview__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* ComputeOverview :: XVE INST EXECUTED XMX ALL */
static uint64_t
acmgt1__compute_overview__xve_inst_executed_xmx_all__read(UNUSED struct intel_perf_config *perf,
                                                          const struct intel_perf_query_info *query,
                                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: A 12 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 12];

   return tmp0;
}

/* ComputeOverview :: XVE INST EXECUTED XMX ALL */
#define acmgt1__compute_overview__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* ComputeOverview :: XVE INST EXECUTED SEND ALL */
static uint64_t
acmgt1__compute_overview__xve_inst_executed_send_all__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: A 13 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 13];

   return tmp0;
}

/* ComputeOverview :: XVE INST EXECUTED SEND ALL */
#define acmgt1__compute_overview__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* ComputeOverview :: XVE INST EXECUTED CONTROL ALL */
static uint64_t
acmgt1__compute_overview__xve_inst_executed_control_all__read(UNUSED struct intel_perf_config *perf,
                                                              const struct intel_perf_query_info *query,
                                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: A 14 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 14];

   return tmp0;
}

/* ComputeOverview :: XVE INST EXECUTED CONTROL ALL */
#define acmgt1__compute_overview__xve_inst_executed_control_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* ComputeOverview :: XVE PIPE ALU0 AND ALU1 ACTIVE */
#define acmgt1__compute_overview__xve_pipe_alu0_and_alu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* ComputeOverview :: XVE PIPE ALU0 AND XMX ACTIVE */
#define acmgt1__compute_overview__xve_pipe_alu0_and_xmx_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* ComputeOverview :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define acmgt1__compute_overview__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* ComputeOverview :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define acmgt1__compute_overview__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* ComputeOverview :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define acmgt1__compute_overview__xve_inst_executed_send_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* ComputeOverview :: XVE INST EXECUTED CONTROL ALL UTILIZATION */
#define acmgt1__compute_overview__xve_inst_executed_control_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* ComputeOverview :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define acmgt1__compute_overview__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__vs_send_active__read

/* L1ProfileReads :: GPU Time Elapsed */
#define acmgt1__l1_profile_reads__xe_core0__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileReads :: GPU Core Clocks */
#define acmgt1__l1_profile_reads__xe_core0__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileReads :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_reads__xe_core0__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileReads :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_reads__xe_core0__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileReads :: LOAD STORE CACHE BYTE READ */
static uint64_t
acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__read(UNUSED struct intel_perf_config *perf,
                                                                     const struct intel_perf_query_info *query,
                                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: 4 $XeCoreTotalCount UMUL B 0 READ 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD 16 B 4 READ UMUL UADD 32 B 5 READ UMUL UADD 64 B 6 READ UMUL UADD UMUL $GtSlice0XeCore0 $GtSlice1XeCore0 UADD $GtSlice2XeCore0 UADD $GtSlice3XeCore0 UADD $GtSlice4XeCore0 UADD $GtSlice5XeCore0 UADD $GtSlice6XeCore0 UADD $GtSlice7XeCore0 UADD UDIV */
   uint64_t tmp0 = 4 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp1 = results->accumulator[query->b_offset + 0];
   uint64_t tmp2 = results->accumulator[query->b_offset + 1];
   uint64_t tmp3 = 2 * tmp2;
   uint64_t tmp4 = tmp1 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 2];
   uint64_t tmp6 = 4 * tmp5;
   uint64_t tmp7 = tmp4 + tmp6;
   uint64_t tmp8 = results->accumulator[query->b_offset + 3];
   uint64_t tmp9 = 8 * tmp8;
   uint64_t tmp10 = tmp7 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 4];
   uint64_t tmp12 = 16 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->b_offset + 5];
   uint64_t tmp15 = 32 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->b_offset + 6];
   uint64_t tmp18 = 64 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = tmp0 * tmp19;
   uint64_t tmp21 = intel_device_info_subslice_available(&perf->devinfo, 0, 0) + intel_device_info_subslice_available(&perf->devinfo, 1, 0);
   uint64_t tmp22 = tmp21 + intel_device_info_subslice_available(&perf->devinfo, 2, 0);
   uint64_t tmp23 = tmp22 + intel_device_info_subslice_available(&perf->devinfo, 3, 0);
   uint64_t tmp24 = tmp23 + intel_device_info_subslice_available(&perf->devinfo, 4, 0);
   uint64_t tmp25 = tmp24 + intel_device_info_subslice_available(&perf->devinfo, 5, 0);
   uint64_t tmp26 = tmp25 + intel_device_info_subslice_available(&perf->devinfo, 6, 0);
   uint64_t tmp27 = tmp26 + intel_device_info_subslice_available(&perf->devinfo, 7, 0);
   uint64_t tmp28 = tmp20;
   uint64_t tmp29 = tmp27;
   uint64_t tmp30 = tmp29 ? tmp28 / tmp29 : 0;

   return tmp30;
}

/* L1ProfileReads :: LOAD STORE CACHE BYTE READ */
static uint64_t
acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max(struct intel_perf_config *perf,
                                                                     const struct intel_perf_query_info *query,
                                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: 256  $XeCoreTotalCount UMUL $GpuCoreClocks UMUL */
   uint64_t tmp0 = 256 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp1 = tmp0 * acmgt1__l1_profile_reads__xe_core0__gpu_core_clocks__read(perf, query, results);

   return tmp1;
}

/* L1ProfileReads :: SLM BYTE READ */
static uint64_t
acmgt1__l1_profile_reads__xe_core0__slm_byte_read__read(UNUSED struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: 4 $XeCoreTotalCount UMUL C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD 16 C 3 READ UMUL UADD 32 C 2 READ UMUL UADD 64 C 1 READ UMUL UADD UMUL $GtSlice0XeCore0 $GtSlice1XeCore0 UADD $GtSlice2XeCore0 UADD $GtSlice3XeCore0 UADD $GtSlice4XeCore0 UADD $GtSlice5XeCore0 UADD $GtSlice6XeCore0 UADD $GtSlice7XeCore0 UADD UDIV */
   uint64_t tmp0 = 4 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   uint64_t tmp2 = results->accumulator[query->c_offset + 6];
   uint64_t tmp3 = 2 * tmp2;
   uint64_t tmp4 = tmp1 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 5];
   uint64_t tmp6 = 4 * tmp5;
   uint64_t tmp7 = tmp4 + tmp6;
   uint64_t tmp8 = results->accumulator[query->c_offset + 4];
   uint64_t tmp9 = 8 * tmp8;
   uint64_t tmp10 = tmp7 + tmp9;
   uint64_t tmp11 = results->accumulator[query->c_offset + 3];
   uint64_t tmp12 = 16 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->c_offset + 2];
   uint64_t tmp15 = 32 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->c_offset + 1];
   uint64_t tmp18 = 64 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = tmp0 * tmp19;
   uint64_t tmp21 = intel_device_info_subslice_available(&perf->devinfo, 0, 0) + intel_device_info_subslice_available(&perf->devinfo, 1, 0);
   uint64_t tmp22 = tmp21 + intel_device_info_subslice_available(&perf->devinfo, 2, 0);
   uint64_t tmp23 = tmp22 + intel_device_info_subslice_available(&perf->devinfo, 3, 0);
   uint64_t tmp24 = tmp23 + intel_device_info_subslice_available(&perf->devinfo, 4, 0);
   uint64_t tmp25 = tmp24 + intel_device_info_subslice_available(&perf->devinfo, 5, 0);
   uint64_t tmp26 = tmp25 + intel_device_info_subslice_available(&perf->devinfo, 6, 0);
   uint64_t tmp27 = tmp26 + intel_device_info_subslice_available(&perf->devinfo, 7, 0);
   uint64_t tmp28 = tmp20;
   uint64_t tmp29 = tmp27;
   uint64_t tmp30 = tmp29 ? tmp28 / tmp29 : 0;

   return tmp30;
}

/* L1ProfileReads :: SLM BYTE READ */
#define acmgt1__l1_profile_reads__xe_core0__slm_byte_read__max \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max

/* L1ProfileReads :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileReads :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileReads :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileReads :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileReads :: XVE ACTIVE */
#define acmgt1__l1_profile_reads__xe_core0__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileReads :: XVE STALL */
#define acmgt1__l1_profile_reads__xe_core0__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileReads :: XVE THREADS OCCUPANCY ALL */
#define acmgt1__l1_profile_reads__xe_core0__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileReads :: XVE BUSY */
#define acmgt1__l1_profile_reads__xe_core0__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileReads :: XVE BUSY */
#define acmgt1__l1_profile_reads__xe_core0__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileReads :: GPU Time Elapsed */
#define acmgt1__l1_profile_reads__xe_core3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileReads :: GPU Core Clocks */
#define acmgt1__l1_profile_reads__xe_core3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileReads :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_reads__xe_core3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileReads :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_reads__xe_core3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileReads :: LOAD STORE CACHE BYTE READ */
static uint64_t
acmgt1__l1_profile_reads__xe_core3__load_store_cache_byte_read__read(UNUSED struct intel_perf_config *perf,
                                                                     const struct intel_perf_query_info *query,
                                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: 4 $XeCoreTotalCount UMUL B 0 READ 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD 16 B 4 READ UMUL UADD 32 B 5 READ UMUL UADD 64 B 6 READ UMUL UADD UMUL $GtSlice0XeCore3 $GtSlice1XeCore3 UADD $GtSlice2XeCore3 UADD $GtSlice3XeCore3 UADD $GtSlice4XeCore3 UADD $GtSlice5XeCore3 UADD $GtSlice6XeCore3 UADD $GtSlice7XeCore3 UADD UDIV */
   uint64_t tmp0 = 4 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp1 = results->accumulator[query->b_offset + 0];
   uint64_t tmp2 = results->accumulator[query->b_offset + 1];
   uint64_t tmp3 = 2 * tmp2;
   uint64_t tmp4 = tmp1 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 2];
   uint64_t tmp6 = 4 * tmp5;
   uint64_t tmp7 = tmp4 + tmp6;
   uint64_t tmp8 = results->accumulator[query->b_offset + 3];
   uint64_t tmp9 = 8 * tmp8;
   uint64_t tmp10 = tmp7 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 4];
   uint64_t tmp12 = 16 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->b_offset + 5];
   uint64_t tmp15 = 32 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->b_offset + 6];
   uint64_t tmp18 = 64 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = tmp0 * tmp19;
   uint64_t tmp21 = intel_device_info_subslice_available(&perf->devinfo, 0, 3) + intel_device_info_subslice_available(&perf->devinfo, 1, 3);
   uint64_t tmp22 = tmp21 + intel_device_info_subslice_available(&perf->devinfo, 2, 3);
   uint64_t tmp23 = tmp22 + intel_device_info_subslice_available(&perf->devinfo, 3, 3);
   uint64_t tmp24 = tmp23 + intel_device_info_subslice_available(&perf->devinfo, 4, 3);
   uint64_t tmp25 = tmp24 + intel_device_info_subslice_available(&perf->devinfo, 5, 3);
   uint64_t tmp26 = tmp25 + intel_device_info_subslice_available(&perf->devinfo, 6, 3);
   uint64_t tmp27 = tmp26 + intel_device_info_subslice_available(&perf->devinfo, 7, 3);
   uint64_t tmp28 = tmp20;
   uint64_t tmp29 = tmp27;
   uint64_t tmp30 = tmp29 ? tmp28 / tmp29 : 0;

   return tmp30;
}

/* L1ProfileReads :: LOAD STORE CACHE BYTE READ */
#define acmgt1__l1_profile_reads__xe_core3__load_store_cache_byte_read__max \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max

/* L1ProfileReads :: SLM BYTE READ */
static uint64_t
acmgt1__l1_profile_reads__xe_core3__slm_byte_read__read(UNUSED struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: 4 $XeCoreTotalCount UMUL C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD 16 C 3 READ UMUL UADD 32 C 2 READ UMUL UADD 64 C 1 READ UMUL UADD UMUL $GtSlice0XeCore3 $GtSlice1XeCore3 UADD $GtSlice2XeCore3 UADD $GtSlice3XeCore3 UADD $GtSlice4XeCore3 UADD $GtSlice5XeCore3 UADD $GtSlice6XeCore3 UADD $GtSlice7XeCore3 UADD UDIV */
   uint64_t tmp0 = 4 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   uint64_t tmp2 = results->accumulator[query->c_offset + 6];
   uint64_t tmp3 = 2 * tmp2;
   uint64_t tmp4 = tmp1 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 5];
   uint64_t tmp6 = 4 * tmp5;
   uint64_t tmp7 = tmp4 + tmp6;
   uint64_t tmp8 = results->accumulator[query->c_offset + 4];
   uint64_t tmp9 = 8 * tmp8;
   uint64_t tmp10 = tmp7 + tmp9;
   uint64_t tmp11 = results->accumulator[query->c_offset + 3];
   uint64_t tmp12 = 16 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->c_offset + 2];
   uint64_t tmp15 = 32 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->c_offset + 1];
   uint64_t tmp18 = 64 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = tmp0 * tmp19;
   uint64_t tmp21 = intel_device_info_subslice_available(&perf->devinfo, 0, 3) + intel_device_info_subslice_available(&perf->devinfo, 1, 3);
   uint64_t tmp22 = tmp21 + intel_device_info_subslice_available(&perf->devinfo, 2, 3);
   uint64_t tmp23 = tmp22 + intel_device_info_subslice_available(&perf->devinfo, 3, 3);
   uint64_t tmp24 = tmp23 + intel_device_info_subslice_available(&perf->devinfo, 4, 3);
   uint64_t tmp25 = tmp24 + intel_device_info_subslice_available(&perf->devinfo, 5, 3);
   uint64_t tmp26 = tmp25 + intel_device_info_subslice_available(&perf->devinfo, 6, 3);
   uint64_t tmp27 = tmp26 + intel_device_info_subslice_available(&perf->devinfo, 7, 3);
   uint64_t tmp28 = tmp20;
   uint64_t tmp29 = tmp27;
   uint64_t tmp30 = tmp29 ? tmp28 / tmp29 : 0;

   return tmp30;
}

/* L1ProfileReads :: SLM BYTE READ */
#define acmgt1__l1_profile_reads__xe_core3__slm_byte_read__max \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max

/* L1ProfileReads :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileReads :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileReads :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileReads :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileReads :: XVE ACTIVE */
#define acmgt1__l1_profile_reads__xe_core3__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileReads :: XVE STALL */
#define acmgt1__l1_profile_reads__xe_core3__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileReads :: XVE THREADS OCCUPANCY ALL */
#define acmgt1__l1_profile_reads__xe_core3__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileReads :: XVE BUSY */
#define acmgt1__l1_profile_reads__xe_core3__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileReads :: XVE BUSY */
#define acmgt1__l1_profile_reads__xe_core3__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileSlmBankConflicts :: GPU Time Elapsed */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileSlmBankConflicts :: GPU Core Clocks */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileSlmBankConflicts :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileSlmBankConflicts :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileSlmBankConflicts :: SLM BANK CONFLICT COUNT */
static uint64_t
acmgt1__l1_profile_slm_bank_conflicts__xe_core0__slm_bank_conflict_count__read(UNUSED struct intel_perf_config *perf,
                                                                               const struct intel_perf_query_info *query,
                                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD C 3 READ 2 C 2 READ UMUL UADD 4 C 1 READ UMUL UADD 8 C 0 READ UMUL UADD UADD B 7 READ 2 B 6 READ UMUL UADD 4 B 5 READ UMUL UADD 8 B 4 READ UMUL UADD UADD B 3 READ 2 B 2 READ UMUL UADD 4 B 1 READ UMUL UADD 8 B 0 READ UMUL UADD UADD $XeCoreTotalCount UMUL $GtSlice0XeCore0 $GtSlice1XeCore0 UADD $GtSlice2XeCore0 UADD $GtSlice3XeCore0 UADD $GtSlice4XeCore0 UADD $GtSlice5XeCore0 UADD $GtSlice6XeCore0 UADD $GtSlice7XeCore0 UADD UDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = results->accumulator[query->c_offset + 2];
   uint64_t tmp12 = 2 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->c_offset + 1];
   uint64_t tmp15 = 4 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->c_offset + 0];
   uint64_t tmp18 = 8 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = tmp9 + tmp19;
   uint64_t tmp21 = results->accumulator[query->b_offset + 7];
   uint64_t tmp22 = results->accumulator[query->b_offset + 6];
   uint64_t tmp23 = 2 * tmp22;
   uint64_t tmp24 = tmp21 + tmp23;
   uint64_t tmp25 = results->accumulator[query->b_offset + 5];
   uint64_t tmp26 = 4 * tmp25;
   uint64_t tmp27 = tmp24 + tmp26;
   uint64_t tmp28 = results->accumulator[query->b_offset + 4];
   uint64_t tmp29 = 8 * tmp28;
   uint64_t tmp30 = tmp27 + tmp29;
   uint64_t tmp31 = tmp20 + tmp30;
   uint64_t tmp32 = results->accumulator[query->b_offset + 3];
   uint64_t tmp33 = results->accumulator[query->b_offset + 2];
   uint64_t tmp34 = 2 * tmp33;
   uint64_t tmp35 = tmp32 + tmp34;
   uint64_t tmp36 = results->accumulator[query->b_offset + 1];
   uint64_t tmp37 = 4 * tmp36;
   uint64_t tmp38 = tmp35 + tmp37;
   uint64_t tmp39 = results->accumulator[query->b_offset + 0];
   uint64_t tmp40 = 8 * tmp39;
   uint64_t tmp41 = tmp38 + tmp40;
   uint64_t tmp42 = tmp31 + tmp41;
   uint64_t tmp43 = tmp42 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp44 = intel_device_info_subslice_available(&perf->devinfo, 0, 0) + intel_device_info_subslice_available(&perf->devinfo, 1, 0);
   uint64_t tmp45 = tmp44 + intel_device_info_subslice_available(&perf->devinfo, 2, 0);
   uint64_t tmp46 = tmp45 + intel_device_info_subslice_available(&perf->devinfo, 3, 0);
   uint64_t tmp47 = tmp46 + intel_device_info_subslice_available(&perf->devinfo, 4, 0);
   uint64_t tmp48 = tmp47 + intel_device_info_subslice_available(&perf->devinfo, 5, 0);
   uint64_t tmp49 = tmp48 + intel_device_info_subslice_available(&perf->devinfo, 6, 0);
   uint64_t tmp50 = tmp49 + intel_device_info_subslice_available(&perf->devinfo, 7, 0);
   uint64_t tmp51 = tmp43;
   uint64_t tmp52 = tmp50;
   uint64_t tmp53 = tmp52 ? tmp51 / tmp52 : 0;

   return tmp53;
}

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileSlmBankConflicts :: XVE ACTIVE */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileSlmBankConflicts :: XVE STALL */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileSlmBankConflicts :: XVE THREADS OCCUPANCY ALL */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileSlmBankConflicts :: XVE BUSY */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileSlmBankConflicts :: XVE BUSY */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileSlmBankConflicts :: GPU Time Elapsed */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileSlmBankConflicts :: GPU Core Clocks */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileSlmBankConflicts :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileSlmBankConflicts :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileSlmBankConflicts :: SLM BANK CONFLICT COUNT */
static uint64_t
acmgt1__l1_profile_slm_bank_conflicts__xe_core3__slm_bank_conflict_count__read(UNUSED struct intel_perf_config *perf,
                                                                               const struct intel_perf_query_info *query,
                                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD C 3 READ 2 C 2 READ UMUL UADD 4 C 1 READ UMUL UADD 8 C 0 READ UMUL UADD UADD B 7 READ 2 B 6 READ UMUL UADD 4 B 5 READ UMUL UADD 8 B 4 READ UMUL UADD UADD B 3 READ 2 B 2 READ UMUL UADD 4 B 1 READ UMUL UADD 8 B 0 READ UMUL UADD UADD $XeCoreTotalCount UMUL $GtSlice0XeCore3 $GtSlice1XeCore3 UADD $GtSlice2XeCore3 UADD $GtSlice3XeCore3 UADD $GtSlice4XeCore3 UADD $GtSlice5XeCore3 UADD $GtSlice6XeCore3 UADD $GtSlice7XeCore3 UADD UDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = results->accumulator[query->c_offset + 2];
   uint64_t tmp12 = 2 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->c_offset + 1];
   uint64_t tmp15 = 4 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->c_offset + 0];
   uint64_t tmp18 = 8 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = tmp9 + tmp19;
   uint64_t tmp21 = results->accumulator[query->b_offset + 7];
   uint64_t tmp22 = results->accumulator[query->b_offset + 6];
   uint64_t tmp23 = 2 * tmp22;
   uint64_t tmp24 = tmp21 + tmp23;
   uint64_t tmp25 = results->accumulator[query->b_offset + 5];
   uint64_t tmp26 = 4 * tmp25;
   uint64_t tmp27 = tmp24 + tmp26;
   uint64_t tmp28 = results->accumulator[query->b_offset + 4];
   uint64_t tmp29 = 8 * tmp28;
   uint64_t tmp30 = tmp27 + tmp29;
   uint64_t tmp31 = tmp20 + tmp30;
   uint64_t tmp32 = results->accumulator[query->b_offset + 3];
   uint64_t tmp33 = results->accumulator[query->b_offset + 2];
   uint64_t tmp34 = 2 * tmp33;
   uint64_t tmp35 = tmp32 + tmp34;
   uint64_t tmp36 = results->accumulator[query->b_offset + 1];
   uint64_t tmp37 = 4 * tmp36;
   uint64_t tmp38 = tmp35 + tmp37;
   uint64_t tmp39 = results->accumulator[query->b_offset + 0];
   uint64_t tmp40 = 8 * tmp39;
   uint64_t tmp41 = tmp38 + tmp40;
   uint64_t tmp42 = tmp31 + tmp41;
   uint64_t tmp43 = tmp42 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp44 = intel_device_info_subslice_available(&perf->devinfo, 0, 3) + intel_device_info_subslice_available(&perf->devinfo, 1, 3);
   uint64_t tmp45 = tmp44 + intel_device_info_subslice_available(&perf->devinfo, 2, 3);
   uint64_t tmp46 = tmp45 + intel_device_info_subslice_available(&perf->devinfo, 3, 3);
   uint64_t tmp47 = tmp46 + intel_device_info_subslice_available(&perf->devinfo, 4, 3);
   uint64_t tmp48 = tmp47 + intel_device_info_subslice_available(&perf->devinfo, 5, 3);
   uint64_t tmp49 = tmp48 + intel_device_info_subslice_available(&perf->devinfo, 6, 3);
   uint64_t tmp50 = tmp49 + intel_device_info_subslice_available(&perf->devinfo, 7, 3);
   uint64_t tmp51 = tmp43;
   uint64_t tmp52 = tmp50;
   uint64_t tmp53 = tmp52 ? tmp51 / tmp52 : 0;

   return tmp53;
}

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileSlmBankConflicts :: XVE ACTIVE */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileSlmBankConflicts :: XVE STALL */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileSlmBankConflicts :: XVE THREADS OCCUPANCY ALL */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileSlmBankConflicts :: XVE BUSY */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileSlmBankConflicts :: XVE BUSY */
#define acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileWrites :: GPU Time Elapsed */
#define acmgt1__l1_profile_writes__xe_core0__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileWrites :: GPU Core Clocks */
#define acmgt1__l1_profile_writes__xe_core0__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileWrites :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_writes__xe_core0__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileWrites :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_writes__xe_core0__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileWrites :: LOAD STORE CACHE BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__read \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__read

/* L1ProfileWrites :: LOAD STORE CACHE BYTE WRITE */
static uint64_t
acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max(struct intel_perf_config *perf,
                                                                       const struct intel_perf_query_info *query,
                                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 128  $XeCoreTotalCount UMUL $GpuCoreClocks UMUL */
   uint64_t tmp0 = 128 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp1 = tmp0 * acmgt1__l1_profile_writes__xe_core0__gpu_core_clocks__read(perf, query, results);

   return tmp1;
}

/* L1ProfileWrites :: SLM BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core0__slm_byte_write__read \
   acmgt1__l1_profile_reads__xe_core0__slm_byte_read__read

/* L1ProfileWrites :: SLM BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core0__slm_byte_write__max \
   acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max

/* L1ProfileWrites :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileWrites :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileWrites :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileWrites :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileWrites :: XVE ACTIVE */
#define acmgt1__l1_profile_writes__xe_core0__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileWrites :: XVE STALL */
#define acmgt1__l1_profile_writes__xe_core0__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileWrites :: XVE THREADS OCCUPANCY ALL */
#define acmgt1__l1_profile_writes__xe_core0__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileWrites :: XVE BUSY */
#define acmgt1__l1_profile_writes__xe_core0__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileWrites :: XVE BUSY */
#define acmgt1__l1_profile_writes__xe_core0__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileWrites :: GPU Time Elapsed */
#define acmgt1__l1_profile_writes__xe_core3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileWrites :: GPU Core Clocks */
#define acmgt1__l1_profile_writes__xe_core3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileWrites :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_writes__xe_core3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileWrites :: AVG GPU Core Frequency */
#define acmgt1__l1_profile_writes__xe_core3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileWrites :: LOAD STORE CACHE BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core3__load_store_cache_byte_write__read \
   acmgt1__l1_profile_reads__xe_core3__load_store_cache_byte_read__read

/* L1ProfileWrites :: LOAD STORE CACHE BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core3__load_store_cache_byte_write__max \
   acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max

/* L1ProfileWrites :: SLM BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core3__slm_byte_write__read \
   acmgt1__l1_profile_reads__xe_core3__slm_byte_read__read

/* L1ProfileWrites :: SLM BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core3__slm_byte_write__max \
   acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max

/* L1ProfileWrites :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileWrites :: GPU MEMORY BYTE READ */
#define acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileWrites :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileWrites :: GPU MEMORY BYTE WRITE */
#define acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileWrites :: XVE ACTIVE */
#define acmgt1__l1_profile_writes__xe_core3__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileWrites :: XVE STALL */
#define acmgt1__l1_profile_writes__xe_core3__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileWrites :: XVE THREADS OCCUPANCY ALL */
#define acmgt1__l1_profile_writes__xe_core3__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileWrites :: XVE BUSY */
#define acmgt1__l1_profile_writes__xe_core3__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileWrites :: XVE BUSY */
#define acmgt1__l1_profile_writes__xe_core3__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* DataportReads :: GPU Time Elapsed */
#define acmgt1__dataport_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DataportReads :: GPU Core Clocks */
#define acmgt1__dataport_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DataportReads :: AVG GPU Core Frequency */
#define acmgt1__dataport_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DataportReads :: AVG GPU Core Frequency */
#define acmgt1__dataport_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DataportReads :: DATAPORT BYTE READ */
static uint64_t
acmgt1__dataport_reads__dataport_byte_read__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 64 2 UMUL B 4 READ B 0 READ UADD B 5 READ UADD B 1 READ UADD B 2 READ UADD B 6 READ UADD B 3 READ UADD B 7 READ UADD UMUL */
   uint64_t tmp0 = 64 * 2;
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = results->accumulator[query->b_offset + 0];
   uint64_t tmp3 = tmp1 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 5];
   uint64_t tmp5 = tmp3 + tmp4;
   uint64_t tmp6 = results->accumulator[query->b_offset + 1];
   uint64_t tmp7 = tmp5 + tmp6;
   uint64_t tmp8 = results->accumulator[query->b_offset + 2];
   uint64_t tmp9 = tmp7 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 6];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->b_offset + 3];
   uint64_t tmp13 = tmp11 + tmp12;
   uint64_t tmp14 = results->accumulator[query->b_offset + 7];
   uint64_t tmp15 = tmp13 + tmp14;
   uint64_t tmp16 = tmp0 * tmp15;

   return tmp16;
}

/* DataportReads :: DATAPORT BYTE READ */
static uint64_t
acmgt1__dataport_reads__dataport_byte_read__max(struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  $XeCoreTotalCount UMUL $GpuCoreClocks UMUL */
   uint64_t tmp0 = 64 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp1 = tmp0 * acmgt1__dataport_reads__gpu_core_clocks__read(perf, query, results);

   return tmp1;
}

/* DataportReads :: HOST TO GPUMEM BYTE READ */
static uint64_t
acmgt1__dataport_reads__host_to_gpumem_byte_read__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  C 6 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = 64 * tmp0;

   return tmp1;
}

/* DataportReads :: HOST TO GPUMEM BYTE READ */
static uint64_t
acmgt1__dataport_reads__host_to_gpumem_byte_read__max(struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 64 $GpuCoreClocks UMUL */
   uint64_t tmp0 = 64 * acmgt1__dataport_reads__gpu_core_clocks__read(perf, query, results);

   return tmp0;
}

/* DataportReads :: HOST TO GPUMEM BYTE WRITE */
static uint64_t
acmgt1__dataport_reads__host_to_gpumem_byte_write__read(UNUSED struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  C 7 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = 64 * tmp0;

   return tmp1;
}

/* DataportReads :: HOST TO GPUMEM BYTE WRITE */
#define acmgt1__dataport_reads__host_to_gpumem_byte_write__max \
   acmgt1__dataport_reads__host_to_gpumem_byte_read__max

/* DataportReads :: GPU MEMORY BYTE READ */
#define acmgt1__dataport_reads__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* DataportReads :: GPU MEMORY BYTE READ */
#define acmgt1__dataport_reads__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* DataportReads :: GPU MEMORY BYTE WRITE */
#define acmgt1__dataport_reads__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* DataportReads :: GPU MEMORY BYTE WRITE */
#define acmgt1__dataport_reads__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* DataportReads :: XVE ACTIVE */
#define acmgt1__dataport_reads__xve_active__read \
   bdw__render_basic__eu_active__read

/* DataportReads :: XVE STALL */
#define acmgt1__dataport_reads__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* DataportReads :: XVE BUSY */
#define acmgt1__dataport_reads__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* DataportReads :: XVE BUSY */
#define acmgt1__dataport_reads__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* DataportReads :: XVE THREADS OCCUPANCY ALL */
#define acmgt1__dataport_reads__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* DataportReads :: XVE COMPUTE THREAD COUNT */
#define acmgt1__dataport_reads__xve_compute_thread_count__read \
   bdw__render_basic__cs_threads__read

/* DataportWrites :: GPU Time Elapsed */
#define acmgt1__dataport_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DataportWrites :: GPU Core Clocks */
#define acmgt1__dataport_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DataportWrites :: AVG GPU Core Frequency */
#define acmgt1__dataport_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DataportWrites :: AVG GPU Core Frequency */
#define acmgt1__dataport_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DataportWrites :: DATAPORT BYTE WRITE */
static uint64_t
acmgt1__dataport_writes__dataport_byte_write__read(UNUSED struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: 32 B 4 READ B 5 READ UADD B 6 READ UADD B 7 READ UADD UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 6];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 7];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = 32 * tmp6;

   return tmp7;
}

/* DataportWrites :: DATAPORT BYTE WRITE */
static uint64_t
acmgt1__dataport_writes__dataport_byte_write__max(struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: 32 $XeCoreTotalCount UMUL $GpuCoreClocks UMUL */
   uint64_t tmp0 = 32 * perf->sys_vars.n_eu_sub_slices;
   uint64_t tmp1 = tmp0 * acmgt1__dataport_writes__gpu_core_clocks__read(perf, query, results);

   return tmp1;
}

/* DataportWrites :: SAMPLER L3 READ */
#define acmgt1__dataport_writes__sampler_l3_read__read \
   hsw__sampler_balance__sampler_l2_cache_misses__read

/* DataportWrites :: SYSMEM BYTE READ */
static uint64_t
acmgt1__dataport_writes__sysmem_byte_read__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  B 0 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = 64 * tmp0;

   return tmp1;
}

/* DataportWrites :: SYSMEM BYTE READ */
#define acmgt1__dataport_writes__sysmem_byte_read__max \
   acmgt1__dataport_reads__host_to_gpumem_byte_read__max

/* DataportWrites :: SYSMEM BYTE WRITE */
static uint64_t
acmgt1__dataport_writes__sysmem_byte_write__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 64  B 1 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = 64 * tmp0;

   return tmp1;
}

/* DataportWrites :: SYSMEM BYTE WRITE */
#define acmgt1__dataport_writes__sysmem_byte_write__max \
   acmgt1__dataport_reads__host_to_gpumem_byte_read__max

/* DataportWrites :: GPU MEMORY BYTE READ */
#define acmgt1__dataport_writes__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* DataportWrites :: GPU MEMORY BYTE READ */
#define acmgt1__dataport_writes__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* DataportWrites :: GPU MEMORY BYTE WRITE */
#define acmgt1__dataport_writes__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* DataportWrites :: GPU MEMORY BYTE WRITE */
#define acmgt1__dataport_writes__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* DataportWrites :: XVE ACTIVE */
#define acmgt1__dataport_writes__xve_active__read \
   bdw__render_basic__eu_active__read

/* DataportWrites :: XVE STALL */
#define acmgt1__dataport_writes__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* DataportWrites :: XVE BUSY */
#define acmgt1__dataport_writes__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* DataportWrites :: XVE BUSY */
#define acmgt1__dataport_writes__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* DataportWrites :: XVE THREADS OCCUPANCY ALL */
#define acmgt1__dataport_writes__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* DataportWrites :: XVE COMPUTE THREAD COUNT */
#define acmgt1__dataport_writes__xve_compute_thread_count__read \
   bdw__render_basic__cs_threads__read

/* Ext1 :: GPU Time Elapsed */
#define acmgt1__ext1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1 :: GPU Core Clocks */
#define acmgt1__ext1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1 :: AVG GPU Core Frequency */
#define acmgt1__ext1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1 :: AVG GPU Core Frequency */
#define acmgt1__ext1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1 :: GPU MEMORY BYTE WRITE SQIDI0 */
static uint64_t
acmgt1__ext1__gpu_memory_byte_write_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext1 :: GPU MEMORY BYTE WRITE SQIDI1 */
#define acmgt1__ext1__gpu_memory_byte_write_sqidi1__read \
   hsw__render_basic__gti_read_throughput__read

/* Ext1 :: GPU MEMORY WRITE SQIDI0 */
#define acmgt1__ext1__gpu_memory_write_sqidi0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext1 :: GPU MEMORY WRITE SQIDI1 */
#define acmgt1__ext1__gpu_memory_write_sqidi1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext1 :: GPU MEMORY WRITE */
#define acmgt1__ext1__gpu_memory_write__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI0 */
#define acmgt1__ext1__gpu_memory_read_sqidi0__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI1 */
static uint64_t
acmgt1__ext1__gpu_memory_read_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                           const struct intel_perf_query_info *query,
                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ B 2 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = results->accumulator[query->b_offset + 2];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext1 :: GPU MEMORY READ */
static uint64_t
acmgt1__ext1__gpu_memory_read__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_READ_SQIDI0 $GPU_MEMORY_READ_SQIDI1 UADD */
   uint64_t tmp0 = acmgt1__ext1__gpu_memory_read_sqidi0__read(perf, query, results) + acmgt1__ext1__gpu_memory_read_sqidi1__read(perf, query, results);

   return tmp0;
}

/* Ext1 :: GPU MEMORY BYTE READ SQIDI0 */
static uint64_t
acmgt1__ext1__gpu_memory_byte_read_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext1 :: GPU MEMORY BYTE READ SQIDI1 */
static uint64_t
acmgt1__ext1__gpu_memory_byte_read_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext1 :: GPU MEMORY ACTIVE SQIDI0 */
#define acmgt1__ext1__gpu_memory_active_sqidi0__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext1 :: GPU MEMORY ACTIVE SQIDI1 */
#define acmgt1__ext1__gpu_memory_active_sqidi1__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext1 :: GPU MEMORY BYTE READ */
static uint64_t
acmgt1__ext1__gpu_memory_byte_read__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ  C 4 READ UADD 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = results->accumulator[query->c_offset + 4];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = tmp2 * 128;

   return tmp3;
}

/* Ext1 :: GPU MEMORY BYTE READ */
#define acmgt1__ext1__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* Ext1 :: GPU MEMORY BYTE WRITE */
#define acmgt1__ext1__gpu_memory_byte_write__read \
   acmgt1__compute_basic__gti_write_throughput__read

/* Ext1 :: GPU MEMORY BYTE WRITE */
#define acmgt1__ext1__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* Ext1 :: SYSMEM TRANSACTION WRITE */
#define acmgt1__ext1__sysmem_transaction_write__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext1 :: SYSMEM TRANSACTION READ */
#define acmgt1__ext1__sysmem_transaction_read__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext1 :: GPU MEMORY BYTE READ BW SQIDI0 */
static float
acmgt1__ext1__gpu_memory_byte_read_bw_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_READ_SQIDI0 $GpuTime FDIV */
   double tmp0 = acmgt1__ext1__gpu_memory_byte_read_sqidi0__read(perf, query, results);
   double tmp1 = acmgt1__ext1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext1 :: GPU MEMORY BYTE READ BW SQIDI1 */
static float
acmgt1__ext1__gpu_memory_byte_read_bw_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_READ_SQIDI1 $GpuTime FDIV */
   double tmp0 = acmgt1__ext1__gpu_memory_byte_read_sqidi1__read(perf, query, results);
   double tmp1 = acmgt1__ext1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext1 :: GPU MEMORY BYTE WRITE BW SQIDI0 */
static float
acmgt1__ext1__gpu_memory_byte_write_bw_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI0 $GpuTime FDIV */
   double tmp0 = acmgt1__ext1__gpu_memory_byte_write_sqidi0__read(perf, query, results);
   double tmp1 = acmgt1__ext1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext1 :: GPU MEMORY BYTE WRITE BW SQIDI1 */
static float
acmgt1__ext1__gpu_memory_byte_write_bw_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI1 $GpuTime FDIV */
   double tmp0 = acmgt1__ext1__gpu_memory_byte_write_sqidi1__read(perf, query, results);
   double tmp1 = acmgt1__ext1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext1 :: GPU MEMORY BYTE READ BW */
static float
acmgt1__ext1__gpu_memory_byte_read_bw__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_READ $GpuTime FDIV */
   double tmp0 = acmgt1__ext1__gpu_memory_byte_read__read(perf, query, results);
   double tmp1 = acmgt1__ext1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext1 :: GPU MEMORY BYTE WRITE BW */
static float
acmgt1__ext1__gpu_memory_byte_write_bw__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE $GpuTime FDIV */
   double tmp0 = acmgt1__ext1__gpu_memory_byte_write__read(perf, query, results);
   double tmp1 = acmgt1__ext1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU Time Elapsed */
#define acmgt1__ext2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext2 :: GPU Core Clocks */
#define acmgt1__ext2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext2 :: AVG GPU Core Frequency */
#define acmgt1__ext2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext2 :: AVG GPU Core Frequency */
#define acmgt1__ext2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext2 :: GPU MEMORY REQUEST QUEUE FULL SQIDI0 */
#define acmgt1__ext2__gpu_memory_request_queue_full_sqidi0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext2 :: GPU MEMORY REQUEST QUEUE FULL SQIDI1 */
#define acmgt1__ext2__gpu_memory_request_queue_full_sqidi1__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext2 :: GPU MEMORY 32B TRANSACTION READ SQIDI0 */
static uint64_t
acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 C 1 READ UMUL C 0 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = 2 * tmp0;
   uint64_t tmp2 = results->accumulator[query->c_offset + 0];
   uint64_t tmp3 = tmp1 + tmp2;

   return tmp3;
}

/* Ext2 :: GPU MEMORY 64B TRANSACTION READ SQIDI0 */
static uint64_t
acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 B 3 READ UMUL B 2 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = 2 * tmp0;
   uint64_t tmp2 = results->accumulator[query->b_offset + 2];
   uint64_t tmp3 = tmp1 + tmp2;

   return tmp3;
}

/* Ext2 :: GPU MEMORY 32B TRANSACTION READ SQIDI1 */
static uint64_t
acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 B 5 READ UMUL B 4 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = 2 * tmp0;
   uint64_t tmp2 = results->accumulator[query->b_offset + 4];
   uint64_t tmp3 = tmp1 + tmp2;

   return tmp3;
}

/* Ext2 :: GPU MEMORY 64B TRANSACTION READ SQIDI1 */
static uint64_t
acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 B 7 READ UMUL B 6 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = 2 * tmp0;
   uint64_t tmp2 = results->accumulator[query->b_offset + 6];
   uint64_t tmp3 = tmp1 + tmp2;

   return tmp3;
}

/* Ext3 :: GPU Time Elapsed */
#define acmgt1__ext3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext3 :: GPU Core Clocks */
#define acmgt1__ext3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext3 :: AVG GPU Core Frequency */
#define acmgt1__ext3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext3 :: AVG GPU Core Frequency */
#define acmgt1__ext3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext3 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI0 */
#define acmgt1__ext3__gpu_memory_32_b_transaction_write_sqidi0__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext3 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI0 */
#define acmgt1__ext3__gpu_memory_64_b_transaction_write_sqidi0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI1 */
#define acmgt1__ext3__gpu_memory_32_b_transaction_write_sqidi1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext3 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI1 */
#define acmgt1__ext3__gpu_memory_64_b_transaction_write_sqidi1__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext3 :: HOST TO GPUMEM TRANSACTION READ */
#define acmgt1__ext3__host_to_gpumem_transaction_read__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext3 :: HOST TO GPUMEM TRANSACTION WRITE */
#define acmgt1__ext3__host_to_gpumem_transaction_write__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext4 :: GPU Time Elapsed */
#define acmgt1__ext4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext4 :: GPU Core Clocks */
#define acmgt1__ext4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext4 :: AVG GPU Core Frequency */
#define acmgt1__ext4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext4 :: AVG GPU Core Frequency */
#define acmgt1__ext4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext4 :: L3 READ L3BANK0 */
#define acmgt1__ext4__l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext4 :: L3 READ L3BANK1 */
#define acmgt1__ext4__l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext4 :: L3 READ L3BANK2 */
#define acmgt1__ext4__l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext4 :: L3 READ L3BANK3 */
#define acmgt1__ext4__l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext4 :: L3 READ L3BANK4 */
#define acmgt1__ext4__l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext4 :: L3 READ L3BANK5 */
#define acmgt1__ext4__l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext4 :: L3 READ L3BANK6 */
#define acmgt1__ext4__l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext4 :: L3 READ L3BANK7 */
#define acmgt1__ext4__l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext4 :: L3 WRITE L3BANK0 */
#define acmgt1__ext4__l3_write_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext4 :: L3 WRITE L3BANK1 */
#define acmgt1__ext4__l3_write_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext4 :: L3 WRITE L3BANK2 */
#define acmgt1__ext4__l3_write_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext4 :: L3 WRITE L3BANK3 */
#define acmgt1__ext4__l3_write_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext4 :: L3 WRITE L3BANK4 */
#define acmgt1__ext4__l3_write_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext4 :: L3 WRITE L3BANK5 */
#define acmgt1__ext4__l3_write_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext4 :: L3 WRITE L3BANK6 */
#define acmgt1__ext4__l3_write_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext4 :: L3 WRITE L3BANK7 */
#define acmgt1__ext4__l3_write_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext5 :: GPU Time Elapsed */
#define acmgt1__ext5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext5 :: GPU Core Clocks */
#define acmgt1__ext5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext5 :: AVG GPU Core Frequency */
#define acmgt1__ext5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext5 :: AVG GPU Core Frequency */
#define acmgt1__ext5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext5 :: DATAPORT L3 READ L3BANK0 */
#define acmgt1__ext5__dataport_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext5 :: DATAPORT L3 READ L3BANK1 */
#define acmgt1__ext5__dataport_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext5 :: DATAPORT L3 READ L3BANK2 */
#define acmgt1__ext5__dataport_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext5 :: DATAPORT L3 READ L3BANK3 */
#define acmgt1__ext5__dataport_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext5 :: DATAPORT L3 READ L3BANK4 */
#define acmgt1__ext5__dataport_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext5 :: DATAPORT L3 READ L3BANK5 */
#define acmgt1__ext5__dataport_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext5 :: DATAPORT L3 READ L3BANK6 */
#define acmgt1__ext5__dataport_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext5 :: DATAPORT L3 READ L3BANK7 */
#define acmgt1__ext5__dataport_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK0 */
#define acmgt1__ext5__dataport_l3_write_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK1 */
#define acmgt1__ext5__dataport_l3_write_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK2 */
#define acmgt1__ext5__dataport_l3_write_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK3 */
#define acmgt1__ext5__dataport_l3_write_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK4 */
#define acmgt1__ext5__dataport_l3_write_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK5 */
#define acmgt1__ext5__dataport_l3_write_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK6 */
#define acmgt1__ext5__dataport_l3_write_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK7 */
#define acmgt1__ext5__dataport_l3_write_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext6 :: GPU Time Elapsed */
#define acmgt1__ext6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext6 :: GPU Core Clocks */
#define acmgt1__ext6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext6 :: AVG GPU Core Frequency */
#define acmgt1__ext6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext6 :: AVG GPU Core Frequency */
#define acmgt1__ext6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext6 :: L3 HIT L3BANK0 */
#define acmgt1__ext6__l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext6 :: L3 HIT L3BANK1 */
#define acmgt1__ext6__l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext6 :: L3 HIT L3BANK2 */
#define acmgt1__ext6__l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext6 :: L3 HIT L3BANK3 */
#define acmgt1__ext6__l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext6 :: L3 HIT L3BANK4 */
#define acmgt1__ext6__l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext6 :: L3 HIT L3BANK5 */
#define acmgt1__ext6__l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext6 :: L3 HIT L3BANK6 */
#define acmgt1__ext6__l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext6 :: L3 HIT L3BANK7 */
#define acmgt1__ext6__l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext7 :: GPU Time Elapsed */
#define acmgt1__ext7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext7 :: GPU Core Clocks */
#define acmgt1__ext7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext7 :: AVG GPU Core Frequency */
#define acmgt1__ext7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext7 :: AVG GPU Core Frequency */
#define acmgt1__ext7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext7 :: SAMPLER L3 READ L3BANK0 */
#define acmgt1__ext7__sampler_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext7 :: SAMPLER L3 READ L3BANK1 */
#define acmgt1__ext7__sampler_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext7 :: SAMPLER L3 READ L3BANK2 */
#define acmgt1__ext7__sampler_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext7 :: SAMPLER L3 READ L3BANK3 */
#define acmgt1__ext7__sampler_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext7 :: SAMPLER L3 READ L3BANK4 */
#define acmgt1__ext7__sampler_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext7 :: SAMPLER L3 READ L3BANK5 */
#define acmgt1__ext7__sampler_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext7 :: SAMPLER L3 READ L3BANK6 */
#define acmgt1__ext7__sampler_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext7 :: SAMPLER L3 READ L3BANK7 */
#define acmgt1__ext7__sampler_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK0 */
#define acmgt1__ext7__sampler_l3_hit_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext7 :: SAMPLER L3 HIT L3BANK1 */
#define acmgt1__ext7__sampler_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK2 */
#define acmgt1__ext7__sampler_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK3 */
#define acmgt1__ext7__sampler_l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK4 */
#define acmgt1__ext7__sampler_l3_hit_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK5 */
#define acmgt1__ext7__sampler_l3_hit_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK6 */
#define acmgt1__ext7__sampler_l3_hit_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK7 */
#define acmgt1__ext7__sampler_l3_hit_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext8 :: GPU Time Elapsed */
#define acmgt1__ext8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext8 :: GPU Core Clocks */
#define acmgt1__ext8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext8 :: AVG GPU Core Frequency */
#define acmgt1__ext8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext8 :: AVG GPU Core Frequency */
#define acmgt1__ext8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext8 :: ICACHE L3 READ L3BANK0 */
#define acmgt1__ext8__icache_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext8 :: ICACHE L3 READ L3BANK1 */
#define acmgt1__ext8__icache_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext8 :: ICACHE L3 READ L3BANK2 */
#define acmgt1__ext8__icache_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext8 :: ICACHE L3 READ L3BANK3 */
#define acmgt1__ext8__icache_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext8 :: ICACHE L3 READ L3BANK4 */
#define acmgt1__ext8__icache_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext8 :: ICACHE L3 READ L3BANK5 */
#define acmgt1__ext8__icache_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext8 :: ICACHE L3 READ L3BANK6 */
#define acmgt1__ext8__icache_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext8 :: ICACHE L3 READ L3BANK7 */
#define acmgt1__ext8__icache_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext8 :: ICACHE L3 HIT L3BANK0 */
#define acmgt1__ext8__icache_l3_hit_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext8 :: ICACHE L3 HIT L3BANK1 */
#define acmgt1__ext8__icache_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext8 :: ICACHE L3 HIT L3BANK2 */
#define acmgt1__ext8__icache_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext8 :: ICACHE L3 HIT L3BANK3 */
#define acmgt1__ext8__icache_l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext8 :: ICACHE L3 HIT L3BANK4 */
#define acmgt1__ext8__icache_l3_hit_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext8 :: ICACHE L3 HIT L3BANK5 */
#define acmgt1__ext8__icache_l3_hit_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext8 :: ICACHE L3 HIT L3BANK6 */
#define acmgt1__ext8__icache_l3_hit_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext8 :: ICACHE L3 HIT L3BANK7 */
#define acmgt1__ext8__icache_l3_hit_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext9 :: GPU Time Elapsed */
#define acmgt1__ext9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext9 :: GPU Core Clocks */
#define acmgt1__ext9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext9 :: AVG GPU Core Frequency */
#define acmgt1__ext9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext9 :: AVG GPU Core Frequency */
#define acmgt1__ext9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext9 :: SAMPLER BUSY XECORE0 */
#define acmgt1__ext9__sampler_busy_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext9 :: SAMPLER BUSY XECORE1 */
#define acmgt1__ext9__sampler_busy_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext9 :: SAMPLER BUSY XECORE2 */
#define acmgt1__ext9__sampler_busy_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext9 :: SAMPLER BUSY XECORE3 */
#define acmgt1__ext9__sampler_busy_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext9 :: SAMPLER BUSY XECORE4 */
#define acmgt1__ext9__sampler_busy_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext9 :: SAMPLER BUSY XECORE5 */
#define acmgt1__ext9__sampler_busy_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext9 :: SAMPLER BUSY XECORE6 */
#define acmgt1__ext9__sampler_busy_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext9 :: SAMPLER BUSY XECORE7 */
#define acmgt1__ext9__sampler_busy_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext10 :: GPU Time Elapsed */
#define acmgt1__ext10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext10 :: GPU Core Clocks */
#define acmgt1__ext10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext10 :: AVG GPU Core Frequency */
#define acmgt1__ext10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext10 :: AVG GPU Core Frequency */
#define acmgt1__ext10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext10 :: DATAPORT L3 HIT L3BANK0 */
#define acmgt1__ext10__dataport_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext10 :: DATAPORT L3 HIT L3BANK1 */
#define acmgt1__ext10__dataport_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext10 :: DATAPORT L3 HIT L3BANK2 */
#define acmgt1__ext10__dataport_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext10 :: DATAPORT L3 HIT L3BANK3 */
#define acmgt1__ext10__dataport_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext10 :: DATAPORT L3 HIT L3BANK4 */
#define acmgt1__ext10__dataport_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext10 :: DATAPORT L3 HIT L3BANK5 */
#define acmgt1__ext10__dataport_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext10 :: DATAPORT L3 HIT L3BANK6 */
#define acmgt1__ext10__dataport_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext10 :: DATAPORT L3 HIT L3BANK7 */
#define acmgt1__ext10__dataport_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext10 :: COLOR L3 HIT L3BANK0 */
#define acmgt1__ext10__color_l3_hit_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext10 :: COLOR L3 HIT L3BANK1 */
#define acmgt1__ext10__color_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext10 :: COLOR L3 HIT L3BANK2 */
#define acmgt1__ext10__color_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext10 :: COLOR L3 HIT L3BANK3 */
#define acmgt1__ext10__color_l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext10 :: COLOR L3 HIT L3BANK4 */
#define acmgt1__ext10__color_l3_hit_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext10 :: COLOR L3 HIT L3BANK5 */
#define acmgt1__ext10__color_l3_hit_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext10 :: COLOR L3 HIT L3BANK6 */
#define acmgt1__ext10__color_l3_hit_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext10 :: COLOR L3 HIT L3BANK7 */
#define acmgt1__ext10__color_l3_hit_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext11 :: GPU Time Elapsed */
#define acmgt1__ext11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext11 :: GPU Core Clocks */
#define acmgt1__ext11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext11 :: AVG GPU Core Frequency */
#define acmgt1__ext11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext11 :: AVG GPU Core Frequency */
#define acmgt1__ext11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext11 :: Z L3 HIT L3BANK0 */
#define acmgt1__ext11__z_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext11 :: Z L3 HIT L3BANK1 */
#define acmgt1__ext11__z_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext11 :: Z L3 HIT L3BANK2 */
#define acmgt1__ext11__z_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext11 :: Z L3 HIT L3BANK3 */
#define acmgt1__ext11__z_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext11 :: Z L3 HIT L3BANK4 */
#define acmgt1__ext11__z_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext11 :: Z L3 HIT L3BANK5 */
#define acmgt1__ext11__z_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext11 :: Z L3 HIT L3BANK6 */
#define acmgt1__ext11__z_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext11 :: Z L3 HIT L3BANK7 */
#define acmgt1__ext11__z_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK0 */
#define acmgt1__ext11__l3_atomic_access_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK1 */
#define acmgt1__ext11__l3_atomic_access_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK2 */
#define acmgt1__ext11__l3_atomic_access_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK3 */
#define acmgt1__ext11__l3_atomic_access_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK4 */
#define acmgt1__ext11__l3_atomic_access_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK5 */
#define acmgt1__ext11__l3_atomic_access_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK6 */
#define acmgt1__ext11__l3_atomic_access_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK7 */
#define acmgt1__ext11__l3_atomic_access_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext12 :: GPU Time Elapsed */
#define acmgt1__ext12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext12 :: GPU Core Clocks */
#define acmgt1__ext12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext12 :: AVG GPU Core Frequency */
#define acmgt1__ext12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext12 :: AVG GPU Core Frequency */
#define acmgt1__ext12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext12 :: L3 BANK INPUT AVAILABLE L3BANK0 */
#define acmgt1__ext12__l3_input_available_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext12 :: L3 BANK INPUT AVAILABLE L3BANK1 */
#define acmgt1__ext12__l3_input_available_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext12 :: L3 BANK INPUT AVAILABLE L3BANK2 */
#define acmgt1__ext12__l3_input_available_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext12 :: L3 BANK INPUT AVAILABLE L3BANK3 */
#define acmgt1__ext12__l3_input_available_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext12 :: L3 BANK INPUT AVAILABLE L3BANK4 */
#define acmgt1__ext12__l3_input_available_l3_bank4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext12 :: L3 BANK INPUT AVAILABLE L3BANK5 */
#define acmgt1__ext12__l3_input_available_l3_bank5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext12 :: L3 BANK INPUT AVAILABLE L3BANK6 */
#define acmgt1__ext12__l3_input_available_l3_bank6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext12 :: L3 BANK INPUT AVAILABLE L3BANK7 */
#define acmgt1__ext12__l3_input_available_l3_bank7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK0 */
#define acmgt1__ext12__l3_output_ready_l3_bank0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK1 */
#define acmgt1__ext12__l3_output_ready_l3_bank1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK2 */
#define acmgt1__ext12__l3_output_ready_l3_bank2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK3 */
#define acmgt1__ext12__l3_output_ready_l3_bank3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK4 */
#define acmgt1__ext12__l3_output_ready_l3_bank4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK5 */
#define acmgt1__ext12__l3_output_ready_l3_bank5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK6 */
#define acmgt1__ext12__l3_output_ready_l3_bank6__read \
   bdw__render_basic__sampler1_busy__read

/* Ext12 :: L3 OUTPUT READY L3BANK7 */
#define acmgt1__ext12__l3_output_ready_l3_bank7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext13 :: GPU Time Elapsed */
#define acmgt1__ext13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext13 :: GPU Core Clocks */
#define acmgt1__ext13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext13 :: AVG GPU Core Frequency */
#define acmgt1__ext13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext13 :: AVG GPU Core Frequency */
#define acmgt1__ext13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext13 :: L3 SUPERQ FULL L3BANK0 */
#define acmgt1__ext13__l3_superq_full_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext13 :: L3 SUPERQ FULL L3BANK1 */
#define acmgt1__ext13__l3_superq_full_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext13 :: L3 SUPERQ FULL L3BANK2 */
#define acmgt1__ext13__l3_superq_full_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext13 :: L3 SUPERQ FULL L3BANK3 */
#define acmgt1__ext13__l3_superq_full_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext13 :: L3 SUPERQ FULL L3BANK4 */
#define acmgt1__ext13__l3_superq_full_l3_bank4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext13 :: L3 SUPERQ FULL L3BANK5 */
#define acmgt1__ext13__l3_superq_full_l3_bank5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext13 :: L3 SUPERQ FULL L3BANK6 */
#define acmgt1__ext13__l3_superq_full_l3_bank6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext13 :: L3 SUPERQ FULL L3BANK7 */
#define acmgt1__ext13__l3_superq_full_l3_bank7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext14 :: GPU Time Elapsed */
#define acmgt1__ext14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext14 :: GPU Core Clocks */
#define acmgt1__ext14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext14 :: AVG GPU Core Frequency */
#define acmgt1__ext14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext14 :: AVG GPU Core Frequency */
#define acmgt1__ext14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext14 :: L3 BANK ACTIVE L3BANK0 */
#define acmgt1__ext14__l3_busy_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK1 */
#define acmgt1__ext14__l3_busy_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK2 */
#define acmgt1__ext14__l3_busy_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK3 */
#define acmgt1__ext14__l3_busy_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK4 */
#define acmgt1__ext14__l3_busy_l3_bank4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK5 */
#define acmgt1__ext14__l3_busy_l3_bank5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK6 */
#define acmgt1__ext14__l3_busy_l3_bank6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK7 */
#define acmgt1__ext14__l3_busy_l3_bank7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext15 :: GPU Time Elapsed */
#define acmgt1__ext15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext15 :: GPU Core Clocks */
#define acmgt1__ext15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext15 :: AVG GPU Core Frequency */
#define acmgt1__ext15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext15 :: AVG GPU Core Frequency */
#define acmgt1__ext15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext15 :: L3 BANK STALL L3BANK0 */
#define acmgt1__ext15__l3_stall_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext15 :: L3 BANK STALL L3BANK1 */
#define acmgt1__ext15__l3_stall_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext15 :: L3 BANK STALL L3BANK2 */
#define acmgt1__ext15__l3_stall_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext15 :: L3 BANK STALL L3BANK3 */
#define acmgt1__ext15__l3_stall_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext16 :: GPU Time Elapsed */
#define acmgt1__ext16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext16 :: GPU Core Clocks */
#define acmgt1__ext16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext16 :: AVG GPU Core Frequency */
#define acmgt1__ext16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext16 :: AVG GPU Core Frequency */
#define acmgt1__ext16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext16 :: L3 BANK STALL L3BANK4 */
#define acmgt1__ext16__l3_stall_l3_bank4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext16 :: L3 BANK STALL L3BANK5 */
#define acmgt1__ext16__l3_stall_l3_bank5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext16 :: L3 BANK STALL L3BANK6 */
#define acmgt1__ext16__l3_stall_l3_bank6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext16 :: L3 BANK STALL L3BANK7 */
#define acmgt1__ext16__l3_stall_l3_bank7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext17 :: GPU Time Elapsed */
#define acmgt1__ext17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext17 :: GPU Core Clocks */
#define acmgt1__ext17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext17 :: AVG GPU Core Frequency */
#define acmgt1__ext17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext17 :: AVG GPU Core Frequency */
#define acmgt1__ext17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE0 */
#define acmgt1__ext17__load_store_cache_input_available_xecore0__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE1 */
#define acmgt1__ext17__load_store_cache_input_available_xecore1__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE2 */
#define acmgt1__ext17__load_store_cache_input_available_xecore2__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE3 */
#define acmgt1__ext17__load_store_cache_input_available_xecore3__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext18 :: GPU Time Elapsed */
#define acmgt1__ext18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext18 :: GPU Core Clocks */
#define acmgt1__ext18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext18 :: AVG GPU Core Frequency */
#define acmgt1__ext18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext18 :: AVG GPU Core Frequency */
#define acmgt1__ext18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext18 :: LOAD STORE CACHE INPUT AVAILABLE XECORE4 */
#define acmgt1__ext18__load_store_cache_input_available_xecore4__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext18 :: LOAD STORE CACHE INPUT AVAILABLE XECORE5 */
#define acmgt1__ext18__load_store_cache_input_available_xecore5__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext18 :: LOAD STORE CACHE INPUT AVAILABLE XECORE6 */
#define acmgt1__ext18__load_store_cache_input_available_xecore6__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext18 :: LOAD STORE CACHE INPUT AVAILABLE XECORE7 */
#define acmgt1__ext18__load_store_cache_input_available_xecore7__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext19 :: GPU Time Elapsed */
#define acmgt1__ext19__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext19 :: GPU Core Clocks */
#define acmgt1__ext19__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext19 :: AVG GPU Core Frequency */
#define acmgt1__ext19__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext19 :: AVG GPU Core Frequency */
#define acmgt1__ext19__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext19 :: LOAD STORE CACHE OUTPUT READY XECORE0 */
#define acmgt1__ext19__load_store_cache_output_ready_xecore0__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext19 :: LOAD STORE CACHE OUTPUT READY XECORE1 */
#define acmgt1__ext19__load_store_cache_output_ready_xecore1__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext19 :: LOAD STORE CACHE OUTPUT READY XECORE2 */
#define acmgt1__ext19__load_store_cache_output_ready_xecore2__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext19 :: LOAD STORE CACHE OUTPUT READY XECORE3 */
#define acmgt1__ext19__load_store_cache_output_ready_xecore3__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext20 :: GPU Time Elapsed */
#define acmgt1__ext20__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext20 :: GPU Core Clocks */
#define acmgt1__ext20__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext20 :: AVG GPU Core Frequency */
#define acmgt1__ext20__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext20 :: AVG GPU Core Frequency */
#define acmgt1__ext20__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext20 :: LOAD STORE CACHE OUTPUT READY XECORE4 */
#define acmgt1__ext20__load_store_cache_output_ready_xecore4__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext20 :: LOAD STORE CACHE OUTPUT READY XECORE5 */
#define acmgt1__ext20__load_store_cache_output_ready_xecore5__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext20 :: LOAD STORE CACHE OUTPUT READY XECORE6 */
#define acmgt1__ext20__load_store_cache_output_ready_xecore6__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext20 :: LOAD STORE CACHE OUTPUT READY XECORE7 */
#define acmgt1__ext20__load_store_cache_output_ready_xecore7__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext21 :: GPU Time Elapsed */
#define acmgt1__ext21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext21 :: GPU Core Clocks */
#define acmgt1__ext21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext21 :: AVG GPU Core Frequency */
#define acmgt1__ext21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext21 :: AVG GPU Core Frequency */
#define acmgt1__ext21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE0 */
#define acmgt1__ext21__load_store_cache_access_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE1 */
static uint64_t
acmgt1__ext21__load_store_cache_access_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ C 2 READ UADD C 1 READ UADD C 0 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 1];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 0];
   uint64_t tmp6 = tmp4 + tmp5;

   return tmp6;
}

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE2 */
#define acmgt1__ext21__load_store_cache_access_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE3 */
#define acmgt1__ext21__load_store_cache_access_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext22 :: GPU Time Elapsed */
#define acmgt1__ext22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext22 :: GPU Core Clocks */
#define acmgt1__ext22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext22 :: AVG GPU Core Frequency */
#define acmgt1__ext22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext22 :: AVG GPU Core Frequency */
#define acmgt1__ext22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext22 :: LOAD STORE CACHE ACCESS XECORE4 */
#define acmgt1__ext22__load_store_cache_access_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext22 :: LOAD STORE CACHE ACCESS XECORE5 */
#define acmgt1__ext22__load_store_cache_access_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext22 :: LOAD STORE CACHE ACCESS XECORE6 */
#define acmgt1__ext22__load_store_cache_access_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext22 :: LOAD STORE CACHE ACCESS XECORE7 */
#define acmgt1__ext22__load_store_cache_access_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext23 :: GPU Time Elapsed */
#define acmgt1__ext23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext23 :: GPU Core Clocks */
#define acmgt1__ext23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext23 :: AVG GPU Core Frequency */
#define acmgt1__ext23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext23 :: AVG GPU Core Frequency */
#define acmgt1__ext23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext23 :: LOAD STORE CACHE HIT XECORE0 */
static uint64_t
acmgt1__ext23__load_store_cache_hit_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ UADD B 2 READ UADD B 3 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 2];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 3];
   uint64_t tmp6 = tmp4 + tmp5;

   return tmp6;
}

/* Ext23 :: LOAD STORE CACHE HIT XECORE1 */
static uint64_t
acmgt1__ext23__load_store_cache_hit_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ UADD B 6 READ UADD B 7 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 6];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 7];
   uint64_t tmp6 = tmp4 + tmp5;

   return tmp6;
}

/* Ext24 :: GPU Time Elapsed */
#define acmgt1__ext24__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext24 :: GPU Core Clocks */
#define acmgt1__ext24__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext24 :: AVG GPU Core Frequency */
#define acmgt1__ext24__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext24 :: AVG GPU Core Frequency */
#define acmgt1__ext24__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext24 :: LOAD STORE CACHE HIT XECORE2 */
#define acmgt1__ext24__load_store_cache_hit_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext24 :: LOAD STORE CACHE HIT XECORE3 */
#define acmgt1__ext24__load_store_cache_hit_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext25 :: GPU Time Elapsed */
#define acmgt1__ext25__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext25 :: GPU Core Clocks */
#define acmgt1__ext25__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext25 :: AVG GPU Core Frequency */
#define acmgt1__ext25__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext25 :: AVG GPU Core Frequency */
#define acmgt1__ext25__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext25 :: LOAD STORE CACHE HIT XECORE4 */
#define acmgt1__ext25__load_store_cache_hit_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext25 :: LOAD STORE CACHE HIT XECORE5 */
#define acmgt1__ext25__load_store_cache_hit_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext26 :: GPU Time Elapsed */
#define acmgt1__ext26__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext26 :: GPU Core Clocks */
#define acmgt1__ext26__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext26 :: AVG GPU Core Frequency */
#define acmgt1__ext26__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext26 :: AVG GPU Core Frequency */
#define acmgt1__ext26__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext26 :: LOAD STORE CACHE HIT XECORE6 */
#define acmgt1__ext26__load_store_cache_hit_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext26 :: LOAD STORE CACHE HIT XECORE7 */
#define acmgt1__ext26__load_store_cache_hit_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext27 :: GPU Time Elapsed */
#define acmgt1__ext27__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext27 :: GPU Core Clocks */
#define acmgt1__ext27__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext27 :: AVG GPU Core Frequency */
#define acmgt1__ext27__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext27 :: AVG GPU Core Frequency */
#define acmgt1__ext27__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext27 :: LOAD STORE CACHE L3 READ XECORE0 */
#define acmgt1__ext27__load_store_cache_l3_read_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext27 :: LOAD STORE CACHE L3 READ XECORE1 */
#define acmgt1__ext27__load_store_cache_l3_read_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext27 :: LOAD STORE CACHE L3 READ XECORE2 */
#define acmgt1__ext27__load_store_cache_l3_read_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext27 :: LOAD STORE CACHE L3 READ XECORE3 */
#define acmgt1__ext27__load_store_cache_l3_read_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext27 :: LOAD STORE CACHE L3 READ XECORE4 */
static uint64_t
acmgt1__ext27__load_store_cache_l3_read_xecore4__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 6 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext27 :: LOAD STORE CACHE L3 READ XECORE5 */
static uint64_t
acmgt1__ext27__load_store_cache_l3_read_xecore5__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ B 4 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext27 :: LOAD STORE CACHE L3 READ XECORE6 */
#define acmgt1__ext27__load_store_cache_l3_read_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext27 :: LOAD STORE CACHE L3 READ XECORE7 */
static uint64_t
acmgt1__ext27__load_store_cache_l3_read_xecore7__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ B 0 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 0];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext28 :: GPU Time Elapsed */
#define acmgt1__ext28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext28 :: GPU Core Clocks */
#define acmgt1__ext28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext28 :: AVG GPU Core Frequency */
#define acmgt1__ext28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext28 :: AVG GPU Core Frequency */
#define acmgt1__ext28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE0 */
#define acmgt1__ext28__load_store_cache_l3_write_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE1 */
#define acmgt1__ext28__load_store_cache_l3_write_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE2 */
#define acmgt1__ext28__load_store_cache_l3_write_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE3 */
#define acmgt1__ext28__load_store_cache_l3_write_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE4 */
#define acmgt1__ext28__load_store_cache_l3_write_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE5 */
#define acmgt1__ext28__load_store_cache_l3_write_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE6 */
#define acmgt1__ext28__load_store_cache_l3_write_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE7 */
#define acmgt1__ext28__load_store_cache_l3_write_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext29 :: GPU Time Elapsed */
#define acmgt1__ext29__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext29 :: GPU Core Clocks */
#define acmgt1__ext29__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext29 :: AVG GPU Core Frequency */
#define acmgt1__ext29__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext29 :: AVG GPU Core Frequency */
#define acmgt1__ext29__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext29 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0 */
#define acmgt1__ext29__load_store_cache_partial_write_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext29 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1 */
#define acmgt1__ext29__load_store_cache_partial_write_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext29 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2 */
#define acmgt1__ext29__load_store_cache_partial_write_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext29 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3 */
#define acmgt1__ext29__load_store_cache_partial_write_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext30 :: GPU Time Elapsed */
#define acmgt1__ext30__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext30 :: GPU Core Clocks */
#define acmgt1__ext30__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext30 :: AVG GPU Core Frequency */
#define acmgt1__ext30__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext30 :: AVG GPU Core Frequency */
#define acmgt1__ext30__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext30 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4 */
#define acmgt1__ext30__load_store_cache_partial_write_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext30 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5 */
#define acmgt1__ext30__load_store_cache_partial_write_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext30 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6 */
#define acmgt1__ext30__load_store_cache_partial_write_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext30 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7 */
#define acmgt1__ext30__load_store_cache_partial_write_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext31 :: GPU Time Elapsed */
#define acmgt1__ext31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext31 :: GPU Core Clocks */
#define acmgt1__ext31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext31 :: AVG GPU Core Frequency */
#define acmgt1__ext31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext31 :: AVG GPU Core Frequency */
#define acmgt1__ext31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define acmgt1__ext31__xve_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define acmgt1__ext31__xve_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext32 :: GPU Time Elapsed */
#define acmgt1__ext32__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext32 :: GPU Core Clocks */
#define acmgt1__ext32__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext32 :: AVG GPU Core Frequency */
#define acmgt1__ext32__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext32 :: AVG GPU Core Frequency */
#define acmgt1__ext32__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext32 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define acmgt1__ext32__xve_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext32 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define acmgt1__ext32__xve_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext33 :: GPU Time Elapsed */
#define acmgt1__ext33__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext33 :: GPU Core Clocks */
#define acmgt1__ext33__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext33 :: AVG GPU Core Frequency */
#define acmgt1__ext33__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext33 :: AVG GPU Core Frequency */
#define acmgt1__ext33__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext33 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4 */
#define acmgt1__ext33__xve_load_store_cache_read_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext33 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5 */
#define acmgt1__ext33__xve_load_store_cache_read_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext34 :: GPU Time Elapsed */
#define acmgt1__ext34__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext34 :: GPU Core Clocks */
#define acmgt1__ext34__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext34 :: AVG GPU Core Frequency */
#define acmgt1__ext34__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext34 :: AVG GPU Core Frequency */
#define acmgt1__ext34__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext34 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6 */
#define acmgt1__ext34__xve_load_store_cache_read_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext34 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7 */
#define acmgt1__ext34__xve_load_store_cache_read_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext35 :: GPU Time Elapsed */
#define acmgt1__ext35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext35 :: GPU Core Clocks */
#define acmgt1__ext35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext35 :: AVG GPU Core Frequency */
#define acmgt1__ext35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext35 :: AVG GPU Core Frequency */
#define acmgt1__ext35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0 */
#define acmgt1__ext35__xve_load_store_cache_write_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1 */
#define acmgt1__ext35__xve_load_store_cache_write_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext36 :: GPU Time Elapsed */
#define acmgt1__ext36__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext36 :: GPU Core Clocks */
#define acmgt1__ext36__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext36 :: AVG GPU Core Frequency */
#define acmgt1__ext36__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext36 :: AVG GPU Core Frequency */
#define acmgt1__ext36__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext36 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2 */
#define acmgt1__ext36__xve_load_store_cache_write_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext36 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3 */
#define acmgt1__ext36__xve_load_store_cache_write_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext37 :: GPU Time Elapsed */
#define acmgt1__ext37__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext37 :: GPU Core Clocks */
#define acmgt1__ext37__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext37 :: AVG GPU Core Frequency */
#define acmgt1__ext37__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext37 :: AVG GPU Core Frequency */
#define acmgt1__ext37__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext37 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4 */
#define acmgt1__ext37__xve_load_store_cache_write_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext37 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5 */
#define acmgt1__ext37__xve_load_store_cache_write_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext38 :: GPU Time Elapsed */
#define acmgt1__ext38__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext38 :: GPU Core Clocks */
#define acmgt1__ext38__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext38 :: AVG GPU Core Frequency */
#define acmgt1__ext38__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext38 :: AVG GPU Core Frequency */
#define acmgt1__ext38__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext38 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6 */
#define acmgt1__ext38__xve_load_store_cache_write_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext38 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7 */
#define acmgt1__ext38__xve_load_store_cache_write_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext39 :: GPU Time Elapsed */
#define acmgt1__ext39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext39 :: GPU Core Clocks */
#define acmgt1__ext39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext39 :: AVG GPU Core Frequency */
#define acmgt1__ext39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext39 :: AVG GPU Core Frequency */
#define acmgt1__ext39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0 */
#define acmgt1__ext39__xve_load_store_cache_fence_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1 */
#define acmgt1__ext39__xve_load_store_cache_fence_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext40 :: GPU Time Elapsed */
#define acmgt1__ext40__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext40 :: GPU Core Clocks */
#define acmgt1__ext40__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext40 :: AVG GPU Core Frequency */
#define acmgt1__ext40__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext40 :: AVG GPU Core Frequency */
#define acmgt1__ext40__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext40 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2 */
#define acmgt1__ext40__xve_load_store_cache_fence_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext40 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3 */
#define acmgt1__ext40__xve_load_store_cache_fence_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext41 :: GPU Time Elapsed */
#define acmgt1__ext41__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext41 :: GPU Core Clocks */
#define acmgt1__ext41__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext41 :: AVG GPU Core Frequency */
#define acmgt1__ext41__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext41 :: AVG GPU Core Frequency */
#define acmgt1__ext41__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext41 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4 */
#define acmgt1__ext41__xve_load_store_cache_fence_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext41 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5 */
#define acmgt1__ext41__xve_load_store_cache_fence_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext42 :: GPU Time Elapsed */
#define acmgt1__ext42__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext42 :: GPU Core Clocks */
#define acmgt1__ext42__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext42 :: AVG GPU Core Frequency */
#define acmgt1__ext42__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext42 :: AVG GPU Core Frequency */
#define acmgt1__ext42__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext42 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6 */
#define acmgt1__ext42__xve_load_store_cache_fence_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext42 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7 */
#define acmgt1__ext42__xve_load_store_cache_fence_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext43 :: GPU Time Elapsed */
#define acmgt1__ext43__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext43 :: GPU Core Clocks */
#define acmgt1__ext43__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext43 :: AVG GPU Core Frequency */
#define acmgt1__ext43__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext43 :: AVG GPU Core Frequency */
#define acmgt1__ext43__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext43 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0 */
#define acmgt1__ext43__xve_load_store_cache_atomic_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext43 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0 */
#define acmgt1__ext43__xve_load_store_cache_register_request_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext44 :: GPU Time Elapsed */
#define acmgt1__ext44__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext44 :: GPU Core Clocks */
#define acmgt1__ext44__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext44 :: AVG GPU Core Frequency */
#define acmgt1__ext44__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext44 :: AVG GPU Core Frequency */
#define acmgt1__ext44__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext44 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1 */
#define acmgt1__ext44__xve_load_store_cache_atomic_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext44 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1 */
#define acmgt1__ext44__xve_load_store_cache_register_request_count_xecore1__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext45 :: GPU Time Elapsed */
#define acmgt1__ext45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext45 :: GPU Core Clocks */
#define acmgt1__ext45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext45 :: AVG GPU Core Frequency */
#define acmgt1__ext45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext45 :: AVG GPU Core Frequency */
#define acmgt1__ext45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext45 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2 */
#define acmgt1__ext45__xve_load_store_cache_atomic_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext45 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2 */
#define acmgt1__ext45__xve_load_store_cache_register_request_count_xecore2__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext46 :: GPU Time Elapsed */
#define acmgt1__ext46__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext46 :: GPU Core Clocks */
#define acmgt1__ext46__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext46 :: AVG GPU Core Frequency */
#define acmgt1__ext46__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext46 :: AVG GPU Core Frequency */
#define acmgt1__ext46__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext46 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3 */
#define acmgt1__ext46__xve_load_store_cache_atomic_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext46 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3 */
#define acmgt1__ext46__xve_load_store_cache_register_request_count_xecore3__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext47 :: GPU Time Elapsed */
#define acmgt1__ext47__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext47 :: GPU Core Clocks */
#define acmgt1__ext47__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext47 :: AVG GPU Core Frequency */
#define acmgt1__ext47__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext47 :: AVG GPU Core Frequency */
#define acmgt1__ext47__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext47 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4 */
#define acmgt1__ext47__xve_load_store_cache_atomic_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext47 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4 */
#define acmgt1__ext47__xve_load_store_cache_register_request_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext48 :: GPU Time Elapsed */
#define acmgt1__ext48__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext48 :: GPU Core Clocks */
#define acmgt1__ext48__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext48 :: AVG GPU Core Frequency */
#define acmgt1__ext48__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext48 :: AVG GPU Core Frequency */
#define acmgt1__ext48__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext48 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5 */
#define acmgt1__ext48__xve_load_store_cache_atomic_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext48 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5 */
#define acmgt1__ext48__xve_load_store_cache_register_request_count_xecore5__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext49 :: GPU Time Elapsed */
#define acmgt1__ext49__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext49 :: GPU Core Clocks */
#define acmgt1__ext49__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext49 :: AVG GPU Core Frequency */
#define acmgt1__ext49__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext49 :: AVG GPU Core Frequency */
#define acmgt1__ext49__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext49 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6 */
#define acmgt1__ext49__xve_load_store_cache_atomic_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext49 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6 */
#define acmgt1__ext49__xve_load_store_cache_register_request_count_xecore6__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext50 :: GPU Time Elapsed */
#define acmgt1__ext50__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext50 :: GPU Core Clocks */
#define acmgt1__ext50__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext50 :: AVG GPU Core Frequency */
#define acmgt1__ext50__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext50 :: AVG GPU Core Frequency */
#define acmgt1__ext50__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext50 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7 */
#define acmgt1__ext50__xve_load_store_cache_atomic_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext50 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7 */
#define acmgt1__ext50__xve_load_store_cache_register_request_count_xecore7__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext51 :: GPU Time Elapsed */
#define acmgt1__ext51__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext51 :: GPU Core Clocks */
#define acmgt1__ext51__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext51 :: AVG GPU Core Frequency */
#define acmgt1__ext51__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext51 :: AVG GPU Core Frequency */
#define acmgt1__ext51__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0 */
#define acmgt1__ext51__xve_load_store_cache_register_response_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1 */
#define acmgt1__ext51__xve_load_store_cache_register_response_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2 */
#define acmgt1__ext51__xve_load_store_cache_register_response_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3 */
#define acmgt1__ext51__xve_load_store_cache_register_response_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext52 :: GPU Time Elapsed */
#define acmgt1__ext52__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext52 :: GPU Core Clocks */
#define acmgt1__ext52__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext52 :: AVG GPU Core Frequency */
#define acmgt1__ext52__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext52 :: AVG GPU Core Frequency */
#define acmgt1__ext52__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext52 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4 */
#define acmgt1__ext52__xve_load_store_cache_register_response_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext52 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5 */
#define acmgt1__ext52__xve_load_store_cache_register_response_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext52 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6 */
#define acmgt1__ext52__xve_load_store_cache_register_response_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext52 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7 */
#define acmgt1__ext52__xve_load_store_cache_register_response_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext53 :: GPU Time Elapsed */
#define acmgt1__ext53__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext53 :: GPU Core Clocks */
#define acmgt1__ext53__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext53 :: AVG GPU Core Frequency */
#define acmgt1__ext53__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext53 :: AVG GPU Core Frequency */
#define acmgt1__ext53__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE0 */
#define acmgt1__ext53__xve_slm_read_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE1 */
#define acmgt1__ext53__xve_slm_read_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext54 :: GPU Time Elapsed */
#define acmgt1__ext54__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext54 :: GPU Core Clocks */
#define acmgt1__ext54__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext54 :: AVG GPU Core Frequency */
#define acmgt1__ext54__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext54 :: AVG GPU Core Frequency */
#define acmgt1__ext54__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext54 :: XVE SLM READ MESSAGE COUNT XECORE2 */
#define acmgt1__ext54__xve_slm_read_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext54 :: XVE SLM READ MESSAGE COUNT XECORE3 */
#define acmgt1__ext54__xve_slm_read_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext55 :: GPU Time Elapsed */
#define acmgt1__ext55__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext55 :: GPU Core Clocks */
#define acmgt1__ext55__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext55 :: AVG GPU Core Frequency */
#define acmgt1__ext55__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext55 :: AVG GPU Core Frequency */
#define acmgt1__ext55__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext55 :: XVE SLM READ MESSAGE COUNT XECORE4 */
#define acmgt1__ext55__xve_slm_read_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext55 :: XVE SLM READ MESSAGE COUNT XECORE5 */
#define acmgt1__ext55__xve_slm_read_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext56 :: GPU Time Elapsed */
#define acmgt1__ext56__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext56 :: GPU Core Clocks */
#define acmgt1__ext56__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext56 :: AVG GPU Core Frequency */
#define acmgt1__ext56__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext56 :: AVG GPU Core Frequency */
#define acmgt1__ext56__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext56 :: XVE SLM READ MESSAGE COUNT XECORE6 */
#define acmgt1__ext56__xve_slm_read_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext56 :: XVE SLM READ MESSAGE COUNT XECORE7 */
#define acmgt1__ext56__xve_slm_read_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext57 :: GPU Time Elapsed */
#define acmgt1__ext57__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext57 :: GPU Core Clocks */
#define acmgt1__ext57__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext57 :: AVG GPU Core Frequency */
#define acmgt1__ext57__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext57 :: AVG GPU Core Frequency */
#define acmgt1__ext57__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE0 */
#define acmgt1__ext57__xve_slm_write_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE1 */
#define acmgt1__ext57__xve_slm_write_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext58 :: GPU Time Elapsed */
#define acmgt1__ext58__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext58 :: GPU Core Clocks */
#define acmgt1__ext58__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext58 :: AVG GPU Core Frequency */
#define acmgt1__ext58__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext58 :: AVG GPU Core Frequency */
#define acmgt1__ext58__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext58 :: XVE SLM WRITE MESSAGE COUNT XECORE2 */
#define acmgt1__ext58__xve_slm_write_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext58 :: XVE SLM WRITE MESSAGE COUNT XECORE3 */
#define acmgt1__ext58__xve_slm_write_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext59 :: GPU Time Elapsed */
#define acmgt1__ext59__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext59 :: GPU Core Clocks */
#define acmgt1__ext59__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext59 :: AVG GPU Core Frequency */
#define acmgt1__ext59__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext59 :: AVG GPU Core Frequency */
#define acmgt1__ext59__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext59 :: XVE SLM WRITE MESSAGE COUNT XECORE4 */
#define acmgt1__ext59__xve_slm_write_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext59 :: XVE SLM WRITE MESSAGE COUNT XECORE5 */
#define acmgt1__ext59__xve_slm_write_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext60 :: GPU Time Elapsed */
#define acmgt1__ext60__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext60 :: GPU Core Clocks */
#define acmgt1__ext60__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext60 :: AVG GPU Core Frequency */
#define acmgt1__ext60__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext60 :: AVG GPU Core Frequency */
#define acmgt1__ext60__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext60 :: XVE SLM WRITE MESSAGE COUNT XECORE6 */
#define acmgt1__ext60__xve_slm_write_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext60 :: XVE SLM WRITE MESSAGE COUNT XECORE7 */
#define acmgt1__ext60__xve_slm_write_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext61 :: GPU Time Elapsed */
#define acmgt1__ext61__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext61 :: GPU Core Clocks */
#define acmgt1__ext61__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext61 :: AVG GPU Core Frequency */
#define acmgt1__ext61__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext61 :: AVG GPU Core Frequency */
#define acmgt1__ext61__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE0 */
#define acmgt1__ext61__xve_slm_fence_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE1 */
#define acmgt1__ext61__xve_slm_fence_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext62 :: GPU Time Elapsed */
#define acmgt1__ext62__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext62 :: GPU Core Clocks */
#define acmgt1__ext62__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext62 :: AVG GPU Core Frequency */
#define acmgt1__ext62__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext62 :: AVG GPU Core Frequency */
#define acmgt1__ext62__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext62 :: XVE SLM FENCE MESSAGE COUNT XECORE2 */
#define acmgt1__ext62__xve_slm_fence_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext62 :: XVE SLM FENCE MESSAGE COUNT XECORE3 */
#define acmgt1__ext62__xve_slm_fence_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext63 :: GPU Time Elapsed */
#define acmgt1__ext63__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext63 :: GPU Core Clocks */
#define acmgt1__ext63__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext63 :: AVG GPU Core Frequency */
#define acmgt1__ext63__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext63 :: AVG GPU Core Frequency */
#define acmgt1__ext63__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext63 :: XVE SLM FENCE MESSAGE COUNT XECORE4 */
#define acmgt1__ext63__xve_slm_fence_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext63 :: XVE SLM FENCE MESSAGE COUNT XECORE5 */
#define acmgt1__ext63__xve_slm_fence_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext64 :: GPU Time Elapsed */
#define acmgt1__ext64__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext64 :: GPU Core Clocks */
#define acmgt1__ext64__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext64 :: AVG GPU Core Frequency */
#define acmgt1__ext64__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext64 :: AVG GPU Core Frequency */
#define acmgt1__ext64__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext64 :: XVE SLM FENCE MESSAGE COUNT XECORE6 */
#define acmgt1__ext64__xve_slm_fence_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext64 :: XVE SLM FENCE MESSAGE COUNT XECORE7 */
#define acmgt1__ext64__xve_slm_fence_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext65 :: GPU Time Elapsed */
#define acmgt1__ext65__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext65 :: GPU Core Clocks */
#define acmgt1__ext65__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext65 :: AVG GPU Core Frequency */
#define acmgt1__ext65__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext65 :: AVG GPU Core Frequency */
#define acmgt1__ext65__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext65 :: XVE SLM ATOMIC MESSAGE COUNT XECORE0 */
#define acmgt1__ext65__xve_slm_atomic_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext66 :: GPU Time Elapsed */
#define acmgt1__ext66__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext66 :: GPU Core Clocks */
#define acmgt1__ext66__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext66 :: AVG GPU Core Frequency */
#define acmgt1__ext66__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext66 :: AVG GPU Core Frequency */
#define acmgt1__ext66__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext66 :: XVE SLM ATOMIC MESSAGE COUNT XECORE1 */
#define acmgt1__ext66__xve_slm_atomic_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext67 :: GPU Time Elapsed */
#define acmgt1__ext67__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext67 :: GPU Core Clocks */
#define acmgt1__ext67__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext67 :: AVG GPU Core Frequency */
#define acmgt1__ext67__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext67 :: AVG GPU Core Frequency */
#define acmgt1__ext67__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext67 :: XVE SLM ATOMIC MESSAGE COUNT XECORE2 */
#define acmgt1__ext67__xve_slm_atomic_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext68 :: GPU Time Elapsed */
#define acmgt1__ext68__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext68 :: GPU Core Clocks */
#define acmgt1__ext68__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext68 :: AVG GPU Core Frequency */
#define acmgt1__ext68__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext68 :: AVG GPU Core Frequency */
#define acmgt1__ext68__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext68 :: XVE SLM ATOMIC MESSAGE COUNT XECORE3 */
#define acmgt1__ext68__xve_slm_atomic_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext69 :: GPU Time Elapsed */
#define acmgt1__ext69__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext69 :: GPU Core Clocks */
#define acmgt1__ext69__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext69 :: AVG GPU Core Frequency */
#define acmgt1__ext69__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext69 :: AVG GPU Core Frequency */
#define acmgt1__ext69__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext69 :: XVE SLM ATOMIC MESSAGE COUNT XECORE4 */
#define acmgt1__ext69__xve_slm_atomic_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext70 :: GPU Time Elapsed */
#define acmgt1__ext70__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext70 :: GPU Core Clocks */
#define acmgt1__ext70__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext70 :: AVG GPU Core Frequency */
#define acmgt1__ext70__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext70 :: AVG GPU Core Frequency */
#define acmgt1__ext70__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext70 :: XVE SLM ATOMIC MESSAGE COUNT XECORE5 */
#define acmgt1__ext70__xve_slm_atomic_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext71 :: GPU Time Elapsed */
#define acmgt1__ext71__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext71 :: GPU Core Clocks */
#define acmgt1__ext71__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext71 :: AVG GPU Core Frequency */
#define acmgt1__ext71__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext71 :: AVG GPU Core Frequency */
#define acmgt1__ext71__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext71 :: XVE SLM ATOMIC MESSAGE COUNT XECORE6 */
#define acmgt1__ext71__xve_slm_atomic_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext72 :: GPU Time Elapsed */
#define acmgt1__ext72__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext72 :: GPU Core Clocks */
#define acmgt1__ext72__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext72 :: AVG GPU Core Frequency */
#define acmgt1__ext72__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext72 :: AVG GPU Core Frequency */
#define acmgt1__ext72__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext72 :: XVE SLM ATOMIC MESSAGE COUNT XECORE7 */
#define acmgt1__ext72__xve_slm_atomic_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext73 :: GPU Time Elapsed */
#define acmgt1__ext73__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext73 :: GPU Core Clocks */
#define acmgt1__ext73__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext73 :: AVG GPU Core Frequency */
#define acmgt1__ext73__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext73 :: AVG GPU Core Frequency */
#define acmgt1__ext73__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext73 :: DATAPORT INPUT AVAILABLE XECORE0 */
#define acmgt1__ext73__dataport_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext73 :: DATAPORT INPUT AVAILABLE XECORE1 */
#define acmgt1__ext73__dataport_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext74 :: GPU Time Elapsed */
#define acmgt1__ext74__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext74 :: GPU Core Clocks */
#define acmgt1__ext74__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext74 :: AVG GPU Core Frequency */
#define acmgt1__ext74__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext74 :: AVG GPU Core Frequency */
#define acmgt1__ext74__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext74 :: DATAPORT INPUT AVAILABLE XECORE2 */
#define acmgt1__ext74__dataport_input_available_xecore2__read \
   bdw__render_basic__sampler0_busy__read

/* Ext74 :: DATAPORT INPUT AVAILABLE XECORE3 */
#define acmgt1__ext74__dataport_input_available_xecore3__read \
   bdw__render_basic__sampler1_busy__read

/* Ext75 :: GPU Time Elapsed */
#define acmgt1__ext75__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext75 :: GPU Core Clocks */
#define acmgt1__ext75__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext75 :: AVG GPU Core Frequency */
#define acmgt1__ext75__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext75 :: AVG GPU Core Frequency */
#define acmgt1__ext75__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext75 :: DATAPORT INPUT AVAILABLE XECORE4 */
#define acmgt1__ext75__dataport_input_available_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext75 :: DATAPORT INPUT AVAILABLE XECORE5 */
#define acmgt1__ext75__dataport_input_available_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext76 :: GPU Time Elapsed */
#define acmgt1__ext76__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext76 :: GPU Core Clocks */
#define acmgt1__ext76__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext76 :: AVG GPU Core Frequency */
#define acmgt1__ext76__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext76 :: AVG GPU Core Frequency */
#define acmgt1__ext76__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext76 :: DATAPORT INPUT AVAILABLE XECORE6 */
#define acmgt1__ext76__dataport_input_available_xecore6__read \
   bdw__render_basic__sampler0_busy__read

/* Ext76 :: DATAPORT INPUT AVAILABLE XECORE7 */
#define acmgt1__ext76__dataport_input_available_xecore7__read \
   bdw__render_basic__sampler1_busy__read

/* Ext77 :: GPU Time Elapsed */
#define acmgt1__ext77__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext77 :: GPU Core Clocks */
#define acmgt1__ext77__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext77 :: AVG GPU Core Frequency */
#define acmgt1__ext77__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext77 :: AVG GPU Core Frequency */
#define acmgt1__ext77__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext77 :: DATAPORT OUTPUT READY XECORE0 */
#define acmgt1__ext77__dataport_output_ready_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext77 :: DATAPORT OUTPUT READY XECORE1 */
#define acmgt1__ext77__dataport_output_ready_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext77 :: DATAPORT OUTPUT READY XECORE2 */
#define acmgt1__ext77__dataport_output_ready_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext77 :: DATAPORT OUTPUT READY XECORE3 */
#define acmgt1__ext77__dataport_output_ready_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext78 :: GPU Time Elapsed */
#define acmgt1__ext78__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext78 :: GPU Core Clocks */
#define acmgt1__ext78__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext78 :: AVG GPU Core Frequency */
#define acmgt1__ext78__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext78 :: AVG GPU Core Frequency */
#define acmgt1__ext78__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext78 :: DATAPORT OUTPUT READY XECORE4 */
#define acmgt1__ext78__dataport_output_ready_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext78 :: DATAPORT OUTPUT READY XECORE5 */
#define acmgt1__ext78__dataport_output_ready_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext78 :: DATAPORT OUTPUT READY XECORE6 */
#define acmgt1__ext78__dataport_output_ready_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext78 :: DATAPORT OUTPUT READY XECORE7 */
#define acmgt1__ext78__dataport_output_ready_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext79 :: GPU Time Elapsed */
#define acmgt1__ext79__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext79 :: GPU Core Clocks */
#define acmgt1__ext79__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext79 :: AVG GPU Core Frequency */
#define acmgt1__ext79__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext79 :: AVG GPU Core Frequency */
#define acmgt1__ext79__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext79 :: DATAPORT BYTE READ XECORE0 */
static uint64_t
acmgt1__ext79__dataport_byte_read_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ UADD B 2 READ UADD B 3 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 2];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 3];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = tmp6 * 64;

   return tmp7;
}

/* Ext79 :: DATAPORT BYTE READ XECORE1 */
static uint64_t
acmgt1__ext79__dataport_byte_read_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ UADD B 6 READ UADD B 7 READ UADD 64 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 6];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 7];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = tmp6 * 64;

   return tmp7;
}

/* Ext80 :: GPU Time Elapsed */
#define acmgt1__ext80__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext80 :: GPU Core Clocks */
#define acmgt1__ext80__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext80 :: AVG GPU Core Frequency */
#define acmgt1__ext80__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext80 :: AVG GPU Core Frequency */
#define acmgt1__ext80__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext80 :: DATAPORT BYTE READ XECORE2 */
#define acmgt1__ext80__dataport_byte_read_xecore2__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext80 :: DATAPORT BYTE READ XECORE3 */
#define acmgt1__ext80__dataport_byte_read_xecore3__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext81 :: GPU Time Elapsed */
#define acmgt1__ext81__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext81 :: GPU Core Clocks */
#define acmgt1__ext81__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext81 :: AVG GPU Core Frequency */
#define acmgt1__ext81__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext81 :: AVG GPU Core Frequency */
#define acmgt1__ext81__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext81 :: DATAPORT BYTE READ XECORE4 */
#define acmgt1__ext81__dataport_byte_read_xecore4__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext81 :: DATAPORT BYTE READ XECORE5 */
#define acmgt1__ext81__dataport_byte_read_xecore5__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext82 :: GPU Time Elapsed */
#define acmgt1__ext82__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext82 :: GPU Core Clocks */
#define acmgt1__ext82__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext82 :: AVG GPU Core Frequency */
#define acmgt1__ext82__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext82 :: AVG GPU Core Frequency */
#define acmgt1__ext82__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext82 :: DATAPORT BYTE READ XECORE6 */
#define acmgt1__ext82__dataport_byte_read_xecore6__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext82 :: DATAPORT BYTE READ XECORE7 */
#define acmgt1__ext82__dataport_byte_read_xecore7__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext83 :: GPU Time Elapsed */
#define acmgt1__ext83__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext83 :: GPU Core Clocks */
#define acmgt1__ext83__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext83 :: AVG GPU Core Frequency */
#define acmgt1__ext83__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext83 :: AVG GPU Core Frequency */
#define acmgt1__ext83__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext83 :: DATAPORT BYTE WRITE XECORE0 */
static uint64_t
acmgt1__ext83__dataport_byte_write_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  C 7 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Ext83 :: DATAPORT BYTE WRITE XECORE1 */
static uint64_t
acmgt1__ext83__dataport_byte_write_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  C 6 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Ext83 :: DATAPORT BYTE WRITE XECORE2 */
static uint64_t
acmgt1__ext83__dataport_byte_write_xecore2__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  C 5 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Ext83 :: DATAPORT BYTE WRITE XECORE3 */
static uint64_t
acmgt1__ext83__dataport_byte_write_xecore3__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  C 4 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Ext83 :: DATAPORT BYTE WRITE XECORE4 */
static uint64_t
acmgt1__ext83__dataport_byte_write_xecore4__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  C 3 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Ext83 :: DATAPORT BYTE WRITE XECORE5 */
static uint64_t
acmgt1__ext83__dataport_byte_write_xecore5__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  C 2 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 2];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Ext83 :: DATAPORT BYTE WRITE XECORE6 */
static uint64_t
acmgt1__ext83__dataport_byte_write_xecore6__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  C 1 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Ext83 :: DATAPORT BYTE WRITE XECORE7 */
static uint64_t
acmgt1__ext83__dataport_byte_write_xecore7__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  C 0 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE0 */
#define acmgt1__ext83__dataport_texture_cache_access_xecore0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE1 */
#define acmgt1__ext83__dataport_texture_cache_access_xecore1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE2 */
#define acmgt1__ext83__dataport_texture_cache_access_xecore2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE3 */
#define acmgt1__ext83__dataport_texture_cache_access_xecore3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE4 */
#define acmgt1__ext83__dataport_texture_cache_access_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE5 */
#define acmgt1__ext83__dataport_texture_cache_access_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE6 */
#define acmgt1__ext83__dataport_texture_cache_access_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE7 */
#define acmgt1__ext83__dataport_texture_cache_access_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext84 :: GPU Time Elapsed */
#define acmgt1__ext84__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext84 :: GPU Core Clocks */
#define acmgt1__ext84__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext84 :: AVG GPU Core Frequency */
#define acmgt1__ext84__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext84 :: AVG GPU Core Frequency */
#define acmgt1__ext84__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext84 :: DATAPORT TEXTURE CACHE HIT XECORE0 */
#define acmgt1__ext84__dataport_texture_cache_hit_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext84 :: DATAPORT TEXTURE CACHE HIT XECORE1 */
#define acmgt1__ext84__dataport_texture_cache_hit_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext84 :: DATAPORT TEXTURE CACHE HIT XECORE2 */
#define acmgt1__ext84__dataport_texture_cache_hit_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext84 :: DATAPORT TEXTURE CACHE HIT XECORE3 */
#define acmgt1__ext84__dataport_texture_cache_hit_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext84 :: DATAPORT TEXTURE CACHE HIT XECORE4 */
#define acmgt1__ext84__dataport_texture_cache_hit_xecore4__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext84 :: DATAPORT TEXTURE CACHE HIT XECORE5 */
#define acmgt1__ext84__dataport_texture_cache_hit_xecore5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext84 :: DATAPORT TEXTURE CACHE HIT XECORE6 */
#define acmgt1__ext84__dataport_texture_cache_hit_xecore6__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext84 :: DATAPORT TEXTURE CACHE HIT XECORE7 */
#define acmgt1__ext84__dataport_texture_cache_hit_xecore7__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext85 :: GPU Time Elapsed */
#define acmgt1__ext85__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext85 :: GPU Core Clocks */
#define acmgt1__ext85__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext85 :: AVG GPU Core Frequency */
#define acmgt1__ext85__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext85 :: AVG GPU Core Frequency */
#define acmgt1__ext85__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE0 */
#define acmgt1__ext85__xve_dataport_read_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE1 */
#define acmgt1__ext85__xve_dataport_read_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE2 */
#define acmgt1__ext85__xve_dataport_read_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE3 */
#define acmgt1__ext85__xve_dataport_read_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext86 :: GPU Time Elapsed */
#define acmgt1__ext86__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext86 :: GPU Core Clocks */
#define acmgt1__ext86__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext86 :: AVG GPU Core Frequency */
#define acmgt1__ext86__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext86 :: AVG GPU Core Frequency */
#define acmgt1__ext86__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext86 :: XVE DATAPORT READ MESSAGE COUNT XECORE4 */
#define acmgt1__ext86__xve_dataport_read_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext86 :: XVE DATAPORT READ MESSAGE COUNT XECORE5 */
#define acmgt1__ext86__xve_dataport_read_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext86 :: XVE DATAPORT READ MESSAGE COUNT XECORE6 */
#define acmgt1__ext86__xve_dataport_read_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext86 :: XVE DATAPORT READ MESSAGE COUNT XECORE7 */
#define acmgt1__ext86__xve_dataport_read_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext87 :: GPU Time Elapsed */
#define acmgt1__ext87__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext87 :: GPU Core Clocks */
#define acmgt1__ext87__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext87 :: AVG GPU Core Frequency */
#define acmgt1__ext87__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext87 :: AVG GPU Core Frequency */
#define acmgt1__ext87__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE0 */
#define acmgt1__ext87__xve_dataport_write_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE1 */
#define acmgt1__ext87__xve_dataport_write_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE2 */
#define acmgt1__ext87__xve_dataport_write_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE3 */
#define acmgt1__ext87__xve_dataport_write_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext88 :: GPU Time Elapsed */
#define acmgt1__ext88__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext88 :: GPU Core Clocks */
#define acmgt1__ext88__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext88 :: AVG GPU Core Frequency */
#define acmgt1__ext88__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext88 :: AVG GPU Core Frequency */
#define acmgt1__ext88__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext88 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE4 */
#define acmgt1__ext88__xve_dataport_write_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext88 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE5 */
#define acmgt1__ext88__xve_dataport_write_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext88 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE6 */
#define acmgt1__ext88__xve_dataport_write_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext88 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE7 */
#define acmgt1__ext88__xve_dataport_write_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext91 :: GPU Time Elapsed */
#define acmgt1__ext91__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext91 :: GPU Core Clocks */
#define acmgt1__ext91__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext91 :: AVG GPU Core Frequency */
#define acmgt1__ext91__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext91 :: AVG GPU Core Frequency */
#define acmgt1__ext91__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0 */
#define acmgt1__ext91__xve_dataport_atomic_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1 */
#define acmgt1__ext91__xve_dataport_atomic_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2 */
#define acmgt1__ext91__xve_dataport_atomic_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3 */
#define acmgt1__ext91__xve_dataport_atomic_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext92 :: GPU Time Elapsed */
#define acmgt1__ext92__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext92 :: GPU Core Clocks */
#define acmgt1__ext92__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext92 :: AVG GPU Core Frequency */
#define acmgt1__ext92__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext92 :: AVG GPU Core Frequency */
#define acmgt1__ext92__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext92 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4 */
#define acmgt1__ext92__xve_dataport_atomic_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext92 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5 */
#define acmgt1__ext92__xve_dataport_atomic_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext92 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6 */
#define acmgt1__ext92__xve_dataport_atomic_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext92 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7 */
#define acmgt1__ext92__xve_dataport_atomic_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext93 :: GPU Time Elapsed */
#define acmgt1__ext93__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext93 :: GPU Core Clocks */
#define acmgt1__ext93__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext93 :: AVG GPU Core Frequency */
#define acmgt1__ext93__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext93 :: AVG GPU Core Frequency */
#define acmgt1__ext93__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext93 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE0 */
static uint64_t
acmgt1__ext93__xve_dataport_register_response_count_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                                  const struct intel_perf_query_info *query,
                                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ UADD B 2 READ UADD B 3 READ UADD 2 UDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 2];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 3];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = tmp6;
   uint64_t tmp8 = 2;
   uint64_t tmp9 = tmp7 / tmp8;

   return tmp9;
}

/* Ext93 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE1 */
static float
acmgt1__ext93__xve_dataport_register_response_count_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                                  const struct intel_perf_query_info *query,
                                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ FADD B 6 READ FADD B 7 READ FADD 2 FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 6];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 7];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 2;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext94 :: GPU Time Elapsed */
#define acmgt1__ext94__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext94 :: GPU Core Clocks */
#define acmgt1__ext94__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext94 :: AVG GPU Core Frequency */
#define acmgt1__ext94__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext94 :: AVG GPU Core Frequency */
#define acmgt1__ext94__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext94 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE2 */
static float
acmgt1__ext94__xve_dataport_register_response_count_xecore2__read(UNUSED struct intel_perf_config *perf,
                                                                  const struct intel_perf_query_info *query,
                                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ FADD B 2 READ FADD B 3 READ FADD 2 FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 2];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 3];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 2;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext94 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE3 */
#define acmgt1__ext94__xve_dataport_register_response_count_xecore3__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext95 :: GPU Time Elapsed */
#define acmgt1__ext95__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext95 :: GPU Core Clocks */
#define acmgt1__ext95__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext95 :: AVG GPU Core Frequency */
#define acmgt1__ext95__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext95 :: AVG GPU Core Frequency */
#define acmgt1__ext95__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext95 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE4 */
#define acmgt1__ext95__xve_dataport_register_response_count_xecore4__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext95 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE5 */
#define acmgt1__ext95__xve_dataport_register_response_count_xecore5__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext96 :: GPU Time Elapsed */
#define acmgt1__ext96__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext96 :: GPU Core Clocks */
#define acmgt1__ext96__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext96 :: AVG GPU Core Frequency */
#define acmgt1__ext96__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext96 :: AVG GPU Core Frequency */
#define acmgt1__ext96__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext96 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE6 */
#define acmgt1__ext96__xve_dataport_register_response_count_xecore6__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext96 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE7 */
#define acmgt1__ext96__xve_dataport_register_response_count_xecore7__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext97 :: GPU Time Elapsed */
#define acmgt1__ext97__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext97 :: GPU Core Clocks */
#define acmgt1__ext97__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext97 :: AVG GPU Core Frequency */
#define acmgt1__ext97__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext97 :: AVG GPU Core Frequency */
#define acmgt1__ext97__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE0 */
#define acmgt1__ext97__xve_dataport_register_request_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE1 */
#define acmgt1__ext97__xve_dataport_register_request_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE2 */
#define acmgt1__ext97__xve_dataport_register_request_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE3 */
#define acmgt1__ext97__xve_dataport_register_request_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE4 */
#define acmgt1__ext97__xve_dataport_register_request_count_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE5 */
#define acmgt1__ext97__xve_dataport_register_request_count_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE6 */
#define acmgt1__ext97__xve_dataport_register_request_count_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE7 */
#define acmgt1__ext97__xve_dataport_register_request_count_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext98 :: GPU Time Elapsed */
#define acmgt1__ext98__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext98 :: GPU Core Clocks */
#define acmgt1__ext98__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext98 :: AVG GPU Core Frequency */
#define acmgt1__ext98__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext98 :: AVG GPU Core Frequency */
#define acmgt1__ext98__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext98 :: SAMPLER OUTPUT READY XECORE0 */
#define acmgt1__ext98__sampler_output_ready_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext98 :: SAMPLER OUTPUT READY XECORE1 */
#define acmgt1__ext98__sampler_output_ready_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext98 :: SAMPLER OUTPUT READY XECORE2 */
#define acmgt1__ext98__sampler_output_ready_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext98 :: SAMPLER OUTPUT READY XECORE3 */
#define acmgt1__ext98__sampler_output_ready_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext99 :: GPU Time Elapsed */
#define acmgt1__ext99__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext99 :: GPU Core Clocks */
#define acmgt1__ext99__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext99 :: AVG GPU Core Frequency */
#define acmgt1__ext99__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext99 :: AVG GPU Core Frequency */
#define acmgt1__ext99__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext99 :: SAMPLER OUTPUT READY XECORE4 */
#define acmgt1__ext99__sampler_output_ready_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext99 :: SAMPLER OUTPUT READY XECORE5 */
#define acmgt1__ext99__sampler_output_ready_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext99 :: SAMPLER OUTPUT READY XECORE6 */
#define acmgt1__ext99__sampler_output_ready_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext99 :: SAMPLER OUTPUT READY XECORE7 */
#define acmgt1__ext99__sampler_output_ready_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext100 :: GPU Time Elapsed */
#define acmgt1__ext100__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext100 :: GPU Core Clocks */
#define acmgt1__ext100__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext100 :: AVG GPU Core Frequency */
#define acmgt1__ext100__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext100 :: AVG GPU Core Frequency */
#define acmgt1__ext100__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE0 */
#define acmgt1__ext100__sampler_memory_latency_stall_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE1 */
#define acmgt1__ext100__sampler_memory_latency_stall_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE2 */
#define acmgt1__ext100__sampler_memory_latency_stall_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE3 */
#define acmgt1__ext100__sampler_memory_latency_stall_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE4 */
#define acmgt1__ext100__sampler_memory_latency_stall_xecore4__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE5 */
#define acmgt1__ext100__sampler_memory_latency_stall_xecore5__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE6 */
#define acmgt1__ext100__sampler_memory_latency_stall_xecore6__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE7 */
#define acmgt1__ext100__sampler_memory_latency_stall_xecore7__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext101 :: GPU Time Elapsed */
#define acmgt1__ext101__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext101 :: GPU Core Clocks */
#define acmgt1__ext101__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext101 :: AVG GPU Core Frequency */
#define acmgt1__ext101__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext101 :: AVG GPU Core Frequency */
#define acmgt1__ext101__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext101 :: THREAD DISPATCH STALL XECORE0 */
#define acmgt1__ext101__thread_dispatch_stall_xecore0__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext101 :: THREAD DISPATCH STALL XECORE1 */
#define acmgt1__ext101__thread_dispatch_stall_xecore1__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext101 :: THREAD DISPATCH STALL XECORE2 */
#define acmgt1__ext101__thread_dispatch_stall_xecore2__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext101 :: THREAD DISPATCH STALL XECORE3 */
#define acmgt1__ext101__thread_dispatch_stall_xecore3__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext101 :: THREAD DISPATCH STALL XECORE4 */
#define acmgt1__ext101__thread_dispatch_stall_xecore4__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext101 :: THREAD DISPATCH STALL XECORE5 */
#define acmgt1__ext101__thread_dispatch_stall_xecore5__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext101 :: THREAD DISPATCH STALL XECORE6 */
#define acmgt1__ext101__thread_dispatch_stall_xecore6__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext101 :: THREAD DISPATCH STALL XECORE7 */
#define acmgt1__ext101__thread_dispatch_stall_xecore7__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE0 */
#define acmgt1__ext101__thread_dispatch_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE1 */
#define acmgt1__ext101__thread_dispatch_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE2 */
#define acmgt1__ext101__thread_dispatch_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE3 */
#define acmgt1__ext101__thread_dispatch_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE4 */
#define acmgt1__ext101__thread_dispatch_input_available_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE5 */
#define acmgt1__ext101__thread_dispatch_input_available_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE6 */
#define acmgt1__ext101__thread_dispatch_input_available_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE7 */
#define acmgt1__ext101__thread_dispatch_input_available_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext102 :: GPU Time Elapsed */
#define acmgt1__ext102__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext102 :: GPU Core Clocks */
#define acmgt1__ext102__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext102 :: AVG GPU Core Frequency */
#define acmgt1__ext102__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext102 :: AVG GPU Core Frequency */
#define acmgt1__ext102__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE0 */
#define acmgt1__ext102__sampler_texture_cache_access_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE1 */
#define acmgt1__ext102__sampler_texture_cache_access_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE2 */
#define acmgt1__ext102__sampler_texture_cache_access_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE3 */
#define acmgt1__ext102__sampler_texture_cache_access_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE4 */
#define acmgt1__ext102__sampler_texture_cache_access_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE5 */
#define acmgt1__ext102__sampler_texture_cache_access_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE6 */
#define acmgt1__ext102__sampler_texture_cache_access_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE7 */
#define acmgt1__ext102__sampler_texture_cache_access_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE0 */
#define acmgt1__ext102__sampler_texture_cache_miss_xecore0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE1 */
#define acmgt1__ext102__sampler_texture_cache_miss_xecore1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE2 */
#define acmgt1__ext102__sampler_texture_cache_miss_xecore2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE3 */
#define acmgt1__ext102__sampler_texture_cache_miss_xecore3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE4 */
#define acmgt1__ext102__sampler_texture_cache_miss_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE5 */
#define acmgt1__ext102__sampler_texture_cache_miss_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE6 */
#define acmgt1__ext102__sampler_texture_cache_miss_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE7 */
#define acmgt1__ext102__sampler_texture_cache_miss_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext103 :: GPU Time Elapsed */
#define acmgt1__ext103__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext103 :: GPU Core Clocks */
#define acmgt1__ext103__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext103 :: AVG GPU Core Frequency */
#define acmgt1__ext103__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext103 :: AVG GPU Core Frequency */
#define acmgt1__ext103__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext103 :: SAMPLER INPUT AVAILABLE XECORE0 */
#define acmgt1__ext103__sampler_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext103 :: SAMPLER INPUT AVAILABLE XECORE1 */
#define acmgt1__ext103__sampler_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext103 :: SAMPLER INPUT AVAILABLE XECORE2 */
#define acmgt1__ext103__sampler_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext103 :: SAMPLER INPUT AVAILABLE XECORE3 */
#define acmgt1__ext103__sampler_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext103 :: SAMPLER INPUT AVAILABLE XECORE4 */
#define acmgt1__ext103__sampler_input_available_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext103 :: SAMPLER INPUT AVAILABLE XECORE5 */
#define acmgt1__ext103__sampler_input_available_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext103 :: SAMPLER INPUT AVAILABLE XECORE6 */
#define acmgt1__ext103__sampler_input_available_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext103 :: SAMPLER INPUT AVAILABLE XECORE7 */
#define acmgt1__ext103__sampler_input_available_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext104 :: GPU Time Elapsed */
#define acmgt1__ext104__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext104 :: GPU Core Clocks */
#define acmgt1__ext104__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext104 :: AVG GPU Core Frequency */
#define acmgt1__ext104__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext104 :: AVG GPU Core Frequency */
#define acmgt1__ext104__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext104 :: ASYNC GPGPU THREAD EXIT COUNT XECORE0 */
#define acmgt1__ext104__async_gpgpu_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext104 :: TASK THREAD EXIT COUNT XECORE0 */
#define acmgt1__ext104__task_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext104 :: GPGPU THREADGROUP COUNT XECORE2 */
#define acmgt1__ext104__gpgpu_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext104 :: GPGPU THREADGROUP COUNT XECORE3 */
#define acmgt1__ext104__gpgpu_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext104 :: TASK THREADGROUP COUNT XECORE2 */
#define acmgt1__ext104__task_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext104 :: TASK THREADGROUP COUNT XECORE3 */
#define acmgt1__ext104__task_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext105 :: GPU Time Elapsed */
#define acmgt1__ext105__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext105 :: GPU Core Clocks */
#define acmgt1__ext105__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext105 :: AVG GPU Core Frequency */
#define acmgt1__ext105__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext105 :: AVG GPU Core Frequency */
#define acmgt1__ext105__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext105 :: ASYNC GPGPU THREAD EXIT COUNT XECORE1 */
#define acmgt1__ext105__async_gpgpu_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext105 :: TASK THREAD EXIT COUNT XECORE1 */
#define acmgt1__ext105__task_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext105 :: GPGPU THREADGROUP COUNT XECORE4 */
#define acmgt1__ext105__gpgpu_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext105 :: GPGPU THREADGROUP COUNT XECORE5 */
#define acmgt1__ext105__gpgpu_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext105 :: TASK THREADGROUP COUNT XECORE4 */
#define acmgt1__ext105__task_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext105 :: TASK THREADGROUP COUNT XECORE5 */
#define acmgt1__ext105__task_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext106 :: GPU Time Elapsed */
#define acmgt1__ext106__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext106 :: GPU Core Clocks */
#define acmgt1__ext106__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext106 :: AVG GPU Core Frequency */
#define acmgt1__ext106__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext106 :: AVG GPU Core Frequency */
#define acmgt1__ext106__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext106 :: ASYNC GPGPU THREAD EXIT COUNT XECORE2 */
#define acmgt1__ext106__async_gpgpu_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext106 :: TASK THREAD EXIT COUNT XECORE2 */
#define acmgt1__ext106__task_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext106 :: GPGPU THREADGROUP COUNT XECORE6 */
#define acmgt1__ext106__gpgpu_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext106 :: GPGPU THREADGROUP COUNT XECORE7 */
#define acmgt1__ext106__gpgpu_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext106 :: TASK THREADGROUP COUNT XECORE6 */
#define acmgt1__ext106__task_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext106 :: TASK THREADGROUP COUNT XECORE7 */
#define acmgt1__ext106__task_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext107 :: GPU Time Elapsed */
#define acmgt1__ext107__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext107 :: GPU Core Clocks */
#define acmgt1__ext107__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext107 :: AVG GPU Core Frequency */
#define acmgt1__ext107__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext107 :: AVG GPU Core Frequency */
#define acmgt1__ext107__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext107 :: ASYNC GPGPU THREAD EXIT COUNT XECORE3 */
#define acmgt1__ext107__async_gpgpu_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext107 :: TASK THREAD EXIT COUNT XECORE3 */
#define acmgt1__ext107__task_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext107 :: GPGPU THREADGROUP COUNT XECORE0 */
#define acmgt1__ext107__gpgpu_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext107 :: GPGPU THREADGROUP COUNT XECORE1 */
#define acmgt1__ext107__gpgpu_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext107 :: TASK THREADGROUP COUNT XECORE0 */
#define acmgt1__ext107__task_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext107 :: TASK THREADGROUP COUNT XECORE1 */
#define acmgt1__ext107__task_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext108 :: GPU Time Elapsed */
#define acmgt1__ext108__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext108 :: GPU Core Clocks */
#define acmgt1__ext108__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext108 :: AVG GPU Core Frequency */
#define acmgt1__ext108__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext108 :: AVG GPU Core Frequency */
#define acmgt1__ext108__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext108 :: ASYNC GPGPU THREAD EXIT COUNT XECORE4 */
#define acmgt1__ext108__async_gpgpu_thread_exit_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext108 :: TASK THREAD EXIT COUNT XECORE4 */
#define acmgt1__ext108__task_thread_exit_count_xecore4__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext108 :: ASYNC GPGPU THREADGROUP COUNT XECORE6 */
#define acmgt1__ext108__async_gpgpu_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext108 :: ASYNC GPGPU THREADGROUP COUNT XECORE7 */
#define acmgt1__ext108__async_gpgpu_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext109 :: GPU Time Elapsed */
#define acmgt1__ext109__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext109 :: GPU Core Clocks */
#define acmgt1__ext109__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext109 :: AVG GPU Core Frequency */
#define acmgt1__ext109__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext109 :: AVG GPU Core Frequency */
#define acmgt1__ext109__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext109 :: ASYNC GPGPU THREAD EXIT COUNT XECORE5 */
#define acmgt1__ext109__async_gpgpu_thread_exit_count_xecore5__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext109 :: TASK THREAD EXIT COUNT XECORE5 */
#define acmgt1__ext109__task_thread_exit_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext109 :: ASYNC GPGPU THREADGROUP COUNT XECORE1 */
#define acmgt1__ext109__async_gpgpu_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext109 :: ASYNC GPGPU THREADGROUP COUNT XECORE2 */
#define acmgt1__ext109__async_gpgpu_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext110 :: GPU Time Elapsed */
#define acmgt1__ext110__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext110 :: GPU Core Clocks */
#define acmgt1__ext110__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext110 :: AVG GPU Core Frequency */
#define acmgt1__ext110__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext110 :: AVG GPU Core Frequency */
#define acmgt1__ext110__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext110 :: ASYNC GPGPU THREAD EXIT COUNT XECORE6 */
#define acmgt1__ext110__async_gpgpu_thread_exit_count_xecore6__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext110 :: TASK THREAD EXIT COUNT XECORE6 */
#define acmgt1__ext110__task_thread_exit_count_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext110 :: ASYNC GPGPU THREADGROUP COUNT XECORE3 */
#define acmgt1__ext110__async_gpgpu_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext110 :: ASYNC GPGPU THREADGROUP COUNT XECORE4 */
#define acmgt1__ext110__async_gpgpu_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext111 :: GPU Time Elapsed */
#define acmgt1__ext111__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext111 :: GPU Core Clocks */
#define acmgt1__ext111__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext111 :: AVG GPU Core Frequency */
#define acmgt1__ext111__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext111 :: AVG GPU Core Frequency */
#define acmgt1__ext111__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext111 :: ASYNC GPGPU THREAD EXIT COUNT XECORE7 */
#define acmgt1__ext111__async_gpgpu_thread_exit_count_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext111 :: TASK THREAD EXIT COUNT XECORE7 */
#define acmgt1__ext111__task_thread_exit_count_xecore7__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext111 :: ASYNC GPGPU THREADGROUP COUNT XECORE5 */
#define acmgt1__ext111__async_gpgpu_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext111 :: ASYNC GPGPU THREADGROUP COUNT XECORE0 */
#define acmgt1__ext111__async_gpgpu_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext112 :: GPU Time Elapsed */
#define acmgt1__ext112__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext112 :: GPU Core Clocks */
#define acmgt1__ext112__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext112 :: AVG GPU Core Frequency */
#define acmgt1__ext112__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext112 :: AVG GPU Core Frequency */
#define acmgt1__ext112__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext112 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE0 */
#define acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE1 */
#define acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE2 */
#define acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE3 */
#define acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE4 */
#define acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE5 */
#define acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE6 */
#define acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE7 */
#define acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE0 */
#define acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE1 */
#define acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE2 */
#define acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE3 */
#define acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE4 */
#define acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE5 */
#define acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE6 */
#define acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore6__read \
   bdw__render_basic__sampler1_busy__read

/* Ext112 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE7 */
#define acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext113 :: GPU Time Elapsed */
#define acmgt1__ext113__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext113 :: GPU Core Clocks */
#define acmgt1__ext113__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext113 :: AVG GPU Core Frequency */
#define acmgt1__ext113__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext113 :: AVG GPU Core Frequency */
#define acmgt1__ext113__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext113 :: THREAD DISPATCH PS ACTIVE XECORE0 */
#define acmgt1__ext113__thread_dispatch_ps_active_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE XECORE1 */
#define acmgt1__ext113__thread_dispatch_ps_active_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE XECORE2 */
#define acmgt1__ext113__thread_dispatch_ps_active_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE XECORE3 */
#define acmgt1__ext113__thread_dispatch_ps_active_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE XECORE4 */
#define acmgt1__ext113__thread_dispatch_ps_active_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE XECORE5 */
#define acmgt1__ext113__thread_dispatch_ps_active_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE XECORE6 */
#define acmgt1__ext113__thread_dispatch_ps_active_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE XECORE7 */
#define acmgt1__ext113__thread_dispatch_ps_active_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext114 :: GPU Time Elapsed */
#define acmgt1__ext114__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext114 :: GPU Core Clocks */
#define acmgt1__ext114__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext114 :: AVG GPU Core Frequency */
#define acmgt1__ext114__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext114 :: AVG GPU Core Frequency */
#define acmgt1__ext114__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE0 */
#define acmgt1__ext114__thread_dispatch_queue0_active_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE1 */
#define acmgt1__ext114__thread_dispatch_queue0_active_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE2 */
#define acmgt1__ext114__thread_dispatch_queue0_active_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE3 */
#define acmgt1__ext114__thread_dispatch_queue0_active_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE4 */
#define acmgt1__ext114__thread_dispatch_queue0_active_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE5 */
#define acmgt1__ext114__thread_dispatch_queue0_active_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE6 */
#define acmgt1__ext114__thread_dispatch_queue0_active_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE7 */
#define acmgt1__ext114__thread_dispatch_queue0_active_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext115 :: GPU Time Elapsed */
#define acmgt1__ext115__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext115 :: GPU Core Clocks */
#define acmgt1__ext115__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext115 :: AVG GPU Core Frequency */
#define acmgt1__ext115__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext115 :: AVG GPU Core Frequency */
#define acmgt1__ext115__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext115 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE0 */
#define acmgt1__ext115__thread_dispatch_queue1_active_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext115 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE1 */
#define acmgt1__ext115__thread_dispatch_queue1_active_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext115 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE2 */
#define acmgt1__ext115__thread_dispatch_queue1_active_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext115 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE3 */
#define acmgt1__ext115__thread_dispatch_queue1_active_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext115 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE4 */
#define acmgt1__ext115__thread_dispatch_queue1_active_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext115 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE5 */
#define acmgt1__ext115__thread_dispatch_queue1_active_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext115 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE6 */
#define acmgt1__ext115__thread_dispatch_queue1_active_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext115 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE7 */
#define acmgt1__ext115__thread_dispatch_queue1_active_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext116 :: GPU Time Elapsed */
#define acmgt1__ext116__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext116 :: GPU Core Clocks */
#define acmgt1__ext116__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext116 :: AVG GPU Core Frequency */
#define acmgt1__ext116__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext116 :: AVG GPU Core Frequency */
#define acmgt1__ext116__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE0 */
#define acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE1 */
#define acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE2 */
#define acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE3 */
#define acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext117 :: GPU Time Elapsed */
#define acmgt1__ext117__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext117 :: GPU Core Clocks */
#define acmgt1__ext117__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext117 :: AVG GPU Core Frequency */
#define acmgt1__ext117__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext117 :: AVG GPU Core Frequency */
#define acmgt1__ext117__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext117 :: THREADGROUP DISPATCH RESOURCE STALL XECORE4 */
#define acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext117 :: THREADGROUP DISPATCH RESOURCE STALL XECORE5 */
#define acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext117 :: THREADGROUP DISPATCH RESOURCE STALL XECORE6 */
#define acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext117 :: THREADGROUP DISPATCH RESOURCE STALL XECORE7 */
#define acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext118 :: GPU Time Elapsed */
#define acmgt1__ext118__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext118 :: GPU Core Clocks */
#define acmgt1__ext118__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext118 :: AVG GPU Core Frequency */
#define acmgt1__ext118__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext118 :: AVG GPU Core Frequency */
#define acmgt1__ext118__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext118 :: AMFS STALL ALL INPUT SLICE0 */
#define acmgt1__ext118__amfs_stall_all_input_slice0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext118 :: AMFS STALL ANY INPUT SLICE0 */
#define acmgt1__ext118__amfs_stall_any_input_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext118 :: AMFS CACHE HIT SLICE0 */
#define acmgt1__ext118__amfs_cache_hit_slice0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext118 :: AMFS CACHE MISS SLICE0 */
#define acmgt1__ext118__amfs_cache_miss_slice0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext118 :: RENDER CACHE HIT L3NODE0 */
#define acmgt1__ext118__render_cache_hit_l3_node0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext118 :: RENDER CACHE READ L3NODE0 */
#define acmgt1__ext118__render_cache_read_l3_node0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext118 :: RENDER CACHE WRITE L3NODE0 */
#define acmgt1__ext118__render_cache_write_l3_node0__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext118 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE0 */
#define acmgt1__ext118__render_cache_input_available_l3_node0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext118 :: RENDER_CACHE_OUTPUT_READY _L3NODE0 */
#define acmgt1__ext118__render_cache_output_ready_l3_node0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext119 :: GPU Time Elapsed */
#define acmgt1__ext119__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext119 :: GPU Core Clocks */
#define acmgt1__ext119__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext119 :: AVG GPU Core Frequency */
#define acmgt1__ext119__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext119 :: AVG GPU Core Frequency */
#define acmgt1__ext119__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext119 :: AMFS STALL ALL INPUT SLICE1 */
#define acmgt1__ext119__amfs_stall_all_input_slice1__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext119 :: AMFS STALL ANY INPUT SLICE1 */
#define acmgt1__ext119__amfs_stall_any_input_slice1__read \
   bdw__render_basic__sampler0_busy__read

/* Ext119 :: AMFS CACHE HIT SLICE1 */
#define acmgt1__ext119__amfs_cache_hit_slice1__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext119 :: AMFS CACHE MISS SLICE1 */
#define acmgt1__ext119__amfs_cache_miss_slice1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext119 :: RENDER CACHE HIT L3NODE1 */
#define acmgt1__ext119__render_cache_hit_l3_node1__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext119 :: RENDER CACHE READ L3NODE1 */
#define acmgt1__ext119__render_cache_read_l3_node1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext119 :: RENDER CACHE WRITE L3NODE1 */
#define acmgt1__ext119__render_cache_write_l3_node1__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext119 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE1 */
#define acmgt1__ext119__render_cache_input_available_l3_node1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext119 :: RENDER_CACHE_OUTPUT_READY _L3NODE1 */
#define acmgt1__ext119__render_cache_output_ready_l3_node1__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext120 :: GPU Time Elapsed */
#define acmgt1__ext120__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext120 :: GPU Core Clocks */
#define acmgt1__ext120__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext120 :: AVG GPU Core Frequency */
#define acmgt1__ext120__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext120 :: AVG GPU Core Frequency */
#define acmgt1__ext120__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE0 */
#define acmgt1__ext120__pixel_post_process_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE1 */
#define acmgt1__ext120__pixel_post_process_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE2 */
#define acmgt1__ext120__pixel_post_process_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE3 */
#define acmgt1__ext120__pixel_post_process_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext121 :: GPU Time Elapsed */
#define acmgt1__ext121__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext121 :: GPU Core Clocks */
#define acmgt1__ext121__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext121 :: AVG GPU Core Frequency */
#define acmgt1__ext121__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext121 :: AVG GPU Core Frequency */
#define acmgt1__ext121__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext121 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE4 */
#define acmgt1__ext121__pixel_post_process_input_available_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext121 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE5 */
#define acmgt1__ext121__pixel_post_process_input_available_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext121 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE6 */
#define acmgt1__ext121__pixel_post_process_input_available_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext121 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE7 */
#define acmgt1__ext121__pixel_post_process_input_available_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext122 :: GPU Time Elapsed */
#define acmgt1__ext122__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext122 :: GPU Core Clocks */
#define acmgt1__ext122__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext122 :: AVG GPU Core Frequency */
#define acmgt1__ext122__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext122 :: AVG GPU Core Frequency */
#define acmgt1__ext122__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext122 :: AMFS 4X4 SHADING REQUEST SLICE0 */
#define acmgt1__ext122__amfs_4_x4_shading_request_slice0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext122 :: AMFS 4X4 SHADING REQUEST SLICE1 */
#define acmgt1__ext122__amfs_4_x4_shading_request_slice1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE0 */
#define acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE1 */
#define acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE2 */
#define acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE3 */
#define acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE0 */
#define acmgt1__ext122__pixel_post_process_output_ready_cpipe0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE1 */
#define acmgt1__ext122__pixel_post_process_output_ready_cpipe1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE2 */
#define acmgt1__ext122__pixel_post_process_output_ready_cpipe2__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE3 */
#define acmgt1__ext122__pixel_post_process_output_ready_cpipe3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext123 :: GPU Time Elapsed */
#define acmgt1__ext123__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext123 :: GPU Core Clocks */
#define acmgt1__ext123__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext123 :: AVG GPU Core Frequency */
#define acmgt1__ext123__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext123 :: AVG GPU Core Frequency */
#define acmgt1__ext123__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext123 :: PS OUTPUT AVAILABLE CPIPE0 */
#define acmgt1__ext123__ps_output_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext123 :: PS OUTPUT AVAILABLE CPIPE1 */
#define acmgt1__ext123__ps_output_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext123 :: PS OUTPUT AVAILABLE CPIPE2 */
#define acmgt1__ext123__ps_output_available_cpipe2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext123 :: PS OUTPUT AVAILABLE CPIPE3 */
#define acmgt1__ext123__ps_output_available_cpipe3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext123 :: AMFS L3 ACCESS SLICE0 */
#define acmgt1__ext123__amfs_l3_access_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext123 :: AMFS L3 ACCESS SLICE1 */
#define acmgt1__ext123__amfs_l3_access_slice1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext123 :: AMFS L3 ATOMIC SLICE0 */
#define acmgt1__ext123__amfs_l3_atomic_slice0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext123 :: AMFS L3 ATOMIC SLICE1 */
#define acmgt1__ext123__amfs_l3_atomic_slice1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext124 :: GPU Time Elapsed */
#define acmgt1__ext124__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext124 :: GPU Core Clocks */
#define acmgt1__ext124__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext124 :: AVG GPU Core Frequency */
#define acmgt1__ext124__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext124 :: AVG GPU Core Frequency */
#define acmgt1__ext124__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext124 :: VERTEX FETCH INPUT AVAILABLE SLICE0 */
#define acmgt1__ext124__vertex_fetch_input_available_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext124 :: VERTEX FETCH INPUT AVAILABLE SLICE1 */
#define acmgt1__ext124__vertex_fetch_input_available_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext124 :: VERTEX FETCH OUTPUT READY SLICE0 */
#define acmgt1__ext124__vertex_fetch_output_ready_slice0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext124 :: VERTEX FETCH OUTPUT READY SLICE1 */
#define acmgt1__ext124__vertex_fetch_output_ready_slice1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext124 :: CLIPPER INPUT VERTEX SLICE0 */
static uint64_t
acmgt1__ext124__clipper_input_vertex_slice0__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ B 3 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->b_offset + 3];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext124 :: CLIPPER INPUT VERTEX SLICE1 */
static uint64_t
acmgt1__ext124__clipper_input_vertex_slice1__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext124 :: STREAMOUT OUTPUT VERTEX COUNT SLICE0 */
#define acmgt1__ext124__streamout_output_vertex_count_slice0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext124 :: STREAMOUT OUTPUT VERTEX COUNT SLICE1 */
#define acmgt1__ext124__streamout_output_vertex_count_slice1__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext124 :: VS OUTPUT READY SLICE0 */
#define acmgt1__ext124__vs_output_ready_slice0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext124 :: VS OUTPUT READY SLICE1 */
#define acmgt1__ext124__vs_output_ready_slice1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext125 :: GPU Time Elapsed */
#define acmgt1__ext125__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext125 :: GPU Core Clocks */
#define acmgt1__ext125__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext125 :: AVG GPU Core Frequency */
#define acmgt1__ext125__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext125 :: AVG GPU Core Frequency */
#define acmgt1__ext125__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext125 :: CLIPPER INPUT AVAILABLE SLICE0 */
#define acmgt1__ext125__clipper_input_available_slice0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext125 :: CLIPPER INPUT AVAILABLE SLICE1 */
#define acmgt1__ext125__clipper_input_available_slice1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext125 :: CLIPPER OUTPUT READY SLICE0 */
#define acmgt1__ext125__clipper_output_ready_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext125 :: CLIPPER OUTPUT READY SLICE1 */
#define acmgt1__ext125__clipper_output_ready_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext125 :: CLIPPER PRIMITIVE OUTPUT SLICE0 */
#define acmgt1__ext125__clipper_primitive_output_slice0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext125 :: CLIPPER PRIMITIVE OUTPUT SLICE1 */
#define acmgt1__ext125__clipper_primitive_output_slice1__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext126 :: GPU Time Elapsed */
#define acmgt1__ext126__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext126 :: GPU Core Clocks */
#define acmgt1__ext126__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext126 :: AVG GPU Core Frequency */
#define acmgt1__ext126__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext126 :: AVG GPU Core Frequency */
#define acmgt1__ext126__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext126 :: CLIPPER TRANSACTION OUTPUT SLICE0 */
#define acmgt1__ext126__clipper_transaction_output_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext126 :: CLIPPER TRANSACTION OUTPUT SLICE1 */
#define acmgt1__ext126__clipper_transaction_output_slice1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext126 :: STRIPSFAN OBJECT COUNT SLICE0 */
#define acmgt1__ext126__stripsfan_object_count_slice0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext126 :: STRIPSFAN OBJECT COUNT SLICE1 */
#define acmgt1__ext126__stripsfan_object_count_slice1__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext126 :: STRIPSFAN OBJECTS CULL SLICE0 */
#define acmgt1__ext126__stripsfan_objects_cull_slice0__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext126 :: STRIPSFAN OBJECTS CULL SLICE1 */
#define acmgt1__ext126__stripsfan_objects_cull_slice1__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext126 :: STRIPSFAN OUTPUT READY SLICE0 */
#define acmgt1__ext126__stripsfan_output_ready_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext126 :: STRIPSFAN OUTPUT READY SLICE1 */
#define acmgt1__ext126__stripsfan_output_ready_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext126 :: RASTERIZER TRANSACTION OUTPUT SLICE0 */
#define acmgt1__ext126__rasterizer_transaction_output_slice0__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext126 :: RASTERIZER TRANSACTION OUTPUT SLICE1 */
#define acmgt1__ext126__rasterizer_transaction_output_slice1__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext127 :: GPU Time Elapsed */
#define acmgt1__ext127__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext127 :: GPU Core Clocks */
#define acmgt1__ext127__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext127 :: AVG GPU Core Frequency */
#define acmgt1__ext127__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext127 :: AVG GPU Core Frequency */
#define acmgt1__ext127__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext127 :: RASTERIZER INPUT AVAILABLE SLICE0 */
#define acmgt1__ext127__rasterizer_input_available_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext127 :: RASTERIZER INPUT AVAILABLE SLICE1 */
#define acmgt1__ext127__rasterizer_input_available_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext127 :: RASTERIZER OUTPUT READY SLICE0 */
#define acmgt1__ext127__rasterizer_output_ready_slice0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext127 :: RASTERIZER OUTPUT READY SLICE1 */
#define acmgt1__ext127__rasterizer_output_ready_slice1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext127 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0 */
#define acmgt1__ext127__clipper_primitive_far_near_clip_slice0__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext127 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1 */
#define acmgt1__ext127__clipper_primitive_far_near_clip_slice1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext127 :: CLIPPER PRIMITIVE CULL SLICE0 */
#define acmgt1__ext127__clipper_primitive_cull_slice0__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext127 :: CLIPPER PRIMITIVE CULL SLICE1 */
#define acmgt1__ext127__clipper_primitive_cull_slice1__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext128 :: GPU Time Elapsed */
#define acmgt1__ext128__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext128 :: GPU Core Clocks */
#define acmgt1__ext128__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext128 :: AVG GPU Core Frequency */
#define acmgt1__ext128__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext128 :: AVG GPU Core Frequency */
#define acmgt1__ext128__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext128 :: URB READ SLICE0 */
static uint64_t
acmgt1__ext128__urb_read_slice0__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ UADD C 5 READ UADD C 4 READ UADD C 3 READ UADD C 2 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 3];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->c_offset + 2];
   uint64_t tmp10 = tmp8 + tmp9;

   return tmp10;
}

/* Ext128 :: URB WRITE SLICE0 */
static uint64_t
acmgt1__ext128__urb_write_slice0__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ C 0 READ UADD B 7 READ UADD B 6 READ UADD B 5 READ UADD B 4 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 0];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 7];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 6];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 5];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->b_offset + 4];
   uint64_t tmp10 = tmp8 + tmp9;

   return tmp10;
}

/* Ext128 :: URB CROSS SLICE READ SLICE0 */
#define acmgt1__ext128__urb_cross_slice_read_slice0__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext129 :: GPU Time Elapsed */
#define acmgt1__ext129__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext129 :: GPU Core Clocks */
#define acmgt1__ext129__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext129 :: AVG GPU Core Frequency */
#define acmgt1__ext129__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext129 :: AVG GPU Core Frequency */
#define acmgt1__ext129__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext129 :: URB READ SLICE1 */
#define acmgt1__ext129__urb_read_slice1__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext129 :: URB WRITE SLICE1 */
#define acmgt1__ext129__urb_write_slice1__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext129 :: URB CROSS SLICE READ SLICE1 */
#define acmgt1__ext129__urb_cross_slice_read_slice1__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext130 :: GPU Time Elapsed */
#define acmgt1__ext130__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext130 :: GPU Core Clocks */
#define acmgt1__ext130__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext130 :: AVG GPU Core Frequency */
#define acmgt1__ext130__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext130 :: AVG GPU Core Frequency */
#define acmgt1__ext130__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext130 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0 */
static uint64_t
acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read(UNUSED struct intel_perf_config *perf,
                                                              const struct intel_perf_query_info *query,
                                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD 16 C 3 READ UMUL UADD B 0 READ 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD 16 B 4 READ UMUL UADD USUB */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 0];
   uint64_t tmp14 = results->accumulator[query->b_offset + 1];
   uint64_t tmp15 = 2 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->b_offset + 2];
   uint64_t tmp18 = 4 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = results->accumulator[query->b_offset + 3];
   uint64_t tmp21 = 8 * tmp20;
   uint64_t tmp22 = tmp19 + tmp21;
   uint64_t tmp23 = results->accumulator[query->b_offset + 4];
   uint64_t tmp24 = 16 * tmp23;
   uint64_t tmp25 = tmp22 + tmp24;
   uint64_t tmp26 = tmp12 - tmp25;

   return tmp26;
}

/* Ext130 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE0 */
static uint64_t
acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read(UNUSED struct intel_perf_config *perf,
                                                             const struct intel_perf_query_info *query,
                                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD 16 B 4 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 2];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 3];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 4];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;

   return tmp12;
}

/* Ext131 :: GPU Time Elapsed */
#define acmgt1__ext131__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext131 :: GPU Core Clocks */
#define acmgt1__ext131__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext131 :: AVG GPU Core Frequency */
#define acmgt1__ext131__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext131 :: AVG GPU Core Frequency */
#define acmgt1__ext131__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext131 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1 */
#define acmgt1__ext131__early_depth_stencil_test_fail_np_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext131 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE1 */
#define acmgt1__ext131__early_depth_stencil_test_fail_p_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext132 :: GPU Time Elapsed */
#define acmgt1__ext132__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext132 :: GPU Core Clocks */
#define acmgt1__ext132__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext132 :: AVG GPU Core Frequency */
#define acmgt1__ext132__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext132 :: AVG GPU Core Frequency */
#define acmgt1__ext132__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext132 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2 */
#define acmgt1__ext132__early_depth_stencil_test_fail_np_zpipe2__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext132 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE2 */
#define acmgt1__ext132__early_depth_stencil_test_fail_p_zpipe2__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext133 :: GPU Time Elapsed */
#define acmgt1__ext133__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext133 :: GPU Core Clocks */
#define acmgt1__ext133__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext133 :: AVG GPU Core Frequency */
#define acmgt1__ext133__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext133 :: AVG GPU Core Frequency */
#define acmgt1__ext133__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext133 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3 */
#define acmgt1__ext133__early_depth_stencil_test_fail_np_zpipe3__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext133 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE3 */
#define acmgt1__ext133__early_depth_stencil_test_fail_p_zpipe3__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext134 :: GPU Time Elapsed */
#define acmgt1__ext134__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext134 :: GPU Core Clocks */
#define acmgt1__ext134__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext134 :: AVG GPU Core Frequency */
#define acmgt1__ext134__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext134 :: AVG GPU Core Frequency */
#define acmgt1__ext134__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext134 :: HIZ DEPTH TEST AMBIG NP ZPIPE0 */
static uint64_t
acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD 16 B 4 READ UMUL UADD 32 B 5 READ UMUL UADD 64 B 6 READ UMUL UADD 128 B 7 READ UMUL UADD 256 C 1 READ UMUL UADD 512 C 3 READ UMUL UADD 1024 C 5 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 2];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 3];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 4];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 5];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->b_offset + 6];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->b_offset + 7];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;
   uint64_t tmp22 = results->accumulator[query->c_offset + 1];
   uint64_t tmp23 = 256 * tmp22;
   uint64_t tmp24 = tmp21 + tmp23;
   uint64_t tmp25 = results->accumulator[query->c_offset + 3];
   uint64_t tmp26 = 512 * tmp25;
   uint64_t tmp27 = tmp24 + tmp26;
   uint64_t tmp28 = results->accumulator[query->c_offset + 5];
   uint64_t tmp29 = 1024 * tmp28;
   uint64_t tmp30 = tmp27 + tmp29;

   return tmp30;
}

/* Ext135 :: GPU Time Elapsed */
#define acmgt1__ext135__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext135 :: GPU Core Clocks */
#define acmgt1__ext135__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext135 :: AVG GPU Core Frequency */
#define acmgt1__ext135__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext135 :: AVG GPU Core Frequency */
#define acmgt1__ext135__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext135 :: HIZ DEPTH TEST AMBIG NP ZPIPE1 */
#define acmgt1__ext135__hiz_depth_test_ambig_np_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext136 :: GPU Time Elapsed */
#define acmgt1__ext136__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext136 :: GPU Core Clocks */
#define acmgt1__ext136__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext136 :: AVG GPU Core Frequency */
#define acmgt1__ext136__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext136 :: AVG GPU Core Frequency */
#define acmgt1__ext136__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext136 :: HIZ DEPTH TEST AMBIG NP ZPIPE2 */
#define acmgt1__ext136__hiz_depth_test_ambig_np_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext137 :: GPU Time Elapsed */
#define acmgt1__ext137__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext137 :: GPU Core Clocks */
#define acmgt1__ext137__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext137 :: AVG GPU Core Frequency */
#define acmgt1__ext137__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext137 :: AVG GPU Core Frequency */
#define acmgt1__ext137__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext137 :: HIZ DEPTH TEST AMBIG NP ZPIPE3 */
#define acmgt1__ext137__hiz_depth_test_ambig_np_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext138 :: GPU Time Elapsed */
#define acmgt1__ext138__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext138 :: GPU Core Clocks */
#define acmgt1__ext138__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext138 :: AVG GPU Core Frequency */
#define acmgt1__ext138__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext138 :: AVG GPU Core Frequency */
#define acmgt1__ext138__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext138 :: HIZ DEPTH TEST AMBIG P ZPIPE0 */
#define acmgt1__ext138__hiz_depth_test_ambig_p_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext139 :: GPU Time Elapsed */
#define acmgt1__ext139__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext139 :: GPU Core Clocks */
#define acmgt1__ext139__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext139 :: AVG GPU Core Frequency */
#define acmgt1__ext139__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext139 :: AVG GPU Core Frequency */
#define acmgt1__ext139__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext139 :: HIZ DEPTH TEST AMBIG P ZPIPE1 */
#define acmgt1__ext139__hiz_depth_test_ambig_p_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext140 :: GPU Time Elapsed */
#define acmgt1__ext140__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext140 :: GPU Core Clocks */
#define acmgt1__ext140__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext140 :: AVG GPU Core Frequency */
#define acmgt1__ext140__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext140 :: AVG GPU Core Frequency */
#define acmgt1__ext140__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext140 :: HIZ DEPTH TEST AMBIG P ZPIPE2 */
#define acmgt1__ext140__hiz_depth_test_ambig_p_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext141 :: GPU Time Elapsed */
#define acmgt1__ext141__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext141 :: GPU Core Clocks */
#define acmgt1__ext141__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext141 :: AVG GPU Core Frequency */
#define acmgt1__ext141__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext141 :: AVG GPU Core Frequency */
#define acmgt1__ext141__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext141 :: HIZ DEPTH TEST AMBIG P ZPIPE3 */
#define acmgt1__ext141__hiz_depth_test_ambig_p_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext142 :: GPU Time Elapsed */
#define acmgt1__ext142__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext142 :: GPU Core Clocks */
#define acmgt1__ext142__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext142 :: AVG GPU Core Frequency */
#define acmgt1__ext142__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext142 :: AVG GPU Core Frequency */
#define acmgt1__ext142__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext142 :: HIZ DEPTH TEST FAIL NP ZPIPE0 */
#define acmgt1__ext142__hiz_depth_test_fail_np_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext143 :: GPU Time Elapsed */
#define acmgt1__ext143__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext143 :: GPU Core Clocks */
#define acmgt1__ext143__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext143 :: AVG GPU Core Frequency */
#define acmgt1__ext143__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext143 :: AVG GPU Core Frequency */
#define acmgt1__ext143__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext143 :: HIZ DEPTH TEST FAIL NP ZPIPE1 */
#define acmgt1__ext143__hiz_depth_test_fail_np_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext144 :: GPU Time Elapsed */
#define acmgt1__ext144__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext144 :: GPU Core Clocks */
#define acmgt1__ext144__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext144 :: AVG GPU Core Frequency */
#define acmgt1__ext144__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext144 :: AVG GPU Core Frequency */
#define acmgt1__ext144__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext144 :: HIZ DEPTH TEST FAIL NP ZPIPE2 */
#define acmgt1__ext144__hiz_depth_test_fail_np_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext145 :: GPU Time Elapsed */
#define acmgt1__ext145__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext145 :: GPU Core Clocks */
#define acmgt1__ext145__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext145 :: AVG GPU Core Frequency */
#define acmgt1__ext145__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext145 :: AVG GPU Core Frequency */
#define acmgt1__ext145__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext145 :: HIZ DEPTH TEST FAIL NP ZPIPE3 */
#define acmgt1__ext145__hiz_depth_test_fail_np_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext146 :: GPU Time Elapsed */
#define acmgt1__ext146__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext146 :: GPU Core Clocks */
#define acmgt1__ext146__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext146 :: AVG GPU Core Frequency */
#define acmgt1__ext146__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext146 :: AVG GPU Core Frequency */
#define acmgt1__ext146__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext146 :: HIZ DEPTH TEST FAIL P ZPIPE0 */
#define acmgt1__ext146__hiz_depth_test_fail_p_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext147 :: GPU Time Elapsed */
#define acmgt1__ext147__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext147 :: GPU Core Clocks */
#define acmgt1__ext147__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext147 :: AVG GPU Core Frequency */
#define acmgt1__ext147__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext147 :: AVG GPU Core Frequency */
#define acmgt1__ext147__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext147 :: HIZ DEPTH TEST FAIL P ZPIPE1 */
#define acmgt1__ext147__hiz_depth_test_fail_p_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext148 :: GPU Time Elapsed */
#define acmgt1__ext148__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext148 :: GPU Core Clocks */
#define acmgt1__ext148__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext148 :: AVG GPU Core Frequency */
#define acmgt1__ext148__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext148 :: AVG GPU Core Frequency */
#define acmgt1__ext148__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext148 :: HIZ DEPTH TEST FAIL P ZPIPE2 */
#define acmgt1__ext148__hiz_depth_test_fail_p_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext149 :: GPU Time Elapsed */
#define acmgt1__ext149__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext149 :: GPU Core Clocks */
#define acmgt1__ext149__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext149 :: AVG GPU Core Frequency */
#define acmgt1__ext149__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext149 :: AVG GPU Core Frequency */
#define acmgt1__ext149__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext149 :: HIZ DEPTH TEST FAIL P ZPIPE3 */
#define acmgt1__ext149__hiz_depth_test_fail_p_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext150 :: GPU Time Elapsed */
#define acmgt1__ext150__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext150 :: GPU Core Clocks */
#define acmgt1__ext150__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext150 :: AVG GPU Core Frequency */
#define acmgt1__ext150__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext150 :: AVG GPU Core Frequency */
#define acmgt1__ext150__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext150 :: HIZ DEPTH TEST PASS P ZPIPE0 */
#define acmgt1__ext150__hiz_depth_test_pass_p_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext151 :: GPU Time Elapsed */
#define acmgt1__ext151__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext151 :: GPU Core Clocks */
#define acmgt1__ext151__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext151 :: AVG GPU Core Frequency */
#define acmgt1__ext151__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext151 :: AVG GPU Core Frequency */
#define acmgt1__ext151__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext151 :: HIZ DEPTH TEST PASS P ZPIPE1 */
#define acmgt1__ext151__hiz_depth_test_pass_p_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext152 :: GPU Time Elapsed */
#define acmgt1__ext152__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext152 :: GPU Core Clocks */
#define acmgt1__ext152__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext152 :: AVG GPU Core Frequency */
#define acmgt1__ext152__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext152 :: AVG GPU Core Frequency */
#define acmgt1__ext152__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext152 :: HIZ DEPTH TEST PASS P ZPIPE2 */
#define acmgt1__ext152__hiz_depth_test_pass_p_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext153 :: GPU Time Elapsed */
#define acmgt1__ext153__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext153 :: GPU Core Clocks */
#define acmgt1__ext153__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext153 :: AVG GPU Core Frequency */
#define acmgt1__ext153__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext153 :: AVG GPU Core Frequency */
#define acmgt1__ext153__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext153 :: HIZ DEPTH TEST PASS P ZPIPE3 */
#define acmgt1__ext153__hiz_depth_test_pass_p_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext154 :: GPU Time Elapsed */
#define acmgt1__ext154__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext154 :: GPU Core Clocks */
#define acmgt1__ext154__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext154 :: AVG GPU Core Frequency */
#define acmgt1__ext154__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext154 :: AVG GPU Core Frequency */
#define acmgt1__ext154__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2 */
#define acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3 */
#define acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define acmgt1__ext154__iz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define acmgt1__ext154__iz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE2 */
#define acmgt1__ext154__iz_subspan_latency_fifofull_zpipe2__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE3 */
#define acmgt1__ext154__iz_subspan_latency_fifofull_zpipe3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext154 :: IZ OUTPUT READY ZPIPE0 */
#define acmgt1__ext154__iz_output_ready_zpipe0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext154 :: IZ OUTPUT READY ZPIPE1 */
#define acmgt1__ext154__iz_output_ready_zpipe1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext154 :: IZ OUTPUT READY ZPIPE2 */
#define acmgt1__ext154__iz_output_ready_zpipe2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext154 :: IZ OUTPUT READY ZPIPE3 */
#define acmgt1__ext154__iz_output_ready_zpipe3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext155 :: GPU Time Elapsed */
#define acmgt1__ext155__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext155 :: GPU Core Clocks */
#define acmgt1__ext155__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext155 :: AVG GPU Core Frequency */
#define acmgt1__ext155__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext155 :: AVG GPU Core Frequency */
#define acmgt1__ext155__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext155 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS0 */
#define acmgt1__ext155__command_parser_compute_engine_busy_ccs0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext155 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS1 */
#define acmgt1__ext155__command_parser_compute_engine_busy_ccs1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext155 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS2 */
#define acmgt1__ext155__command_parser_compute_engine_busy_ccs2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext155 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS3 */
#define acmgt1__ext155__command_parser_compute_engine_busy_ccs3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext155 :: COMMAND PARSER RENDER ENGINE BUSY */
#define acmgt1__ext155__command_parser_render_engine_busy__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext156 :: GPU Time Elapsed */
#define acmgt1__ext156__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext156 :: GPU Core Clocks */
#define acmgt1__ext156__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext156 :: AVG GPU Core Frequency */
#define acmgt1__ext156__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext156 :: AVG GPU Core Frequency */
#define acmgt1__ext156__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext156 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0 */
#define acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext156 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS1 */
#define acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext156 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS2 */
#define acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext156 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS3 */
#define acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext156 :: COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT */
#define acmgt1__ext156__command_parser_render_engine_dispatch_kernel_count__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext156 :: COMMAND PARSER RENDER ENGINE DRAW COUNT */
#define acmgt1__ext156__command_parser_render_engine_draw_count__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext156 :: COMMAND PARSER FLUSH COUNT */
#define acmgt1__ext156__command_parser_flush_count__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext157 :: GPU Time Elapsed */
#define acmgt1__ext157__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext157 :: GPU Core Clocks */
#define acmgt1__ext157__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext157 :: AVG GPU Core Frequency */
#define acmgt1__ext157__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext157 :: AVG GPU Core Frequency */
#define acmgt1__ext157__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext157 :: COMMAND PARSER COPY ENGINE BUSY */
#define acmgt1__ext157__command_parser_copy_engine_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Ext157 :: COMMAND PARSER VIDEO ENGINE BUSY VDBOX0 */
#define acmgt1__ext157__command_parser_video_engine_busy_vdbox0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext157 :: COMMAND PARSER VIDEO ENGINE BUSY VDBOX1 */
#define acmgt1__ext157__command_parser_video_engine_busy_vdbox1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext157 :: COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX0 */
#define acmgt1__ext157__command_parser_video_enhancement_engine_busy_vebox0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext157 :: COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX1 */
#define acmgt1__ext157__command_parser_video_enhancement_engine_busy_vebox1__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext158 :: GPU Time Elapsed */
#define acmgt1__ext158__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext158 :: GPU Core Clocks */
#define acmgt1__ext158__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext158 :: AVG GPU Core Frequency */
#define acmgt1__ext158__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext158 :: AVG GPU Core Frequency */
#define acmgt1__ext158__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE0 */
#define acmgt1__ext158__rt_input_message_ray_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE1 */
#define acmgt1__ext158__rt_input_message_ray_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE2 */
#define acmgt1__ext158__rt_input_message_ray_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE3 */
#define acmgt1__ext158__rt_input_message_ray_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE4 */
#define acmgt1__ext158__rt_input_message_ray_count_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE5 */
#define acmgt1__ext158__rt_input_message_ray_count_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE6 */
#define acmgt1__ext158__rt_input_message_ray_count_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE7 */
#define acmgt1__ext158__rt_input_message_ray_count_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext158 :: RT TRAVERSAL INPUT RAY COUNT XECORE0 */
#define acmgt1__ext158__rt_traversal_input_ray_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext158 :: RT TRAVERSAL INPUT RAY COUNT XECORE1 */
#define acmgt1__ext158__rt_traversal_input_ray_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext158 :: RT TRAVERSAL INPUT RAY COUNT XECORE2 */
#define acmgt1__ext158__rt_traversal_input_ray_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext158 :: RT TRAVERSAL INPUT RAY COUNT XECORE3 */
#define acmgt1__ext158__rt_traversal_input_ray_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext158 :: RT TRAVERSAL INPUT RAY COUNT XECORE4 */
#define acmgt1__ext158__rt_traversal_input_ray_count_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext158 :: RT TRAVERSAL INPUT RAY COUNT XECORE5 */
#define acmgt1__ext158__rt_traversal_input_ray_count_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext158 :: RT TRAVERSAL INPUT RAY COUNT XECORE6 */
#define acmgt1__ext158__rt_traversal_input_ray_count_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext158 :: RT TRAVERSAL INPUT RAY COUNT XECORE7 */
#define acmgt1__ext158__rt_traversal_input_ray_count_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext159 :: GPU Time Elapsed */
#define acmgt1__ext159__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext159 :: GPU Core Clocks */
#define acmgt1__ext159__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext159 :: AVG GPU Core Frequency */
#define acmgt1__ext159__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext159 :: AVG GPU Core Frequency */
#define acmgt1__ext159__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE0 */
static uint64_t
acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE1 */
#define acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE2 */
#define acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE3 */
static uint64_t
acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read(UNUSED struct intel_perf_config *perf,
                                                                 const struct intel_perf_query_info *query,
                                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ B 7 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext160 :: GPU Time Elapsed */
#define acmgt1__ext160__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext160 :: GPU Core Clocks */
#define acmgt1__ext160__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext160 :: AVG GPU Core Frequency */
#define acmgt1__ext160__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext160 :: AVG GPU Core Frequency */
#define acmgt1__ext160__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext160 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE4 */
#define acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext160 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE5 */
#define acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext160 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE6 */
#define acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext160 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE7 */
#define acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext161 :: GPU Time Elapsed */
#define acmgt1__ext161__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext161 :: GPU Core Clocks */
#define acmgt1__ext161__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext161 :: AVG GPU Core Frequency */
#define acmgt1__ext161__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext161 :: AVG GPU Core Frequency */
#define acmgt1__ext161__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE0 */
#define acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE1 */
#define acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE2 */
#define acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE3 */
#define acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext162 :: GPU Time Elapsed */
#define acmgt1__ext162__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext162 :: GPU Core Clocks */
#define acmgt1__ext162__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext162 :: AVG GPU Core Frequency */
#define acmgt1__ext162__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext162 :: AVG GPU Core Frequency */
#define acmgt1__ext162__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext162 :: RT MISS THREAD RAY DISPATCH XECORE4 */
#define acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext162 :: RT MISS THREAD RAY DISPATCH XECORE5 */
#define acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext162 :: RT MISS THREAD RAY DISPATCH XECORE6 */
#define acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext162 :: RT MISS THREAD RAY DISPATCH XECORE7 */
#define acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext163 :: GPU Time Elapsed */
#define acmgt1__ext163__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext163 :: GPU Core Clocks */
#define acmgt1__ext163__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext163 :: AVG GPU Core Frequency */
#define acmgt1__ext163__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext163 :: AVG GPU Core Frequency */
#define acmgt1__ext163__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE0 */
#define acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE1 */
#define acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE2 */
#define acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE3 */
#define acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext164 :: GPU Time Elapsed */
#define acmgt1__ext164__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext164 :: GPU Core Clocks */
#define acmgt1__ext164__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext164 :: AVG GPU Core Frequency */
#define acmgt1__ext164__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext164 :: AVG GPU Core Frequency */
#define acmgt1__ext164__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext164 :: RT ANY HIT THREAD RAY DISPATCH XECORE4 */
#define acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext164 :: RT ANY HIT THREAD RAY DISPATCH XECORE5 */
#define acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext164 :: RT ANY HIT THREAD RAY DISPATCH XECORE6 */
#define acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext164 :: RT ANY HIT THREAD RAY DISPATCH XECORE7 */
#define acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext165 :: GPU Time Elapsed */
#define acmgt1__ext165__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext165 :: GPU Core Clocks */
#define acmgt1__ext165__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext165 :: AVG GPU Core Frequency */
#define acmgt1__ext165__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext165 :: AVG GPU Core Frequency */
#define acmgt1__ext165__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE0 */
#define acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE1 */
#define acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE2 */
#define acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE3 */
#define acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext166 :: GPU Time Elapsed */
#define acmgt1__ext166__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext166 :: GPU Core Clocks */
#define acmgt1__ext166__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext166 :: AVG GPU Core Frequency */
#define acmgt1__ext166__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext166 :: AVG GPU Core Frequency */
#define acmgt1__ext166__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext166 :: RT INTERSECTION THREAD RAY DISPATCH XECORE4 */
#define acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext166 :: RT INTERSECTION THREAD RAY DISPATCH XECORE5 */
#define acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext166 :: RT INTERSECTION THREAD RAY DISPATCH XECORE6 */
#define acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext166 :: RT INTERSECTION THREAD RAY DISPATCH XECORE7 */
#define acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext167 :: GPU Time Elapsed */
#define acmgt1__ext167__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext167 :: GPU Core Clocks */
#define acmgt1__ext167__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext167 :: AVG GPU Core Frequency */
#define acmgt1__ext167__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext167 :: AVG GPU Core Frequency */
#define acmgt1__ext167__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE0 */
#define acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE1 */
#define acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE2 */
#define acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE3 */
#define acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext168 :: GPU Time Elapsed */
#define acmgt1__ext168__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext168 :: GPU Core Clocks */
#define acmgt1__ext168__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext168 :: AVG GPU Core Frequency */
#define acmgt1__ext168__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext168 :: AVG GPU Core Frequency */
#define acmgt1__ext168__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext168 :: RT CALLABLE THREAD RAY DISPATCH XECORE4 */
#define acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext168 :: RT CALLABLE THREAD RAY DISPATCH XECORE5 */
#define acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext168 :: RT CALLABLE THREAD RAY DISPATCH XECORE6 */
#define acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext168 :: RT CALLABLE THREAD RAY DISPATCH XECORE7 */
#define acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext169 :: GPU Time Elapsed */
#define acmgt1__ext169__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext169 :: GPU Core Clocks */
#define acmgt1__ext169__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext169 :: AVG GPU Core Frequency */
#define acmgt1__ext169__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext169 :: AVG GPU Core Frequency */
#define acmgt1__ext169__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE0 */
#define acmgt1__ext169__rt_traversal_output_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE1 */
#define acmgt1__ext169__rt_traversal_output_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE2 */
#define acmgt1__ext169__rt_traversal_output_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE3 */
#define acmgt1__ext169__rt_traversal_output_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext170 :: GPU Time Elapsed */
#define acmgt1__ext170__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext170 :: GPU Core Clocks */
#define acmgt1__ext170__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext170 :: AVG GPU Core Frequency */
#define acmgt1__ext170__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext170 :: AVG GPU Core Frequency */
#define acmgt1__ext170__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext170 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE4 */
#define acmgt1__ext170__rt_traversal_output_ray_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext170 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE5 */
#define acmgt1__ext170__rt_traversal_output_ray_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext170 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE6 */
#define acmgt1__ext170__rt_traversal_output_ray_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext170 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE7 */
#define acmgt1__ext170__rt_traversal_output_ray_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext171 :: GPU Time Elapsed */
#define acmgt1__ext171__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext171 :: GPU Core Clocks */
#define acmgt1__ext171__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext171 :: AVG GPU Core Frequency */
#define acmgt1__ext171__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext171 :: AVG GPU Core Frequency */
#define acmgt1__ext171__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE0 */
#define acmgt1__ext171__rt_quad_test_ray_count_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE1 */
#define acmgt1__ext171__rt_quad_test_ray_count_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE2 */
#define acmgt1__ext171__rt_quad_test_ray_count_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE3 */
#define acmgt1__ext171__rt_quad_test_ray_count_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE4 */
#define acmgt1__ext171__rt_quad_test_ray_count_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE5 */
#define acmgt1__ext171__rt_quad_test_ray_count_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE6 */
#define acmgt1__ext171__rt_quad_test_ray_count_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE7 */
#define acmgt1__ext171__rt_quad_test_ray_count_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE0 */
#define acmgt1__ext171__rt_transform_ray_count_xecore0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE1 */
#define acmgt1__ext171__rt_transform_ray_count_xecore1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE2 */
#define acmgt1__ext171__rt_transform_ray_count_xecore2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE3 */
#define acmgt1__ext171__rt_transform_ray_count_xecore3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE4 */
#define acmgt1__ext171__rt_transform_ray_count_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE5 */
#define acmgt1__ext171__rt_transform_ray_count_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE6 */
#define acmgt1__ext171__rt_transform_ray_count_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE7 */
#define acmgt1__ext171__rt_transform_ray_count_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext172 :: GPU Time Elapsed */
#define acmgt1__ext172__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext172 :: GPU Core Clocks */
#define acmgt1__ext172__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext172 :: AVG GPU Core Frequency */
#define acmgt1__ext172__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext172 :: AVG GPU Core Frequency */
#define acmgt1__ext172__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext172 :: RT MESSAGE STALL COUNT XECORE0 */
#define acmgt1__ext172__rt_message_stall_count_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE1 */
#define acmgt1__ext172__rt_message_stall_count_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE2 */
#define acmgt1__ext172__rt_message_stall_count_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE3 */
#define acmgt1__ext172__rt_message_stall_count_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE4 */
#define acmgt1__ext172__rt_message_stall_count_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE5 */
#define acmgt1__ext172__rt_message_stall_count_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE6 */
#define acmgt1__ext172__rt_message_stall_count_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE7 */
#define acmgt1__ext172__rt_message_stall_count_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext172 :: RT REQUEST COLLISION XECORE0 */
#define acmgt1__ext172__rt_request_collision_xecore0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext172 :: RT REQUEST COLLISION XECORE1 */
#define acmgt1__ext172__rt_request_collision_xecore1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext172 :: RT REQUEST COLLISION XECORE2 */
#define acmgt1__ext172__rt_request_collision_xecore2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext172 :: RT REQUEST COLLISION XECORE3 */
#define acmgt1__ext172__rt_request_collision_xecore3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext172 :: RT REQUEST COLLISION XECORE4 */
#define acmgt1__ext172__rt_request_collision_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext172 :: RT REQUEST COLLISION XECORE5 */
#define acmgt1__ext172__rt_request_collision_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext172 :: RT REQUEST COLLISION XECORE6 */
#define acmgt1__ext172__rt_request_collision_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext172 :: RT REQUEST COLLISION XECORE7 */
#define acmgt1__ext172__rt_request_collision_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext173 :: GPU Time Elapsed */
#define acmgt1__ext173__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext173 :: GPU Core Clocks */
#define acmgt1__ext173__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext173 :: AVG GPU Core Frequency */
#define acmgt1__ext173__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext173 :: AVG GPU Core Frequency */
#define acmgt1__ext173__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext173 :: XVE STALL ALUWR XECORE0 XVE0 THREAD0 */
#define acmgt1__ext173__xve_stall_aluwr_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext173 :: XVE STALL BARRIER XECORE0 XVE0 THREAD0 */
#define acmgt1__ext173__xve_stall_barrier_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext173 :: XVE STALL INSTFETCH XECORE0 XVE0 THREAD0 */
#define acmgt1__ext173__xve_stall_instfetch_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext173 :: XVE STALL OTHER XECORE0 XVE0 THREAD0 */
#define acmgt1__ext173__xve_stall_other_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext173 :: XVE STALL SBID XECORE0 XVE0 THREAD0 */
#define acmgt1__ext173__xve_stall_sbid_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext173 :: XVE STALL SENDWR XECORE0 XVE0 THREAD0 */
#define acmgt1__ext173__xve_stall_sendwr_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext173 :: XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0 */
#define acmgt1__ext173__xve_shared_function_access_hold_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext174 :: GPU Time Elapsed */
#define acmgt1__ext174__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext174 :: GPU Core Clocks */
#define acmgt1__ext174__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext174 :: AVG GPU Core Frequency */
#define acmgt1__ext174__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext174 :: AVG GPU Core Frequency */
#define acmgt1__ext174__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext174 :: XVE STALL ALUWR XECORE1 XVE0 THREAD0 */
#define acmgt1__ext174__xve_stall_aluwr_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext174 :: XVE STALL BARRIER XECORE1 XVE0 THREAD0 */
#define acmgt1__ext174__xve_stall_barrier_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext174 :: XVE STALL INSTFETCH XECORE1 XVE0 THREAD0 */
#define acmgt1__ext174__xve_stall_instfetch_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext174 :: XVE STALL OTHER XECORE1 XVE0 THREAD0 */
#define acmgt1__ext174__xve_stall_other_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext174 :: XVE STALL SBID XECORE1 XVE0 THREAD0 */
#define acmgt1__ext174__xve_stall_sbid_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext174 :: XVE STALL SENDWR XECORE1 XVE0 THREAD0 */
#define acmgt1__ext174__xve_stall_sendwr_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext174 :: XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0 */
#define acmgt1__ext174__xve_shared_function_access_hold_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext175 :: GPU Time Elapsed */
#define acmgt1__ext175__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext175 :: GPU Core Clocks */
#define acmgt1__ext175__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext175 :: AVG GPU Core Frequency */
#define acmgt1__ext175__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext175 :: AVG GPU Core Frequency */
#define acmgt1__ext175__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext175 :: XVE STALL ALUWR XECORE2 XVE0 THREAD0 */
#define acmgt1__ext175__xve_stall_aluwr_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext175 :: XVE STALL BARRIER XECORE2 XVE0 THREAD0 */
#define acmgt1__ext175__xve_stall_barrier_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext175 :: XVE STALL INSTFETCH XECORE2 XVE0 THREAD0 */
#define acmgt1__ext175__xve_stall_instfetch_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext175 :: XVE STALL OTHER XECORE2 XVE0 THREAD0 */
#define acmgt1__ext175__xve_stall_other_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext175 :: XVE STALL SBID XECORE2 XVE0 THREAD0 */
#define acmgt1__ext175__xve_stall_sbid_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext175 :: XVE STALL SENDWR XECORE2 XVE0 THREAD0 */
#define acmgt1__ext175__xve_stall_sendwr_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext175 :: XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0 */
#define acmgt1__ext175__xve_shared_function_access_hold_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext176 :: GPU Time Elapsed */
#define acmgt1__ext176__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext176 :: GPU Core Clocks */
#define acmgt1__ext176__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext176 :: AVG GPU Core Frequency */
#define acmgt1__ext176__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext176 :: AVG GPU Core Frequency */
#define acmgt1__ext176__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext176 :: XVE STALL ALUWR XECORE3 XVE0 THREAD0 */
#define acmgt1__ext176__xve_stall_aluwr_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext176 :: XVE STALL BARRIER XECORE3 XVE0 THREAD0 */
#define acmgt1__ext176__xve_stall_barrier_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext176 :: XVE STALL INSTFETCH XECORE3 XVE0 THREAD0 */
#define acmgt1__ext176__xve_stall_instfetch_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext176 :: XVE STALL OTHER XECORE3 XVE0 THREAD0 */
#define acmgt1__ext176__xve_stall_other_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext176 :: XVE STALL SBID XECORE3 XVE0 THREAD0 */
#define acmgt1__ext176__xve_stall_sbid_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext176 :: XVE STALL SENDWR XECORE3 XVE0 THREAD0 */
#define acmgt1__ext176__xve_stall_sendwr_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext176 :: XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0 */
#define acmgt1__ext176__xve_shared_function_access_hold_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext177 :: GPU Time Elapsed */
#define acmgt1__ext177__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext177 :: GPU Core Clocks */
#define acmgt1__ext177__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext177 :: AVG GPU Core Frequency */
#define acmgt1__ext177__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext177 :: AVG GPU Core Frequency */
#define acmgt1__ext177__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext177 :: XVE STALL ALUWR XECORE4 XVE0 THREAD0 */
#define acmgt1__ext177__xve_stall_aluwr_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext177 :: XVE STALL BARRIER XECORE4 XVE0 THREAD0 */
#define acmgt1__ext177__xve_stall_barrier_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext177 :: XVE STALL INSTFETCH XECORE4 XVE0 THREAD0 */
#define acmgt1__ext177__xve_stall_instfetch_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext177 :: XVE STALL OTHER XECORE4 XVE0 THREAD0 */
#define acmgt1__ext177__xve_stall_other_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext177 :: XVE STALL SBID XECORE4 XVE0 THREAD0 */
#define acmgt1__ext177__xve_stall_sbid_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext177 :: XVE STALL SENDWR XECORE4 XVE0 THREAD0 */
#define acmgt1__ext177__xve_stall_sendwr_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext177 :: XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0 */
#define acmgt1__ext177__xve_shared_function_access_hold_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext178 :: GPU Time Elapsed */
#define acmgt1__ext178__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext178 :: GPU Core Clocks */
#define acmgt1__ext178__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext178 :: AVG GPU Core Frequency */
#define acmgt1__ext178__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext178 :: AVG GPU Core Frequency */
#define acmgt1__ext178__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext178 :: XVE STALL ALUWR XECORE5 XVE0 THREAD0 */
#define acmgt1__ext178__xve_stall_aluwr_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext178 :: XVE STALL BARRIER XECORE5 XVE0 THREAD0 */
#define acmgt1__ext178__xve_stall_barrier_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext178 :: XVE STALL INSTFETCH XECORE5 XVE0 THREAD0 */
#define acmgt1__ext178__xve_stall_instfetch_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext178 :: XVE STALL OTHER XECORE5 XVE0 THREAD0 */
#define acmgt1__ext178__xve_stall_other_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext178 :: XVE STALL SBID XECORE5 XVE0 THREAD0 */
#define acmgt1__ext178__xve_stall_sbid_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext178 :: XVE STALL SENDWR XECORE5 XVE0 THREAD0 */
#define acmgt1__ext178__xve_stall_sendwr_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext178 :: XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0 */
#define acmgt1__ext178__xve_shared_function_access_hold_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext179 :: GPU Time Elapsed */
#define acmgt1__ext179__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext179 :: GPU Core Clocks */
#define acmgt1__ext179__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext179 :: AVG GPU Core Frequency */
#define acmgt1__ext179__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext179 :: AVG GPU Core Frequency */
#define acmgt1__ext179__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext179 :: XVE STALL ALUWR XECORE6 XVE0 THREAD0 */
#define acmgt1__ext179__xve_stall_aluwr_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext179 :: XVE STALL BARRIER XECORE6 XVE0 THREAD0 */
#define acmgt1__ext179__xve_stall_barrier_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext179 :: XVE STALL INSTFETCH XECORE6 XVE0 THREAD0 */
#define acmgt1__ext179__xve_stall_instfetch_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext179 :: XVE STALL OTHER XECORE6 XVE0 THREAD0 */
#define acmgt1__ext179__xve_stall_other_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext179 :: XVE STALL SBID XECORE6 XVE0 THREAD0 */
#define acmgt1__ext179__xve_stall_sbid_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext179 :: XVE STALL SENDWR XECORE6 XVE0 THREAD0 */
#define acmgt1__ext179__xve_stall_sendwr_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext179 :: XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0 */
#define acmgt1__ext179__xve_shared_function_access_hold_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext180 :: GPU Time Elapsed */
#define acmgt1__ext180__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext180 :: GPU Core Clocks */
#define acmgt1__ext180__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext180 :: AVG GPU Core Frequency */
#define acmgt1__ext180__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext180 :: AVG GPU Core Frequency */
#define acmgt1__ext180__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext180 :: XVE STALL ALUWR XECORE7 XVE0 THREAD0 */
#define acmgt1__ext180__xve_stall_aluwr_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext180 :: XVE STALL BARRIER XECORE7 XVE0 THREAD0 */
#define acmgt1__ext180__xve_stall_barrier_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext180 :: XVE STALL INSTFETCH XECORE7 XVE0 THREAD0 */
#define acmgt1__ext180__xve_stall_instfetch_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext180 :: XVE STALL OTHER XECORE7 XVE0 THREAD0 */
#define acmgt1__ext180__xve_stall_other_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext180 :: XVE STALL SBID XECORE7 XVE0 THREAD0 */
#define acmgt1__ext180__xve_stall_sbid_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext180 :: XVE STALL SENDWR XECORE7 XVE0 THREAD0 */
#define acmgt1__ext180__xve_stall_sendwr_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext180 :: XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0 */
#define acmgt1__ext180__xve_shared_function_access_hold_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext181 :: GPU Time Elapsed */
#define acmgt1__ext181__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext181 :: GPU Core Clocks */
#define acmgt1__ext181__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext181 :: AVG GPU Core Frequency */
#define acmgt1__ext181__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext181 :: AVG GPU Core Frequency */
#define acmgt1__ext181__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext181 :: XVE INST ISSUED ALL XECORE0 XVE0 */
#define acmgt1__ext181__xve_inst_issued_all_xecore0_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext181 :: XVE INST ISSUED ALL XECORE1 XVE0 */
#define acmgt1__ext181__xve_inst_issued_all_xecore1_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext181 :: XVE INST ISSUED ALL XECORE2 XVE0 */
#define acmgt1__ext181__xve_inst_issued_all_xecore2_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext182 :: GPU Time Elapsed */
#define acmgt1__ext182__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext182 :: GPU Core Clocks */
#define acmgt1__ext182__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext182 :: AVG GPU Core Frequency */
#define acmgt1__ext182__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext182 :: AVG GPU Core Frequency */
#define acmgt1__ext182__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext182 :: XVE INST ISSUED ALL XECORE3 XVE0 */
#define acmgt1__ext182__xve_inst_issued_all_xecore3_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext182 :: XVE INST ISSUED ALL XECORE4 XVE0 */
#define acmgt1__ext182__xve_inst_issued_all_xecore4_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext182 :: XVE INST ISSUED ALL XECORE5 XVE0 */
#define acmgt1__ext182__xve_inst_issued_all_xecore5_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext183 :: GPU Time Elapsed */
#define acmgt1__ext183__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext183 :: GPU Core Clocks */
#define acmgt1__ext183__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext183 :: AVG GPU Core Frequency */
#define acmgt1__ext183__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext183 :: AVG GPU Core Frequency */
#define acmgt1__ext183__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext183 :: XVE INST ISSUED ALL XECORE6 XVE0 */
#define acmgt1__ext183__xve_inst_issued_all_xecore6_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext183 :: XVE INST ISSUED ALL XECORE7 XVE0 */
#define acmgt1__ext183__xve_inst_issued_all_xecore7_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext183 :: RENDER CACHE ALLOC L3NODE0 */
#define acmgt1__ext183__render_cache_alloc_l3_node0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext183 :: RENDER CACHE ALLOC L3NODE1 */
#define acmgt1__ext183__render_cache_alloc_l3_node1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext184 :: GPU Time Elapsed */
#define acmgt1__ext184__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext184 :: GPU Core Clocks */
#define acmgt1__ext184__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext184 :: AVG GPU Core Frequency */
#define acmgt1__ext184__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext184 :: AVG GPU Core Frequency */
#define acmgt1__ext184__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext184 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define acmgt1__ext184__rt_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext184 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define acmgt1__ext184__rt_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext185 :: GPU Time Elapsed */
#define acmgt1__ext185__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext185 :: GPU Core Clocks */
#define acmgt1__ext185__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext185 :: AVG GPU Core Frequency */
#define acmgt1__ext185__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext185 :: AVG GPU Core Frequency */
#define acmgt1__ext185__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext185 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define acmgt1__ext185__rt_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext185 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define acmgt1__ext185__rt_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext186 :: GPU Time Elapsed */
#define acmgt1__ext186__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext186 :: GPU Core Clocks */
#define acmgt1__ext186__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext186 :: AVG GPU Core Frequency */
#define acmgt1__ext186__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext186 :: AVG GPU Core Frequency */
#define acmgt1__ext186__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext186 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4 */
#define acmgt1__ext186__rt_load_store_cache_read_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext186 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5 */
#define acmgt1__ext186__rt_load_store_cache_read_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext187 :: GPU Time Elapsed */
#define acmgt1__ext187__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext187 :: GPU Core Clocks */
#define acmgt1__ext187__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext187 :: AVG GPU Core Frequency */
#define acmgt1__ext187__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext187 :: AVG GPU Core Frequency */
#define acmgt1__ext187__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext187 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6 */
#define acmgt1__ext187__rt_load_store_cache_read_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext187 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7 */
#define acmgt1__ext187__rt_load_store_cache_read_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext188 :: GPU Time Elapsed */
#define acmgt1__ext188__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext188 :: GPU Core Clocks */
#define acmgt1__ext188__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext188 :: AVG GPU Core Frequency */
#define acmgt1__ext188__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext188 :: AVG GPU Core Frequency */
#define acmgt1__ext188__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0 */
#define acmgt1__ext188__rt_load_store_cache_write_from_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1 */
#define acmgt1__ext188__rt_load_store_cache_write_from_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext189 :: GPU Time Elapsed */
#define acmgt1__ext189__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext189 :: GPU Core Clocks */
#define acmgt1__ext189__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext189 :: AVG GPU Core Frequency */
#define acmgt1__ext189__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext189 :: AVG GPU Core Frequency */
#define acmgt1__ext189__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext189 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2 */
#define acmgt1__ext189__rt_load_store_cache_write_from_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext189 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3 */
#define acmgt1__ext189__rt_load_store_cache_write_from_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext190 :: GPU Time Elapsed */
#define acmgt1__ext190__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext190 :: GPU Core Clocks */
#define acmgt1__ext190__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext190 :: AVG GPU Core Frequency */
#define acmgt1__ext190__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext190 :: AVG GPU Core Frequency */
#define acmgt1__ext190__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext190 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4 */
#define acmgt1__ext190__rt_load_store_cache_write_from_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext190 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5 */
#define acmgt1__ext190__rt_load_store_cache_write_from_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext191 :: GPU Time Elapsed */
#define acmgt1__ext191__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext191 :: GPU Core Clocks */
#define acmgt1__ext191__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext191 :: AVG GPU Core Frequency */
#define acmgt1__ext191__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext191 :: AVG GPU Core Frequency */
#define acmgt1__ext191__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext191 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6 */
#define acmgt1__ext191__rt_load_store_cache_write_from_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext191 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7 */
#define acmgt1__ext191__rt_load_store_cache_write_from_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext192 :: GPU Time Elapsed */
#define acmgt1__ext192__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext192 :: GPU Core Clocks */
#define acmgt1__ext192__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext192 :: AVG GPU Core Frequency */
#define acmgt1__ext192__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext192 :: AVG GPU Core Frequency */
#define acmgt1__ext192__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext192 :: RT INPUT AVAILABLE XECORE0 */
#define acmgt1__ext192__rt_input_available_xecore0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext192 :: RT INPUT AVAILABLE XECORE1 */
#define acmgt1__ext192__rt_input_available_xecore1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext192 :: RT INPUT AVAILABLE XECORE2 */
#define acmgt1__ext192__rt_input_available_xecore2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext192 :: RT INPUT AVAILABLE XECORE3 */
#define acmgt1__ext192__rt_input_available_xecore3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext192 :: RT INPUT AVAILABLE XECORE4 */
#define acmgt1__ext192__rt_input_available_xecore4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext192 :: RT INPUT AVAILABLE XECORE5 */
#define acmgt1__ext192__rt_input_available_xecore5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext192 :: RT INPUT AVAILABLE XECORE6 */
#define acmgt1__ext192__rt_input_available_xecore6__read \
   bdw__render_basic__sampler1_busy__read

/* Ext192 :: RT INPUT AVAILABLE XECORE7 */
#define acmgt1__ext192__rt_input_available_xecore7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext193 :: GPU Time Elapsed */
#define acmgt1__ext193__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext193 :: GPU Core Clocks */
#define acmgt1__ext193__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext193 :: AVG GPU Core Frequency */
#define acmgt1__ext193__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext193 :: AVG GPU Core Frequency */
#define acmgt1__ext193__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext193 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE0 */
#define acmgt1__ext193__pixel_post_process_input_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext193 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE1 */
#define acmgt1__ext193__pixel_post_process_input_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext194 :: GPU Time Elapsed */
#define acmgt1__ext194__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext194 :: GPU Core Clocks */
#define acmgt1__ext194__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext194 :: AVG GPU Core Frequency */
#define acmgt1__ext194__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext194 :: AVG GPU Core Frequency */
#define acmgt1__ext194__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext194 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE2 */
#define acmgt1__ext194__pixel_post_process_input_available_cpipe2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext194 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE3 */
#define acmgt1__ext194__pixel_post_process_input_available_cpipe3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext195 :: GPU Time Elapsed */
#define acmgt1__ext195__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext195 :: GPU Core Clocks */
#define acmgt1__ext195__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext195 :: AVG GPU Core Frequency */
#define acmgt1__ext195__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext195 :: AVG GPU Core Frequency */
#define acmgt1__ext195__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0 */
static float
acmgt1__ext195__xve_multiple_pipe_active_xecore0_xve0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ B 5 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = acmgt1__ext195__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0 */
static float
acmgt1__ext195__xve_multiple_pipe_active_xecore1_xve0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ B 4 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = acmgt1__ext195__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0 */
static float
acmgt1__ext195__xve_multiple_pipe_active_xecore2_xve0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ B 7 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = acmgt1__ext195__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0 */
static float
acmgt1__ext195__xve_multiple_pipe_active_xecore3_xve0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 6 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = acmgt1__ext195__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Ext196 :: GPU Time Elapsed */
#define acmgt1__ext196__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext196 :: GPU Core Clocks */
#define acmgt1__ext196__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext196 :: AVG GPU Core Frequency */
#define acmgt1__ext196__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext196 :: AVG GPU Core Frequency */
#define acmgt1__ext196__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext196 :: XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0 */
static float
acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ B 7 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = acmgt1__ext196__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Ext196 :: XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0 */
static float
acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ B 6 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = acmgt1__ext196__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Ext196 :: XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0 */
static float
acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ B 5 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = acmgt1__ext196__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Ext196 :: XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0 */
static float
acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 4 READ USUB 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   uint64_t tmp2 = tmp0 - tmp1;
   uint64_t tmp3 = tmp2 * 100;
   double tmp4 = tmp3;
   double tmp5 = acmgt1__ext196__gpu_core_clocks__read(perf, query, results);
   double tmp6 = tmp5 ? tmp4 / tmp5 : 0;

   return tmp6;
}

/* Ext197 :: GPU Time Elapsed */
#define acmgt1__ext197__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext197 :: GPU Core Clocks */
#define acmgt1__ext197__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext197 :: AVG GPU Core Frequency */
#define acmgt1__ext197__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext197 :: AVG GPU Core Frequency */
#define acmgt1__ext197__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext197 :: GPGPU DISPATCH XECORE0 */
#define acmgt1__ext197__gpgpu_dispatch_xecore0__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext197 :: GPGPU DISPATCH XECORE1 */
#define acmgt1__ext197__gpgpu_dispatch_xecore1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext197 :: GPGPU DISPATCH XECORE2 */
#define acmgt1__ext197__gpgpu_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext198 :: GPU Time Elapsed */
#define acmgt1__ext198__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext198 :: GPU Core Clocks */
#define acmgt1__ext198__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext198 :: AVG GPU Core Frequency */
#define acmgt1__ext198__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext198 :: AVG GPU Core Frequency */
#define acmgt1__ext198__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext198 :: GPGPU DISPATCH XECORE3 */
#define acmgt1__ext198__gpgpu_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext198 :: GPGPU DISPATCH XECORE4 */
#define acmgt1__ext198__gpgpu_dispatch_xecore4__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext198 :: GPGPU DISPATCH XECORE5 */
#define acmgt1__ext198__gpgpu_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext199 :: GPU Time Elapsed */
#define acmgt1__ext199__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext199 :: GPU Core Clocks */
#define acmgt1__ext199__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext199 :: AVG GPU Core Frequency */
#define acmgt1__ext199__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext199 :: AVG GPU Core Frequency */
#define acmgt1__ext199__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext199 :: GPGPU DISPATCH XECORE6 */
#define acmgt1__ext199__gpgpu_dispatch_xecore6__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext199 :: GPGPU DISPATCH XECORE7 */
#define acmgt1__ext199__gpgpu_dispatch_xecore7__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext200 :: GPU Time Elapsed */
#define acmgt1__ext200__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext200 :: GPU Core Clocks */
#define acmgt1__ext200__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext200 :: AVG GPU Core Frequency */
#define acmgt1__ext200__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext200 :: AVG GPU Core Frequency */
#define acmgt1__ext200__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext200 :: SLM ACCESS COUNT XECORE2 */
#define acmgt1__ext200__slm_access_count_xecore2__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext200 :: SLM ACCESS COUNT XECORE1 */
#define acmgt1__ext200__slm_access_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext200 :: SLM ACCESS COUNT XECORE0 */
#define acmgt1__ext200__slm_access_count_xecore0__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext200 :: SLM ACCESS COUNT XECORE3 */
#define acmgt1__ext200__slm_access_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext201 :: GPU Time Elapsed */
#define acmgt1__ext201__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext201 :: GPU Core Clocks */
#define acmgt1__ext201__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext201 :: AVG GPU Core Frequency */
#define acmgt1__ext201__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext201 :: AVG GPU Core Frequency */
#define acmgt1__ext201__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext201 :: SLM ACCESS COUNT XECORE4 */
#define acmgt1__ext201__slm_access_count_xecore4__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext201 :: SLM ACCESS COUNT XECORE5 */
#define acmgt1__ext201__slm_access_count_xecore5__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext201 :: SLM ACCESS COUNT XECORE6 */
#define acmgt1__ext201__slm_access_count_xecore6__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext201 :: SLM ACCESS COUNT XECORE7 */
#define acmgt1__ext201__slm_access_count_xecore7__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext202 :: GPU Time Elapsed */
#define acmgt1__ext202__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext202 :: GPU Core Clocks */
#define acmgt1__ext202__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext202 :: AVG GPU Core Frequency */
#define acmgt1__ext202__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext202 :: AVG GPU Core Frequency */
#define acmgt1__ext202__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext202 :: GPU MEMORY L3 WRITE SQIDI0 */
#define acmgt1__ext202__gpu_memory_l3_write_sqidi0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext203 :: GPU Time Elapsed */
#define acmgt1__ext203__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext203 :: GPU Core Clocks */
#define acmgt1__ext203__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext203 :: AVG GPU Core Frequency */
#define acmgt1__ext203__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext203 :: AVG GPU Core Frequency */
#define acmgt1__ext203__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext203 :: GPU MEMORY L3 WRITE SQIDI1 */
#define acmgt1__ext203__gpu_memory_l3_write_sqidi1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext204 :: GPU Time Elapsed */
#define acmgt1__ext204__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext204 :: GPU Core Clocks */
#define acmgt1__ext204__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext204 :: AVG GPU Core Frequency */
#define acmgt1__ext204__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext204 :: AVG GPU Core Frequency */
#define acmgt1__ext204__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext204 :: RT INSTANCE NODE RAY COUNT XECORE0 */
#define acmgt1__ext204__rt_instance_node_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext204 :: RT INTERNAL NODE RAY COUNT XECORE0 */
#define acmgt1__ext204__rt_internal_node_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext204 :: RT TRAVERSAL STEP RAY COUNT XECORE0 */
#define acmgt1__ext204__rt_traversal_step_ray_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext205 :: GPU Time Elapsed */
#define acmgt1__ext205__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext205 :: GPU Core Clocks */
#define acmgt1__ext205__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext205 :: AVG GPU Core Frequency */
#define acmgt1__ext205__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext205 :: AVG GPU Core Frequency */
#define acmgt1__ext205__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext205 :: RT INSTANCE NODE RAY COUNT XECORE1 */
#define acmgt1__ext205__rt_instance_node_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext205 :: RT INTERNAL NODE RAY COUNT XECORE1 */
#define acmgt1__ext205__rt_internal_node_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext205 :: RT TRAVERSAL STEP RAY COUNT XECORE1 */
#define acmgt1__ext205__rt_traversal_step_ray_count_xecore1__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext206 :: GPU Time Elapsed */
#define acmgt1__ext206__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext206 :: GPU Core Clocks */
#define acmgt1__ext206__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext206 :: AVG GPU Core Frequency */
#define acmgt1__ext206__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext206 :: AVG GPU Core Frequency */
#define acmgt1__ext206__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext206 :: RT INSTANCE NODE RAY COUNT XECORE2 */
#define acmgt1__ext206__rt_instance_node_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext206 :: RT INTERNAL NODE RAY COUNT XECORE2 */
#define acmgt1__ext206__rt_internal_node_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext206 :: RT TRAVERSAL STEP RAY COUNT XECORE2 */
#define acmgt1__ext206__rt_traversal_step_ray_count_xecore2__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext207 :: GPU Time Elapsed */
#define acmgt1__ext207__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext207 :: GPU Core Clocks */
#define acmgt1__ext207__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext207 :: AVG GPU Core Frequency */
#define acmgt1__ext207__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext207 :: AVG GPU Core Frequency */
#define acmgt1__ext207__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext207 :: RT INSTANCE NODE RAY COUNT XECORE3 */
#define acmgt1__ext207__rt_instance_node_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext207 :: RT INTERNAL NODE RAY COUNT XECORE3 */
#define acmgt1__ext207__rt_internal_node_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext207 :: RT TRAVERSAL STEP RAY COUNT XECORE3 */
#define acmgt1__ext207__rt_traversal_step_ray_count_xecore3__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext208 :: GPU Time Elapsed */
#define acmgt1__ext208__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext208 :: GPU Core Clocks */
#define acmgt1__ext208__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext208 :: AVG GPU Core Frequency */
#define acmgt1__ext208__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext208 :: AVG GPU Core Frequency */
#define acmgt1__ext208__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext208 :: RT INSTANCE NODE RAY COUNT XECORE4 */
#define acmgt1__ext208__rt_instance_node_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext208 :: RT INTERNAL NODE RAY COUNT XECORE4 */
#define acmgt1__ext208__rt_internal_node_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext208 :: RT TRAVERSAL STEP RAY COUNT XECORE4 */
#define acmgt1__ext208__rt_traversal_step_ray_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext209 :: GPU Time Elapsed */
#define acmgt1__ext209__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext209 :: GPU Core Clocks */
#define acmgt1__ext209__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext209 :: AVG GPU Core Frequency */
#define acmgt1__ext209__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext209 :: AVG GPU Core Frequency */
#define acmgt1__ext209__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext209 :: RT INSTANCE NODE RAY COUNT XECORE5 */
#define acmgt1__ext209__rt_instance_node_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext209 :: RT INTERNAL NODE RAY COUNT XECORE5 */
#define acmgt1__ext209__rt_internal_node_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext209 :: RT TRAVERSAL STEP RAY COUNT XECORE5 */
#define acmgt1__ext209__rt_traversal_step_ray_count_xecore5__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext210 :: GPU Time Elapsed */
#define acmgt1__ext210__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext210 :: GPU Core Clocks */
#define acmgt1__ext210__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext210 :: AVG GPU Core Frequency */
#define acmgt1__ext210__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext210 :: AVG GPU Core Frequency */
#define acmgt1__ext210__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext210 :: RT INSTANCE NODE RAY COUNT XECORE6 */
#define acmgt1__ext210__rt_instance_node_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext210 :: RT INTERNAL NODE RAY COUNT XECORE6 */
#define acmgt1__ext210__rt_internal_node_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext210 :: RT TRAVERSAL STEP RAY COUNT XECORE6 */
#define acmgt1__ext210__rt_traversal_step_ray_count_xecore6__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext211 :: GPU Time Elapsed */
#define acmgt1__ext211__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext211 :: GPU Core Clocks */
#define acmgt1__ext211__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext211 :: AVG GPU Core Frequency */
#define acmgt1__ext211__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext211 :: AVG GPU Core Frequency */
#define acmgt1__ext211__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext211 :: RT INSTANCE NODE RAY COUNT XECORE7 */
#define acmgt1__ext211__rt_instance_node_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext211 :: RT INTERNAL NODE RAY COUNT XECORE7 */
#define acmgt1__ext211__rt_internal_node_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext211 :: RT TRAVERSAL STEP RAY COUNT XECORE7 */
#define acmgt1__ext211__rt_traversal_step_ray_count_xecore7__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext212 :: GPU Time Elapsed */
#define acmgt1__ext212__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext212 :: GPU Core Clocks */
#define acmgt1__ext212__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext212 :: AVG GPU Core Frequency */
#define acmgt1__ext212__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext212 :: AVG GPU Core Frequency */
#define acmgt1__ext212__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext212 :: RT QUAD LEAF RAY COUNT XECORE0 */
#define acmgt1__ext212__rt_quad_leaf_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext212 :: RT PROCEDURAL NODE RAY COUNT XECORE0 */
#define acmgt1__ext212__rt_procedural_node_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext213 :: GPU Time Elapsed */
#define acmgt1__ext213__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext213 :: GPU Core Clocks */
#define acmgt1__ext213__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext213 :: AVG GPU Core Frequency */
#define acmgt1__ext213__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext213 :: AVG GPU Core Frequency */
#define acmgt1__ext213__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext213 :: RT QUAD LEAF RAY COUNT XECORE1 */
#define acmgt1__ext213__rt_quad_leaf_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext213 :: RT PROCEDURAL NODE RAY COUNT XECORE1 */
#define acmgt1__ext213__rt_procedural_node_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext214 :: GPU Time Elapsed */
#define acmgt1__ext214__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext214 :: GPU Core Clocks */
#define acmgt1__ext214__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext214 :: AVG GPU Core Frequency */
#define acmgt1__ext214__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext214 :: AVG GPU Core Frequency */
#define acmgt1__ext214__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext214 :: RT QUAD LEAF RAY COUNT XECORE2 */
#define acmgt1__ext214__rt_quad_leaf_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext214 :: RT PROCEDURAL NODE RAY COUNT XECORE2 */
#define acmgt1__ext214__rt_procedural_node_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext215 :: GPU Time Elapsed */
#define acmgt1__ext215__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext215 :: GPU Core Clocks */
#define acmgt1__ext215__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext215 :: AVG GPU Core Frequency */
#define acmgt1__ext215__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext215 :: AVG GPU Core Frequency */
#define acmgt1__ext215__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext215 :: RT QUAD LEAF RAY COUNT XECORE3 */
#define acmgt1__ext215__rt_quad_leaf_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext215 :: RT PROCEDURAL NODE RAY COUNT XECORE3 */
#define acmgt1__ext215__rt_procedural_node_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext216 :: GPU Time Elapsed */
#define acmgt1__ext216__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext216 :: GPU Core Clocks */
#define acmgt1__ext216__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext216 :: AVG GPU Core Frequency */
#define acmgt1__ext216__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext216 :: AVG GPU Core Frequency */
#define acmgt1__ext216__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext216 :: RT QUAD LEAF RAY COUNT XECORE4 */
#define acmgt1__ext216__rt_quad_leaf_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext216 :: RT PROCEDURAL NODE RAY COUNT XECORE4 */
#define acmgt1__ext216__rt_procedural_node_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext217 :: GPU Time Elapsed */
#define acmgt1__ext217__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext217 :: GPU Core Clocks */
#define acmgt1__ext217__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext217 :: AVG GPU Core Frequency */
#define acmgt1__ext217__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext217 :: AVG GPU Core Frequency */
#define acmgt1__ext217__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext217 :: RT QUAD LEAF RAY COUNT XECORE5 */
#define acmgt1__ext217__rt_quad_leaf_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext217 :: RT PROCEDURAL NODE RAY COUNT XECORE5 */
#define acmgt1__ext217__rt_procedural_node_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext218 :: GPU Time Elapsed */
#define acmgt1__ext218__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext218 :: GPU Core Clocks */
#define acmgt1__ext218__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext218 :: AVG GPU Core Frequency */
#define acmgt1__ext218__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext218 :: AVG GPU Core Frequency */
#define acmgt1__ext218__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext218 :: RT QUAD LEAF RAY COUNT XECORE6 */
#define acmgt1__ext218__rt_quad_leaf_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext218 :: RT PROCEDURAL NODE RAY COUNT XECORE6 */
#define acmgt1__ext218__rt_procedural_node_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext219 :: GPU Time Elapsed */
#define acmgt1__ext219__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext219 :: GPU Core Clocks */
#define acmgt1__ext219__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext219 :: AVG GPU Core Frequency */
#define acmgt1__ext219__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext219 :: AVG GPU Core Frequency */
#define acmgt1__ext219__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext219 :: RT QUAD LEAF RAY COUNT XECORE7 */
#define acmgt1__ext219__rt_quad_leaf_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext219 :: RT PROCEDURAL NODE RAY COUNT XECORE7 */
#define acmgt1__ext219__rt_procedural_node_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext220 :: GPU Time Elapsed */
#define acmgt1__ext220__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext220 :: GPU Core Clocks */
#define acmgt1__ext220__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext220 :: AVG GPU Core Frequency */
#define acmgt1__ext220__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext220 :: AVG GPU Core Frequency */
#define acmgt1__ext220__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext220 :: RT BVH CACHE MISS XECORE0 */
#define acmgt1__ext220__rt_bvh_cache_miss_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext220 :: RT BVH CACHE MISS XECORE1 */
#define acmgt1__ext220__rt_bvh_cache_miss_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext220 :: RT BVH CACHE MISS XECORE2 */
#define acmgt1__ext220__rt_bvh_cache_miss_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext220 :: RT BVH CACHE MISS XECORE3 */
#define acmgt1__ext220__rt_bvh_cache_miss_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext221 :: GPU Time Elapsed */
#define acmgt1__ext221__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext221 :: GPU Core Clocks */
#define acmgt1__ext221__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext221 :: AVG GPU Core Frequency */
#define acmgt1__ext221__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext221 :: AVG GPU Core Frequency */
#define acmgt1__ext221__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext221 :: RT BVH CACHE MISS XECORE4 */
#define acmgt1__ext221__rt_bvh_cache_miss_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext221 :: RT BVH CACHE MISS XECORE5 */
#define acmgt1__ext221__rt_bvh_cache_miss_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext221 :: RT BVH CACHE MISS XECORE6 */
#define acmgt1__ext221__rt_bvh_cache_miss_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext221 :: RT BVH CACHE MISS XECORE7 */
#define acmgt1__ext221__rt_bvh_cache_miss_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext222 :: GPU Time Elapsed */
#define acmgt1__ext222__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext222 :: GPU Core Clocks */
#define acmgt1__ext222__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext222 :: AVG GPU Core Frequency */
#define acmgt1__ext222__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext222 :: AVG GPU Core Frequency */
#define acmgt1__ext222__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext222 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE0 */
#define acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore0__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext222 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE1 */
#define acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore1__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext222 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE2 */
#define acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore2__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext222 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE3 */
#define acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore3__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext223 :: GPU Time Elapsed */
#define acmgt1__ext223__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext223 :: GPU Core Clocks */
#define acmgt1__ext223__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext223 :: AVG GPU Core Frequency */
#define acmgt1__ext223__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext223 :: AVG GPU Core Frequency */
#define acmgt1__ext223__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext223 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE4 */
#define acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore4__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext223 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE5 */
#define acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore5__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext223 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE6 */
#define acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore6__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext223 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE7 */
#define acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore7__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext224 :: GPU Time Elapsed */
#define acmgt1__ext224__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext224 :: GPU Core Clocks */
#define acmgt1__ext224__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext224 :: AVG GPU Core Frequency */
#define acmgt1__ext224__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext224 :: AVG GPU Core Frequency */
#define acmgt1__ext224__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext224 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE0 */
#define acmgt1__ext224__color_pipe_cache_latency2_stall_l3_node0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext224 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE1 */
#define acmgt1__ext224__color_pipe_cache_latency2_stall_l3_node1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext225 :: GPU Time Elapsed */
#define acmgt1__ext225__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext225 :: GPU Core Clocks */
#define acmgt1__ext225__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext225 :: AVG GPU Core Frequency */
#define acmgt1__ext225__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext225 :: AVG GPU Core Frequency */
#define acmgt1__ext225__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext225 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0 */
static uint64_t
acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read(UNUSED struct intel_perf_config *perf,
                                                                       const struct intel_perf_query_info *query,
                                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 1 B 0 READ UMUL 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD 16 B 4 READ UMUL UADD 32 B 5 READ UMUL UADD 64 B 6 READ UMUL UADD 128 B 7 READ UMUL UADD 256 C 1 READ UMUL UADD 512 C 3 READ UMUL UADD 1024 C 5 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = 1 * tmp0;
   uint64_t tmp2 = results->accumulator[query->b_offset + 1];
   uint64_t tmp3 = 2 * tmp2;
   uint64_t tmp4 = tmp1 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 2];
   uint64_t tmp6 = 4 * tmp5;
   uint64_t tmp7 = tmp4 + tmp6;
   uint64_t tmp8 = results->accumulator[query->b_offset + 3];
   uint64_t tmp9 = 8 * tmp8;
   uint64_t tmp10 = tmp7 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 4];
   uint64_t tmp12 = 16 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->b_offset + 5];
   uint64_t tmp15 = 32 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->b_offset + 6];
   uint64_t tmp18 = 64 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = results->accumulator[query->b_offset + 7];
   uint64_t tmp21 = 128 * tmp20;
   uint64_t tmp22 = tmp19 + tmp21;
   uint64_t tmp23 = results->accumulator[query->c_offset + 1];
   uint64_t tmp24 = 256 * tmp23;
   uint64_t tmp25 = tmp22 + tmp24;
   uint64_t tmp26 = results->accumulator[query->c_offset + 3];
   uint64_t tmp27 = 512 * tmp26;
   uint64_t tmp28 = tmp25 + tmp27;
   uint64_t tmp29 = results->accumulator[query->c_offset + 5];
   uint64_t tmp30 = 1024 * tmp29;
   uint64_t tmp31 = tmp28 + tmp30;

   return tmp31;
}

/* Ext226 :: GPU Time Elapsed */
#define acmgt1__ext226__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext226 :: GPU Core Clocks */
#define acmgt1__ext226__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext226 :: AVG GPU Core Frequency */
#define acmgt1__ext226__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext226 :: AVG GPU Core Frequency */
#define acmgt1__ext226__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext226 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1 */
#define acmgt1__ext226__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext227 :: GPU Time Elapsed */
#define acmgt1__ext227__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext227 :: GPU Core Clocks */
#define acmgt1__ext227__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext227 :: AVG GPU Core Frequency */
#define acmgt1__ext227__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext227 :: AVG GPU Core Frequency */
#define acmgt1__ext227__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext227 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0 */
#define acmgt1__ext227__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext228 :: GPU Time Elapsed */
#define acmgt1__ext228__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext228 :: GPU Core Clocks */
#define acmgt1__ext228__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext228 :: AVG GPU Core Frequency */
#define acmgt1__ext228__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext228 :: AVG GPU Core Frequency */
#define acmgt1__ext228__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext228 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1 */
#define acmgt1__ext228__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext229 :: GPU Time Elapsed */
#define acmgt1__ext229__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext229 :: GPU Core Clocks */
#define acmgt1__ext229__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext229 :: AVG GPU Core Frequency */
#define acmgt1__ext229__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext229 :: AVG GPU Core Frequency */
#define acmgt1__ext229__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext229 :: SLM BANK CONFLICT COUNT XECORE0 */
static uint64_t
acmgt1__ext229__slm_bank_conflict_count_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD C 3 READ UADD 2 C 2 READ UMUL UADD 4 C 1 READ UMUL UADD 8 C 0 READ UMUL UADD B 7 READ UADD 2 B 6 READ UMUL UADD 4 B 5 READ UMUL UADD 8 B 4 READ UMUL UADD B 3 READ UADD 2 B 2 READ UMUL UADD 4 B 1 READ UMUL UADD 8 B 0 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->c_offset + 2];
   uint64_t tmp13 = 2 * tmp12;
   uint64_t tmp14 = tmp11 + tmp13;
   uint64_t tmp15 = results->accumulator[query->c_offset + 1];
   uint64_t tmp16 = 4 * tmp15;
   uint64_t tmp17 = tmp14 + tmp16;
   uint64_t tmp18 = results->accumulator[query->c_offset + 0];
   uint64_t tmp19 = 8 * tmp18;
   uint64_t tmp20 = tmp17 + tmp19;
   uint64_t tmp21 = results->accumulator[query->b_offset + 7];
   uint64_t tmp22 = tmp20 + tmp21;
   uint64_t tmp23 = results->accumulator[query->b_offset + 6];
   uint64_t tmp24 = 2 * tmp23;
   uint64_t tmp25 = tmp22 + tmp24;
   uint64_t tmp26 = results->accumulator[query->b_offset + 5];
   uint64_t tmp27 = 4 * tmp26;
   uint64_t tmp28 = tmp25 + tmp27;
   uint64_t tmp29 = results->accumulator[query->b_offset + 4];
   uint64_t tmp30 = 8 * tmp29;
   uint64_t tmp31 = tmp28 + tmp30;
   uint64_t tmp32 = results->accumulator[query->b_offset + 3];
   uint64_t tmp33 = tmp31 + tmp32;
   uint64_t tmp34 = results->accumulator[query->b_offset + 2];
   uint64_t tmp35 = 2 * tmp34;
   uint64_t tmp36 = tmp33 + tmp35;
   uint64_t tmp37 = results->accumulator[query->b_offset + 1];
   uint64_t tmp38 = 4 * tmp37;
   uint64_t tmp39 = tmp36 + tmp38;
   uint64_t tmp40 = results->accumulator[query->b_offset + 0];
   uint64_t tmp41 = 8 * tmp40;
   uint64_t tmp42 = tmp39 + tmp41;

   return tmp42;
}

/* Ext230 :: GPU Time Elapsed */
#define acmgt1__ext230__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext230 :: GPU Core Clocks */
#define acmgt1__ext230__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext230 :: AVG GPU Core Frequency */
#define acmgt1__ext230__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext230 :: AVG GPU Core Frequency */
#define acmgt1__ext230__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext230 :: SLM BANK CONFLICT COUNT XECORE1 */
#define acmgt1__ext230__slm_bank_conflict_count_xecore1__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext231 :: GPU Time Elapsed */
#define acmgt1__ext231__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext231 :: GPU Core Clocks */
#define acmgt1__ext231__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext231 :: AVG GPU Core Frequency */
#define acmgt1__ext231__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext231 :: AVG GPU Core Frequency */
#define acmgt1__ext231__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext231 :: SLM BANK CONFLICT COUNT XECORE2 */
#define acmgt1__ext231__slm_bank_conflict_count_xecore2__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext232 :: GPU Time Elapsed */
#define acmgt1__ext232__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext232 :: GPU Core Clocks */
#define acmgt1__ext232__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext232 :: AVG GPU Core Frequency */
#define acmgt1__ext232__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext232 :: AVG GPU Core Frequency */
#define acmgt1__ext232__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext232 :: SLM BANK CONFLICT COUNT XECORE3 */
#define acmgt1__ext232__slm_bank_conflict_count_xecore3__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext233 :: GPU Time Elapsed */
#define acmgt1__ext233__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext233 :: GPU Core Clocks */
#define acmgt1__ext233__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext233 :: AVG GPU Core Frequency */
#define acmgt1__ext233__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext233 :: AVG GPU Core Frequency */
#define acmgt1__ext233__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext233 :: SLM BANK CONFLICT COUNT XECORE4 */
#define acmgt1__ext233__slm_bank_conflict_count_xecore4__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext234 :: GPU Time Elapsed */
#define acmgt1__ext234__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext234 :: GPU Core Clocks */
#define acmgt1__ext234__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext234 :: AVG GPU Core Frequency */
#define acmgt1__ext234__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext234 :: AVG GPU Core Frequency */
#define acmgt1__ext234__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext234 :: SLM BANK CONFLICT COUNT XECORE5 */
#define acmgt1__ext234__slm_bank_conflict_count_xecore5__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext235 :: GPU Time Elapsed */
#define acmgt1__ext235__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext235 :: GPU Core Clocks */
#define acmgt1__ext235__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext235 :: AVG GPU Core Frequency */
#define acmgt1__ext235__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext235 :: AVG GPU Core Frequency */
#define acmgt1__ext235__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext235 :: SLM BANK CONFLICT COUNT XECORE6 */
#define acmgt1__ext235__slm_bank_conflict_count_xecore6__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext236 :: GPU Time Elapsed */
#define acmgt1__ext236__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext236 :: GPU Core Clocks */
#define acmgt1__ext236__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext236 :: AVG GPU Core Frequency */
#define acmgt1__ext236__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext236 :: AVG GPU Core Frequency */
#define acmgt1__ext236__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext236 :: SLM BANK CONFLICT COUNT XECORE7 */
#define acmgt1__ext236__slm_bank_conflict_count_xecore7__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext237 :: GPU Time Elapsed */
#define acmgt1__ext237__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext237 :: GPU Core Clocks */
#define acmgt1__ext237__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext237 :: AVG GPU Core Frequency */
#define acmgt1__ext237__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext237 :: AVG GPU Core Frequency */
#define acmgt1__ext237__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext237 :: L3 MISS L3BANK0 */
#define acmgt1__ext237__l3_miss_l3_bank0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext237 :: L3 MISS L3BANK1 */
#define acmgt1__ext237__l3_miss_l3_bank1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext237 :: L3 MISS L3BANK2 */
#define acmgt1__ext237__l3_miss_l3_bank2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext237 :: L3 MISS L3BANK3 */
#define acmgt1__ext237__l3_miss_l3_bank3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext237 :: L3 MISS L3BANK4 */
#define acmgt1__ext237__l3_miss_l3_bank4__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext237 :: L3 MISS L3BANK5 */
#define acmgt1__ext237__l3_miss_l3_bank5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext237 :: L3 MISS L3BANK6 */
#define acmgt1__ext237__l3_miss_l3_bank6__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext237 :: L3 MISS L3BANK7 */
#define acmgt1__ext237__l3_miss_l3_bank7__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext238 :: GPU Time Elapsed */
#define acmgt1__ext238__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext238 :: GPU Core Clocks */
#define acmgt1__ext238__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext238 :: AVG GPU Core Frequency */
#define acmgt1__ext238__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext238 :: AVG GPU Core Frequency */
#define acmgt1__ext238__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext238 :: AMFS L3 WRITE SLICE0 */
#define acmgt1__ext238__amfs_l3_write_slice0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext238 :: AMFS L3 WRITE SLICE1 */
#define acmgt1__ext238__amfs_l3_write_slice1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE0 */
#define acmgt1__ext238__xve_dataport_fence_message_count_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE1 */
#define acmgt1__ext238__xve_dataport_fence_message_count_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE2 */
#define acmgt1__ext238__xve_dataport_fence_message_count_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE3 */
#define acmgt1__ext238__xve_dataport_fence_message_count_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE4 */
#define acmgt1__ext238__xve_dataport_fence_message_count_xecore4__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE5 */
#define acmgt1__ext238__xve_dataport_fence_message_count_xecore5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE6 */
#define acmgt1__ext238__xve_dataport_fence_message_count_xecore6__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE7 */
#define acmgt1__ext238__xve_dataport_fence_message_count_xecore7__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext239 :: GPU Time Elapsed */
#define acmgt1__ext239__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext239 :: GPU Core Clocks */
#define acmgt1__ext239__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext239 :: AVG GPU Core Frequency */
#define acmgt1__ext239__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext239 :: AVG GPU Core Frequency */
#define acmgt1__ext239__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext239 :: GPU MEMORY L3 READ SQIDI0 */
#define acmgt1__ext239__gpu_memory_l3_read_sqidi0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext240 :: GPU Time Elapsed */
#define acmgt1__ext240__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext240 :: GPU Core Clocks */
#define acmgt1__ext240__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext240 :: AVG GPU Core Frequency */
#define acmgt1__ext240__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext240 :: AVG GPU Core Frequency */
#define acmgt1__ext240__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext240 :: GPU MEMORY L3 READ SQIDI1 */
#define acmgt1__ext240__gpu_memory_l3_read_sqidi1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext500 :: GPU Time Elapsed */
#define acmgt1__ext500__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext500 :: GPU Core Clocks */
#define acmgt1__ext500__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext500 :: AVG GPU Core Frequency */
#define acmgt1__ext500__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext500 :: AVG GPU Core Frequency */
#define acmgt1__ext500__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext500 :: ICACHE HIT BANK0 XECORE0 */
#define acmgt1__ext500__icache_hit_bank0_xecore0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE0 */
#define acmgt1__ext500__icache_miss_bank0_xecore0__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext500 :: ICACHE HIT BANK0 XECORE1 */
#define acmgt1__ext500__icache_hit_bank0_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE1 */
#define acmgt1__ext500__icache_miss_bank0_xecore1__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext500 :: ICACHE HIT BANK0 XECORE2 */
#define acmgt1__ext500__icache_hit_bank0_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE2 */
#define acmgt1__ext500__icache_miss_bank0_xecore2__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext500 :: ICACHE HIT BANK0 XECORE3 */
#define acmgt1__ext500__icache_hit_bank0_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE3 */
#define acmgt1__ext500__icache_miss_bank0_xecore3__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext500 :: ICACHE HIT BANK0 XECORE4 */
#define acmgt1__ext500__icache_hit_bank0_xecore4__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext500 :: ICACHE MISS BANK0 XECORE4 */
#define acmgt1__ext500__icache_miss_bank0_xecore4__read \
   hsw__compute_extended__typed_writes0__read

/* Ext500 :: ICACHE HIT BANK0 XECORE5 */
#define acmgt1__ext500__icache_hit_bank0_xecore5__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE5 */
#define acmgt1__ext500__icache_miss_bank0_xecore5__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext500 :: ICACHE HIT BANK0 XECORE6 */
#define acmgt1__ext500__icache_hit_bank0_xecore6__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE6 */
#define acmgt1__ext500__icache_miss_bank0_xecore6__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext500 :: ICACHE HIT BANK0 XECORE7 */
#define acmgt1__ext500__icache_hit_bank0_xecore7__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE7 */
#define acmgt1__ext500__icache_miss_bank0_xecore7__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext501 :: GPU Time Elapsed */
#define acmgt1__ext501__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext501 :: GPU Core Clocks */
#define acmgt1__ext501__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext501 :: AVG GPU Core Frequency */
#define acmgt1__ext501__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext501 :: AVG GPU Core Frequency */
#define acmgt1__ext501__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext501 :: ICACHE HIT BANK1 XECORE0 */
#define acmgt1__ext501__icache_hit_bank1_xecore0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext501 :: ICACHE MISS BANK1 XECORE0 */
#define acmgt1__ext501__icache_miss_bank1_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext501 :: ICACHE HIT BANK1 XECORE1 */
#define acmgt1__ext501__icache_hit_bank1_xecore1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE1 */
#define acmgt1__ext501__icache_miss_bank1_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext501 :: ICACHE HIT BANK1 XECORE2 */
#define acmgt1__ext501__icache_hit_bank1_xecore2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE2 */
#define acmgt1__ext501__icache_miss_bank1_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext501 :: ICACHE HIT BANK1 XECORE3 */
#define acmgt1__ext501__icache_hit_bank1_xecore3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE3 */
#define acmgt1__ext501__icache_miss_bank1_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext501 :: ICACHE HIT BANK1 XECORE4 */
#define acmgt1__ext501__icache_hit_bank1_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE4 */
#define acmgt1__ext501__icache_miss_bank1_xecore4__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext501 :: ICACHE HIT BANK1 XECORE5 */
#define acmgt1__ext501__icache_hit_bank1_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE5 */
#define acmgt1__ext501__icache_miss_bank1_xecore5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext501 :: ICACHE HIT BANK1 XECORE6 */
#define acmgt1__ext501__icache_hit_bank1_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE6 */
#define acmgt1__ext501__icache_miss_bank1_xecore6__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext501 :: ICACHE HIT BANK1 XECORE7 */
#define acmgt1__ext501__icache_hit_bank1_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE7 */
#define acmgt1__ext501__icache_miss_bank1_xecore7__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext502 :: GPU Time Elapsed */
#define acmgt1__ext502__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext502 :: GPU Core Clocks */
#define acmgt1__ext502__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext502 :: AVG GPU Core Frequency */
#define acmgt1__ext502__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext502 :: AVG GPU Core Frequency */
#define acmgt1__ext502__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext502 :: ICACHE HIT BANK2 XECORE0 */
#define acmgt1__ext502__icache_hit_bank2_xecore0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext502 :: ICACHE MISS BANK2 XECORE0 */
#define acmgt1__ext502__icache_miss_bank2_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext502 :: ICACHE HIT BANK2 XECORE1 */
#define acmgt1__ext502__icache_hit_bank2_xecore1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE1 */
#define acmgt1__ext502__icache_miss_bank2_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext502 :: ICACHE HIT BANK2 XECORE2 */
#define acmgt1__ext502__icache_hit_bank2_xecore2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE2 */
#define acmgt1__ext502__icache_miss_bank2_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext502 :: ICACHE HIT BANK2 XECORE3 */
#define acmgt1__ext502__icache_hit_bank2_xecore3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE3 */
#define acmgt1__ext502__icache_miss_bank2_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext502 :: ICACHE HIT BANK2 XECORE4 */
#define acmgt1__ext502__icache_hit_bank2_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE4 */
#define acmgt1__ext502__icache_miss_bank2_xecore4__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext502 :: ICACHE HIT BANK2 XECORE5 */
#define acmgt1__ext502__icache_hit_bank2_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE5 */
#define acmgt1__ext502__icache_miss_bank2_xecore5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext502 :: ICACHE HIT BANK2 XECORE6 */
#define acmgt1__ext502__icache_hit_bank2_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE6 */
#define acmgt1__ext502__icache_miss_bank2_xecore6__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext502 :: ICACHE HIT BANK2 XECORE7 */
#define acmgt1__ext502__icache_hit_bank2_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE7 */
#define acmgt1__ext502__icache_miss_bank2_xecore7__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext503 :: GPU Time Elapsed */
#define acmgt1__ext503__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext503 :: GPU Core Clocks */
#define acmgt1__ext503__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext503 :: AVG GPU Core Frequency */
#define acmgt1__ext503__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext503 :: AVG GPU Core Frequency */
#define acmgt1__ext503__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext503 :: ICACHE HIT BANK3 XECORE0 */
#define acmgt1__ext503__icache_hit_bank3_xecore0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext503 :: ICACHE MISS BANK3 XECORE0 */
#define acmgt1__ext503__icache_miss_bank3_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext503 :: ICACHE HIT BANK3 XECORE1 */
#define acmgt1__ext503__icache_hit_bank3_xecore1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE1 */
#define acmgt1__ext503__icache_miss_bank3_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext503 :: ICACHE HIT BANK3 XECORE2 */
#define acmgt1__ext503__icache_hit_bank3_xecore2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE2 */
#define acmgt1__ext503__icache_miss_bank3_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext503 :: ICACHE HIT BANK3 XECORE3 */
#define acmgt1__ext503__icache_hit_bank3_xecore3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE3 */
#define acmgt1__ext503__icache_miss_bank3_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext503 :: ICACHE HIT BANK3 XECORE4 */
#define acmgt1__ext503__icache_hit_bank3_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE4 */
#define acmgt1__ext503__icache_miss_bank3_xecore4__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext503 :: ICACHE HIT BANK3 XECORE5 */
#define acmgt1__ext503__icache_hit_bank3_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE5 */
#define acmgt1__ext503__icache_miss_bank3_xecore5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext503 :: ICACHE HIT BANK3 XECORE6 */
#define acmgt1__ext503__icache_hit_bank3_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE6 */
#define acmgt1__ext503__icache_miss_bank3_xecore6__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext503 :: ICACHE HIT BANK3 XECORE7 */
#define acmgt1__ext503__icache_hit_bank3_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE7 */
#define acmgt1__ext503__icache_miss_bank3_xecore7__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext508 :: GPU Time Elapsed */
#define acmgt1__ext508__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext508 :: GPU Core Clocks */
#define acmgt1__ext508__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext508 :: AVG GPU Core Frequency */
#define acmgt1__ext508__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext508 :: AVG GPU Core Frequency */
#define acmgt1__ext508__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext508 :: SLM BYTE READ BANK0 XECORE0 */
static uint64_t
acmgt1__ext508__slm_byte_read_bank0_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD 16 C 3 READ UMUL UADD 32 C 2 READ UMUL UADD 64 C 1 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 2];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 1];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;

   return tmp18;
}

/* Ext508 :: LOAD STORE CACHE BYTE READ BANK0 XECORE0 */
static uint64_t
acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                               const struct intel_perf_query_info *query,
                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD 16 B 4 READ UMUL UADD 32 B 5 READ UMUL UADD 64 B 6 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 2];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 3];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 4];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 5];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->b_offset + 6];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;

   return tmp18;
}

/* Ext509 :: GPU Time Elapsed */
#define acmgt1__ext509__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext509 :: GPU Core Clocks */
#define acmgt1__ext509__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext509 :: AVG GPU Core Frequency */
#define acmgt1__ext509__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext509 :: AVG GPU Core Frequency */
#define acmgt1__ext509__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext509 :: SLM BYTE READ BANK0 XECORE1 */
#define acmgt1__ext509__slm_byte_read_bank0_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext509 :: LOAD STORE CACHE BYTE READ BANK0 XECORE1 */
#define acmgt1__ext509__load_store_cache_byte_read_bank0_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext510 :: GPU Time Elapsed */
#define acmgt1__ext510__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext510 :: GPU Core Clocks */
#define acmgt1__ext510__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext510 :: AVG GPU Core Frequency */
#define acmgt1__ext510__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext510 :: AVG GPU Core Frequency */
#define acmgt1__ext510__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext510 :: SLM BYTE READ BANK0 XECORE2 */
#define acmgt1__ext510__slm_byte_read_bank0_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext510 :: LOAD STORE CACHE BYTE READ BANK0 XECORE2 */
#define acmgt1__ext510__load_store_cache_byte_read_bank0_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext511 :: GPU Time Elapsed */
#define acmgt1__ext511__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext511 :: GPU Core Clocks */
#define acmgt1__ext511__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext511 :: AVG GPU Core Frequency */
#define acmgt1__ext511__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext511 :: AVG GPU Core Frequency */
#define acmgt1__ext511__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext511 :: SLM BYTE READ BANK0 XECORE3 */
#define acmgt1__ext511__slm_byte_read_bank0_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext511 :: LOAD STORE CACHE BYTE READ BANK0 XECORE3 */
#define acmgt1__ext511__load_store_cache_byte_read_bank0_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext512 :: GPU Time Elapsed */
#define acmgt1__ext512__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext512 :: GPU Core Clocks */
#define acmgt1__ext512__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext512 :: AVG GPU Core Frequency */
#define acmgt1__ext512__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext512 :: AVG GPU Core Frequency */
#define acmgt1__ext512__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext512 :: SLM BYTE READ BANK0 XECORE4 */
#define acmgt1__ext512__slm_byte_read_bank0_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext512 :: LOAD STORE CACHE BYTE READ BANK0 XECORE4 */
#define acmgt1__ext512__load_store_cache_byte_read_bank0_xecore4__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext513 :: GPU Time Elapsed */
#define acmgt1__ext513__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext513 :: GPU Core Clocks */
#define acmgt1__ext513__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext513 :: AVG GPU Core Frequency */
#define acmgt1__ext513__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext513 :: AVG GPU Core Frequency */
#define acmgt1__ext513__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext513 :: SLM BYTE READ BANK0 XECORE5 */
#define acmgt1__ext513__slm_byte_read_bank0_xecore5__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext513 :: LOAD STORE CACHE BYTE READ BANK0 XECORE5 */
#define acmgt1__ext513__load_store_cache_byte_read_bank0_xecore5__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext514 :: GPU Time Elapsed */
#define acmgt1__ext514__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext514 :: GPU Core Clocks */
#define acmgt1__ext514__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext514 :: AVG GPU Core Frequency */
#define acmgt1__ext514__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext514 :: AVG GPU Core Frequency */
#define acmgt1__ext514__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext514 :: SLM BYTE READ BANK0 XECORE6 */
#define acmgt1__ext514__slm_byte_read_bank0_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext514 :: LOAD STORE CACHE BYTE READ BANK0 XECORE6 */
#define acmgt1__ext514__load_store_cache_byte_read_bank0_xecore6__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext515 :: GPU Time Elapsed */
#define acmgt1__ext515__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext515 :: GPU Core Clocks */
#define acmgt1__ext515__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext515 :: AVG GPU Core Frequency */
#define acmgt1__ext515__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext515 :: AVG GPU Core Frequency */
#define acmgt1__ext515__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext515 :: SLM BYTE READ BANK0 XECORE7 */
#define acmgt1__ext515__slm_byte_read_bank0_xecore7__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext515 :: LOAD STORE CACHE BYTE READ BANK0 XECORE7 */
#define acmgt1__ext515__load_store_cache_byte_read_bank0_xecore7__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext516 :: GPU Time Elapsed */
#define acmgt1__ext516__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext516 :: GPU Core Clocks */
#define acmgt1__ext516__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext516 :: AVG GPU Core Frequency */
#define acmgt1__ext516__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext516 :: AVG GPU Core Frequency */
#define acmgt1__ext516__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext516 :: SLM BYTE READ BANK1 XECORE0 */
#define acmgt1__ext516__slm_byte_read_bank1_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext516 :: LOAD STORE CACHE BYTE READ BANK1 XECORE0 */
#define acmgt1__ext516__load_store_cache_byte_read_bank1_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext517 :: GPU Time Elapsed */
#define acmgt1__ext517__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext517 :: GPU Core Clocks */
#define acmgt1__ext517__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext517 :: AVG GPU Core Frequency */
#define acmgt1__ext517__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext517 :: AVG GPU Core Frequency */
#define acmgt1__ext517__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext517 :: SLM BYTE READ BANK1 XECORE1 */
#define acmgt1__ext517__slm_byte_read_bank1_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext517 :: LOAD STORE CACHE BYTE READ BANK1 XECORE1 */
#define acmgt1__ext517__load_store_cache_byte_read_bank1_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext518 :: GPU Time Elapsed */
#define acmgt1__ext518__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext518 :: GPU Core Clocks */
#define acmgt1__ext518__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext518 :: AVG GPU Core Frequency */
#define acmgt1__ext518__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext518 :: AVG GPU Core Frequency */
#define acmgt1__ext518__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext518 :: SLM BYTE READ BANK1 XECORE2 */
#define acmgt1__ext518__slm_byte_read_bank1_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext518 :: LOAD STORE CACHE BYTE READ BANK1 XECORE2 */
#define acmgt1__ext518__load_store_cache_byte_read_bank1_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext519 :: GPU Time Elapsed */
#define acmgt1__ext519__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext519 :: GPU Core Clocks */
#define acmgt1__ext519__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext519 :: AVG GPU Core Frequency */
#define acmgt1__ext519__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext519 :: AVG GPU Core Frequency */
#define acmgt1__ext519__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext519 :: SLM BYTE READ BANK1 XECORE3 */
#define acmgt1__ext519__slm_byte_read_bank1_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext519 :: LOAD STORE CACHE BYTE READ BANK1 XECORE3 */
#define acmgt1__ext519__load_store_cache_byte_read_bank1_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext520 :: GPU Time Elapsed */
#define acmgt1__ext520__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext520 :: GPU Core Clocks */
#define acmgt1__ext520__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext520 :: AVG GPU Core Frequency */
#define acmgt1__ext520__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext520 :: AVG GPU Core Frequency */
#define acmgt1__ext520__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext520 :: SLM BYTE READ BANK1 XECORE4 */
#define acmgt1__ext520__slm_byte_read_bank1_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext520 :: LOAD STORE CACHE BYTE READ BANK1 XECORE4 */
#define acmgt1__ext520__load_store_cache_byte_read_bank1_xecore4__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext521 :: GPU Time Elapsed */
#define acmgt1__ext521__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext521 :: GPU Core Clocks */
#define acmgt1__ext521__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext521 :: AVG GPU Core Frequency */
#define acmgt1__ext521__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext521 :: AVG GPU Core Frequency */
#define acmgt1__ext521__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext521 :: SLM BYTE READ BANK1 XECORE5 */
#define acmgt1__ext521__slm_byte_read_bank1_xecore5__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext521 :: LOAD STORE CACHE BYTE READ BANK1 XECORE5 */
#define acmgt1__ext521__load_store_cache_byte_read_bank1_xecore5__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext522 :: GPU Time Elapsed */
#define acmgt1__ext522__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext522 :: GPU Core Clocks */
#define acmgt1__ext522__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext522 :: AVG GPU Core Frequency */
#define acmgt1__ext522__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext522 :: AVG GPU Core Frequency */
#define acmgt1__ext522__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext522 :: SLM BYTE READ BANK1 XECORE6 */
#define acmgt1__ext522__slm_byte_read_bank1_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext522 :: LOAD STORE CACHE BYTE READ BANK1 XECORE6 */
#define acmgt1__ext522__load_store_cache_byte_read_bank1_xecore6__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext523 :: GPU Time Elapsed */
#define acmgt1__ext523__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext523 :: GPU Core Clocks */
#define acmgt1__ext523__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext523 :: AVG GPU Core Frequency */
#define acmgt1__ext523__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext523 :: AVG GPU Core Frequency */
#define acmgt1__ext523__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext523 :: SLM BYTE READ BANK1 XECORE7 */
#define acmgt1__ext523__slm_byte_read_bank1_xecore7__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext523 :: LOAD STORE CACHE BYTE READ BANK1 XECORE7 */
#define acmgt1__ext523__load_store_cache_byte_read_bank1_xecore7__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext524 :: GPU Time Elapsed */
#define acmgt1__ext524__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext524 :: GPU Core Clocks */
#define acmgt1__ext524__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext524 :: AVG GPU Core Frequency */
#define acmgt1__ext524__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext524 :: AVG GPU Core Frequency */
#define acmgt1__ext524__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext524 :: SLM BYTE READ BANK2 XECORE0 */
#define acmgt1__ext524__slm_byte_read_bank2_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext524 :: LOAD STORE CACHE BYTE READ BANK2 XECORE0 */
#define acmgt1__ext524__load_store_cache_byte_read_bank2_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext525 :: GPU Time Elapsed */
#define acmgt1__ext525__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext525 :: GPU Core Clocks */
#define acmgt1__ext525__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext525 :: AVG GPU Core Frequency */
#define acmgt1__ext525__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext525 :: AVG GPU Core Frequency */
#define acmgt1__ext525__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext525 :: SLM BYTE READ BANK2 XECORE1 */
#define acmgt1__ext525__slm_byte_read_bank2_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext525 :: LOAD STORE CACHE BYTE READ BANK2 XECORE1 */
#define acmgt1__ext525__load_store_cache_byte_read_bank2_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext526 :: GPU Time Elapsed */
#define acmgt1__ext526__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext526 :: GPU Core Clocks */
#define acmgt1__ext526__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext526 :: AVG GPU Core Frequency */
#define acmgt1__ext526__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext526 :: AVG GPU Core Frequency */
#define acmgt1__ext526__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext526 :: SLM BYTE READ BANK2 XECORE2 */
#define acmgt1__ext526__slm_byte_read_bank2_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext526 :: LOAD STORE CACHE BYTE READ BANK2 XECORE2 */
#define acmgt1__ext526__load_store_cache_byte_read_bank2_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext527 :: GPU Time Elapsed */
#define acmgt1__ext527__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext527 :: GPU Core Clocks */
#define acmgt1__ext527__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext527 :: AVG GPU Core Frequency */
#define acmgt1__ext527__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext527 :: AVG GPU Core Frequency */
#define acmgt1__ext527__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext527 :: SLM BYTE READ BANK2 XECORE3 */
#define acmgt1__ext527__slm_byte_read_bank2_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext527 :: LOAD STORE CACHE BYTE READ BANK2 XECORE3 */
#define acmgt1__ext527__load_store_cache_byte_read_bank2_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext528 :: GPU Time Elapsed */
#define acmgt1__ext528__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext528 :: GPU Core Clocks */
#define acmgt1__ext528__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext528 :: AVG GPU Core Frequency */
#define acmgt1__ext528__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext528 :: AVG GPU Core Frequency */
#define acmgt1__ext528__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext528 :: SLM BYTE READ BANK2 XECORE4 */
#define acmgt1__ext528__slm_byte_read_bank2_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext528 :: LOAD STORE CACHE BYTE READ BANK2 XECORE4 */
#define acmgt1__ext528__load_store_cache_byte_read_bank2_xecore4__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext529 :: GPU Time Elapsed */
#define acmgt1__ext529__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext529 :: GPU Core Clocks */
#define acmgt1__ext529__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext529 :: AVG GPU Core Frequency */
#define acmgt1__ext529__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext529 :: AVG GPU Core Frequency */
#define acmgt1__ext529__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext529 :: SLM BYTE READ BANK2 XECORE5 */
#define acmgt1__ext529__slm_byte_read_bank2_xecore5__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext529 :: LOAD STORE CACHE BYTE READ BANK2 XECORE5 */
#define acmgt1__ext529__load_store_cache_byte_read_bank2_xecore5__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext530 :: GPU Time Elapsed */
#define acmgt1__ext530__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext530 :: GPU Core Clocks */
#define acmgt1__ext530__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext530 :: AVG GPU Core Frequency */
#define acmgt1__ext530__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext530 :: AVG GPU Core Frequency */
#define acmgt1__ext530__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext530 :: SLM BYTE READ BANK2 XECORE6 */
#define acmgt1__ext530__slm_byte_read_bank2_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext530 :: LOAD STORE CACHE BYTE READ BANK2 XECORE6 */
#define acmgt1__ext530__load_store_cache_byte_read_bank2_xecore6__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext531 :: GPU Time Elapsed */
#define acmgt1__ext531__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext531 :: GPU Core Clocks */
#define acmgt1__ext531__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext531 :: AVG GPU Core Frequency */
#define acmgt1__ext531__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext531 :: AVG GPU Core Frequency */
#define acmgt1__ext531__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext531 :: SLM BYTE READ BANK2 XECORE7 */
#define acmgt1__ext531__slm_byte_read_bank2_xecore7__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext531 :: LOAD STORE CACHE BYTE READ BANK2 XECORE7 */
#define acmgt1__ext531__load_store_cache_byte_read_bank2_xecore7__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext532 :: GPU Time Elapsed */
#define acmgt1__ext532__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext532 :: GPU Core Clocks */
#define acmgt1__ext532__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext532 :: AVG GPU Core Frequency */
#define acmgt1__ext532__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext532 :: AVG GPU Core Frequency */
#define acmgt1__ext532__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext532 :: SLM BYTE READ BANK3 XECORE0 */
#define acmgt1__ext532__slm_byte_read_bank3_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext532 :: LOAD STORE CACHE BYTE READ BANK3 XECORE0 */
#define acmgt1__ext532__load_store_cache_byte_read_bank3_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext533 :: GPU Time Elapsed */
#define acmgt1__ext533__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext533 :: GPU Core Clocks */
#define acmgt1__ext533__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext533 :: AVG GPU Core Frequency */
#define acmgt1__ext533__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext533 :: AVG GPU Core Frequency */
#define acmgt1__ext533__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext533 :: SLM BYTE READ BANK3 XECORE1 */
#define acmgt1__ext533__slm_byte_read_bank3_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext533 :: LOAD STORE CACHE BYTE READ BANK3 XECORE1 */
#define acmgt1__ext533__load_store_cache_byte_read_bank3_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext534 :: GPU Time Elapsed */
#define acmgt1__ext534__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext534 :: GPU Core Clocks */
#define acmgt1__ext534__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext534 :: AVG GPU Core Frequency */
#define acmgt1__ext534__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext534 :: AVG GPU Core Frequency */
#define acmgt1__ext534__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext534 :: SLM BYTE READ BANK3 XECORE2 */
#define acmgt1__ext534__slm_byte_read_bank3_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext534 :: LOAD STORE CACHE BYTE READ BANK3 XECORE2 */
#define acmgt1__ext534__load_store_cache_byte_read_bank3_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext535 :: GPU Time Elapsed */
#define acmgt1__ext535__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext535 :: GPU Core Clocks */
#define acmgt1__ext535__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext535 :: AVG GPU Core Frequency */
#define acmgt1__ext535__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext535 :: AVG GPU Core Frequency */
#define acmgt1__ext535__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext535 :: SLM BYTE READ BANK3 XECORE3 */
#define acmgt1__ext535__slm_byte_read_bank3_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext535 :: LOAD STORE CACHE BYTE READ BANK3 XECORE3 */
#define acmgt1__ext535__load_store_cache_byte_read_bank3_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext536 :: GPU Time Elapsed */
#define acmgt1__ext536__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext536 :: GPU Core Clocks */
#define acmgt1__ext536__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext536 :: AVG GPU Core Frequency */
#define acmgt1__ext536__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext536 :: AVG GPU Core Frequency */
#define acmgt1__ext536__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext536 :: SLM BYTE READ BANK3 XECORE4 */
#define acmgt1__ext536__slm_byte_read_bank3_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext536 :: LOAD STORE CACHE BYTE READ BANK3 XECORE4 */
#define acmgt1__ext536__load_store_cache_byte_read_bank3_xecore4__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext537 :: GPU Time Elapsed */
#define acmgt1__ext537__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext537 :: GPU Core Clocks */
#define acmgt1__ext537__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext537 :: AVG GPU Core Frequency */
#define acmgt1__ext537__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext537 :: AVG GPU Core Frequency */
#define acmgt1__ext537__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext537 :: SLM BYTE READ BANK3 XECORE5 */
#define acmgt1__ext537__slm_byte_read_bank3_xecore5__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext537 :: LOAD STORE CACHE BYTE READ BANK3 XECORE5 */
#define acmgt1__ext537__load_store_cache_byte_read_bank3_xecore5__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext538 :: GPU Time Elapsed */
#define acmgt1__ext538__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext538 :: GPU Core Clocks */
#define acmgt1__ext538__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext538 :: AVG GPU Core Frequency */
#define acmgt1__ext538__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext538 :: AVG GPU Core Frequency */
#define acmgt1__ext538__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext538 :: SLM BYTE READ BANK3 XECORE6 */
#define acmgt1__ext538__slm_byte_read_bank3_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext538 :: LOAD STORE CACHE BYTE READ BANK3 XECORE6 */
#define acmgt1__ext538__load_store_cache_byte_read_bank3_xecore6__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext539 :: GPU Time Elapsed */
#define acmgt1__ext539__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext539 :: GPU Core Clocks */
#define acmgt1__ext539__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext539 :: AVG GPU Core Frequency */
#define acmgt1__ext539__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext539 :: AVG GPU Core Frequency */
#define acmgt1__ext539__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext539 :: SLM BYTE READ BANK3 XECORE7 */
#define acmgt1__ext539__slm_byte_read_bank3_xecore7__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext539 :: LOAD STORE CACHE BYTE READ BANK3 XECORE7 */
#define acmgt1__ext539__load_store_cache_byte_read_bank3_xecore7__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext540 :: GPU Time Elapsed */
#define acmgt1__ext540__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext540 :: GPU Core Clocks */
#define acmgt1__ext540__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext540 :: AVG GPU Core Frequency */
#define acmgt1__ext540__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext540 :: AVG GPU Core Frequency */
#define acmgt1__ext540__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext540 :: SLM BYTE WRITE BANK0 XECORE0 */
#define acmgt1__ext540__slm_byte_write_bank0_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext540 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE0 */
#define acmgt1__ext540__load_store_cache_byte_write_bank0_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext541 :: GPU Time Elapsed */
#define acmgt1__ext541__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext541 :: GPU Core Clocks */
#define acmgt1__ext541__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext541 :: AVG GPU Core Frequency */
#define acmgt1__ext541__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext541 :: AVG GPU Core Frequency */
#define acmgt1__ext541__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext541 :: SLM BYTE WRITE BANK0 XECORE1 */
#define acmgt1__ext541__slm_byte_write_bank0_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext541 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE1 */
#define acmgt1__ext541__load_store_cache_byte_write_bank0_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext542 :: GPU Time Elapsed */
#define acmgt1__ext542__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext542 :: GPU Core Clocks */
#define acmgt1__ext542__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext542 :: AVG GPU Core Frequency */
#define acmgt1__ext542__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext542 :: AVG GPU Core Frequency */
#define acmgt1__ext542__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext542 :: SLM BYTE WRITE BANK0 XECORE2 */
#define acmgt1__ext542__slm_byte_write_bank0_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext542 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE2 */
#define acmgt1__ext542__load_store_cache_byte_write_bank0_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext543 :: GPU Time Elapsed */
#define acmgt1__ext543__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext543 :: GPU Core Clocks */
#define acmgt1__ext543__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext543 :: AVG GPU Core Frequency */
#define acmgt1__ext543__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext543 :: AVG GPU Core Frequency */
#define acmgt1__ext543__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext543 :: SLM BYTE WRITE BANK0 XECORE3 */
#define acmgt1__ext543__slm_byte_write_bank0_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext543 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE3 */
#define acmgt1__ext543__load_store_cache_byte_write_bank0_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext544 :: GPU Time Elapsed */
#define acmgt1__ext544__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext544 :: GPU Core Clocks */
#define acmgt1__ext544__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext544 :: AVG GPU Core Frequency */
#define acmgt1__ext544__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext544 :: AVG GPU Core Frequency */
#define acmgt1__ext544__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext544 :: SLM BYTE WRITE BANK0 XECORE4 */
#define acmgt1__ext544__slm_byte_write_bank0_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext544 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE4 */
#define acmgt1__ext544__load_store_cache_byte_write_bank0_xecore4__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext545 :: GPU Time Elapsed */
#define acmgt1__ext545__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext545 :: GPU Core Clocks */
#define acmgt1__ext545__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext545 :: AVG GPU Core Frequency */
#define acmgt1__ext545__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext545 :: AVG GPU Core Frequency */
#define acmgt1__ext545__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext545 :: SLM BYTE WRITE BANK0 XECORE5 */
#define acmgt1__ext545__slm_byte_write_bank0_xecore5__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext545 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE5 */
#define acmgt1__ext545__load_store_cache_byte_write_bank0_xecore5__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext546 :: GPU Time Elapsed */
#define acmgt1__ext546__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext546 :: GPU Core Clocks */
#define acmgt1__ext546__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext546 :: AVG GPU Core Frequency */
#define acmgt1__ext546__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext546 :: AVG GPU Core Frequency */
#define acmgt1__ext546__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext546 :: SLM BYTE WRITE BANK0 XECORE6 */
#define acmgt1__ext546__slm_byte_write_bank0_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext546 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE6 */
#define acmgt1__ext546__load_store_cache_byte_write_bank0_xecore6__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext547 :: GPU Time Elapsed */
#define acmgt1__ext547__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext547 :: GPU Core Clocks */
#define acmgt1__ext547__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext547 :: AVG GPU Core Frequency */
#define acmgt1__ext547__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext547 :: AVG GPU Core Frequency */
#define acmgt1__ext547__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext547 :: SLM BYTE WRITE BANK0 XECORE7 */
#define acmgt1__ext547__slm_byte_write_bank0_xecore7__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext547 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE7 */
#define acmgt1__ext547__load_store_cache_byte_write_bank0_xecore7__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext548 :: GPU Time Elapsed */
#define acmgt1__ext548__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext548 :: GPU Core Clocks */
#define acmgt1__ext548__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext548 :: AVG GPU Core Frequency */
#define acmgt1__ext548__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext548 :: AVG GPU Core Frequency */
#define acmgt1__ext548__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext548 :: SLM BYTE WRITE BANK1 XECORE0 */
#define acmgt1__ext548__slm_byte_write_bank1_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext548 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE0 */
#define acmgt1__ext548__load_store_cache_byte_write_bank1_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext549 :: GPU Time Elapsed */
#define acmgt1__ext549__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext549 :: GPU Core Clocks */
#define acmgt1__ext549__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext549 :: AVG GPU Core Frequency */
#define acmgt1__ext549__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext549 :: AVG GPU Core Frequency */
#define acmgt1__ext549__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext549 :: SLM BYTE WRITE BANK1 XECORE1 */
#define acmgt1__ext549__slm_byte_write_bank1_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext549 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE1 */
#define acmgt1__ext549__load_store_cache_byte_write_bank1_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext550 :: GPU Time Elapsed */
#define acmgt1__ext550__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext550 :: GPU Core Clocks */
#define acmgt1__ext550__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext550 :: AVG GPU Core Frequency */
#define acmgt1__ext550__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext550 :: AVG GPU Core Frequency */
#define acmgt1__ext550__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext550 :: SLM BYTE WRITE BANK1 XECORE2 */
#define acmgt1__ext550__slm_byte_write_bank1_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext550 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE2 */
#define acmgt1__ext550__load_store_cache_byte_write_bank1_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext551 :: GPU Time Elapsed */
#define acmgt1__ext551__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext551 :: GPU Core Clocks */
#define acmgt1__ext551__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext551 :: AVG GPU Core Frequency */
#define acmgt1__ext551__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext551 :: AVG GPU Core Frequency */
#define acmgt1__ext551__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext551 :: SLM BYTE WRITE BANK1 XECORE3 */
#define acmgt1__ext551__slm_byte_write_bank1_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext551 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE3 */
#define acmgt1__ext551__load_store_cache_byte_write_bank1_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext552 :: GPU Time Elapsed */
#define acmgt1__ext552__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext552 :: GPU Core Clocks */
#define acmgt1__ext552__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext552 :: AVG GPU Core Frequency */
#define acmgt1__ext552__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext552 :: AVG GPU Core Frequency */
#define acmgt1__ext552__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext552 :: SLM BYTE WRITE BANK1 XECORE4 */
#define acmgt1__ext552__slm_byte_write_bank1_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext552 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE4 */
#define acmgt1__ext552__load_store_cache_byte_write_bank1_xecore4__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext553 :: GPU Time Elapsed */
#define acmgt1__ext553__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext553 :: GPU Core Clocks */
#define acmgt1__ext553__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext553 :: AVG GPU Core Frequency */
#define acmgt1__ext553__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext553 :: AVG GPU Core Frequency */
#define acmgt1__ext553__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext553 :: SLM BYTE WRITE BANK1 XECORE5 */
#define acmgt1__ext553__slm_byte_write_bank1_xecore5__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext553 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE5 */
#define acmgt1__ext553__load_store_cache_byte_write_bank1_xecore5__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext554 :: GPU Time Elapsed */
#define acmgt1__ext554__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext554 :: GPU Core Clocks */
#define acmgt1__ext554__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext554 :: AVG GPU Core Frequency */
#define acmgt1__ext554__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext554 :: AVG GPU Core Frequency */
#define acmgt1__ext554__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext554 :: SLM BYTE WRITE BANK1 XECORE6 */
#define acmgt1__ext554__slm_byte_write_bank1_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext554 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE6 */
#define acmgt1__ext554__load_store_cache_byte_write_bank1_xecore6__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext555 :: GPU Time Elapsed */
#define acmgt1__ext555__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext555 :: GPU Core Clocks */
#define acmgt1__ext555__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext555 :: AVG GPU Core Frequency */
#define acmgt1__ext555__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext555 :: AVG GPU Core Frequency */
#define acmgt1__ext555__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext555 :: SLM BYTE WRITE BANK1 XECORE7 */
#define acmgt1__ext555__slm_byte_write_bank1_xecore7__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext555 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE7 */
#define acmgt1__ext555__load_store_cache_byte_write_bank1_xecore7__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext556 :: GPU Time Elapsed */
#define acmgt1__ext556__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext556 :: GPU Core Clocks */
#define acmgt1__ext556__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext556 :: AVG GPU Core Frequency */
#define acmgt1__ext556__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext556 :: AVG GPU Core Frequency */
#define acmgt1__ext556__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext556 :: SLM BYTE WRITE BANK2 XECORE0 */
#define acmgt1__ext556__slm_byte_write_bank2_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext556 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE0 */
#define acmgt1__ext556__load_store_cache_byte_write_bank2_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext557 :: GPU Time Elapsed */
#define acmgt1__ext557__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext557 :: GPU Core Clocks */
#define acmgt1__ext557__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext557 :: AVG GPU Core Frequency */
#define acmgt1__ext557__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext557 :: AVG GPU Core Frequency */
#define acmgt1__ext557__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext557 :: SLM BYTE WRITE BANK2 XECORE1 */
#define acmgt1__ext557__slm_byte_write_bank2_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext557 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE1 */
#define acmgt1__ext557__load_store_cache_byte_write_bank2_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext558 :: GPU Time Elapsed */
#define acmgt1__ext558__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext558 :: GPU Core Clocks */
#define acmgt1__ext558__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext558 :: AVG GPU Core Frequency */
#define acmgt1__ext558__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext558 :: AVG GPU Core Frequency */
#define acmgt1__ext558__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext558 :: SLM BYTE WRITE BANK2 XECORE2 */
#define acmgt1__ext558__slm_byte_write_bank2_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext558 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE2 */
#define acmgt1__ext558__load_store_cache_byte_write_bank2_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext559 :: GPU Time Elapsed */
#define acmgt1__ext559__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext559 :: GPU Core Clocks */
#define acmgt1__ext559__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext559 :: AVG GPU Core Frequency */
#define acmgt1__ext559__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext559 :: AVG GPU Core Frequency */
#define acmgt1__ext559__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext559 :: SLM BYTE WRITE BANK2 XECORE3 */
#define acmgt1__ext559__slm_byte_write_bank2_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext559 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE3 */
#define acmgt1__ext559__load_store_cache_byte_write_bank2_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext560 :: GPU Time Elapsed */
#define acmgt1__ext560__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext560 :: GPU Core Clocks */
#define acmgt1__ext560__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext560 :: AVG GPU Core Frequency */
#define acmgt1__ext560__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext560 :: AVG GPU Core Frequency */
#define acmgt1__ext560__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext560 :: SLM BYTE WRITE BANK2 XECORE4 */
#define acmgt1__ext560__slm_byte_write_bank2_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext560 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE4 */
#define acmgt1__ext560__load_store_cache_byte_write_bank2_xecore4__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext561 :: GPU Time Elapsed */
#define acmgt1__ext561__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext561 :: GPU Core Clocks */
#define acmgt1__ext561__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext561 :: AVG GPU Core Frequency */
#define acmgt1__ext561__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext561 :: AVG GPU Core Frequency */
#define acmgt1__ext561__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext561 :: SLM BYTE WRITE BANK2 XECORE5 */
#define acmgt1__ext561__slm_byte_write_bank2_xecore5__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext561 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE5 */
#define acmgt1__ext561__load_store_cache_byte_write_bank2_xecore5__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext562 :: GPU Time Elapsed */
#define acmgt1__ext562__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext562 :: GPU Core Clocks */
#define acmgt1__ext562__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext562 :: AVG GPU Core Frequency */
#define acmgt1__ext562__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext562 :: AVG GPU Core Frequency */
#define acmgt1__ext562__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext562 :: SLM BYTE WRITE BANK2 XECORE6 */
#define acmgt1__ext562__slm_byte_write_bank2_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext562 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE6 */
#define acmgt1__ext562__load_store_cache_byte_write_bank2_xecore6__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext563 :: GPU Time Elapsed */
#define acmgt1__ext563__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext563 :: GPU Core Clocks */
#define acmgt1__ext563__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext563 :: AVG GPU Core Frequency */
#define acmgt1__ext563__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext563 :: AVG GPU Core Frequency */
#define acmgt1__ext563__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext563 :: SLM BYTE WRITE BANK2 XECORE7 */
#define acmgt1__ext563__slm_byte_write_bank2_xecore7__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext563 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE7 */
#define acmgt1__ext563__load_store_cache_byte_write_bank2_xecore7__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext564 :: GPU Time Elapsed */
#define acmgt1__ext564__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext564 :: GPU Core Clocks */
#define acmgt1__ext564__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext564 :: AVG GPU Core Frequency */
#define acmgt1__ext564__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext564 :: AVG GPU Core Frequency */
#define acmgt1__ext564__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext564 :: SLM BYTE WRITE BANK3 XECORE0 */
#define acmgt1__ext564__slm_byte_write_bank3_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext564 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE0 */
#define acmgt1__ext564__load_store_cache_byte_write_bank3_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext565 :: GPU Time Elapsed */
#define acmgt1__ext565__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext565 :: GPU Core Clocks */
#define acmgt1__ext565__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext565 :: AVG GPU Core Frequency */
#define acmgt1__ext565__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext565 :: AVG GPU Core Frequency */
#define acmgt1__ext565__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext565 :: SLM BYTE WRITE BANK3 XECORE1 */
#define acmgt1__ext565__slm_byte_write_bank3_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext565 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE1 */
#define acmgt1__ext565__load_store_cache_byte_write_bank3_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext566 :: GPU Time Elapsed */
#define acmgt1__ext566__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext566 :: GPU Core Clocks */
#define acmgt1__ext566__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext566 :: AVG GPU Core Frequency */
#define acmgt1__ext566__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext566 :: AVG GPU Core Frequency */
#define acmgt1__ext566__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext566 :: SLM BYTE WRITE BANK3 XECORE2 */
#define acmgt1__ext566__slm_byte_write_bank3_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext566 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE2 */
#define acmgt1__ext566__load_store_cache_byte_write_bank3_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext567 :: GPU Time Elapsed */
#define acmgt1__ext567__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext567 :: GPU Core Clocks */
#define acmgt1__ext567__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext567 :: AVG GPU Core Frequency */
#define acmgt1__ext567__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext567 :: AVG GPU Core Frequency */
#define acmgt1__ext567__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext567 :: SLM BYTE WRITE BANK3 XECORE3 */
#define acmgt1__ext567__slm_byte_write_bank3_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext567 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE3 */
#define acmgt1__ext567__load_store_cache_byte_write_bank3_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext568 :: GPU Time Elapsed */
#define acmgt1__ext568__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext568 :: GPU Core Clocks */
#define acmgt1__ext568__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext568 :: AVG GPU Core Frequency */
#define acmgt1__ext568__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext568 :: AVG GPU Core Frequency */
#define acmgt1__ext568__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext568 :: SLM BYTE WRITE BANK3 XECORE4 */
#define acmgt1__ext568__slm_byte_write_bank3_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext568 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE4 */
#define acmgt1__ext568__load_store_cache_byte_write_bank3_xecore4__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext569 :: GPU Time Elapsed */
#define acmgt1__ext569__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext569 :: GPU Core Clocks */
#define acmgt1__ext569__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext569 :: AVG GPU Core Frequency */
#define acmgt1__ext569__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext569 :: AVG GPU Core Frequency */
#define acmgt1__ext569__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext569 :: SLM BYTE WRITE BANK3 XECORE5 */
#define acmgt1__ext569__slm_byte_write_bank3_xecore5__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext569 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE5 */
#define acmgt1__ext569__load_store_cache_byte_write_bank3_xecore5__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext570 :: GPU Time Elapsed */
#define acmgt1__ext570__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext570 :: GPU Core Clocks */
#define acmgt1__ext570__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext570 :: AVG GPU Core Frequency */
#define acmgt1__ext570__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext570 :: AVG GPU Core Frequency */
#define acmgt1__ext570__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext570 :: SLM BYTE WRITE BANK3 XECORE6 */
#define acmgt1__ext570__slm_byte_write_bank3_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext570 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE6 */
#define acmgt1__ext570__load_store_cache_byte_write_bank3_xecore6__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext571 :: GPU Time Elapsed */
#define acmgt1__ext571__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext571 :: GPU Core Clocks */
#define acmgt1__ext571__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext571 :: AVG GPU Core Frequency */
#define acmgt1__ext571__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext571 :: AVG GPU Core Frequency */
#define acmgt1__ext571__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext571 :: SLM BYTE WRITE BANK3 XECORE7 */
#define acmgt1__ext571__slm_byte_write_bank3_xecore7__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext571 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE7 */
#define acmgt1__ext571__load_store_cache_byte_write_bank3_xecore7__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext1000 :: GPU Time Elapsed */
#define acmgt1__ext1000__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1000 :: GPU Core Clocks */
#define acmgt1__ext1000__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1000 :: AVG GPU Core Frequency */
#define acmgt1__ext1000__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1000 :: AVG GPU Core Frequency */
#define acmgt1__ext1000__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1000 :: XVE ACTIVE */
#define acmgt1__ext1000__xve_active__read \
   bdw__render_basic__eu_active__read

/* Ext1000 :: XVE STALL */
#define acmgt1__ext1000__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Ext1000 :: XVE THREADS OCCUPANCY ALL */
static float
acmgt1__ext1000__xve_threads_occupancy_all__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 8 A 14 READ FMUL $VectorEngineThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->a_offset + 14];
   double tmp1 = 8 * tmp0;
   double tmp2 = tmp1;
   double tmp3 = perf->devinfo.num_thread_per_eu;
   double tmp4 = tmp3 ? tmp2 / tmp3 : 0;
   uint64_t tmp5 = tmp4;
   uint64_t tmp6 = perf->sys_vars.n_eus;
   uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0;
   uint64_t tmp8 = tmp7 * 100;
   double tmp9 = tmp8;
   double tmp10 = acmgt1__ext1000__gpu_core_clocks__read(perf, query, results);
   double tmp11 = tmp10 ? tmp9 / tmp10 : 0;

   return tmp11;
}

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL */
static uint64_t
acmgt1__ext1000__xve_inst_executed_alu0_all__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: A 9 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 9];

   return tmp0;
}

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt1__ext1000__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt1__ext1000__xve_inst_executed_alu1_all__read \
   hsw__render_basic__hs_threads__read

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt1__ext1000__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED XMX ALL */
#define acmgt1__ext1000__xve_inst_executed_xmx_all__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1000 :: XVE INST EXECUTED XMX ALL */
#define acmgt1__ext1000__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED SEND ALL */
#define acmgt1__ext1000__xve_inst_executed_send_all__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1000 :: XVE INST EXECUTED SEND ALL */
#define acmgt1__ext1000__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL */
#define acmgt1__ext1000__xve_inst_executed_control_all__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL */
#define acmgt1__ext1000__xve_inst_executed_control_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE */
#define acmgt1__ext1000__xve_pipe_alu0_and_alu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE */
#define acmgt1__ext1000__xve_pipe_alu0_and_xmx_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define acmgt1__ext1000__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define acmgt1__ext1000__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1000 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define acmgt1__ext1000__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1000 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define acmgt1__ext1000__xve_inst_executed_send_all_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL UTILIZATION */
#define acmgt1__ext1000__xve_inst_executed_control_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1000 :: XVE ACTIVE CYCLES */
static uint64_t
acmgt1__ext1000__xve_active_cycles__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: A 7 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 7];

   return tmp0;
}

/* Ext1000 :: XVE ACTIVE CYCLES */
#define acmgt1__ext1000__xve_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE STALL CYCLES */
static uint64_t
acmgt1__ext1000__xve_stall_cycles__read(UNUSED struct intel_perf_config *perf,
                                        const struct intel_perf_query_info *query,
                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: A 8 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 8];

   return tmp0;
}

/* Ext1000 :: XVE STALL CYCLES */
#define acmgt1__ext1000__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE THREADS OCCUPANCY CYCLES ALL */
static uint64_t
acmgt1__ext1000__xve_threads_occupancy_cycles_all__read(UNUSED struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: 8  A 14 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 14];
   uint64_t tmp1 = 8 * tmp0;

   return tmp1;
}

/* Ext1000 :: XVE THREADS OCCUPANCY CYCLES ALL */
static uint64_t
acmgt1__ext1000__xve_threads_occupancy_cycles_all__max(struct intel_perf_config *perf,
                                                        const struct intel_perf_query_info *query,
                                                        const struct intel_perf_query_result *results)
{
   /* RPN equation: $GpuCoreClocks $VectorEngineTotalCount $VectorEngineThreadsCount UMUL UMUL */
   uint64_t tmp0 = perf->sys_vars.n_eus * perf->devinfo.num_thread_per_eu;
   uint64_t tmp1 = acmgt1__ext1000__gpu_core_clocks__read(perf, query, results) * tmp0;

   return tmp1;
}

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
static uint64_t
acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read(UNUSED struct intel_perf_config *perf,
                                                            const struct intel_perf_query_info *query,
                                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: A 16 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 16];

   return tmp0;
}

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
#define acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define acmgt1__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read \
   hsw__render_basic__ds_threads__read

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define acmgt1__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: GPU Time Elapsed */
#define acmgt1__ext1001__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1001 :: GPU Core Clocks */
#define acmgt1__ext1001__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1001 :: AVG GPU Core Frequency */
#define acmgt1__ext1001__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1001 :: AVG GPU Core Frequency */
#define acmgt1__ext1001__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1001 :: XVE INST EXECUTED ALU0 VS */
#define acmgt1__ext1001__xve_inst_executed_alu0_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU0 VS */
#define acmgt1__ext1001__xve_inst_executed_alu0_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 HS */
#define acmgt1__ext1001__xve_inst_executed_alu0_hs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU0 HS */
#define acmgt1__ext1001__xve_inst_executed_alu0_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 DS */
#define acmgt1__ext1001__xve_inst_executed_alu0_ds__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 DS */
#define acmgt1__ext1001__xve_inst_executed_alu0_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 FS */
#define acmgt1__ext1001__xve_inst_executed_alu0_ps__read \
   hsw__render_basic__hs_threads__read

/* Ext1001 :: XVE INST EXECUTED ALU0 FS */
#define acmgt1__ext1001__xve_inst_executed_alu0_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 CS */
#define acmgt1__ext1001__xve_inst_executed_alu0_cs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 CS */
#define acmgt1__ext1001__xve_inst_executed_alu0_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define acmgt1__ext1001__xve_inst_executed_alu0_async_cs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define acmgt1__ext1001__xve_inst_executed_alu0_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 VS */
#define acmgt1__ext1001__xve_inst_executed_alu1_vs__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1001 :: XVE INST EXECUTED ALU1 VS */
#define acmgt1__ext1001__xve_inst_executed_alu1_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 HS */
#define acmgt1__ext1001__xve_inst_executed_alu1_hs__read \
   hsw__render_basic__ds_threads__read

/* Ext1001 :: XVE INST EXECUTED ALU1 HS */
#define acmgt1__ext1001__xve_inst_executed_alu1_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 DS */
#define acmgt1__ext1001__xve_inst_executed_alu1_ds__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1001 :: XVE INST EXECUTED ALU1 DS */
#define acmgt1__ext1001__xve_inst_executed_alu1_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 FS */
#define acmgt1__ext1001__xve_inst_executed_alu1_ps__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU1 FS */
#define acmgt1__ext1001__xve_inst_executed_alu1_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 CS */
static uint64_t
acmgt1__ext1001__xve_inst_executed_alu1_cs__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: A 17 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 17];

   return tmp0;
}

/* Ext1001 :: XVE INST EXECUTED ALU1 CS */
#define acmgt1__ext1001__xve_inst_executed_alu1_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS */
static uint64_t
acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: A 18 READ */
   uint64_t tmp0 = results->accumulator[query->a_offset + 18];

   return tmp0;
}

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS */
#define acmgt1__ext1001__xve_inst_executed_alu1_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 VS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu0_vs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 HS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu0_hs_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1001 :: XVE INST EXECUTED ALU0 DS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu0_ds_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 FS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu0_ps_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 CS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu0_cs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu0_async_cs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 VS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu1_vs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1001 :: XVE INST EXECUTED ALU1 HS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu1_hs_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 DS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu1_ds_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1001 :: XVE INST EXECUTED ALU1 FS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu1_ps_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 CS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu1_cs_utilization__read \
   bdw__render_basic__ps_send_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION */
#define acmgt1__ext1001__xve_inst_executed_alu1_async_cs_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1002 :: GPU Time Elapsed */
#define acmgt1__ext1002__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1002 :: GPU Core Clocks */
#define acmgt1__ext1002__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1002 :: AVG GPU Core Frequency */
#define acmgt1__ext1002__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1002 :: AVG GPU Core Frequency */
#define acmgt1__ext1002__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS UTILIZATION */
#define acmgt1__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS UTILIZATION */
#define acmgt1__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS UTILIZATION */
#define acmgt1__ext1002__xve_inst_executed_send_rt_ahs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS UTILIZATION */
#define acmgt1__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS UTILIZATION */
#define acmgt1__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS UTILIZATION */
#define acmgt1__ext1002__xve_inst_executed_send_rt_chs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS UTILIZATION */
#define acmgt1__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS UTILIZATION */
#define acmgt1__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1002 :: XVE INST EXECUTED SEND RT MS UTILIZATION */
#define acmgt1__ext1002__xve_inst_executed_send_rt_ms_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS */
#define acmgt1__ext1002__xve_inst_executed_alu0_rt_ahs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS */
#define acmgt1__ext1002__xve_inst_executed_alu0_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS */
#define acmgt1__ext1002__xve_inst_executed_alu1_rt_ahs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS */
#define acmgt1__ext1002__xve_inst_executed_alu1_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS */
#define acmgt1__ext1002__xve_inst_executed_send_rt_ahs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS */
#define acmgt1__ext1002__xve_inst_executed_send_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS */
#define acmgt1__ext1002__xve_inst_executed_alu0_rt_chs__read \
   hsw__render_basic__hs_threads__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS */
#define acmgt1__ext1002__xve_inst_executed_alu0_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS */
#define acmgt1__ext1002__xve_inst_executed_alu1_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS */
#define acmgt1__ext1002__xve_inst_executed_alu1_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS */
#define acmgt1__ext1002__xve_inst_executed_send_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS */
#define acmgt1__ext1002__xve_inst_executed_send_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS */
#define acmgt1__ext1002__xve_inst_executed_alu0_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS */
#define acmgt1__ext1002__xve_inst_executed_alu0_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS */
#define acmgt1__ext1002__xve_inst_executed_alu1_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS */
#define acmgt1__ext1002__xve_inst_executed_alu1_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT MS */
#define acmgt1__ext1002__xve_inst_executed_send_rt_ms__read \
   hsw__render_basic__ds_threads__read

/* Ext1002 :: XVE INST EXECUTED SEND RT MS */
#define acmgt1__ext1002__xve_inst_executed_send_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: GPU Time Elapsed */
#define acmgt1__ext1004__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1004 :: GPU Core Clocks */
#define acmgt1__ext1004__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1004 :: AVG GPU Core Frequency */
#define acmgt1__ext1004__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1004 :: AVG GPU Core Frequency */
#define acmgt1__ext1004__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1004 :: XVE STALL */
#define acmgt1__ext1004__xve_stall__read \
   bdw__render_basic__eu_active__read

/* Ext1004 :: XVE STALL ASYNC CS */
#define acmgt1__ext1004__xve_stall_async_cs__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1004 :: XVE STALL CS */
#define acmgt1__ext1004__xve_stall_cs__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1004 :: XVE STALL DS */
#define acmgt1__ext1004__xve_stall_ds__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1004 :: XVE STALL HS */
#define acmgt1__ext1004__xve_stall_hs__read \
   bdw__render_basic__vs_send_active__read

/* Ext1004 :: XVE STALL MS */
#define acmgt1__ext1004__xve_stall_ms__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1004 :: XVE STALL FS */
#define acmgt1__ext1004__xve_stall_ps__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1004 :: XVE STALL TS */
#define acmgt1__ext1004__xve_stall_ts__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1004 :: XVE STALL VS */
#define acmgt1__ext1004__xve_stall_vs__read \
   bdw__render_basic__eu_stall__read

/* Ext1004 :: XVE STALL RT */
#define acmgt1__ext1004__xve_stall_rt__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1004 :: XVE STALL CYCLES */
#define acmgt1__ext1004__xve_stall_cycles__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1004 :: XVE STALL CYCLES */
#define acmgt1__ext1004__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES ASYNC CS */
#define acmgt1__ext1004__xve_stall_cycles_async_cs__read \
   hsw__render_basic__ds_threads__read

/* Ext1004 :: XVE STALL CYCLES ASYNC CS */
#define acmgt1__ext1004__xve_stall_cycles_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES CS */
#define acmgt1__ext1004__xve_stall_cycles_cs__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1004 :: XVE STALL CYCLES CS */
#define acmgt1__ext1004__xve_stall_cycles_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES DS */
#define acmgt1__ext1004__xve_stall_cycles_ds__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1004 :: XVE STALL CYCLES DS */
#define acmgt1__ext1004__xve_stall_cycles_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES HS */
#define acmgt1__ext1004__xve_stall_cycles_hs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1004 :: XVE STALL CYCLES HS */
#define acmgt1__ext1004__xve_stall_cycles_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES MS */
#define acmgt1__ext1004__xve_stall_cycles_ms__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1004 :: XVE STALL CYCLES MS */
#define acmgt1__ext1004__xve_stall_cycles_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES FS */
#define acmgt1__ext1004__xve_stall_cycles_ps__read \
   hsw__render_basic__hs_threads__read

/* Ext1004 :: XVE STALL CYCLES FS */
#define acmgt1__ext1004__xve_stall_cycles_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES TS */
#define acmgt1__ext1004__xve_stall_cycles_ts__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1004 :: XVE STALL CYCLES TS */
#define acmgt1__ext1004__xve_stall_cycles_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES VS */
#define acmgt1__ext1004__xve_stall_cycles_vs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1004 :: XVE STALL CYCLES VS */
#define acmgt1__ext1004__xve_stall_cycles_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES RT */
#define acmgt1__ext1004__xve_stall_cycles_rt__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1004 :: XVE STALL CYCLES RT */
#define acmgt1__ext1004__xve_stall_cycles_rt__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: GPU Time Elapsed */
#define acmgt1__ext1005__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1005 :: GPU Core Clocks */
#define acmgt1__ext1005__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1005 :: AVG GPU Core Frequency */
#define acmgt1__ext1005__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1005 :: AVG GPU Core Frequency */
#define acmgt1__ext1005__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt1__ext1005__xve_inst_executed_alu0_all__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt1__ext1005__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP16 */
#define acmgt1__ext1005__xve_inst_executed_fp16__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1005 :: XVE INST EXECUTED FP16 */
#define acmgt1__ext1005__xve_inst_executed_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP32 */
#define acmgt1__ext1005__xve_inst_executed_fp32__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1005 :: XVE INST EXECUTED FP32 */
#define acmgt1__ext1005__xve_inst_executed_fp32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP64 */
#define acmgt1__ext1005__xve_inst_executed_fp64__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1005 :: XVE INST EXECUTED FP64 */
#define acmgt1__ext1005__xve_inst_executed_fp64__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt1__ext1005__xve_inst_executed_alu1_all__read \
   acmgt1__ext1001__xve_inst_executed_alu1_cs__read

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt1__ext1005__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED INT16 */
#define acmgt1__ext1005__xve_inst_executed_int16__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1005 :: XVE INST EXECUTED INT16 */
#define acmgt1__ext1005__xve_inst_executed_int16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED INT32 */
#define acmgt1__ext1005__xve_inst_executed_int32__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1005 :: XVE INST EXECUTED INT32 */
#define acmgt1__ext1005__xve_inst_executed_int32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED MATH */
#define acmgt1__ext1005__xve_inst_executed_math__read \
   hsw__render_basic__hs_threads__read

/* Ext1005 :: XVE INST EXECUTED MATH */
#define acmgt1__ext1005__xve_inst_executed_math__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX ALL */
#define acmgt1__ext1005__xve_inst_executed_xmx_all__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1005 :: XVE INST EXECUTED XMX ALL */
#define acmgt1__ext1005__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX BF16 */
#define acmgt1__ext1005__xve_inst_executed_xmx_bf16__read \
   hsw__render_basic__ds_threads__read

/* Ext1005 :: XVE INST EXECUTED XMX BF16 */
#define acmgt1__ext1005__xve_inst_executed_xmx_bf16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX FP16 */
#define acmgt1__ext1005__xve_inst_executed_xmx_fp16__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1005 :: XVE INST EXECUTED XMX FP16 */
#define acmgt1__ext1005__xve_inst_executed_xmx_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX INT8 */
#define acmgt1__ext1005__xve_inst_executed_xmx_int8__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1005 :: XVE INST EXECUTED XMX INT8 */
#define acmgt1__ext1005__xve_inst_executed_xmx_int8__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1005 :: XVE INST EXECUTED FP16 UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_fp16_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1005 :: XVE INST EXECUTED FP32 UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_fp32_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1005 :: XVE INST EXECUTED FP64 UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_fp64_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__ps_send_active__read

/* Ext1005 :: XVE INST EXECUTED INT16 UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_int16_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1005 :: XVE INST EXECUTED INT32 UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_int32_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1005 :: XVE INST EXECUTED MATH UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_math_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1005 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1005 :: XVE INST EXECUTED XMX BF16 UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_xmx_bf16_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1005 :: XVE INST EXECUTED XMX FP16 UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_xmx_fp16_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1005 :: XVE INST EXECUTED XMX INT8 UTILIZATION */
#define acmgt1__ext1005__xve_inst_executed_xmx_int8_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1006 :: GPU Time Elapsed */
#define acmgt1__ext1006__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1006 :: GPU Core Clocks */
#define acmgt1__ext1006__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1006 :: AVG GPU Core Frequency */
#define acmgt1__ext1006__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1006 :: AVG GPU Core Frequency */
#define acmgt1__ext1006__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1006 :: XVE INST EXECUTED SEND ALL */
#define acmgt1__ext1006__xve_inst_executed_send_all__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND ALL */
#define acmgt1__ext1006__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS */
#define acmgt1__ext1006__xve_inst_executed_send_async_cs__read \
   hsw__render_basic__ds_threads__read

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS */
#define acmgt1__ext1006__xve_inst_executed_send_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND CS */
#define acmgt1__ext1006__xve_inst_executed_send_cs__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1006 :: XVE INST EXECUTED SEND CS */
#define acmgt1__ext1006__xve_inst_executed_send_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND DS */
#define acmgt1__ext1006__xve_inst_executed_send_ds__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1006 :: XVE INST EXECUTED SEND DS */
#define acmgt1__ext1006__xve_inst_executed_send_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND GS */
#define acmgt1__ext1006__xve_inst_executed_send_gs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1006 :: XVE INST EXECUTED SEND GS */
#define acmgt1__ext1006__xve_inst_executed_send_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND HS */
#define acmgt1__ext1006__xve_inst_executed_send_hs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1006 :: XVE INST EXECUTED SEND HS */
#define acmgt1__ext1006__xve_inst_executed_send_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND MS */
#define acmgt1__ext1006__xve_inst_executed_send_ms__read \
   hsw__render_basic__hs_threads__read

/* Ext1006 :: XVE INST EXECUTED SEND MS */
#define acmgt1__ext1006__xve_inst_executed_send_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND FS */
#define acmgt1__ext1006__xve_inst_executed_send_ps__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1006 :: XVE INST EXECUTED SEND FS */
#define acmgt1__ext1006__xve_inst_executed_send_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND TS */
#define acmgt1__ext1006__xve_inst_executed_send_ts__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND TS */
#define acmgt1__ext1006__xve_inst_executed_send_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND VS */
#define acmgt1__ext1006__xve_inst_executed_send_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND VS */
#define acmgt1__ext1006__xve_inst_executed_send_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_all_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_async_cs_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1006 :: XVE INST EXECUTED SEND CS UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_cs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1006 :: XVE INST EXECUTED SEND DS UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_ds_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1006 :: XVE INST EXECUTED SEND GS UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_gs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1006 :: XVE INST EXECUTED SEND HS UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_hs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1006 :: XVE INST EXECUTED SEND MS UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_ms_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1006 :: XVE INST EXECUTED SEND FS UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_ps_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1006 :: XVE INST EXECUTED SEND TS UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_ts_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1006 :: XVE INST EXECUTED SEND VS UTILIZATION */
#define acmgt1__ext1006__xve_inst_executed_send_vs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1007 :: GPU Time Elapsed */
#define acmgt1__ext1007__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1007 :: GPU Core Clocks */
#define acmgt1__ext1007__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1007 :: AVG GPU Core Frequency */
#define acmgt1__ext1007__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1007 :: AVG GPU Core Frequency */
#define acmgt1__ext1007__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1007 :: XVE STALL GS */
#define acmgt1__ext1007__xve_stall_gs__read \
   bdw__render_basic__eu_stall__read

/* Ext1007 :: XVE INST EXECUTED ALU0 GS */
#define acmgt1__ext1007__xve_inst_executed_alu0_gs__read \
   hsw__render_basic__hs_threads__read

/* Ext1007 :: XVE INST EXECUTED ALU0 GS */
#define acmgt1__ext1007__xve_inst_executed_alu0_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 GS */
#define acmgt1__ext1007__xve_inst_executed_alu1_gs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 GS */
#define acmgt1__ext1007__xve_inst_executed_alu1_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE STALL CYCLES GS */
#define acmgt1__ext1007__xve_stall_cycles_gs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1007 :: XVE STALL CYCLES GS */
#define acmgt1__ext1007__xve_stall_cycles_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 MS */
#define acmgt1__ext1007__xve_inst_executed_alu0_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1007 :: XVE INST EXECUTED ALU0 MS */
#define acmgt1__ext1007__xve_inst_executed_alu0_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 TS */
#define acmgt1__ext1007__xve_inst_executed_alu0_ts__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1007 :: XVE INST EXECUTED ALU0 TS */
#define acmgt1__ext1007__xve_inst_executed_alu0_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 MS */
#define acmgt1__ext1007__xve_inst_executed_alu1_ms__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 MS */
#define acmgt1__ext1007__xve_inst_executed_alu1_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 TS */
#define acmgt1__ext1007__xve_inst_executed_alu1_ts__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 TS */
#define acmgt1__ext1007__xve_inst_executed_alu1_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 GS UTILIZATION */
#define acmgt1__ext1007__xve_inst_executed_alu0_gs_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1007 :: XVE INST EXECUTED ALU1 GS UTILIZATION */
#define acmgt1__ext1007__xve_inst_executed_alu1_gs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1007 :: XVE INST EXECUTED ALU0 MS UTILIZATION */
#define acmgt1__ext1007__xve_inst_executed_alu0_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1007 :: XVE INST EXECUTED ALU0 TS UTILIZATION */
#define acmgt1__ext1007__xve_inst_executed_alu0_ts_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1007 :: XVE INST EXECUTED ALU1 MS UTILIZATION */
#define acmgt1__ext1007__xve_inst_executed_alu1_ms_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1007 :: XVE INST EXECUTED ALU1 TS UTILIZATION */
#define acmgt1__ext1007__xve_inst_executed_alu1_ts_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1010 :: GPU Time Elapsed */
#define acmgt1__ext1010__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1010 :: GPU Core Clocks */
#define acmgt1__ext1010__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1010 :: AVG GPU Core Frequency */
#define acmgt1__ext1010__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1010 :: AVG GPU Core Frequency */
#define acmgt1__ext1010__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1010 :: SAMPLER 2X2 READ */
#define acmgt1__ext1010__sampler_2_x2_read__read \
   bdw__render_basic__sampler_texels__read

/* Ext1010 :: PIXEL WRITE */
#define acmgt1__ext1010__pixel_write__read \
   bdw__render_basic__samples_written__read

/* Ext1010 :: PIXEL BLEND */
#define acmgt1__ext1010__pixel_blend__read \
   bdw__render_basic__samples_blended__read

/* Ext1010 :: RASTERIZER SAMPLE OUTPUT */
#define acmgt1__ext1010__rasterizer_sample_output__read \
   bdw__render_basic__rasterized_pixels__read

/* Ext1010 :: POSTPS DEPTH STENCIL ALPHA TEST FAIL */
#define acmgt1__ext1010__postps_depth_stencil_alpha_test_fail__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic - aggregation approximation :: GPU Time Elapsed */
#define acmgt2__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic - aggregation approximation :: GPU Core Clocks */
#define acmgt2__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic - aggregation approximation :: AVG GPU Core Frequency */
#define acmgt2__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic - aggregation approximation :: AVG GPU Core Frequency */
#define acmgt2__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic - aggregation approximation :: VS Threads Dispatched */
#define acmgt2__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic - aggregation approximation :: HS Threads Dispatched */
#define acmgt2__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic - aggregation approximation :: DS Threads Dispatched */
#define acmgt2__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic - aggregation approximation :: GS Threads Dispatched */
#define acmgt2__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic - aggregation approximation :: FS Threads Dispatched */
#define acmgt2__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic - aggregation approximation :: CS Threads Dispatched */
#define acmgt2__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic - aggregation approximation :: GPU Busy */
#define acmgt2__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic - aggregation approximation :: XVE Active */
#define acmgt2__render_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic - aggregation approximation :: XVE Stall */
#define acmgt2__render_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic - aggregation approximation :: XVE Thread Occupancy */
#define acmgt2__render_basic__xve_thread_occupancy__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* Render Metrics Basic - aggregation approximation :: EM And FPU Pipes Active */
#define acmgt2__render_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic - aggregation approximation :: VS FPU Pipe Active */
#define acmgt2__render_basic__vs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic - aggregation approximation :: VS EM Pipe Active */
#define acmgt2__render_basic__vs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic - aggregation approximation :: VS Send Pipe Active */
#define acmgt2__render_basic__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Render Metrics Basic - aggregation approximation :: FS FPU Pipe Active */
#define acmgt2__render_basic__ps_fpu_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Render Metrics Basic - aggregation approximation :: FS EM Pipe Active */
#define acmgt2__render_basic__ps_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic - aggregation approximation :: FS Send Pipe Active */
#define acmgt2__render_basic__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic - aggregation approximation :: Rasterized Pixels */
#define acmgt2__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic - aggregation approximation :: Early Hi-Depth Test Fails */
#define acmgt2__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic - aggregation approximation :: Early Depth Test Fails */
#define acmgt2__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic - aggregation approximation :: Samples Killed in FS */
#define acmgt2__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic - aggregation approximation :: Pixels Failing Tests */
#define acmgt2__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic - aggregation approximation :: Samples Written */
#define acmgt2__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic - aggregation approximation :: Samples Blended */
#define acmgt2__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic - aggregation approximation :: Sampler Texels */
#define acmgt2__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic - aggregation approximation :: Sampler Texels Misses */
#define acmgt2__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic - aggregation approximation :: SLM Bytes Read */
#define acmgt2__render_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Render Metrics Basic - aggregation approximation :: SLM Bytes Read */
#define acmgt2__render_basic__slm_reads__max \
   acmgt1__render_basic__slm_reads__max

/* Render Metrics Basic - aggregation approximation :: SLM Writes */
#define acmgt2__render_basic__slm_writes__read \
   acmgt1__render_basic__slm_writes__read

/* Render Metrics Basic - aggregation approximation :: SLM Writes */
#define acmgt2__render_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Render Metrics Basic - aggregation approximation :: Shader Memory Accesses */
#define acmgt2__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic - aggregation approximation :: Shader Atomic Memory Accesses */
#define acmgt2__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic - aggregation approximation :: Shader Barrier Messages */
#define acmgt2__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic - aggregation approximation :: GTI Read Throughput */
#define acmgt2__render_basic__gti_read_throughput__read \
   acmgt1__render_basic__gti_read_throughput__read

/* Render Metrics Basic - aggregation approximation :: GTI Read Throughput */
#define acmgt2__render_basic__gti_read_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Render Metrics Basic - aggregation approximation :: GTI Write Throughput */
static uint64_t
acmgt2__render_basic__gti_write_throughput__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 128  A 37 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 37];
   uint64_t tmp1 = 128 * tmp0;

   return tmp1;
}

/* Render Metrics Basic - aggregation approximation :: GTI Write Throughput */
#define acmgt2__render_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Render Metrics Basic - aggregation approximation :: Sampler Slice2 Xe Core0 is busy */
#define acmgt2__render_basic__sampler20_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics Basic - aggregation approximation :: Samplers Busy */
#define acmgt2__render_basic__samplers_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics Basic - aggregation approximation :: Sampler20 Bottleneck */
#define acmgt2__render_basic__sampler20_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics Basic - aggregation approximation :: Samplers Bottleneck */
#define acmgt2__render_basic__sampler_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Compute Metrics Basic :: GPU Time Elapsed */
#define acmgt2__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic :: GPU Core Clocks */
#define acmgt2__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define acmgt2__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define acmgt2__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic :: GPU Busy */
#define acmgt2__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic :: CS Threads Dispatched */
#define acmgt2__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic :: XVE Active */
#define acmgt2__compute_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic :: XVE Stall */
#define acmgt2__compute_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic :: XVE FPU Pipe Active */
#define acmgt2__compute_basic__fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic :: EM Pipe Active */
#define acmgt2__compute_basic__em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic :: XMX Pipe Active */
#define acmgt2__compute_basic__xmx_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic :: EM And FPU Pipes Active */
#define acmgt2__compute_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic :: XMX And FPU Pipes Active */
#define acmgt2__compute_basic__xve_fpu_xmx_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics Basic :: XVE AVG IPC Rate */
#define acmgt2__compute_basic__xve_avg_ipc_rate__read \
   acmgt1__compute_basic__xve_avg_ipc_rate__read

/* Compute Metrics Basic :: XVE AVG IPC Rate */
#define acmgt2__compute_basic__xve_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic :: Send Pipe Active */
#define acmgt2__compute_basic__send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics Basic :: XVE Thread Occupancy */
#define acmgt2__compute_basic__xve_thread_occupancy__read \
   acmgt1__compute_basic__xve_thread_occupancy__read

/* Compute Metrics Basic :: FPU FLT16 Instruction */
#define acmgt2__compute_basic__xve_fpu_flt16__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics Basic :: FPU FLT32 Instruction */
#define acmgt2__compute_basic__xve_fpu_flt32__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics Basic :: FPU FLT64 Instruction */
#define acmgt2__compute_basic__xve_fpu_flt64__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics Basic :: Sampler Texels */
#define acmgt2__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic :: Sampler Texels Misses */
#define acmgt2__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define acmgt2__compute_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define acmgt2__compute_basic__slm_reads__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: SLM Writes */
#define acmgt2__compute_basic__slm_writes__read \
   acmgt1__render_basic__slm_writes__read

/* Compute Metrics Basic :: SLM Writes */
#define acmgt2__compute_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: Shader Memory Accesses */
#define acmgt2__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic :: Shader Atomic Memory Accesses */
#define acmgt2__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic :: Shader Barrier Messages */
#define acmgt2__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define acmgt2__compute_basic__gti_read_throughput__read \
   acmgt1__render_basic__gti_read_throughput__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define acmgt2__compute_basic__gti_read_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Compute Metrics Basic :: GTI Write Throughput */
#define acmgt2__compute_basic__gti_write_throughput__read \
   acmgt2__render_basic__gti_write_throughput__read

/* Compute Metrics Basic :: GTI Write Throughput */
#define acmgt2__compute_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* AsyncCompute :: GPU Time Elapsed */
#define acmgt2__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define acmgt2__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define acmgt2__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define acmgt2__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define acmgt2__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define acmgt2__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define acmgt2__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define acmgt2__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define acmgt2__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define acmgt2__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define acmgt2__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: XVE FPU Pipe Active */
#define acmgt2__async_compute__fpu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: VS FPU Pipe Active */
#define acmgt2__async_compute__vs_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* AsyncCompute :: FS FPU Pipe Active */
#define acmgt2__async_compute__ps_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: CS FPU Pipe Active */
#define acmgt2__async_compute__cs_fpu_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: ASYNC CS FPU Pipe Active */
#define acmgt2__async_compute__async_cs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: EM Pipe Active */
#define acmgt2__async_compute__em_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: VS EM Pipe Active */
#define acmgt2__async_compute__vs_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: FS EM Pipe Active */
#define acmgt2__async_compute__ps_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: CS EM Pipe Active */
#define acmgt2__async_compute__cs_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: ASYNC CS EM Pipe Active */
#define acmgt2__async_compute__async_cs_em_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: XVE Thread Occupancy */
#define acmgt2__async_compute__xve_thread_occupancy__read \
   acmgt1__async_compute__xve_thread_occupancy__read

/* AsyncCompute :: XVE Active */
#define acmgt2__async_compute__xve_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* AsyncCompute :: XVE Stall */
#define acmgt2__async_compute__xve_stall__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* XveActivity1 :: GPU Time Elapsed */
#define acmgt2__xve_activity1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* XveActivity1 :: GPU Core Clocks */
#define acmgt2__xve_activity1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* XveActivity1 :: AVG GPU Core Frequency */
#define acmgt2__xve_activity1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* XveActivity1 :: AVG GPU Core Frequency */
#define acmgt2__xve_activity1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* XveActivity1 :: GPU Busy */
#define acmgt2__xve_activity1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* XveActivity1 :: VS Threads Dispatched */
#define acmgt2__xve_activity1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* XveActivity1 :: HS Threads Dispatched */
#define acmgt2__xve_activity1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* XveActivity1 :: DS Threads Dispatched */
#define acmgt2__xve_activity1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* XveActivity1 :: GS Threads Dispatched */
#define acmgt2__xve_activity1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* XveActivity1 :: FS Threads Dispatched */
#define acmgt2__xve_activity1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* XveActivity1 :: CS Threads Dispatched */
#define acmgt2__xve_activity1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* XveActivity1 :: HS FPU Pipe Active */
#define acmgt2__xve_activity1__hs_fpu_active__read \
   bdw__render_basic__eu_active__read

/* XveActivity1 :: DS FPU Pipe Active */
#define acmgt2__xve_activity1__ds_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* XveActivity1 :: GS FPU Pipe Active */
#define acmgt2__xve_activity1__gs_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* XveActivity1 :: HS EM Pipe Active */
#define acmgt2__xve_activity1__hs_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* XveActivity1 :: DS EM Pipe Active */
#define acmgt2__xve_activity1__ds_em_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* XveActivity1 :: GS EM Pipe Active */
#define acmgt2__xve_activity1__gs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* XveActivity1 :: HS Send Pipe Active */
#define acmgt2__xve_activity1__hs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* XveActivity1 :: DS Send Pipe Active */
#define acmgt2__xve_activity1__ds_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* XveActivity1 :: GS Send Pipe Active */
#define acmgt2__xve_activity1__gs_send_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* XveActivity1 :: CS Send Pipe Active */
#define acmgt2__xve_activity1__cs_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* GpuBusyness :: GPU Time Elapsed */
#define acmgt2__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define acmgt2__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define acmgt2__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define acmgt2__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define acmgt2__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: XVE Active */
#define acmgt2__gpu_busyness__xve_active__read \
   bdw__render_basic__eu_active__read

/* GpuBusyness :: XVE Stall */
#define acmgt2__gpu_busyness__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* GpuBusyness :: XVE Thread Occupancy */
#define acmgt2__gpu_busyness__xve_thread_occupancy__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* GpuBusyness :: VS Threads Dispatched */
#define acmgt2__gpu_busyness__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* GpuBusyness :: HS Threads Dispatched */
#define acmgt2__gpu_busyness__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* GpuBusyness :: DS Threads Dispatched */
#define acmgt2__gpu_busyness__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* GpuBusyness :: GS Threads Dispatched */
#define acmgt2__gpu_busyness__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* GpuBusyness :: FS Threads Dispatched */
#define acmgt2__gpu_busyness__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* GpuBusyness :: CS Threads Dispatched */
#define acmgt2__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define acmgt2__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: ComputeEngine1 Ring Busy */
#define acmgt2__gpu_busyness__compute_engine1_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* GpuBusyness :: ComputeEngine2 Ring Busy */
#define acmgt2__gpu_busyness__compute_engine2_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* GpuBusyness :: Blitter Ring Busy */
#define acmgt2__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* GpuBusyness :: Vdbox00 Ring Busy */
#define acmgt2__gpu_busyness__vdbox00_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* GpuBusyness :: Vebox0 Ring Busy */
#define acmgt2__gpu_busyness__vebox0_busy__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* GpuBusyness :: Vdbox10 Ring Busy */
#define acmgt2__gpu_busyness__vdbox10_busy__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* GpuBusyness :: Vebox1 Ring Busy */
#define acmgt2__gpu_busyness__vebox1_busy__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* GpuBusyness :: Any compute engine busy */
#define acmgt2__gpu_busyness__any_compute_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* GpuBusyness :: Render and any compute engines are simultaneously busy */
#define acmgt2__gpu_busyness__render_and_any_compute_engine_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt2__render_pipe_profile1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt2__render_pipe_profile1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt2__render_pipe_profile1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt2__render_pipe_profile1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt2__render_pipe_profile1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF2 Bottleneck */
#define acmgt2__render_pipe_profile1__vf2_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS2 Bottleneck */
#define acmgt2__render_pipe_profile1__vs2_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper2 Bottleneck */
#define acmgt2__render_pipe_profile1__cl2_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS2 Bottleneck */
#define acmgt2__render_pipe_profile1__hs2_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS2 Bottleneck */
#define acmgt2__render_pipe_profile1__ds2_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS2 Bottleneck */
#define acmgt2__render_pipe_profile1__gs2_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF2 Bottleneck */
#define acmgt2__render_pipe_profile1__sf2_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO2 Bottleneck */
#define acmgt2__render_pipe_profile1__so2_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL2 Stall */
#define acmgt2__render_pipe_profile1__cl2_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS2 Stall */
#define acmgt2__render_pipe_profile1__hs2_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS2 Stall */
#define acmgt2__render_pipe_profile1__ds2_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF2 Stall */
#define acmgt2__render_pipe_profile1__sf2_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO2 Stall */
#define acmgt2__render_pipe_profile1__so2_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth20 Bottleneck */
#define acmgt2__render_pipe_profile1__hi_depth20_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC20 Bottleneck */
#define acmgt2__render_pipe_profile1__bc20_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt2__render_pipe_profile2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt2__render_pipe_profile2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt2__render_pipe_profile2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt2__render_pipe_profile2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt2__render_pipe_profile2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF3 Bottleneck */
#define acmgt2__render_pipe_profile2__vf3_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS3 Bottleneck */
#define acmgt2__render_pipe_profile2__vs3_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper3 Bottleneck */
#define acmgt2__render_pipe_profile2__cl3_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS3 Bottleneck */
#define acmgt2__render_pipe_profile2__hs3_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS3 Bottleneck */
#define acmgt2__render_pipe_profile2__ds3_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS3 Bottleneck */
#define acmgt2__render_pipe_profile2__gs3_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF3 Bottleneck */
#define acmgt2__render_pipe_profile2__sf3_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO3 Bottleneck */
#define acmgt2__render_pipe_profile2__so3_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL3 Stall */
#define acmgt2__render_pipe_profile2__cl3_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS3 Stall */
#define acmgt2__render_pipe_profile2__hs3_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS3 Stall */
#define acmgt2__render_pipe_profile2__ds3_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF3 Stall */
#define acmgt2__render_pipe_profile2__sf3_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO3 Stall */
#define acmgt2__render_pipe_profile2__so3_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth30 Bottleneck */
#define acmgt2__render_pipe_profile2__hi_depth30_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC30 Bottleneck */
#define acmgt2__render_pipe_profile2__bc30_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt2__render_pipe_profile3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt2__render_pipe_profile3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt2__render_pipe_profile3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt2__render_pipe_profile3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt2__render_pipe_profile3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF4 Bottleneck */
#define acmgt2__render_pipe_profile3__vf4_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS4 Bottleneck */
#define acmgt2__render_pipe_profile3__vs4_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper4 Bottleneck */
#define acmgt2__render_pipe_profile3__cl4_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS4 Bottleneck */
#define acmgt2__render_pipe_profile3__hs4_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS4 Bottleneck */
#define acmgt2__render_pipe_profile3__ds4_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS4 Bottleneck */
#define acmgt2__render_pipe_profile3__gs4_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF4 Bottleneck */
#define acmgt2__render_pipe_profile3__sf4_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO4 Bottleneck */
#define acmgt2__render_pipe_profile3__so4_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL4 Stall */
#define acmgt2__render_pipe_profile3__cl4_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS4 Stall */
#define acmgt2__render_pipe_profile3__hs4_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS4 Stall */
#define acmgt2__render_pipe_profile3__ds4_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF4 Stall */
#define acmgt2__render_pipe_profile3__sf4_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO4 Stall */
#define acmgt2__render_pipe_profile3__so4_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth40 Bottleneck */
#define acmgt2__render_pipe_profile3__hi_depth40_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC40 Bottleneck */
#define acmgt2__render_pipe_profile3__bc40_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt2__render_pipe_profile4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt2__render_pipe_profile4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt2__render_pipe_profile4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt2__render_pipe_profile4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt2__render_pipe_profile4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF5 Bottleneck */
#define acmgt2__render_pipe_profile4__vf5_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS5 Bottleneck */
#define acmgt2__render_pipe_profile4__vs5_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper5 Bottleneck */
#define acmgt2__render_pipe_profile4__cl5_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS5 Bottleneck */
#define acmgt2__render_pipe_profile4__hs5_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS5 Bottleneck */
#define acmgt2__render_pipe_profile4__ds5_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS5 Bottleneck */
#define acmgt2__render_pipe_profile4__gs5_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF5 Bottleneck */
#define acmgt2__render_pipe_profile4__sf5_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO5 Bottleneck */
#define acmgt2__render_pipe_profile4__so5_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL5 Stall */
#define acmgt2__render_pipe_profile4__cl5_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS5 Stall */
#define acmgt2__render_pipe_profile4__hs5_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS5 Stall */
#define acmgt2__render_pipe_profile4__ds5_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF5 Stall */
#define acmgt2__render_pipe_profile4__sf5_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO5 Stall */
#define acmgt2__render_pipe_profile4__so5_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth50 Bottleneck */
#define acmgt2__render_pipe_profile4__hi_depth50_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC50 Bottleneck */
#define acmgt2__render_pipe_profile4__bc50_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* L3_1 :: GPU Time Elapsed */
#define acmgt2__l3_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_1 :: GPU Core Clocks */
#define acmgt2__l3_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_1 :: AVG GPU Core Frequency */
#define acmgt2__l3_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_1 :: AVG GPU Core Frequency */
#define acmgt2__l3_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_1 :: GPU Busy */
#define acmgt2__l3_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_1 :: Quad1 L3 Bank0 Input Available */
#define acmgt2__l3_1__l31_bank0_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3_1 :: Quad1 L3 Bank1 Input Available */
#define acmgt2__l3_1__l31_bank1_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3_1 :: Quad1 L3 Bank2 Input Available */
#define acmgt2__l3_1__l31_bank2_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3_1 :: Quad1 L3 Bank3 Input Available */
#define acmgt2__l3_1__l31_bank3_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3_1 :: Quad1 L3 Bank4 Input Available */
#define acmgt2__l3_1__l31_bank4_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* L3_1 :: Quad1 L3 Bank5 Input Available */
#define acmgt2__l3_1__l31_bank5_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3_1 :: Quad1 L3 Bank6 Input Available */
#define acmgt2__l3_1__l31_bank6_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3_1 :: Quad1 L3 Bank7 Input Available */
#define acmgt2__l3_1__l31_bank7_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3_1 :: Quad1 L3 Bank0 Output Ready */
#define acmgt2__l3_1__l31_bank0_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3_1 :: Quad1 L3 Bank1 Output Ready */
#define acmgt2__l3_1__l31_bank1_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3_1 :: Quad1 L3 Bank2 Output Ready */
#define acmgt2__l3_1__l31_bank2_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3_1 :: Quad1 L3 Bank3 Output Ready */
#define acmgt2__l3_1__l31_bank3_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3_1 :: Quad1 L3 Bank4 Output Ready */
#define acmgt2__l3_1__l31_bank4_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3_1 :: Quad1 L3 Bank5 Output Ready */
#define acmgt2__l3_1__l31_bank5_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3_1 :: Quad1 L3 Bank6 Output Ready */
#define acmgt2__l3_1__l31_bank6_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* L3_1 :: Quad1 L3 Bank7 Output Ready */
#define acmgt2__l3_1__l31_bank7_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* L3_2 :: GPU Time Elapsed */
#define acmgt2__l3_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_2 :: GPU Core Clocks */
#define acmgt2__l3_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_2 :: AVG GPU Core Frequency */
#define acmgt2__l3_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_2 :: AVG GPU Core Frequency */
#define acmgt2__l3_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_2 :: Quad2 L3 Bank0 Input Available */
#define acmgt2__l3_2__l32_bank0_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3_2 :: Quad2 L3 Bank1 Input Available */
#define acmgt2__l3_2__l32_bank1_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3_2 :: Quad2 L3 Bank2 Input Available */
#define acmgt2__l3_2__l32_bank2_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3_2 :: Quad2 L3 Bank3 Input Available */
#define acmgt2__l3_2__l32_bank3_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3_2 :: Quad2 L3 Bank4 Input Available */
#define acmgt2__l3_2__l32_bank4_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* L3_2 :: Quad2 L3 Bank5 Input Available */
#define acmgt2__l3_2__l32_bank5_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3_2 :: Quad2 L3 Bank6 Input Available */
#define acmgt2__l3_2__l32_bank6_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3_2 :: Quad2 L3 Bank7 Input Available */
#define acmgt2__l3_2__l32_bank7_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3_2 :: Quad2 L3 Bank0 Output Ready */
#define acmgt2__l3_2__l32_bank0_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3_2 :: Quad2 L3 Bank1 Output Ready */
#define acmgt2__l3_2__l32_bank1_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3_2 :: Quad2 L3 Bank2 Output Ready */
#define acmgt2__l3_2__l32_bank2_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3_2 :: Quad2 L3 Bank3 Output Ready */
#define acmgt2__l3_2__l32_bank3_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3_2 :: Quad2 L3 Bank4 Output Ready */
#define acmgt2__l3_2__l32_bank4_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3_2 :: Quad2 L3 Bank5 Output Ready */
#define acmgt2__l3_2__l32_bank5_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3_2 :: Quad2 L3 Bank6 Output Ready */
#define acmgt2__l3_2__l32_bank6_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* L3_2 :: Quad2 L3 Bank7 Output Ready */
#define acmgt2__l3_2__l32_bank7_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_1 :: GPU Time Elapsed */
#define acmgt2__sampler_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_1 :: GPU Core Clocks */
#define acmgt2__sampler_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define acmgt2__sampler_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_1 :: AVG GPU Core Frequency */
#define acmgt2__sampler_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_1 :: GPU Busy */
#define acmgt2__sampler_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_1 :: Slice2 Xe Core0 Input Available */
#define acmgt2__sampler_1__sampler20_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler_1 :: Slice2 Xe Core1 Input Available */
#define acmgt2__sampler_1__sampler21_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_1 :: Slice2 Xe Core2 Input Available */
#define acmgt2__sampler_1__sampler22_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler_1 :: Slice2 Xe Core3 Input Available */
#define acmgt2__sampler_1__sampler23_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler_1 :: Slice3 Xe Core0 Input Available */
#define acmgt2__sampler_1__sampler30_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler_1 :: Slice3 Xe Core1 Input Available */
#define acmgt2__sampler_1__sampler31_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler_1 :: Slice3 Xe Core2 Input Available */
#define acmgt2__sampler_1__sampler32_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler_1 :: Slice3 Xe Core3 Input Available */
#define acmgt2__sampler_1__sampler33_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Sampler_1 :: Slice2 Xe Core0 Sampler Output Ready */
#define acmgt2__sampler_1__sampler20_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler_1 :: Slice2 Xe Core1 Sampler Output Ready */
#define acmgt2__sampler_1__sampler21_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler_1 :: Slice2 Xe Core2 Sampler Output Ready */
#define acmgt2__sampler_1__sampler22_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_1 :: Slice2 Xe Core3 Sampler Output Ready */
#define acmgt2__sampler_1__sampler23_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_1 :: Slice3 Xe Core0 Sampler Output Ready */
#define acmgt2__sampler_1__sampler30_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_1 :: Slice3 Xe Core1 Sampler Output Ready */
#define acmgt2__sampler_1__sampler31_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_1 :: Slice3 Xe Core2 Sampler Output Ready */
#define acmgt2__sampler_1__sampler32_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_1 :: Slice3 Xe Core3 Sampler Output Ready */
#define acmgt2__sampler_1__sampler33_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_2 :: GPU Time Elapsed */
#define acmgt2__sampler_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_2 :: GPU Core Clocks */
#define acmgt2__sampler_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_2 :: AVG GPU Core Frequency */
#define acmgt2__sampler_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_2 :: AVG GPU Core Frequency */
#define acmgt2__sampler_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_2 :: GPU Busy */
#define acmgt2__sampler_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_2 :: Slice4 Xe Core0 Input Available */
#define acmgt2__sampler_2__sampler40_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler_2 :: Slice4 Xe Core1 Input Available */
#define acmgt2__sampler_2__sampler41_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_2 :: Slice4 Xe Core2 Input Available */
#define acmgt2__sampler_2__sampler42_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler_2 :: Slice4 Xe Core3 Input Available */
#define acmgt2__sampler_2__sampler43_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler_2 :: Slice5 Xe Core0 Input Available */
#define acmgt2__sampler_2__sampler50_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler_2 :: Slice5 Xe Core1 Input Available */
#define acmgt2__sampler_2__sampler51_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler_2 :: Slice5 Xe Core2 Input Available */
#define acmgt2__sampler_2__sampler52_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler_2 :: Slice5 Xe Core3 Input Available */
#define acmgt2__sampler_2__sampler53_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Sampler_2 :: Slice4 Xe Core0 Sampler Output Ready */
#define acmgt2__sampler_2__sampler40_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler_2 :: Slice4 Xe Core1 Sampler Output Ready */
#define acmgt2__sampler_2__sampler41_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler_2 :: Slice4 Xe Core2 Sampler Output Ready */
#define acmgt2__sampler_2__sampler42_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_2 :: Slice4 Xe Core3 Sampler Output Ready */
#define acmgt2__sampler_2__sampler43_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_2 :: Slice5 Xe Core0 Sampler Output Ready */
#define acmgt2__sampler_2__sampler50_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_2 :: Slice5 Xe Core1 Sampler Output Ready */
#define acmgt2__sampler_2__sampler51_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_2 :: Slice5 Xe Core2 Sampler Output Ready */
#define acmgt2__sampler_2__sampler52_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_2 :: Slice5 Xe Core3 Sampler Output Ready */
#define acmgt2__sampler_2__sampler53_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF1 :: GPU Time Elapsed */
#define acmgt2__hdc_and_sf1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF1 :: GPU Core Clocks */
#define acmgt2__hdc_and_sf1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF1 :: AVG GPU Core Frequency */
#define acmgt2__hdc_and_sf1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF1 :: AVG GPU Core Frequency */
#define acmgt2__hdc_and_sf1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF1 :: GPU Busy */
#define acmgt2__hdc_and_sf1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF1 :: Slice2 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf1__non_sampler_shader20_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF1 :: Slice2 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf1__non_sampler_shader21_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF1 :: Slice2 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf1__non_sampler_shader22_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF1 :: Slice2 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf1__non_sampler_shader23_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF1 :: Slice3 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf1__non_sampler_shader30_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF1 :: Slice3 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf1__non_sampler_shader31_access_stalled_on_l3__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set HDCAndSF1 :: Slice3 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf1__non_sampler_shader32_access_stalled_on_l3__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF1 :: Slice3 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf1__non_sampler_shader33_access_stalled_on_l3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set HDCAndSF2 :: GPU Time Elapsed */
#define acmgt2__hdc_and_sf2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF2 :: GPU Core Clocks */
#define acmgt2__hdc_and_sf2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF2 :: AVG GPU Core Frequency */
#define acmgt2__hdc_and_sf2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF2 :: AVG GPU Core Frequency */
#define acmgt2__hdc_and_sf2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF2 :: GPU Busy */
#define acmgt2__hdc_and_sf2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF2 :: Polygon (Slice2) Data Ready */
#define acmgt2__hdc_and_sf2__poly2_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF2 :: Polygon (Slice3) Data Ready */
#define acmgt2__hdc_and_sf2__poly3_data_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF2 :: Polygon (Slice4) Data Ready */
#define acmgt2__hdc_and_sf2__poly4_data_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF2 :: Polygon (Slice5) Data Ready */
#define acmgt2__hdc_and_sf2__poly5_data_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF2 :: SQ20 is full */
#define acmgt2__hdc_and_sf2__gt_request_queue20_full__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set HDCAndSF2 :: SQ30 is full */
#define acmgt2__hdc_and_sf2__gt_request_queue30_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set HDCAndSF2 :: SQ40 is full */
#define acmgt2__hdc_and_sf2__gt_request_queue40_full__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set HDCAndSF2 :: SQ50 is full */
#define acmgt2__hdc_and_sf2__gt_request_queue50_full__read \
   bdw__render_pipe_profile__cl_stall__read

/* HDCAndSF3 :: GPU Time Elapsed */
#define acmgt2__hdc_and_sf3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* HDCAndSF3 :: GPU Core Clocks */
#define acmgt2__hdc_and_sf3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* HDCAndSF3 :: AVG GPU Core Frequency */
#define acmgt2__hdc_and_sf3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* HDCAndSF3 :: AVG GPU Core Frequency */
#define acmgt2__hdc_and_sf3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* HDCAndSF3 :: GPU Busy */
#define acmgt2__hdc_and_sf3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* HDCAndSF3 :: Slice4 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf3__non_sampler_shader40_access_stalled_on_l3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* HDCAndSF3 :: Slice4 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf3__non_sampler_shader41_access_stalled_on_l3__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* HDCAndSF3 :: Slice4 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf3__non_sampler_shader42_access_stalled_on_l3__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* HDCAndSF3 :: Slice4 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf3__non_sampler_shader43_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* HDCAndSF3 :: Slice5 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf3__non_sampler_shader50_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* HDCAndSF3 :: Slice5 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf3__non_sampler_shader51_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* HDCAndSF3 :: Slice5 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf3__non_sampler_shader52_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* HDCAndSF3 :: Slice5 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt2__hdc_and_sf3__non_sampler_shader53_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Time Elapsed */
#define acmgt2__rasterizer_and_pixel_backend1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Core Clocks */
#define acmgt2__rasterizer_and_pixel_backend1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend1 :: GPU Busy */
#define acmgt2__rasterizer_and_pixel_backend1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice2 Rasterizer Input Available */
#define acmgt2__rasterizer_and_pixel_backend1__rasterizer2_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice3 Rasterizer Output Ready */
#define acmgt2__rasterizer_and_pixel_backend1__rasterizer3_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice4 Rasterizer Input Available */
#define acmgt2__rasterizer_and_pixel_backend1__rasterizer4_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice5 Rasterizer Output Ready */
#define acmgt2__rasterizer_and_pixel_backend1__rasterizer5_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice2 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt2__rasterizer_and_pixel_backend1__pixel_data20_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice2 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt2__rasterizer_and_pixel_backend1__pixel_data21_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice3 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt2__rasterizer_and_pixel_backend1__pixel_data30_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice3 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt2__rasterizer_and_pixel_backend1__pixel_data31_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Time Elapsed */
#define acmgt2__rasterizer_and_pixel_backend2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Core Clocks */
#define acmgt2__rasterizer_and_pixel_backend2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend2 :: GPU Busy */
#define acmgt2__rasterizer_and_pixel_backend2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice2 Rasterizer Output Ready */
#define acmgt2__rasterizer_and_pixel_backend2__rasterizer2_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice3 Rasterizer Input Available */
#define acmgt2__rasterizer_and_pixel_backend2__rasterizer3_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice4 Rasterizer Output Ready */
#define acmgt2__rasterizer_and_pixel_backend2__rasterizer4_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice5 Rasterizer Input Available */
#define acmgt2__rasterizer_and_pixel_backend2__rasterizer5_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice4 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt2__rasterizer_and_pixel_backend2__pixel_data40_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice4 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt2__rasterizer_and_pixel_backend2__pixel_data41_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice5 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt2__rasterizer_and_pixel_backend2__pixel_data50_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice5 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt2__rasterizer_and_pixel_backend2__pixel_data51_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* RasterizerAndPixelBackend3 :: GPU Time Elapsed */
#define acmgt2__rasterizer_and_pixel_backend3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RasterizerAndPixelBackend3 :: GPU Core Clocks */
#define acmgt2__rasterizer_and_pixel_backend3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RasterizerAndPixelBackend3 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RasterizerAndPixelBackend3 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RasterizerAndPixelBackend3 :: PS10 Output Available */
#define acmgt2__rasterizer_and_pixel_backend3__ps_output10_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* RasterizerAndPixelBackend3 :: Pixel Values 10 Ready */
#define acmgt2__rasterizer_and_pixel_backend3__pixel_values10_ready__read \
   bdw__render_pipe_profile__hs_stall__read

/* RasterizerAndPixelBackend3 :: PS11 Output Available */
#define acmgt2__rasterizer_and_pixel_backend3__ps_output11_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* RasterizerAndPixelBackend3 :: Pixel Values 11 Ready */
#define acmgt2__rasterizer_and_pixel_backend3__pixel_values11_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* RasterizerAndPixelBackend3 :: PS20 Output Available */
#define acmgt2__rasterizer_and_pixel_backend3__ps_output20_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* RasterizerAndPixelBackend3 :: Pixel Values 20 Ready */
#define acmgt2__rasterizer_and_pixel_backend3__pixel_values20_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* RasterizerAndPixelBackend3 :: PS21 Output Available */
#define acmgt2__rasterizer_and_pixel_backend3__ps_output21_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* RasterizerAndPixelBackend3 :: Pixel Values 21 Ready */
#define acmgt2__rasterizer_and_pixel_backend3__pixel_values21_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL1 :: GPU Time Elapsed */
#define acmgt2__tdl1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL1 :: GPU Core Clocks */
#define acmgt2__tdl1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL1 :: AVG GPU Core Frequency */
#define acmgt2__tdl1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL1 :: AVG GPU Core Frequency */
#define acmgt2__tdl1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL1 :: GPU Busy */
#define acmgt2__tdl1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl1__non_ps_thread20_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl1__non_ps_thread21_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl1__non_ps_thread22_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl1__non_ps_thread23_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl1__non_ps_thread30_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl1__non_ps_thread31_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl1__non_ps_thread32_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl1__non_ps_thread33_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt2__tdl1__thread_header23_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt2__tdl1__thread_header23_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt2__tdl1__thread_header23_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt2__tdl1__thread_header23_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt2__tdl1__thread_header33_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt2__tdl1__thread_header33_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt2__tdl1__thread_header33_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt2__tdl1__thread_header33_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL2 :: GPU Time Elapsed */
#define acmgt2__tdl2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL2 :: GPU Core Clocks */
#define acmgt2__tdl2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL2 :: AVG GPU Core Frequency */
#define acmgt2__tdl2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL2 :: AVG GPU Core Frequency */
#define acmgt2__tdl2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL2 :: GPU Busy */
#define acmgt2__tdl2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl2__ps_thread20_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl2__ps_thread21_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl2__ps_thread22_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl2__ps_thread23_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl2__ps_thread30_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl2__ps_thread31_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl2__ps_thread32_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl2__ps_thread33_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL3 :: GPU Time Elapsed */
#define acmgt2__tdl3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL3 :: GPU Core Clocks */
#define acmgt2__tdl3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL3 :: AVG GPU Core Frequency */
#define acmgt2__tdl3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL3 :: AVG GPU Core Frequency */
#define acmgt2__tdl3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL3 :: GPU Busy */
#define acmgt2__tdl3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl3__thread_header20_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt2__tdl3__thread_header20_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt2__tdl3__thread_header20_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt2__tdl3__thread_header20_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt2__tdl3__thread_header20_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl3__thread_header21_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt2__tdl3__thread_header21_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt2__tdl3__thread_header21_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt2__tdl3__thread_header21_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt2__tdl3__thread_header21_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl3__thread_header22_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt2__tdl3__thread_header22_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt2__tdl3__thread_header22_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt2__tdl3__thread_header22_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt2__tdl3__thread_header22_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl3__thread_header23_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL4 :: GPU Time Elapsed */
#define acmgt2__tdl4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL4 :: GPU Core Clocks */
#define acmgt2__tdl4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL4 :: AVG GPU Core Frequency */
#define acmgt2__tdl4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL4 :: AVG GPU Core Frequency */
#define acmgt2__tdl4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL4 :: GPU Busy */
#define acmgt2__tdl4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl4__thread_header30_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt2__tdl4__thread_header30_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt2__tdl4__thread_header30_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt2__tdl4__thread_header30_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt2__tdl4__thread_header30_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl4__thread_header31_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt2__tdl4__thread_header31_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt2__tdl4__thread_header31_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt2__tdl4__thread_header31_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt2__tdl4__thread_header31_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl4__thread_header32_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt2__tdl4__thread_header32_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt2__tdl4__thread_header32_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt2__tdl4__thread_header32_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt2__tdl4__thread_header32_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl4__thread_header33_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL5 :: GPU Time Elapsed */
#define acmgt2__tdl5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL5 :: GPU Core Clocks */
#define acmgt2__tdl5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL5 :: AVG GPU Core Frequency */
#define acmgt2__tdl5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL5 :: AVG GPU Core Frequency */
#define acmgt2__tdl5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL5 :: GPU Busy */
#define acmgt2__tdl5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL5 :: Non-PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl5__non_ps_thread40_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL5 :: Non-PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl5__non_ps_thread41_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL5 :: Non-PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl5__non_ps_thread42_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL5 :: Non-PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl5__non_ps_thread43_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL5 :: Non-PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl5__non_ps_thread50_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL5 :: Non-PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl5__non_ps_thread51_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL5 :: Non-PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl5__non_ps_thread52_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL5 :: Non-PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl5__non_ps_thread53_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL5 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt2__tdl5__thread_header43_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL5 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt2__tdl5__thread_header43_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL5 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt2__tdl5__thread_header43_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL5 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt2__tdl5__thread_header43_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL5 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt2__tdl5__thread_header53_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL5 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt2__tdl5__thread_header53_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL5 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt2__tdl5__thread_header53_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL5 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt2__tdl5__thread_header53_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL6 :: GPU Time Elapsed */
#define acmgt2__tdl6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL6 :: GPU Core Clocks */
#define acmgt2__tdl6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL6 :: AVG GPU Core Frequency */
#define acmgt2__tdl6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL6 :: AVG GPU Core Frequency */
#define acmgt2__tdl6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL6 :: GPU Busy */
#define acmgt2__tdl6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL6 :: PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl6__ps_thread40_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL6 :: PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl6__ps_thread41_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL6 :: PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl6__ps_thread42_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL6 :: PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl6__ps_thread43_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL6 :: PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl6__ps_thread50_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL6 :: PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl6__ps_thread51_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL6 :: PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl6__ps_thread52_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL6 :: PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl6__ps_thread53_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL7 :: GPU Time Elapsed */
#define acmgt2__tdl7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL7 :: GPU Core Clocks */
#define acmgt2__tdl7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL7 :: AVG GPU Core Frequency */
#define acmgt2__tdl7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL7 :: AVG GPU Core Frequency */
#define acmgt2__tdl7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL7 :: GPU Busy */
#define acmgt2__tdl7__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl7__thread_header40_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt2__tdl7__thread_header40_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt2__tdl7__thread_header40_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt2__tdl7__thread_header40_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt2__tdl7__thread_header40_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl7__thread_header41_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt2__tdl7__thread_header41_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt2__tdl7__thread_header41_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt2__tdl7__thread_header41_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt2__tdl7__thread_header41_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl7__thread_header42_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt2__tdl7__thread_header42_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt2__tdl7__thread_header42_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt2__tdl7__thread_header42_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt2__tdl7__thread_header42_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL7 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl7__thread_header43_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL8 :: GPU Time Elapsed */
#define acmgt2__tdl8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL8 :: GPU Core Clocks */
#define acmgt2__tdl8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL8 :: AVG GPU Core Frequency */
#define acmgt2__tdl8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL8 :: AVG GPU Core Frequency */
#define acmgt2__tdl8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL8 :: GPU Busy */
#define acmgt2__tdl8__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher */
#define acmgt2__tdl8__thread_header50_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt2__tdl8__thread_header50_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt2__tdl8__thread_header50_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt2__tdl8__thread_header50_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt2__tdl8__thread_header50_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher */
#define acmgt2__tdl8__thread_header51_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt2__tdl8__thread_header51_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt2__tdl8__thread_header51_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt2__tdl8__thread_header51_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt2__tdl8__thread_header51_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher */
#define acmgt2__tdl8__thread_header52_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt2__tdl8__thread_header52_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt2__tdl8__thread_header52_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt2__tdl8__thread_header52_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt2__tdl8__thread_header52_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL8 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher */
#define acmgt2__tdl8__thread_header53_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set TestOa :: GPU Time Elapsed */
#define acmgt2__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define acmgt2__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define acmgt2__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define acmgt2__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define acmgt2__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define acmgt2__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define acmgt2__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define acmgt2__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define acmgt2__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define acmgt2__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define acmgt2__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define acmgt2__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define acmgt2__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define acmgt2__test_oa__counter9__read \
   hsw__compute_extended__untyped_writes0__read

/* AMFS1 :: GPU Time Elapsed */
#define acmgt2__amfs1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AMFS1 :: GPU Core Clocks */
#define acmgt2__amfs1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AMFS1 :: AVG GPU Core Frequency */
#define acmgt2__amfs1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AMFS1 :: AVG GPU Core Frequency */
#define acmgt2__amfs1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AMFS1 :: AMFS CACHE HIT SLICE0 */
#define acmgt2__amfs1__amfs_cache_hit_slice0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* AMFS1 :: AMFS CACHE MISS SLICE0 */
#define acmgt2__amfs1__amfs_cache_miss_slice0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* AMFS1 :: AMFS 4X4 SHADING REQUEST SLICE0 */
#define acmgt2__amfs1__amfs_4_x4_shading_request_slice0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* AMFS1 :: AMFS STALL ANY INPUT SLICE0 */
#define acmgt2__amfs1__amfs_stall_any_input_slice0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* AMFS1 :: AMFS STALL ALL INPUT SLICE0 */
#define acmgt2__amfs1__amfs_stall_all_input_slice0__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* AMFS2 :: GPU Time Elapsed */
#define acmgt2__amfs2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AMFS2 :: GPU Core Clocks */
#define acmgt2__amfs2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AMFS2 :: AVG GPU Core Frequency */
#define acmgt2__amfs2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AMFS2 :: AVG GPU Core Frequency */
#define acmgt2__amfs2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AMFS2 :: AMFS CACHE HIT SLICE1 */
#define acmgt2__amfs2__amfs_cache_hit_slice1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* AMFS2 :: AMFS CACHE MISS SLICE1 */
#define acmgt2__amfs2__amfs_cache_miss_slice1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* AMFS2 :: AMFS 4X4 SHADING REQUEST SLICE1 */
#define acmgt2__amfs2__amfs_4_x4_shading_request_slice1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* AMFS2 :: AMFS STALL ANY INPUT SLICE1 */
#define acmgt2__amfs2__amfs_stall_any_input_slice1__read \
   bdw__render_basic__sampler1_bottleneck__read

/* AMFS2 :: AMFS STALL ALL INPUT SLICE1 */
#define acmgt2__amfs2__amfs_stall_all_input_slice1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* AMFS3 :: GPU Time Elapsed */
#define acmgt2__amfs3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AMFS3 :: GPU Core Clocks */
#define acmgt2__amfs3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AMFS3 :: AVG GPU Core Frequency */
#define acmgt2__amfs3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AMFS3 :: AVG GPU Core Frequency */
#define acmgt2__amfs3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AMFS3 :: AMFS CACHE HIT SLICE2 */
#define acmgt2__amfs3__amfs_cache_hit_slice2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* AMFS3 :: AMFS CACHE MISS SLICE2 */
#define acmgt2__amfs3__amfs_cache_miss_slice2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* AMFS3 :: AMFS 4X4 SHADING REQUEST SLICE2 */
#define acmgt2__amfs3__amfs_4_x4_shading_request_slice2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* AMFS3 :: AMFS STALL ANY INPUT SLICE2 */
#define acmgt2__amfs3__amfs_stall_any_input_slice2__read \
   bdw__render_basic__sampler1_bottleneck__read

/* AMFS3 :: AMFS STALL ALL INPUT SLICE2 */
#define acmgt2__amfs3__amfs_stall_all_input_slice2__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* AMFS4 :: GPU Time Elapsed */
#define acmgt2__amfs4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AMFS4 :: GPU Core Clocks */
#define acmgt2__amfs4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AMFS4 :: AVG GPU Core Frequency */
#define acmgt2__amfs4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AMFS4 :: AVG GPU Core Frequency */
#define acmgt2__amfs4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AMFS4 :: AMFS CACHE HIT SLICE3 */
#define acmgt2__amfs4__amfs_cache_hit_slice3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* AMFS4 :: AMFS CACHE MISS SLICE3 */
#define acmgt2__amfs4__amfs_cache_miss_slice3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* AMFS4 :: AMFS 4X4 SHADING REQUEST SLICE3 */
#define acmgt2__amfs4__amfs_4_x4_shading_request_slice3__read \
   hsw__compute_extended__eu_typed_reads0__read

/* AMFS4 :: AMFS STALL ANY INPUT SLICE3 */
#define acmgt2__amfs4__amfs_stall_any_input_slice3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* AMFS4 :: AMFS STALL ALL INPUT SLICE3 */
#define acmgt2__amfs4__amfs_stall_all_input_slice3__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* AMFS5 :: GPU Time Elapsed */
#define acmgt2__amfs5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AMFS5 :: GPU Core Clocks */
#define acmgt2__amfs5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AMFS5 :: AVG GPU Core Frequency */
#define acmgt2__amfs5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AMFS5 :: AVG GPU Core Frequency */
#define acmgt2__amfs5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AMFS5 :: AMFS L3 ATOMIC SLICE0 */
#define acmgt2__amfs5__amfs_l3_atomic_slice0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* AMFS5 :: AMFS L3 ATOMIC SLICE1 */
#define acmgt2__amfs5__amfs_l3_atomic_slice1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* AMFS5 :: AMFS L3 ATOMIC SLICE2 */
#define acmgt2__amfs5__amfs_l3_atomic_slice2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* AMFS5 :: AMFS L3 ATOMIC SLICE3 */
#define acmgt2__amfs5__amfs_l3_atomic_slice3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* AMFS5 :: AMFS L3 ACCESS SLICE0 */
#define acmgt2__amfs5__amfs_l3_access_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* AMFS5 :: AMFS L3 ACCESS SLICE1 */
#define acmgt2__amfs5__amfs_l3_access_slice1__read \
   hsw__memory_reads__llc_read_accesses__read

/* AMFS5 :: AMFS L3 ACCESS SLICE2 */
#define acmgt2__amfs5__amfs_l3_access_slice2__read \
   hsw__memory_reads__gti_memory_reads__read

/* AMFS5 :: AMFS L3 ACCESS SLICE3 */
#define acmgt2__amfs5__amfs_l3_access_slice3__read \
   hsw__compute_extended__typed_atomics0__read

/* AMFS5 :: AMFS L3 WRITE SLICE0 */
#define acmgt2__amfs5__amfs_l3_write_slice0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* AMFS5 :: AMFS L3 WRITE SLICE1 */
#define acmgt2__amfs5__amfs_l3_write_slice1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* AMFS5 :: AMFS L3 WRITE SLICE2 */
#define acmgt2__amfs5__amfs_l3_write_slice2__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* AMFS5 :: AMFS L3 WRITE SLICE3 */
#define acmgt2__amfs5__amfs_l3_write_slice3__read \
   hsw__compute_extended__gpu_clocks__read

/* ColorPipe1 :: GPU Time Elapsed */
#define acmgt2__color_pipe1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe1 :: GPU Core Clocks */
#define acmgt2__color_pipe1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe1 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe1 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe1 :: RENDER CACHE HIT L3NODE0 */
#define acmgt2__color_pipe1__render_cache_hit_l3_node0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* ColorPipe1 :: RENDER CACHE HIT L3NODE1 */
#define acmgt2__color_pipe1__render_cache_hit_l3_node1__read \
   hsw__memory_reads__llc_read_accesses__read

/* ColorPipe1 :: RENDER CACHE HIT L3NODE2 */
#define acmgt2__color_pipe1__render_cache_hit_l3_node2__read \
   hsw__memory_reads__gti_memory_reads__read

/* ColorPipe1 :: RENDER CACHE READ L3NODE0 */
#define acmgt2__color_pipe1__render_cache_read_l3_node0__read \
   hsw__compute_extended__typed_atomics0__read

/* ColorPipe1 :: RENDER CACHE READ L3NODE1 */
#define acmgt2__color_pipe1__render_cache_read_l3_node1__read \
   hsw__compute_extended__untyped_reads0__read

/* ColorPipe1 :: RENDER CACHE READ L3NODE2 */
#define acmgt2__color_pipe1__render_cache_read_l3_node2__read \
   hsw__render_basic__gpu_core_clocks__read

/* ColorPipe1 :: RENDER CACHE WRITE L3NODE0 */
#define acmgt2__color_pipe1__render_cache_write_l3_node0__read \
   hsw__compute_extended__untyped_writes0__read

/* ColorPipe1 :: RENDER CACHE WRITE L3NODE1 */
#define acmgt2__color_pipe1__render_cache_write_l3_node1__read \
   hsw__compute_extended__typed_writes0__read

/* ColorPipe1 :: RENDER CACHE WRITE L3NODE2 */
#define acmgt2__color_pipe1__render_cache_write_l3_node2__read \
   hsw__compute_extended__gpu_clocks__read

/* ColorPipe1 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE0 */
#define acmgt2__color_pipe1__render_cache_input_available_l3_node0__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ColorPipe1 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE1 */
#define acmgt2__color_pipe1__render_cache_input_available_l3_node1__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ColorPipe1 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE2 */
#define acmgt2__color_pipe1__render_cache_input_available_l3_node2__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ColorPipe1 :: RENDER_CACHE_OUTPUT_READY _L3NODE0 */
#define acmgt2__color_pipe1__render_cache_output_ready_l3_node0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ColorPipe1 :: RENDER_CACHE_OUTPUT_READY _L3NODE1 */
#define acmgt2__color_pipe1__render_cache_output_ready_l3_node1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ColorPipe1 :: RENDER_CACHE_OUTPUT_READY _L3NODE2 */
#define acmgt2__color_pipe1__render_cache_output_ready_l3_node2__read \
   bdw__render_basic__sampler1_busy__read

/* ColorPipe2 :: GPU Time Elapsed */
#define acmgt2__color_pipe2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe2 :: GPU Core Clocks */
#define acmgt2__color_pipe2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe2 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe2 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe2 :: RENDER CACHE HIT L3NODE3 */
#define acmgt2__color_pipe2__render_cache_hit_l3_node3__read \
   hsw__memory_reads__gpu_core_clocks__read

/* ColorPipe2 :: RENDER CACHE READ L3NODE3 */
#define acmgt2__color_pipe2__render_cache_read_l3_node3__read \
   hsw__memory_reads__llc_read_accesses__read

/* ColorPipe2 :: RENDER CACHE WRITE L3NODE3 */
#define acmgt2__color_pipe2__render_cache_write_l3_node3__read \
   hsw__memory_reads__gti_memory_reads__read

/* ColorPipe2 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE3 */
#define acmgt2__color_pipe2__render_cache_input_available_l3_node3__read \
   bdw__render_pipe_profile__cl_stall__read

/* ColorPipe2 :: RENDER_CACHE_OUTPUT_READY _L3NODE3 */
#define acmgt2__color_pipe2__render_cache_output_ready_l3_node3__read \
   bdw__render_pipe_profile__so_stall__read

/* ColorPipe3 :: GPU Time Elapsed */
#define acmgt2__color_pipe3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe3 :: GPU Core Clocks */
#define acmgt2__color_pipe3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe3 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe3 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE0 */
#define acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE1 */
#define acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE2 */
#define acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE3 */
#define acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE4 */
#define acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe4__read \
   bdw__render_pipe_profile__so_stall__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE5 */
#define acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe5__read \
   bdw__render_pipe_profile__ds_stall__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE6 */
#define acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe6__read \
   bdw__render_pipe_profile__hs_stall__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE7 */
#define acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE0 */
#define acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE1 */
#define acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE2 */
#define acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ColorPipe3 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE3 */
#define acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ColorPipe3 :: PS OUTPUT AVAILABLE CPIPE0 */
#define acmgt2__color_pipe3__ps_output_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* ColorPipe3 :: PS OUTPUT AVAILABLE CPIPE1 */
#define acmgt2__color_pipe3__ps_output_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* ColorPipe4 :: GPU Time Elapsed */
#define acmgt2__color_pipe4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe4 :: GPU Core Clocks */
#define acmgt2__color_pipe4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe4 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe4 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe4 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE0 */
#define acmgt2__color_pipe4__pixel_post_process_input_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* ColorPipe4 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE1 */
#define acmgt2__color_pipe4__pixel_post_process_input_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* ColorPipe5 :: GPU Time Elapsed */
#define acmgt2__color_pipe5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe5 :: GPU Core Clocks */
#define acmgt2__color_pipe5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe5 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe5 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe5 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE2 */
#define acmgt2__color_pipe5__pixel_post_process_input_available_cpipe2__read \
   bdw__render_basic__sampler0_busy__read

/* ColorPipe5 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE3 */
#define acmgt2__color_pipe5__pixel_post_process_input_available_cpipe3__read \
   bdw__render_basic__sampler1_busy__read

/* ColorPipe6 :: GPU Time Elapsed */
#define acmgt2__color_pipe6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe6 :: GPU Core Clocks */
#define acmgt2__color_pipe6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe6 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe6 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe6 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE4 */
#define acmgt2__color_pipe6__pixel_post_process_input_available_cpipe4__read \
   bdw__render_basic__sampler0_busy__read

/* ColorPipe6 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE5 */
#define acmgt2__color_pipe6__pixel_post_process_input_available_cpipe5__read \
   bdw__render_basic__sampler1_busy__read

/* ColorPipe7 :: GPU Time Elapsed */
#define acmgt2__color_pipe7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe7 :: GPU Core Clocks */
#define acmgt2__color_pipe7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe7 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe7 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe7 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE6 */
#define acmgt2__color_pipe7__pixel_post_process_input_available_cpipe6__read \
   bdw__render_basic__sampler0_busy__read

/* ColorPipe7 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE7 */
#define acmgt2__color_pipe7__pixel_post_process_input_available_cpipe7__read \
   bdw__render_basic__sampler1_busy__read

/* ColorPipe8 :: GPU Time Elapsed */
#define acmgt2__color_pipe8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe8 :: GPU Core Clocks */
#define acmgt2__color_pipe8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe8 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe8 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe8 :: PS OUTPUT AVAILABLE CPIPE2 */
#define acmgt2__color_pipe8__ps_output_available_cpipe2__read \
   bdw__render_basic__sampler0_busy__read

/* ColorPipe8 :: PS OUTPUT AVAILABLE CPIPE3 */
#define acmgt2__color_pipe8__ps_output_available_cpipe3__read \
   bdw__render_basic__sampler1_busy__read

/* ColorPipe8 :: PS OUTPUT AVAILABLE CPIPE4 */
#define acmgt2__color_pipe8__ps_output_available_cpipe4__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ColorPipe8 :: PS OUTPUT AVAILABLE CPIPE5 */
#define acmgt2__color_pipe8__ps_output_available_cpipe5__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ColorPipe8 :: PS OUTPUT AVAILABLE CPIPE6 */
#define acmgt2__color_pipe8__ps_output_available_cpipe6__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ColorPipe8 :: PS OUTPUT AVAILABLE CPIPE7 */
#define acmgt2__color_pipe8__ps_output_available_cpipe7__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ColorPipe8 :: PIXEL POST PROCESS OUTPUT READY CPIPE0 */
#define acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* ColorPipe8 :: PIXEL POST PROCESS OUTPUT READY CPIPE1 */
#define acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* ColorPipe8 :: PIXEL POST PROCESS OUTPUT READY CPIPE2 */
#define acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* ColorPipe8 :: PIXEL POST PROCESS OUTPUT READY CPIPE3 */
#define acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* ColorPipe9 :: GPU Time Elapsed */
#define acmgt2__color_pipe9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe9 :: GPU Core Clocks */
#define acmgt2__color_pipe9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe9 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe9 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe9 :: PIXEL POST PROCESS OUTPUT READY CPIPE4 */
#define acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe4__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* ColorPipe9 :: PIXEL POST PROCESS OUTPUT READY CPIPE5 */
#define acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe5__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* ColorPipe9 :: PIXEL POST PROCESS OUTPUT READY CPIPE6 */
#define acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe6__read \
   bdw__render_pipe_profile__sf_stall__read

/* ColorPipe9 :: PIXEL POST PROCESS OUTPUT READY CPIPE7 */
#define acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe7__read \
   bdw__render_pipe_profile__cl_stall__read

/* ColorPipe9 :: RENDER CACHE ALLOC L3NODE0 */
#define acmgt2__color_pipe9__render_cache_alloc_l3_node0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ColorPipe9 :: RENDER CACHE ALLOC L3NODE1 */
#define acmgt2__color_pipe9__render_cache_alloc_l3_node1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ColorPipe9 :: RENDER CACHE ALLOC L3NODE2 */
#define acmgt2__color_pipe9__render_cache_alloc_l3_node2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ColorPipe9 :: RENDER CACHE ALLOC L3NODE3 */
#define acmgt2__color_pipe9__render_cache_alloc_l3_node3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* ColorPipe10 :: GPU Time Elapsed */
#define acmgt2__color_pipe10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe10 :: GPU Core Clocks */
#define acmgt2__color_pipe10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe10 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe10 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe10 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0 */
#define acmgt2__color_pipe10__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* ColorPipe11 :: GPU Time Elapsed */
#define acmgt2__color_pipe11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe11 :: GPU Core Clocks */
#define acmgt2__color_pipe11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe11 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe11 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe11 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1 */
#define acmgt2__color_pipe11__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* ColorPipe12 :: GPU Time Elapsed */
#define acmgt2__color_pipe12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe12 :: GPU Core Clocks */
#define acmgt2__color_pipe12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe12 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe12 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe12 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE2 */
#define acmgt2__color_pipe12__pixel_2x2_lit_post_rasterizer_early_depth_slice2__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* ColorPipe13 :: GPU Time Elapsed */
#define acmgt2__color_pipe13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe13 :: GPU Core Clocks */
#define acmgt2__color_pipe13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe13 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe13 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe13 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE3 */
#define acmgt2__color_pipe13__pixel_2x2_lit_post_rasterizer_early_depth_slice3__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* ColorPipe14 :: GPU Time Elapsed */
#define acmgt2__color_pipe14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe14 :: GPU Core Clocks */
#define acmgt2__color_pipe14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe14 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe14 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe14 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0 */
#define acmgt2__color_pipe14__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* ColorPipe15 :: GPU Time Elapsed */
#define acmgt2__color_pipe15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe15 :: GPU Core Clocks */
#define acmgt2__color_pipe15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe15 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe15 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe15 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1 */
#define acmgt2__color_pipe15__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* ColorPipe16 :: GPU Time Elapsed */
#define acmgt2__color_pipe16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe16 :: GPU Core Clocks */
#define acmgt2__color_pipe16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe16 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe16 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe16 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE2 */
#define acmgt2__color_pipe16__pixel_2x2_lit_post_rasterizer_late_depth_slice2__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* ColorPipe17 :: GPU Time Elapsed */
#define acmgt2__color_pipe17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ColorPipe17 :: GPU Core Clocks */
#define acmgt2__color_pipe17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ColorPipe17 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ColorPipe17 :: AVG GPU Core Frequency */
#define acmgt2__color_pipe17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ColorPipe17 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE3 */
#define acmgt2__color_pipe17__pixel_2x2_lit_post_rasterizer_late_depth_slice3__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Dataport1 :: GPU Time Elapsed */
#define acmgt2__dataport1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport1 :: GPU Core Clocks */
#define acmgt2__dataport1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport1 :: AVG GPU Core Frequency */
#define acmgt2__dataport1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport1 :: AVG GPU Core Frequency */
#define acmgt2__dataport1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport1 :: XVE DATAPORT READ MESSAGE COUNT XECORE0 */
#define acmgt2__dataport1__xve_dataport_read_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Dataport1 :: XVE DATAPORT READ MESSAGE COUNT XECORE1 */
#define acmgt2__dataport1__xve_dataport_read_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport1 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE0 */
#define acmgt2__dataport1__xve_dataport_write_message_count_xecore0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport1 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE1 */
#define acmgt2__dataport1__xve_dataport_write_message_count_xecore1__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport1 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0 */
#define acmgt2__dataport1__xve_dataport_atomic_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport1 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1 */
#define acmgt2__dataport1__xve_dataport_atomic_message_count_xecore1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport1 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE0 */
#define acmgt2__dataport1__xve_dataport_fence_message_count_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport1 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE1 */
#define acmgt2__dataport1__xve_dataport_fence_message_count_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport2 :: GPU Time Elapsed */
#define acmgt2__dataport2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport2 :: GPU Core Clocks */
#define acmgt2__dataport2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport2 :: AVG GPU Core Frequency */
#define acmgt2__dataport2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport2 :: AVG GPU Core Frequency */
#define acmgt2__dataport2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport2 :: XVE DATAPORT READ MESSAGE COUNT XECORE2 */
#define acmgt2__dataport2__xve_dataport_read_message_count_xecore2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Dataport2 :: XVE DATAPORT READ MESSAGE COUNT XECORE3 */
#define acmgt2__dataport2__xve_dataport_read_message_count_xecore3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport2 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE2 */
#define acmgt2__dataport2__xve_dataport_write_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport2 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE3 */
#define acmgt2__dataport2__xve_dataport_write_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport2 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2 */
#define acmgt2__dataport2__xve_dataport_atomic_message_count_xecore2__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport2 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3 */
#define acmgt2__dataport2__xve_dataport_atomic_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport2 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE2 */
#define acmgt2__dataport2__xve_dataport_fence_message_count_xecore2__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport2 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE3 */
#define acmgt2__dataport2__xve_dataport_fence_message_count_xecore3__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport3 :: GPU Time Elapsed */
#define acmgt2__dataport3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport3 :: GPU Core Clocks */
#define acmgt2__dataport3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport3 :: AVG GPU Core Frequency */
#define acmgt2__dataport3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport3 :: AVG GPU Core Frequency */
#define acmgt2__dataport3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport3 :: XVE DATAPORT READ MESSAGE COUNT XECORE4 */
#define acmgt2__dataport3__xve_dataport_read_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Dataport3 :: XVE DATAPORT READ MESSAGE COUNT XECORE5 */
#define acmgt2__dataport3__xve_dataport_read_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport3 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE4 */
#define acmgt2__dataport3__xve_dataport_write_message_count_xecore4__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport3 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE5 */
#define acmgt2__dataport3__xve_dataport_write_message_count_xecore5__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport3 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4 */
#define acmgt2__dataport3__xve_dataport_atomic_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport3 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5 */
#define acmgt2__dataport3__xve_dataport_atomic_message_count_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport3 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE4 */
#define acmgt2__dataport3__xve_dataport_fence_message_count_xecore4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport3 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE5 */
#define acmgt2__dataport3__xve_dataport_fence_message_count_xecore5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport4 :: GPU Time Elapsed */
#define acmgt2__dataport4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport4 :: GPU Core Clocks */
#define acmgt2__dataport4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport4 :: AVG GPU Core Frequency */
#define acmgt2__dataport4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport4 :: AVG GPU Core Frequency */
#define acmgt2__dataport4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport4 :: XVE DATAPORT READ MESSAGE COUNT XECORE6 */
#define acmgt2__dataport4__xve_dataport_read_message_count_xecore6__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Dataport4 :: XVE DATAPORT READ MESSAGE COUNT XECORE7 */
#define acmgt2__dataport4__xve_dataport_read_message_count_xecore7__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport4 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE6 */
#define acmgt2__dataport4__xve_dataport_write_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport4 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE7 */
#define acmgt2__dataport4__xve_dataport_write_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport4 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6 */
#define acmgt2__dataport4__xve_dataport_atomic_message_count_xecore6__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport4 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7 */
#define acmgt2__dataport4__xve_dataport_atomic_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport4 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE6 */
#define acmgt2__dataport4__xve_dataport_fence_message_count_xecore6__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport4 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE7 */
#define acmgt2__dataport4__xve_dataport_fence_message_count_xecore7__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport5 :: GPU Time Elapsed */
#define acmgt2__dataport5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport5 :: GPU Core Clocks */
#define acmgt2__dataport5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport5 :: AVG GPU Core Frequency */
#define acmgt2__dataport5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport5 :: AVG GPU Core Frequency */
#define acmgt2__dataport5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport5 :: XVE DATAPORT READ MESSAGE COUNT XECORE8 */
#define acmgt2__dataport5__xve_dataport_read_message_count_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Dataport5 :: XVE DATAPORT READ MESSAGE COUNT XECORE9 */
#define acmgt2__dataport5__xve_dataport_read_message_count_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport5 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE8 */
#define acmgt2__dataport5__xve_dataport_write_message_count_xecore8__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport5 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE9 */
#define acmgt2__dataport5__xve_dataport_write_message_count_xecore9__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport5 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE8 */
#define acmgt2__dataport5__xve_dataport_atomic_message_count_xecore8__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport5 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE9 */
#define acmgt2__dataport5__xve_dataport_atomic_message_count_xecore9__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport5 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE8 */
#define acmgt2__dataport5__xve_dataport_fence_message_count_xecore8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport5 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE9 */
#define acmgt2__dataport5__xve_dataport_fence_message_count_xecore9__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport6 :: GPU Time Elapsed */
#define acmgt2__dataport6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport6 :: GPU Core Clocks */
#define acmgt2__dataport6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport6 :: AVG GPU Core Frequency */
#define acmgt2__dataport6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport6 :: AVG GPU Core Frequency */
#define acmgt2__dataport6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport6 :: XVE DATAPORT READ MESSAGE COUNT XECORE10 */
#define acmgt2__dataport6__xve_dataport_read_message_count_xecore10__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Dataport6 :: XVE DATAPORT READ MESSAGE COUNT XECORE11 */
#define acmgt2__dataport6__xve_dataport_read_message_count_xecore11__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport6 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE10 */
#define acmgt2__dataport6__xve_dataport_write_message_count_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport6 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE11 */
#define acmgt2__dataport6__xve_dataport_write_message_count_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport6 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE10 */
#define acmgt2__dataport6__xve_dataport_atomic_message_count_xecore10__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport6 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE11 */
#define acmgt2__dataport6__xve_dataport_atomic_message_count_xecore11__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport6 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE10 */
#define acmgt2__dataport6__xve_dataport_fence_message_count_xecore10__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport6 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE11 */
#define acmgt2__dataport6__xve_dataport_fence_message_count_xecore11__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport7 :: GPU Time Elapsed */
#define acmgt2__dataport7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport7 :: GPU Core Clocks */
#define acmgt2__dataport7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport7 :: AVG GPU Core Frequency */
#define acmgt2__dataport7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport7 :: AVG GPU Core Frequency */
#define acmgt2__dataport7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport7 :: XVE DATAPORT READ MESSAGE COUNT XECORE12 */
#define acmgt2__dataport7__xve_dataport_read_message_count_xecore12__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Dataport7 :: XVE DATAPORT READ MESSAGE COUNT XECORE13 */
#define acmgt2__dataport7__xve_dataport_read_message_count_xecore13__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport7 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE12 */
#define acmgt2__dataport7__xve_dataport_write_message_count_xecore12__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport7 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE13 */
#define acmgt2__dataport7__xve_dataport_write_message_count_xecore13__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport7 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE12 */
#define acmgt2__dataport7__xve_dataport_atomic_message_count_xecore12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport7 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE13 */
#define acmgt2__dataport7__xve_dataport_atomic_message_count_xecore13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport7 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE12 */
#define acmgt2__dataport7__xve_dataport_fence_message_count_xecore12__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport7 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE13 */
#define acmgt2__dataport7__xve_dataport_fence_message_count_xecore13__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport8 :: GPU Time Elapsed */
#define acmgt2__dataport8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport8 :: GPU Core Clocks */
#define acmgt2__dataport8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport8 :: AVG GPU Core Frequency */
#define acmgt2__dataport8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport8 :: AVG GPU Core Frequency */
#define acmgt2__dataport8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport8 :: XVE DATAPORT READ MESSAGE COUNT XECORE14 */
#define acmgt2__dataport8__xve_dataport_read_message_count_xecore14__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Dataport8 :: XVE DATAPORT READ MESSAGE COUNT XECORE15 */
#define acmgt2__dataport8__xve_dataport_read_message_count_xecore15__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport8 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE14 */
#define acmgt2__dataport8__xve_dataport_write_message_count_xecore14__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport8 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE15 */
#define acmgt2__dataport8__xve_dataport_write_message_count_xecore15__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport8 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE14 */
#define acmgt2__dataport8__xve_dataport_atomic_message_count_xecore14__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport8 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE15 */
#define acmgt2__dataport8__xve_dataport_atomic_message_count_xecore15__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport8 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE14 */
#define acmgt2__dataport8__xve_dataport_fence_message_count_xecore14__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport8 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE15 */
#define acmgt2__dataport8__xve_dataport_fence_message_count_xecore15__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport9 :: GPU Time Elapsed */
#define acmgt2__dataport9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport9 :: GPU Core Clocks */
#define acmgt2__dataport9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport9 :: AVG GPU Core Frequency */
#define acmgt2__dataport9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport9 :: AVG GPU Core Frequency */
#define acmgt2__dataport9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport9 :: DATAPORT INPUT AVAILABLE XECORE0 */
#define acmgt2__dataport9__dataport_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport9 :: DATAPORT INPUT AVAILABLE XECORE1 */
#define acmgt2__dataport9__dataport_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport10 :: GPU Time Elapsed */
#define acmgt2__dataport10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport10 :: GPU Core Clocks */
#define acmgt2__dataport10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport10 :: AVG GPU Core Frequency */
#define acmgt2__dataport10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport10 :: AVG GPU Core Frequency */
#define acmgt2__dataport10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport10 :: DATAPORT INPUT AVAILABLE XECORE2 */
#define acmgt2__dataport10__dataport_input_available_xecore2__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport10 :: DATAPORT INPUT AVAILABLE XECORE3 */
#define acmgt2__dataport10__dataport_input_available_xecore3__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport11 :: GPU Time Elapsed */
#define acmgt2__dataport11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport11 :: GPU Core Clocks */
#define acmgt2__dataport11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport11 :: AVG GPU Core Frequency */
#define acmgt2__dataport11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport11 :: AVG GPU Core Frequency */
#define acmgt2__dataport11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport11 :: DATAPORT INPUT AVAILABLE XECORE4 */
#define acmgt2__dataport11__dataport_input_available_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport11 :: DATAPORT INPUT AVAILABLE XECORE5 */
#define acmgt2__dataport11__dataport_input_available_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport12 :: GPU Time Elapsed */
#define acmgt2__dataport12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport12 :: GPU Core Clocks */
#define acmgt2__dataport12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport12 :: AVG GPU Core Frequency */
#define acmgt2__dataport12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport12 :: AVG GPU Core Frequency */
#define acmgt2__dataport12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport12 :: DATAPORT INPUT AVAILABLE XECORE6 */
#define acmgt2__dataport12__dataport_input_available_xecore6__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport12 :: DATAPORT INPUT AVAILABLE XECORE7 */
#define acmgt2__dataport12__dataport_input_available_xecore7__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport13 :: GPU Time Elapsed */
#define acmgt2__dataport13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport13 :: GPU Core Clocks */
#define acmgt2__dataport13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport13 :: AVG GPU Core Frequency */
#define acmgt2__dataport13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport13 :: AVG GPU Core Frequency */
#define acmgt2__dataport13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport13 :: DATAPORT INPUT AVAILABLE XECORE8 */
#define acmgt2__dataport13__dataport_input_available_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport13 :: DATAPORT INPUT AVAILABLE XECORE9 */
#define acmgt2__dataport13__dataport_input_available_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport14 :: GPU Time Elapsed */
#define acmgt2__dataport14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport14 :: GPU Core Clocks */
#define acmgt2__dataport14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport14 :: AVG GPU Core Frequency */
#define acmgt2__dataport14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport14 :: AVG GPU Core Frequency */
#define acmgt2__dataport14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport14 :: DATAPORT INPUT AVAILABLE XECORE10 */
#define acmgt2__dataport14__dataport_input_available_xecore10__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport14 :: DATAPORT INPUT AVAILABLE XECORE11 */
#define acmgt2__dataport14__dataport_input_available_xecore11__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport15 :: GPU Time Elapsed */
#define acmgt2__dataport15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport15 :: GPU Core Clocks */
#define acmgt2__dataport15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport15 :: AVG GPU Core Frequency */
#define acmgt2__dataport15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport15 :: AVG GPU Core Frequency */
#define acmgt2__dataport15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport15 :: DATAPORT INPUT AVAILABLE XECORE12 */
#define acmgt2__dataport15__dataport_input_available_xecore12__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport15 :: DATAPORT INPUT AVAILABLE XECORE13 */
#define acmgt2__dataport15__dataport_input_available_xecore13__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport16 :: GPU Time Elapsed */
#define acmgt2__dataport16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport16 :: GPU Core Clocks */
#define acmgt2__dataport16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport16 :: AVG GPU Core Frequency */
#define acmgt2__dataport16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport16 :: AVG GPU Core Frequency */
#define acmgt2__dataport16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport16 :: DATAPORT INPUT AVAILABLE XECORE14 */
#define acmgt2__dataport16__dataport_input_available_xecore14__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport16 :: DATAPORT INPUT AVAILABLE XECORE15 */
#define acmgt2__dataport16__dataport_input_available_xecore15__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport17 :: GPU Time Elapsed */
#define acmgt2__dataport17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport17 :: GPU Core Clocks */
#define acmgt2__dataport17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport17 :: AVG GPU Core Frequency */
#define acmgt2__dataport17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport17 :: AVG GPU Core Frequency */
#define acmgt2__dataport17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport17 :: DATAPORT OUTPUT READY XECORE0 */
#define acmgt2__dataport17__dataport_output_ready_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport17 :: DATAPORT OUTPUT READY XECORE1 */
#define acmgt2__dataport17__dataport_output_ready_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport17 :: DATAPORT OUTPUT READY XECORE2 */
#define acmgt2__dataport17__dataport_output_ready_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Dataport17 :: DATAPORT OUTPUT READY XECORE3 */
#define acmgt2__dataport17__dataport_output_ready_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Dataport18 :: GPU Time Elapsed */
#define acmgt2__dataport18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport18 :: GPU Core Clocks */
#define acmgt2__dataport18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport18 :: AVG GPU Core Frequency */
#define acmgt2__dataport18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport18 :: AVG GPU Core Frequency */
#define acmgt2__dataport18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport18 :: DATAPORT OUTPUT READY XECORE4 */
#define acmgt2__dataport18__dataport_output_ready_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport18 :: DATAPORT OUTPUT READY XECORE5 */
#define acmgt2__dataport18__dataport_output_ready_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport18 :: DATAPORT OUTPUT READY XECORE6 */
#define acmgt2__dataport18__dataport_output_ready_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Dataport18 :: DATAPORT OUTPUT READY XECORE7 */
#define acmgt2__dataport18__dataport_output_ready_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Dataport19 :: GPU Time Elapsed */
#define acmgt2__dataport19__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport19 :: GPU Core Clocks */
#define acmgt2__dataport19__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport19 :: AVG GPU Core Frequency */
#define acmgt2__dataport19__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport19 :: AVG GPU Core Frequency */
#define acmgt2__dataport19__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport19 :: DATAPORT OUTPUT READY XECORE8 */
#define acmgt2__dataport19__dataport_output_ready_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport19 :: DATAPORT OUTPUT READY XECORE9 */
#define acmgt2__dataport19__dataport_output_ready_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport19 :: DATAPORT OUTPUT READY XECORE10 */
#define acmgt2__dataport19__dataport_output_ready_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Dataport19 :: DATAPORT OUTPUT READY XECORE11 */
#define acmgt2__dataport19__dataport_output_ready_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Dataport20 :: GPU Time Elapsed */
#define acmgt2__dataport20__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport20 :: GPU Core Clocks */
#define acmgt2__dataport20__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport20 :: AVG GPU Core Frequency */
#define acmgt2__dataport20__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport20 :: AVG GPU Core Frequency */
#define acmgt2__dataport20__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport20 :: DATAPORT OUTPUT READY XECORE12 */
#define acmgt2__dataport20__dataport_output_ready_xecore12__read \
   bdw__render_basic__sampler0_busy__read

/* Dataport20 :: DATAPORT OUTPUT READY XECORE13 */
#define acmgt2__dataport20__dataport_output_ready_xecore13__read \
   bdw__render_basic__sampler1_busy__read

/* Dataport20 :: DATAPORT OUTPUT READY XECORE14 */
#define acmgt2__dataport20__dataport_output_ready_xecore14__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Dataport20 :: DATAPORT OUTPUT READY XECORE15 */
#define acmgt2__dataport20__dataport_output_ready_xecore15__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Dataport21 :: GPU Time Elapsed */
#define acmgt2__dataport21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport21 :: GPU Core Clocks */
#define acmgt2__dataport21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport21 :: AVG GPU Core Frequency */
#define acmgt2__dataport21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport21 :: AVG GPU Core Frequency */
#define acmgt2__dataport21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport21 :: DATAPORT BYTE READ XECORE0 */
#define acmgt2__dataport21__dataport_byte_read_xecore0__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Dataport21 :: DATAPORT BYTE READ XECORE1 */
#define acmgt2__dataport21__dataport_byte_read_xecore1__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Dataport22 :: GPU Time Elapsed */
#define acmgt2__dataport22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport22 :: GPU Core Clocks */
#define acmgt2__dataport22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport22 :: AVG GPU Core Frequency */
#define acmgt2__dataport22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport22 :: AVG GPU Core Frequency */
#define acmgt2__dataport22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport22 :: DATAPORT BYTE READ XECORE2 */
#define acmgt2__dataport22__dataport_byte_read_xecore2__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Dataport22 :: DATAPORT BYTE READ XECORE3 */
#define acmgt2__dataport22__dataport_byte_read_xecore3__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Dataport23 :: GPU Time Elapsed */
#define acmgt2__dataport23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport23 :: GPU Core Clocks */
#define acmgt2__dataport23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport23 :: AVG GPU Core Frequency */
#define acmgt2__dataport23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport23 :: AVG GPU Core Frequency */
#define acmgt2__dataport23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport23 :: DATAPORT BYTE READ XECORE4 */
#define acmgt2__dataport23__dataport_byte_read_xecore4__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Dataport23 :: DATAPORT BYTE READ XECORE5 */
#define acmgt2__dataport23__dataport_byte_read_xecore5__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Dataport24 :: GPU Time Elapsed */
#define acmgt2__dataport24__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport24 :: GPU Core Clocks */
#define acmgt2__dataport24__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport24 :: AVG GPU Core Frequency */
#define acmgt2__dataport24__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport24 :: AVG GPU Core Frequency */
#define acmgt2__dataport24__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport24 :: DATAPORT BYTE READ XECORE6 */
#define acmgt2__dataport24__dataport_byte_read_xecore6__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Dataport24 :: DATAPORT BYTE READ XECORE7 */
#define acmgt2__dataport24__dataport_byte_read_xecore7__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Dataport25 :: GPU Time Elapsed */
#define acmgt2__dataport25__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport25 :: GPU Core Clocks */
#define acmgt2__dataport25__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport25 :: AVG GPU Core Frequency */
#define acmgt2__dataport25__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport25 :: AVG GPU Core Frequency */
#define acmgt2__dataport25__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport25 :: DATAPORT BYTE READ XECORE8 */
#define acmgt2__dataport25__dataport_byte_read_xecore8__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Dataport25 :: DATAPORT BYTE READ XECORE9 */
#define acmgt2__dataport25__dataport_byte_read_xecore9__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Dataport26 :: GPU Time Elapsed */
#define acmgt2__dataport26__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport26 :: GPU Core Clocks */
#define acmgt2__dataport26__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport26 :: AVG GPU Core Frequency */
#define acmgt2__dataport26__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport26 :: AVG GPU Core Frequency */
#define acmgt2__dataport26__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport26 :: DATAPORT BYTE READ XECORE10 */
#define acmgt2__dataport26__dataport_byte_read_xecore10__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Dataport26 :: DATAPORT BYTE READ XECORE11 */
#define acmgt2__dataport26__dataport_byte_read_xecore11__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Dataport27 :: GPU Time Elapsed */
#define acmgt2__dataport27__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport27 :: GPU Core Clocks */
#define acmgt2__dataport27__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport27 :: AVG GPU Core Frequency */
#define acmgt2__dataport27__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport27 :: AVG GPU Core Frequency */
#define acmgt2__dataport27__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport27 :: DATAPORT BYTE READ XECORE12 */
#define acmgt2__dataport27__dataport_byte_read_xecore12__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Dataport27 :: DATAPORT BYTE READ XECORE13 */
#define acmgt2__dataport27__dataport_byte_read_xecore13__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Dataport28 :: GPU Time Elapsed */
#define acmgt2__dataport28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport28 :: GPU Core Clocks */
#define acmgt2__dataport28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport28 :: AVG GPU Core Frequency */
#define acmgt2__dataport28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport28 :: AVG GPU Core Frequency */
#define acmgt2__dataport28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport28 :: DATAPORT BYTE READ XECORE14 */
#define acmgt2__dataport28__dataport_byte_read_xecore14__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Dataport28 :: DATAPORT BYTE READ XECORE15 */
#define acmgt2__dataport28__dataport_byte_read_xecore15__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Dataport29 :: GPU Time Elapsed */
#define acmgt2__dataport29__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport29 :: GPU Core Clocks */
#define acmgt2__dataport29__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport29 :: AVG GPU Core Frequency */
#define acmgt2__dataport29__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport29 :: AVG GPU Core Frequency */
#define acmgt2__dataport29__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport29 :: DATAPORT BYTE WRITE XECORE0 */
#define acmgt2__dataport29__dataport_byte_write_xecore0__read \
   acmgt1__ext83__dataport_byte_write_xecore0__read

/* Dataport29 :: DATAPORT BYTE WRITE XECORE1 */
#define acmgt2__dataport29__dataport_byte_write_xecore1__read \
   acmgt1__ext83__dataport_byte_write_xecore1__read

/* Dataport29 :: DATAPORT BYTE WRITE XECORE2 */
#define acmgt2__dataport29__dataport_byte_write_xecore2__read \
   acmgt1__ext83__dataport_byte_write_xecore2__read

/* Dataport29 :: DATAPORT BYTE WRITE XECORE3 */
#define acmgt2__dataport29__dataport_byte_write_xecore3__read \
   acmgt1__ext83__dataport_byte_write_xecore3__read

/* Dataport29 :: DATAPORT BYTE WRITE XECORE4 */
#define acmgt2__dataport29__dataport_byte_write_xecore4__read \
   acmgt1__ext83__dataport_byte_write_xecore4__read

/* Dataport29 :: DATAPORT BYTE WRITE XECORE5 */
#define acmgt2__dataport29__dataport_byte_write_xecore5__read \
   acmgt1__ext83__dataport_byte_write_xecore5__read

/* Dataport29 :: DATAPORT BYTE WRITE XECORE6 */
#define acmgt2__dataport29__dataport_byte_write_xecore6__read \
   acmgt1__ext83__dataport_byte_write_xecore6__read

/* Dataport29 :: DATAPORT BYTE WRITE XECORE7 */
#define acmgt2__dataport29__dataport_byte_write_xecore7__read \
   acmgt1__ext83__dataport_byte_write_xecore7__read

/* Dataport29 :: DATAPORT BYTE WRITE XECORE8 */
static uint64_t
acmgt2__dataport29__dataport_byte_write_xecore8__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  B 7 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Dataport29 :: DATAPORT BYTE WRITE XECORE9 */
static uint64_t
acmgt2__dataport29__dataport_byte_write_xecore9__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  B 6 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Dataport29 :: DATAPORT BYTE WRITE XECORE10 */
static uint64_t
acmgt2__dataport29__dataport_byte_write_xecore10__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  B 5 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Dataport29 :: DATAPORT BYTE WRITE XECORE11 */
static uint64_t
acmgt2__dataport29__dataport_byte_write_xecore11__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  B 4 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Dataport29 :: DATAPORT BYTE WRITE XECORE12 */
static uint64_t
acmgt2__dataport29__dataport_byte_write_xecore12__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  B 3 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Dataport29 :: DATAPORT BYTE WRITE XECORE13 */
static uint64_t
acmgt2__dataport29__dataport_byte_write_xecore13__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  B 2 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Dataport29 :: DATAPORT BYTE WRITE XECORE14 */
static uint64_t
acmgt2__dataport29__dataport_byte_write_xecore14__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  B 1 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Dataport29 :: DATAPORT BYTE WRITE XECORE15 */
static uint64_t
acmgt2__dataport29__dataport_byte_write_xecore15__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  B 0 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Dataport30 :: GPU Time Elapsed */
#define acmgt2__dataport30__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport30 :: GPU Core Clocks */
#define acmgt2__dataport30__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport30 :: AVG GPU Core Frequency */
#define acmgt2__dataport30__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport30 :: AVG GPU Core Frequency */
#define acmgt2__dataport30__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport30 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE0 */
#define acmgt2__dataport30__xve_dataport_register_request_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Dataport30 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE1 */
#define acmgt2__dataport30__xve_dataport_register_request_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Dataport30 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE2 */
#define acmgt2__dataport30__xve_dataport_register_request_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Dataport30 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE3 */
#define acmgt2__dataport30__xve_dataport_register_request_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Dataport30 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE4 */
#define acmgt2__dataport30__xve_dataport_register_request_count_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Dataport30 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE5 */
#define acmgt2__dataport30__xve_dataport_register_request_count_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Dataport30 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE6 */
#define acmgt2__dataport30__xve_dataport_register_request_count_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Dataport30 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE7 */
#define acmgt2__dataport30__xve_dataport_register_request_count_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Dataport31 :: GPU Time Elapsed */
#define acmgt2__dataport31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport31 :: GPU Core Clocks */
#define acmgt2__dataport31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport31 :: AVG GPU Core Frequency */
#define acmgt2__dataport31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport31 :: AVG GPU Core Frequency */
#define acmgt2__dataport31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport31 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE8 */
#define acmgt2__dataport31__xve_dataport_register_request_count_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Dataport31 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE9 */
#define acmgt2__dataport31__xve_dataport_register_request_count_xecore9__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Dataport31 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE10 */
#define acmgt2__dataport31__xve_dataport_register_request_count_xecore10__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Dataport31 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE11 */
#define acmgt2__dataport31__xve_dataport_register_request_count_xecore11__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Dataport31 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE12 */
#define acmgt2__dataport31__xve_dataport_register_request_count_xecore12__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Dataport31 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE13 */
#define acmgt2__dataport31__xve_dataport_register_request_count_xecore13__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Dataport31 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE14 */
#define acmgt2__dataport31__xve_dataport_register_request_count_xecore14__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Dataport31 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE15 */
#define acmgt2__dataport31__xve_dataport_register_request_count_xecore15__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Dataport32 :: GPU Time Elapsed */
#define acmgt2__dataport32__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport32 :: GPU Core Clocks */
#define acmgt2__dataport32__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport32 :: AVG GPU Core Frequency */
#define acmgt2__dataport32__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport32 :: AVG GPU Core Frequency */
#define acmgt2__dataport32__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport32 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE0 */
#define acmgt2__dataport32__xve_dataport_register_response_count_xecore0__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore0__read

/* Dataport32 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE1 */
#define acmgt2__dataport32__xve_dataport_register_response_count_xecore1__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Dataport33 :: GPU Time Elapsed */
#define acmgt2__dataport33__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport33 :: GPU Core Clocks */
#define acmgt2__dataport33__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport33 :: AVG GPU Core Frequency */
#define acmgt2__dataport33__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport33 :: AVG GPU Core Frequency */
#define acmgt2__dataport33__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport33 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE2 */
#define acmgt2__dataport33__xve_dataport_register_response_count_xecore2__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Dataport33 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE3 */
#define acmgt2__dataport33__xve_dataport_register_response_count_xecore3__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Dataport34 :: GPU Time Elapsed */
#define acmgt2__dataport34__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport34 :: GPU Core Clocks */
#define acmgt2__dataport34__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport34 :: AVG GPU Core Frequency */
#define acmgt2__dataport34__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport34 :: AVG GPU Core Frequency */
#define acmgt2__dataport34__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport34 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE4 */
#define acmgt2__dataport34__xve_dataport_register_response_count_xecore4__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Dataport34 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE5 */
#define acmgt2__dataport34__xve_dataport_register_response_count_xecore5__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Dataport35 :: GPU Time Elapsed */
#define acmgt2__dataport35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport35 :: GPU Core Clocks */
#define acmgt2__dataport35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport35 :: AVG GPU Core Frequency */
#define acmgt2__dataport35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport35 :: AVG GPU Core Frequency */
#define acmgt2__dataport35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport35 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE6 */
#define acmgt2__dataport35__xve_dataport_register_response_count_xecore6__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Dataport35 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE7 */
#define acmgt2__dataport35__xve_dataport_register_response_count_xecore7__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Dataport36 :: GPU Time Elapsed */
#define acmgt2__dataport36__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport36 :: GPU Core Clocks */
#define acmgt2__dataport36__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport36 :: AVG GPU Core Frequency */
#define acmgt2__dataport36__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport36 :: AVG GPU Core Frequency */
#define acmgt2__dataport36__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport36 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE8 */
#define acmgt2__dataport36__xve_dataport_register_response_count_xecore8__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Dataport36 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE9 */
#define acmgt2__dataport36__xve_dataport_register_response_count_xecore9__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Dataport37 :: GPU Time Elapsed */
#define acmgt2__dataport37__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport37 :: GPU Core Clocks */
#define acmgt2__dataport37__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport37 :: AVG GPU Core Frequency */
#define acmgt2__dataport37__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport37 :: AVG GPU Core Frequency */
#define acmgt2__dataport37__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport37 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE10 */
#define acmgt2__dataport37__xve_dataport_register_response_count_xecore10__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Dataport37 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE11 */
#define acmgt2__dataport37__xve_dataport_register_response_count_xecore11__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Dataport38 :: GPU Time Elapsed */
#define acmgt2__dataport38__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport38 :: GPU Core Clocks */
#define acmgt2__dataport38__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport38 :: AVG GPU Core Frequency */
#define acmgt2__dataport38__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport38 :: AVG GPU Core Frequency */
#define acmgt2__dataport38__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport38 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE12 */
#define acmgt2__dataport38__xve_dataport_register_response_count_xecore12__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Dataport38 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE13 */
#define acmgt2__dataport38__xve_dataport_register_response_count_xecore13__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Dataport39 :: GPU Time Elapsed */
#define acmgt2__dataport39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport39 :: GPU Core Clocks */
#define acmgt2__dataport39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport39 :: AVG GPU Core Frequency */
#define acmgt2__dataport39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport39 :: AVG GPU Core Frequency */
#define acmgt2__dataport39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport39 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE14 */
#define acmgt2__dataport39__xve_dataport_register_response_count_xecore14__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Dataport39 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE15 */
#define acmgt2__dataport39__xve_dataport_register_response_count_xecore15__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Dataport40 :: GPU Time Elapsed */
#define acmgt2__dataport40__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport40 :: GPU Core Clocks */
#define acmgt2__dataport40__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport40 :: AVG GPU Core Frequency */
#define acmgt2__dataport40__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport40 :: AVG GPU Core Frequency */
#define acmgt2__dataport40__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE0 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE1 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE2 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE3 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE4 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE5 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE6 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE7 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE8 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore8__read \
   hsw__compute_extended__gpu_clocks__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE9 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE10 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE11 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE12 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE13 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE14 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport40 :: DATAPORT TEXTURE CACHE ACCESS XECORE15 */
#define acmgt2__dataport40__dataport_texture_cache_access_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Dataport41 :: GPU Time Elapsed */
#define acmgt2__dataport41__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Dataport41 :: GPU Core Clocks */
#define acmgt2__dataport41__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Dataport41 :: AVG GPU Core Frequency */
#define acmgt2__dataport41__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Dataport41 :: AVG GPU Core Frequency */
#define acmgt2__dataport41__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE0 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE1 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE2 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE3 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE4 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE5 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE6 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE7 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE8 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore8__read \
   hsw__compute_extended__gpu_clocks__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE9 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE10 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE11 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE12 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE13 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE14 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Dataport41 :: DATAPORT TEXTURE CACHE HIT XECORE15 */
#define acmgt2__dataport41__dataport_texture_cache_hit_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* DepthPipe1 :: GPU Time Elapsed */
#define acmgt2__depth_pipe1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe1 :: GPU Core Clocks */
#define acmgt2__depth_pipe1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe1 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe1 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe1 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0 */
#define acmgt2__depth_pipe1__early_depth_stencil_test_fail_np_zpipe0__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* DepthPipe1 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE0 */
#define acmgt2__depth_pipe1__early_depth_stencil_test_fail_p_zpipe0__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* DepthPipe2 :: GPU Time Elapsed */
#define acmgt2__depth_pipe2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe2 :: GPU Core Clocks */
#define acmgt2__depth_pipe2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe2 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe2 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe2 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1 */
#define acmgt2__depth_pipe2__early_depth_stencil_test_fail_np_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* DepthPipe2 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE1 */
#define acmgt2__depth_pipe2__early_depth_stencil_test_fail_p_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* DepthPipe3 :: GPU Time Elapsed */
#define acmgt2__depth_pipe3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe3 :: GPU Core Clocks */
#define acmgt2__depth_pipe3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe3 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe3 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe3 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2 */
#define acmgt2__depth_pipe3__early_depth_stencil_test_fail_np_zpipe2__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* DepthPipe3 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE2 */
#define acmgt2__depth_pipe3__early_depth_stencil_test_fail_p_zpipe2__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* DepthPipe4 :: GPU Time Elapsed */
#define acmgt2__depth_pipe4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe4 :: GPU Core Clocks */
#define acmgt2__depth_pipe4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe4 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe4 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe4 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3 */
#define acmgt2__depth_pipe4__early_depth_stencil_test_fail_np_zpipe3__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* DepthPipe4 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE3 */
#define acmgt2__depth_pipe4__early_depth_stencil_test_fail_p_zpipe3__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* DepthPipe5 :: GPU Time Elapsed */
#define acmgt2__depth_pipe5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe5 :: GPU Core Clocks */
#define acmgt2__depth_pipe5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe5 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe5 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe5 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE4 */
#define acmgt2__depth_pipe5__early_depth_stencil_test_fail_np_zpipe4__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* DepthPipe5 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE4 */
#define acmgt2__depth_pipe5__early_depth_stencil_test_fail_p_zpipe4__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* DepthPipe6 :: GPU Time Elapsed */
#define acmgt2__depth_pipe6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe6 :: GPU Core Clocks */
#define acmgt2__depth_pipe6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe6 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe6 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe6 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE5 */
#define acmgt2__depth_pipe6__early_depth_stencil_test_fail_np_zpipe5__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* DepthPipe6 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE5 */
#define acmgt2__depth_pipe6__early_depth_stencil_test_fail_p_zpipe5__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* DepthPipe7 :: GPU Time Elapsed */
#define acmgt2__depth_pipe7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe7 :: GPU Core Clocks */
#define acmgt2__depth_pipe7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe7 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe7 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe7 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE6 */
#define acmgt2__depth_pipe7__early_depth_stencil_test_fail_np_zpipe6__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* DepthPipe7 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE6 */
#define acmgt2__depth_pipe7__early_depth_stencil_test_fail_p_zpipe6__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* DepthPipe8 :: GPU Time Elapsed */
#define acmgt2__depth_pipe8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe8 :: GPU Core Clocks */
#define acmgt2__depth_pipe8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe8 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe8 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe8 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE7 */
#define acmgt2__depth_pipe8__early_depth_stencil_test_fail_np_zpipe7__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* DepthPipe8 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE7 */
#define acmgt2__depth_pipe8__early_depth_stencil_test_fail_p_zpipe7__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* DepthPipe9 :: GPU Time Elapsed */
#define acmgt2__depth_pipe9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe9 :: GPU Core Clocks */
#define acmgt2__depth_pipe9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe9 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe9 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe9 :: HIZ DEPTH TEST AMBIG NP ZPIPE0 */
#define acmgt2__depth_pipe9__hiz_depth_test_ambig_np_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe10 :: GPU Time Elapsed */
#define acmgt2__depth_pipe10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe10 :: GPU Core Clocks */
#define acmgt2__depth_pipe10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe10 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe10 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe10 :: HIZ DEPTH TEST AMBIG NP ZPIPE1 */
#define acmgt2__depth_pipe10__hiz_depth_test_ambig_np_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe11 :: GPU Time Elapsed */
#define acmgt2__depth_pipe11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe11 :: GPU Core Clocks */
#define acmgt2__depth_pipe11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe11 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe11 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe11 :: HIZ DEPTH TEST AMBIG NP ZPIPE2 */
#define acmgt2__depth_pipe11__hiz_depth_test_ambig_np_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe12 :: GPU Time Elapsed */
#define acmgt2__depth_pipe12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe12 :: GPU Core Clocks */
#define acmgt2__depth_pipe12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe12 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe12 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe12 :: HIZ DEPTH TEST AMBIG NP ZPIPE3 */
#define acmgt2__depth_pipe12__hiz_depth_test_ambig_np_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe13 :: GPU Time Elapsed */
#define acmgt2__depth_pipe13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe13 :: GPU Core Clocks */
#define acmgt2__depth_pipe13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe13 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe13 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe13 :: HIZ DEPTH TEST AMBIG NP ZPIPE4 */
#define acmgt2__depth_pipe13__hiz_depth_test_ambig_np_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe14 :: GPU Time Elapsed */
#define acmgt2__depth_pipe14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe14 :: GPU Core Clocks */
#define acmgt2__depth_pipe14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe14 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe14 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe14 :: HIZ DEPTH TEST AMBIG NP ZPIPE5 */
#define acmgt2__depth_pipe14__hiz_depth_test_ambig_np_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe15 :: GPU Time Elapsed */
#define acmgt2__depth_pipe15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe15 :: GPU Core Clocks */
#define acmgt2__depth_pipe15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe15 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe15 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe15 :: HIZ DEPTH TEST AMBIG NP ZPIPE6 */
#define acmgt2__depth_pipe15__hiz_depth_test_ambig_np_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe16 :: GPU Time Elapsed */
#define acmgt2__depth_pipe16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe16 :: GPU Core Clocks */
#define acmgt2__depth_pipe16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe16 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe16 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe16 :: HIZ DEPTH TEST AMBIG NP ZPIPE7 */
#define acmgt2__depth_pipe16__hiz_depth_test_ambig_np_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe17 :: GPU Time Elapsed */
#define acmgt2__depth_pipe17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe17 :: GPU Core Clocks */
#define acmgt2__depth_pipe17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe17 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe17 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe17 :: HIZ DEPTH TEST AMBIG P ZPIPE0 */
#define acmgt2__depth_pipe17__hiz_depth_test_ambig_p_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe18 :: GPU Time Elapsed */
#define acmgt2__depth_pipe18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe18 :: GPU Core Clocks */
#define acmgt2__depth_pipe18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe18 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe18 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe18 :: HIZ DEPTH TEST AMBIG P ZPIPE1 */
#define acmgt2__depth_pipe18__hiz_depth_test_ambig_p_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe19 :: GPU Time Elapsed */
#define acmgt2__depth_pipe19__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe19 :: GPU Core Clocks */
#define acmgt2__depth_pipe19__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe19 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe19__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe19 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe19__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe19 :: HIZ DEPTH TEST AMBIG P ZPIPE2 */
#define acmgt2__depth_pipe19__hiz_depth_test_ambig_p_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe20 :: GPU Time Elapsed */
#define acmgt2__depth_pipe20__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe20 :: GPU Core Clocks */
#define acmgt2__depth_pipe20__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe20 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe20__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe20 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe20__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe20 :: HIZ DEPTH TEST AMBIG P ZPIPE3 */
#define acmgt2__depth_pipe20__hiz_depth_test_ambig_p_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe21 :: GPU Time Elapsed */
#define acmgt2__depth_pipe21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe21 :: GPU Core Clocks */
#define acmgt2__depth_pipe21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe21 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe21 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe21 :: HIZ DEPTH TEST AMBIG P ZPIPE4 */
#define acmgt2__depth_pipe21__hiz_depth_test_ambig_p_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe22 :: GPU Time Elapsed */
#define acmgt2__depth_pipe22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe22 :: GPU Core Clocks */
#define acmgt2__depth_pipe22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe22 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe22 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe22 :: HIZ DEPTH TEST AMBIG P ZPIPE5 */
#define acmgt2__depth_pipe22__hiz_depth_test_ambig_p_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe23 :: GPU Time Elapsed */
#define acmgt2__depth_pipe23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe23 :: GPU Core Clocks */
#define acmgt2__depth_pipe23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe23 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe23 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe23 :: HIZ DEPTH TEST AMBIG P ZPIPE6 */
#define acmgt2__depth_pipe23__hiz_depth_test_ambig_p_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe24 :: GPU Time Elapsed */
#define acmgt2__depth_pipe24__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe24 :: GPU Core Clocks */
#define acmgt2__depth_pipe24__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe24 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe24__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe24 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe24__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe24 :: HIZ DEPTH TEST AMBIG P ZPIPE7 */
#define acmgt2__depth_pipe24__hiz_depth_test_ambig_p_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe25 :: GPU Time Elapsed */
#define acmgt2__depth_pipe25__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe25 :: GPU Core Clocks */
#define acmgt2__depth_pipe25__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe25 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe25__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe25 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe25__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe25 :: HIZ DEPTH TEST FAIL NP ZPIPE0 */
#define acmgt2__depth_pipe25__hiz_depth_test_fail_np_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe26 :: GPU Time Elapsed */
#define acmgt2__depth_pipe26__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe26 :: GPU Core Clocks */
#define acmgt2__depth_pipe26__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe26 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe26__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe26 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe26__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe26 :: HIZ DEPTH TEST FAIL NP ZPIPE1 */
#define acmgt2__depth_pipe26__hiz_depth_test_fail_np_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe27 :: GPU Time Elapsed */
#define acmgt2__depth_pipe27__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe27 :: GPU Core Clocks */
#define acmgt2__depth_pipe27__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe27 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe27__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe27 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe27__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe27 :: HIZ DEPTH TEST FAIL NP ZPIPE2 */
#define acmgt2__depth_pipe27__hiz_depth_test_fail_np_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe28 :: GPU Time Elapsed */
#define acmgt2__depth_pipe28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe28 :: GPU Core Clocks */
#define acmgt2__depth_pipe28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe28 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe28 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe28 :: HIZ DEPTH TEST FAIL NP ZPIPE3 */
#define acmgt2__depth_pipe28__hiz_depth_test_fail_np_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe29 :: GPU Time Elapsed */
#define acmgt2__depth_pipe29__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe29 :: GPU Core Clocks */
#define acmgt2__depth_pipe29__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe29 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe29__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe29 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe29__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe29 :: HIZ DEPTH TEST FAIL NP ZPIPE4 */
#define acmgt2__depth_pipe29__hiz_depth_test_fail_np_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe30 :: GPU Time Elapsed */
#define acmgt2__depth_pipe30__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe30 :: GPU Core Clocks */
#define acmgt2__depth_pipe30__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe30 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe30__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe30 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe30__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe30 :: HIZ DEPTH TEST FAIL NP ZPIPE5 */
#define acmgt2__depth_pipe30__hiz_depth_test_fail_np_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe31 :: GPU Time Elapsed */
#define acmgt2__depth_pipe31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe31 :: GPU Core Clocks */
#define acmgt2__depth_pipe31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe31 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe31 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe31 :: HIZ DEPTH TEST FAIL NP ZPIPE6 */
#define acmgt2__depth_pipe31__hiz_depth_test_fail_np_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe32 :: GPU Time Elapsed */
#define acmgt2__depth_pipe32__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe32 :: GPU Core Clocks */
#define acmgt2__depth_pipe32__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe32 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe32__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe32 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe32__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe32 :: HIZ DEPTH TEST FAIL NP ZPIPE7 */
#define acmgt2__depth_pipe32__hiz_depth_test_fail_np_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe33 :: GPU Time Elapsed */
#define acmgt2__depth_pipe33__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe33 :: GPU Core Clocks */
#define acmgt2__depth_pipe33__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe33 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe33__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe33 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe33__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe33 :: HIZ DEPTH TEST FAIL P ZPIPE0 */
#define acmgt2__depth_pipe33__hiz_depth_test_fail_p_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe34 :: GPU Time Elapsed */
#define acmgt2__depth_pipe34__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe34 :: GPU Core Clocks */
#define acmgt2__depth_pipe34__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe34 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe34__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe34 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe34__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe34 :: HIZ DEPTH TEST FAIL P ZPIPE1 */
#define acmgt2__depth_pipe34__hiz_depth_test_fail_p_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe35 :: GPU Time Elapsed */
#define acmgt2__depth_pipe35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe35 :: GPU Core Clocks */
#define acmgt2__depth_pipe35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe35 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe35 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe35 :: HIZ DEPTH TEST FAIL P ZPIPE2 */
#define acmgt2__depth_pipe35__hiz_depth_test_fail_p_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe36 :: GPU Time Elapsed */
#define acmgt2__depth_pipe36__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe36 :: GPU Core Clocks */
#define acmgt2__depth_pipe36__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe36 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe36__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe36 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe36__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe36 :: HIZ DEPTH TEST FAIL P ZPIPE3 */
#define acmgt2__depth_pipe36__hiz_depth_test_fail_p_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe37 :: GPU Time Elapsed */
#define acmgt2__depth_pipe37__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe37 :: GPU Core Clocks */
#define acmgt2__depth_pipe37__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe37 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe37__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe37 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe37__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe37 :: HIZ DEPTH TEST FAIL P ZPIPE4 */
#define acmgt2__depth_pipe37__hiz_depth_test_fail_p_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe38 :: GPU Time Elapsed */
#define acmgt2__depth_pipe38__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe38 :: GPU Core Clocks */
#define acmgt2__depth_pipe38__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe38 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe38__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe38 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe38__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe38 :: HIZ DEPTH TEST FAIL P ZPIPE5 */
#define acmgt2__depth_pipe38__hiz_depth_test_fail_p_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe39 :: GPU Time Elapsed */
#define acmgt2__depth_pipe39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe39 :: GPU Core Clocks */
#define acmgt2__depth_pipe39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe39 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe39 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe39 :: HIZ DEPTH TEST FAIL P ZPIPE6 */
#define acmgt2__depth_pipe39__hiz_depth_test_fail_p_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe40 :: GPU Time Elapsed */
#define acmgt2__depth_pipe40__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe40 :: GPU Core Clocks */
#define acmgt2__depth_pipe40__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe40 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe40__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe40 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe40__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe40 :: HIZ DEPTH TEST FAIL P ZPIPE7 */
#define acmgt2__depth_pipe40__hiz_depth_test_fail_p_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe41 :: GPU Time Elapsed */
#define acmgt2__depth_pipe41__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe41 :: GPU Core Clocks */
#define acmgt2__depth_pipe41__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe41 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe41__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe41 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe41__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe41 :: HIZ DEPTH TEST PASS P ZPIPE0 */
#define acmgt2__depth_pipe41__hiz_depth_test_pass_p_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe42 :: GPU Time Elapsed */
#define acmgt2__depth_pipe42__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe42 :: GPU Core Clocks */
#define acmgt2__depth_pipe42__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe42 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe42__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe42 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe42__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe42 :: HIZ DEPTH TEST PASS P ZPIPE1 */
#define acmgt2__depth_pipe42__hiz_depth_test_pass_p_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe43 :: GPU Time Elapsed */
#define acmgt2__depth_pipe43__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe43 :: GPU Core Clocks */
#define acmgt2__depth_pipe43__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe43 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe43__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe43 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe43__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe43 :: HIZ DEPTH TEST PASS P ZPIPE2 */
#define acmgt2__depth_pipe43__hiz_depth_test_pass_p_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe44 :: GPU Time Elapsed */
#define acmgt2__depth_pipe44__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe44 :: GPU Core Clocks */
#define acmgt2__depth_pipe44__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe44 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe44__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe44 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe44__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe44 :: HIZ DEPTH TEST PASS P ZPIPE3 */
#define acmgt2__depth_pipe44__hiz_depth_test_pass_p_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe45 :: GPU Time Elapsed */
#define acmgt2__depth_pipe45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe45 :: GPU Core Clocks */
#define acmgt2__depth_pipe45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe45 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe45 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe45 :: HIZ DEPTH TEST PASS P ZPIPE4 */
#define acmgt2__depth_pipe45__hiz_depth_test_pass_p_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe46 :: GPU Time Elapsed */
#define acmgt2__depth_pipe46__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe46 :: GPU Core Clocks */
#define acmgt2__depth_pipe46__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe46 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe46__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe46 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe46__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe46 :: HIZ DEPTH TEST PASS P ZPIPE5 */
#define acmgt2__depth_pipe46__hiz_depth_test_pass_p_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe47 :: GPU Time Elapsed */
#define acmgt2__depth_pipe47__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe47 :: GPU Core Clocks */
#define acmgt2__depth_pipe47__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe47 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe47__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe47 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe47__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe47 :: HIZ DEPTH TEST PASS P ZPIPE6 */
#define acmgt2__depth_pipe47__hiz_depth_test_pass_p_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe48 :: GPU Time Elapsed */
#define acmgt2__depth_pipe48__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe48 :: GPU Core Clocks */
#define acmgt2__depth_pipe48__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe48 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe48__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe48 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe48__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe48 :: HIZ DEPTH TEST PASS P ZPIPE7 */
#define acmgt2__depth_pipe48__hiz_depth_test_pass_p_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* DepthPipe49 :: GPU Time Elapsed */
#define acmgt2__depth_pipe49__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe49 :: GPU Core Clocks */
#define acmgt2__depth_pipe49__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe49 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe49__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe49 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe49__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe49 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* DepthPipe49 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* DepthPipe49 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2 */
#define acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* DepthPipe49 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3 */
#define acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* DepthPipe49 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE4 */
#define acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe4__read \
   bdw__render_pipe_profile__so_stall__read

/* DepthPipe49 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE5 */
#define acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe5__read \
   bdw__render_pipe_profile__ds_stall__read

/* DepthPipe49 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE6 */
#define acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe6__read \
   bdw__render_pipe_profile__hs_stall__read

/* DepthPipe49 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE7 */
#define acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* DepthPipe49 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* DepthPipe49 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* DepthPipe49 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE2 */
#define acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* DepthPipe49 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE3 */
#define acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* DepthPipe49 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE4 */
#define acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* DepthPipe49 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE5 */
#define acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* DepthPipe49 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE6 */
#define acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe6__read \
   bdw__render_basic__sampler1_busy__read

/* DepthPipe49 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE7 */
#define acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe7__read \
   bdw__render_basic__sampler0_busy__read

/* DepthPipe50 :: GPU Time Elapsed */
#define acmgt2__depth_pipe50__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DepthPipe50 :: GPU Core Clocks */
#define acmgt2__depth_pipe50__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DepthPipe50 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe50__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DepthPipe50 :: AVG GPU Core Frequency */
#define acmgt2__depth_pipe50__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DepthPipe50 :: IZ OUTPUT READY ZPIPE0 */
#define acmgt2__depth_pipe50__iz_output_ready_zpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* DepthPipe50 :: IZ OUTPUT READY ZPIPE1 */
#define acmgt2__depth_pipe50__iz_output_ready_zpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* DepthPipe50 :: IZ OUTPUT READY ZPIPE2 */
#define acmgt2__depth_pipe50__iz_output_ready_zpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* DepthPipe50 :: IZ OUTPUT READY ZPIPE3 */
#define acmgt2__depth_pipe50__iz_output_ready_zpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* DepthPipe50 :: IZ OUTPUT READY ZPIPE4 */
#define acmgt2__depth_pipe50__iz_output_ready_zpipe4__read \
   bdw__render_pipe_profile__so_stall__read

/* DepthPipe50 :: IZ OUTPUT READY ZPIPE5 */
#define acmgt2__depth_pipe50__iz_output_ready_zpipe5__read \
   bdw__render_pipe_profile__ds_stall__read

/* DepthPipe50 :: IZ OUTPUT READY ZPIPE6 */
#define acmgt2__depth_pipe50__iz_output_ready_zpipe6__read \
   bdw__render_pipe_profile__hs_stall__read

/* DepthPipe50 :: IZ OUTPUT READY ZPIPE7 */
#define acmgt2__depth_pipe50__iz_output_ready_zpipe7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* FrontEnd1 :: GPU Time Elapsed */
#define acmgt2__front_end1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* FrontEnd1 :: GPU Core Clocks */
#define acmgt2__front_end1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* FrontEnd1 :: AVG GPU Core Frequency */
#define acmgt2__front_end1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* FrontEnd1 :: AVG GPU Core Frequency */
#define acmgt2__front_end1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* FrontEnd1 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS0 */
#define acmgt2__front_end1__command_parser_compute_engine_busy_ccs0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* FrontEnd1 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS1 */
#define acmgt2__front_end1__command_parser_compute_engine_busy_ccs1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* FrontEnd1 :: COMMAND PARSER COMPUTE ENGINE BUSY */
static float
acmgt2__front_end1__command_parser_compute_engine_busy__read(UNUSED struct intel_perf_config *perf,
                                                             const struct intel_perf_query_info *query,
                                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ  C 6 READ FADD 2 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   double tmp6 = tmp5;
   double tmp7 = acmgt2__front_end1__gpu_core_clocks__read(perf, query, results);
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;

   return tmp8;
}

/* FrontEnd1 :: COMMAND PARSER RENDER ENGINE BUSY */
#define acmgt2__front_end1__command_parser_render_engine_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* FrontEnd1 :: COMMAND PARSER COPY ENGINE BUSY */
#define acmgt2__front_end1__command_parser_copy_engine_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* FrontEnd1 :: COMMAND PARSER VIDEO ENGINE BUSY VDBOX0 */
#define acmgt2__front_end1__command_parser_video_engine_busy_vdbox0__read \
   bdw__render_pipe_profile__so_stall__read

/* FrontEnd1 :: COMMAND PARSER VIDEO ENGINE BUSY VDBOX1 */
#define acmgt2__front_end1__command_parser_video_engine_busy_vdbox1__read \
   bdw__render_pipe_profile__ds_stall__read

/* FrontEnd1 :: COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX0 */
#define acmgt2__front_end1__command_parser_video_enhancement_engine_busy_vebox0__read \
   bdw__render_pipe_profile__hs_stall__read

/* FrontEnd1 :: COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX1 */
#define acmgt2__front_end1__command_parser_video_enhancement_engine_busy_vebox1__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* FrontEnd1 :: COMMAND PARSER VIDEO ENGINE BUSY */
static float
acmgt2__front_end1__command_parser_video_engine_busy__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ  C 2 READ FADD 2 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   double tmp6 = tmp5;
   double tmp7 = acmgt2__front_end1__gpu_core_clocks__read(perf, query, results);
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;

   return tmp8;
}

/* FrontEnd1 :: COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY */
static float
acmgt2__front_end1__command_parser_video_enhancement_engine_busy__read(UNUSED struct intel_perf_config *perf,
                                                                       const struct intel_perf_query_info *query,
                                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ  C 0 READ FADD 2 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 0];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   double tmp6 = tmp5;
   double tmp7 = acmgt2__front_end1__gpu_core_clocks__read(perf, query, results);
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;

   return tmp8;
}

/* FrontEnd1 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0 */
#define acmgt2__front_end1__command_parser_compute_engine_dispatch_kernel_count_ccs0__read \
   hsw__compute_extended__gpu_clocks__read

/* FrontEnd1 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS1 */
#define acmgt2__front_end1__command_parser_compute_engine_dispatch_kernel_count_ccs1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* FrontEnd1 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT */
#define acmgt2__front_end1__command_parser_compute_engine_dispatch_kernel_count__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* FrontEnd1 :: COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT */
#define acmgt2__front_end1__command_parser_render_engine_dispatch_kernel_count__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* FrontEnd1 :: COMMAND PARSER FLUSH COUNT */
#define acmgt2__front_end1__command_parser_flush_count__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* FrontEnd1 :: COMMAND PARSER RENDER ENGINE DRAW COUNT */
#define acmgt2__front_end1__command_parser_render_engine_draw_count__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Geometry1 :: CLIPPER INPUT VERTEX SLICE0 */
#define acmgt2__geometry1__clipper_input_vertex_slice0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Geometry1 :: CLIPPER INPUT VERTEX SLICE1 */
#define acmgt2__geometry1__clipper_input_vertex_slice1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Geometry1 :: CLIPPER INPUT VERTEX SLICE2 */
#define acmgt2__geometry1__clipper_input_vertex_slice2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Geometry1 :: CLIPPER INPUT VERTEX SLICE3 */
#define acmgt2__geometry1__clipper_input_vertex_slice3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Geometry1 :: STREAMOUT OUTPUT VERTEX COUNT SLICE0 */
#define acmgt2__geometry1__streamout_output_vertex_count_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Geometry1 :: STREAMOUT OUTPUT VERTEX COUNT SLICE1 */
#define acmgt2__geometry1__streamout_output_vertex_count_slice1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Geometry1 :: STREAMOUT OUTPUT VERTEX COUNT SLICE2 */
#define acmgt2__geometry1__streamout_output_vertex_count_slice2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Geometry1 :: STREAMOUT OUTPUT VERTEX COUNT SLICE3 */
#define acmgt2__geometry1__streamout_output_vertex_count_slice3__read \
   hsw__compute_extended__typed_atomics0__read

/* Geometry1 :: GPU Core Clocks */
#define acmgt2__geometry1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Geometry2 :: GPU Core Clocks */
#define acmgt2__geometry2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Geometry2 :: VERTEX FETCH INPUT AVAILABLE SLICE0 */
#define acmgt2__geometry2__vertex_fetch_input_available_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Geometry2 :: VERTEX FETCH INPUT AVAILABLE SLICE1 */
#define acmgt2__geometry2__vertex_fetch_input_available_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Geometry2 :: VERTEX FETCH INPUT AVAILABLE SLICE2 */
#define acmgt2__geometry2__vertex_fetch_input_available_slice2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Geometry2 :: VERTEX FETCH INPUT AVAILABLE SLICE3 */
#define acmgt2__geometry2__vertex_fetch_input_available_slice3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Geometry2 :: VERTEX FETCH OUTPUT READY SLICE0 */
#define acmgt2__geometry2__vertex_fetch_output_ready_slice0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Geometry2 :: VERTEX FETCH OUTPUT READY SLICE1 */
#define acmgt2__geometry2__vertex_fetch_output_ready_slice1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Geometry2 :: VERTEX FETCH OUTPUT READY SLICE2 */
#define acmgt2__geometry2__vertex_fetch_output_ready_slice2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Geometry2 :: VERTEX FETCH OUTPUT READY SLICE3 */
#define acmgt2__geometry2__vertex_fetch_output_ready_slice3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Geometry2 :: CLIPPER INPUT AVAILABLE SLICE0 */
#define acmgt2__geometry2__clipper_input_available_slice0__read \
   bdw__render_pipe_profile__so_stall__read

/* Geometry2 :: CLIPPER INPUT AVAILABLE SLICE1 */
#define acmgt2__geometry2__clipper_input_available_slice1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Geometry2 :: CLIPPER INPUT AVAILABLE SLICE2 */
#define acmgt2__geometry2__clipper_input_available_slice2__read \
   bdw__render_pipe_profile__hs_stall__read

/* Geometry2 :: CLIPPER INPUT AVAILABLE SLICE3 */
#define acmgt2__geometry2__clipper_input_available_slice3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Geometry2 :: CLIPPER OUTPUT READY SLICE0 */
#define acmgt2__geometry2__clipper_output_ready_slice0__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Geometry2 :: CLIPPER OUTPUT READY SLICE1 */
#define acmgt2__geometry2__clipper_output_ready_slice1__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Geometry2 :: CLIPPER OUTPUT READY SLICE2 */
#define acmgt2__geometry2__clipper_output_ready_slice2__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Geometry2 :: CLIPPER OUTPUT READY SLICE3 */
#define acmgt2__geometry2__clipper_output_ready_slice3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Geometry3 :: GPU Core Clocks */
#define acmgt2__geometry3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Geometry3 :: STRIPSFAN OUTPUT READY SLICE0 */
#define acmgt2__geometry3__stripsfan_output_ready_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Geometry3 :: STRIPSFAN OUTPUT READY SLICE1 */
#define acmgt2__geometry3__stripsfan_output_ready_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Geometry3 :: STRIPSFAN OUTPUT READY SLICE2 */
#define acmgt2__geometry3__stripsfan_output_ready_slice2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Geometry3 :: STRIPSFAN OUTPUT READY SLICE3 */
#define acmgt2__geometry3__stripsfan_output_ready_slice3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Geometry3 :: VS OUTPUT READY SLICE0 */
#define acmgt2__geometry3__vs_output_ready_slice0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Geometry3 :: VS OUTPUT READY SLICE1 */
#define acmgt2__geometry3__vs_output_ready_slice1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Geometry3 :: VS OUTPUT READY SLICE2 */
#define acmgt2__geometry3__vs_output_ready_slice2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Geometry3 :: VS OUTPUT READY SLICE3 */
#define acmgt2__geometry3__vs_output_ready_slice3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Geometry3 :: CLIPPER PRIMITIVE CULL SLICE0 */
#define acmgt2__geometry3__clipper_primitive_cull_slice0__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Geometry3 :: CLIPPER PRIMITIVE CULL SLICE1 */
#define acmgt2__geometry3__clipper_primitive_cull_slice1__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Geometry3 :: CLIPPER PRIMITIVE CULL SLICE2 */
#define acmgt2__geometry3__clipper_primitive_cull_slice2__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Geometry3 :: CLIPPER PRIMITIVE CULL SLICE3 */
#define acmgt2__geometry3__clipper_primitive_cull_slice3__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Geometry4 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0 */
#define acmgt2__geometry4__clipper_primitive_far_near_clip_slice0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Geometry4 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1 */
#define acmgt2__geometry4__clipper_primitive_far_near_clip_slice1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Geometry4 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE2 */
#define acmgt2__geometry4__clipper_primitive_far_near_clip_slice2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Geometry4 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE3 */
#define acmgt2__geometry4__clipper_primitive_far_near_clip_slice3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Geometry4 :: CLIPPER PRIMITIVE OUTPUT SLICE0 */
#define acmgt2__geometry4__clipper_primitive_output_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Geometry4 :: CLIPPER PRIMITIVE OUTPUT SLICE1 */
#define acmgt2__geometry4__clipper_primitive_output_slice1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Geometry4 :: CLIPPER PRIMITIVE OUTPUT SLICE2 */
#define acmgt2__geometry4__clipper_primitive_output_slice2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Geometry4 :: CLIPPER PRIMITIVE OUTPUT SLICE3 */
#define acmgt2__geometry4__clipper_primitive_output_slice3__read \
   hsw__compute_extended__typed_atomics0__read

/* Geometry4 :: GPU Core Clocks */
#define acmgt2__geometry4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Geometry5 :: STRIPSFAN OBJECTS CULL SLICE0 */
#define acmgt2__geometry5__stripsfan_objects_cull_slice0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Geometry5 :: STRIPSFAN OBJECTS CULL SLICE1 */
#define acmgt2__geometry5__stripsfan_objects_cull_slice1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Geometry5 :: STRIPSFAN OBJECTS CULL SLICE2 */
#define acmgt2__geometry5__stripsfan_objects_cull_slice2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Geometry5 :: STRIPSFAN OBJECTS CULL SLICE3 */
#define acmgt2__geometry5__stripsfan_objects_cull_slice3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Geometry5 :: STRIPSFAN OBJECT COUNT SLICE0 */
#define acmgt2__geometry5__stripsfan_object_count_slice0__read \
   hsw__compute_extended__gpu_clocks__read

/* Geometry5 :: STRIPSFAN OBJECT COUNT SLICE1 */
#define acmgt2__geometry5__stripsfan_object_count_slice1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Geometry5 :: STRIPSFAN OBJECT COUNT SLICE2 */
#define acmgt2__geometry5__stripsfan_object_count_slice2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Geometry5 :: STRIPSFAN OBJECT COUNT SLICE3 */
#define acmgt2__geometry5__stripsfan_object_count_slice3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Geometry5 :: CLIPPER TRANSACTION OUTPUT SLICE0 */
#define acmgt2__geometry5__clipper_transaction_output_slice0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Geometry5 :: CLIPPER TRANSACTION OUTPUT SLICE1 */
#define acmgt2__geometry5__clipper_transaction_output_slice1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Geometry5 :: CLIPPER TRANSACTION OUTPUT SLICE2 */
#define acmgt2__geometry5__clipper_transaction_output_slice2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Geometry5 :: CLIPPER TRANSACTION OUTPUT SLICE3 */
#define acmgt2__geometry5__clipper_transaction_output_slice3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Geometry5 :: GPU Core Clocks */
#define acmgt2__geometry5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache1 :: GPU Time Elapsed */
#define acmgt2__l1_cache1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache1 :: GPU Core Clocks */
#define acmgt2__l1_cache1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache1 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache1 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache1 :: LOAD STORE CACHE INPUT AVAILABLE XECORE0 */
#define acmgt2__l1_cache1__load_store_cache_input_available_xecore0__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L1Cache1 :: LOAD STORE CACHE INPUT AVAILABLE XECORE1 */
#define acmgt2__l1_cache1__load_store_cache_input_available_xecore1__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L1Cache1 :: LOAD STORE CACHE INPUT AVAILABLE XECORE2 */
#define acmgt2__l1_cache1__load_store_cache_input_available_xecore2__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L1Cache1 :: LOAD STORE CACHE INPUT AVAILABLE XECORE3 */
#define acmgt2__l1_cache1__load_store_cache_input_available_xecore3__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L1Cache2 :: GPU Time Elapsed */
#define acmgt2__l1_cache2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache2 :: GPU Core Clocks */
#define acmgt2__l1_cache2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache2 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache2 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache2 :: LOAD STORE CACHE INPUT AVAILABLE XECORE4 */
#define acmgt2__l1_cache2__load_store_cache_input_available_xecore4__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L1Cache2 :: LOAD STORE CACHE INPUT AVAILABLE XECORE5 */
#define acmgt2__l1_cache2__load_store_cache_input_available_xecore5__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L1Cache2 :: LOAD STORE CACHE INPUT AVAILABLE XECORE6 */
#define acmgt2__l1_cache2__load_store_cache_input_available_xecore6__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L1Cache2 :: LOAD STORE CACHE INPUT AVAILABLE XECORE7 */
#define acmgt2__l1_cache2__load_store_cache_input_available_xecore7__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L1Cache3 :: GPU Time Elapsed */
#define acmgt2__l1_cache3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache3 :: GPU Core Clocks */
#define acmgt2__l1_cache3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache3 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache3 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache3 :: LOAD STORE CACHE INPUT AVAILABLE XECORE8 */
#define acmgt2__l1_cache3__load_store_cache_input_available_xecore8__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L1Cache3 :: LOAD STORE CACHE INPUT AVAILABLE XECORE9 */
#define acmgt2__l1_cache3__load_store_cache_input_available_xecore9__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L1Cache3 :: LOAD STORE CACHE INPUT AVAILABLE XECORE10 */
#define acmgt2__l1_cache3__load_store_cache_input_available_xecore10__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L1Cache3 :: LOAD STORE CACHE INPUT AVAILABLE XECORE11 */
#define acmgt2__l1_cache3__load_store_cache_input_available_xecore11__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L1Cache4 :: GPU Time Elapsed */
#define acmgt2__l1_cache4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache4 :: GPU Core Clocks */
#define acmgt2__l1_cache4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache4 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache4 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache4 :: LOAD STORE CACHE INPUT AVAILABLE XECORE12 */
#define acmgt2__l1_cache4__load_store_cache_input_available_xecore12__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L1Cache4 :: LOAD STORE CACHE INPUT AVAILABLE XECORE13 */
#define acmgt2__l1_cache4__load_store_cache_input_available_xecore13__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L1Cache4 :: LOAD STORE CACHE INPUT AVAILABLE XECORE14 */
#define acmgt2__l1_cache4__load_store_cache_input_available_xecore14__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L1Cache4 :: LOAD STORE CACHE INPUT AVAILABLE XECORE15 */
#define acmgt2__l1_cache4__load_store_cache_input_available_xecore15__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L1Cache5 :: GPU Time Elapsed */
#define acmgt2__l1_cache5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache5 :: GPU Core Clocks */
#define acmgt2__l1_cache5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache5 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache5 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache5 :: LOAD STORE CACHE OUTPUT READY XECORE0 */
#define acmgt2__l1_cache5__load_store_cache_output_ready_xecore0__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L1Cache5 :: LOAD STORE CACHE OUTPUT READY XECORE1 */
#define acmgt2__l1_cache5__load_store_cache_output_ready_xecore1__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L1Cache5 :: LOAD STORE CACHE OUTPUT READY XECORE2 */
#define acmgt2__l1_cache5__load_store_cache_output_ready_xecore2__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L1Cache5 :: LOAD STORE CACHE OUTPUT READY XECORE3 */
#define acmgt2__l1_cache5__load_store_cache_output_ready_xecore3__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L1Cache6 :: GPU Time Elapsed */
#define acmgt2__l1_cache6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache6 :: GPU Core Clocks */
#define acmgt2__l1_cache6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache6 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache6 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache6 :: LOAD STORE CACHE OUTPUT READY XECORE4 */
#define acmgt2__l1_cache6__load_store_cache_output_ready_xecore4__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L1Cache6 :: LOAD STORE CACHE OUTPUT READY XECORE5 */
#define acmgt2__l1_cache6__load_store_cache_output_ready_xecore5__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L1Cache6 :: LOAD STORE CACHE OUTPUT READY XECORE6 */
#define acmgt2__l1_cache6__load_store_cache_output_ready_xecore6__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L1Cache6 :: LOAD STORE CACHE OUTPUT READY XECORE7 */
#define acmgt2__l1_cache6__load_store_cache_output_ready_xecore7__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L1Cache7 :: GPU Time Elapsed */
#define acmgt2__l1_cache7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache7 :: GPU Core Clocks */
#define acmgt2__l1_cache7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache7 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache7 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache7 :: LOAD STORE CACHE OUTPUT READY XECORE8 */
#define acmgt2__l1_cache7__load_store_cache_output_ready_xecore8__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L1Cache7 :: LOAD STORE CACHE OUTPUT READY XECORE9 */
#define acmgt2__l1_cache7__load_store_cache_output_ready_xecore9__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L1Cache7 :: LOAD STORE CACHE OUTPUT READY XECORE10 */
#define acmgt2__l1_cache7__load_store_cache_output_ready_xecore10__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L1Cache7 :: LOAD STORE CACHE OUTPUT READY XECORE11 */
#define acmgt2__l1_cache7__load_store_cache_output_ready_xecore11__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L1Cache8 :: GPU Time Elapsed */
#define acmgt2__l1_cache8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache8 :: GPU Core Clocks */
#define acmgt2__l1_cache8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache8 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache8 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache8 :: LOAD STORE CACHE OUTPUT READY XECORE12 */
#define acmgt2__l1_cache8__load_store_cache_output_ready_xecore12__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* L1Cache8 :: LOAD STORE CACHE OUTPUT READY XECORE13 */
#define acmgt2__l1_cache8__load_store_cache_output_ready_xecore13__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* L1Cache8 :: LOAD STORE CACHE OUTPUT READY XECORE14 */
#define acmgt2__l1_cache8__load_store_cache_output_ready_xecore14__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* L1Cache8 :: LOAD STORE CACHE OUTPUT READY XECORE15 */
#define acmgt2__l1_cache8__load_store_cache_output_ready_xecore15__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* L1Cache9 :: GPU Time Elapsed */
#define acmgt2__l1_cache9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache9 :: GPU Core Clocks */
#define acmgt2__l1_cache9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache9 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache9 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache9 :: LOAD STORE CACHE L3 READ XECORE0 */
#define acmgt2__l1_cache9__load_store_cache_l3_read_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* L1Cache9 :: LOAD STORE CACHE L3 READ XECORE1 */
#define acmgt2__l1_cache9__load_store_cache_l3_read_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* L1Cache9 :: LOAD STORE CACHE L3 READ XECORE2 */
#define acmgt2__l1_cache9__load_store_cache_l3_read_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* L1Cache9 :: LOAD STORE CACHE L3 READ XECORE3 */
#define acmgt2__l1_cache9__load_store_cache_l3_read_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* L1Cache9 :: LOAD STORE CACHE L3 READ XECORE4 */
#define acmgt2__l1_cache9__load_store_cache_l3_read_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* L1Cache9 :: LOAD STORE CACHE L3 READ XECORE5 */
#define acmgt2__l1_cache9__load_store_cache_l3_read_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* L1Cache9 :: LOAD STORE CACHE L3 READ XECORE6 */
#define acmgt2__l1_cache9__load_store_cache_l3_read_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* L1Cache9 :: LOAD STORE CACHE L3 READ XECORE7 */
#define acmgt2__l1_cache9__load_store_cache_l3_read_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* L1Cache10 :: GPU Time Elapsed */
#define acmgt2__l1_cache10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache10 :: GPU Core Clocks */
#define acmgt2__l1_cache10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache10 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache10 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache10 :: LOAD STORE CACHE L3 READ XECORE8 */
#define acmgt2__l1_cache10__load_store_cache_l3_read_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* L1Cache10 :: LOAD STORE CACHE L3 READ XECORE9 */
#define acmgt2__l1_cache10__load_store_cache_l3_read_xecore9__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* L1Cache10 :: LOAD STORE CACHE L3 READ XECORE10 */
#define acmgt2__l1_cache10__load_store_cache_l3_read_xecore10__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* L1Cache10 :: LOAD STORE CACHE L3 READ XECORE11 */
#define acmgt2__l1_cache10__load_store_cache_l3_read_xecore11__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* L1Cache10 :: LOAD STORE CACHE L3 READ XECORE12 */
#define acmgt2__l1_cache10__load_store_cache_l3_read_xecore12__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* L1Cache10 :: LOAD STORE CACHE L3 READ XECORE13 */
#define acmgt2__l1_cache10__load_store_cache_l3_read_xecore13__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* L1Cache10 :: LOAD STORE CACHE L3 READ XECORE14 */
#define acmgt2__l1_cache10__load_store_cache_l3_read_xecore14__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* L1Cache10 :: LOAD STORE CACHE L3 READ XECORE15 */
#define acmgt2__l1_cache10__load_store_cache_l3_read_xecore15__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* L1Cache11 :: GPU Time Elapsed */
#define acmgt2__l1_cache11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache11 :: GPU Core Clocks */
#define acmgt2__l1_cache11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache11 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache11 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache11 :: LOAD STORE CACHE L3 WRITE XECORE0 */
#define acmgt2__l1_cache11__load_store_cache_l3_write_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* L1Cache11 :: LOAD STORE CACHE L3 WRITE XECORE1 */
#define acmgt2__l1_cache11__load_store_cache_l3_write_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* L1Cache11 :: LOAD STORE CACHE L3 WRITE XECORE2 */
#define acmgt2__l1_cache11__load_store_cache_l3_write_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* L1Cache11 :: LOAD STORE CACHE L3 WRITE XECORE3 */
#define acmgt2__l1_cache11__load_store_cache_l3_write_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* L1Cache11 :: LOAD STORE CACHE L3 WRITE XECORE4 */
#define acmgt2__l1_cache11__load_store_cache_l3_write_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* L1Cache11 :: LOAD STORE CACHE L3 WRITE XECORE5 */
#define acmgt2__l1_cache11__load_store_cache_l3_write_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* L1Cache11 :: LOAD STORE CACHE L3 WRITE XECORE6 */
#define acmgt2__l1_cache11__load_store_cache_l3_write_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* L1Cache11 :: LOAD STORE CACHE L3 WRITE XECORE7 */
#define acmgt2__l1_cache11__load_store_cache_l3_write_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* L1Cache12 :: GPU Time Elapsed */
#define acmgt2__l1_cache12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache12 :: GPU Core Clocks */
#define acmgt2__l1_cache12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache12 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache12 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache12 :: LOAD STORE CACHE L3 WRITE XECORE8 */
#define acmgt2__l1_cache12__load_store_cache_l3_write_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* L1Cache12 :: LOAD STORE CACHE L3 WRITE XECORE9 */
#define acmgt2__l1_cache12__load_store_cache_l3_write_xecore9__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* L1Cache12 :: LOAD STORE CACHE L3 WRITE XECORE10 */
#define acmgt2__l1_cache12__load_store_cache_l3_write_xecore10__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* L1Cache12 :: LOAD STORE CACHE L3 WRITE XECORE11 */
#define acmgt2__l1_cache12__load_store_cache_l3_write_xecore11__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* L1Cache12 :: LOAD STORE CACHE L3 WRITE XECORE12 */
#define acmgt2__l1_cache12__load_store_cache_l3_write_xecore12__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* L1Cache12 :: LOAD STORE CACHE L3 WRITE XECORE13 */
#define acmgt2__l1_cache12__load_store_cache_l3_write_xecore13__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* L1Cache12 :: LOAD STORE CACHE L3 WRITE XECORE14 */
#define acmgt2__l1_cache12__load_store_cache_l3_write_xecore14__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* L1Cache12 :: LOAD STORE CACHE L3 WRITE XECORE15 */
#define acmgt2__l1_cache12__load_store_cache_l3_write_xecore15__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* L1Cache13 :: GPU Time Elapsed */
#define acmgt2__l1_cache13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache13 :: GPU Core Clocks */
#define acmgt2__l1_cache13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache13 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache13 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache13 :: LOAD STORE CACHE ACCESS XECORE0 */
#define acmgt2__l1_cache13__load_store_cache_access_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache13 :: LOAD STORE CACHE ACCESS XECORE1 */
#define acmgt2__l1_cache13__load_store_cache_access_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache13 :: LOAD STORE CACHE ACCESS XECORE2 */
#define acmgt2__l1_cache13__load_store_cache_access_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache13 :: LOAD STORE CACHE ACCESS XECORE3 */
#define acmgt2__l1_cache13__load_store_cache_access_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache14 :: GPU Time Elapsed */
#define acmgt2__l1_cache14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache14 :: GPU Core Clocks */
#define acmgt2__l1_cache14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache14 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache14 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache14 :: LOAD STORE CACHE ACCESS XECORE4 */
#define acmgt2__l1_cache14__load_store_cache_access_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache14 :: LOAD STORE CACHE ACCESS XECORE5 */
#define acmgt2__l1_cache14__load_store_cache_access_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache14 :: LOAD STORE CACHE ACCESS XECORE6 */
#define acmgt2__l1_cache14__load_store_cache_access_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache14 :: LOAD STORE CACHE ACCESS XECORE7 */
#define acmgt2__l1_cache14__load_store_cache_access_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache15 :: GPU Time Elapsed */
#define acmgt2__l1_cache15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache15 :: GPU Core Clocks */
#define acmgt2__l1_cache15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache15 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache15 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache15 :: LOAD STORE CACHE ACCESS XECORE8 */
#define acmgt2__l1_cache15__load_store_cache_access_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache15 :: LOAD STORE CACHE ACCESS XECORE9 */
#define acmgt2__l1_cache15__load_store_cache_access_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache15 :: LOAD STORE CACHE ACCESS XECORE10 */
#define acmgt2__l1_cache15__load_store_cache_access_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache15 :: LOAD STORE CACHE ACCESS XECORE11 */
#define acmgt2__l1_cache15__load_store_cache_access_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache16 :: GPU Time Elapsed */
#define acmgt2__l1_cache16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache16 :: GPU Core Clocks */
#define acmgt2__l1_cache16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache16 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache16 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache16 :: LOAD STORE CACHE ACCESS XECORE12 */
#define acmgt2__l1_cache16__load_store_cache_access_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache16 :: LOAD STORE CACHE ACCESS XECORE13 */
#define acmgt2__l1_cache16__load_store_cache_access_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache16 :: LOAD STORE CACHE ACCESS XECORE14 */
#define acmgt2__l1_cache16__load_store_cache_access_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache16 :: LOAD STORE CACHE ACCESS XECORE15 */
#define acmgt2__l1_cache16__load_store_cache_access_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache17 :: GPU Time Elapsed */
#define acmgt2__l1_cache17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache17 :: GPU Core Clocks */
#define acmgt2__l1_cache17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache17 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache17 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache17 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0 */
#define acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache17 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1 */
#define acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache17 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2 */
#define acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache17 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3 */
#define acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache18 :: GPU Time Elapsed */
#define acmgt2__l1_cache18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache18 :: GPU Core Clocks */
#define acmgt2__l1_cache18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache18 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache18 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache18 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4 */
#define acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache18 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5 */
#define acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache18 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6 */
#define acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache18 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7 */
#define acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache19 :: GPU Time Elapsed */
#define acmgt2__l1_cache19__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache19 :: GPU Core Clocks */
#define acmgt2__l1_cache19__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache19 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache19__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache19 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache19__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache19 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE8 */
#define acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache19 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE9 */
#define acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache19 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE10 */
#define acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache19 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE11 */
#define acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache20 :: GPU Time Elapsed */
#define acmgt2__l1_cache20__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache20 :: GPU Core Clocks */
#define acmgt2__l1_cache20__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache20 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache20__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache20 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache20__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache20 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE12 */
#define acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache20 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE13 */
#define acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache20 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE14 */
#define acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache20 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE15 */
#define acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache21 :: GPU Time Elapsed */
#define acmgt2__l1_cache21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache21 :: GPU Core Clocks */
#define acmgt2__l1_cache21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache21 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache21 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache21 :: LOAD STORE CACHE HIT XECORE0 */
#define acmgt2__l1_cache21__load_store_cache_hit_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache21 :: LOAD STORE CACHE HIT XECORE1 */
#define acmgt2__l1_cache21__load_store_cache_hit_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache22 :: GPU Time Elapsed */
#define acmgt2__l1_cache22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache22 :: GPU Core Clocks */
#define acmgt2__l1_cache22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache22 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache22 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache22 :: LOAD STORE CACHE HIT XECORE2 */
#define acmgt2__l1_cache22__load_store_cache_hit_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache22 :: LOAD STORE CACHE HIT XECORE3 */
#define acmgt2__l1_cache22__load_store_cache_hit_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache23 :: GPU Time Elapsed */
#define acmgt2__l1_cache23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache23 :: GPU Core Clocks */
#define acmgt2__l1_cache23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache23 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache23 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache23 :: LOAD STORE CACHE HIT XECORE4 */
#define acmgt2__l1_cache23__load_store_cache_hit_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache23 :: LOAD STORE CACHE HIT XECORE5 */
#define acmgt2__l1_cache23__load_store_cache_hit_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache24 :: GPU Time Elapsed */
#define acmgt2__l1_cache24__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache24 :: GPU Core Clocks */
#define acmgt2__l1_cache24__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache24 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache24__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache24 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache24__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache24 :: LOAD STORE CACHE HIT XECORE6 */
#define acmgt2__l1_cache24__load_store_cache_hit_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache24 :: LOAD STORE CACHE HIT XECORE7 */
#define acmgt2__l1_cache24__load_store_cache_hit_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache25 :: GPU Time Elapsed */
#define acmgt2__l1_cache25__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache25 :: GPU Core Clocks */
#define acmgt2__l1_cache25__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache25 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache25__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache25 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache25__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache25 :: LOAD STORE CACHE HIT XECORE8 */
#define acmgt2__l1_cache25__load_store_cache_hit_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache25 :: LOAD STORE CACHE HIT XECORE9 */
#define acmgt2__l1_cache25__load_store_cache_hit_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache26 :: GPU Time Elapsed */
#define acmgt2__l1_cache26__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache26 :: GPU Core Clocks */
#define acmgt2__l1_cache26__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache26 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache26__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache26 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache26__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache26 :: LOAD STORE CACHE HIT XECORE10 */
#define acmgt2__l1_cache26__load_store_cache_hit_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache26 :: LOAD STORE CACHE HIT XECORE11 */
#define acmgt2__l1_cache26__load_store_cache_hit_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache27 :: GPU Time Elapsed */
#define acmgt2__l1_cache27__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache27 :: GPU Core Clocks */
#define acmgt2__l1_cache27__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache27 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache27__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache27 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache27__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache27 :: LOAD STORE CACHE HIT XECORE12 */
#define acmgt2__l1_cache27__load_store_cache_hit_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache27 :: LOAD STORE CACHE HIT XECORE13 */
#define acmgt2__l1_cache27__load_store_cache_hit_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache28 :: GPU Time Elapsed */
#define acmgt2__l1_cache28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache28 :: GPU Core Clocks */
#define acmgt2__l1_cache28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache28 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache28 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache28 :: LOAD STORE CACHE HIT XECORE14 */
#define acmgt2__l1_cache28__load_store_cache_hit_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache28 :: LOAD STORE CACHE HIT XECORE15 */
#define acmgt2__l1_cache28__load_store_cache_hit_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache29 :: GPU Time Elapsed */
#define acmgt2__l1_cache29__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache29 :: GPU Core Clocks */
#define acmgt2__l1_cache29__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache29 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache29__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache29 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache29__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache29 :: SLM BANK CONFLICT COUNT XECORE0 */
#define acmgt2__l1_cache29__slm_bank_conflict_count_xecore0__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache30 :: GPU Time Elapsed */
#define acmgt2__l1_cache30__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache30 :: GPU Core Clocks */
#define acmgt2__l1_cache30__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache30 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache30__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache30 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache30__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache30 :: SLM BANK CONFLICT COUNT XECORE1 */
#define acmgt2__l1_cache30__slm_bank_conflict_count_xecore1__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache31 :: GPU Time Elapsed */
#define acmgt2__l1_cache31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache31 :: GPU Core Clocks */
#define acmgt2__l1_cache31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache31 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache31 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache31 :: SLM BANK CONFLICT COUNT XECORE2 */
#define acmgt2__l1_cache31__slm_bank_conflict_count_xecore2__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache32 :: GPU Time Elapsed */
#define acmgt2__l1_cache32__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache32 :: GPU Core Clocks */
#define acmgt2__l1_cache32__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache32 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache32__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache32 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache32__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache32 :: SLM BANK CONFLICT COUNT XECORE3 */
#define acmgt2__l1_cache32__slm_bank_conflict_count_xecore3__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache33 :: GPU Time Elapsed */
#define acmgt2__l1_cache33__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache33 :: GPU Core Clocks */
#define acmgt2__l1_cache33__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache33 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache33__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache33 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache33__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache33 :: SLM BANK CONFLICT COUNT XECORE4 */
#define acmgt2__l1_cache33__slm_bank_conflict_count_xecore4__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache34 :: GPU Time Elapsed */
#define acmgt2__l1_cache34__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache34 :: GPU Core Clocks */
#define acmgt2__l1_cache34__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache34 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache34__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache34 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache34__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache34 :: SLM BANK CONFLICT COUNT XECORE5 */
#define acmgt2__l1_cache34__slm_bank_conflict_count_xecore5__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache35 :: GPU Time Elapsed */
#define acmgt2__l1_cache35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache35 :: GPU Core Clocks */
#define acmgt2__l1_cache35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache35 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache35 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache35 :: SLM BANK CONFLICT COUNT XECORE6 */
#define acmgt2__l1_cache35__slm_bank_conflict_count_xecore6__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache36 :: GPU Time Elapsed */
#define acmgt2__l1_cache36__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache36 :: GPU Core Clocks */
#define acmgt2__l1_cache36__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache36 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache36__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache36 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache36__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache36 :: SLM BANK CONFLICT COUNT XECORE7 */
#define acmgt2__l1_cache36__slm_bank_conflict_count_xecore7__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache37 :: GPU Time Elapsed */
#define acmgt2__l1_cache37__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache37 :: GPU Core Clocks */
#define acmgt2__l1_cache37__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache37 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache37__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache37 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache37__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache37 :: SLM BANK CONFLICT COUNT XECORE8 */
#define acmgt2__l1_cache37__slm_bank_conflict_count_xecore8__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache38 :: GPU Time Elapsed */
#define acmgt2__l1_cache38__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache38 :: GPU Core Clocks */
#define acmgt2__l1_cache38__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache38 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache38__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache38 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache38__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache38 :: SLM BANK CONFLICT COUNT XECORE9 */
#define acmgt2__l1_cache38__slm_bank_conflict_count_xecore9__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache39 :: GPU Time Elapsed */
#define acmgt2__l1_cache39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache39 :: GPU Core Clocks */
#define acmgt2__l1_cache39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache39 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache39 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache39 :: SLM BANK CONFLICT COUNT XECORE10 */
#define acmgt2__l1_cache39__slm_bank_conflict_count_xecore10__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache40 :: GPU Time Elapsed */
#define acmgt2__l1_cache40__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache40 :: GPU Core Clocks */
#define acmgt2__l1_cache40__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache40 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache40__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache40 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache40__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache40 :: SLM BANK CONFLICT COUNT XECORE11 */
#define acmgt2__l1_cache40__slm_bank_conflict_count_xecore11__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache41 :: GPU Time Elapsed */
#define acmgt2__l1_cache41__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache41 :: GPU Core Clocks */
#define acmgt2__l1_cache41__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache41 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache41__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache41 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache41__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache41 :: SLM BANK CONFLICT COUNT XECORE12 */
#define acmgt2__l1_cache41__slm_bank_conflict_count_xecore12__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache42 :: GPU Time Elapsed */
#define acmgt2__l1_cache42__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache42 :: GPU Core Clocks */
#define acmgt2__l1_cache42__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache42 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache42__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache42 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache42__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache42 :: SLM BANK CONFLICT COUNT XECORE13 */
#define acmgt2__l1_cache42__slm_bank_conflict_count_xecore13__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache43 :: GPU Time Elapsed */
#define acmgt2__l1_cache43__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache43 :: GPU Core Clocks */
#define acmgt2__l1_cache43__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache43 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache43__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache43 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache43__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache43 :: SLM BANK CONFLICT COUNT XECORE14 */
#define acmgt2__l1_cache43__slm_bank_conflict_count_xecore14__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache44 :: GPU Time Elapsed */
#define acmgt2__l1_cache44__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache44 :: GPU Core Clocks */
#define acmgt2__l1_cache44__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache44 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache44__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache44 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache44__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache44 :: SLM BANK CONFLICT COUNT XECORE15 */
#define acmgt2__l1_cache44__slm_bank_conflict_count_xecore15__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* L1Cache45 :: GPU Time Elapsed */
#define acmgt2__l1_cache45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache45 :: GPU Core Clocks */
#define acmgt2__l1_cache45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache45 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache45 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache45 :: SLM ACCESS COUNT XECORE0 */
#define acmgt2__l1_cache45__slm_access_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache45 :: SLM ACCESS COUNT XECORE1 */
#define acmgt2__l1_cache45__slm_access_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache45 :: SLM ACCESS COUNT XECORE2 */
#define acmgt2__l1_cache45__slm_access_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache45 :: SLM ACCESS COUNT XECORE3 */
#define acmgt2__l1_cache45__slm_access_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache46 :: GPU Time Elapsed */
#define acmgt2__l1_cache46__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache46 :: GPU Core Clocks */
#define acmgt2__l1_cache46__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache46 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache46__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache46 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache46__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache46 :: SLM ACCESS COUNT XECORE4 */
#define acmgt2__l1_cache46__slm_access_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache46 :: SLM ACCESS COUNT XECORE5 */
#define acmgt2__l1_cache46__slm_access_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache46 :: SLM ACCESS COUNT XECORE6 */
#define acmgt2__l1_cache46__slm_access_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache46 :: SLM ACCESS COUNT XECORE7 */
#define acmgt2__l1_cache46__slm_access_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache47 :: GPU Time Elapsed */
#define acmgt2__l1_cache47__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache47 :: GPU Core Clocks */
#define acmgt2__l1_cache47__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache47 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache47__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache47 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache47__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache47 :: SLM ACCESS COUNT XECORE8 */
#define acmgt2__l1_cache47__slm_access_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache47 :: SLM ACCESS COUNT XECORE9 */
#define acmgt2__l1_cache47__slm_access_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache47 :: SLM ACCESS COUNT XECORE10 */
#define acmgt2__l1_cache47__slm_access_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache47 :: SLM ACCESS COUNT XECORE11 */
#define acmgt2__l1_cache47__slm_access_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache48 :: GPU Time Elapsed */
#define acmgt2__l1_cache48__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache48 :: GPU Core Clocks */
#define acmgt2__l1_cache48__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache48 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache48__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache48 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache48__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache48 :: SLM ACCESS COUNT XECORE12 */
#define acmgt2__l1_cache48__slm_access_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache48 :: SLM ACCESS COUNT XECORE13 */
#define acmgt2__l1_cache48__slm_access_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache48 :: SLM ACCESS COUNT XECORE14 */
#define acmgt2__l1_cache48__slm_access_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache48 :: SLM ACCESS COUNT XECORE15 */
#define acmgt2__l1_cache48__slm_access_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache49 :: GPU Time Elapsed */
#define acmgt2__l1_cache49__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache49 :: GPU Core Clocks */
#define acmgt2__l1_cache49__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache49 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache49__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache49 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache49__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache49 :: XVE SLM READ MESSAGE COUNT XECORE0 */
#define acmgt2__l1_cache49__xve_slm_read_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache49 :: XVE SLM READ MESSAGE COUNT XECORE1 */
#define acmgt2__l1_cache49__xve_slm_read_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache50 :: GPU Time Elapsed */
#define acmgt2__l1_cache50__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache50 :: GPU Core Clocks */
#define acmgt2__l1_cache50__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache50 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache50__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache50 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache50__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache50 :: XVE SLM READ MESSAGE COUNT XECORE2 */
#define acmgt2__l1_cache50__xve_slm_read_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache50 :: XVE SLM READ MESSAGE COUNT XECORE3 */
#define acmgt2__l1_cache50__xve_slm_read_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache51 :: GPU Time Elapsed */
#define acmgt2__l1_cache51__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache51 :: GPU Core Clocks */
#define acmgt2__l1_cache51__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache51 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache51__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache51 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache51__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache51 :: XVE SLM READ MESSAGE COUNT XECORE4 */
#define acmgt2__l1_cache51__xve_slm_read_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache51 :: XVE SLM READ MESSAGE COUNT XECORE5 */
#define acmgt2__l1_cache51__xve_slm_read_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache52 :: GPU Time Elapsed */
#define acmgt2__l1_cache52__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache52 :: GPU Core Clocks */
#define acmgt2__l1_cache52__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache52 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache52__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache52 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache52__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache52 :: XVE SLM READ MESSAGE COUNT XECORE6 */
#define acmgt2__l1_cache52__xve_slm_read_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache52 :: XVE SLM READ MESSAGE COUNT XECORE7 */
#define acmgt2__l1_cache52__xve_slm_read_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache53 :: GPU Time Elapsed */
#define acmgt2__l1_cache53__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache53 :: GPU Core Clocks */
#define acmgt2__l1_cache53__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache53 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache53__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache53 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache53__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache53 :: XVE SLM READ MESSAGE COUNT XECORE8 */
#define acmgt2__l1_cache53__xve_slm_read_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache53 :: XVE SLM READ MESSAGE COUNT XECORE9 */
#define acmgt2__l1_cache53__xve_slm_read_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache54 :: GPU Time Elapsed */
#define acmgt2__l1_cache54__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache54 :: GPU Core Clocks */
#define acmgt2__l1_cache54__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache54 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache54__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache54 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache54__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache54 :: XVE SLM READ MESSAGE COUNT XECORE10 */
#define acmgt2__l1_cache54__xve_slm_read_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache54 :: XVE SLM READ MESSAGE COUNT XECORE11 */
#define acmgt2__l1_cache54__xve_slm_read_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache55 :: GPU Time Elapsed */
#define acmgt2__l1_cache55__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache55 :: GPU Core Clocks */
#define acmgt2__l1_cache55__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache55 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache55__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache55 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache55__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache55 :: XVE SLM READ MESSAGE COUNT XECORE12 */
#define acmgt2__l1_cache55__xve_slm_read_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache55 :: XVE SLM READ MESSAGE COUNT XECORE13 */
#define acmgt2__l1_cache55__xve_slm_read_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache56 :: GPU Time Elapsed */
#define acmgt2__l1_cache56__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache56 :: GPU Core Clocks */
#define acmgt2__l1_cache56__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache56 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache56__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache56 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache56__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache56 :: XVE SLM READ MESSAGE COUNT XECORE14 */
#define acmgt2__l1_cache56__xve_slm_read_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache56 :: XVE SLM READ MESSAGE COUNT XECORE15 */
#define acmgt2__l1_cache56__xve_slm_read_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache57 :: GPU Time Elapsed */
#define acmgt2__l1_cache57__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache57 :: GPU Core Clocks */
#define acmgt2__l1_cache57__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache57 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache57__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache57 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache57__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache57 :: XVE SLM WRITE MESSAGE COUNT XECORE0 */
#define acmgt2__l1_cache57__xve_slm_write_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache57 :: XVE SLM WRITE MESSAGE COUNT XECORE1 */
#define acmgt2__l1_cache57__xve_slm_write_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache58 :: GPU Time Elapsed */
#define acmgt2__l1_cache58__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache58 :: GPU Core Clocks */
#define acmgt2__l1_cache58__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache58 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache58__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache58 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache58__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache58 :: XVE SLM WRITE MESSAGE COUNT XECORE2 */
#define acmgt2__l1_cache58__xve_slm_write_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache58 :: XVE SLM WRITE MESSAGE COUNT XECORE3 */
#define acmgt2__l1_cache58__xve_slm_write_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache59 :: GPU Time Elapsed */
#define acmgt2__l1_cache59__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache59 :: GPU Core Clocks */
#define acmgt2__l1_cache59__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache59 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache59__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache59 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache59__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache59 :: XVE SLM WRITE MESSAGE COUNT XECORE4 */
#define acmgt2__l1_cache59__xve_slm_write_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache59 :: XVE SLM WRITE MESSAGE COUNT XECORE5 */
#define acmgt2__l1_cache59__xve_slm_write_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache60 :: GPU Time Elapsed */
#define acmgt2__l1_cache60__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache60 :: GPU Core Clocks */
#define acmgt2__l1_cache60__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache60 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache60__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache60 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache60__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache60 :: XVE SLM WRITE MESSAGE COUNT XECORE6 */
#define acmgt2__l1_cache60__xve_slm_write_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache60 :: XVE SLM WRITE MESSAGE COUNT XECORE7 */
#define acmgt2__l1_cache60__xve_slm_write_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache61 :: GPU Time Elapsed */
#define acmgt2__l1_cache61__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache61 :: GPU Core Clocks */
#define acmgt2__l1_cache61__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache61 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache61__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache61 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache61__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache61 :: XVE SLM WRITE MESSAGE COUNT XECORE8 */
#define acmgt2__l1_cache61__xve_slm_write_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache61 :: XVE SLM WRITE MESSAGE COUNT XECORE9 */
#define acmgt2__l1_cache61__xve_slm_write_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache62 :: GPU Time Elapsed */
#define acmgt2__l1_cache62__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache62 :: GPU Core Clocks */
#define acmgt2__l1_cache62__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache62 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache62__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache62 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache62__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache62 :: XVE SLM WRITE MESSAGE COUNT XECORE10 */
#define acmgt2__l1_cache62__xve_slm_write_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache62 :: XVE SLM WRITE MESSAGE COUNT XECORE11 */
#define acmgt2__l1_cache62__xve_slm_write_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache63 :: GPU Time Elapsed */
#define acmgt2__l1_cache63__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache63 :: GPU Core Clocks */
#define acmgt2__l1_cache63__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache63 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache63__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache63 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache63__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache63 :: XVE SLM WRITE MESSAGE COUNT XECORE12 */
#define acmgt2__l1_cache63__xve_slm_write_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache63 :: XVE SLM WRITE MESSAGE COUNT XECORE13 */
#define acmgt2__l1_cache63__xve_slm_write_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache64 :: GPU Time Elapsed */
#define acmgt2__l1_cache64__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache64 :: GPU Core Clocks */
#define acmgt2__l1_cache64__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache64 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache64__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache64 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache64__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache64 :: XVE SLM WRITE MESSAGE COUNT XECORE14 */
#define acmgt2__l1_cache64__xve_slm_write_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache64 :: XVE SLM WRITE MESSAGE COUNT XECORE15 */
#define acmgt2__l1_cache64__xve_slm_write_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache65 :: GPU Time Elapsed */
#define acmgt2__l1_cache65__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache65 :: GPU Core Clocks */
#define acmgt2__l1_cache65__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache65 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache65__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache65 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache65__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache65 :: XVE SLM ATOMIC MESSAGE COUNT XECORE0 */
#define acmgt2__l1_cache65__xve_slm_atomic_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache65 :: XVE SLM FENCE MESSAGE COUNT XECORE0 */
#define acmgt2__l1_cache65__xve_slm_fence_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache66 :: GPU Time Elapsed */
#define acmgt2__l1_cache66__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache66 :: GPU Core Clocks */
#define acmgt2__l1_cache66__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache66 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache66__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache66 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache66__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache66 :: XVE SLM ATOMIC MESSAGE COUNT XECORE1 */
#define acmgt2__l1_cache66__xve_slm_atomic_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache66 :: XVE SLM FENCE MESSAGE COUNT XECORE1 */
#define acmgt2__l1_cache66__xve_slm_fence_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache67 :: GPU Time Elapsed */
#define acmgt2__l1_cache67__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache67 :: GPU Core Clocks */
#define acmgt2__l1_cache67__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache67 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache67__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache67 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache67__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache67 :: XVE SLM ATOMIC MESSAGE COUNT XECORE2 */
#define acmgt2__l1_cache67__xve_slm_atomic_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache67 :: XVE SLM FENCE MESSAGE COUNT XECORE2 */
#define acmgt2__l1_cache67__xve_slm_fence_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache68 :: GPU Time Elapsed */
#define acmgt2__l1_cache68__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache68 :: GPU Core Clocks */
#define acmgt2__l1_cache68__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache68 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache68__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache68 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache68__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache68 :: XVE SLM ATOMIC MESSAGE COUNT XECORE3 */
#define acmgt2__l1_cache68__xve_slm_atomic_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache68 :: XVE SLM FENCE MESSAGE COUNT XECORE3 */
#define acmgt2__l1_cache68__xve_slm_fence_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache69 :: GPU Time Elapsed */
#define acmgt2__l1_cache69__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache69 :: GPU Core Clocks */
#define acmgt2__l1_cache69__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache69 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache69__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache69 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache69__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache69 :: XVE SLM ATOMIC MESSAGE COUNT XECORE4 */
#define acmgt2__l1_cache69__xve_slm_atomic_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache69 :: XVE SLM FENCE MESSAGE COUNT XECORE4 */
#define acmgt2__l1_cache69__xve_slm_fence_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache70 :: GPU Time Elapsed */
#define acmgt2__l1_cache70__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache70 :: GPU Core Clocks */
#define acmgt2__l1_cache70__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache70 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache70__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache70 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache70__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache70 :: XVE SLM ATOMIC MESSAGE COUNT XECORE5 */
#define acmgt2__l1_cache70__xve_slm_atomic_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache70 :: XVE SLM FENCE MESSAGE COUNT XECORE5 */
#define acmgt2__l1_cache70__xve_slm_fence_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache71 :: GPU Time Elapsed */
#define acmgt2__l1_cache71__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache71 :: GPU Core Clocks */
#define acmgt2__l1_cache71__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache71 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache71__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache71 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache71__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache71 :: XVE SLM ATOMIC MESSAGE COUNT XECORE6 */
#define acmgt2__l1_cache71__xve_slm_atomic_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache71 :: XVE SLM FENCE MESSAGE COUNT XECORE6 */
#define acmgt2__l1_cache71__xve_slm_fence_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache72 :: GPU Time Elapsed */
#define acmgt2__l1_cache72__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache72 :: GPU Core Clocks */
#define acmgt2__l1_cache72__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache72 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache72__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache72 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache72__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache72 :: XVE SLM ATOMIC MESSAGE COUNT XECORE7 */
#define acmgt2__l1_cache72__xve_slm_atomic_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache72 :: XVE SLM FENCE MESSAGE COUNT XECORE7 */
#define acmgt2__l1_cache72__xve_slm_fence_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache73 :: GPU Time Elapsed */
#define acmgt2__l1_cache73__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache73 :: GPU Core Clocks */
#define acmgt2__l1_cache73__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache73 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache73__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache73 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache73__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache73 :: XVE SLM ATOMIC MESSAGE COUNT XECORE8 */
#define acmgt2__l1_cache73__xve_slm_atomic_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache73 :: XVE SLM FENCE MESSAGE COUNT XECORE8 */
#define acmgt2__l1_cache73__xve_slm_fence_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache74 :: GPU Time Elapsed */
#define acmgt2__l1_cache74__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache74 :: GPU Core Clocks */
#define acmgt2__l1_cache74__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache74 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache74__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache74 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache74__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache74 :: XVE SLM ATOMIC MESSAGE COUNT XECORE9 */
#define acmgt2__l1_cache74__xve_slm_atomic_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache74 :: XVE SLM FENCE MESSAGE COUNT XECORE9 */
#define acmgt2__l1_cache74__xve_slm_fence_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache75 :: GPU Time Elapsed */
#define acmgt2__l1_cache75__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache75 :: GPU Core Clocks */
#define acmgt2__l1_cache75__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache75 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache75__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache75 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache75__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache75 :: XVE SLM ATOMIC MESSAGE COUNT XECORE10 */
#define acmgt2__l1_cache75__xve_slm_atomic_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache75 :: XVE SLM FENCE MESSAGE COUNT XECORE10 */
#define acmgt2__l1_cache75__xve_slm_fence_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache76 :: GPU Time Elapsed */
#define acmgt2__l1_cache76__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache76 :: GPU Core Clocks */
#define acmgt2__l1_cache76__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache76 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache76__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache76 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache76__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache76 :: XVE SLM ATOMIC MESSAGE COUNT XECORE11 */
#define acmgt2__l1_cache76__xve_slm_atomic_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache76 :: XVE SLM FENCE MESSAGE COUNT XECORE11 */
#define acmgt2__l1_cache76__xve_slm_fence_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache77 :: GPU Time Elapsed */
#define acmgt2__l1_cache77__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache77 :: GPU Core Clocks */
#define acmgt2__l1_cache77__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache77 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache77__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache77 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache77__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache77 :: XVE SLM ATOMIC MESSAGE COUNT XECORE12 */
#define acmgt2__l1_cache77__xve_slm_atomic_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache77 :: XVE SLM FENCE MESSAGE COUNT XECORE12 */
#define acmgt2__l1_cache77__xve_slm_fence_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache78 :: GPU Time Elapsed */
#define acmgt2__l1_cache78__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache78 :: GPU Core Clocks */
#define acmgt2__l1_cache78__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache78 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache78__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache78 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache78__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache78 :: XVE SLM ATOMIC MESSAGE COUNT XECORE13 */
#define acmgt2__l1_cache78__xve_slm_atomic_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache78 :: XVE SLM FENCE MESSAGE COUNT XECORE13 */
#define acmgt2__l1_cache78__xve_slm_fence_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache79 :: GPU Time Elapsed */
#define acmgt2__l1_cache79__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache79 :: GPU Core Clocks */
#define acmgt2__l1_cache79__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache79 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache79__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache79 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache79__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache79 :: XVE SLM ATOMIC MESSAGE COUNT XECORE14 */
#define acmgt2__l1_cache79__xve_slm_atomic_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache79 :: XVE SLM FENCE MESSAGE COUNT XECORE14 */
#define acmgt2__l1_cache79__xve_slm_fence_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache80 :: GPU Time Elapsed */
#define acmgt2__l1_cache80__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache80 :: GPU Core Clocks */
#define acmgt2__l1_cache80__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache80 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache80__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache80 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache80__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache80 :: XVE SLM ATOMIC MESSAGE COUNT XECORE15 */
#define acmgt2__l1_cache80__xve_slm_atomic_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache80 :: XVE SLM FENCE MESSAGE COUNT XECORE15 */
#define acmgt2__l1_cache80__xve_slm_fence_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache81 :: GPU Time Elapsed */
#define acmgt2__l1_cache81__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache81 :: GPU Core Clocks */
#define acmgt2__l1_cache81__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache81 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache81__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache81 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache81__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache81 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0 */
#define acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache81 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1 */
#define acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache81 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2 */
#define acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache81 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3 */
#define acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache82 :: GPU Time Elapsed */
#define acmgt2__l1_cache82__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache82 :: GPU Core Clocks */
#define acmgt2__l1_cache82__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache82 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache82__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache82 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache82__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache82 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4 */
#define acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache82 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5 */
#define acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache82 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6 */
#define acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache82 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7 */
#define acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache83 :: GPU Time Elapsed */
#define acmgt2__l1_cache83__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache83 :: GPU Core Clocks */
#define acmgt2__l1_cache83__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache83 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache83__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache83 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache83__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache83 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE8 */
#define acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache83 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE9 */
#define acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache83 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE10 */
#define acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache83 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE11 */
#define acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache84 :: GPU Time Elapsed */
#define acmgt2__l1_cache84__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache84 :: GPU Core Clocks */
#define acmgt2__l1_cache84__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache84 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache84__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache84 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache84__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache84 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE12 */
#define acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache84 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE13 */
#define acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache84 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE14 */
#define acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache84 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE15 */
#define acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache85 :: GPU Time Elapsed */
#define acmgt2__l1_cache85__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache85 :: GPU Core Clocks */
#define acmgt2__l1_cache85__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache85 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache85__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache85 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache85__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache85 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0 */
#define acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache85 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1 */
#define acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache85 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2 */
#define acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache85 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3 */
#define acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache86 :: GPU Time Elapsed */
#define acmgt2__l1_cache86__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache86 :: GPU Core Clocks */
#define acmgt2__l1_cache86__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache86 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache86__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache86 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache86__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache86 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4 */
#define acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache86 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5 */
#define acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache86 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6 */
#define acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache86 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7 */
#define acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache87 :: GPU Time Elapsed */
#define acmgt2__l1_cache87__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache87 :: GPU Core Clocks */
#define acmgt2__l1_cache87__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache87 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache87__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache87 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache87__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache87 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE8 */
#define acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache87 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE9 */
#define acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache87 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE10 */
#define acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache87 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE11 */
#define acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache88 :: GPU Time Elapsed */
#define acmgt2__l1_cache88__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache88 :: GPU Core Clocks */
#define acmgt2__l1_cache88__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache88 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache88__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache88 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache88__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache88 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE12 */
#define acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache88 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE13 */
#define acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache88 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE14 */
#define acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache88 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE15 */
#define acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache89 :: GPU Time Elapsed */
#define acmgt2__l1_cache89__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache89 :: GPU Core Clocks */
#define acmgt2__l1_cache89__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache89 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache89__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache89 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache89__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache89 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define acmgt2__l1_cache89__xve_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache89 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define acmgt2__l1_cache89__xve_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache90 :: GPU Time Elapsed */
#define acmgt2__l1_cache90__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache90 :: GPU Core Clocks */
#define acmgt2__l1_cache90__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache90 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache90__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache90 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache90__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache90 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define acmgt2__l1_cache90__xve_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache90 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define acmgt2__l1_cache90__xve_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache91 :: GPU Time Elapsed */
#define acmgt2__l1_cache91__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache91 :: GPU Core Clocks */
#define acmgt2__l1_cache91__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache91 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache91__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache91 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache91__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache91 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4 */
#define acmgt2__l1_cache91__xve_load_store_cache_read_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache91 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5 */
#define acmgt2__l1_cache91__xve_load_store_cache_read_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache92 :: GPU Time Elapsed */
#define acmgt2__l1_cache92__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache92 :: GPU Core Clocks */
#define acmgt2__l1_cache92__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache92 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache92__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache92 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache92__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache92 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6 */
#define acmgt2__l1_cache92__xve_load_store_cache_read_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache92 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7 */
#define acmgt2__l1_cache92__xve_load_store_cache_read_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache93 :: GPU Time Elapsed */
#define acmgt2__l1_cache93__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache93 :: GPU Core Clocks */
#define acmgt2__l1_cache93__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache93 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache93__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache93 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache93__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache93 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE8 */
#define acmgt2__l1_cache93__xve_load_store_cache_read_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache93 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE9 */
#define acmgt2__l1_cache93__xve_load_store_cache_read_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache94 :: GPU Time Elapsed */
#define acmgt2__l1_cache94__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache94 :: GPU Core Clocks */
#define acmgt2__l1_cache94__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache94 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache94__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache94 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache94__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache94 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE10 */
#define acmgt2__l1_cache94__xve_load_store_cache_read_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache94 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE11 */
#define acmgt2__l1_cache94__xve_load_store_cache_read_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache95 :: GPU Time Elapsed */
#define acmgt2__l1_cache95__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache95 :: GPU Core Clocks */
#define acmgt2__l1_cache95__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache95 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache95__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache95 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache95__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache95 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE12 */
#define acmgt2__l1_cache95__xve_load_store_cache_read_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache95 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE13 */
#define acmgt2__l1_cache95__xve_load_store_cache_read_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache96 :: GPU Time Elapsed */
#define acmgt2__l1_cache96__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache96 :: GPU Core Clocks */
#define acmgt2__l1_cache96__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache96 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache96__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache96 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache96__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache96 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE14 */
#define acmgt2__l1_cache96__xve_load_store_cache_read_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache96 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE15 */
#define acmgt2__l1_cache96__xve_load_store_cache_read_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache97 :: GPU Time Elapsed */
#define acmgt2__l1_cache97__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache97 :: GPU Core Clocks */
#define acmgt2__l1_cache97__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache97 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache97__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache97 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache97__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache97 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0 */
#define acmgt2__l1_cache97__xve_load_store_cache_write_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache97 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1 */
#define acmgt2__l1_cache97__xve_load_store_cache_write_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache98 :: GPU Time Elapsed */
#define acmgt2__l1_cache98__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache98 :: GPU Core Clocks */
#define acmgt2__l1_cache98__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache98 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache98__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache98 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache98__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache98 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2 */
#define acmgt2__l1_cache98__xve_load_store_cache_write_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache98 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3 */
#define acmgt2__l1_cache98__xve_load_store_cache_write_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache99 :: GPU Time Elapsed */
#define acmgt2__l1_cache99__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache99 :: GPU Core Clocks */
#define acmgt2__l1_cache99__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache99 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache99__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache99 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache99__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache99 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4 */
#define acmgt2__l1_cache99__xve_load_store_cache_write_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache99 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5 */
#define acmgt2__l1_cache99__xve_load_store_cache_write_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache100 :: GPU Time Elapsed */
#define acmgt2__l1_cache100__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache100 :: GPU Core Clocks */
#define acmgt2__l1_cache100__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache100 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache100__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache100 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache100__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache100 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6 */
#define acmgt2__l1_cache100__xve_load_store_cache_write_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache100 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7 */
#define acmgt2__l1_cache100__xve_load_store_cache_write_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache101 :: GPU Time Elapsed */
#define acmgt2__l1_cache101__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache101 :: GPU Core Clocks */
#define acmgt2__l1_cache101__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache101 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache101__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache101 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache101__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache101 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE8 */
#define acmgt2__l1_cache101__xve_load_store_cache_write_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache101 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE9 */
#define acmgt2__l1_cache101__xve_load_store_cache_write_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache102 :: GPU Time Elapsed */
#define acmgt2__l1_cache102__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache102 :: GPU Core Clocks */
#define acmgt2__l1_cache102__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache102 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache102__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache102 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache102__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache102 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE10 */
#define acmgt2__l1_cache102__xve_load_store_cache_write_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache102 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE11 */
#define acmgt2__l1_cache102__xve_load_store_cache_write_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache103 :: GPU Time Elapsed */
#define acmgt2__l1_cache103__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache103 :: GPU Core Clocks */
#define acmgt2__l1_cache103__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache103 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache103__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache103 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache103__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache103 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE12 */
#define acmgt2__l1_cache103__xve_load_store_cache_write_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache103 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE13 */
#define acmgt2__l1_cache103__xve_load_store_cache_write_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache104 :: GPU Time Elapsed */
#define acmgt2__l1_cache104__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache104 :: GPU Core Clocks */
#define acmgt2__l1_cache104__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache104 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache104__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache104 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache104__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache104 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE14 */
#define acmgt2__l1_cache104__xve_load_store_cache_write_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache104 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE15 */
#define acmgt2__l1_cache104__xve_load_store_cache_write_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache105 :: GPU Time Elapsed */
#define acmgt2__l1_cache105__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache105 :: GPU Core Clocks */
#define acmgt2__l1_cache105__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache105 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache105__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache105 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache105__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache105 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0 */
#define acmgt2__l1_cache105__xve_load_store_cache_atomic_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache105 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0 */
#define acmgt2__l1_cache105__xve_load_store_cache_fence_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache106 :: GPU Time Elapsed */
#define acmgt2__l1_cache106__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache106 :: GPU Core Clocks */
#define acmgt2__l1_cache106__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache106 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache106__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache106 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache106__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache106 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1 */
#define acmgt2__l1_cache106__xve_load_store_cache_atomic_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache106 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1 */
#define acmgt2__l1_cache106__xve_load_store_cache_fence_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache107 :: GPU Time Elapsed */
#define acmgt2__l1_cache107__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache107 :: GPU Core Clocks */
#define acmgt2__l1_cache107__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache107 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache107__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache107 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache107__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache107 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2 */
#define acmgt2__l1_cache107__xve_load_store_cache_atomic_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache107 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2 */
#define acmgt2__l1_cache107__xve_load_store_cache_fence_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache108 :: GPU Time Elapsed */
#define acmgt2__l1_cache108__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache108 :: GPU Core Clocks */
#define acmgt2__l1_cache108__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache108 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache108__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache108 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache108__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache108 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3 */
#define acmgt2__l1_cache108__xve_load_store_cache_atomic_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache108 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3 */
#define acmgt2__l1_cache108__xve_load_store_cache_fence_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache109 :: GPU Time Elapsed */
#define acmgt2__l1_cache109__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache109 :: GPU Core Clocks */
#define acmgt2__l1_cache109__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache109 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache109__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache109 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache109__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache109 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4 */
#define acmgt2__l1_cache109__xve_load_store_cache_atomic_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache109 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4 */
#define acmgt2__l1_cache109__xve_load_store_cache_fence_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache110 :: GPU Time Elapsed */
#define acmgt2__l1_cache110__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache110 :: GPU Core Clocks */
#define acmgt2__l1_cache110__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache110 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache110__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache110 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache110__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache110 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5 */
#define acmgt2__l1_cache110__xve_load_store_cache_atomic_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache110 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5 */
#define acmgt2__l1_cache110__xve_load_store_cache_fence_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache111 :: GPU Time Elapsed */
#define acmgt2__l1_cache111__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache111 :: GPU Core Clocks */
#define acmgt2__l1_cache111__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache111 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache111__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache111 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache111__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache111 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6 */
#define acmgt2__l1_cache111__xve_load_store_cache_atomic_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache111 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6 */
#define acmgt2__l1_cache111__xve_load_store_cache_fence_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache112 :: GPU Time Elapsed */
#define acmgt2__l1_cache112__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache112 :: GPU Core Clocks */
#define acmgt2__l1_cache112__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache112 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache112__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache112 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache112__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache112 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7 */
#define acmgt2__l1_cache112__xve_load_store_cache_atomic_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache112 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7 */
#define acmgt2__l1_cache112__xve_load_store_cache_fence_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache113 :: GPU Time Elapsed */
#define acmgt2__l1_cache113__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache113 :: GPU Core Clocks */
#define acmgt2__l1_cache113__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache113 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache113__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache113 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache113__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache113 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE8 */
#define acmgt2__l1_cache113__xve_load_store_cache_atomic_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache113 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE8 */
#define acmgt2__l1_cache113__xve_load_store_cache_fence_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache114 :: GPU Time Elapsed */
#define acmgt2__l1_cache114__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache114 :: GPU Core Clocks */
#define acmgt2__l1_cache114__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache114 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache114__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache114 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache114__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache114 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE9 */
#define acmgt2__l1_cache114__xve_load_store_cache_atomic_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache114 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE9 */
#define acmgt2__l1_cache114__xve_load_store_cache_fence_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache115 :: GPU Time Elapsed */
#define acmgt2__l1_cache115__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache115 :: GPU Core Clocks */
#define acmgt2__l1_cache115__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache115 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache115__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache115 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache115__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache115 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE10 */
#define acmgt2__l1_cache115__xve_load_store_cache_atomic_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache115 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE10 */
#define acmgt2__l1_cache115__xve_load_store_cache_fence_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache116 :: GPU Time Elapsed */
#define acmgt2__l1_cache116__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache116 :: GPU Core Clocks */
#define acmgt2__l1_cache116__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache116 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache116__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache116 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache116__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache116 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE11 */
#define acmgt2__l1_cache116__xve_load_store_cache_atomic_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache116 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE11 */
#define acmgt2__l1_cache116__xve_load_store_cache_fence_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache117 :: GPU Time Elapsed */
#define acmgt2__l1_cache117__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache117 :: GPU Core Clocks */
#define acmgt2__l1_cache117__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache117 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache117__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache117 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache117__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache117 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE12 */
#define acmgt2__l1_cache117__xve_load_store_cache_atomic_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache117 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE12 */
#define acmgt2__l1_cache117__xve_load_store_cache_fence_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache118 :: GPU Time Elapsed */
#define acmgt2__l1_cache118__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache118 :: GPU Core Clocks */
#define acmgt2__l1_cache118__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache118 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache118__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache118 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache118__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache118 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE13 */
#define acmgt2__l1_cache118__xve_load_store_cache_atomic_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache118 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE13 */
#define acmgt2__l1_cache118__xve_load_store_cache_fence_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache119 :: GPU Time Elapsed */
#define acmgt2__l1_cache119__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache119 :: GPU Core Clocks */
#define acmgt2__l1_cache119__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache119 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache119__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache119 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache119__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache119 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE14 */
#define acmgt2__l1_cache119__xve_load_store_cache_atomic_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache119 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE14 */
#define acmgt2__l1_cache119__xve_load_store_cache_fence_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache120 :: GPU Time Elapsed */
#define acmgt2__l1_cache120__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache120 :: GPU Core Clocks */
#define acmgt2__l1_cache120__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache120 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache120__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache120 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache120__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache120 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE15 */
#define acmgt2__l1_cache120__xve_load_store_cache_atomic_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* L1Cache120 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE15 */
#define acmgt2__l1_cache120__xve_load_store_cache_fence_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* L1Cache121 :: GPU Time Elapsed */
#define acmgt2__l1_cache121__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache121 :: GPU Core Clocks */
#define acmgt2__l1_cache121__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache121 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache121__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache121 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache121__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache121 :: LOAD STORE CACHE BYTE READ BANK0 XECORE0 */
#define acmgt2__l1_cache121__load_store_cache_byte_read_bank0_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache121 :: SLM BYTE READ BANK0 XECORE0 */
#define acmgt2__l1_cache121__slm_byte_read_bank0_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache122 :: GPU Time Elapsed */
#define acmgt2__l1_cache122__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache122 :: GPU Core Clocks */
#define acmgt2__l1_cache122__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache122 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache122__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache122 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache122__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache122 :: LOAD STORE CACHE BYTE READ BANK0 XECORE1 */
#define acmgt2__l1_cache122__load_store_cache_byte_read_bank0_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache122 :: SLM BYTE READ BANK0 XECORE1 */
#define acmgt2__l1_cache122__slm_byte_read_bank0_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache123 :: GPU Time Elapsed */
#define acmgt2__l1_cache123__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache123 :: GPU Core Clocks */
#define acmgt2__l1_cache123__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache123 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache123__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache123 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache123__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache123 :: LOAD STORE CACHE BYTE READ BANK0 XECORE2 */
#define acmgt2__l1_cache123__load_store_cache_byte_read_bank0_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache123 :: SLM BYTE READ BANK0 XECORE2 */
#define acmgt2__l1_cache123__slm_byte_read_bank0_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache124 :: GPU Time Elapsed */
#define acmgt2__l1_cache124__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache124 :: GPU Core Clocks */
#define acmgt2__l1_cache124__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache124 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache124__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache124 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache124__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache124 :: LOAD STORE CACHE BYTE READ BANK0 XECORE3 */
#define acmgt2__l1_cache124__load_store_cache_byte_read_bank0_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache124 :: SLM BYTE READ BANK0 XECORE3 */
#define acmgt2__l1_cache124__slm_byte_read_bank0_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache125 :: GPU Time Elapsed */
#define acmgt2__l1_cache125__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache125 :: GPU Core Clocks */
#define acmgt2__l1_cache125__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache125 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache125__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache125 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache125__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache125 :: LOAD STORE CACHE BYTE READ BANK1 XECORE0 */
#define acmgt2__l1_cache125__load_store_cache_byte_read_bank1_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache125 :: SLM BYTE READ BANK1 XECORE0 */
#define acmgt2__l1_cache125__slm_byte_read_bank1_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache126 :: GPU Time Elapsed */
#define acmgt2__l1_cache126__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache126 :: GPU Core Clocks */
#define acmgt2__l1_cache126__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache126 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache126__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache126 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache126__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache126 :: LOAD STORE CACHE BYTE READ BANK1 XECORE1 */
#define acmgt2__l1_cache126__load_store_cache_byte_read_bank1_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache126 :: SLM BYTE READ BANK1 XECORE1 */
#define acmgt2__l1_cache126__slm_byte_read_bank1_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache127 :: GPU Time Elapsed */
#define acmgt2__l1_cache127__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache127 :: GPU Core Clocks */
#define acmgt2__l1_cache127__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache127 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache127__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache127 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache127__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache127 :: LOAD STORE CACHE BYTE READ BANK1 XECORE2 */
#define acmgt2__l1_cache127__load_store_cache_byte_read_bank1_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache127 :: SLM BYTE READ BANK1 XECORE2 */
#define acmgt2__l1_cache127__slm_byte_read_bank1_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache128 :: GPU Time Elapsed */
#define acmgt2__l1_cache128__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache128 :: GPU Core Clocks */
#define acmgt2__l1_cache128__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache128 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache128__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache128 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache128__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache128 :: LOAD STORE CACHE BYTE READ BANK1 XECORE3 */
#define acmgt2__l1_cache128__load_store_cache_byte_read_bank1_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache128 :: SLM BYTE READ BANK1 XECORE3 */
#define acmgt2__l1_cache128__slm_byte_read_bank1_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache129 :: GPU Time Elapsed */
#define acmgt2__l1_cache129__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache129 :: GPU Core Clocks */
#define acmgt2__l1_cache129__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache129 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache129__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache129 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache129__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache129 :: LOAD STORE CACHE BYTE READ BANK2 XECORE0 */
#define acmgt2__l1_cache129__load_store_cache_byte_read_bank2_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache129 :: SLM BYTE READ BANK2 XECORE0 */
#define acmgt2__l1_cache129__slm_byte_read_bank2_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache130 :: GPU Time Elapsed */
#define acmgt2__l1_cache130__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache130 :: GPU Core Clocks */
#define acmgt2__l1_cache130__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache130 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache130__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache130 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache130__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache130 :: LOAD STORE CACHE BYTE READ BANK2 XECORE1 */
#define acmgt2__l1_cache130__load_store_cache_byte_read_bank2_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache130 :: SLM BYTE READ BANK2 XECORE1 */
#define acmgt2__l1_cache130__slm_byte_read_bank2_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache131 :: GPU Time Elapsed */
#define acmgt2__l1_cache131__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache131 :: GPU Core Clocks */
#define acmgt2__l1_cache131__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache131 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache131__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache131 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache131__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache131 :: LOAD STORE CACHE BYTE READ BANK2 XECORE2 */
#define acmgt2__l1_cache131__load_store_cache_byte_read_bank2_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache131 :: SLM BYTE READ BANK2 XECORE2 */
#define acmgt2__l1_cache131__slm_byte_read_bank2_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache132 :: GPU Time Elapsed */
#define acmgt2__l1_cache132__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache132 :: GPU Core Clocks */
#define acmgt2__l1_cache132__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache132 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache132__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache132 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache132__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache132 :: LOAD STORE CACHE BYTE READ BANK2 XECORE3 */
#define acmgt2__l1_cache132__load_store_cache_byte_read_bank2_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache132 :: SLM BYTE READ BANK2 XECORE3 */
#define acmgt2__l1_cache132__slm_byte_read_bank2_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache133 :: GPU Time Elapsed */
#define acmgt2__l1_cache133__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache133 :: GPU Core Clocks */
#define acmgt2__l1_cache133__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache133 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache133__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache133 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache133__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache133 :: LOAD STORE CACHE BYTE READ BANK3 XECORE0 */
#define acmgt2__l1_cache133__load_store_cache_byte_read_bank3_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache133 :: SLM BYTE READ BANK3 XECORE0 */
#define acmgt2__l1_cache133__slm_byte_read_bank3_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache134 :: GPU Time Elapsed */
#define acmgt2__l1_cache134__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache134 :: GPU Core Clocks */
#define acmgt2__l1_cache134__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache134 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache134__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache134 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache134__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache134 :: LOAD STORE CACHE BYTE READ BANK3 XECORE1 */
#define acmgt2__l1_cache134__load_store_cache_byte_read_bank3_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache134 :: SLM BYTE READ BANK3 XECORE1 */
#define acmgt2__l1_cache134__slm_byte_read_bank3_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache135 :: GPU Time Elapsed */
#define acmgt2__l1_cache135__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache135 :: GPU Core Clocks */
#define acmgt2__l1_cache135__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache135 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache135__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache135 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache135__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache135 :: LOAD STORE CACHE BYTE READ BANK3 XECORE2 */
#define acmgt2__l1_cache135__load_store_cache_byte_read_bank3_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache135 :: SLM BYTE READ BANK3 XECORE2 */
#define acmgt2__l1_cache135__slm_byte_read_bank3_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache136 :: GPU Time Elapsed */
#define acmgt2__l1_cache136__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache136 :: GPU Core Clocks */
#define acmgt2__l1_cache136__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache136 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache136__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache136 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache136__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache136 :: LOAD STORE CACHE BYTE READ BANK3 XECORE3 */
#define acmgt2__l1_cache136__load_store_cache_byte_read_bank3_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache136 :: SLM BYTE READ BANK3 XECORE3 */
#define acmgt2__l1_cache136__slm_byte_read_bank3_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache137 :: GPU Time Elapsed */
#define acmgt2__l1_cache137__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache137 :: GPU Core Clocks */
#define acmgt2__l1_cache137__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache137 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache137__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache137 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache137__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache137 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE0 */
#define acmgt2__l1_cache137__load_store_cache_byte_write_bank0_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache137 :: SLM BYTE WRITE BANK0 XECORE0 */
#define acmgt2__l1_cache137__slm_byte_write_bank0_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache138 :: GPU Time Elapsed */
#define acmgt2__l1_cache138__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache138 :: GPU Core Clocks */
#define acmgt2__l1_cache138__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache138 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache138__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache138 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache138__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache138 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE1 */
#define acmgt2__l1_cache138__load_store_cache_byte_write_bank0_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache138 :: SLM BYTE WRITE BANK0 XECORE1 */
#define acmgt2__l1_cache138__slm_byte_write_bank0_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache139 :: GPU Time Elapsed */
#define acmgt2__l1_cache139__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache139 :: GPU Core Clocks */
#define acmgt2__l1_cache139__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache139 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache139__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache139 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache139__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache139 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE2 */
#define acmgt2__l1_cache139__load_store_cache_byte_write_bank0_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache139 :: SLM BYTE WRITE BANK0 XECORE2 */
#define acmgt2__l1_cache139__slm_byte_write_bank0_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache140 :: GPU Time Elapsed */
#define acmgt2__l1_cache140__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache140 :: GPU Core Clocks */
#define acmgt2__l1_cache140__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache140 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache140__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache140 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache140__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache140 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE3 */
#define acmgt2__l1_cache140__load_store_cache_byte_write_bank0_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache140 :: SLM BYTE WRITE BANK0 XECORE3 */
#define acmgt2__l1_cache140__slm_byte_write_bank0_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache141 :: GPU Time Elapsed */
#define acmgt2__l1_cache141__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache141 :: GPU Core Clocks */
#define acmgt2__l1_cache141__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache141 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache141__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache141 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache141__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache141 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE0 */
#define acmgt2__l1_cache141__load_store_cache_byte_write_bank1_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache141 :: SLM BYTE WRITE BANK1 XECORE0 */
#define acmgt2__l1_cache141__slm_byte_write_bank1_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache142 :: GPU Time Elapsed */
#define acmgt2__l1_cache142__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache142 :: GPU Core Clocks */
#define acmgt2__l1_cache142__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache142 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache142__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache142 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache142__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache142 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE1 */
#define acmgt2__l1_cache142__load_store_cache_byte_write_bank1_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache142 :: SLM BYTE WRITE BANK1 XECORE1 */
#define acmgt2__l1_cache142__slm_byte_write_bank1_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache143 :: GPU Time Elapsed */
#define acmgt2__l1_cache143__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache143 :: GPU Core Clocks */
#define acmgt2__l1_cache143__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache143 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache143__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache143 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache143__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache143 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE2 */
#define acmgt2__l1_cache143__load_store_cache_byte_write_bank1_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache143 :: SLM BYTE WRITE BANK1 XECORE2 */
#define acmgt2__l1_cache143__slm_byte_write_bank1_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache144 :: GPU Time Elapsed */
#define acmgt2__l1_cache144__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache144 :: GPU Core Clocks */
#define acmgt2__l1_cache144__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache144 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache144__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache144 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache144__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache144 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE3 */
#define acmgt2__l1_cache144__load_store_cache_byte_write_bank1_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache144 :: SLM BYTE WRITE BANK1 XECORE3 */
#define acmgt2__l1_cache144__slm_byte_write_bank1_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache145 :: GPU Time Elapsed */
#define acmgt2__l1_cache145__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache145 :: GPU Core Clocks */
#define acmgt2__l1_cache145__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache145 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache145__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache145 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache145__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache145 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE0 */
#define acmgt2__l1_cache145__load_store_cache_byte_write_bank2_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache145 :: SLM BYTE WRITE BANK2 XECORE0 */
#define acmgt2__l1_cache145__slm_byte_write_bank2_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache146 :: GPU Time Elapsed */
#define acmgt2__l1_cache146__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache146 :: GPU Core Clocks */
#define acmgt2__l1_cache146__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache146 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache146__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache146 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache146__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache146 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE1 */
#define acmgt2__l1_cache146__load_store_cache_byte_write_bank2_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache146 :: SLM BYTE WRITE BANK2 XECORE1 */
#define acmgt2__l1_cache146__slm_byte_write_bank2_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache147 :: GPU Time Elapsed */
#define acmgt2__l1_cache147__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache147 :: GPU Core Clocks */
#define acmgt2__l1_cache147__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache147 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache147__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache147 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache147__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache147 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE2 */
#define acmgt2__l1_cache147__load_store_cache_byte_write_bank2_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache147 :: SLM BYTE WRITE BANK2 XECORE2 */
#define acmgt2__l1_cache147__slm_byte_write_bank2_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache148 :: GPU Time Elapsed */
#define acmgt2__l1_cache148__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache148 :: GPU Core Clocks */
#define acmgt2__l1_cache148__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache148 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache148__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache148 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache148__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache148 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE3 */
#define acmgt2__l1_cache148__load_store_cache_byte_write_bank2_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache148 :: SLM BYTE WRITE BANK2 XECORE3 */
#define acmgt2__l1_cache148__slm_byte_write_bank2_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache149 :: GPU Time Elapsed */
#define acmgt2__l1_cache149__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache149 :: GPU Core Clocks */
#define acmgt2__l1_cache149__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache149 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache149__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache149 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache149__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache149 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE0 */
#define acmgt2__l1_cache149__load_store_cache_byte_write_bank3_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache149 :: SLM BYTE WRITE BANK3 XECORE0 */
#define acmgt2__l1_cache149__slm_byte_write_bank3_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache150 :: GPU Time Elapsed */
#define acmgt2__l1_cache150__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache150 :: GPU Core Clocks */
#define acmgt2__l1_cache150__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache150 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache150__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache150 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache150__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache150 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE1 */
#define acmgt2__l1_cache150__load_store_cache_byte_write_bank3_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache150 :: SLM BYTE WRITE BANK3 XECORE1 */
#define acmgt2__l1_cache150__slm_byte_write_bank3_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache151 :: GPU Time Elapsed */
#define acmgt2__l1_cache151__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache151 :: GPU Core Clocks */
#define acmgt2__l1_cache151__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache151 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache151__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache151 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache151__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache151 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE2 */
#define acmgt2__l1_cache151__load_store_cache_byte_write_bank3_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache151 :: SLM BYTE WRITE BANK3 XECORE2 */
#define acmgt2__l1_cache151__slm_byte_write_bank3_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache152 :: GPU Time Elapsed */
#define acmgt2__l1_cache152__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache152 :: GPU Core Clocks */
#define acmgt2__l1_cache152__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache152 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache152__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache152 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache152__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache152 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE3 */
#define acmgt2__l1_cache152__load_store_cache_byte_write_bank3_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* L1Cache152 :: SLM BYTE WRITE BANK3 XECORE3 */
#define acmgt2__l1_cache152__slm_byte_write_bank3_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* L1Cache153 :: GPU Time Elapsed */
#define acmgt2__l1_cache153__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache153 :: GPU Core Clocks */
#define acmgt2__l1_cache153__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache153 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache153__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache153 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache153__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache153 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE0 */
#define acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache153 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE1 */
#define acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache153 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE2 */
#define acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache153 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE3 */
#define acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache154 :: GPU Time Elapsed */
#define acmgt2__l1_cache154__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache154 :: GPU Core Clocks */
#define acmgt2__l1_cache154__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache154 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache154__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache154 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache154__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache154 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE4 */
#define acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache154 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE5 */
#define acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache154 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE6 */
#define acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache154 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE7 */
#define acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache155 :: GPU Time Elapsed */
#define acmgt2__l1_cache155__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache155 :: GPU Core Clocks */
#define acmgt2__l1_cache155__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache155 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache155__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache155 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache155__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache155 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE8 */
#define acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache155 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE9 */
#define acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache155 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE10 */
#define acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache155 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE11 */
#define acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L1Cache156 :: GPU Time Elapsed */
#define acmgt2__l1_cache156__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1Cache156 :: GPU Core Clocks */
#define acmgt2__l1_cache156__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1Cache156 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache156__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1Cache156 :: AVG GPU Core Frequency */
#define acmgt2__l1_cache156__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1Cache156 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE12 */
#define acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* L1Cache156 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE13 */
#define acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* L1Cache156 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE14 */
#define acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* L1Cache156 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE15 */
#define acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* L3Cache1 :: GPU Time Elapsed */
#define acmgt2__l3_cache1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache1 :: GPU Core Clocks */
#define acmgt2__l3_cache1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache1 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache1 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache1 :: L3 BANK INPUT AVAILABLE L3BANK0 */
#define acmgt2__l3_cache1__l3_input_available_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3Cache1 :: L3 BANK INPUT AVAILABLE L3BANK1 */
#define acmgt2__l3_cache1__l3_input_available_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3Cache1 :: L3 BANK INPUT AVAILABLE L3BANK2 */
#define acmgt2__l3_cache1__l3_input_available_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3Cache1 :: L3 BANK INPUT AVAILABLE L3BANK3 */
#define acmgt2__l3_cache1__l3_input_available_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3Cache1 :: L3 BANK INPUT AVAILABLE L3BANK4 */
#define acmgt2__l3_cache1__l3_input_available_l3_bank4__read \
   bdw__render_pipe_profile__so_stall__read

/* L3Cache1 :: L3 BANK INPUT AVAILABLE L3BANK5 */
#define acmgt2__l3_cache1__l3_input_available_l3_bank5__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3Cache1 :: L3 BANK INPUT AVAILABLE L3BANK6 */
#define acmgt2__l3_cache1__l3_input_available_l3_bank6__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3Cache1 :: L3 BANK INPUT AVAILABLE L3BANK7 */
#define acmgt2__l3_cache1__l3_input_available_l3_bank7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3Cache1 :: L3 OUTPUT READY L3BANK0 */
#define acmgt2__l3_cache1__l3_output_ready_l3_bank0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3Cache1 :: L3 OUTPUT READY L3BANK1 */
#define acmgt2__l3_cache1__l3_output_ready_l3_bank1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3Cache1 :: L3 OUTPUT READY L3BANK2 */
#define acmgt2__l3_cache1__l3_output_ready_l3_bank2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3Cache1 :: L3 OUTPUT READY L3BANK3 */
#define acmgt2__l3_cache1__l3_output_ready_l3_bank3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3Cache1 :: L3 OUTPUT READY L3BANK4 */
#define acmgt2__l3_cache1__l3_output_ready_l3_bank4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3Cache1 :: L3 OUTPUT READY L3BANK5 */
#define acmgt2__l3_cache1__l3_output_ready_l3_bank5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3Cache1 :: L3 OUTPUT READY L3BANK6 */
#define acmgt2__l3_cache1__l3_output_ready_l3_bank6__read \
   bdw__render_basic__sampler1_busy__read

/* L3Cache1 :: L3 OUTPUT READY L3BANK7 */
#define acmgt2__l3_cache1__l3_output_ready_l3_bank7__read \
   bdw__render_basic__sampler0_busy__read

/* L3Cache2 :: GPU Time Elapsed */
#define acmgt2__l3_cache2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache2 :: GPU Core Clocks */
#define acmgt2__l3_cache2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache2 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache2 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache2 :: L3 BANK INPUT AVAILABLE L3BANK8 */
#define acmgt2__l3_cache2__l3_input_available_l3_bank8__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3Cache2 :: L3 BANK INPUT AVAILABLE L3BANK9 */
#define acmgt2__l3_cache2__l3_input_available_l3_bank9__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3Cache2 :: L3 BANK INPUT AVAILABLE L3BANK10 */
#define acmgt2__l3_cache2__l3_input_available_l3_bank10__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3Cache2 :: L3 BANK INPUT AVAILABLE L3BANK11 */
#define acmgt2__l3_cache2__l3_input_available_l3_bank11__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3Cache2 :: L3 BANK INPUT AVAILABLE L3BANK12 */
#define acmgt2__l3_cache2__l3_input_available_l3_bank12__read \
   bdw__render_pipe_profile__so_stall__read

/* L3Cache2 :: L3 BANK INPUT AVAILABLE L3BANK13 */
#define acmgt2__l3_cache2__l3_input_available_l3_bank13__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3Cache2 :: L3 BANK INPUT AVAILABLE L3BANK14 */
#define acmgt2__l3_cache2__l3_input_available_l3_bank14__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3Cache2 :: L3 BANK INPUT AVAILABLE L3BANK15 */
#define acmgt2__l3_cache2__l3_input_available_l3_bank15__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3Cache2 :: L3 OUTPUT READY L3BANK8 */
#define acmgt2__l3_cache2__l3_output_ready_l3_bank8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3Cache2 :: L3 OUTPUT READY L3BANK9 */
#define acmgt2__l3_cache2__l3_output_ready_l3_bank9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3Cache2 :: L3 OUTPUT READY L3BANK10 */
#define acmgt2__l3_cache2__l3_output_ready_l3_bank10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3Cache2 :: L3 OUTPUT READY L3BANK11 */
#define acmgt2__l3_cache2__l3_output_ready_l3_bank11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3Cache2 :: L3 OUTPUT READY L3BANK12 */
#define acmgt2__l3_cache2__l3_output_ready_l3_bank12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3Cache2 :: L3 OUTPUT READY L3BANK13 */
#define acmgt2__l3_cache2__l3_output_ready_l3_bank13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3Cache2 :: L3 OUTPUT READY L3BANK14 */
#define acmgt2__l3_cache2__l3_output_ready_l3_bank14__read \
   bdw__render_basic__sampler1_busy__read

/* L3Cache2 :: L3 OUTPUT READY L3BANK15 */
#define acmgt2__l3_cache2__l3_output_ready_l3_bank15__read \
   bdw__render_basic__sampler0_busy__read

/* L3Cache3 :: GPU Time Elapsed */
#define acmgt2__l3_cache3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache3 :: GPU Core Clocks */
#define acmgt2__l3_cache3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache3 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache3 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache3 :: L3 READ L3BANK0 */
#define acmgt2__l3_cache3__l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache3 :: L3 READ L3BANK1 */
#define acmgt2__l3_cache3__l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache3 :: L3 READ L3BANK2 */
#define acmgt2__l3_cache3__l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache3 :: L3 READ L3BANK3 */
#define acmgt2__l3_cache3__l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache3 :: L3 READ L3BANK4 */
#define acmgt2__l3_cache3__l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache3 :: L3 READ L3BANK5 */
#define acmgt2__l3_cache3__l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache3 :: L3 READ L3BANK6 */
#define acmgt2__l3_cache3__l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache3 :: L3 READ L3BANK7 */
#define acmgt2__l3_cache3__l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache3 :: L3 WRITE L3BANK0 */
#define acmgt2__l3_cache3__l3_write_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache3 :: L3 WRITE L3BANK1 */
#define acmgt2__l3_cache3__l3_write_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache3 :: L3 WRITE L3BANK2 */
#define acmgt2__l3_cache3__l3_write_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache3 :: L3 WRITE L3BANK3 */
#define acmgt2__l3_cache3__l3_write_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache3 :: L3 WRITE L3BANK4 */
#define acmgt2__l3_cache3__l3_write_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache3 :: L3 WRITE L3BANK5 */
#define acmgt2__l3_cache3__l3_write_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache3 :: L3 WRITE L3BANK6 */
#define acmgt2__l3_cache3__l3_write_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache3 :: L3 WRITE L3BANK7 */
#define acmgt2__l3_cache3__l3_write_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache4 :: GPU Time Elapsed */
#define acmgt2__l3_cache4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache4 :: GPU Core Clocks */
#define acmgt2__l3_cache4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache4 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache4 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache4 :: L3 READ L3BANK8 */
#define acmgt2__l3_cache4__l3_read_l3_bank8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache4 :: L3 READ L3BANK9 */
#define acmgt2__l3_cache4__l3_read_l3_bank9__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache4 :: L3 READ L3BANK10 */
#define acmgt2__l3_cache4__l3_read_l3_bank10__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache4 :: L3 READ L3BANK11 */
#define acmgt2__l3_cache4__l3_read_l3_bank11__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache4 :: L3 READ L3BANK12 */
#define acmgt2__l3_cache4__l3_read_l3_bank12__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache4 :: L3 READ L3BANK13 */
#define acmgt2__l3_cache4__l3_read_l3_bank13__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache4 :: L3 READ L3BANK14 */
#define acmgt2__l3_cache4__l3_read_l3_bank14__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache4 :: L3 READ L3BANK15 */
#define acmgt2__l3_cache4__l3_read_l3_bank15__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache4 :: L3 WRITE L3BANK8 */
#define acmgt2__l3_cache4__l3_write_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache4 :: L3 WRITE L3BANK9 */
#define acmgt2__l3_cache4__l3_write_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache4 :: L3 WRITE L3BANK10 */
#define acmgt2__l3_cache4__l3_write_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache4 :: L3 WRITE L3BANK11 */
#define acmgt2__l3_cache4__l3_write_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache4 :: L3 WRITE L3BANK12 */
#define acmgt2__l3_cache4__l3_write_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache4 :: L3 WRITE L3BANK13 */
#define acmgt2__l3_cache4__l3_write_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache4 :: L3 WRITE L3BANK14 */
#define acmgt2__l3_cache4__l3_write_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache4 :: L3 WRITE L3BANK15 */
#define acmgt2__l3_cache4__l3_write_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache5 :: GPU Time Elapsed */
#define acmgt2__l3_cache5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache5 :: GPU Core Clocks */
#define acmgt2__l3_cache5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache5 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache5 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache5 :: L3 HIT L3BANK0 */
#define acmgt2__l3_cache5__l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache5 :: L3 HIT L3BANK1 */
#define acmgt2__l3_cache5__l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache5 :: L3 HIT L3BANK2 */
#define acmgt2__l3_cache5__l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache5 :: L3 HIT L3BANK3 */
#define acmgt2__l3_cache5__l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache5 :: L3 HIT L3BANK4 */
#define acmgt2__l3_cache5__l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache5 :: L3 HIT L3BANK5 */
#define acmgt2__l3_cache5__l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache5 :: L3 HIT L3BANK6 */
#define acmgt2__l3_cache5__l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache5 :: L3 HIT L3BANK7 */
#define acmgt2__l3_cache5__l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache5 :: L3 MISS L3BANK0 */
#define acmgt2__l3_cache5__l3_miss_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache5 :: L3 MISS L3BANK1 */
#define acmgt2__l3_cache5__l3_miss_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache5 :: L3 MISS L3BANK2 */
#define acmgt2__l3_cache5__l3_miss_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache5 :: L3 MISS L3BANK3 */
#define acmgt2__l3_cache5__l3_miss_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache5 :: L3 MISS L3BANK4 */
#define acmgt2__l3_cache5__l3_miss_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache5 :: L3 MISS L3BANK5 */
#define acmgt2__l3_cache5__l3_miss_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache5 :: L3 MISS L3BANK6 */
#define acmgt2__l3_cache5__l3_miss_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache5 :: L3 MISS L3BANK7 */
#define acmgt2__l3_cache5__l3_miss_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache6 :: GPU Time Elapsed */
#define acmgt2__l3_cache6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache6 :: GPU Core Clocks */
#define acmgt2__l3_cache6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache6 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache6 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache6 :: L3 HIT L3BANK8 */
#define acmgt2__l3_cache6__l3_hit_l3_bank8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache6 :: L3 HIT L3BANK9 */
#define acmgt2__l3_cache6__l3_hit_l3_bank9__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache6 :: L3 HIT L3BANK10 */
#define acmgt2__l3_cache6__l3_hit_l3_bank10__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache6 :: L3 HIT L3BANK11 */
#define acmgt2__l3_cache6__l3_hit_l3_bank11__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache6 :: L3 HIT L3BANK12 */
#define acmgt2__l3_cache6__l3_hit_l3_bank12__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache6 :: L3 HIT L3BANK13 */
#define acmgt2__l3_cache6__l3_hit_l3_bank13__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache6 :: L3 HIT L3BANK14 */
#define acmgt2__l3_cache6__l3_hit_l3_bank14__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache6 :: L3 HIT L3BANK15 */
#define acmgt2__l3_cache6__l3_hit_l3_bank15__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache6 :: L3 MISS L3BANK8 */
#define acmgt2__l3_cache6__l3_miss_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache6 :: L3 MISS L3BANK9 */
#define acmgt2__l3_cache6__l3_miss_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache6 :: L3 MISS L3BANK10 */
#define acmgt2__l3_cache6__l3_miss_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache6 :: L3 MISS L3BANK11 */
#define acmgt2__l3_cache6__l3_miss_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache6 :: L3 MISS L3BANK12 */
#define acmgt2__l3_cache6__l3_miss_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache6 :: L3 MISS L3BANK13 */
#define acmgt2__l3_cache6__l3_miss_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache6 :: L3 MISS L3BANK14 */
#define acmgt2__l3_cache6__l3_miss_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache6 :: L3 MISS L3BANK15 */
#define acmgt2__l3_cache6__l3_miss_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache7 :: GPU Time Elapsed */
#define acmgt2__l3_cache7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache7 :: GPU Core Clocks */
#define acmgt2__l3_cache7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache7 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache7 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache7 :: DATAPORT L3 READ L3BANK0 */
#define acmgt2__l3_cache7__dataport_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache7 :: DATAPORT L3 READ L3BANK1 */
#define acmgt2__l3_cache7__dataport_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache7 :: DATAPORT L3 READ L3BANK2 */
#define acmgt2__l3_cache7__dataport_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache7 :: DATAPORT L3 READ L3BANK3 */
#define acmgt2__l3_cache7__dataport_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache7 :: DATAPORT L3 READ L3BANK4 */
#define acmgt2__l3_cache7__dataport_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache7 :: DATAPORT L3 READ L3BANK5 */
#define acmgt2__l3_cache7__dataport_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache7 :: DATAPORT L3 READ L3BANK6 */
#define acmgt2__l3_cache7__dataport_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache7 :: DATAPORT L3 READ L3BANK7 */
#define acmgt2__l3_cache7__dataport_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache7 :: DATAPORT L3 WRITE L3BANK0 */
#define acmgt2__l3_cache7__dataport_l3_write_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache7 :: DATAPORT L3 WRITE L3BANK1 */
#define acmgt2__l3_cache7__dataport_l3_write_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache7 :: DATAPORT L3 WRITE L3BANK2 */
#define acmgt2__l3_cache7__dataport_l3_write_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache7 :: DATAPORT L3 WRITE L3BANK3 */
#define acmgt2__l3_cache7__dataport_l3_write_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache7 :: DATAPORT L3 WRITE L3BANK4 */
#define acmgt2__l3_cache7__dataport_l3_write_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache7 :: DATAPORT L3 WRITE L3BANK5 */
#define acmgt2__l3_cache7__dataport_l3_write_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache7 :: DATAPORT L3 WRITE L3BANK6 */
#define acmgt2__l3_cache7__dataport_l3_write_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache7 :: DATAPORT L3 WRITE L3BANK7 */
#define acmgt2__l3_cache7__dataport_l3_write_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache8 :: GPU Time Elapsed */
#define acmgt2__l3_cache8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache8 :: GPU Core Clocks */
#define acmgt2__l3_cache8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache8 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache8 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache8 :: DATAPORT L3 READ L3BANK8 */
#define acmgt2__l3_cache8__dataport_l3_read_l3_bank8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache8 :: DATAPORT L3 READ L3BANK9 */
#define acmgt2__l3_cache8__dataport_l3_read_l3_bank9__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache8 :: DATAPORT L3 READ L3BANK10 */
#define acmgt2__l3_cache8__dataport_l3_read_l3_bank10__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache8 :: DATAPORT L3 READ L3BANK11 */
#define acmgt2__l3_cache8__dataport_l3_read_l3_bank11__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache8 :: DATAPORT L3 READ L3BANK12 */
#define acmgt2__l3_cache8__dataport_l3_read_l3_bank12__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache8 :: DATAPORT L3 READ L3BANK13 */
#define acmgt2__l3_cache8__dataport_l3_read_l3_bank13__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache8 :: DATAPORT L3 READ L3BANK14 */
#define acmgt2__l3_cache8__dataport_l3_read_l3_bank14__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache8 :: DATAPORT L3 READ L3BANK15 */
#define acmgt2__l3_cache8__dataport_l3_read_l3_bank15__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache8 :: DATAPORT L3 WRITE L3BANK8 */
#define acmgt2__l3_cache8__dataport_l3_write_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache8 :: DATAPORT L3 WRITE L3BANK9 */
#define acmgt2__l3_cache8__dataport_l3_write_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache8 :: DATAPORT L3 WRITE L3BANK10 */
#define acmgt2__l3_cache8__dataport_l3_write_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache8 :: DATAPORT L3 WRITE L3BANK11 */
#define acmgt2__l3_cache8__dataport_l3_write_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache8 :: DATAPORT L3 WRITE L3BANK12 */
#define acmgt2__l3_cache8__dataport_l3_write_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache8 :: DATAPORT L3 WRITE L3BANK13 */
#define acmgt2__l3_cache8__dataport_l3_write_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache8 :: DATAPORT L3 WRITE L3BANK14 */
#define acmgt2__l3_cache8__dataport_l3_write_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache8 :: DATAPORT L3 WRITE L3BANK15 */
#define acmgt2__l3_cache8__dataport_l3_write_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache9 :: GPU Time Elapsed */
#define acmgt2__l3_cache9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache9 :: GPU Core Clocks */
#define acmgt2__l3_cache9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache9 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache9 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache9 :: ICACHE L3 READ L3BANK0 */
#define acmgt2__l3_cache9__icache_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache9 :: ICACHE L3 READ L3BANK1 */
#define acmgt2__l3_cache9__icache_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache9 :: ICACHE L3 READ L3BANK2 */
#define acmgt2__l3_cache9__icache_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache9 :: ICACHE L3 READ L3BANK3 */
#define acmgt2__l3_cache9__icache_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache9 :: ICACHE L3 READ L3BANK4 */
#define acmgt2__l3_cache9__icache_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache9 :: ICACHE L3 READ L3BANK5 */
#define acmgt2__l3_cache9__icache_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache9 :: ICACHE L3 READ L3BANK6 */
#define acmgt2__l3_cache9__icache_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache9 :: ICACHE L3 READ L3BANK7 */
#define acmgt2__l3_cache9__icache_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache9 :: ICACHE L3 HIT L3BANK0 */
#define acmgt2__l3_cache9__icache_l3_hit_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache9 :: ICACHE L3 HIT L3BANK1 */
#define acmgt2__l3_cache9__icache_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache9 :: ICACHE L3 HIT L3BANK2 */
#define acmgt2__l3_cache9__icache_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache9 :: ICACHE L3 HIT L3BANK3 */
#define acmgt2__l3_cache9__icache_l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache9 :: ICACHE L3 HIT L3BANK4 */
#define acmgt2__l3_cache9__icache_l3_hit_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache9 :: ICACHE L3 HIT L3BANK5 */
#define acmgt2__l3_cache9__icache_l3_hit_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache9 :: ICACHE L3 HIT L3BANK6 */
#define acmgt2__l3_cache9__icache_l3_hit_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache9 :: ICACHE L3 HIT L3BANK7 */
#define acmgt2__l3_cache9__icache_l3_hit_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache10 :: GPU Time Elapsed */
#define acmgt2__l3_cache10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache10 :: GPU Core Clocks */
#define acmgt2__l3_cache10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache10 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache10 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache10 :: ICACHE L3 READ L3BANK8 */
#define acmgt2__l3_cache10__icache_l3_read_l3_bank8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache10 :: ICACHE L3 READ L3BANK9 */
#define acmgt2__l3_cache10__icache_l3_read_l3_bank9__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache10 :: ICACHE L3 READ L3BANK10 */
#define acmgt2__l3_cache10__icache_l3_read_l3_bank10__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache10 :: ICACHE L3 READ L3BANK11 */
#define acmgt2__l3_cache10__icache_l3_read_l3_bank11__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache10 :: ICACHE L3 READ L3BANK12 */
#define acmgt2__l3_cache10__icache_l3_read_l3_bank12__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache10 :: ICACHE L3 READ L3BANK13 */
#define acmgt2__l3_cache10__icache_l3_read_l3_bank13__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache10 :: ICACHE L3 READ L3BANK14 */
#define acmgt2__l3_cache10__icache_l3_read_l3_bank14__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache10 :: ICACHE L3 READ L3BANK15 */
#define acmgt2__l3_cache10__icache_l3_read_l3_bank15__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache10 :: ICACHE L3 HIT L3BANK8 */
#define acmgt2__l3_cache10__icache_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache10 :: ICACHE L3 HIT L3BANK9 */
#define acmgt2__l3_cache10__icache_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache10 :: ICACHE L3 HIT L3BANK10 */
#define acmgt2__l3_cache10__icache_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache10 :: ICACHE L3 HIT L3BANK11 */
#define acmgt2__l3_cache10__icache_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache10 :: ICACHE L3 HIT L3BANK12 */
#define acmgt2__l3_cache10__icache_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache10 :: ICACHE L3 HIT L3BANK13 */
#define acmgt2__l3_cache10__icache_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache10 :: ICACHE L3 HIT L3BANK14 */
#define acmgt2__l3_cache10__icache_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache10 :: ICACHE L3 HIT L3BANK15 */
#define acmgt2__l3_cache10__icache_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache11 :: GPU Time Elapsed */
#define acmgt2__l3_cache11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache11 :: GPU Core Clocks */
#define acmgt2__l3_cache11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache11 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache11 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache11 :: L3 BANK ACTIVE L3BANK0 */
#define acmgt2__l3_cache11__l3_busy_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3Cache11 :: L3 BANK ACTIVE L3BANK1 */
#define acmgt2__l3_cache11__l3_busy_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3Cache11 :: L3 BANK ACTIVE L3BANK2 */
#define acmgt2__l3_cache11__l3_busy_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3Cache11 :: L3 BANK ACTIVE L3BANK3 */
#define acmgt2__l3_cache11__l3_busy_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3Cache11 :: L3 BANK STALL L3BANK0 */
#define acmgt2__l3_cache11__l3_stall_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* L3Cache11 :: L3 BANK STALL L3BANK1 */
#define acmgt2__l3_cache11__l3_stall_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* L3Cache11 :: L3 BANK STALL L3BANK2 */
#define acmgt2__l3_cache11__l3_stall_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3Cache11 :: L3 BANK STALL L3BANK3 */
#define acmgt2__l3_cache11__l3_stall_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3Cache12 :: GPU Time Elapsed */
#define acmgt2__l3_cache12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache12 :: GPU Core Clocks */
#define acmgt2__l3_cache12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache12 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache12 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache12 :: L3 BANK ACTIVE L3BANK4 */
#define acmgt2__l3_cache12__l3_busy_l3_bank4__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3Cache12 :: L3 BANK ACTIVE L3BANK5 */
#define acmgt2__l3_cache12__l3_busy_l3_bank5__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3Cache12 :: L3 BANK ACTIVE L3BANK6 */
#define acmgt2__l3_cache12__l3_busy_l3_bank6__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3Cache12 :: L3 BANK ACTIVE L3BANK7 */
#define acmgt2__l3_cache12__l3_busy_l3_bank7__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3Cache12 :: L3 BANK STALL L3BANK4 */
#define acmgt2__l3_cache12__l3_stall_l3_bank4__read \
   bdw__render_basic__sampler0_busy__read

/* L3Cache12 :: L3 BANK STALL L3BANK5 */
#define acmgt2__l3_cache12__l3_stall_l3_bank5__read \
   bdw__render_basic__sampler1_busy__read

/* L3Cache12 :: L3 BANK STALL L3BANK6 */
#define acmgt2__l3_cache12__l3_stall_l3_bank6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3Cache12 :: L3 BANK STALL L3BANK7 */
#define acmgt2__l3_cache12__l3_stall_l3_bank7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3Cache13 :: GPU Time Elapsed */
#define acmgt2__l3_cache13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache13 :: GPU Core Clocks */
#define acmgt2__l3_cache13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache13 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache13 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache13 :: L3 BANK ACTIVE L3BANK8 */
#define acmgt2__l3_cache13__l3_busy_l3_bank8__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3Cache13 :: L3 BANK ACTIVE L3BANK9 */
#define acmgt2__l3_cache13__l3_busy_l3_bank9__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3Cache13 :: L3 BANK ACTIVE L3BANK10 */
#define acmgt2__l3_cache13__l3_busy_l3_bank10__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3Cache13 :: L3 BANK ACTIVE L3BANK11 */
#define acmgt2__l3_cache13__l3_busy_l3_bank11__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3Cache13 :: L3 BANK STALL L3BANK8 */
#define acmgt2__l3_cache13__l3_stall_l3_bank8__read \
   bdw__render_basic__sampler0_busy__read

/* L3Cache13 :: L3 BANK STALL L3BANK9 */
#define acmgt2__l3_cache13__l3_stall_l3_bank9__read \
   bdw__render_basic__sampler1_busy__read

/* L3Cache13 :: L3 BANK STALL L3BANK10 */
#define acmgt2__l3_cache13__l3_stall_l3_bank10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3Cache13 :: L3 BANK STALL L3BANK11 */
#define acmgt2__l3_cache13__l3_stall_l3_bank11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3Cache14 :: GPU Time Elapsed */
#define acmgt2__l3_cache14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache14 :: GPU Core Clocks */
#define acmgt2__l3_cache14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache14 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache14 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache14 :: L3 BANK ACTIVE L3BANK12 */
#define acmgt2__l3_cache14__l3_busy_l3_bank12__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3Cache14 :: L3 BANK ACTIVE L3BANK13 */
#define acmgt2__l3_cache14__l3_busy_l3_bank13__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3Cache14 :: L3 BANK ACTIVE L3BANK14 */
#define acmgt2__l3_cache14__l3_busy_l3_bank14__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3Cache14 :: L3 BANK ACTIVE L3BANK15 */
#define acmgt2__l3_cache14__l3_busy_l3_bank15__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3Cache14 :: L3 BANK STALL L3BANK12 */
#define acmgt2__l3_cache14__l3_stall_l3_bank12__read \
   bdw__render_basic__sampler0_busy__read

/* L3Cache14 :: L3 BANK STALL L3BANK13 */
#define acmgt2__l3_cache14__l3_stall_l3_bank13__read \
   bdw__render_basic__sampler1_busy__read

/* L3Cache14 :: L3 BANK STALL L3BANK14 */
#define acmgt2__l3_cache14__l3_stall_l3_bank14__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3Cache14 :: L3 BANK STALL L3BANK15 */
#define acmgt2__l3_cache14__l3_stall_l3_bank15__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3Cache15 :: GPU Time Elapsed */
#define acmgt2__l3_cache15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache15 :: GPU Core Clocks */
#define acmgt2__l3_cache15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache15 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache15 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache15 :: SAMPLER L3 READ L3BANK0 */
#define acmgt2__l3_cache15__sampler_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache15 :: SAMPLER L3 READ L3BANK1 */
#define acmgt2__l3_cache15__sampler_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache15 :: SAMPLER L3 READ L3BANK2 */
#define acmgt2__l3_cache15__sampler_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache15 :: SAMPLER L3 READ L3BANK3 */
#define acmgt2__l3_cache15__sampler_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache15 :: SAMPLER L3 READ L3BANK4 */
#define acmgt2__l3_cache15__sampler_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache15 :: SAMPLER L3 READ L3BANK5 */
#define acmgt2__l3_cache15__sampler_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache15 :: SAMPLER L3 READ L3BANK6 */
#define acmgt2__l3_cache15__sampler_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache15 :: SAMPLER L3 READ L3BANK7 */
#define acmgt2__l3_cache15__sampler_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache15 :: SAMPLER L3 HIT L3BANK0 */
#define acmgt2__l3_cache15__sampler_l3_hit_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache15 :: SAMPLER L3 HIT L3BANK1 */
#define acmgt2__l3_cache15__sampler_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache15 :: SAMPLER L3 HIT L3BANK2 */
#define acmgt2__l3_cache15__sampler_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache15 :: SAMPLER L3 HIT L3BANK3 */
#define acmgt2__l3_cache15__sampler_l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache15 :: SAMPLER L3 HIT L3BANK4 */
#define acmgt2__l3_cache15__sampler_l3_hit_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache15 :: SAMPLER L3 HIT L3BANK5 */
#define acmgt2__l3_cache15__sampler_l3_hit_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache15 :: SAMPLER L3 HIT L3BANK6 */
#define acmgt2__l3_cache15__sampler_l3_hit_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache15 :: SAMPLER L3 HIT L3BANK7 */
#define acmgt2__l3_cache15__sampler_l3_hit_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache16 :: GPU Time Elapsed */
#define acmgt2__l3_cache16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache16 :: GPU Core Clocks */
#define acmgt2__l3_cache16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache16 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache16 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache16 :: SAMPLER L3 READ L3BANK8 */
#define acmgt2__l3_cache16__sampler_l3_read_l3_bank8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache16 :: SAMPLER L3 READ L3BANK9 */
#define acmgt2__l3_cache16__sampler_l3_read_l3_bank9__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache16 :: SAMPLER L3 READ L3BANK10 */
#define acmgt2__l3_cache16__sampler_l3_read_l3_bank10__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache16 :: SAMPLER L3 READ L3BANK11 */
#define acmgt2__l3_cache16__sampler_l3_read_l3_bank11__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache16 :: SAMPLER L3 READ L3BANK12 */
#define acmgt2__l3_cache16__sampler_l3_read_l3_bank12__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache16 :: SAMPLER L3 READ L3BANK13 */
#define acmgt2__l3_cache16__sampler_l3_read_l3_bank13__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache16 :: SAMPLER L3 READ L3BANK14 */
#define acmgt2__l3_cache16__sampler_l3_read_l3_bank14__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache16 :: SAMPLER L3 READ L3BANK15 */
#define acmgt2__l3_cache16__sampler_l3_read_l3_bank15__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache16 :: SAMPLER L3 HIT L3BANK8 */
#define acmgt2__l3_cache16__sampler_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache16 :: SAMPLER L3 HIT L3BANK9 */
#define acmgt2__l3_cache16__sampler_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache16 :: SAMPLER L3 HIT L3BANK10 */
#define acmgt2__l3_cache16__sampler_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache16 :: SAMPLER L3 HIT L3BANK11 */
#define acmgt2__l3_cache16__sampler_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache16 :: SAMPLER L3 HIT L3BANK12 */
#define acmgt2__l3_cache16__sampler_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache16 :: SAMPLER L3 HIT L3BANK13 */
#define acmgt2__l3_cache16__sampler_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache16 :: SAMPLER L3 HIT L3BANK14 */
#define acmgt2__l3_cache16__sampler_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache16 :: SAMPLER L3 HIT L3BANK15 */
#define acmgt2__l3_cache16__sampler_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache17 :: GPU Time Elapsed */
#define acmgt2__l3_cache17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache17 :: GPU Core Clocks */
#define acmgt2__l3_cache17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache17 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache17 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache17 :: L3 SUPERQ FULL L3BANK0 */
#define acmgt2__l3_cache17__l3_superq_full_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* L3Cache17 :: L3 SUPERQ FULL L3BANK1 */
#define acmgt2__l3_cache17__l3_superq_full_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* L3Cache17 :: L3 SUPERQ FULL L3BANK2 */
#define acmgt2__l3_cache17__l3_superq_full_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3Cache17 :: L3 SUPERQ FULL L3BANK3 */
#define acmgt2__l3_cache17__l3_superq_full_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3Cache17 :: L3 SUPERQ FULL L3BANK4 */
#define acmgt2__l3_cache17__l3_superq_full_l3_bank4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3Cache17 :: L3 SUPERQ FULL L3BANK5 */
#define acmgt2__l3_cache17__l3_superq_full_l3_bank5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3Cache17 :: L3 SUPERQ FULL L3BANK6 */
#define acmgt2__l3_cache17__l3_superq_full_l3_bank6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3Cache17 :: L3 SUPERQ FULL L3BANK7 */
#define acmgt2__l3_cache17__l3_superq_full_l3_bank7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3Cache18 :: GPU Time Elapsed */
#define acmgt2__l3_cache18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache18 :: GPU Core Clocks */
#define acmgt2__l3_cache18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache18 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache18 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache18 :: L3 SUPERQ FULL L3BANK8 */
#define acmgt2__l3_cache18__l3_superq_full_l3_bank8__read \
   bdw__render_basic__sampler0_busy__read

/* L3Cache18 :: L3 SUPERQ FULL L3BANK9 */
#define acmgt2__l3_cache18__l3_superq_full_l3_bank9__read \
   bdw__render_basic__sampler1_busy__read

/* L3Cache18 :: L3 SUPERQ FULL L3BANK10 */
#define acmgt2__l3_cache18__l3_superq_full_l3_bank10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3Cache18 :: L3 SUPERQ FULL L3BANK11 */
#define acmgt2__l3_cache18__l3_superq_full_l3_bank11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3Cache18 :: L3 SUPERQ FULL L3BANK12 */
#define acmgt2__l3_cache18__l3_superq_full_l3_bank12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3Cache18 :: L3 SUPERQ FULL L3BANK13 */
#define acmgt2__l3_cache18__l3_superq_full_l3_bank13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3Cache18 :: L3 SUPERQ FULL L3BANK14 */
#define acmgt2__l3_cache18__l3_superq_full_l3_bank14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3Cache18 :: L3 SUPERQ FULL L3BANK15 */
#define acmgt2__l3_cache18__l3_superq_full_l3_bank15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3Cache19 :: GPU Time Elapsed */
#define acmgt2__l3_cache19__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache19 :: GPU Core Clocks */
#define acmgt2__l3_cache19__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache19 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache19__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache19 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache19__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache19 :: COLOR L3 HIT L3BANK0 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache19 :: COLOR L3 HIT L3BANK1 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache19 :: COLOR L3 HIT L3BANK2 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache19 :: COLOR L3 HIT L3BANK3 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK4 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK5 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache19 :: COLOR L3 HIT L3BANK6 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK7 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK8 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache19 :: COLOR L3 HIT L3BANK9 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK10 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK11 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK12 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK13 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK14 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache19 :: COLOR L3 HIT L3BANK15 */
#define acmgt2__l3_cache19__color_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache20 :: GPU Time Elapsed */
#define acmgt2__l3_cache20__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache20 :: GPU Core Clocks */
#define acmgt2__l3_cache20__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache20 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache20__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache20 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache20__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache20 :: Z L3 HIT L3BANK0 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache20 :: Z L3 HIT L3BANK1 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache20 :: Z L3 HIT L3BANK2 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache20 :: Z L3 HIT L3BANK3 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache20 :: Z L3 HIT L3BANK4 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache20 :: Z L3 HIT L3BANK5 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache20 :: Z L3 HIT L3BANK6 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache20 :: Z L3 HIT L3BANK7 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache20 :: Z L3 HIT L3BANK8 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache20 :: Z L3 HIT L3BANK9 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache20 :: Z L3 HIT L3BANK10 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache20 :: Z L3 HIT L3BANK11 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache20 :: Z L3 HIT L3BANK12 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache20 :: Z L3 HIT L3BANK13 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache20 :: Z L3 HIT L3BANK14 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache20 :: Z L3 HIT L3BANK15 */
#define acmgt2__l3_cache20__z_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache21 :: GPU Time Elapsed */
#define acmgt2__l3_cache21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache21 :: GPU Core Clocks */
#define acmgt2__l3_cache21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache21 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache21 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache21 :: DATAPORT L3 HIT L3BANK0 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK1 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK2 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK3 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK4 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK5 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK6 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK7 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK8 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK9 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK10 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK11 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK12 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK13 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK14 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache21 :: DATAPORT L3 HIT L3BANK15 */
#define acmgt2__l3_cache21__dataport_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* L3Cache22 :: GPU Time Elapsed */
#define acmgt2__l3_cache22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3Cache22 :: GPU Core Clocks */
#define acmgt2__l3_cache22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3Cache22 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3Cache22 :: AVG GPU Core Frequency */
#define acmgt2__l3_cache22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK0 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK1 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK2 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK3 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK4 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK5 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK6 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK7 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK8 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK9 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK10 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK11 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK12 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK13 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK14 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* L3Cache22 :: L3 ATOMIC ACCESS L3BANK15 */
#define acmgt2__l3_cache22__l3_atomic_access_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory1 :: GPU Time Elapsed */
#define acmgt2__memory1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory1 :: GPU Core Clocks */
#define acmgt2__memory1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory1 :: AVG GPU Core Frequency */
#define acmgt2__memory1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory1 :: AVG GPU Core Frequency */
#define acmgt2__memory1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory1 :: GPU MEMORY BYTE READ SQIDI0 */
#define acmgt2__memory1__gpu_memory_byte_read_sqidi0__read \
   acmgt1__ext1__gpu_memory_byte_write_sqidi0__read

/* Memory1 :: GPU MEMORY BYTE READ SQIDI1 */
#define acmgt2__memory1__gpu_memory_byte_read_sqidi1__read \
   hsw__render_basic__gti_read_throughput__read

/* Memory1 :: GPU MEMORY BYTE READ SQIDI2 */
#define acmgt2__memory1__gpu_memory_byte_read_sqidi2__read \
   acmgt1__ext1__gpu_memory_byte_read_sqidi0__read

/* Memory1 :: GPU MEMORY BYTE READ SQIDI3 */
#define acmgt2__memory1__gpu_memory_byte_read_sqidi3__read \
   acmgt1__ext1__gpu_memory_byte_read_sqidi1__read

/* Memory1 :: GPU MEMORY BYTE WRITE SQIDI0 */
static uint64_t
acmgt2__memory1__gpu_memory_byte_write_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Memory1 :: GPU MEMORY BYTE WRITE SQIDI1 */
#define acmgt2__memory1__gpu_memory_byte_write_sqidi1__read \
   chv__compute_basic__gti_ring_throughput__read

/* Memory1 :: GPU MEMORY BYTE WRITE SQIDI2 */
static uint64_t
acmgt2__memory1__gpu_memory_byte_write_sqidi2__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Memory1 :: GPU MEMORY BYTE WRITE SQIDI3 */
static uint64_t
acmgt2__memory1__gpu_memory_byte_write_sqidi3__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Memory1 :: GPU MEMORY BYTE READ BW SQIDI0 */
#define acmgt2__memory1__gpu_memory_byte_read_bw_sqidi0__read \
   acmgt1__ext1__gpu_memory_byte_write_bw_sqidi0__read

/* Memory1 :: GPU MEMORY BYTE READ BW SQIDI1 */
#define acmgt2__memory1__gpu_memory_byte_read_bw_sqidi1__read \
   acmgt1__ext1__gpu_memory_byte_write_bw_sqidi1__read

/* Memory1 :: GPU MEMORY BYTE READ BW SQIDI2 */
#define acmgt2__memory1__gpu_memory_byte_read_bw_sqidi2__read \
   acmgt1__ext1__gpu_memory_byte_read_bw_sqidi0__read

/* Memory1 :: GPU MEMORY BYTE READ BW SQIDI3 */
#define acmgt2__memory1__gpu_memory_byte_read_bw_sqidi3__read \
   acmgt1__ext1__gpu_memory_byte_read_bw_sqidi1__read

/* Memory1 :: GPU MEMORY BYTE WRITE BW SQIDI0 */
static float
acmgt2__memory1__gpu_memory_byte_write_bw_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI0 $GpuTime FDIV */
   double tmp0 = acmgt2__memory1__gpu_memory_byte_write_sqidi0__read(perf, query, results);
   double tmp1 = acmgt2__memory1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Memory1 :: GPU MEMORY BYTE WRITE BW SQIDI1 */
static float
acmgt2__memory1__gpu_memory_byte_write_bw_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI1 $GpuTime FDIV */
   double tmp0 = acmgt2__memory1__gpu_memory_byte_write_sqidi1__read(perf, query, results);
   double tmp1 = acmgt2__memory1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Memory1 :: GPU MEMORY BYTE WRITE BW SQIDI2 */
static float
acmgt2__memory1__gpu_memory_byte_write_bw_sqidi2__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI2 $GpuTime FDIV */
   double tmp0 = acmgt2__memory1__gpu_memory_byte_write_sqidi2__read(perf, query, results);
   double tmp1 = acmgt2__memory1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Memory1 :: GPU MEMORY BYTE WRITE BW SQIDI3 */
static float
acmgt2__memory1__gpu_memory_byte_write_bw_sqidi3__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI3 $GpuTime FDIV */
   double tmp0 = acmgt2__memory1__gpu_memory_byte_write_sqidi3__read(perf, query, results);
   double tmp1 = acmgt2__memory1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Memory1 :: GPU MEMORY BYTE READ */
static uint64_t
acmgt2__memory1__gpu_memory_byte_read__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ  C 6 READ UADD  C 5 READ UADD  C 4 READ UADD 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = tmp6 * 128;

   return tmp7;
}

/* Memory1 :: GPU MEMORY BYTE READ */
#define acmgt2__memory1__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* Memory1 :: GPU MEMORY BYTE WRITE */
static uint64_t
acmgt2__memory1__gpu_memory_byte_write__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ  C 2 READ UADD  C 1 READ UADD  C 0 READ UADD 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 1];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 0];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = tmp6 * 128;

   return tmp7;
}

/* Memory1 :: GPU MEMORY BYTE WRITE */
#define acmgt2__memory1__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* Memory1 :: GPU MEMORY BYTE READ BW */
static float
acmgt2__memory1__gpu_memory_byte_read_bw__read(UNUSED struct intel_perf_config *perf,
                                               const struct intel_perf_query_info *query,
                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_READ $GpuTime FDIV */
   double tmp0 = acmgt2__memory1__gpu_memory_byte_read__read(perf, query, results);
   double tmp1 = acmgt2__memory1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Memory1 :: GPU MEMORY BYTE WRITE BW */
static float
acmgt2__memory1__gpu_memory_byte_write_bw__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE $GpuTime FDIV */
   double tmp0 = acmgt2__memory1__gpu_memory_byte_write__read(perf, query, results);
   double tmp1 = acmgt2__memory1__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Memory2 :: GPU Time Elapsed */
#define acmgt2__memory2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory2 :: GPU Core Clocks */
#define acmgt2__memory2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory2 :: AVG GPU Core Frequency */
#define acmgt2__memory2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory2 :: AVG GPU Core Frequency */
#define acmgt2__memory2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory2 :: GPU MEMORY READ SQIDI0 */
#define acmgt2__memory2__gpu_memory_read_sqidi0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Memory2 :: GPU MEMORY READ SQIDI1 */
#define acmgt2__memory2__gpu_memory_read_sqidi1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Memory2 :: GPU MEMORY READ SQIDI2 */
#define acmgt2__memory2__gpu_memory_read_sqidi2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Memory2 :: GPU MEMORY READ SQIDI3 */
#define acmgt2__memory2__gpu_memory_read_sqidi3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Memory2 :: GPU MEMORY READ */
static uint64_t
acmgt2__memory2__gpu_memory_read__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_READ_SQIDI0 $GPU_MEMORY_READ_SQIDI1 UADD $GPU_MEMORY_READ_SQIDI2 UADD $GPU_MEMORY_READ_SQIDI3 UADD */
   uint64_t tmp0 = acmgt2__memory2__gpu_memory_read_sqidi0__read(perf, query, results) + acmgt2__memory2__gpu_memory_read_sqidi1__read(perf, query, results);
   uint64_t tmp1 = tmp0 + acmgt2__memory2__gpu_memory_read_sqidi2__read(perf, query, results);
   uint64_t tmp2 = tmp1 + acmgt2__memory2__gpu_memory_read_sqidi3__read(perf, query, results);

   return tmp2;
}

/* Memory3 :: GPU Time Elapsed */
#define acmgt2__memory3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory3 :: GPU Core Clocks */
#define acmgt2__memory3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory3 :: AVG GPU Core Frequency */
#define acmgt2__memory3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory3 :: AVG GPU Core Frequency */
#define acmgt2__memory3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory3 :: GPU MEMORY WRITE SQIDI0 */
#define acmgt2__memory3__gpu_memory_write_sqidi0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory3 :: GPU MEMORY WRITE SQIDI1 */
#define acmgt2__memory3__gpu_memory_write_sqidi1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory3 :: GPU MEMORY WRITE SQIDI2 */
#define acmgt2__memory3__gpu_memory_write_sqidi2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory3 :: GPU MEMORY WRITE SQIDI3 */
#define acmgt2__memory3__gpu_memory_write_sqidi3__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory3 :: GPU MEMORY WRITE */
#define acmgt2__memory3__gpu_memory_write__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Memory3 :: HOST TO GPUMEM TRANSACTION READ */
#define acmgt2__memory3__host_to_gpumem_transaction_read__read \
   hsw__compute_extended__untyped_reads0__read

/* Memory3 :: HOST TO GPUMEM TRANSACTION WRITE */
#define acmgt2__memory3__host_to_gpumem_transaction_write__read \
   hsw__render_basic__gpu_core_clocks__read

/* Memory4 :: GPU Time Elapsed */
#define acmgt2__memory4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory4 :: GPU Core Clocks */
#define acmgt2__memory4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory4 :: AVG GPU Core Frequency */
#define acmgt2__memory4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory4 :: AVG GPU Core Frequency */
#define acmgt2__memory4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory4 :: GPU MEMORY 32B TRANSACTION READ SQIDI0 */
static uint64_t
acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                               const struct intel_perf_query_info *query,
                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 C 7 READ UMUL C 6 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = 2 * tmp0;
   uint64_t tmp2 = results->accumulator[query->c_offset + 6];
   uint64_t tmp3 = tmp1 + tmp2;

   return tmp3;
}

/* Memory4 :: GPU MEMORY 32B TRANSACTION READ SQIDI1 */
static uint64_t
acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                                               const struct intel_perf_query_info *query,
                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 C 5 READ UMUL C 4 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = 2 * tmp0;
   uint64_t tmp2 = results->accumulator[query->c_offset + 4];
   uint64_t tmp3 = tmp1 + tmp2;

   return tmp3;
}

/* Memory4 :: GPU MEMORY 32B TRANSACTION READ SQIDI2 */
static uint64_t
acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi2__read(UNUSED struct intel_perf_config *perf,
                                                               const struct intel_perf_query_info *query,
                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 C 3 READ UMUL C 2 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = 2 * tmp0;
   uint64_t tmp2 = results->accumulator[query->c_offset + 2];
   uint64_t tmp3 = tmp1 + tmp2;

   return tmp3;
}

/* Memory4 :: GPU MEMORY 32B TRANSACTION READ SQIDI3 */
#define acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi3__read \
   acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi0__read

/* Memory4 :: GPU MEMORY 64B TRANSACTION READ SQIDI0 */
#define acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi0__read \
   acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi1__read

/* Memory4 :: GPU MEMORY 64B TRANSACTION READ SQIDI1 */
#define acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi1__read \
   acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi1__read

/* Memory4 :: GPU MEMORY 64B TRANSACTION READ SQIDI2 */
#define acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi2__read \
   acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi0__read

/* Memory4 :: GPU MEMORY 64B TRANSACTION READ SQIDI3 */
static uint64_t
acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi3__read(UNUSED struct intel_perf_config *perf,
                                                               const struct intel_perf_query_info *query,
                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: 2 B 1 READ UMUL B 0 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = 2 * tmp0;
   uint64_t tmp2 = results->accumulator[query->b_offset + 0];
   uint64_t tmp3 = tmp1 + tmp2;

   return tmp3;
}

/* Memory5 :: GPU Time Elapsed */
#define acmgt2__memory5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory5 :: GPU Core Clocks */
#define acmgt2__memory5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory5 :: AVG GPU Core Frequency */
#define acmgt2__memory5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory5 :: AVG GPU Core Frequency */
#define acmgt2__memory5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI0 */
#define acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI1 */
#define acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI2 */
#define acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Memory5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI3 */
#define acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi3__read \
   hsw__compute_extended__typed_atomics0__read

/* Memory5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI0 */
#define acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi0__read \
   hsw__compute_extended__untyped_reads0__read

/* Memory5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI1 */
#define acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Memory5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI2 */
#define acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi2__read \
   hsw__compute_extended__untyped_writes0__read

/* Memory5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI3 */
#define acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi3__read \
   hsw__compute_extended__typed_writes0__read

/* Memory6 :: GPU Time Elapsed */
#define acmgt2__memory6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory6 :: GPU Core Clocks */
#define acmgt2__memory6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory6 :: AVG GPU Core Frequency */
#define acmgt2__memory6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory6 :: AVG GPU Core Frequency */
#define acmgt2__memory6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory6 :: GPU MEMORY ACTIVE SQIDI0 */
#define acmgt2__memory6__gpu_memory_active_sqidi0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Memory6 :: GPU MEMORY ACTIVE SQIDI1 */
#define acmgt2__memory6__gpu_memory_active_sqidi1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Memory6 :: GPU MEMORY ACTIVE SQIDI2 */
#define acmgt2__memory6__gpu_memory_active_sqidi2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Memory6 :: GPU MEMORY ACTIVE SQIDI3 */
#define acmgt2__memory6__gpu_memory_active_sqidi3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Memory6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI0 */
#define acmgt2__memory6__gpu_memory_request_queue_full_sqidi0__read \
   bdw__render_pipe_profile__so_stall__read

/* Memory6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI1 */
#define acmgt2__memory6__gpu_memory_request_queue_full_sqidi1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Memory6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI2 */
#define acmgt2__memory6__gpu_memory_request_queue_full_sqidi2__read \
   bdw__render_pipe_profile__hs_stall__read

/* Memory6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI3 */
#define acmgt2__memory6__gpu_memory_request_queue_full_sqidi3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Memory6 :: GPU MEMORY ACTIVE */
static float
acmgt2__memory6__gpu_memory_active__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ  C 6 READ FADD  C 5 READ FADD  C 4 READ FADD 8 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 8;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   double tmp10 = tmp9;
   double tmp11 = acmgt2__memory6__gpu_core_clocks__read(perf, query, results);
   double tmp12 = tmp11 ? tmp10 / tmp11 : 0;

   return tmp12;
}

/* Memory6 :: GPU MEMORY REQUEST QUEUE FULL */
static float
acmgt2__memory6__gpu_memory_request_queue_full__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ  C 2 READ FADD  C 1 READ FADD  C 0 READ FADD 4 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 1];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 0];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   double tmp10 = tmp9;
   double tmp11 = acmgt2__memory6__gpu_core_clocks__read(perf, query, results);
   double tmp12 = tmp11 ? tmp10 / tmp11 : 0;

   return tmp12;
}

/* Memory7 :: GPU Time Elapsed */
#define acmgt2__memory7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory7 :: GPU Core Clocks */
#define acmgt2__memory7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory7 :: AVG GPU Core Frequency */
#define acmgt2__memory7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory7 :: AVG GPU Core Frequency */
#define acmgt2__memory7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory7 :: GPU MEMORY L3 WRITE SQIDI0 */
#define acmgt2__memory7__gpu_memory_l3_write_sqidi0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory7 :: SYSMEM TRANSACTION READ */
#define acmgt2__memory7__sysmem_transaction_read__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Memory7 :: SYSMEM TRANSACTION WRITE */
#define acmgt2__memory7__sysmem_transaction_write__read \
   hsw__memory_reads__llc_read_accesses__read

/* Memory8 :: GPU Time Elapsed */
#define acmgt2__memory8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory8 :: GPU Core Clocks */
#define acmgt2__memory8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory8 :: AVG GPU Core Frequency */
#define acmgt2__memory8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory8 :: AVG GPU Core Frequency */
#define acmgt2__memory8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory8 :: GPU MEMORY L3 WRITE SQIDI1 */
#define acmgt2__memory8__gpu_memory_l3_write_sqidi1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory9 :: GPU Time Elapsed */
#define acmgt2__memory9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory9 :: GPU Core Clocks */
#define acmgt2__memory9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory9 :: AVG GPU Core Frequency */
#define acmgt2__memory9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory9 :: AVG GPU Core Frequency */
#define acmgt2__memory9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory9 :: GPU MEMORY L3 WRITE SQIDI2 */
#define acmgt2__memory9__gpu_memory_l3_write_sqidi2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory10 :: GPU Time Elapsed */
#define acmgt2__memory10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory10 :: GPU Core Clocks */
#define acmgt2__memory10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory10 :: AVG GPU Core Frequency */
#define acmgt2__memory10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory10 :: AVG GPU Core Frequency */
#define acmgt2__memory10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory10 :: GPU MEMORY L3 WRITE SQIDI3 */
#define acmgt2__memory10__gpu_memory_l3_write_sqidi3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Memory11 :: GPU Time Elapsed */
#define acmgt2__memory11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory11 :: GPU Core Clocks */
#define acmgt2__memory11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory11 :: AVG GPU Core Frequency */
#define acmgt2__memory11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory11 :: AVG GPU Core Frequency */
#define acmgt2__memory11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory11 :: GPU MEMORY L3 READ SQIDI0 */
#define acmgt2__memory11__gpu_memory_l3_read_sqidi0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Memory12 :: GPU Time Elapsed */
#define acmgt2__memory12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory12 :: GPU Core Clocks */
#define acmgt2__memory12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory12 :: AVG GPU Core Frequency */
#define acmgt2__memory12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory12 :: AVG GPU Core Frequency */
#define acmgt2__memory12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory12 :: GPU MEMORY L3 READ SQIDI1 */
#define acmgt2__memory12__gpu_memory_l3_read_sqidi1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Memory13 :: GPU Time Elapsed */
#define acmgt2__memory13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory13 :: GPU Core Clocks */
#define acmgt2__memory13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory13 :: AVG GPU Core Frequency */
#define acmgt2__memory13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory13 :: AVG GPU Core Frequency */
#define acmgt2__memory13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory13 :: GPU MEMORY L3 READ SQIDI2 */
#define acmgt2__memory13__gpu_memory_l3_read_sqidi2__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Memory14 :: GPU Time Elapsed */
#define acmgt2__memory14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Memory14 :: GPU Core Clocks */
#define acmgt2__memory14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Memory14 :: AVG GPU Core Frequency */
#define acmgt2__memory14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Memory14 :: AVG GPU Core Frequency */
#define acmgt2__memory14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Memory14 :: GPU MEMORY L3 READ SQIDI3 */
#define acmgt2__memory14__gpu_memory_l3_read_sqidi3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Rasterizer1 :: GPU Time Elapsed */
#define acmgt2__rasterizer1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Rasterizer1 :: GPU Core Clocks */
#define acmgt2__rasterizer1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Rasterizer1 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Rasterizer1 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Rasterizer1 :: RASTERIZER SAMPLE OUTPUT */
#define acmgt2__rasterizer1__rasterizer_sample_output__read \
   bdw__render_basic__rasterized_pixels__read

/* Rasterizer1 :: RASTERIZER INPUT AVAILABLE SLICE0 */
#define acmgt2__rasterizer1__rasterizer_input_available_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Rasterizer1 :: RASTERIZER INPUT AVAILABLE SLICE1 */
#define acmgt2__rasterizer1__rasterizer_input_available_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Rasterizer1 :: RASTERIZER INPUT AVAILABLE SLICE2 */
#define acmgt2__rasterizer1__rasterizer_input_available_slice2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Rasterizer1 :: RASTERIZER INPUT AVAILABLE SLICE3 */
#define acmgt2__rasterizer1__rasterizer_input_available_slice3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Rasterizer1 :: RASTERIZER OUTPUT READY SLICE0 */
#define acmgt2__rasterizer1__rasterizer_output_ready_slice0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Rasterizer1 :: RASTERIZER OUTPUT READY SLICE1 */
#define acmgt2__rasterizer1__rasterizer_output_ready_slice1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Rasterizer1 :: RASTERIZER OUTPUT READY SLICE2 */
#define acmgt2__rasterizer1__rasterizer_output_ready_slice2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Rasterizer1 :: RASTERIZER OUTPUT READY SLICE3 */
#define acmgt2__rasterizer1__rasterizer_output_ready_slice3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Rasterizer2 :: GPU Time Elapsed */
#define acmgt2__rasterizer2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Rasterizer2 :: GPU Core Clocks */
#define acmgt2__rasterizer2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Rasterizer2 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Rasterizer2 :: AVG GPU Core Frequency */
#define acmgt2__rasterizer2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Rasterizer2 :: RASTERIZER TRANSACTION OUTPUT SLICE0 */
#define acmgt2__rasterizer2__rasterizer_transaction_output_slice0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Rasterizer2 :: RASTERIZER TRANSACTION OUTPUT SLICE1 */
#define acmgt2__rasterizer2__rasterizer_transaction_output_slice1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Rasterizer2 :: RASTERIZER TRANSACTION OUTPUT SLICE2 */
#define acmgt2__rasterizer2__rasterizer_transaction_output_slice2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Rasterizer2 :: RASTERIZER TRANSACTION OUTPUT SLICE3 */
#define acmgt2__rasterizer2__rasterizer_transaction_output_slice3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* RayTracing1 :: GPU Time Elapsed */
#define acmgt2__ray_tracing1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing1 :: GPU Core Clocks */
#define acmgt2__ray_tracing1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing1 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing1 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing1 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define acmgt2__ray_tracing1__rt_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing1 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0 */
#define acmgt2__ray_tracing1__rt_load_store_cache_write_from_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing1 :: RT TRAVERSAL INPUT RAY COUNT XECORE0 */
#define acmgt2__ray_tracing1__rt_traversal_input_ray_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing1 :: RT QUAD TEST RAY COUNT XECORE0 */
#define acmgt2__ray_tracing1__rt_quad_test_ray_count_xecore0__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing1 :: RT REQUEST COLLISION XECORE0 */
#define acmgt2__ray_tracing1__rt_request_collision_xecore0__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing1 :: RT INPUT MESSAGE RAY COUNT XECORE0 */
#define acmgt2__ray_tracing1__rt_input_message_ray_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing1 :: RT MESSAGE STALL COUNT XECORE0 */
#define acmgt2__ray_tracing1__rt_message_stall_count_xecore0__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing1 :: RT TRANSFORM RAY COUNT XECORE0 */
#define acmgt2__ray_tracing1__rt_transform_ray_count_xecore0__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing2 :: GPU Time Elapsed */
#define acmgt2__ray_tracing2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing2 :: GPU Core Clocks */
#define acmgt2__ray_tracing2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing2 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing2 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing2 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define acmgt2__ray_tracing2__rt_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing2 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1 */
#define acmgt2__ray_tracing2__rt_load_store_cache_write_from_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing2 :: RT TRAVERSAL INPUT RAY COUNT XECORE1 */
#define acmgt2__ray_tracing2__rt_traversal_input_ray_count_xecore1__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing2 :: RT QUAD TEST RAY COUNT XECORE1 */
#define acmgt2__ray_tracing2__rt_quad_test_ray_count_xecore1__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing2 :: RT REQUEST COLLISION XECORE1 */
#define acmgt2__ray_tracing2__rt_request_collision_xecore1__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing2 :: RT INPUT MESSAGE RAY COUNT XECORE1 */
#define acmgt2__ray_tracing2__rt_input_message_ray_count_xecore1__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing2 :: RT MESSAGE STALL COUNT XECORE1 */
#define acmgt2__ray_tracing2__rt_message_stall_count_xecore1__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing2 :: RT TRANSFORM RAY COUNT XECORE1 */
#define acmgt2__ray_tracing2__rt_transform_ray_count_xecore1__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing3 :: GPU Time Elapsed */
#define acmgt2__ray_tracing3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing3 :: GPU Core Clocks */
#define acmgt2__ray_tracing3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing3 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing3 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing3 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define acmgt2__ray_tracing3__rt_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing3 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2 */
#define acmgt2__ray_tracing3__rt_load_store_cache_write_from_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing3 :: RT TRAVERSAL INPUT RAY COUNT XECORE2 */
#define acmgt2__ray_tracing3__rt_traversal_input_ray_count_xecore2__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing3 :: RT QUAD TEST RAY COUNT XECORE2 */
#define acmgt2__ray_tracing3__rt_quad_test_ray_count_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing3 :: RT REQUEST COLLISION XECORE2 */
#define acmgt2__ray_tracing3__rt_request_collision_xecore2__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing3 :: RT INPUT MESSAGE RAY COUNT XECORE2 */
#define acmgt2__ray_tracing3__rt_input_message_ray_count_xecore2__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing3 :: RT MESSAGE STALL COUNT XECORE2 */
#define acmgt2__ray_tracing3__rt_message_stall_count_xecore2__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing3 :: RT TRANSFORM RAY COUNT XECORE2 */
#define acmgt2__ray_tracing3__rt_transform_ray_count_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing4 :: GPU Time Elapsed */
#define acmgt2__ray_tracing4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing4 :: GPU Core Clocks */
#define acmgt2__ray_tracing4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing4 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing4 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing4 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define acmgt2__ray_tracing4__rt_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing4 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3 */
#define acmgt2__ray_tracing4__rt_load_store_cache_write_from_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing4 :: RT TRAVERSAL INPUT RAY COUNT XECORE3 */
#define acmgt2__ray_tracing4__rt_traversal_input_ray_count_xecore3__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing4 :: RT QUAD TEST RAY COUNT XECORE3 */
#define acmgt2__ray_tracing4__rt_quad_test_ray_count_xecore3__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing4 :: RT REQUEST COLLISION XECORE3 */
#define acmgt2__ray_tracing4__rt_request_collision_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing4 :: RT INPUT MESSAGE RAY COUNT XECORE3 */
#define acmgt2__ray_tracing4__rt_input_message_ray_count_xecore3__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing4 :: RT MESSAGE STALL COUNT XECORE3 */
#define acmgt2__ray_tracing4__rt_message_stall_count_xecore3__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing4 :: RT TRANSFORM RAY COUNT XECORE3 */
#define acmgt2__ray_tracing4__rt_transform_ray_count_xecore3__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing5 :: GPU Time Elapsed */
#define acmgt2__ray_tracing5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing5 :: GPU Core Clocks */
#define acmgt2__ray_tracing5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing5 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing5 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing5 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4 */
#define acmgt2__ray_tracing5__rt_load_store_cache_read_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing5 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4 */
#define acmgt2__ray_tracing5__rt_load_store_cache_write_from_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing5 :: RT TRAVERSAL INPUT RAY COUNT XECORE4 */
#define acmgt2__ray_tracing5__rt_traversal_input_ray_count_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing5 :: RT QUAD TEST RAY COUNT XECORE4 */
#define acmgt2__ray_tracing5__rt_quad_test_ray_count_xecore4__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing5 :: RT REQUEST COLLISION XECORE4 */
#define acmgt2__ray_tracing5__rt_request_collision_xecore4__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing5 :: RT INPUT MESSAGE RAY COUNT XECORE4 */
#define acmgt2__ray_tracing5__rt_input_message_ray_count_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing5 :: RT MESSAGE STALL COUNT XECORE4 */
#define acmgt2__ray_tracing5__rt_message_stall_count_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing5 :: RT TRANSFORM RAY COUNT XECORE4 */
#define acmgt2__ray_tracing5__rt_transform_ray_count_xecore4__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing6 :: GPU Time Elapsed */
#define acmgt2__ray_tracing6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing6 :: GPU Core Clocks */
#define acmgt2__ray_tracing6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing6 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing6 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing6 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5 */
#define acmgt2__ray_tracing6__rt_load_store_cache_read_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing6 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5 */
#define acmgt2__ray_tracing6__rt_load_store_cache_write_from_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing6 :: RT TRAVERSAL INPUT RAY COUNT XECORE5 */
#define acmgt2__ray_tracing6__rt_traversal_input_ray_count_xecore5__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing6 :: RT QUAD TEST RAY COUNT XECORE5 */
#define acmgt2__ray_tracing6__rt_quad_test_ray_count_xecore5__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing6 :: RT REQUEST COLLISION XECORE5 */
#define acmgt2__ray_tracing6__rt_request_collision_xecore5__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing6 :: RT INPUT MESSAGE RAY COUNT XECORE5 */
#define acmgt2__ray_tracing6__rt_input_message_ray_count_xecore5__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing6 :: RT MESSAGE STALL COUNT XECORE5 */
#define acmgt2__ray_tracing6__rt_message_stall_count_xecore5__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing6 :: RT TRANSFORM RAY COUNT XECORE5 */
#define acmgt2__ray_tracing6__rt_transform_ray_count_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing7 :: GPU Time Elapsed */
#define acmgt2__ray_tracing7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing7 :: GPU Core Clocks */
#define acmgt2__ray_tracing7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing7 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing7 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing7 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6 */
#define acmgt2__ray_tracing7__rt_load_store_cache_read_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing7 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6 */
#define acmgt2__ray_tracing7__rt_load_store_cache_write_from_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing7 :: RT TRAVERSAL INPUT RAY COUNT XECORE6 */
#define acmgt2__ray_tracing7__rt_traversal_input_ray_count_xecore6__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing7 :: RT QUAD TEST RAY COUNT XECORE6 */
#define acmgt2__ray_tracing7__rt_quad_test_ray_count_xecore6__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing7 :: RT REQUEST COLLISION XECORE6 */
#define acmgt2__ray_tracing7__rt_request_collision_xecore6__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing7 :: RT INPUT MESSAGE RAY COUNT XECORE6 */
#define acmgt2__ray_tracing7__rt_input_message_ray_count_xecore6__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing7 :: RT MESSAGE STALL COUNT XECORE6 */
#define acmgt2__ray_tracing7__rt_message_stall_count_xecore6__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing7 :: RT TRANSFORM RAY COUNT XECORE6 */
#define acmgt2__ray_tracing7__rt_transform_ray_count_xecore6__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing8 :: GPU Time Elapsed */
#define acmgt2__ray_tracing8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing8 :: GPU Core Clocks */
#define acmgt2__ray_tracing8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing8 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing8 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing8 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7 */
#define acmgt2__ray_tracing8__rt_load_store_cache_read_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing8 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7 */
#define acmgt2__ray_tracing8__rt_load_store_cache_write_from_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing8 :: RT TRAVERSAL INPUT RAY COUNT XECORE7 */
#define acmgt2__ray_tracing8__rt_traversal_input_ray_count_xecore7__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing8 :: RT QUAD TEST RAY COUNT XECORE7 */
#define acmgt2__ray_tracing8__rt_quad_test_ray_count_xecore7__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing8 :: RT REQUEST COLLISION XECORE7 */
#define acmgt2__ray_tracing8__rt_request_collision_xecore7__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing8 :: RT INPUT MESSAGE RAY COUNT XECORE7 */
#define acmgt2__ray_tracing8__rt_input_message_ray_count_xecore7__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing8 :: RT MESSAGE STALL COUNT XECORE7 */
#define acmgt2__ray_tracing8__rt_message_stall_count_xecore7__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing8 :: RT TRANSFORM RAY COUNT XECORE7 */
#define acmgt2__ray_tracing8__rt_transform_ray_count_xecore7__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing9 :: GPU Time Elapsed */
#define acmgt2__ray_tracing9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing9 :: GPU Core Clocks */
#define acmgt2__ray_tracing9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing9 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing9 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing9 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE8 */
#define acmgt2__ray_tracing9__rt_load_store_cache_read_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing9 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE8 */
#define acmgt2__ray_tracing9__rt_load_store_cache_write_from_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing9 :: RT TRAVERSAL INPUT RAY COUNT XECORE8 */
#define acmgt2__ray_tracing9__rt_traversal_input_ray_count_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing9 :: RT QUAD TEST RAY COUNT XECORE8 */
#define acmgt2__ray_tracing9__rt_quad_test_ray_count_xecore8__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing9 :: RT REQUEST COLLISION XECORE8 */
#define acmgt2__ray_tracing9__rt_request_collision_xecore8__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing9 :: RT INPUT MESSAGE RAY COUNT XECORE8 */
#define acmgt2__ray_tracing9__rt_input_message_ray_count_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing9 :: RT MESSAGE STALL COUNT XECORE8 */
#define acmgt2__ray_tracing9__rt_message_stall_count_xecore8__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing9 :: RT TRANSFORM RAY COUNT XECORE8 */
#define acmgt2__ray_tracing9__rt_transform_ray_count_xecore8__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing10 :: GPU Time Elapsed */
#define acmgt2__ray_tracing10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing10 :: GPU Core Clocks */
#define acmgt2__ray_tracing10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing10 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing10 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing10 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE9 */
#define acmgt2__ray_tracing10__rt_load_store_cache_read_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing10 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE9 */
#define acmgt2__ray_tracing10__rt_load_store_cache_write_from_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing10 :: RT TRAVERSAL INPUT RAY COUNT XECORE9 */
#define acmgt2__ray_tracing10__rt_traversal_input_ray_count_xecore9__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing10 :: RT QUAD TEST RAY COUNT XECORE9 */
#define acmgt2__ray_tracing10__rt_quad_test_ray_count_xecore9__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing10 :: RT REQUEST COLLISION XECORE9 */
#define acmgt2__ray_tracing10__rt_request_collision_xecore9__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing10 :: RT INPUT MESSAGE RAY COUNT XECORE9 */
#define acmgt2__ray_tracing10__rt_input_message_ray_count_xecore9__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing10 :: RT MESSAGE STALL COUNT XECORE9 */
#define acmgt2__ray_tracing10__rt_message_stall_count_xecore9__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing10 :: RT TRANSFORM RAY COUNT XECORE9 */
#define acmgt2__ray_tracing10__rt_transform_ray_count_xecore9__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing11 :: GPU Time Elapsed */
#define acmgt2__ray_tracing11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing11 :: GPU Core Clocks */
#define acmgt2__ray_tracing11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing11 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing11 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing11 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE10 */
#define acmgt2__ray_tracing11__rt_load_store_cache_read_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing11 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE10 */
#define acmgt2__ray_tracing11__rt_load_store_cache_write_from_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing11 :: RT TRAVERSAL INPUT RAY COUNT XECORE10 */
#define acmgt2__ray_tracing11__rt_traversal_input_ray_count_xecore10__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing11 :: RT QUAD TEST RAY COUNT XECORE10 */
#define acmgt2__ray_tracing11__rt_quad_test_ray_count_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing11 :: RT REQUEST COLLISION XECORE10 */
#define acmgt2__ray_tracing11__rt_request_collision_xecore10__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing11 :: RT INPUT MESSAGE RAY COUNT XECORE10 */
#define acmgt2__ray_tracing11__rt_input_message_ray_count_xecore10__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing11 :: RT MESSAGE STALL COUNT XECORE10 */
#define acmgt2__ray_tracing11__rt_message_stall_count_xecore10__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing11 :: RT TRANSFORM RAY COUNT XECORE10 */
#define acmgt2__ray_tracing11__rt_transform_ray_count_xecore10__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing12 :: GPU Time Elapsed */
#define acmgt2__ray_tracing12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing12 :: GPU Core Clocks */
#define acmgt2__ray_tracing12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing12 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing12 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing12 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE11 */
#define acmgt2__ray_tracing12__rt_load_store_cache_read_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing12 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE11 */
#define acmgt2__ray_tracing12__rt_load_store_cache_write_from_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing12 :: RT TRAVERSAL INPUT RAY COUNT XECORE11 */
#define acmgt2__ray_tracing12__rt_traversal_input_ray_count_xecore11__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing12 :: RT QUAD TEST RAY COUNT XECORE11 */
#define acmgt2__ray_tracing12__rt_quad_test_ray_count_xecore11__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing12 :: RT REQUEST COLLISION XECORE11 */
#define acmgt2__ray_tracing12__rt_request_collision_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing12 :: RT INPUT MESSAGE RAY COUNT XECORE11 */
#define acmgt2__ray_tracing12__rt_input_message_ray_count_xecore11__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing12 :: RT MESSAGE STALL COUNT XECORE11 */
#define acmgt2__ray_tracing12__rt_message_stall_count_xecore11__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing12 :: RT TRANSFORM RAY COUNT XECORE11 */
#define acmgt2__ray_tracing12__rt_transform_ray_count_xecore11__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing13 :: GPU Time Elapsed */
#define acmgt2__ray_tracing13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing13 :: GPU Core Clocks */
#define acmgt2__ray_tracing13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing13 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing13 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing13 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE12 */
#define acmgt2__ray_tracing13__rt_load_store_cache_read_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing13 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE12 */
#define acmgt2__ray_tracing13__rt_load_store_cache_write_from_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing13 :: RT TRAVERSAL INPUT RAY COUNT XECORE12 */
#define acmgt2__ray_tracing13__rt_traversal_input_ray_count_xecore12__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing13 :: RT QUAD TEST RAY COUNT XECORE12 */
#define acmgt2__ray_tracing13__rt_quad_test_ray_count_xecore12__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing13 :: RT REQUEST COLLISION XECORE12 */
#define acmgt2__ray_tracing13__rt_request_collision_xecore12__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing13 :: RT INPUT MESSAGE RAY COUNT XECORE12 */
#define acmgt2__ray_tracing13__rt_input_message_ray_count_xecore12__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing13 :: RT MESSAGE STALL COUNT XECORE12 */
#define acmgt2__ray_tracing13__rt_message_stall_count_xecore12__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing13 :: RT TRANSFORM RAY COUNT XECORE12 */
#define acmgt2__ray_tracing13__rt_transform_ray_count_xecore12__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing14 :: GPU Time Elapsed */
#define acmgt2__ray_tracing14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing14 :: GPU Core Clocks */
#define acmgt2__ray_tracing14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing14 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing14 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing14 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE13 */
#define acmgt2__ray_tracing14__rt_load_store_cache_read_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing14 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE13 */
#define acmgt2__ray_tracing14__rt_load_store_cache_write_from_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing14 :: RT TRAVERSAL INPUT RAY COUNT XECORE13 */
#define acmgt2__ray_tracing14__rt_traversal_input_ray_count_xecore13__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing14 :: RT QUAD TEST RAY COUNT XECORE13 */
#define acmgt2__ray_tracing14__rt_quad_test_ray_count_xecore13__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing14 :: RT REQUEST COLLISION XECORE13 */
#define acmgt2__ray_tracing14__rt_request_collision_xecore13__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing14 :: RT INPUT MESSAGE RAY COUNT XECORE13 */
#define acmgt2__ray_tracing14__rt_input_message_ray_count_xecore13__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing14 :: RT MESSAGE STALL COUNT XECORE13 */
#define acmgt2__ray_tracing14__rt_message_stall_count_xecore13__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing14 :: RT TRANSFORM RAY COUNT XECORE13 */
#define acmgt2__ray_tracing14__rt_transform_ray_count_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing15 :: GPU Time Elapsed */
#define acmgt2__ray_tracing15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing15 :: GPU Core Clocks */
#define acmgt2__ray_tracing15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing15 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing15 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing15 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE14 */
#define acmgt2__ray_tracing15__rt_load_store_cache_read_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing15 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE14 */
#define acmgt2__ray_tracing15__rt_load_store_cache_write_from_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing15 :: RT TRAVERSAL INPUT RAY COUNT XECORE14 */
#define acmgt2__ray_tracing15__rt_traversal_input_ray_count_xecore14__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing15 :: RT QUAD TEST RAY COUNT XECORE14 */
#define acmgt2__ray_tracing15__rt_quad_test_ray_count_xecore14__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing15 :: RT REQUEST COLLISION XECORE14 */
#define acmgt2__ray_tracing15__rt_request_collision_xecore14__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing15 :: RT INPUT MESSAGE RAY COUNT XECORE14 */
#define acmgt2__ray_tracing15__rt_input_message_ray_count_xecore14__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing15 :: RT MESSAGE STALL COUNT XECORE14 */
#define acmgt2__ray_tracing15__rt_message_stall_count_xecore14__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing15 :: RT TRANSFORM RAY COUNT XECORE14 */
#define acmgt2__ray_tracing15__rt_transform_ray_count_xecore14__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing16 :: GPU Time Elapsed */
#define acmgt2__ray_tracing16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing16 :: GPU Core Clocks */
#define acmgt2__ray_tracing16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing16 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing16 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing16 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE15 */
#define acmgt2__ray_tracing16__rt_load_store_cache_read_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing16 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE15 */
#define acmgt2__ray_tracing16__rt_load_store_cache_write_from_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing16 :: RT TRAVERSAL INPUT RAY COUNT XECORE15 */
#define acmgt2__ray_tracing16__rt_traversal_input_ray_count_xecore15__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing16 :: RT QUAD TEST RAY COUNT XECORE15 */
#define acmgt2__ray_tracing16__rt_quad_test_ray_count_xecore15__read \
   hsw__memory_reads__gti_memory_reads__read

/* RayTracing16 :: RT REQUEST COLLISION XECORE15 */
#define acmgt2__ray_tracing16__rt_request_collision_xecore15__read \
   hsw__compute_extended__typed_atomics0__read

/* RayTracing16 :: RT INPUT MESSAGE RAY COUNT XECORE15 */
#define acmgt2__ray_tracing16__rt_input_message_ray_count_xecore15__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* RayTracing16 :: RT MESSAGE STALL COUNT XECORE15 */
#define acmgt2__ray_tracing16__rt_message_stall_count_xecore15__read \
   bdw__render_pipe_profile__so_stall__read

/* RayTracing16 :: RT TRANSFORM RAY COUNT XECORE15 */
#define acmgt2__ray_tracing16__rt_transform_ray_count_xecore15__read \
   hsw__render_basic__gpu_core_clocks__read

/* RayTracing17 :: GPU Time Elapsed */
#define acmgt2__ray_tracing17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing17 :: GPU Core Clocks */
#define acmgt2__ray_tracing17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing17 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing17 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing17 :: RT INSTANCE NODE RAY COUNT XECORE0 */
#define acmgt2__ray_tracing17__rt_instance_node_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing17 :: RT INTERNAL NODE RAY COUNT XECORE0 */
#define acmgt2__ray_tracing17__rt_internal_node_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing17 :: RT TRAVERSAL STEP RAY COUNT XECORE0 */
#define acmgt2__ray_tracing17__rt_traversal_step_ray_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing18 :: GPU Time Elapsed */
#define acmgt2__ray_tracing18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing18 :: GPU Core Clocks */
#define acmgt2__ray_tracing18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing18 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing18 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing18 :: RT INSTANCE NODE RAY COUNT XECORE1 */
#define acmgt2__ray_tracing18__rt_instance_node_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing18 :: RT INTERNAL NODE RAY COUNT XECORE1 */
#define acmgt2__ray_tracing18__rt_internal_node_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing18 :: RT TRAVERSAL STEP RAY COUNT XECORE1 */
#define acmgt2__ray_tracing18__rt_traversal_step_ray_count_xecore1__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing19 :: GPU Time Elapsed */
#define acmgt2__ray_tracing19__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing19 :: GPU Core Clocks */
#define acmgt2__ray_tracing19__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing19 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing19__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing19 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing19__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing19 :: RT INSTANCE NODE RAY COUNT XECORE2 */
#define acmgt2__ray_tracing19__rt_instance_node_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing19 :: RT INTERNAL NODE RAY COUNT XECORE2 */
#define acmgt2__ray_tracing19__rt_internal_node_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing19 :: RT TRAVERSAL STEP RAY COUNT XECORE2 */
#define acmgt2__ray_tracing19__rt_traversal_step_ray_count_xecore2__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing20 :: GPU Time Elapsed */
#define acmgt2__ray_tracing20__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing20 :: GPU Core Clocks */
#define acmgt2__ray_tracing20__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing20 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing20__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing20 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing20__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing20 :: RT INSTANCE NODE RAY COUNT XECORE3 */
#define acmgt2__ray_tracing20__rt_instance_node_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing20 :: RT INTERNAL NODE RAY COUNT XECORE3 */
#define acmgt2__ray_tracing20__rt_internal_node_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing20 :: RT TRAVERSAL STEP RAY COUNT XECORE3 */
#define acmgt2__ray_tracing20__rt_traversal_step_ray_count_xecore3__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing21 :: GPU Time Elapsed */
#define acmgt2__ray_tracing21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing21 :: GPU Core Clocks */
#define acmgt2__ray_tracing21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing21 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing21 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing21 :: RT INSTANCE NODE RAY COUNT XECORE4 */
#define acmgt2__ray_tracing21__rt_instance_node_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing21 :: RT INTERNAL NODE RAY COUNT XECORE4 */
#define acmgt2__ray_tracing21__rt_internal_node_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing21 :: RT TRAVERSAL STEP RAY COUNT XECORE4 */
#define acmgt2__ray_tracing21__rt_traversal_step_ray_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing22 :: GPU Time Elapsed */
#define acmgt2__ray_tracing22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing22 :: GPU Core Clocks */
#define acmgt2__ray_tracing22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing22 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing22 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing22 :: RT INSTANCE NODE RAY COUNT XECORE5 */
#define acmgt2__ray_tracing22__rt_instance_node_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing22 :: RT INTERNAL NODE RAY COUNT XECORE5 */
#define acmgt2__ray_tracing22__rt_internal_node_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing22 :: RT TRAVERSAL STEP RAY COUNT XECORE5 */
#define acmgt2__ray_tracing22__rt_traversal_step_ray_count_xecore5__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing23 :: GPU Time Elapsed */
#define acmgt2__ray_tracing23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing23 :: GPU Core Clocks */
#define acmgt2__ray_tracing23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing23 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing23 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing23 :: RT INSTANCE NODE RAY COUNT XECORE6 */
#define acmgt2__ray_tracing23__rt_instance_node_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing23 :: RT INTERNAL NODE RAY COUNT XECORE6 */
#define acmgt2__ray_tracing23__rt_internal_node_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing23 :: RT TRAVERSAL STEP RAY COUNT XECORE6 */
#define acmgt2__ray_tracing23__rt_traversal_step_ray_count_xecore6__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing24 :: GPU Time Elapsed */
#define acmgt2__ray_tracing24__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing24 :: GPU Core Clocks */
#define acmgt2__ray_tracing24__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing24 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing24__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing24 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing24__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing24 :: RT INSTANCE NODE RAY COUNT XECORE7 */
#define acmgt2__ray_tracing24__rt_instance_node_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing24 :: RT INTERNAL NODE RAY COUNT XECORE7 */
#define acmgt2__ray_tracing24__rt_internal_node_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing24 :: RT TRAVERSAL STEP RAY COUNT XECORE7 */
#define acmgt2__ray_tracing24__rt_traversal_step_ray_count_xecore7__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing25 :: GPU Time Elapsed */
#define acmgt2__ray_tracing25__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing25 :: GPU Core Clocks */
#define acmgt2__ray_tracing25__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing25 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing25__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing25 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing25__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing25 :: RT INSTANCE NODE RAY COUNT XECORE8 */
#define acmgt2__ray_tracing25__rt_instance_node_ray_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing25 :: RT INTERNAL NODE RAY COUNT XECORE8 */
#define acmgt2__ray_tracing25__rt_internal_node_ray_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing25 :: RT TRAVERSAL STEP RAY COUNT XECORE8 */
#define acmgt2__ray_tracing25__rt_traversal_step_ray_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing26 :: GPU Time Elapsed */
#define acmgt2__ray_tracing26__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing26 :: GPU Core Clocks */
#define acmgt2__ray_tracing26__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing26 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing26__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing26 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing26__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing26 :: RT INSTANCE NODE RAY COUNT XECORE9 */
#define acmgt2__ray_tracing26__rt_instance_node_ray_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing26 :: RT INTERNAL NODE RAY COUNT XECORE9 */
#define acmgt2__ray_tracing26__rt_internal_node_ray_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing26 :: RT TRAVERSAL STEP RAY COUNT XECORE9 */
#define acmgt2__ray_tracing26__rt_traversal_step_ray_count_xecore9__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing27 :: GPU Time Elapsed */
#define acmgt2__ray_tracing27__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing27 :: GPU Core Clocks */
#define acmgt2__ray_tracing27__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing27 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing27__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing27 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing27__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing27 :: RT INSTANCE NODE RAY COUNT XECORE10 */
#define acmgt2__ray_tracing27__rt_instance_node_ray_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing27 :: RT INTERNAL NODE RAY COUNT XECORE10 */
#define acmgt2__ray_tracing27__rt_internal_node_ray_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing27 :: RT TRAVERSAL STEP RAY COUNT XECORE10 */
#define acmgt2__ray_tracing27__rt_traversal_step_ray_count_xecore10__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing28 :: GPU Time Elapsed */
#define acmgt2__ray_tracing28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing28 :: GPU Core Clocks */
#define acmgt2__ray_tracing28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing28 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing28 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing28 :: RT INSTANCE NODE RAY COUNT XECORE11 */
#define acmgt2__ray_tracing28__rt_instance_node_ray_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing28 :: RT INTERNAL NODE RAY COUNT XECORE11 */
#define acmgt2__ray_tracing28__rt_internal_node_ray_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing28 :: RT TRAVERSAL STEP RAY COUNT XECORE11 */
#define acmgt2__ray_tracing28__rt_traversal_step_ray_count_xecore11__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing29 :: GPU Time Elapsed */
#define acmgt2__ray_tracing29__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing29 :: GPU Core Clocks */
#define acmgt2__ray_tracing29__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing29 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing29__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing29 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing29__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing29 :: RT INSTANCE NODE RAY COUNT XECORE12 */
#define acmgt2__ray_tracing29__rt_instance_node_ray_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing29 :: RT INTERNAL NODE RAY COUNT XECORE12 */
#define acmgt2__ray_tracing29__rt_internal_node_ray_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing29 :: RT TRAVERSAL STEP RAY COUNT XECORE12 */
#define acmgt2__ray_tracing29__rt_traversal_step_ray_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing30 :: GPU Time Elapsed */
#define acmgt2__ray_tracing30__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing30 :: GPU Core Clocks */
#define acmgt2__ray_tracing30__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing30 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing30__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing30 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing30__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing30 :: RT INSTANCE NODE RAY COUNT XECORE13 */
#define acmgt2__ray_tracing30__rt_instance_node_ray_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing30 :: RT INTERNAL NODE RAY COUNT XECORE13 */
#define acmgt2__ray_tracing30__rt_internal_node_ray_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing30 :: RT TRAVERSAL STEP RAY COUNT XECORE13 */
#define acmgt2__ray_tracing30__rt_traversal_step_ray_count_xecore13__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing31 :: GPU Time Elapsed */
#define acmgt2__ray_tracing31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing31 :: GPU Core Clocks */
#define acmgt2__ray_tracing31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing31 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing31 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing31 :: RT INSTANCE NODE RAY COUNT XECORE14 */
#define acmgt2__ray_tracing31__rt_instance_node_ray_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing31 :: RT INTERNAL NODE RAY COUNT XECORE14 */
#define acmgt2__ray_tracing31__rt_internal_node_ray_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing31 :: RT TRAVERSAL STEP RAY COUNT XECORE14 */
#define acmgt2__ray_tracing31__rt_traversal_step_ray_count_xecore14__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing32 :: GPU Time Elapsed */
#define acmgt2__ray_tracing32__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing32 :: GPU Core Clocks */
#define acmgt2__ray_tracing32__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing32 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing32__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing32 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing32__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing32 :: RT INSTANCE NODE RAY COUNT XECORE15 */
#define acmgt2__ray_tracing32__rt_instance_node_ray_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing32 :: RT INTERNAL NODE RAY COUNT XECORE15 */
#define acmgt2__ray_tracing32__rt_internal_node_ray_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing32 :: RT TRAVERSAL STEP RAY COUNT XECORE15 */
#define acmgt2__ray_tracing32__rt_traversal_step_ray_count_xecore15__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing33 :: GPU Time Elapsed */
#define acmgt2__ray_tracing33__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing33 :: GPU Core Clocks */
#define acmgt2__ray_tracing33__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing33 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing33__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing33 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing33__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing33 :: RT QUAD LEAF RAY COUNT XECORE0 */
#define acmgt2__ray_tracing33__rt_quad_leaf_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing33 :: RT PROCEDURAL NODE RAY COUNT XECORE0 */
#define acmgt2__ray_tracing33__rt_procedural_node_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing34 :: GPU Time Elapsed */
#define acmgt2__ray_tracing34__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing34 :: GPU Core Clocks */
#define acmgt2__ray_tracing34__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing34 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing34__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing34 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing34__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing34 :: RT QUAD LEAF RAY COUNT XECORE1 */
#define acmgt2__ray_tracing34__rt_quad_leaf_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing34 :: RT PROCEDURAL NODE RAY COUNT XECORE1 */
#define acmgt2__ray_tracing34__rt_procedural_node_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing35 :: GPU Time Elapsed */
#define acmgt2__ray_tracing35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing35 :: GPU Core Clocks */
#define acmgt2__ray_tracing35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing35 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing35 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing35 :: RT QUAD LEAF RAY COUNT XECORE2 */
#define acmgt2__ray_tracing35__rt_quad_leaf_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing35 :: RT PROCEDURAL NODE RAY COUNT XECORE2 */
#define acmgt2__ray_tracing35__rt_procedural_node_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing36 :: GPU Time Elapsed */
#define acmgt2__ray_tracing36__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing36 :: GPU Core Clocks */
#define acmgt2__ray_tracing36__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing36 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing36__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing36 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing36__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing36 :: RT QUAD LEAF RAY COUNT XECORE3 */
#define acmgt2__ray_tracing36__rt_quad_leaf_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing36 :: RT PROCEDURAL NODE RAY COUNT XECORE3 */
#define acmgt2__ray_tracing36__rt_procedural_node_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing37 :: GPU Time Elapsed */
#define acmgt2__ray_tracing37__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing37 :: GPU Core Clocks */
#define acmgt2__ray_tracing37__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing37 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing37__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing37 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing37__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing37 :: RT QUAD LEAF RAY COUNT XECORE4 */
#define acmgt2__ray_tracing37__rt_quad_leaf_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing37 :: RT PROCEDURAL NODE RAY COUNT XECORE4 */
#define acmgt2__ray_tracing37__rt_procedural_node_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing38 :: GPU Time Elapsed */
#define acmgt2__ray_tracing38__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing38 :: GPU Core Clocks */
#define acmgt2__ray_tracing38__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing38 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing38__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing38 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing38__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing38 :: RT QUAD LEAF RAY COUNT XECORE5 */
#define acmgt2__ray_tracing38__rt_quad_leaf_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing38 :: RT PROCEDURAL NODE RAY COUNT XECORE5 */
#define acmgt2__ray_tracing38__rt_procedural_node_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing39 :: GPU Time Elapsed */
#define acmgt2__ray_tracing39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing39 :: GPU Core Clocks */
#define acmgt2__ray_tracing39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing39 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing39 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing39 :: RT QUAD LEAF RAY COUNT XECORE6 */
#define acmgt2__ray_tracing39__rt_quad_leaf_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing39 :: RT PROCEDURAL NODE RAY COUNT XECORE6 */
#define acmgt2__ray_tracing39__rt_procedural_node_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing40 :: GPU Time Elapsed */
#define acmgt2__ray_tracing40__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing40 :: GPU Core Clocks */
#define acmgt2__ray_tracing40__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing40 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing40__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing40 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing40__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing40 :: RT QUAD LEAF RAY COUNT XECORE7 */
#define acmgt2__ray_tracing40__rt_quad_leaf_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing40 :: RT PROCEDURAL NODE RAY COUNT XECORE7 */
#define acmgt2__ray_tracing40__rt_procedural_node_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing41 :: GPU Time Elapsed */
#define acmgt2__ray_tracing41__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing41 :: GPU Core Clocks */
#define acmgt2__ray_tracing41__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing41 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing41__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing41 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing41__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing41 :: RT QUAD LEAF RAY COUNT XECORE8 */
#define acmgt2__ray_tracing41__rt_quad_leaf_ray_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing41 :: RT PROCEDURAL NODE RAY COUNT XECORE8 */
#define acmgt2__ray_tracing41__rt_procedural_node_ray_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing42 :: GPU Time Elapsed */
#define acmgt2__ray_tracing42__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing42 :: GPU Core Clocks */
#define acmgt2__ray_tracing42__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing42 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing42__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing42 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing42__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing42 :: RT QUAD LEAF RAY COUNT XECORE9 */
#define acmgt2__ray_tracing42__rt_quad_leaf_ray_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing42 :: RT PROCEDURAL NODE RAY COUNT XECORE9 */
#define acmgt2__ray_tracing42__rt_procedural_node_ray_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing43 :: GPU Time Elapsed */
#define acmgt2__ray_tracing43__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing43 :: GPU Core Clocks */
#define acmgt2__ray_tracing43__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing43 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing43__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing43 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing43__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing43 :: RT QUAD LEAF RAY COUNT XECORE10 */
#define acmgt2__ray_tracing43__rt_quad_leaf_ray_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing43 :: RT PROCEDURAL NODE RAY COUNT XECORE10 */
#define acmgt2__ray_tracing43__rt_procedural_node_ray_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing44 :: GPU Time Elapsed */
#define acmgt2__ray_tracing44__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing44 :: GPU Core Clocks */
#define acmgt2__ray_tracing44__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing44 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing44__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing44 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing44__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing44 :: RT QUAD LEAF RAY COUNT XECORE11 */
#define acmgt2__ray_tracing44__rt_quad_leaf_ray_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing44 :: RT PROCEDURAL NODE RAY COUNT XECORE11 */
#define acmgt2__ray_tracing44__rt_procedural_node_ray_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing45 :: GPU Time Elapsed */
#define acmgt2__ray_tracing45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing45 :: GPU Core Clocks */
#define acmgt2__ray_tracing45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing45 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing45 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing45 :: RT QUAD LEAF RAY COUNT XECORE12 */
#define acmgt2__ray_tracing45__rt_quad_leaf_ray_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing45 :: RT PROCEDURAL NODE RAY COUNT XECORE12 */
#define acmgt2__ray_tracing45__rt_procedural_node_ray_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing46 :: GPU Time Elapsed */
#define acmgt2__ray_tracing46__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing46 :: GPU Core Clocks */
#define acmgt2__ray_tracing46__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing46 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing46__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing46 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing46__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing46 :: RT QUAD LEAF RAY COUNT XECORE13 */
#define acmgt2__ray_tracing46__rt_quad_leaf_ray_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing46 :: RT PROCEDURAL NODE RAY COUNT XECORE13 */
#define acmgt2__ray_tracing46__rt_procedural_node_ray_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing47 :: GPU Time Elapsed */
#define acmgt2__ray_tracing47__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing47 :: GPU Core Clocks */
#define acmgt2__ray_tracing47__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing47 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing47__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing47 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing47__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing47 :: RT QUAD LEAF RAY COUNT XECORE14 */
#define acmgt2__ray_tracing47__rt_quad_leaf_ray_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing47 :: RT PROCEDURAL NODE RAY COUNT XECORE14 */
#define acmgt2__ray_tracing47__rt_procedural_node_ray_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing48 :: GPU Time Elapsed */
#define acmgt2__ray_tracing48__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing48 :: GPU Core Clocks */
#define acmgt2__ray_tracing48__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing48 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing48__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing48 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing48__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing48 :: RT QUAD LEAF RAY COUNT XECORE15 */
#define acmgt2__ray_tracing48__rt_quad_leaf_ray_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* RayTracing48 :: RT PROCEDURAL NODE RAY COUNT XECORE15 */
#define acmgt2__ray_tracing48__rt_procedural_node_ray_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* RayTracing49 :: GPU Time Elapsed */
#define acmgt2__ray_tracing49__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing49 :: GPU Core Clocks */
#define acmgt2__ray_tracing49__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing49 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing49__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing49 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing49__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing49 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE0 */
#define acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing49 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE1 */
#define acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing49 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE2 */
#define acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing49 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE3 */
#define acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing50 :: GPU Time Elapsed */
#define acmgt2__ray_tracing50__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing50 :: GPU Core Clocks */
#define acmgt2__ray_tracing50__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing50 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing50__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing50 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing50__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing50 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE4 */
#define acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing50 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE5 */
#define acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing50 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE6 */
#define acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing50 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE7 */
#define acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing51 :: GPU Time Elapsed */
#define acmgt2__ray_tracing51__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing51 :: GPU Core Clocks */
#define acmgt2__ray_tracing51__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing51 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing51__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing51 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing51__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing51 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE8 */
#define acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing51 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE9 */
#define acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing51 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE10 */
#define acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing51 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE11 */
#define acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing52 :: GPU Time Elapsed */
#define acmgt2__ray_tracing52__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing52 :: GPU Core Clocks */
#define acmgt2__ray_tracing52__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing52 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing52__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing52 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing52__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing52 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE12 */
#define acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing52 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE13 */
#define acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing52 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE14 */
#define acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing52 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE15 */
#define acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing53 :: GPU Time Elapsed */
#define acmgt2__ray_tracing53__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing53 :: GPU Core Clocks */
#define acmgt2__ray_tracing53__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing53 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing53__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing53 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing53__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing53 :: RT ANY HIT THREAD RAY DISPATCH XECORE0 */
#define acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing53 :: RT ANY HIT THREAD RAY DISPATCH XECORE1 */
#define acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing53 :: RT ANY HIT THREAD RAY DISPATCH XECORE2 */
#define acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing53 :: RT ANY HIT THREAD RAY DISPATCH XECORE3 */
#define acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing54 :: GPU Time Elapsed */
#define acmgt2__ray_tracing54__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing54 :: GPU Core Clocks */
#define acmgt2__ray_tracing54__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing54 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing54__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing54 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing54__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing54 :: RT ANY HIT THREAD RAY DISPATCH XECORE4 */
#define acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing54 :: RT ANY HIT THREAD RAY DISPATCH XECORE5 */
#define acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing54 :: RT ANY HIT THREAD RAY DISPATCH XECORE6 */
#define acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing54 :: RT ANY HIT THREAD RAY DISPATCH XECORE7 */
#define acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing55 :: GPU Time Elapsed */
#define acmgt2__ray_tracing55__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing55 :: GPU Core Clocks */
#define acmgt2__ray_tracing55__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing55 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing55__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing55 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing55__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing55 :: RT ANY HIT THREAD RAY DISPATCH XECORE8 */
#define acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing55 :: RT ANY HIT THREAD RAY DISPATCH XECORE9 */
#define acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing55 :: RT ANY HIT THREAD RAY DISPATCH XECORE10 */
#define acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing55 :: RT ANY HIT THREAD RAY DISPATCH XECORE11 */
#define acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing56 :: GPU Time Elapsed */
#define acmgt2__ray_tracing56__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing56 :: GPU Core Clocks */
#define acmgt2__ray_tracing56__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing56 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing56__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing56 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing56__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing56 :: RT ANY HIT THREAD RAY DISPATCH XECORE12 */
#define acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing56 :: RT ANY HIT THREAD RAY DISPATCH XECORE13 */
#define acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing56 :: RT ANY HIT THREAD RAY DISPATCH XECORE14 */
#define acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing56 :: RT ANY HIT THREAD RAY DISPATCH XECORE15 */
#define acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing57 :: GPU Time Elapsed */
#define acmgt2__ray_tracing57__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing57 :: GPU Core Clocks */
#define acmgt2__ray_tracing57__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing57 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing57__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing57 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing57__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing57 :: RT CALLABLE THREAD RAY DISPATCH XECORE0 */
#define acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing57 :: RT CALLABLE THREAD RAY DISPATCH XECORE1 */
#define acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing57 :: RT CALLABLE THREAD RAY DISPATCH XECORE2 */
#define acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing57 :: RT CALLABLE THREAD RAY DISPATCH XECORE3 */
#define acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing58 :: GPU Time Elapsed */
#define acmgt2__ray_tracing58__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing58 :: GPU Core Clocks */
#define acmgt2__ray_tracing58__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing58 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing58__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing58 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing58__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing58 :: RT CALLABLE THREAD RAY DISPATCH XECORE4 */
#define acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing58 :: RT CALLABLE THREAD RAY DISPATCH XECORE5 */
#define acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing58 :: RT CALLABLE THREAD RAY DISPATCH XECORE6 */
#define acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing58 :: RT CALLABLE THREAD RAY DISPATCH XECORE7 */
#define acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing59 :: GPU Time Elapsed */
#define acmgt2__ray_tracing59__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing59 :: GPU Core Clocks */
#define acmgt2__ray_tracing59__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing59 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing59__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing59 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing59__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing59 :: RT CALLABLE THREAD RAY DISPATCH XECORE8 */
#define acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing59 :: RT CALLABLE THREAD RAY DISPATCH XECORE9 */
#define acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing59 :: RT CALLABLE THREAD RAY DISPATCH XECORE10 */
#define acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing59 :: RT CALLABLE THREAD RAY DISPATCH XECORE11 */
#define acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing60 :: GPU Time Elapsed */
#define acmgt2__ray_tracing60__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing60 :: GPU Core Clocks */
#define acmgt2__ray_tracing60__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing60 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing60__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing60 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing60__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing60 :: RT CALLABLE THREAD RAY DISPATCH XECORE12 */
#define acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing60 :: RT CALLABLE THREAD RAY DISPATCH XECORE13 */
#define acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing60 :: RT CALLABLE THREAD RAY DISPATCH XECORE14 */
#define acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing60 :: RT CALLABLE THREAD RAY DISPATCH XECORE15 */
#define acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing61 :: GPU Time Elapsed */
#define acmgt2__ray_tracing61__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing61 :: GPU Core Clocks */
#define acmgt2__ray_tracing61__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing61 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing61__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing61 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing61__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing61 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE0 */
#define acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing61 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE1 */
#define acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing61 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE2 */
#define acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing61 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE3 */
#define acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing62 :: GPU Time Elapsed */
#define acmgt2__ray_tracing62__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing62 :: GPU Core Clocks */
#define acmgt2__ray_tracing62__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing62 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing62__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing62 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing62__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing62 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE4 */
#define acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing62 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE5 */
#define acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing62 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE6 */
#define acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing62 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE7 */
#define acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing63 :: GPU Time Elapsed */
#define acmgt2__ray_tracing63__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing63 :: GPU Core Clocks */
#define acmgt2__ray_tracing63__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing63 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing63__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing63 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing63__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing63 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE8 */
#define acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing63 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE9 */
#define acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing63 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE10 */
#define acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing63 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE11 */
#define acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing64 :: GPU Time Elapsed */
#define acmgt2__ray_tracing64__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing64 :: GPU Core Clocks */
#define acmgt2__ray_tracing64__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing64 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing64__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing64 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing64__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing64 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE12 */
#define acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing64 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE13 */
#define acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing64 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE14 */
#define acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing64 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE15 */
#define acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing65 :: GPU Time Elapsed */
#define acmgt2__ray_tracing65__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing65 :: GPU Core Clocks */
#define acmgt2__ray_tracing65__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing65 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing65__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing65 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing65__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing65 :: RT INTERSECTION THREAD RAY DISPATCH XECORE0 */
#define acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing65 :: RT INTERSECTION THREAD RAY DISPATCH XECORE1 */
#define acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing65 :: RT INTERSECTION THREAD RAY DISPATCH XECORE2 */
#define acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing65 :: RT INTERSECTION THREAD RAY DISPATCH XECORE3 */
#define acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing66 :: GPU Time Elapsed */
#define acmgt2__ray_tracing66__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing66 :: GPU Core Clocks */
#define acmgt2__ray_tracing66__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing66 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing66__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing66 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing66__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing66 :: RT INTERSECTION THREAD RAY DISPATCH XECORE4 */
#define acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing66 :: RT INTERSECTION THREAD RAY DISPATCH XECORE5 */
#define acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing66 :: RT INTERSECTION THREAD RAY DISPATCH XECORE6 */
#define acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing66 :: RT INTERSECTION THREAD RAY DISPATCH XECORE7 */
#define acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing67 :: GPU Time Elapsed */
#define acmgt2__ray_tracing67__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing67 :: GPU Core Clocks */
#define acmgt2__ray_tracing67__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing67 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing67__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing67 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing67__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing67 :: RT INTERSECTION THREAD RAY DISPATCH XECORE8 */
#define acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing67 :: RT INTERSECTION THREAD RAY DISPATCH XECORE9 */
#define acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing67 :: RT INTERSECTION THREAD RAY DISPATCH XECORE10 */
#define acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing67 :: RT INTERSECTION THREAD RAY DISPATCH XECORE11 */
#define acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing68 :: GPU Time Elapsed */
#define acmgt2__ray_tracing68__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing68 :: GPU Core Clocks */
#define acmgt2__ray_tracing68__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing68 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing68__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing68 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing68__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing68 :: RT INTERSECTION THREAD RAY DISPATCH XECORE12 */
#define acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing68 :: RT INTERSECTION THREAD RAY DISPATCH XECORE13 */
#define acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing68 :: RT INTERSECTION THREAD RAY DISPATCH XECORE14 */
#define acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing68 :: RT INTERSECTION THREAD RAY DISPATCH XECORE15 */
#define acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing69 :: GPU Time Elapsed */
#define acmgt2__ray_tracing69__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing69 :: GPU Core Clocks */
#define acmgt2__ray_tracing69__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing69 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing69__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing69 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing69__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing69 :: RT MISS THREAD RAY DISPATCH XECORE0 */
#define acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing69 :: RT MISS THREAD RAY DISPATCH XECORE1 */
#define acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing69 :: RT MISS THREAD RAY DISPATCH XECORE2 */
#define acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing69 :: RT MISS THREAD RAY DISPATCH XECORE3 */
#define acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing70 :: GPU Time Elapsed */
#define acmgt2__ray_tracing70__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing70 :: GPU Core Clocks */
#define acmgt2__ray_tracing70__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing70 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing70__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing70 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing70__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing70 :: RT MISS THREAD RAY DISPATCH XECORE4 */
#define acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing70 :: RT MISS THREAD RAY DISPATCH XECORE5 */
#define acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing70 :: RT MISS THREAD RAY DISPATCH XECORE6 */
#define acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing70 :: RT MISS THREAD RAY DISPATCH XECORE7 */
#define acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing71 :: GPU Time Elapsed */
#define acmgt2__ray_tracing71__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing71 :: GPU Core Clocks */
#define acmgt2__ray_tracing71__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing71 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing71__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing71 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing71__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing71 :: RT MISS THREAD RAY DISPATCH XECORE8 */
#define acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing71 :: RT MISS THREAD RAY DISPATCH XECORE9 */
#define acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing71 :: RT MISS THREAD RAY DISPATCH XECORE10 */
#define acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing71 :: RT MISS THREAD RAY DISPATCH XECORE11 */
#define acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing72 :: GPU Time Elapsed */
#define acmgt2__ray_tracing72__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing72 :: GPU Core Clocks */
#define acmgt2__ray_tracing72__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing72 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing72__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing72 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing72__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing72 :: RT MISS THREAD RAY DISPATCH XECORE12 */
#define acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* RayTracing72 :: RT MISS THREAD RAY DISPATCH XECORE13 */
#define acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* RayTracing72 :: RT MISS THREAD RAY DISPATCH XECORE14 */
#define acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* RayTracing72 :: RT MISS THREAD RAY DISPATCH XECORE15 */
#define acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* RayTracing73 :: GPU Time Elapsed */
#define acmgt2__ray_tracing73__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing73 :: GPU Core Clocks */
#define acmgt2__ray_tracing73__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing73 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing73__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing73 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing73__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing73 :: RT BVH CACHE MISS XECORE0 */
#define acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing73 :: RT BVH CACHE MISS XECORE1 */
#define acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* RayTracing73 :: RT BVH CACHE MISS XECORE2 */
#define acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* RayTracing73 :: RT BVH CACHE MISS XECORE3 */
#define acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* RayTracing74 :: GPU Time Elapsed */
#define acmgt2__ray_tracing74__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing74 :: GPU Core Clocks */
#define acmgt2__ray_tracing74__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing74 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing74__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing74 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing74__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing74 :: RT BVH CACHE MISS XECORE4 */
#define acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing74 :: RT BVH CACHE MISS XECORE5 */
#define acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* RayTracing74 :: RT BVH CACHE MISS XECORE6 */
#define acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* RayTracing74 :: RT BVH CACHE MISS XECORE7 */
#define acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* RayTracing75 :: GPU Time Elapsed */
#define acmgt2__ray_tracing75__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing75 :: GPU Core Clocks */
#define acmgt2__ray_tracing75__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing75 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing75__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing75 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing75__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing75 :: RT BVH CACHE MISS XECORE8 */
#define acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing75 :: RT BVH CACHE MISS XECORE9 */
#define acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* RayTracing75 :: RT BVH CACHE MISS XECORE10 */
#define acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* RayTracing75 :: RT BVH CACHE MISS XECORE11 */
#define acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* RayTracing76 :: GPU Time Elapsed */
#define acmgt2__ray_tracing76__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing76 :: GPU Core Clocks */
#define acmgt2__ray_tracing76__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing76 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing76__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing76 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing76__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing76 :: RT BVH CACHE MISS XECORE12 */
#define acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* RayTracing76 :: RT BVH CACHE MISS XECORE13 */
#define acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* RayTracing76 :: RT BVH CACHE MISS XECORE14 */
#define acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* RayTracing76 :: RT BVH CACHE MISS XECORE15 */
#define acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* RayTracing77 :: GPU Time Elapsed */
#define acmgt2__ray_tracing77__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing77 :: GPU Core Clocks */
#define acmgt2__ray_tracing77__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing77 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing77__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing77 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing77__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing77 :: RT INPUT AVAILABLE XECORE0 */
#define acmgt2__ray_tracing77__rt_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* RayTracing77 :: RT INPUT AVAILABLE XECORE1 */
#define acmgt2__ray_tracing77__rt_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* RayTracing77 :: RT INPUT AVAILABLE XECORE2 */
#define acmgt2__ray_tracing77__rt_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* RayTracing77 :: RT INPUT AVAILABLE XECORE3 */
#define acmgt2__ray_tracing77__rt_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* RayTracing77 :: RT INPUT AVAILABLE XECORE4 */
#define acmgt2__ray_tracing77__rt_input_available_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* RayTracing77 :: RT INPUT AVAILABLE XECORE5 */
#define acmgt2__ray_tracing77__rt_input_available_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* RayTracing77 :: RT INPUT AVAILABLE XECORE6 */
#define acmgt2__ray_tracing77__rt_input_available_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* RayTracing77 :: RT INPUT AVAILABLE XECORE7 */
#define acmgt2__ray_tracing77__rt_input_available_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* RayTracing78 :: GPU Time Elapsed */
#define acmgt2__ray_tracing78__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RayTracing78 :: GPU Core Clocks */
#define acmgt2__ray_tracing78__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RayTracing78 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing78__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RayTracing78 :: AVG GPU Core Frequency */
#define acmgt2__ray_tracing78__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RayTracing78 :: RT INPUT AVAILABLE XECORE8 */
#define acmgt2__ray_tracing78__rt_input_available_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* RayTracing78 :: RT INPUT AVAILABLE XECORE9 */
#define acmgt2__ray_tracing78__rt_input_available_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* RayTracing78 :: RT INPUT AVAILABLE XECORE10 */
#define acmgt2__ray_tracing78__rt_input_available_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* RayTracing78 :: RT INPUT AVAILABLE XECORE11 */
#define acmgt2__ray_tracing78__rt_input_available_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* RayTracing78 :: RT INPUT AVAILABLE XECORE12 */
#define acmgt2__ray_tracing78__rt_input_available_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* RayTracing78 :: RT INPUT AVAILABLE XECORE13 */
#define acmgt2__ray_tracing78__rt_input_available_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* RayTracing78 :: RT INPUT AVAILABLE XECORE14 */
#define acmgt2__ray_tracing78__rt_input_available_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* RayTracing78 :: RT INPUT AVAILABLE XECORE15 */
#define acmgt2__ray_tracing78__rt_input_available_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler1 :: GPU Time Elapsed */
#define acmgt2__sampler1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler1 :: GPU Core Clocks */
#define acmgt2__sampler1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler1 :: AVG GPU Core Frequency */
#define acmgt2__sampler1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler1 :: AVG GPU Core Frequency */
#define acmgt2__sampler1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler1 :: SAMPLER OUTPUT READY XECORE0 */
#define acmgt2__sampler1__sampler_output_ready_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler1 :: SAMPLER OUTPUT READY XECORE1 */
#define acmgt2__sampler1__sampler_output_ready_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler1 :: SAMPLER OUTPUT READY XECORE2 */
#define acmgt2__sampler1__sampler_output_ready_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler1 :: SAMPLER OUTPUT READY XECORE3 */
#define acmgt2__sampler1__sampler_output_ready_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler2 :: GPU Time Elapsed */
#define acmgt2__sampler2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler2 :: GPU Core Clocks */
#define acmgt2__sampler2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler2 :: AVG GPU Core Frequency */
#define acmgt2__sampler2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler2 :: AVG GPU Core Frequency */
#define acmgt2__sampler2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler2 :: SAMPLER OUTPUT READY XECORE4 */
#define acmgt2__sampler2__sampler_output_ready_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler2 :: SAMPLER OUTPUT READY XECORE5 */
#define acmgt2__sampler2__sampler_output_ready_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler2 :: SAMPLER OUTPUT READY XECORE6 */
#define acmgt2__sampler2__sampler_output_ready_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler2 :: SAMPLER OUTPUT READY XECORE7 */
#define acmgt2__sampler2__sampler_output_ready_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler3 :: GPU Time Elapsed */
#define acmgt2__sampler3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler3 :: GPU Core Clocks */
#define acmgt2__sampler3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler3 :: AVG GPU Core Frequency */
#define acmgt2__sampler3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler3 :: AVG GPU Core Frequency */
#define acmgt2__sampler3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler3 :: SAMPLER OUTPUT READY XECORE8 */
#define acmgt2__sampler3__sampler_output_ready_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler3 :: SAMPLER OUTPUT READY XECORE9 */
#define acmgt2__sampler3__sampler_output_ready_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler3 :: SAMPLER OUTPUT READY XECORE10 */
#define acmgt2__sampler3__sampler_output_ready_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler3 :: SAMPLER OUTPUT READY XECORE11 */
#define acmgt2__sampler3__sampler_output_ready_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler4 :: GPU Time Elapsed */
#define acmgt2__sampler4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler4 :: GPU Core Clocks */
#define acmgt2__sampler4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler4 :: AVG GPU Core Frequency */
#define acmgt2__sampler4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler4 :: AVG GPU Core Frequency */
#define acmgt2__sampler4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler4 :: SAMPLER OUTPUT READY XECORE12 */
#define acmgt2__sampler4__sampler_output_ready_xecore12__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler4 :: SAMPLER OUTPUT READY XECORE13 */
#define acmgt2__sampler4__sampler_output_ready_xecore13__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler4 :: SAMPLER OUTPUT READY XECORE14 */
#define acmgt2__sampler4__sampler_output_ready_xecore14__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler4 :: SAMPLER OUTPUT READY XECORE15 */
#define acmgt2__sampler4__sampler_output_ready_xecore15__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler5 :: GPU Time Elapsed */
#define acmgt2__sampler5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler5 :: GPU Core Clocks */
#define acmgt2__sampler5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler5 :: AVG GPU Core Frequency */
#define acmgt2__sampler5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler5 :: AVG GPU Core Frequency */
#define acmgt2__sampler5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler5 :: SAMPLER BUSY XECORE0 */
#define acmgt2__sampler5__sampler_busy_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler5 :: SAMPLER BUSY XECORE1 */
#define acmgt2__sampler5__sampler_busy_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler5 :: SAMPLER BUSY XECORE2 */
#define acmgt2__sampler5__sampler_busy_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler5 :: SAMPLER BUSY XECORE3 */
#define acmgt2__sampler5__sampler_busy_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler5 :: SAMPLER BUSY XECORE4 */
#define acmgt2__sampler5__sampler_busy_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler5 :: SAMPLER BUSY XECORE5 */
#define acmgt2__sampler5__sampler_busy_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler5 :: SAMPLER BUSY XECORE6 */
#define acmgt2__sampler5__sampler_busy_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler5 :: SAMPLER BUSY XECORE7 */
#define acmgt2__sampler5__sampler_busy_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Sampler5 :: SAMPLER BUSY XECORE8 */
#define acmgt2__sampler5__sampler_busy_xecore8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler5 :: SAMPLER BUSY XECORE9 */
#define acmgt2__sampler5__sampler_busy_xecore9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler5 :: SAMPLER BUSY XECORE10 */
#define acmgt2__sampler5__sampler_busy_xecore10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler5 :: SAMPLER BUSY XECORE11 */
#define acmgt2__sampler5__sampler_busy_xecore11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler5 :: SAMPLER BUSY XECORE12 */
#define acmgt2__sampler5__sampler_busy_xecore12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler5 :: SAMPLER BUSY XECORE13 */
#define acmgt2__sampler5__sampler_busy_xecore13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler5 :: SAMPLER BUSY XECORE14 */
#define acmgt2__sampler5__sampler_busy_xecore14__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler5 :: SAMPLER BUSY XECORE15 */
#define acmgt2__sampler5__sampler_busy_xecore15__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler6 :: GPU Time Elapsed */
#define acmgt2__sampler6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler6 :: GPU Core Clocks */
#define acmgt2__sampler6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler6 :: AVG GPU Core Frequency */
#define acmgt2__sampler6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler6 :: AVG GPU Core Frequency */
#define acmgt2__sampler6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler6 :: SAMPLER MEMORY LATENCY STALL XECORE0 */
#define acmgt2__sampler6__sampler_memory_latency_stall_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler6 :: SAMPLER MEMORY LATENCY STALL XECORE1 */
#define acmgt2__sampler6__sampler_memory_latency_stall_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler6 :: SAMPLER MEMORY LATENCY STALL XECORE2 */
#define acmgt2__sampler6__sampler_memory_latency_stall_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler6 :: SAMPLER MEMORY LATENCY STALL XECORE3 */
#define acmgt2__sampler6__sampler_memory_latency_stall_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler6 :: SAMPLER MEMORY LATENCY STALL XECORE4 */
#define acmgt2__sampler6__sampler_memory_latency_stall_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler6 :: SAMPLER MEMORY LATENCY STALL XECORE5 */
#define acmgt2__sampler6__sampler_memory_latency_stall_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler6 :: SAMPLER MEMORY LATENCY STALL XECORE6 */
#define acmgt2__sampler6__sampler_memory_latency_stall_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler6 :: SAMPLER MEMORY LATENCY STALL XECORE7 */
#define acmgt2__sampler6__sampler_memory_latency_stall_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler7 :: GPU Time Elapsed */
#define acmgt2__sampler7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler7 :: GPU Core Clocks */
#define acmgt2__sampler7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler7 :: AVG GPU Core Frequency */
#define acmgt2__sampler7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler7 :: AVG GPU Core Frequency */
#define acmgt2__sampler7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler7 :: SAMPLER MEMORY LATENCY STALL XECORE8 */
#define acmgt2__sampler7__sampler_memory_latency_stall_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler7 :: SAMPLER MEMORY LATENCY STALL XECORE9 */
#define acmgt2__sampler7__sampler_memory_latency_stall_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler7 :: SAMPLER MEMORY LATENCY STALL XECORE10 */
#define acmgt2__sampler7__sampler_memory_latency_stall_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler7 :: SAMPLER MEMORY LATENCY STALL XECORE11 */
#define acmgt2__sampler7__sampler_memory_latency_stall_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler7 :: SAMPLER MEMORY LATENCY STALL XECORE12 */
#define acmgt2__sampler7__sampler_memory_latency_stall_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler7 :: SAMPLER MEMORY LATENCY STALL XECORE13 */
#define acmgt2__sampler7__sampler_memory_latency_stall_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler7 :: SAMPLER MEMORY LATENCY STALL XECORE14 */
#define acmgt2__sampler7__sampler_memory_latency_stall_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler7 :: SAMPLER MEMORY LATENCY STALL XECORE15 */
#define acmgt2__sampler7__sampler_memory_latency_stall_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler8 :: GPU Time Elapsed */
#define acmgt2__sampler8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler8 :: GPU Core Clocks */
#define acmgt2__sampler8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler8 :: AVG GPU Core Frequency */
#define acmgt2__sampler8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler8 :: AVG GPU Core Frequency */
#define acmgt2__sampler8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler8 :: SAMPLER INPUT AVAILABLE XECORE0 */
#define acmgt2__sampler8__sampler_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler8 :: SAMPLER INPUT AVAILABLE XECORE1 */
#define acmgt2__sampler8__sampler_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler8 :: SAMPLER INPUT AVAILABLE XECORE2 */
#define acmgt2__sampler8__sampler_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler8 :: SAMPLER INPUT AVAILABLE XECORE3 */
#define acmgt2__sampler8__sampler_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler8 :: SAMPLER INPUT AVAILABLE XECORE4 */
#define acmgt2__sampler8__sampler_input_available_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler8 :: SAMPLER INPUT AVAILABLE XECORE5 */
#define acmgt2__sampler8__sampler_input_available_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler8 :: SAMPLER INPUT AVAILABLE XECORE6 */
#define acmgt2__sampler8__sampler_input_available_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler8 :: SAMPLER INPUT AVAILABLE XECORE7 */
#define acmgt2__sampler8__sampler_input_available_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler9 :: GPU Time Elapsed */
#define acmgt2__sampler9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler9 :: GPU Core Clocks */
#define acmgt2__sampler9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler9 :: AVG GPU Core Frequency */
#define acmgt2__sampler9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler9 :: AVG GPU Core Frequency */
#define acmgt2__sampler9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler9 :: SAMPLER INPUT AVAILABLE XECORE8 */
#define acmgt2__sampler9__sampler_input_available_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler9 :: SAMPLER INPUT AVAILABLE XECORE9 */
#define acmgt2__sampler9__sampler_input_available_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler9 :: SAMPLER INPUT AVAILABLE XECORE10 */
#define acmgt2__sampler9__sampler_input_available_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler9 :: SAMPLER INPUT AVAILABLE XECORE11 */
#define acmgt2__sampler9__sampler_input_available_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler9 :: SAMPLER INPUT AVAILABLE XECORE12 */
#define acmgt2__sampler9__sampler_input_available_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler9 :: SAMPLER INPUT AVAILABLE XECORE13 */
#define acmgt2__sampler9__sampler_input_available_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler9 :: SAMPLER INPUT AVAILABLE XECORE14 */
#define acmgt2__sampler9__sampler_input_available_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler9 :: SAMPLER INPUT AVAILABLE XECORE15 */
#define acmgt2__sampler9__sampler_input_available_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler10 :: GPU Time Elapsed */
#define acmgt2__sampler10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler10 :: GPU Core Clocks */
#define acmgt2__sampler10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler10 :: AVG GPU Core Frequency */
#define acmgt2__sampler10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler10 :: AVG GPU Core Frequency */
#define acmgt2__sampler10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE0 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE1 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE2 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE3 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE4 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE5 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE6 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE7 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE8 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore8__read \
   hsw__compute_extended__gpu_clocks__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE9 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE10 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE11 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE12 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE13 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE14 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Sampler10 :: SAMPLER TEXTURE CACHE ACCESS XECORE15 */
#define acmgt2__sampler10__sampler_texture_cache_access_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Sampler11 :: GPU Time Elapsed */
#define acmgt2__sampler11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler11 :: GPU Core Clocks */
#define acmgt2__sampler11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler11 :: AVG GPU Core Frequency */
#define acmgt2__sampler11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler11 :: AVG GPU Core Frequency */
#define acmgt2__sampler11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE0 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE1 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE2 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE3 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE4 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE5 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE6 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE7 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE8 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore8__read \
   hsw__compute_extended__gpu_clocks__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE9 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE10 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE11 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE12 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE13 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE14 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Sampler11 :: SAMPLER TEXTURE CACHE MISS XECORE15 */
#define acmgt2__sampler11__sampler_texture_cache_miss_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher1 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher1 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher1 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher1 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher1 :: GPGPU THREADGROUP COUNT XECORE0 */
#define acmgt2__thread_dispatcher1__gpgpu_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher1 :: ASYNC GPGPU THREADGROUP COUNT XECORE4 */
#define acmgt2__thread_dispatcher1__async_gpgpu_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher1 :: ASYNC GPGPU THREAD EXIT COUNT XECORE8 */
#define acmgt2__thread_dispatcher1__async_gpgpu_thread_exit_count_xecore8__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher2 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher2 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher2 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher2 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher2 :: GPGPU THREADGROUP COUNT XECORE1 */
#define acmgt2__thread_dispatcher2__gpgpu_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher2 :: ASYNC GPGPU THREADGROUP COUNT XECORE5 */
#define acmgt2__thread_dispatcher2__async_gpgpu_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher2 :: ASYNC GPGPU THREAD EXIT COUNT XECORE9 */
#define acmgt2__thread_dispatcher2__async_gpgpu_thread_exit_count_xecore9__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher3 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher3 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher3 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher3 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher3 :: GPGPU THREADGROUP COUNT XECORE2 */
#define acmgt2__thread_dispatcher3__gpgpu_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher3 :: ASYNC GPGPU THREADGROUP COUNT XECORE6 */
#define acmgt2__thread_dispatcher3__async_gpgpu_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher3 :: ASYNC GPGPU THREAD EXIT COUNT XECORE10 */
#define acmgt2__thread_dispatcher3__async_gpgpu_thread_exit_count_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher4 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher4 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher4 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher4 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher4 :: GPGPU THREADGROUP COUNT XECORE3 */
#define acmgt2__thread_dispatcher4__gpgpu_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher4 :: ASYNC GPGPU THREADGROUP COUNT XECORE7 */
#define acmgt2__thread_dispatcher4__async_gpgpu_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher4 :: ASYNC GPGPU THREAD EXIT COUNT XECORE11 */
#define acmgt2__thread_dispatcher4__async_gpgpu_thread_exit_count_xecore11__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher5 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher5 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher5 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher5 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher5 :: GPGPU THREADGROUP COUNT XECORE4 */
#define acmgt2__thread_dispatcher5__gpgpu_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher5 :: ASYNC GPGPU THREADGROUP COUNT XECORE8 */
#define acmgt2__thread_dispatcher5__async_gpgpu_threadgroup_count_xecore8__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher5 :: ASYNC GPGPU THREAD EXIT COUNT XECORE12 */
#define acmgt2__thread_dispatcher5__async_gpgpu_thread_exit_count_xecore12__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher6 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher6 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher6 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher6 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher6 :: GPGPU THREADGROUP COUNT XECORE5 */
#define acmgt2__thread_dispatcher6__gpgpu_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher6 :: ASYNC GPGPU THREADGROUP COUNT XECORE9 */
#define acmgt2__thread_dispatcher6__async_gpgpu_threadgroup_count_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher6 :: ASYNC GPGPU THREAD EXIT COUNT XECORE13 */
#define acmgt2__thread_dispatcher6__async_gpgpu_thread_exit_count_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher7 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher7 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher7 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher7 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher7 :: GPGPU THREADGROUP COUNT XECORE6 */
#define acmgt2__thread_dispatcher7__gpgpu_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher7 :: ASYNC GPGPU THREADGROUP COUNT XECORE10 */
#define acmgt2__thread_dispatcher7__async_gpgpu_threadgroup_count_xecore10__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher7 :: ASYNC GPGPU THREAD EXIT COUNT XECORE14 */
#define acmgt2__thread_dispatcher7__async_gpgpu_thread_exit_count_xecore14__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher8 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher8 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher8 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher8 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher8 :: GPGPU THREADGROUP COUNT XECORE7 */
#define acmgt2__thread_dispatcher8__gpgpu_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher8 :: ASYNC GPGPU THREADGROUP COUNT XECORE11 */
#define acmgt2__thread_dispatcher8__async_gpgpu_threadgroup_count_xecore11__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher8 :: ASYNC GPGPU THREAD EXIT COUNT XECORE15 */
#define acmgt2__thread_dispatcher8__async_gpgpu_thread_exit_count_xecore15__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher9 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher9 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher9 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher9 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher9 :: GPGPU THREADGROUP COUNT XECORE8 */
#define acmgt2__thread_dispatcher9__gpgpu_threadgroup_count_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher9 :: ASYNC GPGPU THREADGROUP COUNT XECORE12 */
#define acmgt2__thread_dispatcher9__async_gpgpu_threadgroup_count_xecore12__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher9 :: ASYNC GPGPU THREAD EXIT COUNT XECORE0 */
#define acmgt2__thread_dispatcher9__async_gpgpu_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher10 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher10 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher10 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher10 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher10 :: GPGPU THREADGROUP COUNT XECORE9 */
#define acmgt2__thread_dispatcher10__gpgpu_threadgroup_count_xecore9__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher10 :: ASYNC GPGPU THREADGROUP COUNT XECORE13 */
#define acmgt2__thread_dispatcher10__async_gpgpu_threadgroup_count_xecore13__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher10 :: ASYNC GPGPU THREAD EXIT COUNT XECORE1 */
#define acmgt2__thread_dispatcher10__async_gpgpu_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher11 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher11 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher11 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher11 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher11 :: GPGPU THREADGROUP COUNT XECORE10 */
#define acmgt2__thread_dispatcher11__gpgpu_threadgroup_count_xecore10__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher11 :: ASYNC GPGPU THREADGROUP COUNT XECORE14 */
#define acmgt2__thread_dispatcher11__async_gpgpu_threadgroup_count_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher11 :: ASYNC GPGPU THREAD EXIT COUNT XECORE2 */
#define acmgt2__thread_dispatcher11__async_gpgpu_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher12 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher12 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher12 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher12 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher12 :: GPGPU THREADGROUP COUNT XECORE11 */
#define acmgt2__thread_dispatcher12__gpgpu_threadgroup_count_xecore11__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher12 :: ASYNC GPGPU THREADGROUP COUNT XECORE15 */
#define acmgt2__thread_dispatcher12__async_gpgpu_threadgroup_count_xecore15__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher12 :: ASYNC GPGPU THREAD EXIT COUNT XECORE3 */
#define acmgt2__thread_dispatcher12__async_gpgpu_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher13 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher13 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher13 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher13 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher13 :: GPGPU THREADGROUP COUNT XECORE12 */
#define acmgt2__thread_dispatcher13__gpgpu_threadgroup_count_xecore12__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher13 :: ASYNC GPGPU THREADGROUP COUNT XECORE0 */
#define acmgt2__thread_dispatcher13__async_gpgpu_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher13 :: ASYNC GPGPU THREAD EXIT COUNT XECORE4 */
#define acmgt2__thread_dispatcher13__async_gpgpu_thread_exit_count_xecore4__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher14 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher14 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher14 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher14 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher14 :: GPGPU THREADGROUP COUNT XECORE13 */
#define acmgt2__thread_dispatcher14__gpgpu_threadgroup_count_xecore13__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher14 :: ASYNC GPGPU THREADGROUP COUNT XECORE1 */
#define acmgt2__thread_dispatcher14__async_gpgpu_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher14 :: ASYNC GPGPU THREAD EXIT COUNT XECORE5 */
#define acmgt2__thread_dispatcher14__async_gpgpu_thread_exit_count_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher15 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher15 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher15 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher15 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher15 :: GPGPU THREADGROUP COUNT XECORE14 */
#define acmgt2__thread_dispatcher15__gpgpu_threadgroup_count_xecore14__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher15 :: ASYNC GPGPU THREADGROUP COUNT XECORE2 */
#define acmgt2__thread_dispatcher15__async_gpgpu_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher15 :: ASYNC GPGPU THREAD EXIT COUNT XECORE6 */
#define acmgt2__thread_dispatcher15__async_gpgpu_thread_exit_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher16 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher16 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher16 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher16 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher16 :: GPGPU THREADGROUP COUNT XECORE15 */
#define acmgt2__thread_dispatcher16__gpgpu_threadgroup_count_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* ThreadDispatcher16 :: ASYNC GPGPU THREADGROUP COUNT XECORE3 */
#define acmgt2__thread_dispatcher16__async_gpgpu_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher16 :: ASYNC GPGPU THREAD EXIT COUNT XECORE7 */
#define acmgt2__thread_dispatcher16__async_gpgpu_thread_exit_count_xecore7__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher17 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher17 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher17 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher17 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher17 :: TASK THREADGROUP COUNT XECORE0 */
#define acmgt2__thread_dispatcher17__task_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher17 :: TASK THREAD EXIT COUNT XECORE4 */
#define acmgt2__thread_dispatcher17__task_thread_exit_count_xecore4__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher17 :: THREADGROUP DISPATCH RESOURCE STALL XECORE8 */
#define acmgt2__thread_dispatcher17__threadgroup_dispatch_resource_stall_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher18 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher18 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher18 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher18 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher18 :: TASK THREADGROUP COUNT XECORE1 */
#define acmgt2__thread_dispatcher18__task_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher18 :: TASK THREAD EXIT COUNT XECORE5 */
#define acmgt2__thread_dispatcher18__task_thread_exit_count_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher18 :: THREADGROUP DISPATCH RESOURCE STALL XECORE9 */
#define acmgt2__thread_dispatcher18__threadgroup_dispatch_resource_stall_xecore9__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher19 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher19__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher19 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher19__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher19 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher19__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher19 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher19__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher19 :: TASK THREADGROUP COUNT XECORE2 */
#define acmgt2__thread_dispatcher19__task_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher19 :: TASK THREAD EXIT COUNT XECORE6 */
#define acmgt2__thread_dispatcher19__task_thread_exit_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher19 :: THREADGROUP DISPATCH RESOURCE STALL XECORE10 */
#define acmgt2__thread_dispatcher19__threadgroup_dispatch_resource_stall_xecore10__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher20 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher20__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher20 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher20__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher20 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher20__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher20 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher20__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher20 :: TASK THREADGROUP COUNT XECORE3 */
#define acmgt2__thread_dispatcher20__task_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher20 :: TASK THREAD EXIT COUNT XECORE7 */
#define acmgt2__thread_dispatcher20__task_thread_exit_count_xecore7__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher20 :: THREADGROUP DISPATCH RESOURCE STALL XECORE11 */
#define acmgt2__thread_dispatcher20__threadgroup_dispatch_resource_stall_xecore11__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher21 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher21 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher21 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher21 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher21 :: TASK THREADGROUP COUNT XECORE4 */
#define acmgt2__thread_dispatcher21__task_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher21 :: TASK THREAD EXIT COUNT XECORE8 */
#define acmgt2__thread_dispatcher21__task_thread_exit_count_xecore8__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher21 :: THREADGROUP DISPATCH RESOURCE STALL XECORE12 */
#define acmgt2__thread_dispatcher21__threadgroup_dispatch_resource_stall_xecore12__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher22 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher22 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher22 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher22 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher22 :: TASK THREADGROUP COUNT XECORE5 */
#define acmgt2__thread_dispatcher22__task_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher22 :: TASK THREAD EXIT COUNT XECORE9 */
#define acmgt2__thread_dispatcher22__task_thread_exit_count_xecore9__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher22 :: THREADGROUP DISPATCH RESOURCE STALL XECORE13 */
#define acmgt2__thread_dispatcher22__threadgroup_dispatch_resource_stall_xecore13__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher23 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher23 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher23 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher23 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher23 :: TASK THREADGROUP COUNT XECORE6 */
#define acmgt2__thread_dispatcher23__task_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher23 :: TASK THREAD EXIT COUNT XECORE10 */
#define acmgt2__thread_dispatcher23__task_thread_exit_count_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher23 :: THREADGROUP DISPATCH RESOURCE STALL XECORE14 */
#define acmgt2__thread_dispatcher23__threadgroup_dispatch_resource_stall_xecore14__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher24 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher24__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher24 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher24__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher24 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher24__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher24 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher24__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher24 :: TASK THREADGROUP COUNT XECORE7 */
#define acmgt2__thread_dispatcher24__task_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher24 :: TASK THREAD EXIT COUNT XECORE11 */
#define acmgt2__thread_dispatcher24__task_thread_exit_count_xecore11__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher24 :: THREADGROUP DISPATCH RESOURCE STALL XECORE15 */
#define acmgt2__thread_dispatcher24__threadgroup_dispatch_resource_stall_xecore15__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher25 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher25__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher25 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher25__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher25 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher25__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher25 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher25__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher25 :: TASK THREADGROUP COUNT XECORE8 */
#define acmgt2__thread_dispatcher25__task_threadgroup_count_xecore8__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher25 :: TASK THREAD EXIT COUNT XECORE12 */
#define acmgt2__thread_dispatcher25__task_thread_exit_count_xecore12__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher25 :: THREADGROUP DISPATCH RESOURCE STALL XECORE0 */
#define acmgt2__thread_dispatcher25__threadgroup_dispatch_resource_stall_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher26 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher26__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher26 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher26__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher26 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher26__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher26 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher26__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher26 :: TASK THREADGROUP COUNT XECORE9 */
#define acmgt2__thread_dispatcher26__task_threadgroup_count_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher26 :: TASK THREAD EXIT COUNT XECORE13 */
#define acmgt2__thread_dispatcher26__task_thread_exit_count_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher26 :: THREADGROUP DISPATCH RESOURCE STALL XECORE1 */
#define acmgt2__thread_dispatcher26__threadgroup_dispatch_resource_stall_xecore1__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher27 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher27__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher27 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher27__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher27 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher27__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher27 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher27__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher27 :: TASK THREADGROUP COUNT XECORE10 */
#define acmgt2__thread_dispatcher27__task_threadgroup_count_xecore10__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher27 :: TASK THREAD EXIT COUNT XECORE14 */
#define acmgt2__thread_dispatcher27__task_thread_exit_count_xecore14__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher27 :: THREADGROUP DISPATCH RESOURCE STALL XECORE2 */
#define acmgt2__thread_dispatcher27__threadgroup_dispatch_resource_stall_xecore2__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher28 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher28 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher28 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher28 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher28 :: TASK THREADGROUP COUNT XECORE11 */
#define acmgt2__thread_dispatcher28__task_threadgroup_count_xecore11__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher28 :: TASK THREAD EXIT COUNT XECORE15 */
#define acmgt2__thread_dispatcher28__task_thread_exit_count_xecore15__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher28 :: THREADGROUP DISPATCH RESOURCE STALL XECORE3 */
#define acmgt2__thread_dispatcher28__threadgroup_dispatch_resource_stall_xecore3__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher29 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher29__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher29 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher29__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher29 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher29__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher29 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher29__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher29 :: TASK THREADGROUP COUNT XECORE12 */
#define acmgt2__thread_dispatcher29__task_threadgroup_count_xecore12__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher29 :: TASK THREAD EXIT COUNT XECORE0 */
#define acmgt2__thread_dispatcher29__task_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher29 :: THREADGROUP DISPATCH RESOURCE STALL XECORE4 */
#define acmgt2__thread_dispatcher29__threadgroup_dispatch_resource_stall_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher30 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher30__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher30 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher30__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher30 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher30__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher30 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher30__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher30 :: TASK THREADGROUP COUNT XECORE13 */
#define acmgt2__thread_dispatcher30__task_threadgroup_count_xecore13__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher30 :: TASK THREAD EXIT COUNT XECORE1 */
#define acmgt2__thread_dispatcher30__task_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher30 :: THREADGROUP DISPATCH RESOURCE STALL XECORE5 */
#define acmgt2__thread_dispatcher30__threadgroup_dispatch_resource_stall_xecore5__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher31 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher31 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher31 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher31 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher31 :: TASK THREADGROUP COUNT XECORE14 */
#define acmgt2__thread_dispatcher31__task_threadgroup_count_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher31 :: TASK THREAD EXIT COUNT XECORE2 */
#define acmgt2__thread_dispatcher31__task_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher31 :: THREADGROUP DISPATCH RESOURCE STALL XECORE6 */
#define acmgt2__thread_dispatcher31__threadgroup_dispatch_resource_stall_xecore6__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher32 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher32__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher32 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher32__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher32 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher32__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher32 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher32__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher32 :: TASK THREADGROUP COUNT XECORE15 */
#define acmgt2__thread_dispatcher32__task_threadgroup_count_xecore15__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* ThreadDispatcher32 :: TASK THREAD EXIT COUNT XECORE3 */
#define acmgt2__thread_dispatcher32__task_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_typed_reads0__read

/* ThreadDispatcher32 :: THREADGROUP DISPATCH RESOURCE STALL XECORE7 */
#define acmgt2__thread_dispatcher32__threadgroup_dispatch_resource_stall_xecore7__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher33 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher33__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher33 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher33__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher33 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher33__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher33 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher33__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE0 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE1 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE2 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE3 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE4 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE5 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE6 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE7 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE8 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE9 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE10 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE11 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE12 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE13 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE14 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore14__read \
   bdw__render_basic__sampler1_busy__read

/* ThreadDispatcher33 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE15 */
#define acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore15__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher34 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher34__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher34 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher34__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher34 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher34__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher34 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher34__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE0 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE1 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE2 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE3 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE4 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE5 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE6 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE7 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE8 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE9 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE10 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE11 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE12 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE13 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE14 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore14__read \
   bdw__render_basic__sampler1_busy__read

/* ThreadDispatcher34 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE15 */
#define acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore15__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher35 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher35 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher35 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher35 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher35 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE0 */
#define acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher35 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE1 */
#define acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* ThreadDispatcher35 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE2 */
#define acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ThreadDispatcher35 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE3 */
#define acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ThreadDispatcher35 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE4 */
#define acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ThreadDispatcher35 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE5 */
#define acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ThreadDispatcher35 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE6 */
#define acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ThreadDispatcher35 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE7 */
#define acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* ThreadDispatcher35 :: THREAD DISPATCH STALL XECORE0 */
#define acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* ThreadDispatcher35 :: THREAD DISPATCH STALL XECORE1 */
#define acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* ThreadDispatcher35 :: THREAD DISPATCH STALL XECORE2 */
#define acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* ThreadDispatcher35 :: THREAD DISPATCH STALL XECORE3 */
#define acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* ThreadDispatcher35 :: THREAD DISPATCH STALL XECORE4 */
#define acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* ThreadDispatcher35 :: THREAD DISPATCH STALL XECORE5 */
#define acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* ThreadDispatcher35 :: THREAD DISPATCH STALL XECORE6 */
#define acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* ThreadDispatcher35 :: THREAD DISPATCH STALL XECORE7 */
#define acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* ThreadDispatcher36 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher36__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher36 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher36__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher36 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher36__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher36 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher36__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher36 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE8 */
#define acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher36 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE9 */
#define acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* ThreadDispatcher36 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE10 */
#define acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ThreadDispatcher36 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE11 */
#define acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ThreadDispatcher36 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE12 */
#define acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ThreadDispatcher36 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE13 */
#define acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ThreadDispatcher36 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE14 */
#define acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ThreadDispatcher36 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE15 */
#define acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* ThreadDispatcher36 :: THREAD DISPATCH STALL XECORE8 */
#define acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore8__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* ThreadDispatcher36 :: THREAD DISPATCH STALL XECORE9 */
#define acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore9__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* ThreadDispatcher36 :: THREAD DISPATCH STALL XECORE10 */
#define acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore10__read \
   bdw__render_pipe_profile__sf_stall__read

/* ThreadDispatcher36 :: THREAD DISPATCH STALL XECORE11 */
#define acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore11__read \
   bdw__render_pipe_profile__cl_stall__read

/* ThreadDispatcher36 :: THREAD DISPATCH STALL XECORE12 */
#define acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore12__read \
   bdw__render_pipe_profile__so_stall__read

/* ThreadDispatcher36 :: THREAD DISPATCH STALL XECORE13 */
#define acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore13__read \
   bdw__render_pipe_profile__ds_stall__read

/* ThreadDispatcher36 :: THREAD DISPATCH STALL XECORE14 */
#define acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore14__read \
   bdw__render_pipe_profile__hs_stall__read

/* ThreadDispatcher36 :: THREAD DISPATCH STALL XECORE15 */
#define acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore15__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* ThreadDispatcher37 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher37__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher37 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher37__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher37 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher37__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher37 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher37__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher37 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE0 */
#define acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher37 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE1 */
#define acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* ThreadDispatcher37 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE2 */
#define acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ThreadDispatcher37 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE3 */
#define acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ThreadDispatcher37 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE4 */
#define acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ThreadDispatcher37 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE5 */
#define acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ThreadDispatcher37 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE6 */
#define acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ThreadDispatcher37 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE7 */
#define acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* ThreadDispatcher37 :: THREAD DISPATCH INPUT AVAILABLE XECORE0 */
#define acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* ThreadDispatcher37 :: THREAD DISPATCH INPUT AVAILABLE XECORE1 */
#define acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* ThreadDispatcher37 :: THREAD DISPATCH INPUT AVAILABLE XECORE2 */
#define acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* ThreadDispatcher37 :: THREAD DISPATCH INPUT AVAILABLE XECORE3 */
#define acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* ThreadDispatcher37 :: THREAD DISPATCH INPUT AVAILABLE XECORE4 */
#define acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* ThreadDispatcher37 :: THREAD DISPATCH INPUT AVAILABLE XECORE5 */
#define acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* ThreadDispatcher37 :: THREAD DISPATCH INPUT AVAILABLE XECORE6 */
#define acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* ThreadDispatcher37 :: THREAD DISPATCH INPUT AVAILABLE XECORE7 */
#define acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* ThreadDispatcher38 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher38__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher38 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher38__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher38 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher38__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher38 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher38__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher38 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE8 */
#define acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher38 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE9 */
#define acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* ThreadDispatcher38 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE10 */
#define acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ThreadDispatcher38 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE11 */
#define acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ThreadDispatcher38 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE12 */
#define acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ThreadDispatcher38 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE13 */
#define acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ThreadDispatcher38 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE14 */
#define acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ThreadDispatcher38 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE15 */
#define acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* ThreadDispatcher38 :: THREAD DISPATCH INPUT AVAILABLE XECORE8 */
#define acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore8__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* ThreadDispatcher38 :: THREAD DISPATCH INPUT AVAILABLE XECORE9 */
#define acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore9__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* ThreadDispatcher38 :: THREAD DISPATCH INPUT AVAILABLE XECORE10 */
#define acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore10__read \
   bdw__render_pipe_profile__sf_stall__read

/* ThreadDispatcher38 :: THREAD DISPATCH INPUT AVAILABLE XECORE11 */
#define acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore11__read \
   bdw__render_pipe_profile__cl_stall__read

/* ThreadDispatcher38 :: THREAD DISPATCH INPUT AVAILABLE XECORE12 */
#define acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore12__read \
   bdw__render_pipe_profile__so_stall__read

/* ThreadDispatcher38 :: THREAD DISPATCH INPUT AVAILABLE XECORE13 */
#define acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore13__read \
   bdw__render_pipe_profile__ds_stall__read

/* ThreadDispatcher38 :: THREAD DISPATCH INPUT AVAILABLE XECORE14 */
#define acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore14__read \
   bdw__render_pipe_profile__hs_stall__read

/* ThreadDispatcher38 :: THREAD DISPATCH INPUT AVAILABLE XECORE15 */
#define acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore15__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* ThreadDispatcher39 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher39 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher39 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher39 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher39 :: THREAD DISPATCH PS ACTIVE XECORE0 */
#define acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher39 :: THREAD DISPATCH PS ACTIVE XECORE1 */
#define acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* ThreadDispatcher39 :: THREAD DISPATCH PS ACTIVE XECORE2 */
#define acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ThreadDispatcher39 :: THREAD DISPATCH PS ACTIVE XECORE3 */
#define acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ThreadDispatcher39 :: THREAD DISPATCH PS ACTIVE XECORE4 */
#define acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ThreadDispatcher39 :: THREAD DISPATCH PS ACTIVE XECORE5 */
#define acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ThreadDispatcher39 :: THREAD DISPATCH PS ACTIVE XECORE6 */
#define acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ThreadDispatcher39 :: THREAD DISPATCH PS ACTIVE XECORE7 */
#define acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* ThreadDispatcher40 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher40__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher40 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher40__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher40 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher40__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher40 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher40__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher40 :: THREAD DISPATCH PS ACTIVE XECORE8 */
#define acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* ThreadDispatcher40 :: THREAD DISPATCH PS ACTIVE XECORE9 */
#define acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* ThreadDispatcher40 :: THREAD DISPATCH PS ACTIVE XECORE10 */
#define acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* ThreadDispatcher40 :: THREAD DISPATCH PS ACTIVE XECORE11 */
#define acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ThreadDispatcher40 :: THREAD DISPATCH PS ACTIVE XECORE12 */
#define acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* ThreadDispatcher40 :: THREAD DISPATCH PS ACTIVE XECORE13 */
#define acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* ThreadDispatcher40 :: THREAD DISPATCH PS ACTIVE XECORE14 */
#define acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* ThreadDispatcher40 :: THREAD DISPATCH PS ACTIVE XECORE15 */
#define acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* ThreadDispatcher41 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher41__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher41 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher41__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher41 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher41__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher41 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher41__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher41 :: GPGPU DISPATCH XECORE0 */
#define acmgt2__thread_dispatcher41__gpgpu_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* ThreadDispatcher41 :: GPGPU DISPATCH XECORE1 */
#define acmgt2__thread_dispatcher41__gpgpu_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* ThreadDispatcher41 :: GPGPU DISPATCH XECORE2 */
#define acmgt2__thread_dispatcher41__gpgpu_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* ThreadDispatcher42 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher42__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher42 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher42__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher42 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher42__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher42 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher42__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher42 :: GPGPU DISPATCH XECORE3 */
#define acmgt2__thread_dispatcher42__gpgpu_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* ThreadDispatcher42 :: GPGPU DISPATCH XECORE4 */
#define acmgt2__thread_dispatcher42__gpgpu_dispatch_xecore4__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* ThreadDispatcher42 :: GPGPU DISPATCH XECORE5 */
#define acmgt2__thread_dispatcher42__gpgpu_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* ThreadDispatcher43 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher43__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher43 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher43__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher43 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher43__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher43 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher43__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher43 :: GPGPU DISPATCH XECORE6 */
#define acmgt2__thread_dispatcher43__gpgpu_dispatch_xecore6__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* ThreadDispatcher43 :: GPGPU DISPATCH XECORE7 */
#define acmgt2__thread_dispatcher43__gpgpu_dispatch_xecore7__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* ThreadDispatcher43 :: GPGPU DISPATCH XECORE8 */
#define acmgt2__thread_dispatcher43__gpgpu_dispatch_xecore8__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* ThreadDispatcher44 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher44__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher44 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher44__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher44 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher44__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher44 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher44__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher44 :: GPGPU DISPATCH XECORE9 */
#define acmgt2__thread_dispatcher44__gpgpu_dispatch_xecore9__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* ThreadDispatcher44 :: GPGPU DISPATCH XECORE10 */
#define acmgt2__thread_dispatcher44__gpgpu_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* ThreadDispatcher44 :: GPGPU DISPATCH XECORE11 */
#define acmgt2__thread_dispatcher44__gpgpu_dispatch_xecore11__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* ThreadDispatcher45 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher45 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher45 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher45 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher45 :: GPGPU DISPATCH XECORE12 */
#define acmgt2__thread_dispatcher45__gpgpu_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* ThreadDispatcher45 :: GPGPU DISPATCH XECORE13 */
#define acmgt2__thread_dispatcher45__gpgpu_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* ThreadDispatcher45 :: GPGPU DISPATCH XECORE14 */
#define acmgt2__thread_dispatcher45__gpgpu_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* ThreadDispatcher46 :: GPU Time Elapsed */
#define acmgt2__thread_dispatcher46__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ThreadDispatcher46 :: GPU Core Clocks */
#define acmgt2__thread_dispatcher46__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ThreadDispatcher46 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher46__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ThreadDispatcher46 :: AVG GPU Core Frequency */
#define acmgt2__thread_dispatcher46__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ThreadDispatcher46 :: GPGPU DISPATCH XECORE15 */
#define acmgt2__thread_dispatcher46__gpgpu_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* URB1 :: GPU Time Elapsed */
#define acmgt2__urb1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* URB1 :: GPU Core Clocks */
#define acmgt2__urb1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* URB1 :: AVG GPU Core Frequency */
#define acmgt2__urb1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* URB1 :: AVG GPU Core Frequency */
#define acmgt2__urb1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* URB1 :: URB READ SLICE0 */
#define acmgt2__urb1__urb_read_slice0__read \
   acmgt1__ext128__urb_read_slice0__read

/* URB1 :: URB WRITE SLICE0 */
#define acmgt2__urb1__urb_write_slice0__read \
   acmgt1__ext128__urb_write_slice0__read

/* URB1 :: URB CROSS SLICE READ SLICE0 */
#define acmgt2__urb1__urb_cross_slice_read_slice0__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* URB2 :: GPU Time Elapsed */
#define acmgt2__urb2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* URB2 :: GPU Core Clocks */
#define acmgt2__urb2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* URB2 :: AVG GPU Core Frequency */
#define acmgt2__urb2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* URB2 :: AVG GPU Core Frequency */
#define acmgt2__urb2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* URB2 :: URB READ SLICE1 */
#define acmgt2__urb2__urb_read_slice1__read \
   acmgt1__ext128__urb_read_slice0__read

/* URB2 :: URB WRITE SLICE1 */
#define acmgt2__urb2__urb_write_slice1__read \
   acmgt1__ext128__urb_write_slice0__read

/* URB2 :: URB CROSS SLICE READ SLICE1 */
#define acmgt2__urb2__urb_cross_slice_read_slice1__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* URB3 :: GPU Time Elapsed */
#define acmgt2__urb3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* URB3 :: GPU Core Clocks */
#define acmgt2__urb3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* URB3 :: AVG GPU Core Frequency */
#define acmgt2__urb3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* URB3 :: AVG GPU Core Frequency */
#define acmgt2__urb3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* URB3 :: URB READ SLICE2 */
#define acmgt2__urb3__urb_read_slice2__read \
   acmgt1__ext128__urb_read_slice0__read

/* URB3 :: URB WRITE SLICE2 */
#define acmgt2__urb3__urb_write_slice2__read \
   acmgt1__ext128__urb_write_slice0__read

/* URB3 :: URB CROSS SLICE READ SLICE2 */
#define acmgt2__urb3__urb_cross_slice_read_slice2__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* URB4 :: GPU Time Elapsed */
#define acmgt2__urb4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* URB4 :: GPU Core Clocks */
#define acmgt2__urb4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* URB4 :: AVG GPU Core Frequency */
#define acmgt2__urb4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* URB4 :: AVG GPU Core Frequency */
#define acmgt2__urb4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* URB4 :: URB READ SLICE3 */
#define acmgt2__urb4__urb_read_slice3__read \
   acmgt1__ext128__urb_read_slice0__read

/* URB4 :: URB WRITE SLICE3 */
#define acmgt2__urb4__urb_write_slice3__read \
   acmgt1__ext128__urb_write_slice0__read

/* URB4 :: URB CROSS SLICE READ SLICE3 */
#define acmgt2__urb4__urb_cross_slice_read_slice3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* VectorEngine1 :: GPU Time Elapsed */
#define acmgt2__vector_engine1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine1 :: GPU Core Clocks */
#define acmgt2__vector_engine1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine1 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine1 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine1 :: XVE STALL ALUWR XECORE0 XVE0 THREAD0 */
#define acmgt2__vector_engine1__xve_stall_aluwr_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine1 :: XVE STALL BARRIER XECORE0 XVE0 THREAD0 */
#define acmgt2__vector_engine1__xve_stall_barrier_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine1 :: XVE STALL INSTFETCH XECORE0 XVE0 THREAD0 */
#define acmgt2__vector_engine1__xve_stall_instfetch_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine1 :: XVE STALL OTHER XECORE0 XVE0 THREAD0 */
#define acmgt2__vector_engine1__xve_stall_other_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine1 :: XVE STALL SBID XECORE0 XVE0 THREAD0 */
#define acmgt2__vector_engine1__xve_stall_sbid_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine1 :: XVE STALL SENDWR XECORE0 XVE0 THREAD0 */
#define acmgt2__vector_engine1__xve_stall_sendwr_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine1 :: XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0 */
#define acmgt2__vector_engine1__xve_shared_function_access_hold_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine2 :: GPU Time Elapsed */
#define acmgt2__vector_engine2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine2 :: GPU Core Clocks */
#define acmgt2__vector_engine2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine2 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine2 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine2 :: XVE STALL ALUWR XECORE1 XVE0 THREAD0 */
#define acmgt2__vector_engine2__xve_stall_aluwr_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine2 :: XVE STALL BARRIER XECORE1 XVE0 THREAD0 */
#define acmgt2__vector_engine2__xve_stall_barrier_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine2 :: XVE STALL INSTFETCH XECORE1 XVE0 THREAD0 */
#define acmgt2__vector_engine2__xve_stall_instfetch_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine2 :: XVE STALL OTHER XECORE1 XVE0 THREAD0 */
#define acmgt2__vector_engine2__xve_stall_other_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine2 :: XVE STALL SBID XECORE1 XVE0 THREAD0 */
#define acmgt2__vector_engine2__xve_stall_sbid_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine2 :: XVE STALL SENDWR XECORE1 XVE0 THREAD0 */
#define acmgt2__vector_engine2__xve_stall_sendwr_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine2 :: XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0 */
#define acmgt2__vector_engine2__xve_shared_function_access_hold_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine3 :: GPU Time Elapsed */
#define acmgt2__vector_engine3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine3 :: GPU Core Clocks */
#define acmgt2__vector_engine3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine3 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine3 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine3 :: XVE STALL ALUWR XECORE2 XVE0 THREAD0 */
#define acmgt2__vector_engine3__xve_stall_aluwr_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine3 :: XVE STALL BARRIER XECORE2 XVE0 THREAD0 */
#define acmgt2__vector_engine3__xve_stall_barrier_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine3 :: XVE STALL INSTFETCH XECORE2 XVE0 THREAD0 */
#define acmgt2__vector_engine3__xve_stall_instfetch_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine3 :: XVE STALL OTHER XECORE2 XVE0 THREAD0 */
#define acmgt2__vector_engine3__xve_stall_other_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine3 :: XVE STALL SBID XECORE2 XVE0 THREAD0 */
#define acmgt2__vector_engine3__xve_stall_sbid_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine3 :: XVE STALL SENDWR XECORE2 XVE0 THREAD0 */
#define acmgt2__vector_engine3__xve_stall_sendwr_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine3 :: XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0 */
#define acmgt2__vector_engine3__xve_shared_function_access_hold_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine4 :: GPU Time Elapsed */
#define acmgt2__vector_engine4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine4 :: GPU Core Clocks */
#define acmgt2__vector_engine4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine4 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine4 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine4 :: XVE STALL ALUWR XECORE3 XVE0 THREAD0 */
#define acmgt2__vector_engine4__xve_stall_aluwr_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine4 :: XVE STALL BARRIER XECORE3 XVE0 THREAD0 */
#define acmgt2__vector_engine4__xve_stall_barrier_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine4 :: XVE STALL INSTFETCH XECORE3 XVE0 THREAD0 */
#define acmgt2__vector_engine4__xve_stall_instfetch_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine4 :: XVE STALL OTHER XECORE3 XVE0 THREAD0 */
#define acmgt2__vector_engine4__xve_stall_other_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine4 :: XVE STALL SBID XECORE3 XVE0 THREAD0 */
#define acmgt2__vector_engine4__xve_stall_sbid_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine4 :: XVE STALL SENDWR XECORE3 XVE0 THREAD0 */
#define acmgt2__vector_engine4__xve_stall_sendwr_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine4 :: XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0 */
#define acmgt2__vector_engine4__xve_shared_function_access_hold_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine5 :: GPU Time Elapsed */
#define acmgt2__vector_engine5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine5 :: GPU Core Clocks */
#define acmgt2__vector_engine5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine5 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine5 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine5 :: XVE STALL ALUWR XECORE4 XVE0 THREAD0 */
#define acmgt2__vector_engine5__xve_stall_aluwr_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine5 :: XVE STALL BARRIER XECORE4 XVE0 THREAD0 */
#define acmgt2__vector_engine5__xve_stall_barrier_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine5 :: XVE STALL INSTFETCH XECORE4 XVE0 THREAD0 */
#define acmgt2__vector_engine5__xve_stall_instfetch_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine5 :: XVE STALL OTHER XECORE4 XVE0 THREAD0 */
#define acmgt2__vector_engine5__xve_stall_other_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine5 :: XVE STALL SBID XECORE4 XVE0 THREAD0 */
#define acmgt2__vector_engine5__xve_stall_sbid_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine5 :: XVE STALL SENDWR XECORE4 XVE0 THREAD0 */
#define acmgt2__vector_engine5__xve_stall_sendwr_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine5 :: XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0 */
#define acmgt2__vector_engine5__xve_shared_function_access_hold_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine6 :: GPU Time Elapsed */
#define acmgt2__vector_engine6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine6 :: GPU Core Clocks */
#define acmgt2__vector_engine6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine6 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine6 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine6 :: XVE STALL ALUWR XECORE5 XVE0 THREAD0 */
#define acmgt2__vector_engine6__xve_stall_aluwr_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine6 :: XVE STALL BARRIER XECORE5 XVE0 THREAD0 */
#define acmgt2__vector_engine6__xve_stall_barrier_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine6 :: XVE STALL INSTFETCH XECORE5 XVE0 THREAD0 */
#define acmgt2__vector_engine6__xve_stall_instfetch_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine6 :: XVE STALL OTHER XECORE5 XVE0 THREAD0 */
#define acmgt2__vector_engine6__xve_stall_other_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine6 :: XVE STALL SBID XECORE5 XVE0 THREAD0 */
#define acmgt2__vector_engine6__xve_stall_sbid_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine6 :: XVE STALL SENDWR XECORE5 XVE0 THREAD0 */
#define acmgt2__vector_engine6__xve_stall_sendwr_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine6 :: XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0 */
#define acmgt2__vector_engine6__xve_shared_function_access_hold_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine7 :: GPU Time Elapsed */
#define acmgt2__vector_engine7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine7 :: GPU Core Clocks */
#define acmgt2__vector_engine7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine7 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine7 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine7 :: XVE STALL ALUWR XECORE6 XVE0 THREAD0 */
#define acmgt2__vector_engine7__xve_stall_aluwr_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine7 :: XVE STALL BARRIER XECORE6 XVE0 THREAD0 */
#define acmgt2__vector_engine7__xve_stall_barrier_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine7 :: XVE STALL INSTFETCH XECORE6 XVE0 THREAD0 */
#define acmgt2__vector_engine7__xve_stall_instfetch_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine7 :: XVE STALL OTHER XECORE6 XVE0 THREAD0 */
#define acmgt2__vector_engine7__xve_stall_other_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine7 :: XVE STALL SBID XECORE6 XVE0 THREAD0 */
#define acmgt2__vector_engine7__xve_stall_sbid_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine7 :: XVE STALL SENDWR XECORE6 XVE0 THREAD0 */
#define acmgt2__vector_engine7__xve_stall_sendwr_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine7 :: XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0 */
#define acmgt2__vector_engine7__xve_shared_function_access_hold_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine8 :: GPU Time Elapsed */
#define acmgt2__vector_engine8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine8 :: GPU Core Clocks */
#define acmgt2__vector_engine8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine8 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine8 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine8 :: XVE STALL ALUWR XECORE7 XVE0 THREAD0 */
#define acmgt2__vector_engine8__xve_stall_aluwr_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine8 :: XVE STALL BARRIER XECORE7 XVE0 THREAD0 */
#define acmgt2__vector_engine8__xve_stall_barrier_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine8 :: XVE STALL INSTFETCH XECORE7 XVE0 THREAD0 */
#define acmgt2__vector_engine8__xve_stall_instfetch_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine8 :: XVE STALL OTHER XECORE7 XVE0 THREAD0 */
#define acmgt2__vector_engine8__xve_stall_other_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine8 :: XVE STALL SBID XECORE7 XVE0 THREAD0 */
#define acmgt2__vector_engine8__xve_stall_sbid_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine8 :: XVE STALL SENDWR XECORE7 XVE0 THREAD0 */
#define acmgt2__vector_engine8__xve_stall_sendwr_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine8 :: XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0 */
#define acmgt2__vector_engine8__xve_shared_function_access_hold_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine9 :: GPU Time Elapsed */
#define acmgt2__vector_engine9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine9 :: GPU Core Clocks */
#define acmgt2__vector_engine9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine9 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine9 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine9 :: XVE STALL ALUWR XECORE8 XVE0 THREAD0 */
#define acmgt2__vector_engine9__xve_stall_aluwr_xecore8_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine9 :: XVE STALL BARRIER XECORE8 XVE0 THREAD0 */
#define acmgt2__vector_engine9__xve_stall_barrier_xecore8_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine9 :: XVE STALL INSTFETCH XECORE8 XVE0 THREAD0 */
#define acmgt2__vector_engine9__xve_stall_instfetch_xecore8_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine9 :: XVE STALL OTHER XECORE8 XVE0 THREAD0 */
#define acmgt2__vector_engine9__xve_stall_other_xecore8_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine9 :: XVE STALL SBID XECORE8 XVE0 THREAD0 */
#define acmgt2__vector_engine9__xve_stall_sbid_xecore8_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine9 :: XVE STALL SENDWR XECORE8 XVE0 THREAD0 */
#define acmgt2__vector_engine9__xve_stall_sendwr_xecore8_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine9 :: XVE SHARED FUNCTION ACCESS HOLD XECORE8 XVE0 THREAD0 */
#define acmgt2__vector_engine9__xve_shared_function_access_hold_xecore8_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine10 :: GPU Time Elapsed */
#define acmgt2__vector_engine10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine10 :: GPU Core Clocks */
#define acmgt2__vector_engine10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine10 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine10 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine10 :: XVE STALL ALUWR XECORE9 XVE0 THREAD0 */
#define acmgt2__vector_engine10__xve_stall_aluwr_xecore9_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine10 :: XVE STALL BARRIER XECORE9 XVE0 THREAD0 */
#define acmgt2__vector_engine10__xve_stall_barrier_xecore9_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine10 :: XVE STALL INSTFETCH XECORE9 XVE0 THREAD0 */
#define acmgt2__vector_engine10__xve_stall_instfetch_xecore9_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine10 :: XVE STALL OTHER XECORE9 XVE0 THREAD0 */
#define acmgt2__vector_engine10__xve_stall_other_xecore9_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine10 :: XVE STALL SBID XECORE9 XVE0 THREAD0 */
#define acmgt2__vector_engine10__xve_stall_sbid_xecore9_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine10 :: XVE STALL SENDWR XECORE9 XVE0 THREAD0 */
#define acmgt2__vector_engine10__xve_stall_sendwr_xecore9_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine10 :: XVE SHARED FUNCTION ACCESS HOLD XECORE9 XVE0 THREAD0 */
#define acmgt2__vector_engine10__xve_shared_function_access_hold_xecore9_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine11 :: GPU Time Elapsed */
#define acmgt2__vector_engine11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine11 :: GPU Core Clocks */
#define acmgt2__vector_engine11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine11 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine11 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine11 :: XVE STALL ALUWR XECORE10 XVE0 THREAD0 */
#define acmgt2__vector_engine11__xve_stall_aluwr_xecore10_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine11 :: XVE STALL BARRIER XECORE10 XVE0 THREAD0 */
#define acmgt2__vector_engine11__xve_stall_barrier_xecore10_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine11 :: XVE STALL INSTFETCH XECORE10 XVE0 THREAD0 */
#define acmgt2__vector_engine11__xve_stall_instfetch_xecore10_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine11 :: XVE STALL OTHER XECORE10 XVE0 THREAD0 */
#define acmgt2__vector_engine11__xve_stall_other_xecore10_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine11 :: XVE STALL SBID XECORE10 XVE0 THREAD0 */
#define acmgt2__vector_engine11__xve_stall_sbid_xecore10_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine11 :: XVE STALL SENDWR XECORE10 XVE0 THREAD0 */
#define acmgt2__vector_engine11__xve_stall_sendwr_xecore10_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine11 :: XVE SHARED FUNCTION ACCESS HOLD XECORE10 XVE0 THREAD0 */
#define acmgt2__vector_engine11__xve_shared_function_access_hold_xecore10_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine12 :: GPU Time Elapsed */
#define acmgt2__vector_engine12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine12 :: GPU Core Clocks */
#define acmgt2__vector_engine12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine12 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine12 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine12 :: XVE STALL ALUWR XECORE11 XVE0 THREAD0 */
#define acmgt2__vector_engine12__xve_stall_aluwr_xecore11_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine12 :: XVE STALL BARRIER XECORE11 XVE0 THREAD0 */
#define acmgt2__vector_engine12__xve_stall_barrier_xecore11_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine12 :: XVE STALL INSTFETCH XECORE11 XVE0 THREAD0 */
#define acmgt2__vector_engine12__xve_stall_instfetch_xecore11_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine12 :: XVE STALL OTHER XECORE11 XVE0 THREAD0 */
#define acmgt2__vector_engine12__xve_stall_other_xecore11_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine12 :: XVE STALL SBID XECORE11 XVE0 THREAD0 */
#define acmgt2__vector_engine12__xve_stall_sbid_xecore11_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine12 :: XVE STALL SENDWR XECORE11 XVE0 THREAD0 */
#define acmgt2__vector_engine12__xve_stall_sendwr_xecore11_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine12 :: XVE SHARED FUNCTION ACCESS HOLD XECORE11 XVE0 THREAD0 */
#define acmgt2__vector_engine12__xve_shared_function_access_hold_xecore11_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine13 :: GPU Time Elapsed */
#define acmgt2__vector_engine13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine13 :: GPU Core Clocks */
#define acmgt2__vector_engine13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine13 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine13 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine13 :: XVE STALL ALUWR XECORE12 XVE0 THREAD0 */
#define acmgt2__vector_engine13__xve_stall_aluwr_xecore12_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine13 :: XVE STALL BARRIER XECORE12 XVE0 THREAD0 */
#define acmgt2__vector_engine13__xve_stall_barrier_xecore12_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine13 :: XVE STALL INSTFETCH XECORE12 XVE0 THREAD0 */
#define acmgt2__vector_engine13__xve_stall_instfetch_xecore12_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine13 :: XVE STALL OTHER XECORE12 XVE0 THREAD0 */
#define acmgt2__vector_engine13__xve_stall_other_xecore12_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine13 :: XVE STALL SBID XECORE12 XVE0 THREAD0 */
#define acmgt2__vector_engine13__xve_stall_sbid_xecore12_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine13 :: XVE STALL SENDWR XECORE12 XVE0 THREAD0 */
#define acmgt2__vector_engine13__xve_stall_sendwr_xecore12_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine13 :: XVE SHARED FUNCTION ACCESS HOLD XECORE12 XVE0 THREAD0 */
#define acmgt2__vector_engine13__xve_shared_function_access_hold_xecore12_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine14 :: GPU Time Elapsed */
#define acmgt2__vector_engine14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine14 :: GPU Core Clocks */
#define acmgt2__vector_engine14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine14 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine14 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine14 :: XVE STALL ALUWR XECORE13 XVE0 THREAD0 */
#define acmgt2__vector_engine14__xve_stall_aluwr_xecore13_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine14 :: XVE STALL BARRIER XECORE13 XVE0 THREAD0 */
#define acmgt2__vector_engine14__xve_stall_barrier_xecore13_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine14 :: XVE STALL INSTFETCH XECORE13 XVE0 THREAD0 */
#define acmgt2__vector_engine14__xve_stall_instfetch_xecore13_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine14 :: XVE STALL OTHER XECORE13 XVE0 THREAD0 */
#define acmgt2__vector_engine14__xve_stall_other_xecore13_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine14 :: XVE STALL SBID XECORE13 XVE0 THREAD0 */
#define acmgt2__vector_engine14__xve_stall_sbid_xecore13_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine14 :: XVE STALL SENDWR XECORE13 XVE0 THREAD0 */
#define acmgt2__vector_engine14__xve_stall_sendwr_xecore13_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine14 :: XVE SHARED FUNCTION ACCESS HOLD XECORE13 XVE0 THREAD0 */
#define acmgt2__vector_engine14__xve_shared_function_access_hold_xecore13_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine15 :: GPU Time Elapsed */
#define acmgt2__vector_engine15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine15 :: GPU Core Clocks */
#define acmgt2__vector_engine15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine15 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine15 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine15 :: XVE STALL ALUWR XECORE14 XVE0 THREAD0 */
#define acmgt2__vector_engine15__xve_stall_aluwr_xecore14_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine15 :: XVE STALL BARRIER XECORE14 XVE0 THREAD0 */
#define acmgt2__vector_engine15__xve_stall_barrier_xecore14_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine15 :: XVE STALL INSTFETCH XECORE14 XVE0 THREAD0 */
#define acmgt2__vector_engine15__xve_stall_instfetch_xecore14_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine15 :: XVE STALL OTHER XECORE14 XVE0 THREAD0 */
#define acmgt2__vector_engine15__xve_stall_other_xecore14_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine15 :: XVE STALL SBID XECORE14 XVE0 THREAD0 */
#define acmgt2__vector_engine15__xve_stall_sbid_xecore14_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine15 :: XVE STALL SENDWR XECORE14 XVE0 THREAD0 */
#define acmgt2__vector_engine15__xve_stall_sendwr_xecore14_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine15 :: XVE SHARED FUNCTION ACCESS HOLD XECORE14 XVE0 THREAD0 */
#define acmgt2__vector_engine15__xve_shared_function_access_hold_xecore14_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine16 :: GPU Time Elapsed */
#define acmgt2__vector_engine16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine16 :: GPU Core Clocks */
#define acmgt2__vector_engine16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine16 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine16 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine16 :: XVE STALL ALUWR XECORE15 XVE0 THREAD0 */
#define acmgt2__vector_engine16__xve_stall_aluwr_xecore15_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* VectorEngine16 :: XVE STALL BARRIER XECORE15 XVE0 THREAD0 */
#define acmgt2__vector_engine16__xve_stall_barrier_xecore15_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* VectorEngine16 :: XVE STALL INSTFETCH XECORE15 XVE0 THREAD0 */
#define acmgt2__vector_engine16__xve_stall_instfetch_xecore15_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* VectorEngine16 :: XVE STALL OTHER XECORE15 XVE0 THREAD0 */
#define acmgt2__vector_engine16__xve_stall_other_xecore15_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* VectorEngine16 :: XVE STALL SBID XECORE15 XVE0 THREAD0 */
#define acmgt2__vector_engine16__xve_stall_sbid_xecore15_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* VectorEngine16 :: XVE STALL SENDWR XECORE15 XVE0 THREAD0 */
#define acmgt2__vector_engine16__xve_stall_sendwr_xecore15_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* VectorEngine16 :: XVE SHARED FUNCTION ACCESS HOLD XECORE15 XVE0 THREAD0 */
#define acmgt2__vector_engine16__xve_shared_function_access_hold_xecore15_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* VectorEngine17 :: GPU Time Elapsed */
#define acmgt2__vector_engine17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine17 :: GPU Core Clocks */
#define acmgt2__vector_engine17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine17 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine17 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine17 :: ICACHE HIT BANK0 XECORE0 */
#define acmgt2__vector_engine17__icache_hit_bank0_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine17 :: ICACHE HIT BANK0 XECORE1 */
#define acmgt2__vector_engine17__icache_hit_bank0_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine17 :: ICACHE HIT BANK0 XECORE2 */
#define acmgt2__vector_engine17__icache_hit_bank0_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine17 :: ICACHE HIT BANK0 XECORE3 */
#define acmgt2__vector_engine17__icache_hit_bank0_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* VectorEngine17 :: ICACHE HIT BANK0 XECORE4 */
#define acmgt2__vector_engine17__icache_hit_bank0_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* VectorEngine17 :: ICACHE HIT BANK0 XECORE5 */
#define acmgt2__vector_engine17__icache_hit_bank0_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* VectorEngine17 :: ICACHE HIT BANK0 XECORE6 */
#define acmgt2__vector_engine17__icache_hit_bank0_xecore6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* VectorEngine17 :: ICACHE HIT BANK0 XECORE7 */
#define acmgt2__vector_engine17__icache_hit_bank0_xecore7__read \
   hsw__compute_extended__gpu_clocks__read

/* VectorEngine17 :: ICACHE MISS BANK0 XECORE0 */
#define acmgt2__vector_engine17__icache_miss_bank0_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* VectorEngine17 :: ICACHE MISS BANK0 XECORE1 */
#define acmgt2__vector_engine17__icache_miss_bank0_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* VectorEngine17 :: ICACHE MISS BANK0 XECORE2 */
#define acmgt2__vector_engine17__icache_miss_bank0_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* VectorEngine17 :: ICACHE MISS BANK0 XECORE3 */
#define acmgt2__vector_engine17__icache_miss_bank0_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* VectorEngine17 :: ICACHE MISS BANK0 XECORE4 */
#define acmgt2__vector_engine17__icache_miss_bank0_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* VectorEngine17 :: ICACHE MISS BANK0 XECORE5 */
#define acmgt2__vector_engine17__icache_miss_bank0_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* VectorEngine17 :: ICACHE MISS BANK0 XECORE6 */
#define acmgt2__vector_engine17__icache_miss_bank0_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* VectorEngine17 :: ICACHE MISS BANK0 XECORE7 */
#define acmgt2__vector_engine17__icache_miss_bank0_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* VectorEngine18 :: GPU Time Elapsed */
#define acmgt2__vector_engine18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine18 :: GPU Core Clocks */
#define acmgt2__vector_engine18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine18 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine18 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine18 :: ICACHE HIT BANK0 XECORE8 */
#define acmgt2__vector_engine18__icache_hit_bank0_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine18 :: ICACHE HIT BANK0 XECORE9 */
#define acmgt2__vector_engine18__icache_hit_bank0_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine18 :: ICACHE HIT BANK0 XECORE10 */
#define acmgt2__vector_engine18__icache_hit_bank0_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine18 :: ICACHE HIT BANK0 XECORE11 */
#define acmgt2__vector_engine18__icache_hit_bank0_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* VectorEngine18 :: ICACHE HIT BANK0 XECORE12 */
#define acmgt2__vector_engine18__icache_hit_bank0_xecore12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* VectorEngine18 :: ICACHE HIT BANK0 XECORE13 */
#define acmgt2__vector_engine18__icache_hit_bank0_xecore13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* VectorEngine18 :: ICACHE HIT BANK0 XECORE14 */
#define acmgt2__vector_engine18__icache_hit_bank0_xecore14__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* VectorEngine18 :: ICACHE HIT BANK0 XECORE15 */
#define acmgt2__vector_engine18__icache_hit_bank0_xecore15__read \
   hsw__compute_extended__gpu_clocks__read

/* VectorEngine18 :: ICACHE MISS BANK0 XECORE8 */
#define acmgt2__vector_engine18__icache_miss_bank0_xecore8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* VectorEngine18 :: ICACHE MISS BANK0 XECORE9 */
#define acmgt2__vector_engine18__icache_miss_bank0_xecore9__read \
   hsw__memory_reads__llc_read_accesses__read

/* VectorEngine18 :: ICACHE MISS BANK0 XECORE10 */
#define acmgt2__vector_engine18__icache_miss_bank0_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* VectorEngine18 :: ICACHE MISS BANK0 XECORE11 */
#define acmgt2__vector_engine18__icache_miss_bank0_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* VectorEngine18 :: ICACHE MISS BANK0 XECORE12 */
#define acmgt2__vector_engine18__icache_miss_bank0_xecore12__read \
   hsw__compute_extended__untyped_reads0__read

/* VectorEngine18 :: ICACHE MISS BANK0 XECORE13 */
#define acmgt2__vector_engine18__icache_miss_bank0_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* VectorEngine18 :: ICACHE MISS BANK0 XECORE14 */
#define acmgt2__vector_engine18__icache_miss_bank0_xecore14__read \
   hsw__compute_extended__untyped_writes0__read

/* VectorEngine18 :: ICACHE MISS BANK0 XECORE15 */
#define acmgt2__vector_engine18__icache_miss_bank0_xecore15__read \
   hsw__compute_extended__typed_writes0__read

/* VectorEngine19 :: GPU Time Elapsed */
#define acmgt2__vector_engine19__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine19 :: GPU Core Clocks */
#define acmgt2__vector_engine19__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine19 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine19__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine19 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine19__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine19 :: ICACHE HIT BANK1 XECORE0 */
#define acmgt2__vector_engine19__icache_hit_bank1_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine19 :: ICACHE HIT BANK1 XECORE1 */
#define acmgt2__vector_engine19__icache_hit_bank1_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine19 :: ICACHE HIT BANK1 XECORE2 */
#define acmgt2__vector_engine19__icache_hit_bank1_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine19 :: ICACHE HIT BANK1 XECORE3 */
#define acmgt2__vector_engine19__icache_hit_bank1_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* VectorEngine19 :: ICACHE HIT BANK1 XECORE4 */
#define acmgt2__vector_engine19__icache_hit_bank1_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* VectorEngine19 :: ICACHE HIT BANK1 XECORE5 */
#define acmgt2__vector_engine19__icache_hit_bank1_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* VectorEngine19 :: ICACHE HIT BANK1 XECORE6 */
#define acmgt2__vector_engine19__icache_hit_bank1_xecore6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* VectorEngine19 :: ICACHE HIT BANK1 XECORE7 */
#define acmgt2__vector_engine19__icache_hit_bank1_xecore7__read \
   hsw__compute_extended__gpu_clocks__read

/* VectorEngine19 :: ICACHE MISS BANK1 XECORE0 */
#define acmgt2__vector_engine19__icache_miss_bank1_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* VectorEngine19 :: ICACHE MISS BANK1 XECORE1 */
#define acmgt2__vector_engine19__icache_miss_bank1_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* VectorEngine19 :: ICACHE MISS BANK1 XECORE2 */
#define acmgt2__vector_engine19__icache_miss_bank1_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* VectorEngine19 :: ICACHE MISS BANK1 XECORE3 */
#define acmgt2__vector_engine19__icache_miss_bank1_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* VectorEngine19 :: ICACHE MISS BANK1 XECORE4 */
#define acmgt2__vector_engine19__icache_miss_bank1_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* VectorEngine19 :: ICACHE MISS BANK1 XECORE5 */
#define acmgt2__vector_engine19__icache_miss_bank1_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* VectorEngine19 :: ICACHE MISS BANK1 XECORE6 */
#define acmgt2__vector_engine19__icache_miss_bank1_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* VectorEngine19 :: ICACHE MISS BANK1 XECORE7 */
#define acmgt2__vector_engine19__icache_miss_bank1_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* VectorEngine20 :: GPU Time Elapsed */
#define acmgt2__vector_engine20__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine20 :: GPU Core Clocks */
#define acmgt2__vector_engine20__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine20 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine20__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine20 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine20__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine20 :: ICACHE HIT BANK1 XECORE8 */
#define acmgt2__vector_engine20__icache_hit_bank1_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine20 :: ICACHE HIT BANK1 XECORE9 */
#define acmgt2__vector_engine20__icache_hit_bank1_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine20 :: ICACHE HIT BANK1 XECORE10 */
#define acmgt2__vector_engine20__icache_hit_bank1_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine20 :: ICACHE HIT BANK1 XECORE11 */
#define acmgt2__vector_engine20__icache_hit_bank1_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* VectorEngine20 :: ICACHE HIT BANK1 XECORE12 */
#define acmgt2__vector_engine20__icache_hit_bank1_xecore12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* VectorEngine20 :: ICACHE HIT BANK1 XECORE13 */
#define acmgt2__vector_engine20__icache_hit_bank1_xecore13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* VectorEngine20 :: ICACHE HIT BANK1 XECORE14 */
#define acmgt2__vector_engine20__icache_hit_bank1_xecore14__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* VectorEngine20 :: ICACHE HIT BANK1 XECORE15 */
#define acmgt2__vector_engine20__icache_hit_bank1_xecore15__read \
   hsw__compute_extended__gpu_clocks__read

/* VectorEngine20 :: ICACHE MISS BANK1 XECORE8 */
#define acmgt2__vector_engine20__icache_miss_bank1_xecore8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* VectorEngine20 :: ICACHE MISS BANK1 XECORE9 */
#define acmgt2__vector_engine20__icache_miss_bank1_xecore9__read \
   hsw__memory_reads__llc_read_accesses__read

/* VectorEngine20 :: ICACHE MISS BANK1 XECORE10 */
#define acmgt2__vector_engine20__icache_miss_bank1_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* VectorEngine20 :: ICACHE MISS BANK1 XECORE11 */
#define acmgt2__vector_engine20__icache_miss_bank1_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* VectorEngine20 :: ICACHE MISS BANK1 XECORE12 */
#define acmgt2__vector_engine20__icache_miss_bank1_xecore12__read \
   hsw__compute_extended__untyped_reads0__read

/* VectorEngine20 :: ICACHE MISS BANK1 XECORE13 */
#define acmgt2__vector_engine20__icache_miss_bank1_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* VectorEngine20 :: ICACHE MISS BANK1 XECORE14 */
#define acmgt2__vector_engine20__icache_miss_bank1_xecore14__read \
   hsw__compute_extended__untyped_writes0__read

/* VectorEngine20 :: ICACHE MISS BANK1 XECORE15 */
#define acmgt2__vector_engine20__icache_miss_bank1_xecore15__read \
   hsw__compute_extended__typed_writes0__read

/* VectorEngine21 :: GPU Time Elapsed */
#define acmgt2__vector_engine21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine21 :: GPU Core Clocks */
#define acmgt2__vector_engine21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine21 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine21 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine21 :: ICACHE HIT BANK2 XECORE0 */
#define acmgt2__vector_engine21__icache_hit_bank2_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine21 :: ICACHE HIT BANK2 XECORE1 */
#define acmgt2__vector_engine21__icache_hit_bank2_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine21 :: ICACHE HIT BANK2 XECORE2 */
#define acmgt2__vector_engine21__icache_hit_bank2_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine21 :: ICACHE HIT BANK2 XECORE3 */
#define acmgt2__vector_engine21__icache_hit_bank2_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* VectorEngine21 :: ICACHE HIT BANK2 XECORE4 */
#define acmgt2__vector_engine21__icache_hit_bank2_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* VectorEngine21 :: ICACHE HIT BANK2 XECORE5 */
#define acmgt2__vector_engine21__icache_hit_bank2_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* VectorEngine21 :: ICACHE HIT BANK2 XECORE6 */
#define acmgt2__vector_engine21__icache_hit_bank2_xecore6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* VectorEngine21 :: ICACHE HIT BANK2 XECORE7 */
#define acmgt2__vector_engine21__icache_hit_bank2_xecore7__read \
   hsw__compute_extended__gpu_clocks__read

/* VectorEngine21 :: ICACHE MISS BANK2 XECORE0 */
#define acmgt2__vector_engine21__icache_miss_bank2_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* VectorEngine21 :: ICACHE MISS BANK2 XECORE1 */
#define acmgt2__vector_engine21__icache_miss_bank2_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* VectorEngine21 :: ICACHE MISS BANK2 XECORE2 */
#define acmgt2__vector_engine21__icache_miss_bank2_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* VectorEngine21 :: ICACHE MISS BANK2 XECORE3 */
#define acmgt2__vector_engine21__icache_miss_bank2_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* VectorEngine21 :: ICACHE MISS BANK2 XECORE4 */
#define acmgt2__vector_engine21__icache_miss_bank2_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* VectorEngine21 :: ICACHE MISS BANK2 XECORE5 */
#define acmgt2__vector_engine21__icache_miss_bank2_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* VectorEngine21 :: ICACHE MISS BANK2 XECORE6 */
#define acmgt2__vector_engine21__icache_miss_bank2_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* VectorEngine21 :: ICACHE MISS BANK2 XECORE7 */
#define acmgt2__vector_engine21__icache_miss_bank2_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* VectorEngine22 :: GPU Time Elapsed */
#define acmgt2__vector_engine22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine22 :: GPU Core Clocks */
#define acmgt2__vector_engine22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine22 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine22 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine22 :: ICACHE HIT BANK2 XECORE8 */
#define acmgt2__vector_engine22__icache_hit_bank2_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine22 :: ICACHE HIT BANK2 XECORE9 */
#define acmgt2__vector_engine22__icache_hit_bank2_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine22 :: ICACHE HIT BANK2 XECORE10 */
#define acmgt2__vector_engine22__icache_hit_bank2_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine22 :: ICACHE HIT BANK2 XECORE11 */
#define acmgt2__vector_engine22__icache_hit_bank2_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* VectorEngine22 :: ICACHE HIT BANK2 XECORE12 */
#define acmgt2__vector_engine22__icache_hit_bank2_xecore12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* VectorEngine22 :: ICACHE HIT BANK2 XECORE13 */
#define acmgt2__vector_engine22__icache_hit_bank2_xecore13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* VectorEngine22 :: ICACHE HIT BANK2 XECORE14 */
#define acmgt2__vector_engine22__icache_hit_bank2_xecore14__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* VectorEngine22 :: ICACHE HIT BANK2 XECORE15 */
#define acmgt2__vector_engine22__icache_hit_bank2_xecore15__read \
   hsw__compute_extended__gpu_clocks__read

/* VectorEngine22 :: ICACHE MISS BANK2 XECORE8 */
#define acmgt2__vector_engine22__icache_miss_bank2_xecore8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* VectorEngine22 :: ICACHE MISS BANK2 XECORE9 */
#define acmgt2__vector_engine22__icache_miss_bank2_xecore9__read \
   hsw__memory_reads__llc_read_accesses__read

/* VectorEngine22 :: ICACHE MISS BANK2 XECORE10 */
#define acmgt2__vector_engine22__icache_miss_bank2_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* VectorEngine22 :: ICACHE MISS BANK2 XECORE11 */
#define acmgt2__vector_engine22__icache_miss_bank2_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* VectorEngine22 :: ICACHE MISS BANK2 XECORE12 */
#define acmgt2__vector_engine22__icache_miss_bank2_xecore12__read \
   hsw__compute_extended__untyped_reads0__read

/* VectorEngine22 :: ICACHE MISS BANK2 XECORE13 */
#define acmgt2__vector_engine22__icache_miss_bank2_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* VectorEngine22 :: ICACHE MISS BANK2 XECORE14 */
#define acmgt2__vector_engine22__icache_miss_bank2_xecore14__read \
   hsw__compute_extended__untyped_writes0__read

/* VectorEngine22 :: ICACHE MISS BANK2 XECORE15 */
#define acmgt2__vector_engine22__icache_miss_bank2_xecore15__read \
   hsw__compute_extended__typed_writes0__read

/* VectorEngine23 :: GPU Time Elapsed */
#define acmgt2__vector_engine23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine23 :: GPU Core Clocks */
#define acmgt2__vector_engine23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine23 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine23 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine23 :: ICACHE HIT BANK3 XECORE0 */
#define acmgt2__vector_engine23__icache_hit_bank3_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine23 :: ICACHE HIT BANK3 XECORE1 */
#define acmgt2__vector_engine23__icache_hit_bank3_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine23 :: ICACHE HIT BANK3 XECORE2 */
#define acmgt2__vector_engine23__icache_hit_bank3_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine23 :: ICACHE HIT BANK3 XECORE3 */
#define acmgt2__vector_engine23__icache_hit_bank3_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* VectorEngine23 :: ICACHE HIT BANK3 XECORE4 */
#define acmgt2__vector_engine23__icache_hit_bank3_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* VectorEngine23 :: ICACHE HIT BANK3 XECORE5 */
#define acmgt2__vector_engine23__icache_hit_bank3_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* VectorEngine23 :: ICACHE HIT BANK3 XECORE6 */
#define acmgt2__vector_engine23__icache_hit_bank3_xecore6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* VectorEngine23 :: ICACHE HIT BANK3 XECORE7 */
#define acmgt2__vector_engine23__icache_hit_bank3_xecore7__read \
   hsw__compute_extended__gpu_clocks__read

/* VectorEngine23 :: ICACHE MISS BANK3 XECORE0 */
#define acmgt2__vector_engine23__icache_miss_bank3_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* VectorEngine23 :: ICACHE MISS BANK3 XECORE1 */
#define acmgt2__vector_engine23__icache_miss_bank3_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* VectorEngine23 :: ICACHE MISS BANK3 XECORE2 */
#define acmgt2__vector_engine23__icache_miss_bank3_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* VectorEngine23 :: ICACHE MISS BANK3 XECORE3 */
#define acmgt2__vector_engine23__icache_miss_bank3_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* VectorEngine23 :: ICACHE MISS BANK3 XECORE4 */
#define acmgt2__vector_engine23__icache_miss_bank3_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* VectorEngine23 :: ICACHE MISS BANK3 XECORE5 */
#define acmgt2__vector_engine23__icache_miss_bank3_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* VectorEngine23 :: ICACHE MISS BANK3 XECORE6 */
#define acmgt2__vector_engine23__icache_miss_bank3_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* VectorEngine23 :: ICACHE MISS BANK3 XECORE7 */
#define acmgt2__vector_engine23__icache_miss_bank3_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* VectorEngine24 :: GPU Time Elapsed */
#define acmgt2__vector_engine24__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine24 :: GPU Core Clocks */
#define acmgt2__vector_engine24__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine24 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine24__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine24 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine24__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine24 :: ICACHE HIT BANK3 XECORE8 */
#define acmgt2__vector_engine24__icache_hit_bank3_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine24 :: ICACHE HIT BANK3 XECORE9 */
#define acmgt2__vector_engine24__icache_hit_bank3_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine24 :: ICACHE HIT BANK3 XECORE10 */
#define acmgt2__vector_engine24__icache_hit_bank3_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine24 :: ICACHE HIT BANK3 XECORE11 */
#define acmgt2__vector_engine24__icache_hit_bank3_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* VectorEngine24 :: ICACHE HIT BANK3 XECORE12 */
#define acmgt2__vector_engine24__icache_hit_bank3_xecore12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* VectorEngine24 :: ICACHE HIT BANK3 XECORE13 */
#define acmgt2__vector_engine24__icache_hit_bank3_xecore13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* VectorEngine24 :: ICACHE HIT BANK3 XECORE14 */
#define acmgt2__vector_engine24__icache_hit_bank3_xecore14__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* VectorEngine24 :: ICACHE HIT BANK3 XECORE15 */
#define acmgt2__vector_engine24__icache_hit_bank3_xecore15__read \
   hsw__compute_extended__gpu_clocks__read

/* VectorEngine24 :: ICACHE MISS BANK3 XECORE8 */
#define acmgt2__vector_engine24__icache_miss_bank3_xecore8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* VectorEngine24 :: ICACHE MISS BANK3 XECORE9 */
#define acmgt2__vector_engine24__icache_miss_bank3_xecore9__read \
   hsw__memory_reads__llc_read_accesses__read

/* VectorEngine24 :: ICACHE MISS BANK3 XECORE10 */
#define acmgt2__vector_engine24__icache_miss_bank3_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* VectorEngine24 :: ICACHE MISS BANK3 XECORE11 */
#define acmgt2__vector_engine24__icache_miss_bank3_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* VectorEngine24 :: ICACHE MISS BANK3 XECORE12 */
#define acmgt2__vector_engine24__icache_miss_bank3_xecore12__read \
   hsw__compute_extended__untyped_reads0__read

/* VectorEngine24 :: ICACHE MISS BANK3 XECORE13 */
#define acmgt2__vector_engine24__icache_miss_bank3_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* VectorEngine24 :: ICACHE MISS BANK3 XECORE14 */
#define acmgt2__vector_engine24__icache_miss_bank3_xecore14__read \
   hsw__compute_extended__untyped_writes0__read

/* VectorEngine24 :: ICACHE MISS BANK3 XECORE15 */
#define acmgt2__vector_engine24__icache_miss_bank3_xecore15__read \
   hsw__compute_extended__typed_writes0__read

/* VectorEngine25 :: GPU Time Elapsed */
#define acmgt2__vector_engine25__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine25 :: GPU Core Clocks */
#define acmgt2__vector_engine25__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine25 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine25__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine25 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine25__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine25 :: XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0 */
#define acmgt2__vector_engine25__xve_multiple_pipe_active_xecore0_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* VectorEngine25 :: XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0 */
#define acmgt2__vector_engine25__xve_multiple_pipe_active_xecore1_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* VectorEngine25 :: XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0 */
#define acmgt2__vector_engine25__xve_multiple_pipe_active_xecore2_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* VectorEngine25 :: XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0 */
#define acmgt2__vector_engine25__xve_multiple_pipe_active_xecore3_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* VectorEngine26 :: GPU Time Elapsed */
#define acmgt2__vector_engine26__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine26 :: GPU Core Clocks */
#define acmgt2__vector_engine26__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine26 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine26__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine26 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine26__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine26 :: XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0 */
#define acmgt2__vector_engine26__xve_multiple_pipe_active_xecore4_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* VectorEngine26 :: XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0 */
#define acmgt2__vector_engine26__xve_multiple_pipe_active_xecore5_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* VectorEngine26 :: XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0 */
#define acmgt2__vector_engine26__xve_multiple_pipe_active_xecore6_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* VectorEngine26 :: XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0 */
#define acmgt2__vector_engine26__xve_multiple_pipe_active_xecore7_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* VectorEngine27 :: GPU Time Elapsed */
#define acmgt2__vector_engine27__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine27 :: GPU Core Clocks */
#define acmgt2__vector_engine27__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine27 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine27__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine27 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine27__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine27 :: XVE MULTIPLE PIPE ACTIVE XECORE8 XVE0 */
#define acmgt2__vector_engine27__xve_multiple_pipe_active_xecore8_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* VectorEngine27 :: XVE MULTIPLE PIPE ACTIVE XECORE9 XVE0 */
#define acmgt2__vector_engine27__xve_multiple_pipe_active_xecore9_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* VectorEngine27 :: XVE MULTIPLE PIPE ACTIVE XECORE10 XVE0 */
#define acmgt2__vector_engine27__xve_multiple_pipe_active_xecore10_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* VectorEngine27 :: XVE MULTIPLE PIPE ACTIVE XECORE11 XVE0 */
#define acmgt2__vector_engine27__xve_multiple_pipe_active_xecore11_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* VectorEngine28 :: GPU Time Elapsed */
#define acmgt2__vector_engine28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine28 :: GPU Core Clocks */
#define acmgt2__vector_engine28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine28 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine28 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine28 :: XVE MULTIPLE PIPE ACTIVE XECORE12 XVE0 */
#define acmgt2__vector_engine28__xve_multiple_pipe_active_xecore12_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* VectorEngine28 :: XVE MULTIPLE PIPE ACTIVE XECORE13 XVE0 */
#define acmgt2__vector_engine28__xve_multiple_pipe_active_xecore13_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* VectorEngine28 :: XVE MULTIPLE PIPE ACTIVE XECORE14 XVE0 */
#define acmgt2__vector_engine28__xve_multiple_pipe_active_xecore14_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* VectorEngine28 :: XVE MULTIPLE PIPE ACTIVE XECORE15 XVE0 */
#define acmgt2__vector_engine28__xve_multiple_pipe_active_xecore15_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* VectorEngine29 :: GPU Time Elapsed */
#define acmgt2__vector_engine29__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine29 :: GPU Core Clocks */
#define acmgt2__vector_engine29__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine29 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine29__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine29 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine29__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine29 :: XVE INST ISSUED ALL XECORE0 XVE0 */
#define acmgt2__vector_engine29__xve_inst_issued_all_xecore0_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine29 :: XVE INST ISSUED ALL XECORE1 XVE0 */
#define acmgt2__vector_engine29__xve_inst_issued_all_xecore1_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine29 :: XVE INST ISSUED ALL XECORE2 XVE0 */
#define acmgt2__vector_engine29__xve_inst_issued_all_xecore2_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine30 :: GPU Time Elapsed */
#define acmgt2__vector_engine30__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine30 :: GPU Core Clocks */
#define acmgt2__vector_engine30__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine30 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine30__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine30 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine30__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine30 :: XVE INST ISSUED ALL XECORE3 XVE0 */
#define acmgt2__vector_engine30__xve_inst_issued_all_xecore3_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine30 :: XVE INST ISSUED ALL XECORE4 XVE0 */
#define acmgt2__vector_engine30__xve_inst_issued_all_xecore4_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine30 :: XVE INST ISSUED ALL XECORE5 XVE0 */
#define acmgt2__vector_engine30__xve_inst_issued_all_xecore5_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine31 :: GPU Time Elapsed */
#define acmgt2__vector_engine31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine31 :: GPU Core Clocks */
#define acmgt2__vector_engine31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine31 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine31 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine31 :: XVE INST ISSUED ALL XECORE6 XVE0 */
#define acmgt2__vector_engine31__xve_inst_issued_all_xecore6_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine31 :: XVE INST ISSUED ALL XECORE7 XVE0 */
#define acmgt2__vector_engine31__xve_inst_issued_all_xecore7_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine31 :: XVE INST ISSUED ALL XECORE8 XVE0 */
#define acmgt2__vector_engine31__xve_inst_issued_all_xecore8_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine32 :: GPU Time Elapsed */
#define acmgt2__vector_engine32__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine32 :: GPU Core Clocks */
#define acmgt2__vector_engine32__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine32 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine32__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine32 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine32__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine32 :: XVE INST ISSUED ALL XECORE9 XVE0 */
#define acmgt2__vector_engine32__xve_inst_issued_all_xecore9_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine32 :: XVE INST ISSUED ALL XECORE10 XVE0 */
#define acmgt2__vector_engine32__xve_inst_issued_all_xecore10_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine32 :: XVE INST ISSUED ALL XECORE11 XVE0 */
#define acmgt2__vector_engine32__xve_inst_issued_all_xecore11_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine33 :: GPU Time Elapsed */
#define acmgt2__vector_engine33__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine33 :: GPU Core Clocks */
#define acmgt2__vector_engine33__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine33 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine33__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine33 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine33__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine33 :: XVE INST ISSUED ALL XECORE12 XVE0 */
#define acmgt2__vector_engine33__xve_inst_issued_all_xecore12_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine33 :: XVE INST ISSUED ALL XECORE13 XVE0 */
#define acmgt2__vector_engine33__xve_inst_issued_all_xecore13_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* VectorEngine33 :: XVE INST ISSUED ALL XECORE14 XVE0 */
#define acmgt2__vector_engine33__xve_inst_issued_all_xecore14_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* VectorEngine34 :: GPU Time Elapsed */
#define acmgt2__vector_engine34__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine34 :: GPU Core Clocks */
#define acmgt2__vector_engine34__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine34 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine34__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine34 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine34__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine34 :: XVE INST ISSUED ALL XECORE15 XVE0 */
#define acmgt2__vector_engine34__xve_inst_issued_all_xecore15_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* VectorEngine35 :: GPU Time Elapsed */
#define acmgt2__vector_engine35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine35 :: GPU Core Clocks */
#define acmgt2__vector_engine35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine35 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine35 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine35 :: XVE ACTIVE */
#define acmgt2__vector_engine35__xve_active__read \
   bdw__render_basic__eu_active__read

/* VectorEngine35 :: XVE STALL */
#define acmgt2__vector_engine35__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* VectorEngine35 :: XVE THREADS OCCUPANCY ALL */
#define acmgt2__vector_engine35__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* VectorEngine35 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt2__vector_engine35__xve_inst_executed_alu0_all__read \
   hsw__render_basic__hs_threads__read

/* VectorEngine35 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt2__vector_engine35__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine35 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt2__vector_engine35__xve_inst_executed_alu1_all__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* VectorEngine35 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt2__vector_engine35__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine35 :: XVE INST EXECUTED XMX ALL */
#define acmgt2__vector_engine35__xve_inst_executed_xmx_all__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* VectorEngine35 :: XVE INST EXECUTED XMX ALL */
#define acmgt2__vector_engine35__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine35 :: XVE INST EXECUTED SEND ALL */
#define acmgt2__vector_engine35__xve_inst_executed_send_all__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* VectorEngine35 :: XVE INST EXECUTED SEND ALL */
#define acmgt2__vector_engine35__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine35 :: XVE INST EXECUTED CONTROL ALL */
#define acmgt2__vector_engine35__xve_inst_executed_control_all__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* VectorEngine35 :: XVE INST EXECUTED CONTROL ALL */
#define acmgt2__vector_engine35__xve_inst_executed_control_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine35 :: XVE PIPE ALU0 AND ALU1 ACTIVE */
#define acmgt2__vector_engine35__xve_pipe_alu0_and_alu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* VectorEngine35 :: XVE PIPE ALU0 AND XMX ACTIVE */
#define acmgt2__vector_engine35__xve_pipe_alu0_and_xmx_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* VectorEngine35 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define acmgt2__vector_engine35__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* VectorEngine35 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define acmgt2__vector_engine35__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* VectorEngine35 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define acmgt2__vector_engine35__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__vs_send_active__read

/* VectorEngine35 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define acmgt2__vector_engine35__xve_inst_executed_send_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* VectorEngine35 :: XVE INST EXECUTED CONTROL ALL UTILIZATION */
#define acmgt2__vector_engine35__xve_inst_executed_control_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* VectorEngine35 :: XVE ACTIVE CYCLES */
#define acmgt2__vector_engine35__xve_active_cycles__read \
   acmgt1__ext1000__xve_active_cycles__read

/* VectorEngine35 :: XVE ACTIVE CYCLES */
#define acmgt2__vector_engine35__xve_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine35 :: XVE STALL CYCLES */
#define acmgt2__vector_engine35__xve_stall_cycles__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* VectorEngine35 :: XVE STALL CYCLES */
#define acmgt2__vector_engine35__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine35 :: XVE THREADS OCCUPANCY CYCLES ALL */
static uint64_t
acmgt2__vector_engine35__xve_threads_occupancy_cycles_all__read(UNUSED struct intel_perf_config *perf,
                                                                const struct intel_perf_query_info *query,
                                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: 8  A 9 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 9];
   uint64_t tmp1 = 8 * tmp0;

   return tmp1;
}

/* VectorEngine35 :: XVE THREADS OCCUPANCY CYCLES ALL */
#define acmgt2__vector_engine35__xve_threads_occupancy_cycles_all__max \
   acmgt1__ext1000__xve_threads_occupancy_cycles_all__max

/* VectorEngine35 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
#define acmgt2__vector_engine35__xve_pipe_alu0_and_alu1_active_cycles__read \
   hsw__render_basic__ds_threads__read

/* VectorEngine35 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
#define acmgt2__vector_engine35__xve_pipe_alu0_and_alu1_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine35 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define acmgt2__vector_engine35__xve_pipe_alu0_and_xmx_active_cycles__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* VectorEngine35 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define acmgt2__vector_engine35__xve_pipe_alu0_and_xmx_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: GPU Time Elapsed */
#define acmgt2__vector_engine36__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine36 :: GPU Core Clocks */
#define acmgt2__vector_engine36__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine36 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine36__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine36 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine36__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine36 :: XVE INST EXECUTED ALU0 VS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 VS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU0 HS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_hs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 HS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU0 DS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_ds__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 DS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU0 FS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_ps__read \
   hsw__render_basic__hs_threads__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 FS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU0 CS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_cs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 CS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_async_cs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU1 VS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_vs__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 VS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU1 HS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_hs__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 HS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU1 DS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_ds__read \
   hsw__render_basic__ds_threads__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 DS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU1 FS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_ps__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 FS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU1 CS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_cs__read \
   acmgt1__ext1001__xve_inst_executed_alu1_cs__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 CS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU1 ASYNC CS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_async_cs__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 ASYNC CS */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine36 :: XVE INST EXECUTED ALU0 VS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_vs_utilization__read \
   bdw__render_basic__eu_active__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 HS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_hs_utilization__read \
   bdw__render_basic__eu_stall__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 DS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_ds_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 FS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_ps_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 CS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_cs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* VectorEngine36 :: XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu0_async_cs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 VS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_vs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 HS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_hs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 DS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_ds_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 FS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_ps_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 CS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_cs_utilization__read \
   bdw__render_basic__ps_send_active__read

/* VectorEngine36 :: XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION */
#define acmgt2__vector_engine36__xve_inst_executed_alu1_async_cs_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* VectorEngine37 :: GPU Time Elapsed */
#define acmgt2__vector_engine37__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine37 :: GPU Core Clocks */
#define acmgt2__vector_engine37__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine37 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine37__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine37 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine37__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine37 :: XVE INST EXECUTED ALU0 RT AHS UTILIZATION */
#define acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ahs_utilization__read \
   bdw__render_basic__eu_active__read

/* VectorEngine37 :: XVE INST EXECUTED ALU1 RT AHS UTILIZATION */
#define acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ahs_utilization__read \
   bdw__render_basic__eu_stall__read

/* VectorEngine37 :: XVE INST EXECUTED SEND RT AHS UTILIZATION */
#define acmgt2__vector_engine37__xve_inst_executed_send_rt_ahs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* VectorEngine37 :: XVE INST EXECUTED ALU0 RT CHS UTILIZATION */
#define acmgt2__vector_engine37__xve_inst_executed_alu0_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* VectorEngine37 :: XVE INST EXECUTED ALU1 RT CHS UTILIZATION */
#define acmgt2__vector_engine37__xve_inst_executed_alu1_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* VectorEngine37 :: XVE INST EXECUTED SEND RT CHS UTILIZATION */
#define acmgt2__vector_engine37__xve_inst_executed_send_rt_chs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* VectorEngine37 :: XVE INST EXECUTED ALU0 RT MS UTILIZATION */
#define acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* VectorEngine37 :: XVE INST EXECUTED ALU1 RT MS UTILIZATION */
#define acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* VectorEngine37 :: XVE INST EXECUTED SEND RT MS UTILIZATION */
#define acmgt2__vector_engine37__xve_inst_executed_send_rt_ms_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* VectorEngine37 :: XVE INST EXECUTED ALU0 RT AHS */
#define acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ahs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* VectorEngine37 :: XVE INST EXECUTED ALU0 RT AHS */
#define acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine37 :: XVE INST EXECUTED ALU1 RT AHS */
#define acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ahs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* VectorEngine37 :: XVE INST EXECUTED ALU1 RT AHS */
#define acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine37 :: XVE INST EXECUTED SEND RT AHS */
#define acmgt2__vector_engine37__xve_inst_executed_send_rt_ahs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* VectorEngine37 :: XVE INST EXECUTED SEND RT AHS */
#define acmgt2__vector_engine37__xve_inst_executed_send_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine37 :: XVE INST EXECUTED ALU0 RT CHS */
#define acmgt2__vector_engine37__xve_inst_executed_alu0_rt_chs__read \
   hsw__render_basic__hs_threads__read

/* VectorEngine37 :: XVE INST EXECUTED ALU0 RT CHS */
#define acmgt2__vector_engine37__xve_inst_executed_alu0_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine37 :: XVE INST EXECUTED ALU1 RT CHS */
#define acmgt2__vector_engine37__xve_inst_executed_alu1_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* VectorEngine37 :: XVE INST EXECUTED ALU1 RT CHS */
#define acmgt2__vector_engine37__xve_inst_executed_alu1_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine37 :: XVE INST EXECUTED SEND RT CHS */
#define acmgt2__vector_engine37__xve_inst_executed_send_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* VectorEngine37 :: XVE INST EXECUTED SEND RT CHS */
#define acmgt2__vector_engine37__xve_inst_executed_send_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine37 :: XVE INST EXECUTED ALU0 RT MS */
#define acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* VectorEngine37 :: XVE INST EXECUTED ALU0 RT MS */
#define acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine37 :: XVE INST EXECUTED ALU1 RT MS */
#define acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* VectorEngine37 :: XVE INST EXECUTED ALU1 RT MS */
#define acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine37 :: XVE INST EXECUTED SEND RT MS */
#define acmgt2__vector_engine37__xve_inst_executed_send_rt_ms__read \
   hsw__render_basic__ds_threads__read

/* VectorEngine37 :: XVE INST EXECUTED SEND RT MS */
#define acmgt2__vector_engine37__xve_inst_executed_send_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: GPU Time Elapsed */
#define acmgt2__vector_engine38__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine38 :: GPU Core Clocks */
#define acmgt2__vector_engine38__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine38 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine38__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine38 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine38__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine38 :: XVE STALL */
#define acmgt2__vector_engine38__xve_stall__read \
   bdw__render_basic__eu_active__read

/* VectorEngine38 :: XVE STALL ASYNC CS */
#define acmgt2__vector_engine38__xve_stall_async_cs__read \
   bdw__render_basic__eu_stall__read

/* VectorEngine38 :: XVE STALL CS */
#define acmgt2__vector_engine38__xve_stall_cs__read \
   bdw__render_basic__eu_fpu_both_active__read

/* VectorEngine38 :: XVE STALL DS */
#define acmgt2__vector_engine38__xve_stall_ds__read \
   bdw__render_basic__vs_fpu0_active__read

/* VectorEngine38 :: XVE STALL HS */
#define acmgt2__vector_engine38__xve_stall_hs__read \
   bdw__render_basic__vs_fpu1_active__read

/* VectorEngine38 :: XVE STALL MS */
#define acmgt2__vector_engine38__xve_stall_ms__read \
   bdw__render_basic__vs_send_active__read

/* VectorEngine38 :: XVE STALL FS */
#define acmgt2__vector_engine38__xve_stall_ps__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* VectorEngine38 :: XVE STALL TS */
#define acmgt2__vector_engine38__xve_stall_ts__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* VectorEngine38 :: XVE STALL VS */
#define acmgt2__vector_engine38__xve_stall_vs__read \
   bdw__render_basic__ps_fpu0_active__read

/* VectorEngine38 :: XVE STALL RT */
#define acmgt2__vector_engine38__xve_stall_rt__read \
   bdw__render_basic__ps_fpu1_active__read

/* VectorEngine38 :: XVE STALL CYCLES */
#define acmgt2__vector_engine38__xve_stall_cycles__read \
   acmgt1__ext1000__xve_active_cycles__read

/* VectorEngine38 :: XVE STALL CYCLES */
#define acmgt2__vector_engine38__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: XVE STALL CYCLES ASYNC CS */
#define acmgt2__vector_engine38__xve_stall_cycles_async_cs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* VectorEngine38 :: XVE STALL CYCLES ASYNC CS */
#define acmgt2__vector_engine38__xve_stall_cycles_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: XVE STALL CYCLES CS */
#define acmgt2__vector_engine38__xve_stall_cycles_cs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* VectorEngine38 :: XVE STALL CYCLES CS */
#define acmgt2__vector_engine38__xve_stall_cycles_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: XVE STALL CYCLES DS */
#define acmgt2__vector_engine38__xve_stall_cycles_ds__read \
   hsw__render_basic__hs_threads__read

/* VectorEngine38 :: XVE STALL CYCLES DS */
#define acmgt2__vector_engine38__xve_stall_cycles_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: XVE STALL CYCLES HS */
#define acmgt2__vector_engine38__xve_stall_cycles_hs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* VectorEngine38 :: XVE STALL CYCLES HS */
#define acmgt2__vector_engine38__xve_stall_cycles_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: XVE STALL CYCLES MS */
#define acmgt2__vector_engine38__xve_stall_cycles_ms__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* VectorEngine38 :: XVE STALL CYCLES MS */
#define acmgt2__vector_engine38__xve_stall_cycles_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: XVE STALL CYCLES FS */
#define acmgt2__vector_engine38__xve_stall_cycles_ps__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* VectorEngine38 :: XVE STALL CYCLES FS */
#define acmgt2__vector_engine38__xve_stall_cycles_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: XVE STALL CYCLES TS */
#define acmgt2__vector_engine38__xve_stall_cycles_ts__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* VectorEngine38 :: XVE STALL CYCLES TS */
#define acmgt2__vector_engine38__xve_stall_cycles_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: XVE STALL CYCLES VS */
#define acmgt2__vector_engine38__xve_stall_cycles_vs__read \
   hsw__render_basic__ds_threads__read

/* VectorEngine38 :: XVE STALL CYCLES VS */
#define acmgt2__vector_engine38__xve_stall_cycles_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine38 :: XVE STALL CYCLES RT */
#define acmgt2__vector_engine38__xve_stall_cycles_rt__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* VectorEngine38 :: XVE STALL CYCLES RT */
#define acmgt2__vector_engine38__xve_stall_cycles_rt__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: GPU Time Elapsed */
#define acmgt2__vector_engine39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine39 :: GPU Core Clocks */
#define acmgt2__vector_engine39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine39 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine39 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine39 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt2__vector_engine39__xve_inst_executed_alu0_all__read \
   acmgt1__ext1000__xve_active_cycles__read

/* VectorEngine39 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt2__vector_engine39__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED FP16 */
#define acmgt2__vector_engine39__xve_inst_executed_fp16__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* VectorEngine39 :: XVE INST EXECUTED FP16 */
#define acmgt2__vector_engine39__xve_inst_executed_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED FP32 */
#define acmgt2__vector_engine39__xve_inst_executed_fp32__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* VectorEngine39 :: XVE INST EXECUTED FP32 */
#define acmgt2__vector_engine39__xve_inst_executed_fp32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED FP64 */
#define acmgt2__vector_engine39__xve_inst_executed_fp64__read \
   hsw__render_basic__hs_threads__read

/* VectorEngine39 :: XVE INST EXECUTED FP64 */
#define acmgt2__vector_engine39__xve_inst_executed_fp64__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt2__vector_engine39__xve_inst_executed_alu1_all__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* VectorEngine39 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt2__vector_engine39__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED INT16 */
#define acmgt2__vector_engine39__xve_inst_executed_int16__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* VectorEngine39 :: XVE INST EXECUTED INT16 */
#define acmgt2__vector_engine39__xve_inst_executed_int16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED INT32 */
#define acmgt2__vector_engine39__xve_inst_executed_int32__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* VectorEngine39 :: XVE INST EXECUTED INT32 */
#define acmgt2__vector_engine39__xve_inst_executed_int32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED MATH */
#define acmgt2__vector_engine39__xve_inst_executed_math__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* VectorEngine39 :: XVE INST EXECUTED MATH */
#define acmgt2__vector_engine39__xve_inst_executed_math__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED XMX ALL */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_all__read \
   hsw__render_basic__ds_threads__read

/* VectorEngine39 :: XVE INST EXECUTED XMX ALL */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED XMX BF16 */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_bf16__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* VectorEngine39 :: XVE INST EXECUTED XMX BF16 */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_bf16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED XMX FP16 */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_fp16__read \
   acmgt1__ext1001__xve_inst_executed_alu1_cs__read

/* VectorEngine39 :: XVE INST EXECUTED XMX FP16 */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED XMX INT8 */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_int8__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* VectorEngine39 :: XVE INST EXECUTED XMX INT8 */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_int8__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine39 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__eu_active__read

/* VectorEngine39 :: XVE INST EXECUTED FP16 UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_fp16_utilization__read \
   bdw__render_basic__eu_stall__read

/* VectorEngine39 :: XVE INST EXECUTED FP32 UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_fp32_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* VectorEngine39 :: XVE INST EXECUTED FP64 UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_fp64_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* VectorEngine39 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* VectorEngine39 :: XVE INST EXECUTED INT16 UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_int16_utilization__read \
   bdw__render_basic__vs_send_active__read

/* VectorEngine39 :: XVE INST EXECUTED INT32 UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_int32_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* VectorEngine39 :: XVE INST EXECUTED MATH UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_math_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* VectorEngine39 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* VectorEngine39 :: XVE INST EXECUTED XMX BF16 UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_bf16_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* VectorEngine39 :: XVE INST EXECUTED XMX FP16 UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_fp16_utilization__read \
   bdw__render_basic__ps_send_active__read

/* VectorEngine39 :: XVE INST EXECUTED XMX INT8 UTILIZATION */
#define acmgt2__vector_engine39__xve_inst_executed_xmx_int8_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* VectorEngine40 :: GPU Time Elapsed */
#define acmgt2__vector_engine40__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine40 :: GPU Core Clocks */
#define acmgt2__vector_engine40__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine40 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine40__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine40 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine40__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine40 :: XVE INST EXECUTED SEND ALL */
#define acmgt2__vector_engine40__xve_inst_executed_send_all__read \
   acmgt1__ext1000__xve_active_cycles__read

/* VectorEngine40 :: XVE INST EXECUTED SEND ALL */
#define acmgt2__vector_engine40__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND ASYNC CS */
#define acmgt2__vector_engine40__xve_inst_executed_send_async_cs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* VectorEngine40 :: XVE INST EXECUTED SEND ASYNC CS */
#define acmgt2__vector_engine40__xve_inst_executed_send_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND CS */
#define acmgt2__vector_engine40__xve_inst_executed_send_cs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* VectorEngine40 :: XVE INST EXECUTED SEND CS */
#define acmgt2__vector_engine40__xve_inst_executed_send_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND DS */
#define acmgt2__vector_engine40__xve_inst_executed_send_ds__read \
   hsw__render_basic__hs_threads__read

/* VectorEngine40 :: XVE INST EXECUTED SEND DS */
#define acmgt2__vector_engine40__xve_inst_executed_send_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND GS */
#define acmgt2__vector_engine40__xve_inst_executed_send_gs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* VectorEngine40 :: XVE INST EXECUTED SEND GS */
#define acmgt2__vector_engine40__xve_inst_executed_send_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND HS */
#define acmgt2__vector_engine40__xve_inst_executed_send_hs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* VectorEngine40 :: XVE INST EXECUTED SEND HS */
#define acmgt2__vector_engine40__xve_inst_executed_send_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND MS */
#define acmgt2__vector_engine40__xve_inst_executed_send_ms__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* VectorEngine40 :: XVE INST EXECUTED SEND MS */
#define acmgt2__vector_engine40__xve_inst_executed_send_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND FS */
#define acmgt2__vector_engine40__xve_inst_executed_send_ps__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* VectorEngine40 :: XVE INST EXECUTED SEND FS */
#define acmgt2__vector_engine40__xve_inst_executed_send_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND TS */
#define acmgt2__vector_engine40__xve_inst_executed_send_ts__read \
   hsw__render_basic__ds_threads__read

/* VectorEngine40 :: XVE INST EXECUTED SEND TS */
#define acmgt2__vector_engine40__xve_inst_executed_send_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND VS */
#define acmgt2__vector_engine40__xve_inst_executed_send_vs__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* VectorEngine40 :: XVE INST EXECUTED SEND VS */
#define acmgt2__vector_engine40__xve_inst_executed_send_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine40 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_all_utilization__read \
   bdw__render_basic__eu_active__read

/* VectorEngine40 :: XVE INST EXECUTED SEND ASYNC CS UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_async_cs_utilization__read \
   bdw__render_basic__eu_stall__read

/* VectorEngine40 :: XVE INST EXECUTED SEND CS UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_cs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* VectorEngine40 :: XVE INST EXECUTED SEND DS UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_ds_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* VectorEngine40 :: XVE INST EXECUTED SEND GS UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_gs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* VectorEngine40 :: XVE INST EXECUTED SEND HS UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_hs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* VectorEngine40 :: XVE INST EXECUTED SEND MS UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* VectorEngine40 :: XVE INST EXECUTED SEND FS UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_ps_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* VectorEngine40 :: XVE INST EXECUTED SEND TS UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_ts_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* VectorEngine40 :: XVE INST EXECUTED SEND VS UTILIZATION */
#define acmgt2__vector_engine40__xve_inst_executed_send_vs_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* VectorEngine41 :: GPU Time Elapsed */
#define acmgt2__vector_engine41__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* VectorEngine41 :: GPU Core Clocks */
#define acmgt2__vector_engine41__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* VectorEngine41 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine41__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* VectorEngine41 :: AVG GPU Core Frequency */
#define acmgt2__vector_engine41__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* VectorEngine41 :: XVE STALL GS */
#define acmgt2__vector_engine41__xve_stall_gs__read \
   bdw__render_basic__eu_active__read

/* VectorEngine41 :: XVE INST EXECUTED ALU0 GS */
#define acmgt2__vector_engine41__xve_inst_executed_alu0_gs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* VectorEngine41 :: XVE INST EXECUTED ALU0 GS */
#define acmgt2__vector_engine41__xve_inst_executed_alu0_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine41 :: XVE INST EXECUTED ALU1 GS */
#define acmgt2__vector_engine41__xve_inst_executed_alu1_gs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* VectorEngine41 :: XVE INST EXECUTED ALU1 GS */
#define acmgt2__vector_engine41__xve_inst_executed_alu1_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine41 :: XVE STALL CYCLES GS */
#define acmgt2__vector_engine41__xve_stall_cycles_gs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* VectorEngine41 :: XVE STALL CYCLES GS */
#define acmgt2__vector_engine41__xve_stall_cycles_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine41 :: XVE INST EXECUTED ALU0 MS */
#define acmgt2__vector_engine41__xve_inst_executed_alu0_ms__read \
   hsw__render_basic__hs_threads__read

/* VectorEngine41 :: XVE INST EXECUTED ALU0 MS */
#define acmgt2__vector_engine41__xve_inst_executed_alu0_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine41 :: XVE INST EXECUTED ALU0 TS */
#define acmgt2__vector_engine41__xve_inst_executed_alu0_ts__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* VectorEngine41 :: XVE INST EXECUTED ALU0 TS */
#define acmgt2__vector_engine41__xve_inst_executed_alu0_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine41 :: XVE INST EXECUTED ALU1 MS */
#define acmgt2__vector_engine41__xve_inst_executed_alu1_ms__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* VectorEngine41 :: XVE INST EXECUTED ALU1 MS */
#define acmgt2__vector_engine41__xve_inst_executed_alu1_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine41 :: XVE INST EXECUTED ALU1 TS */
#define acmgt2__vector_engine41__xve_inst_executed_alu1_ts__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* VectorEngine41 :: XVE INST EXECUTED ALU1 TS */
#define acmgt2__vector_engine41__xve_inst_executed_alu1_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* VectorEngine41 :: XVE INST EXECUTED ALU0 GS UTILIZATION */
#define acmgt2__vector_engine41__xve_inst_executed_alu0_gs_utilization__read \
   bdw__render_basic__eu_stall__read

/* VectorEngine41 :: XVE INST EXECUTED ALU1 GS UTILIZATION */
#define acmgt2__vector_engine41__xve_inst_executed_alu1_gs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* VectorEngine41 :: XVE INST EXECUTED ALU0 MS UTILIZATION */
#define acmgt2__vector_engine41__xve_inst_executed_alu0_ms_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* VectorEngine41 :: XVE INST EXECUTED ALU0 TS UTILIZATION */
#define acmgt2__vector_engine41__xve_inst_executed_alu0_ts_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* VectorEngine41 :: XVE INST EXECUTED ALU1 MS UTILIZATION */
#define acmgt2__vector_engine41__xve_inst_executed_alu1_ms_utilization__read \
   bdw__render_basic__vs_send_active__read

/* VectorEngine41 :: XVE INST EXECUTED ALU1 TS UTILIZATION */
#define acmgt2__vector_engine41__xve_inst_executed_alu1_ts_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Render Metrics Basic :: GPU Time Elapsed */
#define acmgt3__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic :: GPU Core Clocks */
#define acmgt3__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic :: AVG GPU Core Frequency */
#define acmgt3__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic :: AVG GPU Core Frequency */
#define acmgt3__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic :: VS Threads Dispatched */
#define acmgt3__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic :: HS Threads Dispatched */
#define acmgt3__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic :: DS Threads Dispatched */
#define acmgt3__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic :: GS Threads Dispatched */
#define acmgt3__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic :: FS Threads Dispatched */
#define acmgt3__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic :: CS Threads Dispatched */
#define acmgt3__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic :: GPU Busy */
#define acmgt3__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic :: XVE Active */
#define acmgt3__render_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic :: XVE Stall */
#define acmgt3__render_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic :: XVE Thread Occupancy */
#define acmgt3__render_basic__xve_thread_occupancy__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* Render Metrics Basic :: EM And FPU Pipes Active */
#define acmgt3__render_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic :: VS FPU Pipe Active */
#define acmgt3__render_basic__vs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic :: VS EM Pipe Active */
#define acmgt3__render_basic__vs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic :: VS Send Pipe Active */
#define acmgt3__render_basic__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Render Metrics Basic :: FS FPU Pipe Active */
#define acmgt3__render_basic__ps_fpu_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Render Metrics Basic :: FS EM Pipe Active */
#define acmgt3__render_basic__ps_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic :: FS Send Pipe Active */
#define acmgt3__render_basic__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic :: Rasterized Pixels */
#define acmgt3__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic :: Early Hi-Depth Test Fails */
#define acmgt3__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic :: Early Depth Test Fails */
#define acmgt3__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic :: Samples Killed in FS */
#define acmgt3__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic :: Pixels Failing Tests */
#define acmgt3__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic :: Samples Written */
#define acmgt3__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic :: Samples Blended */
#define acmgt3__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic :: Sampler Texels */
#define acmgt3__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic :: Sampler Texels Misses */
#define acmgt3__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic :: SLM Bytes Read */
#define acmgt3__render_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Render Metrics Basic :: SLM Bytes Read */
#define acmgt3__render_basic__slm_reads__max \
   acmgt1__render_basic__slm_reads__max

/* Render Metrics Basic :: SLM Writes */
#define acmgt3__render_basic__slm_writes__read \
   acmgt1__render_basic__slm_writes__read

/* Render Metrics Basic :: SLM Writes */
#define acmgt3__render_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Render Metrics Basic :: Shader Memory Accesses */
#define acmgt3__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic :: Shader Atomic Memory Accesses */
#define acmgt3__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic :: Shader Barrier Messages */
#define acmgt3__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic :: GTI Read Throughput */
#define acmgt3__render_basic__gti_read_throughput__read \
   acmgt1__render_basic__gti_read_throughput__read

/* Render Metrics Basic :: GTI Read Throughput */
#define acmgt3__render_basic__gti_read_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Render Metrics Basic :: GTI Write Throughput */
#define acmgt3__render_basic__gti_write_throughput__read \
   acmgt2__render_basic__gti_write_throughput__read

/* Render Metrics Basic :: GTI Write Throughput */
#define acmgt3__render_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Render Metrics Basic :: Sampler Slice0 Xe Core0 is busy */
#define acmgt3__render_basic__sampler00_busy__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics Basic :: Samplers Busy */
#define acmgt3__render_basic__samplers_busy__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics Basic :: Sampler00 Bottleneck */
#define acmgt3__render_basic__sampler00_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics Basic :: Samplers Bottleneck */
#define acmgt3__render_basic__sampler_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Compute Metrics Basic :: GPU Time Elapsed */
#define acmgt3__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic :: GPU Core Clocks */
#define acmgt3__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define acmgt3__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define acmgt3__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic :: GPU Busy */
#define acmgt3__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic :: CS Threads Dispatched */
#define acmgt3__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic :: XVE Active */
#define acmgt3__compute_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic :: XVE Stall */
#define acmgt3__compute_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic :: XVE FPU Pipe Active */
#define acmgt3__compute_basic__fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic :: EM Pipe Active */
#define acmgt3__compute_basic__em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic :: XMX Pipe Active */
#define acmgt3__compute_basic__xmx_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic :: EM And FPU Pipes Active */
#define acmgt3__compute_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic :: XMX And FPU Pipes Active */
#define acmgt3__compute_basic__xve_fpu_xmx_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics Basic :: XVE AVG IPC Rate */
#define acmgt3__compute_basic__xve_avg_ipc_rate__read \
   acmgt1__compute_basic__xve_avg_ipc_rate__read

/* Compute Metrics Basic :: XVE AVG IPC Rate */
#define acmgt3__compute_basic__xve_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic :: Send Pipe Active */
#define acmgt3__compute_basic__send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics Basic :: XVE Thread Occupancy */
#define acmgt3__compute_basic__xve_thread_occupancy__read \
   acmgt1__compute_basic__xve_thread_occupancy__read

/* Compute Metrics Basic :: FPU FLT16 Instruction */
#define acmgt3__compute_basic__xve_fpu_flt16__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics Basic :: FPU FLT32 Instruction */
#define acmgt3__compute_basic__xve_fpu_flt32__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics Basic :: FPU FLT64 Instruction */
#define acmgt3__compute_basic__xve_fpu_flt64__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics Basic :: Sampler Texels */
#define acmgt3__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic :: Sampler Texels Misses */
#define acmgt3__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define acmgt3__compute_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define acmgt3__compute_basic__slm_reads__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: SLM Writes */
#define acmgt3__compute_basic__slm_writes__read \
   acmgt1__render_basic__slm_writes__read

/* Compute Metrics Basic :: SLM Writes */
#define acmgt3__compute_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: Shader Memory Accesses */
#define acmgt3__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic :: Shader Atomic Memory Accesses */
#define acmgt3__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic :: Shader Barrier Messages */
#define acmgt3__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define acmgt3__compute_basic__gti_read_throughput__read \
   acmgt1__render_basic__gti_read_throughput__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define acmgt3__compute_basic__gti_read_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Compute Metrics Basic :: GTI Write Throughput */
#define acmgt3__compute_basic__gti_write_throughput__read \
   acmgt2__render_basic__gti_write_throughput__read

/* Compute Metrics Basic :: GTI Write Throughput */
#define acmgt3__compute_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* AsyncCompute :: GPU Time Elapsed */
#define acmgt3__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define acmgt3__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define acmgt3__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define acmgt3__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define acmgt3__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define acmgt3__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define acmgt3__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define acmgt3__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define acmgt3__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define acmgt3__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define acmgt3__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: XVE FPU Pipe Active */
#define acmgt3__async_compute__fpu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: VS FPU Pipe Active */
#define acmgt3__async_compute__vs_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* AsyncCompute :: FS FPU Pipe Active */
#define acmgt3__async_compute__ps_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: CS FPU Pipe Active */
#define acmgt3__async_compute__cs_fpu_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: ASYNC CS FPU Pipe Active */
#define acmgt3__async_compute__async_cs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: EM Pipe Active */
#define acmgt3__async_compute__em_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: VS EM Pipe Active */
#define acmgt3__async_compute__vs_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: FS EM Pipe Active */
#define acmgt3__async_compute__ps_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: CS EM Pipe Active */
#define acmgt3__async_compute__cs_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: ASYNC CS EM Pipe Active */
#define acmgt3__async_compute__async_cs_em_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: XVE Thread Occupancy */
#define acmgt3__async_compute__xve_thread_occupancy__read \
   acmgt1__async_compute__xve_thread_occupancy__read

/* AsyncCompute :: XVE Active */
#define acmgt3__async_compute__xve_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* AsyncCompute :: XVE Stall */
#define acmgt3__async_compute__xve_stall__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* XveActivity1 :: GPU Time Elapsed */
#define acmgt3__xve_activity1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* XveActivity1 :: GPU Core Clocks */
#define acmgt3__xve_activity1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* XveActivity1 :: AVG GPU Core Frequency */
#define acmgt3__xve_activity1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* XveActivity1 :: AVG GPU Core Frequency */
#define acmgt3__xve_activity1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* XveActivity1 :: GPU Busy */
#define acmgt3__xve_activity1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* XveActivity1 :: VS Threads Dispatched */
#define acmgt3__xve_activity1__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* XveActivity1 :: HS Threads Dispatched */
#define acmgt3__xve_activity1__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* XveActivity1 :: DS Threads Dispatched */
#define acmgt3__xve_activity1__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* XveActivity1 :: GS Threads Dispatched */
#define acmgt3__xve_activity1__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* XveActivity1 :: FS Threads Dispatched */
#define acmgt3__xve_activity1__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* XveActivity1 :: CS Threads Dispatched */
#define acmgt3__xve_activity1__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* XveActivity1 :: HS FPU Pipe Active */
#define acmgt3__xve_activity1__hs_fpu_active__read \
   bdw__render_basic__eu_active__read

/* XveActivity1 :: DS FPU Pipe Active */
#define acmgt3__xve_activity1__ds_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* XveActivity1 :: GS FPU Pipe Active */
#define acmgt3__xve_activity1__gs_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* XveActivity1 :: HS EM Pipe Active */
#define acmgt3__xve_activity1__hs_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* XveActivity1 :: DS EM Pipe Active */
#define acmgt3__xve_activity1__ds_em_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* XveActivity1 :: GS EM Pipe Active */
#define acmgt3__xve_activity1__gs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* XveActivity1 :: HS Send Pipe Active */
#define acmgt3__xve_activity1__hs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* XveActivity1 :: DS Send Pipe Active */
#define acmgt3__xve_activity1__ds_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* XveActivity1 :: GS Send Pipe Active */
#define acmgt3__xve_activity1__gs_send_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* XveActivity1 :: CS Send Pipe Active */
#define acmgt3__xve_activity1__cs_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* GpuBusyness :: GPU Time Elapsed */
#define acmgt3__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define acmgt3__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define acmgt3__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define acmgt3__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define acmgt3__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: XVE Active */
#define acmgt3__gpu_busyness__xve_active__read \
   bdw__render_basic__eu_active__read

/* GpuBusyness :: XVE Stall */
#define acmgt3__gpu_busyness__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* GpuBusyness :: XVE Thread Occupancy */
#define acmgt3__gpu_busyness__xve_thread_occupancy__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* GpuBusyness :: VS Threads Dispatched */
#define acmgt3__gpu_busyness__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* GpuBusyness :: HS Threads Dispatched */
#define acmgt3__gpu_busyness__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* GpuBusyness :: DS Threads Dispatched */
#define acmgt3__gpu_busyness__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* GpuBusyness :: GS Threads Dispatched */
#define acmgt3__gpu_busyness__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* GpuBusyness :: FS Threads Dispatched */
#define acmgt3__gpu_busyness__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* GpuBusyness :: CS Threads Dispatched */
#define acmgt3__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define acmgt3__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: ComputeEngine0 Ring Busy */
#define acmgt3__gpu_busyness__compute_engine0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* GpuBusyness :: ComputeEngine1 Ring Busy */
#define acmgt3__gpu_busyness__compute_engine1_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* GpuBusyness :: ComputeEngine2 Ring Busy */
#define acmgt3__gpu_busyness__compute_engine2_busy__read \
   bdw__render_pipe_profile__cl_stall__read

/* GpuBusyness :: ComputeEngine3 Ring Busy */
#define acmgt3__gpu_busyness__compute_engine3_busy__read \
   bdw__render_pipe_profile__so_stall__read

/* GpuBusyness :: Blitter Ring Busy */
#define acmgt3__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__hs_stall__read

/* GpuBusyness :: Vdbox00 Ring Busy */
#define acmgt3__gpu_busyness__vdbox00_busy__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* GpuBusyness :: Vebox0 Ring Busy */
#define acmgt3__gpu_busyness__vebox0_busy__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* GpuBusyness :: Vdbox10 Ring Busy */
#define acmgt3__gpu_busyness__vdbox10_busy__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* GpuBusyness :: Vebox1 Ring Busy */
#define acmgt3__gpu_busyness__vebox1_busy__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* GpuBusyness :: Any compute engine busy */
#define acmgt3__gpu_busyness__any_compute_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* GpuBusyness :: Render and any compute engines are simultaneously busy */
#define acmgt3__gpu_busyness__render_and_any_compute_engine_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set TestOa :: GPU Time Elapsed */
#define acmgt3__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define acmgt3__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define acmgt3__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define acmgt3__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define acmgt3__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define acmgt3__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define acmgt3__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define acmgt3__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define acmgt3__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define acmgt3__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define acmgt3__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define acmgt3__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define acmgt3__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define acmgt3__test_oa__counter9__read \
   hsw__compute_extended__untyped_writes0__read

/* Metric set HDCAndSF for Slice01 :: GPU Time Elapsed */
#define acmgt3__hdc_and_sf__slice01__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF for Slice01 :: GPU Core Clocks */
#define acmgt3__hdc_and_sf__slice01__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF for Slice01 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf__slice01__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF for Slice01 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf__slice01__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF for Slice01 :: GPU Busy */
#define acmgt3__hdc_and_sf__slice01__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF for Slice01 :: Slice0 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice01__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF for Slice01 :: Slice0 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice01__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF for Slice01 :: Slice0 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice01__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF for Slice01 :: Slice0 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice01__non_sampler_shader03_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF for Slice01 :: Slice1 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice01__non_sampler_shader10_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF for Slice01 :: Slice1 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice01__non_sampler_shader11_access_stalled_on_l3__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set HDCAndSF for Slice01 :: Slice1 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice01__non_sampler_shader12_access_stalled_on_l3__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF for Slice01 :: Slice1 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice01__non_sampler_shader13_access_stalled_on_l3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set HDCAndSF for Slice23 :: GPU Time Elapsed */
#define acmgt3__hdc_and_sf__slice23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF for Slice23 :: GPU Core Clocks */
#define acmgt3__hdc_and_sf__slice23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF for Slice23 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf__slice23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF for Slice23 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf__slice23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF for Slice23 :: GPU Busy */
#define acmgt3__hdc_and_sf__slice23__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF for Slice23 :: Slice2 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice23__non_sampler_shader20_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF for Slice23 :: Slice2 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice23__non_sampler_shader21_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF for Slice23 :: Slice2 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice23__non_sampler_shader22_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF for Slice23 :: Slice2 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice23__non_sampler_shader23_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF for Slice23 :: Slice3 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice23__non_sampler_shader30_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF for Slice23 :: Slice3 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice23__non_sampler_shader31_access_stalled_on_l3__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set HDCAndSF for Slice23 :: Slice3 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice23__non_sampler_shader32_access_stalled_on_l3__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF for Slice23 :: Slice3 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice23__non_sampler_shader33_access_stalled_on_l3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set HDCAndSF for Slice45 :: GPU Time Elapsed */
#define acmgt3__hdc_and_sf__slice45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF for Slice45 :: GPU Core Clocks */
#define acmgt3__hdc_and_sf__slice45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF for Slice45 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf__slice45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF for Slice45 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf__slice45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF for Slice45 :: GPU Busy */
#define acmgt3__hdc_and_sf__slice45__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF for Slice45 :: Slice4 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice45__non_sampler_shader40_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF for Slice45 :: Slice4 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice45__non_sampler_shader41_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF for Slice45 :: Slice4 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice45__non_sampler_shader42_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF for Slice45 :: Slice4 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice45__non_sampler_shader43_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF for Slice45 :: Slice5 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice45__non_sampler_shader50_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF for Slice45 :: Slice5 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice45__non_sampler_shader51_access_stalled_on_l3__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set HDCAndSF for Slice45 :: Slice5 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice45__non_sampler_shader52_access_stalled_on_l3__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF for Slice45 :: Slice5 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice45__non_sampler_shader53_access_stalled_on_l3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set HDCAndSF for Slice67 :: GPU Time Elapsed */
#define acmgt3__hdc_and_sf__slice67__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF for Slice67 :: GPU Core Clocks */
#define acmgt3__hdc_and_sf__slice67__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF for Slice67 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf__slice67__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF for Slice67 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf__slice67__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF for Slice67 :: GPU Busy */
#define acmgt3__hdc_and_sf__slice67__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF for Slice67 :: Slice6 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice67__non_sampler_shader60_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF for Slice67 :: Slice6 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice67__non_sampler_shader61_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF for Slice67 :: Slice6 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice67__non_sampler_shader62_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF for Slice67 :: Slice6 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice67__non_sampler_shader63_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF for Slice67 :: Slice7 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice67__non_sampler_shader70_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF for Slice67 :: Slice7 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice67__non_sampler_shader71_access_stalled_on_l3__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set HDCAndSF for Slice67 :: Slice7 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice67__non_sampler_shader72_access_stalled_on_l3__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF for Slice67 :: Slice7 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define acmgt3__hdc_and_sf__slice67__non_sampler_shader73_access_stalled_on_l3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set HDCAndSF1 :: GPU Time Elapsed */
#define acmgt3__hdc_and_sf1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF1 :: GPU Core Clocks */
#define acmgt3__hdc_and_sf1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF1 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF1 :: AVG GPU Core Frequency */
#define acmgt3__hdc_and_sf1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF1 :: GPU Busy */
#define acmgt3__hdc_and_sf1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF1 :: Polygon (Slice0) Data Ready */
#define acmgt3__hdc_and_sf1__poly0_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF1 :: Polygon (Slice1) Data Ready */
#define acmgt3__hdc_and_sf1__poly1_data_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF1 :: Polygon (Slice2) Data Ready */
#define acmgt3__hdc_and_sf1__poly2_data_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF1 :: Polygon (Slice3) Data Ready */
#define acmgt3__hdc_and_sf1__poly3_data_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF1 :: Polygon (Slice4) Data Ready */
#define acmgt3__hdc_and_sf1__poly4_data_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF1 :: Polygon (Slice5) Data Ready */
#define acmgt3__hdc_and_sf1__poly5_data_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set HDCAndSF1 :: Polygon (Slice6) Data Ready */
#define acmgt3__hdc_and_sf1__poly6_data_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Metric set HDCAndSF1 :: Polygon (Slice7) Data Ready */
#define acmgt3__hdc_and_sf1__poly7_data_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Metric set HDCAndSF1 :: SQ00 is full */
#define acmgt3__hdc_and_sf1__gt_request_queue00_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set HDCAndSF1 :: SQ10 is full */
#define acmgt3__hdc_and_sf1__gt_request_queue10_full__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set HDCAndSF1 :: SQ20 is full */
#define acmgt3__hdc_and_sf1__gt_request_queue20_full__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set HDCAndSF1 :: SQ30 is full */
#define acmgt3__hdc_and_sf1__gt_request_queue30_full__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set HDCAndSF1 :: SQ40 is full */
#define acmgt3__hdc_and_sf1__gt_request_queue40_full__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set HDCAndSF1 :: SQ50 is full */
#define acmgt3__hdc_and_sf1__gt_request_queue50_full__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set HDCAndSF1 :: SQ60 is full */
#define acmgt3__hdc_and_sf1__gt_request_queue60_full__read \
   bdw__render_pipe_profile__hs_stall__read

/* Metric set HDCAndSF1 :: SQ70 is full */
#define acmgt3__hdc_and_sf1__gt_request_queue70_full__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3_Slice01 :: GPU Time Elapsed */
#define acmgt3__l3__slice01__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_Slice01 :: GPU Core Clocks */
#define acmgt3__l3__slice01__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_Slice01 :: AVG GPU Core Frequency */
#define acmgt3__l3__slice01__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_Slice01 :: AVG GPU Core Frequency */
#define acmgt3__l3__slice01__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_Slice01 :: GPU Busy */
#define acmgt3__l3__slice01__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_Slice01 :: Quad0 L3 Bank0 Input Available */
#define acmgt3__l3__slice01__l30_bank0_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3_Slice01 :: Quad0 L3 Bank1 Input Available */
#define acmgt3__l3__slice01__l30_bank1_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3_Slice01 :: Quad0 L3 Bank2 Input Available */
#define acmgt3__l3__slice01__l30_bank2_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3_Slice01 :: Quad0 L3 Bank3 Input Available */
#define acmgt3__l3__slice01__l30_bank3_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3_Slice01 :: Quad0 L3 Bank4 Input Available */
#define acmgt3__l3__slice01__l30_bank4_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* L3_Slice01 :: Quad0 L3 Bank5 Input Available */
#define acmgt3__l3__slice01__l30_bank5_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3_Slice01 :: Quad0 L3 Bank6 Input Available */
#define acmgt3__l3__slice01__l30_bank6_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3_Slice01 :: Quad0 L3 Bank7 Input Available */
#define acmgt3__l3__slice01__l30_bank7_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3_Slice01 :: Quad0 L3 Bank0 Output Ready */
#define acmgt3__l3__slice01__l30_bank0_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3_Slice01 :: Quad0 L3 Bank1 Output Ready */
#define acmgt3__l3__slice01__l30_bank1_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3_Slice01 :: Quad0 L3 Bank2 Output Ready */
#define acmgt3__l3__slice01__l30_bank2_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3_Slice01 :: Quad0 L3 Bank3 Output Ready */
#define acmgt3__l3__slice01__l30_bank3_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3_Slice01 :: Quad0 L3 Bank4 Output Ready */
#define acmgt3__l3__slice01__l30_bank4_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3_Slice01 :: Quad0 L3 Bank5 Output Ready */
#define acmgt3__l3__slice01__l30_bank5_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3_Slice01 :: Quad0 L3 Bank6 Output Ready */
#define acmgt3__l3__slice01__l30_bank6_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* L3_Slice01 :: Quad0 L3 Bank7 Output Ready */
#define acmgt3__l3__slice01__l30_bank7_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* L3_Slice23 :: GPU Time Elapsed */
#define acmgt3__l3__slice23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_Slice23 :: GPU Core Clocks */
#define acmgt3__l3__slice23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_Slice23 :: AVG GPU Core Frequency */
#define acmgt3__l3__slice23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_Slice23 :: AVG GPU Core Frequency */
#define acmgt3__l3__slice23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_Slice23 :: GPU Busy */
#define acmgt3__l3__slice23__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_Slice23 :: Quad1 L3 Bank0 Input Available */
#define acmgt3__l3__slice23__l31_bank0_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3_Slice23 :: Quad1 L3 Bank1 Input Available */
#define acmgt3__l3__slice23__l31_bank1_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3_Slice23 :: Quad1 L3 Bank2 Input Available */
#define acmgt3__l3__slice23__l31_bank2_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3_Slice23 :: Quad1 L3 Bank3 Input Available */
#define acmgt3__l3__slice23__l31_bank3_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3_Slice23 :: Quad1 L3 Bank4 Input Available */
#define acmgt3__l3__slice23__l31_bank4_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* L3_Slice23 :: Quad1 L3 Bank5 Input Available */
#define acmgt3__l3__slice23__l31_bank5_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3_Slice23 :: Quad1 L3 Bank6 Input Available */
#define acmgt3__l3__slice23__l31_bank6_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3_Slice23 :: Quad1 L3 Bank7 Input Available */
#define acmgt3__l3__slice23__l31_bank7_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3_Slice23 :: Quad1 L3 Bank0 Output Ready */
#define acmgt3__l3__slice23__l31_bank0_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3_Slice23 :: Quad1 L3 Bank1 Output Ready */
#define acmgt3__l3__slice23__l31_bank1_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3_Slice23 :: Quad1 L3 Bank2 Output Ready */
#define acmgt3__l3__slice23__l31_bank2_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3_Slice23 :: Quad1 L3 Bank3 Output Ready */
#define acmgt3__l3__slice23__l31_bank3_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3_Slice23 :: Quad1 L3 Bank4 Output Ready */
#define acmgt3__l3__slice23__l31_bank4_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3_Slice23 :: Quad1 L3 Bank5 Output Ready */
#define acmgt3__l3__slice23__l31_bank5_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3_Slice23 :: Quad1 L3 Bank6 Output Ready */
#define acmgt3__l3__slice23__l31_bank6_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* L3_Slice23 :: Quad1 L3 Bank7 Output Ready */
#define acmgt3__l3__slice23__l31_bank7_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* L3_Slice45 :: GPU Time Elapsed */
#define acmgt3__l3__slice45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_Slice45 :: GPU Core Clocks */
#define acmgt3__l3__slice45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_Slice45 :: AVG GPU Core Frequency */
#define acmgt3__l3__slice45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_Slice45 :: AVG GPU Core Frequency */
#define acmgt3__l3__slice45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_Slice45 :: GPU Busy */
#define acmgt3__l3__slice45__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_Slice45 :: Quad2 L3 Bank0 Input Available */
#define acmgt3__l3__slice45__l32_bank0_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3_Slice45 :: Quad2 L3 Bank1 Input Available */
#define acmgt3__l3__slice45__l32_bank1_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3_Slice45 :: Quad2 L3 Bank2 Input Available */
#define acmgt3__l3__slice45__l32_bank2_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3_Slice45 :: Quad2 L3 Bank3 Input Available */
#define acmgt3__l3__slice45__l32_bank3_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3_Slice45 :: Quad2 L3 Bank4 Input Available */
#define acmgt3__l3__slice45__l32_bank4_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* L3_Slice45 :: Quad2 L3 Bank5 Input Available */
#define acmgt3__l3__slice45__l32_bank5_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3_Slice45 :: Quad2 L3 Bank6 Input Available */
#define acmgt3__l3__slice45__l32_bank6_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3_Slice45 :: Quad2 L3 Bank7 Input Available */
#define acmgt3__l3__slice45__l32_bank7_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3_Slice45 :: Quad2 L3 Bank0 Output Ready */
#define acmgt3__l3__slice45__l32_bank0_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3_Slice45 :: Quad2 L3 Bank1 Output Ready */
#define acmgt3__l3__slice45__l32_bank1_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3_Slice45 :: Quad2 L3 Bank2 Output Ready */
#define acmgt3__l3__slice45__l32_bank2_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3_Slice45 :: Quad2 L3 Bank3 Output Ready */
#define acmgt3__l3__slice45__l32_bank3_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3_Slice45 :: Quad2 L3 Bank4 Output Ready */
#define acmgt3__l3__slice45__l32_bank4_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3_Slice45 :: Quad2 L3 Bank5 Output Ready */
#define acmgt3__l3__slice45__l32_bank5_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3_Slice45 :: Quad2 L3 Bank6 Output Ready */
#define acmgt3__l3__slice45__l32_bank6_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* L3_Slice45 :: Quad2 L3 Bank7 Output Ready */
#define acmgt3__l3__slice45__l32_bank7_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* L3_Slice67 :: GPU Time Elapsed */
#define acmgt3__l3__slice67__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3_Slice67 :: GPU Core Clocks */
#define acmgt3__l3__slice67__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3_Slice67 :: AVG GPU Core Frequency */
#define acmgt3__l3__slice67__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3_Slice67 :: AVG GPU Core Frequency */
#define acmgt3__l3__slice67__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3_Slice67 :: GPU Busy */
#define acmgt3__l3__slice67__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3_Slice67 :: Quad3 L3 Bank0 Input Available */
#define acmgt3__l3__slice67__l33_bank0_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3_Slice67 :: Quad3 L3 Bank1 Input Available */
#define acmgt3__l3__slice67__l33_bank1_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3_Slice67 :: Quad3 L3 Bank2 Input Available */
#define acmgt3__l3__slice67__l33_bank2_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3_Slice67 :: Quad3 L3 Bank3 Input Available */
#define acmgt3__l3__slice67__l33_bank3_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3_Slice67 :: Quad3 L3 Bank4 Input Available */
#define acmgt3__l3__slice67__l33_bank4_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* L3_Slice67 :: Quad3 L3 Bank5 Input Available */
#define acmgt3__l3__slice67__l33_bank5_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3_Slice67 :: Quad3 L3 Bank6 Input Available */
#define acmgt3__l3__slice67__l33_bank6_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3_Slice67 :: Quad3 L3 Bank7 Input Available */
#define acmgt3__l3__slice67__l33_bank7_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3_Slice67 :: Quad3 L3 Bank0 Output Ready */
#define acmgt3__l3__slice67__l33_bank0_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3_Slice67 :: Quad3 L3 Bank1 Output Ready */
#define acmgt3__l3__slice67__l33_bank1_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3_Slice67 :: Quad3 L3 Bank2 Output Ready */
#define acmgt3__l3__slice67__l33_bank2_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3_Slice67 :: Quad3 L3 Bank3 Output Ready */
#define acmgt3__l3__slice67__l33_bank3_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3_Slice67 :: Quad3 L3 Bank4 Output Ready */
#define acmgt3__l3__slice67__l33_bank4_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3_Slice67 :: Quad3 L3 Bank5 Output Ready */
#define acmgt3__l3__slice67__l33_bank5_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3_Slice67 :: Quad3 L3 Bank6 Output Ready */
#define acmgt3__l3__slice67__l33_bank6_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* L3_Slice67 :: Quad3 L3 Bank7 Output Ready */
#define acmgt3__l3__slice67__l33_bank7_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Time Elapsed */
#define acmgt3__rasterizer_and_pixel_backend1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Core Clocks */
#define acmgt3__rasterizer_and_pixel_backend1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend1 :: GPU Busy */
#define acmgt3__rasterizer_and_pixel_backend1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice0 Rasterizer Input Available */
#define acmgt3__rasterizer_and_pixel_backend1__rasterizer0_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice1 Rasterizer Output Ready */
#define acmgt3__rasterizer_and_pixel_backend1__rasterizer1_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend1__pixel_data00_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice0 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend1__pixel_data01_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice2 Rasterizer Input Available */
#define acmgt3__rasterizer_and_pixel_backend1__rasterizer2_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice3 Rasterizer Output Ready */
#define acmgt3__rasterizer_and_pixel_backend1__rasterizer3_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice2 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend1__pixel_data20_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice2 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend1__pixel_data21_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Time Elapsed */
#define acmgt3__rasterizer_and_pixel_backend2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Core Clocks */
#define acmgt3__rasterizer_and_pixel_backend2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend2 :: GPU Busy */
#define acmgt3__rasterizer_and_pixel_backend2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice1 Rasterizer Input Available */
#define acmgt3__rasterizer_and_pixel_backend2__rasterizer1_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice0 Rasterizer Output Ready */
#define acmgt3__rasterizer_and_pixel_backend2__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice1 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend2__pixel_data10_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice1 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend2__pixel_data11_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice3 Rasterizer Input Available */
#define acmgt3__rasterizer_and_pixel_backend2__rasterizer3_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice2 Rasterizer Output Ready */
#define acmgt3__rasterizer_and_pixel_backend2__rasterizer2_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice3 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend2__pixel_data30_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice3 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend2__pixel_data31_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend3 :: GPU Time Elapsed */
#define acmgt3__rasterizer_and_pixel_backend3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend3 :: GPU Core Clocks */
#define acmgt3__rasterizer_and_pixel_backend3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend3 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend3 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend3 :: GPU Busy */
#define acmgt3__rasterizer_and_pixel_backend3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend3 :: Slice4 Rasterizer Input Available */
#define acmgt3__rasterizer_and_pixel_backend3__rasterizer4_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend3 :: Slice5 Rasterizer Output Ready */
#define acmgt3__rasterizer_and_pixel_backend3__rasterizer5_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend3 :: Slice4 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend3__pixel_data40_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend3 :: Slice4 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend3__pixel_data41_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend3 :: Slice6 Rasterizer Input Available */
#define acmgt3__rasterizer_and_pixel_backend3__rasterizer6_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set RasterizerAndPixelBackend3 :: Slice7 Rasterizer Output Ready */
#define acmgt3__rasterizer_and_pixel_backend3__rasterizer7_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend3 :: Slice6 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend3__pixel_data60_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set RasterizerAndPixelBackend3 :: Slice6 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend3__pixel_data61_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend4 :: GPU Time Elapsed */
#define acmgt3__rasterizer_and_pixel_backend4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend4 :: GPU Core Clocks */
#define acmgt3__rasterizer_and_pixel_backend4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend4 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend4 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend4 :: GPU Busy */
#define acmgt3__rasterizer_and_pixel_backend4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend4 :: Slice5 Rasterizer Input Available */
#define acmgt3__rasterizer_and_pixel_backend4__rasterizer5_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend4 :: Slice4 Rasterizer Output Ready */
#define acmgt3__rasterizer_and_pixel_backend4__rasterizer4_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend4 :: Slice5 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend4__pixel_data50_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend4 :: Slice5 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend4__pixel_data51_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend4 :: Slice7 Rasterizer Input Available */
#define acmgt3__rasterizer_and_pixel_backend4__rasterizer7_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set RasterizerAndPixelBackend4 :: Slice6 Rasterizer Output Ready */
#define acmgt3__rasterizer_and_pixel_backend4__rasterizer6_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend4 :: Slice7 Pipe0 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend4__pixel_data70_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set RasterizerAndPixelBackend4 :: Slice7 Pipe1 Post-EarlyZ Pixel Data Ready */
#define acmgt3__rasterizer_and_pixel_backend4__pixel_data71_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* RasterizerAndPixelBackend5 :: GPU Time Elapsed */
#define acmgt3__rasterizer_and_pixel_backend5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* RasterizerAndPixelBackend5 :: GPU Core Clocks */
#define acmgt3__rasterizer_and_pixel_backend5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* RasterizerAndPixelBackend5 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* RasterizerAndPixelBackend5 :: AVG GPU Core Frequency */
#define acmgt3__rasterizer_and_pixel_backend5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* RasterizerAndPixelBackend5 :: GPU Busy */
#define acmgt3__rasterizer_and_pixel_backend5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* RasterizerAndPixelBackend5 :: PS00 Output Available */
#define acmgt3__rasterizer_and_pixel_backend5__ps_output00_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* RasterizerAndPixelBackend5 :: PS01 Output Available */
#define acmgt3__rasterizer_and_pixel_backend5__ps_output01_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* RasterizerAndPixelBackend5 :: PS10 Output Available */
#define acmgt3__rasterizer_and_pixel_backend5__ps_output10_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* RasterizerAndPixelBackend5 :: PS11 Output Available */
#define acmgt3__rasterizer_and_pixel_backend5__ps_output11_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* RasterizerAndPixelBackend5 :: PS20 Output Available */
#define acmgt3__rasterizer_and_pixel_backend5__ps_output20_available__read \
   bdw__render_pipe_profile__so_stall__read

/* RasterizerAndPixelBackend5 :: PS21 Output Available */
#define acmgt3__rasterizer_and_pixel_backend5__ps_output21_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* RasterizerAndPixelBackend5 :: PS30 Output Available */
#define acmgt3__rasterizer_and_pixel_backend5__ps_output30_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* RasterizerAndPixelBackend5 :: PS31 Output Available */
#define acmgt3__rasterizer_and_pixel_backend5__ps_output31_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* RasterizerAndPixelBackend5 :: Pixel Values 00 Ready */
#define acmgt3__rasterizer_and_pixel_backend5__pixel_values00_ready__read \
   bdw__render_basic__sampler0_busy__read

/* RasterizerAndPixelBackend5 :: Pixel Values 01 Ready */
#define acmgt3__rasterizer_and_pixel_backend5__pixel_values01_ready__read \
   bdw__render_basic__sampler1_busy__read

/* RasterizerAndPixelBackend5 :: Pixel Values 10 Ready */
#define acmgt3__rasterizer_and_pixel_backend5__pixel_values10_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* RasterizerAndPixelBackend5 :: Pixel Values 11 Ready */
#define acmgt3__rasterizer_and_pixel_backend5__pixel_values11_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* RasterizerAndPixelBackend5 :: Pixel Values 20 Ready */
#define acmgt3__rasterizer_and_pixel_backend5__pixel_values20_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* RasterizerAndPixelBackend5 :: Pixel Values 21 Ready */
#define acmgt3__rasterizer_and_pixel_backend5__pixel_values21_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* RasterizerAndPixelBackend5 :: Pixel Values 30 Ready */
#define acmgt3__rasterizer_and_pixel_backend5__pixel_values30_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* RasterizerAndPixelBackend5 :: Pixel Values 31 Ready */
#define acmgt3__rasterizer_and_pixel_backend5__pixel_values31_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt3__render_pipe_profile__slice0__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt3__render_pipe_profile__slice0__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice0__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice0__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt3__render_pipe_profile__slice0__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF0 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__vf0_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS0 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__vs0_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper0 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__cl0_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS0 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__hs0_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS0 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__ds0_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS0 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__gs0_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF0 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__sf0_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO0 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__so0_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL0 Stall */
#define acmgt3__render_pipe_profile__slice0__cl0_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS0 Stall */
#define acmgt3__render_pipe_profile__slice0__hs0_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS0 Stall */
#define acmgt3__render_pipe_profile__slice0__ds0_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF0 Stall */
#define acmgt3__render_pipe_profile__slice0__sf0_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO0 Stall */
#define acmgt3__render_pipe_profile__slice0__so0_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth00 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__hi_depth00_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC00 Bottleneck */
#define acmgt3__render_pipe_profile__slice0__bc00_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt3__render_pipe_profile__slice1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt3__render_pipe_profile__slice1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt3__render_pipe_profile__slice1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF1 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__vf1_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS1 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__vs1_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper1 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__cl1_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS1 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__hs1_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS1 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__ds1_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS1 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__gs1_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF1 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__sf1_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO1 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__so1_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL1 Stall */
#define acmgt3__render_pipe_profile__slice1__cl1_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS1 Stall */
#define acmgt3__render_pipe_profile__slice1__hs1_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS1 Stall */
#define acmgt3__render_pipe_profile__slice1__ds1_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF1 Stall */
#define acmgt3__render_pipe_profile__slice1__sf1_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO1 Stall */
#define acmgt3__render_pipe_profile__slice1__so1_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth10 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__hi_depth10_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC10 Bottleneck */
#define acmgt3__render_pipe_profile__slice1__bc10_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt3__render_pipe_profile__slice2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt3__render_pipe_profile__slice2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt3__render_pipe_profile__slice2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF2 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__vf2_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS2 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__vs2_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper2 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__cl2_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS2 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__hs2_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS2 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__ds2_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS2 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__gs2_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF2 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__sf2_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO2 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__so2_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL2 Stall */
#define acmgt3__render_pipe_profile__slice2__cl2_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS2 Stall */
#define acmgt3__render_pipe_profile__slice2__hs2_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS2 Stall */
#define acmgt3__render_pipe_profile__slice2__ds2_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF2 Stall */
#define acmgt3__render_pipe_profile__slice2__sf2_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO2 Stall */
#define acmgt3__render_pipe_profile__slice2__so2_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth20 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__hi_depth20_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC20 Bottleneck */
#define acmgt3__render_pipe_profile__slice2__bc20_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt3__render_pipe_profile__slice3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt3__render_pipe_profile__slice3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt3__render_pipe_profile__slice3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF3 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__vf3_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS3 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__vs3_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper3 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__cl3_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS3 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__hs3_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS3 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__ds3_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS3 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__gs3_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF3 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__sf3_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO3 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__so3_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL3 Stall */
#define acmgt3__render_pipe_profile__slice3__cl3_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS3 Stall */
#define acmgt3__render_pipe_profile__slice3__hs3_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS3 Stall */
#define acmgt3__render_pipe_profile__slice3__ds3_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF3 Stall */
#define acmgt3__render_pipe_profile__slice3__sf3_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO3 Stall */
#define acmgt3__render_pipe_profile__slice3__so3_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth30 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__hi_depth30_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC30 Bottleneck */
#define acmgt3__render_pipe_profile__slice3__bc30_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt3__render_pipe_profile__slice4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt3__render_pipe_profile__slice4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt3__render_pipe_profile__slice4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF4 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__vf4_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS4 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__vs4_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper4 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__cl4_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS4 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__hs4_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS4 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__ds4_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS4 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__gs4_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF4 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__sf4_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO4 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__so4_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL4 Stall */
#define acmgt3__render_pipe_profile__slice4__cl4_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS4 Stall */
#define acmgt3__render_pipe_profile__slice4__hs4_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS4 Stall */
#define acmgt3__render_pipe_profile__slice4__ds4_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF4 Stall */
#define acmgt3__render_pipe_profile__slice4__sf4_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO4 Stall */
#define acmgt3__render_pipe_profile__slice4__so4_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth40 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__hi_depth40_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC40 Bottleneck */
#define acmgt3__render_pipe_profile__slice4__bc40_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt3__render_pipe_profile__slice5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt3__render_pipe_profile__slice5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt3__render_pipe_profile__slice5__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF5 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__vf5_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS5 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__vs5_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper5 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__cl5_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS5 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__hs5_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS5 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__ds5_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS5 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__gs5_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF5 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__sf5_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO5 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__so5_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL5 Stall */
#define acmgt3__render_pipe_profile__slice5__cl5_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS5 Stall */
#define acmgt3__render_pipe_profile__slice5__hs5_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS5 Stall */
#define acmgt3__render_pipe_profile__slice5__ds5_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF5 Stall */
#define acmgt3__render_pipe_profile__slice5__sf5_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO5 Stall */
#define acmgt3__render_pipe_profile__slice5__so5_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth50 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__hi_depth50_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC50 Bottleneck */
#define acmgt3__render_pipe_profile__slice5__bc50_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt3__render_pipe_profile__slice6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt3__render_pipe_profile__slice6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt3__render_pipe_profile__slice6__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF6 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__vf6_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS6 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__vs6_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper6 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__cl6_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS6 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__hs6_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS6 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__ds6_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS6 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__gs6_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF6 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__sf6_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO6 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__so6_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL6 Stall */
#define acmgt3__render_pipe_profile__slice6__cl6_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS6 Stall */
#define acmgt3__render_pipe_profile__slice6__hs6_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS6 Stall */
#define acmgt3__render_pipe_profile__slice6__ds6_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF6 Stall */
#define acmgt3__render_pipe_profile__slice6__sf6_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO6 Stall */
#define acmgt3__render_pipe_profile__slice6__so6_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth60 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__hi_depth60_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC60 Bottleneck */
#define acmgt3__render_pipe_profile__slice6__bc60_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define acmgt3__render_pipe_profile__slice7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define acmgt3__render_pipe_profile__slice7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define acmgt3__render_pipe_profile__slice7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define acmgt3__render_pipe_profile__slice7__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF7 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__vf7_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS7 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__vs7_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper7 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__cl7_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS7 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__hs7_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS7 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__ds7_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS7 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__gs7_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF7 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__sf7_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO7 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__so7_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL7 Stall */
#define acmgt3__render_pipe_profile__slice7__cl7_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS7 Stall */
#define acmgt3__render_pipe_profile__slice7__hs7_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS7 Stall */
#define acmgt3__render_pipe_profile__slice7__ds7_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF7 Stall */
#define acmgt3__render_pipe_profile__slice7__sf7_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO7 Stall */
#define acmgt3__render_pipe_profile__slice7__so7_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth70 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__hi_depth70_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC70 Bottleneck */
#define acmgt3__render_pipe_profile__slice7__bc70_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_Slice01 :: GPU Time Elapsed */
#define acmgt3__sampler__slice01__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_Slice01 :: GPU Core Clocks */
#define acmgt3__sampler__slice01__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_Slice01 :: AVG GPU Core Frequency */
#define acmgt3__sampler__slice01__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_Slice01 :: AVG GPU Core Frequency */
#define acmgt3__sampler__slice01__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_Slice01 :: GPU Busy */
#define acmgt3__sampler__slice01__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_Slice01 :: Slice0 Xe Core0 Input Available */
#define acmgt3__sampler__slice01__sampler00_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler_Slice01 :: Slice0 Xe Core1 Input Available */
#define acmgt3__sampler__slice01__sampler01_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_Slice01 :: Slice0 Xe Core2 Input Available */
#define acmgt3__sampler__slice01__sampler02_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler_Slice01 :: Slice0 Xe Core3 Input Available */
#define acmgt3__sampler__slice01__sampler03_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler_Slice01 :: Slice1 Xe Core0 Input Available */
#define acmgt3__sampler__slice01__sampler10_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler_Slice01 :: Slice1 Xe Core1 Input Available */
#define acmgt3__sampler__slice01__sampler11_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler_Slice01 :: Slice1 Xe Core2 Input Available */
#define acmgt3__sampler__slice01__sampler12_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler_Slice01 :: Slice1 Xe Core3 Input Available */
#define acmgt3__sampler__slice01__sampler13_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Sampler_Slice01 :: Slice0 Xe Core0 Sampler Output Ready */
#define acmgt3__sampler__slice01__sampler00_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler_Slice01 :: Slice0 Xe Core1 Sampler Output Ready */
#define acmgt3__sampler__slice01__sampler01_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler_Slice01 :: Slice0 Xe Core2 Sampler Output Ready */
#define acmgt3__sampler__slice01__sampler02_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_Slice01 :: Slice0 Xe Core3 Sampler Output Ready */
#define acmgt3__sampler__slice01__sampler03_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_Slice01 :: Slice1 Xe Core0 Sampler Output Ready */
#define acmgt3__sampler__slice01__sampler10_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_Slice01 :: Slice1 Xe Core1 Sampler Output Ready */
#define acmgt3__sampler__slice01__sampler11_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_Slice01 :: Slice1 Xe Core2 Sampler Output Ready */
#define acmgt3__sampler__slice01__sampler12_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_Slice01 :: Slice1 Xe Core3 Sampler Output Ready */
#define acmgt3__sampler__slice01__sampler13_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_Slice23 :: GPU Time Elapsed */
#define acmgt3__sampler__slice23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_Slice23 :: GPU Core Clocks */
#define acmgt3__sampler__slice23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_Slice23 :: AVG GPU Core Frequency */
#define acmgt3__sampler__slice23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_Slice23 :: AVG GPU Core Frequency */
#define acmgt3__sampler__slice23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_Slice23 :: GPU Busy */
#define acmgt3__sampler__slice23__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_Slice23 :: Slice2 Xe Core0 Input Available */
#define acmgt3__sampler__slice23__sampler20_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core1 Input Available */
#define acmgt3__sampler__slice23__sampler21_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core2 Input Available */
#define acmgt3__sampler__slice23__sampler22_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler_Slice23 :: Slice2 Xe Core3 Input Available */
#define acmgt3__sampler__slice23__sampler23_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler_Slice23 :: Slice3 Xe Core0 Input Available */
#define acmgt3__sampler__slice23__sampler30_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler_Slice23 :: Slice3 Xe Core1 Input Available */
#define acmgt3__sampler__slice23__sampler31_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler_Slice23 :: Slice3 Xe Core2 Input Available */
#define acmgt3__sampler__slice23__sampler32_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler_Slice23 :: Slice3 Xe Core3 Input Available */
#define acmgt3__sampler__slice23__sampler33_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core0 Sampler Output Ready */
#define acmgt3__sampler__slice23__sampler20_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core1 Sampler Output Ready */
#define acmgt3__sampler__slice23__sampler21_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core2 Sampler Output Ready */
#define acmgt3__sampler__slice23__sampler22_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_Slice23 :: Slice2 Xe Core3 Sampler Output Ready */
#define acmgt3__sampler__slice23__sampler23_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_Slice23 :: Slice3 Xe Core0 Sampler Output Ready */
#define acmgt3__sampler__slice23__sampler30_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_Slice23 :: Slice3 Xe Core1 Sampler Output Ready */
#define acmgt3__sampler__slice23__sampler31_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_Slice23 :: Slice3 Xe Core2 Sampler Output Ready */
#define acmgt3__sampler__slice23__sampler32_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_Slice23 :: Slice3 Xe Core3 Sampler Output Ready */
#define acmgt3__sampler__slice23__sampler33_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_Slice45 :: GPU Time Elapsed */
#define acmgt3__sampler__slice45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_Slice45 :: GPU Core Clocks */
#define acmgt3__sampler__slice45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_Slice45 :: AVG GPU Core Frequency */
#define acmgt3__sampler__slice45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_Slice45 :: AVG GPU Core Frequency */
#define acmgt3__sampler__slice45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_Slice45 :: GPU Busy */
#define acmgt3__sampler__slice45__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_Slice45 :: Slice4 Xe Core0 Input Available */
#define acmgt3__sampler__slice45__sampler40_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler_Slice45 :: Slice4 Xe Core1 Input Available */
#define acmgt3__sampler__slice45__sampler41_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_Slice45 :: Slice4 Xe Core2 Input Available */
#define acmgt3__sampler__slice45__sampler42_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler_Slice45 :: Slice4 Xe Core3 Input Available */
#define acmgt3__sampler__slice45__sampler43_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler_Slice45 :: Slice5 Xe Core0 Input Available */
#define acmgt3__sampler__slice45__sampler50_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler_Slice45 :: Slice5 Xe Core1 Input Available */
#define acmgt3__sampler__slice45__sampler51_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler_Slice45 :: Slice5 Xe Core2 Input Available */
#define acmgt3__sampler__slice45__sampler52_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler_Slice45 :: Slice5 Xe Core3 Input Available */
#define acmgt3__sampler__slice45__sampler53_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Sampler_Slice45 :: Slice4 Xe Core0 Sampler Output Ready */
#define acmgt3__sampler__slice45__sampler40_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler_Slice45 :: Slice4 Xe Core1 Sampler Output Ready */
#define acmgt3__sampler__slice45__sampler41_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler_Slice45 :: Slice4 Xe Core2 Sampler Output Ready */
#define acmgt3__sampler__slice45__sampler42_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_Slice45 :: Slice4 Xe Core3 Sampler Output Ready */
#define acmgt3__sampler__slice45__sampler43_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_Slice45 :: Slice5 Xe Core0 Sampler Output Ready */
#define acmgt3__sampler__slice45__sampler50_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_Slice45 :: Slice5 Xe Core1 Sampler Output Ready */
#define acmgt3__sampler__slice45__sampler51_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_Slice45 :: Slice5 Xe Core2 Sampler Output Ready */
#define acmgt3__sampler__slice45__sampler52_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_Slice45 :: Slice5 Xe Core3 Sampler Output Ready */
#define acmgt3__sampler__slice45__sampler53_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_Slice67 :: GPU Time Elapsed */
#define acmgt3__sampler__slice67__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_Slice67 :: GPU Core Clocks */
#define acmgt3__sampler__slice67__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_Slice67 :: AVG GPU Core Frequency */
#define acmgt3__sampler__slice67__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_Slice67 :: AVG GPU Core Frequency */
#define acmgt3__sampler__slice67__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_Slice67 :: GPU Busy */
#define acmgt3__sampler__slice67__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_Slice67 :: Slice6 Xe Core0 Input Available */
#define acmgt3__sampler__slice67__sampler60_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler_Slice67 :: Slice6 Xe Core1 Input Available */
#define acmgt3__sampler__slice67__sampler61_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_Slice67 :: Slice6 Xe Core2 Input Available */
#define acmgt3__sampler__slice67__sampler62_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler_Slice67 :: Slice6 Xe Core3 Input Available */
#define acmgt3__sampler__slice67__sampler63_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler_Slice67 :: Slice7 Xe Core0 Input Available */
#define acmgt3__sampler__slice67__sampler70_input_available__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler_Slice67 :: Slice7 Xe Core1 Input Available */
#define acmgt3__sampler__slice67__sampler71_input_available__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler_Slice67 :: Slice7 Xe Core2 Input Available */
#define acmgt3__sampler__slice67__sampler72_input_available__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler_Slice67 :: Slice7 Xe Core3 Input Available */
#define acmgt3__sampler__slice67__sampler73_input_available__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Sampler_Slice67 :: Slice6 Xe Core0 Sampler Output Ready */
#define acmgt3__sampler__slice67__sampler60_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler_Slice67 :: Slice6 Xe Core1 Sampler Output Ready */
#define acmgt3__sampler__slice67__sampler61_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler_Slice67 :: Slice6 Xe Core2 Sampler Output Ready */
#define acmgt3__sampler__slice67__sampler62_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_Slice67 :: Slice6 Xe Core3 Sampler Output Ready */
#define acmgt3__sampler__slice67__sampler63_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_Slice67 :: Slice7 Xe Core0 Sampler Output Ready */
#define acmgt3__sampler__slice67__sampler70_output_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_Slice67 :: Slice7 Xe Core1 Sampler Output Ready */
#define acmgt3__sampler__slice67__sampler71_output_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_Slice67 :: Slice7 Xe Core2 Sampler Output Ready */
#define acmgt3__sampler__slice67__sampler72_output_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_Slice67 :: Slice7 Xe Core3 Sampler Output Ready */
#define acmgt3__sampler__slice67__sampler73_output_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice01_1 :: GPU Time Elapsed */
#define acmgt3__tdl__slice01_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice01_1 :: GPU Core Clocks */
#define acmgt3__tdl__slice01_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice01_1 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice01_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice01_1 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice01_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice01_1 :: GPU Busy */
#define acmgt3__tdl__slice01_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice01_1 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice01_1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice01_1 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice01_1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice01_1 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice01_1__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice01_1 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice01_1__non_ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice01_1 :: Non-PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice01_1__non_ps_thread10_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice01_1 :: Non-PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice01_1__non_ps_thread11_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice01_1 :: Non-PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice01_1__non_ps_thread12_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice01_1 :: Non-PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice01_1__non_ps_thread13_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice01_1 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice01_1__thread_header03_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice01_1 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice01_1__thread_header03_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice01_1 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice01_1__thread_header03_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice01_1 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice01_1__thread_header03_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice01_1 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice01_1__thread_header13_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice01_1 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice01_1__thread_header13_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice01_1 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice01_1__thread_header13_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice01_1 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice01_1__thread_header13_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice01_2 :: GPU Time Elapsed */
#define acmgt3__tdl__slice01_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice01_2 :: GPU Core Clocks */
#define acmgt3__tdl__slice01_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice01_2 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice01_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice01_2 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice01_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice01_2 :: GPU Busy */
#define acmgt3__tdl__slice01_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice01_2 :: PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice01_2__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice01_2 :: PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice01_2__ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice01_2 :: PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice01_2__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice01_2 :: PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice01_2__ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice01_2 :: PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice01_2__ps_thread10_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice01_2 :: PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice01_2__ps_thread11_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice01_2 :: PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice01_2__ps_thread12_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice01_2 :: PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice01_2__ps_thread13_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice01_3 :: GPU Time Elapsed */
#define acmgt3__tdl__slice01_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice01_3 :: GPU Core Clocks */
#define acmgt3__tdl__slice01_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice01_3 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice01_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice01_3 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice01_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice01_3 :: GPU Busy */
#define acmgt3__tdl__slice01_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice01_3__thread_header00_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice01_3__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice01_3__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice01_3__thread_header00_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice01_3__thread_header00_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice01_3__thread_header01_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice01_3__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice01_3__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice01_3__thread_header01_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice01_3__thread_header01_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice01_3__thread_header02_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice01_3__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice01_3__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice01_3__thread_header02_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice01_3__thread_header02_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice01_3 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice01_3__thread_header03_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice01_4 :: GPU Time Elapsed */
#define acmgt3__tdl__slice01_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice01_4 :: GPU Core Clocks */
#define acmgt3__tdl__slice01_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice01_4 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice01_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice01_4 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice01_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice01_4 :: GPU Busy */
#define acmgt3__tdl__slice01_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice01_4__thread_header10_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice01_4__thread_header10_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice01_4__thread_header10_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice01_4__thread_header10_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice01_4__thread_header10_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice01_4__thread_header11_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice01_4__thread_header11_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice01_4__thread_header11_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice01_4__thread_header11_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice01_4__thread_header11_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice01_4__thread_header12_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice01_4__thread_header12_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice01_4__thread_header12_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice01_4__thread_header12_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice01_4__thread_header12_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice01_4 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice01_4__thread_header13_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice23_1 :: GPU Time Elapsed */
#define acmgt3__tdl__slice23_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice23_1 :: GPU Core Clocks */
#define acmgt3__tdl__slice23_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice23_1 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice23_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice23_1 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice23_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice23_1 :: GPU Busy */
#define acmgt3__tdl__slice23_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice23_1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice23_1__non_ps_thread20_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice23_1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice23_1__non_ps_thread21_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice23_1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice23_1__non_ps_thread22_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice23_1 :: Non-PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice23_1__non_ps_thread23_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice23_1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice23_1__non_ps_thread30_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice23_1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice23_1__non_ps_thread31_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice23_1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice23_1__non_ps_thread32_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice23_1 :: Non-PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice23_1__non_ps_thread33_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice23_1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice23_1__thread_header23_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice23_1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice23_1__thread_header23_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice23_1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice23_1__thread_header23_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice23_1 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice23_1__thread_header23_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice23_1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice23_1__thread_header33_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice23_1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice23_1__thread_header33_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice23_1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice23_1__thread_header33_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice23_1 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice23_1__thread_header33_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice23_2 :: GPU Time Elapsed */
#define acmgt3__tdl__slice23_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice23_2 :: GPU Core Clocks */
#define acmgt3__tdl__slice23_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice23_2 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice23_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice23_2 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice23_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice23_2 :: GPU Busy */
#define acmgt3__tdl__slice23_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice23_2 :: PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice23_2__ps_thread20_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice23_2 :: PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice23_2__ps_thread21_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice23_2 :: PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice23_2__ps_thread22_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice23_2 :: PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice23_2__ps_thread23_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice23_2 :: PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice23_2__ps_thread30_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice23_2 :: PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice23_2__ps_thread31_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice23_2 :: PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice23_2__ps_thread32_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice23_2 :: PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice23_2__ps_thread33_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice23_3 :: GPU Time Elapsed */
#define acmgt3__tdl__slice23_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice23_3 :: GPU Core Clocks */
#define acmgt3__tdl__slice23_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice23_3 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice23_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice23_3 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice23_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice23_3 :: GPU Busy */
#define acmgt3__tdl__slice23_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice23_3__thread_header20_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice23_3__thread_header20_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice23_3__thread_header20_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice23_3__thread_header20_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice23_3__thread_header20_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice23_3__thread_header21_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice23_3__thread_header21_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice23_3__thread_header21_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice23_3__thread_header21_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice23_3__thread_header21_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice23_3__thread_header22_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice23_3__thread_header22_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice23_3__thread_header22_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice23_3__thread_header22_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice23_3__thread_header22_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice23_3 :: Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice23_3__thread_header23_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice23_4 :: GPU Time Elapsed */
#define acmgt3__tdl__slice23_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice23_4 :: GPU Core Clocks */
#define acmgt3__tdl__slice23_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice23_4 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice23_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice23_4 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice23_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice23_4 :: GPU Busy */
#define acmgt3__tdl__slice23_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice23_4__thread_header30_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice23_4__thread_header30_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice23_4__thread_header30_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice23_4__thread_header30_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice23_4__thread_header30_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice23_4__thread_header31_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice23_4__thread_header31_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice23_4__thread_header31_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice23_4__thread_header31_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice23_4__thread_header31_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice23_4__thread_header32_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice23_4__thread_header32_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice23_4__thread_header32_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice23_4__thread_header32_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice23_4__thread_header32_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice23_4 :: Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice23_4__thread_header33_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice45_1 :: GPU Time Elapsed */
#define acmgt3__tdl__slice45_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice45_1 :: GPU Core Clocks */
#define acmgt3__tdl__slice45_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice45_1 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice45_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice45_1 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice45_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice45_1 :: GPU Busy */
#define acmgt3__tdl__slice45_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice45_1 :: Non-PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice45_1__non_ps_thread40_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice45_1 :: Non-PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice45_1__non_ps_thread41_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice45_1 :: Non-PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice45_1__non_ps_thread42_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice45_1 :: Non-PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice45_1__non_ps_thread43_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice45_1 :: Non-PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice45_1__non_ps_thread50_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice45_1 :: Non-PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice45_1__non_ps_thread51_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice45_1 :: Non-PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice45_1__non_ps_thread52_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice45_1 :: Non-PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice45_1__non_ps_thread53_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice45_1 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice45_1__thread_header43_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice45_1 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice45_1__thread_header43_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice45_1 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice45_1__thread_header43_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice45_1 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice45_1__thread_header43_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice45_1 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice45_1__thread_header53_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice45_1 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice45_1__thread_header53_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice45_1 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice45_1__thread_header53_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice45_1 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice45_1__thread_header53_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice45_2 :: GPU Time Elapsed */
#define acmgt3__tdl__slice45_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice45_2 :: GPU Core Clocks */
#define acmgt3__tdl__slice45_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice45_2 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice45_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice45_2 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice45_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice45_2 :: GPU Busy */
#define acmgt3__tdl__slice45_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice45_2 :: PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice45_2__ps_thread40_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice45_2 :: PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice45_2__ps_thread41_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice45_2 :: PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice45_2__ps_thread42_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice45_2 :: PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice45_2__ps_thread43_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice45_2 :: PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice45_2__ps_thread50_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice45_2 :: PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice45_2__ps_thread51_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice45_2 :: PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice45_2__ps_thread52_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice45_2 :: PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice45_2__ps_thread53_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice45_3 :: GPU Time Elapsed */
#define acmgt3__tdl__slice45_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice45_3 :: GPU Core Clocks */
#define acmgt3__tdl__slice45_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice45_3 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice45_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice45_3 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice45_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice45_3 :: GPU Busy */
#define acmgt3__tdl__slice45_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice45_3__thread_header40_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice45_3__thread_header40_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice45_3__thread_header40_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice45_3__thread_header40_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice45_3__thread_header40_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice45_3__thread_header41_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice45_3__thread_header41_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice45_3__thread_header41_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice45_3__thread_header41_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice45_3__thread_header41_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice45_3__thread_header42_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice45_3__thread_header42_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice45_3__thread_header42_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice45_3__thread_header42_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice45_3__thread_header42_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice45_3 :: Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice45_3__thread_header43_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice45_4 :: GPU Time Elapsed */
#define acmgt3__tdl__slice45_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice45_4 :: GPU Core Clocks */
#define acmgt3__tdl__slice45_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice45_4 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice45_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice45_4 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice45_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice45_4 :: GPU Busy */
#define acmgt3__tdl__slice45_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice45_4__thread_header50_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice45_4__thread_header50_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice45_4__thread_header50_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice45_4__thread_header50_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice45_4__thread_header50_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice45_4__thread_header51_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice45_4__thread_header51_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice45_4__thread_header51_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice45_4__thread_header51_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice45_4__thread_header51_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice45_4__thread_header52_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice45_4__thread_header52_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice45_4__thread_header52_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice45_4__thread_header52_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice45_4__thread_header52_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice45_4 :: Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice45_4__thread_header53_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice67_1 :: GPU Time Elapsed */
#define acmgt3__tdl__slice67_1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice67_1 :: GPU Core Clocks */
#define acmgt3__tdl__slice67_1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice67_1 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice67_1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice67_1 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice67_1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice67_1 :: GPU Busy */
#define acmgt3__tdl__slice67_1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice67_1 :: Non-PS Thread Ready For Dispatch on Slice6 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice67_1__non_ps_thread60_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice67_1 :: Non-PS Thread Ready For Dispatch on Slice6 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice67_1__non_ps_thread61_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice67_1 :: Non-PS Thread Ready For Dispatch on Slice6 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice67_1__non_ps_thread62_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice67_1 :: Non-PS Thread Ready For Dispatch on Slice6 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice67_1__non_ps_thread63_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice67_1 :: Non-PS Thread Ready For Dispatch on Slice7 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice67_1__non_ps_thread70_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice67_1 :: Non-PS Thread Ready For Dispatch on Slice7 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice67_1__non_ps_thread71_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice67_1 :: Non-PS Thread Ready For Dispatch on Slice7 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice67_1__non_ps_thread72_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice67_1 :: Non-PS Thread Ready For Dispatch on Slice7 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice67_1__non_ps_thread73_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice67_1 :: Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice67_1__thread_header63_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice67_1 :: Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice67_1__thread_header63_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice67_1 :: Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice67_1__thread_header63_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice67_1 :: Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice67_1__thread_header63_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice67_1 :: Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice67_1__thread_header73_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice67_1 :: Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice67_1__thread_header73_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice67_1 :: Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice67_1__thread_header73_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice67_1 :: Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice67_1__thread_header73_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice67_2 :: GPU Time Elapsed */
#define acmgt3__tdl__slice67_2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice67_2 :: GPU Core Clocks */
#define acmgt3__tdl__slice67_2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice67_2 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice67_2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice67_2 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice67_2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice67_2 :: GPU Busy */
#define acmgt3__tdl__slice67_2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice67_2 :: PS Thread Ready For Dispatch on Slice6 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice67_2__ps_thread60_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice67_2 :: PS Thread Ready For Dispatch on Slice6 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice67_2__ps_thread61_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice67_2 :: PS Thread Ready For Dispatch on Slice6 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice67_2__ps_thread62_ready_for_dispatch__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice67_2 :: PS Thread Ready For Dispatch on Slice6 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice67_2__ps_thread63_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice67_2 :: PS Thread Ready For Dispatch on Slice7 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice67_2__ps_thread70_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice67_2 :: PS Thread Ready For Dispatch on Slice7 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice67_2__ps_thread71_ready_for_dispatch__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice67_2 :: PS Thread Ready For Dispatch on Slice7 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice67_2__ps_thread72_ready_for_dispatch__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice67_2 :: PS Thread Ready For Dispatch on Slice7 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice67_2__ps_thread73_ready_for_dispatch__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice67_3 :: GPU Time Elapsed */
#define acmgt3__tdl__slice67_3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice67_3 :: GPU Core Clocks */
#define acmgt3__tdl__slice67_3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice67_3 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice67_3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice67_3 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice67_3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice67_3 :: GPU Busy */
#define acmgt3__tdl__slice67_3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice67_3__thread_header60_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice67_3__thread_header60_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice67_3__thread_header60_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice67_3__thread_header60_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice67_3__thread_header60_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice67_3__thread_header61_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice67_3__thread_header61_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice67_3__thread_header61_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice67_3__thread_header61_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice67_3__thread_header61_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice67_3__thread_header62_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice67_3__thread_header62_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice67_3__thread_header62_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice67_3__thread_header62_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice67_3__thread_header62_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice67_3 :: Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice67_3__thread_header63_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL_Slice67_4 :: GPU Time Elapsed */
#define acmgt3__tdl__slice67_4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL_Slice67_4 :: GPU Core Clocks */
#define acmgt3__tdl__slice67_4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL_Slice67_4 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice67_4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL_Slice67_4 :: AVG GPU Core Frequency */
#define acmgt3__tdl__slice67_4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL_Slice67_4 :: GPU Busy */
#define acmgt3__tdl__slice67_4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher */
#define acmgt3__tdl__slice67_4__thread_header70_ready__read \
   bdw__render_basic__sampler0_busy__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice67_4__thread_header70_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice67_4__thread_header70_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice67_4__thread_header70_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice67_4__thread_header70_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher */
#define acmgt3__tdl__slice67_4__thread_header71_ready__read \
   bdw__render_basic__sampler1_busy__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice67_4__thread_header71_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice67_4__thread_header71_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice67_4__thread_header71_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice67_4__thread_header71_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher */
#define acmgt3__tdl__slice67_4__thread_header72_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 0 */
#define acmgt3__tdl__slice67_4__thread_header72_ready_port0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 1 */
#define acmgt3__tdl__slice67_4__thread_header72_ready_port1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 2 */
#define acmgt3__tdl__slice67_4__thread_header72_ready_port2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 3 */
#define acmgt3__tdl__slice67_4__thread_header72_ready_port3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL_Slice67_4 :: Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher */
#define acmgt3__tdl__slice67_4__thread_header73_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* ComputeOverview :: GPU Time Elapsed */
#define acmgt3__compute_overview__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* ComputeOverview :: GPU Core Clocks */
#define acmgt3__compute_overview__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* ComputeOverview :: AVG GPU Core Frequency */
#define acmgt3__compute_overview__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* ComputeOverview :: AVG GPU Core Frequency */
#define acmgt3__compute_overview__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* ComputeOverview :: L3 BYTE READ */
#define acmgt3__compute_overview__l3_byte_read__read \
   acmgt1__compute_overview__l3_byte_read__read

/* ComputeOverview :: L3 BYTE READ */
#define acmgt3__compute_overview__l3_byte_read__max \
   acmgt1__compute_overview__l3_byte_read__max

/* ComputeOverview :: L3 BYTE WRITE */
#define acmgt3__compute_overview__l3_byte_write__read \
   acmgt1__compute_overview__l3_byte_write__read

/* ComputeOverview :: L3 BYTE WRITE */
#define acmgt3__compute_overview__l3_byte_write__max \
   acmgt1__compute_overview__l3_byte_read__max

/* ComputeOverview :: GPU MEMORY BYTE READ */
#define acmgt3__compute_overview__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* ComputeOverview :: GPU MEMORY BYTE READ */
#define acmgt3__compute_overview__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* ComputeOverview :: GPU MEMORY BYTE WRITE */
#define acmgt3__compute_overview__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* ComputeOverview :: GPU MEMORY BYTE WRITE */
#define acmgt3__compute_overview__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* ComputeOverview :: XVE ACTIVE */
#define acmgt3__compute_overview__xve_active__read \
   bdw__render_basic__eu_active__read

/* ComputeOverview :: XVE STALL */
#define acmgt3__compute_overview__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* ComputeOverview :: XVE BUSY */
#define acmgt3__compute_overview__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* ComputeOverview :: XVE BUSY */
#define acmgt3__compute_overview__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* ComputeOverview :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__compute_overview__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* ComputeOverview :: XVE COMPUTE THREAD COUNT */
#define acmgt3__compute_overview__xve_compute_thread_count__read \
   bdw__render_basic__cs_threads__read

/* ComputeOverview :: XVE ATOMIC ACCESS COUNT */
#define acmgt3__compute_overview__xve_atomic_access_count__read \
   bdw__render_basic__shader_atomics__read

/* ComputeOverview :: XVE BARRIER MESSAGE COUNT */
#define acmgt3__compute_overview__xve_barrier_message_count__read \
   hsw__render_basic__early_depth_test_fails__read

/* ComputeOverview :: XVE INST EXECUTED ALU0 ALL */
#define acmgt3__compute_overview__xve_inst_executed_alu0_all__read \
   hsw__render_basic__hs_threads__read

/* ComputeOverview :: XVE INST EXECUTED ALU0 ALL */
#define acmgt3__compute_overview__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* ComputeOverview :: XVE INST EXECUTED ALU1 ALL */
#define acmgt3__compute_overview__xve_inst_executed_alu1_all__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* ComputeOverview :: XVE INST EXECUTED ALU1 ALL */
#define acmgt3__compute_overview__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* ComputeOverview :: XVE INST EXECUTED XMX ALL */
#define acmgt3__compute_overview__xve_inst_executed_xmx_all__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* ComputeOverview :: XVE INST EXECUTED XMX ALL */
#define acmgt3__compute_overview__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* ComputeOverview :: XVE INST EXECUTED SEND ALL */
#define acmgt3__compute_overview__xve_inst_executed_send_all__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* ComputeOverview :: XVE INST EXECUTED SEND ALL */
#define acmgt3__compute_overview__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* ComputeOverview :: XVE INST EXECUTED CONTROL ALL */
#define acmgt3__compute_overview__xve_inst_executed_control_all__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* ComputeOverview :: XVE INST EXECUTED CONTROL ALL */
#define acmgt3__compute_overview__xve_inst_executed_control_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* ComputeOverview :: XVE PIPE ALU0 AND ALU1 ACTIVE */
#define acmgt3__compute_overview__xve_pipe_alu0_and_alu1_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* ComputeOverview :: XVE PIPE ALU0 AND XMX ACTIVE */
#define acmgt3__compute_overview__xve_pipe_alu0_and_xmx_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* ComputeOverview :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define acmgt3__compute_overview__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* ComputeOverview :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define acmgt3__compute_overview__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* ComputeOverview :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define acmgt3__compute_overview__xve_inst_executed_send_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* ComputeOverview :: XVE INST EXECUTED CONTROL ALL UTILIZATION */
#define acmgt3__compute_overview__xve_inst_executed_control_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* ComputeOverview :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define acmgt3__compute_overview__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__vs_send_active__read

/* L1ProfileReads :: GPU Time Elapsed */
#define acmgt3__l1_profile_reads__xe_core0__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileReads :: GPU Core Clocks */
#define acmgt3__l1_profile_reads__xe_core0__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileReads :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_reads__xe_core0__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileReads :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_reads__xe_core0__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileReads :: LOAD STORE CACHE BYTE READ */
#define acmgt3__l1_profile_reads__xe_core0__load_store_cache_byte_read__read \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__read

/* L1ProfileReads :: LOAD STORE CACHE BYTE READ */
#define acmgt3__l1_profile_reads__xe_core0__load_store_cache_byte_read__max \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max

/* L1ProfileReads :: SLM BYTE READ */
#define acmgt3__l1_profile_reads__xe_core0__slm_byte_read__read \
   acmgt1__l1_profile_reads__xe_core0__slm_byte_read__read

/* L1ProfileReads :: SLM BYTE READ */
#define acmgt3__l1_profile_reads__xe_core0__slm_byte_read__max \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max

/* L1ProfileReads :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileReads :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileReads :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileReads :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileReads :: XVE ACTIVE */
#define acmgt3__l1_profile_reads__xe_core0__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileReads :: XVE STALL */
#define acmgt3__l1_profile_reads__xe_core0__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileReads :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__l1_profile_reads__xe_core0__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileReads :: XVE BUSY */
#define acmgt3__l1_profile_reads__xe_core0__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileReads :: XVE BUSY */
#define acmgt3__l1_profile_reads__xe_core0__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileReads :: GPU Time Elapsed */
#define acmgt3__l1_profile_reads__xe_core3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileReads :: GPU Core Clocks */
#define acmgt3__l1_profile_reads__xe_core3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileReads :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_reads__xe_core3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileReads :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_reads__xe_core3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileReads :: LOAD STORE CACHE BYTE READ */
#define acmgt3__l1_profile_reads__xe_core3__load_store_cache_byte_read__read \
   acmgt1__l1_profile_reads__xe_core3__load_store_cache_byte_read__read

/* L1ProfileReads :: LOAD STORE CACHE BYTE READ */
#define acmgt3__l1_profile_reads__xe_core3__load_store_cache_byte_read__max \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max

/* L1ProfileReads :: SLM BYTE READ */
#define acmgt3__l1_profile_reads__xe_core3__slm_byte_read__read \
   acmgt1__l1_profile_reads__xe_core3__slm_byte_read__read

/* L1ProfileReads :: SLM BYTE READ */
#define acmgt3__l1_profile_reads__xe_core3__slm_byte_read__max \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max

/* L1ProfileReads :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileReads :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileReads :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileReads :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileReads :: XVE ACTIVE */
#define acmgt3__l1_profile_reads__xe_core3__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileReads :: XVE STALL */
#define acmgt3__l1_profile_reads__xe_core3__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileReads :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__l1_profile_reads__xe_core3__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileReads :: XVE BUSY */
#define acmgt3__l1_profile_reads__xe_core3__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileReads :: XVE BUSY */
#define acmgt3__l1_profile_reads__xe_core3__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileSlmBankConflicts :: GPU Time Elapsed */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileSlmBankConflicts :: GPU Core Clocks */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileSlmBankConflicts :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileSlmBankConflicts :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileSlmBankConflicts :: SLM BANK CONFLICT COUNT */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__slm_bank_conflict_count__read \
   acmgt1__l1_profile_slm_bank_conflicts__xe_core0__slm_bank_conflict_count__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileSlmBankConflicts :: XVE ACTIVE */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileSlmBankConflicts :: XVE STALL */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileSlmBankConflicts :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileSlmBankConflicts :: XVE BUSY */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileSlmBankConflicts :: XVE BUSY */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileSlmBankConflicts :: GPU Time Elapsed */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileSlmBankConflicts :: GPU Core Clocks */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileSlmBankConflicts :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileSlmBankConflicts :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileSlmBankConflicts :: SLM BANK CONFLICT COUNT */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__slm_bank_conflict_count__read \
   acmgt1__l1_profile_slm_bank_conflicts__xe_core3__slm_bank_conflict_count__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileSlmBankConflicts :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileSlmBankConflicts :: XVE ACTIVE */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileSlmBankConflicts :: XVE STALL */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileSlmBankConflicts :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileSlmBankConflicts :: XVE BUSY */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileSlmBankConflicts :: XVE BUSY */
#define acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileWrites :: GPU Time Elapsed */
#define acmgt3__l1_profile_writes__xe_core0__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileWrites :: GPU Core Clocks */
#define acmgt3__l1_profile_writes__xe_core0__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileWrites :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_writes__xe_core0__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileWrites :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_writes__xe_core0__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileWrites :: LOAD STORE CACHE BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core0__load_store_cache_byte_write__read \
   acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__read

/* L1ProfileWrites :: LOAD STORE CACHE BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core0__load_store_cache_byte_write__max \
   acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max

/* L1ProfileWrites :: SLM BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core0__slm_byte_write__read \
   acmgt1__l1_profile_reads__xe_core0__slm_byte_read__read

/* L1ProfileWrites :: SLM BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core0__slm_byte_write__max \
   acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max

/* L1ProfileWrites :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileWrites :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileWrites :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileWrites :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileWrites :: XVE ACTIVE */
#define acmgt3__l1_profile_writes__xe_core0__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileWrites :: XVE STALL */
#define acmgt3__l1_profile_writes__xe_core0__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileWrites :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__l1_profile_writes__xe_core0__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileWrites :: XVE BUSY */
#define acmgt3__l1_profile_writes__xe_core0__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileWrites :: XVE BUSY */
#define acmgt3__l1_profile_writes__xe_core0__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* L1ProfileWrites :: GPU Time Elapsed */
#define acmgt3__l1_profile_writes__xe_core3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L1ProfileWrites :: GPU Core Clocks */
#define acmgt3__l1_profile_writes__xe_core3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L1ProfileWrites :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_writes__xe_core3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L1ProfileWrites :: AVG GPU Core Frequency */
#define acmgt3__l1_profile_writes__xe_core3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L1ProfileWrites :: LOAD STORE CACHE BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core3__load_store_cache_byte_write__read \
   acmgt1__l1_profile_reads__xe_core3__load_store_cache_byte_read__read

/* L1ProfileWrites :: LOAD STORE CACHE BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core3__load_store_cache_byte_write__max \
   acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max

/* L1ProfileWrites :: SLM BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core3__slm_byte_write__read \
   acmgt1__l1_profile_reads__xe_core3__slm_byte_read__read

/* L1ProfileWrites :: SLM BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core3__slm_byte_write__max \
   acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max

/* L1ProfileWrites :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* L1ProfileWrites :: GPU MEMORY BYTE READ */
#define acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileWrites :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* L1ProfileWrites :: GPU MEMORY BYTE WRITE */
#define acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* L1ProfileWrites :: XVE ACTIVE */
#define acmgt3__l1_profile_writes__xe_core3__xve_active__read \
   bdw__render_basic__eu_active__read

/* L1ProfileWrites :: XVE STALL */
#define acmgt3__l1_profile_writes__xe_core3__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* L1ProfileWrites :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__l1_profile_writes__xe_core3__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* L1ProfileWrites :: XVE BUSY */
#define acmgt3__l1_profile_writes__xe_core3__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* L1ProfileWrites :: XVE BUSY */
#define acmgt3__l1_profile_writes__xe_core3__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* DataportReads :: GPU Time Elapsed */
#define acmgt3__dataport_reads__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DataportReads :: GPU Core Clocks */
#define acmgt3__dataport_reads__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DataportReads :: AVG GPU Core Frequency */
#define acmgt3__dataport_reads__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DataportReads :: AVG GPU Core Frequency */
#define acmgt3__dataport_reads__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DataportReads :: DATAPORT BYTE READ */
#define acmgt3__dataport_reads__dataport_byte_read__read \
   acmgt1__dataport_reads__dataport_byte_read__read

/* DataportReads :: DATAPORT BYTE READ */
#define acmgt3__dataport_reads__dataport_byte_read__max \
   acmgt1__dataport_reads__dataport_byte_read__max

/* DataportReads :: HOST TO GPUMEM BYTE READ */
#define acmgt3__dataport_reads__host_to_gpumem_byte_read__read \
   acmgt1__dataport_reads__host_to_gpumem_byte_read__read

/* DataportReads :: HOST TO GPUMEM BYTE READ */
#define acmgt3__dataport_reads__host_to_gpumem_byte_read__max \
   acmgt1__dataport_reads__host_to_gpumem_byte_read__max

/* DataportReads :: HOST TO GPUMEM BYTE WRITE */
#define acmgt3__dataport_reads__host_to_gpumem_byte_write__read \
   acmgt1__dataport_reads__host_to_gpumem_byte_write__read

/* DataportReads :: HOST TO GPUMEM BYTE WRITE */
#define acmgt3__dataport_reads__host_to_gpumem_byte_write__max \
   acmgt1__dataport_reads__host_to_gpumem_byte_read__max

/* DataportReads :: GPU MEMORY BYTE READ */
#define acmgt3__dataport_reads__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* DataportReads :: GPU MEMORY BYTE READ */
#define acmgt3__dataport_reads__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* DataportReads :: GPU MEMORY BYTE WRITE */
#define acmgt3__dataport_reads__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* DataportReads :: GPU MEMORY BYTE WRITE */
#define acmgt3__dataport_reads__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* DataportReads :: XVE ACTIVE */
#define acmgt3__dataport_reads__xve_active__read \
   bdw__render_basic__eu_active__read

/* DataportReads :: XVE STALL */
#define acmgt3__dataport_reads__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* DataportReads :: XVE BUSY */
#define acmgt3__dataport_reads__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* DataportReads :: XVE BUSY */
#define acmgt3__dataport_reads__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* DataportReads :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__dataport_reads__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* DataportReads :: XVE COMPUTE THREAD COUNT */
#define acmgt3__dataport_reads__xve_compute_thread_count__read \
   bdw__render_basic__cs_threads__read

/* DataportWrites :: GPU Time Elapsed */
#define acmgt3__dataport_writes__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* DataportWrites :: GPU Core Clocks */
#define acmgt3__dataport_writes__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* DataportWrites :: AVG GPU Core Frequency */
#define acmgt3__dataport_writes__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* DataportWrites :: AVG GPU Core Frequency */
#define acmgt3__dataport_writes__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* DataportWrites :: DATAPORT BYTE WRITE */
#define acmgt3__dataport_writes__dataport_byte_write__read \
   acmgt1__dataport_writes__dataport_byte_write__read

/* DataportWrites :: DATAPORT BYTE WRITE */
#define acmgt3__dataport_writes__dataport_byte_write__max \
   acmgt1__dataport_writes__dataport_byte_write__max

/* DataportWrites :: SAMPLER L3 READ */
#define acmgt3__dataport_writes__sampler_l3_read__read \
   hsw__sampler_balance__sampler_l2_cache_misses__read

/* DataportWrites :: SYSMEM BYTE READ */
#define acmgt3__dataport_writes__sysmem_byte_read__read \
   acmgt1__dataport_writes__sysmem_byte_read__read

/* DataportWrites :: SYSMEM BYTE READ */
#define acmgt3__dataport_writes__sysmem_byte_read__max \
   acmgt1__dataport_reads__host_to_gpumem_byte_read__max

/* DataportWrites :: SYSMEM BYTE WRITE */
#define acmgt3__dataport_writes__sysmem_byte_write__read \
   acmgt1__dataport_writes__sysmem_byte_write__read

/* DataportWrites :: SYSMEM BYTE WRITE */
#define acmgt3__dataport_writes__sysmem_byte_write__max \
   acmgt1__dataport_reads__host_to_gpumem_byte_read__max

/* DataportWrites :: GPU MEMORY BYTE READ */
#define acmgt3__dataport_writes__gpu_memory_byte_read__read \
   acmgt1__compute_overview__gpu_memory_byte_read__read

/* DataportWrites :: GPU MEMORY BYTE READ */
#define acmgt3__dataport_writes__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* DataportWrites :: GPU MEMORY BYTE WRITE */
#define acmgt3__dataport_writes__gpu_memory_byte_write__read \
   acmgt1__compute_overview__gpu_memory_byte_write__read

/* DataportWrites :: GPU MEMORY BYTE WRITE */
#define acmgt3__dataport_writes__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* DataportWrites :: XVE ACTIVE */
#define acmgt3__dataport_writes__xve_active__read \
   bdw__render_basic__eu_active__read

/* DataportWrites :: XVE STALL */
#define acmgt3__dataport_writes__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* DataportWrites :: XVE BUSY */
#define acmgt3__dataport_writes__xve_busy__read \
   acmgt1__compute_overview__xve_busy__read

/* DataportWrites :: XVE BUSY */
#define acmgt3__dataport_writes__xve_busy__max \
   acmgt1__compute_overview__xve_busy__max

/* DataportWrites :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__dataport_writes__xve_threads_occupancy_all__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* DataportWrites :: XVE COMPUTE THREAD COUNT */
#define acmgt3__dataport_writes__xve_compute_thread_count__read \
   bdw__render_basic__cs_threads__read

/* Ext1 :: GPU Time Elapsed */
#define acmgt3__ext1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1 :: GPU Core Clocks */
#define acmgt3__ext1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1 :: AVG GPU Core Frequency */
#define acmgt3__ext1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1 :: AVG GPU Core Frequency */
#define acmgt3__ext1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1 :: GPU MEMORY READ SQIDI0 */
#define acmgt3__ext1__gpu_memory_read_sqidi0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI1 */
#define acmgt3__ext1__gpu_memory_read_sqidi1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI2 */
#define acmgt3__ext1__gpu_memory_read_sqidi2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI3 */
#define acmgt3__ext1__gpu_memory_read_sqidi3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI4 */
#define acmgt3__ext1__gpu_memory_read_sqidi4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext1 :: GPU MEMORY READ SQIDI5 */
#define acmgt3__ext1__gpu_memory_read_sqidi5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext1 :: GPU MEMORY READ SQIDI6 */
#define acmgt3__ext1__gpu_memory_read_sqidi6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext1 :: GPU MEMORY READ SQIDI7 */
#define acmgt3__ext1__gpu_memory_read_sqidi7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext1 :: GPU MEMORY READ */
static uint64_t
acmgt3__ext1__gpu_memory_read__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_READ_SQIDI2 $GPU_MEMORY_READ_SQIDI0 UADD $GPU_MEMORY_READ_SQIDI1 UADD $GPU_MEMORY_READ_SQIDI3 UADD $GPU_MEMORY_READ_SQIDI4 UADD $GPU_MEMORY_READ_SQIDI5 UADD $GPU_MEMORY_READ_SQIDI6 UADD $GPU_MEMORY_READ_SQIDI7 UADD */
   uint64_t tmp0 = acmgt3__ext1__gpu_memory_read_sqidi2__read(perf, query, results) + acmgt3__ext1__gpu_memory_read_sqidi0__read(perf, query, results);
   uint64_t tmp1 = tmp0 + acmgt3__ext1__gpu_memory_read_sqidi1__read(perf, query, results);
   uint64_t tmp2 = tmp1 + acmgt3__ext1__gpu_memory_read_sqidi3__read(perf, query, results);
   uint64_t tmp3 = tmp2 + acmgt3__ext1__gpu_memory_read_sqidi4__read(perf, query, results);
   uint64_t tmp4 = tmp3 + acmgt3__ext1__gpu_memory_read_sqidi5__read(perf, query, results);
   uint64_t tmp5 = tmp4 + acmgt3__ext1__gpu_memory_read_sqidi6__read(perf, query, results);
   uint64_t tmp6 = tmp5 + acmgt3__ext1__gpu_memory_read_sqidi7__read(perf, query, results);

   return tmp6;
}

/* Ext2 :: GPU Time Elapsed */
#define acmgt3__ext2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext2 :: GPU Core Clocks */
#define acmgt3__ext2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext2 :: AVG GPU Core Frequency */
#define acmgt3__ext2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext2 :: AVG GPU Core Frequency */
#define acmgt3__ext2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext2 :: GPU MEMORY BYTE READ SQIDI0 */
#define acmgt3__ext2__gpu_memory_byte_read_sqidi0__read \
   acmgt1__ext1__gpu_memory_byte_write_sqidi0__read

/* Ext2 :: GPU MEMORY BYTE READ SQIDI1 */
#define acmgt3__ext2__gpu_memory_byte_read_sqidi1__read \
   hsw__render_basic__gti_read_throughput__read

/* Ext2 :: GPU MEMORY BYTE READ SQIDI2 */
#define acmgt3__ext2__gpu_memory_byte_read_sqidi2__read \
   acmgt1__ext1__gpu_memory_byte_read_sqidi0__read

/* Ext2 :: GPU MEMORY BYTE READ SQIDI3 */
#define acmgt3__ext2__gpu_memory_byte_read_sqidi3__read \
   acmgt1__ext1__gpu_memory_byte_read_sqidi1__read

/* Ext2 :: GPU MEMORY BYTE READ SQIDI4 */
#define acmgt3__ext2__gpu_memory_byte_read_sqidi4__read \
   acmgt2__memory1__gpu_memory_byte_write_sqidi0__read

/* Ext2 :: GPU MEMORY BYTE READ SQIDI5 */
#define acmgt3__ext2__gpu_memory_byte_read_sqidi5__read \
   chv__compute_basic__gti_ring_throughput__read

/* Ext2 :: GPU MEMORY BYTE READ SQIDI6 */
#define acmgt3__ext2__gpu_memory_byte_read_sqidi6__read \
   acmgt2__memory1__gpu_memory_byte_write_sqidi2__read

/* Ext2 :: GPU MEMORY BYTE READ SQIDI7 */
#define acmgt3__ext2__gpu_memory_byte_read_sqidi7__read \
   acmgt2__memory1__gpu_memory_byte_write_sqidi3__read

/* Ext2 :: GPU MEMORY BYTE READ */
static uint64_t
acmgt3__ext2__gpu_memory_byte_read__read(UNUSED struct intel_perf_config *perf,
                                         const struct intel_perf_query_info *query,
                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ  C 6 READ UADD  C 5 READ UADD  C 4 READ UADD  C 3 READ UADD  C 2 READ UADD  C 1 READ UADD  C 0 READ UADD 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 3];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->c_offset + 2];
   uint64_t tmp10 = tmp8 + tmp9;
   uint64_t tmp11 = results->accumulator[query->c_offset + 1];
   uint64_t tmp12 = tmp10 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 0];
   uint64_t tmp14 = tmp12 + tmp13;
   uint64_t tmp15 = tmp14 * 128;

   return tmp15;
}

/* Ext2 :: GPU MEMORY BYTE READ */
#define acmgt3__ext2__gpu_memory_byte_read__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* Ext2 :: GPU MEMORY BYTE WRITE SQIDI0 */
static uint64_t
acmgt3__ext2__gpu_memory_byte_write_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext2 :: GPU MEMORY BYTE WRITE SQIDI1 */
static uint64_t
acmgt3__ext2__gpu_memory_byte_write_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext2 :: GPU MEMORY BYTE WRITE SQIDI2 */
static uint64_t
acmgt3__ext2__gpu_memory_byte_write_sqidi2__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext2 :: GPU MEMORY BYTE WRITE SQIDI3 */
static uint64_t
acmgt3__ext2__gpu_memory_byte_write_sqidi3__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext2 :: GPU MEMORY BYTE WRITE SQIDI4 */
static uint64_t
acmgt3__ext2__gpu_memory_byte_write_sqidi4__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext2 :: GPU MEMORY BYTE WRITE SQIDI5 */
static uint64_t
acmgt3__ext2__gpu_memory_byte_write_sqidi5__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext2 :: GPU MEMORY BYTE WRITE SQIDI6 */
static uint64_t
acmgt3__ext2__gpu_memory_byte_write_sqidi6__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext2 :: GPU MEMORY BYTE WRITE SQIDI7 */
static uint64_t
acmgt3__ext2__gpu_memory_byte_write_sqidi7__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = tmp0 * 128;

   return tmp1;
}

/* Ext2 :: GPU MEMORY BYTE WRITE */
static uint64_t
acmgt3__ext2__gpu_memory_byte_write__read(UNUSED struct intel_perf_config *perf,
                                          const struct intel_perf_query_info *query,
                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ  B 6 READ UADD  B 5 READ UADD  B 4 READ UADD  B 3 READ UADD  B 2 READ UADD  B 1 READ UADD  B 0 READ UADD 128 UMUL */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 5];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 4];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 3];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->b_offset + 2];
   uint64_t tmp10 = tmp8 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 1];
   uint64_t tmp12 = tmp10 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 0];
   uint64_t tmp14 = tmp12 + tmp13;
   uint64_t tmp15 = tmp14 * 128;

   return tmp15;
}

/* Ext2 :: GPU MEMORY BYTE WRITE */
#define acmgt3__ext2__gpu_memory_byte_write__max \
   acmgt1__compute_overview__gpu_memory_byte_read__max

/* Ext2 :: GPU MEMORY BYTE READ BW SQIDI0 */
#define acmgt3__ext2__gpu_memory_byte_read_bw_sqidi0__read \
   acmgt1__ext1__gpu_memory_byte_write_bw_sqidi0__read

/* Ext2 :: GPU MEMORY BYTE READ BW SQIDI1 */
#define acmgt3__ext2__gpu_memory_byte_read_bw_sqidi1__read \
   acmgt1__ext1__gpu_memory_byte_write_bw_sqidi1__read

/* Ext2 :: GPU MEMORY BYTE READ BW SQIDI2 */
#define acmgt3__ext2__gpu_memory_byte_read_bw_sqidi2__read \
   acmgt1__ext1__gpu_memory_byte_read_bw_sqidi0__read

/* Ext2 :: GPU MEMORY BYTE READ BW SQIDI3 */
#define acmgt3__ext2__gpu_memory_byte_read_bw_sqidi3__read \
   acmgt1__ext1__gpu_memory_byte_read_bw_sqidi1__read

/* Ext2 :: GPU MEMORY BYTE READ BW SQIDI4 */
#define acmgt3__ext2__gpu_memory_byte_read_bw_sqidi4__read \
   acmgt2__memory1__gpu_memory_byte_write_bw_sqidi0__read

/* Ext2 :: GPU MEMORY BYTE READ BW SQIDI5 */
#define acmgt3__ext2__gpu_memory_byte_read_bw_sqidi5__read \
   acmgt2__memory1__gpu_memory_byte_write_bw_sqidi1__read

/* Ext2 :: GPU MEMORY BYTE READ BW SQIDI6 */
#define acmgt3__ext2__gpu_memory_byte_read_bw_sqidi6__read \
   acmgt2__memory1__gpu_memory_byte_write_bw_sqidi2__read

/* Ext2 :: GPU MEMORY BYTE READ BW SQIDI7 */
#define acmgt3__ext2__gpu_memory_byte_read_bw_sqidi7__read \
   acmgt2__memory1__gpu_memory_byte_write_bw_sqidi3__read

/* Ext2 :: GPU MEMORY BYTE READ BW */
static float
acmgt3__ext2__gpu_memory_byte_read_bw__read(UNUSED struct intel_perf_config *perf,
                                            const struct intel_perf_query_info *query,
                                            const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_READ $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_read__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU MEMORY BYTE WRITE BW SQIDI0 */
static float
acmgt3__ext2__gpu_memory_byte_write_bw_sqidi0__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI0 $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_write_sqidi0__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU MEMORY BYTE WRITE BW SQIDI1 */
static float
acmgt3__ext2__gpu_memory_byte_write_bw_sqidi1__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI1 $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_write_sqidi1__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU MEMORY BYTE WRITE BW SQIDI2 */
static float
acmgt3__ext2__gpu_memory_byte_write_bw_sqidi2__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI2 $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_write_sqidi2__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU MEMORY BYTE WRITE BW SQIDI3 */
static float
acmgt3__ext2__gpu_memory_byte_write_bw_sqidi3__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI3 $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_write_sqidi3__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU MEMORY BYTE WRITE BW SQIDI4 */
static float
acmgt3__ext2__gpu_memory_byte_write_bw_sqidi4__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI4 $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_write_sqidi4__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU MEMORY BYTE WRITE BW SQIDI5 */
static float
acmgt3__ext2__gpu_memory_byte_write_bw_sqidi5__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI5 $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_write_sqidi5__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU MEMORY BYTE WRITE BW SQIDI6 */
static float
acmgt3__ext2__gpu_memory_byte_write_bw_sqidi6__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI6 $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_write_sqidi6__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU MEMORY BYTE WRITE BW SQIDI7 */
static float
acmgt3__ext2__gpu_memory_byte_write_bw_sqidi7__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE_SQIDI7 $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_write_sqidi7__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext2 :: GPU MEMORY BYTE WRITE BW */
static float
acmgt3__ext2__gpu_memory_byte_write_bw__read(UNUSED struct intel_perf_config *perf,
                                             const struct intel_perf_query_info *query,
                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_BYTE_WRITE $GpuTime FDIV */
   double tmp0 = acmgt3__ext2__gpu_memory_byte_write__read(perf, query, results);
   double tmp1 = acmgt3__ext2__gpu_time__read(perf, query, results);
   double tmp2 = tmp1 ? tmp0 / tmp1 : 0;

   return tmp2;
}

/* Ext3 :: GPU Time Elapsed */
#define acmgt3__ext3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext3 :: GPU Core Clocks */
#define acmgt3__ext3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext3 :: AVG GPU Core Frequency */
#define acmgt3__ext3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext3 :: AVG GPU Core Frequency */
#define acmgt3__ext3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI0 */
#define acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi0__read \
   acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi0__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI1 */
#define acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi1__read \
   acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi1__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI2 */
#define acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi2__read \
   acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi2__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI3 */
#define acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi3__read \
   acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi0__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI4 */
#define acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi4__read \
   acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi1__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI5 */
#define acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi5__read \
   acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi1__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI6 */
#define acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi6__read \
   acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi0__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI7 */
#define acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi7__read \
   acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi3__read

/* Ext4 :: GPU Time Elapsed */
#define acmgt3__ext4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext4 :: GPU Core Clocks */
#define acmgt3__ext4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext4 :: AVG GPU Core Frequency */
#define acmgt3__ext4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext4 :: AVG GPU Core Frequency */
#define acmgt3__ext4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext4 :: GPU MEMORY 64B TRANSACTION READ SQIDI0 */
#define acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi0__read \
   acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi0__read

/* Ext4 :: GPU MEMORY 64B TRANSACTION READ SQIDI1 */
#define acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi1__read \
   acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi1__read

/* Ext4 :: GPU MEMORY 64B TRANSACTION READ SQIDI2 */
#define acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi2__read \
   acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi2__read

/* Ext4 :: GPU MEMORY 64B TRANSACTION READ SQIDI3 */
#define acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi3__read \
   acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi0__read

/* Ext4 :: GPU MEMORY 64B TRANSACTION READ SQIDI4 */
#define acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi4__read \
   acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi1__read

/* Ext4 :: GPU MEMORY 64B TRANSACTION READ SQIDI5 */
#define acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi5__read \
   acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi1__read

/* Ext4 :: GPU MEMORY 64B TRANSACTION READ SQIDI6 */
#define acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi6__read \
   acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi0__read

/* Ext4 :: GPU MEMORY 64B TRANSACTION READ SQIDI7 */
#define acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi7__read \
   acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi3__read

/* Ext5 :: GPU Time Elapsed */
#define acmgt3__ext5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext5 :: GPU Core Clocks */
#define acmgt3__ext5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext5 :: AVG GPU Core Frequency */
#define acmgt3__ext5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext5 :: AVG GPU Core Frequency */
#define acmgt3__ext5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI0 */
#define acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI1 */
#define acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI2 */
#define acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI3 */
#define acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI4 */
#define acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI5 */
#define acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI6 */
#define acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext5 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI7 */
#define acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI0 */
#define acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI1 */
#define acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI2 */
#define acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI3 */
#define acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI4 */
#define acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI5 */
#define acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI6 */
#define acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext5 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI7 */
#define acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext6 :: GPU Time Elapsed */
#define acmgt3__ext6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext6 :: GPU Core Clocks */
#define acmgt3__ext6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext6 :: AVG GPU Core Frequency */
#define acmgt3__ext6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext6 :: AVG GPU Core Frequency */
#define acmgt3__ext6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext6 :: GPU MEMORY ACTIVE SQIDI0 */
#define acmgt3__ext6__gpu_memory_active_sqidi0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext6 :: GPU MEMORY ACTIVE SQIDI1 */
#define acmgt3__ext6__gpu_memory_active_sqidi1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext6 :: GPU MEMORY ACTIVE SQIDI2 */
#define acmgt3__ext6__gpu_memory_active_sqidi2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext6 :: GPU MEMORY ACTIVE SQIDI3 */
#define acmgt3__ext6__gpu_memory_active_sqidi3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext6 :: GPU MEMORY ACTIVE SQIDI4 */
#define acmgt3__ext6__gpu_memory_active_sqidi4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext6 :: GPU MEMORY ACTIVE SQIDI5 */
#define acmgt3__ext6__gpu_memory_active_sqidi5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext6 :: GPU MEMORY ACTIVE SQIDI6 */
#define acmgt3__ext6__gpu_memory_active_sqidi6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext6 :: GPU MEMORY ACTIVE SQIDI7 */
#define acmgt3__ext6__gpu_memory_active_sqidi7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI0 */
#define acmgt3__ext6__gpu_memory_request_queue_full_sqidi0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI1 */
#define acmgt3__ext6__gpu_memory_request_queue_full_sqidi1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI2 */
#define acmgt3__ext6__gpu_memory_request_queue_full_sqidi2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI3 */
#define acmgt3__ext6__gpu_memory_request_queue_full_sqidi3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI4 */
#define acmgt3__ext6__gpu_memory_request_queue_full_sqidi4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI5 */
#define acmgt3__ext6__gpu_memory_request_queue_full_sqidi5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI6 */
#define acmgt3__ext6__gpu_memory_request_queue_full_sqidi6__read \
   bdw__render_basic__sampler1_busy__read

/* Ext6 :: GPU MEMORY REQUEST QUEUE FULL SQIDI7 */
#define acmgt3__ext6__gpu_memory_request_queue_full_sqidi7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext6 :: GPU MEMORY ACTIVE */
static float
acmgt3__ext6__gpu_memory_active__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ  C 7 READ FADD  C 6 READ FADD  C 4 READ FADD  C 3 READ FADD  C 2 READ FADD  C 1 READ FADD  C 0 READ FADD 8 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 6];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 4];
   double tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 3];
   double tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->c_offset + 2];
   double tmp10 = tmp8 + tmp9;
   uint64_t tmp11 = results->accumulator[query->c_offset + 1];
   double tmp12 = tmp10 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 0];
   double tmp14 = tmp12 + tmp13;
   double tmp15 = tmp14;
   double tmp16 = 8;
   double tmp17 = tmp16 ? tmp15 / tmp16 : 0;
   double tmp18 = tmp17;
   double tmp19 = acmgt3__ext6__gpu_core_clocks__read(perf, query, results);
   double tmp20 = tmp19 ? tmp18 / tmp19 : 0;

   return tmp20;
}

/* Ext6 :: GPU MEMORY REQUEST QUEUE FULL */
static float
acmgt3__ext6__gpu_memory_request_queue_full__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ  B 7 READ FADD  B 6 READ FADD  B 4 READ FADD  B 3 READ FADD  B 2 READ FADD  B 1 READ FADD  B 0 READ FADD 8 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 6];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 4];
   double tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 3];
   double tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->b_offset + 2];
   double tmp10 = tmp8 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 1];
   double tmp12 = tmp10 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 0];
   double tmp14 = tmp12 + tmp13;
   double tmp15 = tmp14;
   double tmp16 = 8;
   double tmp17 = tmp16 ? tmp15 / tmp16 : 0;
   double tmp18 = tmp17;
   double tmp19 = acmgt3__ext6__gpu_core_clocks__read(perf, query, results);
   double tmp20 = tmp19 ? tmp18 / tmp19 : 0;

   return tmp20;
}

/* Ext7 :: GPU Time Elapsed */
#define acmgt3__ext7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext7 :: GPU Core Clocks */
#define acmgt3__ext7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext7 :: AVG GPU Core Frequency */
#define acmgt3__ext7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext7 :: AVG GPU Core Frequency */
#define acmgt3__ext7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext7 :: L3 HIT L3BANK0 */
#define acmgt3__ext7__l3_hit_l3_bank0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext7 :: L3 HIT L3BANK1 */
#define acmgt3__ext7__l3_hit_l3_bank1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext7 :: L3 HIT L3BANK2 */
#define acmgt3__ext7__l3_hit_l3_bank2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext7 :: L3 HIT L3BANK3 */
#define acmgt3__ext7__l3_hit_l3_bank3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext7 :: L3 HIT L3BANK4 */
#define acmgt3__ext7__l3_hit_l3_bank4__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext7 :: L3 HIT L3BANK5 */
#define acmgt3__ext7__l3_hit_l3_bank5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext7 :: L3 HIT L3BANK6 */
#define acmgt3__ext7__l3_hit_l3_bank6__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext7 :: L3 HIT L3BANK7 */
#define acmgt3__ext7__l3_hit_l3_bank7__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext7 :: L3 HIT L3BANK8 */
#define acmgt3__ext7__l3_hit_l3_bank8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext7 :: L3 HIT L3BANK9 */
#define acmgt3__ext7__l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext7 :: L3 HIT L3BANK10 */
#define acmgt3__ext7__l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext7 :: L3 HIT L3BANK11 */
#define acmgt3__ext7__l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext7 :: L3 HIT L3BANK12 */
#define acmgt3__ext7__l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext7 :: L3 HIT L3BANK13 */
#define acmgt3__ext7__l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext7 :: L3 HIT L3BANK14 */
#define acmgt3__ext7__l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext7 :: L3 HIT L3BANK15 */
#define acmgt3__ext7__l3_hit_l3_bank15__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext8 :: GPU Time Elapsed */
#define acmgt3__ext8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext8 :: GPU Core Clocks */
#define acmgt3__ext8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext8 :: AVG GPU Core Frequency */
#define acmgt3__ext8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext8 :: AVG GPU Core Frequency */
#define acmgt3__ext8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext8 :: L3 HIT L3BANK16 */
#define acmgt3__ext8__l3_hit_l3_bank16__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext8 :: L3 HIT L3BANK17 */
#define acmgt3__ext8__l3_hit_l3_bank17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext8 :: L3 HIT L3BANK18 */
#define acmgt3__ext8__l3_hit_l3_bank18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext8 :: L3 HIT L3BANK19 */
#define acmgt3__ext8__l3_hit_l3_bank19__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext8 :: L3 HIT L3BANK20 */
#define acmgt3__ext8__l3_hit_l3_bank20__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext8 :: L3 HIT L3BANK21 */
#define acmgt3__ext8__l3_hit_l3_bank21__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext8 :: L3 HIT L3BANK22 */
#define acmgt3__ext8__l3_hit_l3_bank22__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext8 :: L3 HIT L3BANK23 */
#define acmgt3__ext8__l3_hit_l3_bank23__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext8 :: L3 HIT L3BANK24 */
#define acmgt3__ext8__l3_hit_l3_bank24__read \
   hsw__compute_extended__typed_writes0__read

/* Ext8 :: L3 HIT L3BANK25 */
#define acmgt3__ext8__l3_hit_l3_bank25__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext8 :: L3 HIT L3BANK26 */
#define acmgt3__ext8__l3_hit_l3_bank26__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext8 :: L3 HIT L3BANK27 */
#define acmgt3__ext8__l3_hit_l3_bank27__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext8 :: L3 HIT L3BANK28 */
#define acmgt3__ext8__l3_hit_l3_bank28__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext8 :: L3 HIT L3BANK29 */
#define acmgt3__ext8__l3_hit_l3_bank29__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext8 :: L3 HIT L3BANK30 */
#define acmgt3__ext8__l3_hit_l3_bank30__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext8 :: L3 HIT L3BANK31 */
#define acmgt3__ext8__l3_hit_l3_bank31__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext9 :: GPU Time Elapsed */
#define acmgt3__ext9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext9 :: GPU Core Clocks */
#define acmgt3__ext9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext9 :: AVG GPU Core Frequency */
#define acmgt3__ext9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext9 :: AVG GPU Core Frequency */
#define acmgt3__ext9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK0 */
#define acmgt3__ext9__l3_input_available_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK1 */
#define acmgt3__ext9__l3_input_available_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK2 */
#define acmgt3__ext9__l3_input_available_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK3 */
#define acmgt3__ext9__l3_input_available_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK4 */
#define acmgt3__ext9__l3_input_available_l3_bank4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK5 */
#define acmgt3__ext9__l3_input_available_l3_bank5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK6 */
#define acmgt3__ext9__l3_input_available_l3_bank6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK7 */
#define acmgt3__ext9__l3_input_available_l3_bank7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK8 */
#define acmgt3__ext9__l3_input_available_l3_bank8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK9 */
#define acmgt3__ext9__l3_input_available_l3_bank9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK10 */
#define acmgt3__ext9__l3_input_available_l3_bank10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK11 */
#define acmgt3__ext9__l3_input_available_l3_bank11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK12 */
#define acmgt3__ext9__l3_input_available_l3_bank12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK13 */
#define acmgt3__ext9__l3_input_available_l3_bank13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK14 */
#define acmgt3__ext9__l3_input_available_l3_bank14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext9 :: L3 BANK INPUT AVAILABLE L3BANK15 */
#define acmgt3__ext9__l3_input_available_l3_bank15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext10 :: GPU Time Elapsed */
#define acmgt3__ext10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext10 :: GPU Core Clocks */
#define acmgt3__ext10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext10 :: AVG GPU Core Frequency */
#define acmgt3__ext10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext10 :: AVG GPU Core Frequency */
#define acmgt3__ext10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK16 */
#define acmgt3__ext10__l3_input_available_l3_bank16__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK17 */
#define acmgt3__ext10__l3_input_available_l3_bank17__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK18 */
#define acmgt3__ext10__l3_input_available_l3_bank18__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK19 */
#define acmgt3__ext10__l3_input_available_l3_bank19__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK20 */
#define acmgt3__ext10__l3_input_available_l3_bank20__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK21 */
#define acmgt3__ext10__l3_input_available_l3_bank21__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK22 */
#define acmgt3__ext10__l3_input_available_l3_bank22__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK23 */
#define acmgt3__ext10__l3_input_available_l3_bank23__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK24 */
#define acmgt3__ext10__l3_input_available_l3_bank24__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK25 */
#define acmgt3__ext10__l3_input_available_l3_bank25__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK26 */
#define acmgt3__ext10__l3_input_available_l3_bank26__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK27 */
#define acmgt3__ext10__l3_input_available_l3_bank27__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK28 */
#define acmgt3__ext10__l3_input_available_l3_bank28__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK29 */
#define acmgt3__ext10__l3_input_available_l3_bank29__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK30 */
#define acmgt3__ext10__l3_input_available_l3_bank30__read \
   bdw__render_basic__sampler1_busy__read

/* Ext10 :: L3 BANK INPUT AVAILABLE L3BANK31 */
#define acmgt3__ext10__l3_input_available_l3_bank31__read \
   bdw__render_basic__sampler0_busy__read

/* Ext11 :: GPU Time Elapsed */
#define acmgt3__ext11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext11 :: GPU Core Clocks */
#define acmgt3__ext11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext11 :: AVG GPU Core Frequency */
#define acmgt3__ext11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext11 :: AVG GPU Core Frequency */
#define acmgt3__ext11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext11 :: L3 OUTPUT READY L3BANK0 */
#define acmgt3__ext11__l3_output_ready_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext11 :: L3 OUTPUT READY L3BANK1 */
#define acmgt3__ext11__l3_output_ready_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext11 :: L3 OUTPUT READY L3BANK2 */
#define acmgt3__ext11__l3_output_ready_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext11 :: L3 OUTPUT READY L3BANK3 */
#define acmgt3__ext11__l3_output_ready_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext11 :: L3 OUTPUT READY L3BANK4 */
#define acmgt3__ext11__l3_output_ready_l3_bank4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext11 :: L3 OUTPUT READY L3BANK5 */
#define acmgt3__ext11__l3_output_ready_l3_bank5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext11 :: L3 OUTPUT READY L3BANK6 */
#define acmgt3__ext11__l3_output_ready_l3_bank6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext11 :: L3 OUTPUT READY L3BANK7 */
#define acmgt3__ext11__l3_output_ready_l3_bank7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext11 :: L3 OUTPUT READY L3BANK8 */
#define acmgt3__ext11__l3_output_ready_l3_bank8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext11 :: L3 OUTPUT READY L3BANK9 */
#define acmgt3__ext11__l3_output_ready_l3_bank9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext11 :: L3 OUTPUT READY L3BANK10 */
#define acmgt3__ext11__l3_output_ready_l3_bank10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext11 :: L3 OUTPUT READY L3BANK11 */
#define acmgt3__ext11__l3_output_ready_l3_bank11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext11 :: L3 OUTPUT READY L3BANK12 */
#define acmgt3__ext11__l3_output_ready_l3_bank12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext11 :: L3 OUTPUT READY L3BANK13 */
#define acmgt3__ext11__l3_output_ready_l3_bank13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext11 :: L3 OUTPUT READY L3BANK14 */
#define acmgt3__ext11__l3_output_ready_l3_bank14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext11 :: L3 OUTPUT READY L3BANK15 */
#define acmgt3__ext11__l3_output_ready_l3_bank15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext12 :: GPU Time Elapsed */
#define acmgt3__ext12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext12 :: GPU Core Clocks */
#define acmgt3__ext12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext12 :: AVG GPU Core Frequency */
#define acmgt3__ext12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext12 :: AVG GPU Core Frequency */
#define acmgt3__ext12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext12 :: L3 OUTPUT READY L3BANK16 */
#define acmgt3__ext12__l3_output_ready_l3_bank16__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK17 */
#define acmgt3__ext12__l3_output_ready_l3_bank17__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK18 */
#define acmgt3__ext12__l3_output_ready_l3_bank18__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK19 */
#define acmgt3__ext12__l3_output_ready_l3_bank19__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK20 */
#define acmgt3__ext12__l3_output_ready_l3_bank20__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK21 */
#define acmgt3__ext12__l3_output_ready_l3_bank21__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK22 */
#define acmgt3__ext12__l3_output_ready_l3_bank22__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK23 */
#define acmgt3__ext12__l3_output_ready_l3_bank23__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK24 */
#define acmgt3__ext12__l3_output_ready_l3_bank24__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK25 */
#define acmgt3__ext12__l3_output_ready_l3_bank25__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK26 */
#define acmgt3__ext12__l3_output_ready_l3_bank26__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK27 */
#define acmgt3__ext12__l3_output_ready_l3_bank27__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK28 */
#define acmgt3__ext12__l3_output_ready_l3_bank28__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK29 */
#define acmgt3__ext12__l3_output_ready_l3_bank29__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK30 */
#define acmgt3__ext12__l3_output_ready_l3_bank30__read \
   bdw__render_basic__sampler1_busy__read

/* Ext12 :: L3 OUTPUT READY L3BANK31 */
#define acmgt3__ext12__l3_output_ready_l3_bank31__read \
   bdw__render_basic__sampler0_busy__read

/* Ext13 :: GPU Time Elapsed */
#define acmgt3__ext13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext13 :: GPU Core Clocks */
#define acmgt3__ext13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext13 :: AVG GPU Core Frequency */
#define acmgt3__ext13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext13 :: AVG GPU Core Frequency */
#define acmgt3__ext13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext13 :: L3 BANK ACTIVE L3BANK0 */
#define acmgt3__ext13__l3_busy_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext13 :: L3 BANK ACTIVE L3BANK1 */
#define acmgt3__ext13__l3_busy_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext13 :: L3 BANK ACTIVE L3BANK2 */
#define acmgt3__ext13__l3_busy_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext13 :: L3 BANK ACTIVE L3BANK3 */
#define acmgt3__ext13__l3_busy_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext13 :: L3 BANK ACTIVE L3BANK4 */
#define acmgt3__ext13__l3_busy_l3_bank4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext13 :: L3 BANK ACTIVE L3BANK5 */
#define acmgt3__ext13__l3_busy_l3_bank5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext13 :: L3 BANK ACTIVE L3BANK6 */
#define acmgt3__ext13__l3_busy_l3_bank6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext13 :: L3 BANK ACTIVE L3BANK7 */
#define acmgt3__ext13__l3_busy_l3_bank7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext13 :: L3 BANK ACTIVE L3BANK8 */
#define acmgt3__ext13__l3_busy_l3_bank8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext13 :: L3 BANK ACTIVE L3BANK9 */
#define acmgt3__ext13__l3_busy_l3_bank9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext13 :: L3 BANK ACTIVE L3BANK10 */
#define acmgt3__ext13__l3_busy_l3_bank10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext13 :: L3 BANK ACTIVE L3BANK11 */
#define acmgt3__ext13__l3_busy_l3_bank11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext13 :: L3 BANK ACTIVE L3BANK12 */
#define acmgt3__ext13__l3_busy_l3_bank12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext13 :: L3 BANK ACTIVE L3BANK13 */
#define acmgt3__ext13__l3_busy_l3_bank13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext13 :: L3 BANK ACTIVE L3BANK14 */
#define acmgt3__ext13__l3_busy_l3_bank14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext13 :: L3 BANK ACTIVE L3BANK15 */
#define acmgt3__ext13__l3_busy_l3_bank15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext14 :: GPU Time Elapsed */
#define acmgt3__ext14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext14 :: GPU Core Clocks */
#define acmgt3__ext14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext14 :: AVG GPU Core Frequency */
#define acmgt3__ext14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext14 :: AVG GPU Core Frequency */
#define acmgt3__ext14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext14 :: L3 BANK ACTIVE L3BANK16 */
#define acmgt3__ext14__l3_busy_l3_bank16__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK17 */
#define acmgt3__ext14__l3_busy_l3_bank17__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK18 */
#define acmgt3__ext14__l3_busy_l3_bank18__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK19 */
#define acmgt3__ext14__l3_busy_l3_bank19__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK20 */
#define acmgt3__ext14__l3_busy_l3_bank20__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK21 */
#define acmgt3__ext14__l3_busy_l3_bank21__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK22 */
#define acmgt3__ext14__l3_busy_l3_bank22__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext14 :: L3 BANK ACTIVE L3BANK23 */
#define acmgt3__ext14__l3_busy_l3_bank23__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK24 */
#define acmgt3__ext14__l3_busy_l3_bank24__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK25 */
#define acmgt3__ext14__l3_busy_l3_bank25__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK26 */
#define acmgt3__ext14__l3_busy_l3_bank26__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK27 */
#define acmgt3__ext14__l3_busy_l3_bank27__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK28 */
#define acmgt3__ext14__l3_busy_l3_bank28__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK29 */
#define acmgt3__ext14__l3_busy_l3_bank29__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext14 :: L3 BANK ACTIVE L3BANK30 */
#define acmgt3__ext14__l3_busy_l3_bank30__read \
   bdw__render_basic__sampler1_busy__read

/* Ext14 :: L3 BANK ACTIVE L3BANK31 */
#define acmgt3__ext14__l3_busy_l3_bank31__read \
   bdw__render_basic__sampler0_busy__read

/* Ext15 :: GPU Time Elapsed */
#define acmgt3__ext15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext15 :: GPU Core Clocks */
#define acmgt3__ext15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext15 :: AVG GPU Core Frequency */
#define acmgt3__ext15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext15 :: AVG GPU Core Frequency */
#define acmgt3__ext15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext15 :: L3 BANK STALL L3BANK0 */
#define acmgt3__ext15__l3_stall_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext15 :: L3 BANK STALL L3BANK1 */
#define acmgt3__ext15__l3_stall_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext15 :: L3 BANK STALL L3BANK2 */
#define acmgt3__ext15__l3_stall_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext15 :: L3 BANK STALL L3BANK3 */
#define acmgt3__ext15__l3_stall_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext15 :: L3 BANK STALL L3BANK4 */
#define acmgt3__ext15__l3_stall_l3_bank4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext16 :: GPU Time Elapsed */
#define acmgt3__ext16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext16 :: GPU Core Clocks */
#define acmgt3__ext16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext16 :: AVG GPU Core Frequency */
#define acmgt3__ext16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext16 :: AVG GPU Core Frequency */
#define acmgt3__ext16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext16 :: L3 BANK STALL L3BANK5 */
#define acmgt3__ext16__l3_stall_l3_bank5__read \
   bdw__render_basic__sampler0_busy__read

/* Ext16 :: L3 BANK STALL L3BANK6 */
#define acmgt3__ext16__l3_stall_l3_bank6__read \
   bdw__render_basic__sampler1_busy__read

/* Ext16 :: L3 BANK STALL L3BANK7 */
#define acmgt3__ext16__l3_stall_l3_bank7__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext16 :: L3 BANK STALL L3BANK8 */
#define acmgt3__ext16__l3_stall_l3_bank8__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext16 :: L3 BANK STALL L3BANK9 */
#define acmgt3__ext16__l3_stall_l3_bank9__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext17 :: GPU Time Elapsed */
#define acmgt3__ext17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext17 :: GPU Core Clocks */
#define acmgt3__ext17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext17 :: AVG GPU Core Frequency */
#define acmgt3__ext17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext17 :: AVG GPU Core Frequency */
#define acmgt3__ext17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext17 :: L3 BANK STALL L3BANK10 */
#define acmgt3__ext17__l3_stall_l3_bank10__read \
   bdw__render_basic__sampler0_busy__read

/* Ext17 :: L3 BANK STALL L3BANK11 */
#define acmgt3__ext17__l3_stall_l3_bank11__read \
   bdw__render_basic__sampler1_busy__read

/* Ext17 :: L3 BANK STALL L3BANK12 */
#define acmgt3__ext17__l3_stall_l3_bank12__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext17 :: L3 BANK STALL L3BANK13 */
#define acmgt3__ext17__l3_stall_l3_bank13__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext17 :: L3 BANK STALL L3BANK14 */
#define acmgt3__ext17__l3_stall_l3_bank14__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext18 :: GPU Time Elapsed */
#define acmgt3__ext18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext18 :: GPU Core Clocks */
#define acmgt3__ext18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext18 :: AVG GPU Core Frequency */
#define acmgt3__ext18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext18 :: AVG GPU Core Frequency */
#define acmgt3__ext18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext18 :: L3 BANK STALL L3BANK15 */
#define acmgt3__ext18__l3_stall_l3_bank15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext18 :: L3 BANK STALL L3BANK16 */
#define acmgt3__ext18__l3_stall_l3_bank16__read \
   bdw__render_basic__sampler1_busy__read

/* Ext18 :: L3 BANK STALL L3BANK17 */
#define acmgt3__ext18__l3_stall_l3_bank17__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext18 :: L3 BANK STALL L3BANK18 */
#define acmgt3__ext18__l3_stall_l3_bank18__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext18 :: L3 BANK STALL L3BANK19 */
#define acmgt3__ext18__l3_stall_l3_bank19__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext19 :: GPU Time Elapsed */
#define acmgt3__ext19__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext19 :: GPU Core Clocks */
#define acmgt3__ext19__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext19 :: AVG GPU Core Frequency */
#define acmgt3__ext19__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext19 :: AVG GPU Core Frequency */
#define acmgt3__ext19__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext19 :: L3 BANK STALL L3BANK20 */
#define acmgt3__ext19__l3_stall_l3_bank20__read \
   bdw__render_basic__sampler0_busy__read

/* Ext19 :: L3 BANK STALL L3BANK21 */
#define acmgt3__ext19__l3_stall_l3_bank21__read \
   bdw__render_basic__sampler1_busy__read

/* Ext19 :: L3 BANK STALL L3BANK22 */
#define acmgt3__ext19__l3_stall_l3_bank22__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext19 :: L3 BANK STALL L3BANK23 */
#define acmgt3__ext19__l3_stall_l3_bank23__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext19 :: L3 BANK STALL L3BANK24 */
#define acmgt3__ext19__l3_stall_l3_bank24__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext20 :: GPU Time Elapsed */
#define acmgt3__ext20__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext20 :: GPU Core Clocks */
#define acmgt3__ext20__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext20 :: AVG GPU Core Frequency */
#define acmgt3__ext20__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext20 :: AVG GPU Core Frequency */
#define acmgt3__ext20__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext20 :: L3 BANK STALL L3BANK25 */
#define acmgt3__ext20__l3_stall_l3_bank25__read \
   bdw__render_basic__sampler0_busy__read

/* Ext20 :: L3 BANK STALL L3BANK26 */
#define acmgt3__ext20__l3_stall_l3_bank26__read \
   bdw__render_basic__sampler1_busy__read

/* Ext20 :: L3 BANK STALL L3BANK27 */
#define acmgt3__ext20__l3_stall_l3_bank27__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext20 :: L3 BANK STALL L3BANK28 */
#define acmgt3__ext20__l3_stall_l3_bank28__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext20 :: L3 BANK STALL L3BANK29 */
#define acmgt3__ext20__l3_stall_l3_bank29__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext21 :: GPU Time Elapsed */
#define acmgt3__ext21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext21 :: GPU Core Clocks */
#define acmgt3__ext21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext21 :: AVG GPU Core Frequency */
#define acmgt3__ext21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext21 :: AVG GPU Core Frequency */
#define acmgt3__ext21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext21 :: L3 READ L3BANK0 */
#define acmgt3__ext21__l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext21 :: L3 READ L3BANK1 */
#define acmgt3__ext21__l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext21 :: L3 READ L3BANK2 */
#define acmgt3__ext21__l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext21 :: L3 READ L3BANK3 */
#define acmgt3__ext21__l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext21 :: L3 READ L3BANK4 */
#define acmgt3__ext21__l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext21 :: L3 READ L3BANK5 */
#define acmgt3__ext21__l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext21 :: L3 READ L3BANK6 */
#define acmgt3__ext21__l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext21 :: L3 READ L3BANK7 */
#define acmgt3__ext21__l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext21 :: L3 READ L3BANK8 */
#define acmgt3__ext21__l3_read_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext21 :: L3 READ L3BANK9 */
#define acmgt3__ext21__l3_read_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext21 :: L3 READ L3BANK10 */
#define acmgt3__ext21__l3_read_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext21 :: L3 READ L3BANK11 */
#define acmgt3__ext21__l3_read_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext21 :: L3 READ L3BANK12 */
#define acmgt3__ext21__l3_read_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext21 :: L3 READ L3BANK13 */
#define acmgt3__ext21__l3_read_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext21 :: L3 READ L3BANK14 */
#define acmgt3__ext21__l3_read_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext21 :: L3 READ L3BANK15 */
#define acmgt3__ext21__l3_read_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext22 :: GPU Time Elapsed */
#define acmgt3__ext22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext22 :: GPU Core Clocks */
#define acmgt3__ext22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext22 :: AVG GPU Core Frequency */
#define acmgt3__ext22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext22 :: AVG GPU Core Frequency */
#define acmgt3__ext22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext22 :: L3 READ L3BANK16 */
#define acmgt3__ext22__l3_read_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext22 :: L3 READ L3BANK17 */
#define acmgt3__ext22__l3_read_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext22 :: L3 READ L3BANK18 */
#define acmgt3__ext22__l3_read_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext22 :: L3 READ L3BANK19 */
#define acmgt3__ext22__l3_read_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext22 :: L3 READ L3BANK20 */
#define acmgt3__ext22__l3_read_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext22 :: L3 READ L3BANK21 */
#define acmgt3__ext22__l3_read_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext22 :: L3 READ L3BANK22 */
#define acmgt3__ext22__l3_read_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext22 :: L3 READ L3BANK23 */
#define acmgt3__ext22__l3_read_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext22 :: L3 READ L3BANK24 */
#define acmgt3__ext22__l3_read_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext22 :: L3 READ L3BANK25 */
#define acmgt3__ext22__l3_read_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext22 :: L3 READ L3BANK26 */
#define acmgt3__ext22__l3_read_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext22 :: L3 READ L3BANK27 */
#define acmgt3__ext22__l3_read_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext22 :: L3 READ L3BANK28 */
#define acmgt3__ext22__l3_read_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext22 :: L3 READ L3BANK29 */
#define acmgt3__ext22__l3_read_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext22 :: L3 READ L3BANK30 */
#define acmgt3__ext22__l3_read_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext22 :: L3 READ L3BANK31 */
#define acmgt3__ext22__l3_read_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext23 :: GPU Time Elapsed */
#define acmgt3__ext23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext23 :: GPU Core Clocks */
#define acmgt3__ext23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext23 :: AVG GPU Core Frequency */
#define acmgt3__ext23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext23 :: AVG GPU Core Frequency */
#define acmgt3__ext23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext23 :: L3 WRITE L3BANK0 */
#define acmgt3__ext23__l3_write_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext23 :: L3 WRITE L3BANK1 */
#define acmgt3__ext23__l3_write_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext23 :: L3 WRITE L3BANK2 */
#define acmgt3__ext23__l3_write_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext23 :: L3 WRITE L3BANK3 */
#define acmgt3__ext23__l3_write_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext23 :: L3 WRITE L3BANK4 */
#define acmgt3__ext23__l3_write_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext23 :: L3 WRITE L3BANK5 */
#define acmgt3__ext23__l3_write_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext23 :: L3 WRITE L3BANK6 */
#define acmgt3__ext23__l3_write_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext23 :: L3 WRITE L3BANK7 */
#define acmgt3__ext23__l3_write_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext23 :: L3 WRITE L3BANK8 */
#define acmgt3__ext23__l3_write_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext23 :: L3 WRITE L3BANK9 */
#define acmgt3__ext23__l3_write_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext23 :: L3 WRITE L3BANK10 */
#define acmgt3__ext23__l3_write_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext23 :: L3 WRITE L3BANK11 */
#define acmgt3__ext23__l3_write_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext23 :: L3 WRITE L3BANK12 */
#define acmgt3__ext23__l3_write_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext23 :: L3 WRITE L3BANK13 */
#define acmgt3__ext23__l3_write_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext23 :: L3 WRITE L3BANK14 */
#define acmgt3__ext23__l3_write_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext23 :: L3 WRITE L3BANK15 */
#define acmgt3__ext23__l3_write_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext24 :: GPU Time Elapsed */
#define acmgt3__ext24__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext24 :: GPU Core Clocks */
#define acmgt3__ext24__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext24 :: AVG GPU Core Frequency */
#define acmgt3__ext24__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext24 :: AVG GPU Core Frequency */
#define acmgt3__ext24__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext24 :: L3 WRITE L3BANK16 */
#define acmgt3__ext24__l3_write_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext24 :: L3 WRITE L3BANK17 */
#define acmgt3__ext24__l3_write_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext24 :: L3 WRITE L3BANK18 */
#define acmgt3__ext24__l3_write_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext24 :: L3 WRITE L3BANK19 */
#define acmgt3__ext24__l3_write_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext24 :: L3 WRITE L3BANK20 */
#define acmgt3__ext24__l3_write_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext24 :: L3 WRITE L3BANK21 */
#define acmgt3__ext24__l3_write_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext24 :: L3 WRITE L3BANK22 */
#define acmgt3__ext24__l3_write_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext24 :: L3 WRITE L3BANK23 */
#define acmgt3__ext24__l3_write_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext24 :: L3 WRITE L3BANK24 */
#define acmgt3__ext24__l3_write_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext24 :: L3 WRITE L3BANK25 */
#define acmgt3__ext24__l3_write_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext24 :: L3 WRITE L3BANK26 */
#define acmgt3__ext24__l3_write_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext24 :: L3 WRITE L3BANK27 */
#define acmgt3__ext24__l3_write_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext24 :: L3 WRITE L3BANK28 */
#define acmgt3__ext24__l3_write_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext24 :: L3 WRITE L3BANK29 */
#define acmgt3__ext24__l3_write_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext24 :: L3 WRITE L3BANK30 */
#define acmgt3__ext24__l3_write_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext24 :: L3 WRITE L3BANK31 */
#define acmgt3__ext24__l3_write_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext27 :: GPU Time Elapsed */
#define acmgt3__ext27__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext27 :: GPU Core Clocks */
#define acmgt3__ext27__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext27 :: AVG GPU Core Frequency */
#define acmgt3__ext27__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext27 :: AVG GPU Core Frequency */
#define acmgt3__ext27__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext27 :: L3 MISS L3BANK0 */
#define acmgt3__ext27__l3_miss_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext27 :: L3 MISS L3BANK1 */
#define acmgt3__ext27__l3_miss_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext27 :: L3 MISS L3BANK2 */
#define acmgt3__ext27__l3_miss_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext27 :: L3 MISS L3BANK3 */
#define acmgt3__ext27__l3_miss_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext27 :: L3 MISS L3BANK4 */
#define acmgt3__ext27__l3_miss_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext27 :: L3 MISS L3BANK5 */
#define acmgt3__ext27__l3_miss_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext27 :: L3 MISS L3BANK6 */
#define acmgt3__ext27__l3_miss_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext27 :: L3 MISS L3BANK7 */
#define acmgt3__ext27__l3_miss_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext27 :: L3 MISS L3BANK8 */
#define acmgt3__ext27__l3_miss_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext27 :: L3 MISS L3BANK9 */
#define acmgt3__ext27__l3_miss_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext27 :: L3 MISS L3BANK10 */
#define acmgt3__ext27__l3_miss_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext27 :: L3 MISS L3BANK11 */
#define acmgt3__ext27__l3_miss_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext27 :: L3 MISS L3BANK12 */
#define acmgt3__ext27__l3_miss_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext27 :: L3 MISS L3BANK13 */
#define acmgt3__ext27__l3_miss_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext27 :: L3 MISS L3BANK14 */
#define acmgt3__ext27__l3_miss_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext27 :: L3 MISS L3BANK15 */
#define acmgt3__ext27__l3_miss_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext28 :: GPU Time Elapsed */
#define acmgt3__ext28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext28 :: GPU Core Clocks */
#define acmgt3__ext28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext28 :: AVG GPU Core Frequency */
#define acmgt3__ext28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext28 :: AVG GPU Core Frequency */
#define acmgt3__ext28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext28 :: L3 MISS L3BANK16 */
#define acmgt3__ext28__l3_miss_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext28 :: L3 MISS L3BANK17 */
#define acmgt3__ext28__l3_miss_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext28 :: L3 MISS L3BANK18 */
#define acmgt3__ext28__l3_miss_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext28 :: L3 MISS L3BANK19 */
#define acmgt3__ext28__l3_miss_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext28 :: L3 MISS L3BANK20 */
#define acmgt3__ext28__l3_miss_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext28 :: L3 MISS L3BANK21 */
#define acmgt3__ext28__l3_miss_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext28 :: L3 MISS L3BANK22 */
#define acmgt3__ext28__l3_miss_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext28 :: L3 MISS L3BANK23 */
#define acmgt3__ext28__l3_miss_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext28 :: L3 MISS L3BANK24 */
#define acmgt3__ext28__l3_miss_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext28 :: L3 MISS L3BANK25 */
#define acmgt3__ext28__l3_miss_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext28 :: L3 MISS L3BANK26 */
#define acmgt3__ext28__l3_miss_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext28 :: L3 MISS L3BANK27 */
#define acmgt3__ext28__l3_miss_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext28 :: L3 MISS L3BANK28 */
#define acmgt3__ext28__l3_miss_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext28 :: L3 MISS L3BANK29 */
#define acmgt3__ext28__l3_miss_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext28 :: L3 MISS L3BANK30 */
#define acmgt3__ext28__l3_miss_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext28 :: L3 MISS L3BANK31 */
#define acmgt3__ext28__l3_miss_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext29 :: GPU Time Elapsed */
#define acmgt3__ext29__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext29 :: GPU Core Clocks */
#define acmgt3__ext29__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext29 :: AVG GPU Core Frequency */
#define acmgt3__ext29__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext29 :: AVG GPU Core Frequency */
#define acmgt3__ext29__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext29 :: DATAPORT L3 READ L3BANK0 */
#define acmgt3__ext29__dataport_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext29 :: DATAPORT L3 READ L3BANK1 */
#define acmgt3__ext29__dataport_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext29 :: DATAPORT L3 READ L3BANK2 */
#define acmgt3__ext29__dataport_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext29 :: DATAPORT L3 READ L3BANK3 */
#define acmgt3__ext29__dataport_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext29 :: DATAPORT L3 READ L3BANK4 */
#define acmgt3__ext29__dataport_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext29 :: DATAPORT L3 READ L3BANK5 */
#define acmgt3__ext29__dataport_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext29 :: DATAPORT L3 READ L3BANK6 */
#define acmgt3__ext29__dataport_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext29 :: DATAPORT L3 READ L3BANK7 */
#define acmgt3__ext29__dataport_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext29 :: DATAPORT L3 READ L3BANK8 */
#define acmgt3__ext29__dataport_l3_read_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext29 :: DATAPORT L3 READ L3BANK9 */
#define acmgt3__ext29__dataport_l3_read_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext29 :: DATAPORT L3 READ L3BANK10 */
#define acmgt3__ext29__dataport_l3_read_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext29 :: DATAPORT L3 READ L3BANK11 */
#define acmgt3__ext29__dataport_l3_read_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext29 :: DATAPORT L3 READ L3BANK12 */
#define acmgt3__ext29__dataport_l3_read_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext29 :: DATAPORT L3 READ L3BANK13 */
#define acmgt3__ext29__dataport_l3_read_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext29 :: DATAPORT L3 READ L3BANK14 */
#define acmgt3__ext29__dataport_l3_read_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext29 :: DATAPORT L3 READ L3BANK15 */
#define acmgt3__ext29__dataport_l3_read_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext30 :: GPU Time Elapsed */
#define acmgt3__ext30__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext30 :: GPU Core Clocks */
#define acmgt3__ext30__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext30 :: AVG GPU Core Frequency */
#define acmgt3__ext30__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext30 :: AVG GPU Core Frequency */
#define acmgt3__ext30__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext30 :: DATAPORT L3 READ L3BANK16 */
#define acmgt3__ext30__dataport_l3_read_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext30 :: DATAPORT L3 READ L3BANK17 */
#define acmgt3__ext30__dataport_l3_read_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext30 :: DATAPORT L3 READ L3BANK18 */
#define acmgt3__ext30__dataport_l3_read_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext30 :: DATAPORT L3 READ L3BANK19 */
#define acmgt3__ext30__dataport_l3_read_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext30 :: DATAPORT L3 READ L3BANK20 */
#define acmgt3__ext30__dataport_l3_read_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext30 :: DATAPORT L3 READ L3BANK21 */
#define acmgt3__ext30__dataport_l3_read_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext30 :: DATAPORT L3 READ L3BANK22 */
#define acmgt3__ext30__dataport_l3_read_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext30 :: DATAPORT L3 READ L3BANK23 */
#define acmgt3__ext30__dataport_l3_read_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext30 :: DATAPORT L3 READ L3BANK24 */
#define acmgt3__ext30__dataport_l3_read_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext30 :: DATAPORT L3 READ L3BANK25 */
#define acmgt3__ext30__dataport_l3_read_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext30 :: DATAPORT L3 READ L3BANK26 */
#define acmgt3__ext30__dataport_l3_read_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext30 :: DATAPORT L3 READ L3BANK27 */
#define acmgt3__ext30__dataport_l3_read_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext30 :: DATAPORT L3 READ L3BANK28 */
#define acmgt3__ext30__dataport_l3_read_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext30 :: DATAPORT L3 READ L3BANK29 */
#define acmgt3__ext30__dataport_l3_read_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext30 :: DATAPORT L3 READ L3BANK30 */
#define acmgt3__ext30__dataport_l3_read_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext30 :: DATAPORT L3 READ L3BANK31 */
#define acmgt3__ext30__dataport_l3_read_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext31 :: GPU Time Elapsed */
#define acmgt3__ext31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext31 :: GPU Core Clocks */
#define acmgt3__ext31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext31 :: AVG GPU Core Frequency */
#define acmgt3__ext31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext31 :: AVG GPU Core Frequency */
#define acmgt3__ext31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext31 :: DATAPORT L3 WRITE L3BANK0 */
#define acmgt3__ext31__dataport_l3_write_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK1 */
#define acmgt3__ext31__dataport_l3_write_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK2 */
#define acmgt3__ext31__dataport_l3_write_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK3 */
#define acmgt3__ext31__dataport_l3_write_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK4 */
#define acmgt3__ext31__dataport_l3_write_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK5 */
#define acmgt3__ext31__dataport_l3_write_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK6 */
#define acmgt3__ext31__dataport_l3_write_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK7 */
#define acmgt3__ext31__dataport_l3_write_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK8 */
#define acmgt3__ext31__dataport_l3_write_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK9 */
#define acmgt3__ext31__dataport_l3_write_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK10 */
#define acmgt3__ext31__dataport_l3_write_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK11 */
#define acmgt3__ext31__dataport_l3_write_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK12 */
#define acmgt3__ext31__dataport_l3_write_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK13 */
#define acmgt3__ext31__dataport_l3_write_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK14 */
#define acmgt3__ext31__dataport_l3_write_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext31 :: DATAPORT L3 WRITE L3BANK15 */
#define acmgt3__ext31__dataport_l3_write_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext32 :: GPU Time Elapsed */
#define acmgt3__ext32__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext32 :: GPU Core Clocks */
#define acmgt3__ext32__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext32 :: AVG GPU Core Frequency */
#define acmgt3__ext32__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext32 :: AVG GPU Core Frequency */
#define acmgt3__ext32__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext32 :: DATAPORT L3 WRITE L3BANK16 */
#define acmgt3__ext32__dataport_l3_write_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK17 */
#define acmgt3__ext32__dataport_l3_write_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK18 */
#define acmgt3__ext32__dataport_l3_write_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK19 */
#define acmgt3__ext32__dataport_l3_write_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK20 */
#define acmgt3__ext32__dataport_l3_write_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK21 */
#define acmgt3__ext32__dataport_l3_write_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK22 */
#define acmgt3__ext32__dataport_l3_write_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK23 */
#define acmgt3__ext32__dataport_l3_write_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK24 */
#define acmgt3__ext32__dataport_l3_write_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK25 */
#define acmgt3__ext32__dataport_l3_write_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK26 */
#define acmgt3__ext32__dataport_l3_write_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK27 */
#define acmgt3__ext32__dataport_l3_write_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK28 */
#define acmgt3__ext32__dataport_l3_write_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK29 */
#define acmgt3__ext32__dataport_l3_write_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK30 */
#define acmgt3__ext32__dataport_l3_write_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext32 :: DATAPORT L3 WRITE L3BANK31 */
#define acmgt3__ext32__dataport_l3_write_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext33 :: GPU Time Elapsed */
#define acmgt3__ext33__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext33 :: GPU Core Clocks */
#define acmgt3__ext33__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext33 :: AVG GPU Core Frequency */
#define acmgt3__ext33__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext33 :: AVG GPU Core Frequency */
#define acmgt3__ext33__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext33 :: ICACHE L3 READ L3BANK0 */
#define acmgt3__ext33__icache_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext33 :: ICACHE L3 READ L3BANK1 */
#define acmgt3__ext33__icache_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext33 :: ICACHE L3 READ L3BANK2 */
#define acmgt3__ext33__icache_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext33 :: ICACHE L3 READ L3BANK3 */
#define acmgt3__ext33__icache_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext33 :: ICACHE L3 READ L3BANK4 */
#define acmgt3__ext33__icache_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext33 :: ICACHE L3 READ L3BANK5 */
#define acmgt3__ext33__icache_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext33 :: ICACHE L3 READ L3BANK6 */
#define acmgt3__ext33__icache_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext33 :: ICACHE L3 READ L3BANK7 */
#define acmgt3__ext33__icache_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext33 :: ICACHE L3 READ L3BANK8 */
#define acmgt3__ext33__icache_l3_read_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext33 :: ICACHE L3 READ L3BANK9 */
#define acmgt3__ext33__icache_l3_read_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext33 :: ICACHE L3 READ L3BANK10 */
#define acmgt3__ext33__icache_l3_read_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext33 :: ICACHE L3 READ L3BANK11 */
#define acmgt3__ext33__icache_l3_read_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext33 :: ICACHE L3 READ L3BANK12 */
#define acmgt3__ext33__icache_l3_read_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext33 :: ICACHE L3 READ L3BANK13 */
#define acmgt3__ext33__icache_l3_read_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext33 :: ICACHE L3 READ L3BANK14 */
#define acmgt3__ext33__icache_l3_read_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext33 :: ICACHE L3 READ L3BANK15 */
#define acmgt3__ext33__icache_l3_read_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext34 :: GPU Time Elapsed */
#define acmgt3__ext34__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext34 :: GPU Core Clocks */
#define acmgt3__ext34__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext34 :: AVG GPU Core Frequency */
#define acmgt3__ext34__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext34 :: AVG GPU Core Frequency */
#define acmgt3__ext34__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext34 :: ICACHE L3 READ L3BANK16 */
#define acmgt3__ext34__icache_l3_read_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext34 :: ICACHE L3 READ L3BANK17 */
#define acmgt3__ext34__icache_l3_read_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext34 :: ICACHE L3 READ L3BANK18 */
#define acmgt3__ext34__icache_l3_read_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext34 :: ICACHE L3 READ L3BANK19 */
#define acmgt3__ext34__icache_l3_read_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext34 :: ICACHE L3 READ L3BANK20 */
#define acmgt3__ext34__icache_l3_read_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext34 :: ICACHE L3 READ L3BANK21 */
#define acmgt3__ext34__icache_l3_read_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext34 :: ICACHE L3 READ L3BANK22 */
#define acmgt3__ext34__icache_l3_read_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext34 :: ICACHE L3 READ L3BANK23 */
#define acmgt3__ext34__icache_l3_read_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext34 :: ICACHE L3 READ L3BANK24 */
#define acmgt3__ext34__icache_l3_read_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext34 :: ICACHE L3 READ L3BANK25 */
#define acmgt3__ext34__icache_l3_read_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext34 :: ICACHE L3 READ L3BANK26 */
#define acmgt3__ext34__icache_l3_read_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext34 :: ICACHE L3 READ L3BANK27 */
#define acmgt3__ext34__icache_l3_read_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext34 :: ICACHE L3 READ L3BANK28 */
#define acmgt3__ext34__icache_l3_read_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext34 :: ICACHE L3 READ L3BANK29 */
#define acmgt3__ext34__icache_l3_read_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext34 :: ICACHE L3 READ L3BANK30 */
#define acmgt3__ext34__icache_l3_read_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext34 :: ICACHE L3 READ L3BANK31 */
#define acmgt3__ext34__icache_l3_read_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext35 :: GPU Time Elapsed */
#define acmgt3__ext35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext35 :: GPU Core Clocks */
#define acmgt3__ext35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext35 :: AVG GPU Core Frequency */
#define acmgt3__ext35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext35 :: AVG GPU Core Frequency */
#define acmgt3__ext35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext35 :: L3 ATOMIC ACCESS L3BANK0 */
#define acmgt3__ext35__l3_atomic_access_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK1 */
#define acmgt3__ext35__l3_atomic_access_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK2 */
#define acmgt3__ext35__l3_atomic_access_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK3 */
#define acmgt3__ext35__l3_atomic_access_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK4 */
#define acmgt3__ext35__l3_atomic_access_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK5 */
#define acmgt3__ext35__l3_atomic_access_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK6 */
#define acmgt3__ext35__l3_atomic_access_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK7 */
#define acmgt3__ext35__l3_atomic_access_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK8 */
#define acmgt3__ext35__l3_atomic_access_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK9 */
#define acmgt3__ext35__l3_atomic_access_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK10 */
#define acmgt3__ext35__l3_atomic_access_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK11 */
#define acmgt3__ext35__l3_atomic_access_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK12 */
#define acmgt3__ext35__l3_atomic_access_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK13 */
#define acmgt3__ext35__l3_atomic_access_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK14 */
#define acmgt3__ext35__l3_atomic_access_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext35 :: L3 ATOMIC ACCESS L3BANK15 */
#define acmgt3__ext35__l3_atomic_access_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext36 :: GPU Time Elapsed */
#define acmgt3__ext36__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext36 :: GPU Core Clocks */
#define acmgt3__ext36__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext36 :: AVG GPU Core Frequency */
#define acmgt3__ext36__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext36 :: AVG GPU Core Frequency */
#define acmgt3__ext36__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext36 :: L3 ATOMIC ACCESS L3BANK16 */
#define acmgt3__ext36__l3_atomic_access_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK17 */
#define acmgt3__ext36__l3_atomic_access_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK18 */
#define acmgt3__ext36__l3_atomic_access_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK19 */
#define acmgt3__ext36__l3_atomic_access_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK20 */
#define acmgt3__ext36__l3_atomic_access_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK21 */
#define acmgt3__ext36__l3_atomic_access_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK22 */
#define acmgt3__ext36__l3_atomic_access_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK23 */
#define acmgt3__ext36__l3_atomic_access_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK24 */
#define acmgt3__ext36__l3_atomic_access_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK25 */
#define acmgt3__ext36__l3_atomic_access_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK26 */
#define acmgt3__ext36__l3_atomic_access_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK27 */
#define acmgt3__ext36__l3_atomic_access_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK28 */
#define acmgt3__ext36__l3_atomic_access_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK29 */
#define acmgt3__ext36__l3_atomic_access_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK30 */
#define acmgt3__ext36__l3_atomic_access_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext36 :: L3 ATOMIC ACCESS L3BANK31 */
#define acmgt3__ext36__l3_atomic_access_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext37 :: GPU Time Elapsed */
#define acmgt3__ext37__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext37 :: GPU Core Clocks */
#define acmgt3__ext37__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext37 :: AVG GPU Core Frequency */
#define acmgt3__ext37__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext37 :: AVG GPU Core Frequency */
#define acmgt3__ext37__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext37 :: SAMPLER L3 READ L3BANK0 */
#define acmgt3__ext37__sampler_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext37 :: SAMPLER L3 READ L3BANK1 */
#define acmgt3__ext37__sampler_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext37 :: SAMPLER L3 READ L3BANK2 */
#define acmgt3__ext37__sampler_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext37 :: SAMPLER L3 READ L3BANK3 */
#define acmgt3__ext37__sampler_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext37 :: SAMPLER L3 READ L3BANK4 */
#define acmgt3__ext37__sampler_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext37 :: SAMPLER L3 READ L3BANK5 */
#define acmgt3__ext37__sampler_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext37 :: SAMPLER L3 READ L3BANK6 */
#define acmgt3__ext37__sampler_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext37 :: SAMPLER L3 READ L3BANK7 */
#define acmgt3__ext37__sampler_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext37 :: SAMPLER L3 READ L3BANK8 */
#define acmgt3__ext37__sampler_l3_read_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext37 :: SAMPLER L3 READ L3BANK9 */
#define acmgt3__ext37__sampler_l3_read_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext37 :: SAMPLER L3 READ L3BANK10 */
#define acmgt3__ext37__sampler_l3_read_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext37 :: SAMPLER L3 READ L3BANK11 */
#define acmgt3__ext37__sampler_l3_read_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext37 :: SAMPLER L3 READ L3BANK12 */
#define acmgt3__ext37__sampler_l3_read_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext37 :: SAMPLER L3 READ L3BANK13 */
#define acmgt3__ext37__sampler_l3_read_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext37 :: SAMPLER L3 READ L3BANK14 */
#define acmgt3__ext37__sampler_l3_read_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext37 :: SAMPLER L3 READ L3BANK15 */
#define acmgt3__ext37__sampler_l3_read_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext38 :: GPU Time Elapsed */
#define acmgt3__ext38__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext38 :: GPU Core Clocks */
#define acmgt3__ext38__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext38 :: AVG GPU Core Frequency */
#define acmgt3__ext38__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext38 :: AVG GPU Core Frequency */
#define acmgt3__ext38__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext38 :: SAMPLER L3 READ L3BANK16 */
#define acmgt3__ext38__sampler_l3_read_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext38 :: SAMPLER L3 READ L3BANK17 */
#define acmgt3__ext38__sampler_l3_read_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext38 :: SAMPLER L3 READ L3BANK18 */
#define acmgt3__ext38__sampler_l3_read_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext38 :: SAMPLER L3 READ L3BANK19 */
#define acmgt3__ext38__sampler_l3_read_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext38 :: SAMPLER L3 READ L3BANK20 */
#define acmgt3__ext38__sampler_l3_read_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext38 :: SAMPLER L3 READ L3BANK21 */
#define acmgt3__ext38__sampler_l3_read_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext38 :: SAMPLER L3 READ L3BANK22 */
#define acmgt3__ext38__sampler_l3_read_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext38 :: SAMPLER L3 READ L3BANK23 */
#define acmgt3__ext38__sampler_l3_read_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext38 :: SAMPLER L3 READ L3BANK24 */
#define acmgt3__ext38__sampler_l3_read_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext38 :: SAMPLER L3 READ L3BANK25 */
#define acmgt3__ext38__sampler_l3_read_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext38 :: SAMPLER L3 READ L3BANK26 */
#define acmgt3__ext38__sampler_l3_read_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext38 :: SAMPLER L3 READ L3BANK27 */
#define acmgt3__ext38__sampler_l3_read_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext38 :: SAMPLER L3 READ L3BANK28 */
#define acmgt3__ext38__sampler_l3_read_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext38 :: SAMPLER L3 READ L3BANK29 */
#define acmgt3__ext38__sampler_l3_read_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext38 :: SAMPLER L3 READ L3BANK30 */
#define acmgt3__ext38__sampler_l3_read_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext38 :: SAMPLER L3 READ L3BANK31 */
#define acmgt3__ext38__sampler_l3_read_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext39 :: GPU Time Elapsed */
#define acmgt3__ext39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext39 :: GPU Core Clocks */
#define acmgt3__ext39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext39 :: AVG GPU Core Frequency */
#define acmgt3__ext39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext39 :: AVG GPU Core Frequency */
#define acmgt3__ext39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext39 :: COLOR L3 HIT L3BANK0 */
#define acmgt3__ext39__color_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext39 :: COLOR L3 HIT L3BANK1 */
#define acmgt3__ext39__color_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext39 :: COLOR L3 HIT L3BANK2 */
#define acmgt3__ext39__color_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext39 :: COLOR L3 HIT L3BANK3 */
#define acmgt3__ext39__color_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext39 :: COLOR L3 HIT L3BANK4 */
#define acmgt3__ext39__color_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext39 :: COLOR L3 HIT L3BANK5 */
#define acmgt3__ext39__color_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext39 :: COLOR L3 HIT L3BANK6 */
#define acmgt3__ext39__color_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext39 :: COLOR L3 HIT L3BANK7 */
#define acmgt3__ext39__color_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext39 :: COLOR L3 HIT L3BANK8 */
#define acmgt3__ext39__color_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext39 :: COLOR L3 HIT L3BANK9 */
#define acmgt3__ext39__color_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext39 :: COLOR L3 HIT L3BANK10 */
#define acmgt3__ext39__color_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext39 :: COLOR L3 HIT L3BANK11 */
#define acmgt3__ext39__color_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext39 :: COLOR L3 HIT L3BANK12 */
#define acmgt3__ext39__color_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext39 :: COLOR L3 HIT L3BANK13 */
#define acmgt3__ext39__color_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext39 :: COLOR L3 HIT L3BANK14 */
#define acmgt3__ext39__color_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext39 :: COLOR L3 HIT L3BANK15 */
#define acmgt3__ext39__color_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext40 :: GPU Time Elapsed */
#define acmgt3__ext40__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext40 :: GPU Core Clocks */
#define acmgt3__ext40__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext40 :: AVG GPU Core Frequency */
#define acmgt3__ext40__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext40 :: AVG GPU Core Frequency */
#define acmgt3__ext40__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext40 :: COLOR L3 HIT L3BANK16 */
#define acmgt3__ext40__color_l3_hit_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext40 :: COLOR L3 HIT L3BANK17 */
#define acmgt3__ext40__color_l3_hit_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext40 :: COLOR L3 HIT L3BANK18 */
#define acmgt3__ext40__color_l3_hit_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext40 :: COLOR L3 HIT L3BANK19 */
#define acmgt3__ext40__color_l3_hit_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext40 :: COLOR L3 HIT L3BANK20 */
#define acmgt3__ext40__color_l3_hit_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext40 :: COLOR L3 HIT L3BANK21 */
#define acmgt3__ext40__color_l3_hit_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext40 :: COLOR L3 HIT L3BANK22 */
#define acmgt3__ext40__color_l3_hit_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext40 :: COLOR L3 HIT L3BANK23 */
#define acmgt3__ext40__color_l3_hit_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext40 :: COLOR L3 HIT L3BANK24 */
#define acmgt3__ext40__color_l3_hit_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext40 :: COLOR L3 HIT L3BANK25 */
#define acmgt3__ext40__color_l3_hit_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext40 :: COLOR L3 HIT L3BANK26 */
#define acmgt3__ext40__color_l3_hit_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext40 :: COLOR L3 HIT L3BANK27 */
#define acmgt3__ext40__color_l3_hit_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext40 :: COLOR L3 HIT L3BANK28 */
#define acmgt3__ext40__color_l3_hit_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext40 :: COLOR L3 HIT L3BANK29 */
#define acmgt3__ext40__color_l3_hit_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext40 :: COLOR L3 HIT L3BANK30 */
#define acmgt3__ext40__color_l3_hit_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext40 :: COLOR L3 HIT L3BANK31 */
#define acmgt3__ext40__color_l3_hit_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext41 :: GPU Time Elapsed */
#define acmgt3__ext41__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext41 :: GPU Core Clocks */
#define acmgt3__ext41__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext41 :: AVG GPU Core Frequency */
#define acmgt3__ext41__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext41 :: AVG GPU Core Frequency */
#define acmgt3__ext41__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext41 :: DATAPORT L3 HIT L3BANK0 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext41 :: DATAPORT L3 HIT L3BANK1 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext41 :: DATAPORT L3 HIT L3BANK2 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext41 :: DATAPORT L3 HIT L3BANK3 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK4 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK5 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext41 :: DATAPORT L3 HIT L3BANK6 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK7 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK8 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext41 :: DATAPORT L3 HIT L3BANK9 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK10 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK11 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK12 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK13 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK14 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext41 :: DATAPORT L3 HIT L3BANK15 */
#define acmgt3__ext41__dataport_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext42 :: GPU Time Elapsed */
#define acmgt3__ext42__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext42 :: GPU Core Clocks */
#define acmgt3__ext42__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext42 :: AVG GPU Core Frequency */
#define acmgt3__ext42__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext42 :: AVG GPU Core Frequency */
#define acmgt3__ext42__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext42 :: DATAPORT L3 HIT L3BANK16 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext42 :: DATAPORT L3 HIT L3BANK17 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext42 :: DATAPORT L3 HIT L3BANK18 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext42 :: DATAPORT L3 HIT L3BANK19 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK20 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK21 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext42 :: DATAPORT L3 HIT L3BANK22 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK23 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK24 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext42 :: DATAPORT L3 HIT L3BANK25 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK26 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK27 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK28 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK29 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK30 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext42 :: DATAPORT L3 HIT L3BANK31 */
#define acmgt3__ext42__dataport_l3_hit_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext43 :: GPU Time Elapsed */
#define acmgt3__ext43__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext43 :: GPU Core Clocks */
#define acmgt3__ext43__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext43 :: AVG GPU Core Frequency */
#define acmgt3__ext43__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext43 :: AVG GPU Core Frequency */
#define acmgt3__ext43__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext43 :: ICACHE L3 HIT L3BANK0 */
#define acmgt3__ext43__icache_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext43 :: ICACHE L3 HIT L3BANK1 */
#define acmgt3__ext43__icache_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext43 :: ICACHE L3 HIT L3BANK2 */
#define acmgt3__ext43__icache_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext43 :: ICACHE L3 HIT L3BANK3 */
#define acmgt3__ext43__icache_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext43 :: ICACHE L3 HIT L3BANK4 */
#define acmgt3__ext43__icache_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext43 :: ICACHE L3 HIT L3BANK5 */
#define acmgt3__ext43__icache_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext43 :: ICACHE L3 HIT L3BANK6 */
#define acmgt3__ext43__icache_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext43 :: ICACHE L3 HIT L3BANK7 */
#define acmgt3__ext43__icache_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext43 :: ICACHE L3 HIT L3BANK8 */
#define acmgt3__ext43__icache_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext43 :: ICACHE L3 HIT L3BANK9 */
#define acmgt3__ext43__icache_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext43 :: ICACHE L3 HIT L3BANK10 */
#define acmgt3__ext43__icache_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext43 :: ICACHE L3 HIT L3BANK11 */
#define acmgt3__ext43__icache_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext43 :: ICACHE L3 HIT L3BANK12 */
#define acmgt3__ext43__icache_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext43 :: ICACHE L3 HIT L3BANK13 */
#define acmgt3__ext43__icache_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext43 :: ICACHE L3 HIT L3BANK14 */
#define acmgt3__ext43__icache_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext43 :: ICACHE L3 HIT L3BANK15 */
#define acmgt3__ext43__icache_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext44 :: GPU Time Elapsed */
#define acmgt3__ext44__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext44 :: GPU Core Clocks */
#define acmgt3__ext44__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext44 :: AVG GPU Core Frequency */
#define acmgt3__ext44__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext44 :: AVG GPU Core Frequency */
#define acmgt3__ext44__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext44 :: ICACHE L3 HIT L3BANK16 */
#define acmgt3__ext44__icache_l3_hit_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext44 :: ICACHE L3 HIT L3BANK17 */
#define acmgt3__ext44__icache_l3_hit_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext44 :: ICACHE L3 HIT L3BANK18 */
#define acmgt3__ext44__icache_l3_hit_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext44 :: ICACHE L3 HIT L3BANK19 */
#define acmgt3__ext44__icache_l3_hit_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext44 :: ICACHE L3 HIT L3BANK20 */
#define acmgt3__ext44__icache_l3_hit_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext44 :: ICACHE L3 HIT L3BANK21 */
#define acmgt3__ext44__icache_l3_hit_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext44 :: ICACHE L3 HIT L3BANK22 */
#define acmgt3__ext44__icache_l3_hit_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext44 :: ICACHE L3 HIT L3BANK23 */
#define acmgt3__ext44__icache_l3_hit_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext44 :: ICACHE L3 HIT L3BANK24 */
#define acmgt3__ext44__icache_l3_hit_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext44 :: ICACHE L3 HIT L3BANK25 */
#define acmgt3__ext44__icache_l3_hit_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext44 :: ICACHE L3 HIT L3BANK26 */
#define acmgt3__ext44__icache_l3_hit_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext44 :: ICACHE L3 HIT L3BANK27 */
#define acmgt3__ext44__icache_l3_hit_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext44 :: ICACHE L3 HIT L3BANK28 */
#define acmgt3__ext44__icache_l3_hit_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext44 :: ICACHE L3 HIT L3BANK29 */
#define acmgt3__ext44__icache_l3_hit_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext44 :: ICACHE L3 HIT L3BANK30 */
#define acmgt3__ext44__icache_l3_hit_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext44 :: ICACHE L3 HIT L3BANK31 */
#define acmgt3__ext44__icache_l3_hit_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext45 :: GPU Time Elapsed */
#define acmgt3__ext45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext45 :: GPU Core Clocks */
#define acmgt3__ext45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext45 :: AVG GPU Core Frequency */
#define acmgt3__ext45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext45 :: AVG GPU Core Frequency */
#define acmgt3__ext45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext45 :: SAMPLER L3 HIT L3BANK0 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext45 :: SAMPLER L3 HIT L3BANK1 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext45 :: SAMPLER L3 HIT L3BANK2 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext45 :: SAMPLER L3 HIT L3BANK3 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK4 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK5 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext45 :: SAMPLER L3 HIT L3BANK6 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK7 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK8 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext45 :: SAMPLER L3 HIT L3BANK9 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK10 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK11 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK12 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK13 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK14 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext45 :: SAMPLER L3 HIT L3BANK15 */
#define acmgt3__ext45__sampler_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext46 :: GPU Time Elapsed */
#define acmgt3__ext46__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext46 :: GPU Core Clocks */
#define acmgt3__ext46__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext46 :: AVG GPU Core Frequency */
#define acmgt3__ext46__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext46 :: AVG GPU Core Frequency */
#define acmgt3__ext46__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext46 :: SAMPLER L3 HIT L3BANK16 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext46 :: SAMPLER L3 HIT L3BANK17 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext46 :: SAMPLER L3 HIT L3BANK18 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext46 :: SAMPLER L3 HIT L3BANK19 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK20 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK21 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext46 :: SAMPLER L3 HIT L3BANK22 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK23 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK24 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext46 :: SAMPLER L3 HIT L3BANK25 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK26 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK27 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK28 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK29 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK30 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext46 :: SAMPLER L3 HIT L3BANK31 */
#define acmgt3__ext46__sampler_l3_hit_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext47 :: GPU Time Elapsed */
#define acmgt3__ext47__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext47 :: GPU Core Clocks */
#define acmgt3__ext47__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext47 :: AVG GPU Core Frequency */
#define acmgt3__ext47__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext47 :: AVG GPU Core Frequency */
#define acmgt3__ext47__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext47 :: Z L3 HIT L3BANK0 */
#define acmgt3__ext47__z_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext47 :: Z L3 HIT L3BANK1 */
#define acmgt3__ext47__z_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext47 :: Z L3 HIT L3BANK2 */
#define acmgt3__ext47__z_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext47 :: Z L3 HIT L3BANK3 */
#define acmgt3__ext47__z_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext47 :: Z L3 HIT L3BANK4 */
#define acmgt3__ext47__z_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext47 :: Z L3 HIT L3BANK5 */
#define acmgt3__ext47__z_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext47 :: Z L3 HIT L3BANK6 */
#define acmgt3__ext47__z_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext47 :: Z L3 HIT L3BANK7 */
#define acmgt3__ext47__z_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext47 :: Z L3 HIT L3BANK8 */
#define acmgt3__ext47__z_l3_hit_l3_bank8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext47 :: Z L3 HIT L3BANK9 */
#define acmgt3__ext47__z_l3_hit_l3_bank9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext47 :: Z L3 HIT L3BANK10 */
#define acmgt3__ext47__z_l3_hit_l3_bank10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext47 :: Z L3 HIT L3BANK11 */
#define acmgt3__ext47__z_l3_hit_l3_bank11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext47 :: Z L3 HIT L3BANK12 */
#define acmgt3__ext47__z_l3_hit_l3_bank12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext47 :: Z L3 HIT L3BANK13 */
#define acmgt3__ext47__z_l3_hit_l3_bank13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext47 :: Z L3 HIT L3BANK14 */
#define acmgt3__ext47__z_l3_hit_l3_bank14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext47 :: Z L3 HIT L3BANK15 */
#define acmgt3__ext47__z_l3_hit_l3_bank15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext48 :: GPU Time Elapsed */
#define acmgt3__ext48__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext48 :: GPU Core Clocks */
#define acmgt3__ext48__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext48 :: AVG GPU Core Frequency */
#define acmgt3__ext48__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext48 :: AVG GPU Core Frequency */
#define acmgt3__ext48__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext48 :: Z L3 HIT L3BANK16 */
#define acmgt3__ext48__z_l3_hit_l3_bank16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext48 :: Z L3 HIT L3BANK17 */
#define acmgt3__ext48__z_l3_hit_l3_bank17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext48 :: Z L3 HIT L3BANK18 */
#define acmgt3__ext48__z_l3_hit_l3_bank18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext48 :: Z L3 HIT L3BANK19 */
#define acmgt3__ext48__z_l3_hit_l3_bank19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext48 :: Z L3 HIT L3BANK20 */
#define acmgt3__ext48__z_l3_hit_l3_bank20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext48 :: Z L3 HIT L3BANK21 */
#define acmgt3__ext48__z_l3_hit_l3_bank21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext48 :: Z L3 HIT L3BANK22 */
#define acmgt3__ext48__z_l3_hit_l3_bank22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext48 :: Z L3 HIT L3BANK23 */
#define acmgt3__ext48__z_l3_hit_l3_bank23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext48 :: Z L3 HIT L3BANK24 */
#define acmgt3__ext48__z_l3_hit_l3_bank24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext48 :: Z L3 HIT L3BANK25 */
#define acmgt3__ext48__z_l3_hit_l3_bank25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext48 :: Z L3 HIT L3BANK26 */
#define acmgt3__ext48__z_l3_hit_l3_bank26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext48 :: Z L3 HIT L3BANK27 */
#define acmgt3__ext48__z_l3_hit_l3_bank27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext48 :: Z L3 HIT L3BANK28 */
#define acmgt3__ext48__z_l3_hit_l3_bank28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext48 :: Z L3 HIT L3BANK29 */
#define acmgt3__ext48__z_l3_hit_l3_bank29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext48 :: Z L3 HIT L3BANK30 */
#define acmgt3__ext48__z_l3_hit_l3_bank30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext48 :: Z L3 HIT L3BANK31 */
#define acmgt3__ext48__z_l3_hit_l3_bank31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext49 :: GPU Time Elapsed */
#define acmgt3__ext49__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext49 :: GPU Core Clocks */
#define acmgt3__ext49__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext49 :: AVG GPU Core Frequency */
#define acmgt3__ext49__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext49 :: AVG GPU Core Frequency */
#define acmgt3__ext49__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext49 :: L3 SUPERQ FULL L3BANK0 */
#define acmgt3__ext49__l3_superq_full_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext49 :: L3 SUPERQ FULL L3BANK1 */
#define acmgt3__ext49__l3_superq_full_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext49 :: L3 SUPERQ FULL L3BANK2 */
#define acmgt3__ext49__l3_superq_full_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext49 :: L3 SUPERQ FULL L3BANK3 */
#define acmgt3__ext49__l3_superq_full_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext49 :: L3 SUPERQ FULL L3BANK4 */
#define acmgt3__ext49__l3_superq_full_l3_bank4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext49 :: L3 SUPERQ FULL L3BANK5 */
#define acmgt3__ext49__l3_superq_full_l3_bank5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext49 :: L3 SUPERQ FULL L3BANK6 */
#define acmgt3__ext49__l3_superq_full_l3_bank6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext49 :: L3 SUPERQ FULL L3BANK7 */
#define acmgt3__ext49__l3_superq_full_l3_bank7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext50 :: GPU Time Elapsed */
#define acmgt3__ext50__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext50 :: GPU Core Clocks */
#define acmgt3__ext50__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext50 :: AVG GPU Core Frequency */
#define acmgt3__ext50__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext50 :: AVG GPU Core Frequency */
#define acmgt3__ext50__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext50 :: L3 SUPERQ FULL L3BANK8 */
#define acmgt3__ext50__l3_superq_full_l3_bank8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext50 :: L3 SUPERQ FULL L3BANK9 */
#define acmgt3__ext50__l3_superq_full_l3_bank9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext50 :: L3 SUPERQ FULL L3BANK10 */
#define acmgt3__ext50__l3_superq_full_l3_bank10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext50 :: L3 SUPERQ FULL L3BANK11 */
#define acmgt3__ext50__l3_superq_full_l3_bank11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext50 :: L3 SUPERQ FULL L3BANK12 */
#define acmgt3__ext50__l3_superq_full_l3_bank12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext50 :: L3 SUPERQ FULL L3BANK13 */
#define acmgt3__ext50__l3_superq_full_l3_bank13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext50 :: L3 SUPERQ FULL L3BANK14 */
#define acmgt3__ext50__l3_superq_full_l3_bank14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext50 :: L3 SUPERQ FULL L3BANK15 */
#define acmgt3__ext50__l3_superq_full_l3_bank15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext51 :: GPU Time Elapsed */
#define acmgt3__ext51__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext51 :: GPU Core Clocks */
#define acmgt3__ext51__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext51 :: AVG GPU Core Frequency */
#define acmgt3__ext51__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext51 :: AVG GPU Core Frequency */
#define acmgt3__ext51__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext51 :: L3 SUPERQ FULL L3BANK16 */
#define acmgt3__ext51__l3_superq_full_l3_bank16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext51 :: L3 SUPERQ FULL L3BANK17 */
#define acmgt3__ext51__l3_superq_full_l3_bank17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext51 :: L3 SUPERQ FULL L3BANK18 */
#define acmgt3__ext51__l3_superq_full_l3_bank18__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext51 :: L3 SUPERQ FULL L3BANK19 */
#define acmgt3__ext51__l3_superq_full_l3_bank19__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext51 :: L3 SUPERQ FULL L3BANK20 */
#define acmgt3__ext51__l3_superq_full_l3_bank20__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext51 :: L3 SUPERQ FULL L3BANK21 */
#define acmgt3__ext51__l3_superq_full_l3_bank21__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext51 :: L3 SUPERQ FULL L3BANK22 */
#define acmgt3__ext51__l3_superq_full_l3_bank22__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext51 :: L3 SUPERQ FULL L3BANK23 */
#define acmgt3__ext51__l3_superq_full_l3_bank23__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext52 :: GPU Time Elapsed */
#define acmgt3__ext52__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext52 :: GPU Core Clocks */
#define acmgt3__ext52__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext52 :: AVG GPU Core Frequency */
#define acmgt3__ext52__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext52 :: AVG GPU Core Frequency */
#define acmgt3__ext52__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext52 :: L3 SUPERQ FULL L3BANK24 */
#define acmgt3__ext52__l3_superq_full_l3_bank24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext52 :: L3 SUPERQ FULL L3BANK25 */
#define acmgt3__ext52__l3_superq_full_l3_bank25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext52 :: L3 SUPERQ FULL L3BANK26 */
#define acmgt3__ext52__l3_superq_full_l3_bank26__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext52 :: L3 SUPERQ FULL L3BANK27 */
#define acmgt3__ext52__l3_superq_full_l3_bank27__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext52 :: L3 SUPERQ FULL L3BANK28 */
#define acmgt3__ext52__l3_superq_full_l3_bank28__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext52 :: L3 SUPERQ FULL L3BANK29 */
#define acmgt3__ext52__l3_superq_full_l3_bank29__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext52 :: L3 SUPERQ FULL L3BANK30 */
#define acmgt3__ext52__l3_superq_full_l3_bank30__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext52 :: L3 SUPERQ FULL L3BANK31 */
#define acmgt3__ext52__l3_superq_full_l3_bank31__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext53 :: GPU Time Elapsed */
#define acmgt3__ext53__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext53 :: GPU Core Clocks */
#define acmgt3__ext53__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext53 :: AVG GPU Core Frequency */
#define acmgt3__ext53__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext53 :: AVG GPU Core Frequency */
#define acmgt3__ext53__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext53 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define acmgt3__ext53__xve_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext53 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define acmgt3__ext53__xve_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext54 :: GPU Time Elapsed */
#define acmgt3__ext54__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext54 :: GPU Core Clocks */
#define acmgt3__ext54__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext54 :: AVG GPU Core Frequency */
#define acmgt3__ext54__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext54 :: AVG GPU Core Frequency */
#define acmgt3__ext54__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext54 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define acmgt3__ext54__xve_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext54 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define acmgt3__ext54__xve_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext55 :: GPU Time Elapsed */
#define acmgt3__ext55__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext55 :: GPU Core Clocks */
#define acmgt3__ext55__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext55 :: AVG GPU Core Frequency */
#define acmgt3__ext55__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext55 :: AVG GPU Core Frequency */
#define acmgt3__ext55__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext55 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4 */
#define acmgt3__ext55__xve_load_store_cache_read_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext55 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5 */
#define acmgt3__ext55__xve_load_store_cache_read_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext56 :: GPU Time Elapsed */
#define acmgt3__ext56__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext56 :: GPU Core Clocks */
#define acmgt3__ext56__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext56 :: AVG GPU Core Frequency */
#define acmgt3__ext56__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext56 :: AVG GPU Core Frequency */
#define acmgt3__ext56__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext56 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6 */
#define acmgt3__ext56__xve_load_store_cache_read_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext56 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7 */
#define acmgt3__ext56__xve_load_store_cache_read_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext57 :: GPU Time Elapsed */
#define acmgt3__ext57__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext57 :: GPU Core Clocks */
#define acmgt3__ext57__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext57 :: AVG GPU Core Frequency */
#define acmgt3__ext57__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext57 :: AVG GPU Core Frequency */
#define acmgt3__ext57__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext57 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE8 */
#define acmgt3__ext57__xve_load_store_cache_read_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext57 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE9 */
#define acmgt3__ext57__xve_load_store_cache_read_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext58 :: GPU Time Elapsed */
#define acmgt3__ext58__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext58 :: GPU Core Clocks */
#define acmgt3__ext58__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext58 :: AVG GPU Core Frequency */
#define acmgt3__ext58__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext58 :: AVG GPU Core Frequency */
#define acmgt3__ext58__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext58 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE10 */
#define acmgt3__ext58__xve_load_store_cache_read_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext58 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE11 */
#define acmgt3__ext58__xve_load_store_cache_read_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext59 :: GPU Time Elapsed */
#define acmgt3__ext59__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext59 :: GPU Core Clocks */
#define acmgt3__ext59__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext59 :: AVG GPU Core Frequency */
#define acmgt3__ext59__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext59 :: AVG GPU Core Frequency */
#define acmgt3__ext59__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext59 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE12 */
#define acmgt3__ext59__xve_load_store_cache_read_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext59 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE13 */
#define acmgt3__ext59__xve_load_store_cache_read_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext60 :: GPU Time Elapsed */
#define acmgt3__ext60__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext60 :: GPU Core Clocks */
#define acmgt3__ext60__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext60 :: AVG GPU Core Frequency */
#define acmgt3__ext60__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext60 :: AVG GPU Core Frequency */
#define acmgt3__ext60__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext60 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE14 */
#define acmgt3__ext60__xve_load_store_cache_read_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext60 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE15 */
#define acmgt3__ext60__xve_load_store_cache_read_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext61 :: GPU Time Elapsed */
#define acmgt3__ext61__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext61 :: GPU Core Clocks */
#define acmgt3__ext61__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext61 :: AVG GPU Core Frequency */
#define acmgt3__ext61__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext61 :: AVG GPU Core Frequency */
#define acmgt3__ext61__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext61 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE16 */
#define acmgt3__ext61__xve_load_store_cache_read_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext61 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE17 */
#define acmgt3__ext61__xve_load_store_cache_read_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext62 :: GPU Time Elapsed */
#define acmgt3__ext62__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext62 :: GPU Core Clocks */
#define acmgt3__ext62__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext62 :: AVG GPU Core Frequency */
#define acmgt3__ext62__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext62 :: AVG GPU Core Frequency */
#define acmgt3__ext62__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext62 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE18 */
#define acmgt3__ext62__xve_load_store_cache_read_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext62 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE19 */
#define acmgt3__ext62__xve_load_store_cache_read_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext63 :: GPU Time Elapsed */
#define acmgt3__ext63__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext63 :: GPU Core Clocks */
#define acmgt3__ext63__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext63 :: AVG GPU Core Frequency */
#define acmgt3__ext63__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext63 :: AVG GPU Core Frequency */
#define acmgt3__ext63__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext63 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE20 */
#define acmgt3__ext63__xve_load_store_cache_read_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext63 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE21 */
#define acmgt3__ext63__xve_load_store_cache_read_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext64 :: GPU Time Elapsed */
#define acmgt3__ext64__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext64 :: GPU Core Clocks */
#define acmgt3__ext64__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext64 :: AVG GPU Core Frequency */
#define acmgt3__ext64__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext64 :: AVG GPU Core Frequency */
#define acmgt3__ext64__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext64 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE22 */
#define acmgt3__ext64__xve_load_store_cache_read_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext64 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE23 */
#define acmgt3__ext64__xve_load_store_cache_read_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext65 :: GPU Time Elapsed */
#define acmgt3__ext65__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext65 :: GPU Core Clocks */
#define acmgt3__ext65__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext65 :: AVG GPU Core Frequency */
#define acmgt3__ext65__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext65 :: AVG GPU Core Frequency */
#define acmgt3__ext65__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext65 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE24 */
#define acmgt3__ext65__xve_load_store_cache_read_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext65 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE25 */
#define acmgt3__ext65__xve_load_store_cache_read_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext66 :: GPU Time Elapsed */
#define acmgt3__ext66__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext66 :: GPU Core Clocks */
#define acmgt3__ext66__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext66 :: AVG GPU Core Frequency */
#define acmgt3__ext66__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext66 :: AVG GPU Core Frequency */
#define acmgt3__ext66__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext66 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE26 */
#define acmgt3__ext66__xve_load_store_cache_read_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext66 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE27 */
#define acmgt3__ext66__xve_load_store_cache_read_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext67 :: GPU Time Elapsed */
#define acmgt3__ext67__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext67 :: GPU Core Clocks */
#define acmgt3__ext67__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext67 :: AVG GPU Core Frequency */
#define acmgt3__ext67__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext67 :: AVG GPU Core Frequency */
#define acmgt3__ext67__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext67 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE28 */
#define acmgt3__ext67__xve_load_store_cache_read_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext67 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE29 */
#define acmgt3__ext67__xve_load_store_cache_read_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext68 :: GPU Time Elapsed */
#define acmgt3__ext68__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext68 :: GPU Core Clocks */
#define acmgt3__ext68__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext68 :: AVG GPU Core Frequency */
#define acmgt3__ext68__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext68 :: AVG GPU Core Frequency */
#define acmgt3__ext68__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext68 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE30 */
#define acmgt3__ext68__xve_load_store_cache_read_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext68 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE31 */
#define acmgt3__ext68__xve_load_store_cache_read_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext69 :: GPU Time Elapsed */
#define acmgt3__ext69__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext69 :: GPU Core Clocks */
#define acmgt3__ext69__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext69 :: AVG GPU Core Frequency */
#define acmgt3__ext69__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext69 :: AVG GPU Core Frequency */
#define acmgt3__ext69__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext69 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0 */
#define acmgt3__ext69__xve_load_store_cache_write_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext69 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1 */
#define acmgt3__ext69__xve_load_store_cache_write_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext70 :: GPU Time Elapsed */
#define acmgt3__ext70__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext70 :: GPU Core Clocks */
#define acmgt3__ext70__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext70 :: AVG GPU Core Frequency */
#define acmgt3__ext70__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext70 :: AVG GPU Core Frequency */
#define acmgt3__ext70__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext70 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2 */
#define acmgt3__ext70__xve_load_store_cache_write_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext70 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3 */
#define acmgt3__ext70__xve_load_store_cache_write_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext71 :: GPU Time Elapsed */
#define acmgt3__ext71__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext71 :: GPU Core Clocks */
#define acmgt3__ext71__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext71 :: AVG GPU Core Frequency */
#define acmgt3__ext71__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext71 :: AVG GPU Core Frequency */
#define acmgt3__ext71__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext71 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4 */
#define acmgt3__ext71__xve_load_store_cache_write_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext71 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5 */
#define acmgt3__ext71__xve_load_store_cache_write_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext72 :: GPU Time Elapsed */
#define acmgt3__ext72__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext72 :: GPU Core Clocks */
#define acmgt3__ext72__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext72 :: AVG GPU Core Frequency */
#define acmgt3__ext72__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext72 :: AVG GPU Core Frequency */
#define acmgt3__ext72__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext72 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6 */
#define acmgt3__ext72__xve_load_store_cache_write_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext72 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7 */
#define acmgt3__ext72__xve_load_store_cache_write_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext73 :: GPU Time Elapsed */
#define acmgt3__ext73__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext73 :: GPU Core Clocks */
#define acmgt3__ext73__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext73 :: AVG GPU Core Frequency */
#define acmgt3__ext73__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext73 :: AVG GPU Core Frequency */
#define acmgt3__ext73__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext73 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE8 */
#define acmgt3__ext73__xve_load_store_cache_write_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext73 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE9 */
#define acmgt3__ext73__xve_load_store_cache_write_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext74 :: GPU Time Elapsed */
#define acmgt3__ext74__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext74 :: GPU Core Clocks */
#define acmgt3__ext74__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext74 :: AVG GPU Core Frequency */
#define acmgt3__ext74__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext74 :: AVG GPU Core Frequency */
#define acmgt3__ext74__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext74 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE10 */
#define acmgt3__ext74__xve_load_store_cache_write_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext74 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE11 */
#define acmgt3__ext74__xve_load_store_cache_write_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext75 :: GPU Time Elapsed */
#define acmgt3__ext75__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext75 :: GPU Core Clocks */
#define acmgt3__ext75__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext75 :: AVG GPU Core Frequency */
#define acmgt3__ext75__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext75 :: AVG GPU Core Frequency */
#define acmgt3__ext75__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext75 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE12 */
#define acmgt3__ext75__xve_load_store_cache_write_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext75 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE13 */
#define acmgt3__ext75__xve_load_store_cache_write_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext76 :: GPU Time Elapsed */
#define acmgt3__ext76__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext76 :: GPU Core Clocks */
#define acmgt3__ext76__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext76 :: AVG GPU Core Frequency */
#define acmgt3__ext76__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext76 :: AVG GPU Core Frequency */
#define acmgt3__ext76__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext76 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE14 */
#define acmgt3__ext76__xve_load_store_cache_write_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext76 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE15 */
#define acmgt3__ext76__xve_load_store_cache_write_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext77 :: GPU Time Elapsed */
#define acmgt3__ext77__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext77 :: GPU Core Clocks */
#define acmgt3__ext77__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext77 :: AVG GPU Core Frequency */
#define acmgt3__ext77__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext77 :: AVG GPU Core Frequency */
#define acmgt3__ext77__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext77 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE16 */
#define acmgt3__ext77__xve_load_store_cache_write_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext77 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE17 */
#define acmgt3__ext77__xve_load_store_cache_write_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext78 :: GPU Time Elapsed */
#define acmgt3__ext78__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext78 :: GPU Core Clocks */
#define acmgt3__ext78__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext78 :: AVG GPU Core Frequency */
#define acmgt3__ext78__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext78 :: AVG GPU Core Frequency */
#define acmgt3__ext78__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext78 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE18 */
#define acmgt3__ext78__xve_load_store_cache_write_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext78 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE19 */
#define acmgt3__ext78__xve_load_store_cache_write_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext79 :: GPU Time Elapsed */
#define acmgt3__ext79__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext79 :: GPU Core Clocks */
#define acmgt3__ext79__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext79 :: AVG GPU Core Frequency */
#define acmgt3__ext79__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext79 :: AVG GPU Core Frequency */
#define acmgt3__ext79__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext79 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE20 */
#define acmgt3__ext79__xve_load_store_cache_write_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext79 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE21 */
#define acmgt3__ext79__xve_load_store_cache_write_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext80 :: GPU Time Elapsed */
#define acmgt3__ext80__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext80 :: GPU Core Clocks */
#define acmgt3__ext80__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext80 :: AVG GPU Core Frequency */
#define acmgt3__ext80__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext80 :: AVG GPU Core Frequency */
#define acmgt3__ext80__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext80 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE22 */
#define acmgt3__ext80__xve_load_store_cache_write_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext80 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE23 */
#define acmgt3__ext80__xve_load_store_cache_write_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext81 :: GPU Time Elapsed */
#define acmgt3__ext81__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext81 :: GPU Core Clocks */
#define acmgt3__ext81__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext81 :: AVG GPU Core Frequency */
#define acmgt3__ext81__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext81 :: AVG GPU Core Frequency */
#define acmgt3__ext81__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext81 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE24 */
#define acmgt3__ext81__xve_load_store_cache_write_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext81 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE25 */
#define acmgt3__ext81__xve_load_store_cache_write_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext82 :: GPU Time Elapsed */
#define acmgt3__ext82__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext82 :: GPU Core Clocks */
#define acmgt3__ext82__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext82 :: AVG GPU Core Frequency */
#define acmgt3__ext82__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext82 :: AVG GPU Core Frequency */
#define acmgt3__ext82__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext82 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE26 */
#define acmgt3__ext82__xve_load_store_cache_write_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext82 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE27 */
#define acmgt3__ext82__xve_load_store_cache_write_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext83 :: GPU Time Elapsed */
#define acmgt3__ext83__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext83 :: GPU Core Clocks */
#define acmgt3__ext83__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext83 :: AVG GPU Core Frequency */
#define acmgt3__ext83__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext83 :: AVG GPU Core Frequency */
#define acmgt3__ext83__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext83 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE28 */
#define acmgt3__ext83__xve_load_store_cache_write_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext83 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE29 */
#define acmgt3__ext83__xve_load_store_cache_write_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext84 :: GPU Time Elapsed */
#define acmgt3__ext84__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext84 :: GPU Core Clocks */
#define acmgt3__ext84__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext84 :: AVG GPU Core Frequency */
#define acmgt3__ext84__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext84 :: AVG GPU Core Frequency */
#define acmgt3__ext84__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext84 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE30 */
#define acmgt3__ext84__xve_load_store_cache_write_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext84 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE31 */
#define acmgt3__ext84__xve_load_store_cache_write_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext85 :: GPU Time Elapsed */
#define acmgt3__ext85__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext85 :: GPU Core Clocks */
#define acmgt3__ext85__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext85 :: AVG GPU Core Frequency */
#define acmgt3__ext85__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext85 :: AVG GPU Core Frequency */
#define acmgt3__ext85__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext85 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0 */
#define acmgt3__ext85__xve_load_store_cache_atomic_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext86 :: GPU Time Elapsed */
#define acmgt3__ext86__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext86 :: GPU Core Clocks */
#define acmgt3__ext86__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext86 :: AVG GPU Core Frequency */
#define acmgt3__ext86__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext86 :: AVG GPU Core Frequency */
#define acmgt3__ext86__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext86 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1 */
#define acmgt3__ext86__xve_load_store_cache_atomic_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext87 :: GPU Time Elapsed */
#define acmgt3__ext87__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext87 :: GPU Core Clocks */
#define acmgt3__ext87__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext87 :: AVG GPU Core Frequency */
#define acmgt3__ext87__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext87 :: AVG GPU Core Frequency */
#define acmgt3__ext87__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext87 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2 */
#define acmgt3__ext87__xve_load_store_cache_atomic_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext88 :: GPU Time Elapsed */
#define acmgt3__ext88__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext88 :: GPU Core Clocks */
#define acmgt3__ext88__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext88 :: AVG GPU Core Frequency */
#define acmgt3__ext88__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext88 :: AVG GPU Core Frequency */
#define acmgt3__ext88__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext88 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3 */
#define acmgt3__ext88__xve_load_store_cache_atomic_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext89 :: GPU Time Elapsed */
#define acmgt3__ext89__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext89 :: GPU Core Clocks */
#define acmgt3__ext89__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext89 :: AVG GPU Core Frequency */
#define acmgt3__ext89__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext89 :: AVG GPU Core Frequency */
#define acmgt3__ext89__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext89 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4 */
#define acmgt3__ext89__xve_load_store_cache_atomic_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext90 :: GPU Time Elapsed */
#define acmgt3__ext90__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext90 :: GPU Core Clocks */
#define acmgt3__ext90__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext90 :: AVG GPU Core Frequency */
#define acmgt3__ext90__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext90 :: AVG GPU Core Frequency */
#define acmgt3__ext90__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext90 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5 */
#define acmgt3__ext90__xve_load_store_cache_atomic_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext91 :: GPU Time Elapsed */
#define acmgt3__ext91__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext91 :: GPU Core Clocks */
#define acmgt3__ext91__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext91 :: AVG GPU Core Frequency */
#define acmgt3__ext91__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext91 :: AVG GPU Core Frequency */
#define acmgt3__ext91__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext91 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6 */
#define acmgt3__ext91__xve_load_store_cache_atomic_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext92 :: GPU Time Elapsed */
#define acmgt3__ext92__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext92 :: GPU Core Clocks */
#define acmgt3__ext92__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext92 :: AVG GPU Core Frequency */
#define acmgt3__ext92__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext92 :: AVG GPU Core Frequency */
#define acmgt3__ext92__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext92 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7 */
#define acmgt3__ext92__xve_load_store_cache_atomic_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext93 :: GPU Time Elapsed */
#define acmgt3__ext93__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext93 :: GPU Core Clocks */
#define acmgt3__ext93__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext93 :: AVG GPU Core Frequency */
#define acmgt3__ext93__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext93 :: AVG GPU Core Frequency */
#define acmgt3__ext93__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext93 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE8 */
#define acmgt3__ext93__xve_load_store_cache_atomic_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext94 :: GPU Time Elapsed */
#define acmgt3__ext94__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext94 :: GPU Core Clocks */
#define acmgt3__ext94__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext94 :: AVG GPU Core Frequency */
#define acmgt3__ext94__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext94 :: AVG GPU Core Frequency */
#define acmgt3__ext94__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext94 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE9 */
#define acmgt3__ext94__xve_load_store_cache_atomic_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext95 :: GPU Time Elapsed */
#define acmgt3__ext95__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext95 :: GPU Core Clocks */
#define acmgt3__ext95__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext95 :: AVG GPU Core Frequency */
#define acmgt3__ext95__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext95 :: AVG GPU Core Frequency */
#define acmgt3__ext95__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext95 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE10 */
#define acmgt3__ext95__xve_load_store_cache_atomic_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext96 :: GPU Time Elapsed */
#define acmgt3__ext96__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext96 :: GPU Core Clocks */
#define acmgt3__ext96__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext96 :: AVG GPU Core Frequency */
#define acmgt3__ext96__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext96 :: AVG GPU Core Frequency */
#define acmgt3__ext96__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext96 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE11 */
#define acmgt3__ext96__xve_load_store_cache_atomic_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext97 :: GPU Time Elapsed */
#define acmgt3__ext97__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext97 :: GPU Core Clocks */
#define acmgt3__ext97__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext97 :: AVG GPU Core Frequency */
#define acmgt3__ext97__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext97 :: AVG GPU Core Frequency */
#define acmgt3__ext97__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext97 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE12 */
#define acmgt3__ext97__xve_load_store_cache_atomic_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext98 :: GPU Time Elapsed */
#define acmgt3__ext98__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext98 :: GPU Core Clocks */
#define acmgt3__ext98__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext98 :: AVG GPU Core Frequency */
#define acmgt3__ext98__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext98 :: AVG GPU Core Frequency */
#define acmgt3__ext98__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext98 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE13 */
#define acmgt3__ext98__xve_load_store_cache_atomic_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext99 :: GPU Time Elapsed */
#define acmgt3__ext99__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext99 :: GPU Core Clocks */
#define acmgt3__ext99__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext99 :: AVG GPU Core Frequency */
#define acmgt3__ext99__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext99 :: AVG GPU Core Frequency */
#define acmgt3__ext99__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext99 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE14 */
#define acmgt3__ext99__xve_load_store_cache_atomic_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext100 :: GPU Time Elapsed */
#define acmgt3__ext100__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext100 :: GPU Core Clocks */
#define acmgt3__ext100__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext100 :: AVG GPU Core Frequency */
#define acmgt3__ext100__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext100 :: AVG GPU Core Frequency */
#define acmgt3__ext100__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext100 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE15 */
#define acmgt3__ext100__xve_load_store_cache_atomic_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext101 :: GPU Time Elapsed */
#define acmgt3__ext101__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext101 :: GPU Core Clocks */
#define acmgt3__ext101__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext101 :: AVG GPU Core Frequency */
#define acmgt3__ext101__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext101 :: AVG GPU Core Frequency */
#define acmgt3__ext101__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext101 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE16 */
#define acmgt3__ext101__xve_load_store_cache_atomic_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext102 :: GPU Time Elapsed */
#define acmgt3__ext102__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext102 :: GPU Core Clocks */
#define acmgt3__ext102__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext102 :: AVG GPU Core Frequency */
#define acmgt3__ext102__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext102 :: AVG GPU Core Frequency */
#define acmgt3__ext102__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext102 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE17 */
#define acmgt3__ext102__xve_load_store_cache_atomic_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext103 :: GPU Time Elapsed */
#define acmgt3__ext103__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext103 :: GPU Core Clocks */
#define acmgt3__ext103__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext103 :: AVG GPU Core Frequency */
#define acmgt3__ext103__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext103 :: AVG GPU Core Frequency */
#define acmgt3__ext103__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext103 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE18 */
#define acmgt3__ext103__xve_load_store_cache_atomic_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext104 :: GPU Time Elapsed */
#define acmgt3__ext104__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext104 :: GPU Core Clocks */
#define acmgt3__ext104__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext104 :: AVG GPU Core Frequency */
#define acmgt3__ext104__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext104 :: AVG GPU Core Frequency */
#define acmgt3__ext104__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext104 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE19 */
#define acmgt3__ext104__xve_load_store_cache_atomic_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext105 :: GPU Time Elapsed */
#define acmgt3__ext105__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext105 :: GPU Core Clocks */
#define acmgt3__ext105__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext105 :: AVG GPU Core Frequency */
#define acmgt3__ext105__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext105 :: AVG GPU Core Frequency */
#define acmgt3__ext105__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext105 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE20 */
#define acmgt3__ext105__xve_load_store_cache_atomic_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext106 :: GPU Time Elapsed */
#define acmgt3__ext106__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext106 :: GPU Core Clocks */
#define acmgt3__ext106__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext106 :: AVG GPU Core Frequency */
#define acmgt3__ext106__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext106 :: AVG GPU Core Frequency */
#define acmgt3__ext106__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext106 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE21 */
#define acmgt3__ext106__xve_load_store_cache_atomic_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext107 :: GPU Time Elapsed */
#define acmgt3__ext107__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext107 :: GPU Core Clocks */
#define acmgt3__ext107__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext107 :: AVG GPU Core Frequency */
#define acmgt3__ext107__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext107 :: AVG GPU Core Frequency */
#define acmgt3__ext107__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext107 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE22 */
#define acmgt3__ext107__xve_load_store_cache_atomic_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext108 :: GPU Time Elapsed */
#define acmgt3__ext108__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext108 :: GPU Core Clocks */
#define acmgt3__ext108__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext108 :: AVG GPU Core Frequency */
#define acmgt3__ext108__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext108 :: AVG GPU Core Frequency */
#define acmgt3__ext108__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext108 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE23 */
#define acmgt3__ext108__xve_load_store_cache_atomic_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext109 :: GPU Time Elapsed */
#define acmgt3__ext109__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext109 :: GPU Core Clocks */
#define acmgt3__ext109__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext109 :: AVG GPU Core Frequency */
#define acmgt3__ext109__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext109 :: AVG GPU Core Frequency */
#define acmgt3__ext109__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext109 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE24 */
#define acmgt3__ext109__xve_load_store_cache_atomic_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext110 :: GPU Time Elapsed */
#define acmgt3__ext110__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext110 :: GPU Core Clocks */
#define acmgt3__ext110__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext110 :: AVG GPU Core Frequency */
#define acmgt3__ext110__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext110 :: AVG GPU Core Frequency */
#define acmgt3__ext110__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext110 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE25 */
#define acmgt3__ext110__xve_load_store_cache_atomic_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext111 :: GPU Time Elapsed */
#define acmgt3__ext111__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext111 :: GPU Core Clocks */
#define acmgt3__ext111__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext111 :: AVG GPU Core Frequency */
#define acmgt3__ext111__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext111 :: AVG GPU Core Frequency */
#define acmgt3__ext111__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext111 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE26 */
#define acmgt3__ext111__xve_load_store_cache_atomic_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext112 :: GPU Time Elapsed */
#define acmgt3__ext112__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext112 :: GPU Core Clocks */
#define acmgt3__ext112__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext112 :: AVG GPU Core Frequency */
#define acmgt3__ext112__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext112 :: AVG GPU Core Frequency */
#define acmgt3__ext112__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext112 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE27 */
#define acmgt3__ext112__xve_load_store_cache_atomic_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext113 :: GPU Time Elapsed */
#define acmgt3__ext113__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext113 :: GPU Core Clocks */
#define acmgt3__ext113__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext113 :: AVG GPU Core Frequency */
#define acmgt3__ext113__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext113 :: AVG GPU Core Frequency */
#define acmgt3__ext113__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext113 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE28 */
#define acmgt3__ext113__xve_load_store_cache_atomic_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext114 :: GPU Time Elapsed */
#define acmgt3__ext114__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext114 :: GPU Core Clocks */
#define acmgt3__ext114__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext114 :: AVG GPU Core Frequency */
#define acmgt3__ext114__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext114 :: AVG GPU Core Frequency */
#define acmgt3__ext114__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext114 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE29 */
#define acmgt3__ext114__xve_load_store_cache_atomic_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext115 :: GPU Time Elapsed */
#define acmgt3__ext115__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext115 :: GPU Core Clocks */
#define acmgt3__ext115__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext115 :: AVG GPU Core Frequency */
#define acmgt3__ext115__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext115 :: AVG GPU Core Frequency */
#define acmgt3__ext115__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext115 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE30 */
#define acmgt3__ext115__xve_load_store_cache_atomic_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext116 :: GPU Time Elapsed */
#define acmgt3__ext116__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext116 :: GPU Core Clocks */
#define acmgt3__ext116__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext116 :: AVG GPU Core Frequency */
#define acmgt3__ext116__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext116 :: AVG GPU Core Frequency */
#define acmgt3__ext116__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext116 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE31 */
#define acmgt3__ext116__xve_load_store_cache_atomic_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext117 :: GPU Time Elapsed */
#define acmgt3__ext117__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext117 :: GPU Core Clocks */
#define acmgt3__ext117__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext117 :: AVG GPU Core Frequency */
#define acmgt3__ext117__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext117 :: AVG GPU Core Frequency */
#define acmgt3__ext117__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext117 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0 */
#define acmgt3__ext117__xve_load_store_cache_fence_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext117 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1 */
#define acmgt3__ext117__xve_load_store_cache_fence_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext118 :: GPU Time Elapsed */
#define acmgt3__ext118__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext118 :: GPU Core Clocks */
#define acmgt3__ext118__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext118 :: AVG GPU Core Frequency */
#define acmgt3__ext118__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext118 :: AVG GPU Core Frequency */
#define acmgt3__ext118__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext118 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2 */
#define acmgt3__ext118__xve_load_store_cache_fence_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext118 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3 */
#define acmgt3__ext118__xve_load_store_cache_fence_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext119 :: GPU Time Elapsed */
#define acmgt3__ext119__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext119 :: GPU Core Clocks */
#define acmgt3__ext119__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext119 :: AVG GPU Core Frequency */
#define acmgt3__ext119__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext119 :: AVG GPU Core Frequency */
#define acmgt3__ext119__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext119 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4 */
#define acmgt3__ext119__xve_load_store_cache_fence_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext119 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5 */
#define acmgt3__ext119__xve_load_store_cache_fence_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext120 :: GPU Time Elapsed */
#define acmgt3__ext120__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext120 :: GPU Core Clocks */
#define acmgt3__ext120__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext120 :: AVG GPU Core Frequency */
#define acmgt3__ext120__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext120 :: AVG GPU Core Frequency */
#define acmgt3__ext120__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext120 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6 */
#define acmgt3__ext120__xve_load_store_cache_fence_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext120 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7 */
#define acmgt3__ext120__xve_load_store_cache_fence_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext121 :: GPU Time Elapsed */
#define acmgt3__ext121__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext121 :: GPU Core Clocks */
#define acmgt3__ext121__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext121 :: AVG GPU Core Frequency */
#define acmgt3__ext121__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext121 :: AVG GPU Core Frequency */
#define acmgt3__ext121__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext121 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE8 */
#define acmgt3__ext121__xve_load_store_cache_fence_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext121 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE9 */
#define acmgt3__ext121__xve_load_store_cache_fence_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext122 :: GPU Time Elapsed */
#define acmgt3__ext122__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext122 :: GPU Core Clocks */
#define acmgt3__ext122__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext122 :: AVG GPU Core Frequency */
#define acmgt3__ext122__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext122 :: AVG GPU Core Frequency */
#define acmgt3__ext122__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext122 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE10 */
#define acmgt3__ext122__xve_load_store_cache_fence_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext122 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE11 */
#define acmgt3__ext122__xve_load_store_cache_fence_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext123 :: GPU Time Elapsed */
#define acmgt3__ext123__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext123 :: GPU Core Clocks */
#define acmgt3__ext123__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext123 :: AVG GPU Core Frequency */
#define acmgt3__ext123__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext123 :: AVG GPU Core Frequency */
#define acmgt3__ext123__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext123 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE12 */
#define acmgt3__ext123__xve_load_store_cache_fence_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext123 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE13 */
#define acmgt3__ext123__xve_load_store_cache_fence_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext124 :: GPU Time Elapsed */
#define acmgt3__ext124__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext124 :: GPU Core Clocks */
#define acmgt3__ext124__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext124 :: AVG GPU Core Frequency */
#define acmgt3__ext124__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext124 :: AVG GPU Core Frequency */
#define acmgt3__ext124__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext124 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE14 */
#define acmgt3__ext124__xve_load_store_cache_fence_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext124 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE15 */
#define acmgt3__ext124__xve_load_store_cache_fence_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext125 :: GPU Time Elapsed */
#define acmgt3__ext125__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext125 :: GPU Core Clocks */
#define acmgt3__ext125__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext125 :: AVG GPU Core Frequency */
#define acmgt3__ext125__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext125 :: AVG GPU Core Frequency */
#define acmgt3__ext125__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext125 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE16 */
#define acmgt3__ext125__xve_load_store_cache_fence_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext125 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE17 */
#define acmgt3__ext125__xve_load_store_cache_fence_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext126 :: GPU Time Elapsed */
#define acmgt3__ext126__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext126 :: GPU Core Clocks */
#define acmgt3__ext126__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext126 :: AVG GPU Core Frequency */
#define acmgt3__ext126__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext126 :: AVG GPU Core Frequency */
#define acmgt3__ext126__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext126 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE18 */
#define acmgt3__ext126__xve_load_store_cache_fence_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext126 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE19 */
#define acmgt3__ext126__xve_load_store_cache_fence_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext127 :: GPU Time Elapsed */
#define acmgt3__ext127__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext127 :: GPU Core Clocks */
#define acmgt3__ext127__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext127 :: AVG GPU Core Frequency */
#define acmgt3__ext127__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext127 :: AVG GPU Core Frequency */
#define acmgt3__ext127__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext127 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE20 */
#define acmgt3__ext127__xve_load_store_cache_fence_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext127 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE21 */
#define acmgt3__ext127__xve_load_store_cache_fence_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext128 :: GPU Time Elapsed */
#define acmgt3__ext128__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext128 :: GPU Core Clocks */
#define acmgt3__ext128__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext128 :: AVG GPU Core Frequency */
#define acmgt3__ext128__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext128 :: AVG GPU Core Frequency */
#define acmgt3__ext128__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext128 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE22 */
#define acmgt3__ext128__xve_load_store_cache_fence_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext128 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE23 */
#define acmgt3__ext128__xve_load_store_cache_fence_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext129 :: GPU Time Elapsed */
#define acmgt3__ext129__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext129 :: GPU Core Clocks */
#define acmgt3__ext129__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext129 :: AVG GPU Core Frequency */
#define acmgt3__ext129__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext129 :: AVG GPU Core Frequency */
#define acmgt3__ext129__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext129 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE24 */
#define acmgt3__ext129__xve_load_store_cache_fence_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext129 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE25 */
#define acmgt3__ext129__xve_load_store_cache_fence_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext130 :: GPU Time Elapsed */
#define acmgt3__ext130__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext130 :: GPU Core Clocks */
#define acmgt3__ext130__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext130 :: AVG GPU Core Frequency */
#define acmgt3__ext130__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext130 :: AVG GPU Core Frequency */
#define acmgt3__ext130__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext130 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE26 */
#define acmgt3__ext130__xve_load_store_cache_fence_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext130 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE27 */
#define acmgt3__ext130__xve_load_store_cache_fence_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext131 :: GPU Time Elapsed */
#define acmgt3__ext131__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext131 :: GPU Core Clocks */
#define acmgt3__ext131__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext131 :: AVG GPU Core Frequency */
#define acmgt3__ext131__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext131 :: AVG GPU Core Frequency */
#define acmgt3__ext131__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext131 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE28 */
#define acmgt3__ext131__xve_load_store_cache_fence_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext131 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE29 */
#define acmgt3__ext131__xve_load_store_cache_fence_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext132 :: GPU Time Elapsed */
#define acmgt3__ext132__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext132 :: GPU Core Clocks */
#define acmgt3__ext132__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext132 :: AVG GPU Core Frequency */
#define acmgt3__ext132__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext132 :: AVG GPU Core Frequency */
#define acmgt3__ext132__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext132 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE30 */
#define acmgt3__ext132__xve_load_store_cache_fence_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext132 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE31 */
#define acmgt3__ext132__xve_load_store_cache_fence_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext133 :: GPU Time Elapsed */
#define acmgt3__ext133__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext133 :: GPU Core Clocks */
#define acmgt3__ext133__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext133 :: AVG GPU Core Frequency */
#define acmgt3__ext133__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext133 :: AVG GPU Core Frequency */
#define acmgt3__ext133__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext133 :: XVE SLM READ MESSAGE COUNT XECORE0 */
#define acmgt3__ext133__xve_slm_read_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext133 :: XVE SLM READ MESSAGE COUNT XECORE1 */
#define acmgt3__ext133__xve_slm_read_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext134 :: GPU Time Elapsed */
#define acmgt3__ext134__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext134 :: GPU Core Clocks */
#define acmgt3__ext134__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext134 :: AVG GPU Core Frequency */
#define acmgt3__ext134__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext134 :: AVG GPU Core Frequency */
#define acmgt3__ext134__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext134 :: XVE SLM READ MESSAGE COUNT XECORE2 */
#define acmgt3__ext134__xve_slm_read_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext134 :: XVE SLM READ MESSAGE COUNT XECORE3 */
#define acmgt3__ext134__xve_slm_read_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext135 :: GPU Time Elapsed */
#define acmgt3__ext135__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext135 :: GPU Core Clocks */
#define acmgt3__ext135__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext135 :: AVG GPU Core Frequency */
#define acmgt3__ext135__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext135 :: AVG GPU Core Frequency */
#define acmgt3__ext135__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext135 :: XVE SLM READ MESSAGE COUNT XECORE4 */
#define acmgt3__ext135__xve_slm_read_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext135 :: XVE SLM READ MESSAGE COUNT XECORE5 */
#define acmgt3__ext135__xve_slm_read_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext136 :: GPU Time Elapsed */
#define acmgt3__ext136__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext136 :: GPU Core Clocks */
#define acmgt3__ext136__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext136 :: AVG GPU Core Frequency */
#define acmgt3__ext136__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext136 :: AVG GPU Core Frequency */
#define acmgt3__ext136__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext136 :: XVE SLM READ MESSAGE COUNT XECORE6 */
#define acmgt3__ext136__xve_slm_read_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext136 :: XVE SLM READ MESSAGE COUNT XECORE7 */
#define acmgt3__ext136__xve_slm_read_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext137 :: GPU Time Elapsed */
#define acmgt3__ext137__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext137 :: GPU Core Clocks */
#define acmgt3__ext137__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext137 :: AVG GPU Core Frequency */
#define acmgt3__ext137__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext137 :: AVG GPU Core Frequency */
#define acmgt3__ext137__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext137 :: XVE SLM READ MESSAGE COUNT XECORE8 */
#define acmgt3__ext137__xve_slm_read_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext137 :: XVE SLM READ MESSAGE COUNT XECORE9 */
#define acmgt3__ext137__xve_slm_read_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext138 :: GPU Time Elapsed */
#define acmgt3__ext138__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext138 :: GPU Core Clocks */
#define acmgt3__ext138__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext138 :: AVG GPU Core Frequency */
#define acmgt3__ext138__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext138 :: AVG GPU Core Frequency */
#define acmgt3__ext138__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext138 :: XVE SLM READ MESSAGE COUNT XECORE10 */
#define acmgt3__ext138__xve_slm_read_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext138 :: XVE SLM READ MESSAGE COUNT XECORE11 */
#define acmgt3__ext138__xve_slm_read_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext139 :: GPU Time Elapsed */
#define acmgt3__ext139__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext139 :: GPU Core Clocks */
#define acmgt3__ext139__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext139 :: AVG GPU Core Frequency */
#define acmgt3__ext139__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext139 :: AVG GPU Core Frequency */
#define acmgt3__ext139__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext139 :: XVE SLM READ MESSAGE COUNT XECORE12 */
#define acmgt3__ext139__xve_slm_read_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext139 :: XVE SLM READ MESSAGE COUNT XECORE13 */
#define acmgt3__ext139__xve_slm_read_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext140 :: GPU Time Elapsed */
#define acmgt3__ext140__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext140 :: GPU Core Clocks */
#define acmgt3__ext140__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext140 :: AVG GPU Core Frequency */
#define acmgt3__ext140__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext140 :: AVG GPU Core Frequency */
#define acmgt3__ext140__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext140 :: XVE SLM READ MESSAGE COUNT XECORE14 */
#define acmgt3__ext140__xve_slm_read_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext140 :: XVE SLM READ MESSAGE COUNT XECORE15 */
#define acmgt3__ext140__xve_slm_read_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext141 :: GPU Time Elapsed */
#define acmgt3__ext141__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext141 :: GPU Core Clocks */
#define acmgt3__ext141__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext141 :: AVG GPU Core Frequency */
#define acmgt3__ext141__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext141 :: AVG GPU Core Frequency */
#define acmgt3__ext141__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext141 :: XVE SLM READ MESSAGE COUNT XECORE16 */
#define acmgt3__ext141__xve_slm_read_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext141 :: XVE SLM READ MESSAGE COUNT XECORE17 */
#define acmgt3__ext141__xve_slm_read_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext142 :: GPU Time Elapsed */
#define acmgt3__ext142__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext142 :: GPU Core Clocks */
#define acmgt3__ext142__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext142 :: AVG GPU Core Frequency */
#define acmgt3__ext142__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext142 :: AVG GPU Core Frequency */
#define acmgt3__ext142__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext142 :: XVE SLM READ MESSAGE COUNT XECORE18 */
#define acmgt3__ext142__xve_slm_read_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext142 :: XVE SLM READ MESSAGE COUNT XECORE19 */
#define acmgt3__ext142__xve_slm_read_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext143 :: GPU Time Elapsed */
#define acmgt3__ext143__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext143 :: GPU Core Clocks */
#define acmgt3__ext143__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext143 :: AVG GPU Core Frequency */
#define acmgt3__ext143__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext143 :: AVG GPU Core Frequency */
#define acmgt3__ext143__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext143 :: XVE SLM READ MESSAGE COUNT XECORE20 */
#define acmgt3__ext143__xve_slm_read_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext143 :: XVE SLM READ MESSAGE COUNT XECORE21 */
#define acmgt3__ext143__xve_slm_read_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext144 :: GPU Time Elapsed */
#define acmgt3__ext144__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext144 :: GPU Core Clocks */
#define acmgt3__ext144__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext144 :: AVG GPU Core Frequency */
#define acmgt3__ext144__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext144 :: AVG GPU Core Frequency */
#define acmgt3__ext144__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext144 :: XVE SLM READ MESSAGE COUNT XECORE22 */
#define acmgt3__ext144__xve_slm_read_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext144 :: XVE SLM READ MESSAGE COUNT XECORE23 */
#define acmgt3__ext144__xve_slm_read_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext145 :: GPU Time Elapsed */
#define acmgt3__ext145__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext145 :: GPU Core Clocks */
#define acmgt3__ext145__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext145 :: AVG GPU Core Frequency */
#define acmgt3__ext145__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext145 :: AVG GPU Core Frequency */
#define acmgt3__ext145__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext145 :: XVE SLM READ MESSAGE COUNT XECORE24 */
#define acmgt3__ext145__xve_slm_read_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext145 :: XVE SLM READ MESSAGE COUNT XECORE25 */
#define acmgt3__ext145__xve_slm_read_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext146 :: GPU Time Elapsed */
#define acmgt3__ext146__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext146 :: GPU Core Clocks */
#define acmgt3__ext146__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext146 :: AVG GPU Core Frequency */
#define acmgt3__ext146__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext146 :: AVG GPU Core Frequency */
#define acmgt3__ext146__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext146 :: XVE SLM READ MESSAGE COUNT XECORE26 */
#define acmgt3__ext146__xve_slm_read_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext146 :: XVE SLM READ MESSAGE COUNT XECORE27 */
#define acmgt3__ext146__xve_slm_read_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext147 :: GPU Time Elapsed */
#define acmgt3__ext147__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext147 :: GPU Core Clocks */
#define acmgt3__ext147__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext147 :: AVG GPU Core Frequency */
#define acmgt3__ext147__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext147 :: AVG GPU Core Frequency */
#define acmgt3__ext147__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext147 :: XVE SLM READ MESSAGE COUNT XECORE28 */
#define acmgt3__ext147__xve_slm_read_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext147 :: XVE SLM READ MESSAGE COUNT XECORE29 */
#define acmgt3__ext147__xve_slm_read_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext148 :: GPU Time Elapsed */
#define acmgt3__ext148__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext148 :: GPU Core Clocks */
#define acmgt3__ext148__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext148 :: AVG GPU Core Frequency */
#define acmgt3__ext148__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext148 :: AVG GPU Core Frequency */
#define acmgt3__ext148__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext148 :: XVE SLM READ MESSAGE COUNT XECORE30 */
#define acmgt3__ext148__xve_slm_read_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext148 :: XVE SLM READ MESSAGE COUNT XECORE31 */
#define acmgt3__ext148__xve_slm_read_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext149 :: GPU Time Elapsed */
#define acmgt3__ext149__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext149 :: GPU Core Clocks */
#define acmgt3__ext149__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext149 :: AVG GPU Core Frequency */
#define acmgt3__ext149__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext149 :: AVG GPU Core Frequency */
#define acmgt3__ext149__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext149 :: XVE SLM WRITE MESSAGE COUNT XECORE0 */
#define acmgt3__ext149__xve_slm_write_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext149 :: XVE SLM WRITE MESSAGE COUNT XECORE1 */
#define acmgt3__ext149__xve_slm_write_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext150 :: GPU Time Elapsed */
#define acmgt3__ext150__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext150 :: GPU Core Clocks */
#define acmgt3__ext150__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext150 :: AVG GPU Core Frequency */
#define acmgt3__ext150__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext150 :: AVG GPU Core Frequency */
#define acmgt3__ext150__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext150 :: XVE SLM WRITE MESSAGE COUNT XECORE2 */
#define acmgt3__ext150__xve_slm_write_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext150 :: XVE SLM WRITE MESSAGE COUNT XECORE3 */
#define acmgt3__ext150__xve_slm_write_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext151 :: GPU Time Elapsed */
#define acmgt3__ext151__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext151 :: GPU Core Clocks */
#define acmgt3__ext151__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext151 :: AVG GPU Core Frequency */
#define acmgt3__ext151__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext151 :: AVG GPU Core Frequency */
#define acmgt3__ext151__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext151 :: XVE SLM WRITE MESSAGE COUNT XECORE4 */
#define acmgt3__ext151__xve_slm_write_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext151 :: XVE SLM WRITE MESSAGE COUNT XECORE5 */
#define acmgt3__ext151__xve_slm_write_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext152 :: GPU Time Elapsed */
#define acmgt3__ext152__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext152 :: GPU Core Clocks */
#define acmgt3__ext152__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext152 :: AVG GPU Core Frequency */
#define acmgt3__ext152__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext152 :: AVG GPU Core Frequency */
#define acmgt3__ext152__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext152 :: XVE SLM WRITE MESSAGE COUNT XECORE6 */
#define acmgt3__ext152__xve_slm_write_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext152 :: XVE SLM WRITE MESSAGE COUNT XECORE7 */
#define acmgt3__ext152__xve_slm_write_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext153 :: GPU Time Elapsed */
#define acmgt3__ext153__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext153 :: GPU Core Clocks */
#define acmgt3__ext153__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext153 :: AVG GPU Core Frequency */
#define acmgt3__ext153__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext153 :: AVG GPU Core Frequency */
#define acmgt3__ext153__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext153 :: XVE SLM WRITE MESSAGE COUNT XECORE8 */
#define acmgt3__ext153__xve_slm_write_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext153 :: XVE SLM WRITE MESSAGE COUNT XECORE9 */
#define acmgt3__ext153__xve_slm_write_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext154 :: GPU Time Elapsed */
#define acmgt3__ext154__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext154 :: GPU Core Clocks */
#define acmgt3__ext154__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext154 :: AVG GPU Core Frequency */
#define acmgt3__ext154__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext154 :: AVG GPU Core Frequency */
#define acmgt3__ext154__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext154 :: XVE SLM WRITE MESSAGE COUNT XECORE10 */
#define acmgt3__ext154__xve_slm_write_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext154 :: XVE SLM WRITE MESSAGE COUNT XECORE11 */
#define acmgt3__ext154__xve_slm_write_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext155 :: GPU Time Elapsed */
#define acmgt3__ext155__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext155 :: GPU Core Clocks */
#define acmgt3__ext155__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext155 :: AVG GPU Core Frequency */
#define acmgt3__ext155__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext155 :: AVG GPU Core Frequency */
#define acmgt3__ext155__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext155 :: XVE SLM WRITE MESSAGE COUNT XECORE12 */
#define acmgt3__ext155__xve_slm_write_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext155 :: XVE SLM WRITE MESSAGE COUNT XECORE13 */
#define acmgt3__ext155__xve_slm_write_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext156 :: GPU Time Elapsed */
#define acmgt3__ext156__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext156 :: GPU Core Clocks */
#define acmgt3__ext156__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext156 :: AVG GPU Core Frequency */
#define acmgt3__ext156__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext156 :: AVG GPU Core Frequency */
#define acmgt3__ext156__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext156 :: XVE SLM WRITE MESSAGE COUNT XECORE14 */
#define acmgt3__ext156__xve_slm_write_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext156 :: XVE SLM WRITE MESSAGE COUNT XECORE15 */
#define acmgt3__ext156__xve_slm_write_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext157 :: GPU Time Elapsed */
#define acmgt3__ext157__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext157 :: GPU Core Clocks */
#define acmgt3__ext157__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext157 :: AVG GPU Core Frequency */
#define acmgt3__ext157__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext157 :: AVG GPU Core Frequency */
#define acmgt3__ext157__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext157 :: XVE SLM WRITE MESSAGE COUNT XECORE16 */
#define acmgt3__ext157__xve_slm_write_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext157 :: XVE SLM WRITE MESSAGE COUNT XECORE17 */
#define acmgt3__ext157__xve_slm_write_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext158 :: GPU Time Elapsed */
#define acmgt3__ext158__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext158 :: GPU Core Clocks */
#define acmgt3__ext158__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext158 :: AVG GPU Core Frequency */
#define acmgt3__ext158__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext158 :: AVG GPU Core Frequency */
#define acmgt3__ext158__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext158 :: XVE SLM WRITE MESSAGE COUNT XECORE18 */
#define acmgt3__ext158__xve_slm_write_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext158 :: XVE SLM WRITE MESSAGE COUNT XECORE19 */
#define acmgt3__ext158__xve_slm_write_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext159 :: GPU Time Elapsed */
#define acmgt3__ext159__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext159 :: GPU Core Clocks */
#define acmgt3__ext159__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext159 :: AVG GPU Core Frequency */
#define acmgt3__ext159__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext159 :: AVG GPU Core Frequency */
#define acmgt3__ext159__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext159 :: XVE SLM WRITE MESSAGE COUNT XECORE20 */
#define acmgt3__ext159__xve_slm_write_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext159 :: XVE SLM WRITE MESSAGE COUNT XECORE21 */
#define acmgt3__ext159__xve_slm_write_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext160 :: GPU Time Elapsed */
#define acmgt3__ext160__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext160 :: GPU Core Clocks */
#define acmgt3__ext160__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext160 :: AVG GPU Core Frequency */
#define acmgt3__ext160__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext160 :: AVG GPU Core Frequency */
#define acmgt3__ext160__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext160 :: XVE SLM WRITE MESSAGE COUNT XECORE22 */
#define acmgt3__ext160__xve_slm_write_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext160 :: XVE SLM WRITE MESSAGE COUNT XECORE23 */
#define acmgt3__ext160__xve_slm_write_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext161 :: GPU Time Elapsed */
#define acmgt3__ext161__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext161 :: GPU Core Clocks */
#define acmgt3__ext161__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext161 :: AVG GPU Core Frequency */
#define acmgt3__ext161__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext161 :: AVG GPU Core Frequency */
#define acmgt3__ext161__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext161 :: XVE SLM WRITE MESSAGE COUNT XECORE24 */
#define acmgt3__ext161__xve_slm_write_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext161 :: XVE SLM WRITE MESSAGE COUNT XECORE25 */
#define acmgt3__ext161__xve_slm_write_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext162 :: GPU Time Elapsed */
#define acmgt3__ext162__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext162 :: GPU Core Clocks */
#define acmgt3__ext162__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext162 :: AVG GPU Core Frequency */
#define acmgt3__ext162__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext162 :: AVG GPU Core Frequency */
#define acmgt3__ext162__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext162 :: XVE SLM WRITE MESSAGE COUNT XECORE26 */
#define acmgt3__ext162__xve_slm_write_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext162 :: XVE SLM WRITE MESSAGE COUNT XECORE27 */
#define acmgt3__ext162__xve_slm_write_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext163 :: GPU Time Elapsed */
#define acmgt3__ext163__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext163 :: GPU Core Clocks */
#define acmgt3__ext163__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext163 :: AVG GPU Core Frequency */
#define acmgt3__ext163__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext163 :: AVG GPU Core Frequency */
#define acmgt3__ext163__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext163 :: XVE SLM WRITE MESSAGE COUNT XECORE28 */
#define acmgt3__ext163__xve_slm_write_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext163 :: XVE SLM WRITE MESSAGE COUNT XECORE29 */
#define acmgt3__ext163__xve_slm_write_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext164 :: GPU Time Elapsed */
#define acmgt3__ext164__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext164 :: GPU Core Clocks */
#define acmgt3__ext164__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext164 :: AVG GPU Core Frequency */
#define acmgt3__ext164__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext164 :: AVG GPU Core Frequency */
#define acmgt3__ext164__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext164 :: XVE SLM WRITE MESSAGE COUNT XECORE30 */
#define acmgt3__ext164__xve_slm_write_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext164 :: XVE SLM WRITE MESSAGE COUNT XECORE31 */
#define acmgt3__ext164__xve_slm_write_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext165 :: GPU Time Elapsed */
#define acmgt3__ext165__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext165 :: GPU Core Clocks */
#define acmgt3__ext165__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext165 :: AVG GPU Core Frequency */
#define acmgt3__ext165__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext165 :: AVG GPU Core Frequency */
#define acmgt3__ext165__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext165 :: XVE SLM ATOMIC MESSAGE COUNT XECORE0 */
#define acmgt3__ext165__xve_slm_atomic_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext166 :: GPU Time Elapsed */
#define acmgt3__ext166__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext166 :: GPU Core Clocks */
#define acmgt3__ext166__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext166 :: AVG GPU Core Frequency */
#define acmgt3__ext166__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext166 :: AVG GPU Core Frequency */
#define acmgt3__ext166__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext166 :: XVE SLM ATOMIC MESSAGE COUNT XECORE1 */
#define acmgt3__ext166__xve_slm_atomic_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext167 :: GPU Time Elapsed */
#define acmgt3__ext167__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext167 :: GPU Core Clocks */
#define acmgt3__ext167__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext167 :: AVG GPU Core Frequency */
#define acmgt3__ext167__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext167 :: AVG GPU Core Frequency */
#define acmgt3__ext167__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext167 :: XVE SLM ATOMIC MESSAGE COUNT XECORE2 */
#define acmgt3__ext167__xve_slm_atomic_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext168 :: GPU Time Elapsed */
#define acmgt3__ext168__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext168 :: GPU Core Clocks */
#define acmgt3__ext168__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext168 :: AVG GPU Core Frequency */
#define acmgt3__ext168__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext168 :: AVG GPU Core Frequency */
#define acmgt3__ext168__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext168 :: XVE SLM ATOMIC MESSAGE COUNT XECORE3 */
#define acmgt3__ext168__xve_slm_atomic_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext169 :: GPU Time Elapsed */
#define acmgt3__ext169__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext169 :: GPU Core Clocks */
#define acmgt3__ext169__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext169 :: AVG GPU Core Frequency */
#define acmgt3__ext169__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext169 :: AVG GPU Core Frequency */
#define acmgt3__ext169__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext169 :: XVE SLM ATOMIC MESSAGE COUNT XECORE4 */
#define acmgt3__ext169__xve_slm_atomic_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext170 :: GPU Time Elapsed */
#define acmgt3__ext170__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext170 :: GPU Core Clocks */
#define acmgt3__ext170__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext170 :: AVG GPU Core Frequency */
#define acmgt3__ext170__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext170 :: AVG GPU Core Frequency */
#define acmgt3__ext170__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext170 :: XVE SLM ATOMIC MESSAGE COUNT XECORE5 */
#define acmgt3__ext170__xve_slm_atomic_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext171 :: GPU Time Elapsed */
#define acmgt3__ext171__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext171 :: GPU Core Clocks */
#define acmgt3__ext171__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext171 :: AVG GPU Core Frequency */
#define acmgt3__ext171__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext171 :: AVG GPU Core Frequency */
#define acmgt3__ext171__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext171 :: XVE SLM ATOMIC MESSAGE COUNT XECORE6 */
#define acmgt3__ext171__xve_slm_atomic_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext172 :: GPU Time Elapsed */
#define acmgt3__ext172__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext172 :: GPU Core Clocks */
#define acmgt3__ext172__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext172 :: AVG GPU Core Frequency */
#define acmgt3__ext172__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext172 :: AVG GPU Core Frequency */
#define acmgt3__ext172__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext172 :: XVE SLM ATOMIC MESSAGE COUNT XECORE7 */
#define acmgt3__ext172__xve_slm_atomic_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext173 :: GPU Time Elapsed */
#define acmgt3__ext173__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext173 :: GPU Core Clocks */
#define acmgt3__ext173__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext173 :: AVG GPU Core Frequency */
#define acmgt3__ext173__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext173 :: AVG GPU Core Frequency */
#define acmgt3__ext173__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext173 :: XVE SLM ATOMIC MESSAGE COUNT XECORE8 */
#define acmgt3__ext173__xve_slm_atomic_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext174 :: GPU Time Elapsed */
#define acmgt3__ext174__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext174 :: GPU Core Clocks */
#define acmgt3__ext174__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext174 :: AVG GPU Core Frequency */
#define acmgt3__ext174__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext174 :: AVG GPU Core Frequency */
#define acmgt3__ext174__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext174 :: XVE SLM ATOMIC MESSAGE COUNT XECORE9 */
#define acmgt3__ext174__xve_slm_atomic_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext175 :: GPU Time Elapsed */
#define acmgt3__ext175__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext175 :: GPU Core Clocks */
#define acmgt3__ext175__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext175 :: AVG GPU Core Frequency */
#define acmgt3__ext175__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext175 :: AVG GPU Core Frequency */
#define acmgt3__ext175__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext175 :: XVE SLM ATOMIC MESSAGE COUNT XECORE10 */
#define acmgt3__ext175__xve_slm_atomic_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext176 :: GPU Time Elapsed */
#define acmgt3__ext176__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext176 :: GPU Core Clocks */
#define acmgt3__ext176__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext176 :: AVG GPU Core Frequency */
#define acmgt3__ext176__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext176 :: AVG GPU Core Frequency */
#define acmgt3__ext176__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext176 :: XVE SLM ATOMIC MESSAGE COUNT XECORE11 */
#define acmgt3__ext176__xve_slm_atomic_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext177 :: GPU Time Elapsed */
#define acmgt3__ext177__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext177 :: GPU Core Clocks */
#define acmgt3__ext177__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext177 :: AVG GPU Core Frequency */
#define acmgt3__ext177__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext177 :: AVG GPU Core Frequency */
#define acmgt3__ext177__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext177 :: XVE SLM ATOMIC MESSAGE COUNT XECORE12 */
#define acmgt3__ext177__xve_slm_atomic_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext178 :: GPU Time Elapsed */
#define acmgt3__ext178__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext178 :: GPU Core Clocks */
#define acmgt3__ext178__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext178 :: AVG GPU Core Frequency */
#define acmgt3__ext178__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext178 :: AVG GPU Core Frequency */
#define acmgt3__ext178__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext178 :: XVE SLM ATOMIC MESSAGE COUNT XECORE13 */
#define acmgt3__ext178__xve_slm_atomic_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext179 :: GPU Time Elapsed */
#define acmgt3__ext179__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext179 :: GPU Core Clocks */
#define acmgt3__ext179__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext179 :: AVG GPU Core Frequency */
#define acmgt3__ext179__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext179 :: AVG GPU Core Frequency */
#define acmgt3__ext179__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext179 :: XVE SLM ATOMIC MESSAGE COUNT XECORE14 */
#define acmgt3__ext179__xve_slm_atomic_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext180 :: GPU Time Elapsed */
#define acmgt3__ext180__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext180 :: GPU Core Clocks */
#define acmgt3__ext180__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext180 :: AVG GPU Core Frequency */
#define acmgt3__ext180__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext180 :: AVG GPU Core Frequency */
#define acmgt3__ext180__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext180 :: XVE SLM ATOMIC MESSAGE COUNT XECORE15 */
#define acmgt3__ext180__xve_slm_atomic_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext181 :: GPU Time Elapsed */
#define acmgt3__ext181__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext181 :: GPU Core Clocks */
#define acmgt3__ext181__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext181 :: AVG GPU Core Frequency */
#define acmgt3__ext181__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext181 :: AVG GPU Core Frequency */
#define acmgt3__ext181__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext181 :: XVE SLM ATOMIC MESSAGE COUNT XECORE16 */
#define acmgt3__ext181__xve_slm_atomic_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext182 :: GPU Time Elapsed */
#define acmgt3__ext182__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext182 :: GPU Core Clocks */
#define acmgt3__ext182__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext182 :: AVG GPU Core Frequency */
#define acmgt3__ext182__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext182 :: AVG GPU Core Frequency */
#define acmgt3__ext182__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext182 :: XVE SLM ATOMIC MESSAGE COUNT XECORE17 */
#define acmgt3__ext182__xve_slm_atomic_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext183 :: GPU Time Elapsed */
#define acmgt3__ext183__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext183 :: GPU Core Clocks */
#define acmgt3__ext183__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext183 :: AVG GPU Core Frequency */
#define acmgt3__ext183__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext183 :: AVG GPU Core Frequency */
#define acmgt3__ext183__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext183 :: XVE SLM ATOMIC MESSAGE COUNT XECORE18 */
#define acmgt3__ext183__xve_slm_atomic_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext184 :: GPU Time Elapsed */
#define acmgt3__ext184__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext184 :: GPU Core Clocks */
#define acmgt3__ext184__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext184 :: AVG GPU Core Frequency */
#define acmgt3__ext184__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext184 :: AVG GPU Core Frequency */
#define acmgt3__ext184__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext184 :: XVE SLM ATOMIC MESSAGE COUNT XECORE19 */
#define acmgt3__ext184__xve_slm_atomic_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext185 :: GPU Time Elapsed */
#define acmgt3__ext185__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext185 :: GPU Core Clocks */
#define acmgt3__ext185__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext185 :: AVG GPU Core Frequency */
#define acmgt3__ext185__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext185 :: AVG GPU Core Frequency */
#define acmgt3__ext185__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext185 :: XVE SLM ATOMIC MESSAGE COUNT XECORE20 */
#define acmgt3__ext185__xve_slm_atomic_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext186 :: GPU Time Elapsed */
#define acmgt3__ext186__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext186 :: GPU Core Clocks */
#define acmgt3__ext186__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext186 :: AVG GPU Core Frequency */
#define acmgt3__ext186__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext186 :: AVG GPU Core Frequency */
#define acmgt3__ext186__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext186 :: XVE SLM ATOMIC MESSAGE COUNT XECORE21 */
#define acmgt3__ext186__xve_slm_atomic_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext187 :: GPU Time Elapsed */
#define acmgt3__ext187__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext187 :: GPU Core Clocks */
#define acmgt3__ext187__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext187 :: AVG GPU Core Frequency */
#define acmgt3__ext187__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext187 :: AVG GPU Core Frequency */
#define acmgt3__ext187__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext187 :: XVE SLM ATOMIC MESSAGE COUNT XECORE22 */
#define acmgt3__ext187__xve_slm_atomic_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext188 :: GPU Time Elapsed */
#define acmgt3__ext188__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext188 :: GPU Core Clocks */
#define acmgt3__ext188__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext188 :: AVG GPU Core Frequency */
#define acmgt3__ext188__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext188 :: AVG GPU Core Frequency */
#define acmgt3__ext188__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext188 :: XVE SLM ATOMIC MESSAGE COUNT XECORE23 */
#define acmgt3__ext188__xve_slm_atomic_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext189 :: GPU Time Elapsed */
#define acmgt3__ext189__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext189 :: GPU Core Clocks */
#define acmgt3__ext189__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext189 :: AVG GPU Core Frequency */
#define acmgt3__ext189__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext189 :: AVG GPU Core Frequency */
#define acmgt3__ext189__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext189 :: XVE SLM ATOMIC MESSAGE COUNT XECORE24 */
#define acmgt3__ext189__xve_slm_atomic_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext190 :: GPU Time Elapsed */
#define acmgt3__ext190__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext190 :: GPU Core Clocks */
#define acmgt3__ext190__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext190 :: AVG GPU Core Frequency */
#define acmgt3__ext190__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext190 :: AVG GPU Core Frequency */
#define acmgt3__ext190__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext190 :: XVE SLM ATOMIC MESSAGE COUNT XECORE25 */
#define acmgt3__ext190__xve_slm_atomic_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext191 :: GPU Time Elapsed */
#define acmgt3__ext191__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext191 :: GPU Core Clocks */
#define acmgt3__ext191__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext191 :: AVG GPU Core Frequency */
#define acmgt3__ext191__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext191 :: AVG GPU Core Frequency */
#define acmgt3__ext191__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext191 :: XVE SLM ATOMIC MESSAGE COUNT XECORE26 */
#define acmgt3__ext191__xve_slm_atomic_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext192 :: GPU Time Elapsed */
#define acmgt3__ext192__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext192 :: GPU Core Clocks */
#define acmgt3__ext192__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext192 :: AVG GPU Core Frequency */
#define acmgt3__ext192__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext192 :: AVG GPU Core Frequency */
#define acmgt3__ext192__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext192 :: XVE SLM ATOMIC MESSAGE COUNT XECORE27 */
#define acmgt3__ext192__xve_slm_atomic_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext193 :: GPU Time Elapsed */
#define acmgt3__ext193__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext193 :: GPU Core Clocks */
#define acmgt3__ext193__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext193 :: AVG GPU Core Frequency */
#define acmgt3__ext193__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext193 :: AVG GPU Core Frequency */
#define acmgt3__ext193__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext193 :: XVE SLM ATOMIC MESSAGE COUNT XECORE28 */
#define acmgt3__ext193__xve_slm_atomic_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext194 :: GPU Time Elapsed */
#define acmgt3__ext194__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext194 :: GPU Core Clocks */
#define acmgt3__ext194__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext194 :: AVG GPU Core Frequency */
#define acmgt3__ext194__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext194 :: AVG GPU Core Frequency */
#define acmgt3__ext194__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext194 :: XVE SLM ATOMIC MESSAGE COUNT XECORE29 */
#define acmgt3__ext194__xve_slm_atomic_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext195 :: GPU Time Elapsed */
#define acmgt3__ext195__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext195 :: GPU Core Clocks */
#define acmgt3__ext195__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext195 :: AVG GPU Core Frequency */
#define acmgt3__ext195__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext195 :: AVG GPU Core Frequency */
#define acmgt3__ext195__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext195 :: XVE SLM ATOMIC MESSAGE COUNT XECORE30 */
#define acmgt3__ext195__xve_slm_atomic_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext196 :: GPU Time Elapsed */
#define acmgt3__ext196__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext196 :: GPU Core Clocks */
#define acmgt3__ext196__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext196 :: AVG GPU Core Frequency */
#define acmgt3__ext196__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext196 :: AVG GPU Core Frequency */
#define acmgt3__ext196__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext196 :: XVE SLM ATOMIC MESSAGE COUNT XECORE31 */
#define acmgt3__ext196__xve_slm_atomic_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext197 :: GPU Time Elapsed */
#define acmgt3__ext197__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext197 :: GPU Core Clocks */
#define acmgt3__ext197__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext197 :: AVG GPU Core Frequency */
#define acmgt3__ext197__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext197 :: AVG GPU Core Frequency */
#define acmgt3__ext197__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext197 :: XVE SLM FENCE MESSAGE COUNT XECORE0 */
#define acmgt3__ext197__xve_slm_fence_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext197 :: XVE SLM FENCE MESSAGE COUNT XECORE1 */
#define acmgt3__ext197__xve_slm_fence_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext198 :: GPU Time Elapsed */
#define acmgt3__ext198__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext198 :: GPU Core Clocks */
#define acmgt3__ext198__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext198 :: AVG GPU Core Frequency */
#define acmgt3__ext198__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext198 :: AVG GPU Core Frequency */
#define acmgt3__ext198__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext198 :: XVE SLM FENCE MESSAGE COUNT XECORE2 */
#define acmgt3__ext198__xve_slm_fence_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext198 :: XVE SLM FENCE MESSAGE COUNT XECORE3 */
#define acmgt3__ext198__xve_slm_fence_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext199 :: GPU Time Elapsed */
#define acmgt3__ext199__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext199 :: GPU Core Clocks */
#define acmgt3__ext199__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext199 :: AVG GPU Core Frequency */
#define acmgt3__ext199__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext199 :: AVG GPU Core Frequency */
#define acmgt3__ext199__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext199 :: XVE SLM FENCE MESSAGE COUNT XECORE4 */
#define acmgt3__ext199__xve_slm_fence_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext199 :: XVE SLM FENCE MESSAGE COUNT XECORE5 */
#define acmgt3__ext199__xve_slm_fence_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext200 :: GPU Time Elapsed */
#define acmgt3__ext200__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext200 :: GPU Core Clocks */
#define acmgt3__ext200__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext200 :: AVG GPU Core Frequency */
#define acmgt3__ext200__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext200 :: AVG GPU Core Frequency */
#define acmgt3__ext200__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext200 :: XVE SLM FENCE MESSAGE COUNT XECORE6 */
#define acmgt3__ext200__xve_slm_fence_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext200 :: XVE SLM FENCE MESSAGE COUNT XECORE7 */
#define acmgt3__ext200__xve_slm_fence_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext201 :: GPU Time Elapsed */
#define acmgt3__ext201__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext201 :: GPU Core Clocks */
#define acmgt3__ext201__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext201 :: AVG GPU Core Frequency */
#define acmgt3__ext201__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext201 :: AVG GPU Core Frequency */
#define acmgt3__ext201__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext201 :: XVE SLM FENCE MESSAGE COUNT XECORE8 */
#define acmgt3__ext201__xve_slm_fence_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext201 :: XVE SLM FENCE MESSAGE COUNT XECORE9 */
#define acmgt3__ext201__xve_slm_fence_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext202 :: GPU Time Elapsed */
#define acmgt3__ext202__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext202 :: GPU Core Clocks */
#define acmgt3__ext202__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext202 :: AVG GPU Core Frequency */
#define acmgt3__ext202__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext202 :: AVG GPU Core Frequency */
#define acmgt3__ext202__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext202 :: XVE SLM FENCE MESSAGE COUNT XECORE10 */
#define acmgt3__ext202__xve_slm_fence_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext202 :: XVE SLM FENCE MESSAGE COUNT XECORE11 */
#define acmgt3__ext202__xve_slm_fence_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext203 :: GPU Time Elapsed */
#define acmgt3__ext203__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext203 :: GPU Core Clocks */
#define acmgt3__ext203__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext203 :: AVG GPU Core Frequency */
#define acmgt3__ext203__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext203 :: AVG GPU Core Frequency */
#define acmgt3__ext203__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext203 :: XVE SLM FENCE MESSAGE COUNT XECORE12 */
#define acmgt3__ext203__xve_slm_fence_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext203 :: XVE SLM FENCE MESSAGE COUNT XECORE13 */
#define acmgt3__ext203__xve_slm_fence_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext204 :: GPU Time Elapsed */
#define acmgt3__ext204__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext204 :: GPU Core Clocks */
#define acmgt3__ext204__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext204 :: AVG GPU Core Frequency */
#define acmgt3__ext204__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext204 :: AVG GPU Core Frequency */
#define acmgt3__ext204__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext204 :: XVE SLM FENCE MESSAGE COUNT XECORE14 */
#define acmgt3__ext204__xve_slm_fence_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext204 :: XVE SLM FENCE MESSAGE COUNT XECORE15 */
#define acmgt3__ext204__xve_slm_fence_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext205 :: GPU Time Elapsed */
#define acmgt3__ext205__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext205 :: GPU Core Clocks */
#define acmgt3__ext205__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext205 :: AVG GPU Core Frequency */
#define acmgt3__ext205__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext205 :: AVG GPU Core Frequency */
#define acmgt3__ext205__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext205 :: XVE SLM FENCE MESSAGE COUNT XECORE16 */
#define acmgt3__ext205__xve_slm_fence_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext205 :: XVE SLM FENCE MESSAGE COUNT XECORE17 */
#define acmgt3__ext205__xve_slm_fence_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext206 :: GPU Time Elapsed */
#define acmgt3__ext206__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext206 :: GPU Core Clocks */
#define acmgt3__ext206__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext206 :: AVG GPU Core Frequency */
#define acmgt3__ext206__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext206 :: AVG GPU Core Frequency */
#define acmgt3__ext206__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext206 :: XVE SLM FENCE MESSAGE COUNT XECORE18 */
#define acmgt3__ext206__xve_slm_fence_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext206 :: XVE SLM FENCE MESSAGE COUNT XECORE19 */
#define acmgt3__ext206__xve_slm_fence_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext207 :: GPU Time Elapsed */
#define acmgt3__ext207__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext207 :: GPU Core Clocks */
#define acmgt3__ext207__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext207 :: AVG GPU Core Frequency */
#define acmgt3__ext207__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext207 :: AVG GPU Core Frequency */
#define acmgt3__ext207__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext207 :: XVE SLM FENCE MESSAGE COUNT XECORE20 */
#define acmgt3__ext207__xve_slm_fence_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext207 :: XVE SLM FENCE MESSAGE COUNT XECORE21 */
#define acmgt3__ext207__xve_slm_fence_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext208 :: GPU Time Elapsed */
#define acmgt3__ext208__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext208 :: GPU Core Clocks */
#define acmgt3__ext208__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext208 :: AVG GPU Core Frequency */
#define acmgt3__ext208__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext208 :: AVG GPU Core Frequency */
#define acmgt3__ext208__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext208 :: XVE SLM FENCE MESSAGE COUNT XECORE22 */
#define acmgt3__ext208__xve_slm_fence_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext208 :: XVE SLM FENCE MESSAGE COUNT XECORE23 */
#define acmgt3__ext208__xve_slm_fence_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext209 :: GPU Time Elapsed */
#define acmgt3__ext209__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext209 :: GPU Core Clocks */
#define acmgt3__ext209__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext209 :: AVG GPU Core Frequency */
#define acmgt3__ext209__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext209 :: AVG GPU Core Frequency */
#define acmgt3__ext209__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext209 :: XVE SLM FENCE MESSAGE COUNT XECORE24 */
#define acmgt3__ext209__xve_slm_fence_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext209 :: XVE SLM FENCE MESSAGE COUNT XECORE25 */
#define acmgt3__ext209__xve_slm_fence_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext210 :: GPU Time Elapsed */
#define acmgt3__ext210__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext210 :: GPU Core Clocks */
#define acmgt3__ext210__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext210 :: AVG GPU Core Frequency */
#define acmgt3__ext210__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext210 :: AVG GPU Core Frequency */
#define acmgt3__ext210__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext210 :: XVE SLM FENCE MESSAGE COUNT XECORE26 */
#define acmgt3__ext210__xve_slm_fence_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext210 :: XVE SLM FENCE MESSAGE COUNT XECORE27 */
#define acmgt3__ext210__xve_slm_fence_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext211 :: GPU Time Elapsed */
#define acmgt3__ext211__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext211 :: GPU Core Clocks */
#define acmgt3__ext211__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext211 :: AVG GPU Core Frequency */
#define acmgt3__ext211__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext211 :: AVG GPU Core Frequency */
#define acmgt3__ext211__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext211 :: XVE SLM FENCE MESSAGE COUNT XECORE28 */
#define acmgt3__ext211__xve_slm_fence_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext211 :: XVE SLM FENCE MESSAGE COUNT XECORE29 */
#define acmgt3__ext211__xve_slm_fence_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext212 :: GPU Time Elapsed */
#define acmgt3__ext212__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext212 :: GPU Core Clocks */
#define acmgt3__ext212__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext212 :: AVG GPU Core Frequency */
#define acmgt3__ext212__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext212 :: AVG GPU Core Frequency */
#define acmgt3__ext212__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext212 :: XVE SLM FENCE MESSAGE COUNT XECORE30 */
#define acmgt3__ext212__xve_slm_fence_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext212 :: XVE SLM FENCE MESSAGE COUNT XECORE31 */
#define acmgt3__ext212__xve_slm_fence_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext213 :: GPU Time Elapsed */
#define acmgt3__ext213__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext213 :: GPU Core Clocks */
#define acmgt3__ext213__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext213 :: AVG GPU Core Frequency */
#define acmgt3__ext213__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext213 :: AVG GPU Core Frequency */
#define acmgt3__ext213__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext213 :: LOAD STORE CACHE ACCESS XECORE0 */
#define acmgt3__ext213__load_store_cache_access_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext213 :: LOAD STORE CACHE ACCESS XECORE1 */
#define acmgt3__ext213__load_store_cache_access_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext213 :: LOAD STORE CACHE ACCESS XECORE2 */
#define acmgt3__ext213__load_store_cache_access_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext213 :: LOAD STORE CACHE ACCESS XECORE3 */
#define acmgt3__ext213__load_store_cache_access_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext214 :: GPU Time Elapsed */
#define acmgt3__ext214__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext214 :: GPU Core Clocks */
#define acmgt3__ext214__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext214 :: AVG GPU Core Frequency */
#define acmgt3__ext214__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext214 :: AVG GPU Core Frequency */
#define acmgt3__ext214__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext214 :: LOAD STORE CACHE ACCESS XECORE4 */
#define acmgt3__ext214__load_store_cache_access_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext214 :: LOAD STORE CACHE ACCESS XECORE5 */
#define acmgt3__ext214__load_store_cache_access_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext214 :: LOAD STORE CACHE ACCESS XECORE6 */
#define acmgt3__ext214__load_store_cache_access_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext214 :: LOAD STORE CACHE ACCESS XECORE7 */
#define acmgt3__ext214__load_store_cache_access_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext215 :: GPU Time Elapsed */
#define acmgt3__ext215__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext215 :: GPU Core Clocks */
#define acmgt3__ext215__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext215 :: AVG GPU Core Frequency */
#define acmgt3__ext215__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext215 :: AVG GPU Core Frequency */
#define acmgt3__ext215__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext215 :: LOAD STORE CACHE ACCESS XECORE8 */
#define acmgt3__ext215__load_store_cache_access_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext215 :: LOAD STORE CACHE ACCESS XECORE9 */
#define acmgt3__ext215__load_store_cache_access_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext215 :: LOAD STORE CACHE ACCESS XECORE10 */
#define acmgt3__ext215__load_store_cache_access_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext215 :: LOAD STORE CACHE ACCESS XECORE11 */
#define acmgt3__ext215__load_store_cache_access_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext216 :: GPU Time Elapsed */
#define acmgt3__ext216__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext216 :: GPU Core Clocks */
#define acmgt3__ext216__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext216 :: AVG GPU Core Frequency */
#define acmgt3__ext216__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext216 :: AVG GPU Core Frequency */
#define acmgt3__ext216__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext216 :: LOAD STORE CACHE ACCESS XECORE12 */
#define acmgt3__ext216__load_store_cache_access_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext216 :: LOAD STORE CACHE ACCESS XECORE13 */
#define acmgt3__ext216__load_store_cache_access_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext216 :: LOAD STORE CACHE ACCESS XECORE14 */
#define acmgt3__ext216__load_store_cache_access_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext216 :: LOAD STORE CACHE ACCESS XECORE15 */
#define acmgt3__ext216__load_store_cache_access_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext217 :: GPU Time Elapsed */
#define acmgt3__ext217__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext217 :: GPU Core Clocks */
#define acmgt3__ext217__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext217 :: AVG GPU Core Frequency */
#define acmgt3__ext217__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext217 :: AVG GPU Core Frequency */
#define acmgt3__ext217__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext217 :: LOAD STORE CACHE ACCESS XECORE16 */
#define acmgt3__ext217__load_store_cache_access_xecore16__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext217 :: LOAD STORE CACHE ACCESS XECORE17 */
#define acmgt3__ext217__load_store_cache_access_xecore17__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext217 :: LOAD STORE CACHE ACCESS XECORE18 */
#define acmgt3__ext217__load_store_cache_access_xecore18__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext217 :: LOAD STORE CACHE ACCESS XECORE19 */
#define acmgt3__ext217__load_store_cache_access_xecore19__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext218 :: GPU Time Elapsed */
#define acmgt3__ext218__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext218 :: GPU Core Clocks */
#define acmgt3__ext218__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext218 :: AVG GPU Core Frequency */
#define acmgt3__ext218__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext218 :: AVG GPU Core Frequency */
#define acmgt3__ext218__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext218 :: LOAD STORE CACHE ACCESS XECORE20 */
#define acmgt3__ext218__load_store_cache_access_xecore20__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext218 :: LOAD STORE CACHE ACCESS XECORE21 */
#define acmgt3__ext218__load_store_cache_access_xecore21__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext218 :: LOAD STORE CACHE ACCESS XECORE22 */
#define acmgt3__ext218__load_store_cache_access_xecore22__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext218 :: LOAD STORE CACHE ACCESS XECORE23 */
#define acmgt3__ext218__load_store_cache_access_xecore23__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext219 :: GPU Time Elapsed */
#define acmgt3__ext219__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext219 :: GPU Core Clocks */
#define acmgt3__ext219__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext219 :: AVG GPU Core Frequency */
#define acmgt3__ext219__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext219 :: AVG GPU Core Frequency */
#define acmgt3__ext219__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext219 :: LOAD STORE CACHE ACCESS XECORE24 */
#define acmgt3__ext219__load_store_cache_access_xecore24__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext219 :: LOAD STORE CACHE ACCESS XECORE25 */
#define acmgt3__ext219__load_store_cache_access_xecore25__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext219 :: LOAD STORE CACHE ACCESS XECORE26 */
#define acmgt3__ext219__load_store_cache_access_xecore26__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext219 :: LOAD STORE CACHE ACCESS XECORE27 */
#define acmgt3__ext219__load_store_cache_access_xecore27__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext220 :: GPU Time Elapsed */
#define acmgt3__ext220__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext220 :: GPU Core Clocks */
#define acmgt3__ext220__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext220 :: AVG GPU Core Frequency */
#define acmgt3__ext220__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext220 :: AVG GPU Core Frequency */
#define acmgt3__ext220__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext220 :: LOAD STORE CACHE ACCESS XECORE28 */
#define acmgt3__ext220__load_store_cache_access_xecore28__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext220 :: LOAD STORE CACHE ACCESS XECORE29 */
#define acmgt3__ext220__load_store_cache_access_xecore29__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext220 :: LOAD STORE CACHE ACCESS XECORE30 */
#define acmgt3__ext220__load_store_cache_access_xecore30__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext220 :: LOAD STORE CACHE ACCESS XECORE31 */
#define acmgt3__ext220__load_store_cache_access_xecore31__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext221 :: GPU Time Elapsed */
#define acmgt3__ext221__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext221 :: GPU Core Clocks */
#define acmgt3__ext221__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext221 :: AVG GPU Core Frequency */
#define acmgt3__ext221__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext221 :: AVG GPU Core Frequency */
#define acmgt3__ext221__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext221 :: LOAD STORE CACHE HIT XECORE0 */
#define acmgt3__ext221__load_store_cache_hit_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext221 :: LOAD STORE CACHE HIT XECORE1 */
#define acmgt3__ext221__load_store_cache_hit_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext222 :: GPU Time Elapsed */
#define acmgt3__ext222__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext222 :: GPU Core Clocks */
#define acmgt3__ext222__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext222 :: AVG GPU Core Frequency */
#define acmgt3__ext222__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext222 :: AVG GPU Core Frequency */
#define acmgt3__ext222__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext222 :: LOAD STORE CACHE HIT XECORE2 */
#define acmgt3__ext222__load_store_cache_hit_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext222 :: LOAD STORE CACHE HIT XECORE3 */
#define acmgt3__ext222__load_store_cache_hit_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext223 :: GPU Time Elapsed */
#define acmgt3__ext223__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext223 :: GPU Core Clocks */
#define acmgt3__ext223__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext223 :: AVG GPU Core Frequency */
#define acmgt3__ext223__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext223 :: AVG GPU Core Frequency */
#define acmgt3__ext223__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext223 :: LOAD STORE CACHE HIT XECORE4 */
#define acmgt3__ext223__load_store_cache_hit_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext223 :: LOAD STORE CACHE HIT XECORE5 */
#define acmgt3__ext223__load_store_cache_hit_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext224 :: GPU Time Elapsed */
#define acmgt3__ext224__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext224 :: GPU Core Clocks */
#define acmgt3__ext224__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext224 :: AVG GPU Core Frequency */
#define acmgt3__ext224__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext224 :: AVG GPU Core Frequency */
#define acmgt3__ext224__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext224 :: LOAD STORE CACHE HIT XECORE6 */
#define acmgt3__ext224__load_store_cache_hit_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext224 :: LOAD STORE CACHE HIT XECORE7 */
#define acmgt3__ext224__load_store_cache_hit_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext225 :: GPU Time Elapsed */
#define acmgt3__ext225__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext225 :: GPU Core Clocks */
#define acmgt3__ext225__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext225 :: AVG GPU Core Frequency */
#define acmgt3__ext225__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext225 :: AVG GPU Core Frequency */
#define acmgt3__ext225__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext225 :: LOAD STORE CACHE HIT XECORE8 */
#define acmgt3__ext225__load_store_cache_hit_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext225 :: LOAD STORE CACHE HIT XECORE9 */
#define acmgt3__ext225__load_store_cache_hit_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext226 :: GPU Time Elapsed */
#define acmgt3__ext226__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext226 :: GPU Core Clocks */
#define acmgt3__ext226__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext226 :: AVG GPU Core Frequency */
#define acmgt3__ext226__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext226 :: AVG GPU Core Frequency */
#define acmgt3__ext226__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext226 :: LOAD STORE CACHE HIT XECORE10 */
#define acmgt3__ext226__load_store_cache_hit_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext226 :: LOAD STORE CACHE HIT XECORE11 */
#define acmgt3__ext226__load_store_cache_hit_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext227 :: GPU Time Elapsed */
#define acmgt3__ext227__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext227 :: GPU Core Clocks */
#define acmgt3__ext227__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext227 :: AVG GPU Core Frequency */
#define acmgt3__ext227__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext227 :: AVG GPU Core Frequency */
#define acmgt3__ext227__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext227 :: LOAD STORE CACHE HIT XECORE12 */
#define acmgt3__ext227__load_store_cache_hit_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext227 :: LOAD STORE CACHE HIT XECORE13 */
#define acmgt3__ext227__load_store_cache_hit_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext228 :: GPU Time Elapsed */
#define acmgt3__ext228__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext228 :: GPU Core Clocks */
#define acmgt3__ext228__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext228 :: AVG GPU Core Frequency */
#define acmgt3__ext228__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext228 :: AVG GPU Core Frequency */
#define acmgt3__ext228__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext228 :: LOAD STORE CACHE HIT XECORE14 */
#define acmgt3__ext228__load_store_cache_hit_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext228 :: LOAD STORE CACHE HIT XECORE15 */
#define acmgt3__ext228__load_store_cache_hit_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext229 :: GPU Time Elapsed */
#define acmgt3__ext229__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext229 :: GPU Core Clocks */
#define acmgt3__ext229__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext229 :: AVG GPU Core Frequency */
#define acmgt3__ext229__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext229 :: AVG GPU Core Frequency */
#define acmgt3__ext229__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext229 :: LOAD STORE CACHE HIT XECORE16 */
#define acmgt3__ext229__load_store_cache_hit_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext229 :: LOAD STORE CACHE HIT XECORE17 */
#define acmgt3__ext229__load_store_cache_hit_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext230 :: GPU Time Elapsed */
#define acmgt3__ext230__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext230 :: GPU Core Clocks */
#define acmgt3__ext230__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext230 :: AVG GPU Core Frequency */
#define acmgt3__ext230__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext230 :: AVG GPU Core Frequency */
#define acmgt3__ext230__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext230 :: LOAD STORE CACHE HIT XECORE18 */
#define acmgt3__ext230__load_store_cache_hit_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext230 :: LOAD STORE CACHE HIT XECORE19 */
#define acmgt3__ext230__load_store_cache_hit_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext231 :: GPU Time Elapsed */
#define acmgt3__ext231__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext231 :: GPU Core Clocks */
#define acmgt3__ext231__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext231 :: AVG GPU Core Frequency */
#define acmgt3__ext231__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext231 :: AVG GPU Core Frequency */
#define acmgt3__ext231__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext231 :: LOAD STORE CACHE HIT XECORE20 */
#define acmgt3__ext231__load_store_cache_hit_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext231 :: LOAD STORE CACHE HIT XECORE21 */
#define acmgt3__ext231__load_store_cache_hit_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext232 :: GPU Time Elapsed */
#define acmgt3__ext232__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext232 :: GPU Core Clocks */
#define acmgt3__ext232__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext232 :: AVG GPU Core Frequency */
#define acmgt3__ext232__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext232 :: AVG GPU Core Frequency */
#define acmgt3__ext232__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext232 :: LOAD STORE CACHE HIT XECORE22 */
#define acmgt3__ext232__load_store_cache_hit_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext232 :: LOAD STORE CACHE HIT XECORE23 */
#define acmgt3__ext232__load_store_cache_hit_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext233 :: GPU Time Elapsed */
#define acmgt3__ext233__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext233 :: GPU Core Clocks */
#define acmgt3__ext233__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext233 :: AVG GPU Core Frequency */
#define acmgt3__ext233__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext233 :: AVG GPU Core Frequency */
#define acmgt3__ext233__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext233 :: LOAD STORE CACHE HIT XECORE24 */
#define acmgt3__ext233__load_store_cache_hit_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext233 :: LOAD STORE CACHE HIT XECORE25 */
#define acmgt3__ext233__load_store_cache_hit_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext234 :: GPU Time Elapsed */
#define acmgt3__ext234__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext234 :: GPU Core Clocks */
#define acmgt3__ext234__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext234 :: AVG GPU Core Frequency */
#define acmgt3__ext234__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext234 :: AVG GPU Core Frequency */
#define acmgt3__ext234__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext234 :: LOAD STORE CACHE HIT XECORE26 */
#define acmgt3__ext234__load_store_cache_hit_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext234 :: LOAD STORE CACHE HIT XECORE27 */
#define acmgt3__ext234__load_store_cache_hit_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext235 :: GPU Time Elapsed */
#define acmgt3__ext235__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext235 :: GPU Core Clocks */
#define acmgt3__ext235__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext235 :: AVG GPU Core Frequency */
#define acmgt3__ext235__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext235 :: AVG GPU Core Frequency */
#define acmgt3__ext235__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext235 :: LOAD STORE CACHE HIT XECORE28 */
#define acmgt3__ext235__load_store_cache_hit_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext235 :: LOAD STORE CACHE HIT XECORE29 */
#define acmgt3__ext235__load_store_cache_hit_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext236 :: GPU Time Elapsed */
#define acmgt3__ext236__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext236 :: GPU Core Clocks */
#define acmgt3__ext236__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext236 :: AVG GPU Core Frequency */
#define acmgt3__ext236__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext236 :: AVG GPU Core Frequency */
#define acmgt3__ext236__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext236 :: LOAD STORE CACHE HIT XECORE30 */
#define acmgt3__ext236__load_store_cache_hit_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext236 :: LOAD STORE CACHE HIT XECORE31 */
#define acmgt3__ext236__load_store_cache_hit_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext237 :: GPU Time Elapsed */
#define acmgt3__ext237__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext237 :: GPU Core Clocks */
#define acmgt3__ext237__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext237 :: AVG GPU Core Frequency */
#define acmgt3__ext237__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext237 :: AVG GPU Core Frequency */
#define acmgt3__ext237__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext237 :: LOAD STORE CACHE L3 READ XECORE0 */
#define acmgt3__ext237__load_store_cache_l3_read_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext237 :: LOAD STORE CACHE L3 READ XECORE1 */
#define acmgt3__ext237__load_store_cache_l3_read_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext237 :: LOAD STORE CACHE L3 READ XECORE2 */
#define acmgt3__ext237__load_store_cache_l3_read_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext237 :: LOAD STORE CACHE L3 READ XECORE3 */
#define acmgt3__ext237__load_store_cache_l3_read_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext237 :: LOAD STORE CACHE L3 READ XECORE4 */
#define acmgt3__ext237__load_store_cache_l3_read_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext237 :: LOAD STORE CACHE L3 READ XECORE5 */
#define acmgt3__ext237__load_store_cache_l3_read_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext237 :: LOAD STORE CACHE L3 READ XECORE6 */
#define acmgt3__ext237__load_store_cache_l3_read_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext237 :: LOAD STORE CACHE L3 READ XECORE7 */
#define acmgt3__ext237__load_store_cache_l3_read_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext238 :: GPU Time Elapsed */
#define acmgt3__ext238__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext238 :: GPU Core Clocks */
#define acmgt3__ext238__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext238 :: AVG GPU Core Frequency */
#define acmgt3__ext238__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext238 :: AVG GPU Core Frequency */
#define acmgt3__ext238__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext238 :: LOAD STORE CACHE L3 READ XECORE8 */
#define acmgt3__ext238__load_store_cache_l3_read_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext238 :: LOAD STORE CACHE L3 READ XECORE9 */
#define acmgt3__ext238__load_store_cache_l3_read_xecore9__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext238 :: LOAD STORE CACHE L3 READ XECORE10 */
#define acmgt3__ext238__load_store_cache_l3_read_xecore10__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext238 :: LOAD STORE CACHE L3 READ XECORE11 */
#define acmgt3__ext238__load_store_cache_l3_read_xecore11__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext238 :: LOAD STORE CACHE L3 READ XECORE12 */
#define acmgt3__ext238__load_store_cache_l3_read_xecore12__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext238 :: LOAD STORE CACHE L3 READ XECORE13 */
#define acmgt3__ext238__load_store_cache_l3_read_xecore13__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext238 :: LOAD STORE CACHE L3 READ XECORE14 */
#define acmgt3__ext238__load_store_cache_l3_read_xecore14__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext238 :: LOAD STORE CACHE L3 READ XECORE15 */
#define acmgt3__ext238__load_store_cache_l3_read_xecore15__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext239 :: GPU Time Elapsed */
#define acmgt3__ext239__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext239 :: GPU Core Clocks */
#define acmgt3__ext239__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext239 :: AVG GPU Core Frequency */
#define acmgt3__ext239__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext239 :: AVG GPU Core Frequency */
#define acmgt3__ext239__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext239 :: LOAD STORE CACHE L3 READ XECORE16 */
#define acmgt3__ext239__load_store_cache_l3_read_xecore16__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext239 :: LOAD STORE CACHE L3 READ XECORE17 */
#define acmgt3__ext239__load_store_cache_l3_read_xecore17__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext239 :: LOAD STORE CACHE L3 READ XECORE18 */
#define acmgt3__ext239__load_store_cache_l3_read_xecore18__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext239 :: LOAD STORE CACHE L3 READ XECORE19 */
#define acmgt3__ext239__load_store_cache_l3_read_xecore19__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext239 :: LOAD STORE CACHE L3 READ XECORE20 */
#define acmgt3__ext239__load_store_cache_l3_read_xecore20__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext239 :: LOAD STORE CACHE L3 READ XECORE21 */
#define acmgt3__ext239__load_store_cache_l3_read_xecore21__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext239 :: LOAD STORE CACHE L3 READ XECORE22 */
#define acmgt3__ext239__load_store_cache_l3_read_xecore22__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext239 :: LOAD STORE CACHE L3 READ XECORE23 */
#define acmgt3__ext239__load_store_cache_l3_read_xecore23__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext240 :: GPU Time Elapsed */
#define acmgt3__ext240__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext240 :: GPU Core Clocks */
#define acmgt3__ext240__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext240 :: AVG GPU Core Frequency */
#define acmgt3__ext240__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext240 :: AVG GPU Core Frequency */
#define acmgt3__ext240__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext240 :: LOAD STORE CACHE L3 READ XECORE24 */
#define acmgt3__ext240__load_store_cache_l3_read_xecore24__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext240 :: LOAD STORE CACHE L3 READ XECORE25 */
#define acmgt3__ext240__load_store_cache_l3_read_xecore25__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext240 :: LOAD STORE CACHE L3 READ XECORE26 */
#define acmgt3__ext240__load_store_cache_l3_read_xecore26__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext240 :: LOAD STORE CACHE L3 READ XECORE27 */
#define acmgt3__ext240__load_store_cache_l3_read_xecore27__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext240 :: LOAD STORE CACHE L3 READ XECORE28 */
#define acmgt3__ext240__load_store_cache_l3_read_xecore28__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext240 :: LOAD STORE CACHE L3 READ XECORE29 */
#define acmgt3__ext240__load_store_cache_l3_read_xecore29__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext240 :: LOAD STORE CACHE L3 READ XECORE30 */
#define acmgt3__ext240__load_store_cache_l3_read_xecore30__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext240 :: LOAD STORE CACHE L3 READ XECORE31 */
#define acmgt3__ext240__load_store_cache_l3_read_xecore31__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext241 :: GPU Time Elapsed */
#define acmgt3__ext241__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext241 :: GPU Core Clocks */
#define acmgt3__ext241__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext241 :: AVG GPU Core Frequency */
#define acmgt3__ext241__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext241 :: AVG GPU Core Frequency */
#define acmgt3__ext241__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext241 :: LOAD STORE CACHE L3 WRITE XECORE0 */
#define acmgt3__ext241__load_store_cache_l3_write_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext241 :: LOAD STORE CACHE L3 WRITE XECORE1 */
#define acmgt3__ext241__load_store_cache_l3_write_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext241 :: LOAD STORE CACHE L3 WRITE XECORE2 */
#define acmgt3__ext241__load_store_cache_l3_write_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext241 :: LOAD STORE CACHE L3 WRITE XECORE3 */
#define acmgt3__ext241__load_store_cache_l3_write_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext241 :: LOAD STORE CACHE L3 WRITE XECORE4 */
#define acmgt3__ext241__load_store_cache_l3_write_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext241 :: LOAD STORE CACHE L3 WRITE XECORE5 */
#define acmgt3__ext241__load_store_cache_l3_write_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext241 :: LOAD STORE CACHE L3 WRITE XECORE6 */
#define acmgt3__ext241__load_store_cache_l3_write_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext241 :: LOAD STORE CACHE L3 WRITE XECORE7 */
#define acmgt3__ext241__load_store_cache_l3_write_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext242 :: GPU Time Elapsed */
#define acmgt3__ext242__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext242 :: GPU Core Clocks */
#define acmgt3__ext242__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext242 :: AVG GPU Core Frequency */
#define acmgt3__ext242__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext242 :: AVG GPU Core Frequency */
#define acmgt3__ext242__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext242 :: LOAD STORE CACHE L3 WRITE XECORE8 */
#define acmgt3__ext242__load_store_cache_l3_write_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext242 :: LOAD STORE CACHE L3 WRITE XECORE9 */
#define acmgt3__ext242__load_store_cache_l3_write_xecore9__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext242 :: LOAD STORE CACHE L3 WRITE XECORE10 */
#define acmgt3__ext242__load_store_cache_l3_write_xecore10__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext242 :: LOAD STORE CACHE L3 WRITE XECORE11 */
#define acmgt3__ext242__load_store_cache_l3_write_xecore11__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext242 :: LOAD STORE CACHE L3 WRITE XECORE12 */
#define acmgt3__ext242__load_store_cache_l3_write_xecore12__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext242 :: LOAD STORE CACHE L3 WRITE XECORE13 */
#define acmgt3__ext242__load_store_cache_l3_write_xecore13__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext242 :: LOAD STORE CACHE L3 WRITE XECORE14 */
#define acmgt3__ext242__load_store_cache_l3_write_xecore14__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext242 :: LOAD STORE CACHE L3 WRITE XECORE15 */
#define acmgt3__ext242__load_store_cache_l3_write_xecore15__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext243 :: GPU Time Elapsed */
#define acmgt3__ext243__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext243 :: GPU Core Clocks */
#define acmgt3__ext243__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext243 :: AVG GPU Core Frequency */
#define acmgt3__ext243__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext243 :: AVG GPU Core Frequency */
#define acmgt3__ext243__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext243 :: LOAD STORE CACHE L3 WRITE XECORE16 */
#define acmgt3__ext243__load_store_cache_l3_write_xecore16__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext243 :: LOAD STORE CACHE L3 WRITE XECORE17 */
#define acmgt3__ext243__load_store_cache_l3_write_xecore17__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext243 :: LOAD STORE CACHE L3 WRITE XECORE18 */
#define acmgt3__ext243__load_store_cache_l3_write_xecore18__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext243 :: LOAD STORE CACHE L3 WRITE XECORE19 */
#define acmgt3__ext243__load_store_cache_l3_write_xecore19__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext243 :: LOAD STORE CACHE L3 WRITE XECORE20 */
#define acmgt3__ext243__load_store_cache_l3_write_xecore20__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext243 :: LOAD STORE CACHE L3 WRITE XECORE21 */
#define acmgt3__ext243__load_store_cache_l3_write_xecore21__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext243 :: LOAD STORE CACHE L3 WRITE XECORE22 */
#define acmgt3__ext243__load_store_cache_l3_write_xecore22__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext243 :: LOAD STORE CACHE L3 WRITE XECORE23 */
#define acmgt3__ext243__load_store_cache_l3_write_xecore23__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext244 :: GPU Time Elapsed */
#define acmgt3__ext244__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext244 :: GPU Core Clocks */
#define acmgt3__ext244__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext244 :: AVG GPU Core Frequency */
#define acmgt3__ext244__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext244 :: AVG GPU Core Frequency */
#define acmgt3__ext244__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext244 :: LOAD STORE CACHE L3 WRITE XECORE24 */
#define acmgt3__ext244__load_store_cache_l3_write_xecore24__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext244 :: LOAD STORE CACHE L3 WRITE XECORE25 */
#define acmgt3__ext244__load_store_cache_l3_write_xecore25__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext244 :: LOAD STORE CACHE L3 WRITE XECORE26 */
#define acmgt3__ext244__load_store_cache_l3_write_xecore26__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext244 :: LOAD STORE CACHE L3 WRITE XECORE27 */
#define acmgt3__ext244__load_store_cache_l3_write_xecore27__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext244 :: LOAD STORE CACHE L3 WRITE XECORE28 */
#define acmgt3__ext244__load_store_cache_l3_write_xecore28__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext244 :: LOAD STORE CACHE L3 WRITE XECORE29 */
#define acmgt3__ext244__load_store_cache_l3_write_xecore29__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext244 :: LOAD STORE CACHE L3 WRITE XECORE30 */
#define acmgt3__ext244__load_store_cache_l3_write_xecore30__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext244 :: LOAD STORE CACHE L3 WRITE XECORE31 */
#define acmgt3__ext244__load_store_cache_l3_write_xecore31__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext245 :: GPU Time Elapsed */
#define acmgt3__ext245__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext245 :: GPU Core Clocks */
#define acmgt3__ext245__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext245 :: AVG GPU Core Frequency */
#define acmgt3__ext245__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext245 :: AVG GPU Core Frequency */
#define acmgt3__ext245__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext245 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0 */
#define acmgt3__ext245__load_store_cache_partial_write_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext245 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1 */
#define acmgt3__ext245__load_store_cache_partial_write_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext245 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2 */
#define acmgt3__ext245__load_store_cache_partial_write_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext245 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3 */
#define acmgt3__ext245__load_store_cache_partial_write_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext246 :: GPU Time Elapsed */
#define acmgt3__ext246__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext246 :: GPU Core Clocks */
#define acmgt3__ext246__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext246 :: AVG GPU Core Frequency */
#define acmgt3__ext246__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext246 :: AVG GPU Core Frequency */
#define acmgt3__ext246__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext246 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4 */
#define acmgt3__ext246__load_store_cache_partial_write_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext246 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5 */
#define acmgt3__ext246__load_store_cache_partial_write_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext246 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6 */
#define acmgt3__ext246__load_store_cache_partial_write_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext246 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7 */
#define acmgt3__ext246__load_store_cache_partial_write_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext247 :: GPU Time Elapsed */
#define acmgt3__ext247__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext247 :: GPU Core Clocks */
#define acmgt3__ext247__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext247 :: AVG GPU Core Frequency */
#define acmgt3__ext247__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext247 :: AVG GPU Core Frequency */
#define acmgt3__ext247__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext247 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE8 */
#define acmgt3__ext247__load_store_cache_partial_write_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext247 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE9 */
#define acmgt3__ext247__load_store_cache_partial_write_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext247 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE10 */
#define acmgt3__ext247__load_store_cache_partial_write_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext247 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE11 */
#define acmgt3__ext247__load_store_cache_partial_write_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext248 :: GPU Time Elapsed */
#define acmgt3__ext248__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext248 :: GPU Core Clocks */
#define acmgt3__ext248__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext248 :: AVG GPU Core Frequency */
#define acmgt3__ext248__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext248 :: AVG GPU Core Frequency */
#define acmgt3__ext248__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext248 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE12 */
#define acmgt3__ext248__load_store_cache_partial_write_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext248 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE13 */
#define acmgt3__ext248__load_store_cache_partial_write_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext248 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE14 */
#define acmgt3__ext248__load_store_cache_partial_write_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext248 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE15 */
#define acmgt3__ext248__load_store_cache_partial_write_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext249 :: GPU Time Elapsed */
#define acmgt3__ext249__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext249 :: GPU Core Clocks */
#define acmgt3__ext249__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext249 :: AVG GPU Core Frequency */
#define acmgt3__ext249__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext249 :: AVG GPU Core Frequency */
#define acmgt3__ext249__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext249 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE16 */
#define acmgt3__ext249__load_store_cache_partial_write_count_xecore16__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext249 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE17 */
#define acmgt3__ext249__load_store_cache_partial_write_count_xecore17__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext249 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE18 */
#define acmgt3__ext249__load_store_cache_partial_write_count_xecore18__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext249 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE19 */
#define acmgt3__ext249__load_store_cache_partial_write_count_xecore19__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext250 :: GPU Time Elapsed */
#define acmgt3__ext250__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext250 :: GPU Core Clocks */
#define acmgt3__ext250__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext250 :: AVG GPU Core Frequency */
#define acmgt3__ext250__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext250 :: AVG GPU Core Frequency */
#define acmgt3__ext250__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext250 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE20 */
#define acmgt3__ext250__load_store_cache_partial_write_count_xecore20__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext250 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE21 */
#define acmgt3__ext250__load_store_cache_partial_write_count_xecore21__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext250 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE22 */
#define acmgt3__ext250__load_store_cache_partial_write_count_xecore22__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext250 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE23 */
#define acmgt3__ext250__load_store_cache_partial_write_count_xecore23__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext251 :: GPU Time Elapsed */
#define acmgt3__ext251__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext251 :: GPU Core Clocks */
#define acmgt3__ext251__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext251 :: AVG GPU Core Frequency */
#define acmgt3__ext251__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext251 :: AVG GPU Core Frequency */
#define acmgt3__ext251__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext251 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE24 */
#define acmgt3__ext251__load_store_cache_partial_write_count_xecore24__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext251 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE25 */
#define acmgt3__ext251__load_store_cache_partial_write_count_xecore25__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext251 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE26 */
#define acmgt3__ext251__load_store_cache_partial_write_count_xecore26__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext251 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE27 */
#define acmgt3__ext251__load_store_cache_partial_write_count_xecore27__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext252 :: GPU Time Elapsed */
#define acmgt3__ext252__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext252 :: GPU Core Clocks */
#define acmgt3__ext252__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext252 :: AVG GPU Core Frequency */
#define acmgt3__ext252__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext252 :: AVG GPU Core Frequency */
#define acmgt3__ext252__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext252 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE28 */
#define acmgt3__ext252__load_store_cache_partial_write_count_xecore28__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext252 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE29 */
#define acmgt3__ext252__load_store_cache_partial_write_count_xecore29__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext252 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE30 */
#define acmgt3__ext252__load_store_cache_partial_write_count_xecore30__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext252 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE31 */
#define acmgt3__ext252__load_store_cache_partial_write_count_xecore31__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext253 :: GPU Time Elapsed */
#define acmgt3__ext253__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext253 :: GPU Core Clocks */
#define acmgt3__ext253__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext253 :: AVG GPU Core Frequency */
#define acmgt3__ext253__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext253 :: AVG GPU Core Frequency */
#define acmgt3__ext253__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext253 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0 */
#define acmgt3__ext253__xve_load_store_cache_register_request_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext253 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1 */
#define acmgt3__ext253__xve_load_store_cache_register_request_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext253 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2 */
#define acmgt3__ext253__xve_load_store_cache_register_request_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext253 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3 */
#define acmgt3__ext253__xve_load_store_cache_register_request_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext254 :: GPU Time Elapsed */
#define acmgt3__ext254__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext254 :: GPU Core Clocks */
#define acmgt3__ext254__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext254 :: AVG GPU Core Frequency */
#define acmgt3__ext254__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext254 :: AVG GPU Core Frequency */
#define acmgt3__ext254__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext254 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4 */
#define acmgt3__ext254__xve_load_store_cache_register_request_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext254 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5 */
#define acmgt3__ext254__xve_load_store_cache_register_request_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext254 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6 */
#define acmgt3__ext254__xve_load_store_cache_register_request_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext254 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7 */
#define acmgt3__ext254__xve_load_store_cache_register_request_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext255 :: GPU Time Elapsed */
#define acmgt3__ext255__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext255 :: GPU Core Clocks */
#define acmgt3__ext255__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext255 :: AVG GPU Core Frequency */
#define acmgt3__ext255__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext255 :: AVG GPU Core Frequency */
#define acmgt3__ext255__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext255 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE8 */
#define acmgt3__ext255__xve_load_store_cache_register_request_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext255 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE9 */
#define acmgt3__ext255__xve_load_store_cache_register_request_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext255 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE10 */
#define acmgt3__ext255__xve_load_store_cache_register_request_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext255 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE11 */
#define acmgt3__ext255__xve_load_store_cache_register_request_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext256 :: GPU Time Elapsed */
#define acmgt3__ext256__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext256 :: GPU Core Clocks */
#define acmgt3__ext256__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext256 :: AVG GPU Core Frequency */
#define acmgt3__ext256__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext256 :: AVG GPU Core Frequency */
#define acmgt3__ext256__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext256 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE12 */
#define acmgt3__ext256__xve_load_store_cache_register_request_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext256 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE13 */
#define acmgt3__ext256__xve_load_store_cache_register_request_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext256 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE14 */
#define acmgt3__ext256__xve_load_store_cache_register_request_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext256 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE15 */
#define acmgt3__ext256__xve_load_store_cache_register_request_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext257 :: GPU Time Elapsed */
#define acmgt3__ext257__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext257 :: GPU Core Clocks */
#define acmgt3__ext257__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext257 :: AVG GPU Core Frequency */
#define acmgt3__ext257__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext257 :: AVG GPU Core Frequency */
#define acmgt3__ext257__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext257 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE16 */
#define acmgt3__ext257__xve_load_store_cache_register_request_count_xecore16__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext257 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE17 */
#define acmgt3__ext257__xve_load_store_cache_register_request_count_xecore17__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext257 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE18 */
#define acmgt3__ext257__xve_load_store_cache_register_request_count_xecore18__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext257 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE19 */
#define acmgt3__ext257__xve_load_store_cache_register_request_count_xecore19__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext258 :: GPU Time Elapsed */
#define acmgt3__ext258__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext258 :: GPU Core Clocks */
#define acmgt3__ext258__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext258 :: AVG GPU Core Frequency */
#define acmgt3__ext258__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext258 :: AVG GPU Core Frequency */
#define acmgt3__ext258__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext258 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE20 */
#define acmgt3__ext258__xve_load_store_cache_register_request_count_xecore20__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext258 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE21 */
#define acmgt3__ext258__xve_load_store_cache_register_request_count_xecore21__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext258 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE22 */
#define acmgt3__ext258__xve_load_store_cache_register_request_count_xecore22__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext258 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE23 */
#define acmgt3__ext258__xve_load_store_cache_register_request_count_xecore23__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext259 :: GPU Time Elapsed */
#define acmgt3__ext259__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext259 :: GPU Core Clocks */
#define acmgt3__ext259__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext259 :: AVG GPU Core Frequency */
#define acmgt3__ext259__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext259 :: AVG GPU Core Frequency */
#define acmgt3__ext259__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext259 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE24 */
#define acmgt3__ext259__xve_load_store_cache_register_request_count_xecore24__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext259 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE25 */
#define acmgt3__ext259__xve_load_store_cache_register_request_count_xecore25__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext259 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE26 */
#define acmgt3__ext259__xve_load_store_cache_register_request_count_xecore26__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext259 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE27 */
#define acmgt3__ext259__xve_load_store_cache_register_request_count_xecore27__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext260 :: GPU Time Elapsed */
#define acmgt3__ext260__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext260 :: GPU Core Clocks */
#define acmgt3__ext260__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext260 :: AVG GPU Core Frequency */
#define acmgt3__ext260__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext260 :: AVG GPU Core Frequency */
#define acmgt3__ext260__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext260 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE28 */
#define acmgt3__ext260__xve_load_store_cache_register_request_count_xecore28__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext260 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE29 */
#define acmgt3__ext260__xve_load_store_cache_register_request_count_xecore29__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext260 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE30 */
#define acmgt3__ext260__xve_load_store_cache_register_request_count_xecore30__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext260 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE31 */
#define acmgt3__ext260__xve_load_store_cache_register_request_count_xecore31__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext261 :: GPU Time Elapsed */
#define acmgt3__ext261__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext261 :: GPU Core Clocks */
#define acmgt3__ext261__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext261 :: AVG GPU Core Frequency */
#define acmgt3__ext261__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext261 :: AVG GPU Core Frequency */
#define acmgt3__ext261__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext261 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0 */
#define acmgt3__ext261__xve_load_store_cache_register_response_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext261 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1 */
#define acmgt3__ext261__xve_load_store_cache_register_response_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext261 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2 */
#define acmgt3__ext261__xve_load_store_cache_register_response_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext261 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3 */
#define acmgt3__ext261__xve_load_store_cache_register_response_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext262 :: GPU Time Elapsed */
#define acmgt3__ext262__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext262 :: GPU Core Clocks */
#define acmgt3__ext262__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext262 :: AVG GPU Core Frequency */
#define acmgt3__ext262__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext262 :: AVG GPU Core Frequency */
#define acmgt3__ext262__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext262 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4 */
#define acmgt3__ext262__xve_load_store_cache_register_response_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext262 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5 */
#define acmgt3__ext262__xve_load_store_cache_register_response_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext262 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6 */
#define acmgt3__ext262__xve_load_store_cache_register_response_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext262 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7 */
#define acmgt3__ext262__xve_load_store_cache_register_response_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext263 :: GPU Time Elapsed */
#define acmgt3__ext263__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext263 :: GPU Core Clocks */
#define acmgt3__ext263__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext263 :: AVG GPU Core Frequency */
#define acmgt3__ext263__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext263 :: AVG GPU Core Frequency */
#define acmgt3__ext263__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext263 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE8 */
#define acmgt3__ext263__xve_load_store_cache_register_response_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext263 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE9 */
#define acmgt3__ext263__xve_load_store_cache_register_response_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext263 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE10 */
#define acmgt3__ext263__xve_load_store_cache_register_response_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext263 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE11 */
#define acmgt3__ext263__xve_load_store_cache_register_response_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext264 :: GPU Time Elapsed */
#define acmgt3__ext264__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext264 :: GPU Core Clocks */
#define acmgt3__ext264__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext264 :: AVG GPU Core Frequency */
#define acmgt3__ext264__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext264 :: AVG GPU Core Frequency */
#define acmgt3__ext264__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext264 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE12 */
#define acmgt3__ext264__xve_load_store_cache_register_response_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext264 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE13 */
#define acmgt3__ext264__xve_load_store_cache_register_response_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext264 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE14 */
#define acmgt3__ext264__xve_load_store_cache_register_response_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext264 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE15 */
#define acmgt3__ext264__xve_load_store_cache_register_response_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext265 :: GPU Time Elapsed */
#define acmgt3__ext265__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext265 :: GPU Core Clocks */
#define acmgt3__ext265__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext265 :: AVG GPU Core Frequency */
#define acmgt3__ext265__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext265 :: AVG GPU Core Frequency */
#define acmgt3__ext265__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext265 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE16 */
#define acmgt3__ext265__xve_load_store_cache_register_response_count_xecore16__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext265 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE17 */
#define acmgt3__ext265__xve_load_store_cache_register_response_count_xecore17__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext265 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE18 */
#define acmgt3__ext265__xve_load_store_cache_register_response_count_xecore18__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext265 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE19 */
#define acmgt3__ext265__xve_load_store_cache_register_response_count_xecore19__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext266 :: GPU Time Elapsed */
#define acmgt3__ext266__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext266 :: GPU Core Clocks */
#define acmgt3__ext266__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext266 :: AVG GPU Core Frequency */
#define acmgt3__ext266__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext266 :: AVG GPU Core Frequency */
#define acmgt3__ext266__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext266 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE20 */
#define acmgt3__ext266__xve_load_store_cache_register_response_count_xecore20__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext266 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE21 */
#define acmgt3__ext266__xve_load_store_cache_register_response_count_xecore21__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext266 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE22 */
#define acmgt3__ext266__xve_load_store_cache_register_response_count_xecore22__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext266 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE23 */
#define acmgt3__ext266__xve_load_store_cache_register_response_count_xecore23__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext267 :: GPU Time Elapsed */
#define acmgt3__ext267__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext267 :: GPU Core Clocks */
#define acmgt3__ext267__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext267 :: AVG GPU Core Frequency */
#define acmgt3__ext267__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext267 :: AVG GPU Core Frequency */
#define acmgt3__ext267__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext267 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE24 */
#define acmgt3__ext267__xve_load_store_cache_register_response_count_xecore24__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext267 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE25 */
#define acmgt3__ext267__xve_load_store_cache_register_response_count_xecore25__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext267 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE26 */
#define acmgt3__ext267__xve_load_store_cache_register_response_count_xecore26__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext267 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE27 */
#define acmgt3__ext267__xve_load_store_cache_register_response_count_xecore27__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext268 :: GPU Time Elapsed */
#define acmgt3__ext268__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext268 :: GPU Core Clocks */
#define acmgt3__ext268__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext268 :: AVG GPU Core Frequency */
#define acmgt3__ext268__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext268 :: AVG GPU Core Frequency */
#define acmgt3__ext268__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext268 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE28 */
#define acmgt3__ext268__xve_load_store_cache_register_response_count_xecore28__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext268 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE29 */
#define acmgt3__ext268__xve_load_store_cache_register_response_count_xecore29__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext268 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE30 */
#define acmgt3__ext268__xve_load_store_cache_register_response_count_xecore30__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext268 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE31 */
#define acmgt3__ext268__xve_load_store_cache_register_response_count_xecore31__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext269 :: GPU Time Elapsed */
#define acmgt3__ext269__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext269 :: GPU Core Clocks */
#define acmgt3__ext269__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext269 :: AVG GPU Core Frequency */
#define acmgt3__ext269__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext269 :: AVG GPU Core Frequency */
#define acmgt3__ext269__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext269 :: LOAD STORE CACHE INPUT AVAILABLE XECORE0 */
#define acmgt3__ext269__load_store_cache_input_available_xecore0__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext269 :: LOAD STORE CACHE INPUT AVAILABLE XECORE1 */
#define acmgt3__ext269__load_store_cache_input_available_xecore1__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext269 :: LOAD STORE CACHE INPUT AVAILABLE XECORE2 */
#define acmgt3__ext269__load_store_cache_input_available_xecore2__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext269 :: LOAD STORE CACHE INPUT AVAILABLE XECORE3 */
#define acmgt3__ext269__load_store_cache_input_available_xecore3__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext270 :: GPU Time Elapsed */
#define acmgt3__ext270__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext270 :: GPU Core Clocks */
#define acmgt3__ext270__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext270 :: AVG GPU Core Frequency */
#define acmgt3__ext270__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext270 :: AVG GPU Core Frequency */
#define acmgt3__ext270__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext270 :: LOAD STORE CACHE INPUT AVAILABLE XECORE4 */
#define acmgt3__ext270__load_store_cache_input_available_xecore4__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext270 :: LOAD STORE CACHE INPUT AVAILABLE XECORE5 */
#define acmgt3__ext270__load_store_cache_input_available_xecore5__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext270 :: LOAD STORE CACHE INPUT AVAILABLE XECORE6 */
#define acmgt3__ext270__load_store_cache_input_available_xecore6__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext270 :: LOAD STORE CACHE INPUT AVAILABLE XECORE7 */
#define acmgt3__ext270__load_store_cache_input_available_xecore7__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext271 :: GPU Time Elapsed */
#define acmgt3__ext271__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext271 :: GPU Core Clocks */
#define acmgt3__ext271__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext271 :: AVG GPU Core Frequency */
#define acmgt3__ext271__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext271 :: AVG GPU Core Frequency */
#define acmgt3__ext271__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext271 :: LOAD STORE CACHE INPUT AVAILABLE XECORE8 */
#define acmgt3__ext271__load_store_cache_input_available_xecore8__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext271 :: LOAD STORE CACHE INPUT AVAILABLE XECORE9 */
#define acmgt3__ext271__load_store_cache_input_available_xecore9__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext271 :: LOAD STORE CACHE INPUT AVAILABLE XECORE10 */
#define acmgt3__ext271__load_store_cache_input_available_xecore10__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext271 :: LOAD STORE CACHE INPUT AVAILABLE XECORE11 */
#define acmgt3__ext271__load_store_cache_input_available_xecore11__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext272 :: GPU Time Elapsed */
#define acmgt3__ext272__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext272 :: GPU Core Clocks */
#define acmgt3__ext272__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext272 :: AVG GPU Core Frequency */
#define acmgt3__ext272__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext272 :: AVG GPU Core Frequency */
#define acmgt3__ext272__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext272 :: LOAD STORE CACHE INPUT AVAILABLE XECORE12 */
#define acmgt3__ext272__load_store_cache_input_available_xecore12__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext272 :: LOAD STORE CACHE INPUT AVAILABLE XECORE13 */
#define acmgt3__ext272__load_store_cache_input_available_xecore13__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext272 :: LOAD STORE CACHE INPUT AVAILABLE XECORE14 */
#define acmgt3__ext272__load_store_cache_input_available_xecore14__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext272 :: LOAD STORE CACHE INPUT AVAILABLE XECORE15 */
#define acmgt3__ext272__load_store_cache_input_available_xecore15__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext273 :: GPU Time Elapsed */
#define acmgt3__ext273__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext273 :: GPU Core Clocks */
#define acmgt3__ext273__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext273 :: AVG GPU Core Frequency */
#define acmgt3__ext273__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext273 :: AVG GPU Core Frequency */
#define acmgt3__ext273__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext273 :: LOAD STORE CACHE INPUT AVAILABLE XECORE16 */
#define acmgt3__ext273__load_store_cache_input_available_xecore16__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext273 :: LOAD STORE CACHE INPUT AVAILABLE XECORE17 */
#define acmgt3__ext273__load_store_cache_input_available_xecore17__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext273 :: LOAD STORE CACHE INPUT AVAILABLE XECORE18 */
#define acmgt3__ext273__load_store_cache_input_available_xecore18__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext273 :: LOAD STORE CACHE INPUT AVAILABLE XECORE19 */
#define acmgt3__ext273__load_store_cache_input_available_xecore19__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext274 :: GPU Time Elapsed */
#define acmgt3__ext274__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext274 :: GPU Core Clocks */
#define acmgt3__ext274__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext274 :: AVG GPU Core Frequency */
#define acmgt3__ext274__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext274 :: AVG GPU Core Frequency */
#define acmgt3__ext274__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext274 :: LOAD STORE CACHE INPUT AVAILABLE XECORE20 */
#define acmgt3__ext274__load_store_cache_input_available_xecore20__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext274 :: LOAD STORE CACHE INPUT AVAILABLE XECORE21 */
#define acmgt3__ext274__load_store_cache_input_available_xecore21__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext274 :: LOAD STORE CACHE INPUT AVAILABLE XECORE22 */
#define acmgt3__ext274__load_store_cache_input_available_xecore22__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext274 :: LOAD STORE CACHE INPUT AVAILABLE XECORE23 */
#define acmgt3__ext274__load_store_cache_input_available_xecore23__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext275 :: GPU Time Elapsed */
#define acmgt3__ext275__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext275 :: GPU Core Clocks */
#define acmgt3__ext275__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext275 :: AVG GPU Core Frequency */
#define acmgt3__ext275__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext275 :: AVG GPU Core Frequency */
#define acmgt3__ext275__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext275 :: LOAD STORE CACHE INPUT AVAILABLE XECORE24 */
#define acmgt3__ext275__load_store_cache_input_available_xecore24__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext275 :: LOAD STORE CACHE INPUT AVAILABLE XECORE25 */
#define acmgt3__ext275__load_store_cache_input_available_xecore25__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext275 :: LOAD STORE CACHE INPUT AVAILABLE XECORE26 */
#define acmgt3__ext275__load_store_cache_input_available_xecore26__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext275 :: LOAD STORE CACHE INPUT AVAILABLE XECORE27 */
#define acmgt3__ext275__load_store_cache_input_available_xecore27__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext276 :: GPU Time Elapsed */
#define acmgt3__ext276__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext276 :: GPU Core Clocks */
#define acmgt3__ext276__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext276 :: AVG GPU Core Frequency */
#define acmgt3__ext276__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext276 :: AVG GPU Core Frequency */
#define acmgt3__ext276__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext276 :: LOAD STORE CACHE INPUT AVAILABLE XECORE28 */
#define acmgt3__ext276__load_store_cache_input_available_xecore28__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext276 :: LOAD STORE CACHE INPUT AVAILABLE XECORE29 */
#define acmgt3__ext276__load_store_cache_input_available_xecore29__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext276 :: LOAD STORE CACHE INPUT AVAILABLE XECORE30 */
#define acmgt3__ext276__load_store_cache_input_available_xecore30__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext276 :: LOAD STORE CACHE INPUT AVAILABLE XECORE31 */
#define acmgt3__ext276__load_store_cache_input_available_xecore31__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext277 :: GPU Time Elapsed */
#define acmgt3__ext277__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext277 :: GPU Core Clocks */
#define acmgt3__ext277__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext277 :: AVG GPU Core Frequency */
#define acmgt3__ext277__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext277 :: AVG GPU Core Frequency */
#define acmgt3__ext277__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext277 :: LOAD STORE CACHE OUTPUT READY XECORE0 */
#define acmgt3__ext277__load_store_cache_output_ready_xecore0__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext277 :: LOAD STORE CACHE OUTPUT READY XECORE1 */
#define acmgt3__ext277__load_store_cache_output_ready_xecore1__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext277 :: LOAD STORE CACHE OUTPUT READY XECORE2 */
#define acmgt3__ext277__load_store_cache_output_ready_xecore2__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext277 :: LOAD STORE CACHE OUTPUT READY XECORE3 */
#define acmgt3__ext277__load_store_cache_output_ready_xecore3__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext278 :: GPU Time Elapsed */
#define acmgt3__ext278__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext278 :: GPU Core Clocks */
#define acmgt3__ext278__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext278 :: AVG GPU Core Frequency */
#define acmgt3__ext278__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext278 :: AVG GPU Core Frequency */
#define acmgt3__ext278__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext278 :: LOAD STORE CACHE OUTPUT READY XECORE4 */
#define acmgt3__ext278__load_store_cache_output_ready_xecore4__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext278 :: LOAD STORE CACHE OUTPUT READY XECORE5 */
#define acmgt3__ext278__load_store_cache_output_ready_xecore5__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext278 :: LOAD STORE CACHE OUTPUT READY XECORE6 */
#define acmgt3__ext278__load_store_cache_output_ready_xecore6__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext278 :: LOAD STORE CACHE OUTPUT READY XECORE7 */
#define acmgt3__ext278__load_store_cache_output_ready_xecore7__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext279 :: GPU Time Elapsed */
#define acmgt3__ext279__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext279 :: GPU Core Clocks */
#define acmgt3__ext279__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext279 :: AVG GPU Core Frequency */
#define acmgt3__ext279__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext279 :: AVG GPU Core Frequency */
#define acmgt3__ext279__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext279 :: LOAD STORE CACHE OUTPUT READY XECORE8 */
#define acmgt3__ext279__load_store_cache_output_ready_xecore8__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext279 :: LOAD STORE CACHE OUTPUT READY XECORE9 */
#define acmgt3__ext279__load_store_cache_output_ready_xecore9__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext279 :: LOAD STORE CACHE OUTPUT READY XECORE10 */
#define acmgt3__ext279__load_store_cache_output_ready_xecore10__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext279 :: LOAD STORE CACHE OUTPUT READY XECORE11 */
#define acmgt3__ext279__load_store_cache_output_ready_xecore11__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext280 :: GPU Time Elapsed */
#define acmgt3__ext280__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext280 :: GPU Core Clocks */
#define acmgt3__ext280__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext280 :: AVG GPU Core Frequency */
#define acmgt3__ext280__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext280 :: AVG GPU Core Frequency */
#define acmgt3__ext280__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext280 :: LOAD STORE CACHE OUTPUT READY XECORE12 */
#define acmgt3__ext280__load_store_cache_output_ready_xecore12__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext280 :: LOAD STORE CACHE OUTPUT READY XECORE13 */
#define acmgt3__ext280__load_store_cache_output_ready_xecore13__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext280 :: LOAD STORE CACHE OUTPUT READY XECORE14 */
#define acmgt3__ext280__load_store_cache_output_ready_xecore14__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext280 :: LOAD STORE CACHE OUTPUT READY XECORE15 */
#define acmgt3__ext280__load_store_cache_output_ready_xecore15__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext281 :: GPU Time Elapsed */
#define acmgt3__ext281__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext281 :: GPU Core Clocks */
#define acmgt3__ext281__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext281 :: AVG GPU Core Frequency */
#define acmgt3__ext281__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext281 :: AVG GPU Core Frequency */
#define acmgt3__ext281__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext281 :: LOAD STORE CACHE OUTPUT READY XECORE16 */
#define acmgt3__ext281__load_store_cache_output_ready_xecore16__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext281 :: LOAD STORE CACHE OUTPUT READY XECORE17 */
#define acmgt3__ext281__load_store_cache_output_ready_xecore17__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext281 :: LOAD STORE CACHE OUTPUT READY XECORE18 */
#define acmgt3__ext281__load_store_cache_output_ready_xecore18__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext281 :: LOAD STORE CACHE OUTPUT READY XECORE19 */
#define acmgt3__ext281__load_store_cache_output_ready_xecore19__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext282 :: GPU Time Elapsed */
#define acmgt3__ext282__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext282 :: GPU Core Clocks */
#define acmgt3__ext282__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext282 :: AVG GPU Core Frequency */
#define acmgt3__ext282__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext282 :: AVG GPU Core Frequency */
#define acmgt3__ext282__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext282 :: LOAD STORE CACHE OUTPUT READY XECORE20 */
#define acmgt3__ext282__load_store_cache_output_ready_xecore20__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext282 :: LOAD STORE CACHE OUTPUT READY XECORE21 */
#define acmgt3__ext282__load_store_cache_output_ready_xecore21__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext282 :: LOAD STORE CACHE OUTPUT READY XECORE22 */
#define acmgt3__ext282__load_store_cache_output_ready_xecore22__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext282 :: LOAD STORE CACHE OUTPUT READY XECORE23 */
#define acmgt3__ext282__load_store_cache_output_ready_xecore23__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext283 :: GPU Time Elapsed */
#define acmgt3__ext283__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext283 :: GPU Core Clocks */
#define acmgt3__ext283__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext283 :: AVG GPU Core Frequency */
#define acmgt3__ext283__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext283 :: AVG GPU Core Frequency */
#define acmgt3__ext283__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext283 :: LOAD STORE CACHE OUTPUT READY XECORE24 */
#define acmgt3__ext283__load_store_cache_output_ready_xecore24__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext283 :: LOAD STORE CACHE OUTPUT READY XECORE25 */
#define acmgt3__ext283__load_store_cache_output_ready_xecore25__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext283 :: LOAD STORE CACHE OUTPUT READY XECORE26 */
#define acmgt3__ext283__load_store_cache_output_ready_xecore26__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext283 :: LOAD STORE CACHE OUTPUT READY XECORE27 */
#define acmgt3__ext283__load_store_cache_output_ready_xecore27__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext284 :: GPU Time Elapsed */
#define acmgt3__ext284__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext284 :: GPU Core Clocks */
#define acmgt3__ext284__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext284 :: AVG GPU Core Frequency */
#define acmgt3__ext284__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext284 :: AVG GPU Core Frequency */
#define acmgt3__ext284__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext284 :: LOAD STORE CACHE OUTPUT READY XECORE28 */
#define acmgt3__ext284__load_store_cache_output_ready_xecore28__read \
   tglgt2__l3_1__l30_bank0_input_available__read

/* Ext284 :: LOAD STORE CACHE OUTPUT READY XECORE29 */
#define acmgt3__ext284__load_store_cache_output_ready_xecore29__read \
   tglgt2__l3_1__l30_bank1_input_available__read

/* Ext284 :: LOAD STORE CACHE OUTPUT READY XECORE30 */
#define acmgt3__ext284__load_store_cache_output_ready_xecore30__read \
   tglgt1__l3_2__l30_bank3_input_available__read

/* Ext284 :: LOAD STORE CACHE OUTPUT READY XECORE31 */
#define acmgt3__ext284__load_store_cache_output_ready_xecore31__read \
   tglgt1__l3_2__l30_bank2_input_available__read

/* Ext285 :: GPU Time Elapsed */
#define acmgt3__ext285__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext285 :: GPU Core Clocks */
#define acmgt3__ext285__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext285 :: AVG GPU Core Frequency */
#define acmgt3__ext285__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext285 :: AVG GPU Core Frequency */
#define acmgt3__ext285__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext285 :: L3 BANK STALL L3BANK30 */
#define acmgt3__ext285__l3_stall_l3_bank30__read \
   bdw__render_basic__sampler0_busy__read

/* Ext285 :: L3 BANK STALL L3BANK31 */
#define acmgt3__ext285__l3_stall_l3_bank31__read \
   bdw__render_basic__sampler1_busy__read

/* Ext286 :: GPU Time Elapsed */
#define acmgt3__ext286__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext286 :: GPU Core Clocks */
#define acmgt3__ext286__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext286 :: AVG GPU Core Frequency */
#define acmgt3__ext286__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext286 :: AVG GPU Core Frequency */
#define acmgt3__ext286__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext286 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE0 */
#define acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node0__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext286 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE1 */
#define acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node1__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext286 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE2 */
#define acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node2__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext286 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE3 */
#define acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node3__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext286 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE4 */
#define acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node4__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext286 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE5 */
#define acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node5__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext286 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE6 */
#define acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node6__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext286 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE7 */
#define acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node7__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext288 :: GPU Time Elapsed */
#define acmgt3__ext288__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext288 :: GPU Core Clocks */
#define acmgt3__ext288__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext288 :: AVG GPU Core Frequency */
#define acmgt3__ext288__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext288 :: AVG GPU Core Frequency */
#define acmgt3__ext288__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext288 :: SAMPLER OUTPUT READY XECORE0 */
#define acmgt3__ext288__sampler_output_ready_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext288 :: SAMPLER OUTPUT READY XECORE1 */
#define acmgt3__ext288__sampler_output_ready_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext288 :: SAMPLER OUTPUT READY XECORE2 */
#define acmgt3__ext288__sampler_output_ready_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext288 :: SAMPLER OUTPUT READY XECORE3 */
#define acmgt3__ext288__sampler_output_ready_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext289 :: GPU Time Elapsed */
#define acmgt3__ext289__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext289 :: GPU Core Clocks */
#define acmgt3__ext289__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext289 :: AVG GPU Core Frequency */
#define acmgt3__ext289__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext289 :: AVG GPU Core Frequency */
#define acmgt3__ext289__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext289 :: SAMPLER OUTPUT READY XECORE4 */
#define acmgt3__ext289__sampler_output_ready_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext289 :: SAMPLER OUTPUT READY XECORE5 */
#define acmgt3__ext289__sampler_output_ready_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext289 :: SAMPLER OUTPUT READY XECORE6 */
#define acmgt3__ext289__sampler_output_ready_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext289 :: SAMPLER OUTPUT READY XECORE7 */
#define acmgt3__ext289__sampler_output_ready_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext290 :: GPU Time Elapsed */
#define acmgt3__ext290__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext290 :: GPU Core Clocks */
#define acmgt3__ext290__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext290 :: AVG GPU Core Frequency */
#define acmgt3__ext290__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext290 :: AVG GPU Core Frequency */
#define acmgt3__ext290__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext290 :: SAMPLER OUTPUT READY XECORE8 */
#define acmgt3__ext290__sampler_output_ready_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext290 :: SAMPLER OUTPUT READY XECORE9 */
#define acmgt3__ext290__sampler_output_ready_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext290 :: SAMPLER OUTPUT READY XECORE10 */
#define acmgt3__ext290__sampler_output_ready_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext290 :: SAMPLER OUTPUT READY XECORE11 */
#define acmgt3__ext290__sampler_output_ready_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext291 :: GPU Time Elapsed */
#define acmgt3__ext291__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext291 :: GPU Core Clocks */
#define acmgt3__ext291__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext291 :: AVG GPU Core Frequency */
#define acmgt3__ext291__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext291 :: AVG GPU Core Frequency */
#define acmgt3__ext291__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext291 :: SAMPLER OUTPUT READY XECORE12 */
#define acmgt3__ext291__sampler_output_ready_xecore12__read \
   bdw__render_basic__sampler0_busy__read

/* Ext291 :: SAMPLER OUTPUT READY XECORE13 */
#define acmgt3__ext291__sampler_output_ready_xecore13__read \
   bdw__render_basic__sampler1_busy__read

/* Ext291 :: SAMPLER OUTPUT READY XECORE14 */
#define acmgt3__ext291__sampler_output_ready_xecore14__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext291 :: SAMPLER OUTPUT READY XECORE15 */
#define acmgt3__ext291__sampler_output_ready_xecore15__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext292 :: GPU Time Elapsed */
#define acmgt3__ext292__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext292 :: GPU Core Clocks */
#define acmgt3__ext292__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext292 :: AVG GPU Core Frequency */
#define acmgt3__ext292__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext292 :: AVG GPU Core Frequency */
#define acmgt3__ext292__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext292 :: SAMPLER OUTPUT READY XECORE16 */
#define acmgt3__ext292__sampler_output_ready_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext292 :: SAMPLER OUTPUT READY XECORE17 */
#define acmgt3__ext292__sampler_output_ready_xecore17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext292 :: SAMPLER OUTPUT READY XECORE18 */
#define acmgt3__ext292__sampler_output_ready_xecore18__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext292 :: SAMPLER OUTPUT READY XECORE19 */
#define acmgt3__ext292__sampler_output_ready_xecore19__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext293 :: GPU Time Elapsed */
#define acmgt3__ext293__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext293 :: GPU Core Clocks */
#define acmgt3__ext293__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext293 :: AVG GPU Core Frequency */
#define acmgt3__ext293__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext293 :: AVG GPU Core Frequency */
#define acmgt3__ext293__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext293 :: SAMPLER OUTPUT READY XECORE20 */
#define acmgt3__ext293__sampler_output_ready_xecore20__read \
   bdw__render_basic__sampler0_busy__read

/* Ext293 :: SAMPLER OUTPUT READY XECORE21 */
#define acmgt3__ext293__sampler_output_ready_xecore21__read \
   bdw__render_basic__sampler1_busy__read

/* Ext293 :: SAMPLER OUTPUT READY XECORE22 */
#define acmgt3__ext293__sampler_output_ready_xecore22__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext293 :: SAMPLER OUTPUT READY XECORE23 */
#define acmgt3__ext293__sampler_output_ready_xecore23__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext294 :: GPU Time Elapsed */
#define acmgt3__ext294__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext294 :: GPU Core Clocks */
#define acmgt3__ext294__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext294 :: AVG GPU Core Frequency */
#define acmgt3__ext294__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext294 :: AVG GPU Core Frequency */
#define acmgt3__ext294__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext294 :: SAMPLER OUTPUT READY XECORE24 */
#define acmgt3__ext294__sampler_output_ready_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext294 :: SAMPLER OUTPUT READY XECORE25 */
#define acmgt3__ext294__sampler_output_ready_xecore25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext294 :: SAMPLER OUTPUT READY XECORE26 */
#define acmgt3__ext294__sampler_output_ready_xecore26__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext294 :: SAMPLER OUTPUT READY XECORE27 */
#define acmgt3__ext294__sampler_output_ready_xecore27__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext295 :: GPU Time Elapsed */
#define acmgt3__ext295__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext295 :: GPU Core Clocks */
#define acmgt3__ext295__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext295 :: AVG GPU Core Frequency */
#define acmgt3__ext295__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext295 :: AVG GPU Core Frequency */
#define acmgt3__ext295__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext295 :: SAMPLER OUTPUT READY XECORE28 */
#define acmgt3__ext295__sampler_output_ready_xecore28__read \
   bdw__render_basic__sampler0_busy__read

/* Ext295 :: SAMPLER OUTPUT READY XECORE29 */
#define acmgt3__ext295__sampler_output_ready_xecore29__read \
   bdw__render_basic__sampler1_busy__read

/* Ext295 :: SAMPLER OUTPUT READY XECORE30 */
#define acmgt3__ext295__sampler_output_ready_xecore30__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext295 :: SAMPLER OUTPUT READY XECORE31 */
#define acmgt3__ext295__sampler_output_ready_xecore31__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext296 :: GPU Time Elapsed */
#define acmgt3__ext296__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext296 :: GPU Core Clocks */
#define acmgt3__ext296__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext296 :: AVG GPU Core Frequency */
#define acmgt3__ext296__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext296 :: AVG GPU Core Frequency */
#define acmgt3__ext296__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext296 :: SAMPLER BUSY XECORE0 */
#define acmgt3__ext296__sampler_busy_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext296 :: SAMPLER BUSY XECORE1 */
#define acmgt3__ext296__sampler_busy_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext296 :: SAMPLER BUSY XECORE2 */
#define acmgt3__ext296__sampler_busy_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext296 :: SAMPLER BUSY XECORE3 */
#define acmgt3__ext296__sampler_busy_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext296 :: SAMPLER BUSY XECORE4 */
#define acmgt3__ext296__sampler_busy_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext296 :: SAMPLER BUSY XECORE5 */
#define acmgt3__ext296__sampler_busy_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext296 :: SAMPLER BUSY XECORE6 */
#define acmgt3__ext296__sampler_busy_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext296 :: SAMPLER BUSY XECORE7 */
#define acmgt3__ext296__sampler_busy_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext296 :: SAMPLER BUSY XECORE8 */
#define acmgt3__ext296__sampler_busy_xecore8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext296 :: SAMPLER BUSY XECORE9 */
#define acmgt3__ext296__sampler_busy_xecore9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext296 :: SAMPLER BUSY XECORE10 */
#define acmgt3__ext296__sampler_busy_xecore10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext296 :: SAMPLER BUSY XECORE11 */
#define acmgt3__ext296__sampler_busy_xecore11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext296 :: SAMPLER BUSY XECORE12 */
#define acmgt3__ext296__sampler_busy_xecore12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext296 :: SAMPLER BUSY XECORE13 */
#define acmgt3__ext296__sampler_busy_xecore13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext296 :: SAMPLER BUSY XECORE14 */
#define acmgt3__ext296__sampler_busy_xecore14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext296 :: SAMPLER BUSY XECORE15 */
#define acmgt3__ext296__sampler_busy_xecore15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext297 :: GPU Time Elapsed */
#define acmgt3__ext297__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext297 :: GPU Core Clocks */
#define acmgt3__ext297__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext297 :: AVG GPU Core Frequency */
#define acmgt3__ext297__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext297 :: AVG GPU Core Frequency */
#define acmgt3__ext297__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext297 :: SAMPLER BUSY XECORE16 */
#define acmgt3__ext297__sampler_busy_xecore16__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext297 :: SAMPLER BUSY XECORE17 */
#define acmgt3__ext297__sampler_busy_xecore17__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext297 :: SAMPLER BUSY XECORE18 */
#define acmgt3__ext297__sampler_busy_xecore18__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext297 :: SAMPLER BUSY XECORE19 */
#define acmgt3__ext297__sampler_busy_xecore19__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext297 :: SAMPLER BUSY XECORE20 */
#define acmgt3__ext297__sampler_busy_xecore20__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext297 :: SAMPLER BUSY XECORE21 */
#define acmgt3__ext297__sampler_busy_xecore21__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext297 :: SAMPLER BUSY XECORE22 */
#define acmgt3__ext297__sampler_busy_xecore22__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext297 :: SAMPLER BUSY XECORE23 */
#define acmgt3__ext297__sampler_busy_xecore23__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext297 :: SAMPLER BUSY XECORE24 */
#define acmgt3__ext297__sampler_busy_xecore24__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext297 :: SAMPLER BUSY XECORE25 */
#define acmgt3__ext297__sampler_busy_xecore25__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext297 :: SAMPLER BUSY XECORE26 */
#define acmgt3__ext297__sampler_busy_xecore26__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext297 :: SAMPLER BUSY XECORE27 */
#define acmgt3__ext297__sampler_busy_xecore27__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext297 :: SAMPLER BUSY XECORE28 */
#define acmgt3__ext297__sampler_busy_xecore28__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext297 :: SAMPLER BUSY XECORE29 */
#define acmgt3__ext297__sampler_busy_xecore29__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext297 :: SAMPLER BUSY XECORE30 */
#define acmgt3__ext297__sampler_busy_xecore30__read \
   bdw__render_basic__sampler1_busy__read

/* Ext297 :: SAMPLER BUSY XECORE31 */
#define acmgt3__ext297__sampler_busy_xecore31__read \
   bdw__render_basic__sampler0_busy__read

/* Ext298 :: GPU Time Elapsed */
#define acmgt3__ext298__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext298 :: GPU Core Clocks */
#define acmgt3__ext298__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext298 :: AVG GPU Core Frequency */
#define acmgt3__ext298__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext298 :: AVG GPU Core Frequency */
#define acmgt3__ext298__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext298 :: SAMPLER MEMORY LATENCY STALL XECORE0 */
#define acmgt3__ext298__sampler_memory_latency_stall_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext298 :: SAMPLER MEMORY LATENCY STALL XECORE1 */
#define acmgt3__ext298__sampler_memory_latency_stall_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext298 :: SAMPLER MEMORY LATENCY STALL XECORE2 */
#define acmgt3__ext298__sampler_memory_latency_stall_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext298 :: SAMPLER MEMORY LATENCY STALL XECORE3 */
#define acmgt3__ext298__sampler_memory_latency_stall_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext298 :: SAMPLER MEMORY LATENCY STALL XECORE4 */
#define acmgt3__ext298__sampler_memory_latency_stall_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext298 :: SAMPLER MEMORY LATENCY STALL XECORE5 */
#define acmgt3__ext298__sampler_memory_latency_stall_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext298 :: SAMPLER MEMORY LATENCY STALL XECORE6 */
#define acmgt3__ext298__sampler_memory_latency_stall_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext298 :: SAMPLER MEMORY LATENCY STALL XECORE7 */
#define acmgt3__ext298__sampler_memory_latency_stall_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext299 :: GPU Time Elapsed */
#define acmgt3__ext299__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext299 :: GPU Core Clocks */
#define acmgt3__ext299__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext299 :: AVG GPU Core Frequency */
#define acmgt3__ext299__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext299 :: AVG GPU Core Frequency */
#define acmgt3__ext299__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext299 :: SAMPLER MEMORY LATENCY STALL XECORE8 */
#define acmgt3__ext299__sampler_memory_latency_stall_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext299 :: SAMPLER MEMORY LATENCY STALL XECORE9 */
#define acmgt3__ext299__sampler_memory_latency_stall_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext299 :: SAMPLER MEMORY LATENCY STALL XECORE10 */
#define acmgt3__ext299__sampler_memory_latency_stall_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext299 :: SAMPLER MEMORY LATENCY STALL XECORE11 */
#define acmgt3__ext299__sampler_memory_latency_stall_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext299 :: SAMPLER MEMORY LATENCY STALL XECORE12 */
#define acmgt3__ext299__sampler_memory_latency_stall_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext299 :: SAMPLER MEMORY LATENCY STALL XECORE13 */
#define acmgt3__ext299__sampler_memory_latency_stall_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext299 :: SAMPLER MEMORY LATENCY STALL XECORE14 */
#define acmgt3__ext299__sampler_memory_latency_stall_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext299 :: SAMPLER MEMORY LATENCY STALL XECORE15 */
#define acmgt3__ext299__sampler_memory_latency_stall_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext300 :: GPU Time Elapsed */
#define acmgt3__ext300__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext300 :: GPU Core Clocks */
#define acmgt3__ext300__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext300 :: AVG GPU Core Frequency */
#define acmgt3__ext300__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext300 :: AVG GPU Core Frequency */
#define acmgt3__ext300__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext300 :: SAMPLER MEMORY LATENCY STALL XECORE16 */
#define acmgt3__ext300__sampler_memory_latency_stall_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext300 :: SAMPLER MEMORY LATENCY STALL XECORE17 */
#define acmgt3__ext300__sampler_memory_latency_stall_xecore17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext300 :: SAMPLER MEMORY LATENCY STALL XECORE18 */
#define acmgt3__ext300__sampler_memory_latency_stall_xecore18__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext300 :: SAMPLER MEMORY LATENCY STALL XECORE19 */
#define acmgt3__ext300__sampler_memory_latency_stall_xecore19__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext300 :: SAMPLER MEMORY LATENCY STALL XECORE20 */
#define acmgt3__ext300__sampler_memory_latency_stall_xecore20__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext300 :: SAMPLER MEMORY LATENCY STALL XECORE21 */
#define acmgt3__ext300__sampler_memory_latency_stall_xecore21__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext300 :: SAMPLER MEMORY LATENCY STALL XECORE22 */
#define acmgt3__ext300__sampler_memory_latency_stall_xecore22__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext300 :: SAMPLER MEMORY LATENCY STALL XECORE23 */
#define acmgt3__ext300__sampler_memory_latency_stall_xecore23__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext301 :: GPU Time Elapsed */
#define acmgt3__ext301__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext301 :: GPU Core Clocks */
#define acmgt3__ext301__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext301 :: AVG GPU Core Frequency */
#define acmgt3__ext301__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext301 :: AVG GPU Core Frequency */
#define acmgt3__ext301__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext301 :: SAMPLER MEMORY LATENCY STALL XECORE24 */
#define acmgt3__ext301__sampler_memory_latency_stall_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext301 :: SAMPLER MEMORY LATENCY STALL XECORE25 */
#define acmgt3__ext301__sampler_memory_latency_stall_xecore25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext301 :: SAMPLER MEMORY LATENCY STALL XECORE26 */
#define acmgt3__ext301__sampler_memory_latency_stall_xecore26__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext301 :: SAMPLER MEMORY LATENCY STALL XECORE27 */
#define acmgt3__ext301__sampler_memory_latency_stall_xecore27__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext301 :: SAMPLER MEMORY LATENCY STALL XECORE28 */
#define acmgt3__ext301__sampler_memory_latency_stall_xecore28__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext301 :: SAMPLER MEMORY LATENCY STALL XECORE29 */
#define acmgt3__ext301__sampler_memory_latency_stall_xecore29__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext301 :: SAMPLER MEMORY LATENCY STALL XECORE30 */
#define acmgt3__ext301__sampler_memory_latency_stall_xecore30__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext301 :: SAMPLER MEMORY LATENCY STALL XECORE31 */
#define acmgt3__ext301__sampler_memory_latency_stall_xecore31__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext302 :: GPU Time Elapsed */
#define acmgt3__ext302__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext302 :: GPU Core Clocks */
#define acmgt3__ext302__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext302 :: AVG GPU Core Frequency */
#define acmgt3__ext302__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext302 :: AVG GPU Core Frequency */
#define acmgt3__ext302__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext302 :: SAMPLER INPUT AVAILABLE XECORE0 */
#define acmgt3__ext302__sampler_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext302 :: SAMPLER INPUT AVAILABLE XECORE1 */
#define acmgt3__ext302__sampler_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext302 :: SAMPLER INPUT AVAILABLE XECORE2 */
#define acmgt3__ext302__sampler_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext302 :: SAMPLER INPUT AVAILABLE XECORE3 */
#define acmgt3__ext302__sampler_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext302 :: SAMPLER INPUT AVAILABLE XECORE4 */
#define acmgt3__ext302__sampler_input_available_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext302 :: SAMPLER INPUT AVAILABLE XECORE5 */
#define acmgt3__ext302__sampler_input_available_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext302 :: SAMPLER INPUT AVAILABLE XECORE6 */
#define acmgt3__ext302__sampler_input_available_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext302 :: SAMPLER INPUT AVAILABLE XECORE7 */
#define acmgt3__ext302__sampler_input_available_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext303 :: GPU Time Elapsed */
#define acmgt3__ext303__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext303 :: GPU Core Clocks */
#define acmgt3__ext303__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext303 :: AVG GPU Core Frequency */
#define acmgt3__ext303__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext303 :: AVG GPU Core Frequency */
#define acmgt3__ext303__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext303 :: SAMPLER INPUT AVAILABLE XECORE8 */
#define acmgt3__ext303__sampler_input_available_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext303 :: SAMPLER INPUT AVAILABLE XECORE9 */
#define acmgt3__ext303__sampler_input_available_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext303 :: SAMPLER INPUT AVAILABLE XECORE10 */
#define acmgt3__ext303__sampler_input_available_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext303 :: SAMPLER INPUT AVAILABLE XECORE11 */
#define acmgt3__ext303__sampler_input_available_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext303 :: SAMPLER INPUT AVAILABLE XECORE12 */
#define acmgt3__ext303__sampler_input_available_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext303 :: SAMPLER INPUT AVAILABLE XECORE13 */
#define acmgt3__ext303__sampler_input_available_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext303 :: SAMPLER INPUT AVAILABLE XECORE14 */
#define acmgt3__ext303__sampler_input_available_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext303 :: SAMPLER INPUT AVAILABLE XECORE15 */
#define acmgt3__ext303__sampler_input_available_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext304 :: GPU Time Elapsed */
#define acmgt3__ext304__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext304 :: GPU Core Clocks */
#define acmgt3__ext304__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext304 :: AVG GPU Core Frequency */
#define acmgt3__ext304__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext304 :: AVG GPU Core Frequency */
#define acmgt3__ext304__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext304 :: SAMPLER INPUT AVAILABLE XECORE16 */
#define acmgt3__ext304__sampler_input_available_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext304 :: SAMPLER INPUT AVAILABLE XECORE17 */
#define acmgt3__ext304__sampler_input_available_xecore17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext304 :: SAMPLER INPUT AVAILABLE XECORE18 */
#define acmgt3__ext304__sampler_input_available_xecore18__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext304 :: SAMPLER INPUT AVAILABLE XECORE19 */
#define acmgt3__ext304__sampler_input_available_xecore19__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext304 :: SAMPLER INPUT AVAILABLE XECORE20 */
#define acmgt3__ext304__sampler_input_available_xecore20__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext304 :: SAMPLER INPUT AVAILABLE XECORE21 */
#define acmgt3__ext304__sampler_input_available_xecore21__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext304 :: SAMPLER INPUT AVAILABLE XECORE22 */
#define acmgt3__ext304__sampler_input_available_xecore22__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext304 :: SAMPLER INPUT AVAILABLE XECORE23 */
#define acmgt3__ext304__sampler_input_available_xecore23__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext305 :: GPU Time Elapsed */
#define acmgt3__ext305__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext305 :: GPU Core Clocks */
#define acmgt3__ext305__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext305 :: AVG GPU Core Frequency */
#define acmgt3__ext305__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext305 :: AVG GPU Core Frequency */
#define acmgt3__ext305__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext305 :: SAMPLER INPUT AVAILABLE XECORE24 */
#define acmgt3__ext305__sampler_input_available_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext305 :: SAMPLER INPUT AVAILABLE XECORE25 */
#define acmgt3__ext305__sampler_input_available_xecore25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext305 :: SAMPLER INPUT AVAILABLE XECORE26 */
#define acmgt3__ext305__sampler_input_available_xecore26__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext305 :: SAMPLER INPUT AVAILABLE XECORE27 */
#define acmgt3__ext305__sampler_input_available_xecore27__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext305 :: SAMPLER INPUT AVAILABLE XECORE28 */
#define acmgt3__ext305__sampler_input_available_xecore28__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext305 :: SAMPLER INPUT AVAILABLE XECORE29 */
#define acmgt3__ext305__sampler_input_available_xecore29__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext305 :: SAMPLER INPUT AVAILABLE XECORE30 */
#define acmgt3__ext305__sampler_input_available_xecore30__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext305 :: SAMPLER INPUT AVAILABLE XECORE31 */
#define acmgt3__ext305__sampler_input_available_xecore31__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext306 :: GPU Time Elapsed */
#define acmgt3__ext306__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext306 :: GPU Core Clocks */
#define acmgt3__ext306__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext306 :: AVG GPU Core Frequency */
#define acmgt3__ext306__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext306 :: AVG GPU Core Frequency */
#define acmgt3__ext306__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE0 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE1 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE2 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE3 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE4 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE5 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE6 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE7 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE8 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE9 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE10 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE11 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE12 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE13 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE14 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext306 :: SAMPLER TEXTURE CACHE ACCESS XECORE15 */
#define acmgt3__ext306__sampler_texture_cache_access_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext307 :: GPU Time Elapsed */
#define acmgt3__ext307__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext307 :: GPU Core Clocks */
#define acmgt3__ext307__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext307 :: AVG GPU Core Frequency */
#define acmgt3__ext307__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext307 :: AVG GPU Core Frequency */
#define acmgt3__ext307__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE16 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE17 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE18 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE19 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE20 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE21 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE22 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE23 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE24 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE25 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE26 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE27 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE28 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE29 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE30 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext307 :: SAMPLER TEXTURE CACHE ACCESS XECORE31 */
#define acmgt3__ext307__sampler_texture_cache_access_xecore31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext308 :: GPU Time Elapsed */
#define acmgt3__ext308__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext308 :: GPU Core Clocks */
#define acmgt3__ext308__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext308 :: AVG GPU Core Frequency */
#define acmgt3__ext308__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext308 :: AVG GPU Core Frequency */
#define acmgt3__ext308__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE0 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE1 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE2 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE3 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE4 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE5 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE6 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE7 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE8 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE9 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE10 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE11 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE12 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE13 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE14 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext308 :: SAMPLER TEXTURE CACHE MISS XECORE15 */
#define acmgt3__ext308__sampler_texture_cache_miss_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext309 :: GPU Time Elapsed */
#define acmgt3__ext309__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext309 :: GPU Core Clocks */
#define acmgt3__ext309__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext309 :: AVG GPU Core Frequency */
#define acmgt3__ext309__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext309 :: AVG GPU Core Frequency */
#define acmgt3__ext309__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE16 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE17 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE18 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE19 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE20 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE21 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE22 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE23 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE24 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE25 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE26 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE27 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE28 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE29 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE30 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext309 :: SAMPLER TEXTURE CACHE MISS XECORE31 */
#define acmgt3__ext309__sampler_texture_cache_miss_xecore31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext310 :: GPU Time Elapsed */
#define acmgt3__ext310__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext310 :: GPU Core Clocks */
#define acmgt3__ext310__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext310 :: AVG GPU Core Frequency */
#define acmgt3__ext310__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext310 :: AVG GPU Core Frequency */
#define acmgt3__ext310__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext310 :: XVE DATAPORT READ MESSAGE COUNT XECORE0 */
#define acmgt3__ext310__xve_dataport_read_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext310 :: XVE DATAPORT READ MESSAGE COUNT XECORE1 */
#define acmgt3__ext310__xve_dataport_read_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext310 :: XVE DATAPORT READ MESSAGE COUNT XECORE2 */
#define acmgt3__ext310__xve_dataport_read_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext310 :: XVE DATAPORT READ MESSAGE COUNT XECORE3 */
#define acmgt3__ext310__xve_dataport_read_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext311 :: GPU Time Elapsed */
#define acmgt3__ext311__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext311 :: GPU Core Clocks */
#define acmgt3__ext311__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext311 :: AVG GPU Core Frequency */
#define acmgt3__ext311__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext311 :: AVG GPU Core Frequency */
#define acmgt3__ext311__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext311 :: XVE DATAPORT READ MESSAGE COUNT XECORE4 */
#define acmgt3__ext311__xve_dataport_read_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext311 :: XVE DATAPORT READ MESSAGE COUNT XECORE5 */
#define acmgt3__ext311__xve_dataport_read_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext311 :: XVE DATAPORT READ MESSAGE COUNT XECORE6 */
#define acmgt3__ext311__xve_dataport_read_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext311 :: XVE DATAPORT READ MESSAGE COUNT XECORE7 */
#define acmgt3__ext311__xve_dataport_read_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext312 :: GPU Time Elapsed */
#define acmgt3__ext312__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext312 :: GPU Core Clocks */
#define acmgt3__ext312__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext312 :: AVG GPU Core Frequency */
#define acmgt3__ext312__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext312 :: AVG GPU Core Frequency */
#define acmgt3__ext312__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext312 :: XVE DATAPORT READ MESSAGE COUNT XECORE8 */
#define acmgt3__ext312__xve_dataport_read_message_count_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext312 :: XVE DATAPORT READ MESSAGE COUNT XECORE9 */
#define acmgt3__ext312__xve_dataport_read_message_count_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext312 :: XVE DATAPORT READ MESSAGE COUNT XECORE10 */
#define acmgt3__ext312__xve_dataport_read_message_count_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext312 :: XVE DATAPORT READ MESSAGE COUNT XECORE11 */
#define acmgt3__ext312__xve_dataport_read_message_count_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext313 :: GPU Time Elapsed */
#define acmgt3__ext313__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext313 :: GPU Core Clocks */
#define acmgt3__ext313__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext313 :: AVG GPU Core Frequency */
#define acmgt3__ext313__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext313 :: AVG GPU Core Frequency */
#define acmgt3__ext313__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext313 :: XVE DATAPORT READ MESSAGE COUNT XECORE12 */
#define acmgt3__ext313__xve_dataport_read_message_count_xecore12__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext313 :: XVE DATAPORT READ MESSAGE COUNT XECORE13 */
#define acmgt3__ext313__xve_dataport_read_message_count_xecore13__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext313 :: XVE DATAPORT READ MESSAGE COUNT XECORE14 */
#define acmgt3__ext313__xve_dataport_read_message_count_xecore14__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext313 :: XVE DATAPORT READ MESSAGE COUNT XECORE15 */
#define acmgt3__ext313__xve_dataport_read_message_count_xecore15__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext314 :: GPU Time Elapsed */
#define acmgt3__ext314__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext314 :: GPU Core Clocks */
#define acmgt3__ext314__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext314 :: AVG GPU Core Frequency */
#define acmgt3__ext314__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext314 :: AVG GPU Core Frequency */
#define acmgt3__ext314__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext314 :: XVE DATAPORT READ MESSAGE COUNT XECORE16 */
#define acmgt3__ext314__xve_dataport_read_message_count_xecore16__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext314 :: XVE DATAPORT READ MESSAGE COUNT XECORE17 */
#define acmgt3__ext314__xve_dataport_read_message_count_xecore17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext314 :: XVE DATAPORT READ MESSAGE COUNT XECORE18 */
#define acmgt3__ext314__xve_dataport_read_message_count_xecore18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext314 :: XVE DATAPORT READ MESSAGE COUNT XECORE19 */
#define acmgt3__ext314__xve_dataport_read_message_count_xecore19__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext315 :: GPU Time Elapsed */
#define acmgt3__ext315__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext315 :: GPU Core Clocks */
#define acmgt3__ext315__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext315 :: AVG GPU Core Frequency */
#define acmgt3__ext315__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext315 :: AVG GPU Core Frequency */
#define acmgt3__ext315__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext315 :: XVE DATAPORT READ MESSAGE COUNT XECORE20 */
#define acmgt3__ext315__xve_dataport_read_message_count_xecore20__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext315 :: XVE DATAPORT READ MESSAGE COUNT XECORE21 */
#define acmgt3__ext315__xve_dataport_read_message_count_xecore21__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext315 :: XVE DATAPORT READ MESSAGE COUNT XECORE22 */
#define acmgt3__ext315__xve_dataport_read_message_count_xecore22__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext315 :: XVE DATAPORT READ MESSAGE COUNT XECORE23 */
#define acmgt3__ext315__xve_dataport_read_message_count_xecore23__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext316 :: GPU Time Elapsed */
#define acmgt3__ext316__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext316 :: GPU Core Clocks */
#define acmgt3__ext316__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext316 :: AVG GPU Core Frequency */
#define acmgt3__ext316__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext316 :: AVG GPU Core Frequency */
#define acmgt3__ext316__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext316 :: XVE DATAPORT READ MESSAGE COUNT XECORE24 */
#define acmgt3__ext316__xve_dataport_read_message_count_xecore24__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext316 :: XVE DATAPORT READ MESSAGE COUNT XECORE25 */
#define acmgt3__ext316__xve_dataport_read_message_count_xecore25__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext316 :: XVE DATAPORT READ MESSAGE COUNT XECORE26 */
#define acmgt3__ext316__xve_dataport_read_message_count_xecore26__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext316 :: XVE DATAPORT READ MESSAGE COUNT XECORE27 */
#define acmgt3__ext316__xve_dataport_read_message_count_xecore27__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext317 :: GPU Time Elapsed */
#define acmgt3__ext317__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext317 :: GPU Core Clocks */
#define acmgt3__ext317__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext317 :: AVG GPU Core Frequency */
#define acmgt3__ext317__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext317 :: AVG GPU Core Frequency */
#define acmgt3__ext317__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext317 :: XVE DATAPORT READ MESSAGE COUNT XECORE28 */
#define acmgt3__ext317__xve_dataport_read_message_count_xecore28__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext317 :: XVE DATAPORT READ MESSAGE COUNT XECORE29 */
#define acmgt3__ext317__xve_dataport_read_message_count_xecore29__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext317 :: XVE DATAPORT READ MESSAGE COUNT XECORE30 */
#define acmgt3__ext317__xve_dataport_read_message_count_xecore30__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext317 :: XVE DATAPORT READ MESSAGE COUNT XECORE31 */
#define acmgt3__ext317__xve_dataport_read_message_count_xecore31__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext318 :: GPU Time Elapsed */
#define acmgt3__ext318__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext318 :: GPU Core Clocks */
#define acmgt3__ext318__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext318 :: AVG GPU Core Frequency */
#define acmgt3__ext318__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext318 :: AVG GPU Core Frequency */
#define acmgt3__ext318__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext318 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE0 */
#define acmgt3__ext318__xve_dataport_write_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext318 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE1 */
#define acmgt3__ext318__xve_dataport_write_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext318 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE2 */
#define acmgt3__ext318__xve_dataport_write_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext318 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE3 */
#define acmgt3__ext318__xve_dataport_write_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext319 :: GPU Time Elapsed */
#define acmgt3__ext319__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext319 :: GPU Core Clocks */
#define acmgt3__ext319__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext319 :: AVG GPU Core Frequency */
#define acmgt3__ext319__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext319 :: AVG GPU Core Frequency */
#define acmgt3__ext319__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext319 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE4 */
#define acmgt3__ext319__xve_dataport_write_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext319 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE5 */
#define acmgt3__ext319__xve_dataport_write_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext319 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE6 */
#define acmgt3__ext319__xve_dataport_write_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext319 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE7 */
#define acmgt3__ext319__xve_dataport_write_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext320 :: GPU Time Elapsed */
#define acmgt3__ext320__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext320 :: GPU Core Clocks */
#define acmgt3__ext320__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext320 :: AVG GPU Core Frequency */
#define acmgt3__ext320__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext320 :: AVG GPU Core Frequency */
#define acmgt3__ext320__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext320 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE8 */
#define acmgt3__ext320__xve_dataport_write_message_count_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext320 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE9 */
#define acmgt3__ext320__xve_dataport_write_message_count_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext320 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE10 */
#define acmgt3__ext320__xve_dataport_write_message_count_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext320 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE11 */
#define acmgt3__ext320__xve_dataport_write_message_count_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext321 :: GPU Time Elapsed */
#define acmgt3__ext321__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext321 :: GPU Core Clocks */
#define acmgt3__ext321__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext321 :: AVG GPU Core Frequency */
#define acmgt3__ext321__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext321 :: AVG GPU Core Frequency */
#define acmgt3__ext321__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext321 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE12 */
#define acmgt3__ext321__xve_dataport_write_message_count_xecore12__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext321 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE13 */
#define acmgt3__ext321__xve_dataport_write_message_count_xecore13__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext321 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE14 */
#define acmgt3__ext321__xve_dataport_write_message_count_xecore14__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext321 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE15 */
#define acmgt3__ext321__xve_dataport_write_message_count_xecore15__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext322 :: GPU Time Elapsed */
#define acmgt3__ext322__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext322 :: GPU Core Clocks */
#define acmgt3__ext322__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext322 :: AVG GPU Core Frequency */
#define acmgt3__ext322__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext322 :: AVG GPU Core Frequency */
#define acmgt3__ext322__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext322 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE16 */
#define acmgt3__ext322__xve_dataport_write_message_count_xecore16__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext322 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE17 */
#define acmgt3__ext322__xve_dataport_write_message_count_xecore17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext322 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE18 */
#define acmgt3__ext322__xve_dataport_write_message_count_xecore18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext322 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE19 */
#define acmgt3__ext322__xve_dataport_write_message_count_xecore19__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext323 :: GPU Time Elapsed */
#define acmgt3__ext323__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext323 :: GPU Core Clocks */
#define acmgt3__ext323__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext323 :: AVG GPU Core Frequency */
#define acmgt3__ext323__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext323 :: AVG GPU Core Frequency */
#define acmgt3__ext323__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext323 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE20 */
#define acmgt3__ext323__xve_dataport_write_message_count_xecore20__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext323 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE21 */
#define acmgt3__ext323__xve_dataport_write_message_count_xecore21__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext323 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE22 */
#define acmgt3__ext323__xve_dataport_write_message_count_xecore22__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext323 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE23 */
#define acmgt3__ext323__xve_dataport_write_message_count_xecore23__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext324 :: GPU Time Elapsed */
#define acmgt3__ext324__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext324 :: GPU Core Clocks */
#define acmgt3__ext324__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext324 :: AVG GPU Core Frequency */
#define acmgt3__ext324__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext324 :: AVG GPU Core Frequency */
#define acmgt3__ext324__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext324 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE24 */
#define acmgt3__ext324__xve_dataport_write_message_count_xecore24__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext324 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE25 */
#define acmgt3__ext324__xve_dataport_write_message_count_xecore25__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext324 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE26 */
#define acmgt3__ext324__xve_dataport_write_message_count_xecore26__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext324 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE27 */
#define acmgt3__ext324__xve_dataport_write_message_count_xecore27__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext325 :: GPU Time Elapsed */
#define acmgt3__ext325__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext325 :: GPU Core Clocks */
#define acmgt3__ext325__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext325 :: AVG GPU Core Frequency */
#define acmgt3__ext325__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext325 :: AVG GPU Core Frequency */
#define acmgt3__ext325__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext325 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE28 */
#define acmgt3__ext325__xve_dataport_write_message_count_xecore28__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext325 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE29 */
#define acmgt3__ext325__xve_dataport_write_message_count_xecore29__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext325 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE30 */
#define acmgt3__ext325__xve_dataport_write_message_count_xecore30__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext325 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE31 */
#define acmgt3__ext325__xve_dataport_write_message_count_xecore31__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext326 :: GPU Time Elapsed */
#define acmgt3__ext326__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext326 :: GPU Core Clocks */
#define acmgt3__ext326__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext326 :: AVG GPU Core Frequency */
#define acmgt3__ext326__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext326 :: AVG GPU Core Frequency */
#define acmgt3__ext326__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext326 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0 */
#define acmgt3__ext326__xve_dataport_atomic_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext326 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1 */
#define acmgt3__ext326__xve_dataport_atomic_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext326 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2 */
#define acmgt3__ext326__xve_dataport_atomic_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext326 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3 */
#define acmgt3__ext326__xve_dataport_atomic_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext327 :: GPU Time Elapsed */
#define acmgt3__ext327__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext327 :: GPU Core Clocks */
#define acmgt3__ext327__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext327 :: AVG GPU Core Frequency */
#define acmgt3__ext327__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext327 :: AVG GPU Core Frequency */
#define acmgt3__ext327__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext327 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4 */
#define acmgt3__ext327__xve_dataport_atomic_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext327 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5 */
#define acmgt3__ext327__xve_dataport_atomic_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext327 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6 */
#define acmgt3__ext327__xve_dataport_atomic_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext327 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7 */
#define acmgt3__ext327__xve_dataport_atomic_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext328 :: GPU Time Elapsed */
#define acmgt3__ext328__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext328 :: GPU Core Clocks */
#define acmgt3__ext328__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext328 :: AVG GPU Core Frequency */
#define acmgt3__ext328__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext328 :: AVG GPU Core Frequency */
#define acmgt3__ext328__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext328 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE8 */
#define acmgt3__ext328__xve_dataport_atomic_message_count_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext328 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE9 */
#define acmgt3__ext328__xve_dataport_atomic_message_count_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext328 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE10 */
#define acmgt3__ext328__xve_dataport_atomic_message_count_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext328 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE11 */
#define acmgt3__ext328__xve_dataport_atomic_message_count_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext329 :: GPU Time Elapsed */
#define acmgt3__ext329__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext329 :: GPU Core Clocks */
#define acmgt3__ext329__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext329 :: AVG GPU Core Frequency */
#define acmgt3__ext329__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext329 :: AVG GPU Core Frequency */
#define acmgt3__ext329__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext329 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE12 */
#define acmgt3__ext329__xve_dataport_atomic_message_count_xecore12__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext329 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE13 */
#define acmgt3__ext329__xve_dataport_atomic_message_count_xecore13__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext329 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE14 */
#define acmgt3__ext329__xve_dataport_atomic_message_count_xecore14__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext329 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE15 */
#define acmgt3__ext329__xve_dataport_atomic_message_count_xecore15__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext330 :: GPU Time Elapsed */
#define acmgt3__ext330__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext330 :: GPU Core Clocks */
#define acmgt3__ext330__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext330 :: AVG GPU Core Frequency */
#define acmgt3__ext330__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext330 :: AVG GPU Core Frequency */
#define acmgt3__ext330__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext330 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE16 */
#define acmgt3__ext330__xve_dataport_atomic_message_count_xecore16__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext330 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE17 */
#define acmgt3__ext330__xve_dataport_atomic_message_count_xecore17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext330 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE18 */
#define acmgt3__ext330__xve_dataport_atomic_message_count_xecore18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext330 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE19 */
#define acmgt3__ext330__xve_dataport_atomic_message_count_xecore19__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext331 :: GPU Time Elapsed */
#define acmgt3__ext331__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext331 :: GPU Core Clocks */
#define acmgt3__ext331__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext331 :: AVG GPU Core Frequency */
#define acmgt3__ext331__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext331 :: AVG GPU Core Frequency */
#define acmgt3__ext331__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext331 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE20 */
#define acmgt3__ext331__xve_dataport_atomic_message_count_xecore20__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext331 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE21 */
#define acmgt3__ext331__xve_dataport_atomic_message_count_xecore21__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext331 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE22 */
#define acmgt3__ext331__xve_dataport_atomic_message_count_xecore22__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext331 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE23 */
#define acmgt3__ext331__xve_dataport_atomic_message_count_xecore23__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext332 :: GPU Time Elapsed */
#define acmgt3__ext332__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext332 :: GPU Core Clocks */
#define acmgt3__ext332__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext332 :: AVG GPU Core Frequency */
#define acmgt3__ext332__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext332 :: AVG GPU Core Frequency */
#define acmgt3__ext332__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext332 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE24 */
#define acmgt3__ext332__xve_dataport_atomic_message_count_xecore24__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext332 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE25 */
#define acmgt3__ext332__xve_dataport_atomic_message_count_xecore25__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext332 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE26 */
#define acmgt3__ext332__xve_dataport_atomic_message_count_xecore26__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext332 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE27 */
#define acmgt3__ext332__xve_dataport_atomic_message_count_xecore27__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext333 :: GPU Time Elapsed */
#define acmgt3__ext333__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext333 :: GPU Core Clocks */
#define acmgt3__ext333__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext333 :: AVG GPU Core Frequency */
#define acmgt3__ext333__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext333 :: AVG GPU Core Frequency */
#define acmgt3__ext333__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext333 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE28 */
#define acmgt3__ext333__xve_dataport_atomic_message_count_xecore28__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext333 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE29 */
#define acmgt3__ext333__xve_dataport_atomic_message_count_xecore29__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext333 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE30 */
#define acmgt3__ext333__xve_dataport_atomic_message_count_xecore30__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext333 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE31 */
#define acmgt3__ext333__xve_dataport_atomic_message_count_xecore31__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext334 :: GPU Time Elapsed */
#define acmgt3__ext334__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext334 :: GPU Core Clocks */
#define acmgt3__ext334__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext334 :: AVG GPU Core Frequency */
#define acmgt3__ext334__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext334 :: AVG GPU Core Frequency */
#define acmgt3__ext334__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE0 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE1 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE2 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE3 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE4 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE5 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE6 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE7 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE8 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE9 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE10 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE11 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE12 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE13 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE14 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext334 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE15 */
#define acmgt3__ext334__xve_dataport_fence_message_count_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext335 :: GPU Time Elapsed */
#define acmgt3__ext335__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext335 :: GPU Core Clocks */
#define acmgt3__ext335__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext335 :: AVG GPU Core Frequency */
#define acmgt3__ext335__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext335 :: AVG GPU Core Frequency */
#define acmgt3__ext335__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE16 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE17 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE18 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE19 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE20 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE21 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE22 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE23 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE24 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE25 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE26 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE27 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE28 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE29 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE30 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext335 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE31 */
#define acmgt3__ext335__xve_dataport_fence_message_count_xecore31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext342 :: GPU Time Elapsed */
#define acmgt3__ext342__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext342 :: GPU Core Clocks */
#define acmgt3__ext342__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext342 :: AVG GPU Core Frequency */
#define acmgt3__ext342__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext342 :: AVG GPU Core Frequency */
#define acmgt3__ext342__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext342 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE0 */
#define acmgt3__ext342__xve_dataport_register_request_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext342 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE1 */
#define acmgt3__ext342__xve_dataport_register_request_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext342 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE2 */
#define acmgt3__ext342__xve_dataport_register_request_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext342 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE3 */
#define acmgt3__ext342__xve_dataport_register_request_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext342 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE4 */
#define acmgt3__ext342__xve_dataport_register_request_count_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext342 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE5 */
#define acmgt3__ext342__xve_dataport_register_request_count_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext342 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE6 */
#define acmgt3__ext342__xve_dataport_register_request_count_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext342 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE7 */
#define acmgt3__ext342__xve_dataport_register_request_count_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext343 :: GPU Time Elapsed */
#define acmgt3__ext343__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext343 :: GPU Core Clocks */
#define acmgt3__ext343__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext343 :: AVG GPU Core Frequency */
#define acmgt3__ext343__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext343 :: AVG GPU Core Frequency */
#define acmgt3__ext343__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext343 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE8 */
#define acmgt3__ext343__xve_dataport_register_request_count_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext343 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE9 */
#define acmgt3__ext343__xve_dataport_register_request_count_xecore9__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext343 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE10 */
#define acmgt3__ext343__xve_dataport_register_request_count_xecore10__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext343 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE11 */
#define acmgt3__ext343__xve_dataport_register_request_count_xecore11__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext343 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE12 */
#define acmgt3__ext343__xve_dataport_register_request_count_xecore12__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext343 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE13 */
#define acmgt3__ext343__xve_dataport_register_request_count_xecore13__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext343 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE14 */
#define acmgt3__ext343__xve_dataport_register_request_count_xecore14__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext343 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE15 */
#define acmgt3__ext343__xve_dataport_register_request_count_xecore15__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext344 :: GPU Time Elapsed */
#define acmgt3__ext344__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext344 :: GPU Core Clocks */
#define acmgt3__ext344__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext344 :: AVG GPU Core Frequency */
#define acmgt3__ext344__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext344 :: AVG GPU Core Frequency */
#define acmgt3__ext344__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext344 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE16 */
#define acmgt3__ext344__xve_dataport_register_request_count_xecore16__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext344 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE17 */
#define acmgt3__ext344__xve_dataport_register_request_count_xecore17__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext344 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE18 */
#define acmgt3__ext344__xve_dataport_register_request_count_xecore18__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext344 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE19 */
#define acmgt3__ext344__xve_dataport_register_request_count_xecore19__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext344 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE20 */
#define acmgt3__ext344__xve_dataport_register_request_count_xecore20__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext344 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE21 */
#define acmgt3__ext344__xve_dataport_register_request_count_xecore21__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext344 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE22 */
#define acmgt3__ext344__xve_dataport_register_request_count_xecore22__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext344 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE23 */
#define acmgt3__ext344__xve_dataport_register_request_count_xecore23__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext345 :: GPU Time Elapsed */
#define acmgt3__ext345__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext345 :: GPU Core Clocks */
#define acmgt3__ext345__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext345 :: AVG GPU Core Frequency */
#define acmgt3__ext345__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext345 :: AVG GPU Core Frequency */
#define acmgt3__ext345__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext345 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE24 */
#define acmgt3__ext345__xve_dataport_register_request_count_xecore24__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext345 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE25 */
#define acmgt3__ext345__xve_dataport_register_request_count_xecore25__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext345 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE26 */
#define acmgt3__ext345__xve_dataport_register_request_count_xecore26__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext345 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE27 */
#define acmgt3__ext345__xve_dataport_register_request_count_xecore27__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext345 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE28 */
#define acmgt3__ext345__xve_dataport_register_request_count_xecore28__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext345 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE29 */
#define acmgt3__ext345__xve_dataport_register_request_count_xecore29__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext345 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE30 */
#define acmgt3__ext345__xve_dataport_register_request_count_xecore30__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext345 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE31 */
#define acmgt3__ext345__xve_dataport_register_request_count_xecore31__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext346 :: GPU Time Elapsed */
#define acmgt3__ext346__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext346 :: GPU Core Clocks */
#define acmgt3__ext346__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext346 :: AVG GPU Core Frequency */
#define acmgt3__ext346__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext346 :: AVG GPU Core Frequency */
#define acmgt3__ext346__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext346 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE0 */
#define acmgt3__ext346__xve_dataport_register_response_count_xecore0__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext346 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE1 */
#define acmgt3__ext346__xve_dataport_register_response_count_xecore1__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext347 :: GPU Time Elapsed */
#define acmgt3__ext347__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext347 :: GPU Core Clocks */
#define acmgt3__ext347__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext347 :: AVG GPU Core Frequency */
#define acmgt3__ext347__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext347 :: AVG GPU Core Frequency */
#define acmgt3__ext347__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext347 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE2 */
#define acmgt3__ext347__xve_dataport_register_response_count_xecore2__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext347 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE3 */
#define acmgt3__ext347__xve_dataport_register_response_count_xecore3__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext348 :: GPU Time Elapsed */
#define acmgt3__ext348__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext348 :: GPU Core Clocks */
#define acmgt3__ext348__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext348 :: AVG GPU Core Frequency */
#define acmgt3__ext348__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext348 :: AVG GPU Core Frequency */
#define acmgt3__ext348__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext348 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE4 */
#define acmgt3__ext348__xve_dataport_register_response_count_xecore4__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext348 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE5 */
#define acmgt3__ext348__xve_dataport_register_response_count_xecore5__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext349 :: GPU Time Elapsed */
#define acmgt3__ext349__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext349 :: GPU Core Clocks */
#define acmgt3__ext349__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext349 :: AVG GPU Core Frequency */
#define acmgt3__ext349__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext349 :: AVG GPU Core Frequency */
#define acmgt3__ext349__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext349 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE6 */
#define acmgt3__ext349__xve_dataport_register_response_count_xecore6__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext349 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE7 */
#define acmgt3__ext349__xve_dataport_register_response_count_xecore7__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext350 :: GPU Time Elapsed */
#define acmgt3__ext350__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext350 :: GPU Core Clocks */
#define acmgt3__ext350__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext350 :: AVG GPU Core Frequency */
#define acmgt3__ext350__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext350 :: AVG GPU Core Frequency */
#define acmgt3__ext350__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext350 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE8 */
#define acmgt3__ext350__xve_dataport_register_response_count_xecore8__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore0__read

/* Ext350 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE9 */
#define acmgt3__ext350__xve_dataport_register_response_count_xecore9__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext351 :: GPU Time Elapsed */
#define acmgt3__ext351__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext351 :: GPU Core Clocks */
#define acmgt3__ext351__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext351 :: AVG GPU Core Frequency */
#define acmgt3__ext351__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext351 :: AVG GPU Core Frequency */
#define acmgt3__ext351__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext351 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE10 */
#define acmgt3__ext351__xve_dataport_register_response_count_xecore10__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext351 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE11 */
#define acmgt3__ext351__xve_dataport_register_response_count_xecore11__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext352 :: GPU Time Elapsed */
#define acmgt3__ext352__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext352 :: GPU Core Clocks */
#define acmgt3__ext352__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext352 :: AVG GPU Core Frequency */
#define acmgt3__ext352__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext352 :: AVG GPU Core Frequency */
#define acmgt3__ext352__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext352 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE12 */
#define acmgt3__ext352__xve_dataport_register_response_count_xecore12__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext352 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE13 */
#define acmgt3__ext352__xve_dataport_register_response_count_xecore13__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext353 :: GPU Time Elapsed */
#define acmgt3__ext353__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext353 :: GPU Core Clocks */
#define acmgt3__ext353__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext353 :: AVG GPU Core Frequency */
#define acmgt3__ext353__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext353 :: AVG GPU Core Frequency */
#define acmgt3__ext353__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext353 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE14 */
#define acmgt3__ext353__xve_dataport_register_response_count_xecore14__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext353 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE15 */
#define acmgt3__ext353__xve_dataport_register_response_count_xecore15__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext354 :: GPU Time Elapsed */
#define acmgt3__ext354__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext354 :: GPU Core Clocks */
#define acmgt3__ext354__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext354 :: AVG GPU Core Frequency */
#define acmgt3__ext354__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext354 :: AVG GPU Core Frequency */
#define acmgt3__ext354__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext354 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE16 */
#define acmgt3__ext354__xve_dataport_register_response_count_xecore16__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext354 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE17 */
#define acmgt3__ext354__xve_dataport_register_response_count_xecore17__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext355 :: GPU Time Elapsed */
#define acmgt3__ext355__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext355 :: GPU Core Clocks */
#define acmgt3__ext355__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext355 :: AVG GPU Core Frequency */
#define acmgt3__ext355__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext355 :: AVG GPU Core Frequency */
#define acmgt3__ext355__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext355 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE18 */
#define acmgt3__ext355__xve_dataport_register_response_count_xecore18__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext355 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE19 */
#define acmgt3__ext355__xve_dataport_register_response_count_xecore19__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext356 :: GPU Time Elapsed */
#define acmgt3__ext356__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext356 :: GPU Core Clocks */
#define acmgt3__ext356__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext356 :: AVG GPU Core Frequency */
#define acmgt3__ext356__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext356 :: AVG GPU Core Frequency */
#define acmgt3__ext356__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext356 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE20 */
#define acmgt3__ext356__xve_dataport_register_response_count_xecore20__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext356 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE21 */
#define acmgt3__ext356__xve_dataport_register_response_count_xecore21__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext357 :: GPU Time Elapsed */
#define acmgt3__ext357__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext357 :: GPU Core Clocks */
#define acmgt3__ext357__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext357 :: AVG GPU Core Frequency */
#define acmgt3__ext357__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext357 :: AVG GPU Core Frequency */
#define acmgt3__ext357__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext357 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE22 */
#define acmgt3__ext357__xve_dataport_register_response_count_xecore22__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext357 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE23 */
#define acmgt3__ext357__xve_dataport_register_response_count_xecore23__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext358 :: GPU Time Elapsed */
#define acmgt3__ext358__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext358 :: GPU Core Clocks */
#define acmgt3__ext358__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext358 :: AVG GPU Core Frequency */
#define acmgt3__ext358__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext358 :: AVG GPU Core Frequency */
#define acmgt3__ext358__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext358 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE24 */
#define acmgt3__ext358__xve_dataport_register_response_count_xecore24__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext358 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE25 */
#define acmgt3__ext358__xve_dataport_register_response_count_xecore25__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext359 :: GPU Time Elapsed */
#define acmgt3__ext359__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext359 :: GPU Core Clocks */
#define acmgt3__ext359__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext359 :: AVG GPU Core Frequency */
#define acmgt3__ext359__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext359 :: AVG GPU Core Frequency */
#define acmgt3__ext359__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext359 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE26 */
#define acmgt3__ext359__xve_dataport_register_response_count_xecore26__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext359 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE27 */
#define acmgt3__ext359__xve_dataport_register_response_count_xecore27__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext360 :: GPU Time Elapsed */
#define acmgt3__ext360__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext360 :: GPU Core Clocks */
#define acmgt3__ext360__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext360 :: AVG GPU Core Frequency */
#define acmgt3__ext360__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext360 :: AVG GPU Core Frequency */
#define acmgt3__ext360__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext360 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE28 */
#define acmgt3__ext360__xve_dataport_register_response_count_xecore28__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext360 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE29 */
#define acmgt3__ext360__xve_dataport_register_response_count_xecore29__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext361 :: GPU Time Elapsed */
#define acmgt3__ext361__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext361 :: GPU Core Clocks */
#define acmgt3__ext361__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext361 :: AVG GPU Core Frequency */
#define acmgt3__ext361__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext361 :: AVG GPU Core Frequency */
#define acmgt3__ext361__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext361 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE30 */
#define acmgt3__ext361__xve_dataport_register_response_count_xecore30__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext361 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE31 */
#define acmgt3__ext361__xve_dataport_register_response_count_xecore31__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext362 :: GPU Time Elapsed */
#define acmgt3__ext362__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext362 :: GPU Core Clocks */
#define acmgt3__ext362__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext362 :: AVG GPU Core Frequency */
#define acmgt3__ext362__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext362 :: AVG GPU Core Frequency */
#define acmgt3__ext362__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext362 :: DATAPORT INPUT AVAILABLE XECORE0 */
#define acmgt3__ext362__dataport_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext362 :: DATAPORT INPUT AVAILABLE XECORE1 */
#define acmgt3__ext362__dataport_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext363 :: GPU Time Elapsed */
#define acmgt3__ext363__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext363 :: GPU Core Clocks */
#define acmgt3__ext363__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext363 :: AVG GPU Core Frequency */
#define acmgt3__ext363__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext363 :: AVG GPU Core Frequency */
#define acmgt3__ext363__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext363 :: DATAPORT INPUT AVAILABLE XECORE2 */
#define acmgt3__ext363__dataport_input_available_xecore2__read \
   bdw__render_basic__sampler0_busy__read

/* Ext363 :: DATAPORT INPUT AVAILABLE XECORE3 */
#define acmgt3__ext363__dataport_input_available_xecore3__read \
   bdw__render_basic__sampler1_busy__read

/* Ext364 :: GPU Time Elapsed */
#define acmgt3__ext364__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext364 :: GPU Core Clocks */
#define acmgt3__ext364__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext364 :: AVG GPU Core Frequency */
#define acmgt3__ext364__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext364 :: AVG GPU Core Frequency */
#define acmgt3__ext364__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext364 :: DATAPORT INPUT AVAILABLE XECORE4 */
#define acmgt3__ext364__dataport_input_available_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext364 :: DATAPORT INPUT AVAILABLE XECORE5 */
#define acmgt3__ext364__dataport_input_available_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext365 :: GPU Time Elapsed */
#define acmgt3__ext365__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext365 :: GPU Core Clocks */
#define acmgt3__ext365__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext365 :: AVG GPU Core Frequency */
#define acmgt3__ext365__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext365 :: AVG GPU Core Frequency */
#define acmgt3__ext365__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext365 :: DATAPORT INPUT AVAILABLE XECORE6 */
#define acmgt3__ext365__dataport_input_available_xecore6__read \
   bdw__render_basic__sampler0_busy__read

/* Ext365 :: DATAPORT INPUT AVAILABLE XECORE7 */
#define acmgt3__ext365__dataport_input_available_xecore7__read \
   bdw__render_basic__sampler1_busy__read

/* Ext366 :: GPU Time Elapsed */
#define acmgt3__ext366__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext366 :: GPU Core Clocks */
#define acmgt3__ext366__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext366 :: AVG GPU Core Frequency */
#define acmgt3__ext366__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext366 :: AVG GPU Core Frequency */
#define acmgt3__ext366__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext366 :: DATAPORT INPUT AVAILABLE XECORE8 */
#define acmgt3__ext366__dataport_input_available_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext366 :: DATAPORT INPUT AVAILABLE XECORE9 */
#define acmgt3__ext366__dataport_input_available_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext367 :: GPU Time Elapsed */
#define acmgt3__ext367__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext367 :: GPU Core Clocks */
#define acmgt3__ext367__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext367 :: AVG GPU Core Frequency */
#define acmgt3__ext367__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext367 :: AVG GPU Core Frequency */
#define acmgt3__ext367__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext367 :: DATAPORT INPUT AVAILABLE XECORE10 */
#define acmgt3__ext367__dataport_input_available_xecore10__read \
   bdw__render_basic__sampler0_busy__read

/* Ext367 :: DATAPORT INPUT AVAILABLE XECORE11 */
#define acmgt3__ext367__dataport_input_available_xecore11__read \
   bdw__render_basic__sampler1_busy__read

/* Ext368 :: GPU Time Elapsed */
#define acmgt3__ext368__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext368 :: GPU Core Clocks */
#define acmgt3__ext368__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext368 :: AVG GPU Core Frequency */
#define acmgt3__ext368__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext368 :: AVG GPU Core Frequency */
#define acmgt3__ext368__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext368 :: DATAPORT INPUT AVAILABLE XECORE12 */
#define acmgt3__ext368__dataport_input_available_xecore12__read \
   bdw__render_basic__sampler0_busy__read

/* Ext368 :: DATAPORT INPUT AVAILABLE XECORE13 */
#define acmgt3__ext368__dataport_input_available_xecore13__read \
   bdw__render_basic__sampler1_busy__read

/* Ext369 :: GPU Time Elapsed */
#define acmgt3__ext369__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext369 :: GPU Core Clocks */
#define acmgt3__ext369__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext369 :: AVG GPU Core Frequency */
#define acmgt3__ext369__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext369 :: AVG GPU Core Frequency */
#define acmgt3__ext369__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext369 :: DATAPORT INPUT AVAILABLE XECORE14 */
#define acmgt3__ext369__dataport_input_available_xecore14__read \
   bdw__render_basic__sampler0_busy__read

/* Ext369 :: DATAPORT INPUT AVAILABLE XECORE15 */
#define acmgt3__ext369__dataport_input_available_xecore15__read \
   bdw__render_basic__sampler1_busy__read

/* Ext370 :: GPU Time Elapsed */
#define acmgt3__ext370__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext370 :: GPU Core Clocks */
#define acmgt3__ext370__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext370 :: AVG GPU Core Frequency */
#define acmgt3__ext370__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext370 :: AVG GPU Core Frequency */
#define acmgt3__ext370__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext370 :: DATAPORT INPUT AVAILABLE XECORE16 */
#define acmgt3__ext370__dataport_input_available_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext370 :: DATAPORT INPUT AVAILABLE XECORE17 */
#define acmgt3__ext370__dataport_input_available_xecore17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext371 :: GPU Time Elapsed */
#define acmgt3__ext371__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext371 :: GPU Core Clocks */
#define acmgt3__ext371__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext371 :: AVG GPU Core Frequency */
#define acmgt3__ext371__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext371 :: AVG GPU Core Frequency */
#define acmgt3__ext371__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext371 :: DATAPORT INPUT AVAILABLE XECORE18 */
#define acmgt3__ext371__dataport_input_available_xecore18__read \
   bdw__render_basic__sampler0_busy__read

/* Ext371 :: DATAPORT INPUT AVAILABLE XECORE19 */
#define acmgt3__ext371__dataport_input_available_xecore19__read \
   bdw__render_basic__sampler1_busy__read

/* Ext372 :: GPU Time Elapsed */
#define acmgt3__ext372__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext372 :: GPU Core Clocks */
#define acmgt3__ext372__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext372 :: AVG GPU Core Frequency */
#define acmgt3__ext372__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext372 :: AVG GPU Core Frequency */
#define acmgt3__ext372__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext372 :: DATAPORT INPUT AVAILABLE XECORE20 */
#define acmgt3__ext372__dataport_input_available_xecore20__read \
   bdw__render_basic__sampler0_busy__read

/* Ext372 :: DATAPORT INPUT AVAILABLE XECORE21 */
#define acmgt3__ext372__dataport_input_available_xecore21__read \
   bdw__render_basic__sampler1_busy__read

/* Ext373 :: GPU Time Elapsed */
#define acmgt3__ext373__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext373 :: GPU Core Clocks */
#define acmgt3__ext373__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext373 :: AVG GPU Core Frequency */
#define acmgt3__ext373__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext373 :: AVG GPU Core Frequency */
#define acmgt3__ext373__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext373 :: DATAPORT INPUT AVAILABLE XECORE22 */
#define acmgt3__ext373__dataport_input_available_xecore22__read \
   bdw__render_basic__sampler0_busy__read

/* Ext373 :: DATAPORT INPUT AVAILABLE XECORE23 */
#define acmgt3__ext373__dataport_input_available_xecore23__read \
   bdw__render_basic__sampler1_busy__read

/* Ext374 :: GPU Time Elapsed */
#define acmgt3__ext374__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext374 :: GPU Core Clocks */
#define acmgt3__ext374__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext374 :: AVG GPU Core Frequency */
#define acmgt3__ext374__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext374 :: AVG GPU Core Frequency */
#define acmgt3__ext374__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext374 :: DATAPORT INPUT AVAILABLE XECORE24 */
#define acmgt3__ext374__dataport_input_available_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext374 :: DATAPORT INPUT AVAILABLE XECORE25 */
#define acmgt3__ext374__dataport_input_available_xecore25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext375 :: GPU Time Elapsed */
#define acmgt3__ext375__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext375 :: GPU Core Clocks */
#define acmgt3__ext375__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext375 :: AVG GPU Core Frequency */
#define acmgt3__ext375__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext375 :: AVG GPU Core Frequency */
#define acmgt3__ext375__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext375 :: DATAPORT INPUT AVAILABLE XECORE26 */
#define acmgt3__ext375__dataport_input_available_xecore26__read \
   bdw__render_basic__sampler0_busy__read

/* Ext375 :: DATAPORT INPUT AVAILABLE XECORE27 */
#define acmgt3__ext375__dataport_input_available_xecore27__read \
   bdw__render_basic__sampler1_busy__read

/* Ext376 :: GPU Time Elapsed */
#define acmgt3__ext376__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext376 :: GPU Core Clocks */
#define acmgt3__ext376__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext376 :: AVG GPU Core Frequency */
#define acmgt3__ext376__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext376 :: AVG GPU Core Frequency */
#define acmgt3__ext376__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext376 :: DATAPORT INPUT AVAILABLE XECORE28 */
#define acmgt3__ext376__dataport_input_available_xecore28__read \
   bdw__render_basic__sampler0_busy__read

/* Ext376 :: DATAPORT INPUT AVAILABLE XECORE29 */
#define acmgt3__ext376__dataport_input_available_xecore29__read \
   bdw__render_basic__sampler1_busy__read

/* Ext377 :: GPU Time Elapsed */
#define acmgt3__ext377__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext377 :: GPU Core Clocks */
#define acmgt3__ext377__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext377 :: AVG GPU Core Frequency */
#define acmgt3__ext377__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext377 :: AVG GPU Core Frequency */
#define acmgt3__ext377__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext377 :: DATAPORT INPUT AVAILABLE XECORE30 */
#define acmgt3__ext377__dataport_input_available_xecore30__read \
   bdw__render_basic__sampler0_busy__read

/* Ext377 :: DATAPORT INPUT AVAILABLE XECORE31 */
#define acmgt3__ext377__dataport_input_available_xecore31__read \
   bdw__render_basic__sampler1_busy__read

/* Ext378 :: GPU Time Elapsed */
#define acmgt3__ext378__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext378 :: GPU Core Clocks */
#define acmgt3__ext378__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext378 :: AVG GPU Core Frequency */
#define acmgt3__ext378__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext378 :: AVG GPU Core Frequency */
#define acmgt3__ext378__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext378 :: DATAPORT OUTPUT READY XECORE0 */
#define acmgt3__ext378__dataport_output_ready_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext378 :: DATAPORT OUTPUT READY XECORE1 */
#define acmgt3__ext378__dataport_output_ready_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext378 :: DATAPORT OUTPUT READY XECORE2 */
#define acmgt3__ext378__dataport_output_ready_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext378 :: DATAPORT OUTPUT READY XECORE3 */
#define acmgt3__ext378__dataport_output_ready_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext379 :: GPU Time Elapsed */
#define acmgt3__ext379__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext379 :: GPU Core Clocks */
#define acmgt3__ext379__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext379 :: AVG GPU Core Frequency */
#define acmgt3__ext379__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext379 :: AVG GPU Core Frequency */
#define acmgt3__ext379__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext379 :: DATAPORT OUTPUT READY XECORE4 */
#define acmgt3__ext379__dataport_output_ready_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext379 :: DATAPORT OUTPUT READY XECORE5 */
#define acmgt3__ext379__dataport_output_ready_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext379 :: DATAPORT OUTPUT READY XECORE6 */
#define acmgt3__ext379__dataport_output_ready_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext379 :: DATAPORT OUTPUT READY XECORE7 */
#define acmgt3__ext379__dataport_output_ready_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext380 :: GPU Time Elapsed */
#define acmgt3__ext380__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext380 :: GPU Core Clocks */
#define acmgt3__ext380__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext380 :: AVG GPU Core Frequency */
#define acmgt3__ext380__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext380 :: AVG GPU Core Frequency */
#define acmgt3__ext380__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext380 :: DATAPORT OUTPUT READY XECORE8 */
#define acmgt3__ext380__dataport_output_ready_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext380 :: DATAPORT OUTPUT READY XECORE9 */
#define acmgt3__ext380__dataport_output_ready_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext380 :: DATAPORT OUTPUT READY XECORE10 */
#define acmgt3__ext380__dataport_output_ready_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext380 :: DATAPORT OUTPUT READY XECORE11 */
#define acmgt3__ext380__dataport_output_ready_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext381 :: GPU Time Elapsed */
#define acmgt3__ext381__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext381 :: GPU Core Clocks */
#define acmgt3__ext381__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext381 :: AVG GPU Core Frequency */
#define acmgt3__ext381__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext381 :: AVG GPU Core Frequency */
#define acmgt3__ext381__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext381 :: DATAPORT OUTPUT READY XECORE12 */
#define acmgt3__ext381__dataport_output_ready_xecore12__read \
   bdw__render_basic__sampler0_busy__read

/* Ext381 :: DATAPORT OUTPUT READY XECORE13 */
#define acmgt3__ext381__dataport_output_ready_xecore13__read \
   bdw__render_basic__sampler1_busy__read

/* Ext381 :: DATAPORT OUTPUT READY XECORE14 */
#define acmgt3__ext381__dataport_output_ready_xecore14__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext381 :: DATAPORT OUTPUT READY XECORE15 */
#define acmgt3__ext381__dataport_output_ready_xecore15__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext382 :: GPU Time Elapsed */
#define acmgt3__ext382__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext382 :: GPU Core Clocks */
#define acmgt3__ext382__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext382 :: AVG GPU Core Frequency */
#define acmgt3__ext382__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext382 :: AVG GPU Core Frequency */
#define acmgt3__ext382__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext382 :: DATAPORT OUTPUT READY XECORE16 */
#define acmgt3__ext382__dataport_output_ready_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext382 :: DATAPORT OUTPUT READY XECORE17 */
#define acmgt3__ext382__dataport_output_ready_xecore17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext382 :: DATAPORT OUTPUT READY XECORE18 */
#define acmgt3__ext382__dataport_output_ready_xecore18__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext382 :: DATAPORT OUTPUT READY XECORE19 */
#define acmgt3__ext382__dataport_output_ready_xecore19__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext383 :: GPU Time Elapsed */
#define acmgt3__ext383__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext383 :: GPU Core Clocks */
#define acmgt3__ext383__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext383 :: AVG GPU Core Frequency */
#define acmgt3__ext383__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext383 :: AVG GPU Core Frequency */
#define acmgt3__ext383__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext383 :: DATAPORT OUTPUT READY XECORE20 */
#define acmgt3__ext383__dataport_output_ready_xecore20__read \
   bdw__render_basic__sampler0_busy__read

/* Ext383 :: DATAPORT OUTPUT READY XECORE21 */
#define acmgt3__ext383__dataport_output_ready_xecore21__read \
   bdw__render_basic__sampler1_busy__read

/* Ext383 :: DATAPORT OUTPUT READY XECORE22 */
#define acmgt3__ext383__dataport_output_ready_xecore22__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext383 :: DATAPORT OUTPUT READY XECORE23 */
#define acmgt3__ext383__dataport_output_ready_xecore23__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext384 :: GPU Time Elapsed */
#define acmgt3__ext384__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext384 :: GPU Core Clocks */
#define acmgt3__ext384__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext384 :: AVG GPU Core Frequency */
#define acmgt3__ext384__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext384 :: AVG GPU Core Frequency */
#define acmgt3__ext384__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext384 :: DATAPORT OUTPUT READY XECORE24 */
#define acmgt3__ext384__dataport_output_ready_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext384 :: DATAPORT OUTPUT READY XECORE25 */
#define acmgt3__ext384__dataport_output_ready_xecore25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext384 :: DATAPORT OUTPUT READY XECORE26 */
#define acmgt3__ext384__dataport_output_ready_xecore26__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext384 :: DATAPORT OUTPUT READY XECORE27 */
#define acmgt3__ext384__dataport_output_ready_xecore27__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext385 :: GPU Time Elapsed */
#define acmgt3__ext385__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext385 :: GPU Core Clocks */
#define acmgt3__ext385__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext385 :: AVG GPU Core Frequency */
#define acmgt3__ext385__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext385 :: AVG GPU Core Frequency */
#define acmgt3__ext385__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext385 :: DATAPORT OUTPUT READY XECORE28 */
#define acmgt3__ext385__dataport_output_ready_xecore28__read \
   bdw__render_basic__sampler0_busy__read

/* Ext385 :: DATAPORT OUTPUT READY XECORE29 */
#define acmgt3__ext385__dataport_output_ready_xecore29__read \
   bdw__render_basic__sampler1_busy__read

/* Ext385 :: DATAPORT OUTPUT READY XECORE30 */
#define acmgt3__ext385__dataport_output_ready_xecore30__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext385 :: DATAPORT OUTPUT READY XECORE31 */
#define acmgt3__ext385__dataport_output_ready_xecore31__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext386 :: GPU Time Elapsed */
#define acmgt3__ext386__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext386 :: GPU Core Clocks */
#define acmgt3__ext386__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext386 :: AVG GPU Core Frequency */
#define acmgt3__ext386__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext386 :: AVG GPU Core Frequency */
#define acmgt3__ext386__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext386 :: DATAPORT BYTE READ XECORE0 */
#define acmgt3__ext386__dataport_byte_read_xecore0__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext386 :: DATAPORT BYTE READ XECORE1 */
#define acmgt3__ext386__dataport_byte_read_xecore1__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext387 :: GPU Time Elapsed */
#define acmgt3__ext387__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext387 :: GPU Core Clocks */
#define acmgt3__ext387__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext387 :: AVG GPU Core Frequency */
#define acmgt3__ext387__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext387 :: AVG GPU Core Frequency */
#define acmgt3__ext387__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext387 :: DATAPORT BYTE READ XECORE2 */
#define acmgt3__ext387__dataport_byte_read_xecore2__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext387 :: DATAPORT BYTE READ XECORE3 */
#define acmgt3__ext387__dataport_byte_read_xecore3__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext388 :: GPU Time Elapsed */
#define acmgt3__ext388__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext388 :: GPU Core Clocks */
#define acmgt3__ext388__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext388 :: AVG GPU Core Frequency */
#define acmgt3__ext388__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext388 :: AVG GPU Core Frequency */
#define acmgt3__ext388__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext388 :: DATAPORT BYTE READ XECORE4 */
#define acmgt3__ext388__dataport_byte_read_xecore4__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext388 :: DATAPORT BYTE READ XECORE5 */
#define acmgt3__ext388__dataport_byte_read_xecore5__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext389 :: GPU Time Elapsed */
#define acmgt3__ext389__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext389 :: GPU Core Clocks */
#define acmgt3__ext389__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext389 :: AVG GPU Core Frequency */
#define acmgt3__ext389__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext389 :: AVG GPU Core Frequency */
#define acmgt3__ext389__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext389 :: DATAPORT BYTE READ XECORE6 */
#define acmgt3__ext389__dataport_byte_read_xecore6__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext389 :: DATAPORT BYTE READ XECORE7 */
#define acmgt3__ext389__dataport_byte_read_xecore7__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext390 :: GPU Time Elapsed */
#define acmgt3__ext390__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext390 :: GPU Core Clocks */
#define acmgt3__ext390__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext390 :: AVG GPU Core Frequency */
#define acmgt3__ext390__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext390 :: AVG GPU Core Frequency */
#define acmgt3__ext390__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext390 :: DATAPORT BYTE READ XECORE8 */
#define acmgt3__ext390__dataport_byte_read_xecore8__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext390 :: DATAPORT BYTE READ XECORE9 */
#define acmgt3__ext390__dataport_byte_read_xecore9__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext391 :: GPU Time Elapsed */
#define acmgt3__ext391__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext391 :: GPU Core Clocks */
#define acmgt3__ext391__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext391 :: AVG GPU Core Frequency */
#define acmgt3__ext391__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext391 :: AVG GPU Core Frequency */
#define acmgt3__ext391__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext391 :: DATAPORT BYTE READ XECORE10 */
#define acmgt3__ext391__dataport_byte_read_xecore10__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext391 :: DATAPORT BYTE READ XECORE11 */
#define acmgt3__ext391__dataport_byte_read_xecore11__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext392 :: GPU Time Elapsed */
#define acmgt3__ext392__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext392 :: GPU Core Clocks */
#define acmgt3__ext392__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext392 :: AVG GPU Core Frequency */
#define acmgt3__ext392__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext392 :: AVG GPU Core Frequency */
#define acmgt3__ext392__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext392 :: DATAPORT BYTE READ XECORE12 */
#define acmgt3__ext392__dataport_byte_read_xecore12__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext392 :: DATAPORT BYTE READ XECORE13 */
#define acmgt3__ext392__dataport_byte_read_xecore13__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext393 :: GPU Time Elapsed */
#define acmgt3__ext393__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext393 :: GPU Core Clocks */
#define acmgt3__ext393__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext393 :: AVG GPU Core Frequency */
#define acmgt3__ext393__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext393 :: AVG GPU Core Frequency */
#define acmgt3__ext393__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext393 :: DATAPORT BYTE READ XECORE14 */
#define acmgt3__ext393__dataport_byte_read_xecore14__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext393 :: DATAPORT BYTE READ XECORE15 */
#define acmgt3__ext393__dataport_byte_read_xecore15__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext394 :: GPU Time Elapsed */
#define acmgt3__ext394__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext394 :: GPU Core Clocks */
#define acmgt3__ext394__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext394 :: AVG GPU Core Frequency */
#define acmgt3__ext394__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext394 :: AVG GPU Core Frequency */
#define acmgt3__ext394__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext394 :: DATAPORT BYTE READ XECORE16 */
#define acmgt3__ext394__dataport_byte_read_xecore16__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext394 :: DATAPORT BYTE READ XECORE17 */
#define acmgt3__ext394__dataport_byte_read_xecore17__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext395 :: GPU Time Elapsed */
#define acmgt3__ext395__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext395 :: GPU Core Clocks */
#define acmgt3__ext395__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext395 :: AVG GPU Core Frequency */
#define acmgt3__ext395__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext395 :: AVG GPU Core Frequency */
#define acmgt3__ext395__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext395 :: DATAPORT BYTE READ XECORE18 */
#define acmgt3__ext395__dataport_byte_read_xecore18__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext395 :: DATAPORT BYTE READ XECORE19 */
#define acmgt3__ext395__dataport_byte_read_xecore19__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext396 :: GPU Time Elapsed */
#define acmgt3__ext396__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext396 :: GPU Core Clocks */
#define acmgt3__ext396__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext396 :: AVG GPU Core Frequency */
#define acmgt3__ext396__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext396 :: AVG GPU Core Frequency */
#define acmgt3__ext396__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext396 :: DATAPORT BYTE READ XECORE20 */
#define acmgt3__ext396__dataport_byte_read_xecore20__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext396 :: DATAPORT BYTE READ XECORE21 */
#define acmgt3__ext396__dataport_byte_read_xecore21__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext397 :: GPU Time Elapsed */
#define acmgt3__ext397__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext397 :: GPU Core Clocks */
#define acmgt3__ext397__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext397 :: AVG GPU Core Frequency */
#define acmgt3__ext397__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext397 :: AVG GPU Core Frequency */
#define acmgt3__ext397__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext397 :: DATAPORT BYTE READ XECORE22 */
#define acmgt3__ext397__dataport_byte_read_xecore22__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext397 :: DATAPORT BYTE READ XECORE23 */
#define acmgt3__ext397__dataport_byte_read_xecore23__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext398 :: GPU Time Elapsed */
#define acmgt3__ext398__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext398 :: GPU Core Clocks */
#define acmgt3__ext398__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext398 :: AVG GPU Core Frequency */
#define acmgt3__ext398__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext398 :: AVG GPU Core Frequency */
#define acmgt3__ext398__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext398 :: DATAPORT BYTE READ XECORE24 */
#define acmgt3__ext398__dataport_byte_read_xecore24__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext398 :: DATAPORT BYTE READ XECORE25 */
#define acmgt3__ext398__dataport_byte_read_xecore25__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext399 :: GPU Time Elapsed */
#define acmgt3__ext399__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext399 :: GPU Core Clocks */
#define acmgt3__ext399__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext399 :: AVG GPU Core Frequency */
#define acmgt3__ext399__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext399 :: AVG GPU Core Frequency */
#define acmgt3__ext399__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext399 :: DATAPORT BYTE READ XECORE26 */
#define acmgt3__ext399__dataport_byte_read_xecore26__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext399 :: DATAPORT BYTE READ XECORE27 */
#define acmgt3__ext399__dataport_byte_read_xecore27__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext400 :: GPU Time Elapsed */
#define acmgt3__ext400__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext400 :: GPU Core Clocks */
#define acmgt3__ext400__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext400 :: AVG GPU Core Frequency */
#define acmgt3__ext400__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext400 :: AVG GPU Core Frequency */
#define acmgt3__ext400__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext400 :: DATAPORT BYTE READ XECORE28 */
#define acmgt3__ext400__dataport_byte_read_xecore28__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext400 :: DATAPORT BYTE READ XECORE29 */
#define acmgt3__ext400__dataport_byte_read_xecore29__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext401 :: GPU Time Elapsed */
#define acmgt3__ext401__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext401 :: GPU Core Clocks */
#define acmgt3__ext401__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext401 :: AVG GPU Core Frequency */
#define acmgt3__ext401__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext401 :: AVG GPU Core Frequency */
#define acmgt3__ext401__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext401 :: DATAPORT BYTE READ XECORE30 */
#define acmgt3__ext401__dataport_byte_read_xecore30__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext401 :: DATAPORT BYTE READ XECORE31 */
#define acmgt3__ext401__dataport_byte_read_xecore31__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext402 :: GPU Time Elapsed */
#define acmgt3__ext402__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext402 :: GPU Core Clocks */
#define acmgt3__ext402__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext402 :: AVG GPU Core Frequency */
#define acmgt3__ext402__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext402 :: AVG GPU Core Frequency */
#define acmgt3__ext402__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext402 :: DATAPORT BYTE WRITE XECORE0 */
#define acmgt3__ext402__dataport_byte_write_xecore0__read \
   acmgt1__ext83__dataport_byte_write_xecore0__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE1 */
#define acmgt3__ext402__dataport_byte_write_xecore1__read \
   acmgt1__ext83__dataport_byte_write_xecore1__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE2 */
#define acmgt3__ext402__dataport_byte_write_xecore2__read \
   acmgt1__ext83__dataport_byte_write_xecore2__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE3 */
#define acmgt3__ext402__dataport_byte_write_xecore3__read \
   acmgt1__ext83__dataport_byte_write_xecore3__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE4 */
#define acmgt3__ext402__dataport_byte_write_xecore4__read \
   acmgt1__ext83__dataport_byte_write_xecore4__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE5 */
#define acmgt3__ext402__dataport_byte_write_xecore5__read \
   acmgt1__ext83__dataport_byte_write_xecore5__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE6 */
#define acmgt3__ext402__dataport_byte_write_xecore6__read \
   acmgt1__ext83__dataport_byte_write_xecore6__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE7 */
#define acmgt3__ext402__dataport_byte_write_xecore7__read \
   acmgt1__ext83__dataport_byte_write_xecore7__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE8 */
#define acmgt3__ext402__dataport_byte_write_xecore8__read \
   acmgt2__dataport29__dataport_byte_write_xecore8__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE9 */
#define acmgt3__ext402__dataport_byte_write_xecore9__read \
   acmgt2__dataport29__dataport_byte_write_xecore9__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE10 */
#define acmgt3__ext402__dataport_byte_write_xecore10__read \
   acmgt2__dataport29__dataport_byte_write_xecore10__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE11 */
#define acmgt3__ext402__dataport_byte_write_xecore11__read \
   acmgt2__dataport29__dataport_byte_write_xecore11__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE12 */
#define acmgt3__ext402__dataport_byte_write_xecore12__read \
   acmgt2__dataport29__dataport_byte_write_xecore12__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE13 */
#define acmgt3__ext402__dataport_byte_write_xecore13__read \
   acmgt2__dataport29__dataport_byte_write_xecore13__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE14 */
#define acmgt3__ext402__dataport_byte_write_xecore14__read \
   acmgt2__dataport29__dataport_byte_write_xecore14__read

/* Ext402 :: DATAPORT BYTE WRITE XECORE15 */
#define acmgt3__ext402__dataport_byte_write_xecore15__read \
   acmgt2__dataport29__dataport_byte_write_xecore15__read

/* Ext403 :: GPU Time Elapsed */
#define acmgt3__ext403__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext403 :: GPU Core Clocks */
#define acmgt3__ext403__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext403 :: AVG GPU Core Frequency */
#define acmgt3__ext403__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext403 :: AVG GPU Core Frequency */
#define acmgt3__ext403__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext403 :: DATAPORT BYTE WRITE XECORE16 */
#define acmgt3__ext403__dataport_byte_write_xecore16__read \
   acmgt1__ext83__dataport_byte_write_xecore0__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE17 */
#define acmgt3__ext403__dataport_byte_write_xecore17__read \
   acmgt1__ext83__dataport_byte_write_xecore1__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE18 */
#define acmgt3__ext403__dataport_byte_write_xecore18__read \
   acmgt1__ext83__dataport_byte_write_xecore2__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE19 */
#define acmgt3__ext403__dataport_byte_write_xecore19__read \
   acmgt1__ext83__dataport_byte_write_xecore3__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE20 */
#define acmgt3__ext403__dataport_byte_write_xecore20__read \
   acmgt1__ext83__dataport_byte_write_xecore4__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE21 */
#define acmgt3__ext403__dataport_byte_write_xecore21__read \
   acmgt1__ext83__dataport_byte_write_xecore5__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE22 */
#define acmgt3__ext403__dataport_byte_write_xecore22__read \
   acmgt1__ext83__dataport_byte_write_xecore6__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE23 */
#define acmgt3__ext403__dataport_byte_write_xecore23__read \
   acmgt1__ext83__dataport_byte_write_xecore7__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE24 */
#define acmgt3__ext403__dataport_byte_write_xecore24__read \
   acmgt2__dataport29__dataport_byte_write_xecore8__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE25 */
#define acmgt3__ext403__dataport_byte_write_xecore25__read \
   acmgt2__dataport29__dataport_byte_write_xecore9__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE26 */
#define acmgt3__ext403__dataport_byte_write_xecore26__read \
   acmgt2__dataport29__dataport_byte_write_xecore10__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE27 */
#define acmgt3__ext403__dataport_byte_write_xecore27__read \
   acmgt2__dataport29__dataport_byte_write_xecore11__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE28 */
#define acmgt3__ext403__dataport_byte_write_xecore28__read \
   acmgt2__dataport29__dataport_byte_write_xecore12__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE29 */
#define acmgt3__ext403__dataport_byte_write_xecore29__read \
   acmgt2__dataport29__dataport_byte_write_xecore13__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE30 */
#define acmgt3__ext403__dataport_byte_write_xecore30__read \
   acmgt2__dataport29__dataport_byte_write_xecore14__read

/* Ext403 :: DATAPORT BYTE WRITE XECORE31 */
#define acmgt3__ext403__dataport_byte_write_xecore31__read \
   acmgt2__dataport29__dataport_byte_write_xecore15__read

/* Ext404 :: GPU Time Elapsed */
#define acmgt3__ext404__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext404 :: GPU Core Clocks */
#define acmgt3__ext404__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext404 :: AVG GPU Core Frequency */
#define acmgt3__ext404__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext404 :: AVG GPU Core Frequency */
#define acmgt3__ext404__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE0 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE1 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE2 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE3 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE4 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE5 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE6 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE7 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE8 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE9 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE10 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE11 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE12 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE13 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE14 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext404 :: DATAPORT TEXTURE CACHE ACCESS XECORE15 */
#define acmgt3__ext404__dataport_texture_cache_access_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext405 :: GPU Time Elapsed */
#define acmgt3__ext405__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext405 :: GPU Core Clocks */
#define acmgt3__ext405__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext405 :: AVG GPU Core Frequency */
#define acmgt3__ext405__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext405 :: AVG GPU Core Frequency */
#define acmgt3__ext405__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE16 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE17 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE18 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE19 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE20 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE21 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE22 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE23 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE24 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE25 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE26 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE27 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE28 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE29 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE30 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext405 :: DATAPORT TEXTURE CACHE ACCESS XECORE31 */
#define acmgt3__ext405__dataport_texture_cache_access_xecore31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext406 :: GPU Time Elapsed */
#define acmgt3__ext406__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext406 :: GPU Core Clocks */
#define acmgt3__ext406__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext406 :: AVG GPU Core Frequency */
#define acmgt3__ext406__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext406 :: AVG GPU Core Frequency */
#define acmgt3__ext406__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE0 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE1 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE2 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE3 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE4 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE5 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE6 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE7 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE8 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore8__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE9 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore9__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE10 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore10__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE11 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore11__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE12 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore12__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE13 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE14 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext406 :: DATAPORT TEXTURE CACHE HIT XECORE15 */
#define acmgt3__ext406__dataport_texture_cache_hit_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext407 :: GPU Time Elapsed */
#define acmgt3__ext407__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext407 :: GPU Core Clocks */
#define acmgt3__ext407__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext407 :: AVG GPU Core Frequency */
#define acmgt3__ext407__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext407 :: AVG GPU Core Frequency */
#define acmgt3__ext407__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE16 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE17 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE18 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE19 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE20 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE21 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE22 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE23 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE24 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore24__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE25 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore25__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE26 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore26__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE27 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore27__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE28 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore28__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE29 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE30 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext407 :: DATAPORT TEXTURE CACHE HIT XECORE31 */
#define acmgt3__ext407__dataport_texture_cache_hit_xecore31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext408 :: GPU Time Elapsed */
#define acmgt3__ext408__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext408 :: GPU Core Clocks */
#define acmgt3__ext408__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext408 :: AVG GPU Core Frequency */
#define acmgt3__ext408__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext408 :: AVG GPU Core Frequency */
#define acmgt3__ext408__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext408 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define acmgt3__ext408__rt_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext408 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0 */
#define acmgt3__ext408__rt_load_store_cache_write_from_message_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext408 :: RT TRAVERSAL INPUT RAY COUNT XECORE0 */
#define acmgt3__ext408__rt_traversal_input_ray_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext408 :: RT QUAD TEST RAY COUNT XECORE0 */
#define acmgt3__ext408__rt_quad_test_ray_count_xecore0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext408 :: RT REQUEST COLLISION XECORE0 */
#define acmgt3__ext408__rt_request_collision_xecore0__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext408 :: RT INPUT MESSAGE RAY COUNT XECORE0 */
#define acmgt3__ext408__rt_input_message_ray_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext408 :: RT MESSAGE STALL COUNT XECORE0 */
#define acmgt3__ext408__rt_message_stall_count_xecore0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext408 :: RT TRANSFORM RAY COUNT XECORE0 */
#define acmgt3__ext408__rt_transform_ray_count_xecore0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext409 :: GPU Time Elapsed */
#define acmgt3__ext409__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext409 :: GPU Core Clocks */
#define acmgt3__ext409__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext409 :: AVG GPU Core Frequency */
#define acmgt3__ext409__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext409 :: AVG GPU Core Frequency */
#define acmgt3__ext409__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext409 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define acmgt3__ext409__rt_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext409 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1 */
#define acmgt3__ext409__rt_load_store_cache_write_from_message_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext409 :: RT TRAVERSAL INPUT RAY COUNT XECORE1 */
#define acmgt3__ext409__rt_traversal_input_ray_count_xecore1__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext409 :: RT QUAD TEST RAY COUNT XECORE1 */
#define acmgt3__ext409__rt_quad_test_ray_count_xecore1__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext409 :: RT REQUEST COLLISION XECORE1 */
#define acmgt3__ext409__rt_request_collision_xecore1__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext409 :: RT INPUT MESSAGE RAY COUNT XECORE1 */
#define acmgt3__ext409__rt_input_message_ray_count_xecore1__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext409 :: RT MESSAGE STALL COUNT XECORE1 */
#define acmgt3__ext409__rt_message_stall_count_xecore1__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext409 :: RT TRANSFORM RAY COUNT XECORE1 */
#define acmgt3__ext409__rt_transform_ray_count_xecore1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext410 :: GPU Time Elapsed */
#define acmgt3__ext410__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext410 :: GPU Core Clocks */
#define acmgt3__ext410__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext410 :: AVG GPU Core Frequency */
#define acmgt3__ext410__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext410 :: AVG GPU Core Frequency */
#define acmgt3__ext410__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext410 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define acmgt3__ext410__rt_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext410 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2 */
#define acmgt3__ext410__rt_load_store_cache_write_from_message_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext410 :: RT TRAVERSAL INPUT RAY COUNT XECORE2 */
#define acmgt3__ext410__rt_traversal_input_ray_count_xecore2__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext410 :: RT QUAD TEST RAY COUNT XECORE2 */
#define acmgt3__ext410__rt_quad_test_ray_count_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext410 :: RT REQUEST COLLISION XECORE2 */
#define acmgt3__ext410__rt_request_collision_xecore2__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext410 :: RT INPUT MESSAGE RAY COUNT XECORE2 */
#define acmgt3__ext410__rt_input_message_ray_count_xecore2__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext410 :: RT MESSAGE STALL COUNT XECORE2 */
#define acmgt3__ext410__rt_message_stall_count_xecore2__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext410 :: RT TRANSFORM RAY COUNT XECORE2 */
#define acmgt3__ext410__rt_transform_ray_count_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext411 :: GPU Time Elapsed */
#define acmgt3__ext411__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext411 :: GPU Core Clocks */
#define acmgt3__ext411__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext411 :: AVG GPU Core Frequency */
#define acmgt3__ext411__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext411 :: AVG GPU Core Frequency */
#define acmgt3__ext411__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext411 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define acmgt3__ext411__rt_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext411 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3 */
#define acmgt3__ext411__rt_load_store_cache_write_from_message_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext411 :: RT TRAVERSAL INPUT RAY COUNT XECORE3 */
#define acmgt3__ext411__rt_traversal_input_ray_count_xecore3__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext411 :: RT QUAD TEST RAY COUNT XECORE3 */
#define acmgt3__ext411__rt_quad_test_ray_count_xecore3__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext411 :: RT REQUEST COLLISION XECORE3 */
#define acmgt3__ext411__rt_request_collision_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext411 :: RT INPUT MESSAGE RAY COUNT XECORE3 */
#define acmgt3__ext411__rt_input_message_ray_count_xecore3__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext411 :: RT MESSAGE STALL COUNT XECORE3 */
#define acmgt3__ext411__rt_message_stall_count_xecore3__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext411 :: RT TRANSFORM RAY COUNT XECORE3 */
#define acmgt3__ext411__rt_transform_ray_count_xecore3__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext412 :: GPU Time Elapsed */
#define acmgt3__ext412__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext412 :: GPU Core Clocks */
#define acmgt3__ext412__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext412 :: AVG GPU Core Frequency */
#define acmgt3__ext412__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext412 :: AVG GPU Core Frequency */
#define acmgt3__ext412__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext412 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4 */
#define acmgt3__ext412__rt_load_store_cache_read_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext412 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4 */
#define acmgt3__ext412__rt_load_store_cache_write_from_message_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext412 :: RT TRAVERSAL INPUT RAY COUNT XECORE4 */
#define acmgt3__ext412__rt_traversal_input_ray_count_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext412 :: RT QUAD TEST RAY COUNT XECORE4 */
#define acmgt3__ext412__rt_quad_test_ray_count_xecore4__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext412 :: RT REQUEST COLLISION XECORE4 */
#define acmgt3__ext412__rt_request_collision_xecore4__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext412 :: RT INPUT MESSAGE RAY COUNT XECORE4 */
#define acmgt3__ext412__rt_input_message_ray_count_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext412 :: RT MESSAGE STALL COUNT XECORE4 */
#define acmgt3__ext412__rt_message_stall_count_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext412 :: RT TRANSFORM RAY COUNT XECORE4 */
#define acmgt3__ext412__rt_transform_ray_count_xecore4__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext413 :: GPU Time Elapsed */
#define acmgt3__ext413__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext413 :: GPU Core Clocks */
#define acmgt3__ext413__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext413 :: AVG GPU Core Frequency */
#define acmgt3__ext413__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext413 :: AVG GPU Core Frequency */
#define acmgt3__ext413__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext413 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5 */
#define acmgt3__ext413__rt_load_store_cache_read_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext413 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5 */
#define acmgt3__ext413__rt_load_store_cache_write_from_message_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext413 :: RT TRAVERSAL INPUT RAY COUNT XECORE5 */
#define acmgt3__ext413__rt_traversal_input_ray_count_xecore5__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext413 :: RT QUAD TEST RAY COUNT XECORE5 */
#define acmgt3__ext413__rt_quad_test_ray_count_xecore5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext413 :: RT REQUEST COLLISION XECORE5 */
#define acmgt3__ext413__rt_request_collision_xecore5__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext413 :: RT INPUT MESSAGE RAY COUNT XECORE5 */
#define acmgt3__ext413__rt_input_message_ray_count_xecore5__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext413 :: RT MESSAGE STALL COUNT XECORE5 */
#define acmgt3__ext413__rt_message_stall_count_xecore5__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext413 :: RT TRANSFORM RAY COUNT XECORE5 */
#define acmgt3__ext413__rt_transform_ray_count_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext414 :: GPU Time Elapsed */
#define acmgt3__ext414__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext414 :: GPU Core Clocks */
#define acmgt3__ext414__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext414 :: AVG GPU Core Frequency */
#define acmgt3__ext414__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext414 :: AVG GPU Core Frequency */
#define acmgt3__ext414__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext414 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6 */
#define acmgt3__ext414__rt_load_store_cache_read_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext414 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6 */
#define acmgt3__ext414__rt_load_store_cache_write_from_message_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext414 :: RT TRAVERSAL INPUT RAY COUNT XECORE6 */
#define acmgt3__ext414__rt_traversal_input_ray_count_xecore6__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext414 :: RT QUAD TEST RAY COUNT XECORE6 */
#define acmgt3__ext414__rt_quad_test_ray_count_xecore6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext414 :: RT REQUEST COLLISION XECORE6 */
#define acmgt3__ext414__rt_request_collision_xecore6__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext414 :: RT INPUT MESSAGE RAY COUNT XECORE6 */
#define acmgt3__ext414__rt_input_message_ray_count_xecore6__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext414 :: RT MESSAGE STALL COUNT XECORE6 */
#define acmgt3__ext414__rt_message_stall_count_xecore6__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext414 :: RT TRANSFORM RAY COUNT XECORE6 */
#define acmgt3__ext414__rt_transform_ray_count_xecore6__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext415 :: GPU Time Elapsed */
#define acmgt3__ext415__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext415 :: GPU Core Clocks */
#define acmgt3__ext415__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext415 :: AVG GPU Core Frequency */
#define acmgt3__ext415__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext415 :: AVG GPU Core Frequency */
#define acmgt3__ext415__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext415 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7 */
#define acmgt3__ext415__rt_load_store_cache_read_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext415 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7 */
#define acmgt3__ext415__rt_load_store_cache_write_from_message_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext415 :: RT TRAVERSAL INPUT RAY COUNT XECORE7 */
#define acmgt3__ext415__rt_traversal_input_ray_count_xecore7__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext415 :: RT QUAD TEST RAY COUNT XECORE7 */
#define acmgt3__ext415__rt_quad_test_ray_count_xecore7__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext415 :: RT REQUEST COLLISION XECORE7 */
#define acmgt3__ext415__rt_request_collision_xecore7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext415 :: RT INPUT MESSAGE RAY COUNT XECORE7 */
#define acmgt3__ext415__rt_input_message_ray_count_xecore7__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext415 :: RT MESSAGE STALL COUNT XECORE7 */
#define acmgt3__ext415__rt_message_stall_count_xecore7__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext415 :: RT TRANSFORM RAY COUNT XECORE7 */
#define acmgt3__ext415__rt_transform_ray_count_xecore7__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext416 :: GPU Time Elapsed */
#define acmgt3__ext416__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext416 :: GPU Core Clocks */
#define acmgt3__ext416__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext416 :: AVG GPU Core Frequency */
#define acmgt3__ext416__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext416 :: AVG GPU Core Frequency */
#define acmgt3__ext416__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext416 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE8 */
#define acmgt3__ext416__rt_load_store_cache_read_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext416 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE8 */
#define acmgt3__ext416__rt_load_store_cache_write_from_message_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext416 :: RT TRAVERSAL INPUT RAY COUNT XECORE8 */
#define acmgt3__ext416__rt_traversal_input_ray_count_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext416 :: RT QUAD TEST RAY COUNT XECORE8 */
#define acmgt3__ext416__rt_quad_test_ray_count_xecore8__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext416 :: RT REQUEST COLLISION XECORE8 */
#define acmgt3__ext416__rt_request_collision_xecore8__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext416 :: RT INPUT MESSAGE RAY COUNT XECORE8 */
#define acmgt3__ext416__rt_input_message_ray_count_xecore8__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext416 :: RT MESSAGE STALL COUNT XECORE8 */
#define acmgt3__ext416__rt_message_stall_count_xecore8__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext416 :: RT TRANSFORM RAY COUNT XECORE8 */
#define acmgt3__ext416__rt_transform_ray_count_xecore8__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext417 :: GPU Time Elapsed */
#define acmgt3__ext417__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext417 :: GPU Core Clocks */
#define acmgt3__ext417__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext417 :: AVG GPU Core Frequency */
#define acmgt3__ext417__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext417 :: AVG GPU Core Frequency */
#define acmgt3__ext417__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext417 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE9 */
#define acmgt3__ext417__rt_load_store_cache_read_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext417 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE9 */
#define acmgt3__ext417__rt_load_store_cache_write_from_message_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext417 :: RT TRAVERSAL INPUT RAY COUNT XECORE9 */
#define acmgt3__ext417__rt_traversal_input_ray_count_xecore9__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext417 :: RT QUAD TEST RAY COUNT XECORE9 */
#define acmgt3__ext417__rt_quad_test_ray_count_xecore9__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext417 :: RT REQUEST COLLISION XECORE9 */
#define acmgt3__ext417__rt_request_collision_xecore9__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext417 :: RT INPUT MESSAGE RAY COUNT XECORE9 */
#define acmgt3__ext417__rt_input_message_ray_count_xecore9__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext417 :: RT MESSAGE STALL COUNT XECORE9 */
#define acmgt3__ext417__rt_message_stall_count_xecore9__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext417 :: RT TRANSFORM RAY COUNT XECORE9 */
#define acmgt3__ext417__rt_transform_ray_count_xecore9__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext418 :: GPU Time Elapsed */
#define acmgt3__ext418__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext418 :: GPU Core Clocks */
#define acmgt3__ext418__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext418 :: AVG GPU Core Frequency */
#define acmgt3__ext418__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext418 :: AVG GPU Core Frequency */
#define acmgt3__ext418__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext418 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE10 */
#define acmgt3__ext418__rt_load_store_cache_read_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext418 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE10 */
#define acmgt3__ext418__rt_load_store_cache_write_from_message_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext418 :: RT TRAVERSAL INPUT RAY COUNT XECORE10 */
#define acmgt3__ext418__rt_traversal_input_ray_count_xecore10__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext418 :: RT QUAD TEST RAY COUNT XECORE10 */
#define acmgt3__ext418__rt_quad_test_ray_count_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext418 :: RT REQUEST COLLISION XECORE10 */
#define acmgt3__ext418__rt_request_collision_xecore10__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext418 :: RT INPUT MESSAGE RAY COUNT XECORE10 */
#define acmgt3__ext418__rt_input_message_ray_count_xecore10__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext418 :: RT MESSAGE STALL COUNT XECORE10 */
#define acmgt3__ext418__rt_message_stall_count_xecore10__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext418 :: RT TRANSFORM RAY COUNT XECORE10 */
#define acmgt3__ext418__rt_transform_ray_count_xecore10__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext419 :: GPU Time Elapsed */
#define acmgt3__ext419__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext419 :: GPU Core Clocks */
#define acmgt3__ext419__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext419 :: AVG GPU Core Frequency */
#define acmgt3__ext419__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext419 :: AVG GPU Core Frequency */
#define acmgt3__ext419__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext419 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE11 */
#define acmgt3__ext419__rt_load_store_cache_read_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext419 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE11 */
#define acmgt3__ext419__rt_load_store_cache_write_from_message_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext419 :: RT TRAVERSAL INPUT RAY COUNT XECORE11 */
#define acmgt3__ext419__rt_traversal_input_ray_count_xecore11__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext419 :: RT QUAD TEST RAY COUNT XECORE11 */
#define acmgt3__ext419__rt_quad_test_ray_count_xecore11__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext419 :: RT REQUEST COLLISION XECORE11 */
#define acmgt3__ext419__rt_request_collision_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext419 :: RT INPUT MESSAGE RAY COUNT XECORE11 */
#define acmgt3__ext419__rt_input_message_ray_count_xecore11__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext419 :: RT MESSAGE STALL COUNT XECORE11 */
#define acmgt3__ext419__rt_message_stall_count_xecore11__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext419 :: RT TRANSFORM RAY COUNT XECORE11 */
#define acmgt3__ext419__rt_transform_ray_count_xecore11__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext420 :: GPU Time Elapsed */
#define acmgt3__ext420__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext420 :: GPU Core Clocks */
#define acmgt3__ext420__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext420 :: AVG GPU Core Frequency */
#define acmgt3__ext420__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext420 :: AVG GPU Core Frequency */
#define acmgt3__ext420__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext420 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE12 */
#define acmgt3__ext420__rt_load_store_cache_read_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext420 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE12 */
#define acmgt3__ext420__rt_load_store_cache_write_from_message_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext420 :: RT TRAVERSAL INPUT RAY COUNT XECORE12 */
#define acmgt3__ext420__rt_traversal_input_ray_count_xecore12__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext420 :: RT QUAD TEST RAY COUNT XECORE12 */
#define acmgt3__ext420__rt_quad_test_ray_count_xecore12__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext420 :: RT REQUEST COLLISION XECORE12 */
#define acmgt3__ext420__rt_request_collision_xecore12__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext420 :: RT INPUT MESSAGE RAY COUNT XECORE12 */
#define acmgt3__ext420__rt_input_message_ray_count_xecore12__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext420 :: RT MESSAGE STALL COUNT XECORE12 */
#define acmgt3__ext420__rt_message_stall_count_xecore12__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext420 :: RT TRANSFORM RAY COUNT XECORE12 */
#define acmgt3__ext420__rt_transform_ray_count_xecore12__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext421 :: GPU Time Elapsed */
#define acmgt3__ext421__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext421 :: GPU Core Clocks */
#define acmgt3__ext421__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext421 :: AVG GPU Core Frequency */
#define acmgt3__ext421__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext421 :: AVG GPU Core Frequency */
#define acmgt3__ext421__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext421 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE13 */
#define acmgt3__ext421__rt_load_store_cache_read_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext421 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE13 */
#define acmgt3__ext421__rt_load_store_cache_write_from_message_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext421 :: RT TRAVERSAL INPUT RAY COUNT XECORE13 */
#define acmgt3__ext421__rt_traversal_input_ray_count_xecore13__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext421 :: RT QUAD TEST RAY COUNT XECORE13 */
#define acmgt3__ext421__rt_quad_test_ray_count_xecore13__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext421 :: RT REQUEST COLLISION XECORE13 */
#define acmgt3__ext421__rt_request_collision_xecore13__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext421 :: RT INPUT MESSAGE RAY COUNT XECORE13 */
#define acmgt3__ext421__rt_input_message_ray_count_xecore13__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext421 :: RT MESSAGE STALL COUNT XECORE13 */
#define acmgt3__ext421__rt_message_stall_count_xecore13__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext421 :: RT TRANSFORM RAY COUNT XECORE13 */
#define acmgt3__ext421__rt_transform_ray_count_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext422 :: GPU Time Elapsed */
#define acmgt3__ext422__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext422 :: GPU Core Clocks */
#define acmgt3__ext422__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext422 :: AVG GPU Core Frequency */
#define acmgt3__ext422__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext422 :: AVG GPU Core Frequency */
#define acmgt3__ext422__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext422 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE14 */
#define acmgt3__ext422__rt_load_store_cache_read_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext422 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE14 */
#define acmgt3__ext422__rt_load_store_cache_write_from_message_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext422 :: RT TRAVERSAL INPUT RAY COUNT XECORE14 */
#define acmgt3__ext422__rt_traversal_input_ray_count_xecore14__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext422 :: RT QUAD TEST RAY COUNT XECORE14 */
#define acmgt3__ext422__rt_quad_test_ray_count_xecore14__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext422 :: RT REQUEST COLLISION XECORE14 */
#define acmgt3__ext422__rt_request_collision_xecore14__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext422 :: RT INPUT MESSAGE RAY COUNT XECORE14 */
#define acmgt3__ext422__rt_input_message_ray_count_xecore14__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext422 :: RT MESSAGE STALL COUNT XECORE14 */
#define acmgt3__ext422__rt_message_stall_count_xecore14__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext422 :: RT TRANSFORM RAY COUNT XECORE14 */
#define acmgt3__ext422__rt_transform_ray_count_xecore14__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext423 :: GPU Time Elapsed */
#define acmgt3__ext423__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext423 :: GPU Core Clocks */
#define acmgt3__ext423__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext423 :: AVG GPU Core Frequency */
#define acmgt3__ext423__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext423 :: AVG GPU Core Frequency */
#define acmgt3__ext423__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext423 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE15 */
#define acmgt3__ext423__rt_load_store_cache_read_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext423 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE15 */
#define acmgt3__ext423__rt_load_store_cache_write_from_message_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext423 :: RT TRAVERSAL INPUT RAY COUNT XECORE15 */
#define acmgt3__ext423__rt_traversal_input_ray_count_xecore15__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext423 :: RT QUAD TEST RAY COUNT XECORE15 */
#define acmgt3__ext423__rt_quad_test_ray_count_xecore15__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext423 :: RT REQUEST COLLISION XECORE15 */
#define acmgt3__ext423__rt_request_collision_xecore15__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext423 :: RT INPUT MESSAGE RAY COUNT XECORE15 */
#define acmgt3__ext423__rt_input_message_ray_count_xecore15__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext423 :: RT MESSAGE STALL COUNT XECORE15 */
#define acmgt3__ext423__rt_message_stall_count_xecore15__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext423 :: RT TRANSFORM RAY COUNT XECORE15 */
#define acmgt3__ext423__rt_transform_ray_count_xecore15__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext424 :: GPU Time Elapsed */
#define acmgt3__ext424__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext424 :: GPU Core Clocks */
#define acmgt3__ext424__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext424 :: AVG GPU Core Frequency */
#define acmgt3__ext424__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext424 :: AVG GPU Core Frequency */
#define acmgt3__ext424__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext424 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE16 */
#define acmgt3__ext424__rt_load_store_cache_read_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext424 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE16 */
#define acmgt3__ext424__rt_load_store_cache_write_from_message_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext424 :: RT TRAVERSAL INPUT RAY COUNT XECORE16 */
#define acmgt3__ext424__rt_traversal_input_ray_count_xecore16__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext424 :: RT QUAD TEST RAY COUNT XECORE16 */
#define acmgt3__ext424__rt_quad_test_ray_count_xecore16__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext424 :: RT REQUEST COLLISION XECORE16 */
#define acmgt3__ext424__rt_request_collision_xecore16__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext424 :: RT INPUT MESSAGE RAY COUNT XECORE16 */
#define acmgt3__ext424__rt_input_message_ray_count_xecore16__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext424 :: RT MESSAGE STALL COUNT XECORE16 */
#define acmgt3__ext424__rt_message_stall_count_xecore16__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext424 :: RT TRANSFORM RAY COUNT XECORE16 */
#define acmgt3__ext424__rt_transform_ray_count_xecore16__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext425 :: GPU Time Elapsed */
#define acmgt3__ext425__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext425 :: GPU Core Clocks */
#define acmgt3__ext425__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext425 :: AVG GPU Core Frequency */
#define acmgt3__ext425__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext425 :: AVG GPU Core Frequency */
#define acmgt3__ext425__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext425 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE17 */
#define acmgt3__ext425__rt_load_store_cache_read_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext425 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE17 */
#define acmgt3__ext425__rt_load_store_cache_write_from_message_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext425 :: RT TRAVERSAL INPUT RAY COUNT XECORE17 */
#define acmgt3__ext425__rt_traversal_input_ray_count_xecore17__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext425 :: RT QUAD TEST RAY COUNT XECORE17 */
#define acmgt3__ext425__rt_quad_test_ray_count_xecore17__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext425 :: RT REQUEST COLLISION XECORE17 */
#define acmgt3__ext425__rt_request_collision_xecore17__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext425 :: RT INPUT MESSAGE RAY COUNT XECORE17 */
#define acmgt3__ext425__rt_input_message_ray_count_xecore17__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext425 :: RT MESSAGE STALL COUNT XECORE17 */
#define acmgt3__ext425__rt_message_stall_count_xecore17__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext425 :: RT TRANSFORM RAY COUNT XECORE17 */
#define acmgt3__ext425__rt_transform_ray_count_xecore17__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext426 :: GPU Time Elapsed */
#define acmgt3__ext426__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext426 :: GPU Core Clocks */
#define acmgt3__ext426__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext426 :: AVG GPU Core Frequency */
#define acmgt3__ext426__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext426 :: AVG GPU Core Frequency */
#define acmgt3__ext426__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext426 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE18 */
#define acmgt3__ext426__rt_load_store_cache_read_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext426 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE18 */
#define acmgt3__ext426__rt_load_store_cache_write_from_message_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext426 :: RT TRAVERSAL INPUT RAY COUNT XECORE18 */
#define acmgt3__ext426__rt_traversal_input_ray_count_xecore18__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext426 :: RT QUAD TEST RAY COUNT XECORE18 */
#define acmgt3__ext426__rt_quad_test_ray_count_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext426 :: RT REQUEST COLLISION XECORE18 */
#define acmgt3__ext426__rt_request_collision_xecore18__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext426 :: RT INPUT MESSAGE RAY COUNT XECORE18 */
#define acmgt3__ext426__rt_input_message_ray_count_xecore18__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext426 :: RT MESSAGE STALL COUNT XECORE18 */
#define acmgt3__ext426__rt_message_stall_count_xecore18__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext426 :: RT TRANSFORM RAY COUNT XECORE18 */
#define acmgt3__ext426__rt_transform_ray_count_xecore18__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext427 :: GPU Time Elapsed */
#define acmgt3__ext427__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext427 :: GPU Core Clocks */
#define acmgt3__ext427__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext427 :: AVG GPU Core Frequency */
#define acmgt3__ext427__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext427 :: AVG GPU Core Frequency */
#define acmgt3__ext427__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext427 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE19 */
#define acmgt3__ext427__rt_load_store_cache_read_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext427 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE19 */
#define acmgt3__ext427__rt_load_store_cache_write_from_message_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext427 :: RT TRAVERSAL INPUT RAY COUNT XECORE19 */
#define acmgt3__ext427__rt_traversal_input_ray_count_xecore19__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext427 :: RT QUAD TEST RAY COUNT XECORE19 */
#define acmgt3__ext427__rt_quad_test_ray_count_xecore19__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext427 :: RT REQUEST COLLISION XECORE19 */
#define acmgt3__ext427__rt_request_collision_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext427 :: RT INPUT MESSAGE RAY COUNT XECORE19 */
#define acmgt3__ext427__rt_input_message_ray_count_xecore19__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext427 :: RT MESSAGE STALL COUNT XECORE19 */
#define acmgt3__ext427__rt_message_stall_count_xecore19__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext427 :: RT TRANSFORM RAY COUNT XECORE19 */
#define acmgt3__ext427__rt_transform_ray_count_xecore19__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext428 :: GPU Time Elapsed */
#define acmgt3__ext428__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext428 :: GPU Core Clocks */
#define acmgt3__ext428__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext428 :: AVG GPU Core Frequency */
#define acmgt3__ext428__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext428 :: AVG GPU Core Frequency */
#define acmgt3__ext428__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext428 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE20 */
#define acmgt3__ext428__rt_load_store_cache_read_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext428 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE20 */
#define acmgt3__ext428__rt_load_store_cache_write_from_message_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext428 :: RT TRAVERSAL INPUT RAY COUNT XECORE20 */
#define acmgt3__ext428__rt_traversal_input_ray_count_xecore20__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext428 :: RT QUAD TEST RAY COUNT XECORE20 */
#define acmgt3__ext428__rt_quad_test_ray_count_xecore20__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext428 :: RT REQUEST COLLISION XECORE20 */
#define acmgt3__ext428__rt_request_collision_xecore20__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext428 :: RT INPUT MESSAGE RAY COUNT XECORE20 */
#define acmgt3__ext428__rt_input_message_ray_count_xecore20__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext428 :: RT MESSAGE STALL COUNT XECORE20 */
#define acmgt3__ext428__rt_message_stall_count_xecore20__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext428 :: RT TRANSFORM RAY COUNT XECORE20 */
#define acmgt3__ext428__rt_transform_ray_count_xecore20__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext429 :: GPU Time Elapsed */
#define acmgt3__ext429__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext429 :: GPU Core Clocks */
#define acmgt3__ext429__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext429 :: AVG GPU Core Frequency */
#define acmgt3__ext429__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext429 :: AVG GPU Core Frequency */
#define acmgt3__ext429__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext429 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE21 */
#define acmgt3__ext429__rt_load_store_cache_read_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext429 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE21 */
#define acmgt3__ext429__rt_load_store_cache_write_from_message_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext429 :: RT TRAVERSAL INPUT RAY COUNT XECORE21 */
#define acmgt3__ext429__rt_traversal_input_ray_count_xecore21__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext429 :: RT QUAD TEST RAY COUNT XECORE21 */
#define acmgt3__ext429__rt_quad_test_ray_count_xecore21__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext429 :: RT REQUEST COLLISION XECORE21 */
#define acmgt3__ext429__rt_request_collision_xecore21__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext429 :: RT INPUT MESSAGE RAY COUNT XECORE21 */
#define acmgt3__ext429__rt_input_message_ray_count_xecore21__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext429 :: RT MESSAGE STALL COUNT XECORE21 */
#define acmgt3__ext429__rt_message_stall_count_xecore21__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext429 :: RT TRANSFORM RAY COUNT XECORE21 */
#define acmgt3__ext429__rt_transform_ray_count_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext430 :: GPU Time Elapsed */
#define acmgt3__ext430__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext430 :: GPU Core Clocks */
#define acmgt3__ext430__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext430 :: AVG GPU Core Frequency */
#define acmgt3__ext430__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext430 :: AVG GPU Core Frequency */
#define acmgt3__ext430__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext430 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE22 */
#define acmgt3__ext430__rt_load_store_cache_read_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext430 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE22 */
#define acmgt3__ext430__rt_load_store_cache_write_from_message_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext430 :: RT TRAVERSAL INPUT RAY COUNT XECORE22 */
#define acmgt3__ext430__rt_traversal_input_ray_count_xecore22__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext430 :: RT QUAD TEST RAY COUNT XECORE22 */
#define acmgt3__ext430__rt_quad_test_ray_count_xecore22__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext430 :: RT REQUEST COLLISION XECORE22 */
#define acmgt3__ext430__rt_request_collision_xecore22__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext430 :: RT INPUT MESSAGE RAY COUNT XECORE22 */
#define acmgt3__ext430__rt_input_message_ray_count_xecore22__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext430 :: RT MESSAGE STALL COUNT XECORE22 */
#define acmgt3__ext430__rt_message_stall_count_xecore22__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext430 :: RT TRANSFORM RAY COUNT XECORE22 */
#define acmgt3__ext430__rt_transform_ray_count_xecore22__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext431 :: GPU Time Elapsed */
#define acmgt3__ext431__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext431 :: GPU Core Clocks */
#define acmgt3__ext431__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext431 :: AVG GPU Core Frequency */
#define acmgt3__ext431__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext431 :: AVG GPU Core Frequency */
#define acmgt3__ext431__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext431 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE23 */
#define acmgt3__ext431__rt_load_store_cache_read_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext431 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE23 */
#define acmgt3__ext431__rt_load_store_cache_write_from_message_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext431 :: RT TRAVERSAL INPUT RAY COUNT XECORE23 */
#define acmgt3__ext431__rt_traversal_input_ray_count_xecore23__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext431 :: RT QUAD TEST RAY COUNT XECORE23 */
#define acmgt3__ext431__rt_quad_test_ray_count_xecore23__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext431 :: RT REQUEST COLLISION XECORE23 */
#define acmgt3__ext431__rt_request_collision_xecore23__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext431 :: RT INPUT MESSAGE RAY COUNT XECORE23 */
#define acmgt3__ext431__rt_input_message_ray_count_xecore23__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext431 :: RT MESSAGE STALL COUNT XECORE23 */
#define acmgt3__ext431__rt_message_stall_count_xecore23__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext431 :: RT TRANSFORM RAY COUNT XECORE23 */
#define acmgt3__ext431__rt_transform_ray_count_xecore23__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext432 :: GPU Time Elapsed */
#define acmgt3__ext432__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext432 :: GPU Core Clocks */
#define acmgt3__ext432__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext432 :: AVG GPU Core Frequency */
#define acmgt3__ext432__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext432 :: AVG GPU Core Frequency */
#define acmgt3__ext432__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext432 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE24 */
#define acmgt3__ext432__rt_load_store_cache_read_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext432 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE24 */
#define acmgt3__ext432__rt_load_store_cache_write_from_message_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext432 :: RT TRAVERSAL INPUT RAY COUNT XECORE24 */
#define acmgt3__ext432__rt_traversal_input_ray_count_xecore24__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext432 :: RT QUAD TEST RAY COUNT XECORE24 */
#define acmgt3__ext432__rt_quad_test_ray_count_xecore24__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext432 :: RT REQUEST COLLISION XECORE24 */
#define acmgt3__ext432__rt_request_collision_xecore24__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext432 :: RT INPUT MESSAGE RAY COUNT XECORE24 */
#define acmgt3__ext432__rt_input_message_ray_count_xecore24__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext432 :: RT MESSAGE STALL COUNT XECORE24 */
#define acmgt3__ext432__rt_message_stall_count_xecore24__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext432 :: RT TRANSFORM RAY COUNT XECORE24 */
#define acmgt3__ext432__rt_transform_ray_count_xecore24__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext433 :: GPU Time Elapsed */
#define acmgt3__ext433__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext433 :: GPU Core Clocks */
#define acmgt3__ext433__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext433 :: AVG GPU Core Frequency */
#define acmgt3__ext433__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext433 :: AVG GPU Core Frequency */
#define acmgt3__ext433__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext433 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE25 */
#define acmgt3__ext433__rt_load_store_cache_read_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext433 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE25 */
#define acmgt3__ext433__rt_load_store_cache_write_from_message_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext433 :: RT TRAVERSAL INPUT RAY COUNT XECORE25 */
#define acmgt3__ext433__rt_traversal_input_ray_count_xecore25__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext433 :: RT QUAD TEST RAY COUNT XECORE25 */
#define acmgt3__ext433__rt_quad_test_ray_count_xecore25__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext433 :: RT REQUEST COLLISION XECORE25 */
#define acmgt3__ext433__rt_request_collision_xecore25__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext433 :: RT INPUT MESSAGE RAY COUNT XECORE25 */
#define acmgt3__ext433__rt_input_message_ray_count_xecore25__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext433 :: RT MESSAGE STALL COUNT XECORE25 */
#define acmgt3__ext433__rt_message_stall_count_xecore25__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext433 :: RT TRANSFORM RAY COUNT XECORE25 */
#define acmgt3__ext433__rt_transform_ray_count_xecore25__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext434 :: GPU Time Elapsed */
#define acmgt3__ext434__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext434 :: GPU Core Clocks */
#define acmgt3__ext434__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext434 :: AVG GPU Core Frequency */
#define acmgt3__ext434__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext434 :: AVG GPU Core Frequency */
#define acmgt3__ext434__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext434 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE26 */
#define acmgt3__ext434__rt_load_store_cache_read_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext434 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE26 */
#define acmgt3__ext434__rt_load_store_cache_write_from_message_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext434 :: RT TRAVERSAL INPUT RAY COUNT XECORE26 */
#define acmgt3__ext434__rt_traversal_input_ray_count_xecore26__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext434 :: RT QUAD TEST RAY COUNT XECORE26 */
#define acmgt3__ext434__rt_quad_test_ray_count_xecore26__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext434 :: RT REQUEST COLLISION XECORE26 */
#define acmgt3__ext434__rt_request_collision_xecore26__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext434 :: RT INPUT MESSAGE RAY COUNT XECORE26 */
#define acmgt3__ext434__rt_input_message_ray_count_xecore26__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext434 :: RT MESSAGE STALL COUNT XECORE26 */
#define acmgt3__ext434__rt_message_stall_count_xecore26__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext434 :: RT TRANSFORM RAY COUNT XECORE26 */
#define acmgt3__ext434__rt_transform_ray_count_xecore26__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext435 :: GPU Time Elapsed */
#define acmgt3__ext435__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext435 :: GPU Core Clocks */
#define acmgt3__ext435__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext435 :: AVG GPU Core Frequency */
#define acmgt3__ext435__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext435 :: AVG GPU Core Frequency */
#define acmgt3__ext435__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext435 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE27 */
#define acmgt3__ext435__rt_load_store_cache_read_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext435 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE27 */
#define acmgt3__ext435__rt_load_store_cache_write_from_message_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext435 :: RT TRAVERSAL INPUT RAY COUNT XECORE27 */
#define acmgt3__ext435__rt_traversal_input_ray_count_xecore27__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext435 :: RT QUAD TEST RAY COUNT XECORE27 */
#define acmgt3__ext435__rt_quad_test_ray_count_xecore27__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext435 :: RT REQUEST COLLISION XECORE27 */
#define acmgt3__ext435__rt_request_collision_xecore27__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext435 :: RT INPUT MESSAGE RAY COUNT XECORE27 */
#define acmgt3__ext435__rt_input_message_ray_count_xecore27__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext435 :: RT MESSAGE STALL COUNT XECORE27 */
#define acmgt3__ext435__rt_message_stall_count_xecore27__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext435 :: RT TRANSFORM RAY COUNT XECORE27 */
#define acmgt3__ext435__rt_transform_ray_count_xecore27__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext436 :: GPU Time Elapsed */
#define acmgt3__ext436__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext436 :: GPU Core Clocks */
#define acmgt3__ext436__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext436 :: AVG GPU Core Frequency */
#define acmgt3__ext436__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext436 :: AVG GPU Core Frequency */
#define acmgt3__ext436__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext436 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE28 */
#define acmgt3__ext436__rt_load_store_cache_read_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext436 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE28 */
#define acmgt3__ext436__rt_load_store_cache_write_from_message_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext436 :: RT TRAVERSAL INPUT RAY COUNT XECORE28 */
#define acmgt3__ext436__rt_traversal_input_ray_count_xecore28__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext436 :: RT QUAD TEST RAY COUNT XECORE28 */
#define acmgt3__ext436__rt_quad_test_ray_count_xecore28__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext436 :: RT REQUEST COLLISION XECORE28 */
#define acmgt3__ext436__rt_request_collision_xecore28__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext436 :: RT INPUT MESSAGE RAY COUNT XECORE28 */
#define acmgt3__ext436__rt_input_message_ray_count_xecore28__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext436 :: RT MESSAGE STALL COUNT XECORE28 */
#define acmgt3__ext436__rt_message_stall_count_xecore28__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext436 :: RT TRANSFORM RAY COUNT XECORE28 */
#define acmgt3__ext436__rt_transform_ray_count_xecore28__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext437 :: GPU Time Elapsed */
#define acmgt3__ext437__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext437 :: GPU Core Clocks */
#define acmgt3__ext437__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext437 :: AVG GPU Core Frequency */
#define acmgt3__ext437__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext437 :: AVG GPU Core Frequency */
#define acmgt3__ext437__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext437 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE29 */
#define acmgt3__ext437__rt_load_store_cache_read_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext437 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE29 */
#define acmgt3__ext437__rt_load_store_cache_write_from_message_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext437 :: RT TRAVERSAL INPUT RAY COUNT XECORE29 */
#define acmgt3__ext437__rt_traversal_input_ray_count_xecore29__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext437 :: RT QUAD TEST RAY COUNT XECORE29 */
#define acmgt3__ext437__rt_quad_test_ray_count_xecore29__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext437 :: RT REQUEST COLLISION XECORE29 */
#define acmgt3__ext437__rt_request_collision_xecore29__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext437 :: RT INPUT MESSAGE RAY COUNT XECORE29 */
#define acmgt3__ext437__rt_input_message_ray_count_xecore29__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext437 :: RT MESSAGE STALL COUNT XECORE29 */
#define acmgt3__ext437__rt_message_stall_count_xecore29__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext437 :: RT TRANSFORM RAY COUNT XECORE29 */
#define acmgt3__ext437__rt_transform_ray_count_xecore29__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext438 :: GPU Time Elapsed */
#define acmgt3__ext438__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext438 :: GPU Core Clocks */
#define acmgt3__ext438__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext438 :: AVG GPU Core Frequency */
#define acmgt3__ext438__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext438 :: AVG GPU Core Frequency */
#define acmgt3__ext438__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext438 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE30 */
#define acmgt3__ext438__rt_load_store_cache_read_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext438 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE30 */
#define acmgt3__ext438__rt_load_store_cache_write_from_message_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext438 :: RT TRAVERSAL INPUT RAY COUNT XECORE30 */
#define acmgt3__ext438__rt_traversal_input_ray_count_xecore30__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext438 :: RT QUAD TEST RAY COUNT XECORE30 */
#define acmgt3__ext438__rt_quad_test_ray_count_xecore30__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext438 :: RT REQUEST COLLISION XECORE30 */
#define acmgt3__ext438__rt_request_collision_xecore30__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext438 :: RT INPUT MESSAGE RAY COUNT XECORE30 */
#define acmgt3__ext438__rt_input_message_ray_count_xecore30__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext438 :: RT MESSAGE STALL COUNT XECORE30 */
#define acmgt3__ext438__rt_message_stall_count_xecore30__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext438 :: RT TRANSFORM RAY COUNT XECORE30 */
#define acmgt3__ext438__rt_transform_ray_count_xecore30__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext439 :: GPU Time Elapsed */
#define acmgt3__ext439__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext439 :: GPU Core Clocks */
#define acmgt3__ext439__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext439 :: AVG GPU Core Frequency */
#define acmgt3__ext439__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext439 :: AVG GPU Core Frequency */
#define acmgt3__ext439__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext439 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE31 */
#define acmgt3__ext439__rt_load_store_cache_read_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext439 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE31 */
#define acmgt3__ext439__rt_load_store_cache_write_from_message_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext439 :: RT TRAVERSAL INPUT RAY COUNT XECORE31 */
#define acmgt3__ext439__rt_traversal_input_ray_count_xecore31__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext439 :: RT QUAD TEST RAY COUNT XECORE31 */
#define acmgt3__ext439__rt_quad_test_ray_count_xecore31__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext439 :: RT REQUEST COLLISION XECORE31 */
#define acmgt3__ext439__rt_request_collision_xecore31__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext439 :: RT INPUT MESSAGE RAY COUNT XECORE31 */
#define acmgt3__ext439__rt_input_message_ray_count_xecore31__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext439 :: RT MESSAGE STALL COUNT XECORE31 */
#define acmgt3__ext439__rt_message_stall_count_xecore31__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext439 :: RT TRANSFORM RAY COUNT XECORE31 */
#define acmgt3__ext439__rt_transform_ray_count_xecore31__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext440 :: GPU Time Elapsed */
#define acmgt3__ext440__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext440 :: GPU Core Clocks */
#define acmgt3__ext440__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext440 :: AVG GPU Core Frequency */
#define acmgt3__ext440__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext440 :: AVG GPU Core Frequency */
#define acmgt3__ext440__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext440 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE0 */
#define acmgt3__ext440__rt_traversal_output_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext440 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE1 */
#define acmgt3__ext440__rt_traversal_output_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext440 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE2 */
#define acmgt3__ext440__rt_traversal_output_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext440 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE3 */
#define acmgt3__ext440__rt_traversal_output_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext441 :: GPU Time Elapsed */
#define acmgt3__ext441__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext441 :: GPU Core Clocks */
#define acmgt3__ext441__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext441 :: AVG GPU Core Frequency */
#define acmgt3__ext441__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext441 :: AVG GPU Core Frequency */
#define acmgt3__ext441__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext441 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE4 */
#define acmgt3__ext441__rt_traversal_output_ray_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext441 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE5 */
#define acmgt3__ext441__rt_traversal_output_ray_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext441 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE6 */
#define acmgt3__ext441__rt_traversal_output_ray_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext441 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE7 */
#define acmgt3__ext441__rt_traversal_output_ray_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext442 :: GPU Time Elapsed */
#define acmgt3__ext442__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext442 :: GPU Core Clocks */
#define acmgt3__ext442__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext442 :: AVG GPU Core Frequency */
#define acmgt3__ext442__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext442 :: AVG GPU Core Frequency */
#define acmgt3__ext442__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext442 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE8 */
#define acmgt3__ext442__rt_traversal_output_ray_count_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext442 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE9 */
#define acmgt3__ext442__rt_traversal_output_ray_count_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext442 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE10 */
#define acmgt3__ext442__rt_traversal_output_ray_count_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext442 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE11 */
#define acmgt3__ext442__rt_traversal_output_ray_count_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext443 :: GPU Time Elapsed */
#define acmgt3__ext443__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext443 :: GPU Core Clocks */
#define acmgt3__ext443__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext443 :: AVG GPU Core Frequency */
#define acmgt3__ext443__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext443 :: AVG GPU Core Frequency */
#define acmgt3__ext443__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext443 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE12 */
#define acmgt3__ext443__rt_traversal_output_ray_count_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext443 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE13 */
#define acmgt3__ext443__rt_traversal_output_ray_count_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext443 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE14 */
#define acmgt3__ext443__rt_traversal_output_ray_count_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext443 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE15 */
#define acmgt3__ext443__rt_traversal_output_ray_count_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext444 :: GPU Time Elapsed */
#define acmgt3__ext444__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext444 :: GPU Core Clocks */
#define acmgt3__ext444__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext444 :: AVG GPU Core Frequency */
#define acmgt3__ext444__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext444 :: AVG GPU Core Frequency */
#define acmgt3__ext444__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext444 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE16 */
#define acmgt3__ext444__rt_traversal_output_ray_count_xecore16__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext444 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE17 */
#define acmgt3__ext444__rt_traversal_output_ray_count_xecore17__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext444 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE18 */
#define acmgt3__ext444__rt_traversal_output_ray_count_xecore18__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext444 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE19 */
#define acmgt3__ext444__rt_traversal_output_ray_count_xecore19__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext445 :: GPU Time Elapsed */
#define acmgt3__ext445__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext445 :: GPU Core Clocks */
#define acmgt3__ext445__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext445 :: AVG GPU Core Frequency */
#define acmgt3__ext445__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext445 :: AVG GPU Core Frequency */
#define acmgt3__ext445__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext445 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE20 */
#define acmgt3__ext445__rt_traversal_output_ray_count_xecore20__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext445 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE21 */
#define acmgt3__ext445__rt_traversal_output_ray_count_xecore21__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext445 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE22 */
#define acmgt3__ext445__rt_traversal_output_ray_count_xecore22__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext445 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE23 */
#define acmgt3__ext445__rt_traversal_output_ray_count_xecore23__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext446 :: GPU Time Elapsed */
#define acmgt3__ext446__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext446 :: GPU Core Clocks */
#define acmgt3__ext446__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext446 :: AVG GPU Core Frequency */
#define acmgt3__ext446__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext446 :: AVG GPU Core Frequency */
#define acmgt3__ext446__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext446 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE24 */
#define acmgt3__ext446__rt_traversal_output_ray_count_xecore24__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext446 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE25 */
#define acmgt3__ext446__rt_traversal_output_ray_count_xecore25__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext446 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE26 */
#define acmgt3__ext446__rt_traversal_output_ray_count_xecore26__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext446 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE27 */
#define acmgt3__ext446__rt_traversal_output_ray_count_xecore27__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext447 :: GPU Time Elapsed */
#define acmgt3__ext447__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext447 :: GPU Core Clocks */
#define acmgt3__ext447__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext447 :: AVG GPU Core Frequency */
#define acmgt3__ext447__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext447 :: AVG GPU Core Frequency */
#define acmgt3__ext447__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext447 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE28 */
#define acmgt3__ext447__rt_traversal_output_ray_count_xecore28__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext447 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE29 */
#define acmgt3__ext447__rt_traversal_output_ray_count_xecore29__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext447 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE30 */
#define acmgt3__ext447__rt_traversal_output_ray_count_xecore30__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext447 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE31 */
#define acmgt3__ext447__rt_traversal_output_ray_count_xecore31__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext448 :: GPU Time Elapsed */
#define acmgt3__ext448__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext448 :: GPU Core Clocks */
#define acmgt3__ext448__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext448 :: AVG GPU Core Frequency */
#define acmgt3__ext448__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext448 :: AVG GPU Core Frequency */
#define acmgt3__ext448__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext448 :: RT ANY HIT THREAD RAY DISPATCH XECORE0 */
#define acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext448 :: RT ANY HIT THREAD RAY DISPATCH XECORE1 */
#define acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext448 :: RT ANY HIT THREAD RAY DISPATCH XECORE2 */
#define acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext448 :: RT ANY HIT THREAD RAY DISPATCH XECORE3 */
#define acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext449 :: GPU Time Elapsed */
#define acmgt3__ext449__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext449 :: GPU Core Clocks */
#define acmgt3__ext449__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext449 :: AVG GPU Core Frequency */
#define acmgt3__ext449__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext449 :: AVG GPU Core Frequency */
#define acmgt3__ext449__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext449 :: RT ANY HIT THREAD RAY DISPATCH XECORE4 */
#define acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext449 :: RT ANY HIT THREAD RAY DISPATCH XECORE5 */
#define acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext449 :: RT ANY HIT THREAD RAY DISPATCH XECORE6 */
#define acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext449 :: RT ANY HIT THREAD RAY DISPATCH XECORE7 */
#define acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext450 :: GPU Time Elapsed */
#define acmgt3__ext450__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext450 :: GPU Core Clocks */
#define acmgt3__ext450__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext450 :: AVG GPU Core Frequency */
#define acmgt3__ext450__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext450 :: AVG GPU Core Frequency */
#define acmgt3__ext450__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext450 :: RT ANY HIT THREAD RAY DISPATCH XECORE8 */
#define acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext450 :: RT ANY HIT THREAD RAY DISPATCH XECORE9 */
#define acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext450 :: RT ANY HIT THREAD RAY DISPATCH XECORE10 */
#define acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext450 :: RT ANY HIT THREAD RAY DISPATCH XECORE11 */
#define acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext451 :: GPU Time Elapsed */
#define acmgt3__ext451__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext451 :: GPU Core Clocks */
#define acmgt3__ext451__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext451 :: AVG GPU Core Frequency */
#define acmgt3__ext451__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext451 :: AVG GPU Core Frequency */
#define acmgt3__ext451__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext451 :: RT ANY HIT THREAD RAY DISPATCH XECORE12 */
#define acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext451 :: RT ANY HIT THREAD RAY DISPATCH XECORE13 */
#define acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext451 :: RT ANY HIT THREAD RAY DISPATCH XECORE14 */
#define acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext451 :: RT ANY HIT THREAD RAY DISPATCH XECORE15 */
#define acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext452 :: GPU Time Elapsed */
#define acmgt3__ext452__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext452 :: GPU Core Clocks */
#define acmgt3__ext452__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext452 :: AVG GPU Core Frequency */
#define acmgt3__ext452__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext452 :: AVG GPU Core Frequency */
#define acmgt3__ext452__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext452 :: RT ANY HIT THREAD RAY DISPATCH XECORE16 */
#define acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore16__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext452 :: RT ANY HIT THREAD RAY DISPATCH XECORE17 */
#define acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore17__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext452 :: RT ANY HIT THREAD RAY DISPATCH XECORE18 */
#define acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore18__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext452 :: RT ANY HIT THREAD RAY DISPATCH XECORE19 */
#define acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore19__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext453 :: GPU Time Elapsed */
#define acmgt3__ext453__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext453 :: GPU Core Clocks */
#define acmgt3__ext453__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext453 :: AVG GPU Core Frequency */
#define acmgt3__ext453__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext453 :: AVG GPU Core Frequency */
#define acmgt3__ext453__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext453 :: RT ANY HIT THREAD RAY DISPATCH XECORE20 */
#define acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore20__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext453 :: RT ANY HIT THREAD RAY DISPATCH XECORE21 */
#define acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore21__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext453 :: RT ANY HIT THREAD RAY DISPATCH XECORE22 */
#define acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore22__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext453 :: RT ANY HIT THREAD RAY DISPATCH XECORE23 */
#define acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore23__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext454 :: GPU Time Elapsed */
#define acmgt3__ext454__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext454 :: GPU Core Clocks */
#define acmgt3__ext454__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext454 :: AVG GPU Core Frequency */
#define acmgt3__ext454__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext454 :: AVG GPU Core Frequency */
#define acmgt3__ext454__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext454 :: RT ANY HIT THREAD RAY DISPATCH XECORE24 */
#define acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore24__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext454 :: RT ANY HIT THREAD RAY DISPATCH XECORE25 */
#define acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore25__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext454 :: RT ANY HIT THREAD RAY DISPATCH XECORE26 */
#define acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore26__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext454 :: RT ANY HIT THREAD RAY DISPATCH XECORE27 */
#define acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore27__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext455 :: GPU Time Elapsed */
#define acmgt3__ext455__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext455 :: GPU Core Clocks */
#define acmgt3__ext455__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext455 :: AVG GPU Core Frequency */
#define acmgt3__ext455__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext455 :: AVG GPU Core Frequency */
#define acmgt3__ext455__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext455 :: RT ANY HIT THREAD RAY DISPATCH XECORE28 */
#define acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore28__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext455 :: RT ANY HIT THREAD RAY DISPATCH XECORE29 */
#define acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore29__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext455 :: RT ANY HIT THREAD RAY DISPATCH XECORE30 */
#define acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore30__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext455 :: RT ANY HIT THREAD RAY DISPATCH XECORE31 */
#define acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore31__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext456 :: GPU Time Elapsed */
#define acmgt3__ext456__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext456 :: GPU Core Clocks */
#define acmgt3__ext456__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext456 :: AVG GPU Core Frequency */
#define acmgt3__ext456__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext456 :: AVG GPU Core Frequency */
#define acmgt3__ext456__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext456 :: RT CALLABLE THREAD RAY DISPATCH XECORE0 */
#define acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext456 :: RT CALLABLE THREAD RAY DISPATCH XECORE1 */
#define acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext456 :: RT CALLABLE THREAD RAY DISPATCH XECORE2 */
#define acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext456 :: RT CALLABLE THREAD RAY DISPATCH XECORE3 */
#define acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext457 :: GPU Time Elapsed */
#define acmgt3__ext457__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext457 :: GPU Core Clocks */
#define acmgt3__ext457__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext457 :: AVG GPU Core Frequency */
#define acmgt3__ext457__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext457 :: AVG GPU Core Frequency */
#define acmgt3__ext457__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext457 :: RT CALLABLE THREAD RAY DISPATCH XECORE4 */
#define acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext457 :: RT CALLABLE THREAD RAY DISPATCH XECORE5 */
#define acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext457 :: RT CALLABLE THREAD RAY DISPATCH XECORE6 */
#define acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext457 :: RT CALLABLE THREAD RAY DISPATCH XECORE7 */
#define acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext458 :: GPU Time Elapsed */
#define acmgt3__ext458__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext458 :: GPU Core Clocks */
#define acmgt3__ext458__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext458 :: AVG GPU Core Frequency */
#define acmgt3__ext458__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext458 :: AVG GPU Core Frequency */
#define acmgt3__ext458__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext458 :: RT CALLABLE THREAD RAY DISPATCH XECORE8 */
#define acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext458 :: RT CALLABLE THREAD RAY DISPATCH XECORE9 */
#define acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext458 :: RT CALLABLE THREAD RAY DISPATCH XECORE10 */
#define acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext458 :: RT CALLABLE THREAD RAY DISPATCH XECORE11 */
#define acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext459 :: GPU Time Elapsed */
#define acmgt3__ext459__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext459 :: GPU Core Clocks */
#define acmgt3__ext459__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext459 :: AVG GPU Core Frequency */
#define acmgt3__ext459__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext459 :: AVG GPU Core Frequency */
#define acmgt3__ext459__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext459 :: RT CALLABLE THREAD RAY DISPATCH XECORE12 */
#define acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext459 :: RT CALLABLE THREAD RAY DISPATCH XECORE13 */
#define acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext459 :: RT CALLABLE THREAD RAY DISPATCH XECORE14 */
#define acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext459 :: RT CALLABLE THREAD RAY DISPATCH XECORE15 */
#define acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext460 :: GPU Time Elapsed */
#define acmgt3__ext460__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext460 :: GPU Core Clocks */
#define acmgt3__ext460__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext460 :: AVG GPU Core Frequency */
#define acmgt3__ext460__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext460 :: AVG GPU Core Frequency */
#define acmgt3__ext460__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext460 :: RT CALLABLE THREAD RAY DISPATCH XECORE16 */
#define acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore16__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext460 :: RT CALLABLE THREAD RAY DISPATCH XECORE17 */
#define acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore17__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext460 :: RT CALLABLE THREAD RAY DISPATCH XECORE18 */
#define acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore18__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext460 :: RT CALLABLE THREAD RAY DISPATCH XECORE19 */
#define acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore19__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext461 :: GPU Time Elapsed */
#define acmgt3__ext461__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext461 :: GPU Core Clocks */
#define acmgt3__ext461__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext461 :: AVG GPU Core Frequency */
#define acmgt3__ext461__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext461 :: AVG GPU Core Frequency */
#define acmgt3__ext461__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext461 :: RT CALLABLE THREAD RAY DISPATCH XECORE20 */
#define acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore20__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext461 :: RT CALLABLE THREAD RAY DISPATCH XECORE21 */
#define acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore21__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext461 :: RT CALLABLE THREAD RAY DISPATCH XECORE22 */
#define acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore22__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext461 :: RT CALLABLE THREAD RAY DISPATCH XECORE23 */
#define acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore23__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext462 :: GPU Time Elapsed */
#define acmgt3__ext462__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext462 :: GPU Core Clocks */
#define acmgt3__ext462__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext462 :: AVG GPU Core Frequency */
#define acmgt3__ext462__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext462 :: AVG GPU Core Frequency */
#define acmgt3__ext462__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext462 :: RT CALLABLE THREAD RAY DISPATCH XECORE24 */
#define acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore24__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext462 :: RT CALLABLE THREAD RAY DISPATCH XECORE25 */
#define acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore25__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext462 :: RT CALLABLE THREAD RAY DISPATCH XECORE26 */
#define acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore26__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext462 :: RT CALLABLE THREAD RAY DISPATCH XECORE27 */
#define acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore27__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext463 :: GPU Time Elapsed */
#define acmgt3__ext463__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext463 :: GPU Core Clocks */
#define acmgt3__ext463__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext463 :: AVG GPU Core Frequency */
#define acmgt3__ext463__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext463 :: AVG GPU Core Frequency */
#define acmgt3__ext463__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext463 :: RT CALLABLE THREAD RAY DISPATCH XECORE28 */
#define acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore28__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext463 :: RT CALLABLE THREAD RAY DISPATCH XECORE29 */
#define acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore29__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext463 :: RT CALLABLE THREAD RAY DISPATCH XECORE30 */
#define acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore30__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext463 :: RT CALLABLE THREAD RAY DISPATCH XECORE31 */
#define acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore31__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext464 :: GPU Time Elapsed */
#define acmgt3__ext464__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext464 :: GPU Core Clocks */
#define acmgt3__ext464__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext464 :: AVG GPU Core Frequency */
#define acmgt3__ext464__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext464 :: AVG GPU Core Frequency */
#define acmgt3__ext464__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext464 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE0 */
#define acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext464 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE1 */
#define acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext464 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE2 */
#define acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext464 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE3 */
#define acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext465 :: GPU Time Elapsed */
#define acmgt3__ext465__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext465 :: GPU Core Clocks */
#define acmgt3__ext465__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext465 :: AVG GPU Core Frequency */
#define acmgt3__ext465__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext465 :: AVG GPU Core Frequency */
#define acmgt3__ext465__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext465 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE4 */
#define acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext465 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE5 */
#define acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext465 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE6 */
#define acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext465 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE7 */
#define acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext466 :: GPU Time Elapsed */
#define acmgt3__ext466__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext466 :: GPU Core Clocks */
#define acmgt3__ext466__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext466 :: AVG GPU Core Frequency */
#define acmgt3__ext466__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext466 :: AVG GPU Core Frequency */
#define acmgt3__ext466__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext466 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE8 */
#define acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext466 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE9 */
#define acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext466 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE10 */
#define acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext466 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE11 */
#define acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext467 :: GPU Time Elapsed */
#define acmgt3__ext467__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext467 :: GPU Core Clocks */
#define acmgt3__ext467__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext467 :: AVG GPU Core Frequency */
#define acmgt3__ext467__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext467 :: AVG GPU Core Frequency */
#define acmgt3__ext467__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext467 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE12 */
#define acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext467 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE13 */
#define acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext467 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE14 */
#define acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext467 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE15 */
#define acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext468 :: GPU Time Elapsed */
#define acmgt3__ext468__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext468 :: GPU Core Clocks */
#define acmgt3__ext468__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext468 :: AVG GPU Core Frequency */
#define acmgt3__ext468__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext468 :: AVG GPU Core Frequency */
#define acmgt3__ext468__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext468 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE16 */
#define acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore16__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext468 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE17 */
#define acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore17__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext468 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE18 */
#define acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore18__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext468 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE19 */
#define acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore19__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext469 :: GPU Time Elapsed */
#define acmgt3__ext469__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext469 :: GPU Core Clocks */
#define acmgt3__ext469__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext469 :: AVG GPU Core Frequency */
#define acmgt3__ext469__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext469 :: AVG GPU Core Frequency */
#define acmgt3__ext469__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext469 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE20 */
#define acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore20__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext469 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE21 */
#define acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore21__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext469 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE22 */
#define acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore22__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext469 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE23 */
#define acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore23__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext470 :: GPU Time Elapsed */
#define acmgt3__ext470__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext470 :: GPU Core Clocks */
#define acmgt3__ext470__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext470 :: AVG GPU Core Frequency */
#define acmgt3__ext470__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext470 :: AVG GPU Core Frequency */
#define acmgt3__ext470__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext470 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE24 */
#define acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore24__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext470 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE25 */
#define acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore25__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext470 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE26 */
#define acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore26__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext470 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE27 */
#define acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore27__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext471 :: GPU Time Elapsed */
#define acmgt3__ext471__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext471 :: GPU Core Clocks */
#define acmgt3__ext471__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext471 :: AVG GPU Core Frequency */
#define acmgt3__ext471__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext471 :: AVG GPU Core Frequency */
#define acmgt3__ext471__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext471 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE28 */
#define acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore28__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext471 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE29 */
#define acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore29__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext471 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE30 */
#define acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore30__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext471 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE31 */
#define acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore31__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext472 :: GPU Time Elapsed */
#define acmgt3__ext472__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext472 :: GPU Core Clocks */
#define acmgt3__ext472__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext472 :: AVG GPU Core Frequency */
#define acmgt3__ext472__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext472 :: AVG GPU Core Frequency */
#define acmgt3__ext472__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext472 :: RT INTERSECTION THREAD RAY DISPATCH XECORE0 */
#define acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext472 :: RT INTERSECTION THREAD RAY DISPATCH XECORE1 */
#define acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext472 :: RT INTERSECTION THREAD RAY DISPATCH XECORE2 */
#define acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext472 :: RT INTERSECTION THREAD RAY DISPATCH XECORE3 */
#define acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext473 :: GPU Time Elapsed */
#define acmgt3__ext473__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext473 :: GPU Core Clocks */
#define acmgt3__ext473__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext473 :: AVG GPU Core Frequency */
#define acmgt3__ext473__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext473 :: AVG GPU Core Frequency */
#define acmgt3__ext473__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext473 :: RT INTERSECTION THREAD RAY DISPATCH XECORE4 */
#define acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext473 :: RT INTERSECTION THREAD RAY DISPATCH XECORE5 */
#define acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext473 :: RT INTERSECTION THREAD RAY DISPATCH XECORE6 */
#define acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext473 :: RT INTERSECTION THREAD RAY DISPATCH XECORE7 */
#define acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext474 :: GPU Time Elapsed */
#define acmgt3__ext474__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext474 :: GPU Core Clocks */
#define acmgt3__ext474__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext474 :: AVG GPU Core Frequency */
#define acmgt3__ext474__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext474 :: AVG GPU Core Frequency */
#define acmgt3__ext474__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext474 :: RT INTERSECTION THREAD RAY DISPATCH XECORE8 */
#define acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext474 :: RT INTERSECTION THREAD RAY DISPATCH XECORE9 */
#define acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext474 :: RT INTERSECTION THREAD RAY DISPATCH XECORE10 */
#define acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext474 :: RT INTERSECTION THREAD RAY DISPATCH XECORE11 */
#define acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext475 :: GPU Time Elapsed */
#define acmgt3__ext475__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext475 :: GPU Core Clocks */
#define acmgt3__ext475__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext475 :: AVG GPU Core Frequency */
#define acmgt3__ext475__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext475 :: AVG GPU Core Frequency */
#define acmgt3__ext475__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext475 :: RT INTERSECTION THREAD RAY DISPATCH XECORE12 */
#define acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext475 :: RT INTERSECTION THREAD RAY DISPATCH XECORE13 */
#define acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext475 :: RT INTERSECTION THREAD RAY DISPATCH XECORE14 */
#define acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext475 :: RT INTERSECTION THREAD RAY DISPATCH XECORE15 */
#define acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext476 :: GPU Time Elapsed */
#define acmgt3__ext476__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext476 :: GPU Core Clocks */
#define acmgt3__ext476__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext476 :: AVG GPU Core Frequency */
#define acmgt3__ext476__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext476 :: AVG GPU Core Frequency */
#define acmgt3__ext476__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext476 :: RT INTERSECTION THREAD RAY DISPATCH XECORE16 */
#define acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore16__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext476 :: RT INTERSECTION THREAD RAY DISPATCH XECORE17 */
#define acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore17__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext476 :: RT INTERSECTION THREAD RAY DISPATCH XECORE18 */
#define acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore18__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext476 :: RT INTERSECTION THREAD RAY DISPATCH XECORE19 */
#define acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore19__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext477 :: GPU Time Elapsed */
#define acmgt3__ext477__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext477 :: GPU Core Clocks */
#define acmgt3__ext477__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext477 :: AVG GPU Core Frequency */
#define acmgt3__ext477__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext477 :: AVG GPU Core Frequency */
#define acmgt3__ext477__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext477 :: RT INTERSECTION THREAD RAY DISPATCH XECORE20 */
#define acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore20__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext477 :: RT INTERSECTION THREAD RAY DISPATCH XECORE21 */
#define acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore21__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext477 :: RT INTERSECTION THREAD RAY DISPATCH XECORE22 */
#define acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore22__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext477 :: RT INTERSECTION THREAD RAY DISPATCH XECORE23 */
#define acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore23__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext478 :: GPU Time Elapsed */
#define acmgt3__ext478__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext478 :: GPU Core Clocks */
#define acmgt3__ext478__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext478 :: AVG GPU Core Frequency */
#define acmgt3__ext478__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext478 :: AVG GPU Core Frequency */
#define acmgt3__ext478__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext478 :: RT INTERSECTION THREAD RAY DISPATCH XECORE24 */
#define acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore24__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext478 :: RT INTERSECTION THREAD RAY DISPATCH XECORE25 */
#define acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore25__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext478 :: RT INTERSECTION THREAD RAY DISPATCH XECORE26 */
#define acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore26__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext478 :: RT INTERSECTION THREAD RAY DISPATCH XECORE27 */
#define acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore27__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext479 :: GPU Time Elapsed */
#define acmgt3__ext479__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext479 :: GPU Core Clocks */
#define acmgt3__ext479__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext479 :: AVG GPU Core Frequency */
#define acmgt3__ext479__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext479 :: AVG GPU Core Frequency */
#define acmgt3__ext479__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext479 :: RT INTERSECTION THREAD RAY DISPATCH XECORE28 */
#define acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore28__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext479 :: RT INTERSECTION THREAD RAY DISPATCH XECORE29 */
#define acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore29__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext479 :: RT INTERSECTION THREAD RAY DISPATCH XECORE30 */
#define acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore30__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext479 :: RT INTERSECTION THREAD RAY DISPATCH XECORE31 */
#define acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore31__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext480 :: GPU Time Elapsed */
#define acmgt3__ext480__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext480 :: GPU Core Clocks */
#define acmgt3__ext480__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext480 :: AVG GPU Core Frequency */
#define acmgt3__ext480__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext480 :: AVG GPU Core Frequency */
#define acmgt3__ext480__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext480 :: RT MISS THREAD RAY DISPATCH XECORE0 */
#define acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext480 :: RT MISS THREAD RAY DISPATCH XECORE1 */
#define acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext480 :: RT MISS THREAD RAY DISPATCH XECORE2 */
#define acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext480 :: RT MISS THREAD RAY DISPATCH XECORE3 */
#define acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext481 :: GPU Time Elapsed */
#define acmgt3__ext481__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext481 :: GPU Core Clocks */
#define acmgt3__ext481__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext481 :: AVG GPU Core Frequency */
#define acmgt3__ext481__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext481 :: AVG GPU Core Frequency */
#define acmgt3__ext481__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext481 :: RT MISS THREAD RAY DISPATCH XECORE4 */
#define acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext481 :: RT MISS THREAD RAY DISPATCH XECORE5 */
#define acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext481 :: RT MISS THREAD RAY DISPATCH XECORE6 */
#define acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext481 :: RT MISS THREAD RAY DISPATCH XECORE7 */
#define acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext482 :: GPU Time Elapsed */
#define acmgt3__ext482__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext482 :: GPU Core Clocks */
#define acmgt3__ext482__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext482 :: AVG GPU Core Frequency */
#define acmgt3__ext482__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext482 :: AVG GPU Core Frequency */
#define acmgt3__ext482__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext482 :: RT MISS THREAD RAY DISPATCH XECORE8 */
#define acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore8__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext482 :: RT MISS THREAD RAY DISPATCH XECORE9 */
#define acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore9__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext482 :: RT MISS THREAD RAY DISPATCH XECORE10 */
#define acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext482 :: RT MISS THREAD RAY DISPATCH XECORE11 */
#define acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore11__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext483 :: GPU Time Elapsed */
#define acmgt3__ext483__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext483 :: GPU Core Clocks */
#define acmgt3__ext483__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext483 :: AVG GPU Core Frequency */
#define acmgt3__ext483__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext483 :: AVG GPU Core Frequency */
#define acmgt3__ext483__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext483 :: RT MISS THREAD RAY DISPATCH XECORE12 */
#define acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext483 :: RT MISS THREAD RAY DISPATCH XECORE13 */
#define acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext483 :: RT MISS THREAD RAY DISPATCH XECORE14 */
#define acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext483 :: RT MISS THREAD RAY DISPATCH XECORE15 */
#define acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext484 :: GPU Time Elapsed */
#define acmgt3__ext484__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext484 :: GPU Core Clocks */
#define acmgt3__ext484__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext484 :: AVG GPU Core Frequency */
#define acmgt3__ext484__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext484 :: AVG GPU Core Frequency */
#define acmgt3__ext484__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext484 :: RT MISS THREAD RAY DISPATCH XECORE16 */
#define acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore16__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext484 :: RT MISS THREAD RAY DISPATCH XECORE17 */
#define acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore17__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext484 :: RT MISS THREAD RAY DISPATCH XECORE18 */
#define acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore18__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext484 :: RT MISS THREAD RAY DISPATCH XECORE19 */
#define acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore19__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext485 :: GPU Time Elapsed */
#define acmgt3__ext485__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext485 :: GPU Core Clocks */
#define acmgt3__ext485__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext485 :: AVG GPU Core Frequency */
#define acmgt3__ext485__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext485 :: AVG GPU Core Frequency */
#define acmgt3__ext485__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext485 :: RT MISS THREAD RAY DISPATCH XECORE20 */
#define acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore20__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext485 :: RT MISS THREAD RAY DISPATCH XECORE21 */
#define acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore21__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext485 :: RT MISS THREAD RAY DISPATCH XECORE22 */
#define acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore22__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext485 :: RT MISS THREAD RAY DISPATCH XECORE23 */
#define acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore23__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext486 :: GPU Time Elapsed */
#define acmgt3__ext486__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext486 :: GPU Core Clocks */
#define acmgt3__ext486__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext486 :: AVG GPU Core Frequency */
#define acmgt3__ext486__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext486 :: AVG GPU Core Frequency */
#define acmgt3__ext486__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext486 :: RT MISS THREAD RAY DISPATCH XECORE24 */
#define acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore24__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext486 :: RT MISS THREAD RAY DISPATCH XECORE25 */
#define acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore25__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext486 :: RT MISS THREAD RAY DISPATCH XECORE26 */
#define acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore26__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext486 :: RT MISS THREAD RAY DISPATCH XECORE27 */
#define acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore27__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext487 :: GPU Time Elapsed */
#define acmgt3__ext487__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext487 :: GPU Core Clocks */
#define acmgt3__ext487__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext487 :: AVG GPU Core Frequency */
#define acmgt3__ext487__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext487 :: AVG GPU Core Frequency */
#define acmgt3__ext487__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext487 :: RT MISS THREAD RAY DISPATCH XECORE28 */
#define acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore28__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext487 :: RT MISS THREAD RAY DISPATCH XECORE29 */
#define acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore29__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext487 :: RT MISS THREAD RAY DISPATCH XECORE30 */
#define acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore30__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext487 :: RT MISS THREAD RAY DISPATCH XECORE31 */
#define acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore31__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext488 :: GPU Time Elapsed */
#define acmgt3__ext488__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext488 :: GPU Core Clocks */
#define acmgt3__ext488__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext488 :: AVG GPU Core Frequency */
#define acmgt3__ext488__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext488 :: AVG GPU Core Frequency */
#define acmgt3__ext488__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext488 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0 */
#define acmgt3__ext488__early_depth_stencil_test_fail_np_zpipe0__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext488 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE0 */
#define acmgt3__ext488__early_depth_stencil_test_fail_p_zpipe0__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext489 :: GPU Time Elapsed */
#define acmgt3__ext489__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext489 :: GPU Core Clocks */
#define acmgt3__ext489__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext489 :: AVG GPU Core Frequency */
#define acmgt3__ext489__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext489 :: AVG GPU Core Frequency */
#define acmgt3__ext489__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext489 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1 */
#define acmgt3__ext489__early_depth_stencil_test_fail_np_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext489 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE1 */
#define acmgt3__ext489__early_depth_stencil_test_fail_p_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext490 :: GPU Time Elapsed */
#define acmgt3__ext490__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext490 :: GPU Core Clocks */
#define acmgt3__ext490__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext490 :: AVG GPU Core Frequency */
#define acmgt3__ext490__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext490 :: AVG GPU Core Frequency */
#define acmgt3__ext490__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext490 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2 */
#define acmgt3__ext490__early_depth_stencil_test_fail_np_zpipe2__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext490 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE2 */
#define acmgt3__ext490__early_depth_stencil_test_fail_p_zpipe2__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext491 :: GPU Time Elapsed */
#define acmgt3__ext491__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext491 :: GPU Core Clocks */
#define acmgt3__ext491__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext491 :: AVG GPU Core Frequency */
#define acmgt3__ext491__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext491 :: AVG GPU Core Frequency */
#define acmgt3__ext491__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext491 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3 */
#define acmgt3__ext491__early_depth_stencil_test_fail_np_zpipe3__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext491 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE3 */
#define acmgt3__ext491__early_depth_stencil_test_fail_p_zpipe3__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext492 :: GPU Time Elapsed */
#define acmgt3__ext492__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext492 :: GPU Core Clocks */
#define acmgt3__ext492__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext492 :: AVG GPU Core Frequency */
#define acmgt3__ext492__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext492 :: AVG GPU Core Frequency */
#define acmgt3__ext492__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext492 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE4 */
#define acmgt3__ext492__early_depth_stencil_test_fail_np_zpipe4__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext492 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE4 */
#define acmgt3__ext492__early_depth_stencil_test_fail_p_zpipe4__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext493 :: GPU Time Elapsed */
#define acmgt3__ext493__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext493 :: GPU Core Clocks */
#define acmgt3__ext493__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext493 :: AVG GPU Core Frequency */
#define acmgt3__ext493__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext493 :: AVG GPU Core Frequency */
#define acmgt3__ext493__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext493 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE5 */
#define acmgt3__ext493__early_depth_stencil_test_fail_np_zpipe5__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext493 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE5 */
#define acmgt3__ext493__early_depth_stencil_test_fail_p_zpipe5__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext494 :: GPU Time Elapsed */
#define acmgt3__ext494__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext494 :: GPU Core Clocks */
#define acmgt3__ext494__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext494 :: AVG GPU Core Frequency */
#define acmgt3__ext494__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext494 :: AVG GPU Core Frequency */
#define acmgt3__ext494__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext494 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE6 */
#define acmgt3__ext494__early_depth_stencil_test_fail_np_zpipe6__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext494 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE6 */
#define acmgt3__ext494__early_depth_stencil_test_fail_p_zpipe6__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext495 :: GPU Time Elapsed */
#define acmgt3__ext495__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext495 :: GPU Core Clocks */
#define acmgt3__ext495__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext495 :: AVG GPU Core Frequency */
#define acmgt3__ext495__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext495 :: AVG GPU Core Frequency */
#define acmgt3__ext495__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext495 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE7 */
#define acmgt3__ext495__early_depth_stencil_test_fail_np_zpipe7__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext495 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE7 */
#define acmgt3__ext495__early_depth_stencil_test_fail_p_zpipe7__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext496 :: GPU Time Elapsed */
#define acmgt3__ext496__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext496 :: GPU Core Clocks */
#define acmgt3__ext496__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext496 :: AVG GPU Core Frequency */
#define acmgt3__ext496__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext496 :: AVG GPU Core Frequency */
#define acmgt3__ext496__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext496 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE8 */
#define acmgt3__ext496__early_depth_stencil_test_fail_np_zpipe8__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext496 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE8 */
#define acmgt3__ext496__early_depth_stencil_test_fail_p_zpipe8__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext497 :: GPU Time Elapsed */
#define acmgt3__ext497__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext497 :: GPU Core Clocks */
#define acmgt3__ext497__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext497 :: AVG GPU Core Frequency */
#define acmgt3__ext497__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext497 :: AVG GPU Core Frequency */
#define acmgt3__ext497__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext497 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE9 */
#define acmgt3__ext497__early_depth_stencil_test_fail_np_zpipe9__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext497 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE9 */
#define acmgt3__ext497__early_depth_stencil_test_fail_p_zpipe9__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext498 :: GPU Time Elapsed */
#define acmgt3__ext498__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext498 :: GPU Core Clocks */
#define acmgt3__ext498__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext498 :: AVG GPU Core Frequency */
#define acmgt3__ext498__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext498 :: AVG GPU Core Frequency */
#define acmgt3__ext498__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext498 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE10 */
#define acmgt3__ext498__early_depth_stencil_test_fail_np_zpipe10__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext498 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE10 */
#define acmgt3__ext498__early_depth_stencil_test_fail_p_zpipe10__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext499 :: GPU Time Elapsed */
#define acmgt3__ext499__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext499 :: GPU Core Clocks */
#define acmgt3__ext499__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext499 :: AVG GPU Core Frequency */
#define acmgt3__ext499__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext499 :: AVG GPU Core Frequency */
#define acmgt3__ext499__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext499 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE11 */
#define acmgt3__ext499__early_depth_stencil_test_fail_np_zpipe11__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext499 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE11 */
#define acmgt3__ext499__early_depth_stencil_test_fail_p_zpipe11__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext500 :: GPU Time Elapsed */
#define acmgt3__ext500__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext500 :: GPU Core Clocks */
#define acmgt3__ext500__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext500 :: AVG GPU Core Frequency */
#define acmgt3__ext500__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext500 :: AVG GPU Core Frequency */
#define acmgt3__ext500__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext500 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE12 */
#define acmgt3__ext500__early_depth_stencil_test_fail_np_zpipe12__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext500 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE12 */
#define acmgt3__ext500__early_depth_stencil_test_fail_p_zpipe12__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext501 :: GPU Time Elapsed */
#define acmgt3__ext501__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext501 :: GPU Core Clocks */
#define acmgt3__ext501__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext501 :: AVG GPU Core Frequency */
#define acmgt3__ext501__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext501 :: AVG GPU Core Frequency */
#define acmgt3__ext501__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext501 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE13 */
#define acmgt3__ext501__early_depth_stencil_test_fail_np_zpipe13__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext501 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE13 */
#define acmgt3__ext501__early_depth_stencil_test_fail_p_zpipe13__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext502 :: GPU Time Elapsed */
#define acmgt3__ext502__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext502 :: GPU Core Clocks */
#define acmgt3__ext502__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext502 :: AVG GPU Core Frequency */
#define acmgt3__ext502__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext502 :: AVG GPU Core Frequency */
#define acmgt3__ext502__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext502 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE14 */
#define acmgt3__ext502__early_depth_stencil_test_fail_np_zpipe14__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext502 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE14 */
#define acmgt3__ext502__early_depth_stencil_test_fail_p_zpipe14__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext503 :: GPU Time Elapsed */
#define acmgt3__ext503__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext503 :: GPU Core Clocks */
#define acmgt3__ext503__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext503 :: AVG GPU Core Frequency */
#define acmgt3__ext503__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext503 :: AVG GPU Core Frequency */
#define acmgt3__ext503__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext503 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE15 */
#define acmgt3__ext503__early_depth_stencil_test_fail_np_zpipe15__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext503 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE15 */
#define acmgt3__ext503__early_depth_stencil_test_fail_p_zpipe15__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext504 :: GPU Time Elapsed */
#define acmgt3__ext504__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext504 :: GPU Core Clocks */
#define acmgt3__ext504__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext504 :: AVG GPU Core Frequency */
#define acmgt3__ext504__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext504 :: AVG GPU Core Frequency */
#define acmgt3__ext504__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext504 :: HIZ DEPTH TEST AMBIG NP ZPIPE0 */
#define acmgt3__ext504__hiz_depth_test_ambig_np_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext505 :: GPU Time Elapsed */
#define acmgt3__ext505__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext505 :: GPU Core Clocks */
#define acmgt3__ext505__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext505 :: AVG GPU Core Frequency */
#define acmgt3__ext505__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext505 :: AVG GPU Core Frequency */
#define acmgt3__ext505__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext505 :: HIZ DEPTH TEST AMBIG NP ZPIPE1 */
#define acmgt3__ext505__hiz_depth_test_ambig_np_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext506 :: GPU Time Elapsed */
#define acmgt3__ext506__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext506 :: GPU Core Clocks */
#define acmgt3__ext506__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext506 :: AVG GPU Core Frequency */
#define acmgt3__ext506__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext506 :: AVG GPU Core Frequency */
#define acmgt3__ext506__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext506 :: HIZ DEPTH TEST AMBIG NP ZPIPE2 */
#define acmgt3__ext506__hiz_depth_test_ambig_np_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext507 :: GPU Time Elapsed */
#define acmgt3__ext507__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext507 :: GPU Core Clocks */
#define acmgt3__ext507__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext507 :: AVG GPU Core Frequency */
#define acmgt3__ext507__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext507 :: AVG GPU Core Frequency */
#define acmgt3__ext507__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext507 :: HIZ DEPTH TEST AMBIG NP ZPIPE3 */
#define acmgt3__ext507__hiz_depth_test_ambig_np_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext508 :: GPU Time Elapsed */
#define acmgt3__ext508__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext508 :: GPU Core Clocks */
#define acmgt3__ext508__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext508 :: AVG GPU Core Frequency */
#define acmgt3__ext508__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext508 :: AVG GPU Core Frequency */
#define acmgt3__ext508__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext508 :: HIZ DEPTH TEST AMBIG NP ZPIPE4 */
#define acmgt3__ext508__hiz_depth_test_ambig_np_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext509 :: GPU Time Elapsed */
#define acmgt3__ext509__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext509 :: GPU Core Clocks */
#define acmgt3__ext509__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext509 :: AVG GPU Core Frequency */
#define acmgt3__ext509__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext509 :: AVG GPU Core Frequency */
#define acmgt3__ext509__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext509 :: HIZ DEPTH TEST AMBIG NP ZPIPE5 */
#define acmgt3__ext509__hiz_depth_test_ambig_np_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext510 :: GPU Time Elapsed */
#define acmgt3__ext510__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext510 :: GPU Core Clocks */
#define acmgt3__ext510__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext510 :: AVG GPU Core Frequency */
#define acmgt3__ext510__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext510 :: AVG GPU Core Frequency */
#define acmgt3__ext510__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext510 :: HIZ DEPTH TEST AMBIG NP ZPIPE6 */
#define acmgt3__ext510__hiz_depth_test_ambig_np_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext511 :: GPU Time Elapsed */
#define acmgt3__ext511__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext511 :: GPU Core Clocks */
#define acmgt3__ext511__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext511 :: AVG GPU Core Frequency */
#define acmgt3__ext511__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext511 :: AVG GPU Core Frequency */
#define acmgt3__ext511__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext511 :: HIZ DEPTH TEST AMBIG NP ZPIPE7 */
#define acmgt3__ext511__hiz_depth_test_ambig_np_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext512 :: GPU Time Elapsed */
#define acmgt3__ext512__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext512 :: GPU Core Clocks */
#define acmgt3__ext512__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext512 :: AVG GPU Core Frequency */
#define acmgt3__ext512__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext512 :: AVG GPU Core Frequency */
#define acmgt3__ext512__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext512 :: HIZ DEPTH TEST AMBIG NP ZPIPE8 */
#define acmgt3__ext512__hiz_depth_test_ambig_np_zpipe8__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext513 :: GPU Time Elapsed */
#define acmgt3__ext513__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext513 :: GPU Core Clocks */
#define acmgt3__ext513__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext513 :: AVG GPU Core Frequency */
#define acmgt3__ext513__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext513 :: AVG GPU Core Frequency */
#define acmgt3__ext513__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext513 :: HIZ DEPTH TEST AMBIG NP ZPIPE9 */
#define acmgt3__ext513__hiz_depth_test_ambig_np_zpipe9__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext514 :: GPU Time Elapsed */
#define acmgt3__ext514__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext514 :: GPU Core Clocks */
#define acmgt3__ext514__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext514 :: AVG GPU Core Frequency */
#define acmgt3__ext514__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext514 :: AVG GPU Core Frequency */
#define acmgt3__ext514__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext514 :: HIZ DEPTH TEST AMBIG NP ZPIPE10 */
#define acmgt3__ext514__hiz_depth_test_ambig_np_zpipe10__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext515 :: GPU Time Elapsed */
#define acmgt3__ext515__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext515 :: GPU Core Clocks */
#define acmgt3__ext515__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext515 :: AVG GPU Core Frequency */
#define acmgt3__ext515__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext515 :: AVG GPU Core Frequency */
#define acmgt3__ext515__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext515 :: HIZ DEPTH TEST AMBIG NP ZPIPE11 */
#define acmgt3__ext515__hiz_depth_test_ambig_np_zpipe11__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext516 :: GPU Time Elapsed */
#define acmgt3__ext516__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext516 :: GPU Core Clocks */
#define acmgt3__ext516__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext516 :: AVG GPU Core Frequency */
#define acmgt3__ext516__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext516 :: AVG GPU Core Frequency */
#define acmgt3__ext516__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext516 :: HIZ DEPTH TEST AMBIG NP ZPIPE12 */
#define acmgt3__ext516__hiz_depth_test_ambig_np_zpipe12__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext517 :: GPU Time Elapsed */
#define acmgt3__ext517__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext517 :: GPU Core Clocks */
#define acmgt3__ext517__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext517 :: AVG GPU Core Frequency */
#define acmgt3__ext517__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext517 :: AVG GPU Core Frequency */
#define acmgt3__ext517__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext517 :: HIZ DEPTH TEST AMBIG NP ZPIPE13 */
#define acmgt3__ext517__hiz_depth_test_ambig_np_zpipe13__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext518 :: GPU Time Elapsed */
#define acmgt3__ext518__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext518 :: GPU Core Clocks */
#define acmgt3__ext518__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext518 :: AVG GPU Core Frequency */
#define acmgt3__ext518__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext518 :: AVG GPU Core Frequency */
#define acmgt3__ext518__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext518 :: HIZ DEPTH TEST AMBIG NP ZPIPE14 */
#define acmgt3__ext518__hiz_depth_test_ambig_np_zpipe14__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext519 :: GPU Time Elapsed */
#define acmgt3__ext519__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext519 :: GPU Core Clocks */
#define acmgt3__ext519__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext519 :: AVG GPU Core Frequency */
#define acmgt3__ext519__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext519 :: AVG GPU Core Frequency */
#define acmgt3__ext519__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext519 :: HIZ DEPTH TEST AMBIG NP ZPIPE15 */
#define acmgt3__ext519__hiz_depth_test_ambig_np_zpipe15__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext520 :: GPU Time Elapsed */
#define acmgt3__ext520__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext520 :: GPU Core Clocks */
#define acmgt3__ext520__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext520 :: AVG GPU Core Frequency */
#define acmgt3__ext520__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext520 :: AVG GPU Core Frequency */
#define acmgt3__ext520__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext520 :: HIZ DEPTH TEST AMBIG P ZPIPE0 */
#define acmgt3__ext520__hiz_depth_test_ambig_p_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext521 :: GPU Time Elapsed */
#define acmgt3__ext521__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext521 :: GPU Core Clocks */
#define acmgt3__ext521__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext521 :: AVG GPU Core Frequency */
#define acmgt3__ext521__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext521 :: AVG GPU Core Frequency */
#define acmgt3__ext521__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext521 :: HIZ DEPTH TEST AMBIG P ZPIPE1 */
#define acmgt3__ext521__hiz_depth_test_ambig_p_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext522 :: GPU Time Elapsed */
#define acmgt3__ext522__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext522 :: GPU Core Clocks */
#define acmgt3__ext522__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext522 :: AVG GPU Core Frequency */
#define acmgt3__ext522__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext522 :: AVG GPU Core Frequency */
#define acmgt3__ext522__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext522 :: HIZ DEPTH TEST AMBIG P ZPIPE2 */
#define acmgt3__ext522__hiz_depth_test_ambig_p_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext523 :: GPU Time Elapsed */
#define acmgt3__ext523__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext523 :: GPU Core Clocks */
#define acmgt3__ext523__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext523 :: AVG GPU Core Frequency */
#define acmgt3__ext523__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext523 :: AVG GPU Core Frequency */
#define acmgt3__ext523__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext523 :: HIZ DEPTH TEST AMBIG P ZPIPE3 */
#define acmgt3__ext523__hiz_depth_test_ambig_p_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext524 :: GPU Time Elapsed */
#define acmgt3__ext524__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext524 :: GPU Core Clocks */
#define acmgt3__ext524__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext524 :: AVG GPU Core Frequency */
#define acmgt3__ext524__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext524 :: AVG GPU Core Frequency */
#define acmgt3__ext524__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext524 :: HIZ DEPTH TEST AMBIG P ZPIPE4 */
#define acmgt3__ext524__hiz_depth_test_ambig_p_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext525 :: GPU Time Elapsed */
#define acmgt3__ext525__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext525 :: GPU Core Clocks */
#define acmgt3__ext525__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext525 :: AVG GPU Core Frequency */
#define acmgt3__ext525__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext525 :: AVG GPU Core Frequency */
#define acmgt3__ext525__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext525 :: HIZ DEPTH TEST AMBIG P ZPIPE5 */
#define acmgt3__ext525__hiz_depth_test_ambig_p_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext526 :: GPU Time Elapsed */
#define acmgt3__ext526__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext526 :: GPU Core Clocks */
#define acmgt3__ext526__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext526 :: AVG GPU Core Frequency */
#define acmgt3__ext526__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext526 :: AVG GPU Core Frequency */
#define acmgt3__ext526__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext526 :: HIZ DEPTH TEST AMBIG P ZPIPE6 */
#define acmgt3__ext526__hiz_depth_test_ambig_p_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext527 :: GPU Time Elapsed */
#define acmgt3__ext527__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext527 :: GPU Core Clocks */
#define acmgt3__ext527__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext527 :: AVG GPU Core Frequency */
#define acmgt3__ext527__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext527 :: AVG GPU Core Frequency */
#define acmgt3__ext527__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext527 :: HIZ DEPTH TEST AMBIG P ZPIPE7 */
#define acmgt3__ext527__hiz_depth_test_ambig_p_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext528 :: GPU Time Elapsed */
#define acmgt3__ext528__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext528 :: GPU Core Clocks */
#define acmgt3__ext528__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext528 :: AVG GPU Core Frequency */
#define acmgt3__ext528__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext528 :: AVG GPU Core Frequency */
#define acmgt3__ext528__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext528 :: HIZ DEPTH TEST AMBIG P ZPIPE8 */
#define acmgt3__ext528__hiz_depth_test_ambig_p_zpipe8__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext529 :: GPU Time Elapsed */
#define acmgt3__ext529__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext529 :: GPU Core Clocks */
#define acmgt3__ext529__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext529 :: AVG GPU Core Frequency */
#define acmgt3__ext529__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext529 :: AVG GPU Core Frequency */
#define acmgt3__ext529__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext529 :: HIZ DEPTH TEST AMBIG P ZPIPE9 */
#define acmgt3__ext529__hiz_depth_test_ambig_p_zpipe9__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext530 :: GPU Time Elapsed */
#define acmgt3__ext530__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext530 :: GPU Core Clocks */
#define acmgt3__ext530__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext530 :: AVG GPU Core Frequency */
#define acmgt3__ext530__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext530 :: AVG GPU Core Frequency */
#define acmgt3__ext530__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext530 :: HIZ DEPTH TEST AMBIG P ZPIPE10 */
#define acmgt3__ext530__hiz_depth_test_ambig_p_zpipe10__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext531 :: GPU Time Elapsed */
#define acmgt3__ext531__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext531 :: GPU Core Clocks */
#define acmgt3__ext531__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext531 :: AVG GPU Core Frequency */
#define acmgt3__ext531__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext531 :: AVG GPU Core Frequency */
#define acmgt3__ext531__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext531 :: HIZ DEPTH TEST AMBIG P ZPIPE11 */
#define acmgt3__ext531__hiz_depth_test_ambig_p_zpipe11__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext532 :: GPU Time Elapsed */
#define acmgt3__ext532__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext532 :: GPU Core Clocks */
#define acmgt3__ext532__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext532 :: AVG GPU Core Frequency */
#define acmgt3__ext532__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext532 :: AVG GPU Core Frequency */
#define acmgt3__ext532__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext532 :: HIZ DEPTH TEST AMBIG P ZPIPE12 */
#define acmgt3__ext532__hiz_depth_test_ambig_p_zpipe12__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext533 :: GPU Time Elapsed */
#define acmgt3__ext533__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext533 :: GPU Core Clocks */
#define acmgt3__ext533__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext533 :: AVG GPU Core Frequency */
#define acmgt3__ext533__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext533 :: AVG GPU Core Frequency */
#define acmgt3__ext533__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext533 :: HIZ DEPTH TEST AMBIG P ZPIPE13 */
#define acmgt3__ext533__hiz_depth_test_ambig_p_zpipe13__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext534 :: GPU Time Elapsed */
#define acmgt3__ext534__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext534 :: GPU Core Clocks */
#define acmgt3__ext534__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext534 :: AVG GPU Core Frequency */
#define acmgt3__ext534__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext534 :: AVG GPU Core Frequency */
#define acmgt3__ext534__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext534 :: HIZ DEPTH TEST AMBIG P ZPIPE14 */
#define acmgt3__ext534__hiz_depth_test_ambig_p_zpipe14__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext535 :: GPU Time Elapsed */
#define acmgt3__ext535__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext535 :: GPU Core Clocks */
#define acmgt3__ext535__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext535 :: AVG GPU Core Frequency */
#define acmgt3__ext535__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext535 :: AVG GPU Core Frequency */
#define acmgt3__ext535__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext535 :: HIZ DEPTH TEST AMBIG P ZPIPE15 */
#define acmgt3__ext535__hiz_depth_test_ambig_p_zpipe15__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext536 :: GPU Time Elapsed */
#define acmgt3__ext536__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext536 :: GPU Core Clocks */
#define acmgt3__ext536__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext536 :: AVG GPU Core Frequency */
#define acmgt3__ext536__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext536 :: AVG GPU Core Frequency */
#define acmgt3__ext536__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext536 :: HIZ DEPTH TEST FAIL NP ZPIPE0 */
#define acmgt3__ext536__hiz_depth_test_fail_np_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext537 :: GPU Time Elapsed */
#define acmgt3__ext537__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext537 :: GPU Core Clocks */
#define acmgt3__ext537__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext537 :: AVG GPU Core Frequency */
#define acmgt3__ext537__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext537 :: AVG GPU Core Frequency */
#define acmgt3__ext537__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext537 :: HIZ DEPTH TEST FAIL NP ZPIPE1 */
#define acmgt3__ext537__hiz_depth_test_fail_np_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext538 :: GPU Time Elapsed */
#define acmgt3__ext538__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext538 :: GPU Core Clocks */
#define acmgt3__ext538__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext538 :: AVG GPU Core Frequency */
#define acmgt3__ext538__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext538 :: AVG GPU Core Frequency */
#define acmgt3__ext538__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext538 :: HIZ DEPTH TEST FAIL NP ZPIPE2 */
#define acmgt3__ext538__hiz_depth_test_fail_np_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext539 :: GPU Time Elapsed */
#define acmgt3__ext539__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext539 :: GPU Core Clocks */
#define acmgt3__ext539__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext539 :: AVG GPU Core Frequency */
#define acmgt3__ext539__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext539 :: AVG GPU Core Frequency */
#define acmgt3__ext539__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext539 :: HIZ DEPTH TEST FAIL NP ZPIPE3 */
#define acmgt3__ext539__hiz_depth_test_fail_np_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext540 :: GPU Time Elapsed */
#define acmgt3__ext540__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext540 :: GPU Core Clocks */
#define acmgt3__ext540__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext540 :: AVG GPU Core Frequency */
#define acmgt3__ext540__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext540 :: AVG GPU Core Frequency */
#define acmgt3__ext540__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext540 :: HIZ DEPTH TEST FAIL NP ZPIPE4 */
#define acmgt3__ext540__hiz_depth_test_fail_np_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext541 :: GPU Time Elapsed */
#define acmgt3__ext541__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext541 :: GPU Core Clocks */
#define acmgt3__ext541__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext541 :: AVG GPU Core Frequency */
#define acmgt3__ext541__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext541 :: AVG GPU Core Frequency */
#define acmgt3__ext541__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext541 :: HIZ DEPTH TEST FAIL NP ZPIPE5 */
#define acmgt3__ext541__hiz_depth_test_fail_np_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext542 :: GPU Time Elapsed */
#define acmgt3__ext542__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext542 :: GPU Core Clocks */
#define acmgt3__ext542__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext542 :: AVG GPU Core Frequency */
#define acmgt3__ext542__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext542 :: AVG GPU Core Frequency */
#define acmgt3__ext542__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext542 :: HIZ DEPTH TEST FAIL NP ZPIPE6 */
#define acmgt3__ext542__hiz_depth_test_fail_np_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext543 :: GPU Time Elapsed */
#define acmgt3__ext543__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext543 :: GPU Core Clocks */
#define acmgt3__ext543__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext543 :: AVG GPU Core Frequency */
#define acmgt3__ext543__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext543 :: AVG GPU Core Frequency */
#define acmgt3__ext543__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext543 :: HIZ DEPTH TEST FAIL NP ZPIPE7 */
#define acmgt3__ext543__hiz_depth_test_fail_np_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext544 :: GPU Time Elapsed */
#define acmgt3__ext544__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext544 :: GPU Core Clocks */
#define acmgt3__ext544__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext544 :: AVG GPU Core Frequency */
#define acmgt3__ext544__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext544 :: AVG GPU Core Frequency */
#define acmgt3__ext544__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext544 :: HIZ DEPTH TEST FAIL NP ZPIPE8 */
#define acmgt3__ext544__hiz_depth_test_fail_np_zpipe8__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext545 :: GPU Time Elapsed */
#define acmgt3__ext545__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext545 :: GPU Core Clocks */
#define acmgt3__ext545__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext545 :: AVG GPU Core Frequency */
#define acmgt3__ext545__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext545 :: AVG GPU Core Frequency */
#define acmgt3__ext545__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext545 :: HIZ DEPTH TEST FAIL NP ZPIPE9 */
#define acmgt3__ext545__hiz_depth_test_fail_np_zpipe9__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext546 :: GPU Time Elapsed */
#define acmgt3__ext546__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext546 :: GPU Core Clocks */
#define acmgt3__ext546__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext546 :: AVG GPU Core Frequency */
#define acmgt3__ext546__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext546 :: AVG GPU Core Frequency */
#define acmgt3__ext546__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext546 :: HIZ DEPTH TEST FAIL NP ZPIPE10 */
#define acmgt3__ext546__hiz_depth_test_fail_np_zpipe10__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext547 :: GPU Time Elapsed */
#define acmgt3__ext547__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext547 :: GPU Core Clocks */
#define acmgt3__ext547__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext547 :: AVG GPU Core Frequency */
#define acmgt3__ext547__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext547 :: AVG GPU Core Frequency */
#define acmgt3__ext547__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext547 :: HIZ DEPTH TEST FAIL NP ZPIPE11 */
#define acmgt3__ext547__hiz_depth_test_fail_np_zpipe11__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext548 :: GPU Time Elapsed */
#define acmgt3__ext548__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext548 :: GPU Core Clocks */
#define acmgt3__ext548__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext548 :: AVG GPU Core Frequency */
#define acmgt3__ext548__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext548 :: AVG GPU Core Frequency */
#define acmgt3__ext548__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext548 :: HIZ DEPTH TEST FAIL NP ZPIPE12 */
#define acmgt3__ext548__hiz_depth_test_fail_np_zpipe12__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext549 :: GPU Time Elapsed */
#define acmgt3__ext549__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext549 :: GPU Core Clocks */
#define acmgt3__ext549__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext549 :: AVG GPU Core Frequency */
#define acmgt3__ext549__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext549 :: AVG GPU Core Frequency */
#define acmgt3__ext549__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext549 :: HIZ DEPTH TEST FAIL NP ZPIPE13 */
#define acmgt3__ext549__hiz_depth_test_fail_np_zpipe13__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext550 :: GPU Time Elapsed */
#define acmgt3__ext550__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext550 :: GPU Core Clocks */
#define acmgt3__ext550__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext550 :: AVG GPU Core Frequency */
#define acmgt3__ext550__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext550 :: AVG GPU Core Frequency */
#define acmgt3__ext550__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext550 :: HIZ DEPTH TEST FAIL NP ZPIPE14 */
#define acmgt3__ext550__hiz_depth_test_fail_np_zpipe14__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext551 :: GPU Time Elapsed */
#define acmgt3__ext551__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext551 :: GPU Core Clocks */
#define acmgt3__ext551__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext551 :: AVG GPU Core Frequency */
#define acmgt3__ext551__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext551 :: AVG GPU Core Frequency */
#define acmgt3__ext551__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext551 :: HIZ DEPTH TEST FAIL NP ZPIPE15 */
#define acmgt3__ext551__hiz_depth_test_fail_np_zpipe15__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext552 :: GPU Time Elapsed */
#define acmgt3__ext552__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext552 :: GPU Core Clocks */
#define acmgt3__ext552__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext552 :: AVG GPU Core Frequency */
#define acmgt3__ext552__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext552 :: AVG GPU Core Frequency */
#define acmgt3__ext552__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext552 :: HIZ DEPTH TEST FAIL P ZPIPE0 */
#define acmgt3__ext552__hiz_depth_test_fail_p_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext553 :: GPU Time Elapsed */
#define acmgt3__ext553__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext553 :: GPU Core Clocks */
#define acmgt3__ext553__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext553 :: AVG GPU Core Frequency */
#define acmgt3__ext553__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext553 :: AVG GPU Core Frequency */
#define acmgt3__ext553__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext553 :: HIZ DEPTH TEST FAIL P ZPIPE1 */
#define acmgt3__ext553__hiz_depth_test_fail_p_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext554 :: GPU Time Elapsed */
#define acmgt3__ext554__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext554 :: GPU Core Clocks */
#define acmgt3__ext554__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext554 :: AVG GPU Core Frequency */
#define acmgt3__ext554__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext554 :: AVG GPU Core Frequency */
#define acmgt3__ext554__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext554 :: HIZ DEPTH TEST FAIL P ZPIPE2 */
#define acmgt3__ext554__hiz_depth_test_fail_p_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext555 :: GPU Time Elapsed */
#define acmgt3__ext555__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext555 :: GPU Core Clocks */
#define acmgt3__ext555__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext555 :: AVG GPU Core Frequency */
#define acmgt3__ext555__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext555 :: AVG GPU Core Frequency */
#define acmgt3__ext555__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext555 :: HIZ DEPTH TEST FAIL P ZPIPE3 */
#define acmgt3__ext555__hiz_depth_test_fail_p_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext556 :: GPU Time Elapsed */
#define acmgt3__ext556__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext556 :: GPU Core Clocks */
#define acmgt3__ext556__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext556 :: AVG GPU Core Frequency */
#define acmgt3__ext556__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext556 :: AVG GPU Core Frequency */
#define acmgt3__ext556__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext556 :: HIZ DEPTH TEST FAIL P ZPIPE4 */
#define acmgt3__ext556__hiz_depth_test_fail_p_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext557 :: GPU Time Elapsed */
#define acmgt3__ext557__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext557 :: GPU Core Clocks */
#define acmgt3__ext557__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext557 :: AVG GPU Core Frequency */
#define acmgt3__ext557__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext557 :: AVG GPU Core Frequency */
#define acmgt3__ext557__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext557 :: HIZ DEPTH TEST FAIL P ZPIPE5 */
#define acmgt3__ext557__hiz_depth_test_fail_p_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext558 :: GPU Time Elapsed */
#define acmgt3__ext558__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext558 :: GPU Core Clocks */
#define acmgt3__ext558__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext558 :: AVG GPU Core Frequency */
#define acmgt3__ext558__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext558 :: AVG GPU Core Frequency */
#define acmgt3__ext558__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext558 :: HIZ DEPTH TEST FAIL P ZPIPE6 */
#define acmgt3__ext558__hiz_depth_test_fail_p_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext559 :: GPU Time Elapsed */
#define acmgt3__ext559__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext559 :: GPU Core Clocks */
#define acmgt3__ext559__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext559 :: AVG GPU Core Frequency */
#define acmgt3__ext559__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext559 :: AVG GPU Core Frequency */
#define acmgt3__ext559__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext559 :: HIZ DEPTH TEST FAIL P ZPIPE7 */
#define acmgt3__ext559__hiz_depth_test_fail_p_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext560 :: GPU Time Elapsed */
#define acmgt3__ext560__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext560 :: GPU Core Clocks */
#define acmgt3__ext560__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext560 :: AVG GPU Core Frequency */
#define acmgt3__ext560__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext560 :: AVG GPU Core Frequency */
#define acmgt3__ext560__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext560 :: HIZ DEPTH TEST FAIL P ZPIPE8 */
#define acmgt3__ext560__hiz_depth_test_fail_p_zpipe8__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext561 :: GPU Time Elapsed */
#define acmgt3__ext561__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext561 :: GPU Core Clocks */
#define acmgt3__ext561__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext561 :: AVG GPU Core Frequency */
#define acmgt3__ext561__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext561 :: AVG GPU Core Frequency */
#define acmgt3__ext561__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext561 :: HIZ DEPTH TEST FAIL P ZPIPE9 */
#define acmgt3__ext561__hiz_depth_test_fail_p_zpipe9__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext562 :: GPU Time Elapsed */
#define acmgt3__ext562__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext562 :: GPU Core Clocks */
#define acmgt3__ext562__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext562 :: AVG GPU Core Frequency */
#define acmgt3__ext562__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext562 :: AVG GPU Core Frequency */
#define acmgt3__ext562__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext562 :: HIZ DEPTH TEST FAIL P ZPIPE10 */
#define acmgt3__ext562__hiz_depth_test_fail_p_zpipe10__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext563 :: GPU Time Elapsed */
#define acmgt3__ext563__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext563 :: GPU Core Clocks */
#define acmgt3__ext563__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext563 :: AVG GPU Core Frequency */
#define acmgt3__ext563__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext563 :: AVG GPU Core Frequency */
#define acmgt3__ext563__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext563 :: HIZ DEPTH TEST FAIL P ZPIPE11 */
#define acmgt3__ext563__hiz_depth_test_fail_p_zpipe11__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext564 :: GPU Time Elapsed */
#define acmgt3__ext564__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext564 :: GPU Core Clocks */
#define acmgt3__ext564__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext564 :: AVG GPU Core Frequency */
#define acmgt3__ext564__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext564 :: AVG GPU Core Frequency */
#define acmgt3__ext564__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext564 :: HIZ DEPTH TEST FAIL P ZPIPE12 */
#define acmgt3__ext564__hiz_depth_test_fail_p_zpipe12__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext565 :: GPU Time Elapsed */
#define acmgt3__ext565__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext565 :: GPU Core Clocks */
#define acmgt3__ext565__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext565 :: AVG GPU Core Frequency */
#define acmgt3__ext565__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext565 :: AVG GPU Core Frequency */
#define acmgt3__ext565__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext565 :: HIZ DEPTH TEST FAIL P ZPIPE13 */
#define acmgt3__ext565__hiz_depth_test_fail_p_zpipe13__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext566 :: GPU Time Elapsed */
#define acmgt3__ext566__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext566 :: GPU Core Clocks */
#define acmgt3__ext566__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext566 :: AVG GPU Core Frequency */
#define acmgt3__ext566__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext566 :: AVG GPU Core Frequency */
#define acmgt3__ext566__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext566 :: HIZ DEPTH TEST FAIL P ZPIPE14 */
#define acmgt3__ext566__hiz_depth_test_fail_p_zpipe14__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext567 :: GPU Time Elapsed */
#define acmgt3__ext567__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext567 :: GPU Core Clocks */
#define acmgt3__ext567__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext567 :: AVG GPU Core Frequency */
#define acmgt3__ext567__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext567 :: AVG GPU Core Frequency */
#define acmgt3__ext567__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext567 :: HIZ DEPTH TEST FAIL P ZPIPE15 */
#define acmgt3__ext567__hiz_depth_test_fail_p_zpipe15__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext568 :: GPU Time Elapsed */
#define acmgt3__ext568__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext568 :: GPU Core Clocks */
#define acmgt3__ext568__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext568 :: AVG GPU Core Frequency */
#define acmgt3__ext568__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext568 :: AVG GPU Core Frequency */
#define acmgt3__ext568__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext568 :: HIZ DEPTH TEST PASS P ZPIPE0 */
#define acmgt3__ext568__hiz_depth_test_pass_p_zpipe0__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext569 :: GPU Time Elapsed */
#define acmgt3__ext569__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext569 :: GPU Core Clocks */
#define acmgt3__ext569__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext569 :: AVG GPU Core Frequency */
#define acmgt3__ext569__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext569 :: AVG GPU Core Frequency */
#define acmgt3__ext569__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext569 :: HIZ DEPTH TEST PASS P ZPIPE1 */
#define acmgt3__ext569__hiz_depth_test_pass_p_zpipe1__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext570 :: GPU Time Elapsed */
#define acmgt3__ext570__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext570 :: GPU Core Clocks */
#define acmgt3__ext570__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext570 :: AVG GPU Core Frequency */
#define acmgt3__ext570__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext570 :: AVG GPU Core Frequency */
#define acmgt3__ext570__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext570 :: HIZ DEPTH TEST PASS P ZPIPE2 */
#define acmgt3__ext570__hiz_depth_test_pass_p_zpipe2__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext571 :: GPU Time Elapsed */
#define acmgt3__ext571__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext571 :: GPU Core Clocks */
#define acmgt3__ext571__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext571 :: AVG GPU Core Frequency */
#define acmgt3__ext571__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext571 :: AVG GPU Core Frequency */
#define acmgt3__ext571__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext571 :: HIZ DEPTH TEST PASS P ZPIPE3 */
#define acmgt3__ext571__hiz_depth_test_pass_p_zpipe3__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext572 :: GPU Time Elapsed */
#define acmgt3__ext572__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext572 :: GPU Core Clocks */
#define acmgt3__ext572__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext572 :: AVG GPU Core Frequency */
#define acmgt3__ext572__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext572 :: AVG GPU Core Frequency */
#define acmgt3__ext572__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext572 :: HIZ DEPTH TEST PASS P ZPIPE4 */
#define acmgt3__ext572__hiz_depth_test_pass_p_zpipe4__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext573 :: GPU Time Elapsed */
#define acmgt3__ext573__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext573 :: GPU Core Clocks */
#define acmgt3__ext573__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext573 :: AVG GPU Core Frequency */
#define acmgt3__ext573__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext573 :: AVG GPU Core Frequency */
#define acmgt3__ext573__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext573 :: HIZ DEPTH TEST PASS P ZPIPE5 */
#define acmgt3__ext573__hiz_depth_test_pass_p_zpipe5__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext574 :: GPU Time Elapsed */
#define acmgt3__ext574__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext574 :: GPU Core Clocks */
#define acmgt3__ext574__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext574 :: AVG GPU Core Frequency */
#define acmgt3__ext574__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext574 :: AVG GPU Core Frequency */
#define acmgt3__ext574__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext574 :: HIZ DEPTH TEST PASS P ZPIPE6 */
#define acmgt3__ext574__hiz_depth_test_pass_p_zpipe6__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext575 :: GPU Time Elapsed */
#define acmgt3__ext575__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext575 :: GPU Core Clocks */
#define acmgt3__ext575__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext575 :: AVG GPU Core Frequency */
#define acmgt3__ext575__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext575 :: AVG GPU Core Frequency */
#define acmgt3__ext575__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext575 :: HIZ DEPTH TEST PASS P ZPIPE7 */
#define acmgt3__ext575__hiz_depth_test_pass_p_zpipe7__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext576 :: GPU Time Elapsed */
#define acmgt3__ext576__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext576 :: GPU Core Clocks */
#define acmgt3__ext576__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext576 :: AVG GPU Core Frequency */
#define acmgt3__ext576__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext576 :: AVG GPU Core Frequency */
#define acmgt3__ext576__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext576 :: HIZ DEPTH TEST PASS P ZPIPE8 */
#define acmgt3__ext576__hiz_depth_test_pass_p_zpipe8__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext577 :: GPU Time Elapsed */
#define acmgt3__ext577__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext577 :: GPU Core Clocks */
#define acmgt3__ext577__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext577 :: AVG GPU Core Frequency */
#define acmgt3__ext577__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext577 :: AVG GPU Core Frequency */
#define acmgt3__ext577__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext577 :: HIZ DEPTH TEST PASS P ZPIPE9 */
#define acmgt3__ext577__hiz_depth_test_pass_p_zpipe9__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext578 :: GPU Time Elapsed */
#define acmgt3__ext578__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext578 :: GPU Core Clocks */
#define acmgt3__ext578__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext578 :: AVG GPU Core Frequency */
#define acmgt3__ext578__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext578 :: AVG GPU Core Frequency */
#define acmgt3__ext578__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext578 :: HIZ DEPTH TEST PASS P ZPIPE10 */
#define acmgt3__ext578__hiz_depth_test_pass_p_zpipe10__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext579 :: GPU Time Elapsed */
#define acmgt3__ext579__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext579 :: GPU Core Clocks */
#define acmgt3__ext579__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext579 :: AVG GPU Core Frequency */
#define acmgt3__ext579__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext579 :: AVG GPU Core Frequency */
#define acmgt3__ext579__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext579 :: HIZ DEPTH TEST PASS P ZPIPE11 */
#define acmgt3__ext579__hiz_depth_test_pass_p_zpipe11__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext580 :: GPU Time Elapsed */
#define acmgt3__ext580__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext580 :: GPU Core Clocks */
#define acmgt3__ext580__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext580 :: AVG GPU Core Frequency */
#define acmgt3__ext580__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext580 :: AVG GPU Core Frequency */
#define acmgt3__ext580__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext580 :: HIZ DEPTH TEST PASS P ZPIPE12 */
#define acmgt3__ext580__hiz_depth_test_pass_p_zpipe12__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext581 :: GPU Time Elapsed */
#define acmgt3__ext581__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext581 :: GPU Core Clocks */
#define acmgt3__ext581__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext581 :: AVG GPU Core Frequency */
#define acmgt3__ext581__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext581 :: AVG GPU Core Frequency */
#define acmgt3__ext581__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext581 :: HIZ DEPTH TEST PASS P ZPIPE13 */
#define acmgt3__ext581__hiz_depth_test_pass_p_zpipe13__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext582 :: GPU Time Elapsed */
#define acmgt3__ext582__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext582 :: GPU Core Clocks */
#define acmgt3__ext582__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext582 :: AVG GPU Core Frequency */
#define acmgt3__ext582__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext582 :: AVG GPU Core Frequency */
#define acmgt3__ext582__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext582 :: HIZ DEPTH TEST PASS P ZPIPE14 */
#define acmgt3__ext582__hiz_depth_test_pass_p_zpipe14__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext583 :: GPU Time Elapsed */
#define acmgt3__ext583__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext583 :: GPU Core Clocks */
#define acmgt3__ext583__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext583 :: AVG GPU Core Frequency */
#define acmgt3__ext583__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext583 :: AVG GPU Core Frequency */
#define acmgt3__ext583__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext583 :: HIZ DEPTH TEST PASS P ZPIPE15 */
#define acmgt3__ext583__hiz_depth_test_pass_p_zpipe15__read \
   acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext584 :: GPU Time Elapsed */
#define acmgt3__ext584__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext584 :: GPU Core Clocks */
#define acmgt3__ext584__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext584 :: AVG GPU Core Frequency */
#define acmgt3__ext584__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext584 :: AVG GPU Core Frequency */
#define acmgt3__ext584__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext584 :: IZ OUTPUT READY ZPIPE0 */
#define acmgt3__ext584__iz_output_ready_zpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext584 :: IZ OUTPUT READY ZPIPE1 */
#define acmgt3__ext584__iz_output_ready_zpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext584 :: IZ OUTPUT READY ZPIPE2 */
#define acmgt3__ext584__iz_output_ready_zpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext584 :: IZ OUTPUT READY ZPIPE3 */
#define acmgt3__ext584__iz_output_ready_zpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext584 :: IZ OUTPUT READY ZPIPE4 */
#define acmgt3__ext584__iz_output_ready_zpipe4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext584 :: IZ OUTPUT READY ZPIPE5 */
#define acmgt3__ext584__iz_output_ready_zpipe5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext584 :: IZ OUTPUT READY ZPIPE6 */
#define acmgt3__ext584__iz_output_ready_zpipe6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext584 :: IZ OUTPUT READY ZPIPE7 */
#define acmgt3__ext584__iz_output_ready_zpipe7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext584 :: IZ OUTPUT READY ZPIPE8 */
#define acmgt3__ext584__iz_output_ready_zpipe8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext584 :: IZ OUTPUT READY ZPIPE9 */
#define acmgt3__ext584__iz_output_ready_zpipe9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext584 :: IZ OUTPUT READY ZPIPE10 */
#define acmgt3__ext584__iz_output_ready_zpipe10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext584 :: IZ OUTPUT READY ZPIPE11 */
#define acmgt3__ext584__iz_output_ready_zpipe11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext584 :: IZ OUTPUT READY ZPIPE12 */
#define acmgt3__ext584__iz_output_ready_zpipe12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext584 :: IZ OUTPUT READY ZPIPE13 */
#define acmgt3__ext584__iz_output_ready_zpipe13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext584 :: IZ OUTPUT READY ZPIPE14 */
#define acmgt3__ext584__iz_output_ready_zpipe14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext584 :: IZ OUTPUT READY ZPIPE15 */
#define acmgt3__ext584__iz_output_ready_zpipe15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext585 :: GPU Time Elapsed */
#define acmgt3__ext585__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext585 :: GPU Core Clocks */
#define acmgt3__ext585__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext585 :: AVG GPU Core Frequency */
#define acmgt3__ext585__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext585 :: AVG GPU Core Frequency */
#define acmgt3__ext585__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE4 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE5 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE6 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE7 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE8 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE9 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE10 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE11 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE12 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE13 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE14 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext585 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE15 */
#define acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext586 :: GPU Time Elapsed */
#define acmgt3__ext586__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext586 :: GPU Core Clocks */
#define acmgt3__ext586__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext586 :: AVG GPU Core Frequency */
#define acmgt3__ext586__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext586 :: AVG GPU Core Frequency */
#define acmgt3__ext586__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE2 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE3 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE4 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE5 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE6 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE7 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE8 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE9 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE10 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE11 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE12 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE13 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE14 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext586 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE15 */
#define acmgt3__ext586__iz_subspan_latency_fifofull_zpipe15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext587 :: GPU Time Elapsed */
#define acmgt3__ext587__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext587 :: GPU Core Clocks */
#define acmgt3__ext587__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext587 :: AVG GPU Core Frequency */
#define acmgt3__ext587__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext587 :: AVG GPU Core Frequency */
#define acmgt3__ext587__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE0 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE1 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE2 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE3 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE4 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE5 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE6 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE7 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE8 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE9 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE10 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE11 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE12 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE13 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE14 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext587 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE15 */
#define acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext588 :: GPU Time Elapsed */
#define acmgt3__ext588__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext588 :: GPU Core Clocks */
#define acmgt3__ext588__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext588 :: AVG GPU Core Frequency */
#define acmgt3__ext588__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext588 :: AVG GPU Core Frequency */
#define acmgt3__ext588__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext588 :: PS OUTPUT AVAILABLE CPIPE0 */
#define acmgt3__ext588__ps_output_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext588 :: PS OUTPUT AVAILABLE CPIPE1 */
#define acmgt3__ext588__ps_output_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext588 :: PS OUTPUT AVAILABLE CPIPE2 */
#define acmgt3__ext588__ps_output_available_cpipe2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext588 :: PS OUTPUT AVAILABLE CPIPE3 */
#define acmgt3__ext588__ps_output_available_cpipe3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext588 :: PS OUTPUT AVAILABLE CPIPE4 */
#define acmgt3__ext588__ps_output_available_cpipe4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext588 :: PS OUTPUT AVAILABLE CPIPE5 */
#define acmgt3__ext588__ps_output_available_cpipe5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext588 :: PS OUTPUT AVAILABLE CPIPE6 */
#define acmgt3__ext588__ps_output_available_cpipe6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext588 :: PS OUTPUT AVAILABLE CPIPE7 */
#define acmgt3__ext588__ps_output_available_cpipe7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext589 :: GPU Time Elapsed */
#define acmgt3__ext589__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext589 :: GPU Core Clocks */
#define acmgt3__ext589__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext589 :: AVG GPU Core Frequency */
#define acmgt3__ext589__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext589 :: AVG GPU Core Frequency */
#define acmgt3__ext589__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext589 :: PS OUTPUT AVAILABLE CPIPE8 */
#define acmgt3__ext589__ps_output_available_cpipe8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext589 :: PS OUTPUT AVAILABLE CPIPE9 */
#define acmgt3__ext589__ps_output_available_cpipe9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext589 :: PS OUTPUT AVAILABLE CPIPE10 */
#define acmgt3__ext589__ps_output_available_cpipe10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext589 :: PS OUTPUT AVAILABLE CPIPE11 */
#define acmgt3__ext589__ps_output_available_cpipe11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext589 :: PS OUTPUT AVAILABLE CPIPE12 */
#define acmgt3__ext589__ps_output_available_cpipe12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext589 :: PS OUTPUT AVAILABLE CPIPE13 */
#define acmgt3__ext589__ps_output_available_cpipe13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext589 :: PS OUTPUT AVAILABLE CPIPE14 */
#define acmgt3__ext589__ps_output_available_cpipe14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext589 :: PS OUTPUT AVAILABLE CPIPE15 */
#define acmgt3__ext589__ps_output_available_cpipe15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext590 :: GPU Time Elapsed */
#define acmgt3__ext590__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext590 :: GPU Core Clocks */
#define acmgt3__ext590__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext590 :: AVG GPU Core Frequency */
#define acmgt3__ext590__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext590 :: AVG GPU Core Frequency */
#define acmgt3__ext590__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE0 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE1 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE2 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE3 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE4 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE5 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE6 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE7 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE8 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE9 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE10 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE11 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE12 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE13 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE14 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext590 :: PIXEL POST PROCESS OUTPUT READY CPIPE15 */
#define acmgt3__ext590__pixel_post_process_output_ready_cpipe15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext591 :: GPU Time Elapsed */
#define acmgt3__ext591__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext591 :: GPU Core Clocks */
#define acmgt3__ext591__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext591 :: AVG GPU Core Frequency */
#define acmgt3__ext591__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext591 :: AVG GPU Core Frequency */
#define acmgt3__ext591__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext591 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE0 */
#define acmgt3__ext591__pixel_post_process_input_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext591 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE1 */
#define acmgt3__ext591__pixel_post_process_input_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext592 :: GPU Time Elapsed */
#define acmgt3__ext592__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext592 :: GPU Core Clocks */
#define acmgt3__ext592__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext592 :: AVG GPU Core Frequency */
#define acmgt3__ext592__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext592 :: AVG GPU Core Frequency */
#define acmgt3__ext592__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext592 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE2 */
#define acmgt3__ext592__pixel_post_process_input_available_cpipe2__read \
   bdw__render_basic__sampler0_busy__read

/* Ext592 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE3 */
#define acmgt3__ext592__pixel_post_process_input_available_cpipe3__read \
   bdw__render_basic__sampler1_busy__read

/* Ext593 :: GPU Time Elapsed */
#define acmgt3__ext593__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext593 :: GPU Core Clocks */
#define acmgt3__ext593__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext593 :: AVG GPU Core Frequency */
#define acmgt3__ext593__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext593 :: AVG GPU Core Frequency */
#define acmgt3__ext593__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext593 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE4 */
#define acmgt3__ext593__pixel_post_process_input_available_cpipe4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext593 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE5 */
#define acmgt3__ext593__pixel_post_process_input_available_cpipe5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext594 :: GPU Time Elapsed */
#define acmgt3__ext594__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext594 :: GPU Core Clocks */
#define acmgt3__ext594__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext594 :: AVG GPU Core Frequency */
#define acmgt3__ext594__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext594 :: AVG GPU Core Frequency */
#define acmgt3__ext594__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext594 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE6 */
#define acmgt3__ext594__pixel_post_process_input_available_cpipe6__read \
   bdw__render_basic__sampler0_busy__read

/* Ext594 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE7 */
#define acmgt3__ext594__pixel_post_process_input_available_cpipe7__read \
   bdw__render_basic__sampler1_busy__read

/* Ext595 :: GPU Time Elapsed */
#define acmgt3__ext595__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext595 :: GPU Core Clocks */
#define acmgt3__ext595__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext595 :: AVG GPU Core Frequency */
#define acmgt3__ext595__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext595 :: AVG GPU Core Frequency */
#define acmgt3__ext595__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext595 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE8 */
#define acmgt3__ext595__pixel_post_process_input_available_cpipe8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext595 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE9 */
#define acmgt3__ext595__pixel_post_process_input_available_cpipe9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext596 :: GPU Time Elapsed */
#define acmgt3__ext596__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext596 :: GPU Core Clocks */
#define acmgt3__ext596__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext596 :: AVG GPU Core Frequency */
#define acmgt3__ext596__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext596 :: AVG GPU Core Frequency */
#define acmgt3__ext596__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext596 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE10 */
#define acmgt3__ext596__pixel_post_process_input_available_cpipe10__read \
   bdw__render_basic__sampler0_busy__read

/* Ext596 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE11 */
#define acmgt3__ext596__pixel_post_process_input_available_cpipe11__read \
   bdw__render_basic__sampler1_busy__read

/* Ext597 :: GPU Time Elapsed */
#define acmgt3__ext597__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext597 :: GPU Core Clocks */
#define acmgt3__ext597__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext597 :: AVG GPU Core Frequency */
#define acmgt3__ext597__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext597 :: AVG GPU Core Frequency */
#define acmgt3__ext597__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext597 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE12 */
#define acmgt3__ext597__pixel_post_process_input_available_cpipe12__read \
   bdw__render_basic__sampler0_busy__read

/* Ext597 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE13 */
#define acmgt3__ext597__pixel_post_process_input_available_cpipe13__read \
   bdw__render_basic__sampler1_busy__read

/* Ext598 :: GPU Time Elapsed */
#define acmgt3__ext598__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext598 :: GPU Core Clocks */
#define acmgt3__ext598__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext598 :: AVG GPU Core Frequency */
#define acmgt3__ext598__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext598 :: AVG GPU Core Frequency */
#define acmgt3__ext598__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext598 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE14 */
#define acmgt3__ext598__pixel_post_process_input_available_cpipe14__read \
   bdw__render_basic__sampler0_busy__read

/* Ext598 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE15 */
#define acmgt3__ext598__pixel_post_process_input_available_cpipe15__read \
   bdw__render_basic__sampler1_busy__read

/* Ext599 :: GPU Time Elapsed */
#define acmgt3__ext599__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext599 :: GPU Core Clocks */
#define acmgt3__ext599__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext599 :: AVG GPU Core Frequency */
#define acmgt3__ext599__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext599 :: AVG GPU Core Frequency */
#define acmgt3__ext599__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext599 :: AMFS STALL ALL INPUT SLICE0 */
#define acmgt3__ext599__amfs_stall_all_input_slice0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext599 :: AMFS STALL ANY INPUT SLICE0 */
#define acmgt3__ext599__amfs_stall_any_input_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext599 :: AMFS CACHE HIT SLICE0 */
#define acmgt3__ext599__amfs_cache_hit_slice0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext599 :: AMFS CACHE MISS SLICE0 */
#define acmgt3__ext599__amfs_cache_miss_slice0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext599 :: RENDER CACHE HIT L3NODE0 */
#define acmgt3__ext599__render_cache_hit_l3_node0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext599 :: RENDER CACHE READ L3NODE0 */
#define acmgt3__ext599__render_cache_read_l3_node0__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext599 :: RENDER CACHE WRITE L3NODE0 */
#define acmgt3__ext599__render_cache_write_l3_node0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext599 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE0 */
#define acmgt3__ext599__render_cache_input_available_l3_node0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext599 :: RENDER_CACHE_OUTPUT_READY _L3NODE0 */
#define acmgt3__ext599__render_cache_output_ready_l3_node0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext600 :: GPU Time Elapsed */
#define acmgt3__ext600__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext600 :: GPU Core Clocks */
#define acmgt3__ext600__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext600 :: AVG GPU Core Frequency */
#define acmgt3__ext600__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext600 :: AVG GPU Core Frequency */
#define acmgt3__ext600__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext600 :: AMFS STALL ALL INPUT SLICE1 */
#define acmgt3__ext600__amfs_stall_all_input_slice1__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext600 :: AMFS STALL ANY INPUT SLICE1 */
#define acmgt3__ext600__amfs_stall_any_input_slice1__read \
   bdw__render_basic__sampler0_busy__read

/* Ext600 :: AMFS CACHE HIT SLICE1 */
#define acmgt3__ext600__amfs_cache_hit_slice1__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext600 :: AMFS CACHE MISS SLICE1 */
#define acmgt3__ext600__amfs_cache_miss_slice1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext600 :: RENDER CACHE HIT L3NODE1 */
#define acmgt3__ext600__render_cache_hit_l3_node1__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext600 :: RENDER CACHE READ L3NODE1 */
#define acmgt3__ext600__render_cache_read_l3_node1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext600 :: RENDER CACHE WRITE L3NODE1 */
#define acmgt3__ext600__render_cache_write_l3_node1__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext600 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE1 */
#define acmgt3__ext600__render_cache_input_available_l3_node1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext600 :: RENDER_CACHE_OUTPUT_READY _L3NODE1 */
#define acmgt3__ext600__render_cache_output_ready_l3_node1__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext601 :: GPU Time Elapsed */
#define acmgt3__ext601__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext601 :: GPU Core Clocks */
#define acmgt3__ext601__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext601 :: AVG GPU Core Frequency */
#define acmgt3__ext601__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext601 :: AVG GPU Core Frequency */
#define acmgt3__ext601__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext601 :: AMFS STALL ALL INPUT SLICE2 */
#define acmgt3__ext601__amfs_stall_all_input_slice2__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext601 :: AMFS STALL ANY INPUT SLICE2 */
#define acmgt3__ext601__amfs_stall_any_input_slice2__read \
   bdw__render_basic__sampler0_busy__read

/* Ext601 :: AMFS CACHE HIT SLICE2 */
#define acmgt3__ext601__amfs_cache_hit_slice2__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext601 :: AMFS CACHE MISS SLICE2 */
#define acmgt3__ext601__amfs_cache_miss_slice2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext601 :: RENDER CACHE HIT L3NODE2 */
#define acmgt3__ext601__render_cache_hit_l3_node2__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext601 :: RENDER CACHE READ L3NODE2 */
#define acmgt3__ext601__render_cache_read_l3_node2__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext601 :: RENDER CACHE WRITE L3NODE2 */
#define acmgt3__ext601__render_cache_write_l3_node2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext601 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE2 */
#define acmgt3__ext601__render_cache_input_available_l3_node2__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext601 :: RENDER_CACHE_OUTPUT_READY _L3NODE2 */
#define acmgt3__ext601__render_cache_output_ready_l3_node2__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext602 :: GPU Time Elapsed */
#define acmgt3__ext602__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext602 :: GPU Core Clocks */
#define acmgt3__ext602__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext602 :: AVG GPU Core Frequency */
#define acmgt3__ext602__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext602 :: AVG GPU Core Frequency */
#define acmgt3__ext602__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext602 :: AMFS STALL ALL INPUT SLICE3 */
#define acmgt3__ext602__amfs_stall_all_input_slice3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext602 :: AMFS STALL ANY INPUT SLICE3 */
#define acmgt3__ext602__amfs_stall_any_input_slice3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext602 :: AMFS CACHE HIT SLICE3 */
#define acmgt3__ext602__amfs_cache_hit_slice3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext602 :: AMFS CACHE MISS SLICE3 */
#define acmgt3__ext602__amfs_cache_miss_slice3__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext602 :: RENDER CACHE HIT L3NODE3 */
#define acmgt3__ext602__render_cache_hit_l3_node3__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext602 :: RENDER CACHE READ L3NODE3 */
#define acmgt3__ext602__render_cache_read_l3_node3__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext602 :: RENDER CACHE WRITE L3NODE3 */
#define acmgt3__ext602__render_cache_write_l3_node3__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext602 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE3 */
#define acmgt3__ext602__render_cache_input_available_l3_node3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext602 :: RENDER_CACHE_OUTPUT_READY _L3NODE3 */
#define acmgt3__ext602__render_cache_output_ready_l3_node3__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext603 :: GPU Time Elapsed */
#define acmgt3__ext603__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext603 :: GPU Core Clocks */
#define acmgt3__ext603__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext603 :: AVG GPU Core Frequency */
#define acmgt3__ext603__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext603 :: AVG GPU Core Frequency */
#define acmgt3__ext603__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext603 :: AMFS STALL ALL INPUT SLICE4 */
#define acmgt3__ext603__amfs_stall_all_input_slice4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext603 :: AMFS STALL ANY INPUT SLICE4 */
#define acmgt3__ext603__amfs_stall_any_input_slice4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext603 :: AMFS CACHE HIT SLICE4 */
#define acmgt3__ext603__amfs_cache_hit_slice4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext603 :: AMFS CACHE MISS SLICE4 */
#define acmgt3__ext603__amfs_cache_miss_slice4__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext603 :: RENDER CACHE HIT L3NODE4 */
#define acmgt3__ext603__render_cache_hit_l3_node4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext603 :: RENDER CACHE READ L3NODE4 */
#define acmgt3__ext603__render_cache_read_l3_node4__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext603 :: RENDER CACHE WRITE L3NODE4 */
#define acmgt3__ext603__render_cache_write_l3_node4__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext603 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE4 */
#define acmgt3__ext603__render_cache_input_available_l3_node4__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext603 :: RENDER_CACHE_OUTPUT_READY _L3NODE4 */
#define acmgt3__ext603__render_cache_output_ready_l3_node4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext604 :: GPU Time Elapsed */
#define acmgt3__ext604__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext604 :: GPU Core Clocks */
#define acmgt3__ext604__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext604 :: AVG GPU Core Frequency */
#define acmgt3__ext604__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext604 :: AVG GPU Core Frequency */
#define acmgt3__ext604__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext604 :: AMFS STALL ALL INPUT SLICE5 */
#define acmgt3__ext604__amfs_stall_all_input_slice5__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext604 :: AMFS STALL ANY INPUT SLICE5 */
#define acmgt3__ext604__amfs_stall_any_input_slice5__read \
   bdw__render_basic__sampler0_busy__read

/* Ext604 :: AMFS CACHE HIT SLICE5 */
#define acmgt3__ext604__amfs_cache_hit_slice5__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext604 :: AMFS CACHE MISS SLICE5 */
#define acmgt3__ext604__amfs_cache_miss_slice5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext604 :: RENDER CACHE HIT L3NODE5 */
#define acmgt3__ext604__render_cache_hit_l3_node5__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext604 :: RENDER CACHE READ L3NODE5 */
#define acmgt3__ext604__render_cache_read_l3_node5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext604 :: RENDER CACHE WRITE L3NODE5 */
#define acmgt3__ext604__render_cache_write_l3_node5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext604 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE5 */
#define acmgt3__ext604__render_cache_input_available_l3_node5__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext604 :: RENDER_CACHE_OUTPUT_READY _L3NODE5 */
#define acmgt3__ext604__render_cache_output_ready_l3_node5__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext605 :: GPU Time Elapsed */
#define acmgt3__ext605__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext605 :: GPU Core Clocks */
#define acmgt3__ext605__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext605 :: AVG GPU Core Frequency */
#define acmgt3__ext605__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext605 :: AVG GPU Core Frequency */
#define acmgt3__ext605__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext605 :: AMFS STALL ALL INPUT SLICE6 */
#define acmgt3__ext605__amfs_stall_all_input_slice6__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext605 :: AMFS STALL ANY INPUT SLICE6 */
#define acmgt3__ext605__amfs_stall_any_input_slice6__read \
   bdw__render_basic__sampler0_busy__read

/* Ext605 :: AMFS CACHE HIT SLICE6 */
#define acmgt3__ext605__amfs_cache_hit_slice6__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext605 :: AMFS CACHE MISS SLICE6 */
#define acmgt3__ext605__amfs_cache_miss_slice6__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext605 :: RENDER CACHE HIT L3NODE6 */
#define acmgt3__ext605__render_cache_hit_l3_node6__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext605 :: RENDER CACHE READ L3NODE6 */
#define acmgt3__ext605__render_cache_read_l3_node6__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext605 :: RENDER CACHE WRITE L3NODE6 */
#define acmgt3__ext605__render_cache_write_l3_node6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext605 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE6 */
#define acmgt3__ext605__render_cache_input_available_l3_node6__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext605 :: RENDER_CACHE_OUTPUT_READY _L3NODE6 */
#define acmgt3__ext605__render_cache_output_ready_l3_node6__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext606 :: GPU Time Elapsed */
#define acmgt3__ext606__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext606 :: GPU Core Clocks */
#define acmgt3__ext606__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext606 :: AVG GPU Core Frequency */
#define acmgt3__ext606__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext606 :: AVG GPU Core Frequency */
#define acmgt3__ext606__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext606 :: AMFS STALL ALL INPUT SLICE7 */
#define acmgt3__ext606__amfs_stall_all_input_slice7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext606 :: AMFS STALL ANY INPUT SLICE7 */
#define acmgt3__ext606__amfs_stall_any_input_slice7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext606 :: AMFS CACHE HIT SLICE7 */
#define acmgt3__ext606__amfs_cache_hit_slice7__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext606 :: AMFS CACHE MISS SLICE7 */
#define acmgt3__ext606__amfs_cache_miss_slice7__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext606 :: RENDER CACHE HIT L3NODE7 */
#define acmgt3__ext606__render_cache_hit_l3_node7__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext606 :: RENDER CACHE READ L3NODE7 */
#define acmgt3__ext606__render_cache_read_l3_node7__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext606 :: RENDER CACHE WRITE L3NODE7 */
#define acmgt3__ext606__render_cache_write_l3_node7__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext606 :: RENDER_CACHE_INPUT_AVAILABLE _L3NODE7 */
#define acmgt3__ext606__render_cache_input_available_l3_node7__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext606 :: RENDER_CACHE_OUTPUT_READY _L3NODE7 */
#define acmgt3__ext606__render_cache_output_ready_l3_node7__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext607 :: GPU Time Elapsed */
#define acmgt3__ext607__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext607 :: GPU Core Clocks */
#define acmgt3__ext607__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext607 :: AVG GPU Core Frequency */
#define acmgt3__ext607__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext607 :: AVG GPU Core Frequency */
#define acmgt3__ext607__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext607 :: AMFS 4X4 SHADING REQUEST SLICE0 */
#define acmgt3__ext607__amfs_4_x4_shading_request_slice0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext607 :: AMFS 4X4 SHADING REQUEST SLICE1 */
#define acmgt3__ext607__amfs_4_x4_shading_request_slice1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext607 :: AMFS 4X4 SHADING REQUEST SLICE2 */
#define acmgt3__ext607__amfs_4_x4_shading_request_slice2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext607 :: AMFS 4X4 SHADING REQUEST SLICE3 */
#define acmgt3__ext607__amfs_4_x4_shading_request_slice3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext607 :: AMFS 4X4 SHADING REQUEST SLICE4 */
#define acmgt3__ext607__amfs_4_x4_shading_request_slice4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext607 :: AMFS 4X4 SHADING REQUEST SLICE5 */
#define acmgt3__ext607__amfs_4_x4_shading_request_slice5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext607 :: AMFS 4X4 SHADING REQUEST SLICE6 */
#define acmgt3__ext607__amfs_4_x4_shading_request_slice6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext607 :: AMFS 4X4 SHADING REQUEST SLICE7 */
#define acmgt3__ext607__amfs_4_x4_shading_request_slice7__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext608 :: GPU Time Elapsed */
#define acmgt3__ext608__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext608 :: GPU Core Clocks */
#define acmgt3__ext608__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext608 :: AVG GPU Core Frequency */
#define acmgt3__ext608__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext608 :: AVG GPU Core Frequency */
#define acmgt3__ext608__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext608 :: AMFS L3 ATOMIC SLICE0 */
#define acmgt3__ext608__amfs_l3_atomic_slice0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext608 :: AMFS L3 ATOMIC SLICE1 */
#define acmgt3__ext608__amfs_l3_atomic_slice1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext608 :: AMFS L3 ATOMIC SLICE2 */
#define acmgt3__ext608__amfs_l3_atomic_slice2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext608 :: AMFS L3 ATOMIC SLICE3 */
#define acmgt3__ext608__amfs_l3_atomic_slice3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext608 :: AMFS L3 ATOMIC SLICE4 */
#define acmgt3__ext608__amfs_l3_atomic_slice4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext608 :: AMFS L3 ATOMIC SLICE5 */
#define acmgt3__ext608__amfs_l3_atomic_slice5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext608 :: AMFS L3 ATOMIC SLICE6 */
#define acmgt3__ext608__amfs_l3_atomic_slice6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext608 :: AMFS L3 ATOMIC SLICE7 */
#define acmgt3__ext608__amfs_l3_atomic_slice7__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext609 :: GPU Time Elapsed */
#define acmgt3__ext609__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext609 :: GPU Core Clocks */
#define acmgt3__ext609__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext609 :: AVG GPU Core Frequency */
#define acmgt3__ext609__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext609 :: AVG GPU Core Frequency */
#define acmgt3__ext609__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext609 :: AMFS L3 ACCESS SLICE0 */
#define acmgt3__ext609__amfs_l3_access_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext609 :: AMFS L3 ACCESS SLICE1 */
#define acmgt3__ext609__amfs_l3_access_slice1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext609 :: AMFS L3 ACCESS SLICE2 */
#define acmgt3__ext609__amfs_l3_access_slice2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext609 :: AMFS L3 ACCESS SLICE3 */
#define acmgt3__ext609__amfs_l3_access_slice3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext609 :: AMFS L3 ACCESS SLICE4 */
#define acmgt3__ext609__amfs_l3_access_slice4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext609 :: AMFS L3 ACCESS SLICE5 */
#define acmgt3__ext609__amfs_l3_access_slice5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext609 :: AMFS L3 ACCESS SLICE6 */
#define acmgt3__ext609__amfs_l3_access_slice6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext609 :: AMFS L3 ACCESS SLICE7 */
#define acmgt3__ext609__amfs_l3_access_slice7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext610 :: GPU Time Elapsed */
#define acmgt3__ext610__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext610 :: GPU Core Clocks */
#define acmgt3__ext610__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext610 :: AVG GPU Core Frequency */
#define acmgt3__ext610__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext610 :: AVG GPU Core Frequency */
#define acmgt3__ext610__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext610 :: AMFS L3 WRITE SLICE0 */
#define acmgt3__ext610__amfs_l3_write_slice0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext610 :: AMFS L3 WRITE SLICE1 */
#define acmgt3__ext610__amfs_l3_write_slice1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext610 :: AMFS L3 WRITE SLICE2 */
#define acmgt3__ext610__amfs_l3_write_slice2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext610 :: AMFS L3 WRITE SLICE3 */
#define acmgt3__ext610__amfs_l3_write_slice3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext610 :: AMFS L3 WRITE SLICE4 */
#define acmgt3__ext610__amfs_l3_write_slice4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext610 :: AMFS L3 WRITE SLICE5 */
#define acmgt3__ext610__amfs_l3_write_slice5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext610 :: AMFS L3 WRITE SLICE6 */
#define acmgt3__ext610__amfs_l3_write_slice6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext610 :: AMFS L3 WRITE SLICE7 */
#define acmgt3__ext610__amfs_l3_write_slice7__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext611 :: GPU Time Elapsed */
#define acmgt3__ext611__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext611 :: GPU Core Clocks */
#define acmgt3__ext611__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext611 :: AVG GPU Core Frequency */
#define acmgt3__ext611__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext611 :: AVG GPU Core Frequency */
#define acmgt3__ext611__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext611 :: CLIPPER INPUT VERTEX SLICE0 */
#define acmgt3__ext611__clipper_input_vertex_slice0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext611 :: CLIPPER INPUT VERTEX SLICE1 */
#define acmgt3__ext611__clipper_input_vertex_slice1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext611 :: CLIPPER INPUT VERTEX SLICE2 */
#define acmgt3__ext611__clipper_input_vertex_slice2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext611 :: CLIPPER INPUT VERTEX SLICE3 */
#define acmgt3__ext611__clipper_input_vertex_slice3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext611 :: STREAMOUT OUTPUT VERTEX COUNT SLICE0 */
#define acmgt3__ext611__streamout_output_vertex_count_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext611 :: STREAMOUT OUTPUT VERTEX COUNT SLICE1 */
#define acmgt3__ext611__streamout_output_vertex_count_slice1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext611 :: STREAMOUT OUTPUT VERTEX COUNT SLICE2 */
#define acmgt3__ext611__streamout_output_vertex_count_slice2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext611 :: STREAMOUT OUTPUT VERTEX COUNT SLICE3 */
#define acmgt3__ext611__streamout_output_vertex_count_slice3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext612 :: GPU Time Elapsed */
#define acmgt3__ext612__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext612 :: GPU Core Clocks */
#define acmgt3__ext612__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext612 :: AVG GPU Core Frequency */
#define acmgt3__ext612__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext612 :: AVG GPU Core Frequency */
#define acmgt3__ext612__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext612 :: CLIPPER INPUT VERTEX SLICE4 */
#define acmgt3__ext612__clipper_input_vertex_slice4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext612 :: CLIPPER INPUT VERTEX SLICE5 */
#define acmgt3__ext612__clipper_input_vertex_slice5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext612 :: CLIPPER INPUT VERTEX SLICE6 */
#define acmgt3__ext612__clipper_input_vertex_slice6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext612 :: CLIPPER INPUT VERTEX SLICE7 */
#define acmgt3__ext612__clipper_input_vertex_slice7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext612 :: STREAMOUT OUTPUT VERTEX COUNT SLICE4 */
#define acmgt3__ext612__streamout_output_vertex_count_slice4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext612 :: STREAMOUT OUTPUT VERTEX COUNT SLICE5 */
#define acmgt3__ext612__streamout_output_vertex_count_slice5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext612 :: STREAMOUT OUTPUT VERTEX COUNT SLICE6 */
#define acmgt3__ext612__streamout_output_vertex_count_slice6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext612 :: STREAMOUT OUTPUT VERTEX COUNT SLICE7 */
#define acmgt3__ext612__streamout_output_vertex_count_slice7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext613 :: GPU Time Elapsed */
#define acmgt3__ext613__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext613 :: GPU Core Clocks */
#define acmgt3__ext613__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext613 :: AVG GPU Core Frequency */
#define acmgt3__ext613__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext613 :: AVG GPU Core Frequency */
#define acmgt3__ext613__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext613 :: VERTEX FETCH INPUT AVAILABLE SLICE0 */
#define acmgt3__ext613__vertex_fetch_input_available_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext613 :: VERTEX FETCH INPUT AVAILABLE SLICE1 */
#define acmgt3__ext613__vertex_fetch_input_available_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext613 :: VERTEX FETCH INPUT AVAILABLE SLICE2 */
#define acmgt3__ext613__vertex_fetch_input_available_slice2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext613 :: VERTEX FETCH INPUT AVAILABLE SLICE3 */
#define acmgt3__ext613__vertex_fetch_input_available_slice3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext613 :: VERTEX FETCH INPUT AVAILABLE SLICE4 */
#define acmgt3__ext613__vertex_fetch_input_available_slice4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext613 :: VERTEX FETCH INPUT AVAILABLE SLICE5 */
#define acmgt3__ext613__vertex_fetch_input_available_slice5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext613 :: VERTEX FETCH INPUT AVAILABLE SLICE6 */
#define acmgt3__ext613__vertex_fetch_input_available_slice6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext613 :: VERTEX FETCH INPUT AVAILABLE SLICE7 */
#define acmgt3__ext613__vertex_fetch_input_available_slice7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext613 :: VERTEX FETCH OUTPUT READY SLICE0 */
#define acmgt3__ext613__vertex_fetch_output_ready_slice0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext613 :: VERTEX FETCH OUTPUT READY SLICE1 */
#define acmgt3__ext613__vertex_fetch_output_ready_slice1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext613 :: VERTEX FETCH OUTPUT READY SLICE2 */
#define acmgt3__ext613__vertex_fetch_output_ready_slice2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext613 :: VERTEX FETCH OUTPUT READY SLICE3 */
#define acmgt3__ext613__vertex_fetch_output_ready_slice3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext613 :: VERTEX FETCH OUTPUT READY SLICE4 */
#define acmgt3__ext613__vertex_fetch_output_ready_slice4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext613 :: VERTEX FETCH OUTPUT READY SLICE5 */
#define acmgt3__ext613__vertex_fetch_output_ready_slice5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext613 :: VERTEX FETCH OUTPUT READY SLICE6 */
#define acmgt3__ext613__vertex_fetch_output_ready_slice6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext613 :: VERTEX FETCH OUTPUT READY SLICE7 */
#define acmgt3__ext613__vertex_fetch_output_ready_slice7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext614 :: GPU Time Elapsed */
#define acmgt3__ext614__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext614 :: GPU Core Clocks */
#define acmgt3__ext614__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext614 :: AVG GPU Core Frequency */
#define acmgt3__ext614__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext614 :: AVG GPU Core Frequency */
#define acmgt3__ext614__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext614 :: VS OUTPUT READY SLICE0 */
#define acmgt3__ext614__vs_output_ready_slice0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext614 :: VS OUTPUT READY SLICE1 */
#define acmgt3__ext614__vs_output_ready_slice1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext614 :: VS OUTPUT READY SLICE2 */
#define acmgt3__ext614__vs_output_ready_slice2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext614 :: VS OUTPUT READY SLICE3 */
#define acmgt3__ext614__vs_output_ready_slice3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext614 :: VS OUTPUT READY SLICE4 */
#define acmgt3__ext614__vs_output_ready_slice4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext614 :: VS OUTPUT READY SLICE5 */
#define acmgt3__ext614__vs_output_ready_slice5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext614 :: VS OUTPUT READY SLICE6 */
#define acmgt3__ext614__vs_output_ready_slice6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext614 :: VS OUTPUT READY SLICE7 */
#define acmgt3__ext614__vs_output_ready_slice7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext614 :: CLIPPER INPUT AVAILABLE SLICE0 */
#define acmgt3__ext614__clipper_input_available_slice0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext614 :: CLIPPER INPUT AVAILABLE SLICE1 */
#define acmgt3__ext614__clipper_input_available_slice1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext614 :: CLIPPER INPUT AVAILABLE SLICE2 */
#define acmgt3__ext614__clipper_input_available_slice2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext614 :: CLIPPER INPUT AVAILABLE SLICE3 */
#define acmgt3__ext614__clipper_input_available_slice3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext614 :: CLIPPER INPUT AVAILABLE SLICE4 */
#define acmgt3__ext614__clipper_input_available_slice4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext614 :: CLIPPER INPUT AVAILABLE SLICE5 */
#define acmgt3__ext614__clipper_input_available_slice5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext614 :: CLIPPER INPUT AVAILABLE SLICE6 */
#define acmgt3__ext614__clipper_input_available_slice6__read \
   bdw__render_basic__sampler1_busy__read

/* Ext614 :: CLIPPER INPUT AVAILABLE SLICE7 */
#define acmgt3__ext614__clipper_input_available_slice7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext615 :: GPU Time Elapsed */
#define acmgt3__ext615__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext615 :: GPU Core Clocks */
#define acmgt3__ext615__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext615 :: AVG GPU Core Frequency */
#define acmgt3__ext615__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext615 :: AVG GPU Core Frequency */
#define acmgt3__ext615__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext615 :: CLIPPER OUTPUT READY SLICE0 */
#define acmgt3__ext615__clipper_output_ready_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext615 :: CLIPPER OUTPUT READY SLICE1 */
#define acmgt3__ext615__clipper_output_ready_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext615 :: CLIPPER OUTPUT READY SLICE2 */
#define acmgt3__ext615__clipper_output_ready_slice2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext615 :: CLIPPER OUTPUT READY SLICE3 */
#define acmgt3__ext615__clipper_output_ready_slice3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext615 :: CLIPPER OUTPUT READY SLICE4 */
#define acmgt3__ext615__clipper_output_ready_slice4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext615 :: CLIPPER OUTPUT READY SLICE5 */
#define acmgt3__ext615__clipper_output_ready_slice5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext615 :: CLIPPER OUTPUT READY SLICE6 */
#define acmgt3__ext615__clipper_output_ready_slice6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext615 :: CLIPPER OUTPUT READY SLICE7 */
#define acmgt3__ext615__clipper_output_ready_slice7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext616 :: GPU Time Elapsed */
#define acmgt3__ext616__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext616 :: GPU Core Clocks */
#define acmgt3__ext616__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext616 :: AVG GPU Core Frequency */
#define acmgt3__ext616__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext616 :: AVG GPU Core Frequency */
#define acmgt3__ext616__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext616 :: GPU MEMORY WRITE SQIDI0 */
#define acmgt3__ext616__gpu_memory_write_sqidi0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext616 :: GPU MEMORY WRITE SQIDI1 */
#define acmgt3__ext616__gpu_memory_write_sqidi1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext616 :: GPU MEMORY WRITE SQIDI2 */
#define acmgt3__ext616__gpu_memory_write_sqidi2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext616 :: GPU MEMORY WRITE SQIDI3 */
#define acmgt3__ext616__gpu_memory_write_sqidi3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext616 :: GPU MEMORY WRITE SQIDI4 */
#define acmgt3__ext616__gpu_memory_write_sqidi4__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext616 :: GPU MEMORY WRITE SQIDI5 */
#define acmgt3__ext616__gpu_memory_write_sqidi5__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext616 :: GPU MEMORY WRITE SQIDI6 */
#define acmgt3__ext616__gpu_memory_write_sqidi6__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext616 :: GPU MEMORY WRITE SQIDI7 */
#define acmgt3__ext616__gpu_memory_write_sqidi7__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext616 :: GPU MEMORY WRITE */
static uint64_t
acmgt3__ext616__gpu_memory_write__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_WRITE_SQIDI2 $GPU_MEMORY_WRITE_SQIDI0 UADD $GPU_MEMORY_WRITE_SQIDI1 UADD $GPU_MEMORY_WRITE_SQIDI3 UADD $GPU_MEMORY_WRITE_SQIDI4 UADD $GPU_MEMORY_WRITE_SQIDI5 UADD $GPU_MEMORY_WRITE_SQIDI6 UADD $GPU_MEMORY_WRITE_SQIDI7 UADD */
   uint64_t tmp0 = acmgt3__ext616__gpu_memory_write_sqidi2__read(perf, query, results) + acmgt3__ext616__gpu_memory_write_sqidi0__read(perf, query, results);
   uint64_t tmp1 = tmp0 + acmgt3__ext616__gpu_memory_write_sqidi1__read(perf, query, results);
   uint64_t tmp2 = tmp1 + acmgt3__ext616__gpu_memory_write_sqidi3__read(perf, query, results);
   uint64_t tmp3 = tmp2 + acmgt3__ext616__gpu_memory_write_sqidi4__read(perf, query, results);
   uint64_t tmp4 = tmp3 + acmgt3__ext616__gpu_memory_write_sqidi5__read(perf, query, results);
   uint64_t tmp5 = tmp4 + acmgt3__ext616__gpu_memory_write_sqidi6__read(perf, query, results);
   uint64_t tmp6 = tmp5 + acmgt3__ext616__gpu_memory_write_sqidi7__read(perf, query, results);

   return tmp6;
}

/* Ext617 :: GPU Time Elapsed */
#define acmgt3__ext617__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext617 :: GPU Core Clocks */
#define acmgt3__ext617__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext617 :: AVG GPU Core Frequency */
#define acmgt3__ext617__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext617 :: AVG GPU Core Frequency */
#define acmgt3__ext617__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext617 :: CLIPPER PRIMITIVE OUTPUT SLICE0 */
#define acmgt3__ext617__clipper_primitive_output_slice0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext617 :: CLIPPER PRIMITIVE OUTPUT SLICE1 */
#define acmgt3__ext617__clipper_primitive_output_slice1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext617 :: CLIPPER PRIMITIVE OUTPUT SLICE2 */
#define acmgt3__ext617__clipper_primitive_output_slice2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext617 :: CLIPPER PRIMITIVE OUTPUT SLICE3 */
#define acmgt3__ext617__clipper_primitive_output_slice3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext617 :: CLIPPER PRIMITIVE OUTPUT SLICE4 */
#define acmgt3__ext617__clipper_primitive_output_slice4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext617 :: CLIPPER PRIMITIVE OUTPUT SLICE5 */
#define acmgt3__ext617__clipper_primitive_output_slice5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext617 :: CLIPPER PRIMITIVE OUTPUT SLICE6 */
#define acmgt3__ext617__clipper_primitive_output_slice6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext617 :: CLIPPER PRIMITIVE OUTPUT SLICE7 */
#define acmgt3__ext617__clipper_primitive_output_slice7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext618 :: GPU Time Elapsed */
#define acmgt3__ext618__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext618 :: GPU Core Clocks */
#define acmgt3__ext618__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext618 :: AVG GPU Core Frequency */
#define acmgt3__ext618__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext618 :: AVG GPU Core Frequency */
#define acmgt3__ext618__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext618 :: CLIPPER PRIMITIVE CULL SLICE0 */
#define acmgt3__ext618__clipper_primitive_cull_slice0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext618 :: CLIPPER PRIMITIVE CULL SLICE1 */
#define acmgt3__ext618__clipper_primitive_cull_slice1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext618 :: CLIPPER PRIMITIVE CULL SLICE2 */
#define acmgt3__ext618__clipper_primitive_cull_slice2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext618 :: CLIPPER PRIMITIVE CULL SLICE3 */
#define acmgt3__ext618__clipper_primitive_cull_slice3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext618 :: CLIPPER PRIMITIVE CULL SLICE4 */
#define acmgt3__ext618__clipper_primitive_cull_slice4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext618 :: CLIPPER PRIMITIVE CULL SLICE5 */
#define acmgt3__ext618__clipper_primitive_cull_slice5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext618 :: CLIPPER PRIMITIVE CULL SLICE6 */
#define acmgt3__ext618__clipper_primitive_cull_slice6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext618 :: CLIPPER PRIMITIVE CULL SLICE7 */
#define acmgt3__ext618__clipper_primitive_cull_slice7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext619 :: GPU Time Elapsed */
#define acmgt3__ext619__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext619 :: GPU Core Clocks */
#define acmgt3__ext619__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext619 :: AVG GPU Core Frequency */
#define acmgt3__ext619__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext619 :: AVG GPU Core Frequency */
#define acmgt3__ext619__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext619 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0 */
#define acmgt3__ext619__clipper_primitive_far_near_clip_slice0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext619 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1 */
#define acmgt3__ext619__clipper_primitive_far_near_clip_slice1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext619 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE2 */
#define acmgt3__ext619__clipper_primitive_far_near_clip_slice2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext619 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE3 */
#define acmgt3__ext619__clipper_primitive_far_near_clip_slice3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext620 :: GPU Time Elapsed */
#define acmgt3__ext620__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext620 :: GPU Core Clocks */
#define acmgt3__ext620__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext620 :: AVG GPU Core Frequency */
#define acmgt3__ext620__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext620 :: AVG GPU Core Frequency */
#define acmgt3__ext620__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext620 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE4 */
#define acmgt3__ext620__clipper_primitive_far_near_clip_slice4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext620 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE5 */
#define acmgt3__ext620__clipper_primitive_far_near_clip_slice5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext620 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE6 */
#define acmgt3__ext620__clipper_primitive_far_near_clip_slice6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext620 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE7 */
#define acmgt3__ext620__clipper_primitive_far_near_clip_slice7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext621 :: GPU Time Elapsed */
#define acmgt3__ext621__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext621 :: GPU Core Clocks */
#define acmgt3__ext621__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext621 :: AVG GPU Core Frequency */
#define acmgt3__ext621__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext621 :: AVG GPU Core Frequency */
#define acmgt3__ext621__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext621 :: CLIPPER TRANSACTION OUTPUT SLICE0 */
#define acmgt3__ext621__clipper_transaction_output_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext621 :: CLIPPER TRANSACTION OUTPUT SLICE1 */
#define acmgt3__ext621__clipper_transaction_output_slice1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext621 :: CLIPPER TRANSACTION OUTPUT SLICE2 */
#define acmgt3__ext621__clipper_transaction_output_slice2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext621 :: CLIPPER TRANSACTION OUTPUT SLICE3 */
#define acmgt3__ext621__clipper_transaction_output_slice3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext621 :: CLIPPER TRANSACTION OUTPUT SLICE4 */
#define acmgt3__ext621__clipper_transaction_output_slice4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext621 :: CLIPPER TRANSACTION OUTPUT SLICE5 */
#define acmgt3__ext621__clipper_transaction_output_slice5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext621 :: CLIPPER TRANSACTION OUTPUT SLICE6 */
#define acmgt3__ext621__clipper_transaction_output_slice6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext621 :: CLIPPER TRANSACTION OUTPUT SLICE7 */
#define acmgt3__ext621__clipper_transaction_output_slice7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext621 :: RASTERIZER INPUT AVAILABLE SLICE0 */
#define acmgt3__ext621__rasterizer_input_available_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext621 :: RASTERIZER INPUT AVAILABLE SLICE1 */
#define acmgt3__ext621__rasterizer_input_available_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext621 :: RASTERIZER INPUT AVAILABLE SLICE2 */
#define acmgt3__ext621__rasterizer_input_available_slice2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext621 :: RASTERIZER INPUT AVAILABLE SLICE3 */
#define acmgt3__ext621__rasterizer_input_available_slice3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext622 :: GPU Time Elapsed */
#define acmgt3__ext622__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext622 :: GPU Core Clocks */
#define acmgt3__ext622__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext622 :: AVG GPU Core Frequency */
#define acmgt3__ext622__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext622 :: AVG GPU Core Frequency */
#define acmgt3__ext622__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext622 :: RASTERIZER INPUT AVAILABLE SLICE4 */
#define acmgt3__ext622__rasterizer_input_available_slice4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext622 :: RASTERIZER INPUT AVAILABLE SLICE5 */
#define acmgt3__ext622__rasterizer_input_available_slice5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext622 :: RASTERIZER INPUT AVAILABLE SLICE6 */
#define acmgt3__ext622__rasterizer_input_available_slice6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext622 :: RASTERIZER INPUT AVAILABLE SLICE7 */
#define acmgt3__ext622__rasterizer_input_available_slice7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext622 :: RASTERIZER TRANSACTION OUTPUT SLICE0 */
#define acmgt3__ext622__rasterizer_transaction_output_slice0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext622 :: RASTERIZER TRANSACTION OUTPUT SLICE1 */
#define acmgt3__ext622__rasterizer_transaction_output_slice1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext622 :: RASTERIZER TRANSACTION OUTPUT SLICE2 */
#define acmgt3__ext622__rasterizer_transaction_output_slice2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext622 :: RASTERIZER TRANSACTION OUTPUT SLICE3 */
#define acmgt3__ext622__rasterizer_transaction_output_slice3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext623 :: GPU Time Elapsed */
#define acmgt3__ext623__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext623 :: GPU Core Clocks */
#define acmgt3__ext623__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext623 :: AVG GPU Core Frequency */
#define acmgt3__ext623__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext623 :: AVG GPU Core Frequency */
#define acmgt3__ext623__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext623 :: RASTERIZER TRANSACTION OUTPUT SLICE4 */
#define acmgt3__ext623__rasterizer_transaction_output_slice4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext623 :: RASTERIZER TRANSACTION OUTPUT SLICE5 */
#define acmgt3__ext623__rasterizer_transaction_output_slice5__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext623 :: RASTERIZER TRANSACTION OUTPUT SLICE6 */
#define acmgt3__ext623__rasterizer_transaction_output_slice6__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext623 :: RASTERIZER TRANSACTION OUTPUT SLICE7 */
#define acmgt3__ext623__rasterizer_transaction_output_slice7__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext623 :: STRIPSFAN OBJECTS CULL SLICE0 */
#define acmgt3__ext623__stripsfan_objects_cull_slice0__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext623 :: STRIPSFAN OBJECTS CULL SLICE1 */
#define acmgt3__ext623__stripsfan_objects_cull_slice1__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext623 :: STRIPSFAN OBJECTS CULL SLICE2 */
#define acmgt3__ext623__stripsfan_objects_cull_slice2__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext623 :: STRIPSFAN OBJECTS CULL SLICE3 */
#define acmgt3__ext623__stripsfan_objects_cull_slice3__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext624 :: GPU Time Elapsed */
#define acmgt3__ext624__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext624 :: GPU Core Clocks */
#define acmgt3__ext624__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext624 :: AVG GPU Core Frequency */
#define acmgt3__ext624__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext624 :: AVG GPU Core Frequency */
#define acmgt3__ext624__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext624 :: STRIPSFAN OBJECT COUNT SLICE0 */
#define acmgt3__ext624__stripsfan_object_count_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext624 :: STRIPSFAN OBJECT COUNT SLICE1 */
#define acmgt3__ext624__stripsfan_object_count_slice1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext624 :: STRIPSFAN OBJECT COUNT SLICE2 */
#define acmgt3__ext624__stripsfan_object_count_slice2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext624 :: STRIPSFAN OBJECT COUNT SLICE3 */
#define acmgt3__ext624__stripsfan_object_count_slice3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext624 :: STRIPSFAN OBJECT COUNT SLICE4 */
#define acmgt3__ext624__stripsfan_object_count_slice4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext624 :: STRIPSFAN OBJECT COUNT SLICE5 */
#define acmgt3__ext624__stripsfan_object_count_slice5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext624 :: STRIPSFAN OBJECT COUNT SLICE6 */
#define acmgt3__ext624__stripsfan_object_count_slice6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext624 :: STRIPSFAN OBJECT COUNT SLICE7 */
#define acmgt3__ext624__stripsfan_object_count_slice7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext624 :: RASTERIZER OUTPUT READY SLICE0 */
#define acmgt3__ext624__rasterizer_output_ready_slice0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext624 :: RASTERIZER OUTPUT READY SLICE1 */
#define acmgt3__ext624__rasterizer_output_ready_slice1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext624 :: RASTERIZER OUTPUT READY SLICE2 */
#define acmgt3__ext624__rasterizer_output_ready_slice2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext624 :: RASTERIZER OUTPUT READY SLICE3 */
#define acmgt3__ext624__rasterizer_output_ready_slice3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext624 :: RASTERIZER OUTPUT READY SLICE4 */
#define acmgt3__ext624__rasterizer_output_ready_slice4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext624 :: RASTERIZER OUTPUT READY SLICE5 */
#define acmgt3__ext624__rasterizer_output_ready_slice5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext624 :: RASTERIZER OUTPUT READY SLICE6 */
#define acmgt3__ext624__rasterizer_output_ready_slice6__read \
   bdw__render_basic__sampler1_busy__read

/* Ext624 :: RASTERIZER OUTPUT READY SLICE7 */
#define acmgt3__ext624__rasterizer_output_ready_slice7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext625 :: GPU Time Elapsed */
#define acmgt3__ext625__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext625 :: GPU Core Clocks */
#define acmgt3__ext625__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext625 :: AVG GPU Core Frequency */
#define acmgt3__ext625__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext625 :: AVG GPU Core Frequency */
#define acmgt3__ext625__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext625 :: STRIPSFAN OBJECTS CULL SLICE4 */
#define acmgt3__ext625__stripsfan_objects_cull_slice4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext625 :: STRIPSFAN OBJECTS CULL SLICE5 */
#define acmgt3__ext625__stripsfan_objects_cull_slice5__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext625 :: STRIPSFAN OBJECTS CULL SLICE6 */
#define acmgt3__ext625__stripsfan_objects_cull_slice6__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext625 :: STRIPSFAN OBJECTS CULL SLICE7 */
#define acmgt3__ext625__stripsfan_objects_cull_slice7__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext625 :: STRIPSFAN OUTPUT READY SLICE0 */
#define acmgt3__ext625__stripsfan_output_ready_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext625 :: STRIPSFAN OUTPUT READY SLICE1 */
#define acmgt3__ext625__stripsfan_output_ready_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext625 :: STRIPSFAN OUTPUT READY SLICE2 */
#define acmgt3__ext625__stripsfan_output_ready_slice2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext625 :: STRIPSFAN OUTPUT READY SLICE3 */
#define acmgt3__ext625__stripsfan_output_ready_slice3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext625 :: STRIPSFAN OUTPUT READY SLICE4 */
#define acmgt3__ext625__stripsfan_output_ready_slice4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext625 :: STRIPSFAN OUTPUT READY SLICE5 */
#define acmgt3__ext625__stripsfan_output_ready_slice5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext625 :: STRIPSFAN OUTPUT READY SLICE6 */
#define acmgt3__ext625__stripsfan_output_ready_slice6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext625 :: STRIPSFAN OUTPUT READY SLICE7 */
#define acmgt3__ext625__stripsfan_output_ready_slice7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext626 :: GPU Time Elapsed */
#define acmgt3__ext626__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext626 :: GPU Core Clocks */
#define acmgt3__ext626__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext626 :: AVG GPU Core Frequency */
#define acmgt3__ext626__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext626 :: AVG GPU Core Frequency */
#define acmgt3__ext626__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext626 :: URB READ SLICE0 */
#define acmgt3__ext626__urb_read_slice0__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext626 :: URB WRITE SLICE0 */
#define acmgt3__ext626__urb_write_slice0__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext626 :: URB CROSS SLICE READ SLICE0 */
#define acmgt3__ext626__urb_cross_slice_read_slice0__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext627 :: GPU Time Elapsed */
#define acmgt3__ext627__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext627 :: GPU Core Clocks */
#define acmgt3__ext627__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext627 :: AVG GPU Core Frequency */
#define acmgt3__ext627__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext627 :: AVG GPU Core Frequency */
#define acmgt3__ext627__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext627 :: URB READ SLICE1 */
#define acmgt3__ext627__urb_read_slice1__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext627 :: URB WRITE SLICE1 */
#define acmgt3__ext627__urb_write_slice1__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext627 :: URB CROSS SLICE READ SLICE1 */
#define acmgt3__ext627__urb_cross_slice_read_slice1__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext628 :: GPU Time Elapsed */
#define acmgt3__ext628__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext628 :: GPU Core Clocks */
#define acmgt3__ext628__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext628 :: AVG GPU Core Frequency */
#define acmgt3__ext628__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext628 :: AVG GPU Core Frequency */
#define acmgt3__ext628__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext628 :: URB READ SLICE2 */
#define acmgt3__ext628__urb_read_slice2__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext628 :: URB WRITE SLICE2 */
#define acmgt3__ext628__urb_write_slice2__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext628 :: URB CROSS SLICE READ SLICE2 */
#define acmgt3__ext628__urb_cross_slice_read_slice2__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext629 :: GPU Time Elapsed */
#define acmgt3__ext629__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext629 :: GPU Core Clocks */
#define acmgt3__ext629__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext629 :: AVG GPU Core Frequency */
#define acmgt3__ext629__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext629 :: AVG GPU Core Frequency */
#define acmgt3__ext629__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext629 :: URB READ SLICE3 */
#define acmgt3__ext629__urb_read_slice3__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext629 :: URB WRITE SLICE3 */
#define acmgt3__ext629__urb_write_slice3__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext629 :: URB CROSS SLICE READ SLICE3 */
#define acmgt3__ext629__urb_cross_slice_read_slice3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext630 :: GPU Time Elapsed */
#define acmgt3__ext630__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext630 :: GPU Core Clocks */
#define acmgt3__ext630__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext630 :: AVG GPU Core Frequency */
#define acmgt3__ext630__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext630 :: AVG GPU Core Frequency */
#define acmgt3__ext630__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext630 :: URB READ SLICE4 */
#define acmgt3__ext630__urb_read_slice4__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext630 :: URB WRITE SLICE4 */
#define acmgt3__ext630__urb_write_slice4__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext630 :: URB CROSS SLICE READ SLICE4 */
#define acmgt3__ext630__urb_cross_slice_read_slice4__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext631 :: GPU Time Elapsed */
#define acmgt3__ext631__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext631 :: GPU Core Clocks */
#define acmgt3__ext631__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext631 :: AVG GPU Core Frequency */
#define acmgt3__ext631__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext631 :: AVG GPU Core Frequency */
#define acmgt3__ext631__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext631 :: URB READ SLICE5 */
#define acmgt3__ext631__urb_read_slice5__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext631 :: URB WRITE SLICE5 */
#define acmgt3__ext631__urb_write_slice5__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext631 :: URB CROSS SLICE READ SLICE5 */
#define acmgt3__ext631__urb_cross_slice_read_slice5__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext632 :: GPU Time Elapsed */
#define acmgt3__ext632__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext632 :: GPU Core Clocks */
#define acmgt3__ext632__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext632 :: AVG GPU Core Frequency */
#define acmgt3__ext632__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext632 :: AVG GPU Core Frequency */
#define acmgt3__ext632__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext632 :: URB READ SLICE6 */
#define acmgt3__ext632__urb_read_slice6__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext632 :: URB WRITE SLICE6 */
#define acmgt3__ext632__urb_write_slice6__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext632 :: URB CROSS SLICE READ SLICE6 */
#define acmgt3__ext632__urb_cross_slice_read_slice6__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext633 :: GPU Time Elapsed */
#define acmgt3__ext633__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext633 :: GPU Core Clocks */
#define acmgt3__ext633__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext633 :: AVG GPU Core Frequency */
#define acmgt3__ext633__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext633 :: AVG GPU Core Frequency */
#define acmgt3__ext633__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext633 :: URB READ SLICE7 */
#define acmgt3__ext633__urb_read_slice7__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext633 :: URB WRITE SLICE7 */
#define acmgt3__ext633__urb_write_slice7__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext633 :: URB CROSS SLICE READ SLICE7 */
#define acmgt3__ext633__urb_cross_slice_read_slice7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext634 :: GPU Time Elapsed */
#define acmgt3__ext634__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext634 :: GPU Core Clocks */
#define acmgt3__ext634__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext634 :: AVG GPU Core Frequency */
#define acmgt3__ext634__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext634 :: AVG GPU Core Frequency */
#define acmgt3__ext634__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext634 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS0 */
#define acmgt3__ext634__command_parser_compute_engine_busy_ccs0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext634 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS1 */
#define acmgt3__ext634__command_parser_compute_engine_busy_ccs1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext634 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS2 */
#define acmgt3__ext634__command_parser_compute_engine_busy_ccs2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext634 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS3 */
#define acmgt3__ext634__command_parser_compute_engine_busy_ccs3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext634 :: COMMAND PARSER COMPUTE ENGINE BUSY */
static float
acmgt3__ext634__command_parser_compute_engine_busy__read(UNUSED struct intel_perf_config *perf,
                                                         const struct intel_perf_query_info *query,
                                                         const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ  B 0 READ FADD  B 2 READ FADD  B 3 READ FADD 4 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 0];
   double tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 2];
   double tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 3];
   double tmp6 = tmp4 + tmp5;
   double tmp7 = tmp6;
   double tmp8 = 4;
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;
   double tmp10 = tmp9;
   double tmp11 = acmgt3__ext634__gpu_core_clocks__read(perf, query, results);
   double tmp12 = tmp11 ? tmp10 / tmp11 : 0;

   return tmp12;
}

/* Ext634 :: COMMAND PARSER RENDER ENGINE BUSY */
#define acmgt3__ext634__command_parser_render_engine_busy__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext635 :: GPU Time Elapsed */
#define acmgt3__ext635__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext635 :: GPU Core Clocks */
#define acmgt3__ext635__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext635 :: AVG GPU Core Frequency */
#define acmgt3__ext635__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext635 :: AVG GPU Core Frequency */
#define acmgt3__ext635__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext635 :: COMMAND PARSER COPY ENGINE BUSY */
#define acmgt3__ext635__command_parser_copy_engine_busy__read \
   bdw__render_basic__sampler0_busy__read

/* Ext635 :: COMMAND PARSER VIDEO ENGINE BUSY VDBOX0 */
#define acmgt3__ext635__command_parser_video_engine_busy_vdbox0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext635 :: COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX0 */
#define acmgt3__ext635__command_parser_video_enhancement_engine_busy_vebox0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext635 :: COMMAND PARSER VIDEO ENGINE BUSY VDBOX1 */
#define acmgt3__ext635__command_parser_video_engine_busy_vdbox1__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext635 :: COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX1 */
#define acmgt3__ext635__command_parser_video_enhancement_engine_busy_vebox1__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext635 :: COMMAND PARSER VIDEO ENGINE BUSY */
static float
acmgt3__ext635__command_parser_video_engine_busy__read(UNUSED struct intel_perf_config *perf,
                                                       const struct intel_perf_query_info *query,
                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ  B 3 READ FADD 2 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 3];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   double tmp6 = tmp5;
   double tmp7 = acmgt3__ext635__gpu_core_clocks__read(perf, query, results);
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;

   return tmp8;
}

/* Ext635 :: COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY */
static float
acmgt3__ext635__command_parser_video_enhancement_engine_busy__read(UNUSED struct intel_perf_config *perf,
                                                                   const struct intel_perf_query_info *query,
                                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ  B 4 READ FADD 2 FDIV $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   double tmp6 = tmp5;
   double tmp7 = acmgt3__ext635__gpu_core_clocks__read(perf, query, results);
   double tmp8 = tmp7 ? tmp6 / tmp7 : 0;

   return tmp8;
}

/* Ext636 :: GPU Time Elapsed */
#define acmgt3__ext636__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext636 :: GPU Core Clocks */
#define acmgt3__ext636__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext636 :: AVG GPU Core Frequency */
#define acmgt3__ext636__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext636 :: AVG GPU Core Frequency */
#define acmgt3__ext636__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext636 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0 */
#define acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext636 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS1 */
#define acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext636 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS2 */
#define acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext636 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS3 */
#define acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext636 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT */
static uint64_t
acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count__read(UNUSED struct intel_perf_config *perf,
                                                                          const struct intel_perf_query_info *query,
                                                                          const struct intel_perf_query_result *results)
{
   /* RPN equation: $COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS1 $COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS0 UADD $COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS2 UADD $COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS3 UADD */
   uint64_t tmp0 = acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs1__read(perf, query, results) + acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs0__read(perf, query, results);
   uint64_t tmp1 = tmp0 + acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs2__read(perf, query, results);
   uint64_t tmp2 = tmp1 + acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs3__read(perf, query, results);

   return tmp2;
}

/* Ext636 :: COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT */
#define acmgt3__ext636__command_parser_render_engine_dispatch_kernel_count__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext636 :: COMMAND PARSER FLUSH COUNT */
#define acmgt3__ext636__command_parser_flush_count__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext636 :: COMMAND PARSER RENDER ENGINE DRAW COUNT */
#define acmgt3__ext636__command_parser_render_engine_draw_count__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext637 :: GPU Time Elapsed */
#define acmgt3__ext637__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext637 :: GPU Core Clocks */
#define acmgt3__ext637__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext637 :: AVG GPU Core Frequency */
#define acmgt3__ext637__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext637 :: AVG GPU Core Frequency */
#define acmgt3__ext637__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext637 :: XVE STALL ALUWR XECORE0 XVE0 THREAD0 */
#define acmgt3__ext637__xve_stall_aluwr_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext637 :: XVE STALL BARRIER XECORE0 XVE0 THREAD0 */
#define acmgt3__ext637__xve_stall_barrier_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext637 :: XVE STALL INSTFETCH XECORE0 XVE0 THREAD0 */
#define acmgt3__ext637__xve_stall_instfetch_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext637 :: XVE STALL OTHER XECORE0 XVE0 THREAD0 */
#define acmgt3__ext637__xve_stall_other_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext637 :: XVE STALL SBID XECORE0 XVE0 THREAD0 */
#define acmgt3__ext637__xve_stall_sbid_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext637 :: XVE STALL SENDWR XECORE0 XVE0 THREAD0 */
#define acmgt3__ext637__xve_stall_sendwr_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext637 :: XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0 */
#define acmgt3__ext637__xve_shared_function_access_hold_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext638 :: GPU Time Elapsed */
#define acmgt3__ext638__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext638 :: GPU Core Clocks */
#define acmgt3__ext638__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext638 :: AVG GPU Core Frequency */
#define acmgt3__ext638__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext638 :: AVG GPU Core Frequency */
#define acmgt3__ext638__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext638 :: XVE STALL ALUWR XECORE1 XVE0 THREAD0 */
#define acmgt3__ext638__xve_stall_aluwr_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext638 :: XVE STALL BARRIER XECORE1 XVE0 THREAD0 */
#define acmgt3__ext638__xve_stall_barrier_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext638 :: XVE STALL INSTFETCH XECORE1 XVE0 THREAD0 */
#define acmgt3__ext638__xve_stall_instfetch_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext638 :: XVE STALL OTHER XECORE1 XVE0 THREAD0 */
#define acmgt3__ext638__xve_stall_other_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext638 :: XVE STALL SBID XECORE1 XVE0 THREAD0 */
#define acmgt3__ext638__xve_stall_sbid_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext638 :: XVE STALL SENDWR XECORE1 XVE0 THREAD0 */
#define acmgt3__ext638__xve_stall_sendwr_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext638 :: XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0 */
#define acmgt3__ext638__xve_shared_function_access_hold_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext639 :: GPU Time Elapsed */
#define acmgt3__ext639__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext639 :: GPU Core Clocks */
#define acmgt3__ext639__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext639 :: AVG GPU Core Frequency */
#define acmgt3__ext639__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext639 :: AVG GPU Core Frequency */
#define acmgt3__ext639__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext639 :: XVE STALL ALUWR XECORE2 XVE0 THREAD0 */
#define acmgt3__ext639__xve_stall_aluwr_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext639 :: XVE STALL BARRIER XECORE2 XVE0 THREAD0 */
#define acmgt3__ext639__xve_stall_barrier_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext639 :: XVE STALL INSTFETCH XECORE2 XVE0 THREAD0 */
#define acmgt3__ext639__xve_stall_instfetch_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext639 :: XVE STALL OTHER XECORE2 XVE0 THREAD0 */
#define acmgt3__ext639__xve_stall_other_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext639 :: XVE STALL SBID XECORE2 XVE0 THREAD0 */
#define acmgt3__ext639__xve_stall_sbid_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext639 :: XVE STALL SENDWR XECORE2 XVE0 THREAD0 */
#define acmgt3__ext639__xve_stall_sendwr_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext639 :: XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0 */
#define acmgt3__ext639__xve_shared_function_access_hold_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext640 :: GPU Time Elapsed */
#define acmgt3__ext640__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext640 :: GPU Core Clocks */
#define acmgt3__ext640__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext640 :: AVG GPU Core Frequency */
#define acmgt3__ext640__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext640 :: AVG GPU Core Frequency */
#define acmgt3__ext640__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext640 :: XVE STALL ALUWR XECORE3 XVE0 THREAD0 */
#define acmgt3__ext640__xve_stall_aluwr_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext640 :: XVE STALL BARRIER XECORE3 XVE0 THREAD0 */
#define acmgt3__ext640__xve_stall_barrier_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext640 :: XVE STALL INSTFETCH XECORE3 XVE0 THREAD0 */
#define acmgt3__ext640__xve_stall_instfetch_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext640 :: XVE STALL OTHER XECORE3 XVE0 THREAD0 */
#define acmgt3__ext640__xve_stall_other_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext640 :: XVE STALL SBID XECORE3 XVE0 THREAD0 */
#define acmgt3__ext640__xve_stall_sbid_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext640 :: XVE STALL SENDWR XECORE3 XVE0 THREAD0 */
#define acmgt3__ext640__xve_stall_sendwr_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext640 :: XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0 */
#define acmgt3__ext640__xve_shared_function_access_hold_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext641 :: GPU Time Elapsed */
#define acmgt3__ext641__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext641 :: GPU Core Clocks */
#define acmgt3__ext641__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext641 :: AVG GPU Core Frequency */
#define acmgt3__ext641__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext641 :: AVG GPU Core Frequency */
#define acmgt3__ext641__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext641 :: XVE STALL ALUWR XECORE4 XVE0 THREAD0 */
#define acmgt3__ext641__xve_stall_aluwr_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext641 :: XVE STALL BARRIER XECORE4 XVE0 THREAD0 */
#define acmgt3__ext641__xve_stall_barrier_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext641 :: XVE STALL INSTFETCH XECORE4 XVE0 THREAD0 */
#define acmgt3__ext641__xve_stall_instfetch_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext641 :: XVE STALL OTHER XECORE4 XVE0 THREAD0 */
#define acmgt3__ext641__xve_stall_other_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext641 :: XVE STALL SBID XECORE4 XVE0 THREAD0 */
#define acmgt3__ext641__xve_stall_sbid_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext641 :: XVE STALL SENDWR XECORE4 XVE0 THREAD0 */
#define acmgt3__ext641__xve_stall_sendwr_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext641 :: XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0 */
#define acmgt3__ext641__xve_shared_function_access_hold_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext642 :: GPU Time Elapsed */
#define acmgt3__ext642__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext642 :: GPU Core Clocks */
#define acmgt3__ext642__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext642 :: AVG GPU Core Frequency */
#define acmgt3__ext642__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext642 :: AVG GPU Core Frequency */
#define acmgt3__ext642__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext642 :: XVE STALL ALUWR XECORE5 XVE0 THREAD0 */
#define acmgt3__ext642__xve_stall_aluwr_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext642 :: XVE STALL BARRIER XECORE5 XVE0 THREAD0 */
#define acmgt3__ext642__xve_stall_barrier_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext642 :: XVE STALL INSTFETCH XECORE5 XVE0 THREAD0 */
#define acmgt3__ext642__xve_stall_instfetch_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext642 :: XVE STALL OTHER XECORE5 XVE0 THREAD0 */
#define acmgt3__ext642__xve_stall_other_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext642 :: XVE STALL SBID XECORE5 XVE0 THREAD0 */
#define acmgt3__ext642__xve_stall_sbid_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext642 :: XVE STALL SENDWR XECORE5 XVE0 THREAD0 */
#define acmgt3__ext642__xve_stall_sendwr_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext642 :: XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0 */
#define acmgt3__ext642__xve_shared_function_access_hold_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext643 :: GPU Time Elapsed */
#define acmgt3__ext643__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext643 :: GPU Core Clocks */
#define acmgt3__ext643__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext643 :: AVG GPU Core Frequency */
#define acmgt3__ext643__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext643 :: AVG GPU Core Frequency */
#define acmgt3__ext643__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext643 :: XVE STALL ALUWR XECORE6 XVE0 THREAD0 */
#define acmgt3__ext643__xve_stall_aluwr_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext643 :: XVE STALL BARRIER XECORE6 XVE0 THREAD0 */
#define acmgt3__ext643__xve_stall_barrier_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext643 :: XVE STALL INSTFETCH XECORE6 XVE0 THREAD0 */
#define acmgt3__ext643__xve_stall_instfetch_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext643 :: XVE STALL OTHER XECORE6 XVE0 THREAD0 */
#define acmgt3__ext643__xve_stall_other_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext643 :: XVE STALL SBID XECORE6 XVE0 THREAD0 */
#define acmgt3__ext643__xve_stall_sbid_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext643 :: XVE STALL SENDWR XECORE6 XVE0 THREAD0 */
#define acmgt3__ext643__xve_stall_sendwr_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext643 :: XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0 */
#define acmgt3__ext643__xve_shared_function_access_hold_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext644 :: GPU Time Elapsed */
#define acmgt3__ext644__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext644 :: GPU Core Clocks */
#define acmgt3__ext644__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext644 :: AVG GPU Core Frequency */
#define acmgt3__ext644__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext644 :: AVG GPU Core Frequency */
#define acmgt3__ext644__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext644 :: XVE STALL ALUWR XECORE7 XVE0 THREAD0 */
#define acmgt3__ext644__xve_stall_aluwr_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext644 :: XVE STALL BARRIER XECORE7 XVE0 THREAD0 */
#define acmgt3__ext644__xve_stall_barrier_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext644 :: XVE STALL INSTFETCH XECORE7 XVE0 THREAD0 */
#define acmgt3__ext644__xve_stall_instfetch_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext644 :: XVE STALL OTHER XECORE7 XVE0 THREAD0 */
#define acmgt3__ext644__xve_stall_other_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext644 :: XVE STALL SBID XECORE7 XVE0 THREAD0 */
#define acmgt3__ext644__xve_stall_sbid_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext644 :: XVE STALL SENDWR XECORE7 XVE0 THREAD0 */
#define acmgt3__ext644__xve_stall_sendwr_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext644 :: XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0 */
#define acmgt3__ext644__xve_shared_function_access_hold_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext645 :: GPU Time Elapsed */
#define acmgt3__ext645__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext645 :: GPU Core Clocks */
#define acmgt3__ext645__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext645 :: AVG GPU Core Frequency */
#define acmgt3__ext645__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext645 :: AVG GPU Core Frequency */
#define acmgt3__ext645__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext645 :: XVE STALL ALUWR XECORE8 XVE0 THREAD0 */
#define acmgt3__ext645__xve_stall_aluwr_xecore8_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext645 :: XVE STALL BARRIER XECORE8 XVE0 THREAD0 */
#define acmgt3__ext645__xve_stall_barrier_xecore8_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext645 :: XVE STALL INSTFETCH XECORE8 XVE0 THREAD0 */
#define acmgt3__ext645__xve_stall_instfetch_xecore8_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext645 :: XVE STALL OTHER XECORE8 XVE0 THREAD0 */
#define acmgt3__ext645__xve_stall_other_xecore8_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext645 :: XVE STALL SBID XECORE8 XVE0 THREAD0 */
#define acmgt3__ext645__xve_stall_sbid_xecore8_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext645 :: XVE STALL SENDWR XECORE8 XVE0 THREAD0 */
#define acmgt3__ext645__xve_stall_sendwr_xecore8_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext645 :: XVE SHARED FUNCTION ACCESS HOLD XECORE8 XVE0 THREAD0 */
#define acmgt3__ext645__xve_shared_function_access_hold_xecore8_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext646 :: GPU Time Elapsed */
#define acmgt3__ext646__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext646 :: GPU Core Clocks */
#define acmgt3__ext646__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext646 :: AVG GPU Core Frequency */
#define acmgt3__ext646__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext646 :: AVG GPU Core Frequency */
#define acmgt3__ext646__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext646 :: XVE STALL ALUWR XECORE9 XVE0 THREAD0 */
#define acmgt3__ext646__xve_stall_aluwr_xecore9_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext646 :: XVE STALL BARRIER XECORE9 XVE0 THREAD0 */
#define acmgt3__ext646__xve_stall_barrier_xecore9_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext646 :: XVE STALL INSTFETCH XECORE9 XVE0 THREAD0 */
#define acmgt3__ext646__xve_stall_instfetch_xecore9_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext646 :: XVE STALL OTHER XECORE9 XVE0 THREAD0 */
#define acmgt3__ext646__xve_stall_other_xecore9_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext646 :: XVE STALL SBID XECORE9 XVE0 THREAD0 */
#define acmgt3__ext646__xve_stall_sbid_xecore9_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext646 :: XVE STALL SENDWR XECORE9 XVE0 THREAD0 */
#define acmgt3__ext646__xve_stall_sendwr_xecore9_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext646 :: XVE SHARED FUNCTION ACCESS HOLD XECORE9 XVE0 THREAD0 */
#define acmgt3__ext646__xve_shared_function_access_hold_xecore9_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext647 :: GPU Time Elapsed */
#define acmgt3__ext647__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext647 :: GPU Core Clocks */
#define acmgt3__ext647__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext647 :: AVG GPU Core Frequency */
#define acmgt3__ext647__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext647 :: AVG GPU Core Frequency */
#define acmgt3__ext647__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext647 :: XVE STALL ALUWR XECORE10 XVE0 THREAD0 */
#define acmgt3__ext647__xve_stall_aluwr_xecore10_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext647 :: XVE STALL BARRIER XECORE10 XVE0 THREAD0 */
#define acmgt3__ext647__xve_stall_barrier_xecore10_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext647 :: XVE STALL INSTFETCH XECORE10 XVE0 THREAD0 */
#define acmgt3__ext647__xve_stall_instfetch_xecore10_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext647 :: XVE STALL OTHER XECORE10 XVE0 THREAD0 */
#define acmgt3__ext647__xve_stall_other_xecore10_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext647 :: XVE STALL SBID XECORE10 XVE0 THREAD0 */
#define acmgt3__ext647__xve_stall_sbid_xecore10_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext647 :: XVE STALL SENDWR XECORE10 XVE0 THREAD0 */
#define acmgt3__ext647__xve_stall_sendwr_xecore10_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext647 :: XVE SHARED FUNCTION ACCESS HOLD XECORE10 XVE0 THREAD0 */
#define acmgt3__ext647__xve_shared_function_access_hold_xecore10_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext648 :: GPU Time Elapsed */
#define acmgt3__ext648__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext648 :: GPU Core Clocks */
#define acmgt3__ext648__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext648 :: AVG GPU Core Frequency */
#define acmgt3__ext648__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext648 :: AVG GPU Core Frequency */
#define acmgt3__ext648__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext648 :: XVE STALL ALUWR XECORE11 XVE0 THREAD0 */
#define acmgt3__ext648__xve_stall_aluwr_xecore11_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext648 :: XVE STALL BARRIER XECORE11 XVE0 THREAD0 */
#define acmgt3__ext648__xve_stall_barrier_xecore11_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext648 :: XVE STALL INSTFETCH XECORE11 XVE0 THREAD0 */
#define acmgt3__ext648__xve_stall_instfetch_xecore11_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext648 :: XVE STALL OTHER XECORE11 XVE0 THREAD0 */
#define acmgt3__ext648__xve_stall_other_xecore11_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext648 :: XVE STALL SBID XECORE11 XVE0 THREAD0 */
#define acmgt3__ext648__xve_stall_sbid_xecore11_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext648 :: XVE STALL SENDWR XECORE11 XVE0 THREAD0 */
#define acmgt3__ext648__xve_stall_sendwr_xecore11_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext648 :: XVE SHARED FUNCTION ACCESS HOLD XECORE11 XVE0 THREAD0 */
#define acmgt3__ext648__xve_shared_function_access_hold_xecore11_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext649 :: GPU Time Elapsed */
#define acmgt3__ext649__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext649 :: GPU Core Clocks */
#define acmgt3__ext649__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext649 :: AVG GPU Core Frequency */
#define acmgt3__ext649__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext649 :: AVG GPU Core Frequency */
#define acmgt3__ext649__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext649 :: XVE STALL ALUWR XECORE12 XVE0 THREAD0 */
#define acmgt3__ext649__xve_stall_aluwr_xecore12_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext649 :: XVE STALL BARRIER XECORE12 XVE0 THREAD0 */
#define acmgt3__ext649__xve_stall_barrier_xecore12_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext649 :: XVE STALL INSTFETCH XECORE12 XVE0 THREAD0 */
#define acmgt3__ext649__xve_stall_instfetch_xecore12_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext649 :: XVE STALL OTHER XECORE12 XVE0 THREAD0 */
#define acmgt3__ext649__xve_stall_other_xecore12_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext649 :: XVE STALL SBID XECORE12 XVE0 THREAD0 */
#define acmgt3__ext649__xve_stall_sbid_xecore12_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext649 :: XVE STALL SENDWR XECORE12 XVE0 THREAD0 */
#define acmgt3__ext649__xve_stall_sendwr_xecore12_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext649 :: XVE SHARED FUNCTION ACCESS HOLD XECORE12 XVE0 THREAD0 */
#define acmgt3__ext649__xve_shared_function_access_hold_xecore12_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext650 :: GPU Time Elapsed */
#define acmgt3__ext650__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext650 :: GPU Core Clocks */
#define acmgt3__ext650__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext650 :: AVG GPU Core Frequency */
#define acmgt3__ext650__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext650 :: AVG GPU Core Frequency */
#define acmgt3__ext650__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext650 :: XVE STALL ALUWR XECORE13 XVE0 THREAD0 */
#define acmgt3__ext650__xve_stall_aluwr_xecore13_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext650 :: XVE STALL BARRIER XECORE13 XVE0 THREAD0 */
#define acmgt3__ext650__xve_stall_barrier_xecore13_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext650 :: XVE STALL INSTFETCH XECORE13 XVE0 THREAD0 */
#define acmgt3__ext650__xve_stall_instfetch_xecore13_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext650 :: XVE STALL OTHER XECORE13 XVE0 THREAD0 */
#define acmgt3__ext650__xve_stall_other_xecore13_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext650 :: XVE STALL SBID XECORE13 XVE0 THREAD0 */
#define acmgt3__ext650__xve_stall_sbid_xecore13_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext650 :: XVE STALL SENDWR XECORE13 XVE0 THREAD0 */
#define acmgt3__ext650__xve_stall_sendwr_xecore13_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext650 :: XVE SHARED FUNCTION ACCESS HOLD XECORE13 XVE0 THREAD0 */
#define acmgt3__ext650__xve_shared_function_access_hold_xecore13_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext651 :: GPU Time Elapsed */
#define acmgt3__ext651__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext651 :: GPU Core Clocks */
#define acmgt3__ext651__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext651 :: AVG GPU Core Frequency */
#define acmgt3__ext651__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext651 :: AVG GPU Core Frequency */
#define acmgt3__ext651__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext651 :: XVE STALL ALUWR XECORE14 XVE0 THREAD0 */
#define acmgt3__ext651__xve_stall_aluwr_xecore14_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext651 :: XVE STALL BARRIER XECORE14 XVE0 THREAD0 */
#define acmgt3__ext651__xve_stall_barrier_xecore14_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext651 :: XVE STALL INSTFETCH XECORE14 XVE0 THREAD0 */
#define acmgt3__ext651__xve_stall_instfetch_xecore14_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext651 :: XVE STALL OTHER XECORE14 XVE0 THREAD0 */
#define acmgt3__ext651__xve_stall_other_xecore14_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext651 :: XVE STALL SBID XECORE14 XVE0 THREAD0 */
#define acmgt3__ext651__xve_stall_sbid_xecore14_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext651 :: XVE STALL SENDWR XECORE14 XVE0 THREAD0 */
#define acmgt3__ext651__xve_stall_sendwr_xecore14_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext651 :: XVE SHARED FUNCTION ACCESS HOLD XECORE14 XVE0 THREAD0 */
#define acmgt3__ext651__xve_shared_function_access_hold_xecore14_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext652 :: GPU Time Elapsed */
#define acmgt3__ext652__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext652 :: GPU Core Clocks */
#define acmgt3__ext652__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext652 :: AVG GPU Core Frequency */
#define acmgt3__ext652__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext652 :: AVG GPU Core Frequency */
#define acmgt3__ext652__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext652 :: XVE STALL ALUWR XECORE15 XVE0 THREAD0 */
#define acmgt3__ext652__xve_stall_aluwr_xecore15_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext652 :: XVE STALL BARRIER XECORE15 XVE0 THREAD0 */
#define acmgt3__ext652__xve_stall_barrier_xecore15_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext652 :: XVE STALL INSTFETCH XECORE15 XVE0 THREAD0 */
#define acmgt3__ext652__xve_stall_instfetch_xecore15_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext652 :: XVE STALL OTHER XECORE15 XVE0 THREAD0 */
#define acmgt3__ext652__xve_stall_other_xecore15_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext652 :: XVE STALL SBID XECORE15 XVE0 THREAD0 */
#define acmgt3__ext652__xve_stall_sbid_xecore15_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext652 :: XVE STALL SENDWR XECORE15 XVE0 THREAD0 */
#define acmgt3__ext652__xve_stall_sendwr_xecore15_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext652 :: XVE SHARED FUNCTION ACCESS HOLD XECORE15 XVE0 THREAD0 */
#define acmgt3__ext652__xve_shared_function_access_hold_xecore15_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext653 :: GPU Time Elapsed */
#define acmgt3__ext653__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext653 :: GPU Core Clocks */
#define acmgt3__ext653__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext653 :: AVG GPU Core Frequency */
#define acmgt3__ext653__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext653 :: AVG GPU Core Frequency */
#define acmgt3__ext653__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext653 :: XVE STALL ALUWR XECORE16 XVE0 THREAD0 */
#define acmgt3__ext653__xve_stall_aluwr_xecore16_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext653 :: XVE STALL BARRIER XECORE16 XVE0 THREAD0 */
#define acmgt3__ext653__xve_stall_barrier_xecore16_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext653 :: XVE STALL INSTFETCH XECORE16 XVE0 THREAD0 */
#define acmgt3__ext653__xve_stall_instfetch_xecore16_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext653 :: XVE STALL OTHER XECORE16 XVE0 THREAD0 */
#define acmgt3__ext653__xve_stall_other_xecore16_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext653 :: XVE STALL SBID XECORE16 XVE0 THREAD0 */
#define acmgt3__ext653__xve_stall_sbid_xecore16_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext653 :: XVE STALL SENDWR XECORE16 XVE0 THREAD0 */
#define acmgt3__ext653__xve_stall_sendwr_xecore16_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext653 :: XVE SHARED FUNCTION ACCESS HOLD XECORE16 XVE0 THREAD0 */
#define acmgt3__ext653__xve_shared_function_access_hold_xecore16_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext654 :: GPU Time Elapsed */
#define acmgt3__ext654__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext654 :: GPU Core Clocks */
#define acmgt3__ext654__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext654 :: AVG GPU Core Frequency */
#define acmgt3__ext654__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext654 :: AVG GPU Core Frequency */
#define acmgt3__ext654__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext654 :: XVE STALL ALUWR XECORE17 XVE0 THREAD0 */
#define acmgt3__ext654__xve_stall_aluwr_xecore17_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext654 :: XVE STALL BARRIER XECORE17 XVE0 THREAD0 */
#define acmgt3__ext654__xve_stall_barrier_xecore17_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext654 :: XVE STALL INSTFETCH XECORE17 XVE0 THREAD0 */
#define acmgt3__ext654__xve_stall_instfetch_xecore17_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext654 :: XVE STALL OTHER XECORE17 XVE0 THREAD0 */
#define acmgt3__ext654__xve_stall_other_xecore17_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext654 :: XVE STALL SBID XECORE17 XVE0 THREAD0 */
#define acmgt3__ext654__xve_stall_sbid_xecore17_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext654 :: XVE STALL SENDWR XECORE17 XVE0 THREAD0 */
#define acmgt3__ext654__xve_stall_sendwr_xecore17_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext654 :: XVE SHARED FUNCTION ACCESS HOLD XECORE17 XVE0 THREAD0 */
#define acmgt3__ext654__xve_shared_function_access_hold_xecore17_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext655 :: GPU Time Elapsed */
#define acmgt3__ext655__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext655 :: GPU Core Clocks */
#define acmgt3__ext655__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext655 :: AVG GPU Core Frequency */
#define acmgt3__ext655__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext655 :: AVG GPU Core Frequency */
#define acmgt3__ext655__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext655 :: XVE STALL ALUWR XECORE18 XVE0 THREAD0 */
#define acmgt3__ext655__xve_stall_aluwr_xecore18_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext655 :: XVE STALL BARRIER XECORE18 XVE0 THREAD0 */
#define acmgt3__ext655__xve_stall_barrier_xecore18_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext655 :: XVE STALL INSTFETCH XECORE18 XVE0 THREAD0 */
#define acmgt3__ext655__xve_stall_instfetch_xecore18_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext655 :: XVE STALL OTHER XECORE18 XVE0 THREAD0 */
#define acmgt3__ext655__xve_stall_other_xecore18_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext655 :: XVE STALL SBID XECORE18 XVE0 THREAD0 */
#define acmgt3__ext655__xve_stall_sbid_xecore18_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext655 :: XVE STALL SENDWR XECORE18 XVE0 THREAD0 */
#define acmgt3__ext655__xve_stall_sendwr_xecore18_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext655 :: XVE SHARED FUNCTION ACCESS HOLD XECORE18 XVE0 THREAD0 */
#define acmgt3__ext655__xve_shared_function_access_hold_xecore18_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext656 :: GPU Time Elapsed */
#define acmgt3__ext656__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext656 :: GPU Core Clocks */
#define acmgt3__ext656__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext656 :: AVG GPU Core Frequency */
#define acmgt3__ext656__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext656 :: AVG GPU Core Frequency */
#define acmgt3__ext656__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext656 :: XVE STALL ALUWR XECORE19 XVE0 THREAD0 */
#define acmgt3__ext656__xve_stall_aluwr_xecore19_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext656 :: XVE STALL BARRIER XECORE19 XVE0 THREAD0 */
#define acmgt3__ext656__xve_stall_barrier_xecore19_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext656 :: XVE STALL INSTFETCH XECORE19 XVE0 THREAD0 */
#define acmgt3__ext656__xve_stall_instfetch_xecore19_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext656 :: XVE STALL OTHER XECORE19 XVE0 THREAD0 */
#define acmgt3__ext656__xve_stall_other_xecore19_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext656 :: XVE STALL SBID XECORE19 XVE0 THREAD0 */
#define acmgt3__ext656__xve_stall_sbid_xecore19_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext656 :: XVE STALL SENDWR XECORE19 XVE0 THREAD0 */
#define acmgt3__ext656__xve_stall_sendwr_xecore19_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext656 :: XVE SHARED FUNCTION ACCESS HOLD XECORE19 XVE0 THREAD0 */
#define acmgt3__ext656__xve_shared_function_access_hold_xecore19_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext657 :: GPU Time Elapsed */
#define acmgt3__ext657__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext657 :: GPU Core Clocks */
#define acmgt3__ext657__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext657 :: AVG GPU Core Frequency */
#define acmgt3__ext657__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext657 :: AVG GPU Core Frequency */
#define acmgt3__ext657__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext657 :: XVE STALL ALUWR XECORE20 XVE0 THREAD0 */
#define acmgt3__ext657__xve_stall_aluwr_xecore20_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext657 :: XVE STALL BARRIER XECORE20 XVE0 THREAD0 */
#define acmgt3__ext657__xve_stall_barrier_xecore20_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext657 :: XVE STALL INSTFETCH XECORE20 XVE0 THREAD0 */
#define acmgt3__ext657__xve_stall_instfetch_xecore20_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext657 :: XVE STALL OTHER XECORE20 XVE0 THREAD0 */
#define acmgt3__ext657__xve_stall_other_xecore20_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext657 :: XVE STALL SBID XECORE20 XVE0 THREAD0 */
#define acmgt3__ext657__xve_stall_sbid_xecore20_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext657 :: XVE STALL SENDWR XECORE20 XVE0 THREAD0 */
#define acmgt3__ext657__xve_stall_sendwr_xecore20_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext657 :: XVE SHARED FUNCTION ACCESS HOLD XECORE20 XVE0 THREAD0 */
#define acmgt3__ext657__xve_shared_function_access_hold_xecore20_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext658 :: GPU Time Elapsed */
#define acmgt3__ext658__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext658 :: GPU Core Clocks */
#define acmgt3__ext658__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext658 :: AVG GPU Core Frequency */
#define acmgt3__ext658__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext658 :: AVG GPU Core Frequency */
#define acmgt3__ext658__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext658 :: XVE STALL ALUWR XECORE21 XVE0 THREAD0 */
#define acmgt3__ext658__xve_stall_aluwr_xecore21_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext658 :: XVE STALL BARRIER XECORE21 XVE0 THREAD0 */
#define acmgt3__ext658__xve_stall_barrier_xecore21_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext658 :: XVE STALL INSTFETCH XECORE21 XVE0 THREAD0 */
#define acmgt3__ext658__xve_stall_instfetch_xecore21_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext658 :: XVE STALL OTHER XECORE21 XVE0 THREAD0 */
#define acmgt3__ext658__xve_stall_other_xecore21_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext658 :: XVE STALL SBID XECORE21 XVE0 THREAD0 */
#define acmgt3__ext658__xve_stall_sbid_xecore21_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext658 :: XVE STALL SENDWR XECORE21 XVE0 THREAD0 */
#define acmgt3__ext658__xve_stall_sendwr_xecore21_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext658 :: XVE SHARED FUNCTION ACCESS HOLD XECORE21 XVE0 THREAD0 */
#define acmgt3__ext658__xve_shared_function_access_hold_xecore21_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext659 :: GPU Time Elapsed */
#define acmgt3__ext659__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext659 :: GPU Core Clocks */
#define acmgt3__ext659__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext659 :: AVG GPU Core Frequency */
#define acmgt3__ext659__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext659 :: AVG GPU Core Frequency */
#define acmgt3__ext659__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext659 :: XVE STALL ALUWR XECORE22 XVE0 THREAD0 */
#define acmgt3__ext659__xve_stall_aluwr_xecore22_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext659 :: XVE STALL BARRIER XECORE22 XVE0 THREAD0 */
#define acmgt3__ext659__xve_stall_barrier_xecore22_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext659 :: XVE STALL INSTFETCH XECORE22 XVE0 THREAD0 */
#define acmgt3__ext659__xve_stall_instfetch_xecore22_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext659 :: XVE STALL OTHER XECORE22 XVE0 THREAD0 */
#define acmgt3__ext659__xve_stall_other_xecore22_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext659 :: XVE STALL SBID XECORE22 XVE0 THREAD0 */
#define acmgt3__ext659__xve_stall_sbid_xecore22_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext659 :: XVE STALL SENDWR XECORE22 XVE0 THREAD0 */
#define acmgt3__ext659__xve_stall_sendwr_xecore22_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext659 :: XVE SHARED FUNCTION ACCESS HOLD XECORE22 XVE0 THREAD0 */
#define acmgt3__ext659__xve_shared_function_access_hold_xecore22_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext660 :: GPU Time Elapsed */
#define acmgt3__ext660__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext660 :: GPU Core Clocks */
#define acmgt3__ext660__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext660 :: AVG GPU Core Frequency */
#define acmgt3__ext660__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext660 :: AVG GPU Core Frequency */
#define acmgt3__ext660__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext660 :: XVE STALL ALUWR XECORE23 XVE0 THREAD0 */
#define acmgt3__ext660__xve_stall_aluwr_xecore23_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext660 :: XVE STALL BARRIER XECORE23 XVE0 THREAD0 */
#define acmgt3__ext660__xve_stall_barrier_xecore23_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext660 :: XVE STALL INSTFETCH XECORE23 XVE0 THREAD0 */
#define acmgt3__ext660__xve_stall_instfetch_xecore23_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext660 :: XVE STALL OTHER XECORE23 XVE0 THREAD0 */
#define acmgt3__ext660__xve_stall_other_xecore23_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext660 :: XVE STALL SBID XECORE23 XVE0 THREAD0 */
#define acmgt3__ext660__xve_stall_sbid_xecore23_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext660 :: XVE STALL SENDWR XECORE23 XVE0 THREAD0 */
#define acmgt3__ext660__xve_stall_sendwr_xecore23_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext660 :: XVE SHARED FUNCTION ACCESS HOLD XECORE23 XVE0 THREAD0 */
#define acmgt3__ext660__xve_shared_function_access_hold_xecore23_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext661 :: GPU Time Elapsed */
#define acmgt3__ext661__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext661 :: GPU Core Clocks */
#define acmgt3__ext661__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext661 :: AVG GPU Core Frequency */
#define acmgt3__ext661__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext661 :: AVG GPU Core Frequency */
#define acmgt3__ext661__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext661 :: XVE STALL ALUWR XECORE24 XVE0 THREAD0 */
#define acmgt3__ext661__xve_stall_aluwr_xecore24_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext661 :: XVE STALL BARRIER XECORE24 XVE0 THREAD0 */
#define acmgt3__ext661__xve_stall_barrier_xecore24_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext661 :: XVE STALL INSTFETCH XECORE24 XVE0 THREAD0 */
#define acmgt3__ext661__xve_stall_instfetch_xecore24_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext661 :: XVE STALL OTHER XECORE24 XVE0 THREAD0 */
#define acmgt3__ext661__xve_stall_other_xecore24_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext661 :: XVE STALL SBID XECORE24 XVE0 THREAD0 */
#define acmgt3__ext661__xve_stall_sbid_xecore24_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext661 :: XVE STALL SENDWR XECORE24 XVE0 THREAD0 */
#define acmgt3__ext661__xve_stall_sendwr_xecore24_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext661 :: XVE SHARED FUNCTION ACCESS HOLD XECORE24 XVE0 THREAD0 */
#define acmgt3__ext661__xve_shared_function_access_hold_xecore24_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext662 :: GPU Time Elapsed */
#define acmgt3__ext662__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext662 :: GPU Core Clocks */
#define acmgt3__ext662__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext662 :: AVG GPU Core Frequency */
#define acmgt3__ext662__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext662 :: AVG GPU Core Frequency */
#define acmgt3__ext662__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext662 :: XVE STALL ALUWR XECORE25 XVE0 THREAD0 */
#define acmgt3__ext662__xve_stall_aluwr_xecore25_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext662 :: XVE STALL BARRIER XECORE25 XVE0 THREAD0 */
#define acmgt3__ext662__xve_stall_barrier_xecore25_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext662 :: XVE STALL INSTFETCH XECORE25 XVE0 THREAD0 */
#define acmgt3__ext662__xve_stall_instfetch_xecore25_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext662 :: XVE STALL OTHER XECORE25 XVE0 THREAD0 */
#define acmgt3__ext662__xve_stall_other_xecore25_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext662 :: XVE STALL SBID XECORE25 XVE0 THREAD0 */
#define acmgt3__ext662__xve_stall_sbid_xecore25_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext662 :: XVE STALL SENDWR XECORE25 XVE0 THREAD0 */
#define acmgt3__ext662__xve_stall_sendwr_xecore25_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext662 :: XVE SHARED FUNCTION ACCESS HOLD XECORE25 XVE0 THREAD0 */
#define acmgt3__ext662__xve_shared_function_access_hold_xecore25_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext663 :: GPU Time Elapsed */
#define acmgt3__ext663__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext663 :: GPU Core Clocks */
#define acmgt3__ext663__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext663 :: AVG GPU Core Frequency */
#define acmgt3__ext663__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext663 :: AVG GPU Core Frequency */
#define acmgt3__ext663__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext663 :: XVE STALL ALUWR XECORE26 XVE0 THREAD0 */
#define acmgt3__ext663__xve_stall_aluwr_xecore26_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext663 :: XVE STALL BARRIER XECORE26 XVE0 THREAD0 */
#define acmgt3__ext663__xve_stall_barrier_xecore26_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext663 :: XVE STALL INSTFETCH XECORE26 XVE0 THREAD0 */
#define acmgt3__ext663__xve_stall_instfetch_xecore26_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext663 :: XVE STALL OTHER XECORE26 XVE0 THREAD0 */
#define acmgt3__ext663__xve_stall_other_xecore26_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext663 :: XVE STALL SBID XECORE26 XVE0 THREAD0 */
#define acmgt3__ext663__xve_stall_sbid_xecore26_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext663 :: XVE STALL SENDWR XECORE26 XVE0 THREAD0 */
#define acmgt3__ext663__xve_stall_sendwr_xecore26_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext663 :: XVE SHARED FUNCTION ACCESS HOLD XECORE26 XVE0 THREAD0 */
#define acmgt3__ext663__xve_shared_function_access_hold_xecore26_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext664 :: GPU Time Elapsed */
#define acmgt3__ext664__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext664 :: GPU Core Clocks */
#define acmgt3__ext664__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext664 :: AVG GPU Core Frequency */
#define acmgt3__ext664__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext664 :: AVG GPU Core Frequency */
#define acmgt3__ext664__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext664 :: XVE STALL ALUWR XECORE27 XVE0 THREAD0 */
#define acmgt3__ext664__xve_stall_aluwr_xecore27_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext664 :: XVE STALL BARRIER XECORE27 XVE0 THREAD0 */
#define acmgt3__ext664__xve_stall_barrier_xecore27_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext664 :: XVE STALL INSTFETCH XECORE27 XVE0 THREAD0 */
#define acmgt3__ext664__xve_stall_instfetch_xecore27_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext664 :: XVE STALL OTHER XECORE27 XVE0 THREAD0 */
#define acmgt3__ext664__xve_stall_other_xecore27_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext664 :: XVE STALL SBID XECORE27 XVE0 THREAD0 */
#define acmgt3__ext664__xve_stall_sbid_xecore27_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext664 :: XVE STALL SENDWR XECORE27 XVE0 THREAD0 */
#define acmgt3__ext664__xve_stall_sendwr_xecore27_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext664 :: XVE SHARED FUNCTION ACCESS HOLD XECORE27 XVE0 THREAD0 */
#define acmgt3__ext664__xve_shared_function_access_hold_xecore27_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext665 :: GPU Time Elapsed */
#define acmgt3__ext665__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext665 :: GPU Core Clocks */
#define acmgt3__ext665__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext665 :: AVG GPU Core Frequency */
#define acmgt3__ext665__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext665 :: AVG GPU Core Frequency */
#define acmgt3__ext665__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext665 :: XVE STALL ALUWR XECORE28 XVE0 THREAD0 */
#define acmgt3__ext665__xve_stall_aluwr_xecore28_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext665 :: XVE STALL BARRIER XECORE28 XVE0 THREAD0 */
#define acmgt3__ext665__xve_stall_barrier_xecore28_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext665 :: XVE STALL INSTFETCH XECORE28 XVE0 THREAD0 */
#define acmgt3__ext665__xve_stall_instfetch_xecore28_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext665 :: XVE STALL OTHER XECORE28 XVE0 THREAD0 */
#define acmgt3__ext665__xve_stall_other_xecore28_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext665 :: XVE STALL SBID XECORE28 XVE0 THREAD0 */
#define acmgt3__ext665__xve_stall_sbid_xecore28_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext665 :: XVE STALL SENDWR XECORE28 XVE0 THREAD0 */
#define acmgt3__ext665__xve_stall_sendwr_xecore28_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext665 :: XVE SHARED FUNCTION ACCESS HOLD XECORE28 XVE0 THREAD0 */
#define acmgt3__ext665__xve_shared_function_access_hold_xecore28_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext666 :: GPU Time Elapsed */
#define acmgt3__ext666__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext666 :: GPU Core Clocks */
#define acmgt3__ext666__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext666 :: AVG GPU Core Frequency */
#define acmgt3__ext666__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext666 :: AVG GPU Core Frequency */
#define acmgt3__ext666__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext666 :: XVE STALL ALUWR XECORE29 XVE0 THREAD0 */
#define acmgt3__ext666__xve_stall_aluwr_xecore29_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext666 :: XVE STALL BARRIER XECORE29 XVE0 THREAD0 */
#define acmgt3__ext666__xve_stall_barrier_xecore29_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext666 :: XVE STALL INSTFETCH XECORE29 XVE0 THREAD0 */
#define acmgt3__ext666__xve_stall_instfetch_xecore29_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext666 :: XVE STALL OTHER XECORE29 XVE0 THREAD0 */
#define acmgt3__ext666__xve_stall_other_xecore29_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext666 :: XVE STALL SBID XECORE29 XVE0 THREAD0 */
#define acmgt3__ext666__xve_stall_sbid_xecore29_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext666 :: XVE STALL SENDWR XECORE29 XVE0 THREAD0 */
#define acmgt3__ext666__xve_stall_sendwr_xecore29_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext666 :: XVE SHARED FUNCTION ACCESS HOLD XECORE29 XVE0 THREAD0 */
#define acmgt3__ext666__xve_shared_function_access_hold_xecore29_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext667 :: GPU Time Elapsed */
#define acmgt3__ext667__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext667 :: GPU Core Clocks */
#define acmgt3__ext667__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext667 :: AVG GPU Core Frequency */
#define acmgt3__ext667__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext667 :: AVG GPU Core Frequency */
#define acmgt3__ext667__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext667 :: XVE STALL ALUWR XECORE30 XVE0 THREAD0 */
#define acmgt3__ext667__xve_stall_aluwr_xecore30_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext667 :: XVE STALL BARRIER XECORE30 XVE0 THREAD0 */
#define acmgt3__ext667__xve_stall_barrier_xecore30_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext667 :: XVE STALL INSTFETCH XECORE30 XVE0 THREAD0 */
#define acmgt3__ext667__xve_stall_instfetch_xecore30_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext667 :: XVE STALL OTHER XECORE30 XVE0 THREAD0 */
#define acmgt3__ext667__xve_stall_other_xecore30_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext667 :: XVE STALL SBID XECORE30 XVE0 THREAD0 */
#define acmgt3__ext667__xve_stall_sbid_xecore30_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext667 :: XVE STALL SENDWR XECORE30 XVE0 THREAD0 */
#define acmgt3__ext667__xve_stall_sendwr_xecore30_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext667 :: XVE SHARED FUNCTION ACCESS HOLD XECORE30 XVE0 THREAD0 */
#define acmgt3__ext667__xve_shared_function_access_hold_xecore30_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext668 :: GPU Time Elapsed */
#define acmgt3__ext668__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext668 :: GPU Core Clocks */
#define acmgt3__ext668__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext668 :: AVG GPU Core Frequency */
#define acmgt3__ext668__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext668 :: AVG GPU Core Frequency */
#define acmgt3__ext668__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext668 :: XVE STALL ALUWR XECORE31 XVE0 THREAD0 */
#define acmgt3__ext668__xve_stall_aluwr_xecore31_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext668 :: XVE STALL BARRIER XECORE31 XVE0 THREAD0 */
#define acmgt3__ext668__xve_stall_barrier_xecore31_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext668 :: XVE STALL INSTFETCH XECORE31 XVE0 THREAD0 */
#define acmgt3__ext668__xve_stall_instfetch_xecore31_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext668 :: XVE STALL OTHER XECORE31 XVE0 THREAD0 */
#define acmgt3__ext668__xve_stall_other_xecore31_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext668 :: XVE STALL SBID XECORE31 XVE0 THREAD0 */
#define acmgt3__ext668__xve_stall_sbid_xecore31_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext668 :: XVE STALL SENDWR XECORE31 XVE0 THREAD0 */
#define acmgt3__ext668__xve_stall_sendwr_xecore31_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext668 :: XVE SHARED FUNCTION ACCESS HOLD XECORE31 XVE0 THREAD0 */
#define acmgt3__ext668__xve_shared_function_access_hold_xecore31_xve0_thread0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext669 :: GPU Time Elapsed */
#define acmgt3__ext669__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext669 :: GPU Core Clocks */
#define acmgt3__ext669__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext669 :: AVG GPU Core Frequency */
#define acmgt3__ext669__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext669 :: AVG GPU Core Frequency */
#define acmgt3__ext669__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext669 :: XVE INST ISSUED ALL XECORE0 XVE0 */
#define acmgt3__ext669__xve_inst_issued_all_xecore0_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext669 :: XVE INST ISSUED ALL XECORE1 XVE0 */
#define acmgt3__ext669__xve_inst_issued_all_xecore1_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext669 :: XVE INST ISSUED ALL XECORE2 XVE0 */
#define acmgt3__ext669__xve_inst_issued_all_xecore2_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext670 :: GPU Time Elapsed */
#define acmgt3__ext670__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext670 :: GPU Core Clocks */
#define acmgt3__ext670__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext670 :: AVG GPU Core Frequency */
#define acmgt3__ext670__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext670 :: AVG GPU Core Frequency */
#define acmgt3__ext670__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext670 :: XVE INST ISSUED ALL XECORE3 XVE0 */
#define acmgt3__ext670__xve_inst_issued_all_xecore3_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext670 :: XVE INST ISSUED ALL XECORE4 XVE0 */
#define acmgt3__ext670__xve_inst_issued_all_xecore4_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext670 :: XVE INST ISSUED ALL XECORE5 XVE0 */
#define acmgt3__ext670__xve_inst_issued_all_xecore5_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext671 :: GPU Time Elapsed */
#define acmgt3__ext671__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext671 :: GPU Core Clocks */
#define acmgt3__ext671__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext671 :: AVG GPU Core Frequency */
#define acmgt3__ext671__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext671 :: AVG GPU Core Frequency */
#define acmgt3__ext671__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext671 :: XVE INST ISSUED ALL XECORE6 XVE0 */
#define acmgt3__ext671__xve_inst_issued_all_xecore6_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext671 :: XVE INST ISSUED ALL XECORE7 XVE0 */
#define acmgt3__ext671__xve_inst_issued_all_xecore7_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext671 :: XVE INST ISSUED ALL XECORE8 XVE0 */
#define acmgt3__ext671__xve_inst_issued_all_xecore8_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext672 :: GPU Time Elapsed */
#define acmgt3__ext672__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext672 :: GPU Core Clocks */
#define acmgt3__ext672__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext672 :: AVG GPU Core Frequency */
#define acmgt3__ext672__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext672 :: AVG GPU Core Frequency */
#define acmgt3__ext672__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext672 :: XVE INST ISSUED ALL XECORE9 XVE0 */
#define acmgt3__ext672__xve_inst_issued_all_xecore9_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext672 :: XVE INST ISSUED ALL XECORE10 XVE0 */
#define acmgt3__ext672__xve_inst_issued_all_xecore10_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext672 :: XVE INST ISSUED ALL XECORE11 XVE0 */
#define acmgt3__ext672__xve_inst_issued_all_xecore11_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext673 :: GPU Time Elapsed */
#define acmgt3__ext673__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext673 :: GPU Core Clocks */
#define acmgt3__ext673__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext673 :: AVG GPU Core Frequency */
#define acmgt3__ext673__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext673 :: AVG GPU Core Frequency */
#define acmgt3__ext673__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext673 :: XVE INST ISSUED ALL XECORE12 XVE0 */
#define acmgt3__ext673__xve_inst_issued_all_xecore12_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext673 :: XVE INST ISSUED ALL XECORE13 XVE0 */
#define acmgt3__ext673__xve_inst_issued_all_xecore13_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext673 :: XVE INST ISSUED ALL XECORE14 XVE0 */
#define acmgt3__ext673__xve_inst_issued_all_xecore14_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext674 :: GPU Time Elapsed */
#define acmgt3__ext674__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext674 :: GPU Core Clocks */
#define acmgt3__ext674__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext674 :: AVG GPU Core Frequency */
#define acmgt3__ext674__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext674 :: AVG GPU Core Frequency */
#define acmgt3__ext674__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext674 :: XVE INST ISSUED ALL XECORE15 XVE0 */
#define acmgt3__ext674__xve_inst_issued_all_xecore15_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext674 :: XVE INST ISSUED ALL XECORE16 XVE0 */
#define acmgt3__ext674__xve_inst_issued_all_xecore16_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext674 :: XVE INST ISSUED ALL XECORE17 XVE0 */
#define acmgt3__ext674__xve_inst_issued_all_xecore17_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext675 :: GPU Time Elapsed */
#define acmgt3__ext675__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext675 :: GPU Core Clocks */
#define acmgt3__ext675__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext675 :: AVG GPU Core Frequency */
#define acmgt3__ext675__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext675 :: AVG GPU Core Frequency */
#define acmgt3__ext675__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext675 :: XVE INST ISSUED ALL XECORE18 XVE0 */
#define acmgt3__ext675__xve_inst_issued_all_xecore18_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext675 :: XVE INST ISSUED ALL XECORE19 XVE0 */
#define acmgt3__ext675__xve_inst_issued_all_xecore19_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext675 :: XVE INST ISSUED ALL XECORE20 XVE0 */
#define acmgt3__ext675__xve_inst_issued_all_xecore20_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext676 :: GPU Time Elapsed */
#define acmgt3__ext676__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext676 :: GPU Core Clocks */
#define acmgt3__ext676__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext676 :: AVG GPU Core Frequency */
#define acmgt3__ext676__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext676 :: AVG GPU Core Frequency */
#define acmgt3__ext676__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext676 :: XVE INST ISSUED ALL XECORE21 XVE0 */
#define acmgt3__ext676__xve_inst_issued_all_xecore21_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext676 :: XVE INST ISSUED ALL XECORE22 XVE0 */
#define acmgt3__ext676__xve_inst_issued_all_xecore22_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext676 :: XVE INST ISSUED ALL XECORE23 XVE0 */
#define acmgt3__ext676__xve_inst_issued_all_xecore23_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext677 :: GPU Time Elapsed */
#define acmgt3__ext677__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext677 :: GPU Core Clocks */
#define acmgt3__ext677__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext677 :: AVG GPU Core Frequency */
#define acmgt3__ext677__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext677 :: AVG GPU Core Frequency */
#define acmgt3__ext677__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext677 :: XVE INST ISSUED ALL XECORE24 XVE0 */
#define acmgt3__ext677__xve_inst_issued_all_xecore24_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext677 :: XVE INST ISSUED ALL XECORE25 XVE0 */
#define acmgt3__ext677__xve_inst_issued_all_xecore25_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext677 :: XVE INST ISSUED ALL XECORE26 XVE0 */
#define acmgt3__ext677__xve_inst_issued_all_xecore26_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext678 :: GPU Time Elapsed */
#define acmgt3__ext678__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext678 :: GPU Core Clocks */
#define acmgt3__ext678__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext678 :: AVG GPU Core Frequency */
#define acmgt3__ext678__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext678 :: AVG GPU Core Frequency */
#define acmgt3__ext678__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext678 :: XVE INST ISSUED ALL XECORE27 XVE0 */
#define acmgt3__ext678__xve_inst_issued_all_xecore27_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext678 :: XVE INST ISSUED ALL XECORE28 XVE0 */
#define acmgt3__ext678__xve_inst_issued_all_xecore28_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext678 :: XVE INST ISSUED ALL XECORE29 XVE0 */
#define acmgt3__ext678__xve_inst_issued_all_xecore29_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext679 :: GPU Time Elapsed */
#define acmgt3__ext679__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext679 :: GPU Core Clocks */
#define acmgt3__ext679__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext679 :: AVG GPU Core Frequency */
#define acmgt3__ext679__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext679 :: AVG GPU Core Frequency */
#define acmgt3__ext679__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext679 :: XVE INST ISSUED ALL XECORE30 XVE0 */
#define acmgt3__ext679__xve_inst_issued_all_xecore30_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext679 :: XVE INST ISSUED ALL XECORE31 XVE0 */
#define acmgt3__ext679__xve_inst_issued_all_xecore31_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext680 :: GPU Time Elapsed */
#define acmgt3__ext680__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext680 :: GPU Core Clocks */
#define acmgt3__ext680__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext680 :: AVG GPU Core Frequency */
#define acmgt3__ext680__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext680 :: AVG GPU Core Frequency */
#define acmgt3__ext680__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext680 :: RENDER CACHE ALLOC L3NODE0 */
#define acmgt3__ext680__render_cache_alloc_l3_node0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext680 :: RENDER CACHE ALLOC L3NODE1 */
#define acmgt3__ext680__render_cache_alloc_l3_node1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext680 :: RENDER CACHE ALLOC L3NODE2 */
#define acmgt3__ext680__render_cache_alloc_l3_node2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext680 :: RENDER CACHE ALLOC L3NODE3 */
#define acmgt3__ext680__render_cache_alloc_l3_node3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext680 :: RENDER CACHE ALLOC L3NODE4 */
#define acmgt3__ext680__render_cache_alloc_l3_node4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext680 :: RENDER CACHE ALLOC L3NODE5 */
#define acmgt3__ext680__render_cache_alloc_l3_node5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext680 :: RENDER CACHE ALLOC L3NODE6 */
#define acmgt3__ext680__render_cache_alloc_l3_node6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext680 :: RENDER CACHE ALLOC L3NODE7 */
#define acmgt3__ext680__render_cache_alloc_l3_node7__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext681 :: GPU Time Elapsed */
#define acmgt3__ext681__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext681 :: GPU Core Clocks */
#define acmgt3__ext681__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext681 :: AVG GPU Core Frequency */
#define acmgt3__ext681__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext681 :: AVG GPU Core Frequency */
#define acmgt3__ext681__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext681 :: GPGPU THREADGROUP COUNT XECORE0 */
#define acmgt3__ext681__gpgpu_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext681 :: ASYNC GPGPU THREADGROUP COUNT XECORE4 */
#define acmgt3__ext681__async_gpgpu_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext681 :: ASYNC GPGPU THREAD EXIT COUNT XECORE8 */
#define acmgt3__ext681__async_gpgpu_thread_exit_count_xecore8__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext682 :: GPU Time Elapsed */
#define acmgt3__ext682__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext682 :: GPU Core Clocks */
#define acmgt3__ext682__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext682 :: AVG GPU Core Frequency */
#define acmgt3__ext682__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext682 :: AVG GPU Core Frequency */
#define acmgt3__ext682__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext682 :: GPGPU THREADGROUP COUNT XECORE1 */
#define acmgt3__ext682__gpgpu_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext682 :: ASYNC GPGPU THREADGROUP COUNT XECORE5 */
#define acmgt3__ext682__async_gpgpu_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext682 :: ASYNC GPGPU THREAD EXIT COUNT XECORE9 */
#define acmgt3__ext682__async_gpgpu_thread_exit_count_xecore9__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext683 :: GPU Time Elapsed */
#define acmgt3__ext683__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext683 :: GPU Core Clocks */
#define acmgt3__ext683__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext683 :: AVG GPU Core Frequency */
#define acmgt3__ext683__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext683 :: AVG GPU Core Frequency */
#define acmgt3__ext683__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext683 :: GPGPU THREADGROUP COUNT XECORE2 */
#define acmgt3__ext683__gpgpu_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext683 :: ASYNC GPGPU THREADGROUP COUNT XECORE6 */
#define acmgt3__ext683__async_gpgpu_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext683 :: ASYNC GPGPU THREAD EXIT COUNT XECORE10 */
#define acmgt3__ext683__async_gpgpu_thread_exit_count_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext684 :: GPU Time Elapsed */
#define acmgt3__ext684__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext684 :: GPU Core Clocks */
#define acmgt3__ext684__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext684 :: AVG GPU Core Frequency */
#define acmgt3__ext684__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext684 :: AVG GPU Core Frequency */
#define acmgt3__ext684__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext684 :: GPGPU THREADGROUP COUNT XECORE3 */
#define acmgt3__ext684__gpgpu_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext684 :: ASYNC GPGPU THREADGROUP COUNT XECORE7 */
#define acmgt3__ext684__async_gpgpu_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext684 :: ASYNC GPGPU THREAD EXIT COUNT XECORE11 */
#define acmgt3__ext684__async_gpgpu_thread_exit_count_xecore11__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext685 :: GPU Time Elapsed */
#define acmgt3__ext685__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext685 :: GPU Core Clocks */
#define acmgt3__ext685__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext685 :: AVG GPU Core Frequency */
#define acmgt3__ext685__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext685 :: AVG GPU Core Frequency */
#define acmgt3__ext685__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext685 :: GPGPU THREADGROUP COUNT XECORE4 */
#define acmgt3__ext685__gpgpu_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext685 :: ASYNC GPGPU THREADGROUP COUNT XECORE8 */
#define acmgt3__ext685__async_gpgpu_threadgroup_count_xecore8__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext685 :: ASYNC GPGPU THREAD EXIT COUNT XECORE12 */
#define acmgt3__ext685__async_gpgpu_thread_exit_count_xecore12__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext686 :: GPU Time Elapsed */
#define acmgt3__ext686__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext686 :: GPU Core Clocks */
#define acmgt3__ext686__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext686 :: AVG GPU Core Frequency */
#define acmgt3__ext686__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext686 :: AVG GPU Core Frequency */
#define acmgt3__ext686__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext686 :: GPGPU THREADGROUP COUNT XECORE5 */
#define acmgt3__ext686__gpgpu_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext686 :: ASYNC GPGPU THREADGROUP COUNT XECORE9 */
#define acmgt3__ext686__async_gpgpu_threadgroup_count_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext686 :: ASYNC GPGPU THREAD EXIT COUNT XECORE13 */
#define acmgt3__ext686__async_gpgpu_thread_exit_count_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext687 :: GPU Time Elapsed */
#define acmgt3__ext687__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext687 :: GPU Core Clocks */
#define acmgt3__ext687__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext687 :: AVG GPU Core Frequency */
#define acmgt3__ext687__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext687 :: AVG GPU Core Frequency */
#define acmgt3__ext687__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext687 :: GPGPU THREADGROUP COUNT XECORE6 */
#define acmgt3__ext687__gpgpu_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext687 :: ASYNC GPGPU THREADGROUP COUNT XECORE10 */
#define acmgt3__ext687__async_gpgpu_threadgroup_count_xecore10__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext687 :: ASYNC GPGPU THREAD EXIT COUNT XECORE14 */
#define acmgt3__ext687__async_gpgpu_thread_exit_count_xecore14__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext688 :: GPU Time Elapsed */
#define acmgt3__ext688__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext688 :: GPU Core Clocks */
#define acmgt3__ext688__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext688 :: AVG GPU Core Frequency */
#define acmgt3__ext688__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext688 :: AVG GPU Core Frequency */
#define acmgt3__ext688__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext688 :: GPGPU THREADGROUP COUNT XECORE7 */
#define acmgt3__ext688__gpgpu_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext688 :: ASYNC GPGPU THREADGROUP COUNT XECORE11 */
#define acmgt3__ext688__async_gpgpu_threadgroup_count_xecore11__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext688 :: ASYNC GPGPU THREAD EXIT COUNT XECORE15 */
#define acmgt3__ext688__async_gpgpu_thread_exit_count_xecore15__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext689 :: GPU Time Elapsed */
#define acmgt3__ext689__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext689 :: GPU Core Clocks */
#define acmgt3__ext689__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext689 :: AVG GPU Core Frequency */
#define acmgt3__ext689__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext689 :: AVG GPU Core Frequency */
#define acmgt3__ext689__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext689 :: GPGPU THREADGROUP COUNT XECORE8 */
#define acmgt3__ext689__gpgpu_threadgroup_count_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext689 :: ASYNC GPGPU THREADGROUP COUNT XECORE12 */
#define acmgt3__ext689__async_gpgpu_threadgroup_count_xecore12__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext689 :: ASYNC GPGPU THREAD EXIT COUNT XECORE16 */
#define acmgt3__ext689__async_gpgpu_thread_exit_count_xecore16__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext690 :: GPU Time Elapsed */
#define acmgt3__ext690__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext690 :: GPU Core Clocks */
#define acmgt3__ext690__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext690 :: AVG GPU Core Frequency */
#define acmgt3__ext690__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext690 :: AVG GPU Core Frequency */
#define acmgt3__ext690__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext690 :: GPGPU THREADGROUP COUNT XECORE9 */
#define acmgt3__ext690__gpgpu_threadgroup_count_xecore9__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext690 :: ASYNC GPGPU THREADGROUP COUNT XECORE13 */
#define acmgt3__ext690__async_gpgpu_threadgroup_count_xecore13__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext690 :: ASYNC GPGPU THREAD EXIT COUNT XECORE17 */
#define acmgt3__ext690__async_gpgpu_thread_exit_count_xecore17__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext691 :: GPU Time Elapsed */
#define acmgt3__ext691__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext691 :: GPU Core Clocks */
#define acmgt3__ext691__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext691 :: AVG GPU Core Frequency */
#define acmgt3__ext691__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext691 :: AVG GPU Core Frequency */
#define acmgt3__ext691__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext691 :: GPGPU THREADGROUP COUNT XECORE10 */
#define acmgt3__ext691__gpgpu_threadgroup_count_xecore10__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext691 :: ASYNC GPGPU THREADGROUP COUNT XECORE14 */
#define acmgt3__ext691__async_gpgpu_threadgroup_count_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext691 :: ASYNC GPGPU THREAD EXIT COUNT XECORE18 */
#define acmgt3__ext691__async_gpgpu_thread_exit_count_xecore18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext692 :: GPU Time Elapsed */
#define acmgt3__ext692__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext692 :: GPU Core Clocks */
#define acmgt3__ext692__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext692 :: AVG GPU Core Frequency */
#define acmgt3__ext692__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext692 :: AVG GPU Core Frequency */
#define acmgt3__ext692__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext692 :: GPGPU THREADGROUP COUNT XECORE11 */
#define acmgt3__ext692__gpgpu_threadgroup_count_xecore11__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext692 :: ASYNC GPGPU THREADGROUP COUNT XECORE15 */
#define acmgt3__ext692__async_gpgpu_threadgroup_count_xecore15__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext692 :: ASYNC GPGPU THREAD EXIT COUNT XECORE19 */
#define acmgt3__ext692__async_gpgpu_thread_exit_count_xecore19__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext693 :: GPU Time Elapsed */
#define acmgt3__ext693__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext693 :: GPU Core Clocks */
#define acmgt3__ext693__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext693 :: AVG GPU Core Frequency */
#define acmgt3__ext693__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext693 :: AVG GPU Core Frequency */
#define acmgt3__ext693__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext693 :: GPGPU THREADGROUP COUNT XECORE12 */
#define acmgt3__ext693__gpgpu_threadgroup_count_xecore12__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext693 :: ASYNC GPGPU THREADGROUP COUNT XECORE16 */
#define acmgt3__ext693__async_gpgpu_threadgroup_count_xecore16__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext693 :: ASYNC GPGPU THREAD EXIT COUNT XECORE20 */
#define acmgt3__ext693__async_gpgpu_thread_exit_count_xecore20__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext694 :: GPU Time Elapsed */
#define acmgt3__ext694__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext694 :: GPU Core Clocks */
#define acmgt3__ext694__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext694 :: AVG GPU Core Frequency */
#define acmgt3__ext694__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext694 :: AVG GPU Core Frequency */
#define acmgt3__ext694__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext694 :: GPGPU THREADGROUP COUNT XECORE13 */
#define acmgt3__ext694__gpgpu_threadgroup_count_xecore13__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext694 :: ASYNC GPGPU THREADGROUP COUNT XECORE17 */
#define acmgt3__ext694__async_gpgpu_threadgroup_count_xecore17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext694 :: ASYNC GPGPU THREAD EXIT COUNT XECORE21 */
#define acmgt3__ext694__async_gpgpu_thread_exit_count_xecore21__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext695 :: GPU Time Elapsed */
#define acmgt3__ext695__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext695 :: GPU Core Clocks */
#define acmgt3__ext695__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext695 :: AVG GPU Core Frequency */
#define acmgt3__ext695__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext695 :: AVG GPU Core Frequency */
#define acmgt3__ext695__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext695 :: GPGPU THREADGROUP COUNT XECORE14 */
#define acmgt3__ext695__gpgpu_threadgroup_count_xecore14__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext695 :: ASYNC GPGPU THREADGROUP COUNT XECORE18 */
#define acmgt3__ext695__async_gpgpu_threadgroup_count_xecore18__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext695 :: ASYNC GPGPU THREAD EXIT COUNT XECORE22 */
#define acmgt3__ext695__async_gpgpu_thread_exit_count_xecore22__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext696 :: GPU Time Elapsed */
#define acmgt3__ext696__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext696 :: GPU Core Clocks */
#define acmgt3__ext696__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext696 :: AVG GPU Core Frequency */
#define acmgt3__ext696__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext696 :: AVG GPU Core Frequency */
#define acmgt3__ext696__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext696 :: GPGPU THREADGROUP COUNT XECORE15 */
#define acmgt3__ext696__gpgpu_threadgroup_count_xecore15__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext696 :: ASYNC GPGPU THREADGROUP COUNT XECORE19 */
#define acmgt3__ext696__async_gpgpu_threadgroup_count_xecore19__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext696 :: ASYNC GPGPU THREAD EXIT COUNT XECORE23 */
#define acmgt3__ext696__async_gpgpu_thread_exit_count_xecore23__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext697 :: GPU Time Elapsed */
#define acmgt3__ext697__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext697 :: GPU Core Clocks */
#define acmgt3__ext697__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext697 :: AVG GPU Core Frequency */
#define acmgt3__ext697__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext697 :: AVG GPU Core Frequency */
#define acmgt3__ext697__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext697 :: GPGPU THREADGROUP COUNT XECORE16 */
#define acmgt3__ext697__gpgpu_threadgroup_count_xecore16__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext697 :: ASYNC GPGPU THREADGROUP COUNT XECORE20 */
#define acmgt3__ext697__async_gpgpu_threadgroup_count_xecore20__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext697 :: ASYNC GPGPU THREAD EXIT COUNT XECORE24 */
#define acmgt3__ext697__async_gpgpu_thread_exit_count_xecore24__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext698 :: GPU Time Elapsed */
#define acmgt3__ext698__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext698 :: GPU Core Clocks */
#define acmgt3__ext698__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext698 :: AVG GPU Core Frequency */
#define acmgt3__ext698__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext698 :: AVG GPU Core Frequency */
#define acmgt3__ext698__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext698 :: GPGPU THREADGROUP COUNT XECORE17 */
#define acmgt3__ext698__gpgpu_threadgroup_count_xecore17__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext698 :: ASYNC GPGPU THREADGROUP COUNT XECORE21 */
#define acmgt3__ext698__async_gpgpu_threadgroup_count_xecore21__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext698 :: ASYNC GPGPU THREAD EXIT COUNT XECORE25 */
#define acmgt3__ext698__async_gpgpu_thread_exit_count_xecore25__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext699 :: GPU Time Elapsed */
#define acmgt3__ext699__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext699 :: GPU Core Clocks */
#define acmgt3__ext699__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext699 :: AVG GPU Core Frequency */
#define acmgt3__ext699__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext699 :: AVG GPU Core Frequency */
#define acmgt3__ext699__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext699 :: GPGPU THREADGROUP COUNT XECORE18 */
#define acmgt3__ext699__gpgpu_threadgroup_count_xecore18__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext699 :: ASYNC GPGPU THREADGROUP COUNT XECORE22 */
#define acmgt3__ext699__async_gpgpu_threadgroup_count_xecore22__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext699 :: ASYNC GPGPU THREAD EXIT COUNT XECORE26 */
#define acmgt3__ext699__async_gpgpu_thread_exit_count_xecore26__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext700 :: GPU Time Elapsed */
#define acmgt3__ext700__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext700 :: GPU Core Clocks */
#define acmgt3__ext700__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext700 :: AVG GPU Core Frequency */
#define acmgt3__ext700__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext700 :: AVG GPU Core Frequency */
#define acmgt3__ext700__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext700 :: GPGPU THREADGROUP COUNT XECORE19 */
#define acmgt3__ext700__gpgpu_threadgroup_count_xecore19__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext700 :: ASYNC GPGPU THREADGROUP COUNT XECORE23 */
#define acmgt3__ext700__async_gpgpu_threadgroup_count_xecore23__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext700 :: ASYNC GPGPU THREAD EXIT COUNT XECORE27 */
#define acmgt3__ext700__async_gpgpu_thread_exit_count_xecore27__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext701 :: GPU Time Elapsed */
#define acmgt3__ext701__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext701 :: GPU Core Clocks */
#define acmgt3__ext701__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext701 :: AVG GPU Core Frequency */
#define acmgt3__ext701__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext701 :: AVG GPU Core Frequency */
#define acmgt3__ext701__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext701 :: GPGPU THREADGROUP COUNT XECORE20 */
#define acmgt3__ext701__gpgpu_threadgroup_count_xecore20__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext701 :: ASYNC GPGPU THREADGROUP COUNT XECORE24 */
#define acmgt3__ext701__async_gpgpu_threadgroup_count_xecore24__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext701 :: ASYNC GPGPU THREAD EXIT COUNT XECORE28 */
#define acmgt3__ext701__async_gpgpu_thread_exit_count_xecore28__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext702 :: GPU Time Elapsed */
#define acmgt3__ext702__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext702 :: GPU Core Clocks */
#define acmgt3__ext702__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext702 :: AVG GPU Core Frequency */
#define acmgt3__ext702__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext702 :: AVG GPU Core Frequency */
#define acmgt3__ext702__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext702 :: GPGPU THREADGROUP COUNT XECORE21 */
#define acmgt3__ext702__gpgpu_threadgroup_count_xecore21__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext702 :: ASYNC GPGPU THREADGROUP COUNT XECORE25 */
#define acmgt3__ext702__async_gpgpu_threadgroup_count_xecore25__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext702 :: ASYNC GPGPU THREAD EXIT COUNT XECORE29 */
#define acmgt3__ext702__async_gpgpu_thread_exit_count_xecore29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext703 :: GPU Time Elapsed */
#define acmgt3__ext703__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext703 :: GPU Core Clocks */
#define acmgt3__ext703__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext703 :: AVG GPU Core Frequency */
#define acmgt3__ext703__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext703 :: AVG GPU Core Frequency */
#define acmgt3__ext703__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext703 :: GPGPU THREADGROUP COUNT XECORE22 */
#define acmgt3__ext703__gpgpu_threadgroup_count_xecore22__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext703 :: ASYNC GPGPU THREADGROUP COUNT XECORE26 */
#define acmgt3__ext703__async_gpgpu_threadgroup_count_xecore26__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext703 :: ASYNC GPGPU THREAD EXIT COUNT XECORE30 */
#define acmgt3__ext703__async_gpgpu_thread_exit_count_xecore30__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext704 :: GPU Time Elapsed */
#define acmgt3__ext704__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext704 :: GPU Core Clocks */
#define acmgt3__ext704__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext704 :: AVG GPU Core Frequency */
#define acmgt3__ext704__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext704 :: AVG GPU Core Frequency */
#define acmgt3__ext704__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext704 :: GPGPU THREADGROUP COUNT XECORE23 */
#define acmgt3__ext704__gpgpu_threadgroup_count_xecore23__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext704 :: ASYNC GPGPU THREADGROUP COUNT XECORE27 */
#define acmgt3__ext704__async_gpgpu_threadgroup_count_xecore27__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext704 :: ASYNC GPGPU THREAD EXIT COUNT XECORE31 */
#define acmgt3__ext704__async_gpgpu_thread_exit_count_xecore31__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext705 :: GPU Time Elapsed */
#define acmgt3__ext705__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext705 :: GPU Core Clocks */
#define acmgt3__ext705__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext705 :: AVG GPU Core Frequency */
#define acmgt3__ext705__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext705 :: AVG GPU Core Frequency */
#define acmgt3__ext705__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext705 :: GPGPU THREADGROUP COUNT XECORE24 */
#define acmgt3__ext705__gpgpu_threadgroup_count_xecore24__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext705 :: ASYNC GPGPU THREADGROUP COUNT XECORE28 */
#define acmgt3__ext705__async_gpgpu_threadgroup_count_xecore28__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext705 :: ASYNC GPGPU THREAD EXIT COUNT XECORE0 */
#define acmgt3__ext705__async_gpgpu_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext706 :: GPU Time Elapsed */
#define acmgt3__ext706__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext706 :: GPU Core Clocks */
#define acmgt3__ext706__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext706 :: AVG GPU Core Frequency */
#define acmgt3__ext706__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext706 :: AVG GPU Core Frequency */
#define acmgt3__ext706__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext706 :: GPGPU THREADGROUP COUNT XECORE25 */
#define acmgt3__ext706__gpgpu_threadgroup_count_xecore25__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext706 :: ASYNC GPGPU THREADGROUP COUNT XECORE29 */
#define acmgt3__ext706__async_gpgpu_threadgroup_count_xecore29__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext706 :: ASYNC GPGPU THREAD EXIT COUNT XECORE1 */
#define acmgt3__ext706__async_gpgpu_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext707 :: GPU Time Elapsed */
#define acmgt3__ext707__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext707 :: GPU Core Clocks */
#define acmgt3__ext707__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext707 :: AVG GPU Core Frequency */
#define acmgt3__ext707__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext707 :: AVG GPU Core Frequency */
#define acmgt3__ext707__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext707 :: GPGPU THREADGROUP COUNT XECORE26 */
#define acmgt3__ext707__gpgpu_threadgroup_count_xecore26__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext707 :: ASYNC GPGPU THREADGROUP COUNT XECORE30 */
#define acmgt3__ext707__async_gpgpu_threadgroup_count_xecore30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext707 :: ASYNC GPGPU THREAD EXIT COUNT XECORE2 */
#define acmgt3__ext707__async_gpgpu_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext708 :: GPU Time Elapsed */
#define acmgt3__ext708__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext708 :: GPU Core Clocks */
#define acmgt3__ext708__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext708 :: AVG GPU Core Frequency */
#define acmgt3__ext708__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext708 :: AVG GPU Core Frequency */
#define acmgt3__ext708__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext708 :: GPGPU THREADGROUP COUNT XECORE27 */
#define acmgt3__ext708__gpgpu_threadgroup_count_xecore27__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext708 :: ASYNC GPGPU THREADGROUP COUNT XECORE31 */
#define acmgt3__ext708__async_gpgpu_threadgroup_count_xecore31__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext708 :: ASYNC GPGPU THREAD EXIT COUNT XECORE3 */
#define acmgt3__ext708__async_gpgpu_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext709 :: GPU Time Elapsed */
#define acmgt3__ext709__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext709 :: GPU Core Clocks */
#define acmgt3__ext709__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext709 :: AVG GPU Core Frequency */
#define acmgt3__ext709__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext709 :: AVG GPU Core Frequency */
#define acmgt3__ext709__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext709 :: GPGPU THREADGROUP COUNT XECORE28 */
#define acmgt3__ext709__gpgpu_threadgroup_count_xecore28__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext709 :: ASYNC GPGPU THREADGROUP COUNT XECORE0 */
#define acmgt3__ext709__async_gpgpu_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext709 :: ASYNC GPGPU THREAD EXIT COUNT XECORE4 */
#define acmgt3__ext709__async_gpgpu_thread_exit_count_xecore4__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext710 :: GPU Time Elapsed */
#define acmgt3__ext710__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext710 :: GPU Core Clocks */
#define acmgt3__ext710__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext710 :: AVG GPU Core Frequency */
#define acmgt3__ext710__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext710 :: AVG GPU Core Frequency */
#define acmgt3__ext710__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext710 :: GPGPU THREADGROUP COUNT XECORE29 */
#define acmgt3__ext710__gpgpu_threadgroup_count_xecore29__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext710 :: ASYNC GPGPU THREADGROUP COUNT XECORE1 */
#define acmgt3__ext710__async_gpgpu_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext710 :: ASYNC GPGPU THREAD EXIT COUNT XECORE5 */
#define acmgt3__ext710__async_gpgpu_thread_exit_count_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext711 :: GPU Time Elapsed */
#define acmgt3__ext711__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext711 :: GPU Core Clocks */
#define acmgt3__ext711__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext711 :: AVG GPU Core Frequency */
#define acmgt3__ext711__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext711 :: AVG GPU Core Frequency */
#define acmgt3__ext711__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext711 :: GPGPU THREADGROUP COUNT XECORE30 */
#define acmgt3__ext711__gpgpu_threadgroup_count_xecore30__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext711 :: ASYNC GPGPU THREADGROUP COUNT XECORE2 */
#define acmgt3__ext711__async_gpgpu_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext711 :: ASYNC GPGPU THREAD EXIT COUNT XECORE6 */
#define acmgt3__ext711__async_gpgpu_thread_exit_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext712 :: GPU Time Elapsed */
#define acmgt3__ext712__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext712 :: GPU Core Clocks */
#define acmgt3__ext712__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext712 :: AVG GPU Core Frequency */
#define acmgt3__ext712__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext712 :: AVG GPU Core Frequency */
#define acmgt3__ext712__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext712 :: GPGPU THREADGROUP COUNT XECORE31 */
#define acmgt3__ext712__gpgpu_threadgroup_count_xecore31__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext712 :: ASYNC GPGPU THREADGROUP COUNT XECORE3 */
#define acmgt3__ext712__async_gpgpu_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext712 :: ASYNC GPGPU THREAD EXIT COUNT XECORE7 */
#define acmgt3__ext712__async_gpgpu_thread_exit_count_xecore7__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext713 :: GPU Time Elapsed */
#define acmgt3__ext713__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext713 :: GPU Core Clocks */
#define acmgt3__ext713__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext713 :: AVG GPU Core Frequency */
#define acmgt3__ext713__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext713 :: AVG GPU Core Frequency */
#define acmgt3__ext713__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext713 :: TASK THREADGROUP COUNT XECORE0 */
#define acmgt3__ext713__task_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext713 :: TASK THREAD EXIT COUNT XECORE4 */
#define acmgt3__ext713__task_thread_exit_count_xecore4__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext713 :: THREADGROUP DISPATCH RESOURCE STALL XECORE8 */
#define acmgt3__ext713__threadgroup_dispatch_resource_stall_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext714 :: GPU Time Elapsed */
#define acmgt3__ext714__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext714 :: GPU Core Clocks */
#define acmgt3__ext714__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext714 :: AVG GPU Core Frequency */
#define acmgt3__ext714__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext714 :: AVG GPU Core Frequency */
#define acmgt3__ext714__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext714 :: TASK THREADGROUP COUNT XECORE1 */
#define acmgt3__ext714__task_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext714 :: TASK THREAD EXIT COUNT XECORE5 */
#define acmgt3__ext714__task_thread_exit_count_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext714 :: THREADGROUP DISPATCH RESOURCE STALL XECORE9 */
#define acmgt3__ext714__threadgroup_dispatch_resource_stall_xecore9__read \
   bdw__render_basic__sampler0_busy__read

/* Ext715 :: GPU Time Elapsed */
#define acmgt3__ext715__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext715 :: GPU Core Clocks */
#define acmgt3__ext715__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext715 :: AVG GPU Core Frequency */
#define acmgt3__ext715__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext715 :: AVG GPU Core Frequency */
#define acmgt3__ext715__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext715 :: TASK THREADGROUP COUNT XECORE2 */
#define acmgt3__ext715__task_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext715 :: TASK THREAD EXIT COUNT XECORE6 */
#define acmgt3__ext715__task_thread_exit_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext715 :: THREADGROUP DISPATCH RESOURCE STALL XECORE10 */
#define acmgt3__ext715__threadgroup_dispatch_resource_stall_xecore10__read \
   bdw__render_basic__sampler0_busy__read

/* Ext716 :: GPU Time Elapsed */
#define acmgt3__ext716__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext716 :: GPU Core Clocks */
#define acmgt3__ext716__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext716 :: AVG GPU Core Frequency */
#define acmgt3__ext716__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext716 :: AVG GPU Core Frequency */
#define acmgt3__ext716__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext716 :: TASK THREADGROUP COUNT XECORE3 */
#define acmgt3__ext716__task_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext716 :: TASK THREAD EXIT COUNT XECORE7 */
#define acmgt3__ext716__task_thread_exit_count_xecore7__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext716 :: THREADGROUP DISPATCH RESOURCE STALL XECORE11 */
#define acmgt3__ext716__threadgroup_dispatch_resource_stall_xecore11__read \
   bdw__render_basic__sampler0_busy__read

/* Ext717 :: GPU Time Elapsed */
#define acmgt3__ext717__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext717 :: GPU Core Clocks */
#define acmgt3__ext717__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext717 :: AVG GPU Core Frequency */
#define acmgt3__ext717__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext717 :: AVG GPU Core Frequency */
#define acmgt3__ext717__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext717 :: TASK THREADGROUP COUNT XECORE4 */
#define acmgt3__ext717__task_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext717 :: TASK THREAD EXIT COUNT XECORE8 */
#define acmgt3__ext717__task_thread_exit_count_xecore8__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext717 :: THREADGROUP DISPATCH RESOURCE STALL XECORE12 */
#define acmgt3__ext717__threadgroup_dispatch_resource_stall_xecore12__read \
   bdw__render_basic__sampler0_busy__read

/* Ext718 :: GPU Time Elapsed */
#define acmgt3__ext718__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext718 :: GPU Core Clocks */
#define acmgt3__ext718__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext718 :: AVG GPU Core Frequency */
#define acmgt3__ext718__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext718 :: AVG GPU Core Frequency */
#define acmgt3__ext718__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext718 :: TASK THREADGROUP COUNT XECORE5 */
#define acmgt3__ext718__task_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext718 :: TASK THREAD EXIT COUNT XECORE9 */
#define acmgt3__ext718__task_thread_exit_count_xecore9__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext718 :: THREADGROUP DISPATCH RESOURCE STALL XECORE13 */
#define acmgt3__ext718__threadgroup_dispatch_resource_stall_xecore13__read \
   bdw__render_basic__sampler0_busy__read

/* Ext719 :: GPU Time Elapsed */
#define acmgt3__ext719__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext719 :: GPU Core Clocks */
#define acmgt3__ext719__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext719 :: AVG GPU Core Frequency */
#define acmgt3__ext719__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext719 :: AVG GPU Core Frequency */
#define acmgt3__ext719__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext719 :: TASK THREADGROUP COUNT XECORE6 */
#define acmgt3__ext719__task_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext719 :: TASK THREAD EXIT COUNT XECORE10 */
#define acmgt3__ext719__task_thread_exit_count_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext719 :: THREADGROUP DISPATCH RESOURCE STALL XECORE14 */
#define acmgt3__ext719__threadgroup_dispatch_resource_stall_xecore14__read \
   bdw__render_basic__sampler0_busy__read

/* Ext720 :: GPU Time Elapsed */
#define acmgt3__ext720__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext720 :: GPU Core Clocks */
#define acmgt3__ext720__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext720 :: AVG GPU Core Frequency */
#define acmgt3__ext720__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext720 :: AVG GPU Core Frequency */
#define acmgt3__ext720__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext720 :: TASK THREADGROUP COUNT XECORE7 */
#define acmgt3__ext720__task_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext720 :: TASK THREAD EXIT COUNT XECORE11 */
#define acmgt3__ext720__task_thread_exit_count_xecore11__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext720 :: THREADGROUP DISPATCH RESOURCE STALL XECORE15 */
#define acmgt3__ext720__threadgroup_dispatch_resource_stall_xecore15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext721 :: GPU Time Elapsed */
#define acmgt3__ext721__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext721 :: GPU Core Clocks */
#define acmgt3__ext721__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext721 :: AVG GPU Core Frequency */
#define acmgt3__ext721__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext721 :: AVG GPU Core Frequency */
#define acmgt3__ext721__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext721 :: TASK THREADGROUP COUNT XECORE8 */
#define acmgt3__ext721__task_threadgroup_count_xecore8__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext721 :: TASK THREAD EXIT COUNT XECORE12 */
#define acmgt3__ext721__task_thread_exit_count_xecore12__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext721 :: THREADGROUP DISPATCH RESOURCE STALL XECORE16 */
#define acmgt3__ext721__threadgroup_dispatch_resource_stall_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext722 :: GPU Time Elapsed */
#define acmgt3__ext722__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext722 :: GPU Core Clocks */
#define acmgt3__ext722__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext722 :: AVG GPU Core Frequency */
#define acmgt3__ext722__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext722 :: AVG GPU Core Frequency */
#define acmgt3__ext722__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext722 :: TASK THREADGROUP COUNT XECORE9 */
#define acmgt3__ext722__task_threadgroup_count_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext722 :: TASK THREAD EXIT COUNT XECORE13 */
#define acmgt3__ext722__task_thread_exit_count_xecore13__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext722 :: THREADGROUP DISPATCH RESOURCE STALL XECORE17 */
#define acmgt3__ext722__threadgroup_dispatch_resource_stall_xecore17__read \
   bdw__render_basic__sampler0_busy__read

/* Ext723 :: GPU Time Elapsed */
#define acmgt3__ext723__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext723 :: GPU Core Clocks */
#define acmgt3__ext723__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext723 :: AVG GPU Core Frequency */
#define acmgt3__ext723__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext723 :: AVG GPU Core Frequency */
#define acmgt3__ext723__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext723 :: TASK THREADGROUP COUNT XECORE10 */
#define acmgt3__ext723__task_threadgroup_count_xecore10__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext723 :: TASK THREAD EXIT COUNT XECORE14 */
#define acmgt3__ext723__task_thread_exit_count_xecore14__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext723 :: THREADGROUP DISPATCH RESOURCE STALL XECORE18 */
#define acmgt3__ext723__threadgroup_dispatch_resource_stall_xecore18__read \
   bdw__render_basic__sampler0_busy__read

/* Ext724 :: GPU Time Elapsed */
#define acmgt3__ext724__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext724 :: GPU Core Clocks */
#define acmgt3__ext724__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext724 :: AVG GPU Core Frequency */
#define acmgt3__ext724__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext724 :: AVG GPU Core Frequency */
#define acmgt3__ext724__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext724 :: TASK THREADGROUP COUNT XECORE11 */
#define acmgt3__ext724__task_threadgroup_count_xecore11__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext724 :: TASK THREAD EXIT COUNT XECORE15 */
#define acmgt3__ext724__task_thread_exit_count_xecore15__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext724 :: THREADGROUP DISPATCH RESOURCE STALL XECORE19 */
#define acmgt3__ext724__threadgroup_dispatch_resource_stall_xecore19__read \
   bdw__render_basic__sampler0_busy__read

/* Ext725 :: GPU Time Elapsed */
#define acmgt3__ext725__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext725 :: GPU Core Clocks */
#define acmgt3__ext725__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext725 :: AVG GPU Core Frequency */
#define acmgt3__ext725__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext725 :: AVG GPU Core Frequency */
#define acmgt3__ext725__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext725 :: TASK THREADGROUP COUNT XECORE12 */
#define acmgt3__ext725__task_threadgroup_count_xecore12__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext725 :: TASK THREAD EXIT COUNT XECORE16 */
#define acmgt3__ext725__task_thread_exit_count_xecore16__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext725 :: THREADGROUP DISPATCH RESOURCE STALL XECORE20 */
#define acmgt3__ext725__threadgroup_dispatch_resource_stall_xecore20__read \
   bdw__render_basic__sampler0_busy__read

/* Ext726 :: GPU Time Elapsed */
#define acmgt3__ext726__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext726 :: GPU Core Clocks */
#define acmgt3__ext726__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext726 :: AVG GPU Core Frequency */
#define acmgt3__ext726__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext726 :: AVG GPU Core Frequency */
#define acmgt3__ext726__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext726 :: TASK THREADGROUP COUNT XECORE13 */
#define acmgt3__ext726__task_threadgroup_count_xecore13__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext726 :: TASK THREAD EXIT COUNT XECORE17 */
#define acmgt3__ext726__task_thread_exit_count_xecore17__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext726 :: THREADGROUP DISPATCH RESOURCE STALL XECORE21 */
#define acmgt3__ext726__threadgroup_dispatch_resource_stall_xecore21__read \
   bdw__render_basic__sampler0_busy__read

/* Ext727 :: GPU Time Elapsed */
#define acmgt3__ext727__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext727 :: GPU Core Clocks */
#define acmgt3__ext727__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext727 :: AVG GPU Core Frequency */
#define acmgt3__ext727__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext727 :: AVG GPU Core Frequency */
#define acmgt3__ext727__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext727 :: TASK THREADGROUP COUNT XECORE14 */
#define acmgt3__ext727__task_threadgroup_count_xecore14__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext727 :: TASK THREAD EXIT COUNT XECORE18 */
#define acmgt3__ext727__task_thread_exit_count_xecore18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext727 :: THREADGROUP DISPATCH RESOURCE STALL XECORE22 */
#define acmgt3__ext727__threadgroup_dispatch_resource_stall_xecore22__read \
   bdw__render_basic__sampler0_busy__read

/* Ext728 :: GPU Time Elapsed */
#define acmgt3__ext728__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext728 :: GPU Core Clocks */
#define acmgt3__ext728__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext728 :: AVG GPU Core Frequency */
#define acmgt3__ext728__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext728 :: AVG GPU Core Frequency */
#define acmgt3__ext728__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext728 :: TASK THREADGROUP COUNT XECORE15 */
#define acmgt3__ext728__task_threadgroup_count_xecore15__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext728 :: TASK THREAD EXIT COUNT XECORE19 */
#define acmgt3__ext728__task_thread_exit_count_xecore19__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext728 :: THREADGROUP DISPATCH RESOURCE STALL XECORE23 */
#define acmgt3__ext728__threadgroup_dispatch_resource_stall_xecore23__read \
   bdw__render_basic__sampler0_busy__read

/* Ext729 :: GPU Time Elapsed */
#define acmgt3__ext729__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext729 :: GPU Core Clocks */
#define acmgt3__ext729__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext729 :: AVG GPU Core Frequency */
#define acmgt3__ext729__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext729 :: AVG GPU Core Frequency */
#define acmgt3__ext729__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext729 :: TASK THREADGROUP COUNT XECORE16 */
#define acmgt3__ext729__task_threadgroup_count_xecore16__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext729 :: TASK THREAD EXIT COUNT XECORE20 */
#define acmgt3__ext729__task_thread_exit_count_xecore20__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext729 :: THREADGROUP DISPATCH RESOURCE STALL XECORE24 */
#define acmgt3__ext729__threadgroup_dispatch_resource_stall_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext730 :: GPU Time Elapsed */
#define acmgt3__ext730__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext730 :: GPU Core Clocks */
#define acmgt3__ext730__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext730 :: AVG GPU Core Frequency */
#define acmgt3__ext730__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext730 :: AVG GPU Core Frequency */
#define acmgt3__ext730__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext730 :: TASK THREADGROUP COUNT XECORE17 */
#define acmgt3__ext730__task_threadgroup_count_xecore17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext730 :: TASK THREAD EXIT COUNT XECORE21 */
#define acmgt3__ext730__task_thread_exit_count_xecore21__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext730 :: THREADGROUP DISPATCH RESOURCE STALL XECORE25 */
#define acmgt3__ext730__threadgroup_dispatch_resource_stall_xecore25__read \
   bdw__render_basic__sampler0_busy__read

/* Ext731 :: GPU Time Elapsed */
#define acmgt3__ext731__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext731 :: GPU Core Clocks */
#define acmgt3__ext731__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext731 :: AVG GPU Core Frequency */
#define acmgt3__ext731__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext731 :: AVG GPU Core Frequency */
#define acmgt3__ext731__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext731 :: TASK THREADGROUP COUNT XECORE18 */
#define acmgt3__ext731__task_threadgroup_count_xecore18__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext731 :: TASK THREAD EXIT COUNT XECORE22 */
#define acmgt3__ext731__task_thread_exit_count_xecore22__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext731 :: THREADGROUP DISPATCH RESOURCE STALL XECORE26 */
#define acmgt3__ext731__threadgroup_dispatch_resource_stall_xecore26__read \
   bdw__render_basic__sampler0_busy__read

/* Ext732 :: GPU Time Elapsed */
#define acmgt3__ext732__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext732 :: GPU Core Clocks */
#define acmgt3__ext732__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext732 :: AVG GPU Core Frequency */
#define acmgt3__ext732__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext732 :: AVG GPU Core Frequency */
#define acmgt3__ext732__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext732 :: TASK THREADGROUP COUNT XECORE19 */
#define acmgt3__ext732__task_threadgroup_count_xecore19__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext732 :: TASK THREAD EXIT COUNT XECORE23 */
#define acmgt3__ext732__task_thread_exit_count_xecore23__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext732 :: THREADGROUP DISPATCH RESOURCE STALL XECORE27 */
#define acmgt3__ext732__threadgroup_dispatch_resource_stall_xecore27__read \
   bdw__render_basic__sampler0_busy__read

/* Ext733 :: GPU Time Elapsed */
#define acmgt3__ext733__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext733 :: GPU Core Clocks */
#define acmgt3__ext733__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext733 :: AVG GPU Core Frequency */
#define acmgt3__ext733__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext733 :: AVG GPU Core Frequency */
#define acmgt3__ext733__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext733 :: TASK THREADGROUP COUNT XECORE20 */
#define acmgt3__ext733__task_threadgroup_count_xecore20__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext733 :: TASK THREAD EXIT COUNT XECORE24 */
#define acmgt3__ext733__task_thread_exit_count_xecore24__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext733 :: THREADGROUP DISPATCH RESOURCE STALL XECORE28 */
#define acmgt3__ext733__threadgroup_dispatch_resource_stall_xecore28__read \
   bdw__render_basic__sampler0_busy__read

/* Ext734 :: GPU Time Elapsed */
#define acmgt3__ext734__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext734 :: GPU Core Clocks */
#define acmgt3__ext734__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext734 :: AVG GPU Core Frequency */
#define acmgt3__ext734__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext734 :: AVG GPU Core Frequency */
#define acmgt3__ext734__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext734 :: TASK THREADGROUP COUNT XECORE21 */
#define acmgt3__ext734__task_threadgroup_count_xecore21__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext734 :: TASK THREAD EXIT COUNT XECORE25 */
#define acmgt3__ext734__task_thread_exit_count_xecore25__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext734 :: THREADGROUP DISPATCH RESOURCE STALL XECORE29 */
#define acmgt3__ext734__threadgroup_dispatch_resource_stall_xecore29__read \
   bdw__render_basic__sampler0_busy__read

/* Ext735 :: GPU Time Elapsed */
#define acmgt3__ext735__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext735 :: GPU Core Clocks */
#define acmgt3__ext735__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext735 :: AVG GPU Core Frequency */
#define acmgt3__ext735__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext735 :: AVG GPU Core Frequency */
#define acmgt3__ext735__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext735 :: TASK THREADGROUP COUNT XECORE22 */
#define acmgt3__ext735__task_threadgroup_count_xecore22__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext735 :: TASK THREAD EXIT COUNT XECORE26 */
#define acmgt3__ext735__task_thread_exit_count_xecore26__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext735 :: THREADGROUP DISPATCH RESOURCE STALL XECORE30 */
#define acmgt3__ext735__threadgroup_dispatch_resource_stall_xecore30__read \
   bdw__render_basic__sampler0_busy__read

/* Ext736 :: GPU Time Elapsed */
#define acmgt3__ext736__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext736 :: GPU Core Clocks */
#define acmgt3__ext736__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext736 :: AVG GPU Core Frequency */
#define acmgt3__ext736__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext736 :: AVG GPU Core Frequency */
#define acmgt3__ext736__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext736 :: TASK THREADGROUP COUNT XECORE23 */
#define acmgt3__ext736__task_threadgroup_count_xecore23__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext736 :: TASK THREAD EXIT COUNT XECORE27 */
#define acmgt3__ext736__task_thread_exit_count_xecore27__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext736 :: THREADGROUP DISPATCH RESOURCE STALL XECORE31 */
#define acmgt3__ext736__threadgroup_dispatch_resource_stall_xecore31__read \
   bdw__render_basic__sampler0_busy__read

/* Ext737 :: GPU Time Elapsed */
#define acmgt3__ext737__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext737 :: GPU Core Clocks */
#define acmgt3__ext737__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext737 :: AVG GPU Core Frequency */
#define acmgt3__ext737__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext737 :: AVG GPU Core Frequency */
#define acmgt3__ext737__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext737 :: TASK THREADGROUP COUNT XECORE24 */
#define acmgt3__ext737__task_threadgroup_count_xecore24__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext737 :: TASK THREAD EXIT COUNT XECORE28 */
#define acmgt3__ext737__task_thread_exit_count_xecore28__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext737 :: THREADGROUP DISPATCH RESOURCE STALL XECORE0 */
#define acmgt3__ext737__threadgroup_dispatch_resource_stall_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext738 :: GPU Time Elapsed */
#define acmgt3__ext738__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext738 :: GPU Core Clocks */
#define acmgt3__ext738__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext738 :: AVG GPU Core Frequency */
#define acmgt3__ext738__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext738 :: AVG GPU Core Frequency */
#define acmgt3__ext738__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext738 :: TASK THREADGROUP COUNT XECORE25 */
#define acmgt3__ext738__task_threadgroup_count_xecore25__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext738 :: TASK THREAD EXIT COUNT XECORE29 */
#define acmgt3__ext738__task_thread_exit_count_xecore29__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext738 :: THREADGROUP DISPATCH RESOURCE STALL XECORE1 */
#define acmgt3__ext738__threadgroup_dispatch_resource_stall_xecore1__read \
   bdw__render_basic__sampler0_busy__read

/* Ext739 :: GPU Time Elapsed */
#define acmgt3__ext739__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext739 :: GPU Core Clocks */
#define acmgt3__ext739__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext739 :: AVG GPU Core Frequency */
#define acmgt3__ext739__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext739 :: AVG GPU Core Frequency */
#define acmgt3__ext739__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext739 :: TASK THREADGROUP COUNT XECORE26 */
#define acmgt3__ext739__task_threadgroup_count_xecore26__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext739 :: TASK THREAD EXIT COUNT XECORE30 */
#define acmgt3__ext739__task_thread_exit_count_xecore30__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext739 :: THREADGROUP DISPATCH RESOURCE STALL XECORE2 */
#define acmgt3__ext739__threadgroup_dispatch_resource_stall_xecore2__read \
   bdw__render_basic__sampler0_busy__read

/* Ext740 :: GPU Time Elapsed */
#define acmgt3__ext740__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext740 :: GPU Core Clocks */
#define acmgt3__ext740__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext740 :: AVG GPU Core Frequency */
#define acmgt3__ext740__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext740 :: AVG GPU Core Frequency */
#define acmgt3__ext740__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext740 :: TASK THREADGROUP COUNT XECORE27 */
#define acmgt3__ext740__task_threadgroup_count_xecore27__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext740 :: TASK THREAD EXIT COUNT XECORE31 */
#define acmgt3__ext740__task_thread_exit_count_xecore31__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext740 :: THREADGROUP DISPATCH RESOURCE STALL XECORE3 */
#define acmgt3__ext740__threadgroup_dispatch_resource_stall_xecore3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext741 :: GPU Time Elapsed */
#define acmgt3__ext741__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext741 :: GPU Core Clocks */
#define acmgt3__ext741__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext741 :: AVG GPU Core Frequency */
#define acmgt3__ext741__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext741 :: AVG GPU Core Frequency */
#define acmgt3__ext741__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext741 :: TASK THREADGROUP COUNT XECORE28 */
#define acmgt3__ext741__task_threadgroup_count_xecore28__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext741 :: TASK THREAD EXIT COUNT XECORE0 */
#define acmgt3__ext741__task_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext741 :: THREADGROUP DISPATCH RESOURCE STALL XECORE4 */
#define acmgt3__ext741__threadgroup_dispatch_resource_stall_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext742 :: GPU Time Elapsed */
#define acmgt3__ext742__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext742 :: GPU Core Clocks */
#define acmgt3__ext742__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext742 :: AVG GPU Core Frequency */
#define acmgt3__ext742__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext742 :: AVG GPU Core Frequency */
#define acmgt3__ext742__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext742 :: TASK THREADGROUP COUNT XECORE29 */
#define acmgt3__ext742__task_threadgroup_count_xecore29__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext742 :: TASK THREAD EXIT COUNT XECORE1 */
#define acmgt3__ext742__task_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext742 :: THREADGROUP DISPATCH RESOURCE STALL XECORE5 */
#define acmgt3__ext742__threadgroup_dispatch_resource_stall_xecore5__read \
   bdw__render_basic__sampler0_busy__read

/* Ext743 :: GPU Time Elapsed */
#define acmgt3__ext743__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext743 :: GPU Core Clocks */
#define acmgt3__ext743__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext743 :: AVG GPU Core Frequency */
#define acmgt3__ext743__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext743 :: AVG GPU Core Frequency */
#define acmgt3__ext743__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext743 :: TASK THREADGROUP COUNT XECORE30 */
#define acmgt3__ext743__task_threadgroup_count_xecore30__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext743 :: TASK THREAD EXIT COUNT XECORE2 */
#define acmgt3__ext743__task_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext743 :: THREADGROUP DISPATCH RESOURCE STALL XECORE6 */
#define acmgt3__ext743__threadgroup_dispatch_resource_stall_xecore6__read \
   bdw__render_basic__sampler0_busy__read

/* Ext744 :: GPU Time Elapsed */
#define acmgt3__ext744__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext744 :: GPU Core Clocks */
#define acmgt3__ext744__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext744 :: AVG GPU Core Frequency */
#define acmgt3__ext744__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext744 :: AVG GPU Core Frequency */
#define acmgt3__ext744__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext744 :: TASK THREADGROUP COUNT XECORE31 */
#define acmgt3__ext744__task_threadgroup_count_xecore31__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext744 :: TASK THREAD EXIT COUNT XECORE3 */
#define acmgt3__ext744__task_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext744 :: THREADGROUP DISPATCH RESOURCE STALL XECORE7 */
#define acmgt3__ext744__threadgroup_dispatch_resource_stall_xecore7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext745 :: GPU Time Elapsed */
#define acmgt3__ext745__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext745 :: GPU Core Clocks */
#define acmgt3__ext745__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext745 :: AVG GPU Core Frequency */
#define acmgt3__ext745__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext745 :: AVG GPU Core Frequency */
#define acmgt3__ext745__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE0 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE1 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE2 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE3 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE4 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE5 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE6 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE7 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE8 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE9 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE10 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE11 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE12 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE13 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE14 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext745 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE15 */
#define acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext746 :: GPU Time Elapsed */
#define acmgt3__ext746__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext746 :: GPU Core Clocks */
#define acmgt3__ext746__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext746 :: AVG GPU Core Frequency */
#define acmgt3__ext746__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext746 :: AVG GPU Core Frequency */
#define acmgt3__ext746__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE16 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore16__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE17 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore17__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE18 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore18__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE19 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore19__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE20 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore20__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE21 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore21__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE22 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore22__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE23 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore23__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE24 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore24__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE25 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore25__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE26 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore26__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE27 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore27__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE28 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore28__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE29 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore29__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE30 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore30__read \
   bdw__render_basic__sampler1_busy__read

/* Ext746 :: THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE31 */
#define acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore31__read \
   bdw__render_basic__sampler0_busy__read

/* Ext747 :: GPU Time Elapsed */
#define acmgt3__ext747__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext747 :: GPU Core Clocks */
#define acmgt3__ext747__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext747 :: AVG GPU Core Frequency */
#define acmgt3__ext747__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext747 :: AVG GPU Core Frequency */
#define acmgt3__ext747__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE0 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE1 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE2 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE3 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE4 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE5 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE6 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE7 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE8 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE9 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE10 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE11 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE12 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE13 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE14 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext747 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE15 */
#define acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext748 :: GPU Time Elapsed */
#define acmgt3__ext748__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext748 :: GPU Core Clocks */
#define acmgt3__ext748__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext748 :: AVG GPU Core Frequency */
#define acmgt3__ext748__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext748 :: AVG GPU Core Frequency */
#define acmgt3__ext748__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE16 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore16__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE17 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore17__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE18 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore18__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE19 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore19__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE20 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore20__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE21 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore21__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE22 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore22__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE23 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore23__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE24 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore24__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE25 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore25__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE26 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore26__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE27 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore27__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE28 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore28__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE29 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore29__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE30 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore30__read \
   bdw__render_basic__sampler1_busy__read

/* Ext748 :: THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE31 */
#define acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore31__read \
   bdw__render_basic__sampler0_busy__read

/* Ext749 :: GPU Time Elapsed */
#define acmgt3__ext749__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext749 :: GPU Core Clocks */
#define acmgt3__ext749__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext749 :: AVG GPU Core Frequency */
#define acmgt3__ext749__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext749 :: AVG GPU Core Frequency */
#define acmgt3__ext749__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext749 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE0 */
#define acmgt3__ext749__thread_dispatch_queue0_active_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext749 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE1 */
#define acmgt3__ext749__thread_dispatch_queue0_active_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext749 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE2 */
#define acmgt3__ext749__thread_dispatch_queue0_active_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext749 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE3 */
#define acmgt3__ext749__thread_dispatch_queue0_active_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext749 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE4 */
#define acmgt3__ext749__thread_dispatch_queue0_active_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext749 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE5 */
#define acmgt3__ext749__thread_dispatch_queue0_active_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext749 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE6 */
#define acmgt3__ext749__thread_dispatch_queue0_active_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext749 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE7 */
#define acmgt3__ext749__thread_dispatch_queue0_active_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext750 :: GPU Time Elapsed */
#define acmgt3__ext750__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext750 :: GPU Core Clocks */
#define acmgt3__ext750__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext750 :: AVG GPU Core Frequency */
#define acmgt3__ext750__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext750 :: AVG GPU Core Frequency */
#define acmgt3__ext750__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext750 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE8 */
#define acmgt3__ext750__thread_dispatch_queue0_active_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext750 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE9 */
#define acmgt3__ext750__thread_dispatch_queue0_active_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext750 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE10 */
#define acmgt3__ext750__thread_dispatch_queue0_active_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext750 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE11 */
#define acmgt3__ext750__thread_dispatch_queue0_active_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext750 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE12 */
#define acmgt3__ext750__thread_dispatch_queue0_active_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext750 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE13 */
#define acmgt3__ext750__thread_dispatch_queue0_active_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext750 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE14 */
#define acmgt3__ext750__thread_dispatch_queue0_active_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext750 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE15 */
#define acmgt3__ext750__thread_dispatch_queue0_active_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext751 :: GPU Time Elapsed */
#define acmgt3__ext751__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext751 :: GPU Core Clocks */
#define acmgt3__ext751__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext751 :: AVG GPU Core Frequency */
#define acmgt3__ext751__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext751 :: AVG GPU Core Frequency */
#define acmgt3__ext751__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext751 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE16 */
#define acmgt3__ext751__thread_dispatch_queue0_active_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext751 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE17 */
#define acmgt3__ext751__thread_dispatch_queue0_active_xecore17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext751 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE18 */
#define acmgt3__ext751__thread_dispatch_queue0_active_xecore18__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext751 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE19 */
#define acmgt3__ext751__thread_dispatch_queue0_active_xecore19__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext751 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE20 */
#define acmgt3__ext751__thread_dispatch_queue0_active_xecore20__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext751 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE21 */
#define acmgt3__ext751__thread_dispatch_queue0_active_xecore21__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext751 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE22 */
#define acmgt3__ext751__thread_dispatch_queue0_active_xecore22__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext751 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE23 */
#define acmgt3__ext751__thread_dispatch_queue0_active_xecore23__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext752 :: GPU Time Elapsed */
#define acmgt3__ext752__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext752 :: GPU Core Clocks */
#define acmgt3__ext752__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext752 :: AVG GPU Core Frequency */
#define acmgt3__ext752__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext752 :: AVG GPU Core Frequency */
#define acmgt3__ext752__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext752 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE24 */
#define acmgt3__ext752__thread_dispatch_queue0_active_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext752 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE25 */
#define acmgt3__ext752__thread_dispatch_queue0_active_xecore25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext752 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE26 */
#define acmgt3__ext752__thread_dispatch_queue0_active_xecore26__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext752 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE27 */
#define acmgt3__ext752__thread_dispatch_queue0_active_xecore27__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext752 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE28 */
#define acmgt3__ext752__thread_dispatch_queue0_active_xecore28__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext752 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE29 */
#define acmgt3__ext752__thread_dispatch_queue0_active_xecore29__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext752 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE30 */
#define acmgt3__ext752__thread_dispatch_queue0_active_xecore30__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext752 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE31 */
#define acmgt3__ext752__thread_dispatch_queue0_active_xecore31__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext753 :: GPU Time Elapsed */
#define acmgt3__ext753__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext753 :: GPU Core Clocks */
#define acmgt3__ext753__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext753 :: AVG GPU Core Frequency */
#define acmgt3__ext753__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext753 :: AVG GPU Core Frequency */
#define acmgt3__ext753__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext753 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE0 */
#define acmgt3__ext753__thread_dispatch_queue1_active_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext753 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE1 */
#define acmgt3__ext753__thread_dispatch_queue1_active_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext753 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE2 */
#define acmgt3__ext753__thread_dispatch_queue1_active_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext753 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE3 */
#define acmgt3__ext753__thread_dispatch_queue1_active_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext753 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE4 */
#define acmgt3__ext753__thread_dispatch_queue1_active_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext753 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE5 */
#define acmgt3__ext753__thread_dispatch_queue1_active_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext753 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE6 */
#define acmgt3__ext753__thread_dispatch_queue1_active_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext753 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE7 */
#define acmgt3__ext753__thread_dispatch_queue1_active_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext753 :: THREAD DISPATCH STALL XECORE0 */
#define acmgt3__ext753__thread_dispatch_stall_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext753 :: THREAD DISPATCH STALL XECORE1 */
#define acmgt3__ext753__thread_dispatch_stall_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext753 :: THREAD DISPATCH STALL XECORE2 */
#define acmgt3__ext753__thread_dispatch_stall_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext753 :: THREAD DISPATCH STALL XECORE3 */
#define acmgt3__ext753__thread_dispatch_stall_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext753 :: THREAD DISPATCH STALL XECORE4 */
#define acmgt3__ext753__thread_dispatch_stall_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext753 :: THREAD DISPATCH STALL XECORE5 */
#define acmgt3__ext753__thread_dispatch_stall_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext753 :: THREAD DISPATCH STALL XECORE6 */
#define acmgt3__ext753__thread_dispatch_stall_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext753 :: THREAD DISPATCH STALL XECORE7 */
#define acmgt3__ext753__thread_dispatch_stall_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext754 :: GPU Time Elapsed */
#define acmgt3__ext754__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext754 :: GPU Core Clocks */
#define acmgt3__ext754__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext754 :: AVG GPU Core Frequency */
#define acmgt3__ext754__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext754 :: AVG GPU Core Frequency */
#define acmgt3__ext754__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext754 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE8 */
#define acmgt3__ext754__thread_dispatch_queue1_active_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext754 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE9 */
#define acmgt3__ext754__thread_dispatch_queue1_active_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext754 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE10 */
#define acmgt3__ext754__thread_dispatch_queue1_active_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext754 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE11 */
#define acmgt3__ext754__thread_dispatch_queue1_active_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext754 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE12 */
#define acmgt3__ext754__thread_dispatch_queue1_active_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext754 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE13 */
#define acmgt3__ext754__thread_dispatch_queue1_active_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext754 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE14 */
#define acmgt3__ext754__thread_dispatch_queue1_active_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext754 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE15 */
#define acmgt3__ext754__thread_dispatch_queue1_active_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext754 :: THREAD DISPATCH STALL XECORE8 */
#define acmgt3__ext754__thread_dispatch_stall_xecore8__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext754 :: THREAD DISPATCH STALL XECORE9 */
#define acmgt3__ext754__thread_dispatch_stall_xecore9__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext754 :: THREAD DISPATCH STALL XECORE10 */
#define acmgt3__ext754__thread_dispatch_stall_xecore10__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext754 :: THREAD DISPATCH STALL XECORE11 */
#define acmgt3__ext754__thread_dispatch_stall_xecore11__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext754 :: THREAD DISPATCH STALL XECORE12 */
#define acmgt3__ext754__thread_dispatch_stall_xecore12__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext754 :: THREAD DISPATCH STALL XECORE13 */
#define acmgt3__ext754__thread_dispatch_stall_xecore13__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext754 :: THREAD DISPATCH STALL XECORE14 */
#define acmgt3__ext754__thread_dispatch_stall_xecore14__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext754 :: THREAD DISPATCH STALL XECORE15 */
#define acmgt3__ext754__thread_dispatch_stall_xecore15__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext755 :: GPU Time Elapsed */
#define acmgt3__ext755__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext755 :: GPU Core Clocks */
#define acmgt3__ext755__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext755 :: AVG GPU Core Frequency */
#define acmgt3__ext755__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext755 :: AVG GPU Core Frequency */
#define acmgt3__ext755__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext755 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE16 */
#define acmgt3__ext755__thread_dispatch_queue1_active_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext755 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE17 */
#define acmgt3__ext755__thread_dispatch_queue1_active_xecore17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext755 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE18 */
#define acmgt3__ext755__thread_dispatch_queue1_active_xecore18__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext755 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE19 */
#define acmgt3__ext755__thread_dispatch_queue1_active_xecore19__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext755 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE20 */
#define acmgt3__ext755__thread_dispatch_queue1_active_xecore20__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext755 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE21 */
#define acmgt3__ext755__thread_dispatch_queue1_active_xecore21__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext755 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE22 */
#define acmgt3__ext755__thread_dispatch_queue1_active_xecore22__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext755 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE23 */
#define acmgt3__ext755__thread_dispatch_queue1_active_xecore23__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext755 :: THREAD DISPATCH STALL XECORE16 */
#define acmgt3__ext755__thread_dispatch_stall_xecore16__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext755 :: THREAD DISPATCH STALL XECORE17 */
#define acmgt3__ext755__thread_dispatch_stall_xecore17__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext755 :: THREAD DISPATCH STALL XECORE18 */
#define acmgt3__ext755__thread_dispatch_stall_xecore18__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext755 :: THREAD DISPATCH STALL XECORE19 */
#define acmgt3__ext755__thread_dispatch_stall_xecore19__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext755 :: THREAD DISPATCH STALL XECORE20 */
#define acmgt3__ext755__thread_dispatch_stall_xecore20__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext755 :: THREAD DISPATCH STALL XECORE21 */
#define acmgt3__ext755__thread_dispatch_stall_xecore21__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext755 :: THREAD DISPATCH STALL XECORE22 */
#define acmgt3__ext755__thread_dispatch_stall_xecore22__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext755 :: THREAD DISPATCH STALL XECORE23 */
#define acmgt3__ext755__thread_dispatch_stall_xecore23__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext756 :: GPU Time Elapsed */
#define acmgt3__ext756__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext756 :: GPU Core Clocks */
#define acmgt3__ext756__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext756 :: AVG GPU Core Frequency */
#define acmgt3__ext756__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext756 :: AVG GPU Core Frequency */
#define acmgt3__ext756__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext756 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE24 */
#define acmgt3__ext756__thread_dispatch_queue1_active_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext756 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE25 */
#define acmgt3__ext756__thread_dispatch_queue1_active_xecore25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext756 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE26 */
#define acmgt3__ext756__thread_dispatch_queue1_active_xecore26__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext756 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE27 */
#define acmgt3__ext756__thread_dispatch_queue1_active_xecore27__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext756 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE28 */
#define acmgt3__ext756__thread_dispatch_queue1_active_xecore28__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext756 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE29 */
#define acmgt3__ext756__thread_dispatch_queue1_active_xecore29__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext756 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE30 */
#define acmgt3__ext756__thread_dispatch_queue1_active_xecore30__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext756 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE31 */
#define acmgt3__ext756__thread_dispatch_queue1_active_xecore31__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext756 :: THREAD DISPATCH STALL XECORE24 */
#define acmgt3__ext756__thread_dispatch_stall_xecore24__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext756 :: THREAD DISPATCH STALL XECORE25 */
#define acmgt3__ext756__thread_dispatch_stall_xecore25__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext756 :: THREAD DISPATCH STALL XECORE26 */
#define acmgt3__ext756__thread_dispatch_stall_xecore26__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext756 :: THREAD DISPATCH STALL XECORE27 */
#define acmgt3__ext756__thread_dispatch_stall_xecore27__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext756 :: THREAD DISPATCH STALL XECORE28 */
#define acmgt3__ext756__thread_dispatch_stall_xecore28__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext756 :: THREAD DISPATCH STALL XECORE29 */
#define acmgt3__ext756__thread_dispatch_stall_xecore29__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext756 :: THREAD DISPATCH STALL XECORE30 */
#define acmgt3__ext756__thread_dispatch_stall_xecore30__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext756 :: THREAD DISPATCH STALL XECORE31 */
#define acmgt3__ext756__thread_dispatch_stall_xecore31__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext757 :: GPU Time Elapsed */
#define acmgt3__ext757__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext757 :: GPU Core Clocks */
#define acmgt3__ext757__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext757 :: AVG GPU Core Frequency */
#define acmgt3__ext757__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext757 :: AVG GPU Core Frequency */
#define acmgt3__ext757__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE0 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE1 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE2 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE3 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE4 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE5 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE6 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE7 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE8 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore8__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE9 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore9__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE10 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore10__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE11 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore11__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE12 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore12__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE13 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore13__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE14 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore14__read \
   bdw__render_basic__sampler1_busy__read

/* Ext757 :: THREAD DISPATCH INPUT AVAILABLE XECORE15 */
#define acmgt3__ext757__thread_dispatch_input_available_xecore15__read \
   bdw__render_basic__sampler0_busy__read

/* Ext758 :: GPU Time Elapsed */
#define acmgt3__ext758__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext758 :: GPU Core Clocks */
#define acmgt3__ext758__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext758 :: AVG GPU Core Frequency */
#define acmgt3__ext758__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext758 :: AVG GPU Core Frequency */
#define acmgt3__ext758__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE16 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore16__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE17 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore17__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE18 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore18__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE19 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore19__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE20 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore20__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE21 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore21__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE22 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore22__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE23 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore23__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE24 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore24__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE25 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore25__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE26 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore26__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE27 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore27__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE28 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore28__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE29 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore29__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE30 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore30__read \
   bdw__render_basic__sampler1_busy__read

/* Ext758 :: THREAD DISPATCH INPUT AVAILABLE XECORE31 */
#define acmgt3__ext758__thread_dispatch_input_available_xecore31__read \
   bdw__render_basic__sampler0_busy__read

/* Ext759 :: GPU Time Elapsed */
#define acmgt3__ext759__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext759 :: GPU Core Clocks */
#define acmgt3__ext759__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext759 :: AVG GPU Core Frequency */
#define acmgt3__ext759__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext759 :: AVG GPU Core Frequency */
#define acmgt3__ext759__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext759 :: THREAD DISPATCH PS ACTIVE XECORE0 */
#define acmgt3__ext759__thread_dispatch_ps_active_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext759 :: THREAD DISPATCH PS ACTIVE XECORE1 */
#define acmgt3__ext759__thread_dispatch_ps_active_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext759 :: THREAD DISPATCH PS ACTIVE XECORE2 */
#define acmgt3__ext759__thread_dispatch_ps_active_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext759 :: THREAD DISPATCH PS ACTIVE XECORE3 */
#define acmgt3__ext759__thread_dispatch_ps_active_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext759 :: THREAD DISPATCH PS ACTIVE XECORE4 */
#define acmgt3__ext759__thread_dispatch_ps_active_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext759 :: THREAD DISPATCH PS ACTIVE XECORE5 */
#define acmgt3__ext759__thread_dispatch_ps_active_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext759 :: THREAD DISPATCH PS ACTIVE XECORE6 */
#define acmgt3__ext759__thread_dispatch_ps_active_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext759 :: THREAD DISPATCH PS ACTIVE XECORE7 */
#define acmgt3__ext759__thread_dispatch_ps_active_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext760 :: GPU Time Elapsed */
#define acmgt3__ext760__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext760 :: GPU Core Clocks */
#define acmgt3__ext760__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext760 :: AVG GPU Core Frequency */
#define acmgt3__ext760__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext760 :: AVG GPU Core Frequency */
#define acmgt3__ext760__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext760 :: THREAD DISPATCH PS ACTIVE XECORE8 */
#define acmgt3__ext760__thread_dispatch_ps_active_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext760 :: THREAD DISPATCH PS ACTIVE XECORE9 */
#define acmgt3__ext760__thread_dispatch_ps_active_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext760 :: THREAD DISPATCH PS ACTIVE XECORE10 */
#define acmgt3__ext760__thread_dispatch_ps_active_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext760 :: THREAD DISPATCH PS ACTIVE XECORE11 */
#define acmgt3__ext760__thread_dispatch_ps_active_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext760 :: THREAD DISPATCH PS ACTIVE XECORE12 */
#define acmgt3__ext760__thread_dispatch_ps_active_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext760 :: THREAD DISPATCH PS ACTIVE XECORE13 */
#define acmgt3__ext760__thread_dispatch_ps_active_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext760 :: THREAD DISPATCH PS ACTIVE XECORE14 */
#define acmgt3__ext760__thread_dispatch_ps_active_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext760 :: THREAD DISPATCH PS ACTIVE XECORE15 */
#define acmgt3__ext760__thread_dispatch_ps_active_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext761 :: GPU Time Elapsed */
#define acmgt3__ext761__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext761 :: GPU Core Clocks */
#define acmgt3__ext761__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext761 :: AVG GPU Core Frequency */
#define acmgt3__ext761__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext761 :: AVG GPU Core Frequency */
#define acmgt3__ext761__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext761 :: THREAD DISPATCH PS ACTIVE XECORE16 */
#define acmgt3__ext761__thread_dispatch_ps_active_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext761 :: THREAD DISPATCH PS ACTIVE XECORE17 */
#define acmgt3__ext761__thread_dispatch_ps_active_xecore17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext761 :: THREAD DISPATCH PS ACTIVE XECORE18 */
#define acmgt3__ext761__thread_dispatch_ps_active_xecore18__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext761 :: THREAD DISPATCH PS ACTIVE XECORE19 */
#define acmgt3__ext761__thread_dispatch_ps_active_xecore19__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext761 :: THREAD DISPATCH PS ACTIVE XECORE20 */
#define acmgt3__ext761__thread_dispatch_ps_active_xecore20__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext761 :: THREAD DISPATCH PS ACTIVE XECORE21 */
#define acmgt3__ext761__thread_dispatch_ps_active_xecore21__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext761 :: THREAD DISPATCH PS ACTIVE XECORE22 */
#define acmgt3__ext761__thread_dispatch_ps_active_xecore22__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext761 :: THREAD DISPATCH PS ACTIVE XECORE23 */
#define acmgt3__ext761__thread_dispatch_ps_active_xecore23__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext762 :: GPU Time Elapsed */
#define acmgt3__ext762__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext762 :: GPU Core Clocks */
#define acmgt3__ext762__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext762 :: AVG GPU Core Frequency */
#define acmgt3__ext762__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext762 :: AVG GPU Core Frequency */
#define acmgt3__ext762__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext762 :: THREAD DISPATCH PS ACTIVE XECORE24 */
#define acmgt3__ext762__thread_dispatch_ps_active_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext762 :: THREAD DISPATCH PS ACTIVE XECORE25 */
#define acmgt3__ext762__thread_dispatch_ps_active_xecore25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext762 :: THREAD DISPATCH PS ACTIVE XECORE26 */
#define acmgt3__ext762__thread_dispatch_ps_active_xecore26__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext762 :: THREAD DISPATCH PS ACTIVE XECORE27 */
#define acmgt3__ext762__thread_dispatch_ps_active_xecore27__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext762 :: THREAD DISPATCH PS ACTIVE XECORE28 */
#define acmgt3__ext762__thread_dispatch_ps_active_xecore28__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext762 :: THREAD DISPATCH PS ACTIVE XECORE29 */
#define acmgt3__ext762__thread_dispatch_ps_active_xecore29__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext762 :: THREAD DISPATCH PS ACTIVE XECORE30 */
#define acmgt3__ext762__thread_dispatch_ps_active_xecore30__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext762 :: THREAD DISPATCH PS ACTIVE XECORE31 */
#define acmgt3__ext762__thread_dispatch_ps_active_xecore31__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext763 :: GPU Time Elapsed */
#define acmgt3__ext763__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext763 :: GPU Core Clocks */
#define acmgt3__ext763__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext763 :: AVG GPU Core Frequency */
#define acmgt3__ext763__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext763 :: AVG GPU Core Frequency */
#define acmgt3__ext763__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext763 :: HOST TO GPUMEM TRANSACTION READ */
#define acmgt3__ext763__host_to_gpumem_transaction_read__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext763 :: HOST TO GPUMEM TRANSACTION WRITE */
#define acmgt3__ext763__host_to_gpumem_transaction_write__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext764 :: GPU Time Elapsed */
#define acmgt3__ext764__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext764 :: GPU Core Clocks */
#define acmgt3__ext764__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext764 :: AVG GPU Core Frequency */
#define acmgt3__ext764__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext764 :: AVG GPU Core Frequency */
#define acmgt3__ext764__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext764 :: SYSMEM TRANSACTION READ */
#define acmgt3__ext764__sysmem_transaction_read__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext764 :: SYSMEM TRANSACTION WRITE */
#define acmgt3__ext764__sysmem_transaction_write__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext765 :: GPU Time Elapsed */
#define acmgt3__ext765__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext765 :: GPU Core Clocks */
#define acmgt3__ext765__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext765 :: AVG GPU Core Frequency */
#define acmgt3__ext765__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext765 :: AVG GPU Core Frequency */
#define acmgt3__ext765__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext765 :: GPGPU DISPATCH XECORE0 */
#define acmgt3__ext765__gpgpu_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext765 :: GPGPU DISPATCH XECORE1 */
#define acmgt3__ext765__gpgpu_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext765 :: GPGPU DISPATCH XECORE2 */
#define acmgt3__ext765__gpgpu_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext766 :: GPU Time Elapsed */
#define acmgt3__ext766__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext766 :: GPU Core Clocks */
#define acmgt3__ext766__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext766 :: AVG GPU Core Frequency */
#define acmgt3__ext766__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext766 :: AVG GPU Core Frequency */
#define acmgt3__ext766__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext766 :: GPGPU DISPATCH XECORE3 */
#define acmgt3__ext766__gpgpu_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext766 :: GPGPU DISPATCH XECORE4 */
#define acmgt3__ext766__gpgpu_dispatch_xecore4__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext766 :: GPGPU DISPATCH XECORE5 */
#define acmgt3__ext766__gpgpu_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext767 :: GPU Time Elapsed */
#define acmgt3__ext767__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext767 :: GPU Core Clocks */
#define acmgt3__ext767__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext767 :: AVG GPU Core Frequency */
#define acmgt3__ext767__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext767 :: AVG GPU Core Frequency */
#define acmgt3__ext767__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext767 :: GPGPU DISPATCH XECORE6 */
#define acmgt3__ext767__gpgpu_dispatch_xecore6__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext767 :: GPGPU DISPATCH XECORE7 */
#define acmgt3__ext767__gpgpu_dispatch_xecore7__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext767 :: GPGPU DISPATCH XECORE8 */
#define acmgt3__ext767__gpgpu_dispatch_xecore8__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext768 :: GPU Time Elapsed */
#define acmgt3__ext768__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext768 :: GPU Core Clocks */
#define acmgt3__ext768__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext768 :: AVG GPU Core Frequency */
#define acmgt3__ext768__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext768 :: AVG GPU Core Frequency */
#define acmgt3__ext768__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext768 :: GPGPU DISPATCH XECORE9 */
#define acmgt3__ext768__gpgpu_dispatch_xecore9__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext768 :: GPGPU DISPATCH XECORE10 */
#define acmgt3__ext768__gpgpu_dispatch_xecore10__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext768 :: GPGPU DISPATCH XECORE11 */
#define acmgt3__ext768__gpgpu_dispatch_xecore11__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext769 :: GPU Time Elapsed */
#define acmgt3__ext769__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext769 :: GPU Core Clocks */
#define acmgt3__ext769__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext769 :: AVG GPU Core Frequency */
#define acmgt3__ext769__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext769 :: AVG GPU Core Frequency */
#define acmgt3__ext769__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext769 :: GPGPU DISPATCH XECORE12 */
#define acmgt3__ext769__gpgpu_dispatch_xecore12__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext769 :: GPGPU DISPATCH XECORE13 */
#define acmgt3__ext769__gpgpu_dispatch_xecore13__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext769 :: GPGPU DISPATCH XECORE14 */
#define acmgt3__ext769__gpgpu_dispatch_xecore14__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext770 :: GPU Time Elapsed */
#define acmgt3__ext770__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext770 :: GPU Core Clocks */
#define acmgt3__ext770__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext770 :: AVG GPU Core Frequency */
#define acmgt3__ext770__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext770 :: AVG GPU Core Frequency */
#define acmgt3__ext770__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext770 :: GPGPU DISPATCH XECORE15 */
#define acmgt3__ext770__gpgpu_dispatch_xecore15__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext770 :: GPGPU DISPATCH XECORE16 */
#define acmgt3__ext770__gpgpu_dispatch_xecore16__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext770 :: GPGPU DISPATCH XECORE17 */
#define acmgt3__ext770__gpgpu_dispatch_xecore17__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext771 :: GPU Time Elapsed */
#define acmgt3__ext771__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext771 :: GPU Core Clocks */
#define acmgt3__ext771__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext771 :: AVG GPU Core Frequency */
#define acmgt3__ext771__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext771 :: AVG GPU Core Frequency */
#define acmgt3__ext771__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext771 :: GPGPU DISPATCH XECORE18 */
#define acmgt3__ext771__gpgpu_dispatch_xecore18__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext771 :: GPGPU DISPATCH XECORE19 */
#define acmgt3__ext771__gpgpu_dispatch_xecore19__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext771 :: GPGPU DISPATCH XECORE20 */
#define acmgt3__ext771__gpgpu_dispatch_xecore20__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext772 :: GPU Time Elapsed */
#define acmgt3__ext772__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext772 :: GPU Core Clocks */
#define acmgt3__ext772__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext772 :: AVG GPU Core Frequency */
#define acmgt3__ext772__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext772 :: AVG GPU Core Frequency */
#define acmgt3__ext772__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext772 :: GPGPU DISPATCH XECORE21 */
#define acmgt3__ext772__gpgpu_dispatch_xecore21__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext772 :: GPGPU DISPATCH XECORE22 */
#define acmgt3__ext772__gpgpu_dispatch_xecore22__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext772 :: GPGPU DISPATCH XECORE23 */
#define acmgt3__ext772__gpgpu_dispatch_xecore23__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext773 :: GPU Time Elapsed */
#define acmgt3__ext773__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext773 :: GPU Core Clocks */
#define acmgt3__ext773__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext773 :: AVG GPU Core Frequency */
#define acmgt3__ext773__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext773 :: AVG GPU Core Frequency */
#define acmgt3__ext773__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext773 :: GPGPU DISPATCH XECORE24 */
#define acmgt3__ext773__gpgpu_dispatch_xecore24__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext773 :: GPGPU DISPATCH XECORE25 */
#define acmgt3__ext773__gpgpu_dispatch_xecore25__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext773 :: GPGPU DISPATCH XECORE26 */
#define acmgt3__ext773__gpgpu_dispatch_xecore26__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext774 :: GPU Time Elapsed */
#define acmgt3__ext774__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext774 :: GPU Core Clocks */
#define acmgt3__ext774__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext774 :: AVG GPU Core Frequency */
#define acmgt3__ext774__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext774 :: AVG GPU Core Frequency */
#define acmgt3__ext774__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext774 :: GPGPU DISPATCH XECORE27 */
#define acmgt3__ext774__gpgpu_dispatch_xecore27__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext774 :: GPGPU DISPATCH XECORE28 */
#define acmgt3__ext774__gpgpu_dispatch_xecore28__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext774 :: GPGPU DISPATCH XECORE29 */
#define acmgt3__ext774__gpgpu_dispatch_xecore29__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext775 :: GPU Time Elapsed */
#define acmgt3__ext775__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext775 :: GPU Core Clocks */
#define acmgt3__ext775__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext775 :: AVG GPU Core Frequency */
#define acmgt3__ext775__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext775 :: AVG GPU Core Frequency */
#define acmgt3__ext775__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext775 :: GPGPU DISPATCH XECORE30 */
#define acmgt3__ext775__gpgpu_dispatch_xecore30__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext775 :: GPGPU DISPATCH XECORE31 */
#define acmgt3__ext775__gpgpu_dispatch_xecore31__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext776 :: GPU Time Elapsed */
#define acmgt3__ext776__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext776 :: GPU Core Clocks */
#define acmgt3__ext776__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext776 :: AVG GPU Core Frequency */
#define acmgt3__ext776__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext776 :: AVG GPU Core Frequency */
#define acmgt3__ext776__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext776 :: XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0 */
#define acmgt3__ext776__xve_multiple_pipe_active_xecore0_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext776 :: XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0 */
#define acmgt3__ext776__xve_multiple_pipe_active_xecore1_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext776 :: XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0 */
#define acmgt3__ext776__xve_multiple_pipe_active_xecore2_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext776 :: XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0 */
#define acmgt3__ext776__xve_multiple_pipe_active_xecore3_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext777 :: GPU Time Elapsed */
#define acmgt3__ext777__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext777 :: GPU Core Clocks */
#define acmgt3__ext777__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext777 :: AVG GPU Core Frequency */
#define acmgt3__ext777__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext777 :: AVG GPU Core Frequency */
#define acmgt3__ext777__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext777 :: XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0 */
#define acmgt3__ext777__xve_multiple_pipe_active_xecore4_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext777 :: XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0 */
#define acmgt3__ext777__xve_multiple_pipe_active_xecore5_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext777 :: XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0 */
#define acmgt3__ext777__xve_multiple_pipe_active_xecore6_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext777 :: XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0 */
#define acmgt3__ext777__xve_multiple_pipe_active_xecore7_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext778 :: GPU Time Elapsed */
#define acmgt3__ext778__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext778 :: GPU Core Clocks */
#define acmgt3__ext778__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext778 :: AVG GPU Core Frequency */
#define acmgt3__ext778__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext778 :: AVG GPU Core Frequency */
#define acmgt3__ext778__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext778 :: XVE MULTIPLE PIPE ACTIVE XECORE8 XVE0 */
#define acmgt3__ext778__xve_multiple_pipe_active_xecore8_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext778 :: XVE MULTIPLE PIPE ACTIVE XECORE9 XVE0 */
#define acmgt3__ext778__xve_multiple_pipe_active_xecore9_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext778 :: XVE MULTIPLE PIPE ACTIVE XECORE10 XVE0 */
#define acmgt3__ext778__xve_multiple_pipe_active_xecore10_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext778 :: XVE MULTIPLE PIPE ACTIVE XECORE11 XVE0 */
#define acmgt3__ext778__xve_multiple_pipe_active_xecore11_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext779 :: GPU Time Elapsed */
#define acmgt3__ext779__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext779 :: GPU Core Clocks */
#define acmgt3__ext779__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext779 :: AVG GPU Core Frequency */
#define acmgt3__ext779__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext779 :: AVG GPU Core Frequency */
#define acmgt3__ext779__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext779 :: XVE MULTIPLE PIPE ACTIVE XECORE12 XVE0 */
#define acmgt3__ext779__xve_multiple_pipe_active_xecore12_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext779 :: XVE MULTIPLE PIPE ACTIVE XECORE13 XVE0 */
#define acmgt3__ext779__xve_multiple_pipe_active_xecore13_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext779 :: XVE MULTIPLE PIPE ACTIVE XECORE14 XVE0 */
#define acmgt3__ext779__xve_multiple_pipe_active_xecore14_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext779 :: XVE MULTIPLE PIPE ACTIVE XECORE15 XVE0 */
#define acmgt3__ext779__xve_multiple_pipe_active_xecore15_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext780 :: GPU Time Elapsed */
#define acmgt3__ext780__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext780 :: GPU Core Clocks */
#define acmgt3__ext780__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext780 :: AVG GPU Core Frequency */
#define acmgt3__ext780__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext780 :: AVG GPU Core Frequency */
#define acmgt3__ext780__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext780 :: XVE MULTIPLE PIPE ACTIVE XECORE16 XVE0 */
#define acmgt3__ext780__xve_multiple_pipe_active_xecore16_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext780 :: XVE MULTIPLE PIPE ACTIVE XECORE17 XVE0 */
#define acmgt3__ext780__xve_multiple_pipe_active_xecore17_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext780 :: XVE MULTIPLE PIPE ACTIVE XECORE18 XVE0 */
#define acmgt3__ext780__xve_multiple_pipe_active_xecore18_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext780 :: XVE MULTIPLE PIPE ACTIVE XECORE19 XVE0 */
#define acmgt3__ext780__xve_multiple_pipe_active_xecore19_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext781 :: GPU Time Elapsed */
#define acmgt3__ext781__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext781 :: GPU Core Clocks */
#define acmgt3__ext781__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext781 :: AVG GPU Core Frequency */
#define acmgt3__ext781__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext781 :: AVG GPU Core Frequency */
#define acmgt3__ext781__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext781 :: XVE MULTIPLE PIPE ACTIVE XECORE20 XVE0 */
#define acmgt3__ext781__xve_multiple_pipe_active_xecore20_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext781 :: XVE MULTIPLE PIPE ACTIVE XECORE21 XVE0 */
#define acmgt3__ext781__xve_multiple_pipe_active_xecore21_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext781 :: XVE MULTIPLE PIPE ACTIVE XECORE22 XVE0 */
#define acmgt3__ext781__xve_multiple_pipe_active_xecore22_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext781 :: XVE MULTIPLE PIPE ACTIVE XECORE23 XVE0 */
#define acmgt3__ext781__xve_multiple_pipe_active_xecore23_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext782 :: GPU Time Elapsed */
#define acmgt3__ext782__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext782 :: GPU Core Clocks */
#define acmgt3__ext782__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext782 :: AVG GPU Core Frequency */
#define acmgt3__ext782__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext782 :: AVG GPU Core Frequency */
#define acmgt3__ext782__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext782 :: XVE MULTIPLE PIPE ACTIVE XECORE24 XVE0 */
#define acmgt3__ext782__xve_multiple_pipe_active_xecore24_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext782 :: XVE MULTIPLE PIPE ACTIVE XECORE25 XVE0 */
#define acmgt3__ext782__xve_multiple_pipe_active_xecore25_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext782 :: XVE MULTIPLE PIPE ACTIVE XECORE26 XVE0 */
#define acmgt3__ext782__xve_multiple_pipe_active_xecore26_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext782 :: XVE MULTIPLE PIPE ACTIVE XECORE27 XVE0 */
#define acmgt3__ext782__xve_multiple_pipe_active_xecore27_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext783 :: GPU Time Elapsed */
#define acmgt3__ext783__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext783 :: GPU Core Clocks */
#define acmgt3__ext783__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext783 :: AVG GPU Core Frequency */
#define acmgt3__ext783__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext783 :: AVG GPU Core Frequency */
#define acmgt3__ext783__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext783 :: XVE MULTIPLE PIPE ACTIVE XECORE28 XVE0 */
#define acmgt3__ext783__xve_multiple_pipe_active_xecore28_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext783 :: XVE MULTIPLE PIPE ACTIVE XECORE29 XVE0 */
#define acmgt3__ext783__xve_multiple_pipe_active_xecore29_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext783 :: XVE MULTIPLE PIPE ACTIVE XECORE30 XVE0 */
#define acmgt3__ext783__xve_multiple_pipe_active_xecore30_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext783 :: XVE MULTIPLE PIPE ACTIVE XECORE31 XVE0 */
#define acmgt3__ext783__xve_multiple_pipe_active_xecore31_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext784 :: GPU Time Elapsed */
#define acmgt3__ext784__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext784 :: GPU Core Clocks */
#define acmgt3__ext784__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext784 :: AVG GPU Core Frequency */
#define acmgt3__ext784__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext784 :: AVG GPU Core Frequency */
#define acmgt3__ext784__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext784 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0 */
#define acmgt3__ext784__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext785 :: GPU Time Elapsed */
#define acmgt3__ext785__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext785 :: GPU Core Clocks */
#define acmgt3__ext785__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext785 :: AVG GPU Core Frequency */
#define acmgt3__ext785__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext785 :: AVG GPU Core Frequency */
#define acmgt3__ext785__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext785 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1 */
#define acmgt3__ext785__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext786 :: GPU Time Elapsed */
#define acmgt3__ext786__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext786 :: GPU Core Clocks */
#define acmgt3__ext786__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext786 :: AVG GPU Core Frequency */
#define acmgt3__ext786__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext786 :: AVG GPU Core Frequency */
#define acmgt3__ext786__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext786 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE2 */
#define acmgt3__ext786__pixel_2x2_lit_post_rasterizer_early_depth_slice2__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext787 :: GPU Time Elapsed */
#define acmgt3__ext787__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext787 :: GPU Core Clocks */
#define acmgt3__ext787__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext787 :: AVG GPU Core Frequency */
#define acmgt3__ext787__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext787 :: AVG GPU Core Frequency */
#define acmgt3__ext787__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext787 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE3 */
#define acmgt3__ext787__pixel_2x2_lit_post_rasterizer_early_depth_slice3__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext788 :: GPU Time Elapsed */
#define acmgt3__ext788__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext788 :: GPU Core Clocks */
#define acmgt3__ext788__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext788 :: AVG GPU Core Frequency */
#define acmgt3__ext788__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext788 :: AVG GPU Core Frequency */
#define acmgt3__ext788__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext788 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE4 */
#define acmgt3__ext788__pixel_2x2_lit_post_rasterizer_early_depth_slice4__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext789 :: GPU Time Elapsed */
#define acmgt3__ext789__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext789 :: GPU Core Clocks */
#define acmgt3__ext789__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext789 :: AVG GPU Core Frequency */
#define acmgt3__ext789__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext789 :: AVG GPU Core Frequency */
#define acmgt3__ext789__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext789 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE5 */
#define acmgt3__ext789__pixel_2x2_lit_post_rasterizer_early_depth_slice5__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext790 :: GPU Time Elapsed */
#define acmgt3__ext790__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext790 :: GPU Core Clocks */
#define acmgt3__ext790__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext790 :: AVG GPU Core Frequency */
#define acmgt3__ext790__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext790 :: AVG GPU Core Frequency */
#define acmgt3__ext790__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext790 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE6 */
#define acmgt3__ext790__pixel_2x2_lit_post_rasterizer_early_depth_slice6__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext791 :: GPU Time Elapsed */
#define acmgt3__ext791__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext791 :: GPU Core Clocks */
#define acmgt3__ext791__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext791 :: AVG GPU Core Frequency */
#define acmgt3__ext791__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext791 :: AVG GPU Core Frequency */
#define acmgt3__ext791__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext791 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE7 */
#define acmgt3__ext791__pixel_2x2_lit_post_rasterizer_early_depth_slice7__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext792 :: GPU Time Elapsed */
#define acmgt3__ext792__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext792 :: GPU Core Clocks */
#define acmgt3__ext792__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext792 :: AVG GPU Core Frequency */
#define acmgt3__ext792__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext792 :: AVG GPU Core Frequency */
#define acmgt3__ext792__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext792 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0 */
#define acmgt3__ext792__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext793 :: GPU Time Elapsed */
#define acmgt3__ext793__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext793 :: GPU Core Clocks */
#define acmgt3__ext793__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext793 :: AVG GPU Core Frequency */
#define acmgt3__ext793__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext793 :: AVG GPU Core Frequency */
#define acmgt3__ext793__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext793 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1 */
#define acmgt3__ext793__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext794 :: GPU Time Elapsed */
#define acmgt3__ext794__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext794 :: GPU Core Clocks */
#define acmgt3__ext794__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext794 :: AVG GPU Core Frequency */
#define acmgt3__ext794__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext794 :: AVG GPU Core Frequency */
#define acmgt3__ext794__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext794 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE2 */
#define acmgt3__ext794__pixel_2x2_lit_post_rasterizer_late_depth_slice2__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext795 :: GPU Time Elapsed */
#define acmgt3__ext795__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext795 :: GPU Core Clocks */
#define acmgt3__ext795__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext795 :: AVG GPU Core Frequency */
#define acmgt3__ext795__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext795 :: AVG GPU Core Frequency */
#define acmgt3__ext795__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext795 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE3 */
#define acmgt3__ext795__pixel_2x2_lit_post_rasterizer_late_depth_slice3__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext796 :: GPU Time Elapsed */
#define acmgt3__ext796__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext796 :: GPU Core Clocks */
#define acmgt3__ext796__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext796 :: AVG GPU Core Frequency */
#define acmgt3__ext796__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext796 :: AVG GPU Core Frequency */
#define acmgt3__ext796__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext796 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE4 */
#define acmgt3__ext796__pixel_2x2_lit_post_rasterizer_late_depth_slice4__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext797 :: GPU Time Elapsed */
#define acmgt3__ext797__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext797 :: GPU Core Clocks */
#define acmgt3__ext797__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext797 :: AVG GPU Core Frequency */
#define acmgt3__ext797__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext797 :: AVG GPU Core Frequency */
#define acmgt3__ext797__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext797 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE5 */
#define acmgt3__ext797__pixel_2x2_lit_post_rasterizer_late_depth_slice5__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext798 :: GPU Time Elapsed */
#define acmgt3__ext798__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext798 :: GPU Core Clocks */
#define acmgt3__ext798__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext798 :: AVG GPU Core Frequency */
#define acmgt3__ext798__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext798 :: AVG GPU Core Frequency */
#define acmgt3__ext798__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext798 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE6 */
#define acmgt3__ext798__pixel_2x2_lit_post_rasterizer_late_depth_slice6__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext799 :: GPU Time Elapsed */
#define acmgt3__ext799__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext799 :: GPU Core Clocks */
#define acmgt3__ext799__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext799 :: AVG GPU Core Frequency */
#define acmgt3__ext799__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext799 :: AVG GPU Core Frequency */
#define acmgt3__ext799__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext799 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE7 */
#define acmgt3__ext799__pixel_2x2_lit_post_rasterizer_late_depth_slice7__read \
   acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext800 :: GPU Time Elapsed */
#define acmgt3__ext800__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext800 :: GPU Core Clocks */
#define acmgt3__ext800__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext800 :: AVG GPU Core Frequency */
#define acmgt3__ext800__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext800 :: AVG GPU Core Frequency */
#define acmgt3__ext800__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext800 :: RT INSTANCE NODE RAY COUNT XECORE0 */
#define acmgt3__ext800__rt_instance_node_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext800 :: RT INTERNAL NODE RAY COUNT XECORE0 */
#define acmgt3__ext800__rt_internal_node_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext800 :: RT TRAVERSAL STEP RAY COUNT XECORE0 */
#define acmgt3__ext800__rt_traversal_step_ray_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext801 :: GPU Time Elapsed */
#define acmgt3__ext801__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext801 :: GPU Core Clocks */
#define acmgt3__ext801__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext801 :: AVG GPU Core Frequency */
#define acmgt3__ext801__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext801 :: AVG GPU Core Frequency */
#define acmgt3__ext801__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext801 :: RT INSTANCE NODE RAY COUNT XECORE1 */
#define acmgt3__ext801__rt_instance_node_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext801 :: RT INTERNAL NODE RAY COUNT XECORE1 */
#define acmgt3__ext801__rt_internal_node_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext801 :: RT TRAVERSAL STEP RAY COUNT XECORE1 */
#define acmgt3__ext801__rt_traversal_step_ray_count_xecore1__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext802 :: GPU Time Elapsed */
#define acmgt3__ext802__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext802 :: GPU Core Clocks */
#define acmgt3__ext802__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext802 :: AVG GPU Core Frequency */
#define acmgt3__ext802__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext802 :: AVG GPU Core Frequency */
#define acmgt3__ext802__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext802 :: RT INSTANCE NODE RAY COUNT XECORE2 */
#define acmgt3__ext802__rt_instance_node_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext802 :: RT INTERNAL NODE RAY COUNT XECORE2 */
#define acmgt3__ext802__rt_internal_node_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext802 :: RT TRAVERSAL STEP RAY COUNT XECORE2 */
#define acmgt3__ext802__rt_traversal_step_ray_count_xecore2__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext803 :: GPU Time Elapsed */
#define acmgt3__ext803__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext803 :: GPU Core Clocks */
#define acmgt3__ext803__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext803 :: AVG GPU Core Frequency */
#define acmgt3__ext803__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext803 :: AVG GPU Core Frequency */
#define acmgt3__ext803__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext803 :: RT INSTANCE NODE RAY COUNT XECORE3 */
#define acmgt3__ext803__rt_instance_node_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext803 :: RT INTERNAL NODE RAY COUNT XECORE3 */
#define acmgt3__ext803__rt_internal_node_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext803 :: RT TRAVERSAL STEP RAY COUNT XECORE3 */
#define acmgt3__ext803__rt_traversal_step_ray_count_xecore3__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext804 :: GPU Time Elapsed */
#define acmgt3__ext804__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext804 :: GPU Core Clocks */
#define acmgt3__ext804__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext804 :: AVG GPU Core Frequency */
#define acmgt3__ext804__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext804 :: AVG GPU Core Frequency */
#define acmgt3__ext804__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext804 :: RT INSTANCE NODE RAY COUNT XECORE4 */
#define acmgt3__ext804__rt_instance_node_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext804 :: RT INTERNAL NODE RAY COUNT XECORE4 */
#define acmgt3__ext804__rt_internal_node_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext804 :: RT TRAVERSAL STEP RAY COUNT XECORE4 */
#define acmgt3__ext804__rt_traversal_step_ray_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext805 :: GPU Time Elapsed */
#define acmgt3__ext805__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext805 :: GPU Core Clocks */
#define acmgt3__ext805__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext805 :: AVG GPU Core Frequency */
#define acmgt3__ext805__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext805 :: AVG GPU Core Frequency */
#define acmgt3__ext805__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext805 :: RT INSTANCE NODE RAY COUNT XECORE5 */
#define acmgt3__ext805__rt_instance_node_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext805 :: RT INTERNAL NODE RAY COUNT XECORE5 */
#define acmgt3__ext805__rt_internal_node_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext805 :: RT TRAVERSAL STEP RAY COUNT XECORE5 */
#define acmgt3__ext805__rt_traversal_step_ray_count_xecore5__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext806 :: GPU Time Elapsed */
#define acmgt3__ext806__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext806 :: GPU Core Clocks */
#define acmgt3__ext806__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext806 :: AVG GPU Core Frequency */
#define acmgt3__ext806__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext806 :: AVG GPU Core Frequency */
#define acmgt3__ext806__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext806 :: RT INSTANCE NODE RAY COUNT XECORE6 */
#define acmgt3__ext806__rt_instance_node_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext806 :: RT INTERNAL NODE RAY COUNT XECORE6 */
#define acmgt3__ext806__rt_internal_node_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext806 :: RT TRAVERSAL STEP RAY COUNT XECORE6 */
#define acmgt3__ext806__rt_traversal_step_ray_count_xecore6__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext807 :: GPU Time Elapsed */
#define acmgt3__ext807__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext807 :: GPU Core Clocks */
#define acmgt3__ext807__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext807 :: AVG GPU Core Frequency */
#define acmgt3__ext807__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext807 :: AVG GPU Core Frequency */
#define acmgt3__ext807__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext807 :: RT INSTANCE NODE RAY COUNT XECORE7 */
#define acmgt3__ext807__rt_instance_node_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext807 :: RT INTERNAL NODE RAY COUNT XECORE7 */
#define acmgt3__ext807__rt_internal_node_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext807 :: RT TRAVERSAL STEP RAY COUNT XECORE7 */
#define acmgt3__ext807__rt_traversal_step_ray_count_xecore7__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext808 :: GPU Time Elapsed */
#define acmgt3__ext808__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext808 :: GPU Core Clocks */
#define acmgt3__ext808__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext808 :: AVG GPU Core Frequency */
#define acmgt3__ext808__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext808 :: AVG GPU Core Frequency */
#define acmgt3__ext808__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext808 :: RT INSTANCE NODE RAY COUNT XECORE8 */
#define acmgt3__ext808__rt_instance_node_ray_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext808 :: RT INTERNAL NODE RAY COUNT XECORE8 */
#define acmgt3__ext808__rt_internal_node_ray_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext808 :: RT TRAVERSAL STEP RAY COUNT XECORE8 */
#define acmgt3__ext808__rt_traversal_step_ray_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext809 :: GPU Time Elapsed */
#define acmgt3__ext809__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext809 :: GPU Core Clocks */
#define acmgt3__ext809__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext809 :: AVG GPU Core Frequency */
#define acmgt3__ext809__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext809 :: AVG GPU Core Frequency */
#define acmgt3__ext809__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext809 :: RT INSTANCE NODE RAY COUNT XECORE9 */
#define acmgt3__ext809__rt_instance_node_ray_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext809 :: RT INTERNAL NODE RAY COUNT XECORE9 */
#define acmgt3__ext809__rt_internal_node_ray_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext809 :: RT TRAVERSAL STEP RAY COUNT XECORE9 */
#define acmgt3__ext809__rt_traversal_step_ray_count_xecore9__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext810 :: GPU Time Elapsed */
#define acmgt3__ext810__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext810 :: GPU Core Clocks */
#define acmgt3__ext810__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext810 :: AVG GPU Core Frequency */
#define acmgt3__ext810__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext810 :: AVG GPU Core Frequency */
#define acmgt3__ext810__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext810 :: RT INSTANCE NODE RAY COUNT XECORE10 */
#define acmgt3__ext810__rt_instance_node_ray_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext810 :: RT INTERNAL NODE RAY COUNT XECORE10 */
#define acmgt3__ext810__rt_internal_node_ray_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext810 :: RT TRAVERSAL STEP RAY COUNT XECORE10 */
#define acmgt3__ext810__rt_traversal_step_ray_count_xecore10__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext811 :: GPU Time Elapsed */
#define acmgt3__ext811__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext811 :: GPU Core Clocks */
#define acmgt3__ext811__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext811 :: AVG GPU Core Frequency */
#define acmgt3__ext811__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext811 :: AVG GPU Core Frequency */
#define acmgt3__ext811__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext811 :: RT INSTANCE NODE RAY COUNT XECORE11 */
#define acmgt3__ext811__rt_instance_node_ray_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext811 :: RT INTERNAL NODE RAY COUNT XECORE11 */
#define acmgt3__ext811__rt_internal_node_ray_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext811 :: RT TRAVERSAL STEP RAY COUNT XECORE11 */
#define acmgt3__ext811__rt_traversal_step_ray_count_xecore11__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext812 :: GPU Time Elapsed */
#define acmgt3__ext812__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext812 :: GPU Core Clocks */
#define acmgt3__ext812__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext812 :: AVG GPU Core Frequency */
#define acmgt3__ext812__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext812 :: AVG GPU Core Frequency */
#define acmgt3__ext812__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext812 :: RT INSTANCE NODE RAY COUNT XECORE12 */
#define acmgt3__ext812__rt_instance_node_ray_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext812 :: RT INTERNAL NODE RAY COUNT XECORE12 */
#define acmgt3__ext812__rt_internal_node_ray_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext812 :: RT TRAVERSAL STEP RAY COUNT XECORE12 */
#define acmgt3__ext812__rt_traversal_step_ray_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext813 :: GPU Time Elapsed */
#define acmgt3__ext813__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext813 :: GPU Core Clocks */
#define acmgt3__ext813__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext813 :: AVG GPU Core Frequency */
#define acmgt3__ext813__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext813 :: AVG GPU Core Frequency */
#define acmgt3__ext813__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext813 :: RT INSTANCE NODE RAY COUNT XECORE13 */
#define acmgt3__ext813__rt_instance_node_ray_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext813 :: RT INTERNAL NODE RAY COUNT XECORE13 */
#define acmgt3__ext813__rt_internal_node_ray_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext813 :: RT TRAVERSAL STEP RAY COUNT XECORE13 */
#define acmgt3__ext813__rt_traversal_step_ray_count_xecore13__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext814 :: GPU Time Elapsed */
#define acmgt3__ext814__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext814 :: GPU Core Clocks */
#define acmgt3__ext814__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext814 :: AVG GPU Core Frequency */
#define acmgt3__ext814__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext814 :: AVG GPU Core Frequency */
#define acmgt3__ext814__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext814 :: RT INSTANCE NODE RAY COUNT XECORE14 */
#define acmgt3__ext814__rt_instance_node_ray_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext814 :: RT INTERNAL NODE RAY COUNT XECORE14 */
#define acmgt3__ext814__rt_internal_node_ray_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext814 :: RT TRAVERSAL STEP RAY COUNT XECORE14 */
#define acmgt3__ext814__rt_traversal_step_ray_count_xecore14__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext815 :: GPU Time Elapsed */
#define acmgt3__ext815__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext815 :: GPU Core Clocks */
#define acmgt3__ext815__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext815 :: AVG GPU Core Frequency */
#define acmgt3__ext815__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext815 :: AVG GPU Core Frequency */
#define acmgt3__ext815__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext815 :: RT INSTANCE NODE RAY COUNT XECORE15 */
#define acmgt3__ext815__rt_instance_node_ray_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext815 :: RT INTERNAL NODE RAY COUNT XECORE15 */
#define acmgt3__ext815__rt_internal_node_ray_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext815 :: RT TRAVERSAL STEP RAY COUNT XECORE15 */
#define acmgt3__ext815__rt_traversal_step_ray_count_xecore15__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext816 :: GPU Time Elapsed */
#define acmgt3__ext816__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext816 :: GPU Core Clocks */
#define acmgt3__ext816__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext816 :: AVG GPU Core Frequency */
#define acmgt3__ext816__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext816 :: AVG GPU Core Frequency */
#define acmgt3__ext816__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext816 :: RT INSTANCE NODE RAY COUNT XECORE16 */
#define acmgt3__ext816__rt_instance_node_ray_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext816 :: RT INTERNAL NODE RAY COUNT XECORE16 */
#define acmgt3__ext816__rt_internal_node_ray_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext816 :: RT TRAVERSAL STEP RAY COUNT XECORE16 */
#define acmgt3__ext816__rt_traversal_step_ray_count_xecore16__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext817 :: GPU Time Elapsed */
#define acmgt3__ext817__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext817 :: GPU Core Clocks */
#define acmgt3__ext817__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext817 :: AVG GPU Core Frequency */
#define acmgt3__ext817__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext817 :: AVG GPU Core Frequency */
#define acmgt3__ext817__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext817 :: RT INSTANCE NODE RAY COUNT XECORE17 */
#define acmgt3__ext817__rt_instance_node_ray_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext817 :: RT INTERNAL NODE RAY COUNT XECORE17 */
#define acmgt3__ext817__rt_internal_node_ray_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext817 :: RT TRAVERSAL STEP RAY COUNT XECORE17 */
#define acmgt3__ext817__rt_traversal_step_ray_count_xecore17__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext818 :: GPU Time Elapsed */
#define acmgt3__ext818__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext818 :: GPU Core Clocks */
#define acmgt3__ext818__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext818 :: AVG GPU Core Frequency */
#define acmgt3__ext818__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext818 :: AVG GPU Core Frequency */
#define acmgt3__ext818__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext818 :: RT INSTANCE NODE RAY COUNT XECORE18 */
#define acmgt3__ext818__rt_instance_node_ray_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext818 :: RT INTERNAL NODE RAY COUNT XECORE18 */
#define acmgt3__ext818__rt_internal_node_ray_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext818 :: RT TRAVERSAL STEP RAY COUNT XECORE18 */
#define acmgt3__ext818__rt_traversal_step_ray_count_xecore18__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext819 :: GPU Time Elapsed */
#define acmgt3__ext819__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext819 :: GPU Core Clocks */
#define acmgt3__ext819__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext819 :: AVG GPU Core Frequency */
#define acmgt3__ext819__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext819 :: AVG GPU Core Frequency */
#define acmgt3__ext819__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext819 :: RT INSTANCE NODE RAY COUNT XECORE19 */
#define acmgt3__ext819__rt_instance_node_ray_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext819 :: RT INTERNAL NODE RAY COUNT XECORE19 */
#define acmgt3__ext819__rt_internal_node_ray_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext819 :: RT TRAVERSAL STEP RAY COUNT XECORE19 */
#define acmgt3__ext819__rt_traversal_step_ray_count_xecore19__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext820 :: GPU Time Elapsed */
#define acmgt3__ext820__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext820 :: GPU Core Clocks */
#define acmgt3__ext820__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext820 :: AVG GPU Core Frequency */
#define acmgt3__ext820__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext820 :: AVG GPU Core Frequency */
#define acmgt3__ext820__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext820 :: RT INSTANCE NODE RAY COUNT XECORE20 */
#define acmgt3__ext820__rt_instance_node_ray_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext820 :: RT INTERNAL NODE RAY COUNT XECORE20 */
#define acmgt3__ext820__rt_internal_node_ray_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext820 :: RT TRAVERSAL STEP RAY COUNT XECORE20 */
#define acmgt3__ext820__rt_traversal_step_ray_count_xecore20__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext821 :: GPU Time Elapsed */
#define acmgt3__ext821__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext821 :: GPU Core Clocks */
#define acmgt3__ext821__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext821 :: AVG GPU Core Frequency */
#define acmgt3__ext821__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext821 :: AVG GPU Core Frequency */
#define acmgt3__ext821__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext821 :: RT INSTANCE NODE RAY COUNT XECORE21 */
#define acmgt3__ext821__rt_instance_node_ray_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext821 :: RT INTERNAL NODE RAY COUNT XECORE21 */
#define acmgt3__ext821__rt_internal_node_ray_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext821 :: RT TRAVERSAL STEP RAY COUNT XECORE21 */
#define acmgt3__ext821__rt_traversal_step_ray_count_xecore21__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext822 :: GPU Time Elapsed */
#define acmgt3__ext822__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext822 :: GPU Core Clocks */
#define acmgt3__ext822__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext822 :: AVG GPU Core Frequency */
#define acmgt3__ext822__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext822 :: AVG GPU Core Frequency */
#define acmgt3__ext822__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext822 :: RT INSTANCE NODE RAY COUNT XECORE22 */
#define acmgt3__ext822__rt_instance_node_ray_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext822 :: RT INTERNAL NODE RAY COUNT XECORE22 */
#define acmgt3__ext822__rt_internal_node_ray_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext822 :: RT TRAVERSAL STEP RAY COUNT XECORE22 */
#define acmgt3__ext822__rt_traversal_step_ray_count_xecore22__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext823 :: GPU Time Elapsed */
#define acmgt3__ext823__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext823 :: GPU Core Clocks */
#define acmgt3__ext823__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext823 :: AVG GPU Core Frequency */
#define acmgt3__ext823__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext823 :: AVG GPU Core Frequency */
#define acmgt3__ext823__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext823 :: RT INSTANCE NODE RAY COUNT XECORE23 */
#define acmgt3__ext823__rt_instance_node_ray_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext823 :: RT INTERNAL NODE RAY COUNT XECORE23 */
#define acmgt3__ext823__rt_internal_node_ray_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext823 :: RT TRAVERSAL STEP RAY COUNT XECORE23 */
#define acmgt3__ext823__rt_traversal_step_ray_count_xecore23__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext824 :: GPU Time Elapsed */
#define acmgt3__ext824__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext824 :: GPU Core Clocks */
#define acmgt3__ext824__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext824 :: AVG GPU Core Frequency */
#define acmgt3__ext824__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext824 :: AVG GPU Core Frequency */
#define acmgt3__ext824__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext824 :: RT INSTANCE NODE RAY COUNT XECORE24 */
#define acmgt3__ext824__rt_instance_node_ray_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext824 :: RT INTERNAL NODE RAY COUNT XECORE24 */
#define acmgt3__ext824__rt_internal_node_ray_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext824 :: RT TRAVERSAL STEP RAY COUNT XECORE24 */
#define acmgt3__ext824__rt_traversal_step_ray_count_xecore24__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext825 :: GPU Time Elapsed */
#define acmgt3__ext825__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext825 :: GPU Core Clocks */
#define acmgt3__ext825__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext825 :: AVG GPU Core Frequency */
#define acmgt3__ext825__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext825 :: AVG GPU Core Frequency */
#define acmgt3__ext825__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext825 :: RT INSTANCE NODE RAY COUNT XECORE25 */
#define acmgt3__ext825__rt_instance_node_ray_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext825 :: RT INTERNAL NODE RAY COUNT XECORE25 */
#define acmgt3__ext825__rt_internal_node_ray_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext825 :: RT TRAVERSAL STEP RAY COUNT XECORE25 */
#define acmgt3__ext825__rt_traversal_step_ray_count_xecore25__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext826 :: GPU Time Elapsed */
#define acmgt3__ext826__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext826 :: GPU Core Clocks */
#define acmgt3__ext826__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext826 :: AVG GPU Core Frequency */
#define acmgt3__ext826__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext826 :: AVG GPU Core Frequency */
#define acmgt3__ext826__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext826 :: RT INSTANCE NODE RAY COUNT XECORE26 */
#define acmgt3__ext826__rt_instance_node_ray_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext826 :: RT INTERNAL NODE RAY COUNT XECORE26 */
#define acmgt3__ext826__rt_internal_node_ray_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext826 :: RT TRAVERSAL STEP RAY COUNT XECORE26 */
#define acmgt3__ext826__rt_traversal_step_ray_count_xecore26__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext827 :: GPU Time Elapsed */
#define acmgt3__ext827__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext827 :: GPU Core Clocks */
#define acmgt3__ext827__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext827 :: AVG GPU Core Frequency */
#define acmgt3__ext827__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext827 :: AVG GPU Core Frequency */
#define acmgt3__ext827__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext827 :: RT INSTANCE NODE RAY COUNT XECORE27 */
#define acmgt3__ext827__rt_instance_node_ray_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext827 :: RT INTERNAL NODE RAY COUNT XECORE27 */
#define acmgt3__ext827__rt_internal_node_ray_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext827 :: RT TRAVERSAL STEP RAY COUNT XECORE27 */
#define acmgt3__ext827__rt_traversal_step_ray_count_xecore27__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext828 :: GPU Time Elapsed */
#define acmgt3__ext828__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext828 :: GPU Core Clocks */
#define acmgt3__ext828__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext828 :: AVG GPU Core Frequency */
#define acmgt3__ext828__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext828 :: AVG GPU Core Frequency */
#define acmgt3__ext828__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext828 :: RT INSTANCE NODE RAY COUNT XECORE28 */
#define acmgt3__ext828__rt_instance_node_ray_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext828 :: RT INTERNAL NODE RAY COUNT XECORE28 */
#define acmgt3__ext828__rt_internal_node_ray_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext828 :: RT TRAVERSAL STEP RAY COUNT XECORE28 */
#define acmgt3__ext828__rt_traversal_step_ray_count_xecore28__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext829 :: GPU Time Elapsed */
#define acmgt3__ext829__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext829 :: GPU Core Clocks */
#define acmgt3__ext829__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext829 :: AVG GPU Core Frequency */
#define acmgt3__ext829__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext829 :: AVG GPU Core Frequency */
#define acmgt3__ext829__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext829 :: RT INSTANCE NODE RAY COUNT XECORE29 */
#define acmgt3__ext829__rt_instance_node_ray_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext829 :: RT INTERNAL NODE RAY COUNT XECORE29 */
#define acmgt3__ext829__rt_internal_node_ray_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext829 :: RT TRAVERSAL STEP RAY COUNT XECORE29 */
#define acmgt3__ext829__rt_traversal_step_ray_count_xecore29__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext830 :: GPU Time Elapsed */
#define acmgt3__ext830__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext830 :: GPU Core Clocks */
#define acmgt3__ext830__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext830 :: AVG GPU Core Frequency */
#define acmgt3__ext830__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext830 :: AVG GPU Core Frequency */
#define acmgt3__ext830__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext830 :: RT INSTANCE NODE RAY COUNT XECORE30 */
#define acmgt3__ext830__rt_instance_node_ray_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext830 :: RT INTERNAL NODE RAY COUNT XECORE30 */
#define acmgt3__ext830__rt_internal_node_ray_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext830 :: RT TRAVERSAL STEP RAY COUNT XECORE30 */
#define acmgt3__ext830__rt_traversal_step_ray_count_xecore30__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext831 :: GPU Time Elapsed */
#define acmgt3__ext831__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext831 :: GPU Core Clocks */
#define acmgt3__ext831__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext831 :: AVG GPU Core Frequency */
#define acmgt3__ext831__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext831 :: AVG GPU Core Frequency */
#define acmgt3__ext831__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext831 :: RT INSTANCE NODE RAY COUNT XECORE31 */
#define acmgt3__ext831__rt_instance_node_ray_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext831 :: RT INTERNAL NODE RAY COUNT XECORE31 */
#define acmgt3__ext831__rt_internal_node_ray_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext831 :: RT TRAVERSAL STEP RAY COUNT XECORE31 */
#define acmgt3__ext831__rt_traversal_step_ray_count_xecore31__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext832 :: GPU Time Elapsed */
#define acmgt3__ext832__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext832 :: GPU Core Clocks */
#define acmgt3__ext832__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext832 :: AVG GPU Core Frequency */
#define acmgt3__ext832__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext832 :: AVG GPU Core Frequency */
#define acmgt3__ext832__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext832 :: RT QUAD LEAF RAY COUNT XECORE0 */
#define acmgt3__ext832__rt_quad_leaf_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext832 :: RT PROCEDURAL NODE RAY COUNT XECORE0 */
#define acmgt3__ext832__rt_procedural_node_ray_count_xecore0__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext833 :: GPU Time Elapsed */
#define acmgt3__ext833__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext833 :: GPU Core Clocks */
#define acmgt3__ext833__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext833 :: AVG GPU Core Frequency */
#define acmgt3__ext833__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext833 :: AVG GPU Core Frequency */
#define acmgt3__ext833__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext833 :: RT QUAD LEAF RAY COUNT XECORE1 */
#define acmgt3__ext833__rt_quad_leaf_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext833 :: RT PROCEDURAL NODE RAY COUNT XECORE1 */
#define acmgt3__ext833__rt_procedural_node_ray_count_xecore1__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext834 :: GPU Time Elapsed */
#define acmgt3__ext834__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext834 :: GPU Core Clocks */
#define acmgt3__ext834__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext834 :: AVG GPU Core Frequency */
#define acmgt3__ext834__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext834 :: AVG GPU Core Frequency */
#define acmgt3__ext834__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext834 :: RT QUAD LEAF RAY COUNT XECORE2 */
#define acmgt3__ext834__rt_quad_leaf_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext834 :: RT PROCEDURAL NODE RAY COUNT XECORE2 */
#define acmgt3__ext834__rt_procedural_node_ray_count_xecore2__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext835 :: GPU Time Elapsed */
#define acmgt3__ext835__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext835 :: GPU Core Clocks */
#define acmgt3__ext835__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext835 :: AVG GPU Core Frequency */
#define acmgt3__ext835__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext835 :: AVG GPU Core Frequency */
#define acmgt3__ext835__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext835 :: RT QUAD LEAF RAY COUNT XECORE3 */
#define acmgt3__ext835__rt_quad_leaf_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext835 :: RT PROCEDURAL NODE RAY COUNT XECORE3 */
#define acmgt3__ext835__rt_procedural_node_ray_count_xecore3__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext836 :: GPU Time Elapsed */
#define acmgt3__ext836__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext836 :: GPU Core Clocks */
#define acmgt3__ext836__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext836 :: AVG GPU Core Frequency */
#define acmgt3__ext836__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext836 :: AVG GPU Core Frequency */
#define acmgt3__ext836__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext836 :: RT QUAD LEAF RAY COUNT XECORE4 */
#define acmgt3__ext836__rt_quad_leaf_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext836 :: RT PROCEDURAL NODE RAY COUNT XECORE4 */
#define acmgt3__ext836__rt_procedural_node_ray_count_xecore4__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext837 :: GPU Time Elapsed */
#define acmgt3__ext837__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext837 :: GPU Core Clocks */
#define acmgt3__ext837__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext837 :: AVG GPU Core Frequency */
#define acmgt3__ext837__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext837 :: AVG GPU Core Frequency */
#define acmgt3__ext837__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext837 :: RT QUAD LEAF RAY COUNT XECORE5 */
#define acmgt3__ext837__rt_quad_leaf_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext837 :: RT PROCEDURAL NODE RAY COUNT XECORE5 */
#define acmgt3__ext837__rt_procedural_node_ray_count_xecore5__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext838 :: GPU Time Elapsed */
#define acmgt3__ext838__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext838 :: GPU Core Clocks */
#define acmgt3__ext838__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext838 :: AVG GPU Core Frequency */
#define acmgt3__ext838__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext838 :: AVG GPU Core Frequency */
#define acmgt3__ext838__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext838 :: RT QUAD LEAF RAY COUNT XECORE6 */
#define acmgt3__ext838__rt_quad_leaf_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext838 :: RT PROCEDURAL NODE RAY COUNT XECORE6 */
#define acmgt3__ext838__rt_procedural_node_ray_count_xecore6__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext839 :: GPU Time Elapsed */
#define acmgt3__ext839__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext839 :: GPU Core Clocks */
#define acmgt3__ext839__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext839 :: AVG GPU Core Frequency */
#define acmgt3__ext839__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext839 :: AVG GPU Core Frequency */
#define acmgt3__ext839__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext839 :: RT QUAD LEAF RAY COUNT XECORE7 */
#define acmgt3__ext839__rt_quad_leaf_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext839 :: RT PROCEDURAL NODE RAY COUNT XECORE7 */
#define acmgt3__ext839__rt_procedural_node_ray_count_xecore7__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext840 :: GPU Time Elapsed */
#define acmgt3__ext840__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext840 :: GPU Core Clocks */
#define acmgt3__ext840__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext840 :: AVG GPU Core Frequency */
#define acmgt3__ext840__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext840 :: AVG GPU Core Frequency */
#define acmgt3__ext840__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext840 :: RT QUAD LEAF RAY COUNT XECORE8 */
#define acmgt3__ext840__rt_quad_leaf_ray_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext840 :: RT PROCEDURAL NODE RAY COUNT XECORE8 */
#define acmgt3__ext840__rt_procedural_node_ray_count_xecore8__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext841 :: GPU Time Elapsed */
#define acmgt3__ext841__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext841 :: GPU Core Clocks */
#define acmgt3__ext841__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext841 :: AVG GPU Core Frequency */
#define acmgt3__ext841__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext841 :: AVG GPU Core Frequency */
#define acmgt3__ext841__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext841 :: RT QUAD LEAF RAY COUNT XECORE9 */
#define acmgt3__ext841__rt_quad_leaf_ray_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext841 :: RT PROCEDURAL NODE RAY COUNT XECORE9 */
#define acmgt3__ext841__rt_procedural_node_ray_count_xecore9__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext842 :: GPU Time Elapsed */
#define acmgt3__ext842__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext842 :: GPU Core Clocks */
#define acmgt3__ext842__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext842 :: AVG GPU Core Frequency */
#define acmgt3__ext842__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext842 :: AVG GPU Core Frequency */
#define acmgt3__ext842__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext842 :: RT QUAD LEAF RAY COUNT XECORE10 */
#define acmgt3__ext842__rt_quad_leaf_ray_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext842 :: RT PROCEDURAL NODE RAY COUNT XECORE10 */
#define acmgt3__ext842__rt_procedural_node_ray_count_xecore10__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext843 :: GPU Time Elapsed */
#define acmgt3__ext843__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext843 :: GPU Core Clocks */
#define acmgt3__ext843__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext843 :: AVG GPU Core Frequency */
#define acmgt3__ext843__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext843 :: AVG GPU Core Frequency */
#define acmgt3__ext843__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext843 :: RT QUAD LEAF RAY COUNT XECORE11 */
#define acmgt3__ext843__rt_quad_leaf_ray_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext843 :: RT PROCEDURAL NODE RAY COUNT XECORE11 */
#define acmgt3__ext843__rt_procedural_node_ray_count_xecore11__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext844 :: GPU Time Elapsed */
#define acmgt3__ext844__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext844 :: GPU Core Clocks */
#define acmgt3__ext844__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext844 :: AVG GPU Core Frequency */
#define acmgt3__ext844__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext844 :: AVG GPU Core Frequency */
#define acmgt3__ext844__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext844 :: RT QUAD LEAF RAY COUNT XECORE12 */
#define acmgt3__ext844__rt_quad_leaf_ray_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext844 :: RT PROCEDURAL NODE RAY COUNT XECORE12 */
#define acmgt3__ext844__rt_procedural_node_ray_count_xecore12__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext845 :: GPU Time Elapsed */
#define acmgt3__ext845__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext845 :: GPU Core Clocks */
#define acmgt3__ext845__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext845 :: AVG GPU Core Frequency */
#define acmgt3__ext845__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext845 :: AVG GPU Core Frequency */
#define acmgt3__ext845__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext845 :: RT QUAD LEAF RAY COUNT XECORE13 */
#define acmgt3__ext845__rt_quad_leaf_ray_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext845 :: RT PROCEDURAL NODE RAY COUNT XECORE13 */
#define acmgt3__ext845__rt_procedural_node_ray_count_xecore13__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext846 :: GPU Time Elapsed */
#define acmgt3__ext846__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext846 :: GPU Core Clocks */
#define acmgt3__ext846__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext846 :: AVG GPU Core Frequency */
#define acmgt3__ext846__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext846 :: AVG GPU Core Frequency */
#define acmgt3__ext846__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext846 :: RT QUAD LEAF RAY COUNT XECORE14 */
#define acmgt3__ext846__rt_quad_leaf_ray_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext846 :: RT PROCEDURAL NODE RAY COUNT XECORE14 */
#define acmgt3__ext846__rt_procedural_node_ray_count_xecore14__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext847 :: GPU Time Elapsed */
#define acmgt3__ext847__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext847 :: GPU Core Clocks */
#define acmgt3__ext847__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext847 :: AVG GPU Core Frequency */
#define acmgt3__ext847__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext847 :: AVG GPU Core Frequency */
#define acmgt3__ext847__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext847 :: RT QUAD LEAF RAY COUNT XECORE15 */
#define acmgt3__ext847__rt_quad_leaf_ray_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext847 :: RT PROCEDURAL NODE RAY COUNT XECORE15 */
#define acmgt3__ext847__rt_procedural_node_ray_count_xecore15__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext848 :: GPU Time Elapsed */
#define acmgt3__ext848__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext848 :: GPU Core Clocks */
#define acmgt3__ext848__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext848 :: AVG GPU Core Frequency */
#define acmgt3__ext848__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext848 :: AVG GPU Core Frequency */
#define acmgt3__ext848__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext848 :: RT QUAD LEAF RAY COUNT XECORE16 */
#define acmgt3__ext848__rt_quad_leaf_ray_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext848 :: RT PROCEDURAL NODE RAY COUNT XECORE16 */
#define acmgt3__ext848__rt_procedural_node_ray_count_xecore16__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext849 :: GPU Time Elapsed */
#define acmgt3__ext849__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext849 :: GPU Core Clocks */
#define acmgt3__ext849__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext849 :: AVG GPU Core Frequency */
#define acmgt3__ext849__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext849 :: AVG GPU Core Frequency */
#define acmgt3__ext849__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext849 :: RT QUAD LEAF RAY COUNT XECORE17 */
#define acmgt3__ext849__rt_quad_leaf_ray_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext849 :: RT PROCEDURAL NODE RAY COUNT XECORE17 */
#define acmgt3__ext849__rt_procedural_node_ray_count_xecore17__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext850 :: GPU Time Elapsed */
#define acmgt3__ext850__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext850 :: GPU Core Clocks */
#define acmgt3__ext850__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext850 :: AVG GPU Core Frequency */
#define acmgt3__ext850__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext850 :: AVG GPU Core Frequency */
#define acmgt3__ext850__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext850 :: RT QUAD LEAF RAY COUNT XECORE18 */
#define acmgt3__ext850__rt_quad_leaf_ray_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext850 :: RT PROCEDURAL NODE RAY COUNT XECORE18 */
#define acmgt3__ext850__rt_procedural_node_ray_count_xecore18__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext851 :: GPU Time Elapsed */
#define acmgt3__ext851__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext851 :: GPU Core Clocks */
#define acmgt3__ext851__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext851 :: AVG GPU Core Frequency */
#define acmgt3__ext851__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext851 :: AVG GPU Core Frequency */
#define acmgt3__ext851__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext851 :: RT QUAD LEAF RAY COUNT XECORE19 */
#define acmgt3__ext851__rt_quad_leaf_ray_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext851 :: RT PROCEDURAL NODE RAY COUNT XECORE19 */
#define acmgt3__ext851__rt_procedural_node_ray_count_xecore19__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext852 :: GPU Time Elapsed */
#define acmgt3__ext852__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext852 :: GPU Core Clocks */
#define acmgt3__ext852__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext852 :: AVG GPU Core Frequency */
#define acmgt3__ext852__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext852 :: AVG GPU Core Frequency */
#define acmgt3__ext852__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext852 :: RT QUAD LEAF RAY COUNT XECORE20 */
#define acmgt3__ext852__rt_quad_leaf_ray_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext852 :: RT PROCEDURAL NODE RAY COUNT XECORE20 */
#define acmgt3__ext852__rt_procedural_node_ray_count_xecore20__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext853 :: GPU Time Elapsed */
#define acmgt3__ext853__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext853 :: GPU Core Clocks */
#define acmgt3__ext853__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext853 :: AVG GPU Core Frequency */
#define acmgt3__ext853__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext853 :: AVG GPU Core Frequency */
#define acmgt3__ext853__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext853 :: RT QUAD LEAF RAY COUNT XECORE21 */
#define acmgt3__ext853__rt_quad_leaf_ray_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext853 :: RT PROCEDURAL NODE RAY COUNT XECORE21 */
#define acmgt3__ext853__rt_procedural_node_ray_count_xecore21__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext854 :: GPU Time Elapsed */
#define acmgt3__ext854__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext854 :: GPU Core Clocks */
#define acmgt3__ext854__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext854 :: AVG GPU Core Frequency */
#define acmgt3__ext854__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext854 :: AVG GPU Core Frequency */
#define acmgt3__ext854__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext854 :: RT QUAD LEAF RAY COUNT XECORE22 */
#define acmgt3__ext854__rt_quad_leaf_ray_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext854 :: RT PROCEDURAL NODE RAY COUNT XECORE22 */
#define acmgt3__ext854__rt_procedural_node_ray_count_xecore22__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext855 :: GPU Time Elapsed */
#define acmgt3__ext855__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext855 :: GPU Core Clocks */
#define acmgt3__ext855__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext855 :: AVG GPU Core Frequency */
#define acmgt3__ext855__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext855 :: AVG GPU Core Frequency */
#define acmgt3__ext855__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext855 :: RT QUAD LEAF RAY COUNT XECORE23 */
#define acmgt3__ext855__rt_quad_leaf_ray_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext855 :: RT PROCEDURAL NODE RAY COUNT XECORE23 */
#define acmgt3__ext855__rt_procedural_node_ray_count_xecore23__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext856 :: GPU Time Elapsed */
#define acmgt3__ext856__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext856 :: GPU Core Clocks */
#define acmgt3__ext856__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext856 :: AVG GPU Core Frequency */
#define acmgt3__ext856__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext856 :: AVG GPU Core Frequency */
#define acmgt3__ext856__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext856 :: RT QUAD LEAF RAY COUNT XECORE24 */
#define acmgt3__ext856__rt_quad_leaf_ray_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext856 :: RT PROCEDURAL NODE RAY COUNT XECORE24 */
#define acmgt3__ext856__rt_procedural_node_ray_count_xecore24__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext857 :: GPU Time Elapsed */
#define acmgt3__ext857__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext857 :: GPU Core Clocks */
#define acmgt3__ext857__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext857 :: AVG GPU Core Frequency */
#define acmgt3__ext857__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext857 :: AVG GPU Core Frequency */
#define acmgt3__ext857__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext857 :: RT QUAD LEAF RAY COUNT XECORE25 */
#define acmgt3__ext857__rt_quad_leaf_ray_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext857 :: RT PROCEDURAL NODE RAY COUNT XECORE25 */
#define acmgt3__ext857__rt_procedural_node_ray_count_xecore25__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext858 :: GPU Time Elapsed */
#define acmgt3__ext858__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext858 :: GPU Core Clocks */
#define acmgt3__ext858__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext858 :: AVG GPU Core Frequency */
#define acmgt3__ext858__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext858 :: AVG GPU Core Frequency */
#define acmgt3__ext858__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext858 :: RT QUAD LEAF RAY COUNT XECORE26 */
#define acmgt3__ext858__rt_quad_leaf_ray_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext858 :: RT PROCEDURAL NODE RAY COUNT XECORE26 */
#define acmgt3__ext858__rt_procedural_node_ray_count_xecore26__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext859 :: GPU Time Elapsed */
#define acmgt3__ext859__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext859 :: GPU Core Clocks */
#define acmgt3__ext859__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext859 :: AVG GPU Core Frequency */
#define acmgt3__ext859__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext859 :: AVG GPU Core Frequency */
#define acmgt3__ext859__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext859 :: RT QUAD LEAF RAY COUNT XECORE27 */
#define acmgt3__ext859__rt_quad_leaf_ray_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext859 :: RT PROCEDURAL NODE RAY COUNT XECORE27 */
#define acmgt3__ext859__rt_procedural_node_ray_count_xecore27__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext860 :: GPU Time Elapsed */
#define acmgt3__ext860__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext860 :: GPU Core Clocks */
#define acmgt3__ext860__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext860 :: AVG GPU Core Frequency */
#define acmgt3__ext860__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext860 :: AVG GPU Core Frequency */
#define acmgt3__ext860__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext860 :: RT QUAD LEAF RAY COUNT XECORE28 */
#define acmgt3__ext860__rt_quad_leaf_ray_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext860 :: RT PROCEDURAL NODE RAY COUNT XECORE28 */
#define acmgt3__ext860__rt_procedural_node_ray_count_xecore28__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext861 :: GPU Time Elapsed */
#define acmgt3__ext861__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext861 :: GPU Core Clocks */
#define acmgt3__ext861__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext861 :: AVG GPU Core Frequency */
#define acmgt3__ext861__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext861 :: AVG GPU Core Frequency */
#define acmgt3__ext861__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext861 :: RT QUAD LEAF RAY COUNT XECORE29 */
#define acmgt3__ext861__rt_quad_leaf_ray_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext861 :: RT PROCEDURAL NODE RAY COUNT XECORE29 */
#define acmgt3__ext861__rt_procedural_node_ray_count_xecore29__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext862 :: GPU Time Elapsed */
#define acmgt3__ext862__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext862 :: GPU Core Clocks */
#define acmgt3__ext862__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext862 :: AVG GPU Core Frequency */
#define acmgt3__ext862__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext862 :: AVG GPU Core Frequency */
#define acmgt3__ext862__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext862 :: RT QUAD LEAF RAY COUNT XECORE30 */
#define acmgt3__ext862__rt_quad_leaf_ray_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext862 :: RT PROCEDURAL NODE RAY COUNT XECORE30 */
#define acmgt3__ext862__rt_procedural_node_ray_count_xecore30__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext863 :: GPU Time Elapsed */
#define acmgt3__ext863__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext863 :: GPU Core Clocks */
#define acmgt3__ext863__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext863 :: AVG GPU Core Frequency */
#define acmgt3__ext863__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext863 :: AVG GPU Core Frequency */
#define acmgt3__ext863__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext863 :: RT QUAD LEAF RAY COUNT XECORE31 */
#define acmgt3__ext863__rt_quad_leaf_ray_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore0__read

/* Ext863 :: RT PROCEDURAL NODE RAY COUNT XECORE31 */
#define acmgt3__ext863__rt_procedural_node_ray_count_xecore31__read \
   acmgt1__ext23__load_store_cache_hit_xecore1__read

/* Ext864 :: GPU Time Elapsed */
#define acmgt3__ext864__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext864 :: GPU Core Clocks */
#define acmgt3__ext864__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext864 :: AVG GPU Core Frequency */
#define acmgt3__ext864__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext864 :: AVG GPU Core Frequency */
#define acmgt3__ext864__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext864 :: RT BVH CACHE MISS XECORE0 */
#define acmgt3__ext864__rt_bvh_cache_miss_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext864 :: RT BVH CACHE MISS XECORE1 */
#define acmgt3__ext864__rt_bvh_cache_miss_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext864 :: RT BVH CACHE MISS XECORE2 */
#define acmgt3__ext864__rt_bvh_cache_miss_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext864 :: RT BVH CACHE MISS XECORE3 */
#define acmgt3__ext864__rt_bvh_cache_miss_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext865 :: GPU Time Elapsed */
#define acmgt3__ext865__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext865 :: GPU Core Clocks */
#define acmgt3__ext865__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext865 :: AVG GPU Core Frequency */
#define acmgt3__ext865__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext865 :: AVG GPU Core Frequency */
#define acmgt3__ext865__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext865 :: RT BVH CACHE MISS XECORE4 */
#define acmgt3__ext865__rt_bvh_cache_miss_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext865 :: RT BVH CACHE MISS XECORE5 */
#define acmgt3__ext865__rt_bvh_cache_miss_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext865 :: RT BVH CACHE MISS XECORE6 */
#define acmgt3__ext865__rt_bvh_cache_miss_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext865 :: RT BVH CACHE MISS XECORE7 */
#define acmgt3__ext865__rt_bvh_cache_miss_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext866 :: GPU Time Elapsed */
#define acmgt3__ext866__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext866 :: GPU Core Clocks */
#define acmgt3__ext866__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext866 :: AVG GPU Core Frequency */
#define acmgt3__ext866__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext866 :: AVG GPU Core Frequency */
#define acmgt3__ext866__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext866 :: RT BVH CACHE MISS XECORE8 */
#define acmgt3__ext866__rt_bvh_cache_miss_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext866 :: RT BVH CACHE MISS XECORE9 */
#define acmgt3__ext866__rt_bvh_cache_miss_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext866 :: RT BVH CACHE MISS XECORE10 */
#define acmgt3__ext866__rt_bvh_cache_miss_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext866 :: RT BVH CACHE MISS XECORE11 */
#define acmgt3__ext866__rt_bvh_cache_miss_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext867 :: GPU Time Elapsed */
#define acmgt3__ext867__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext867 :: GPU Core Clocks */
#define acmgt3__ext867__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext867 :: AVG GPU Core Frequency */
#define acmgt3__ext867__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext867 :: AVG GPU Core Frequency */
#define acmgt3__ext867__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext867 :: RT BVH CACHE MISS XECORE12 */
#define acmgt3__ext867__rt_bvh_cache_miss_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext867 :: RT BVH CACHE MISS XECORE13 */
#define acmgt3__ext867__rt_bvh_cache_miss_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext867 :: RT BVH CACHE MISS XECORE14 */
#define acmgt3__ext867__rt_bvh_cache_miss_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext867 :: RT BVH CACHE MISS XECORE15 */
#define acmgt3__ext867__rt_bvh_cache_miss_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext868 :: GPU Time Elapsed */
#define acmgt3__ext868__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext868 :: GPU Core Clocks */
#define acmgt3__ext868__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext868 :: AVG GPU Core Frequency */
#define acmgt3__ext868__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext868 :: AVG GPU Core Frequency */
#define acmgt3__ext868__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext868 :: RT BVH CACHE MISS XECORE16 */
#define acmgt3__ext868__rt_bvh_cache_miss_xecore16__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext868 :: RT BVH CACHE MISS XECORE17 */
#define acmgt3__ext868__rt_bvh_cache_miss_xecore17__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext868 :: RT BVH CACHE MISS XECORE18 */
#define acmgt3__ext868__rt_bvh_cache_miss_xecore18__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext868 :: RT BVH CACHE MISS XECORE19 */
#define acmgt3__ext868__rt_bvh_cache_miss_xecore19__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext869 :: GPU Time Elapsed */
#define acmgt3__ext869__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext869 :: GPU Core Clocks */
#define acmgt3__ext869__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext869 :: AVG GPU Core Frequency */
#define acmgt3__ext869__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext869 :: AVG GPU Core Frequency */
#define acmgt3__ext869__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext869 :: RT BVH CACHE MISS XECORE20 */
#define acmgt3__ext869__rt_bvh_cache_miss_xecore20__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext869 :: RT BVH CACHE MISS XECORE21 */
#define acmgt3__ext869__rt_bvh_cache_miss_xecore21__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext869 :: RT BVH CACHE MISS XECORE22 */
#define acmgt3__ext869__rt_bvh_cache_miss_xecore22__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext869 :: RT BVH CACHE MISS XECORE23 */
#define acmgt3__ext869__rt_bvh_cache_miss_xecore23__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext870 :: GPU Time Elapsed */
#define acmgt3__ext870__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext870 :: GPU Core Clocks */
#define acmgt3__ext870__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext870 :: AVG GPU Core Frequency */
#define acmgt3__ext870__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext870 :: AVG GPU Core Frequency */
#define acmgt3__ext870__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext870 :: RT BVH CACHE MISS XECORE24 */
#define acmgt3__ext870__rt_bvh_cache_miss_xecore24__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext870 :: RT BVH CACHE MISS XECORE25 */
#define acmgt3__ext870__rt_bvh_cache_miss_xecore25__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext870 :: RT BVH CACHE MISS XECORE26 */
#define acmgt3__ext870__rt_bvh_cache_miss_xecore26__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext870 :: RT BVH CACHE MISS XECORE27 */
#define acmgt3__ext870__rt_bvh_cache_miss_xecore27__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext871 :: GPU Time Elapsed */
#define acmgt3__ext871__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext871 :: GPU Core Clocks */
#define acmgt3__ext871__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext871 :: AVG GPU Core Frequency */
#define acmgt3__ext871__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext871 :: AVG GPU Core Frequency */
#define acmgt3__ext871__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext871 :: RT BVH CACHE MISS XECORE28 */
#define acmgt3__ext871__rt_bvh_cache_miss_xecore28__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext871 :: RT BVH CACHE MISS XECORE29 */
#define acmgt3__ext871__rt_bvh_cache_miss_xecore29__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext871 :: RT BVH CACHE MISS XECORE30 */
#define acmgt3__ext871__rt_bvh_cache_miss_xecore30__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext871 :: RT BVH CACHE MISS XECORE31 */
#define acmgt3__ext871__rt_bvh_cache_miss_xecore31__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext872 :: GPU Time Elapsed */
#define acmgt3__ext872__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext872 :: GPU Core Clocks */
#define acmgt3__ext872__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext872 :: AVG GPU Core Frequency */
#define acmgt3__ext872__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext872 :: AVG GPU Core Frequency */
#define acmgt3__ext872__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext872 :: SLM ACCESS COUNT XECORE0 */
#define acmgt3__ext872__slm_access_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext872 :: SLM ACCESS COUNT XECORE1 */
#define acmgt3__ext872__slm_access_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext872 :: SLM ACCESS COUNT XECORE2 */
#define acmgt3__ext872__slm_access_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext872 :: SLM ACCESS COUNT XECORE3 */
#define acmgt3__ext872__slm_access_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext873 :: GPU Time Elapsed */
#define acmgt3__ext873__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext873 :: GPU Core Clocks */
#define acmgt3__ext873__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext873 :: AVG GPU Core Frequency */
#define acmgt3__ext873__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext873 :: AVG GPU Core Frequency */
#define acmgt3__ext873__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext873 :: SLM ACCESS COUNT XECORE4 */
#define acmgt3__ext873__slm_access_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext873 :: SLM ACCESS COUNT XECORE5 */
#define acmgt3__ext873__slm_access_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext873 :: SLM ACCESS COUNT XECORE6 */
#define acmgt3__ext873__slm_access_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext873 :: SLM ACCESS COUNT XECORE7 */
#define acmgt3__ext873__slm_access_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext874 :: GPU Time Elapsed */
#define acmgt3__ext874__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext874 :: GPU Core Clocks */
#define acmgt3__ext874__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext874 :: AVG GPU Core Frequency */
#define acmgt3__ext874__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext874 :: AVG GPU Core Frequency */
#define acmgt3__ext874__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext874 :: SLM ACCESS COUNT XECORE8 */
#define acmgt3__ext874__slm_access_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext874 :: SLM ACCESS COUNT XECORE9 */
#define acmgt3__ext874__slm_access_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext874 :: SLM ACCESS COUNT XECORE10 */
#define acmgt3__ext874__slm_access_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext874 :: SLM ACCESS COUNT XECORE11 */
#define acmgt3__ext874__slm_access_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext875 :: GPU Time Elapsed */
#define acmgt3__ext875__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext875 :: GPU Core Clocks */
#define acmgt3__ext875__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext875 :: AVG GPU Core Frequency */
#define acmgt3__ext875__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext875 :: AVG GPU Core Frequency */
#define acmgt3__ext875__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext875 :: SLM ACCESS COUNT XECORE12 */
#define acmgt3__ext875__slm_access_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext875 :: SLM ACCESS COUNT XECORE13 */
#define acmgt3__ext875__slm_access_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext875 :: SLM ACCESS COUNT XECORE14 */
#define acmgt3__ext875__slm_access_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext875 :: SLM ACCESS COUNT XECORE15 */
#define acmgt3__ext875__slm_access_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext876 :: GPU Time Elapsed */
#define acmgt3__ext876__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext876 :: GPU Core Clocks */
#define acmgt3__ext876__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext876 :: AVG GPU Core Frequency */
#define acmgt3__ext876__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext876 :: AVG GPU Core Frequency */
#define acmgt3__ext876__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext876 :: SLM ACCESS COUNT XECORE16 */
#define acmgt3__ext876__slm_access_count_xecore16__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext876 :: SLM ACCESS COUNT XECORE17 */
#define acmgt3__ext876__slm_access_count_xecore17__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext876 :: SLM ACCESS COUNT XECORE18 */
#define acmgt3__ext876__slm_access_count_xecore18__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext876 :: SLM ACCESS COUNT XECORE19 */
#define acmgt3__ext876__slm_access_count_xecore19__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext877 :: GPU Time Elapsed */
#define acmgt3__ext877__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext877 :: GPU Core Clocks */
#define acmgt3__ext877__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext877 :: AVG GPU Core Frequency */
#define acmgt3__ext877__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext877 :: AVG GPU Core Frequency */
#define acmgt3__ext877__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext877 :: SLM ACCESS COUNT XECORE20 */
#define acmgt3__ext877__slm_access_count_xecore20__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext877 :: SLM ACCESS COUNT XECORE21 */
#define acmgt3__ext877__slm_access_count_xecore21__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext877 :: SLM ACCESS COUNT XECORE22 */
#define acmgt3__ext877__slm_access_count_xecore22__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext877 :: SLM ACCESS COUNT XECORE23 */
#define acmgt3__ext877__slm_access_count_xecore23__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext878 :: GPU Time Elapsed */
#define acmgt3__ext878__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext878 :: GPU Core Clocks */
#define acmgt3__ext878__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext878 :: AVG GPU Core Frequency */
#define acmgt3__ext878__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext878 :: AVG GPU Core Frequency */
#define acmgt3__ext878__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext878 :: SLM ACCESS COUNT XECORE24 */
#define acmgt3__ext878__slm_access_count_xecore24__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext878 :: SLM ACCESS COUNT XECORE25 */
#define acmgt3__ext878__slm_access_count_xecore25__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext878 :: SLM ACCESS COUNT XECORE26 */
#define acmgt3__ext878__slm_access_count_xecore26__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext878 :: SLM ACCESS COUNT XECORE27 */
#define acmgt3__ext878__slm_access_count_xecore27__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext879 :: GPU Time Elapsed */
#define acmgt3__ext879__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext879 :: GPU Core Clocks */
#define acmgt3__ext879__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext879 :: AVG GPU Core Frequency */
#define acmgt3__ext879__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext879 :: AVG GPU Core Frequency */
#define acmgt3__ext879__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext879 :: SLM ACCESS COUNT XECORE28 */
#define acmgt3__ext879__slm_access_count_xecore28__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext879 :: SLM ACCESS COUNT XECORE29 */
#define acmgt3__ext879__slm_access_count_xecore29__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext879 :: SLM ACCESS COUNT XECORE30 */
#define acmgt3__ext879__slm_access_count_xecore30__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext879 :: SLM ACCESS COUNT XECORE31 */
#define acmgt3__ext879__slm_access_count_xecore31__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext880 :: GPU Time Elapsed */
#define acmgt3__ext880__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext880 :: GPU Core Clocks */
#define acmgt3__ext880__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext880 :: AVG GPU Core Frequency */
#define acmgt3__ext880__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext880 :: AVG GPU Core Frequency */
#define acmgt3__ext880__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext880 :: GPU MEMORY L3 WRITE SQIDI0 */
#define acmgt3__ext880__gpu_memory_l3_write_sqidi0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext881 :: GPU Time Elapsed */
#define acmgt3__ext881__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext881 :: GPU Core Clocks */
#define acmgt3__ext881__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext881 :: AVG GPU Core Frequency */
#define acmgt3__ext881__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext881 :: AVG GPU Core Frequency */
#define acmgt3__ext881__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext881 :: GPU MEMORY L3 WRITE SQIDI1 */
#define acmgt3__ext881__gpu_memory_l3_write_sqidi1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext882 :: GPU Time Elapsed */
#define acmgt3__ext882__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext882 :: GPU Core Clocks */
#define acmgt3__ext882__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext882 :: AVG GPU Core Frequency */
#define acmgt3__ext882__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext882 :: AVG GPU Core Frequency */
#define acmgt3__ext882__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext882 :: GPU MEMORY L3 WRITE SQIDI2 */
#define acmgt3__ext882__gpu_memory_l3_write_sqidi2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext883 :: GPU Time Elapsed */
#define acmgt3__ext883__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext883 :: GPU Core Clocks */
#define acmgt3__ext883__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext883 :: AVG GPU Core Frequency */
#define acmgt3__ext883__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext883 :: AVG GPU Core Frequency */
#define acmgt3__ext883__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext883 :: GPU MEMORY L3 WRITE SQIDI3 */
#define acmgt3__ext883__gpu_memory_l3_write_sqidi3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext884 :: GPU Time Elapsed */
#define acmgt3__ext884__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext884 :: GPU Core Clocks */
#define acmgt3__ext884__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext884 :: AVG GPU Core Frequency */
#define acmgt3__ext884__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext884 :: AVG GPU Core Frequency */
#define acmgt3__ext884__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext884 :: GPU MEMORY L3 WRITE SQIDI4 */
#define acmgt3__ext884__gpu_memory_l3_write_sqidi4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext885 :: GPU Time Elapsed */
#define acmgt3__ext885__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext885 :: GPU Core Clocks */
#define acmgt3__ext885__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext885 :: AVG GPU Core Frequency */
#define acmgt3__ext885__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext885 :: AVG GPU Core Frequency */
#define acmgt3__ext885__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext885 :: GPU MEMORY L3 WRITE SQIDI5 */
#define acmgt3__ext885__gpu_memory_l3_write_sqidi5__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext886 :: GPU Time Elapsed */
#define acmgt3__ext886__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext886 :: GPU Core Clocks */
#define acmgt3__ext886__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext886 :: AVG GPU Core Frequency */
#define acmgt3__ext886__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext886 :: AVG GPU Core Frequency */
#define acmgt3__ext886__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext886 :: GPU MEMORY L3 WRITE SQIDI6 */
#define acmgt3__ext886__gpu_memory_l3_write_sqidi6__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext887 :: GPU Time Elapsed */
#define acmgt3__ext887__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext887 :: GPU Core Clocks */
#define acmgt3__ext887__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext887 :: AVG GPU Core Frequency */
#define acmgt3__ext887__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext887 :: AVG GPU Core Frequency */
#define acmgt3__ext887__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext887 :: GPU MEMORY L3 WRITE SQIDI7 */
#define acmgt3__ext887__gpu_memory_l3_write_sqidi7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext888 :: GPU Time Elapsed */
#define acmgt3__ext888__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext888 :: GPU Core Clocks */
#define acmgt3__ext888__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext888 :: AVG GPU Core Frequency */
#define acmgt3__ext888__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext888 :: AVG GPU Core Frequency */
#define acmgt3__ext888__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext888 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE0 */
#define acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore0__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext888 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE1 */
#define acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore1__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext888 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE2 */
#define acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore2__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext888 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE3 */
#define acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore3__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext889 :: GPU Time Elapsed */
#define acmgt3__ext889__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext889 :: GPU Core Clocks */
#define acmgt3__ext889__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext889 :: AVG GPU Core Frequency */
#define acmgt3__ext889__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext889 :: AVG GPU Core Frequency */
#define acmgt3__ext889__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext889 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE4 */
#define acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore4__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext889 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE5 */
#define acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore5__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext889 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE6 */
#define acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore6__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext889 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE7 */
#define acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore7__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext890 :: GPU Time Elapsed */
#define acmgt3__ext890__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext890 :: GPU Core Clocks */
#define acmgt3__ext890__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext890 :: AVG GPU Core Frequency */
#define acmgt3__ext890__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext890 :: AVG GPU Core Frequency */
#define acmgt3__ext890__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext890 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE8 */
#define acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore8__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext890 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE9 */
#define acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore9__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext890 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE10 */
#define acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore10__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext890 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE11 */
#define acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore11__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext891 :: GPU Time Elapsed */
#define acmgt3__ext891__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext891 :: GPU Core Clocks */
#define acmgt3__ext891__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext891 :: AVG GPU Core Frequency */
#define acmgt3__ext891__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext891 :: AVG GPU Core Frequency */
#define acmgt3__ext891__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext891 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE12 */
#define acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore12__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext891 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE13 */
#define acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore13__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext891 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE14 */
#define acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore14__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext891 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE15 */
#define acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore15__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext892 :: GPU Time Elapsed */
#define acmgt3__ext892__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext892 :: GPU Core Clocks */
#define acmgt3__ext892__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext892 :: AVG GPU Core Frequency */
#define acmgt3__ext892__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext892 :: AVG GPU Core Frequency */
#define acmgt3__ext892__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext892 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE16 */
#define acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore16__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext892 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE17 */
#define acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore17__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext892 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE18 */
#define acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore18__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext892 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE19 */
#define acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore19__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext893 :: GPU Time Elapsed */
#define acmgt3__ext893__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext893 :: GPU Core Clocks */
#define acmgt3__ext893__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext893 :: AVG GPU Core Frequency */
#define acmgt3__ext893__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext893 :: AVG GPU Core Frequency */
#define acmgt3__ext893__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext893 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE20 */
#define acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore20__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext893 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE21 */
#define acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore21__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext893 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE22 */
#define acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore22__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext893 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE23 */
#define acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore23__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext894 :: GPU Time Elapsed */
#define acmgt3__ext894__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext894 :: GPU Core Clocks */
#define acmgt3__ext894__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext894 :: AVG GPU Core Frequency */
#define acmgt3__ext894__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext894 :: AVG GPU Core Frequency */
#define acmgt3__ext894__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext894 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE24 */
#define acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore24__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext894 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE25 */
#define acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore25__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext894 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE26 */
#define acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore26__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext894 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE27 */
#define acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore27__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext895 :: GPU Time Elapsed */
#define acmgt3__ext895__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext895 :: GPU Core Clocks */
#define acmgt3__ext895__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext895 :: AVG GPU Core Frequency */
#define acmgt3__ext895__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext895 :: AVG GPU Core Frequency */
#define acmgt3__ext895__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext895 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE28 */
#define acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore28__read \
   acmgt1__threads_and_rast3__gs_threads__read

/* Ext895 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE29 */
#define acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore29__read \
   acmgt1__ext21__load_store_cache_access_xecore1__read

/* Ext895 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE30 */
#define acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore30__read \
   acmgt1__threads_and_rast1__hs_threads__read

/* Ext895 :: LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE31 */
#define acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore31__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext896 :: GPU Time Elapsed */
#define acmgt3__ext896__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext896 :: GPU Core Clocks */
#define acmgt3__ext896__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext896 :: AVG GPU Core Frequency */
#define acmgt3__ext896__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext896 :: AVG GPU Core Frequency */
#define acmgt3__ext896__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext896 :: ICACHE HIT BANK0 XECORE0 */
#define acmgt3__ext896__icache_hit_bank0_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext896 :: ICACHE HIT BANK0 XECORE1 */
#define acmgt3__ext896__icache_hit_bank0_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext896 :: ICACHE HIT BANK0 XECORE2 */
#define acmgt3__ext896__icache_hit_bank0_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext896 :: ICACHE HIT BANK0 XECORE3 */
#define acmgt3__ext896__icache_hit_bank0_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext896 :: ICACHE HIT BANK0 XECORE4 */
#define acmgt3__ext896__icache_hit_bank0_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext896 :: ICACHE HIT BANK0 XECORE5 */
#define acmgt3__ext896__icache_hit_bank0_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext896 :: ICACHE HIT BANK0 XECORE6 */
#define acmgt3__ext896__icache_hit_bank0_xecore6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext896 :: ICACHE HIT BANK0 XECORE7 */
#define acmgt3__ext896__icache_hit_bank0_xecore7__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext896 :: ICACHE MISS BANK0 XECORE0 */
#define acmgt3__ext896__icache_miss_bank0_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext896 :: ICACHE MISS BANK0 XECORE1 */
#define acmgt3__ext896__icache_miss_bank0_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext896 :: ICACHE MISS BANK0 XECORE2 */
#define acmgt3__ext896__icache_miss_bank0_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext896 :: ICACHE MISS BANK0 XECORE3 */
#define acmgt3__ext896__icache_miss_bank0_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext896 :: ICACHE MISS BANK0 XECORE4 */
#define acmgt3__ext896__icache_miss_bank0_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext896 :: ICACHE MISS BANK0 XECORE5 */
#define acmgt3__ext896__icache_miss_bank0_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext896 :: ICACHE MISS BANK0 XECORE6 */
#define acmgt3__ext896__icache_miss_bank0_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext896 :: ICACHE MISS BANK0 XECORE7 */
#define acmgt3__ext896__icache_miss_bank0_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext897 :: GPU Time Elapsed */
#define acmgt3__ext897__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext897 :: GPU Core Clocks */
#define acmgt3__ext897__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext897 :: AVG GPU Core Frequency */
#define acmgt3__ext897__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext897 :: AVG GPU Core Frequency */
#define acmgt3__ext897__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext897 :: ICACHE HIT BANK0 XECORE8 */
#define acmgt3__ext897__icache_hit_bank0_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext897 :: ICACHE HIT BANK0 XECORE9 */
#define acmgt3__ext897__icache_hit_bank0_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext897 :: ICACHE HIT BANK0 XECORE10 */
#define acmgt3__ext897__icache_hit_bank0_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext897 :: ICACHE HIT BANK0 XECORE11 */
#define acmgt3__ext897__icache_hit_bank0_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext897 :: ICACHE HIT BANK0 XECORE12 */
#define acmgt3__ext897__icache_hit_bank0_xecore12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext897 :: ICACHE HIT BANK0 XECORE13 */
#define acmgt3__ext897__icache_hit_bank0_xecore13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext897 :: ICACHE HIT BANK0 XECORE14 */
#define acmgt3__ext897__icache_hit_bank0_xecore14__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext897 :: ICACHE HIT BANK0 XECORE15 */
#define acmgt3__ext897__icache_hit_bank0_xecore15__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext897 :: ICACHE MISS BANK0 XECORE8 */
#define acmgt3__ext897__icache_miss_bank0_xecore8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext897 :: ICACHE MISS BANK0 XECORE9 */
#define acmgt3__ext897__icache_miss_bank0_xecore9__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext897 :: ICACHE MISS BANK0 XECORE10 */
#define acmgt3__ext897__icache_miss_bank0_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext897 :: ICACHE MISS BANK0 XECORE11 */
#define acmgt3__ext897__icache_miss_bank0_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext897 :: ICACHE MISS BANK0 XECORE12 */
#define acmgt3__ext897__icache_miss_bank0_xecore12__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext897 :: ICACHE MISS BANK0 XECORE13 */
#define acmgt3__ext897__icache_miss_bank0_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext897 :: ICACHE MISS BANK0 XECORE14 */
#define acmgt3__ext897__icache_miss_bank0_xecore14__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext897 :: ICACHE MISS BANK0 XECORE15 */
#define acmgt3__ext897__icache_miss_bank0_xecore15__read \
   hsw__compute_extended__typed_writes0__read

/* Ext898 :: GPU Time Elapsed */
#define acmgt3__ext898__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext898 :: GPU Core Clocks */
#define acmgt3__ext898__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext898 :: AVG GPU Core Frequency */
#define acmgt3__ext898__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext898 :: AVG GPU Core Frequency */
#define acmgt3__ext898__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext898 :: ICACHE HIT BANK0 XECORE16 */
#define acmgt3__ext898__icache_hit_bank0_xecore16__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext898 :: ICACHE HIT BANK0 XECORE17 */
#define acmgt3__ext898__icache_hit_bank0_xecore17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext898 :: ICACHE HIT BANK0 XECORE18 */
#define acmgt3__ext898__icache_hit_bank0_xecore18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext898 :: ICACHE HIT BANK0 XECORE19 */
#define acmgt3__ext898__icache_hit_bank0_xecore19__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext898 :: ICACHE HIT BANK0 XECORE20 */
#define acmgt3__ext898__icache_hit_bank0_xecore20__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext898 :: ICACHE HIT BANK0 XECORE21 */
#define acmgt3__ext898__icache_hit_bank0_xecore21__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext898 :: ICACHE HIT BANK0 XECORE22 */
#define acmgt3__ext898__icache_hit_bank0_xecore22__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext898 :: ICACHE HIT BANK0 XECORE23 */
#define acmgt3__ext898__icache_hit_bank0_xecore23__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext898 :: ICACHE MISS BANK0 XECORE16 */
#define acmgt3__ext898__icache_miss_bank0_xecore16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext898 :: ICACHE MISS BANK0 XECORE17 */
#define acmgt3__ext898__icache_miss_bank0_xecore17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext898 :: ICACHE MISS BANK0 XECORE18 */
#define acmgt3__ext898__icache_miss_bank0_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext898 :: ICACHE MISS BANK0 XECORE19 */
#define acmgt3__ext898__icache_miss_bank0_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext898 :: ICACHE MISS BANK0 XECORE20 */
#define acmgt3__ext898__icache_miss_bank0_xecore20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext898 :: ICACHE MISS BANK0 XECORE21 */
#define acmgt3__ext898__icache_miss_bank0_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext898 :: ICACHE MISS BANK0 XECORE22 */
#define acmgt3__ext898__icache_miss_bank0_xecore22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext898 :: ICACHE MISS BANK0 XECORE23 */
#define acmgt3__ext898__icache_miss_bank0_xecore23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext899 :: GPU Time Elapsed */
#define acmgt3__ext899__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext899 :: GPU Core Clocks */
#define acmgt3__ext899__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext899 :: AVG GPU Core Frequency */
#define acmgt3__ext899__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext899 :: AVG GPU Core Frequency */
#define acmgt3__ext899__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext899 :: ICACHE HIT BANK0 XECORE24 */
#define acmgt3__ext899__icache_hit_bank0_xecore24__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext899 :: ICACHE HIT BANK0 XECORE25 */
#define acmgt3__ext899__icache_hit_bank0_xecore25__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext899 :: ICACHE HIT BANK0 XECORE26 */
#define acmgt3__ext899__icache_hit_bank0_xecore26__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext899 :: ICACHE HIT BANK0 XECORE27 */
#define acmgt3__ext899__icache_hit_bank0_xecore27__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext899 :: ICACHE HIT BANK0 XECORE28 */
#define acmgt3__ext899__icache_hit_bank0_xecore28__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext899 :: ICACHE HIT BANK0 XECORE29 */
#define acmgt3__ext899__icache_hit_bank0_xecore29__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext899 :: ICACHE HIT BANK0 XECORE30 */
#define acmgt3__ext899__icache_hit_bank0_xecore30__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext899 :: ICACHE HIT BANK0 XECORE31 */
#define acmgt3__ext899__icache_hit_bank0_xecore31__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext899 :: ICACHE MISS BANK0 XECORE24 */
#define acmgt3__ext899__icache_miss_bank0_xecore24__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext899 :: ICACHE MISS BANK0 XECORE25 */
#define acmgt3__ext899__icache_miss_bank0_xecore25__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext899 :: ICACHE MISS BANK0 XECORE26 */
#define acmgt3__ext899__icache_miss_bank0_xecore26__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext899 :: ICACHE MISS BANK0 XECORE27 */
#define acmgt3__ext899__icache_miss_bank0_xecore27__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext899 :: ICACHE MISS BANK0 XECORE28 */
#define acmgt3__ext899__icache_miss_bank0_xecore28__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext899 :: ICACHE MISS BANK0 XECORE29 */
#define acmgt3__ext899__icache_miss_bank0_xecore29__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext899 :: ICACHE MISS BANK0 XECORE30 */
#define acmgt3__ext899__icache_miss_bank0_xecore30__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext899 :: ICACHE MISS BANK0 XECORE31 */
#define acmgt3__ext899__icache_miss_bank0_xecore31__read \
   hsw__compute_extended__typed_writes0__read

/* Ext900 :: GPU Time Elapsed */
#define acmgt3__ext900__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext900 :: GPU Core Clocks */
#define acmgt3__ext900__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext900 :: AVG GPU Core Frequency */
#define acmgt3__ext900__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext900 :: AVG GPU Core Frequency */
#define acmgt3__ext900__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext900 :: ICACHE HIT BANK1 XECORE0 */
#define acmgt3__ext900__icache_hit_bank1_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext900 :: ICACHE HIT BANK1 XECORE1 */
#define acmgt3__ext900__icache_hit_bank1_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext900 :: ICACHE HIT BANK1 XECORE2 */
#define acmgt3__ext900__icache_hit_bank1_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext900 :: ICACHE HIT BANK1 XECORE3 */
#define acmgt3__ext900__icache_hit_bank1_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext900 :: ICACHE HIT BANK1 XECORE4 */
#define acmgt3__ext900__icache_hit_bank1_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext900 :: ICACHE HIT BANK1 XECORE5 */
#define acmgt3__ext900__icache_hit_bank1_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext900 :: ICACHE HIT BANK1 XECORE6 */
#define acmgt3__ext900__icache_hit_bank1_xecore6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext900 :: ICACHE HIT BANK1 XECORE7 */
#define acmgt3__ext900__icache_hit_bank1_xecore7__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext900 :: ICACHE MISS BANK1 XECORE0 */
#define acmgt3__ext900__icache_miss_bank1_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext900 :: ICACHE MISS BANK1 XECORE1 */
#define acmgt3__ext900__icache_miss_bank1_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext900 :: ICACHE MISS BANK1 XECORE2 */
#define acmgt3__ext900__icache_miss_bank1_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext900 :: ICACHE MISS BANK1 XECORE3 */
#define acmgt3__ext900__icache_miss_bank1_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext900 :: ICACHE MISS BANK1 XECORE4 */
#define acmgt3__ext900__icache_miss_bank1_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext900 :: ICACHE MISS BANK1 XECORE5 */
#define acmgt3__ext900__icache_miss_bank1_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext900 :: ICACHE MISS BANK1 XECORE6 */
#define acmgt3__ext900__icache_miss_bank1_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext900 :: ICACHE MISS BANK1 XECORE7 */
#define acmgt3__ext900__icache_miss_bank1_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext901 :: GPU Time Elapsed */
#define acmgt3__ext901__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext901 :: GPU Core Clocks */
#define acmgt3__ext901__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext901 :: AVG GPU Core Frequency */
#define acmgt3__ext901__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext901 :: AVG GPU Core Frequency */
#define acmgt3__ext901__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext901 :: ICACHE HIT BANK1 XECORE8 */
#define acmgt3__ext901__icache_hit_bank1_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext901 :: ICACHE HIT BANK1 XECORE9 */
#define acmgt3__ext901__icache_hit_bank1_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext901 :: ICACHE HIT BANK1 XECORE10 */
#define acmgt3__ext901__icache_hit_bank1_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext901 :: ICACHE HIT BANK1 XECORE11 */
#define acmgt3__ext901__icache_hit_bank1_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext901 :: ICACHE HIT BANK1 XECORE12 */
#define acmgt3__ext901__icache_hit_bank1_xecore12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext901 :: ICACHE HIT BANK1 XECORE13 */
#define acmgt3__ext901__icache_hit_bank1_xecore13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext901 :: ICACHE HIT BANK1 XECORE14 */
#define acmgt3__ext901__icache_hit_bank1_xecore14__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext901 :: ICACHE HIT BANK1 XECORE15 */
#define acmgt3__ext901__icache_hit_bank1_xecore15__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext901 :: ICACHE MISS BANK1 XECORE8 */
#define acmgt3__ext901__icache_miss_bank1_xecore8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext901 :: ICACHE MISS BANK1 XECORE9 */
#define acmgt3__ext901__icache_miss_bank1_xecore9__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext901 :: ICACHE MISS BANK1 XECORE10 */
#define acmgt3__ext901__icache_miss_bank1_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext901 :: ICACHE MISS BANK1 XECORE11 */
#define acmgt3__ext901__icache_miss_bank1_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext901 :: ICACHE MISS BANK1 XECORE12 */
#define acmgt3__ext901__icache_miss_bank1_xecore12__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext901 :: ICACHE MISS BANK1 XECORE13 */
#define acmgt3__ext901__icache_miss_bank1_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext901 :: ICACHE MISS BANK1 XECORE14 */
#define acmgt3__ext901__icache_miss_bank1_xecore14__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext901 :: ICACHE MISS BANK1 XECORE15 */
#define acmgt3__ext901__icache_miss_bank1_xecore15__read \
   hsw__compute_extended__typed_writes0__read

/* Ext902 :: GPU Time Elapsed */
#define acmgt3__ext902__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext902 :: GPU Core Clocks */
#define acmgt3__ext902__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext902 :: AVG GPU Core Frequency */
#define acmgt3__ext902__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext902 :: AVG GPU Core Frequency */
#define acmgt3__ext902__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext902 :: ICACHE HIT BANK1 XECORE16 */
#define acmgt3__ext902__icache_hit_bank1_xecore16__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext902 :: ICACHE HIT BANK1 XECORE17 */
#define acmgt3__ext902__icache_hit_bank1_xecore17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext902 :: ICACHE HIT BANK1 XECORE18 */
#define acmgt3__ext902__icache_hit_bank1_xecore18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext902 :: ICACHE HIT BANK1 XECORE19 */
#define acmgt3__ext902__icache_hit_bank1_xecore19__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext902 :: ICACHE HIT BANK1 XECORE20 */
#define acmgt3__ext902__icache_hit_bank1_xecore20__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext902 :: ICACHE HIT BANK1 XECORE21 */
#define acmgt3__ext902__icache_hit_bank1_xecore21__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext902 :: ICACHE HIT BANK1 XECORE22 */
#define acmgt3__ext902__icache_hit_bank1_xecore22__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext902 :: ICACHE HIT BANK1 XECORE23 */
#define acmgt3__ext902__icache_hit_bank1_xecore23__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext902 :: ICACHE MISS BANK1 XECORE16 */
#define acmgt3__ext902__icache_miss_bank1_xecore16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext902 :: ICACHE MISS BANK1 XECORE17 */
#define acmgt3__ext902__icache_miss_bank1_xecore17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext902 :: ICACHE MISS BANK1 XECORE18 */
#define acmgt3__ext902__icache_miss_bank1_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext902 :: ICACHE MISS BANK1 XECORE19 */
#define acmgt3__ext902__icache_miss_bank1_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext902 :: ICACHE MISS BANK1 XECORE20 */
#define acmgt3__ext902__icache_miss_bank1_xecore20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext902 :: ICACHE MISS BANK1 XECORE21 */
#define acmgt3__ext902__icache_miss_bank1_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext902 :: ICACHE MISS BANK1 XECORE22 */
#define acmgt3__ext902__icache_miss_bank1_xecore22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext902 :: ICACHE MISS BANK1 XECORE23 */
#define acmgt3__ext902__icache_miss_bank1_xecore23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext903 :: GPU Time Elapsed */
#define acmgt3__ext903__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext903 :: GPU Core Clocks */
#define acmgt3__ext903__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext903 :: AVG GPU Core Frequency */
#define acmgt3__ext903__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext903 :: AVG GPU Core Frequency */
#define acmgt3__ext903__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext903 :: ICACHE HIT BANK1 XECORE24 */
#define acmgt3__ext903__icache_hit_bank1_xecore24__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext903 :: ICACHE HIT BANK1 XECORE25 */
#define acmgt3__ext903__icache_hit_bank1_xecore25__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext903 :: ICACHE HIT BANK1 XECORE26 */
#define acmgt3__ext903__icache_hit_bank1_xecore26__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext903 :: ICACHE HIT BANK1 XECORE27 */
#define acmgt3__ext903__icache_hit_bank1_xecore27__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext903 :: ICACHE HIT BANK1 XECORE28 */
#define acmgt3__ext903__icache_hit_bank1_xecore28__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext903 :: ICACHE HIT BANK1 XECORE29 */
#define acmgt3__ext903__icache_hit_bank1_xecore29__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext903 :: ICACHE HIT BANK1 XECORE30 */
#define acmgt3__ext903__icache_hit_bank1_xecore30__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext903 :: ICACHE HIT BANK1 XECORE31 */
#define acmgt3__ext903__icache_hit_bank1_xecore31__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext903 :: ICACHE MISS BANK1 XECORE24 */
#define acmgt3__ext903__icache_miss_bank1_xecore24__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext903 :: ICACHE MISS BANK1 XECORE25 */
#define acmgt3__ext903__icache_miss_bank1_xecore25__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext903 :: ICACHE MISS BANK1 XECORE26 */
#define acmgt3__ext903__icache_miss_bank1_xecore26__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext903 :: ICACHE MISS BANK1 XECORE27 */
#define acmgt3__ext903__icache_miss_bank1_xecore27__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext903 :: ICACHE MISS BANK1 XECORE28 */
#define acmgt3__ext903__icache_miss_bank1_xecore28__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext903 :: ICACHE MISS BANK1 XECORE29 */
#define acmgt3__ext903__icache_miss_bank1_xecore29__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext903 :: ICACHE MISS BANK1 XECORE30 */
#define acmgt3__ext903__icache_miss_bank1_xecore30__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext903 :: ICACHE MISS BANK1 XECORE31 */
#define acmgt3__ext903__icache_miss_bank1_xecore31__read \
   hsw__compute_extended__typed_writes0__read

/* Ext904 :: GPU Time Elapsed */
#define acmgt3__ext904__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext904 :: GPU Core Clocks */
#define acmgt3__ext904__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext904 :: AVG GPU Core Frequency */
#define acmgt3__ext904__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext904 :: AVG GPU Core Frequency */
#define acmgt3__ext904__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext904 :: ICACHE HIT BANK2 XECORE0 */
#define acmgt3__ext904__icache_hit_bank2_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext904 :: ICACHE HIT BANK2 XECORE1 */
#define acmgt3__ext904__icache_hit_bank2_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext904 :: ICACHE HIT BANK2 XECORE2 */
#define acmgt3__ext904__icache_hit_bank2_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext904 :: ICACHE HIT BANK2 XECORE3 */
#define acmgt3__ext904__icache_hit_bank2_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext904 :: ICACHE HIT BANK2 XECORE4 */
#define acmgt3__ext904__icache_hit_bank2_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext904 :: ICACHE HIT BANK2 XECORE5 */
#define acmgt3__ext904__icache_hit_bank2_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext904 :: ICACHE HIT BANK2 XECORE6 */
#define acmgt3__ext904__icache_hit_bank2_xecore6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext904 :: ICACHE HIT BANK2 XECORE7 */
#define acmgt3__ext904__icache_hit_bank2_xecore7__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext904 :: ICACHE MISS BANK2 XECORE0 */
#define acmgt3__ext904__icache_miss_bank2_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext904 :: ICACHE MISS BANK2 XECORE1 */
#define acmgt3__ext904__icache_miss_bank2_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext904 :: ICACHE MISS BANK2 XECORE2 */
#define acmgt3__ext904__icache_miss_bank2_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext904 :: ICACHE MISS BANK2 XECORE3 */
#define acmgt3__ext904__icache_miss_bank2_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext904 :: ICACHE MISS BANK2 XECORE4 */
#define acmgt3__ext904__icache_miss_bank2_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext904 :: ICACHE MISS BANK2 XECORE5 */
#define acmgt3__ext904__icache_miss_bank2_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext904 :: ICACHE MISS BANK2 XECORE6 */
#define acmgt3__ext904__icache_miss_bank2_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext904 :: ICACHE MISS BANK2 XECORE7 */
#define acmgt3__ext904__icache_miss_bank2_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext905 :: GPU Time Elapsed */
#define acmgt3__ext905__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext905 :: GPU Core Clocks */
#define acmgt3__ext905__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext905 :: AVG GPU Core Frequency */
#define acmgt3__ext905__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext905 :: AVG GPU Core Frequency */
#define acmgt3__ext905__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext905 :: ICACHE HIT BANK2 XECORE8 */
#define acmgt3__ext905__icache_hit_bank2_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext905 :: ICACHE HIT BANK2 XECORE9 */
#define acmgt3__ext905__icache_hit_bank2_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext905 :: ICACHE HIT BANK2 XECORE10 */
#define acmgt3__ext905__icache_hit_bank2_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext905 :: ICACHE HIT BANK2 XECORE11 */
#define acmgt3__ext905__icache_hit_bank2_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext905 :: ICACHE HIT BANK2 XECORE12 */
#define acmgt3__ext905__icache_hit_bank2_xecore12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext905 :: ICACHE HIT BANK2 XECORE13 */
#define acmgt3__ext905__icache_hit_bank2_xecore13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext905 :: ICACHE HIT BANK2 XECORE14 */
#define acmgt3__ext905__icache_hit_bank2_xecore14__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext905 :: ICACHE HIT BANK2 XECORE15 */
#define acmgt3__ext905__icache_hit_bank2_xecore15__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext905 :: ICACHE MISS BANK2 XECORE8 */
#define acmgt3__ext905__icache_miss_bank2_xecore8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext905 :: ICACHE MISS BANK2 XECORE9 */
#define acmgt3__ext905__icache_miss_bank2_xecore9__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext905 :: ICACHE MISS BANK2 XECORE10 */
#define acmgt3__ext905__icache_miss_bank2_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext905 :: ICACHE MISS BANK2 XECORE11 */
#define acmgt3__ext905__icache_miss_bank2_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext905 :: ICACHE MISS BANK2 XECORE12 */
#define acmgt3__ext905__icache_miss_bank2_xecore12__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext905 :: ICACHE MISS BANK2 XECORE13 */
#define acmgt3__ext905__icache_miss_bank2_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext905 :: ICACHE MISS BANK2 XECORE14 */
#define acmgt3__ext905__icache_miss_bank2_xecore14__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext905 :: ICACHE MISS BANK2 XECORE15 */
#define acmgt3__ext905__icache_miss_bank2_xecore15__read \
   hsw__compute_extended__typed_writes0__read

/* Ext906 :: GPU Time Elapsed */
#define acmgt3__ext906__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext906 :: GPU Core Clocks */
#define acmgt3__ext906__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext906 :: AVG GPU Core Frequency */
#define acmgt3__ext906__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext906 :: AVG GPU Core Frequency */
#define acmgt3__ext906__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext906 :: ICACHE HIT BANK2 XECORE16 */
#define acmgt3__ext906__icache_hit_bank2_xecore16__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext906 :: ICACHE HIT BANK2 XECORE17 */
#define acmgt3__ext906__icache_hit_bank2_xecore17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext906 :: ICACHE HIT BANK2 XECORE18 */
#define acmgt3__ext906__icache_hit_bank2_xecore18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext906 :: ICACHE HIT BANK2 XECORE19 */
#define acmgt3__ext906__icache_hit_bank2_xecore19__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext906 :: ICACHE HIT BANK2 XECORE20 */
#define acmgt3__ext906__icache_hit_bank2_xecore20__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext906 :: ICACHE HIT BANK2 XECORE21 */
#define acmgt3__ext906__icache_hit_bank2_xecore21__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext906 :: ICACHE HIT BANK2 XECORE22 */
#define acmgt3__ext906__icache_hit_bank2_xecore22__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext906 :: ICACHE HIT BANK2 XECORE23 */
#define acmgt3__ext906__icache_hit_bank2_xecore23__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext906 :: ICACHE MISS BANK2 XECORE16 */
#define acmgt3__ext906__icache_miss_bank2_xecore16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext906 :: ICACHE MISS BANK2 XECORE17 */
#define acmgt3__ext906__icache_miss_bank2_xecore17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext906 :: ICACHE MISS BANK2 XECORE18 */
#define acmgt3__ext906__icache_miss_bank2_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext906 :: ICACHE MISS BANK2 XECORE19 */
#define acmgt3__ext906__icache_miss_bank2_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext906 :: ICACHE MISS BANK2 XECORE20 */
#define acmgt3__ext906__icache_miss_bank2_xecore20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext906 :: ICACHE MISS BANK2 XECORE21 */
#define acmgt3__ext906__icache_miss_bank2_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext906 :: ICACHE MISS BANK2 XECORE22 */
#define acmgt3__ext906__icache_miss_bank2_xecore22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext906 :: ICACHE MISS BANK2 XECORE23 */
#define acmgt3__ext906__icache_miss_bank2_xecore23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext907 :: GPU Time Elapsed */
#define acmgt3__ext907__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext907 :: GPU Core Clocks */
#define acmgt3__ext907__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext907 :: AVG GPU Core Frequency */
#define acmgt3__ext907__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext907 :: AVG GPU Core Frequency */
#define acmgt3__ext907__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext907 :: ICACHE HIT BANK2 XECORE24 */
#define acmgt3__ext907__icache_hit_bank2_xecore24__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext907 :: ICACHE HIT BANK2 XECORE25 */
#define acmgt3__ext907__icache_hit_bank2_xecore25__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext907 :: ICACHE HIT BANK2 XECORE26 */
#define acmgt3__ext907__icache_hit_bank2_xecore26__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext907 :: ICACHE HIT BANK2 XECORE27 */
#define acmgt3__ext907__icache_hit_bank2_xecore27__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext907 :: ICACHE HIT BANK2 XECORE28 */
#define acmgt3__ext907__icache_hit_bank2_xecore28__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext907 :: ICACHE HIT BANK2 XECORE29 */
#define acmgt3__ext907__icache_hit_bank2_xecore29__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext907 :: ICACHE HIT BANK2 XECORE30 */
#define acmgt3__ext907__icache_hit_bank2_xecore30__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext907 :: ICACHE HIT BANK2 XECORE31 */
#define acmgt3__ext907__icache_hit_bank2_xecore31__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext907 :: ICACHE MISS BANK2 XECORE24 */
#define acmgt3__ext907__icache_miss_bank2_xecore24__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext907 :: ICACHE MISS BANK2 XECORE25 */
#define acmgt3__ext907__icache_miss_bank2_xecore25__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext907 :: ICACHE MISS BANK2 XECORE26 */
#define acmgt3__ext907__icache_miss_bank2_xecore26__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext907 :: ICACHE MISS BANK2 XECORE27 */
#define acmgt3__ext907__icache_miss_bank2_xecore27__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext907 :: ICACHE MISS BANK2 XECORE28 */
#define acmgt3__ext907__icache_miss_bank2_xecore28__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext907 :: ICACHE MISS BANK2 XECORE29 */
#define acmgt3__ext907__icache_miss_bank2_xecore29__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext907 :: ICACHE MISS BANK2 XECORE30 */
#define acmgt3__ext907__icache_miss_bank2_xecore30__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext907 :: ICACHE MISS BANK2 XECORE31 */
#define acmgt3__ext907__icache_miss_bank2_xecore31__read \
   hsw__compute_extended__typed_writes0__read

/* Ext908 :: GPU Time Elapsed */
#define acmgt3__ext908__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext908 :: GPU Core Clocks */
#define acmgt3__ext908__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext908 :: AVG GPU Core Frequency */
#define acmgt3__ext908__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext908 :: AVG GPU Core Frequency */
#define acmgt3__ext908__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext908 :: ICACHE HIT BANK3 XECORE0 */
#define acmgt3__ext908__icache_hit_bank3_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext908 :: ICACHE HIT BANK3 XECORE1 */
#define acmgt3__ext908__icache_hit_bank3_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext908 :: ICACHE HIT BANK3 XECORE2 */
#define acmgt3__ext908__icache_hit_bank3_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext908 :: ICACHE HIT BANK3 XECORE3 */
#define acmgt3__ext908__icache_hit_bank3_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext908 :: ICACHE HIT BANK3 XECORE4 */
#define acmgt3__ext908__icache_hit_bank3_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext908 :: ICACHE HIT BANK3 XECORE5 */
#define acmgt3__ext908__icache_hit_bank3_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext908 :: ICACHE HIT BANK3 XECORE6 */
#define acmgt3__ext908__icache_hit_bank3_xecore6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext908 :: ICACHE HIT BANK3 XECORE7 */
#define acmgt3__ext908__icache_hit_bank3_xecore7__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext908 :: ICACHE MISS BANK3 XECORE0 */
#define acmgt3__ext908__icache_miss_bank3_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext908 :: ICACHE MISS BANK3 XECORE1 */
#define acmgt3__ext908__icache_miss_bank3_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext908 :: ICACHE MISS BANK3 XECORE2 */
#define acmgt3__ext908__icache_miss_bank3_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext908 :: ICACHE MISS BANK3 XECORE3 */
#define acmgt3__ext908__icache_miss_bank3_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext908 :: ICACHE MISS BANK3 XECORE4 */
#define acmgt3__ext908__icache_miss_bank3_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext908 :: ICACHE MISS BANK3 XECORE5 */
#define acmgt3__ext908__icache_miss_bank3_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext908 :: ICACHE MISS BANK3 XECORE6 */
#define acmgt3__ext908__icache_miss_bank3_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext908 :: ICACHE MISS BANK3 XECORE7 */
#define acmgt3__ext908__icache_miss_bank3_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext909 :: GPU Time Elapsed */
#define acmgt3__ext909__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext909 :: GPU Core Clocks */
#define acmgt3__ext909__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext909 :: AVG GPU Core Frequency */
#define acmgt3__ext909__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext909 :: AVG GPU Core Frequency */
#define acmgt3__ext909__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext909 :: ICACHE HIT BANK3 XECORE8 */
#define acmgt3__ext909__icache_hit_bank3_xecore8__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext909 :: ICACHE HIT BANK3 XECORE9 */
#define acmgt3__ext909__icache_hit_bank3_xecore9__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext909 :: ICACHE HIT BANK3 XECORE10 */
#define acmgt3__ext909__icache_hit_bank3_xecore10__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext909 :: ICACHE HIT BANK3 XECORE11 */
#define acmgt3__ext909__icache_hit_bank3_xecore11__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext909 :: ICACHE HIT BANK3 XECORE12 */
#define acmgt3__ext909__icache_hit_bank3_xecore12__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext909 :: ICACHE HIT BANK3 XECORE13 */
#define acmgt3__ext909__icache_hit_bank3_xecore13__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext909 :: ICACHE HIT BANK3 XECORE14 */
#define acmgt3__ext909__icache_hit_bank3_xecore14__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext909 :: ICACHE HIT BANK3 XECORE15 */
#define acmgt3__ext909__icache_hit_bank3_xecore15__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext909 :: ICACHE MISS BANK3 XECORE8 */
#define acmgt3__ext909__icache_miss_bank3_xecore8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext909 :: ICACHE MISS BANK3 XECORE9 */
#define acmgt3__ext909__icache_miss_bank3_xecore9__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext909 :: ICACHE MISS BANK3 XECORE10 */
#define acmgt3__ext909__icache_miss_bank3_xecore10__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext909 :: ICACHE MISS BANK3 XECORE11 */
#define acmgt3__ext909__icache_miss_bank3_xecore11__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext909 :: ICACHE MISS BANK3 XECORE12 */
#define acmgt3__ext909__icache_miss_bank3_xecore12__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext909 :: ICACHE MISS BANK3 XECORE13 */
#define acmgt3__ext909__icache_miss_bank3_xecore13__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext909 :: ICACHE MISS BANK3 XECORE14 */
#define acmgt3__ext909__icache_miss_bank3_xecore14__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext909 :: ICACHE MISS BANK3 XECORE15 */
#define acmgt3__ext909__icache_miss_bank3_xecore15__read \
   hsw__compute_extended__typed_writes0__read

/* Ext910 :: GPU Time Elapsed */
#define acmgt3__ext910__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext910 :: GPU Core Clocks */
#define acmgt3__ext910__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext910 :: AVG GPU Core Frequency */
#define acmgt3__ext910__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext910 :: AVG GPU Core Frequency */
#define acmgt3__ext910__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext910 :: ICACHE HIT BANK3 XECORE16 */
#define acmgt3__ext910__icache_hit_bank3_xecore16__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext910 :: ICACHE HIT BANK3 XECORE17 */
#define acmgt3__ext910__icache_hit_bank3_xecore17__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext910 :: ICACHE HIT BANK3 XECORE18 */
#define acmgt3__ext910__icache_hit_bank3_xecore18__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext910 :: ICACHE HIT BANK3 XECORE19 */
#define acmgt3__ext910__icache_hit_bank3_xecore19__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext910 :: ICACHE HIT BANK3 XECORE20 */
#define acmgt3__ext910__icache_hit_bank3_xecore20__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext910 :: ICACHE HIT BANK3 XECORE21 */
#define acmgt3__ext910__icache_hit_bank3_xecore21__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext910 :: ICACHE HIT BANK3 XECORE22 */
#define acmgt3__ext910__icache_hit_bank3_xecore22__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext910 :: ICACHE HIT BANK3 XECORE23 */
#define acmgt3__ext910__icache_hit_bank3_xecore23__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext910 :: ICACHE MISS BANK3 XECORE16 */
#define acmgt3__ext910__icache_miss_bank3_xecore16__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext910 :: ICACHE MISS BANK3 XECORE17 */
#define acmgt3__ext910__icache_miss_bank3_xecore17__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext910 :: ICACHE MISS BANK3 XECORE18 */
#define acmgt3__ext910__icache_miss_bank3_xecore18__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext910 :: ICACHE MISS BANK3 XECORE19 */
#define acmgt3__ext910__icache_miss_bank3_xecore19__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext910 :: ICACHE MISS BANK3 XECORE20 */
#define acmgt3__ext910__icache_miss_bank3_xecore20__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext910 :: ICACHE MISS BANK3 XECORE21 */
#define acmgt3__ext910__icache_miss_bank3_xecore21__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext910 :: ICACHE MISS BANK3 XECORE22 */
#define acmgt3__ext910__icache_miss_bank3_xecore22__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext910 :: ICACHE MISS BANK3 XECORE23 */
#define acmgt3__ext910__icache_miss_bank3_xecore23__read \
   hsw__compute_extended__typed_writes0__read

/* Ext911 :: GPU Time Elapsed */
#define acmgt3__ext911__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext911 :: GPU Core Clocks */
#define acmgt3__ext911__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext911 :: AVG GPU Core Frequency */
#define acmgt3__ext911__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext911 :: AVG GPU Core Frequency */
#define acmgt3__ext911__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext911 :: ICACHE HIT BANK3 XECORE24 */
#define acmgt3__ext911__icache_hit_bank3_xecore24__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext911 :: ICACHE HIT BANK3 XECORE25 */
#define acmgt3__ext911__icache_hit_bank3_xecore25__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext911 :: ICACHE HIT BANK3 XECORE26 */
#define acmgt3__ext911__icache_hit_bank3_xecore26__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext911 :: ICACHE HIT BANK3 XECORE27 */
#define acmgt3__ext911__icache_hit_bank3_xecore27__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext911 :: ICACHE HIT BANK3 XECORE28 */
#define acmgt3__ext911__icache_hit_bank3_xecore28__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext911 :: ICACHE HIT BANK3 XECORE29 */
#define acmgt3__ext911__icache_hit_bank3_xecore29__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext911 :: ICACHE HIT BANK3 XECORE30 */
#define acmgt3__ext911__icache_hit_bank3_xecore30__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext911 :: ICACHE HIT BANK3 XECORE31 */
#define acmgt3__ext911__icache_hit_bank3_xecore31__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext911 :: ICACHE MISS BANK3 XECORE24 */
#define acmgt3__ext911__icache_miss_bank3_xecore24__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext911 :: ICACHE MISS BANK3 XECORE25 */
#define acmgt3__ext911__icache_miss_bank3_xecore25__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext911 :: ICACHE MISS BANK3 XECORE26 */
#define acmgt3__ext911__icache_miss_bank3_xecore26__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext911 :: ICACHE MISS BANK3 XECORE27 */
#define acmgt3__ext911__icache_miss_bank3_xecore27__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext911 :: ICACHE MISS BANK3 XECORE28 */
#define acmgt3__ext911__icache_miss_bank3_xecore28__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext911 :: ICACHE MISS BANK3 XECORE29 */
#define acmgt3__ext911__icache_miss_bank3_xecore29__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext911 :: ICACHE MISS BANK3 XECORE30 */
#define acmgt3__ext911__icache_miss_bank3_xecore30__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext911 :: ICACHE MISS BANK3 XECORE31 */
#define acmgt3__ext911__icache_miss_bank3_xecore31__read \
   hsw__compute_extended__typed_writes0__read

/* Ext912 :: GPU Time Elapsed */
#define acmgt3__ext912__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext912 :: GPU Core Clocks */
#define acmgt3__ext912__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext912 :: AVG GPU Core Frequency */
#define acmgt3__ext912__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext912 :: AVG GPU Core Frequency */
#define acmgt3__ext912__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext912 :: SLM BANK CONFLICT COUNT XECORE0 */
#define acmgt3__ext912__slm_bank_conflict_count_xecore0__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext913 :: GPU Time Elapsed */
#define acmgt3__ext913__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext913 :: GPU Core Clocks */
#define acmgt3__ext913__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext913 :: AVG GPU Core Frequency */
#define acmgt3__ext913__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext913 :: AVG GPU Core Frequency */
#define acmgt3__ext913__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext913 :: SLM BANK CONFLICT COUNT XECORE1 */
#define acmgt3__ext913__slm_bank_conflict_count_xecore1__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext914 :: GPU Time Elapsed */
#define acmgt3__ext914__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext914 :: GPU Core Clocks */
#define acmgt3__ext914__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext914 :: AVG GPU Core Frequency */
#define acmgt3__ext914__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext914 :: AVG GPU Core Frequency */
#define acmgt3__ext914__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext914 :: SLM BANK CONFLICT COUNT XECORE2 */
#define acmgt3__ext914__slm_bank_conflict_count_xecore2__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext915 :: GPU Time Elapsed */
#define acmgt3__ext915__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext915 :: GPU Core Clocks */
#define acmgt3__ext915__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext915 :: AVG GPU Core Frequency */
#define acmgt3__ext915__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext915 :: AVG GPU Core Frequency */
#define acmgt3__ext915__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext915 :: SLM BANK CONFLICT COUNT XECORE3 */
#define acmgt3__ext915__slm_bank_conflict_count_xecore3__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext916 :: GPU Time Elapsed */
#define acmgt3__ext916__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext916 :: GPU Core Clocks */
#define acmgt3__ext916__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext916 :: AVG GPU Core Frequency */
#define acmgt3__ext916__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext916 :: AVG GPU Core Frequency */
#define acmgt3__ext916__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext916 :: SLM BANK CONFLICT COUNT XECORE4 */
#define acmgt3__ext916__slm_bank_conflict_count_xecore4__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext917 :: GPU Time Elapsed */
#define acmgt3__ext917__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext917 :: GPU Core Clocks */
#define acmgt3__ext917__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext917 :: AVG GPU Core Frequency */
#define acmgt3__ext917__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext917 :: AVG GPU Core Frequency */
#define acmgt3__ext917__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext917 :: SLM BANK CONFLICT COUNT XECORE5 */
#define acmgt3__ext917__slm_bank_conflict_count_xecore5__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext918 :: GPU Time Elapsed */
#define acmgt3__ext918__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext918 :: GPU Core Clocks */
#define acmgt3__ext918__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext918 :: AVG GPU Core Frequency */
#define acmgt3__ext918__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext918 :: AVG GPU Core Frequency */
#define acmgt3__ext918__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext918 :: SLM BANK CONFLICT COUNT XECORE6 */
#define acmgt3__ext918__slm_bank_conflict_count_xecore6__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext919 :: GPU Time Elapsed */
#define acmgt3__ext919__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext919 :: GPU Core Clocks */
#define acmgt3__ext919__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext919 :: AVG GPU Core Frequency */
#define acmgt3__ext919__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext919 :: AVG GPU Core Frequency */
#define acmgt3__ext919__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext919 :: SLM BANK CONFLICT COUNT XECORE7 */
#define acmgt3__ext919__slm_bank_conflict_count_xecore7__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext920 :: GPU Time Elapsed */
#define acmgt3__ext920__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext920 :: GPU Core Clocks */
#define acmgt3__ext920__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext920 :: AVG GPU Core Frequency */
#define acmgt3__ext920__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext920 :: AVG GPU Core Frequency */
#define acmgt3__ext920__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext920 :: SLM BANK CONFLICT COUNT XECORE8 */
#define acmgt3__ext920__slm_bank_conflict_count_xecore8__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext921 :: GPU Time Elapsed */
#define acmgt3__ext921__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext921 :: GPU Core Clocks */
#define acmgt3__ext921__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext921 :: AVG GPU Core Frequency */
#define acmgt3__ext921__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext921 :: AVG GPU Core Frequency */
#define acmgt3__ext921__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext921 :: SLM BANK CONFLICT COUNT XECORE9 */
#define acmgt3__ext921__slm_bank_conflict_count_xecore9__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext922 :: GPU Time Elapsed */
#define acmgt3__ext922__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext922 :: GPU Core Clocks */
#define acmgt3__ext922__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext922 :: AVG GPU Core Frequency */
#define acmgt3__ext922__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext922 :: AVG GPU Core Frequency */
#define acmgt3__ext922__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext922 :: SLM BANK CONFLICT COUNT XECORE10 */
#define acmgt3__ext922__slm_bank_conflict_count_xecore10__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext923 :: GPU Time Elapsed */
#define acmgt3__ext923__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext923 :: GPU Core Clocks */
#define acmgt3__ext923__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext923 :: AVG GPU Core Frequency */
#define acmgt3__ext923__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext923 :: AVG GPU Core Frequency */
#define acmgt3__ext923__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext923 :: SLM BANK CONFLICT COUNT XECORE11 */
#define acmgt3__ext923__slm_bank_conflict_count_xecore11__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext924 :: GPU Time Elapsed */
#define acmgt3__ext924__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext924 :: GPU Core Clocks */
#define acmgt3__ext924__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext924 :: AVG GPU Core Frequency */
#define acmgt3__ext924__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext924 :: AVG GPU Core Frequency */
#define acmgt3__ext924__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext924 :: SLM BANK CONFLICT COUNT XECORE12 */
#define acmgt3__ext924__slm_bank_conflict_count_xecore12__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext925 :: GPU Time Elapsed */
#define acmgt3__ext925__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext925 :: GPU Core Clocks */
#define acmgt3__ext925__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext925 :: AVG GPU Core Frequency */
#define acmgt3__ext925__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext925 :: AVG GPU Core Frequency */
#define acmgt3__ext925__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext925 :: SLM BANK CONFLICT COUNT XECORE13 */
#define acmgt3__ext925__slm_bank_conflict_count_xecore13__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext926 :: GPU Time Elapsed */
#define acmgt3__ext926__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext926 :: GPU Core Clocks */
#define acmgt3__ext926__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext926 :: AVG GPU Core Frequency */
#define acmgt3__ext926__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext926 :: AVG GPU Core Frequency */
#define acmgt3__ext926__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext926 :: SLM BANK CONFLICT COUNT XECORE14 */
#define acmgt3__ext926__slm_bank_conflict_count_xecore14__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext927 :: GPU Time Elapsed */
#define acmgt3__ext927__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext927 :: GPU Core Clocks */
#define acmgt3__ext927__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext927 :: AVG GPU Core Frequency */
#define acmgt3__ext927__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext927 :: AVG GPU Core Frequency */
#define acmgt3__ext927__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext927 :: SLM BANK CONFLICT COUNT XECORE15 */
#define acmgt3__ext927__slm_bank_conflict_count_xecore15__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext928 :: GPU Time Elapsed */
#define acmgt3__ext928__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext928 :: GPU Core Clocks */
#define acmgt3__ext928__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext928 :: AVG GPU Core Frequency */
#define acmgt3__ext928__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext928 :: AVG GPU Core Frequency */
#define acmgt3__ext928__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext928 :: SLM BANK CONFLICT COUNT XECORE16 */
#define acmgt3__ext928__slm_bank_conflict_count_xecore16__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext929 :: GPU Time Elapsed */
#define acmgt3__ext929__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext929 :: GPU Core Clocks */
#define acmgt3__ext929__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext929 :: AVG GPU Core Frequency */
#define acmgt3__ext929__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext929 :: AVG GPU Core Frequency */
#define acmgt3__ext929__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext929 :: SLM BANK CONFLICT COUNT XECORE17 */
#define acmgt3__ext929__slm_bank_conflict_count_xecore17__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext930 :: GPU Time Elapsed */
#define acmgt3__ext930__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext930 :: GPU Core Clocks */
#define acmgt3__ext930__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext930 :: AVG GPU Core Frequency */
#define acmgt3__ext930__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext930 :: AVG GPU Core Frequency */
#define acmgt3__ext930__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext930 :: SLM BANK CONFLICT COUNT XECORE18 */
#define acmgt3__ext930__slm_bank_conflict_count_xecore18__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext931 :: GPU Time Elapsed */
#define acmgt3__ext931__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext931 :: GPU Core Clocks */
#define acmgt3__ext931__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext931 :: AVG GPU Core Frequency */
#define acmgt3__ext931__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext931 :: AVG GPU Core Frequency */
#define acmgt3__ext931__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext931 :: SLM BANK CONFLICT COUNT XECORE19 */
#define acmgt3__ext931__slm_bank_conflict_count_xecore19__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext932 :: GPU Time Elapsed */
#define acmgt3__ext932__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext932 :: GPU Core Clocks */
#define acmgt3__ext932__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext932 :: AVG GPU Core Frequency */
#define acmgt3__ext932__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext932 :: AVG GPU Core Frequency */
#define acmgt3__ext932__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext932 :: SLM BANK CONFLICT COUNT XECORE20 */
#define acmgt3__ext932__slm_bank_conflict_count_xecore20__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext933 :: GPU Time Elapsed */
#define acmgt3__ext933__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext933 :: GPU Core Clocks */
#define acmgt3__ext933__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext933 :: AVG GPU Core Frequency */
#define acmgt3__ext933__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext933 :: AVG GPU Core Frequency */
#define acmgt3__ext933__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext933 :: SLM BANK CONFLICT COUNT XECORE21 */
#define acmgt3__ext933__slm_bank_conflict_count_xecore21__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext934 :: GPU Time Elapsed */
#define acmgt3__ext934__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext934 :: GPU Core Clocks */
#define acmgt3__ext934__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext934 :: AVG GPU Core Frequency */
#define acmgt3__ext934__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext934 :: AVG GPU Core Frequency */
#define acmgt3__ext934__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext934 :: SLM BANK CONFLICT COUNT XECORE22 */
#define acmgt3__ext934__slm_bank_conflict_count_xecore22__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext935 :: GPU Time Elapsed */
#define acmgt3__ext935__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext935 :: GPU Core Clocks */
#define acmgt3__ext935__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext935 :: AVG GPU Core Frequency */
#define acmgt3__ext935__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext935 :: AVG GPU Core Frequency */
#define acmgt3__ext935__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext935 :: SLM BANK CONFLICT COUNT XECORE23 */
#define acmgt3__ext935__slm_bank_conflict_count_xecore23__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext936 :: GPU Time Elapsed */
#define acmgt3__ext936__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext936 :: GPU Core Clocks */
#define acmgt3__ext936__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext936 :: AVG GPU Core Frequency */
#define acmgt3__ext936__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext936 :: AVG GPU Core Frequency */
#define acmgt3__ext936__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext936 :: SLM BANK CONFLICT COUNT XECORE24 */
#define acmgt3__ext936__slm_bank_conflict_count_xecore24__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext937 :: GPU Time Elapsed */
#define acmgt3__ext937__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext937 :: GPU Core Clocks */
#define acmgt3__ext937__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext937 :: AVG GPU Core Frequency */
#define acmgt3__ext937__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext937 :: AVG GPU Core Frequency */
#define acmgt3__ext937__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext937 :: SLM BANK CONFLICT COUNT XECORE25 */
#define acmgt3__ext937__slm_bank_conflict_count_xecore25__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext938 :: GPU Time Elapsed */
#define acmgt3__ext938__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext938 :: GPU Core Clocks */
#define acmgt3__ext938__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext938 :: AVG GPU Core Frequency */
#define acmgt3__ext938__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext938 :: AVG GPU Core Frequency */
#define acmgt3__ext938__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext938 :: SLM BANK CONFLICT COUNT XECORE26 */
#define acmgt3__ext938__slm_bank_conflict_count_xecore26__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext939 :: GPU Time Elapsed */
#define acmgt3__ext939__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext939 :: GPU Core Clocks */
#define acmgt3__ext939__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext939 :: AVG GPU Core Frequency */
#define acmgt3__ext939__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext939 :: AVG GPU Core Frequency */
#define acmgt3__ext939__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext939 :: SLM BANK CONFLICT COUNT XECORE27 */
#define acmgt3__ext939__slm_bank_conflict_count_xecore27__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext940 :: GPU Time Elapsed */
#define acmgt3__ext940__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext940 :: GPU Core Clocks */
#define acmgt3__ext940__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext940 :: AVG GPU Core Frequency */
#define acmgt3__ext940__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext940 :: AVG GPU Core Frequency */
#define acmgt3__ext940__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext940 :: SLM BANK CONFLICT COUNT XECORE28 */
#define acmgt3__ext940__slm_bank_conflict_count_xecore28__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext941 :: GPU Time Elapsed */
#define acmgt3__ext941__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext941 :: GPU Core Clocks */
#define acmgt3__ext941__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext941 :: AVG GPU Core Frequency */
#define acmgt3__ext941__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext941 :: AVG GPU Core Frequency */
#define acmgt3__ext941__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext941 :: SLM BANK CONFLICT COUNT XECORE29 */
#define acmgt3__ext941__slm_bank_conflict_count_xecore29__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext942 :: GPU Time Elapsed */
#define acmgt3__ext942__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext942 :: GPU Core Clocks */
#define acmgt3__ext942__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext942 :: AVG GPU Core Frequency */
#define acmgt3__ext942__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext942 :: AVG GPU Core Frequency */
#define acmgt3__ext942__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext942 :: SLM BANK CONFLICT COUNT XECORE30 */
#define acmgt3__ext942__slm_bank_conflict_count_xecore30__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext943 :: GPU Time Elapsed */
#define acmgt3__ext943__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext943 :: GPU Core Clocks */
#define acmgt3__ext943__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext943 :: AVG GPU Core Frequency */
#define acmgt3__ext943__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext943 :: AVG GPU Core Frequency */
#define acmgt3__ext943__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext943 :: SLM BANK CONFLICT COUNT XECORE31 */
#define acmgt3__ext943__slm_bank_conflict_count_xecore31__read \
   acmgt1__ext229__slm_bank_conflict_count_xecore0__read

/* Ext944 :: GPU Time Elapsed */
#define acmgt3__ext944__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext944 :: GPU Core Clocks */
#define acmgt3__ext944__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext944 :: AVG GPU Core Frequency */
#define acmgt3__ext944__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext944 :: AVG GPU Core Frequency */
#define acmgt3__ext944__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext944 :: SLM BYTE READ BANK0 XECORE0 */
#define acmgt3__ext944__slm_byte_read_bank0_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext944 :: LOAD STORE CACHE BYTE READ BANK0 XECORE0 */
#define acmgt3__ext944__load_store_cache_byte_read_bank0_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext945 :: GPU Time Elapsed */
#define acmgt3__ext945__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext945 :: GPU Core Clocks */
#define acmgt3__ext945__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext945 :: AVG GPU Core Frequency */
#define acmgt3__ext945__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext945 :: AVG GPU Core Frequency */
#define acmgt3__ext945__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext945 :: SLM BYTE READ BANK0 XECORE1 */
#define acmgt3__ext945__slm_byte_read_bank0_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext945 :: LOAD STORE CACHE BYTE READ BANK0 XECORE1 */
#define acmgt3__ext945__load_store_cache_byte_read_bank0_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext946 :: GPU Time Elapsed */
#define acmgt3__ext946__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext946 :: GPU Core Clocks */
#define acmgt3__ext946__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext946 :: AVG GPU Core Frequency */
#define acmgt3__ext946__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext946 :: AVG GPU Core Frequency */
#define acmgt3__ext946__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext946 :: SLM BYTE READ BANK0 XECORE2 */
#define acmgt3__ext946__slm_byte_read_bank0_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext946 :: LOAD STORE CACHE BYTE READ BANK0 XECORE2 */
#define acmgt3__ext946__load_store_cache_byte_read_bank0_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext947 :: GPU Time Elapsed */
#define acmgt3__ext947__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext947 :: GPU Core Clocks */
#define acmgt3__ext947__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext947 :: AVG GPU Core Frequency */
#define acmgt3__ext947__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext947 :: AVG GPU Core Frequency */
#define acmgt3__ext947__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext947 :: SLM BYTE READ BANK0 XECORE3 */
#define acmgt3__ext947__slm_byte_read_bank0_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext947 :: LOAD STORE CACHE BYTE READ BANK0 XECORE3 */
#define acmgt3__ext947__load_store_cache_byte_read_bank0_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext948 :: GPU Time Elapsed */
#define acmgt3__ext948__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext948 :: GPU Core Clocks */
#define acmgt3__ext948__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext948 :: AVG GPU Core Frequency */
#define acmgt3__ext948__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext948 :: AVG GPU Core Frequency */
#define acmgt3__ext948__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext948 :: SLM BYTE READ BANK1 XECORE0 */
#define acmgt3__ext948__slm_byte_read_bank1_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext948 :: LOAD STORE CACHE BYTE READ BANK1 XECORE0 */
#define acmgt3__ext948__load_store_cache_byte_read_bank1_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext949 :: GPU Time Elapsed */
#define acmgt3__ext949__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext949 :: GPU Core Clocks */
#define acmgt3__ext949__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext949 :: AVG GPU Core Frequency */
#define acmgt3__ext949__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext949 :: AVG GPU Core Frequency */
#define acmgt3__ext949__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext949 :: SLM BYTE READ BANK1 XECORE1 */
#define acmgt3__ext949__slm_byte_read_bank1_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext949 :: LOAD STORE CACHE BYTE READ BANK1 XECORE1 */
#define acmgt3__ext949__load_store_cache_byte_read_bank1_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext950 :: GPU Time Elapsed */
#define acmgt3__ext950__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext950 :: GPU Core Clocks */
#define acmgt3__ext950__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext950 :: AVG GPU Core Frequency */
#define acmgt3__ext950__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext950 :: AVG GPU Core Frequency */
#define acmgt3__ext950__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext950 :: SLM BYTE READ BANK1 XECORE2 */
#define acmgt3__ext950__slm_byte_read_bank1_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext950 :: LOAD STORE CACHE BYTE READ BANK1 XECORE2 */
#define acmgt3__ext950__load_store_cache_byte_read_bank1_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext951 :: GPU Time Elapsed */
#define acmgt3__ext951__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext951 :: GPU Core Clocks */
#define acmgt3__ext951__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext951 :: AVG GPU Core Frequency */
#define acmgt3__ext951__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext951 :: AVG GPU Core Frequency */
#define acmgt3__ext951__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext951 :: SLM BYTE READ BANK1 XECORE3 */
#define acmgt3__ext951__slm_byte_read_bank1_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext951 :: LOAD STORE CACHE BYTE READ BANK1 XECORE3 */
#define acmgt3__ext951__load_store_cache_byte_read_bank1_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext952 :: GPU Time Elapsed */
#define acmgt3__ext952__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext952 :: GPU Core Clocks */
#define acmgt3__ext952__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext952 :: AVG GPU Core Frequency */
#define acmgt3__ext952__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext952 :: AVG GPU Core Frequency */
#define acmgt3__ext952__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext952 :: SLM BYTE READ BANK2 XECORE0 */
#define acmgt3__ext952__slm_byte_read_bank2_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext952 :: LOAD STORE CACHE BYTE READ BANK2 XECORE0 */
#define acmgt3__ext952__load_store_cache_byte_read_bank2_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext953 :: GPU Time Elapsed */
#define acmgt3__ext953__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext953 :: GPU Core Clocks */
#define acmgt3__ext953__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext953 :: AVG GPU Core Frequency */
#define acmgt3__ext953__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext953 :: AVG GPU Core Frequency */
#define acmgt3__ext953__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext953 :: SLM BYTE READ BANK2 XECORE1 */
#define acmgt3__ext953__slm_byte_read_bank2_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext953 :: LOAD STORE CACHE BYTE READ BANK2 XECORE1 */
#define acmgt3__ext953__load_store_cache_byte_read_bank2_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext954 :: GPU Time Elapsed */
#define acmgt3__ext954__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext954 :: GPU Core Clocks */
#define acmgt3__ext954__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext954 :: AVG GPU Core Frequency */
#define acmgt3__ext954__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext954 :: AVG GPU Core Frequency */
#define acmgt3__ext954__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext954 :: SLM BYTE READ BANK2 XECORE2 */
#define acmgt3__ext954__slm_byte_read_bank2_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext954 :: LOAD STORE CACHE BYTE READ BANK2 XECORE2 */
#define acmgt3__ext954__load_store_cache_byte_read_bank2_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext955 :: GPU Time Elapsed */
#define acmgt3__ext955__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext955 :: GPU Core Clocks */
#define acmgt3__ext955__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext955 :: AVG GPU Core Frequency */
#define acmgt3__ext955__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext955 :: AVG GPU Core Frequency */
#define acmgt3__ext955__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext955 :: SLM BYTE READ BANK2 XECORE3 */
#define acmgt3__ext955__slm_byte_read_bank2_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext955 :: LOAD STORE CACHE BYTE READ BANK2 XECORE3 */
#define acmgt3__ext955__load_store_cache_byte_read_bank2_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext956 :: GPU Time Elapsed */
#define acmgt3__ext956__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext956 :: GPU Core Clocks */
#define acmgt3__ext956__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext956 :: AVG GPU Core Frequency */
#define acmgt3__ext956__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext956 :: AVG GPU Core Frequency */
#define acmgt3__ext956__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext956 :: SLM BYTE READ BANK3 XECORE0 */
#define acmgt3__ext956__slm_byte_read_bank3_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext956 :: LOAD STORE CACHE BYTE READ BANK3 XECORE0 */
#define acmgt3__ext956__load_store_cache_byte_read_bank3_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext957 :: GPU Time Elapsed */
#define acmgt3__ext957__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext957 :: GPU Core Clocks */
#define acmgt3__ext957__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext957 :: AVG GPU Core Frequency */
#define acmgt3__ext957__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext957 :: AVG GPU Core Frequency */
#define acmgt3__ext957__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext957 :: SLM BYTE READ BANK3 XECORE1 */
#define acmgt3__ext957__slm_byte_read_bank3_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext957 :: LOAD STORE CACHE BYTE READ BANK3 XECORE1 */
#define acmgt3__ext957__load_store_cache_byte_read_bank3_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext958 :: GPU Time Elapsed */
#define acmgt3__ext958__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext958 :: GPU Core Clocks */
#define acmgt3__ext958__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext958 :: AVG GPU Core Frequency */
#define acmgt3__ext958__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext958 :: AVG GPU Core Frequency */
#define acmgt3__ext958__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext958 :: SLM BYTE READ BANK3 XECORE2 */
#define acmgt3__ext958__slm_byte_read_bank3_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext958 :: LOAD STORE CACHE BYTE READ BANK3 XECORE2 */
#define acmgt3__ext958__load_store_cache_byte_read_bank3_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext959 :: GPU Time Elapsed */
#define acmgt3__ext959__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext959 :: GPU Core Clocks */
#define acmgt3__ext959__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext959 :: AVG GPU Core Frequency */
#define acmgt3__ext959__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext959 :: AVG GPU Core Frequency */
#define acmgt3__ext959__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext959 :: SLM BYTE READ BANK3 XECORE3 */
#define acmgt3__ext959__slm_byte_read_bank3_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext959 :: LOAD STORE CACHE BYTE READ BANK3 XECORE3 */
#define acmgt3__ext959__load_store_cache_byte_read_bank3_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext960 :: GPU Time Elapsed */
#define acmgt3__ext960__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext960 :: GPU Core Clocks */
#define acmgt3__ext960__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext960 :: AVG GPU Core Frequency */
#define acmgt3__ext960__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext960 :: AVG GPU Core Frequency */
#define acmgt3__ext960__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext960 :: SLM BYTE WRITE BANK0 XECORE0 */
#define acmgt3__ext960__slm_byte_write_bank0_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext960 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE0 */
#define acmgt3__ext960__load_store_cache_byte_write_bank0_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext961 :: GPU Time Elapsed */
#define acmgt3__ext961__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext961 :: GPU Core Clocks */
#define acmgt3__ext961__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext961 :: AVG GPU Core Frequency */
#define acmgt3__ext961__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext961 :: AVG GPU Core Frequency */
#define acmgt3__ext961__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext961 :: SLM BYTE WRITE BANK0 XECORE1 */
#define acmgt3__ext961__slm_byte_write_bank0_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext961 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE1 */
#define acmgt3__ext961__load_store_cache_byte_write_bank0_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext962 :: GPU Time Elapsed */
#define acmgt3__ext962__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext962 :: GPU Core Clocks */
#define acmgt3__ext962__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext962 :: AVG GPU Core Frequency */
#define acmgt3__ext962__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext962 :: AVG GPU Core Frequency */
#define acmgt3__ext962__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext962 :: SLM BYTE WRITE BANK0 XECORE2 */
#define acmgt3__ext962__slm_byte_write_bank0_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext962 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE2 */
#define acmgt3__ext962__load_store_cache_byte_write_bank0_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext963 :: GPU Time Elapsed */
#define acmgt3__ext963__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext963 :: GPU Core Clocks */
#define acmgt3__ext963__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext963 :: AVG GPU Core Frequency */
#define acmgt3__ext963__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext963 :: AVG GPU Core Frequency */
#define acmgt3__ext963__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext963 :: SLM BYTE WRITE BANK0 XECORE3 */
#define acmgt3__ext963__slm_byte_write_bank0_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext963 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE3 */
#define acmgt3__ext963__load_store_cache_byte_write_bank0_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext964 :: GPU Time Elapsed */
#define acmgt3__ext964__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext964 :: GPU Core Clocks */
#define acmgt3__ext964__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext964 :: AVG GPU Core Frequency */
#define acmgt3__ext964__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext964 :: AVG GPU Core Frequency */
#define acmgt3__ext964__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext964 :: SLM BYTE WRITE BANK1 XECORE0 */
#define acmgt3__ext964__slm_byte_write_bank1_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext964 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE0 */
#define acmgt3__ext964__load_store_cache_byte_write_bank1_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext965 :: GPU Time Elapsed */
#define acmgt3__ext965__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext965 :: GPU Core Clocks */
#define acmgt3__ext965__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext965 :: AVG GPU Core Frequency */
#define acmgt3__ext965__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext965 :: AVG GPU Core Frequency */
#define acmgt3__ext965__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext965 :: SLM BYTE WRITE BANK1 XECORE1 */
#define acmgt3__ext965__slm_byte_write_bank1_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext965 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE1 */
#define acmgt3__ext965__load_store_cache_byte_write_bank1_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext966 :: GPU Time Elapsed */
#define acmgt3__ext966__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext966 :: GPU Core Clocks */
#define acmgt3__ext966__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext966 :: AVG GPU Core Frequency */
#define acmgt3__ext966__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext966 :: AVG GPU Core Frequency */
#define acmgt3__ext966__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext966 :: SLM BYTE WRITE BANK1 XECORE2 */
#define acmgt3__ext966__slm_byte_write_bank1_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext966 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE2 */
#define acmgt3__ext966__load_store_cache_byte_write_bank1_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext967 :: GPU Time Elapsed */
#define acmgt3__ext967__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext967 :: GPU Core Clocks */
#define acmgt3__ext967__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext967 :: AVG GPU Core Frequency */
#define acmgt3__ext967__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext967 :: AVG GPU Core Frequency */
#define acmgt3__ext967__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext967 :: SLM BYTE WRITE BANK1 XECORE3 */
#define acmgt3__ext967__slm_byte_write_bank1_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext967 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE3 */
#define acmgt3__ext967__load_store_cache_byte_write_bank1_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext968 :: GPU Time Elapsed */
#define acmgt3__ext968__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext968 :: GPU Core Clocks */
#define acmgt3__ext968__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext968 :: AVG GPU Core Frequency */
#define acmgt3__ext968__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext968 :: AVG GPU Core Frequency */
#define acmgt3__ext968__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext968 :: SLM BYTE WRITE BANK2 XECORE0 */
#define acmgt3__ext968__slm_byte_write_bank2_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext968 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE0 */
#define acmgt3__ext968__load_store_cache_byte_write_bank2_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext969 :: GPU Time Elapsed */
#define acmgt3__ext969__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext969 :: GPU Core Clocks */
#define acmgt3__ext969__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext969 :: AVG GPU Core Frequency */
#define acmgt3__ext969__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext969 :: AVG GPU Core Frequency */
#define acmgt3__ext969__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext969 :: SLM BYTE WRITE BANK2 XECORE1 */
#define acmgt3__ext969__slm_byte_write_bank2_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext969 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE1 */
#define acmgt3__ext969__load_store_cache_byte_write_bank2_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext970 :: GPU Time Elapsed */
#define acmgt3__ext970__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext970 :: GPU Core Clocks */
#define acmgt3__ext970__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext970 :: AVG GPU Core Frequency */
#define acmgt3__ext970__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext970 :: AVG GPU Core Frequency */
#define acmgt3__ext970__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext970 :: SLM BYTE WRITE BANK2 XECORE2 */
#define acmgt3__ext970__slm_byte_write_bank2_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext970 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE2 */
#define acmgt3__ext970__load_store_cache_byte_write_bank2_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext971 :: GPU Time Elapsed */
#define acmgt3__ext971__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext971 :: GPU Core Clocks */
#define acmgt3__ext971__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext971 :: AVG GPU Core Frequency */
#define acmgt3__ext971__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext971 :: AVG GPU Core Frequency */
#define acmgt3__ext971__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext971 :: SLM BYTE WRITE BANK2 XECORE3 */
#define acmgt3__ext971__slm_byte_write_bank2_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext971 :: LOAD STORE CACHE BYTE WRITE BANK2 XECORE3 */
#define acmgt3__ext971__load_store_cache_byte_write_bank2_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext972 :: GPU Time Elapsed */
#define acmgt3__ext972__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext972 :: GPU Core Clocks */
#define acmgt3__ext972__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext972 :: AVG GPU Core Frequency */
#define acmgt3__ext972__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext972 :: AVG GPU Core Frequency */
#define acmgt3__ext972__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext972 :: SLM BYTE WRITE BANK3 XECORE0 */
#define acmgt3__ext972__slm_byte_write_bank3_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext972 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE0 */
#define acmgt3__ext972__load_store_cache_byte_write_bank3_xecore0__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext973 :: GPU Time Elapsed */
#define acmgt3__ext973__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext973 :: GPU Core Clocks */
#define acmgt3__ext973__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext973 :: AVG GPU Core Frequency */
#define acmgt3__ext973__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext973 :: AVG GPU Core Frequency */
#define acmgt3__ext973__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext973 :: SLM BYTE WRITE BANK3 XECORE1 */
#define acmgt3__ext973__slm_byte_write_bank3_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext973 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE1 */
#define acmgt3__ext973__load_store_cache_byte_write_bank3_xecore1__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext974 :: GPU Time Elapsed */
#define acmgt3__ext974__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext974 :: GPU Core Clocks */
#define acmgt3__ext974__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext974 :: AVG GPU Core Frequency */
#define acmgt3__ext974__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext974 :: AVG GPU Core Frequency */
#define acmgt3__ext974__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext974 :: SLM BYTE WRITE BANK3 XECORE2 */
#define acmgt3__ext974__slm_byte_write_bank3_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext974 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE2 */
#define acmgt3__ext974__load_store_cache_byte_write_bank3_xecore2__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext975 :: GPU Time Elapsed */
#define acmgt3__ext975__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext975 :: GPU Core Clocks */
#define acmgt3__ext975__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext975 :: AVG GPU Core Frequency */
#define acmgt3__ext975__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext975 :: AVG GPU Core Frequency */
#define acmgt3__ext975__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext975 :: SLM BYTE WRITE BANK3 XECORE3 */
#define acmgt3__ext975__slm_byte_write_bank3_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext975 :: LOAD STORE CACHE BYTE WRITE BANK3 XECORE3 */
#define acmgt3__ext975__load_store_cache_byte_write_bank3_xecore3__read \
   acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read

/* Ext976 :: GPU Time Elapsed */
#define acmgt3__ext976__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext976 :: GPU Core Clocks */
#define acmgt3__ext976__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext976 :: AVG GPU Core Frequency */
#define acmgt3__ext976__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext976 :: AVG GPU Core Frequency */
#define acmgt3__ext976__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext976 :: RT INPUT AVAILABLE XECORE0 */
#define acmgt3__ext976__rt_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext976 :: RT INPUT AVAILABLE XECORE1 */
#define acmgt3__ext976__rt_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext976 :: RT INPUT AVAILABLE XECORE2 */
#define acmgt3__ext976__rt_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext976 :: RT INPUT AVAILABLE XECORE3 */
#define acmgt3__ext976__rt_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext976 :: RT INPUT AVAILABLE XECORE4 */
#define acmgt3__ext976__rt_input_available_xecore4__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext976 :: RT INPUT AVAILABLE XECORE5 */
#define acmgt3__ext976__rt_input_available_xecore5__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext976 :: RT INPUT AVAILABLE XECORE6 */
#define acmgt3__ext976__rt_input_available_xecore6__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext976 :: RT INPUT AVAILABLE XECORE7 */
#define acmgt3__ext976__rt_input_available_xecore7__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext977 :: GPU Time Elapsed */
#define acmgt3__ext977__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext977 :: GPU Core Clocks */
#define acmgt3__ext977__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext977 :: AVG GPU Core Frequency */
#define acmgt3__ext977__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext977 :: AVG GPU Core Frequency */
#define acmgt3__ext977__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext977 :: RT INPUT AVAILABLE XECORE8 */
#define acmgt3__ext977__rt_input_available_xecore8__read \
   bdw__render_basic__sampler0_busy__read

/* Ext977 :: RT INPUT AVAILABLE XECORE9 */
#define acmgt3__ext977__rt_input_available_xecore9__read \
   bdw__render_basic__sampler1_busy__read

/* Ext977 :: RT INPUT AVAILABLE XECORE10 */
#define acmgt3__ext977__rt_input_available_xecore10__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext977 :: RT INPUT AVAILABLE XECORE11 */
#define acmgt3__ext977__rt_input_available_xecore11__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext977 :: RT INPUT AVAILABLE XECORE12 */
#define acmgt3__ext977__rt_input_available_xecore12__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext977 :: RT INPUT AVAILABLE XECORE13 */
#define acmgt3__ext977__rt_input_available_xecore13__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext977 :: RT INPUT AVAILABLE XECORE14 */
#define acmgt3__ext977__rt_input_available_xecore14__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext977 :: RT INPUT AVAILABLE XECORE15 */
#define acmgt3__ext977__rt_input_available_xecore15__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext978 :: GPU Time Elapsed */
#define acmgt3__ext978__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext978 :: GPU Core Clocks */
#define acmgt3__ext978__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext978 :: AVG GPU Core Frequency */
#define acmgt3__ext978__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext978 :: AVG GPU Core Frequency */
#define acmgt3__ext978__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext978 :: RT INPUT AVAILABLE XECORE16 */
#define acmgt3__ext978__rt_input_available_xecore16__read \
   bdw__render_basic__sampler0_busy__read

/* Ext978 :: RT INPUT AVAILABLE XECORE17 */
#define acmgt3__ext978__rt_input_available_xecore17__read \
   bdw__render_basic__sampler1_busy__read

/* Ext978 :: RT INPUT AVAILABLE XECORE18 */
#define acmgt3__ext978__rt_input_available_xecore18__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext978 :: RT INPUT AVAILABLE XECORE19 */
#define acmgt3__ext978__rt_input_available_xecore19__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext978 :: RT INPUT AVAILABLE XECORE20 */
#define acmgt3__ext978__rt_input_available_xecore20__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext978 :: RT INPUT AVAILABLE XECORE21 */
#define acmgt3__ext978__rt_input_available_xecore21__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext978 :: RT INPUT AVAILABLE XECORE22 */
#define acmgt3__ext978__rt_input_available_xecore22__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext978 :: RT INPUT AVAILABLE XECORE23 */
#define acmgt3__ext978__rt_input_available_xecore23__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext979 :: GPU Time Elapsed */
#define acmgt3__ext979__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext979 :: GPU Core Clocks */
#define acmgt3__ext979__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext979 :: AVG GPU Core Frequency */
#define acmgt3__ext979__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext979 :: AVG GPU Core Frequency */
#define acmgt3__ext979__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext979 :: RT INPUT AVAILABLE XECORE24 */
#define acmgt3__ext979__rt_input_available_xecore24__read \
   bdw__render_basic__sampler0_busy__read

/* Ext979 :: RT INPUT AVAILABLE XECORE25 */
#define acmgt3__ext979__rt_input_available_xecore25__read \
   bdw__render_basic__sampler1_busy__read

/* Ext979 :: RT INPUT AVAILABLE XECORE26 */
#define acmgt3__ext979__rt_input_available_xecore26__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext979 :: RT INPUT AVAILABLE XECORE27 */
#define acmgt3__ext979__rt_input_available_xecore27__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext979 :: RT INPUT AVAILABLE XECORE28 */
#define acmgt3__ext979__rt_input_available_xecore28__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext979 :: RT INPUT AVAILABLE XECORE29 */
#define acmgt3__ext979__rt_input_available_xecore29__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext979 :: RT INPUT AVAILABLE XECORE30 */
#define acmgt3__ext979__rt_input_available_xecore30__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext979 :: RT INPUT AVAILABLE XECORE31 */
#define acmgt3__ext979__rt_input_available_xecore31__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext980 :: GPU Time Elapsed */
#define acmgt3__ext980__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext980 :: GPU Core Clocks */
#define acmgt3__ext980__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext980 :: AVG GPU Core Frequency */
#define acmgt3__ext980__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext980 :: AVG GPU Core Frequency */
#define acmgt3__ext980__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext980 :: GPU MEMORY L3 READ SQIDI0 */
#define acmgt3__ext980__gpu_memory_l3_read_sqidi0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext981 :: GPU Time Elapsed */
#define acmgt3__ext981__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext981 :: GPU Core Clocks */
#define acmgt3__ext981__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext981 :: AVG GPU Core Frequency */
#define acmgt3__ext981__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext981 :: AVG GPU Core Frequency */
#define acmgt3__ext981__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext981 :: GPU MEMORY L3 READ SQIDI1 */
#define acmgt3__ext981__gpu_memory_l3_read_sqidi1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext982 :: GPU Time Elapsed */
#define acmgt3__ext982__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext982 :: GPU Core Clocks */
#define acmgt3__ext982__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext982 :: AVG GPU Core Frequency */
#define acmgt3__ext982__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext982 :: AVG GPU Core Frequency */
#define acmgt3__ext982__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext982 :: GPU MEMORY L3 READ SQIDI2 */
#define acmgt3__ext982__gpu_memory_l3_read_sqidi2__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext983 :: GPU Time Elapsed */
#define acmgt3__ext983__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext983 :: GPU Core Clocks */
#define acmgt3__ext983__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext983 :: AVG GPU Core Frequency */
#define acmgt3__ext983__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext983 :: AVG GPU Core Frequency */
#define acmgt3__ext983__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext983 :: GPU MEMORY L3 READ SQIDI3 */
#define acmgt3__ext983__gpu_memory_l3_read_sqidi3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext984 :: GPU Time Elapsed */
#define acmgt3__ext984__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext984 :: GPU Core Clocks */
#define acmgt3__ext984__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext984 :: AVG GPU Core Frequency */
#define acmgt3__ext984__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext984 :: AVG GPU Core Frequency */
#define acmgt3__ext984__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext984 :: GPU MEMORY L3 READ SQIDI4 */
#define acmgt3__ext984__gpu_memory_l3_read_sqidi4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext985 :: GPU Time Elapsed */
#define acmgt3__ext985__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext985 :: GPU Core Clocks */
#define acmgt3__ext985__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext985 :: AVG GPU Core Frequency */
#define acmgt3__ext985__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext985 :: AVG GPU Core Frequency */
#define acmgt3__ext985__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext985 :: GPU MEMORY L3 READ SQIDI5 */
#define acmgt3__ext985__gpu_memory_l3_read_sqidi5__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext986 :: GPU Time Elapsed */
#define acmgt3__ext986__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext986 :: GPU Core Clocks */
#define acmgt3__ext986__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext986 :: AVG GPU Core Frequency */
#define acmgt3__ext986__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext986 :: AVG GPU Core Frequency */
#define acmgt3__ext986__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext986 :: GPU MEMORY L3 READ SQIDI6 */
#define acmgt3__ext986__gpu_memory_l3_read_sqidi6__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext987 :: GPU Time Elapsed */
#define acmgt3__ext987__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext987 :: GPU Core Clocks */
#define acmgt3__ext987__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext987 :: AVG GPU Core Frequency */
#define acmgt3__ext987__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext987 :: AVG GPU Core Frequency */
#define acmgt3__ext987__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext987 :: GPU MEMORY L3 READ SQIDI7 */
#define acmgt3__ext987__gpu_memory_l3_read_sqidi7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext1000 :: GPU Time Elapsed */
#define acmgt3__ext1000__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1000 :: GPU Core Clocks */
#define acmgt3__ext1000__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1000 :: AVG GPU Core Frequency */
#define acmgt3__ext1000__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1000 :: AVG GPU Core Frequency */
#define acmgt3__ext1000__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1000 :: XVE ACTIVE */
#define acmgt3__ext1000__xve_active__read \
   bdw__render_basic__eu_active__read

/* Ext1000 :: XVE STALL */
#define acmgt3__ext1000__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Ext1000 :: XVE THREADS OCCUPANCY ALL */
#define acmgt3__ext1000__xve_threads_occupancy_all__read \
   acmgt1__ext1000__xve_threads_occupancy_all__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt3__ext1000__xve_inst_executed_alu0_all__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt3__ext1000__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt3__ext1000__xve_inst_executed_alu1_all__read \
   hsw__render_basic__hs_threads__read

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt3__ext1000__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED XMX ALL */
#define acmgt3__ext1000__xve_inst_executed_xmx_all__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1000 :: XVE INST EXECUTED XMX ALL */
#define acmgt3__ext1000__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED SEND ALL */
#define acmgt3__ext1000__xve_inst_executed_send_all__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1000 :: XVE INST EXECUTED SEND ALL */
#define acmgt3__ext1000__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL */
#define acmgt3__ext1000__xve_inst_executed_control_all__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL */
#define acmgt3__ext1000__xve_inst_executed_control_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE */
#define acmgt3__ext1000__xve_pipe_alu0_and_alu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE */
#define acmgt3__ext1000__xve_pipe_alu0_and_xmx_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define acmgt3__ext1000__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define acmgt3__ext1000__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1000 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define acmgt3__ext1000__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1000 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define acmgt3__ext1000__xve_inst_executed_send_all_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL UTILIZATION */
#define acmgt3__ext1000__xve_inst_executed_control_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1000 :: XVE ACTIVE CYCLES */
#define acmgt3__ext1000__xve_active_cycles__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1000 :: XVE ACTIVE CYCLES */
#define acmgt3__ext1000__xve_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE STALL CYCLES */
#define acmgt3__ext1000__xve_stall_cycles__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1000 :: XVE STALL CYCLES */
#define acmgt3__ext1000__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE THREADS OCCUPANCY CYCLES ALL */
#define acmgt3__ext1000__xve_threads_occupancy_cycles_all__read \
   acmgt1__ext1000__xve_threads_occupancy_cycles_all__read

/* Ext1000 :: XVE THREADS OCCUPANCY CYCLES ALL */
#define acmgt3__ext1000__xve_threads_occupancy_cycles_all__max \
   acmgt1__ext1000__xve_threads_occupancy_cycles_all__max

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
#define acmgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
#define acmgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define acmgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read \
   hsw__render_basic__ds_threads__read

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define acmgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: GPU Time Elapsed */
#define acmgt3__ext1001__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1001 :: GPU Core Clocks */
#define acmgt3__ext1001__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1001 :: AVG GPU Core Frequency */
#define acmgt3__ext1001__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1001 :: AVG GPU Core Frequency */
#define acmgt3__ext1001__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1001 :: XVE INST EXECUTED ALU0 VS */
#define acmgt3__ext1001__xve_inst_executed_alu0_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU0 VS */
#define acmgt3__ext1001__xve_inst_executed_alu0_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 HS */
#define acmgt3__ext1001__xve_inst_executed_alu0_hs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU0 HS */
#define acmgt3__ext1001__xve_inst_executed_alu0_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 DS */
#define acmgt3__ext1001__xve_inst_executed_alu0_ds__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 DS */
#define acmgt3__ext1001__xve_inst_executed_alu0_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 FS */
#define acmgt3__ext1001__xve_inst_executed_alu0_ps__read \
   hsw__render_basic__hs_threads__read

/* Ext1001 :: XVE INST EXECUTED ALU0 FS */
#define acmgt3__ext1001__xve_inst_executed_alu0_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 CS */
#define acmgt3__ext1001__xve_inst_executed_alu0_cs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 CS */
#define acmgt3__ext1001__xve_inst_executed_alu0_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define acmgt3__ext1001__xve_inst_executed_alu0_async_cs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define acmgt3__ext1001__xve_inst_executed_alu0_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 VS */
#define acmgt3__ext1001__xve_inst_executed_alu1_vs__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1001 :: XVE INST EXECUTED ALU1 VS */
#define acmgt3__ext1001__xve_inst_executed_alu1_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 HS */
#define acmgt3__ext1001__xve_inst_executed_alu1_hs__read \
   hsw__render_basic__ds_threads__read

/* Ext1001 :: XVE INST EXECUTED ALU1 HS */
#define acmgt3__ext1001__xve_inst_executed_alu1_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 DS */
#define acmgt3__ext1001__xve_inst_executed_alu1_ds__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1001 :: XVE INST EXECUTED ALU1 DS */
#define acmgt3__ext1001__xve_inst_executed_alu1_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 FS */
#define acmgt3__ext1001__xve_inst_executed_alu1_ps__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU1 FS */
#define acmgt3__ext1001__xve_inst_executed_alu1_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 CS */
#define acmgt3__ext1001__xve_inst_executed_alu1_cs__read \
   acmgt1__ext1001__xve_inst_executed_alu1_cs__read

/* Ext1001 :: XVE INST EXECUTED ALU1 CS */
#define acmgt3__ext1001__xve_inst_executed_alu1_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS */
#define acmgt3__ext1001__xve_inst_executed_alu1_async_cs__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS */
#define acmgt3__ext1001__xve_inst_executed_alu1_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 VS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu0_vs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 HS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu0_hs_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1001 :: XVE INST EXECUTED ALU0 DS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu0_ds_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 FS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu0_ps_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 CS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu0_cs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu0_async_cs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 VS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu1_vs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1001 :: XVE INST EXECUTED ALU1 HS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu1_hs_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 DS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu1_ds_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1001 :: XVE INST EXECUTED ALU1 FS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu1_ps_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 CS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu1_cs_utilization__read \
   bdw__render_basic__ps_send_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION */
#define acmgt3__ext1001__xve_inst_executed_alu1_async_cs_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1002 :: GPU Time Elapsed */
#define acmgt3__ext1002__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1002 :: GPU Core Clocks */
#define acmgt3__ext1002__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1002 :: AVG GPU Core Frequency */
#define acmgt3__ext1002__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1002 :: AVG GPU Core Frequency */
#define acmgt3__ext1002__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS UTILIZATION */
#define acmgt3__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS UTILIZATION */
#define acmgt3__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS UTILIZATION */
#define acmgt3__ext1002__xve_inst_executed_send_rt_ahs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS UTILIZATION */
#define acmgt3__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS UTILIZATION */
#define acmgt3__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS UTILIZATION */
#define acmgt3__ext1002__xve_inst_executed_send_rt_chs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS UTILIZATION */
#define acmgt3__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS UTILIZATION */
#define acmgt3__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1002 :: XVE INST EXECUTED SEND RT MS UTILIZATION */
#define acmgt3__ext1002__xve_inst_executed_send_rt_ms_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS */
#define acmgt3__ext1002__xve_inst_executed_alu0_rt_ahs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS */
#define acmgt3__ext1002__xve_inst_executed_alu0_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS */
#define acmgt3__ext1002__xve_inst_executed_alu1_rt_ahs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS */
#define acmgt3__ext1002__xve_inst_executed_alu1_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS */
#define acmgt3__ext1002__xve_inst_executed_send_rt_ahs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS */
#define acmgt3__ext1002__xve_inst_executed_send_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS */
#define acmgt3__ext1002__xve_inst_executed_alu0_rt_chs__read \
   hsw__render_basic__hs_threads__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS */
#define acmgt3__ext1002__xve_inst_executed_alu0_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS */
#define acmgt3__ext1002__xve_inst_executed_alu1_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS */
#define acmgt3__ext1002__xve_inst_executed_alu1_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS */
#define acmgt3__ext1002__xve_inst_executed_send_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS */
#define acmgt3__ext1002__xve_inst_executed_send_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS */
#define acmgt3__ext1002__xve_inst_executed_alu0_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS */
#define acmgt3__ext1002__xve_inst_executed_alu0_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS */
#define acmgt3__ext1002__xve_inst_executed_alu1_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS */
#define acmgt3__ext1002__xve_inst_executed_alu1_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT MS */
#define acmgt3__ext1002__xve_inst_executed_send_rt_ms__read \
   hsw__render_basic__ds_threads__read

/* Ext1002 :: XVE INST EXECUTED SEND RT MS */
#define acmgt3__ext1002__xve_inst_executed_send_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: GPU Time Elapsed */
#define acmgt3__ext1004__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1004 :: GPU Core Clocks */
#define acmgt3__ext1004__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1004 :: AVG GPU Core Frequency */
#define acmgt3__ext1004__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1004 :: AVG GPU Core Frequency */
#define acmgt3__ext1004__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1004 :: XVE STALL */
#define acmgt3__ext1004__xve_stall__read \
   bdw__render_basic__eu_active__read

/* Ext1004 :: XVE STALL ASYNC CS */
#define acmgt3__ext1004__xve_stall_async_cs__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1004 :: XVE STALL CS */
#define acmgt3__ext1004__xve_stall_cs__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1004 :: XVE STALL DS */
#define acmgt3__ext1004__xve_stall_ds__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1004 :: XVE STALL HS */
#define acmgt3__ext1004__xve_stall_hs__read \
   bdw__render_basic__vs_send_active__read

/* Ext1004 :: XVE STALL MS */
#define acmgt3__ext1004__xve_stall_ms__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1004 :: XVE STALL FS */
#define acmgt3__ext1004__xve_stall_ps__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1004 :: XVE STALL TS */
#define acmgt3__ext1004__xve_stall_ts__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1004 :: XVE STALL VS */
#define acmgt3__ext1004__xve_stall_vs__read \
   bdw__render_basic__eu_stall__read

/* Ext1004 :: XVE STALL RT */
#define acmgt3__ext1004__xve_stall_rt__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1004 :: XVE STALL CYCLES */
#define acmgt3__ext1004__xve_stall_cycles__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1004 :: XVE STALL CYCLES */
#define acmgt3__ext1004__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES ASYNC CS */
#define acmgt3__ext1004__xve_stall_cycles_async_cs__read \
   hsw__render_basic__ds_threads__read

/* Ext1004 :: XVE STALL CYCLES ASYNC CS */
#define acmgt3__ext1004__xve_stall_cycles_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES CS */
#define acmgt3__ext1004__xve_stall_cycles_cs__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1004 :: XVE STALL CYCLES CS */
#define acmgt3__ext1004__xve_stall_cycles_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES DS */
#define acmgt3__ext1004__xve_stall_cycles_ds__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1004 :: XVE STALL CYCLES DS */
#define acmgt3__ext1004__xve_stall_cycles_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES HS */
#define acmgt3__ext1004__xve_stall_cycles_hs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1004 :: XVE STALL CYCLES HS */
#define acmgt3__ext1004__xve_stall_cycles_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES MS */
#define acmgt3__ext1004__xve_stall_cycles_ms__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1004 :: XVE STALL CYCLES MS */
#define acmgt3__ext1004__xve_stall_cycles_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES FS */
#define acmgt3__ext1004__xve_stall_cycles_ps__read \
   hsw__render_basic__hs_threads__read

/* Ext1004 :: XVE STALL CYCLES FS */
#define acmgt3__ext1004__xve_stall_cycles_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES TS */
#define acmgt3__ext1004__xve_stall_cycles_ts__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1004 :: XVE STALL CYCLES TS */
#define acmgt3__ext1004__xve_stall_cycles_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES VS */
#define acmgt3__ext1004__xve_stall_cycles_vs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1004 :: XVE STALL CYCLES VS */
#define acmgt3__ext1004__xve_stall_cycles_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES RT */
#define acmgt3__ext1004__xve_stall_cycles_rt__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1004 :: XVE STALL CYCLES RT */
#define acmgt3__ext1004__xve_stall_cycles_rt__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: GPU Time Elapsed */
#define acmgt3__ext1005__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1005 :: GPU Core Clocks */
#define acmgt3__ext1005__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1005 :: AVG GPU Core Frequency */
#define acmgt3__ext1005__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1005 :: AVG GPU Core Frequency */
#define acmgt3__ext1005__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt3__ext1005__xve_inst_executed_alu0_all__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL */
#define acmgt3__ext1005__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP16 */
#define acmgt3__ext1005__xve_inst_executed_fp16__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1005 :: XVE INST EXECUTED FP16 */
#define acmgt3__ext1005__xve_inst_executed_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP32 */
#define acmgt3__ext1005__xve_inst_executed_fp32__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1005 :: XVE INST EXECUTED FP32 */
#define acmgt3__ext1005__xve_inst_executed_fp32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP64 */
#define acmgt3__ext1005__xve_inst_executed_fp64__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1005 :: XVE INST EXECUTED FP64 */
#define acmgt3__ext1005__xve_inst_executed_fp64__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt3__ext1005__xve_inst_executed_alu1_all__read \
   acmgt1__ext1001__xve_inst_executed_alu1_cs__read

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL */
#define acmgt3__ext1005__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED INT16 */
#define acmgt3__ext1005__xve_inst_executed_int16__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1005 :: XVE INST EXECUTED INT16 */
#define acmgt3__ext1005__xve_inst_executed_int16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED INT32 */
#define acmgt3__ext1005__xve_inst_executed_int32__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1005 :: XVE INST EXECUTED INT32 */
#define acmgt3__ext1005__xve_inst_executed_int32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED MATH */
#define acmgt3__ext1005__xve_inst_executed_math__read \
   hsw__render_basic__hs_threads__read

/* Ext1005 :: XVE INST EXECUTED MATH */
#define acmgt3__ext1005__xve_inst_executed_math__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX ALL */
#define acmgt3__ext1005__xve_inst_executed_xmx_all__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1005 :: XVE INST EXECUTED XMX ALL */
#define acmgt3__ext1005__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX BF16 */
#define acmgt3__ext1005__xve_inst_executed_xmx_bf16__read \
   hsw__render_basic__ds_threads__read

/* Ext1005 :: XVE INST EXECUTED XMX BF16 */
#define acmgt3__ext1005__xve_inst_executed_xmx_bf16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX FP16 */
#define acmgt3__ext1005__xve_inst_executed_xmx_fp16__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1005 :: XVE INST EXECUTED XMX FP16 */
#define acmgt3__ext1005__xve_inst_executed_xmx_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX INT8 */
#define acmgt3__ext1005__xve_inst_executed_xmx_int8__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1005 :: XVE INST EXECUTED XMX INT8 */
#define acmgt3__ext1005__xve_inst_executed_xmx_int8__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1005 :: XVE INST EXECUTED FP16 UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_fp16_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1005 :: XVE INST EXECUTED FP32 UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_fp32_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1005 :: XVE INST EXECUTED FP64 UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_fp64_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__ps_send_active__read

/* Ext1005 :: XVE INST EXECUTED INT16 UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_int16_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1005 :: XVE INST EXECUTED INT32 UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_int32_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1005 :: XVE INST EXECUTED MATH UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_math_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1005 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1005 :: XVE INST EXECUTED XMX BF16 UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_xmx_bf16_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1005 :: XVE INST EXECUTED XMX FP16 UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_xmx_fp16_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1005 :: XVE INST EXECUTED XMX INT8 UTILIZATION */
#define acmgt3__ext1005__xve_inst_executed_xmx_int8_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1006 :: GPU Time Elapsed */
#define acmgt3__ext1006__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1006 :: GPU Core Clocks */
#define acmgt3__ext1006__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1006 :: AVG GPU Core Frequency */
#define acmgt3__ext1006__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1006 :: AVG GPU Core Frequency */
#define acmgt3__ext1006__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1006 :: XVE INST EXECUTED SEND ALL */
#define acmgt3__ext1006__xve_inst_executed_send_all__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND ALL */
#define acmgt3__ext1006__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS */
#define acmgt3__ext1006__xve_inst_executed_send_async_cs__read \
   hsw__render_basic__ds_threads__read

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS */
#define acmgt3__ext1006__xve_inst_executed_send_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND CS */
#define acmgt3__ext1006__xve_inst_executed_send_cs__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1006 :: XVE INST EXECUTED SEND CS */
#define acmgt3__ext1006__xve_inst_executed_send_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND DS */
#define acmgt3__ext1006__xve_inst_executed_send_ds__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1006 :: XVE INST EXECUTED SEND DS */
#define acmgt3__ext1006__xve_inst_executed_send_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND GS */
#define acmgt3__ext1006__xve_inst_executed_send_gs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1006 :: XVE INST EXECUTED SEND GS */
#define acmgt3__ext1006__xve_inst_executed_send_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND HS */
#define acmgt3__ext1006__xve_inst_executed_send_hs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1006 :: XVE INST EXECUTED SEND HS */
#define acmgt3__ext1006__xve_inst_executed_send_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND MS */
#define acmgt3__ext1006__xve_inst_executed_send_ms__read \
   hsw__render_basic__hs_threads__read

/* Ext1006 :: XVE INST EXECUTED SEND MS */
#define acmgt3__ext1006__xve_inst_executed_send_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND FS */
#define acmgt3__ext1006__xve_inst_executed_send_ps__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1006 :: XVE INST EXECUTED SEND FS */
#define acmgt3__ext1006__xve_inst_executed_send_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND TS */
#define acmgt3__ext1006__xve_inst_executed_send_ts__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND TS */
#define acmgt3__ext1006__xve_inst_executed_send_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND VS */
#define acmgt3__ext1006__xve_inst_executed_send_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND VS */
#define acmgt3__ext1006__xve_inst_executed_send_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_all_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_async_cs_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1006 :: XVE INST EXECUTED SEND CS UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_cs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1006 :: XVE INST EXECUTED SEND DS UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_ds_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1006 :: XVE INST EXECUTED SEND GS UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_gs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1006 :: XVE INST EXECUTED SEND HS UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_hs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1006 :: XVE INST EXECUTED SEND MS UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_ms_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1006 :: XVE INST EXECUTED SEND FS UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_ps_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1006 :: XVE INST EXECUTED SEND TS UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_ts_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1006 :: XVE INST EXECUTED SEND VS UTILIZATION */
#define acmgt3__ext1006__xve_inst_executed_send_vs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1007 :: GPU Time Elapsed */
#define acmgt3__ext1007__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1007 :: GPU Core Clocks */
#define acmgt3__ext1007__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1007 :: AVG GPU Core Frequency */
#define acmgt3__ext1007__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1007 :: AVG GPU Core Frequency */
#define acmgt3__ext1007__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1007 :: XVE STALL GS */
#define acmgt3__ext1007__xve_stall_gs__read \
   bdw__render_basic__eu_stall__read

/* Ext1007 :: XVE INST EXECUTED ALU0 GS */
#define acmgt3__ext1007__xve_inst_executed_alu0_gs__read \
   hsw__render_basic__hs_threads__read

/* Ext1007 :: XVE INST EXECUTED ALU0 GS */
#define acmgt3__ext1007__xve_inst_executed_alu0_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 GS */
#define acmgt3__ext1007__xve_inst_executed_alu1_gs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 GS */
#define acmgt3__ext1007__xve_inst_executed_alu1_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE STALL CYCLES GS */
#define acmgt3__ext1007__xve_stall_cycles_gs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1007 :: XVE STALL CYCLES GS */
#define acmgt3__ext1007__xve_stall_cycles_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 MS */
#define acmgt3__ext1007__xve_inst_executed_alu0_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1007 :: XVE INST EXECUTED ALU0 MS */
#define acmgt3__ext1007__xve_inst_executed_alu0_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 TS */
#define acmgt3__ext1007__xve_inst_executed_alu0_ts__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1007 :: XVE INST EXECUTED ALU0 TS */
#define acmgt3__ext1007__xve_inst_executed_alu0_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 MS */
#define acmgt3__ext1007__xve_inst_executed_alu1_ms__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 MS */
#define acmgt3__ext1007__xve_inst_executed_alu1_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 TS */
#define acmgt3__ext1007__xve_inst_executed_alu1_ts__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 TS */
#define acmgt3__ext1007__xve_inst_executed_alu1_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 GS UTILIZATION */
#define acmgt3__ext1007__xve_inst_executed_alu0_gs_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1007 :: XVE INST EXECUTED ALU1 GS UTILIZATION */
#define acmgt3__ext1007__xve_inst_executed_alu1_gs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1007 :: XVE INST EXECUTED ALU0 MS UTILIZATION */
#define acmgt3__ext1007__xve_inst_executed_alu0_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1007 :: XVE INST EXECUTED ALU0 TS UTILIZATION */
#define acmgt3__ext1007__xve_inst_executed_alu0_ts_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1007 :: XVE INST EXECUTED ALU1 MS UTILIZATION */
#define acmgt3__ext1007__xve_inst_executed_alu1_ms_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1007 :: XVE INST EXECUTED ALU1 TS UTILIZATION */
#define acmgt3__ext1007__xve_inst_executed_alu1_ts_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1010 :: GPU Time Elapsed */
#define acmgt3__ext1010__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1010 :: GPU Core Clocks */
#define acmgt3__ext1010__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1010 :: AVG GPU Core Frequency */
#define acmgt3__ext1010__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1010 :: AVG GPU Core Frequency */
#define acmgt3__ext1010__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1010 :: SAMPLER 2X2 READ */
#define acmgt3__ext1010__sampler_2_x2_read__read \
   bdw__render_basic__sampler_texels__read

/* Ext1010 :: PIXEL WRITE */
#define acmgt3__ext1010__pixel_write__read \
   bdw__render_basic__samples_written__read

/* Ext1010 :: PIXEL BLEND */
#define acmgt3__ext1010__pixel_blend__read \
   bdw__render_basic__samples_blended__read

/* Ext1010 :: RASTERIZER SAMPLE OUTPUT */
#define acmgt3__ext1010__rasterizer_sample_output__read \
   bdw__render_basic__rasterized_pixels__read

/* Ext1010 :: POSTPS DEPTH STENCIL ALPHA TEST FAIL */
#define acmgt3__ext1010__postps_depth_stencil_alpha_test_fail__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic :: GPU Time Elapsed */
#define mtlgt2__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic :: GPU Core Clocks */
#define mtlgt2__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic :: AVG GPU Core Frequency */
#define mtlgt2__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic :: AVG GPU Core Frequency */
#define mtlgt2__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic :: VS Threads Dispatched */
#define mtlgt2__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic :: HS Threads Dispatched */
#define mtlgt2__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic :: DS Threads Dispatched */
#define mtlgt2__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic :: GS Threads Dispatched */
#define mtlgt2__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic :: FS Threads Dispatched */
#define mtlgt2__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic :: CS Threads Dispatched */
#define mtlgt2__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic :: GPU Busy */
#define mtlgt2__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic :: XVE Active */
#define mtlgt2__render_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic :: XVE Stall */
#define mtlgt2__render_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic :: XVE Thread Occupancy */
#define mtlgt2__render_basic__xve_thread_occupancy__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* Render Metrics Basic :: EM And FPU Pipes Active */
#define mtlgt2__render_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic :: VS FPU Pipe Active */
#define mtlgt2__render_basic__vs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic :: VS EM Pipe Active */
#define mtlgt2__render_basic__vs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic :: VS Send Pipe Active */
#define mtlgt2__render_basic__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Render Metrics Basic :: FS FPU Pipe Active */
#define mtlgt2__render_basic__ps_fpu_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Render Metrics Basic :: FS EM Pipe Active */
#define mtlgt2__render_basic__ps_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic :: FS Send Pipe Active */
#define mtlgt2__render_basic__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic :: Rasterized Pixels */
#define mtlgt2__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic :: Early Hi-Depth Test Fails */
#define mtlgt2__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic :: Early Depth Test Fails */
#define mtlgt2__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic :: Samples Killed in FS */
#define mtlgt2__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic :: Pixels Failing Tests */
#define mtlgt2__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic :: Samples Written */
#define mtlgt2__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic :: Samples Blended */
#define mtlgt2__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic :: Sampler Texels */
#define mtlgt2__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic :: Sampler Texels Misses */
#define mtlgt2__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic :: SLM Bytes Read */
#define mtlgt2__render_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Render Metrics Basic :: SLM Bytes Read */
#define mtlgt2__render_basic__slm_reads__max \
   acmgt1__render_basic__slm_reads__max

/* Render Metrics Basic :: SLM Writes */
#define mtlgt2__render_basic__slm_writes__read \
   acmgt1__render_basic__slm_writes__read

/* Render Metrics Basic :: SLM Writes */
#define mtlgt2__render_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Render Metrics Basic :: Shader Memory Accesses */
#define mtlgt2__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic :: Shader Atomic Memory Accesses */
#define mtlgt2__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic :: Shader Barrier Messages */
#define mtlgt2__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic :: GTI Read Throughput */
static uint64_t
mtlgt2__render_basic__gti_read_throughput__read(UNUSED struct intel_perf_config *perf,
                                                const struct intel_perf_query_info *query,
                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  A 36 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 36];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Render Metrics Basic :: GTI Read Throughput */
#define mtlgt2__render_basic__gti_read_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Render Metrics Basic :: GTI Write Throughput */
static uint64_t
mtlgt2__render_basic__gti_write_throughput__read(UNUSED struct intel_perf_config *perf,
                                                 const struct intel_perf_query_info *query,
                                                 const struct intel_perf_query_result *results)
{
   /* RPN equation: 32  A 37 READ UMUL */
   uint64_t tmp0 = results->accumulator[query->a_offset + 37];
   uint64_t tmp1 = 32 * tmp0;

   return tmp1;
}

/* Render Metrics Basic :: GTI Write Throughput */
#define mtlgt2__render_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Render Metrics Basic :: Samplers Busy */
#define mtlgt2__render_basic__samplers_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics Basic :: Samplers Bottleneck */
#define mtlgt2__render_basic__sampler_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Compute Metrics Basic :: GPU Time Elapsed */
#define mtlgt2__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic :: GPU Core Clocks */
#define mtlgt2__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define mtlgt2__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define mtlgt2__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic :: GPU Busy */
#define mtlgt2__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic :: VS Threads Dispatched */
#define mtlgt2__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic :: HS Threads Dispatched */
#define mtlgt2__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic :: DS Threads Dispatched */
#define mtlgt2__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic :: GS Threads Dispatched */
#define mtlgt2__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic :: FS Threads Dispatched */
#define mtlgt2__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic :: CS Threads Dispatched */
#define mtlgt2__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic :: XVE Active */
#define mtlgt2__compute_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic :: XVE Stall */
#define mtlgt2__compute_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic :: XVE FPU Pipe Active */
#define mtlgt2__compute_basic__fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic :: EM Pipe Active */
#define mtlgt2__compute_basic__em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic :: XMX Pipe Active */
#define mtlgt2__compute_basic__xmx_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic :: EM And FPU Pipes Active */
#define mtlgt2__compute_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic :: XMX And FPU Pipes Active */
#define mtlgt2__compute_basic__xve_fpu_xmx_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics Basic :: XVE AVG IPC Rate */
#define mtlgt2__compute_basic__xve_avg_ipc_rate__read \
   acmgt1__compute_basic__xve_avg_ipc_rate__read

/* Compute Metrics Basic :: XVE AVG IPC Rate */
#define mtlgt2__compute_basic__xve_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic :: Send Pipe Active */
#define mtlgt2__compute_basic__send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics Basic :: XVE Thread Occupancy */
#define mtlgt2__compute_basic__xve_thread_occupancy__read \
   acmgt1__compute_basic__xve_thread_occupancy__read

/* Compute Metrics Basic :: FPU FLT16 Instruction */
#define mtlgt2__compute_basic__xve_fpu_flt16__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics Basic :: FPU FLT32 Instruction */
#define mtlgt2__compute_basic__xve_fpu_flt32__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics Basic :: FPU FLT64 Instruction */
#define mtlgt2__compute_basic__xve_fpu_flt64__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics Basic :: Rasterized Pixels */
#define mtlgt2__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic :: Early Hi-Depth Test Fails */
#define mtlgt2__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic :: Early Depth Test Fails */
#define mtlgt2__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic :: Samples Killed in FS */
#define mtlgt2__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic :: Pixels Failing Tests */
#define mtlgt2__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic :: Samples Written */
#define mtlgt2__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic :: Samples Blended */
#define mtlgt2__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic :: Sampler Texels */
#define mtlgt2__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic :: Sampler Texels Misses */
#define mtlgt2__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define mtlgt2__compute_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define mtlgt2__compute_basic__slm_reads__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: SLM Writes */
#define mtlgt2__compute_basic__slm_writes__read \
   acmgt1__render_basic__slm_writes__read

/* Compute Metrics Basic :: SLM Writes */
#define mtlgt2__compute_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: Shader Memory Accesses */
#define mtlgt2__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic :: Shader Atomic Memory Accesses */
#define mtlgt2__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic :: Shader Barrier Messages */
#define mtlgt2__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define mtlgt2__compute_basic__gti_read_throughput__read \
   mtlgt2__render_basic__gti_read_throughput__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define mtlgt2__compute_basic__gti_read_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Compute Metrics Basic :: GTI Write Throughput */
#define mtlgt2__compute_basic__gti_write_throughput__read \
   mtlgt2__render_basic__gti_write_throughput__read

/* Compute Metrics Basic :: GTI Write Throughput */
#define mtlgt2__compute_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* AsyncCompute :: GPU Time Elapsed */
#define mtlgt2__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define mtlgt2__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define mtlgt2__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define mtlgt2__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define mtlgt2__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define mtlgt2__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define mtlgt2__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define mtlgt2__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define mtlgt2__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define mtlgt2__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define mtlgt2__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: XVE FPU Pipe Active */
#define mtlgt2__async_compute__fpu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: VS FPU Pipe Active */
#define mtlgt2__async_compute__vs_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* AsyncCompute :: FS FPU Pipe Active */
#define mtlgt2__async_compute__ps_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: CS FPU Pipe Active */
#define mtlgt2__async_compute__cs_fpu_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: ASYNC CS FPU Pipe Active */
#define mtlgt2__async_compute__async_cs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: EM Pipe Active */
#define mtlgt2__async_compute__em_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: VS EM Pipe Active */
#define mtlgt2__async_compute__vs_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: FS EM Pipe Active */
#define mtlgt2__async_compute__ps_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: CS EM Pipe Active */
#define mtlgt2__async_compute__cs_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: ASYNC CS EM Pipe Active */
#define mtlgt2__async_compute__async_cs_em_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: XVE Thread Occupancy */
#define mtlgt2__async_compute__xve_thread_occupancy__read \
   acmgt1__async_compute__xve_thread_occupancy__read

/* AsyncCompute :: XVE Active */
#define mtlgt2__async_compute__xve_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* AsyncCompute :: XVE Stall */
#define mtlgt2__async_compute__xve_stall__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* XveActivity :: GPU Time Elapsed */
#define mtlgt2__xve_activity__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* XveActivity :: GPU Core Clocks */
#define mtlgt2__xve_activity__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* XveActivity :: AVG GPU Core Frequency */
#define mtlgt2__xve_activity__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* XveActivity :: AVG GPU Core Frequency */
#define mtlgt2__xve_activity__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* XveActivity :: GPU Busy */
#define mtlgt2__xve_activity__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* XveActivity :: VS Threads Dispatched */
#define mtlgt2__xve_activity__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* XveActivity :: HS Threads Dispatched */
#define mtlgt2__xve_activity__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* XveActivity :: DS Threads Dispatched */
#define mtlgt2__xve_activity__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* XveActivity :: GS Threads Dispatched */
#define mtlgt2__xve_activity__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* XveActivity :: FS Threads Dispatched */
#define mtlgt2__xve_activity__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* XveActivity :: CS Threads Dispatched */
#define mtlgt2__xve_activity__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* XveActivity :: HS FPU Pipe Active */
#define mtlgt2__xve_activity__hs_fpu_active__read \
   bdw__render_basic__eu_active__read

/* XveActivity :: DS FPU Pipe Active */
#define mtlgt2__xve_activity__ds_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* XveActivity :: GS FPU Pipe Active */
#define mtlgt2__xve_activity__gs_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* XveActivity :: HS EM Pipe Active */
#define mtlgt2__xve_activity__hs_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* XveActivity :: DS EM Pipe Active */
#define mtlgt2__xve_activity__ds_em_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* XveActivity :: GS EM Pipe Active */
#define mtlgt2__xve_activity__gs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* XveActivity :: HS Send Pipe Active */
#define mtlgt2__xve_activity__hs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* XveActivity :: DS Send Pipe Active */
#define mtlgt2__xve_activity__ds_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* XveActivity :: GS Send Pipe Active */
#define mtlgt2__xve_activity__gs_send_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* XveActivity :: CS Send Pipe Active */
#define mtlgt2__xve_activity__cs_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* GpuBusyness :: GPU Time Elapsed */
#define mtlgt2__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define mtlgt2__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define mtlgt2__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define mtlgt2__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define mtlgt2__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: XVE Active */
#define mtlgt2__gpu_busyness__xve_active__read \
   bdw__render_basic__eu_active__read

/* GpuBusyness :: XVE Stall */
#define mtlgt2__gpu_busyness__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* GpuBusyness :: XVE Thread Occupancy */
#define mtlgt2__gpu_busyness__xve_thread_occupancy__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* GpuBusyness :: VS Threads Dispatched */
#define mtlgt2__gpu_busyness__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* GpuBusyness :: HS Threads Dispatched */
#define mtlgt2__gpu_busyness__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* GpuBusyness :: DS Threads Dispatched */
#define mtlgt2__gpu_busyness__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* GpuBusyness :: GS Threads Dispatched */
#define mtlgt2__gpu_busyness__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* GpuBusyness :: FS Threads Dispatched */
#define mtlgt2__gpu_busyness__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* GpuBusyness :: CS Threads Dispatched */
#define mtlgt2__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define mtlgt2__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: ComputeEngine0 Ring Busy */
#define mtlgt2__gpu_busyness__compute_engine0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* GpuBusyness :: Blitter Ring Busy */
#define mtlgt2__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set HDCAndSF :: GPU Time Elapsed */
#define mtlgt2__hdc_and_sf__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF :: GPU Core Clocks */
#define mtlgt2__hdc_and_sf__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define mtlgt2__hdc_and_sf__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF :: AVG GPU Core Frequency */
#define mtlgt2__hdc_and_sf__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF :: GPU Busy */
#define mtlgt2__hdc_and_sf__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF :: Slice0 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define mtlgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF :: Slice0 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define mtlgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF :: Slice0 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define mtlgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF :: Slice0 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define mtlgt2__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF :: Polygon (Slice0) Data Ready */
#define mtlgt2__hdc_and_sf__poly0_data_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF :: SQ00 is full */
#define mtlgt2__hdc_and_sf__gt_request_queue00_full__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set HDCAndSF :: SQ01 is full */
#define mtlgt2__hdc_and_sf__gt_request_queue01_full__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set HDCAndSF :: SQ10 is full */
#define mtlgt2__hdc_and_sf__gt_request_queue10_full__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set HDCAndSF :: SQ11 is full */
#define mtlgt2__hdc_and_sf__gt_request_queue11_full__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3 :: GPU Time Elapsed */
#define mtlgt2__l3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3 :: GPU Core Clocks */
#define mtlgt2__l3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3 :: AVG GPU Core Frequency */
#define mtlgt2__l3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3 :: AVG GPU Core Frequency */
#define mtlgt2__l3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3 :: GPU Busy */
#define mtlgt2__l3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3 :: L3 INPUT AVAILABLE L3BANK0 */
#define mtlgt2__l3__l3_input_available_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* L3 :: L3 INPUT AVAILABLE L3BANK1 */
#define mtlgt2__l3__l3_input_available_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3 :: L3 INPUT AVAILABLE L3BANK2 */
#define mtlgt2__l3__l3_input_available_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3 :: L3 INPUT AVAILABLE L3BANK3 */
#define mtlgt2__l3__l3_input_available_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3 :: L3 OUTPUT READY L3BANK0 */
#define mtlgt2__l3__l3_output_ready_l3_bank0__read \
   bdw__render_pipe_profile__so_stall__read

/* L3 :: L3 OUTPUT READY L3BANK1 */
#define mtlgt2__l3__l3_output_ready_l3_bank1__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3 :: L3 OUTPUT READY L3BANK2 */
#define mtlgt2__l3__l3_output_ready_l3_bank2__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3 :: L3 OUTPUT READY L3BANK3 */
#define mtlgt2__l3__l3_output_ready_l3_bank3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Time Elapsed */
#define mtlgt2__rasterizer_and_pixel_backend1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Core Clocks */
#define mtlgt2__rasterizer_and_pixel_backend1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define mtlgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define mtlgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend1 :: GPU Busy */
#define mtlgt2__rasterizer_and_pixel_backend1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice0 Rasterizer Output Ready */
#define mtlgt2__rasterizer_and_pixel_backend1__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define mtlgt2__rasterizer_and_pixel_backend1__pixel_data00_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice0 Pipe1 Post-EarlyZ Pixel Data Ready */
#define mtlgt2__rasterizer_and_pixel_backend1__pixel_data01_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend1 :: PS00 Output Available */
#define mtlgt2__rasterizer_and_pixel_backend1__ps_output00_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Pixel Values 00 Ready */
#define mtlgt2__rasterizer_and_pixel_backend1__pixel_values00_ready__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Time Elapsed */
#define mtlgt2__rasterizer_and_pixel_backend2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Core Clocks */
#define mtlgt2__rasterizer_and_pixel_backend2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define mtlgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define mtlgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend2 :: GPU Busy */
#define mtlgt2__rasterizer_and_pixel_backend2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice0 Rasterizer Input Available */
#define mtlgt2__rasterizer_and_pixel_backend2__rasterizer0_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define mtlgt2__rasterizer_and_pixel_backend2__pixel_data00_ready__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend2 :: Slice0 Pipe1 Post-EarlyZ Pixel Data Ready */
#define mtlgt2__rasterizer_and_pixel_backend2__pixel_data01_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: PS00 Output Available */
#define mtlgt2__rasterizer_and_pixel_backend2__ps_output00_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Pixel Values 00 Ready */
#define mtlgt2__rasterizer_and_pixel_backend2__pixel_values00_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define mtlgt2__render_pipe_profile__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define mtlgt2__render_pipe_profile__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define mtlgt2__render_pipe_profile__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define mtlgt2__render_pipe_profile__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define mtlgt2__render_pipe_profile__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF0 Bottleneck */
#define mtlgt2__render_pipe_profile__vf0_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: VS0 Bottleneck */
#define mtlgt2__render_pipe_profile__vs0_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics for 3D Pipeline Profile :: Clipper0 Bottleneck */
#define mtlgt2__render_pipe_profile__cl0_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS0 Bottleneck */
#define mtlgt2__render_pipe_profile__hs0_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS0 Bottleneck */
#define mtlgt2__render_pipe_profile__ds0_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: GS0 Bottleneck */
#define mtlgt2__render_pipe_profile__gs0_bottleneck__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF0 Bottleneck */
#define mtlgt2__render_pipe_profile__sf0_bottleneck__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO0 Bottleneck */
#define mtlgt2__render_pipe_profile__so0_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL0 Stall */
#define mtlgt2__render_pipe_profile__cl0_stall__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS0 Stall */
#define mtlgt2__render_pipe_profile__hs0_stall__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS0 Stall */
#define mtlgt2__render_pipe_profile__ds0_stall__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF0 Stall */
#define mtlgt2__render_pipe_profile__sf0_stall__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO0 Stall */
#define mtlgt2__render_pipe_profile__so0_stall__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth00 Bottleneck */
#define mtlgt2__render_pipe_profile__hi_depth00_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth01 Bottleneck */
#define mtlgt2__render_pipe_profile__hi_depth01_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC00 Bottleneck */
#define mtlgt2__render_pipe_profile__bc00_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_Slice0 :: GPU Time Elapsed */
#define mtlgt2__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_Slice0 :: GPU Core Clocks */
#define mtlgt2__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_Slice0 :: AVG GPU Core Frequency */
#define mtlgt2__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_Slice0 :: AVG GPU Core Frequency */
#define mtlgt2__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_Slice0 :: GPU Busy */
#define mtlgt2__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_Slice0 :: Slice0 Xe Core0 Input Available */
#define mtlgt2__sampler__sampler00_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler_Slice0 :: Slice0 Xe Core1 Input Available */
#define mtlgt2__sampler__sampler01_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_Slice0 :: Slice0 Xe Core2 Input Available */
#define mtlgt2__sampler__sampler02_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler_Slice0 :: Slice0 Xe Core3 Input Available */
#define mtlgt2__sampler__sampler03_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler_Slice0 :: Slice0 Xe Core0 Sampler Output Ready */
#define mtlgt2__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler_Slice0 :: Slice0 Xe Core1 Sampler Output Ready */
#define mtlgt2__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler_Slice0 :: Slice0 Xe Core2 Sampler Output Ready */
#define mtlgt2__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler_Slice0 :: Slice0 Xe Core3 Sampler Output Ready */
#define mtlgt2__sampler__sampler03_output_ready__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL1 :: GPU Time Elapsed */
#define mtlgt2__tdl1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL1 :: GPU Core Clocks */
#define mtlgt2__tdl1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL1 :: AVG GPU Core Frequency */
#define mtlgt2__tdl1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL1 :: AVG GPU Core Frequency */
#define mtlgt2__tdl1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL1 :: GPU Busy */
#define mtlgt2__tdl1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher */
#define mtlgt2__tdl1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL1 :: PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher */
#define mtlgt2__tdl1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher */
#define mtlgt2__tdl1__thread_header00_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 0 */
#define mtlgt2__tdl1__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 1 */
#define mtlgt2__tdl1__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 2 */
#define mtlgt2__tdl1__thread_header00_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 3 */
#define mtlgt2__tdl1__thread_header00_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher */
#define mtlgt2__tdl1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL1 :: PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher */
#define mtlgt2__tdl1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher */
#define mtlgt2__tdl1__thread_header01_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 0 */
#define mtlgt2__tdl1__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 1 */
#define mtlgt2__tdl1__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 2 */
#define mtlgt2__tdl1__thread_header01_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 3 */
#define mtlgt2__tdl1__thread_header01_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL2 :: GPU Time Elapsed */
#define mtlgt2__tdl2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL2 :: GPU Core Clocks */
#define mtlgt2__tdl2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL2 :: AVG GPU Core Frequency */
#define mtlgt2__tdl2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL2 :: AVG GPU Core Frequency */
#define mtlgt2__tdl2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL2 :: GPU Busy */
#define mtlgt2__tdl2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL2 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher */
#define mtlgt2__tdl2__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher */
#define mtlgt2__tdl2__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher */
#define mtlgt2__tdl2__thread_header02_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 0 */
#define mtlgt2__tdl2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 1 */
#define mtlgt2__tdl2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 2 */
#define mtlgt2__tdl2__thread_header02_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 3 */
#define mtlgt2__tdl2__thread_header02_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL2 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher */
#define mtlgt2__tdl2__non_ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher */
#define mtlgt2__tdl2__ps_thread03_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher */
#define mtlgt2__tdl2__thread_header03_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 0 */
#define mtlgt2__tdl2__thread_header03_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 1 */
#define mtlgt2__tdl2__thread_header03_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 2 */
#define mtlgt2__tdl2__thread_header03_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 3 */
#define mtlgt2__tdl2__thread_header03_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set TestOa :: GPU Time Elapsed */
#define mtlgt2__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define mtlgt2__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define mtlgt2__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define mtlgt2__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define mtlgt2__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define mtlgt2__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define mtlgt2__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define mtlgt2__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define mtlgt2__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define mtlgt2__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define mtlgt2__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define mtlgt2__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define mtlgt2__test_oa__counter8__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define mtlgt2__test_oa__counter9__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext1 :: GPU Time Elapsed */
#define mtlgt2__ext1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1 :: GPU Core Clocks */
#define mtlgt2__ext1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1 :: AVG GPU Core Frequency */
#define mtlgt2__ext1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1 :: AVG GPU Core Frequency */
#define mtlgt2__ext1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1 :: GPU MEMORY BYTE WRITE SQIDI0 */
#define mtlgt2__ext1__gpu_memory_byte_write_sqidi0__read \
   acmgt1__ext1__gpu_memory_byte_write_sqidi0__read

/* Ext1 :: GPU MEMORY BYTE WRITE SQIDI1 */
#define mtlgt2__ext1__gpu_memory_byte_write_sqidi1__read \
   hsw__render_basic__gti_read_throughput__read

/* Ext1 :: GPU MEMORY WRITE SQIDI0 */
#define mtlgt2__ext1__gpu_memory_write_sqidi0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext1 :: GPU MEMORY WRITE SQIDI1 */
#define mtlgt2__ext1__gpu_memory_write_sqidi1__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext1 :: GPU MEMORY WRITE */
#define mtlgt2__ext1__gpu_memory_write__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI0 */
#define mtlgt2__ext1__gpu_memory_read_sqidi0__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI1 */
#define mtlgt2__ext1__gpu_memory_read_sqidi1__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ */
static uint64_t
mtlgt2__ext1__gpu_memory_read__read(UNUSED struct intel_perf_config *perf,
                                    const struct intel_perf_query_info *query,
                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: $GPU_MEMORY_READ_SQIDI0 $GPU_MEMORY_READ_SQIDI1 UADD */
   uint64_t tmp0 = mtlgt2__ext1__gpu_memory_read_sqidi0__read(perf, query, results) + mtlgt2__ext1__gpu_memory_read_sqidi1__read(perf, query, results);

   return tmp0;
}

/* Ext1 :: GPU MEMORY BYTE READ SQIDI0 */
#define mtlgt2__ext1__gpu_memory_byte_read_sqidi0__read \
   acmgt3__ext2__gpu_memory_byte_write_sqidi0__read

/* Ext1 :: GPU MEMORY BYTE READ SQIDI1 */
#define mtlgt2__ext1__gpu_memory_byte_read_sqidi1__read \
   acmgt3__ext2__gpu_memory_byte_write_sqidi1__read

/* Ext1 :: GPU MEMORY ACTIVE SQIDI0 */
#define mtlgt2__ext1__gpu_memory_active_sqidi0__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext1 :: GPU MEMORY ACTIVE SQIDI1 */
#define mtlgt2__ext1__gpu_memory_active_sqidi1__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext1 :: GPU MEMORY BYTE READ BW SQIDI0 */
#define mtlgt2__ext1__gpu_memory_byte_read_bw_sqidi0__read \
   acmgt3__ext2__gpu_memory_byte_write_bw_sqidi0__read

/* Ext1 :: GPU MEMORY BYTE READ BW SQIDI1 */
#define mtlgt2__ext1__gpu_memory_byte_read_bw_sqidi1__read \
   acmgt3__ext2__gpu_memory_byte_write_bw_sqidi1__read

/* Ext1 :: GPU MEMORY BYTE WRITE BW SQIDI0 */
#define mtlgt2__ext1__gpu_memory_byte_write_bw_sqidi0__read \
   acmgt1__ext1__gpu_memory_byte_write_bw_sqidi0__read

/* Ext1 :: GPU MEMORY BYTE WRITE BW SQIDI1 */
#define mtlgt2__ext1__gpu_memory_byte_write_bw_sqidi1__read \
   acmgt1__ext1__gpu_memory_byte_write_bw_sqidi1__read

/* Ext4 :: GPU Time Elapsed */
#define mtlgt2__ext4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext4 :: GPU Core Clocks */
#define mtlgt2__ext4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext4 :: AVG GPU Core Frequency */
#define mtlgt2__ext4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext4 :: AVG GPU Core Frequency */
#define mtlgt2__ext4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext4 :: L3 READ L3BANK0 */
#define mtlgt2__ext4__l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext4 :: L3 READ L3BANK1 */
#define mtlgt2__ext4__l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext4 :: L3 READ L3BANK2 */
#define mtlgt2__ext4__l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext4 :: L3 READ L3BANK3 */
#define mtlgt2__ext4__l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext4 :: L3 WRITE L3BANK0 */
#define mtlgt2__ext4__l3_write_l3_bank0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext4 :: L3 WRITE L3BANK1 */
#define mtlgt2__ext4__l3_write_l3_bank1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext4 :: L3 WRITE L3BANK2 */
#define mtlgt2__ext4__l3_write_l3_bank2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext4 :: L3 WRITE L3BANK3 */
#define mtlgt2__ext4__l3_write_l3_bank3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext5 :: GPU Time Elapsed */
#define mtlgt2__ext5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext5 :: GPU Core Clocks */
#define mtlgt2__ext5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext5 :: AVG GPU Core Frequency */
#define mtlgt2__ext5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext5 :: AVG GPU Core Frequency */
#define mtlgt2__ext5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext5 :: DATAPORT L3 READ L3BANK0 */
#define mtlgt2__ext5__dataport_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext5 :: DATAPORT L3 READ L3BANK1 */
#define mtlgt2__ext5__dataport_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext5 :: DATAPORT L3 READ L3BANK2 */
#define mtlgt2__ext5__dataport_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext5 :: DATAPORT L3 READ L3BANK3 */
#define mtlgt2__ext5__dataport_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK0 */
#define mtlgt2__ext5__dataport_l3_write_l3_bank0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK1 */
#define mtlgt2__ext5__dataport_l3_write_l3_bank1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK2 */
#define mtlgt2__ext5__dataport_l3_write_l3_bank2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK3 */
#define mtlgt2__ext5__dataport_l3_write_l3_bank3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext5 :: L3 HIT L3BANK0 */
#define mtlgt2__ext5__l3_hit_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext5 :: L3 HIT L3BANK1 */
#define mtlgt2__ext5__l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext5 :: L3 HIT L3BANK2 */
#define mtlgt2__ext5__l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext5 :: L3 HIT L3BANK3 */
#define mtlgt2__ext5__l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext7 :: GPU Time Elapsed */
#define mtlgt2__ext7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext7 :: GPU Core Clocks */
#define mtlgt2__ext7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext7 :: AVG GPU Core Frequency */
#define mtlgt2__ext7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext7 :: AVG GPU Core Frequency */
#define mtlgt2__ext7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext7 :: SAMPLER L3 READ L3BANK0 */
#define mtlgt2__ext7__sampler_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext7 :: SAMPLER L3 READ L3BANK1 */
#define mtlgt2__ext7__sampler_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext7 :: SAMPLER L3 READ L3BANK2 */
#define mtlgt2__ext7__sampler_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext7 :: SAMPLER L3 READ L3BANK3 */
#define mtlgt2__ext7__sampler_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK0 */
#define mtlgt2__ext7__sampler_l3_hit_l3_bank0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK1 */
#define mtlgt2__ext7__sampler_l3_hit_l3_bank1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext7 :: SAMPLER L3 HIT L3BANK2 */
#define mtlgt2__ext7__sampler_l3_hit_l3_bank2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK3 */
#define mtlgt2__ext7__sampler_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext7 :: SAMPLER BUSY XECORE0 */
#define mtlgt2__ext7__sampler_busy_xecore0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext7 :: SAMPLER BUSY XECORE1 */
#define mtlgt2__ext7__sampler_busy_xecore1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext7 :: SAMPLER BUSY XECORE2 */
#define mtlgt2__ext7__sampler_busy_xecore2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext7 :: SAMPLER BUSY XECORE3 */
#define mtlgt2__ext7__sampler_busy_xecore3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext8 :: GPU Time Elapsed */
#define mtlgt2__ext8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext8 :: GPU Core Clocks */
#define mtlgt2__ext8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext8 :: AVG GPU Core Frequency */
#define mtlgt2__ext8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext8 :: AVG GPU Core Frequency */
#define mtlgt2__ext8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext8 :: ICACHE L3 READ L3BANK0 */
#define mtlgt2__ext8__icache_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext8 :: ICACHE L3 READ L3BANK1 */
#define mtlgt2__ext8__icache_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext8 :: ICACHE L3 READ L3BANK2 */
#define mtlgt2__ext8__icache_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext8 :: ICACHE L3 READ L3BANK3 */
#define mtlgt2__ext8__icache_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext8 :: ICACHE L3 HIT L3BANK0 */
#define mtlgt2__ext8__icache_l3_hit_l3_bank0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext8 :: ICACHE L3 HIT L3BANK1 */
#define mtlgt2__ext8__icache_l3_hit_l3_bank1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext8 :: ICACHE L3 HIT L3BANK2 */
#define mtlgt2__ext8__icache_l3_hit_l3_bank2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext8 :: ICACHE L3 HIT L3BANK3 */
#define mtlgt2__ext8__icache_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext10 :: GPU Time Elapsed */
#define mtlgt2__ext10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext10 :: GPU Core Clocks */
#define mtlgt2__ext10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext10 :: AVG GPU Core Frequency */
#define mtlgt2__ext10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext10 :: AVG GPU Core Frequency */
#define mtlgt2__ext10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext10 :: DATAPORT L3 HIT L3BANK0 */
#define mtlgt2__ext10__dataport_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext10 :: DATAPORT L3 HIT L3BANK1 */
#define mtlgt2__ext10__dataport_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext10 :: DATAPORT L3 HIT L3BANK2 */
#define mtlgt2__ext10__dataport_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext10 :: DATAPORT L3 HIT L3BANK3 */
#define mtlgt2__ext10__dataport_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext10 :: COLOR L3 HIT L3BANK0 */
#define mtlgt2__ext10__color_l3_hit_l3_bank0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext10 :: COLOR L3 HIT L3BANK1 */
#define mtlgt2__ext10__color_l3_hit_l3_bank1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext10 :: COLOR L3 HIT L3BANK2 */
#define mtlgt2__ext10__color_l3_hit_l3_bank2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext10 :: COLOR L3 HIT L3BANK3 */
#define mtlgt2__ext10__color_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext10 :: Z L3 ACCESS L3BANK0 */
#define mtlgt2__ext10__z_l3_access_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext10 :: Z L3 ACCESS L3BANK1 */
#define mtlgt2__ext10__z_l3_access_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext10 :: Z L3 ACCESS L3BANK2 */
#define mtlgt2__ext10__z_l3_access_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext10 :: Z L3 ACCESS L3BANK3 */
#define mtlgt2__ext10__z_l3_access_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext11 :: GPU Time Elapsed */
#define mtlgt2__ext11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext11 :: GPU Core Clocks */
#define mtlgt2__ext11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext11 :: AVG GPU Core Frequency */
#define mtlgt2__ext11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext11 :: AVG GPU Core Frequency */
#define mtlgt2__ext11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext11 :: Z L3 HIT L3BANK0 */
#define mtlgt2__ext11__z_l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext11 :: Z L3 HIT L3BANK1 */
#define mtlgt2__ext11__z_l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext11 :: Z L3 HIT L3BANK2 */
#define mtlgt2__ext11__z_l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext11 :: Z L3 HIT L3BANK3 */
#define mtlgt2__ext11__z_l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK0 */
#define mtlgt2__ext11__l3_atomic_access_l3_bank0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK1 */
#define mtlgt2__ext11__l3_atomic_access_l3_bank1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK2 */
#define mtlgt2__ext11__l3_atomic_access_l3_bank2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK3 */
#define mtlgt2__ext11__l3_atomic_access_l3_bank3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext12 :: GPU Time Elapsed */
#define mtlgt2__ext12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext12 :: GPU Core Clocks */
#define mtlgt2__ext12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext12 :: AVG GPU Core Frequency */
#define mtlgt2__ext12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext12 :: AVG GPU Core Frequency */
#define mtlgt2__ext12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext12 :: L3 INPUT AVAILABLE L3BANK0 */
#define mtlgt2__ext12__l3_input_available_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK1 */
#define mtlgt2__ext12__l3_input_available_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK2 */
#define mtlgt2__ext12__l3_input_available_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK3 */
#define mtlgt2__ext12__l3_input_available_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK0 */
#define mtlgt2__ext12__l3_output_ready_l3_bank0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK1 */
#define mtlgt2__ext12__l3_output_ready_l3_bank1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK2 */
#define mtlgt2__ext12__l3_output_ready_l3_bank2__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK3 */
#define mtlgt2__ext12__l3_output_ready_l3_bank3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext13 :: GPU Time Elapsed */
#define mtlgt2__ext13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext13 :: GPU Core Clocks */
#define mtlgt2__ext13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext13 :: AVG GPU Core Frequency */
#define mtlgt2__ext13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext13 :: AVG GPU Core Frequency */
#define mtlgt2__ext13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext13 :: L3 SUPERQ FULL L3BANK0 */
#define mtlgt2__ext13__l3_superq_full_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext13 :: L3 SUPERQ FULL L3BANK1 */
#define mtlgt2__ext13__l3_superq_full_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext13 :: L3 SUPERQ FULL L3BANK2 */
#define mtlgt2__ext13__l3_superq_full_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext13 :: L3 SUPERQ FULL L3BANK3 */
#define mtlgt2__ext13__l3_superq_full_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext13 :: COLOR L3 ACCESS L3BANK0 */
#define mtlgt2__ext13__color_l3_access_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext13 :: COLOR L3 ACCESS L3BANK1 */
#define mtlgt2__ext13__color_l3_access_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext13 :: COLOR L3 ACCESS L3BANK2 */
#define mtlgt2__ext13__color_l3_access_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext13 :: COLOR L3 ACCESS L3BANK3 */
#define mtlgt2__ext13__color_l3_access_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext14 :: GPU Time Elapsed */
#define mtlgt2__ext14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext14 :: GPU Core Clocks */
#define mtlgt2__ext14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext14 :: AVG GPU Core Frequency */
#define mtlgt2__ext14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext14 :: AVG GPU Core Frequency */
#define mtlgt2__ext14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext14 :: L3 BUSY L3BANK0 */
#define mtlgt2__ext14__l3_busy_l3_bank0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext14 :: L3 BUSY L3BANK1 */
#define mtlgt2__ext14__l3_busy_l3_bank1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext14 :: L3 BUSY L3BANK2 */
#define mtlgt2__ext14__l3_busy_l3_bank2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext14 :: L3 BUSY L3BANK3 */
#define mtlgt2__ext14__l3_busy_l3_bank3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext14 :: L3 STALL L3BANK0 */
#define mtlgt2__ext14__l3_stall_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext14 :: L3 STALL L3BANK1 */
#define mtlgt2__ext14__l3_stall_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext14 :: L3 STALL L3BANK2 */
#define mtlgt2__ext14__l3_stall_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext14 :: L3 STALL L3BANK3 */
#define mtlgt2__ext14__l3_stall_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext17 :: GPU Time Elapsed */
#define mtlgt2__ext17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext17 :: GPU Core Clocks */
#define mtlgt2__ext17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext17 :: AVG GPU Core Frequency */
#define mtlgt2__ext17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext17 :: AVG GPU Core Frequency */
#define mtlgt2__ext17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE0 */
static float
mtlgt2__ext17__load_store_cache_input_available_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                              const struct intel_perf_query_info *query,
                                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ C 6 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = mtlgt2__ext17__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE1 */
static float
mtlgt2__ext17__load_store_cache_input_available_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                              const struct intel_perf_query_info *query,
                                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 5 READ C 4 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 5];
   uint64_t tmp1 = results->accumulator[query->c_offset + 4];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = mtlgt2__ext17__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE2 */
static float
mtlgt2__ext17__load_store_cache_input_available_xecore2__read(UNUSED struct intel_perf_config *perf,
                                                              const struct intel_perf_query_info *query,
                                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ C 2 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = mtlgt2__ext17__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE3 */
static float
mtlgt2__ext17__load_store_cache_input_available_xecore3__read(UNUSED struct intel_perf_config *perf,
                                                              const struct intel_perf_query_info *query,
                                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ C 0 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 0];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 2;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = mtlgt2__ext17__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext17 :: LOAD STORE CACHE OUTPUT READY XECORE0 */
static float
mtlgt2__ext17__load_store_cache_output_ready_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ B 6 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 4;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = mtlgt2__ext17__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext17 :: LOAD STORE CACHE OUTPUT READY XECORE1 */
static float
mtlgt2__ext17__load_store_cache_output_ready_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ B 4 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = results->accumulator[query->b_offset + 4];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 4;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = mtlgt2__ext17__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext17 :: LOAD STORE CACHE OUTPUT READY XECORE2 */
static float
mtlgt2__ext17__load_store_cache_output_ready_xecore2__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 3 READ B 2 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 3];
   uint64_t tmp1 = results->accumulator[query->b_offset + 2];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 4;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = mtlgt2__ext17__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext17 :: LOAD STORE CACHE OUTPUT READY XECORE3 */
static float
mtlgt2__ext17__load_store_cache_output_ready_xecore3__read(UNUSED struct intel_perf_config *perf,
                                                           const struct intel_perf_query_info *query,
                                                           const struct intel_perf_query_result *results)
{
   /* RPN equation: B 1 READ B 0 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 1];
   uint64_t tmp1 = results->accumulator[query->b_offset + 0];
   double tmp2 = tmp0 + tmp1;
   double tmp3 = tmp2;
   double tmp4 = 4;
   double tmp5 = tmp4 ? tmp3 / tmp4 : 0;
   uint64_t tmp6 = tmp5 * 100;
   double tmp7 = tmp6;
   double tmp8 = mtlgt2__ext17__gpu_core_clocks__read(perf, query, results);
   double tmp9 = tmp8 ? tmp7 / tmp8 : 0;

   return tmp9;
}

/* Ext21 :: GPU Time Elapsed */
#define mtlgt2__ext21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext21 :: GPU Core Clocks */
#define mtlgt2__ext21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext21 :: AVG GPU Core Frequency */
#define mtlgt2__ext21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext21 :: AVG GPU Core Frequency */
#define mtlgt2__ext21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE0 */
#define mtlgt2__ext21__load_store_cache_access_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE1 */
#define mtlgt2__ext21__load_store_cache_access_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE2 */
#define mtlgt2__ext21__load_store_cache_access_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE3 */
#define mtlgt2__ext21__load_store_cache_access_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext21 :: LOAD STORE CACHE L3 READ XECORE0 */
#define mtlgt2__ext21__load_store_cache_l3_read_xecore0__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext21 :: LOAD STORE CACHE L3 READ XECORE1 */
#define mtlgt2__ext21__load_store_cache_l3_read_xecore1__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext21 :: LOAD STORE CACHE L3 READ XECORE2 */
#define mtlgt2__ext21__load_store_cache_l3_read_xecore2__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext21 :: LOAD STORE CACHE L3 READ XECORE3 */
#define mtlgt2__ext21__load_store_cache_l3_read_xecore3__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext23 :: GPU Time Elapsed */
#define mtlgt2__ext23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext23 :: GPU Core Clocks */
#define mtlgt2__ext23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext23 :: AVG GPU Core Frequency */
#define mtlgt2__ext23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext23 :: AVG GPU Core Frequency */
#define mtlgt2__ext23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext23 :: LOAD STORE CACHE HIT XECORE0 */
#define mtlgt2__ext23__load_store_cache_hit_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext23 :: LOAD STORE CACHE HIT XECORE1 */
#define mtlgt2__ext23__load_store_cache_hit_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext23 :: LOAD STORE CACHE HIT XECORE2 */
#define mtlgt2__ext23__load_store_cache_hit_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext23 :: LOAD STORE CACHE HIT XECORE3 */
#define mtlgt2__ext23__load_store_cache_hit_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext28 :: GPU Time Elapsed */
#define mtlgt2__ext28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext28 :: GPU Core Clocks */
#define mtlgt2__ext28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext28 :: AVG GPU Core Frequency */
#define mtlgt2__ext28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext28 :: AVG GPU Core Frequency */
#define mtlgt2__ext28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE0 */
#define mtlgt2__ext28__load_store_cache_l3_write_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE1 */
#define mtlgt2__ext28__load_store_cache_l3_write_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE2 */
#define mtlgt2__ext28__load_store_cache_l3_write_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE3 */
#define mtlgt2__ext28__load_store_cache_l3_write_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext28 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0 */
#define mtlgt2__ext28__load_store_cache_partial_write_count_xecore0__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext28 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1 */
#define mtlgt2__ext28__load_store_cache_partial_write_count_xecore1__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext28 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2 */
#define mtlgt2__ext28__load_store_cache_partial_write_count_xecore2__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext28 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3 */
#define mtlgt2__ext28__load_store_cache_partial_write_count_xecore3__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext31 :: GPU Time Elapsed */
#define mtlgt2__ext31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext31 :: GPU Core Clocks */
#define mtlgt2__ext31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext31 :: AVG GPU Core Frequency */
#define mtlgt2__ext31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext31 :: AVG GPU Core Frequency */
#define mtlgt2__ext31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define mtlgt2__ext31__xve_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define mtlgt2__ext31__xve_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define mtlgt2__ext31__xve_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define mtlgt2__ext31__xve_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext35 :: GPU Time Elapsed */
#define mtlgt2__ext35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext35 :: GPU Core Clocks */
#define mtlgt2__ext35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext35 :: AVG GPU Core Frequency */
#define mtlgt2__ext35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext35 :: AVG GPU Core Frequency */
#define mtlgt2__ext35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0 */
#define mtlgt2__ext35__xve_load_store_cache_write_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1 */
#define mtlgt2__ext35__xve_load_store_cache_write_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2 */
#define mtlgt2__ext35__xve_load_store_cache_write_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3 */
#define mtlgt2__ext35__xve_load_store_cache_write_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext39 :: GPU Time Elapsed */
#define mtlgt2__ext39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext39 :: GPU Core Clocks */
#define mtlgt2__ext39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext39 :: AVG GPU Core Frequency */
#define mtlgt2__ext39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext39 :: AVG GPU Core Frequency */
#define mtlgt2__ext39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0 */
#define mtlgt2__ext39__xve_load_store_cache_fence_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1 */
#define mtlgt2__ext39__xve_load_store_cache_fence_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2 */
#define mtlgt2__ext39__xve_load_store_cache_fence_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3 */
#define mtlgt2__ext39__xve_load_store_cache_fence_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext43 :: GPU Time Elapsed */
#define mtlgt2__ext43__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext43 :: GPU Core Clocks */
#define mtlgt2__ext43__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext43 :: AVG GPU Core Frequency */
#define mtlgt2__ext43__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext43 :: AVG GPU Core Frequency */
#define mtlgt2__ext43__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext43 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0 */
#define mtlgt2__ext43__xve_load_store_cache_atomic_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext43 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1 */
#define mtlgt2__ext43__xve_load_store_cache_atomic_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext43 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0 */
#define mtlgt2__ext43__xve_load_store_cache_register_request_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext43 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1 */
#define mtlgt2__ext43__xve_load_store_cache_register_request_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext45 :: GPU Time Elapsed */
#define mtlgt2__ext45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext45 :: GPU Core Clocks */
#define mtlgt2__ext45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext45 :: AVG GPU Core Frequency */
#define mtlgt2__ext45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext45 :: AVG GPU Core Frequency */
#define mtlgt2__ext45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext45 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2 */
#define mtlgt2__ext45__xve_load_store_cache_atomic_message_count_xecore2__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext45 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3 */
#define mtlgt2__ext45__xve_load_store_cache_atomic_message_count_xecore3__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext45 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2 */
#define mtlgt2__ext45__xve_load_store_cache_register_request_count_xecore2__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext45 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3 */
#define mtlgt2__ext45__xve_load_store_cache_register_request_count_xecore3__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext51 :: GPU Time Elapsed */
#define mtlgt2__ext51__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext51 :: GPU Core Clocks */
#define mtlgt2__ext51__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext51 :: AVG GPU Core Frequency */
#define mtlgt2__ext51__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext51 :: AVG GPU Core Frequency */
#define mtlgt2__ext51__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0 */
#define mtlgt2__ext51__xve_load_store_cache_register_response_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1 */
#define mtlgt2__ext51__xve_load_store_cache_register_response_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2 */
#define mtlgt2__ext51__xve_load_store_cache_register_response_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3 */
#define mtlgt2__ext51__xve_load_store_cache_register_response_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext53 :: GPU Time Elapsed */
#define mtlgt2__ext53__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext53 :: GPU Core Clocks */
#define mtlgt2__ext53__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext53 :: AVG GPU Core Frequency */
#define mtlgt2__ext53__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext53 :: AVG GPU Core Frequency */
#define mtlgt2__ext53__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE0 */
#define mtlgt2__ext53__xve_slm_read_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE1 */
#define mtlgt2__ext53__xve_slm_read_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE2 */
#define mtlgt2__ext53__xve_slm_read_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE3 */
#define mtlgt2__ext53__xve_slm_read_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext57 :: GPU Time Elapsed */
#define mtlgt2__ext57__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext57 :: GPU Core Clocks */
#define mtlgt2__ext57__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext57 :: AVG GPU Core Frequency */
#define mtlgt2__ext57__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext57 :: AVG GPU Core Frequency */
#define mtlgt2__ext57__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE0 */
#define mtlgt2__ext57__xve_slm_write_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE1 */
#define mtlgt2__ext57__xve_slm_write_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE2 */
#define mtlgt2__ext57__xve_slm_write_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE3 */
#define mtlgt2__ext57__xve_slm_write_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext61 :: GPU Time Elapsed */
#define mtlgt2__ext61__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext61 :: GPU Core Clocks */
#define mtlgt2__ext61__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext61 :: AVG GPU Core Frequency */
#define mtlgt2__ext61__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext61 :: AVG GPU Core Frequency */
#define mtlgt2__ext61__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE0 */
#define mtlgt2__ext61__xve_slm_fence_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE1 */
#define mtlgt2__ext61__xve_slm_fence_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE2 */
#define mtlgt2__ext61__xve_slm_fence_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE3 */
#define mtlgt2__ext61__xve_slm_fence_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext65 :: GPU Time Elapsed */
#define mtlgt2__ext65__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext65 :: GPU Core Clocks */
#define mtlgt2__ext65__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext65 :: AVG GPU Core Frequency */
#define mtlgt2__ext65__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext65 :: AVG GPU Core Frequency */
#define mtlgt2__ext65__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext65 :: XVE SLM ATOMIC MESSAGE COUNT XECORE0 */
#define mtlgt2__ext65__xve_slm_atomic_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext65 :: XVE SLM ATOMIC MESSAGE COUNT XECORE1 */
#define mtlgt2__ext65__xve_slm_atomic_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext66 :: GPU Time Elapsed */
#define mtlgt2__ext66__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext66 :: GPU Core Clocks */
#define mtlgt2__ext66__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext66 :: AVG GPU Core Frequency */
#define mtlgt2__ext66__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext66 :: AVG GPU Core Frequency */
#define mtlgt2__ext66__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext66 :: XVE SLM ATOMIC MESSAGE COUNT XECORE2 */
#define mtlgt2__ext66__xve_slm_atomic_message_count_xecore2__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext66 :: XVE SLM ATOMIC MESSAGE COUNT XECORE3 */
#define mtlgt2__ext66__xve_slm_atomic_message_count_xecore3__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext73 :: GPU Time Elapsed */
#define mtlgt2__ext73__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext73 :: GPU Core Clocks */
#define mtlgt2__ext73__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext73 :: AVG GPU Core Frequency */
#define mtlgt2__ext73__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext73 :: AVG GPU Core Frequency */
#define mtlgt2__ext73__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext73 :: DATAPORT INPUT AVAILABLE XECORE0 */
#define mtlgt2__ext73__dataport_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext73 :: DATAPORT INPUT AVAILABLE XECORE1 */
#define mtlgt2__ext73__dataport_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext74 :: GPU Time Elapsed */
#define mtlgt2__ext74__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext74 :: GPU Core Clocks */
#define mtlgt2__ext74__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext74 :: AVG GPU Core Frequency */
#define mtlgt2__ext74__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext74 :: AVG GPU Core Frequency */
#define mtlgt2__ext74__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext74 :: DATAPORT INPUT AVAILABLE XECORE2 */
#define mtlgt2__ext74__dataport_input_available_xecore2__read \
   bdw__render_basic__sampler0_busy__read

/* Ext74 :: DATAPORT INPUT AVAILABLE XECORE3 */
#define mtlgt2__ext74__dataport_input_available_xecore3__read \
   bdw__render_basic__sampler1_busy__read

/* Ext77 :: GPU Time Elapsed */
#define mtlgt2__ext77__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext77 :: GPU Core Clocks */
#define mtlgt2__ext77__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext77 :: AVG GPU Core Frequency */
#define mtlgt2__ext77__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext77 :: AVG GPU Core Frequency */
#define mtlgt2__ext77__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext77 :: DATAPORT OUTPUT READY XECORE0 */
#define mtlgt2__ext77__dataport_output_ready_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext77 :: DATAPORT OUTPUT READY XECORE1 */
#define mtlgt2__ext77__dataport_output_ready_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext77 :: DATAPORT OUTPUT READY XECORE2 */
#define mtlgt2__ext77__dataport_output_ready_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext77 :: DATAPORT OUTPUT READY XECORE3 */
#define mtlgt2__ext77__dataport_output_ready_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext79 :: GPU Time Elapsed */
#define mtlgt2__ext79__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext79 :: GPU Core Clocks */
#define mtlgt2__ext79__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext79 :: AVG GPU Core Frequency */
#define mtlgt2__ext79__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext79 :: AVG GPU Core Frequency */
#define mtlgt2__ext79__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext79 :: DATAPORT BYTE READ XECORE0 */
#define mtlgt2__ext79__dataport_byte_read_xecore0__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext79 :: DATAPORT BYTE READ XECORE1 */
#define mtlgt2__ext79__dataport_byte_read_xecore1__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext80 :: GPU Time Elapsed */
#define mtlgt2__ext80__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext80 :: GPU Core Clocks */
#define mtlgt2__ext80__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext80 :: AVG GPU Core Frequency */
#define mtlgt2__ext80__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext80 :: AVG GPU Core Frequency */
#define mtlgt2__ext80__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext80 :: DATAPORT BYTE READ XECORE2 */
#define mtlgt2__ext80__dataport_byte_read_xecore2__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext80 :: DATAPORT BYTE READ XECORE3 */
#define mtlgt2__ext80__dataport_byte_read_xecore3__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext83 :: GPU Time Elapsed */
#define mtlgt2__ext83__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext83 :: GPU Core Clocks */
#define mtlgt2__ext83__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext83 :: AVG GPU Core Frequency */
#define mtlgt2__ext83__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext83 :: AVG GPU Core Frequency */
#define mtlgt2__ext83__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext83 :: DATAPORT BYTE WRITE XECORE0 */
#define mtlgt2__ext83__dataport_byte_write_xecore0__read \
   acmgt1__ext83__dataport_byte_write_xecore0__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE1 */
#define mtlgt2__ext83__dataport_byte_write_xecore1__read \
   acmgt1__ext83__dataport_byte_write_xecore1__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE2 */
#define mtlgt2__ext83__dataport_byte_write_xecore2__read \
   acmgt1__ext83__dataport_byte_write_xecore2__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE3 */
#define mtlgt2__ext83__dataport_byte_write_xecore3__read \
   acmgt1__ext83__dataport_byte_write_xecore3__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE0 */
#define mtlgt2__ext83__dataport_texture_cache_access_xecore0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE1 */
#define mtlgt2__ext83__dataport_texture_cache_access_xecore1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE2 */
#define mtlgt2__ext83__dataport_texture_cache_access_xecore2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE3 */
#define mtlgt2__ext83__dataport_texture_cache_access_xecore3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext85 :: GPU Time Elapsed */
#define mtlgt2__ext85__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext85 :: GPU Core Clocks */
#define mtlgt2__ext85__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext85 :: AVG GPU Core Frequency */
#define mtlgt2__ext85__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext85 :: AVG GPU Core Frequency */
#define mtlgt2__ext85__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE0 */
#define mtlgt2__ext85__xve_dataport_read_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE1 */
#define mtlgt2__ext85__xve_dataport_read_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE2 */
#define mtlgt2__ext85__xve_dataport_read_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE3 */
#define mtlgt2__ext85__xve_dataport_read_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext85 :: DATAPORT TEXTURE CACHE HIT XECORE0 */
#define mtlgt2__ext85__dataport_texture_cache_hit_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext85 :: DATAPORT TEXTURE CACHE HIT XECORE1 */
#define mtlgt2__ext85__dataport_texture_cache_hit_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext85 :: DATAPORT TEXTURE CACHE HIT XECORE2 */
#define mtlgt2__ext85__dataport_texture_cache_hit_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext85 :: DATAPORT TEXTURE CACHE HIT XECORE3 */
#define mtlgt2__ext85__dataport_texture_cache_hit_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext87 :: GPU Time Elapsed */
#define mtlgt2__ext87__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext87 :: GPU Core Clocks */
#define mtlgt2__ext87__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext87 :: AVG GPU Core Frequency */
#define mtlgt2__ext87__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext87 :: AVG GPU Core Frequency */
#define mtlgt2__ext87__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE0 */
#define mtlgt2__ext87__xve_dataport_write_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE1 */
#define mtlgt2__ext87__xve_dataport_write_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE2 */
#define mtlgt2__ext87__xve_dataport_write_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE3 */
#define mtlgt2__ext87__xve_dataport_write_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext91 :: GPU Time Elapsed */
#define mtlgt2__ext91__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext91 :: GPU Core Clocks */
#define mtlgt2__ext91__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext91 :: AVG GPU Core Frequency */
#define mtlgt2__ext91__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext91 :: AVG GPU Core Frequency */
#define mtlgt2__ext91__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0 */
#define mtlgt2__ext91__xve_dataport_atomic_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1 */
#define mtlgt2__ext91__xve_dataport_atomic_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2 */
#define mtlgt2__ext91__xve_dataport_atomic_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3 */
#define mtlgt2__ext91__xve_dataport_atomic_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext93 :: GPU Time Elapsed */
#define mtlgt2__ext93__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext93 :: GPU Core Clocks */
#define mtlgt2__ext93__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext93 :: AVG GPU Core Frequency */
#define mtlgt2__ext93__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext93 :: AVG GPU Core Frequency */
#define mtlgt2__ext93__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext93 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE0 */
#define mtlgt2__ext93__xve_dataport_register_response_count_xecore0__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore0__read

/* Ext93 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE1 */
#define mtlgt2__ext93__xve_dataport_register_response_count_xecore1__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext94 :: GPU Time Elapsed */
#define mtlgt2__ext94__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext94 :: GPU Core Clocks */
#define mtlgt2__ext94__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext94 :: AVG GPU Core Frequency */
#define mtlgt2__ext94__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext94 :: AVG GPU Core Frequency */
#define mtlgt2__ext94__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext94 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE2 */
#define mtlgt2__ext94__xve_dataport_register_response_count_xecore2__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext94 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE3 */
#define mtlgt2__ext94__xve_dataport_register_response_count_xecore3__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext97 :: GPU Time Elapsed */
#define mtlgt2__ext97__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext97 :: GPU Core Clocks */
#define mtlgt2__ext97__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext97 :: AVG GPU Core Frequency */
#define mtlgt2__ext97__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext97 :: AVG GPU Core Frequency */
#define mtlgt2__ext97__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE0 */
#define mtlgt2__ext97__xve_dataport_register_request_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE1 */
#define mtlgt2__ext97__xve_dataport_register_request_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE2 */
#define mtlgt2__ext97__xve_dataport_register_request_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE3 */
#define mtlgt2__ext97__xve_dataport_register_request_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext98 :: GPU Time Elapsed */
#define mtlgt2__ext98__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext98 :: GPU Core Clocks */
#define mtlgt2__ext98__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext98 :: AVG GPU Core Frequency */
#define mtlgt2__ext98__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext98 :: AVG GPU Core Frequency */
#define mtlgt2__ext98__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext98 :: SAMPLER OUTPUT READY XECORE0 */
#define mtlgt2__ext98__sampler_output_ready_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext98 :: SAMPLER OUTPUT READY XECORE1 */
#define mtlgt2__ext98__sampler_output_ready_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext98 :: SAMPLER OUTPUT READY XECORE2 */
#define mtlgt2__ext98__sampler_output_ready_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext98 :: SAMPLER OUTPUT READY XECORE3 */
#define mtlgt2__ext98__sampler_output_ready_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext100 :: GPU Time Elapsed */
#define mtlgt2__ext100__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext100 :: GPU Core Clocks */
#define mtlgt2__ext100__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext100 :: AVG GPU Core Frequency */
#define mtlgt2__ext100__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext100 :: AVG GPU Core Frequency */
#define mtlgt2__ext100__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE0 */
#define mtlgt2__ext100__sampler_memory_latency_stall_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE1 */
#define mtlgt2__ext100__sampler_memory_latency_stall_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE2 */
#define mtlgt2__ext100__sampler_memory_latency_stall_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE3 */
#define mtlgt2__ext100__sampler_memory_latency_stall_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext100 :: SAMPLER INPUT AVAILABLE XECORE0 */
#define mtlgt2__ext100__sampler_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext100 :: SAMPLER INPUT AVAILABLE XECORE1 */
#define mtlgt2__ext100__sampler_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext100 :: SAMPLER INPUT AVAILABLE XECORE2 */
#define mtlgt2__ext100__sampler_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext100 :: SAMPLER INPUT AVAILABLE XECORE3 */
#define mtlgt2__ext100__sampler_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext101 :: GPU Time Elapsed */
#define mtlgt2__ext101__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext101 :: GPU Core Clocks */
#define mtlgt2__ext101__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext101 :: AVG GPU Core Frequency */
#define mtlgt2__ext101__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext101 :: AVG GPU Core Frequency */
#define mtlgt2__ext101__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext101 :: THREAD DISPATCH STALL XECORE0 */
#define mtlgt2__ext101__thread_dispatch_stall_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext101 :: THREAD DISPATCH STALL XECORE1 */
#define mtlgt2__ext101__thread_dispatch_stall_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext101 :: THREAD DISPATCH STALL XECORE2 */
#define mtlgt2__ext101__thread_dispatch_stall_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext101 :: THREAD DISPATCH STALL XECORE3 */
#define mtlgt2__ext101__thread_dispatch_stall_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE0 */
#define mtlgt2__ext101__thread_dispatch_input_available_xecore0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE1 */
#define mtlgt2__ext101__thread_dispatch_input_available_xecore1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE2 */
#define mtlgt2__ext101__thread_dispatch_input_available_xecore2__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext101 :: THREAD DISPATCH INPUT AVAILABLE XECORE3 */
#define mtlgt2__ext101__thread_dispatch_input_available_xecore3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext102 :: GPU Time Elapsed */
#define mtlgt2__ext102__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext102 :: GPU Core Clocks */
#define mtlgt2__ext102__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext102 :: AVG GPU Core Frequency */
#define mtlgt2__ext102__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext102 :: AVG GPU Core Frequency */
#define mtlgt2__ext102__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE0 */
#define mtlgt2__ext102__sampler_texture_cache_access_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE1 */
#define mtlgt2__ext102__sampler_texture_cache_access_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE2 */
#define mtlgt2__ext102__sampler_texture_cache_access_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext102 :: SAMPLER TEXTURE CACHE ACCESS XECORE3 */
#define mtlgt2__ext102__sampler_texture_cache_access_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE0 */
#define mtlgt2__ext102__sampler_texture_cache_miss_xecore0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE1 */
#define mtlgt2__ext102__sampler_texture_cache_miss_xecore1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE2 */
#define mtlgt2__ext102__sampler_texture_cache_miss_xecore2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext102 :: SAMPLER TEXTURE CACHE MISS XECORE3 */
#define mtlgt2__ext102__sampler_texture_cache_miss_xecore3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext104 :: GPU Time Elapsed */
#define mtlgt2__ext104__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext104 :: GPU Core Clocks */
#define mtlgt2__ext104__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext104 :: AVG GPU Core Frequency */
#define mtlgt2__ext104__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext104 :: AVG GPU Core Frequency */
#define mtlgt2__ext104__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext104 :: ASYNC GPGPU THREAD EXIT COUNT XECORE0 */
#define mtlgt2__ext104__async_gpgpu_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext104 :: TASK THREAD EXIT COUNT XECORE0 */
#define mtlgt2__ext104__task_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext104 :: GPGPU THREADGROUP COUNT XECORE2 */
#define mtlgt2__ext104__gpgpu_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext104 :: TASK THREADGROUP COUNT XECORE2 */
#define mtlgt2__ext104__task_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext105 :: GPU Time Elapsed */
#define mtlgt2__ext105__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext105 :: GPU Core Clocks */
#define mtlgt2__ext105__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext105 :: AVG GPU Core Frequency */
#define mtlgt2__ext105__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext105 :: AVG GPU Core Frequency */
#define mtlgt2__ext105__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext105 :: ASYNC GPGPU THREAD EXIT COUNT XECORE1 */
#define mtlgt2__ext105__async_gpgpu_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext105 :: TASK THREAD EXIT COUNT XECORE1 */
#define mtlgt2__ext105__task_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext105 :: GPGPU THREADGROUP COUNT XECORE3 */
#define mtlgt2__ext105__gpgpu_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext105 :: TASK THREADGROUP COUNT XECORE3 */
#define mtlgt2__ext105__task_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext106 :: GPU Time Elapsed */
#define mtlgt2__ext106__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext106 :: GPU Core Clocks */
#define mtlgt2__ext106__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext106 :: AVG GPU Core Frequency */
#define mtlgt2__ext106__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext106 :: AVG GPU Core Frequency */
#define mtlgt2__ext106__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext106 :: ASYNC GPGPU THREAD EXIT COUNT XECORE2 */
#define mtlgt2__ext106__async_gpgpu_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext106 :: TASK THREAD EXIT COUNT XECORE2 */
#define mtlgt2__ext106__task_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext106 :: GPGPU THREADGROUP COUNT XECORE0 */
#define mtlgt2__ext106__gpgpu_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext106 :: TASK THREADGROUP COUNT XECORE0 */
#define mtlgt2__ext106__task_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext107 :: GPU Time Elapsed */
#define mtlgt2__ext107__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext107 :: GPU Core Clocks */
#define mtlgt2__ext107__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext107 :: AVG GPU Core Frequency */
#define mtlgt2__ext107__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext107 :: AVG GPU Core Frequency */
#define mtlgt2__ext107__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext107 :: ASYNC GPGPU THREAD EXIT COUNT XECORE3 */
#define mtlgt2__ext107__async_gpgpu_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext107 :: TASK THREAD EXIT COUNT XECORE3 */
#define mtlgt2__ext107__task_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext107 :: GPGPU THREADGROUP COUNT XECORE1 */
#define mtlgt2__ext107__gpgpu_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext107 :: TASK THREADGROUP COUNT XECORE1 */
#define mtlgt2__ext107__task_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext113 :: GPU Time Elapsed */
#define mtlgt2__ext113__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext113 :: GPU Core Clocks */
#define mtlgt2__ext113__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext113 :: AVG GPU Core Frequency */
#define mtlgt2__ext113__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext113 :: AVG GPU Core Frequency */
#define mtlgt2__ext113__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext113 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE0 */
#define mtlgt2__ext113__thread_dispatch_ps_active_cycles_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE1 */
#define mtlgt2__ext113__thread_dispatch_ps_active_cycles_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE2 */
#define mtlgt2__ext113__thread_dispatch_ps_active_cycles_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE3 */
#define mtlgt2__ext113__thread_dispatch_ps_active_cycles_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext113 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE0 */
#define mtlgt2__ext113__thread_dispatch_queue0_active_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext113 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE0 */
#define mtlgt2__ext113__thread_dispatch_queue1_active_xecore0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext113 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE1 */
#define mtlgt2__ext113__thread_dispatch_queue0_active_xecore1__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE1 */
#define mtlgt2__ext113__thread_dispatch_queue1_active_xecore1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE2 */
#define mtlgt2__ext113__thread_dispatch_queue0_active_xecore2__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE2 */
#define mtlgt2__ext113__thread_dispatch_queue1_active_xecore2__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE3 */
#define mtlgt2__ext113__thread_dispatch_queue0_active_xecore3__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE3 */
#define mtlgt2__ext113__thread_dispatch_queue1_active_xecore3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext116 :: GPU Time Elapsed */
#define mtlgt2__ext116__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext116 :: GPU Core Clocks */
#define mtlgt2__ext116__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext116 :: AVG GPU Core Frequency */
#define mtlgt2__ext116__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext116 :: AVG GPU Core Frequency */
#define mtlgt2__ext116__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE0 */
#define mtlgt2__ext116__threadgroup_dispatch_resource_stall_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE1 */
#define mtlgt2__ext116__threadgroup_dispatch_resource_stall_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE2 */
#define mtlgt2__ext116__threadgroup_dispatch_resource_stall_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE3 */
#define mtlgt2__ext116__threadgroup_dispatch_resource_stall_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext118 :: GPU Time Elapsed */
#define mtlgt2__ext118__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext118 :: GPU Core Clocks */
#define mtlgt2__ext118__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext118 :: AVG GPU Core Frequency */
#define mtlgt2__ext118__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext118 :: AVG GPU Core Frequency */
#define mtlgt2__ext118__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext118 :: AMFS STALL ALL INPUT SLICE0 */
#define mtlgt2__ext118__amfs_stall_all_input_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext118 :: AMFS STALL ANY INPUT SLICE0 */
#define mtlgt2__ext118__amfs_stall_any_input_slice0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext118 :: AMFS CACHE HIT SLICE0 */
#define mtlgt2__ext118__amfs_cache_hit_slice0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext118 :: AMFS CACHE MISS SLICE0 */
#define mtlgt2__ext118__amfs_cache_miss_slice0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext118 :: RENDER CACHE HIT L3NODE0 */
#define mtlgt2__ext118__render_cache_hit_l3_node0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext118 :: RENDER CACHE READ L3NODE0 */
#define mtlgt2__ext118__render_cache_read_l3_node0__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext118 :: RENDER CACHE WRITE L3NODE0 */
#define mtlgt2__ext118__render_cache_write_l3_node0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext118 :: RENDER CACHE INPUT AVAILABLE _L3NODE0 */
#define mtlgt2__ext118__render_cache_input_available_l3_node0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext118 :: RENDER CACHE OUTPUT READY _L3NODE0 */
#define mtlgt2__ext118__render_cache_output_ready_l3_node0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext120 :: GPU Time Elapsed */
#define mtlgt2__ext120__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext120 :: GPU Core Clocks */
#define mtlgt2__ext120__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext120 :: AVG GPU Core Frequency */
#define mtlgt2__ext120__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext120 :: AVG GPU Core Frequency */
#define mtlgt2__ext120__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE0 */
#define mtlgt2__ext120__pixel_post_process_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE1 */
#define mtlgt2__ext120__pixel_post_process_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE2 */
#define mtlgt2__ext120__pixel_post_process_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE3 */
#define mtlgt2__ext120__pixel_post_process_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext122 :: GPU Time Elapsed */
#define mtlgt2__ext122__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext122 :: GPU Core Clocks */
#define mtlgt2__ext122__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext122 :: AVG GPU Core Frequency */
#define mtlgt2__ext122__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext122 :: AVG GPU Core Frequency */
#define mtlgt2__ext122__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext122 :: AMFS 4X4 SHADING REQUEST SLICE0 */
#define mtlgt2__ext122__amfs_4_x4_shading_request_slice0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE0 */
#define mtlgt2__ext122__color_pipe_cache_latency1_stall_cpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE1 */
#define mtlgt2__ext122__color_pipe_cache_latency1_stall_cpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE0 */
#define mtlgt2__ext122__pixel_post_process_output_ready_cpipe0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE1 */
#define mtlgt2__ext122__pixel_post_process_output_ready_cpipe1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext122 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE0 */
#define mtlgt2__ext122__color_pipe_cache_latency2_stall_l3_node0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext122 :: PIXEL BACKEND INPUT AVAILABLE _L3NODE0 */
#define mtlgt2__ext122__pixel_backend_input_available_l3_node0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext122 :: PIXEL BACKEND OUTPUT READY _L3NODE0 */
#define mtlgt2__ext122__pixel_backend_output_ready_l3_node0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext123 :: GPU Time Elapsed */
#define mtlgt2__ext123__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext123 :: GPU Core Clocks */
#define mtlgt2__ext123__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext123 :: AVG GPU Core Frequency */
#define mtlgt2__ext123__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext123 :: AVG GPU Core Frequency */
#define mtlgt2__ext123__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext123 :: PS OUTPUT AVAILABLE CPIPE0 */
#define mtlgt2__ext123__ps_output_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext123 :: PS OUTPUT AVAILABLE CPIPE1 */
#define mtlgt2__ext123__ps_output_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext123 :: AMFS L3 ACCESS SLICE0 */
#define mtlgt2__ext123__amfs_l3_access_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext123 :: AMFS L3 ATOMIC SLICE0 */
#define mtlgt2__ext123__amfs_l3_atomic_slice0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext123 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0 */
static uint64_t
mtlgt2__ext123__clipper_primitive_far_near_clip_slice0__read(UNUSED struct intel_perf_config *perf,
                                                             const struct intel_perf_query_info *query,
                                                             const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ C 5 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext124 :: GPU Time Elapsed */
#define mtlgt2__ext124__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext124 :: GPU Core Clocks */
#define mtlgt2__ext124__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext124 :: AVG GPU Core Frequency */
#define mtlgt2__ext124__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext124 :: AVG GPU Core Frequency */
#define mtlgt2__ext124__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext124 :: VERTEX FETCH INPUT AVAILABLE SLICE0 */
#define mtlgt2__ext124__vertex_fetch_input_available_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext124 :: VERTEX FETCH OUTPUT READY SLICE0 */
#define mtlgt2__ext124__vertex_fetch_output_ready_slice0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext124 :: CLIPPER INPUT VERTEX SLICE0 */
#define mtlgt2__ext124__clipper_input_vertex_slice0__read \
   mtlgt2__ext123__clipper_primitive_far_near_clip_slice0__read

/* Ext124 :: STREAMOUT OUTPUT VERTEX COUNT SLICE0 */
#define mtlgt2__ext124__streamout_output_vertex_count_slice0__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext124 :: VS OUTPUT READY SLICE0 */
#define mtlgt2__ext124__vs_output_ready_slice0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext124 :: CLIPPER INPUT AVAILABLE SLICE0 */
#define mtlgt2__ext124__clipper_input_available_slice0__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext124 :: CLIPPER OUTPUT READY SLICE0 */
#define mtlgt2__ext124__clipper_output_ready_slice0__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext124 :: CLIPPER PRIMITIVE OUTPUT SLICE0 */
#define mtlgt2__ext124__clipper_primitive_output_slice0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext124 :: STRIPSFAN OUTPUT READY SLICE0 */
#define mtlgt2__ext124__stripsfan_output_ready_slice0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext126 :: GPU Time Elapsed */
#define mtlgt2__ext126__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext126 :: GPU Core Clocks */
#define mtlgt2__ext126__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext126 :: AVG GPU Core Frequency */
#define mtlgt2__ext126__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext126 :: AVG GPU Core Frequency */
#define mtlgt2__ext126__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext126 :: STRIPSFAN OBJECT COUNT SLICE0 */
#define mtlgt2__ext126__stripsfan_object_count_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext126 :: STRIPSFAN OBJECTS CULL SLICE0 */
#define mtlgt2__ext126__stripsfan_objects_cull_slice0__read \
   mtlgt2__ext123__clipper_primitive_far_near_clip_slice0__read

/* Ext126 :: CLIPPER TRANSACTION OUTPUT SLICE0 */
#define mtlgt2__ext126__clipper_transaction_output_slice0__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext126 :: RASTERIZER TRANSACTION OUTPUT SLICE0 */
#define mtlgt2__ext126__rasterizer_transaction_output_slice0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext126 :: CLIPPER PRIMITIVE CULL SLICE0 */
#define mtlgt2__ext126__clipper_primitive_cull_slice0__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext126 :: RASTERIZER INPUT AVAILABLE SLICE0 */
#define mtlgt2__ext126__rasterizer_input_available_slice0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext126 :: RASTERIZER OUTPUT READY SLICE0 */
#define mtlgt2__ext126__rasterizer_output_ready_slice0__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext128 :: GPU Time Elapsed */
#define mtlgt2__ext128__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext128 :: GPU Core Clocks */
#define mtlgt2__ext128__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext128 :: AVG GPU Core Frequency */
#define mtlgt2__ext128__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext128 :: AVG GPU Core Frequency */
#define mtlgt2__ext128__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext128 :: URB READ SLICE0 */
#define mtlgt2__ext128__urb_read_slice0__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext128 :: URB WRITE SLICE0 */
#define mtlgt2__ext128__urb_write_slice0__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext128 :: URB CROSS SLICE READ SLICE0 */
#define mtlgt2__ext128__urb_cross_slice_read_slice0__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext130 :: GPU Time Elapsed */
#define mtlgt2__ext130__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext130 :: GPU Core Clocks */
#define mtlgt2__ext130__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext130 :: AVG GPU Core Frequency */
#define mtlgt2__ext130__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext130 :: AVG GPU Core Frequency */
#define mtlgt2__ext130__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext130 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0 */
#define mtlgt2__ext130__early_depth_stencil_test_fail_np_zpipe0__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext130 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE0 */
#define mtlgt2__ext130__early_depth_stencil_test_fail_p_zpipe0__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext131 :: GPU Time Elapsed */
#define mtlgt2__ext131__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext131 :: GPU Core Clocks */
#define mtlgt2__ext131__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext131 :: AVG GPU Core Frequency */
#define mtlgt2__ext131__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext131 :: AVG GPU Core Frequency */
#define mtlgt2__ext131__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext131 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1 */
#define mtlgt2__ext131__early_depth_stencil_test_fail_np_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext131 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE1 */
#define mtlgt2__ext131__early_depth_stencil_test_fail_p_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext134 :: GPU Time Elapsed */
#define mtlgt2__ext134__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext134 :: GPU Core Clocks */
#define mtlgt2__ext134__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext134 :: AVG GPU Core Frequency */
#define mtlgt2__ext134__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext134 :: AVG GPU Core Frequency */
#define mtlgt2__ext134__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext134 :: HIZ DEPTH TEST AMBIG NP ZPIPE0 */
static uint64_t
mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD 16 C 3 READ UMUL UADD 32 C 2 READ UMUL UADD 64 C 1 READ UMUL UADD 128 C 0 READ UMUL UADD 256 B 7 READ UMUL UADD 512 B 6 READ UMUL UADD 1024 B 5 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 2];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 1];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->c_offset + 0];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;
   uint64_t tmp22 = results->accumulator[query->b_offset + 7];
   uint64_t tmp23 = 256 * tmp22;
   uint64_t tmp24 = tmp21 + tmp23;
   uint64_t tmp25 = results->accumulator[query->b_offset + 6];
   uint64_t tmp26 = 512 * tmp25;
   uint64_t tmp27 = tmp24 + tmp26;
   uint64_t tmp28 = results->accumulator[query->b_offset + 5];
   uint64_t tmp29 = 1024 * tmp28;
   uint64_t tmp30 = tmp27 + tmp29;

   return tmp30;
}

/* Ext135 :: GPU Time Elapsed */
#define mtlgt2__ext135__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext135 :: GPU Core Clocks */
#define mtlgt2__ext135__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext135 :: AVG GPU Core Frequency */
#define mtlgt2__ext135__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext135 :: AVG GPU Core Frequency */
#define mtlgt2__ext135__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext135 :: HIZ DEPTH TEST AMBIG NP ZPIPE1 */
#define mtlgt2__ext135__hiz_depth_test_ambig_np_zpipe1__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext138 :: GPU Time Elapsed */
#define mtlgt2__ext138__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext138 :: GPU Core Clocks */
#define mtlgt2__ext138__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext138 :: AVG GPU Core Frequency */
#define mtlgt2__ext138__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext138 :: AVG GPU Core Frequency */
#define mtlgt2__ext138__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext138 :: HIZ DEPTH TEST AMBIG P ZPIPE0 */
#define mtlgt2__ext138__hiz_depth_test_ambig_p_zpipe0__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext139 :: GPU Time Elapsed */
#define mtlgt2__ext139__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext139 :: GPU Core Clocks */
#define mtlgt2__ext139__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext139 :: AVG GPU Core Frequency */
#define mtlgt2__ext139__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext139 :: AVG GPU Core Frequency */
#define mtlgt2__ext139__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext139 :: HIZ DEPTH TEST AMBIG P ZPIPE1 */
#define mtlgt2__ext139__hiz_depth_test_ambig_p_zpipe1__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext142 :: GPU Time Elapsed */
#define mtlgt2__ext142__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext142 :: GPU Core Clocks */
#define mtlgt2__ext142__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext142 :: AVG GPU Core Frequency */
#define mtlgt2__ext142__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext142 :: AVG GPU Core Frequency */
#define mtlgt2__ext142__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext142 :: HIZ DEPTH TEST FAIL NP ZPIPE0 */
#define mtlgt2__ext142__hiz_depth_test_fail_np_zpipe0__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext143 :: GPU Time Elapsed */
#define mtlgt2__ext143__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext143 :: GPU Core Clocks */
#define mtlgt2__ext143__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext143 :: AVG GPU Core Frequency */
#define mtlgt2__ext143__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext143 :: AVG GPU Core Frequency */
#define mtlgt2__ext143__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext143 :: HIZ DEPTH TEST FAIL NP ZPIPE1 */
#define mtlgt2__ext143__hiz_depth_test_fail_np_zpipe1__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext146 :: GPU Time Elapsed */
#define mtlgt2__ext146__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext146 :: GPU Core Clocks */
#define mtlgt2__ext146__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext146 :: AVG GPU Core Frequency */
#define mtlgt2__ext146__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext146 :: AVG GPU Core Frequency */
#define mtlgt2__ext146__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext146 :: HIZ DEPTH TEST FAIL P ZPIPE0 */
#define mtlgt2__ext146__hiz_depth_test_fail_p_zpipe0__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext147 :: GPU Time Elapsed */
#define mtlgt2__ext147__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext147 :: GPU Core Clocks */
#define mtlgt2__ext147__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext147 :: AVG GPU Core Frequency */
#define mtlgt2__ext147__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext147 :: AVG GPU Core Frequency */
#define mtlgt2__ext147__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext147 :: HIZ DEPTH TEST FAIL P ZPIPE1 */
#define mtlgt2__ext147__hiz_depth_test_fail_p_zpipe1__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext150 :: GPU Time Elapsed */
#define mtlgt2__ext150__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext150 :: GPU Core Clocks */
#define mtlgt2__ext150__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext150 :: AVG GPU Core Frequency */
#define mtlgt2__ext150__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext150 :: AVG GPU Core Frequency */
#define mtlgt2__ext150__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext150 :: HIZ DEPTH TEST PASS P ZPIPE0 */
static uint64_t
mtlgt2__ext150__hiz_depth_test_pass_p_zpipe0__read(UNUSED struct intel_perf_config *perf,
                                                   const struct intel_perf_query_info *query,
                                                   const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD 16 C 3 READ UMUL UADD 32 C 2 READ UMUL UADD 64 C 1 READ UMUL UADD 128 C 0 READ UMUL UADD 256 B 7 READ UMUL UADD 512 B 6 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 2];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 1];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->c_offset + 0];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;
   uint64_t tmp22 = results->accumulator[query->b_offset + 7];
   uint64_t tmp23 = 256 * tmp22;
   uint64_t tmp24 = tmp21 + tmp23;
   uint64_t tmp25 = results->accumulator[query->b_offset + 6];
   uint64_t tmp26 = 512 * tmp25;
   uint64_t tmp27 = tmp24 + tmp26;

   return tmp27;
}

/* Ext151 :: GPU Time Elapsed */
#define mtlgt2__ext151__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext151 :: GPU Core Clocks */
#define mtlgt2__ext151__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext151 :: AVG GPU Core Frequency */
#define mtlgt2__ext151__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext151 :: AVG GPU Core Frequency */
#define mtlgt2__ext151__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext151 :: HIZ DEPTH TEST PASS P ZPIPE1 */
#define mtlgt2__ext151__hiz_depth_test_pass_p_zpipe1__read \
   mtlgt2__ext150__hiz_depth_test_pass_p_zpipe0__read

/* Ext154 :: GPU Time Elapsed */
#define mtlgt2__ext154__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext154 :: GPU Core Clocks */
#define mtlgt2__ext154__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext154 :: AVG GPU Core Frequency */
#define mtlgt2__ext154__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext154 :: AVG GPU Core Frequency */
#define mtlgt2__ext154__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define mtlgt2__ext154__hiz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define mtlgt2__ext154__hiz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define mtlgt2__ext154__iz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define mtlgt2__ext154__iz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext154 :: IZ OUTPUT READY ZPIPE0 */
#define mtlgt2__ext154__iz_output_ready_zpipe0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext154 :: IZ OUTPUT READY ZPIPE1 */
#define mtlgt2__ext154__iz_output_ready_zpipe1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext155 :: GPU Time Elapsed */
#define mtlgt2__ext155__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext155 :: GPU Core Clocks */
#define mtlgt2__ext155__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext155 :: AVG GPU Core Frequency */
#define mtlgt2__ext155__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext155 :: AVG GPU Core Frequency */
#define mtlgt2__ext155__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext155 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS0 */
#define mtlgt2__ext155__command_parser_compute_engine_busy_ccs0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext155 :: COMMAND PARSER RENDER ENGINE BUSY */
#define mtlgt2__ext155__command_parser_render_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Ext155 :: COMMAND PARSER COPY ENGINE BUSY */
#define mtlgt2__ext155__command_parser_copy_engine_busy__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext156 :: GPU Time Elapsed */
#define mtlgt2__ext156__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext156 :: GPU Core Clocks */
#define mtlgt2__ext156__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext156 :: AVG GPU Core Frequency */
#define mtlgt2__ext156__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext156 :: AVG GPU Core Frequency */
#define mtlgt2__ext156__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext156 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0 */
#define mtlgt2__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext156 :: COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT */
#define mtlgt2__ext156__command_parser_render_engine_dispatch_kernel_count__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext156 :: COMMAND PARSER RENDER ENGINE DRAW COUNT */
#define mtlgt2__ext156__command_parser_render_engine_draw_count__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext156 :: COMMAND PARSER FLUSH COUNT */
#define mtlgt2__ext156__command_parser_flush_count__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext158 :: GPU Time Elapsed */
#define mtlgt2__ext158__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext158 :: GPU Core Clocks */
#define mtlgt2__ext158__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext158 :: AVG GPU Core Frequency */
#define mtlgt2__ext158__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext158 :: AVG GPU Core Frequency */
#define mtlgt2__ext158__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE0 */
#define mtlgt2__ext158__rt_input_message_ray_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE1 */
#define mtlgt2__ext158__rt_input_message_ray_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE2 */
#define mtlgt2__ext158__rt_input_message_ray_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE3 */
#define mtlgt2__ext158__rt_input_message_ray_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext159 :: GPU Time Elapsed */
#define mtlgt2__ext159__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext159 :: GPU Core Clocks */
#define mtlgt2__ext159__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext159 :: AVG GPU Core Frequency */
#define mtlgt2__ext159__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext159 :: AVG GPU Core Frequency */
#define mtlgt2__ext159__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE0 */
#define mtlgt2__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE1 */
#define mtlgt2__ext159__rt_closest_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE2 */
#define mtlgt2__ext159__rt_closest_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE3 */
#define mtlgt2__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext161 :: GPU Time Elapsed */
#define mtlgt2__ext161__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext161 :: GPU Core Clocks */
#define mtlgt2__ext161__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext161 :: AVG GPU Core Frequency */
#define mtlgt2__ext161__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext161 :: AVG GPU Core Frequency */
#define mtlgt2__ext161__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE0 */
#define mtlgt2__ext161__rt_miss_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE1 */
#define mtlgt2__ext161__rt_miss_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE2 */
#define mtlgt2__ext161__rt_miss_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE3 */
#define mtlgt2__ext161__rt_miss_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext163 :: GPU Time Elapsed */
#define mtlgt2__ext163__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext163 :: GPU Core Clocks */
#define mtlgt2__ext163__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext163 :: AVG GPU Core Frequency */
#define mtlgt2__ext163__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext163 :: AVG GPU Core Frequency */
#define mtlgt2__ext163__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE0 */
#define mtlgt2__ext163__rt_any_hit_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE1 */
#define mtlgt2__ext163__rt_any_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE2 */
#define mtlgt2__ext163__rt_any_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE3 */
#define mtlgt2__ext163__rt_any_hit_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext165 :: GPU Time Elapsed */
#define mtlgt2__ext165__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext165 :: GPU Core Clocks */
#define mtlgt2__ext165__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext165 :: AVG GPU Core Frequency */
#define mtlgt2__ext165__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext165 :: AVG GPU Core Frequency */
#define mtlgt2__ext165__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE0 */
#define mtlgt2__ext165__rt_intersection_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE1 */
#define mtlgt2__ext165__rt_intersection_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE2 */
#define mtlgt2__ext165__rt_intersection_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE3 */
#define mtlgt2__ext165__rt_intersection_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext167 :: GPU Time Elapsed */
#define mtlgt2__ext167__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext167 :: GPU Core Clocks */
#define mtlgt2__ext167__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext167 :: AVG GPU Core Frequency */
#define mtlgt2__ext167__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext167 :: AVG GPU Core Frequency */
#define mtlgt2__ext167__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE0 */
#define mtlgt2__ext167__rt_callable_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE1 */
#define mtlgt2__ext167__rt_callable_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE2 */
#define mtlgt2__ext167__rt_callable_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE3 */
#define mtlgt2__ext167__rt_callable_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext169 :: GPU Time Elapsed */
#define mtlgt2__ext169__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext169 :: GPU Core Clocks */
#define mtlgt2__ext169__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext169 :: AVG GPU Core Frequency */
#define mtlgt2__ext169__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext169 :: AVG GPU Core Frequency */
#define mtlgt2__ext169__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE0 */
#define mtlgt2__ext169__rt_traversal_output_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE1 */
#define mtlgt2__ext169__rt_traversal_output_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE2 */
#define mtlgt2__ext169__rt_traversal_output_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE3 */
#define mtlgt2__ext169__rt_traversal_output_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext171 :: GPU Time Elapsed */
#define mtlgt2__ext171__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext171 :: GPU Core Clocks */
#define mtlgt2__ext171__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext171 :: AVG GPU Core Frequency */
#define mtlgt2__ext171__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext171 :: AVG GPU Core Frequency */
#define mtlgt2__ext171__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE0 */
#define mtlgt2__ext171__rt_quad_test_ray_count_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE1 */
#define mtlgt2__ext171__rt_quad_test_ray_count_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE2 */
#define mtlgt2__ext171__rt_quad_test_ray_count_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE3 */
#define mtlgt2__ext171__rt_quad_test_ray_count_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE0 */
#define mtlgt2__ext171__rt_transform_ray_count_xecore0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE1 */
#define mtlgt2__ext171__rt_transform_ray_count_xecore1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE2 */
#define mtlgt2__ext171__rt_transform_ray_count_xecore2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE3 */
#define mtlgt2__ext171__rt_transform_ray_count_xecore3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext171 :: RT REQUEST COLLISION XECORE0 */
#define mtlgt2__ext171__rt_request_collision_xecore0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext171 :: RT REQUEST COLLISION XECORE1 */
#define mtlgt2__ext171__rt_request_collision_xecore1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext171 :: RT REQUEST COLLISION XECORE2 */
#define mtlgt2__ext171__rt_request_collision_xecore2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext171 :: RT REQUEST COLLISION XECORE3 */
#define mtlgt2__ext171__rt_request_collision_xecore3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext171 :: RT MESSAGE STALL COUNT XECORE0 */
#define mtlgt2__ext171__rt_message_stall_count_xecore0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext171 :: RT MESSAGE STALL COUNT XECORE1 */
#define mtlgt2__ext171__rt_message_stall_count_xecore1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext171 :: RT MESSAGE STALL COUNT XECORE2 */
#define mtlgt2__ext171__rt_message_stall_count_xecore2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext171 :: RT MESSAGE STALL COUNT XECORE3 */
#define mtlgt2__ext171__rt_message_stall_count_xecore3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext173 :: GPU Time Elapsed */
#define mtlgt2__ext173__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext173 :: GPU Core Clocks */
#define mtlgt2__ext173__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext173 :: AVG GPU Core Frequency */
#define mtlgt2__ext173__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext173 :: AVG GPU Core Frequency */
#define mtlgt2__ext173__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext173 :: XVE STALL ALUWR XECORE0 XVE0 THREAD0 */
#define mtlgt2__ext173__xve_stall_aluwr_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext173 :: XVE STALL BARRIER XECORE0 XVE0 THREAD0 */
#define mtlgt2__ext173__xve_stall_barrier_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext173 :: XVE STALL INSTFETCH XECORE0 XVE0 THREAD0 */
#define mtlgt2__ext173__xve_stall_instfetch_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext173 :: XVE STALL OTHER XECORE0 XVE0 THREAD0 */
#define mtlgt2__ext173__xve_stall_other_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext173 :: XVE STALL SBID XECORE0 XVE0 THREAD0 */
#define mtlgt2__ext173__xve_stall_sbid_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext173 :: XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0 */
#define mtlgt2__ext173__xve_shared_function_access_hold_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext173 :: XVE STALL CONTROL XECORE0 XVE0 THREAD0 */
#define mtlgt2__ext173__xve_stall_control_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext174 :: GPU Time Elapsed */
#define mtlgt2__ext174__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext174 :: GPU Core Clocks */
#define mtlgt2__ext174__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext174 :: AVG GPU Core Frequency */
#define mtlgt2__ext174__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext174 :: AVG GPU Core Frequency */
#define mtlgt2__ext174__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext174 :: XVE STALL ALUWR XECORE1 XVE0 THREAD0 */
#define mtlgt2__ext174__xve_stall_aluwr_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext174 :: XVE STALL BARRIER XECORE1 XVE0 THREAD0 */
#define mtlgt2__ext174__xve_stall_barrier_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext174 :: XVE STALL INSTFETCH XECORE1 XVE0 THREAD0 */
#define mtlgt2__ext174__xve_stall_instfetch_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext174 :: XVE STALL OTHER XECORE1 XVE0 THREAD0 */
#define mtlgt2__ext174__xve_stall_other_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext174 :: XVE STALL SBID XECORE1 XVE0 THREAD0 */
#define mtlgt2__ext174__xve_stall_sbid_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext174 :: XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0 */
#define mtlgt2__ext174__xve_shared_function_access_hold_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext174 :: XVE STALL CONTROL XECORE1 XVE0 THREAD0 */
#define mtlgt2__ext174__xve_stall_control_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext175 :: GPU Time Elapsed */
#define mtlgt2__ext175__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext175 :: GPU Core Clocks */
#define mtlgt2__ext175__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext175 :: AVG GPU Core Frequency */
#define mtlgt2__ext175__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext175 :: AVG GPU Core Frequency */
#define mtlgt2__ext175__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext175 :: XVE STALL ALUWR XECORE2 XVE0 THREAD0 */
#define mtlgt2__ext175__xve_stall_aluwr_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext175 :: XVE STALL BARRIER XECORE2 XVE0 THREAD0 */
#define mtlgt2__ext175__xve_stall_barrier_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext175 :: XVE STALL INSTFETCH XECORE2 XVE0 THREAD0 */
#define mtlgt2__ext175__xve_stall_instfetch_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext175 :: XVE STALL OTHER XECORE2 XVE0 THREAD0 */
#define mtlgt2__ext175__xve_stall_other_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext175 :: XVE STALL SBID XECORE2 XVE0 THREAD0 */
#define mtlgt2__ext175__xve_stall_sbid_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext175 :: XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0 */
#define mtlgt2__ext175__xve_shared_function_access_hold_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext175 :: XVE STALL CONTROL XECORE2 XVE0 THREAD0 */
#define mtlgt2__ext175__xve_stall_control_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext176 :: GPU Time Elapsed */
#define mtlgt2__ext176__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext176 :: GPU Core Clocks */
#define mtlgt2__ext176__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext176 :: AVG GPU Core Frequency */
#define mtlgt2__ext176__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext176 :: AVG GPU Core Frequency */
#define mtlgt2__ext176__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext176 :: XVE STALL ALUWR XECORE3 XVE0 THREAD0 */
#define mtlgt2__ext176__xve_stall_aluwr_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext176 :: XVE STALL BARRIER XECORE3 XVE0 THREAD0 */
#define mtlgt2__ext176__xve_stall_barrier_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext176 :: XVE STALL INSTFETCH XECORE3 XVE0 THREAD0 */
#define mtlgt2__ext176__xve_stall_instfetch_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext176 :: XVE STALL OTHER XECORE3 XVE0 THREAD0 */
#define mtlgt2__ext176__xve_stall_other_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext176 :: XVE STALL SBID XECORE3 XVE0 THREAD0 */
#define mtlgt2__ext176__xve_stall_sbid_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext176 :: XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0 */
#define mtlgt2__ext176__xve_shared_function_access_hold_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext176 :: XVE STALL CONTROL XECORE3 XVE0 THREAD0 */
#define mtlgt2__ext176__xve_stall_control_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext177 :: GPU Time Elapsed */
#define mtlgt2__ext177__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext177 :: GPU Core Clocks */
#define mtlgt2__ext177__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext177 :: AVG GPU Core Frequency */
#define mtlgt2__ext177__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext177 :: AVG GPU Core Frequency */
#define mtlgt2__ext177__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext177 :: XVE STALL PIPESTALL XECORE0 XVE0 */
#define mtlgt2__ext177__xve_stall_pipestall_xecore0_xve0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext177 :: XVE STALL PIPESTALL XECORE1 XVE0 */
#define mtlgt2__ext177__xve_stall_pipestall_xecore1_xve0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext177 :: XVE STALL PIPESTALL XECORE2 XVE0 */
#define mtlgt2__ext177__xve_stall_pipestall_xecore2_xve0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext177 :: XVE STALL PIPESTALL XECORE3 XVE0 */
#define mtlgt2__ext177__xve_stall_pipestall_xecore3_xve0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext177 :: XVE INST ISSUED ALL XECORE3 XVE0 */
#define mtlgt2__ext177__xve_inst_issued_all_xecore3_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext177 :: RENDER CACHE ALLOC L3NODE0 */
#define mtlgt2__ext177__render_cache_alloc_l3_node0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext181 :: GPU Time Elapsed */
#define mtlgt2__ext181__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext181 :: GPU Core Clocks */
#define mtlgt2__ext181__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext181 :: AVG GPU Core Frequency */
#define mtlgt2__ext181__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext181 :: AVG GPU Core Frequency */
#define mtlgt2__ext181__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext181 :: XVE INST ISSUED ALL XECORE0 XVE0 */
#define mtlgt2__ext181__xve_inst_issued_all_xecore0_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext181 :: XVE INST ISSUED ALL XECORE1 XVE0 */
#define mtlgt2__ext181__xve_inst_issued_all_xecore1_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext181 :: XVE INST ISSUED ALL XECORE2 XVE0 */
#define mtlgt2__ext181__xve_inst_issued_all_xecore2_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext184 :: GPU Time Elapsed */
#define mtlgt2__ext184__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext184 :: GPU Core Clocks */
#define mtlgt2__ext184__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext184 :: AVG GPU Core Frequency */
#define mtlgt2__ext184__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext184 :: AVG GPU Core Frequency */
#define mtlgt2__ext184__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext184 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define mtlgt2__ext184__rt_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext184 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define mtlgt2__ext184__rt_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext184 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define mtlgt2__ext184__rt_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext184 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define mtlgt2__ext184__rt_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext188 :: GPU Time Elapsed */
#define mtlgt2__ext188__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext188 :: GPU Core Clocks */
#define mtlgt2__ext188__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext188 :: AVG GPU Core Frequency */
#define mtlgt2__ext188__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext188 :: AVG GPU Core Frequency */
#define mtlgt2__ext188__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0 */
#define mtlgt2__ext188__rt_load_store_cache_write_from_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1 */
#define mtlgt2__ext188__rt_load_store_cache_write_from_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2 */
#define mtlgt2__ext188__rt_load_store_cache_write_from_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3 */
#define mtlgt2__ext188__rt_load_store_cache_write_from_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext190 :: GPU Time Elapsed */
#define mtlgt2__ext190__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext190 :: GPU Core Clocks */
#define mtlgt2__ext190__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext190 :: AVG GPU Core Frequency */
#define mtlgt2__ext190__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext190 :: AVG GPU Core Frequency */
#define mtlgt2__ext190__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext190 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE0 */
#define mtlgt2__ext190__pixel_post_process_input_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext190 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE1 */
#define mtlgt2__ext190__pixel_post_process_input_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext192 :: GPU Time Elapsed */
#define mtlgt2__ext192__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext192 :: GPU Core Clocks */
#define mtlgt2__ext192__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext192 :: AVG GPU Core Frequency */
#define mtlgt2__ext192__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext192 :: AVG GPU Core Frequency */
#define mtlgt2__ext192__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext192 :: RT INPUT AVAILABLE XECORE0 */
#define mtlgt2__ext192__rt_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext192 :: RT INPUT AVAILABLE XECORE1 */
#define mtlgt2__ext192__rt_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext192 :: RT INPUT AVAILABLE XECORE2 */
#define mtlgt2__ext192__rt_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext192 :: RT INPUT AVAILABLE XECORE3 */
#define mtlgt2__ext192__rt_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext192 :: RT TRAVERSAL STEP RAY COUNT XECORE0 */
#define mtlgt2__ext192__rt_traversal_step_ray_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext192 :: RT TRAVERSAL STEP RAY COUNT XECORE1 */
#define mtlgt2__ext192__rt_traversal_step_ray_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext192 :: RT TRAVERSAL STEP RAY COUNT XECORE2 */
#define mtlgt2__ext192__rt_traversal_step_ray_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext192 :: RT TRAVERSAL STEP RAY COUNT XECORE3 */
#define mtlgt2__ext192__rt_traversal_step_ray_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext195 :: GPU Time Elapsed */
#define mtlgt2__ext195__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext195 :: GPU Core Clocks */
#define mtlgt2__ext195__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext195 :: AVG GPU Core Frequency */
#define mtlgt2__ext195__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext195 :: AVG GPU Core Frequency */
#define mtlgt2__ext195__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0 */
#define mtlgt2__ext195__xve_multiple_pipe_active_xecore0_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0 */
#define mtlgt2__ext195__xve_multiple_pipe_active_xecore1_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0 */
#define mtlgt2__ext195__xve_multiple_pipe_active_xecore2_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0 */
#define mtlgt2__ext195__xve_multiple_pipe_active_xecore3_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext195 :: GPGPU DISPATCH XECORE0 */
#define mtlgt2__ext195__gpgpu_dispatch_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext195 :: GPGPU DISPATCH XECORE1 */
#define mtlgt2__ext195__gpgpu_dispatch_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext195 :: GPGPU DISPATCH XECORE2 */
#define mtlgt2__ext195__gpgpu_dispatch_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext195 :: GPGPU DISPATCH XECORE3 */
#define mtlgt2__ext195__gpgpu_dispatch_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext200 :: GPU Time Elapsed */
#define mtlgt2__ext200__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext200 :: GPU Core Clocks */
#define mtlgt2__ext200__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext200 :: AVG GPU Core Frequency */
#define mtlgt2__ext200__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext200 :: AVG GPU Core Frequency */
#define mtlgt2__ext200__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext200 :: SLM ACCESS COUNT BANK0 XECORE0 */
#define mtlgt2__ext200__slm_access_count_bank0_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext200 :: SLM ACCESS COUNT BANK0 XECORE1 */
#define mtlgt2__ext200__slm_access_count_bank0_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext200 :: SLM ACCESS COUNT BANK0 XECORE2 */
#define mtlgt2__ext200__slm_access_count_bank0_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext200 :: SLM ACCESS COUNT BANK0 XECORE3 */
#define mtlgt2__ext200__slm_access_count_bank0_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext201 :: GPU Time Elapsed */
#define mtlgt2__ext201__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext201 :: GPU Core Clocks */
#define mtlgt2__ext201__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext201 :: AVG GPU Core Frequency */
#define mtlgt2__ext201__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext201 :: AVG GPU Core Frequency */
#define mtlgt2__ext201__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext201 :: SLM ACCESS COUNT BANK1 XECORE0 */
#define mtlgt2__ext201__slm_access_count_bank1_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext201 :: SLM ACCESS COUNT BANK1 XECORE1 */
#define mtlgt2__ext201__slm_access_count_bank1_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext201 :: SLM ACCESS COUNT BANK1 XECORE2 */
#define mtlgt2__ext201__slm_access_count_bank1_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext201 :: SLM ACCESS COUNT BANK1 XECORE3 */
#define mtlgt2__ext201__slm_access_count_bank1_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext202 :: GPU Time Elapsed */
#define mtlgt2__ext202__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext202 :: GPU Core Clocks */
#define mtlgt2__ext202__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext202 :: AVG GPU Core Frequency */
#define mtlgt2__ext202__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext202 :: AVG GPU Core Frequency */
#define mtlgt2__ext202__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext202 :: GPU MEMORY L3 WRITE SQIDI0 */
#define mtlgt2__ext202__gpu_memory_l3_write_sqidi0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext203 :: GPU Time Elapsed */
#define mtlgt2__ext203__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext203 :: GPU Core Clocks */
#define mtlgt2__ext203__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext203 :: AVG GPU Core Frequency */
#define mtlgt2__ext203__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext203 :: AVG GPU Core Frequency */
#define mtlgt2__ext203__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext203 :: GPU MEMORY L3 WRITE SQIDI1 */
#define mtlgt2__ext203__gpu_memory_l3_write_sqidi1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext204 :: GPU Time Elapsed */
#define mtlgt2__ext204__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext204 :: GPU Core Clocks */
#define mtlgt2__ext204__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext204 :: AVG GPU Core Frequency */
#define mtlgt2__ext204__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext204 :: AVG GPU Core Frequency */
#define mtlgt2__ext204__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext204 :: RT INTERNAL NODE RAY COUNT XECORE0 */
#define mtlgt2__ext204__rt_internal_node_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext204 :: RT INTERNAL NODE RAY COUNT XECORE1 */
#define mtlgt2__ext204__rt_internal_node_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext204 :: RT INTERNAL NODE RAY COUNT XECORE2 */
#define mtlgt2__ext204__rt_internal_node_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext204 :: RT INTERNAL NODE RAY COUNT XECORE3 */
#define mtlgt2__ext204__rt_internal_node_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext205 :: GPU Time Elapsed */
#define mtlgt2__ext205__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext205 :: GPU Core Clocks */
#define mtlgt2__ext205__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext205 :: AVG GPU Core Frequency */
#define mtlgt2__ext205__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext205 :: AVG GPU Core Frequency */
#define mtlgt2__ext205__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext205 :: RT INSTANCE NODE RAY COUNT XECORE0 */
#define mtlgt2__ext205__rt_instance_node_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext205 :: RT INSTANCE NODE RAY COUNT XECORE1 */
#define mtlgt2__ext205__rt_instance_node_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext205 :: RT INSTANCE NODE RAY COUNT XECORE2 */
#define mtlgt2__ext205__rt_instance_node_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext205 :: RT INSTANCE NODE RAY COUNT XECORE3 */
#define mtlgt2__ext205__rt_instance_node_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext212 :: GPU Time Elapsed */
#define mtlgt2__ext212__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext212 :: GPU Core Clocks */
#define mtlgt2__ext212__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext212 :: AVG GPU Core Frequency */
#define mtlgt2__ext212__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext212 :: AVG GPU Core Frequency */
#define mtlgt2__ext212__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext212 :: RT QUAD LEAF RAY COUNT XECORE0 */
#define mtlgt2__ext212__rt_quad_leaf_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext212 :: RT PROCEDURAL NODE RAY COUNT XECORE0 */
#define mtlgt2__ext212__rt_procedural_node_ray_count_xecore0__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext212 :: RT QUAD LEAF RAY COUNT XECORE1 */
#define mtlgt2__ext212__rt_quad_leaf_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext212 :: RT PROCEDURAL NODE RAY COUNT XECORE1 */
#define mtlgt2__ext212__rt_procedural_node_ray_count_xecore1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext214 :: GPU Time Elapsed */
#define mtlgt2__ext214__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext214 :: GPU Core Clocks */
#define mtlgt2__ext214__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext214 :: AVG GPU Core Frequency */
#define mtlgt2__ext214__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext214 :: AVG GPU Core Frequency */
#define mtlgt2__ext214__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext214 :: RT QUAD LEAF RAY COUNT XECORE2 */
#define mtlgt2__ext214__rt_quad_leaf_ray_count_xecore2__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext214 :: RT PROCEDURAL NODE RAY COUNT XECORE2 */
#define mtlgt2__ext214__rt_procedural_node_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext214 :: RT QUAD LEAF RAY COUNT XECORE3 */
#define mtlgt2__ext214__rt_quad_leaf_ray_count_xecore3__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext214 :: RT PROCEDURAL NODE RAY COUNT XECORE3 */
#define mtlgt2__ext214__rt_procedural_node_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext220 :: GPU Time Elapsed */
#define mtlgt2__ext220__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext220 :: GPU Core Clocks */
#define mtlgt2__ext220__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext220 :: AVG GPU Core Frequency */
#define mtlgt2__ext220__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext220 :: AVG GPU Core Frequency */
#define mtlgt2__ext220__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext220 :: RT BVH CACHE MISS XECORE0 */
#define mtlgt2__ext220__rt_bvh_cache_miss_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext220 :: RT BVH CACHE MISS XECORE1 */
#define mtlgt2__ext220__rt_bvh_cache_miss_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext220 :: RT BVH CACHE MISS XECORE2 */
#define mtlgt2__ext220__rt_bvh_cache_miss_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext220 :: RT BVH CACHE MISS XECORE3 */
#define mtlgt2__ext220__rt_bvh_cache_miss_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext225 :: GPU Time Elapsed */
#define mtlgt2__ext225__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext225 :: GPU Core Clocks */
#define mtlgt2__ext225__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext225 :: AVG GPU Core Frequency */
#define mtlgt2__ext225__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext225 :: AVG GPU Core Frequency */
#define mtlgt2__ext225__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext225 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0 */
static uint64_t
mtlgt2__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read(UNUSED struct intel_perf_config *perf,
                                                                       const struct intel_perf_query_info *query,
                                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 1 B 0 READ UMUL 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD 16 B 4 READ UMUL UADD 32 B 5 READ UMUL UADD 64 B 6 READ UMUL UADD 128 B 7 READ UMUL UADD 256 C 1 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = 1 * tmp0;
   uint64_t tmp2 = results->accumulator[query->b_offset + 1];
   uint64_t tmp3 = 2 * tmp2;
   uint64_t tmp4 = tmp1 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 2];
   uint64_t tmp6 = 4 * tmp5;
   uint64_t tmp7 = tmp4 + tmp6;
   uint64_t tmp8 = results->accumulator[query->b_offset + 3];
   uint64_t tmp9 = 8 * tmp8;
   uint64_t tmp10 = tmp7 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 4];
   uint64_t tmp12 = 16 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->b_offset + 5];
   uint64_t tmp15 = 32 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->b_offset + 6];
   uint64_t tmp18 = 64 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = results->accumulator[query->b_offset + 7];
   uint64_t tmp21 = 128 * tmp20;
   uint64_t tmp22 = tmp19 + tmp21;
   uint64_t tmp23 = results->accumulator[query->c_offset + 1];
   uint64_t tmp24 = 256 * tmp23;
   uint64_t tmp25 = tmp22 + tmp24;

   return tmp25;
}

/* Ext227 :: GPU Time Elapsed */
#define mtlgt2__ext227__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext227 :: GPU Core Clocks */
#define mtlgt2__ext227__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext227 :: AVG GPU Core Frequency */
#define mtlgt2__ext227__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext227 :: AVG GPU Core Frequency */
#define mtlgt2__ext227__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext227 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0 */
#define mtlgt2__ext227__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read \
   mtlgt2__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext229 :: GPU Time Elapsed */
#define mtlgt2__ext229__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext229 :: GPU Core Clocks */
#define mtlgt2__ext229__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext229 :: AVG GPU Core Frequency */
#define mtlgt2__ext229__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext229 :: AVG GPU Core Frequency */
#define mtlgt2__ext229__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext229 :: SLM BANK CONFLICT COUNT XECORE0 */
static uint64_t
mtlgt2__ext229__slm_bank_conflict_count_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD C 3 READ UADD 2 C 2 READ UMUL UADD 4 C 1 READ UMUL UADD 8 C 0 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->c_offset + 2];
   uint64_t tmp13 = 2 * tmp12;
   uint64_t tmp14 = tmp11 + tmp13;
   uint64_t tmp15 = results->accumulator[query->c_offset + 1];
   uint64_t tmp16 = 4 * tmp15;
   uint64_t tmp17 = tmp14 + tmp16;
   uint64_t tmp18 = results->accumulator[query->c_offset + 0];
   uint64_t tmp19 = 8 * tmp18;
   uint64_t tmp20 = tmp17 + tmp19;

   return tmp20;
}

/* Ext229 :: SLM BANK CONFLICT COUNT XECORE1 */
static uint64_t
mtlgt2__ext229__slm_bank_conflict_count_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ 2 B 6 READ UMUL UADD 4 B 5 READ UMUL UADD 8 B 4 READ UMUL UADD B 3 READ UADD 2 B 2 READ UMUL UADD 4 B 1 READ UMUL UADD 8 B 0 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 3];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->b_offset + 2];
   uint64_t tmp13 = 2 * tmp12;
   uint64_t tmp14 = tmp11 + tmp13;
   uint64_t tmp15 = results->accumulator[query->b_offset + 1];
   uint64_t tmp16 = 4 * tmp15;
   uint64_t tmp17 = tmp14 + tmp16;
   uint64_t tmp18 = results->accumulator[query->b_offset + 0];
   uint64_t tmp19 = 8 * tmp18;
   uint64_t tmp20 = tmp17 + tmp19;

   return tmp20;
}

/* Ext231 :: GPU Time Elapsed */
#define mtlgt2__ext231__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext231 :: GPU Core Clocks */
#define mtlgt2__ext231__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext231 :: AVG GPU Core Frequency */
#define mtlgt2__ext231__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext231 :: AVG GPU Core Frequency */
#define mtlgt2__ext231__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext231 :: SLM BANK CONFLICT COUNT XECORE2 */
#define mtlgt2__ext231__slm_bank_conflict_count_xecore2__read \
   mtlgt2__ext229__slm_bank_conflict_count_xecore0__read

/* Ext231 :: SLM BANK CONFLICT COUNT XECORE3 */
#define mtlgt2__ext231__slm_bank_conflict_count_xecore3__read \
   mtlgt2__ext229__slm_bank_conflict_count_xecore1__read

/* Ext237 :: GPU Time Elapsed */
#define mtlgt2__ext237__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext237 :: GPU Core Clocks */
#define mtlgt2__ext237__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext237 :: AVG GPU Core Frequency */
#define mtlgt2__ext237__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext237 :: AVG GPU Core Frequency */
#define mtlgt2__ext237__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext237 :: L3 MISS L3BANK0 */
#define mtlgt2__ext237__l3_miss_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext237 :: L3 MISS L3BANK1 */
#define mtlgt2__ext237__l3_miss_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext237 :: L3 MISS L3BANK2 */
#define mtlgt2__ext237__l3_miss_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext237 :: L3 MISS L3BANK3 */
#define mtlgt2__ext237__l3_miss_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext238 :: GPU Time Elapsed */
#define mtlgt2__ext238__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext238 :: GPU Core Clocks */
#define mtlgt2__ext238__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext238 :: AVG GPU Core Frequency */
#define mtlgt2__ext238__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext238 :: AVG GPU Core Frequency */
#define mtlgt2__ext238__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext238 :: AMFS L3 WRITE SLICE0 */
#define mtlgt2__ext238__amfs_l3_write_slice0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE0 */
#define mtlgt2__ext238__xve_dataport_fence_message_count_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE1 */
#define mtlgt2__ext238__xve_dataport_fence_message_count_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE2 */
#define mtlgt2__ext238__xve_dataport_fence_message_count_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext238 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE3 */
#define mtlgt2__ext238__xve_dataport_fence_message_count_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext239 :: GPU Time Elapsed */
#define mtlgt2__ext239__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext239 :: GPU Core Clocks */
#define mtlgt2__ext239__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext239 :: AVG GPU Core Frequency */
#define mtlgt2__ext239__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext239 :: AVG GPU Core Frequency */
#define mtlgt2__ext239__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext239 :: GPU MEMORY L3 READ SQIDI0 */
#define mtlgt2__ext239__gpu_memory_l3_read_sqidi0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext240 :: GPU Time Elapsed */
#define mtlgt2__ext240__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext240 :: GPU Core Clocks */
#define mtlgt2__ext240__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext240 :: AVG GPU Core Frequency */
#define mtlgt2__ext240__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext240 :: AVG GPU Core Frequency */
#define mtlgt2__ext240__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext240 :: GPU MEMORY L3 READ SQIDI1 */
#define mtlgt2__ext240__gpu_memory_l3_read_sqidi1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext500 :: GPU Time Elapsed */
#define mtlgt2__ext500__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext500 :: GPU Core Clocks */
#define mtlgt2__ext500__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext500 :: AVG GPU Core Frequency */
#define mtlgt2__ext500__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext500 :: AVG GPU Core Frequency */
#define mtlgt2__ext500__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext500 :: ICACHE HIT BANK0 XECORE0 */
#define mtlgt2__ext500__icache_hit_bank0_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE0 */
#define mtlgt2__ext500__icache_miss_bank0_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext500 :: ICACHE HIT BANK0 XECORE1 */
#define mtlgt2__ext500__icache_hit_bank0_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE1 */
#define mtlgt2__ext500__icache_miss_bank0_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext500 :: ICACHE HIT BANK0 XECORE2 */
#define mtlgt2__ext500__icache_hit_bank0_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE2 */
#define mtlgt2__ext500__icache_miss_bank0_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext500 :: ICACHE HIT BANK0 XECORE3 */
#define mtlgt2__ext500__icache_hit_bank0_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE3 */
#define mtlgt2__ext500__icache_miss_bank0_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext501 :: GPU Time Elapsed */
#define mtlgt2__ext501__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext501 :: GPU Core Clocks */
#define mtlgt2__ext501__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext501 :: AVG GPU Core Frequency */
#define mtlgt2__ext501__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext501 :: AVG GPU Core Frequency */
#define mtlgt2__ext501__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext501 :: ICACHE HIT BANK1 XECORE0 */
#define mtlgt2__ext501__icache_hit_bank1_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE0 */
#define mtlgt2__ext501__icache_miss_bank1_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext501 :: ICACHE HIT BANK1 XECORE1 */
#define mtlgt2__ext501__icache_hit_bank1_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE1 */
#define mtlgt2__ext501__icache_miss_bank1_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext501 :: ICACHE HIT BANK1 XECORE2 */
#define mtlgt2__ext501__icache_hit_bank1_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE2 */
#define mtlgt2__ext501__icache_miss_bank1_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext501 :: ICACHE HIT BANK1 XECORE3 */
#define mtlgt2__ext501__icache_hit_bank1_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE3 */
#define mtlgt2__ext501__icache_miss_bank1_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext502 :: GPU Time Elapsed */
#define mtlgt2__ext502__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext502 :: GPU Core Clocks */
#define mtlgt2__ext502__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext502 :: AVG GPU Core Frequency */
#define mtlgt2__ext502__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext502 :: AVG GPU Core Frequency */
#define mtlgt2__ext502__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext502 :: ICACHE HIT BANK2 XECORE0 */
#define mtlgt2__ext502__icache_hit_bank2_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE0 */
#define mtlgt2__ext502__icache_miss_bank2_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext502 :: ICACHE HIT BANK2 XECORE1 */
#define mtlgt2__ext502__icache_hit_bank2_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE1 */
#define mtlgt2__ext502__icache_miss_bank2_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext502 :: ICACHE HIT BANK2 XECORE2 */
#define mtlgt2__ext502__icache_hit_bank2_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE2 */
#define mtlgt2__ext502__icache_miss_bank2_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext502 :: ICACHE HIT BANK2 XECORE3 */
#define mtlgt2__ext502__icache_hit_bank2_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE3 */
#define mtlgt2__ext502__icache_miss_bank2_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext503 :: GPU Time Elapsed */
#define mtlgt2__ext503__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext503 :: GPU Core Clocks */
#define mtlgt2__ext503__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext503 :: AVG GPU Core Frequency */
#define mtlgt2__ext503__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext503 :: AVG GPU Core Frequency */
#define mtlgt2__ext503__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext503 :: ICACHE HIT BANK3 XECORE0 */
#define mtlgt2__ext503__icache_hit_bank3_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE0 */
#define mtlgt2__ext503__icache_miss_bank3_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext503 :: ICACHE HIT BANK3 XECORE1 */
#define mtlgt2__ext503__icache_hit_bank3_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE1 */
#define mtlgt2__ext503__icache_miss_bank3_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext503 :: ICACHE HIT BANK3 XECORE2 */
#define mtlgt2__ext503__icache_hit_bank3_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE2 */
#define mtlgt2__ext503__icache_miss_bank3_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext503 :: ICACHE HIT BANK3 XECORE3 */
#define mtlgt2__ext503__icache_hit_bank3_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE3 */
#define mtlgt2__ext503__icache_miss_bank3_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext508 :: GPU Time Elapsed */
#define mtlgt2__ext508__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext508 :: GPU Core Clocks */
#define mtlgt2__ext508__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext508 :: AVG GPU Core Frequency */
#define mtlgt2__ext508__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext508 :: AVG GPU Core Frequency */
#define mtlgt2__ext508__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext508 :: SLM BYTE READ BANK0 XECORE0 */
#define mtlgt2__ext508__slm_byte_read_bank0_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext508 :: SLM BYTE READ BANK0 XECORE1 */
static uint64_t
mtlgt2__ext508__slm_byte_read_bank0_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ 2 B 7 READ UMUL UADD 4 B 6 READ UMUL UADD 8 B 5 READ UMUL UADD 16 B 4 READ UMUL UADD 32 B 3 READ UMUL UADD 64 B 2 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 6];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 5];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 4];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 3];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->b_offset + 2];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;

   return tmp18;
}

/* Ext509 :: GPU Time Elapsed */
#define mtlgt2__ext509__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext509 :: GPU Core Clocks */
#define mtlgt2__ext509__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext509 :: AVG GPU Core Frequency */
#define mtlgt2__ext509__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext509 :: AVG GPU Core Frequency */
#define mtlgt2__ext509__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext509 :: SLM BYTE READ BANK1 XECORE0 */
#define mtlgt2__ext509__slm_byte_read_bank1_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext509 :: SLM BYTE READ BANK1 XECORE1 */
#define mtlgt2__ext509__slm_byte_read_bank1_xecore1__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext510 :: GPU Time Elapsed */
#define mtlgt2__ext510__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext510 :: GPU Core Clocks */
#define mtlgt2__ext510__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext510 :: AVG GPU Core Frequency */
#define mtlgt2__ext510__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext510 :: AVG GPU Core Frequency */
#define mtlgt2__ext510__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext510 :: SLM BYTE READ BANK0 XECORE2 */
#define mtlgt2__ext510__slm_byte_read_bank0_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext510 :: SLM BYTE READ BANK0 XECORE3 */
#define mtlgt2__ext510__slm_byte_read_bank0_xecore3__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext511 :: GPU Time Elapsed */
#define mtlgt2__ext511__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext511 :: GPU Core Clocks */
#define mtlgt2__ext511__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext511 :: AVG GPU Core Frequency */
#define mtlgt2__ext511__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext511 :: AVG GPU Core Frequency */
#define mtlgt2__ext511__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext511 :: SLM BYTE READ BANK1 XECORE2 */
#define mtlgt2__ext511__slm_byte_read_bank1_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext511 :: SLM BYTE READ BANK1 XECORE3 */
#define mtlgt2__ext511__slm_byte_read_bank1_xecore3__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext516 :: GPU Time Elapsed */
#define mtlgt2__ext516__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext516 :: GPU Core Clocks */
#define mtlgt2__ext516__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext516 :: AVG GPU Core Frequency */
#define mtlgt2__ext516__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext516 :: AVG GPU Core Frequency */
#define mtlgt2__ext516__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext516 :: LOAD STORE CACHE BYTE READ BANK0 XECORE0 */
static uint64_t
mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                               const struct intel_perf_query_info *query,
                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD 16 C 3 READ UMUL UADD 32 C 2 READ UMUL UADD 64 C 1 READ UMUL UADD 128 C 0 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 2];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 1];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->c_offset + 0];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;

   return tmp21;
}

/* Ext516 :: LOAD STORE CACHE BYTE READ BANK1 XECORE0 */
static uint64_t
mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                               const struct intel_perf_query_info *query,
                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: B 7 READ 2 B 6 READ UMUL UADD 4 B 5 READ UMUL UADD 8 B 4 READ UMUL UADD 16 B 3 READ UMUL UADD 32 B 2 READ UMUL UADD 64 B 1 READ UMUL UADD 128 B 0 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 3];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 2];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->b_offset + 1];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->b_offset + 0];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;

   return tmp21;
}

/* Ext517 :: GPU Time Elapsed */
#define mtlgt2__ext517__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext517 :: GPU Core Clocks */
#define mtlgt2__ext517__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext517 :: AVG GPU Core Frequency */
#define mtlgt2__ext517__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext517 :: AVG GPU Core Frequency */
#define mtlgt2__ext517__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext517 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE0 */
#define mtlgt2__ext517__load_store_cache_byte_write_bank0_xecore0__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext517 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE0 */
#define mtlgt2__ext517__load_store_cache_byte_write_bank1_xecore0__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext518 :: GPU Time Elapsed */
#define mtlgt2__ext518__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext518 :: GPU Core Clocks */
#define mtlgt2__ext518__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext518 :: AVG GPU Core Frequency */
#define mtlgt2__ext518__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext518 :: AVG GPU Core Frequency */
#define mtlgt2__ext518__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext518 :: LOAD STORE CACHE BYTE READ BANK0 XECORE1 */
#define mtlgt2__ext518__load_store_cache_byte_read_bank0_xecore1__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext518 :: LOAD STORE CACHE BYTE READ BANK1 XECORE1 */
#define mtlgt2__ext518__load_store_cache_byte_read_bank1_xecore1__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext519 :: GPU Time Elapsed */
#define mtlgt2__ext519__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext519 :: GPU Core Clocks */
#define mtlgt2__ext519__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext519 :: AVG GPU Core Frequency */
#define mtlgt2__ext519__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext519 :: AVG GPU Core Frequency */
#define mtlgt2__ext519__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext519 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE1 */
#define mtlgt2__ext519__load_store_cache_byte_write_bank0_xecore1__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext519 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE1 */
#define mtlgt2__ext519__load_store_cache_byte_write_bank1_xecore1__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext520 :: GPU Time Elapsed */
#define mtlgt2__ext520__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext520 :: GPU Core Clocks */
#define mtlgt2__ext520__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext520 :: AVG GPU Core Frequency */
#define mtlgt2__ext520__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext520 :: AVG GPU Core Frequency */
#define mtlgt2__ext520__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext520 :: LOAD STORE CACHE BYTE READ BANK0 XECORE2 */
#define mtlgt2__ext520__load_store_cache_byte_read_bank0_xecore2__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext520 :: LOAD STORE CACHE BYTE READ BANK1 XECORE2 */
#define mtlgt2__ext520__load_store_cache_byte_read_bank1_xecore2__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext521 :: GPU Time Elapsed */
#define mtlgt2__ext521__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext521 :: GPU Core Clocks */
#define mtlgt2__ext521__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext521 :: AVG GPU Core Frequency */
#define mtlgt2__ext521__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext521 :: AVG GPU Core Frequency */
#define mtlgt2__ext521__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext521 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE2 */
#define mtlgt2__ext521__load_store_cache_byte_write_bank0_xecore2__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext521 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE2 */
#define mtlgt2__ext521__load_store_cache_byte_write_bank1_xecore2__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext522 :: GPU Time Elapsed */
#define mtlgt2__ext522__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext522 :: GPU Core Clocks */
#define mtlgt2__ext522__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext522 :: AVG GPU Core Frequency */
#define mtlgt2__ext522__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext522 :: AVG GPU Core Frequency */
#define mtlgt2__ext522__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext522 :: LOAD STORE CACHE BYTE READ BANK0 XECORE3 */
#define mtlgt2__ext522__load_store_cache_byte_read_bank0_xecore3__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext522 :: LOAD STORE CACHE BYTE READ BANK1 XECORE3 */
#define mtlgt2__ext522__load_store_cache_byte_read_bank1_xecore3__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext523 :: GPU Time Elapsed */
#define mtlgt2__ext523__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext523 :: GPU Core Clocks */
#define mtlgt2__ext523__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext523 :: AVG GPU Core Frequency */
#define mtlgt2__ext523__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext523 :: AVG GPU Core Frequency */
#define mtlgt2__ext523__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext523 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE3 */
#define mtlgt2__ext523__load_store_cache_byte_write_bank0_xecore3__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext523 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE3 */
#define mtlgt2__ext523__load_store_cache_byte_write_bank1_xecore3__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext540 :: GPU Time Elapsed */
#define mtlgt2__ext540__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext540 :: GPU Core Clocks */
#define mtlgt2__ext540__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext540 :: AVG GPU Core Frequency */
#define mtlgt2__ext540__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext540 :: AVG GPU Core Frequency */
#define mtlgt2__ext540__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext540 :: SLM BYTE WRITE BANK0 XECORE0 */
#define mtlgt2__ext540__slm_byte_write_bank0_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext540 :: SLM BYTE WRITE BANK1 XECORE0 */
#define mtlgt2__ext540__slm_byte_write_bank1_xecore0__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext541 :: GPU Time Elapsed */
#define mtlgt2__ext541__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext541 :: GPU Core Clocks */
#define mtlgt2__ext541__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext541 :: AVG GPU Core Frequency */
#define mtlgt2__ext541__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext541 :: AVG GPU Core Frequency */
#define mtlgt2__ext541__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext541 :: SLM BYTE WRITE BANK0 XECORE1 */
#define mtlgt2__ext541__slm_byte_write_bank0_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext541 :: SLM BYTE WRITE BANK1 XECORE1 */
#define mtlgt2__ext541__slm_byte_write_bank1_xecore1__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext542 :: GPU Time Elapsed */
#define mtlgt2__ext542__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext542 :: GPU Core Clocks */
#define mtlgt2__ext542__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext542 :: AVG GPU Core Frequency */
#define mtlgt2__ext542__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext542 :: AVG GPU Core Frequency */
#define mtlgt2__ext542__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext542 :: SLM BYTE WRITE BANK0 XECORE2 */
#define mtlgt2__ext542__slm_byte_write_bank0_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext542 :: SLM BYTE WRITE BANK1 XECORE2 */
#define mtlgt2__ext542__slm_byte_write_bank1_xecore2__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext543 :: GPU Time Elapsed */
#define mtlgt2__ext543__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext543 :: GPU Core Clocks */
#define mtlgt2__ext543__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext543 :: AVG GPU Core Frequency */
#define mtlgt2__ext543__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext543 :: AVG GPU Core Frequency */
#define mtlgt2__ext543__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext543 :: SLM BYTE WRITE BANK0 XECORE3 */
#define mtlgt2__ext543__slm_byte_write_bank0_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext543 :: SLM BYTE WRITE BANK1 XECORE3 */
#define mtlgt2__ext543__slm_byte_write_bank1_xecore3__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext604 :: GPU Time Elapsed */
#define mtlgt2__ext604__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext604 :: GPU Core Clocks */
#define mtlgt2__ext604__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext604 :: AVG GPU Core Frequency */
#define mtlgt2__ext604__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext604 :: AVG GPU Core Frequency */
#define mtlgt2__ext604__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE0 */
#define mtlgt2__ext604__threadgroup_dispatch_queue0_active_cycles_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE1 */
#define mtlgt2__ext604__threadgroup_dispatch_queue0_active_cycles_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE2 */
#define mtlgt2__ext604__threadgroup_dispatch_queue0_active_cycles_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE3 */
#define mtlgt2__ext604__threadgroup_dispatch_queue0_active_cycles_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE0 */
#define mtlgt2__ext604__threadgroup_dispatch_queue1_active_cycles_xecore0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE1 */
#define mtlgt2__ext604__threadgroup_dispatch_queue1_active_cycles_xecore1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE2 */
#define mtlgt2__ext604__threadgroup_dispatch_queue1_active_cycles_xecore2__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE3 */
#define mtlgt2__ext604__threadgroup_dispatch_queue1_active_cycles_xecore3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext1000 :: GPU Time Elapsed */
#define mtlgt2__ext1000__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1000 :: GPU Core Clocks */
#define mtlgt2__ext1000__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1000 :: AVG GPU Core Frequency */
#define mtlgt2__ext1000__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1000 :: AVG GPU Core Frequency */
#define mtlgt2__ext1000__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1000 :: XVE ACTIVE */
#define mtlgt2__ext1000__xve_active__read \
   bdw__render_basic__eu_active__read

/* Ext1000 :: XVE STALL */
#define mtlgt2__ext1000__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Ext1000 :: XVE THREADS OCCUPANCY ALL */
#define mtlgt2__ext1000__xve_threads_occupancy_all__read \
   acmgt1__ext1000__xve_threads_occupancy_all__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL */
#define mtlgt2__ext1000__xve_inst_executed_alu0_all__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL */
#define mtlgt2__ext1000__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL */
#define mtlgt2__ext1000__xve_inst_executed_alu1_all__read \
   hsw__render_basic__hs_threads__read

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL */
#define mtlgt2__ext1000__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED XMX ALL */
#define mtlgt2__ext1000__xve_inst_executed_xmx_all__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1000 :: XVE INST EXECUTED XMX ALL */
#define mtlgt2__ext1000__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED SEND ALL */
#define mtlgt2__ext1000__xve_inst_executed_send_all__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1000 :: XVE INST EXECUTED SEND ALL */
#define mtlgt2__ext1000__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL */
#define mtlgt2__ext1000__xve_inst_executed_control_all__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL */
#define mtlgt2__ext1000__xve_inst_executed_control_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE */
#define mtlgt2__ext1000__xve_pipe_alu0_and_alu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE */
#define mtlgt2__ext1000__xve_pipe_alu0_and_xmx_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define mtlgt2__ext1000__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define mtlgt2__ext1000__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1000 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define mtlgt2__ext1000__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1000 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define mtlgt2__ext1000__xve_inst_executed_send_all_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL UTILIZATION */
#define mtlgt2__ext1000__xve_inst_executed_control_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1000 :: XVE ACTIVE CYCLES */
#define mtlgt2__ext1000__xve_active_cycles__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1000 :: XVE ACTIVE CYCLES */
#define mtlgt2__ext1000__xve_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE STALL CYCLES */
#define mtlgt2__ext1000__xve_stall_cycles__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1000 :: XVE STALL CYCLES */
#define mtlgt2__ext1000__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE THREADS OCCUPANCY CYCLES ALL */
#define mtlgt2__ext1000__xve_threads_occupancy_cycles_all__read \
   acmgt1__ext1000__xve_threads_occupancy_cycles_all__read

/* Ext1000 :: XVE THREADS OCCUPANCY CYCLES ALL */
#define mtlgt2__ext1000__xve_threads_occupancy_cycles_all__max \
   acmgt1__ext1000__xve_threads_occupancy_cycles_all__max

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
#define mtlgt2__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
#define mtlgt2__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define mtlgt2__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read \
   hsw__render_basic__ds_threads__read

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define mtlgt2__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: GPU Time Elapsed */
#define mtlgt2__ext1001__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1001 :: GPU Core Clocks */
#define mtlgt2__ext1001__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1001 :: AVG GPU Core Frequency */
#define mtlgt2__ext1001__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1001 :: AVG GPU Core Frequency */
#define mtlgt2__ext1001__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1001 :: XVE INST EXECUTED ALU0 VS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU0 VS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 HS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_hs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU0 HS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 DS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_ds__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 DS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 FS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_ps__read \
   hsw__render_basic__hs_threads__read

/* Ext1001 :: XVE INST EXECUTED ALU0 FS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 CS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_cs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 CS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_async_cs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define mtlgt2__ext1001__xve_inst_executed_alu0_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 VS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_vs__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1001 :: XVE INST EXECUTED ALU1 VS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 HS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_hs__read \
   hsw__render_basic__ds_threads__read

/* Ext1001 :: XVE INST EXECUTED ALU1 HS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 DS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_ds__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1001 :: XVE INST EXECUTED ALU1 DS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 FS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_ps__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU1 FS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 CS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_cs__read \
   acmgt1__ext1001__xve_inst_executed_alu1_cs__read

/* Ext1001 :: XVE INST EXECUTED ALU1 CS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_async_cs__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS */
#define mtlgt2__ext1001__xve_inst_executed_alu1_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 VS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu0_vs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 HS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu0_hs_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1001 :: XVE INST EXECUTED ALU0 DS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu0_ds_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 FS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu0_ps_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 CS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu0_cs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu0_async_cs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 VS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu1_vs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1001 :: XVE INST EXECUTED ALU1 HS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu1_hs_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 DS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu1_ds_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1001 :: XVE INST EXECUTED ALU1 FS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu1_ps_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 CS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu1_cs_utilization__read \
   bdw__render_basic__ps_send_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION */
#define mtlgt2__ext1001__xve_inst_executed_alu1_async_cs_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1002 :: GPU Time Elapsed */
#define mtlgt2__ext1002__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1002 :: GPU Core Clocks */
#define mtlgt2__ext1002__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1002 :: AVG GPU Core Frequency */
#define mtlgt2__ext1002__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1002 :: AVG GPU Core Frequency */
#define mtlgt2__ext1002__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS UTILIZATION */
#define mtlgt2__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS UTILIZATION */
#define mtlgt2__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS UTILIZATION */
#define mtlgt2__ext1002__xve_inst_executed_send_rt_ahs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS UTILIZATION */
#define mtlgt2__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS UTILIZATION */
#define mtlgt2__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS UTILIZATION */
#define mtlgt2__ext1002__xve_inst_executed_send_rt_chs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS UTILIZATION */
#define mtlgt2__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS UTILIZATION */
#define mtlgt2__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1002 :: XVE INST EXECUTED SEND RT MS UTILIZATION */
#define mtlgt2__ext1002__xve_inst_executed_send_rt_ms_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS */
#define mtlgt2__ext1002__xve_inst_executed_alu0_rt_ahs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS */
#define mtlgt2__ext1002__xve_inst_executed_alu0_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS */
#define mtlgt2__ext1002__xve_inst_executed_alu1_rt_ahs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS */
#define mtlgt2__ext1002__xve_inst_executed_alu1_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS */
#define mtlgt2__ext1002__xve_inst_executed_send_rt_ahs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS */
#define mtlgt2__ext1002__xve_inst_executed_send_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS */
#define mtlgt2__ext1002__xve_inst_executed_alu0_rt_chs__read \
   hsw__render_basic__hs_threads__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS */
#define mtlgt2__ext1002__xve_inst_executed_alu0_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS */
#define mtlgt2__ext1002__xve_inst_executed_alu1_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS */
#define mtlgt2__ext1002__xve_inst_executed_alu1_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS */
#define mtlgt2__ext1002__xve_inst_executed_send_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS */
#define mtlgt2__ext1002__xve_inst_executed_send_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS */
#define mtlgt2__ext1002__xve_inst_executed_alu0_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS */
#define mtlgt2__ext1002__xve_inst_executed_alu0_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS */
#define mtlgt2__ext1002__xve_inst_executed_alu1_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS */
#define mtlgt2__ext1002__xve_inst_executed_alu1_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT MS */
#define mtlgt2__ext1002__xve_inst_executed_send_rt_ms__read \
   hsw__render_basic__ds_threads__read

/* Ext1002 :: XVE INST EXECUTED SEND RT MS */
#define mtlgt2__ext1002__xve_inst_executed_send_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: GPU Time Elapsed */
#define mtlgt2__ext1003__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1003 :: GPU Core Clocks */
#define mtlgt2__ext1003__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1003 :: AVG GPU Core Frequency */
#define mtlgt2__ext1003__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1003 :: AVG GPU Core Frequency */
#define mtlgt2__ext1003__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1003 :: XVE ACTIVE */
#define mtlgt2__ext1003__xve_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1003 :: XVE ACTIVE DS */
#define mtlgt2__ext1003__xve_active_ds__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1003 :: XVE ACTIVE HS */
#define mtlgt2__ext1003__xve_active_hs__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1003 :: XVE ACTIVE FS */
#define mtlgt2__ext1003__xve_active_ps__read \
   bdw__render_basic__eu_stall__read

/* Ext1003 :: XVE ACTIVE VS */
#define mtlgt2__ext1003__xve_active_vs__read \
   bdw__render_basic__eu_active__read

/* Ext1003 :: XVE ACTIVE ASYNC CS */
#define mtlgt2__ext1003__xve_active_async_cs__read \
   bdw__render_basic__vs_send_active__read

/* Ext1003 :: XVE ACTIVE CS */
#define mtlgt2__ext1003__xve_active_cs__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1003 :: XVE ACTIVE MS */
#define mtlgt2__ext1003__xve_active_ms__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1003 :: XVE ACTIVE TS */
#define mtlgt2__ext1003__xve_active_ts__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1003 :: XVE ACTIVE RT */
#define mtlgt2__ext1003__xve_active_rt__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1003 :: XVE ACTIVE CYCLES */
#define mtlgt2__ext1003__xve_active_cycles__read \
   hsw__render_basic__ds_threads__read

/* Ext1003 :: XVE ACTIVE CYCLES */
#define mtlgt2__ext1003__xve_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES ASYNC CS */
#define mtlgt2__ext1003__xve_active_cycles_async_cs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1003 :: XVE ACTIVE CYCLES ASYNC CS */
#define mtlgt2__ext1003__xve_active_cycles_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES CS */
#define mtlgt2__ext1003__xve_active_cycles_cs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1003 :: XVE ACTIVE CYCLES CS */
#define mtlgt2__ext1003__xve_active_cycles_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES HS */
#define mtlgt2__ext1003__xve_active_cycles_hs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1003 :: XVE ACTIVE CYCLES FS */
#define mtlgt2__ext1003__xve_active_cycles_ps__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1003 :: XVE ACTIVE CYCLES FS */
#define mtlgt2__ext1003__xve_active_cycles_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES VS */
#define mtlgt2__ext1003__xve_active_cycles_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1003 :: XVE ACTIVE CYCLES VS */
#define mtlgt2__ext1003__xve_active_cycles_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES DS */
#define mtlgt2__ext1003__xve_active_cycles_ds__read \
   hsw__render_basic__hs_threads__read

/* Ext1003 :: XVE ACTIVE CYCLES DS */
#define mtlgt2__ext1003__xve_active_cycles_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES MS */
#define mtlgt2__ext1003__xve_active_cycles_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1003 :: XVE ACTIVE CYCLES MS */
#define mtlgt2__ext1003__xve_active_cycles_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES TS */
#define mtlgt2__ext1003__xve_active_cycles_ts__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1003 :: XVE ACTIVE CYCLES TS */
#define mtlgt2__ext1003__xve_active_cycles_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES RT */
#define mtlgt2__ext1003__xve_active_cycles_rt__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1003 :: XVE ACTIVE CYCLES RT */
#define mtlgt2__ext1003__xve_active_cycles_rt__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: GPU Time Elapsed */
#define mtlgt2__ext1004__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1004 :: GPU Core Clocks */
#define mtlgt2__ext1004__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1004 :: AVG GPU Core Frequency */
#define mtlgt2__ext1004__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1004 :: AVG GPU Core Frequency */
#define mtlgt2__ext1004__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1004 :: XVE STALL */
#define mtlgt2__ext1004__xve_stall__read \
   bdw__render_basic__eu_active__read

/* Ext1004 :: XVE STALL ASYNC CS */
#define mtlgt2__ext1004__xve_stall_async_cs__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1004 :: XVE STALL CS */
#define mtlgt2__ext1004__xve_stall_cs__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1004 :: XVE STALL DS */
#define mtlgt2__ext1004__xve_stall_ds__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1004 :: XVE STALL HS */
#define mtlgt2__ext1004__xve_stall_hs__read \
   bdw__render_basic__vs_send_active__read

/* Ext1004 :: XVE STALL MS */
#define mtlgt2__ext1004__xve_stall_ms__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1004 :: XVE STALL FS */
#define mtlgt2__ext1004__xve_stall_ps__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1004 :: XVE STALL TS */
#define mtlgt2__ext1004__xve_stall_ts__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1004 :: XVE STALL VS */
#define mtlgt2__ext1004__xve_stall_vs__read \
   bdw__render_basic__eu_stall__read

/* Ext1004 :: XVE STALL RT */
#define mtlgt2__ext1004__xve_stall_rt__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1004 :: XVE STALL CYCLES */
#define mtlgt2__ext1004__xve_stall_cycles__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1004 :: XVE STALL CYCLES */
#define mtlgt2__ext1004__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES ASYNC CS */
#define mtlgt2__ext1004__xve_stall_cycles_async_cs__read \
   hsw__render_basic__ds_threads__read

/* Ext1004 :: XVE STALL CYCLES ASYNC CS */
#define mtlgt2__ext1004__xve_stall_cycles_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES CS */
#define mtlgt2__ext1004__xve_stall_cycles_cs__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1004 :: XVE STALL CYCLES CS */
#define mtlgt2__ext1004__xve_stall_cycles_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES DS */
#define mtlgt2__ext1004__xve_stall_cycles_ds__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1004 :: XVE STALL CYCLES DS */
#define mtlgt2__ext1004__xve_stall_cycles_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES HS */
#define mtlgt2__ext1004__xve_stall_cycles_hs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1004 :: XVE STALL CYCLES HS */
#define mtlgt2__ext1004__xve_stall_cycles_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES MS */
#define mtlgt2__ext1004__xve_stall_cycles_ms__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1004 :: XVE STALL CYCLES MS */
#define mtlgt2__ext1004__xve_stall_cycles_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES FS */
#define mtlgt2__ext1004__xve_stall_cycles_ps__read \
   hsw__render_basic__hs_threads__read

/* Ext1004 :: XVE STALL CYCLES FS */
#define mtlgt2__ext1004__xve_stall_cycles_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES TS */
#define mtlgt2__ext1004__xve_stall_cycles_ts__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1004 :: XVE STALL CYCLES TS */
#define mtlgt2__ext1004__xve_stall_cycles_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES VS */
#define mtlgt2__ext1004__xve_stall_cycles_vs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1004 :: XVE STALL CYCLES VS */
#define mtlgt2__ext1004__xve_stall_cycles_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES RT */
#define mtlgt2__ext1004__xve_stall_cycles_rt__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1004 :: XVE STALL CYCLES RT */
#define mtlgt2__ext1004__xve_stall_cycles_rt__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: GPU Time Elapsed */
#define mtlgt2__ext1005__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1005 :: GPU Core Clocks */
#define mtlgt2__ext1005__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1005 :: AVG GPU Core Frequency */
#define mtlgt2__ext1005__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1005 :: AVG GPU Core Frequency */
#define mtlgt2__ext1005__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL */
#define mtlgt2__ext1005__xve_inst_executed_alu0_all__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL */
#define mtlgt2__ext1005__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP16 */
#define mtlgt2__ext1005__xve_inst_executed_fp16__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1005 :: XVE INST EXECUTED FP16 */
#define mtlgt2__ext1005__xve_inst_executed_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP32 */
#define mtlgt2__ext1005__xve_inst_executed_fp32__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1005 :: XVE INST EXECUTED FP32 */
#define mtlgt2__ext1005__xve_inst_executed_fp32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP64 */
#define mtlgt2__ext1005__xve_inst_executed_fp64__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1005 :: XVE INST EXECUTED FP64 */
#define mtlgt2__ext1005__xve_inst_executed_fp64__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL */
#define mtlgt2__ext1005__xve_inst_executed_alu1_all__read \
   acmgt1__ext1001__xve_inst_executed_alu1_cs__read

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL */
#define mtlgt2__ext1005__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED INT16 */
#define mtlgt2__ext1005__xve_inst_executed_int16__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1005 :: XVE INST EXECUTED INT16 */
#define mtlgt2__ext1005__xve_inst_executed_int16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED INT32 */
#define mtlgt2__ext1005__xve_inst_executed_int32__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1005 :: XVE INST EXECUTED INT32 */
#define mtlgt2__ext1005__xve_inst_executed_int32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED MATH */
#define mtlgt2__ext1005__xve_inst_executed_math__read \
   hsw__render_basic__hs_threads__read

/* Ext1005 :: XVE INST EXECUTED MATH */
#define mtlgt2__ext1005__xve_inst_executed_math__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX ALL */
#define mtlgt2__ext1005__xve_inst_executed_xmx_all__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1005 :: XVE INST EXECUTED XMX ALL */
#define mtlgt2__ext1005__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX BF16 */
#define mtlgt2__ext1005__xve_inst_executed_xmx_bf16__read \
   hsw__render_basic__ds_threads__read

/* Ext1005 :: XVE INST EXECUTED XMX BF16 */
#define mtlgt2__ext1005__xve_inst_executed_xmx_bf16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX FP16 */
#define mtlgt2__ext1005__xve_inst_executed_xmx_fp16__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1005 :: XVE INST EXECUTED XMX FP16 */
#define mtlgt2__ext1005__xve_inst_executed_xmx_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX INT8 */
#define mtlgt2__ext1005__xve_inst_executed_xmx_int8__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1005 :: XVE INST EXECUTED XMX INT8 */
#define mtlgt2__ext1005__xve_inst_executed_xmx_int8__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1005 :: XVE INST EXECUTED FP16 UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_fp16_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1005 :: XVE INST EXECUTED FP32 UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_fp32_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1005 :: XVE INST EXECUTED FP64 UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_fp64_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__ps_send_active__read

/* Ext1005 :: XVE INST EXECUTED INT16 UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_int16_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1005 :: XVE INST EXECUTED INT32 UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_int32_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1005 :: XVE INST EXECUTED MATH UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_math_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1005 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1005 :: XVE INST EXECUTED XMX BF16 UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_xmx_bf16_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1005 :: XVE INST EXECUTED XMX FP16 UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_xmx_fp16_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1005 :: XVE INST EXECUTED XMX INT8 UTILIZATION */
#define mtlgt2__ext1005__xve_inst_executed_xmx_int8_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1006 :: GPU Time Elapsed */
#define mtlgt2__ext1006__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1006 :: GPU Core Clocks */
#define mtlgt2__ext1006__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1006 :: AVG GPU Core Frequency */
#define mtlgt2__ext1006__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1006 :: AVG GPU Core Frequency */
#define mtlgt2__ext1006__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1006 :: XVE INST EXECUTED SEND ALL */
#define mtlgt2__ext1006__xve_inst_executed_send_all__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND ALL */
#define mtlgt2__ext1006__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS */
#define mtlgt2__ext1006__xve_inst_executed_send_async_cs__read \
   hsw__render_basic__ds_threads__read

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS */
#define mtlgt2__ext1006__xve_inst_executed_send_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND CS */
#define mtlgt2__ext1006__xve_inst_executed_send_cs__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1006 :: XVE INST EXECUTED SEND CS */
#define mtlgt2__ext1006__xve_inst_executed_send_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND DS */
#define mtlgt2__ext1006__xve_inst_executed_send_ds__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1006 :: XVE INST EXECUTED SEND DS */
#define mtlgt2__ext1006__xve_inst_executed_send_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND GS */
#define mtlgt2__ext1006__xve_inst_executed_send_gs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1006 :: XVE INST EXECUTED SEND GS */
#define mtlgt2__ext1006__xve_inst_executed_send_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND HS */
#define mtlgt2__ext1006__xve_inst_executed_send_hs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1006 :: XVE INST EXECUTED SEND HS */
#define mtlgt2__ext1006__xve_inst_executed_send_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND MS */
#define mtlgt2__ext1006__xve_inst_executed_send_ms__read \
   hsw__render_basic__hs_threads__read

/* Ext1006 :: XVE INST EXECUTED SEND MS */
#define mtlgt2__ext1006__xve_inst_executed_send_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND FS */
#define mtlgt2__ext1006__xve_inst_executed_send_ps__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1006 :: XVE INST EXECUTED SEND FS */
#define mtlgt2__ext1006__xve_inst_executed_send_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND TS */
#define mtlgt2__ext1006__xve_inst_executed_send_ts__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND TS */
#define mtlgt2__ext1006__xve_inst_executed_send_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND VS */
#define mtlgt2__ext1006__xve_inst_executed_send_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND VS */
#define mtlgt2__ext1006__xve_inst_executed_send_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_all_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_async_cs_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1006 :: XVE INST EXECUTED SEND CS UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_cs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1006 :: XVE INST EXECUTED SEND DS UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_ds_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1006 :: XVE INST EXECUTED SEND GS UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_gs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1006 :: XVE INST EXECUTED SEND HS UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_hs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1006 :: XVE INST EXECUTED SEND MS UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_ms_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1006 :: XVE INST EXECUTED SEND FS UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_ps_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1006 :: XVE INST EXECUTED SEND TS UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_ts_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1006 :: XVE INST EXECUTED SEND VS UTILIZATION */
#define mtlgt2__ext1006__xve_inst_executed_send_vs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1007 :: GPU Time Elapsed */
#define mtlgt2__ext1007__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1007 :: GPU Core Clocks */
#define mtlgt2__ext1007__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1007 :: AVG GPU Core Frequency */
#define mtlgt2__ext1007__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1007 :: AVG GPU Core Frequency */
#define mtlgt2__ext1007__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1007 :: XVE ACTIVE GS */
#define mtlgt2__ext1007__xve_active_gs__read \
   bdw__render_basic__eu_active__read

/* Ext1007 :: XVE STALL GS */
#define mtlgt2__ext1007__xve_stall_gs__read \
   bdw__render_basic__eu_stall__read

/* Ext1007 :: XVE INST EXECUTED ALU0 GS */
#define mtlgt2__ext1007__xve_inst_executed_alu0_gs__read \
   hsw__render_basic__hs_threads__read

/* Ext1007 :: XVE INST EXECUTED ALU0 GS */
#define mtlgt2__ext1007__xve_inst_executed_alu0_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 GS */
#define mtlgt2__ext1007__xve_inst_executed_alu1_gs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 GS */
#define mtlgt2__ext1007__xve_inst_executed_alu1_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE ACTIVE CYCLES GS */
#define mtlgt2__ext1007__xve_active_cycles_gs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1007 :: XVE ACTIVE CYCLES GS */
#define mtlgt2__ext1007__xve_active_cycles_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE STALL CYCLES GS */
#define mtlgt2__ext1007__xve_stall_cycles_gs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1007 :: XVE STALL CYCLES GS */
#define mtlgt2__ext1007__xve_stall_cycles_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 MS */
#define mtlgt2__ext1007__xve_inst_executed_alu0_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1007 :: XVE INST EXECUTED ALU0 MS */
#define mtlgt2__ext1007__xve_inst_executed_alu0_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 TS */
#define mtlgt2__ext1007__xve_inst_executed_alu0_ts__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1007 :: XVE INST EXECUTED ALU0 TS */
#define mtlgt2__ext1007__xve_inst_executed_alu0_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 MS */
#define mtlgt2__ext1007__xve_inst_executed_alu1_ms__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 MS */
#define mtlgt2__ext1007__xve_inst_executed_alu1_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 TS */
#define mtlgt2__ext1007__xve_inst_executed_alu1_ts__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 TS */
#define mtlgt2__ext1007__xve_inst_executed_alu1_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 GS UTILIZATION */
#define mtlgt2__ext1007__xve_inst_executed_alu0_gs_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1007 :: XVE INST EXECUTED ALU1 GS UTILIZATION */
#define mtlgt2__ext1007__xve_inst_executed_alu1_gs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1007 :: XVE INST EXECUTED ALU0 MS UTILIZATION */
#define mtlgt2__ext1007__xve_inst_executed_alu0_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1007 :: XVE INST EXECUTED ALU0 TS UTILIZATION */
#define mtlgt2__ext1007__xve_inst_executed_alu0_ts_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1007 :: XVE INST EXECUTED ALU1 MS UTILIZATION */
#define mtlgt2__ext1007__xve_inst_executed_alu1_ms_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1007 :: XVE INST EXECUTED ALU1 TS UTILIZATION */
#define mtlgt2__ext1007__xve_inst_executed_alu1_ts_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1010 :: GPU Time Elapsed */
#define mtlgt2__ext1010__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1010 :: GPU Core Clocks */
#define mtlgt2__ext1010__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1010 :: AVG GPU Core Frequency */
#define mtlgt2__ext1010__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1010 :: AVG GPU Core Frequency */
#define mtlgt2__ext1010__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1010 :: SAMPLER 2X2 READ */
#define mtlgt2__ext1010__sampler_2_x2_read__read \
   bdw__render_basic__sampler_texels__read

/* Ext1010 :: PIXEL WRITE */
#define mtlgt2__ext1010__pixel_write__read \
   bdw__render_basic__samples_written__read

/* Ext1010 :: PIXEL BLEND */
#define mtlgt2__ext1010__pixel_blend__read \
   bdw__render_basic__samples_blended__read

/* Ext1010 :: RASTERIZER SAMPLE OUTPUT */
#define mtlgt2__ext1010__rasterizer_sample_output__read \
   bdw__render_basic__rasterized_pixels__read

/* Ext1010 :: POSTPS DEPTH STENCIL ALPHA TEST FAIL */
#define mtlgt2__ext1010__postps_depth_stencil_alpha_test_fail__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic :: GPU Time Elapsed */
#define mtlgt3__render_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics Basic :: GPU Core Clocks */
#define mtlgt3__render_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics Basic :: AVG GPU Core Frequency */
#define mtlgt3__render_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics Basic :: AVG GPU Core Frequency */
#define mtlgt3__render_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics Basic :: VS Threads Dispatched */
#define mtlgt3__render_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Render Metrics Basic :: HS Threads Dispatched */
#define mtlgt3__render_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Render Metrics Basic :: DS Threads Dispatched */
#define mtlgt3__render_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Render Metrics Basic :: GS Threads Dispatched */
#define mtlgt3__render_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Render Metrics Basic :: FS Threads Dispatched */
#define mtlgt3__render_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Render Metrics Basic :: CS Threads Dispatched */
#define mtlgt3__render_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Render Metrics Basic :: GPU Busy */
#define mtlgt3__render_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics Basic :: XVE Active */
#define mtlgt3__render_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Render Metrics Basic :: XVE Stall */
#define mtlgt3__render_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Render Metrics Basic :: XVE Thread Occupancy */
#define mtlgt3__render_basic__xve_thread_occupancy__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* Render Metrics Basic :: EM And FPU Pipes Active */
#define mtlgt3__render_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Render Metrics Basic :: VS FPU Pipe Active */
#define mtlgt3__render_basic__vs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Render Metrics Basic :: VS EM Pipe Active */
#define mtlgt3__render_basic__vs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Render Metrics Basic :: VS Send Pipe Active */
#define mtlgt3__render_basic__vs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Render Metrics Basic :: FS FPU Pipe Active */
#define mtlgt3__render_basic__ps_fpu_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Render Metrics Basic :: FS EM Pipe Active */
#define mtlgt3__render_basic__ps_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Render Metrics Basic :: FS Send Pipe Active */
#define mtlgt3__render_basic__ps_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Render Metrics Basic :: Rasterized Pixels */
#define mtlgt3__render_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Render Metrics Basic :: Early Hi-Depth Test Fails */
#define mtlgt3__render_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Render Metrics Basic :: Early Depth Test Fails */
#define mtlgt3__render_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic :: Samples Killed in FS */
#define mtlgt3__render_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Render Metrics Basic :: Pixels Failing Tests */
#define mtlgt3__render_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Render Metrics Basic :: Samples Written */
#define mtlgt3__render_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Render Metrics Basic :: Samples Blended */
#define mtlgt3__render_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Render Metrics Basic :: Sampler Texels */
#define mtlgt3__render_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Render Metrics Basic :: Sampler Texels Misses */
#define mtlgt3__render_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Render Metrics Basic :: SLM Bytes Read */
#define mtlgt3__render_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Render Metrics Basic :: SLM Bytes Read */
#define mtlgt3__render_basic__slm_reads__max \
   acmgt1__render_basic__slm_reads__max

/* Render Metrics Basic :: SLM Writes */
#define mtlgt3__render_basic__slm_writes__read \
   acmgt1__render_basic__slm_writes__read

/* Render Metrics Basic :: SLM Writes */
#define mtlgt3__render_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Render Metrics Basic :: Shader Memory Accesses */
#define mtlgt3__render_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Render Metrics Basic :: Shader Atomic Memory Accesses */
#define mtlgt3__render_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Render Metrics Basic :: Shader Barrier Messages */
#define mtlgt3__render_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Render Metrics Basic :: GTI Read Throughput */
#define mtlgt3__render_basic__gti_read_throughput__read \
   mtlgt2__render_basic__gti_read_throughput__read

/* Render Metrics Basic :: GTI Read Throughput */
#define mtlgt3__render_basic__gti_read_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Render Metrics Basic :: GTI Write Throughput */
#define mtlgt3__render_basic__gti_write_throughput__read \
   mtlgt2__render_basic__gti_write_throughput__read

/* Render Metrics Basic :: GTI Write Throughput */
#define mtlgt3__render_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Render Metrics Basic :: Samplers Busy */
#define mtlgt3__render_basic__samplers_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics Basic :: Samplers Bottleneck */
#define mtlgt3__render_basic__sampler_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Compute Metrics Basic :: GPU Time Elapsed */
#define mtlgt3__compute_basic__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Compute Metrics Basic :: GPU Core Clocks */
#define mtlgt3__compute_basic__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define mtlgt3__compute_basic__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Compute Metrics Basic :: AVG GPU Core Frequency */
#define mtlgt3__compute_basic__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Compute Metrics Basic :: GPU Busy */
#define mtlgt3__compute_basic__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Compute Metrics Basic :: VS Threads Dispatched */
#define mtlgt3__compute_basic__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* Compute Metrics Basic :: HS Threads Dispatched */
#define mtlgt3__compute_basic__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* Compute Metrics Basic :: DS Threads Dispatched */
#define mtlgt3__compute_basic__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* Compute Metrics Basic :: GS Threads Dispatched */
#define mtlgt3__compute_basic__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* Compute Metrics Basic :: FS Threads Dispatched */
#define mtlgt3__compute_basic__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* Compute Metrics Basic :: CS Threads Dispatched */
#define mtlgt3__compute_basic__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* Compute Metrics Basic :: XVE Active */
#define mtlgt3__compute_basic__xve_active__read \
   bdw__render_basic__eu_active__read

/* Compute Metrics Basic :: XVE Stall */
#define mtlgt3__compute_basic__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Compute Metrics Basic :: XVE FPU Pipe Active */
#define mtlgt3__compute_basic__fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Compute Metrics Basic :: EM Pipe Active */
#define mtlgt3__compute_basic__em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* Compute Metrics Basic :: XMX Pipe Active */
#define mtlgt3__compute_basic__xmx_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* Compute Metrics Basic :: EM And FPU Pipes Active */
#define mtlgt3__compute_basic__xve_fpu_em_active__read \
   bdw__render_basic__vs_send_active__read

/* Compute Metrics Basic :: XMX And FPU Pipes Active */
#define mtlgt3__compute_basic__xve_fpu_xmx_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Compute Metrics Basic :: XVE AVG IPC Rate */
#define mtlgt3__compute_basic__xve_avg_ipc_rate__read \
   acmgt1__compute_basic__xve_avg_ipc_rate__read

/* Compute Metrics Basic :: XVE AVG IPC Rate */
#define mtlgt3__compute_basic__xve_avg_ipc_rate__max \
   bdw__compute_basic__eu_avg_ipc_rate__max

/* Compute Metrics Basic :: Send Pipe Active */
#define mtlgt3__compute_basic__send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Compute Metrics Basic :: XVE Thread Occupancy */
#define mtlgt3__compute_basic__xve_thread_occupancy__read \
   acmgt1__compute_basic__xve_thread_occupancy__read

/* Compute Metrics Basic :: FPU FLT16 Instruction */
#define mtlgt3__compute_basic__xve_fpu_flt16__read \
   bdw__render_basic__ps_fpu1_active__read

/* Compute Metrics Basic :: FPU FLT32 Instruction */
#define mtlgt3__compute_basic__xve_fpu_flt32__read \
   bdw__render_basic__ps_send_active__read

/* Compute Metrics Basic :: FPU FLT64 Instruction */
#define mtlgt3__compute_basic__xve_fpu_flt64__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Compute Metrics Basic :: Rasterized Pixels */
#define mtlgt3__compute_basic__rasterized_pixels__read \
   bdw__render_basic__rasterized_pixels__read

/* Compute Metrics Basic :: Early Hi-Depth Test Fails */
#define mtlgt3__compute_basic__hi_depth_test_fails__read \
   bdw__render_basic__hi_depth_test_fails__read

/* Compute Metrics Basic :: Early Depth Test Fails */
#define mtlgt3__compute_basic__early_depth_test_fails__read \
   bdw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic :: Samples Killed in FS */
#define mtlgt3__compute_basic__samples_killed_in_ps__read \
   bdw__render_basic__samples_killed_in_ps__read

/* Compute Metrics Basic :: Pixels Failing Tests */
#define mtlgt3__compute_basic__pixels_failing_post_ps_tests__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

/* Compute Metrics Basic :: Samples Written */
#define mtlgt3__compute_basic__samples_written__read \
   bdw__render_basic__samples_written__read

/* Compute Metrics Basic :: Samples Blended */
#define mtlgt3__compute_basic__samples_blended__read \
   bdw__render_basic__samples_blended__read

/* Compute Metrics Basic :: Sampler Texels */
#define mtlgt3__compute_basic__sampler_texels__read \
   bdw__render_basic__sampler_texels__read

/* Compute Metrics Basic :: Sampler Texels Misses */
#define mtlgt3__compute_basic__sampler_texel_misses__read \
   bdw__render_basic__sampler_texel_misses__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define mtlgt3__compute_basic__slm_reads__read \
   hsw__render_basic__ps_threads__read

/* Compute Metrics Basic :: SLM Bytes Read */
#define mtlgt3__compute_basic__slm_reads__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: SLM Writes */
#define mtlgt3__compute_basic__slm_writes__read \
   acmgt1__render_basic__slm_writes__read

/* Compute Metrics Basic :: SLM Writes */
#define mtlgt3__compute_basic__slm_writes__max \
   acmgt1__render_basic__slm_reads__max

/* Compute Metrics Basic :: Shader Memory Accesses */
#define mtlgt3__compute_basic__shader_memory_accesses__read \
   bdw__render_basic__shader_memory_accesses__read

/* Compute Metrics Basic :: Shader Atomic Memory Accesses */
#define mtlgt3__compute_basic__shader_atomics__read \
   bdw__render_basic__shader_atomics__read

/* Compute Metrics Basic :: Shader Barrier Messages */
#define mtlgt3__compute_basic__shader_barriers__read \
   hsw__render_basic__early_depth_test_fails__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define mtlgt3__compute_basic__gti_read_throughput__read \
   mtlgt2__render_basic__gti_read_throughput__read

/* Compute Metrics Basic :: GTI Read Throughput */
#define mtlgt3__compute_basic__gti_read_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* Compute Metrics Basic :: GTI Write Throughput */
#define mtlgt3__compute_basic__gti_write_throughput__read \
   mtlgt2__render_basic__gti_write_throughput__read

/* Compute Metrics Basic :: GTI Write Throughput */
#define mtlgt3__compute_basic__gti_write_throughput__max \
   acmgt1__render_basic__gti_read_throughput__max

/* AsyncCompute :: GPU Time Elapsed */
#define mtlgt3__async_compute__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* AsyncCompute :: GPU Core Clocks */
#define mtlgt3__async_compute__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define mtlgt3__async_compute__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* AsyncCompute :: AVG GPU Core Frequency */
#define mtlgt3__async_compute__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* AsyncCompute :: GPU Busy */
#define mtlgt3__async_compute__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* AsyncCompute :: VS Threads Dispatched */
#define mtlgt3__async_compute__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* AsyncCompute :: HS Threads Dispatched */
#define mtlgt3__async_compute__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* AsyncCompute :: DS Threads Dispatched */
#define mtlgt3__async_compute__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* AsyncCompute :: GS Threads Dispatched */
#define mtlgt3__async_compute__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* AsyncCompute :: FS Threads Dispatched */
#define mtlgt3__async_compute__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* AsyncCompute :: CS Threads Dispatched */
#define mtlgt3__async_compute__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* AsyncCompute :: XVE FPU Pipe Active */
#define mtlgt3__async_compute__fpu_active__read \
   bdw__render_basic__eu_active__read

/* AsyncCompute :: VS FPU Pipe Active */
#define mtlgt3__async_compute__vs_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* AsyncCompute :: FS FPU Pipe Active */
#define mtlgt3__async_compute__ps_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* AsyncCompute :: CS FPU Pipe Active */
#define mtlgt3__async_compute__cs_fpu_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* AsyncCompute :: ASYNC CS FPU Pipe Active */
#define mtlgt3__async_compute__async_cs_fpu_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* AsyncCompute :: EM Pipe Active */
#define mtlgt3__async_compute__em_active__read \
   bdw__render_basic__vs_send_active__read

/* AsyncCompute :: VS EM Pipe Active */
#define mtlgt3__async_compute__vs_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* AsyncCompute :: FS EM Pipe Active */
#define mtlgt3__async_compute__ps_em_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* AsyncCompute :: CS EM Pipe Active */
#define mtlgt3__async_compute__cs_em_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* AsyncCompute :: ASYNC CS EM Pipe Active */
#define mtlgt3__async_compute__async_cs_em_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* AsyncCompute :: XVE Thread Occupancy */
#define mtlgt3__async_compute__xve_thread_occupancy__read \
   acmgt1__async_compute__xve_thread_occupancy__read

/* AsyncCompute :: XVE Active */
#define mtlgt3__async_compute__xve_active__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* AsyncCompute :: XVE Stall */
#define mtlgt3__async_compute__xve_stall__read \
   bdw__compute_l3_cache__eu_move_fpu0_instruction__read

/* XveActivity :: GPU Time Elapsed */
#define mtlgt3__xve_activity__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* XveActivity :: GPU Core Clocks */
#define mtlgt3__xve_activity__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* XveActivity :: AVG GPU Core Frequency */
#define mtlgt3__xve_activity__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* XveActivity :: AVG GPU Core Frequency */
#define mtlgt3__xve_activity__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* XveActivity :: GPU Busy */
#define mtlgt3__xve_activity__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* XveActivity :: VS Threads Dispatched */
#define mtlgt3__xve_activity__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* XveActivity :: HS Threads Dispatched */
#define mtlgt3__xve_activity__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* XveActivity :: DS Threads Dispatched */
#define mtlgt3__xve_activity__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* XveActivity :: GS Threads Dispatched */
#define mtlgt3__xve_activity__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* XveActivity :: FS Threads Dispatched */
#define mtlgt3__xve_activity__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* XveActivity :: CS Threads Dispatched */
#define mtlgt3__xve_activity__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* XveActivity :: HS FPU Pipe Active */
#define mtlgt3__xve_activity__hs_fpu_active__read \
   bdw__render_basic__eu_active__read

/* XveActivity :: DS FPU Pipe Active */
#define mtlgt3__xve_activity__ds_fpu_active__read \
   bdw__render_basic__eu_stall__read

/* XveActivity :: GS FPU Pipe Active */
#define mtlgt3__xve_activity__gs_fpu_active__read \
   bdw__render_basic__eu_fpu_both_active__read

/* XveActivity :: HS EM Pipe Active */
#define mtlgt3__xve_activity__hs_em_active__read \
   bdw__render_basic__vs_fpu0_active__read

/* XveActivity :: DS EM Pipe Active */
#define mtlgt3__xve_activity__ds_em_active__read \
   bdw__render_basic__vs_fpu1_active__read

/* XveActivity :: GS EM Pipe Active */
#define mtlgt3__xve_activity__gs_em_active__read \
   bdw__render_basic__vs_send_active__read

/* XveActivity :: HS Send Pipe Active */
#define mtlgt3__xve_activity__hs_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* XveActivity :: DS Send Pipe Active */
#define mtlgt3__xve_activity__ds_send_active__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* XveActivity :: GS Send Pipe Active */
#define mtlgt3__xve_activity__gs_send_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* XveActivity :: CS Send Pipe Active */
#define mtlgt3__xve_activity__cs_send_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* GpuBusyness :: GPU Time Elapsed */
#define mtlgt3__gpu_busyness__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* GpuBusyness :: GPU Core Clocks */
#define mtlgt3__gpu_busyness__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define mtlgt3__gpu_busyness__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* GpuBusyness :: AVG GPU Core Frequency */
#define mtlgt3__gpu_busyness__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* GpuBusyness :: GPU Busy */
#define mtlgt3__gpu_busyness__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* GpuBusyness :: XVE Active */
#define mtlgt3__gpu_busyness__xve_active__read \
   bdw__render_basic__eu_active__read

/* GpuBusyness :: XVE Stall */
#define mtlgt3__gpu_busyness__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* GpuBusyness :: XVE Thread Occupancy */
#define mtlgt3__gpu_busyness__xve_thread_occupancy__read \
   acmgt1__render_basic__xve_thread_occupancy__read

/* GpuBusyness :: VS Threads Dispatched */
#define mtlgt3__gpu_busyness__vs_threads__read \
   bdw__render_basic__vs_threads__read

/* GpuBusyness :: HS Threads Dispatched */
#define mtlgt3__gpu_busyness__hs_threads__read \
   bdw__render_basic__hs_threads__read

/* GpuBusyness :: DS Threads Dispatched */
#define mtlgt3__gpu_busyness__ds_threads__read \
   bdw__render_basic__ds_threads__read

/* GpuBusyness :: GS Threads Dispatched */
#define mtlgt3__gpu_busyness__gs_threads__read \
   hsw__render_basic__vs_threads__read

/* GpuBusyness :: FS Threads Dispatched */
#define mtlgt3__gpu_busyness__ps_threads__read \
   bdw__render_basic__ps_threads__read

/* GpuBusyness :: CS Threads Dispatched */
#define mtlgt3__gpu_busyness__cs_threads__read \
   bdw__render_basic__cs_threads__read

/* GpuBusyness :: Render Ring Busy */
#define mtlgt3__gpu_busyness__render_busy__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* GpuBusyness :: ComputeEngine0 Ring Busy */
#define mtlgt3__gpu_busyness__compute_engine0_busy__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* GpuBusyness :: Blitter Ring Busy */
#define mtlgt3__gpu_busyness__blitter_busy__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set HDCAndSF1 :: GPU Time Elapsed */
#define mtlgt3__hdc_and_sf1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF1 :: GPU Core Clocks */
#define mtlgt3__hdc_and_sf1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF1 :: AVG GPU Core Frequency */
#define mtlgt3__hdc_and_sf1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF1 :: AVG GPU Core Frequency */
#define mtlgt3__hdc_and_sf1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF1 :: GPU Busy */
#define mtlgt3__hdc_and_sf1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF1 :: Slice0 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define mtlgt3__hdc_and_sf1__non_sampler_shader00_access_stalled_on_l3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set HDCAndSF1 :: Slice0 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define mtlgt3__hdc_and_sf1__non_sampler_shader01_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF1 :: Slice0 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define mtlgt3__hdc_and_sf1__non_sampler_shader02_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF1 :: Slice0 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define mtlgt3__hdc_and_sf1__non_sampler_shader03_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF1 :: Polygon (Slice0) Data Ready */
#define mtlgt3__hdc_and_sf1__poly0_data_ready__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF2 :: GPU Time Elapsed */
#define mtlgt3__hdc_and_sf2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set HDCAndSF2 :: GPU Core Clocks */
#define mtlgt3__hdc_and_sf2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set HDCAndSF2 :: AVG GPU Core Frequency */
#define mtlgt3__hdc_and_sf2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set HDCAndSF2 :: AVG GPU Core Frequency */
#define mtlgt3__hdc_and_sf2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set HDCAndSF2 :: GPU Busy */
#define mtlgt3__hdc_and_sf2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set HDCAndSF2 :: Slice1 Xe Core0 Non-sampler Shader Access Stalled On L3 */
#define mtlgt3__hdc_and_sf2__non_sampler_shader10_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set HDCAndSF2 :: Slice1 Xe Core1 Non-sampler Shader Access Stalled On L3 */
#define mtlgt3__hdc_and_sf2__non_sampler_shader11_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set HDCAndSF2 :: Slice1 Xe Core2 Non-sampler Shader Access Stalled On L3 */
#define mtlgt3__hdc_and_sf2__non_sampler_shader12_access_stalled_on_l3__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set HDCAndSF2 :: Slice1 Xe Core3 Non-sampler Shader Access Stalled On L3 */
#define mtlgt3__hdc_and_sf2__non_sampler_shader13_access_stalled_on_l3__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set HDCAndSF2 :: Polygon (Slice1) Data Ready */
#define mtlgt3__hdc_and_sf2__poly1_data_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3 :: GPU Time Elapsed */
#define mtlgt3__l3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* L3 :: GPU Core Clocks */
#define mtlgt3__l3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* L3 :: AVG GPU Core Frequency */
#define mtlgt3__l3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* L3 :: AVG GPU Core Frequency */
#define mtlgt3__l3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* L3 :: GPU Busy */
#define mtlgt3__l3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* L3 :: L3 INPUT AVAILABLE L3BANK0 */
#define mtlgt3__l3__l3_input_available_l3_bank0__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* L3 :: L3 INPUT AVAILABLE L3BANK1 */
#define mtlgt3__l3__l3_input_available_l3_bank1__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* L3 :: L3 INPUT AVAILABLE L3BANK2 */
#define mtlgt3__l3__l3_input_available_l3_bank2__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* L3 :: L3 INPUT AVAILABLE L3BANK3 */
#define mtlgt3__l3__l3_input_available_l3_bank3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* L3 :: L3 INPUT AVAILABLE L3BANK4 */
#define mtlgt3__l3__l3_input_available_l3_bank4__read \
   bdw__render_pipe_profile__so_stall__read

/* L3 :: L3 INPUT AVAILABLE L3BANK5 */
#define mtlgt3__l3__l3_input_available_l3_bank5__read \
   bdw__render_pipe_profile__ds_stall__read

/* L3 :: L3 INPUT AVAILABLE L3BANK6 */
#define mtlgt3__l3__l3_input_available_l3_bank6__read \
   bdw__render_pipe_profile__hs_stall__read

/* L3 :: L3 INPUT AVAILABLE L3BANK7 */
#define mtlgt3__l3__l3_input_available_l3_bank7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* L3 :: L3 OUTPUT READY L3BANK0 */
#define mtlgt3__l3__l3_output_ready_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* L3 :: L3 OUTPUT READY L3BANK1 */
#define mtlgt3__l3__l3_output_ready_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* L3 :: L3 OUTPUT READY L3BANK2 */
#define mtlgt3__l3__l3_output_ready_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* L3 :: L3 OUTPUT READY L3BANK3 */
#define mtlgt3__l3__l3_output_ready_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* L3 :: L3 OUTPUT READY L3BANK4 */
#define mtlgt3__l3__l3_output_ready_l3_bank4__read \
   bdw__render_pipe_profile__cl_stall__read

/* L3 :: L3 OUTPUT READY L3BANK5 */
#define mtlgt3__l3__l3_output_ready_l3_bank5__read \
   bdw__render_pipe_profile__sf_stall__read

/* L3 :: L3 OUTPUT READY L3BANK6 */
#define mtlgt3__l3__l3_output_ready_l3_bank6__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* L3 :: L3 OUTPUT READY L3BANK7 */
#define mtlgt3__l3__l3_output_ready_l3_bank7__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Time Elapsed */
#define mtlgt3__rasterizer_and_pixel_backend1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend1 :: GPU Core Clocks */
#define mtlgt3__rasterizer_and_pixel_backend1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define mtlgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend1 :: AVG GPU Core Frequency */
#define mtlgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend1 :: GPU Busy */
#define mtlgt3__rasterizer_and_pixel_backend1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice1 Pipe0 Post-EarlyZ Pixel Data Ready */
#define mtlgt3__rasterizer_and_pixel_backend1__pixel_data10_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice1 Pipe1 Post-EarlyZ Pixel Data Ready */
#define mtlgt3__rasterizer_and_pixel_backend1__pixel_data11_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */
#define mtlgt3__rasterizer_and_pixel_backend1__pixel_data00_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice0 Pipe1 Post-EarlyZ Pixel Data Ready */
#define mtlgt3__rasterizer_and_pixel_backend1__pixel_data01_ready__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Metric set RasterizerAndPixelBackend1 :: Slice1 Rasterizer Input Available */
#define mtlgt3__rasterizer_and_pixel_backend1__rasterizer1_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Metric set RasterizerAndPixelBackend1 :: Slice0 Rasterizer Input Available */
#define mtlgt3__rasterizer_and_pixel_backend1__rasterizer0_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Time Elapsed */
#define mtlgt3__rasterizer_and_pixel_backend2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set RasterizerAndPixelBackend2 :: GPU Core Clocks */
#define mtlgt3__rasterizer_and_pixel_backend2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define mtlgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set RasterizerAndPixelBackend2 :: AVG GPU Core Frequency */
#define mtlgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set RasterizerAndPixelBackend2 :: GPU Busy */
#define mtlgt3__rasterizer_and_pixel_backend2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Metric set RasterizerAndPixelBackend2 :: PS00 Output Available */
#define mtlgt3__rasterizer_and_pixel_backend2__ps_output00_available__read \
   bdw__render_pipe_profile__so_stall__read

/* Metric set RasterizerAndPixelBackend2 :: Pixel Values 00 Ready */
#define mtlgt3__rasterizer_and_pixel_backend2__pixel_values00_ready__read \
   bdw__render_pipe_profile__ds_stall__read

/* Metric set RasterizerAndPixelBackend2 :: PS01 Output Available */
#define mtlgt3__rasterizer_and_pixel_backend2__ps_output01_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Metric set RasterizerAndPixelBackend2 :: Pixel Values 01 Ready */
#define mtlgt3__rasterizer_and_pixel_backend2__pixel_values01_ready__read \
   bdw__render_pipe_profile__cl_stall__read

/* Metric set RasterizerAndPixelBackend2 :: Slice0 Rasterizer Output Ready */
#define mtlgt3__rasterizer_and_pixel_backend2__rasterizer0_output_ready__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Metric set RasterizerAndPixelBackend2 :: Slice1 Rasterizer Output Ready */
#define mtlgt3__rasterizer_and_pixel_backend2__rasterizer1_output_ready__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define mtlgt3__render_pipe_profile1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define mtlgt3__render_pipe_profile1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define mtlgt3__render_pipe_profile1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define mtlgt3__render_pipe_profile1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define mtlgt3__render_pipe_profile1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF0 Bottleneck */
#define mtlgt3__render_pipe_profile1__vf0_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS0 Bottleneck */
#define mtlgt3__render_pipe_profile1__vs0_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: Clipper0 Bottleneck */
#define mtlgt3__render_pipe_profile1__cl0_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS0 Bottleneck */
#define mtlgt3__render_pipe_profile1__hs0_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS0 Bottleneck */
#define mtlgt3__render_pipe_profile1__ds0_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS0 Bottleneck */
#define mtlgt3__render_pipe_profile1__gs0_bottleneck__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF0 Bottleneck */
#define mtlgt3__render_pipe_profile1__sf0_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO0 Bottleneck */
#define mtlgt3__render_pipe_profile1__so0_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: CL0 Stall */
#define mtlgt3__render_pipe_profile1__cl0_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS0 Stall */
#define mtlgt3__render_pipe_profile1__hs0_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS0 Stall */
#define mtlgt3__render_pipe_profile1__ds0_stall__read \
   bdw__render_basic__sampler0_busy__read

/* Render Metrics for 3D Pipeline Profile :: SF0 Stall */
#define mtlgt3__render_pipe_profile1__sf0_stall__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics for 3D Pipeline Profile :: SO0 Stall */
#define mtlgt3__render_pipe_profile1__so0_stall__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth00 Bottleneck */
#define mtlgt3__render_pipe_profile1__hi_depth00_bottleneck__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth01 Bottleneck */
#define mtlgt3__render_pipe_profile1__hi_depth01_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: BC00 Bottleneck */
#define mtlgt3__render_pipe_profile1__bc00_bottleneck__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */
#define mtlgt3__render_pipe_profile2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */
#define mtlgt3__render_pipe_profile2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define mtlgt3__render_pipe_profile2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */
#define mtlgt3__render_pipe_profile2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Render Metrics for 3D Pipeline Profile :: GPU Busy */
#define mtlgt3__render_pipe_profile2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Render Metrics for 3D Pipeline Profile :: VF1 Bottleneck */
#define mtlgt3__render_pipe_profile2__vf1_bottleneck__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: VS1 Bottleneck */
#define mtlgt3__render_pipe_profile2__vs1_bottleneck__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Clipper1 Bottleneck */
#define mtlgt3__render_pipe_profile2__cl1_bottleneck__read \
   bdw__render_pipe_profile__sf_stall__read

/* Render Metrics for 3D Pipeline Profile :: HS1 Bottleneck */
#define mtlgt3__render_pipe_profile2__hs1_bottleneck__read \
   bdw__render_pipe_profile__cl_stall__read

/* Render Metrics for 3D Pipeline Profile :: DS1 Bottleneck */
#define mtlgt3__render_pipe_profile2__ds1_bottleneck__read \
   bdw__render_pipe_profile__so_stall__read

/* Render Metrics for 3D Pipeline Profile :: GS1 Bottleneck */
#define mtlgt3__render_pipe_profile2__gs1_bottleneck__read \
   bdw__render_pipe_profile__ds_stall__read

/* Render Metrics for 3D Pipeline Profile :: SF1 Bottleneck */
#define mtlgt3__render_pipe_profile2__sf1_bottleneck__read \
   bdw__render_pipe_profile__hs_stall__read

/* Render Metrics for 3D Pipeline Profile :: SO1 Bottleneck */
#define mtlgt3__render_pipe_profile2__so1_bottleneck__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: CL1 Stall */
#define mtlgt3__render_pipe_profile2__cl1_stall__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: HS1 Stall */
#define mtlgt3__render_pipe_profile2__hs1_stall__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: DS1 Stall */
#define mtlgt3__render_pipe_profile2__ds1_stall__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SF1 Stall */
#define mtlgt3__render_pipe_profile2__sf1_stall__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: SO1 Stall */
#define mtlgt3__render_pipe_profile2__so1_stall__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth10 Bottleneck */
#define mtlgt3__render_pipe_profile2__hi_depth10_bottleneck__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Render Metrics for 3D Pipeline Profile :: Hi-Depth11 Bottleneck */
#define mtlgt3__render_pipe_profile2__hi_depth11_bottleneck__read \
   bdw__render_basic__sampler1_busy__read

/* Render Metrics for 3D Pipeline Profile :: BC10 Bottleneck */
#define mtlgt3__render_pipe_profile2__bc10_bottleneck__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_Slice0 :: GPU Time Elapsed */
#define mtlgt3__sampler__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Sampler_Slice0 :: GPU Core Clocks */
#define mtlgt3__sampler__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Sampler_Slice0 :: AVG GPU Core Frequency */
#define mtlgt3__sampler__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Sampler_Slice0 :: AVG GPU Core Frequency */
#define mtlgt3__sampler__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Sampler_Slice0 :: GPU Busy */
#define mtlgt3__sampler__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* Sampler_Slice0 :: Slice0 Xe Core0 Input Available */
#define mtlgt3__sampler__sampler00_input_available__read \
   bdw__render_basic__sampler0_busy__read

/* Sampler_Slice0 :: Slice0 Xe Core1 Input Available */
#define mtlgt3__sampler__sampler01_input_available__read \
   bdw__render_basic__sampler1_busy__read

/* Sampler_Slice0 :: Slice0 Xe Core2 Input Available */
#define mtlgt3__sampler__sampler02_input_available__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Sampler_Slice0 :: Slice0 Xe Core3 Input Available */
#define mtlgt3__sampler__sampler03_input_available__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Sampler_Slice0 :: Slice0 Xe Core0 Sampler Output Ready */
#define mtlgt3__sampler__sampler00_output_ready__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Sampler_Slice0 :: Slice0 Xe Core1 Sampler Output Ready */
#define mtlgt3__sampler__sampler01_output_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Sampler_Slice0 :: Slice0 Xe Core2 Sampler Output Ready */
#define mtlgt3__sampler__sampler02_output_ready__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Sampler_Slice0 :: Slice0 Xe Core3 Sampler Output Ready */
#define mtlgt3__sampler__sampler03_output_ready__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Sampler_Slice0 :: Slice1 Xe Core0 Input Available */
#define mtlgt3__sampler__sampler10_input_available__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Sampler_Slice0 :: Slice1 Xe Core1 Input Available */
#define mtlgt3__sampler__sampler11_input_available__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Sampler_Slice0 :: Slice1 Xe Core2 Input Available */
#define mtlgt3__sampler__sampler12_input_available__read \
   bdw__render_pipe_profile__sf_stall__read

/* Sampler_Slice0 :: Slice1 Xe Core3 Input Available */
#define mtlgt3__sampler__sampler13_input_available__read \
   bdw__render_pipe_profile__cl_stall__read

/* Sampler_Slice0 :: Slice1 Xe Core0 Sampler Output Ready */
#define mtlgt3__sampler__sampler10_output_ready__read \
   bdw__render_pipe_profile__so_stall__read

/* Sampler_Slice0 :: Slice1 Xe Core1 Sampler Output Ready */
#define mtlgt3__sampler__sampler11_output_ready__read \
   bdw__render_pipe_profile__ds_stall__read

/* Sampler_Slice0 :: Slice1 Xe Core2 Sampler Output Ready */
#define mtlgt3__sampler__sampler12_output_ready__read \
   bdw__render_pipe_profile__hs_stall__read

/* Sampler_Slice0 :: Slice1 Xe Core3 Sampler Output Ready */
#define mtlgt3__sampler__sampler13_output_ready__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL1 :: GPU Time Elapsed */
#define mtlgt3__tdl1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL1 :: GPU Core Clocks */
#define mtlgt3__tdl1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL1 :: AVG GPU Core Frequency */
#define mtlgt3__tdl1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL1 :: AVG GPU Core Frequency */
#define mtlgt3__tdl1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL1 :: GPU Busy */
#define mtlgt3__tdl1__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher */
#define mtlgt3__tdl1__non_ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL1 :: PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher */
#define mtlgt3__tdl1__ps_thread00_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher */
#define mtlgt3__tdl1__thread_header00_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 0 */
#define mtlgt3__tdl1__thread_header00_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 1 */
#define mtlgt3__tdl1__thread_header00_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 2 */
#define mtlgt3__tdl1__thread_header00_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 3 */
#define mtlgt3__tdl1__thread_header00_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL1 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher */
#define mtlgt3__tdl1__non_ps_thread01_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL1 :: PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher */
#define mtlgt3__tdl1__ps_thread01_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher */
#define mtlgt3__tdl1__thread_header01_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 0 */
#define mtlgt3__tdl1__thread_header01_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 1 */
#define mtlgt3__tdl1__thread_header01_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 2 */
#define mtlgt3__tdl1__thread_header01_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL1 :: Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 3 */
#define mtlgt3__tdl1__thread_header01_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL2 :: GPU Time Elapsed */
#define mtlgt3__tdl2__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL2 :: GPU Core Clocks */
#define mtlgt3__tdl2__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL2 :: AVG GPU Core Frequency */
#define mtlgt3__tdl2__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL2 :: AVG GPU Core Frequency */
#define mtlgt3__tdl2__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL2 :: GPU Busy */
#define mtlgt3__tdl2__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL2 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher */
#define mtlgt3__tdl2__non_ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher */
#define mtlgt3__tdl2__ps_thread02_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher */
#define mtlgt3__tdl2__thread_header02_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 0 */
#define mtlgt3__tdl2__thread_header02_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 1 */
#define mtlgt3__tdl2__thread_header02_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 2 */
#define mtlgt3__tdl2__thread_header02_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 3 */
#define mtlgt3__tdl2__thread_header02_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL2 :: Non-PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher */
#define mtlgt3__tdl2__non_ps_thread03_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL2 :: PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher */
#define mtlgt3__tdl2__ps_thread03_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher */
#define mtlgt3__tdl2__thread_header03_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 0 */
#define mtlgt3__tdl2__thread_header03_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 1 */
#define mtlgt3__tdl2__thread_header03_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 2 */
#define mtlgt3__tdl2__thread_header03_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL2 :: Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 3 */
#define mtlgt3__tdl2__thread_header03_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL3 :: GPU Time Elapsed */
#define mtlgt3__tdl3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL3 :: GPU Core Clocks */
#define mtlgt3__tdl3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL3 :: AVG GPU Core Frequency */
#define mtlgt3__tdl3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL3 :: AVG GPU Core Frequency */
#define mtlgt3__tdl3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL3 :: GPU Busy */
#define mtlgt3__tdl3__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL3 :: Non-PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher */
#define mtlgt3__tdl3__non_ps_thread10_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL3 :: PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher */
#define mtlgt3__tdl3__ps_thread10_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher */
#define mtlgt3__tdl3__thread_header10_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 0 */
#define mtlgt3__tdl3__thread_header10_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 1 */
#define mtlgt3__tdl3__thread_header10_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 2 */
#define mtlgt3__tdl3__thread_header10_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 3 */
#define mtlgt3__tdl3__thread_header10_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL3 :: Non-PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher */
#define mtlgt3__tdl3__non_ps_thread11_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL3 :: PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher */
#define mtlgt3__tdl3__ps_thread11_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher */
#define mtlgt3__tdl3__thread_header11_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 0 */
#define mtlgt3__tdl3__thread_header11_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 1 */
#define mtlgt3__tdl3__thread_header11_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 2 */
#define mtlgt3__tdl3__thread_header11_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL3 :: Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 3 */
#define mtlgt3__tdl3__thread_header11_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* TDL4 :: GPU Time Elapsed */
#define mtlgt3__tdl4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* TDL4 :: GPU Core Clocks */
#define mtlgt3__tdl4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* TDL4 :: AVG GPU Core Frequency */
#define mtlgt3__tdl4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* TDL4 :: AVG GPU Core Frequency */
#define mtlgt3__tdl4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* TDL4 :: GPU Busy */
#define mtlgt3__tdl4__gpu_busy__read \
   bdw__render_basic__gpu_busy__read

/* TDL4 :: Non-PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher */
#define mtlgt3__tdl4__non_ps_thread12_ready_for_dispatch__read \
   bdw__render_basic__sampler0_busy__read

/* TDL4 :: PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher */
#define mtlgt3__tdl4__ps_thread12_ready_for_dispatch__read \
   bdw__render_basic__sampler1_busy__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher */
#define mtlgt3__tdl4__thread_header12_ready__read \
   bdw__render_basic__sampler0_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 0 */
#define mtlgt3__tdl4__thread_header12_ready_port0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 1 */
#define mtlgt3__tdl4__thread_header12_ready_port1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 2 */
#define mtlgt3__tdl4__thread_header12_ready_port2__read \
   bdw__render_pipe_profile__sf_stall__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 3 */
#define mtlgt3__tdl4__thread_header12_ready_port3__read \
   bdw__render_pipe_profile__cl_stall__read

/* TDL4 :: Non-PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher */
#define mtlgt3__tdl4__non_ps_thread13_ready_for_dispatch__read \
   bdw__render_basic__sampler1_bottleneck__read

/* TDL4 :: PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher */
#define mtlgt3__tdl4__ps_thread13_ready_for_dispatch__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher */
#define mtlgt3__tdl4__thread_header13_ready__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 0 */
#define mtlgt3__tdl4__thread_header13_ready_port0__read \
   bdw__render_pipe_profile__so_stall__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 1 */
#define mtlgt3__tdl4__thread_header13_ready_port1__read \
   bdw__render_pipe_profile__ds_stall__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 2 */
#define mtlgt3__tdl4__thread_header13_ready_port2__read \
   bdw__render_pipe_profile__hs_stall__read

/* TDL4 :: Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 3 */
#define mtlgt3__tdl4__thread_header13_ready_port3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Metric set TestOa :: GPU Time Elapsed */
#define mtlgt3__test_oa__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Metric set TestOa :: GPU Core Clocks */
#define mtlgt3__test_oa__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define mtlgt3__test_oa__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Metric set TestOa :: AVG GPU Core Frequency */
#define mtlgt3__test_oa__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Metric set TestOa :: TestCounter0 */
#define mtlgt3__test_oa__counter0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Metric set TestOa :: TestCounter1 */
#define mtlgt3__test_oa__counter1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Metric set TestOa :: TestCounter2 */
#define mtlgt3__test_oa__counter2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Metric set TestOa :: TestCounter3 */
#define mtlgt3__test_oa__counter3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Metric set TestOa :: TestCounter4 */
#define mtlgt3__test_oa__counter4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Metric set TestOa :: TestCounter5 */
#define mtlgt3__test_oa__counter5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Metric set TestOa :: TestCounter6 */
#define mtlgt3__test_oa__counter6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Metric set TestOa :: TestCounter7 */
#define mtlgt3__test_oa__counter7__read \
   hsw__compute_extended__gpu_clocks__read

/* Metric set TestOa :: TestCounter8 */
#define mtlgt3__test_oa__counter8__read \
   hsw__compute_extended__typed_writes0__read

/* Metric set TestOa :: TestCounter9 - OAR enable */
#define mtlgt3__test_oa__counter9__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext1 :: GPU Time Elapsed */
#define mtlgt3__ext1__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1 :: GPU Core Clocks */
#define mtlgt3__ext1__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1 :: AVG GPU Core Frequency */
#define mtlgt3__ext1__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1 :: AVG GPU Core Frequency */
#define mtlgt3__ext1__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1 :: GPU MEMORY BYTE WRITE SQIDI0 */
#define mtlgt3__ext1__gpu_memory_byte_write_sqidi0__read \
   acmgt1__ext1__gpu_memory_byte_write_sqidi0__read

/* Ext1 :: GPU MEMORY BYTE WRITE SQIDI1 */
#define mtlgt3__ext1__gpu_memory_byte_write_sqidi1__read \
   hsw__render_basic__gti_read_throughput__read

/* Ext1 :: GPU MEMORY WRITE SQIDI0 */
#define mtlgt3__ext1__gpu_memory_write_sqidi0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext1 :: GPU MEMORY WRITE SQIDI1 */
#define mtlgt3__ext1__gpu_memory_write_sqidi1__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext1 :: GPU MEMORY WRITE */
#define mtlgt3__ext1__gpu_memory_write__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI0 */
#define mtlgt3__ext1__gpu_memory_read_sqidi0__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ SQIDI1 */
#define mtlgt3__ext1__gpu_memory_read_sqidi1__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext1 :: GPU MEMORY READ */
#define mtlgt3__ext1__gpu_memory_read__read \
   mtlgt2__ext1__gpu_memory_read__read

/* Ext1 :: GPU MEMORY BYTE READ SQIDI0 */
#define mtlgt3__ext1__gpu_memory_byte_read_sqidi0__read \
   acmgt3__ext2__gpu_memory_byte_write_sqidi0__read

/* Ext1 :: GPU MEMORY BYTE READ SQIDI1 */
#define mtlgt3__ext1__gpu_memory_byte_read_sqidi1__read \
   acmgt3__ext2__gpu_memory_byte_write_sqidi1__read

/* Ext1 :: GPU MEMORY ACTIVE SQIDI0 */
#define mtlgt3__ext1__gpu_memory_active_sqidi0__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext1 :: GPU MEMORY ACTIVE SQIDI1 */
#define mtlgt3__ext1__gpu_memory_active_sqidi1__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext1 :: GPU MEMORY BYTE READ BW SQIDI0 */
#define mtlgt3__ext1__gpu_memory_byte_read_bw_sqidi0__read \
   acmgt3__ext2__gpu_memory_byte_write_bw_sqidi0__read

/* Ext1 :: GPU MEMORY BYTE READ BW SQIDI1 */
#define mtlgt3__ext1__gpu_memory_byte_read_bw_sqidi1__read \
   acmgt3__ext2__gpu_memory_byte_write_bw_sqidi1__read

/* Ext1 :: GPU MEMORY BYTE WRITE BW SQIDI0 */
#define mtlgt3__ext1__gpu_memory_byte_write_bw_sqidi0__read \
   acmgt1__ext1__gpu_memory_byte_write_bw_sqidi0__read

/* Ext1 :: GPU MEMORY BYTE WRITE BW SQIDI1 */
#define mtlgt3__ext1__gpu_memory_byte_write_bw_sqidi1__read \
   acmgt1__ext1__gpu_memory_byte_write_bw_sqidi1__read

/* Ext1 :: GPU MEMORY REQUEST QUEUE FULL SQIDI0 */
#define mtlgt3__ext1__gpu_memory_request_queue_full_sqidi0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext1 :: GPU MEMORY REQUEST QUEUE FULL SQIDI1 */
#define mtlgt3__ext1__gpu_memory_request_queue_full_sqidi1__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext3 :: GPU Time Elapsed */
#define mtlgt3__ext3__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext3 :: GPU Core Clocks */
#define mtlgt3__ext3__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext3 :: AVG GPU Core Frequency */
#define mtlgt3__ext3__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext3 :: AVG GPU Core Frequency */
#define mtlgt3__ext3__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI0 */
#define mtlgt3__ext3__gpu_memory_32_b_transaction_read_sqidi0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ SQIDI1 */
#define mtlgt3__ext3__gpu_memory_32_b_transaction_read_sqidi1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext3 :: GPU MEMORY 64B TRANSACTION READ SQIDI0 */
#define mtlgt3__ext3__gpu_memory_64_b_transaction_read_sqidi0__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext3 :: GPU MEMORY 64B TRANSACTION READ SQIDI1 */
#define mtlgt3__ext3__gpu_memory_64_b_transaction_read_sqidi1__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI0 */
#define mtlgt3__ext3__gpu_memory_32_b_transaction_write_sqidi0__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION WRITE SQIDI1 */
#define mtlgt3__ext3__gpu_memory_32_b_transaction_write_sqidi1__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext3 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI0 */
#define mtlgt3__ext3__gpu_memory_64_b_transaction_write_sqidi0__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext3 :: GPU MEMORY 64B TRANSACTION WRITE SQIDI1 */
#define mtlgt3__ext3__gpu_memory_64_b_transaction_write_sqidi1__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext3 :: GPU MEMORY 32B TRANSACTION READ */
static uint64_t
mtlgt3__ext3__gpu_memory_32_b_transaction_read__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ  C 1 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext3 :: GPU MEMORY 64B TRANSACTION READ */
static uint64_t
mtlgt3__ext3__gpu_memory_64_b_transaction_read__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 2 READ  C 3 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 2];
   uint64_t tmp1 = results->accumulator[query->c_offset + 3];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext3 :: GPU MEMORY 32B TRANSACTION WRITE */
#define mtlgt3__ext3__gpu_memory_32_b_transaction_write__read \
   bdw__compute_l3_cache__l3_misses__read

/* Ext3 :: GPU MEMORY 64B TRANSACTION WRITE */
static uint64_t
mtlgt3__ext3__gpu_memory_64_b_transaction_write__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ  C 7 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   uint64_t tmp2 = tmp0 + tmp1;

   return tmp2;
}

/* Ext4 :: GPU Time Elapsed */
#define mtlgt3__ext4__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext4 :: GPU Core Clocks */
#define mtlgt3__ext4__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext4 :: AVG GPU Core Frequency */
#define mtlgt3__ext4__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext4 :: AVG GPU Core Frequency */
#define mtlgt3__ext4__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext4 :: L3 READ L3BANK0 */
#define mtlgt3__ext4__l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext4 :: L3 READ L3BANK1 */
#define mtlgt3__ext4__l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext4 :: L3 READ L3BANK2 */
#define mtlgt3__ext4__l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext4 :: L3 READ L3BANK3 */
#define mtlgt3__ext4__l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext4 :: L3 READ L3BANK4 */
#define mtlgt3__ext4__l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext4 :: L3 READ L3BANK5 */
#define mtlgt3__ext4__l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext4 :: L3 READ L3BANK6 */
#define mtlgt3__ext4__l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext4 :: L3 READ L3BANK7 */
#define mtlgt3__ext4__l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext4 :: L3 WRITE L3BANK0 */
#define mtlgt3__ext4__l3_write_l3_bank0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext4 :: L3 WRITE L3BANK1 */
#define mtlgt3__ext4__l3_write_l3_bank1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext4 :: L3 WRITE L3BANK2 */
#define mtlgt3__ext4__l3_write_l3_bank2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext4 :: L3 WRITE L3BANK3 */
#define mtlgt3__ext4__l3_write_l3_bank3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext4 :: L3 WRITE L3BANK4 */
#define mtlgt3__ext4__l3_write_l3_bank4__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext4 :: L3 WRITE L3BANK5 */
#define mtlgt3__ext4__l3_write_l3_bank5__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext4 :: L3 WRITE L3BANK6 */
#define mtlgt3__ext4__l3_write_l3_bank6__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext4 :: L3 WRITE L3BANK7 */
#define mtlgt3__ext4__l3_write_l3_bank7__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext5 :: GPU Time Elapsed */
#define mtlgt3__ext5__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext5 :: GPU Core Clocks */
#define mtlgt3__ext5__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext5 :: AVG GPU Core Frequency */
#define mtlgt3__ext5__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext5 :: AVG GPU Core Frequency */
#define mtlgt3__ext5__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext5 :: DATAPORT L3 READ L3BANK0 */
#define mtlgt3__ext5__dataport_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext5 :: DATAPORT L3 READ L3BANK1 */
#define mtlgt3__ext5__dataport_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext5 :: DATAPORT L3 READ L3BANK2 */
#define mtlgt3__ext5__dataport_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext5 :: DATAPORT L3 READ L3BANK3 */
#define mtlgt3__ext5__dataport_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext5 :: DATAPORT L3 READ L3BANK4 */
#define mtlgt3__ext5__dataport_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext5 :: DATAPORT L3 READ L3BANK5 */
#define mtlgt3__ext5__dataport_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext5 :: DATAPORT L3 READ L3BANK6 */
#define mtlgt3__ext5__dataport_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext5 :: DATAPORT L3 READ L3BANK7 */
#define mtlgt3__ext5__dataport_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK0 */
#define mtlgt3__ext5__dataport_l3_write_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK1 */
#define mtlgt3__ext5__dataport_l3_write_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK2 */
#define mtlgt3__ext5__dataport_l3_write_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK3 */
#define mtlgt3__ext5__dataport_l3_write_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK4 */
#define mtlgt3__ext5__dataport_l3_write_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK5 */
#define mtlgt3__ext5__dataport_l3_write_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK6 */
#define mtlgt3__ext5__dataport_l3_write_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext5 :: DATAPORT L3 WRITE L3BANK7 */
#define mtlgt3__ext5__dataport_l3_write_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext6 :: GPU Time Elapsed */
#define mtlgt3__ext6__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext6 :: GPU Core Clocks */
#define mtlgt3__ext6__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext6 :: AVG GPU Core Frequency */
#define mtlgt3__ext6__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext6 :: AVG GPU Core Frequency */
#define mtlgt3__ext6__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext6 :: L3 HIT L3BANK0 */
#define mtlgt3__ext6__l3_hit_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext6 :: L3 HIT L3BANK1 */
#define mtlgt3__ext6__l3_hit_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext6 :: L3 HIT L3BANK2 */
#define mtlgt3__ext6__l3_hit_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext6 :: L3 HIT L3BANK3 */
#define mtlgt3__ext6__l3_hit_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext6 :: L3 HIT L3BANK4 */
#define mtlgt3__ext6__l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext6 :: L3 HIT L3BANK5 */
#define mtlgt3__ext6__l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext6 :: L3 HIT L3BANK6 */
#define mtlgt3__ext6__l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext6 :: L3 HIT L3BANK7 */
#define mtlgt3__ext6__l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext6 :: SAMPLER BUSY XECORE0 */
#define mtlgt3__ext6__sampler_busy_xecore0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext6 :: SAMPLER BUSY XECORE1 */
#define mtlgt3__ext6__sampler_busy_xecore1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext6 :: SAMPLER BUSY XECORE2 */
#define mtlgt3__ext6__sampler_busy_xecore2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext6 :: SAMPLER BUSY XECORE3 */
#define mtlgt3__ext6__sampler_busy_xecore3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext6 :: SAMPLER BUSY XECORE4 */
#define mtlgt3__ext6__sampler_busy_xecore4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext6 :: SAMPLER BUSY XECORE5 */
#define mtlgt3__ext6__sampler_busy_xecore5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext6 :: SAMPLER BUSY XECORE6 */
#define mtlgt3__ext6__sampler_busy_xecore6__read \
   bdw__render_basic__sampler1_busy__read

/* Ext6 :: SAMPLER BUSY XECORE7 */
#define mtlgt3__ext6__sampler_busy_xecore7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext7 :: GPU Time Elapsed */
#define mtlgt3__ext7__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext7 :: GPU Core Clocks */
#define mtlgt3__ext7__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext7 :: AVG GPU Core Frequency */
#define mtlgt3__ext7__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext7 :: AVG GPU Core Frequency */
#define mtlgt3__ext7__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext7 :: SAMPLER L3 READ L3BANK0 */
#define mtlgt3__ext7__sampler_l3_read_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext7 :: SAMPLER L3 READ L3BANK1 */
#define mtlgt3__ext7__sampler_l3_read_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext7 :: SAMPLER L3 READ L3BANK2 */
#define mtlgt3__ext7__sampler_l3_read_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext7 :: SAMPLER L3 READ L3BANK3 */
#define mtlgt3__ext7__sampler_l3_read_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext7 :: SAMPLER L3 READ L3BANK4 */
#define mtlgt3__ext7__sampler_l3_read_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext7 :: SAMPLER L3 READ L3BANK5 */
#define mtlgt3__ext7__sampler_l3_read_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext7 :: SAMPLER L3 READ L3BANK6 */
#define mtlgt3__ext7__sampler_l3_read_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext7 :: SAMPLER L3 READ L3BANK7 */
#define mtlgt3__ext7__sampler_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK0 */
#define mtlgt3__ext7__sampler_l3_hit_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext7 :: SAMPLER L3 HIT L3BANK1 */
#define mtlgt3__ext7__sampler_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK2 */
#define mtlgt3__ext7__sampler_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK3 */
#define mtlgt3__ext7__sampler_l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK4 */
#define mtlgt3__ext7__sampler_l3_hit_l3_bank4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK5 */
#define mtlgt3__ext7__sampler_l3_hit_l3_bank5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK6 */
#define mtlgt3__ext7__sampler_l3_hit_l3_bank6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext7 :: SAMPLER L3 HIT L3BANK7 */
#define mtlgt3__ext7__sampler_l3_hit_l3_bank7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext8 :: GPU Time Elapsed */
#define mtlgt3__ext8__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext8 :: GPU Core Clocks */
#define mtlgt3__ext8__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext8 :: AVG GPU Core Frequency */
#define mtlgt3__ext8__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext8 :: AVG GPU Core Frequency */
#define mtlgt3__ext8__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext8 :: ICACHE L3 READ L3BANK0 */
#define mtlgt3__ext8__icache_l3_read_l3_bank0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext8 :: ICACHE L3 READ L3BANK1 */
#define mtlgt3__ext8__icache_l3_read_l3_bank1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext8 :: ICACHE L3 READ L3BANK2 */
#define mtlgt3__ext8__icache_l3_read_l3_bank2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext8 :: ICACHE L3 READ L3BANK3 */
#define mtlgt3__ext8__icache_l3_read_l3_bank3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext8 :: ICACHE L3 READ L3BANK4 */
#define mtlgt3__ext8__icache_l3_read_l3_bank4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext8 :: ICACHE L3 READ L3BANK5 */
#define mtlgt3__ext8__icache_l3_read_l3_bank5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext8 :: ICACHE L3 READ L3BANK6 */
#define mtlgt3__ext8__icache_l3_read_l3_bank6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext8 :: ICACHE L3 READ L3BANK7 */
#define mtlgt3__ext8__icache_l3_read_l3_bank7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext8 :: ICACHE L3 HIT L3BANK0 */
#define mtlgt3__ext8__icache_l3_hit_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext8 :: ICACHE L3 HIT L3BANK1 */
#define mtlgt3__ext8__icache_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext8 :: ICACHE L3 HIT L3BANK2 */
#define mtlgt3__ext8__icache_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext8 :: ICACHE L3 HIT L3BANK3 */
#define mtlgt3__ext8__icache_l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext8 :: ICACHE L3 HIT L3BANK4 */
#define mtlgt3__ext8__icache_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext8 :: ICACHE L3 HIT L3BANK5 */
#define mtlgt3__ext8__icache_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext8 :: ICACHE L3 HIT L3BANK6 */
#define mtlgt3__ext8__icache_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext8 :: ICACHE L3 HIT L3BANK7 */
#define mtlgt3__ext8__icache_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext9 :: GPU Time Elapsed */
#define mtlgt3__ext9__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext9 :: GPU Core Clocks */
#define mtlgt3__ext9__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext9 :: AVG GPU Core Frequency */
#define mtlgt3__ext9__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext9 :: AVG GPU Core Frequency */
#define mtlgt3__ext9__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext9 :: Z L3 ACCESS L3BANK0 */
#define mtlgt3__ext9__z_l3_access_l3_bank0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext9 :: Z L3 ACCESS L3BANK1 */
#define mtlgt3__ext9__z_l3_access_l3_bank1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext9 :: Z L3 ACCESS L3BANK2 */
#define mtlgt3__ext9__z_l3_access_l3_bank2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext9 :: Z L3 ACCESS L3BANK3 */
#define mtlgt3__ext9__z_l3_access_l3_bank3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext9 :: Z L3 ACCESS L3BANK4 */
#define mtlgt3__ext9__z_l3_access_l3_bank4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext9 :: Z L3 ACCESS L3BANK5 */
#define mtlgt3__ext9__z_l3_access_l3_bank5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext9 :: Z L3 ACCESS L3BANK6 */
#define mtlgt3__ext9__z_l3_access_l3_bank6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext9 :: Z L3 ACCESS L3BANK7 */
#define mtlgt3__ext9__z_l3_access_l3_bank7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext10 :: GPU Time Elapsed */
#define mtlgt3__ext10__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext10 :: GPU Core Clocks */
#define mtlgt3__ext10__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext10 :: AVG GPU Core Frequency */
#define mtlgt3__ext10__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext10 :: AVG GPU Core Frequency */
#define mtlgt3__ext10__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext10 :: DATAPORT L3 HIT L3BANK0 */
#define mtlgt3__ext10__dataport_l3_hit_l3_bank0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext10 :: DATAPORT L3 HIT L3BANK1 */
#define mtlgt3__ext10__dataport_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext10 :: DATAPORT L3 HIT L3BANK2 */
#define mtlgt3__ext10__dataport_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext10 :: DATAPORT L3 HIT L3BANK3 */
#define mtlgt3__ext10__dataport_l3_hit_l3_bank3__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext10 :: DATAPORT L3 HIT L3BANK4 */
#define mtlgt3__ext10__dataport_l3_hit_l3_bank4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext10 :: DATAPORT L3 HIT L3BANK5 */
#define mtlgt3__ext10__dataport_l3_hit_l3_bank5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext10 :: DATAPORT L3 HIT L3BANK6 */
#define mtlgt3__ext10__dataport_l3_hit_l3_bank6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext10 :: DATAPORT L3 HIT L3BANK7 */
#define mtlgt3__ext10__dataport_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext10 :: COLOR L3 HIT L3BANK0 */
#define mtlgt3__ext10__color_l3_hit_l3_bank0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext10 :: COLOR L3 HIT L3BANK1 */
#define mtlgt3__ext10__color_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext10 :: COLOR L3 HIT L3BANK2 */
#define mtlgt3__ext10__color_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext10 :: COLOR L3 HIT L3BANK3 */
#define mtlgt3__ext10__color_l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext10 :: COLOR L3 HIT L3BANK4 */
#define mtlgt3__ext10__color_l3_hit_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext10 :: COLOR L3 HIT L3BANK5 */
#define mtlgt3__ext10__color_l3_hit_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext10 :: COLOR L3 HIT L3BANK6 */
#define mtlgt3__ext10__color_l3_hit_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext10 :: COLOR L3 HIT L3BANK7 */
#define mtlgt3__ext10__color_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext11 :: GPU Time Elapsed */
#define mtlgt3__ext11__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext11 :: GPU Core Clocks */
#define mtlgt3__ext11__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext11 :: AVG GPU Core Frequency */
#define mtlgt3__ext11__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext11 :: AVG GPU Core Frequency */
#define mtlgt3__ext11__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext11 :: Z L3 HIT L3BANK0 */
#define mtlgt3__ext11__z_l3_hit_l3_bank0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext11 :: Z L3 HIT L3BANK1 */
#define mtlgt3__ext11__z_l3_hit_l3_bank1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext11 :: Z L3 HIT L3BANK2 */
#define mtlgt3__ext11__z_l3_hit_l3_bank2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext11 :: Z L3 HIT L3BANK3 */
#define mtlgt3__ext11__z_l3_hit_l3_bank3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext11 :: Z L3 HIT L3BANK4 */
#define mtlgt3__ext11__z_l3_hit_l3_bank4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext11 :: Z L3 HIT L3BANK5 */
#define mtlgt3__ext11__z_l3_hit_l3_bank5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext11 :: Z L3 HIT L3BANK6 */
#define mtlgt3__ext11__z_l3_hit_l3_bank6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext11 :: Z L3 HIT L3BANK7 */
#define mtlgt3__ext11__z_l3_hit_l3_bank7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK0 */
#define mtlgt3__ext11__l3_atomic_access_l3_bank0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK1 */
#define mtlgt3__ext11__l3_atomic_access_l3_bank1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK2 */
#define mtlgt3__ext11__l3_atomic_access_l3_bank2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK3 */
#define mtlgt3__ext11__l3_atomic_access_l3_bank3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK4 */
#define mtlgt3__ext11__l3_atomic_access_l3_bank4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK5 */
#define mtlgt3__ext11__l3_atomic_access_l3_bank5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK6 */
#define mtlgt3__ext11__l3_atomic_access_l3_bank6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext11 :: L3 ATOMIC ACCESS L3BANK7 */
#define mtlgt3__ext11__l3_atomic_access_l3_bank7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext12 :: GPU Time Elapsed */
#define mtlgt3__ext12__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext12 :: GPU Core Clocks */
#define mtlgt3__ext12__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext12 :: AVG GPU Core Frequency */
#define mtlgt3__ext12__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext12 :: AVG GPU Core Frequency */
#define mtlgt3__ext12__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext12 :: L3 INPUT AVAILABLE L3BANK0 */
#define mtlgt3__ext12__l3_input_available_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK1 */
#define mtlgt3__ext12__l3_input_available_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK2 */
#define mtlgt3__ext12__l3_input_available_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK3 */
#define mtlgt3__ext12__l3_input_available_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK4 */
#define mtlgt3__ext12__l3_input_available_l3_bank4__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK5 */
#define mtlgt3__ext12__l3_input_available_l3_bank5__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK6 */
#define mtlgt3__ext12__l3_input_available_l3_bank6__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext12 :: L3 INPUT AVAILABLE L3BANK7 */
#define mtlgt3__ext12__l3_input_available_l3_bank7__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK0 */
#define mtlgt3__ext12__l3_output_ready_l3_bank0__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK1 */
#define mtlgt3__ext12__l3_output_ready_l3_bank1__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK2 */
#define mtlgt3__ext12__l3_output_ready_l3_bank2__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK3 */
#define mtlgt3__ext12__l3_output_ready_l3_bank3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext12 :: L3 OUTPUT READY L3BANK4 */
#define mtlgt3__ext12__l3_output_ready_l3_bank4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK5 */
#define mtlgt3__ext12__l3_output_ready_l3_bank5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK6 */
#define mtlgt3__ext12__l3_output_ready_l3_bank6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext12 :: L3 OUTPUT READY L3BANK7 */
#define mtlgt3__ext12__l3_output_ready_l3_bank7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext13 :: GPU Time Elapsed */
#define mtlgt3__ext13__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext13 :: GPU Core Clocks */
#define mtlgt3__ext13__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext13 :: AVG GPU Core Frequency */
#define mtlgt3__ext13__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext13 :: AVG GPU Core Frequency */
#define mtlgt3__ext13__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext13 :: L3 SUPERQ FULL L3BANK0 */
#define mtlgt3__ext13__l3_superq_full_l3_bank0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext13 :: L3 SUPERQ FULL L3BANK1 */
#define mtlgt3__ext13__l3_superq_full_l3_bank1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext13 :: L3 SUPERQ FULL L3BANK2 */
#define mtlgt3__ext13__l3_superq_full_l3_bank2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext13 :: L3 SUPERQ FULL L3BANK3 */
#define mtlgt3__ext13__l3_superq_full_l3_bank3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext13 :: COLOR L3 ACCESS L3BANK0 */
#define mtlgt3__ext13__color_l3_access_l3_bank0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext13 :: COLOR L3 ACCESS L3BANK1 */
#define mtlgt3__ext13__color_l3_access_l3_bank1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext13 :: COLOR L3 ACCESS L3BANK2 */
#define mtlgt3__ext13__color_l3_access_l3_bank2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext13 :: COLOR L3 ACCESS L3BANK3 */
#define mtlgt3__ext13__color_l3_access_l3_bank3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext14 :: GPU Time Elapsed */
#define mtlgt3__ext14__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext14 :: GPU Core Clocks */
#define mtlgt3__ext14__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext14 :: AVG GPU Core Frequency */
#define mtlgt3__ext14__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext14 :: AVG GPU Core Frequency */
#define mtlgt3__ext14__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext14 :: L3 SUPERQ FULL L3BANK4 */
#define mtlgt3__ext14__l3_superq_full_l3_bank4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext14 :: L3 SUPERQ FULL L3BANK5 */
#define mtlgt3__ext14__l3_superq_full_l3_bank5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext14 :: L3 SUPERQ FULL L3BANK6 */
#define mtlgt3__ext14__l3_superq_full_l3_bank6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext14 :: L3 SUPERQ FULL L3BANK7 */
#define mtlgt3__ext14__l3_superq_full_l3_bank7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext14 :: COLOR L3 ACCESS L3BANK4 */
#define mtlgt3__ext14__color_l3_access_l3_bank4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext14 :: COLOR L3 ACCESS L3BANK5 */
#define mtlgt3__ext14__color_l3_access_l3_bank5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext14 :: COLOR L3 ACCESS L3BANK6 */
#define mtlgt3__ext14__color_l3_access_l3_bank6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext14 :: COLOR L3 ACCESS L3BANK7 */
#define mtlgt3__ext14__color_l3_access_l3_bank7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext15 :: GPU Time Elapsed */
#define mtlgt3__ext15__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext15 :: GPU Core Clocks */
#define mtlgt3__ext15__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext15 :: AVG GPU Core Frequency */
#define mtlgt3__ext15__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext15 :: AVG GPU Core Frequency */
#define mtlgt3__ext15__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext15 :: L3 BUSY L3BANK0 */
#define mtlgt3__ext15__l3_busy_l3_bank0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext15 :: L3 BUSY L3BANK1 */
#define mtlgt3__ext15__l3_busy_l3_bank1__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext15 :: L3 BUSY L3BANK2 */
#define mtlgt3__ext15__l3_busy_l3_bank2__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext15 :: L3 BUSY L3BANK3 */
#define mtlgt3__ext15__l3_busy_l3_bank3__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext15 :: L3 STALL L3BANK0 */
#define mtlgt3__ext15__l3_stall_l3_bank0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext15 :: L3 STALL L3BANK1 */
#define mtlgt3__ext15__l3_stall_l3_bank1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext15 :: L3 STALL L3BANK2 */
#define mtlgt3__ext15__l3_stall_l3_bank2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext15 :: L3 STALL L3BANK3 */
#define mtlgt3__ext15__l3_stall_l3_bank3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext16 :: GPU Time Elapsed */
#define mtlgt3__ext16__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext16 :: GPU Core Clocks */
#define mtlgt3__ext16__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext16 :: AVG GPU Core Frequency */
#define mtlgt3__ext16__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext16 :: AVG GPU Core Frequency */
#define mtlgt3__ext16__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext16 :: L3 BUSY L3BANK4 */
#define mtlgt3__ext16__l3_busy_l3_bank4__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext16 :: L3 BUSY L3BANK5 */
#define mtlgt3__ext16__l3_busy_l3_bank5__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext16 :: L3 BUSY L3BANK6 */
#define mtlgt3__ext16__l3_busy_l3_bank6__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext16 :: L3 BUSY L3BANK7 */
#define mtlgt3__ext16__l3_busy_l3_bank7__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext16 :: L3 STALL L3BANK4 */
#define mtlgt3__ext16__l3_stall_l3_bank4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext16 :: L3 STALL L3BANK5 */
#define mtlgt3__ext16__l3_stall_l3_bank5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext16 :: L3 STALL L3BANK6 */
#define mtlgt3__ext16__l3_stall_l3_bank6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext16 :: L3 STALL L3BANK7 */
#define mtlgt3__ext16__l3_stall_l3_bank7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext17 :: GPU Time Elapsed */
#define mtlgt3__ext17__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext17 :: GPU Core Clocks */
#define mtlgt3__ext17__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext17 :: AVG GPU Core Frequency */
#define mtlgt3__ext17__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext17 :: AVG GPU Core Frequency */
#define mtlgt3__ext17__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE0 */
#define mtlgt3__ext17__load_store_cache_input_available_xecore0__read \
   mtlgt2__ext17__load_store_cache_input_available_xecore3__read

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE1 */
#define mtlgt3__ext17__load_store_cache_input_available_xecore1__read \
   mtlgt2__ext17__load_store_cache_input_available_xecore2__read

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE2 */
#define mtlgt3__ext17__load_store_cache_input_available_xecore2__read \
   mtlgt2__ext17__load_store_cache_input_available_xecore1__read

/* Ext17 :: LOAD STORE CACHE INPUT AVAILABLE XECORE3 */
#define mtlgt3__ext17__load_store_cache_input_available_xecore3__read \
   mtlgt2__ext17__load_store_cache_input_available_xecore0__read

/* Ext17 :: LOAD STORE CACHE OUTPUT READY XECORE0 */
#define mtlgt3__ext17__load_store_cache_output_ready_xecore0__read \
   mtlgt2__ext17__load_store_cache_output_ready_xecore0__read

/* Ext17 :: LOAD STORE CACHE OUTPUT READY XECORE1 */
#define mtlgt3__ext17__load_store_cache_output_ready_xecore1__read \
   mtlgt2__ext17__load_store_cache_output_ready_xecore3__read

/* Ext17 :: LOAD STORE CACHE OUTPUT READY XECORE2 */
#define mtlgt3__ext17__load_store_cache_output_ready_xecore2__read \
   mtlgt2__ext17__load_store_cache_output_ready_xecore2__read

/* Ext17 :: LOAD STORE CACHE OUTPUT READY XECORE3 */
#define mtlgt3__ext17__load_store_cache_output_ready_xecore3__read \
   mtlgt2__ext17__load_store_cache_output_ready_xecore1__read

/* Ext18 :: GPU Time Elapsed */
#define mtlgt3__ext18__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext18 :: GPU Core Clocks */
#define mtlgt3__ext18__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext18 :: AVG GPU Core Frequency */
#define mtlgt3__ext18__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext18 :: AVG GPU Core Frequency */
#define mtlgt3__ext18__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext18 :: LOAD STORE CACHE INPUT AVAILABLE XECORE4 */
#define mtlgt3__ext18__load_store_cache_input_available_xecore4__read \
   mtlgt2__ext17__load_store_cache_input_available_xecore0__read

/* Ext18 :: LOAD STORE CACHE INPUT AVAILABLE XECORE5 */
#define mtlgt3__ext18__load_store_cache_input_available_xecore5__read \
   mtlgt2__ext17__load_store_cache_input_available_xecore1__read

/* Ext18 :: LOAD STORE CACHE INPUT AVAILABLE XECORE6 */
#define mtlgt3__ext18__load_store_cache_input_available_xecore6__read \
   mtlgt2__ext17__load_store_cache_input_available_xecore2__read

/* Ext18 :: LOAD STORE CACHE INPUT AVAILABLE XECORE7 */
#define mtlgt3__ext18__load_store_cache_input_available_xecore7__read \
   mtlgt2__ext17__load_store_cache_input_available_xecore3__read

/* Ext18 :: LOAD STORE CACHE OUTPUT READY XECORE4 */
#define mtlgt3__ext18__load_store_cache_output_ready_xecore4__read \
   mtlgt2__ext17__load_store_cache_output_ready_xecore0__read

/* Ext18 :: LOAD STORE CACHE OUTPUT READY XECORE5 */
#define mtlgt3__ext18__load_store_cache_output_ready_xecore5__read \
   mtlgt2__ext17__load_store_cache_output_ready_xecore1__read

/* Ext18 :: LOAD STORE CACHE OUTPUT READY XECORE6 */
#define mtlgt3__ext18__load_store_cache_output_ready_xecore6__read \
   mtlgt2__ext17__load_store_cache_output_ready_xecore2__read

/* Ext18 :: LOAD STORE CACHE OUTPUT READY XECORE7 */
#define mtlgt3__ext18__load_store_cache_output_ready_xecore7__read \
   mtlgt2__ext17__load_store_cache_output_ready_xecore3__read

/* Ext21 :: GPU Time Elapsed */
#define mtlgt3__ext21__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext21 :: GPU Core Clocks */
#define mtlgt3__ext21__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext21 :: AVG GPU Core Frequency */
#define mtlgt3__ext21__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext21 :: AVG GPU Core Frequency */
#define mtlgt3__ext21__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE0 */
#define mtlgt3__ext21__load_store_cache_access_xecore0__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE1 */
#define mtlgt3__ext21__load_store_cache_access_xecore1__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE2 */
#define mtlgt3__ext21__load_store_cache_access_xecore2__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext21 :: LOAD STORE CACHE ACCESS XECORE3 */
#define mtlgt3__ext21__load_store_cache_access_xecore3__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext21 :: LOAD STORE CACHE L3 READ XECORE0 */
#define mtlgt3__ext21__load_store_cache_l3_read_xecore0__read \
   mtlgt3__ext3__gpu_memory_32_b_transaction_read__read

/* Ext21 :: LOAD STORE CACHE L3 READ XECORE1 */
#define mtlgt3__ext21__load_store_cache_l3_read_xecore1__read \
   mtlgt3__ext3__gpu_memory_64_b_transaction_write__read

/* Ext21 :: LOAD STORE CACHE L3 READ XECORE2 */
#define mtlgt3__ext21__load_store_cache_l3_read_xecore2__read \
   bdw__compute_l3_cache__l3_misses__read

/* Ext21 :: LOAD STORE CACHE L3 READ XECORE3 */
#define mtlgt3__ext21__load_store_cache_l3_read_xecore3__read \
   mtlgt3__ext3__gpu_memory_64_b_transaction_read__read

/* Ext22 :: GPU Time Elapsed */
#define mtlgt3__ext22__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext22 :: GPU Core Clocks */
#define mtlgt3__ext22__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext22 :: AVG GPU Core Frequency */
#define mtlgt3__ext22__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext22 :: AVG GPU Core Frequency */
#define mtlgt3__ext22__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext22 :: LOAD STORE CACHE ACCESS XECORE4 */
#define mtlgt3__ext22__load_store_cache_access_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext22 :: LOAD STORE CACHE ACCESS XECORE5 */
#define mtlgt3__ext22__load_store_cache_access_xecore5__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext22 :: LOAD STORE CACHE ACCESS XECORE6 */
#define mtlgt3__ext22__load_store_cache_access_xecore6__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext22 :: LOAD STORE CACHE ACCESS XECORE7 */
#define mtlgt3__ext22__load_store_cache_access_xecore7__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext22 :: LOAD STORE CACHE L3 READ XECORE4 */
#define mtlgt3__ext22__load_store_cache_l3_read_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext22 :: LOAD STORE CACHE L3 READ XECORE5 */
#define mtlgt3__ext22__load_store_cache_l3_read_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext22 :: LOAD STORE CACHE L3 READ XECORE6 */
#define mtlgt3__ext22__load_store_cache_l3_read_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext22 :: LOAD STORE CACHE L3 READ XECORE7 */
#define mtlgt3__ext22__load_store_cache_l3_read_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext23 :: GPU Time Elapsed */
#define mtlgt3__ext23__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext23 :: GPU Core Clocks */
#define mtlgt3__ext23__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext23 :: AVG GPU Core Frequency */
#define mtlgt3__ext23__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext23 :: AVG GPU Core Frequency */
#define mtlgt3__ext23__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext23 :: LOAD STORE CACHE HIT XECORE0 */
#define mtlgt3__ext23__load_store_cache_hit_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext23 :: LOAD STORE CACHE HIT XECORE1 */
#define mtlgt3__ext23__load_store_cache_hit_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext23 :: LOAD STORE CACHE HIT XECORE2 */
#define mtlgt3__ext23__load_store_cache_hit_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext23 :: LOAD STORE CACHE HIT XECORE3 */
#define mtlgt3__ext23__load_store_cache_hit_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext24 :: GPU Time Elapsed */
#define mtlgt3__ext24__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext24 :: GPU Core Clocks */
#define mtlgt3__ext24__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext24 :: AVG GPU Core Frequency */
#define mtlgt3__ext24__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext24 :: AVG GPU Core Frequency */
#define mtlgt3__ext24__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext24 :: LOAD STORE CACHE HIT XECORE4 */
#define mtlgt3__ext24__load_store_cache_hit_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext24 :: LOAD STORE CACHE HIT XECORE5 */
#define mtlgt3__ext24__load_store_cache_hit_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext24 :: LOAD STORE CACHE HIT XECORE6 */
#define mtlgt3__ext24__load_store_cache_hit_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext24 :: LOAD STORE CACHE HIT XECORE7 */
#define mtlgt3__ext24__load_store_cache_hit_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext28 :: GPU Time Elapsed */
#define mtlgt3__ext28__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext28 :: GPU Core Clocks */
#define mtlgt3__ext28__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext28 :: AVG GPU Core Frequency */
#define mtlgt3__ext28__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext28 :: AVG GPU Core Frequency */
#define mtlgt3__ext28__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE0 */
#define mtlgt3__ext28__load_store_cache_l3_write_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE1 */
#define mtlgt3__ext28__load_store_cache_l3_write_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE2 */
#define mtlgt3__ext28__load_store_cache_l3_write_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext28 :: LOAD STORE CACHE L3 WRITE XECORE3 */
#define mtlgt3__ext28__load_store_cache_l3_write_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext28 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0 */
#define mtlgt3__ext28__load_store_cache_partial_write_count_xecore0__read \
   mtlgt3__ext3__gpu_memory_32_b_transaction_read__read

/* Ext28 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1 */
#define mtlgt3__ext28__load_store_cache_partial_write_count_xecore1__read \
   mtlgt3__ext3__gpu_memory_64_b_transaction_write__read

/* Ext28 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2 */
#define mtlgt3__ext28__load_store_cache_partial_write_count_xecore2__read \
   bdw__compute_l3_cache__l3_misses__read

/* Ext28 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3 */
#define mtlgt3__ext28__load_store_cache_partial_write_count_xecore3__read \
   mtlgt3__ext3__gpu_memory_64_b_transaction_read__read

/* Ext29 :: GPU Time Elapsed */
#define mtlgt3__ext29__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext29 :: GPU Core Clocks */
#define mtlgt3__ext29__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext29 :: AVG GPU Core Frequency */
#define mtlgt3__ext29__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext29 :: AVG GPU Core Frequency */
#define mtlgt3__ext29__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext29 :: LOAD STORE CACHE L3 WRITE XECORE4 */
#define mtlgt3__ext29__load_store_cache_l3_write_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext29 :: LOAD STORE CACHE L3 WRITE XECORE5 */
#define mtlgt3__ext29__load_store_cache_l3_write_xecore5__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext29 :: LOAD STORE CACHE L3 WRITE XECORE6 */
#define mtlgt3__ext29__load_store_cache_l3_write_xecore6__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext29 :: LOAD STORE CACHE L3 WRITE XECORE7 */
#define mtlgt3__ext29__load_store_cache_l3_write_xecore7__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext29 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4 */
#define mtlgt3__ext29__load_store_cache_partial_write_count_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext29 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5 */
#define mtlgt3__ext29__load_store_cache_partial_write_count_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext29 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6 */
#define mtlgt3__ext29__load_store_cache_partial_write_count_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext29 :: LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7 */
#define mtlgt3__ext29__load_store_cache_partial_write_count_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext31 :: GPU Time Elapsed */
#define mtlgt3__ext31__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext31 :: GPU Core Clocks */
#define mtlgt3__ext31__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext31 :: AVG GPU Core Frequency */
#define mtlgt3__ext31__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext31 :: AVG GPU Core Frequency */
#define mtlgt3__ext31__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext31 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext32 :: GPU Time Elapsed */
#define mtlgt3__ext32__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext32 :: GPU Core Clocks */
#define mtlgt3__ext32__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext32 :: AVG GPU Core Frequency */
#define mtlgt3__ext32__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext32 :: AVG GPU Core Frequency */
#define mtlgt3__ext32__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext32 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4 */
#define mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext32 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5 */
#define mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext32 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6 */
#define mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext32 :: XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7 */
#define mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext35 :: GPU Time Elapsed */
#define mtlgt3__ext35__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext35 :: GPU Core Clocks */
#define mtlgt3__ext35__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext35 :: AVG GPU Core Frequency */
#define mtlgt3__ext35__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext35 :: AVG GPU Core Frequency */
#define mtlgt3__ext35__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0 */
#define mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1 */
#define mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2 */
#define mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext35 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3 */
#define mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext36 :: GPU Time Elapsed */
#define mtlgt3__ext36__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext36 :: GPU Core Clocks */
#define mtlgt3__ext36__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext36 :: AVG GPU Core Frequency */
#define mtlgt3__ext36__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext36 :: AVG GPU Core Frequency */
#define mtlgt3__ext36__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext36 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4 */
#define mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext36 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5 */
#define mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext36 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6 */
#define mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext36 :: XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7 */
#define mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext39 :: GPU Time Elapsed */
#define mtlgt3__ext39__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext39 :: GPU Core Clocks */
#define mtlgt3__ext39__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext39 :: AVG GPU Core Frequency */
#define mtlgt3__ext39__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext39 :: AVG GPU Core Frequency */
#define mtlgt3__ext39__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0 */
#define mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1 */
#define mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2 */
#define mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext39 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3 */
#define mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext40 :: GPU Time Elapsed */
#define mtlgt3__ext40__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext40 :: GPU Core Clocks */
#define mtlgt3__ext40__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext40 :: AVG GPU Core Frequency */
#define mtlgt3__ext40__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext40 :: AVG GPU Core Frequency */
#define mtlgt3__ext40__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext40 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4 */
#define mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext40 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5 */
#define mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext40 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6 */
#define mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext40 :: XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7 */
#define mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext43 :: GPU Time Elapsed */
#define mtlgt3__ext43__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext43 :: GPU Core Clocks */
#define mtlgt3__ext43__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext43 :: AVG GPU Core Frequency */
#define mtlgt3__ext43__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext43 :: AVG GPU Core Frequency */
#define mtlgt3__ext43__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext43 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0 */
#define mtlgt3__ext43__xve_load_store_cache_atomic_message_count_xecore0__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext43 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1 */
#define mtlgt3__ext43__xve_load_store_cache_atomic_message_count_xecore1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext43 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0 */
#define mtlgt3__ext43__xve_load_store_cache_register_request_count_xecore0__read \
   mtlgt3__ext3__gpu_memory_64_b_transaction_write__read

/* Ext43 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1 */
#define mtlgt3__ext43__xve_load_store_cache_register_request_count_xecore1__read \
   bdw__compute_l3_cache__l3_misses__read

/* Ext44 :: GPU Time Elapsed */
#define mtlgt3__ext44__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext44 :: GPU Core Clocks */
#define mtlgt3__ext44__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext44 :: AVG GPU Core Frequency */
#define mtlgt3__ext44__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext44 :: AVG GPU Core Frequency */
#define mtlgt3__ext44__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext44 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4 */
#define mtlgt3__ext44__xve_load_store_cache_atomic_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext44 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5 */
#define mtlgt3__ext44__xve_load_store_cache_atomic_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext44 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4 */
#define mtlgt3__ext44__xve_load_store_cache_register_request_count_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext44 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5 */
#define mtlgt3__ext44__xve_load_store_cache_register_request_count_xecore5__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext45 :: GPU Time Elapsed */
#define mtlgt3__ext45__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext45 :: GPU Core Clocks */
#define mtlgt3__ext45__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext45 :: AVG GPU Core Frequency */
#define mtlgt3__ext45__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext45 :: AVG GPU Core Frequency */
#define mtlgt3__ext45__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext45 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2 */
#define mtlgt3__ext45__xve_load_store_cache_atomic_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext45 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3 */
#define mtlgt3__ext45__xve_load_store_cache_atomic_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext45 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2 */
#define mtlgt3__ext45__xve_load_store_cache_register_request_count_xecore2__read \
   mtlgt3__ext3__gpu_memory_64_b_transaction_write__read

/* Ext45 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3 */
#define mtlgt3__ext45__xve_load_store_cache_register_request_count_xecore3__read \
   bdw__compute_l3_cache__l3_misses__read

/* Ext46 :: GPU Time Elapsed */
#define mtlgt3__ext46__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext46 :: GPU Core Clocks */
#define mtlgt3__ext46__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext46 :: AVG GPU Core Frequency */
#define mtlgt3__ext46__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext46 :: AVG GPU Core Frequency */
#define mtlgt3__ext46__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext46 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6 */
#define mtlgt3__ext46__xve_load_store_cache_atomic_message_count_xecore6__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext46 :: XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7 */
#define mtlgt3__ext46__xve_load_store_cache_atomic_message_count_xecore7__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext46 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6 */
#define mtlgt3__ext46__xve_load_store_cache_register_request_count_xecore6__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext46 :: XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7 */
#define mtlgt3__ext46__xve_load_store_cache_register_request_count_xecore7__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext51 :: GPU Time Elapsed */
#define mtlgt3__ext51__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext51 :: GPU Core Clocks */
#define mtlgt3__ext51__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext51 :: AVG GPU Core Frequency */
#define mtlgt3__ext51__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext51 :: AVG GPU Core Frequency */
#define mtlgt3__ext51__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0 */
#define mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1 */
#define mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2 */
#define mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3 */
#define mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4 */
#define mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5 */
#define mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore5__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6 */
#define mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore6__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext51 :: XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7 */
#define mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore7__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext53 :: GPU Time Elapsed */
#define mtlgt3__ext53__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext53 :: GPU Core Clocks */
#define mtlgt3__ext53__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext53 :: AVG GPU Core Frequency */
#define mtlgt3__ext53__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext53 :: AVG GPU Core Frequency */
#define mtlgt3__ext53__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE0 */
#define mtlgt3__ext53__xve_slm_read_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE1 */
#define mtlgt3__ext53__xve_slm_read_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE2 */
#define mtlgt3__ext53__xve_slm_read_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext53 :: XVE SLM READ MESSAGE COUNT XECORE3 */
#define mtlgt3__ext53__xve_slm_read_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext54 :: GPU Time Elapsed */
#define mtlgt3__ext54__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext54 :: GPU Core Clocks */
#define mtlgt3__ext54__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext54 :: AVG GPU Core Frequency */
#define mtlgt3__ext54__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext54 :: AVG GPU Core Frequency */
#define mtlgt3__ext54__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext54 :: XVE SLM READ MESSAGE COUNT XECORE4 */
#define mtlgt3__ext54__xve_slm_read_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext54 :: XVE SLM READ MESSAGE COUNT XECORE5 */
#define mtlgt3__ext54__xve_slm_read_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext54 :: XVE SLM READ MESSAGE COUNT XECORE6 */
#define mtlgt3__ext54__xve_slm_read_message_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext54 :: XVE SLM READ MESSAGE COUNT XECORE7 */
#define mtlgt3__ext54__xve_slm_read_message_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext57 :: GPU Time Elapsed */
#define mtlgt3__ext57__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext57 :: GPU Core Clocks */
#define mtlgt3__ext57__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext57 :: AVG GPU Core Frequency */
#define mtlgt3__ext57__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext57 :: AVG GPU Core Frequency */
#define mtlgt3__ext57__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE0 */
#define mtlgt3__ext57__xve_slm_write_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE1 */
#define mtlgt3__ext57__xve_slm_write_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE2 */
#define mtlgt3__ext57__xve_slm_write_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext57 :: XVE SLM WRITE MESSAGE COUNT XECORE3 */
#define mtlgt3__ext57__xve_slm_write_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext58 :: GPU Time Elapsed */
#define mtlgt3__ext58__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext58 :: GPU Core Clocks */
#define mtlgt3__ext58__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext58 :: AVG GPU Core Frequency */
#define mtlgt3__ext58__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext58 :: AVG GPU Core Frequency */
#define mtlgt3__ext58__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext58 :: XVE SLM WRITE MESSAGE COUNT XECORE4 */
#define mtlgt3__ext58__xve_slm_write_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext58 :: XVE SLM WRITE MESSAGE COUNT XECORE5 */
#define mtlgt3__ext58__xve_slm_write_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext58 :: XVE SLM WRITE MESSAGE COUNT XECORE6 */
#define mtlgt3__ext58__xve_slm_write_message_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext58 :: XVE SLM WRITE MESSAGE COUNT XECORE7 */
#define mtlgt3__ext58__xve_slm_write_message_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext61 :: GPU Time Elapsed */
#define mtlgt3__ext61__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext61 :: GPU Core Clocks */
#define mtlgt3__ext61__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext61 :: AVG GPU Core Frequency */
#define mtlgt3__ext61__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext61 :: AVG GPU Core Frequency */
#define mtlgt3__ext61__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE0 */
#define mtlgt3__ext61__xve_slm_fence_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE1 */
#define mtlgt3__ext61__xve_slm_fence_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE2 */
#define mtlgt3__ext61__xve_slm_fence_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext61 :: XVE SLM FENCE MESSAGE COUNT XECORE3 */
#define mtlgt3__ext61__xve_slm_fence_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext62 :: GPU Time Elapsed */
#define mtlgt3__ext62__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext62 :: GPU Core Clocks */
#define mtlgt3__ext62__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext62 :: AVG GPU Core Frequency */
#define mtlgt3__ext62__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext62 :: AVG GPU Core Frequency */
#define mtlgt3__ext62__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext62 :: XVE SLM FENCE MESSAGE COUNT XECORE4 */
#define mtlgt3__ext62__xve_slm_fence_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext62 :: XVE SLM FENCE MESSAGE COUNT XECORE5 */
#define mtlgt3__ext62__xve_slm_fence_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext62 :: XVE SLM FENCE MESSAGE COUNT XECORE6 */
#define mtlgt3__ext62__xve_slm_fence_message_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext62 :: XVE SLM FENCE MESSAGE COUNT XECORE7 */
#define mtlgt3__ext62__xve_slm_fence_message_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext65 :: GPU Time Elapsed */
#define mtlgt3__ext65__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext65 :: GPU Core Clocks */
#define mtlgt3__ext65__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext65 :: AVG GPU Core Frequency */
#define mtlgt3__ext65__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext65 :: AVG GPU Core Frequency */
#define mtlgt3__ext65__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext65 :: XVE SLM ATOMIC MESSAGE COUNT XECORE0 */
#define mtlgt3__ext65__xve_slm_atomic_message_count_xecore0__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext65 :: XVE SLM ATOMIC MESSAGE COUNT XECORE1 */
#define mtlgt3__ext65__xve_slm_atomic_message_count_xecore1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext66 :: GPU Time Elapsed */
#define mtlgt3__ext66__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext66 :: GPU Core Clocks */
#define mtlgt3__ext66__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext66 :: AVG GPU Core Frequency */
#define mtlgt3__ext66__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext66 :: AVG GPU Core Frequency */
#define mtlgt3__ext66__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext66 :: XVE SLM ATOMIC MESSAGE COUNT XECORE2 */
#define mtlgt3__ext66__xve_slm_atomic_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext66 :: XVE SLM ATOMIC MESSAGE COUNT XECORE3 */
#define mtlgt3__ext66__xve_slm_atomic_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext67 :: GPU Time Elapsed */
#define mtlgt3__ext67__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext67 :: GPU Core Clocks */
#define mtlgt3__ext67__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext67 :: AVG GPU Core Frequency */
#define mtlgt3__ext67__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext67 :: AVG GPU Core Frequency */
#define mtlgt3__ext67__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext67 :: XVE SLM ATOMIC MESSAGE COUNT XECORE4 */
#define mtlgt3__ext67__xve_slm_atomic_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext67 :: XVE SLM ATOMIC MESSAGE COUNT XECORE5 */
#define mtlgt3__ext67__xve_slm_atomic_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext68 :: GPU Time Elapsed */
#define mtlgt3__ext68__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext68 :: GPU Core Clocks */
#define mtlgt3__ext68__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext68 :: AVG GPU Core Frequency */
#define mtlgt3__ext68__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext68 :: AVG GPU Core Frequency */
#define mtlgt3__ext68__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext68 :: XVE SLM ATOMIC MESSAGE COUNT XECORE6 */
#define mtlgt3__ext68__xve_slm_atomic_message_count_xecore6__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext68 :: XVE SLM ATOMIC MESSAGE COUNT XECORE7 */
#define mtlgt3__ext68__xve_slm_atomic_message_count_xecore7__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext73 :: GPU Time Elapsed */
#define mtlgt3__ext73__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext73 :: GPU Core Clocks */
#define mtlgt3__ext73__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext73 :: AVG GPU Core Frequency */
#define mtlgt3__ext73__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext73 :: AVG GPU Core Frequency */
#define mtlgt3__ext73__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext73 :: DATAPORT INPUT AVAILABLE XECORE0 */
#define mtlgt3__ext73__dataport_input_available_xecore0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext73 :: DATAPORT INPUT AVAILABLE XECORE1 */
#define mtlgt3__ext73__dataport_input_available_xecore1__read \
   bdw__render_basic__sampler0_busy__read

/* Ext74 :: GPU Time Elapsed */
#define mtlgt3__ext74__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext74 :: GPU Core Clocks */
#define mtlgt3__ext74__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext74 :: AVG GPU Core Frequency */
#define mtlgt3__ext74__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext74 :: AVG GPU Core Frequency */
#define mtlgt3__ext74__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext74 :: DATAPORT INPUT AVAILABLE XECORE2 */
#define mtlgt3__ext74__dataport_input_available_xecore2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext74 :: DATAPORT INPUT AVAILABLE XECORE3 */
#define mtlgt3__ext74__dataport_input_available_xecore3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext75 :: GPU Time Elapsed */
#define mtlgt3__ext75__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext75 :: GPU Core Clocks */
#define mtlgt3__ext75__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext75 :: AVG GPU Core Frequency */
#define mtlgt3__ext75__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext75 :: AVG GPU Core Frequency */
#define mtlgt3__ext75__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext75 :: DATAPORT INPUT AVAILABLE XECORE4 */
#define mtlgt3__ext75__dataport_input_available_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext75 :: DATAPORT INPUT AVAILABLE XECORE5 */
#define mtlgt3__ext75__dataport_input_available_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext76 :: GPU Time Elapsed */
#define mtlgt3__ext76__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext76 :: GPU Core Clocks */
#define mtlgt3__ext76__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext76 :: AVG GPU Core Frequency */
#define mtlgt3__ext76__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext76 :: AVG GPU Core Frequency */
#define mtlgt3__ext76__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext76 :: DATAPORT INPUT AVAILABLE XECORE6 */
#define mtlgt3__ext76__dataport_input_available_xecore6__read \
   bdw__render_basic__sampler0_busy__read

/* Ext76 :: DATAPORT INPUT AVAILABLE XECORE7 */
#define mtlgt3__ext76__dataport_input_available_xecore7__read \
   bdw__render_basic__sampler1_busy__read

/* Ext77 :: GPU Time Elapsed */
#define mtlgt3__ext77__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext77 :: GPU Core Clocks */
#define mtlgt3__ext77__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext77 :: AVG GPU Core Frequency */
#define mtlgt3__ext77__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext77 :: AVG GPU Core Frequency */
#define mtlgt3__ext77__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext77 :: DATAPORT OUTPUT READY XECORE0 */
#define mtlgt3__ext77__dataport_output_ready_xecore0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext77 :: DATAPORT OUTPUT READY XECORE1 */
#define mtlgt3__ext77__dataport_output_ready_xecore1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext77 :: DATAPORT OUTPUT READY XECORE2 */
#define mtlgt3__ext77__dataport_output_ready_xecore2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext77 :: DATAPORT OUTPUT READY XECORE3 */
#define mtlgt3__ext77__dataport_output_ready_xecore3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext78 :: GPU Time Elapsed */
#define mtlgt3__ext78__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext78 :: GPU Core Clocks */
#define mtlgt3__ext78__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext78 :: AVG GPU Core Frequency */
#define mtlgt3__ext78__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext78 :: AVG GPU Core Frequency */
#define mtlgt3__ext78__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext78 :: DATAPORT OUTPUT READY XECORE4 */
#define mtlgt3__ext78__dataport_output_ready_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext78 :: DATAPORT OUTPUT READY XECORE5 */
#define mtlgt3__ext78__dataport_output_ready_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext78 :: DATAPORT OUTPUT READY XECORE6 */
#define mtlgt3__ext78__dataport_output_ready_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext78 :: DATAPORT OUTPUT READY XECORE7 */
#define mtlgt3__ext78__dataport_output_ready_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext79 :: GPU Time Elapsed */
#define mtlgt3__ext79__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext79 :: GPU Core Clocks */
#define mtlgt3__ext79__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext79 :: AVG GPU Core Frequency */
#define mtlgt3__ext79__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext79 :: AVG GPU Core Frequency */
#define mtlgt3__ext79__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext79 :: DATAPORT BYTE READ XECORE0 */
#define mtlgt3__ext79__dataport_byte_read_xecore0__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext79 :: DATAPORT BYTE READ XECORE1 */
#define mtlgt3__ext79__dataport_byte_read_xecore1__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext80 :: GPU Time Elapsed */
#define mtlgt3__ext80__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext80 :: GPU Core Clocks */
#define mtlgt3__ext80__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext80 :: AVG GPU Core Frequency */
#define mtlgt3__ext80__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext80 :: AVG GPU Core Frequency */
#define mtlgt3__ext80__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext80 :: DATAPORT BYTE READ XECORE2 */
#define mtlgt3__ext80__dataport_byte_read_xecore2__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext80 :: DATAPORT BYTE READ XECORE3 */
#define mtlgt3__ext80__dataport_byte_read_xecore3__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext81 :: GPU Time Elapsed */
#define mtlgt3__ext81__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext81 :: GPU Core Clocks */
#define mtlgt3__ext81__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext81 :: AVG GPU Core Frequency */
#define mtlgt3__ext81__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext81 :: AVG GPU Core Frequency */
#define mtlgt3__ext81__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext81 :: DATAPORT BYTE READ XECORE4 */
#define mtlgt3__ext81__dataport_byte_read_xecore4__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext81 :: DATAPORT BYTE READ XECORE5 */
#define mtlgt3__ext81__dataport_byte_read_xecore5__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext82 :: GPU Time Elapsed */
#define mtlgt3__ext82__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext82 :: GPU Core Clocks */
#define mtlgt3__ext82__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext82 :: AVG GPU Core Frequency */
#define mtlgt3__ext82__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext82 :: AVG GPU Core Frequency */
#define mtlgt3__ext82__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext82 :: DATAPORT BYTE READ XECORE6 */
#define mtlgt3__ext82__dataport_byte_read_xecore6__read \
   acmgt1__ext79__dataport_byte_read_xecore0__read

/* Ext82 :: DATAPORT BYTE READ XECORE7 */
#define mtlgt3__ext82__dataport_byte_read_xecore7__read \
   acmgt1__ext79__dataport_byte_read_xecore1__read

/* Ext83 :: GPU Time Elapsed */
#define mtlgt3__ext83__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext83 :: GPU Core Clocks */
#define mtlgt3__ext83__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext83 :: AVG GPU Core Frequency */
#define mtlgt3__ext83__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext83 :: AVG GPU Core Frequency */
#define mtlgt3__ext83__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext83 :: DATAPORT BYTE WRITE XECORE0 */
#define mtlgt3__ext83__dataport_byte_write_xecore0__read \
   acmgt2__dataport29__dataport_byte_write_xecore12__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE1 */
#define mtlgt3__ext83__dataport_byte_write_xecore1__read \
   acmgt2__dataport29__dataport_byte_write_xecore13__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE2 */
#define mtlgt3__ext83__dataport_byte_write_xecore2__read \
   acmgt2__dataport29__dataport_byte_write_xecore14__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE3 */
#define mtlgt3__ext83__dataport_byte_write_xecore3__read \
   acmgt2__dataport29__dataport_byte_write_xecore15__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE4 */
#define mtlgt3__ext83__dataport_byte_write_xecore4__read \
   acmgt1__ext83__dataport_byte_write_xecore0__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE5 */
#define mtlgt3__ext83__dataport_byte_write_xecore5__read \
   acmgt1__ext83__dataport_byte_write_xecore1__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE6 */
#define mtlgt3__ext83__dataport_byte_write_xecore6__read \
   acmgt1__ext83__dataport_byte_write_xecore2__read

/* Ext83 :: DATAPORT BYTE WRITE XECORE7 */
#define mtlgt3__ext83__dataport_byte_write_xecore7__read \
   acmgt1__ext83__dataport_byte_write_xecore3__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE0 */
#define mtlgt3__ext83__dataport_texture_cache_access_xecore0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE1 */
#define mtlgt3__ext83__dataport_texture_cache_access_xecore1__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE2 */
#define mtlgt3__ext83__dataport_texture_cache_access_xecore2__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE3 */
#define mtlgt3__ext83__dataport_texture_cache_access_xecore3__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE4 */
#define mtlgt3__ext83__dataport_texture_cache_access_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE5 */
#define mtlgt3__ext83__dataport_texture_cache_access_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE6 */
#define mtlgt3__ext83__dataport_texture_cache_access_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext83 :: DATAPORT TEXTURE CACHE ACCESS XECORE7 */
#define mtlgt3__ext83__dataport_texture_cache_access_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext85 :: GPU Time Elapsed */
#define mtlgt3__ext85__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext85 :: GPU Core Clocks */
#define mtlgt3__ext85__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext85 :: AVG GPU Core Frequency */
#define mtlgt3__ext85__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext85 :: AVG GPU Core Frequency */
#define mtlgt3__ext85__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE0 */
#define mtlgt3__ext85__xve_dataport_read_message_count_xecore0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE1 */
#define mtlgt3__ext85__xve_dataport_read_message_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE2 */
#define mtlgt3__ext85__xve_dataport_read_message_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext85 :: XVE DATAPORT READ MESSAGE COUNT XECORE3 */
#define mtlgt3__ext85__xve_dataport_read_message_count_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext85 :: DATAPORT TEXTURE CACHE HIT XECORE0 */
#define mtlgt3__ext85__dataport_texture_cache_hit_xecore0__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext85 :: DATAPORT TEXTURE CACHE HIT XECORE1 */
#define mtlgt3__ext85__dataport_texture_cache_hit_xecore1__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext85 :: DATAPORT TEXTURE CACHE HIT XECORE2 */
#define mtlgt3__ext85__dataport_texture_cache_hit_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext85 :: DATAPORT TEXTURE CACHE HIT XECORE3 */
#define mtlgt3__ext85__dataport_texture_cache_hit_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext86 :: GPU Time Elapsed */
#define mtlgt3__ext86__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext86 :: GPU Core Clocks */
#define mtlgt3__ext86__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext86 :: AVG GPU Core Frequency */
#define mtlgt3__ext86__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext86 :: AVG GPU Core Frequency */
#define mtlgt3__ext86__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext86 :: XVE DATAPORT READ MESSAGE COUNT XECORE4 */
#define mtlgt3__ext86__xve_dataport_read_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext86 :: XVE DATAPORT READ MESSAGE COUNT XECORE5 */
#define mtlgt3__ext86__xve_dataport_read_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext86 :: XVE DATAPORT READ MESSAGE COUNT XECORE6 */
#define mtlgt3__ext86__xve_dataport_read_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext86 :: XVE DATAPORT READ MESSAGE COUNT XECORE7 */
#define mtlgt3__ext86__xve_dataport_read_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext86 :: DATAPORT TEXTURE CACHE HIT XECORE4 */
#define mtlgt3__ext86__dataport_texture_cache_hit_xecore4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext86 :: DATAPORT TEXTURE CACHE HIT XECORE5 */
#define mtlgt3__ext86__dataport_texture_cache_hit_xecore5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext86 :: DATAPORT TEXTURE CACHE HIT XECORE6 */
#define mtlgt3__ext86__dataport_texture_cache_hit_xecore6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext86 :: DATAPORT TEXTURE CACHE HIT XECORE7 */
#define mtlgt3__ext86__dataport_texture_cache_hit_xecore7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext87 :: GPU Time Elapsed */
#define mtlgt3__ext87__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext87 :: GPU Core Clocks */
#define mtlgt3__ext87__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext87 :: AVG GPU Core Frequency */
#define mtlgt3__ext87__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext87 :: AVG GPU Core Frequency */
#define mtlgt3__ext87__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE0 */
#define mtlgt3__ext87__xve_dataport_write_message_count_xecore0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE1 */
#define mtlgt3__ext87__xve_dataport_write_message_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE2 */
#define mtlgt3__ext87__xve_dataport_write_message_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext87 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE3 */
#define mtlgt3__ext87__xve_dataport_write_message_count_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext88 :: GPU Time Elapsed */
#define mtlgt3__ext88__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext88 :: GPU Core Clocks */
#define mtlgt3__ext88__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext88 :: AVG GPU Core Frequency */
#define mtlgt3__ext88__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext88 :: AVG GPU Core Frequency */
#define mtlgt3__ext88__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext88 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE4 */
#define mtlgt3__ext88__xve_dataport_write_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext88 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE5 */
#define mtlgt3__ext88__xve_dataport_write_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext88 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE6 */
#define mtlgt3__ext88__xve_dataport_write_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext88 :: XVE DATAPORT WRITE MESSAGE COUNT XECORE7 */
#define mtlgt3__ext88__xve_dataport_write_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext91 :: GPU Time Elapsed */
#define mtlgt3__ext91__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext91 :: GPU Core Clocks */
#define mtlgt3__ext91__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext91 :: AVG GPU Core Frequency */
#define mtlgt3__ext91__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext91 :: AVG GPU Core Frequency */
#define mtlgt3__ext91__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0 */
#define mtlgt3__ext91__xve_dataport_atomic_message_count_xecore0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1 */
#define mtlgt3__ext91__xve_dataport_atomic_message_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2 */
#define mtlgt3__ext91__xve_dataport_atomic_message_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext91 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3 */
#define mtlgt3__ext91__xve_dataport_atomic_message_count_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext92 :: GPU Time Elapsed */
#define mtlgt3__ext92__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext92 :: GPU Core Clocks */
#define mtlgt3__ext92__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext92 :: AVG GPU Core Frequency */
#define mtlgt3__ext92__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext92 :: AVG GPU Core Frequency */
#define mtlgt3__ext92__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext92 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4 */
#define mtlgt3__ext92__xve_dataport_atomic_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext92 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5 */
#define mtlgt3__ext92__xve_dataport_atomic_message_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext92 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6 */
#define mtlgt3__ext92__xve_dataport_atomic_message_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext92 :: XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7 */
#define mtlgt3__ext92__xve_dataport_atomic_message_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext93 :: GPU Time Elapsed */
#define mtlgt3__ext93__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext93 :: GPU Core Clocks */
#define mtlgt3__ext93__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext93 :: AVG GPU Core Frequency */
#define mtlgt3__ext93__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext93 :: AVG GPU Core Frequency */
#define mtlgt3__ext93__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext93 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE0 */
static uint64_t
mtlgt3__ext93__xve_dataport_register_response_count_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                                  const struct intel_perf_query_info *query,
                                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 4 READ B 5 READ UADD B 6 READ UADD B 7 READ UADD 2 UDIV */
   uint64_t tmp0 = results->accumulator[query->b_offset + 4];
   uint64_t tmp1 = results->accumulator[query->b_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 6];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 7];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = tmp6;
   uint64_t tmp8 = 2;
   uint64_t tmp9 = tmp7 / tmp8;

   return tmp9;
}

/* Ext93 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE1 */
#define mtlgt3__ext93__xve_dataport_register_response_count_xecore1__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext94 :: GPU Time Elapsed */
#define mtlgt3__ext94__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext94 :: GPU Core Clocks */
#define mtlgt3__ext94__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext94 :: AVG GPU Core Frequency */
#define mtlgt3__ext94__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext94 :: AVG GPU Core Frequency */
#define mtlgt3__ext94__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext94 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE2 */
#define mtlgt3__ext94__xve_dataport_register_response_count_xecore2__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext94 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE3 */
#define mtlgt3__ext94__xve_dataport_register_response_count_xecore3__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext95 :: GPU Time Elapsed */
#define mtlgt3__ext95__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext95 :: GPU Core Clocks */
#define mtlgt3__ext95__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext95 :: AVG GPU Core Frequency */
#define mtlgt3__ext95__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext95 :: AVG GPU Core Frequency */
#define mtlgt3__ext95__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext95 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE4 */
#define mtlgt3__ext95__xve_dataport_register_response_count_xecore4__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext95 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE5 */
#define mtlgt3__ext95__xve_dataport_register_response_count_xecore5__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext96 :: GPU Time Elapsed */
#define mtlgt3__ext96__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext96 :: GPU Core Clocks */
#define mtlgt3__ext96__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext96 :: AVG GPU Core Frequency */
#define mtlgt3__ext96__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext96 :: AVG GPU Core Frequency */
#define mtlgt3__ext96__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext96 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE6 */
#define mtlgt3__ext96__xve_dataport_register_response_count_xecore6__read \
   acmgt1__ext94__xve_dataport_register_response_count_xecore2__read

/* Ext96 :: XVE DATAPORT REGISTER RESPONSE COUNT XECORE7 */
#define mtlgt3__ext96__xve_dataport_register_response_count_xecore7__read \
   acmgt1__ext93__xve_dataport_register_response_count_xecore1__read

/* Ext97 :: GPU Time Elapsed */
#define mtlgt3__ext97__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext97 :: GPU Core Clocks */
#define mtlgt3__ext97__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext97 :: AVG GPU Core Frequency */
#define mtlgt3__ext97__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext97 :: AVG GPU Core Frequency */
#define mtlgt3__ext97__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE0 */
#define mtlgt3__ext97__xve_dataport_register_request_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE1 */
#define mtlgt3__ext97__xve_dataport_register_request_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE2 */
#define mtlgt3__ext97__xve_dataport_register_request_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE3 */
#define mtlgt3__ext97__xve_dataport_register_request_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE4 */
#define mtlgt3__ext97__xve_dataport_register_request_count_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE5 */
#define mtlgt3__ext97__xve_dataport_register_request_count_xecore5__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE6 */
#define mtlgt3__ext97__xve_dataport_register_request_count_xecore6__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext97 :: XVE DATAPORT REGISTER REQUEST COUNT XECORE7 */
#define mtlgt3__ext97__xve_dataport_register_request_count_xecore7__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext98 :: GPU Time Elapsed */
#define mtlgt3__ext98__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext98 :: GPU Core Clocks */
#define mtlgt3__ext98__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext98 :: AVG GPU Core Frequency */
#define mtlgt3__ext98__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext98 :: AVG GPU Core Frequency */
#define mtlgt3__ext98__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext98 :: SAMPLER OUTPUT READY XECORE0 */
#define mtlgt3__ext98__sampler_output_ready_xecore0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext98 :: SAMPLER OUTPUT READY XECORE1 */
#define mtlgt3__ext98__sampler_output_ready_xecore1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext98 :: SAMPLER OUTPUT READY XECORE2 */
#define mtlgt3__ext98__sampler_output_ready_xecore2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext98 :: SAMPLER OUTPUT READY XECORE3 */
#define mtlgt3__ext98__sampler_output_ready_xecore3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext99 :: GPU Time Elapsed */
#define mtlgt3__ext99__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext99 :: GPU Core Clocks */
#define mtlgt3__ext99__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext99 :: AVG GPU Core Frequency */
#define mtlgt3__ext99__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext99 :: AVG GPU Core Frequency */
#define mtlgt3__ext99__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext99 :: SAMPLER OUTPUT READY XECORE4 */
#define mtlgt3__ext99__sampler_output_ready_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext99 :: SAMPLER OUTPUT READY XECORE5 */
#define mtlgt3__ext99__sampler_output_ready_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext99 :: SAMPLER OUTPUT READY XECORE6 */
#define mtlgt3__ext99__sampler_output_ready_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext99 :: SAMPLER OUTPUT READY XECORE7 */
#define mtlgt3__ext99__sampler_output_ready_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext100 :: GPU Time Elapsed */
#define mtlgt3__ext100__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext100 :: GPU Core Clocks */
#define mtlgt3__ext100__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext100 :: AVG GPU Core Frequency */
#define mtlgt3__ext100__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext100 :: AVG GPU Core Frequency */
#define mtlgt3__ext100__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE0 */
#define mtlgt3__ext100__sampler_memory_latency_stall_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE1 */
#define mtlgt3__ext100__sampler_memory_latency_stall_xecore1__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE2 */
#define mtlgt3__ext100__sampler_memory_latency_stall_xecore2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext100 :: SAMPLER MEMORY LATENCY STALL XECORE3 */
#define mtlgt3__ext100__sampler_memory_latency_stall_xecore3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext100 :: SAMPLER INPUT AVAILABLE XECORE0 */
#define mtlgt3__ext100__sampler_input_available_xecore0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext100 :: SAMPLER INPUT AVAILABLE XECORE1 */
#define mtlgt3__ext100__sampler_input_available_xecore1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext100 :: SAMPLER INPUT AVAILABLE XECORE2 */
#define mtlgt3__ext100__sampler_input_available_xecore2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext100 :: SAMPLER INPUT AVAILABLE XECORE3 */
#define mtlgt3__ext100__sampler_input_available_xecore3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext101 :: GPU Time Elapsed */
#define mtlgt3__ext101__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext101 :: GPU Core Clocks */
#define mtlgt3__ext101__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext101 :: AVG GPU Core Frequency */
#define mtlgt3__ext101__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext101 :: AVG GPU Core Frequency */
#define mtlgt3__ext101__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext101 :: SAMPLER MEMORY LATENCY STALL XECORE4 */
#define mtlgt3__ext101__sampler_memory_latency_stall_xecore4__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext101 :: SAMPLER MEMORY LATENCY STALL XECORE5 */
#define mtlgt3__ext101__sampler_memory_latency_stall_xecore5__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext101 :: SAMPLER MEMORY LATENCY STALL XECORE6 */
#define mtlgt3__ext101__sampler_memory_latency_stall_xecore6__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext101 :: SAMPLER MEMORY LATENCY STALL XECORE7 */
#define mtlgt3__ext101__sampler_memory_latency_stall_xecore7__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext101 :: SAMPLER INPUT AVAILABLE XECORE4 */
#define mtlgt3__ext101__sampler_input_available_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext101 :: SAMPLER INPUT AVAILABLE XECORE5 */
#define mtlgt3__ext101__sampler_input_available_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext101 :: SAMPLER INPUT AVAILABLE XECORE6 */
#define mtlgt3__ext101__sampler_input_available_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext101 :: SAMPLER INPUT AVAILABLE XECORE7 */
#define mtlgt3__ext101__sampler_input_available_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext102 :: GPU Time Elapsed */
#define mtlgt3__ext102__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext102 :: GPU Core Clocks */
#define mtlgt3__ext102__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext102 :: AVG GPU Core Frequency */
#define mtlgt3__ext102__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext102 :: AVG GPU Core Frequency */
#define mtlgt3__ext102__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext102 :: THREAD DISPATCH STALL XECORE0 */
#define mtlgt3__ext102__thread_dispatch_stall_xecore0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext102 :: THREAD DISPATCH STALL XECORE1 */
#define mtlgt3__ext102__thread_dispatch_stall_xecore1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext102 :: THREAD DISPATCH STALL XECORE2 */
#define mtlgt3__ext102__thread_dispatch_stall_xecore2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext102 :: THREAD DISPATCH STALL XECORE3 */
#define mtlgt3__ext102__thread_dispatch_stall_xecore3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext102 :: THREAD DISPATCH INPUT AVAILABLE XECORE0 */
#define mtlgt3__ext102__thread_dispatch_input_available_xecore0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext102 :: THREAD DISPATCH INPUT AVAILABLE XECORE1 */
#define mtlgt3__ext102__thread_dispatch_input_available_xecore1__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext102 :: THREAD DISPATCH INPUT AVAILABLE XECORE2 */
#define mtlgt3__ext102__thread_dispatch_input_available_xecore2__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext102 :: THREAD DISPATCH INPUT AVAILABLE XECORE3 */
#define mtlgt3__ext102__thread_dispatch_input_available_xecore3__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext102 :: THREAD DISPATCH STALL XECORE4 */
#define mtlgt3__ext102__thread_dispatch_stall_xecore4__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext102 :: THREAD DISPATCH STALL XECORE5 */
#define mtlgt3__ext102__thread_dispatch_stall_xecore5__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext102 :: THREAD DISPATCH STALL XECORE6 */
#define mtlgt3__ext102__thread_dispatch_stall_xecore6__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext102 :: THREAD DISPATCH STALL XECORE7 */
#define mtlgt3__ext102__thread_dispatch_stall_xecore7__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext102 :: THREAD DISPATCH INPUT AVAILABLE XECORE4 */
#define mtlgt3__ext102__thread_dispatch_input_available_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext102 :: THREAD DISPATCH INPUT AVAILABLE XECORE5 */
#define mtlgt3__ext102__thread_dispatch_input_available_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext102 :: THREAD DISPATCH INPUT AVAILABLE XECORE6 */
#define mtlgt3__ext102__thread_dispatch_input_available_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext102 :: THREAD DISPATCH INPUT AVAILABLE XECORE7 */
#define mtlgt3__ext102__thread_dispatch_input_available_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext103 :: GPU Time Elapsed */
#define mtlgt3__ext103__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext103 :: GPU Core Clocks */
#define mtlgt3__ext103__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext103 :: AVG GPU Core Frequency */
#define mtlgt3__ext103__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext103 :: AVG GPU Core Frequency */
#define mtlgt3__ext103__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext103 :: SAMPLER TEXTURE CACHE ACCESS XECORE0 */
#define mtlgt3__ext103__sampler_texture_cache_access_xecore0__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext103 :: SAMPLER TEXTURE CACHE ACCESS XECORE1 */
#define mtlgt3__ext103__sampler_texture_cache_access_xecore1__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext103 :: SAMPLER TEXTURE CACHE ACCESS XECORE2 */
#define mtlgt3__ext103__sampler_texture_cache_access_xecore2__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext103 :: SAMPLER TEXTURE CACHE ACCESS XECORE3 */
#define mtlgt3__ext103__sampler_texture_cache_access_xecore3__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext103 :: SAMPLER TEXTURE CACHE MISS XECORE0 */
#define mtlgt3__ext103__sampler_texture_cache_miss_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext103 :: SAMPLER TEXTURE CACHE MISS XECORE1 */
#define mtlgt3__ext103__sampler_texture_cache_miss_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext103 :: SAMPLER TEXTURE CACHE MISS XECORE2 */
#define mtlgt3__ext103__sampler_texture_cache_miss_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext103 :: SAMPLER TEXTURE CACHE MISS XECORE3 */
#define mtlgt3__ext103__sampler_texture_cache_miss_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext103 :: SAMPLER TEXTURE CACHE ACCESS XECORE4 */
#define mtlgt3__ext103__sampler_texture_cache_access_xecore4__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext103 :: SAMPLER TEXTURE CACHE ACCESS XECORE5 */
#define mtlgt3__ext103__sampler_texture_cache_access_xecore5__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext103 :: SAMPLER TEXTURE CACHE ACCESS XECORE6 */
#define mtlgt3__ext103__sampler_texture_cache_access_xecore6__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext103 :: SAMPLER TEXTURE CACHE ACCESS XECORE7 */
#define mtlgt3__ext103__sampler_texture_cache_access_xecore7__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext103 :: SAMPLER TEXTURE CACHE MISS XECORE4 */
#define mtlgt3__ext103__sampler_texture_cache_miss_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext103 :: SAMPLER TEXTURE CACHE MISS XECORE5 */
#define mtlgt3__ext103__sampler_texture_cache_miss_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext103 :: SAMPLER TEXTURE CACHE MISS XECORE6 */
#define mtlgt3__ext103__sampler_texture_cache_miss_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext103 :: SAMPLER TEXTURE CACHE MISS XECORE7 */
#define mtlgt3__ext103__sampler_texture_cache_miss_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext104 :: GPU Time Elapsed */
#define mtlgt3__ext104__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext104 :: GPU Core Clocks */
#define mtlgt3__ext104__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext104 :: AVG GPU Core Frequency */
#define mtlgt3__ext104__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext104 :: AVG GPU Core Frequency */
#define mtlgt3__ext104__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext104 :: ASYNC GPGPU THREAD EXIT COUNT XECORE0 */
#define mtlgt3__ext104__async_gpgpu_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext104 :: TASK THREAD EXIT COUNT XECORE0 */
#define mtlgt3__ext104__task_thread_exit_count_xecore0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext104 :: GPGPU THREADGROUP COUNT XECORE2 */
#define mtlgt3__ext104__gpgpu_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext104 :: TASK THREADGROUP COUNT XECORE2 */
#define mtlgt3__ext104__task_threadgroup_count_xecore2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext105 :: GPU Time Elapsed */
#define mtlgt3__ext105__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext105 :: GPU Core Clocks */
#define mtlgt3__ext105__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext105 :: AVG GPU Core Frequency */
#define mtlgt3__ext105__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext105 :: AVG GPU Core Frequency */
#define mtlgt3__ext105__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext105 :: ASYNC GPGPU THREAD EXIT COUNT XECORE1 */
#define mtlgt3__ext105__async_gpgpu_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext105 :: TASK THREAD EXIT COUNT XECORE1 */
#define mtlgt3__ext105__task_thread_exit_count_xecore1__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext105 :: GPGPU THREADGROUP COUNT XECORE3 */
#define mtlgt3__ext105__gpgpu_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext105 :: TASK THREADGROUP COUNT XECORE3 */
#define mtlgt3__ext105__task_threadgroup_count_xecore3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext106 :: GPU Time Elapsed */
#define mtlgt3__ext106__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext106 :: GPU Core Clocks */
#define mtlgt3__ext106__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext106 :: AVG GPU Core Frequency */
#define mtlgt3__ext106__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext106 :: AVG GPU Core Frequency */
#define mtlgt3__ext106__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext106 :: ASYNC GPGPU THREAD EXIT COUNT XECORE2 */
#define mtlgt3__ext106__async_gpgpu_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext106 :: TASK THREAD EXIT COUNT XECORE2 */
#define mtlgt3__ext106__task_thread_exit_count_xecore2__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext106 :: GPGPU THREADGROUP COUNT XECORE0 */
#define mtlgt3__ext106__gpgpu_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext106 :: TASK THREADGROUP COUNT XECORE0 */
#define mtlgt3__ext106__task_threadgroup_count_xecore0__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext107 :: GPU Time Elapsed */
#define mtlgt3__ext107__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext107 :: GPU Core Clocks */
#define mtlgt3__ext107__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext107 :: AVG GPU Core Frequency */
#define mtlgt3__ext107__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext107 :: AVG GPU Core Frequency */
#define mtlgt3__ext107__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext107 :: ASYNC GPGPU THREAD EXIT COUNT XECORE3 */
#define mtlgt3__ext107__async_gpgpu_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext107 :: TASK THREAD EXIT COUNT XECORE3 */
#define mtlgt3__ext107__task_thread_exit_count_xecore3__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext107 :: GPGPU THREADGROUP COUNT XECORE1 */
#define mtlgt3__ext107__gpgpu_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext107 :: TASK THREADGROUP COUNT XECORE1 */
#define mtlgt3__ext107__task_threadgroup_count_xecore1__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext108 :: GPU Time Elapsed */
#define mtlgt3__ext108__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext108 :: GPU Core Clocks */
#define mtlgt3__ext108__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext108 :: AVG GPU Core Frequency */
#define mtlgt3__ext108__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext108 :: AVG GPU Core Frequency */
#define mtlgt3__ext108__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext108 :: ASYNC GPGPU THREAD EXIT COUNT XECORE4 */
#define mtlgt3__ext108__async_gpgpu_thread_exit_count_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext108 :: TASK THREAD EXIT COUNT XECORE4 */
#define mtlgt3__ext108__task_thread_exit_count_xecore4__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext108 :: GPGPU THREADGROUP COUNT XECORE6 */
#define mtlgt3__ext108__gpgpu_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext108 :: TASK THREADGROUP COUNT XECORE6 */
#define mtlgt3__ext108__task_threadgroup_count_xecore6__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext109 :: GPU Time Elapsed */
#define mtlgt3__ext109__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext109 :: GPU Core Clocks */
#define mtlgt3__ext109__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext109 :: AVG GPU Core Frequency */
#define mtlgt3__ext109__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext109 :: AVG GPU Core Frequency */
#define mtlgt3__ext109__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext109 :: ASYNC GPGPU THREAD EXIT COUNT XECORE5 */
#define mtlgt3__ext109__async_gpgpu_thread_exit_count_xecore5__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext109 :: TASK THREAD EXIT COUNT XECORE5 */
#define mtlgt3__ext109__task_thread_exit_count_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext109 :: GPGPU THREADGROUP COUNT XECORE7 */
#define mtlgt3__ext109__gpgpu_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext109 :: TASK THREADGROUP COUNT XECORE7 */
#define mtlgt3__ext109__task_threadgroup_count_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext110 :: GPU Time Elapsed */
#define mtlgt3__ext110__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext110 :: GPU Core Clocks */
#define mtlgt3__ext110__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext110 :: AVG GPU Core Frequency */
#define mtlgt3__ext110__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext110 :: AVG GPU Core Frequency */
#define mtlgt3__ext110__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext110 :: ASYNC GPGPU THREAD EXIT COUNT XECORE6 */
#define mtlgt3__ext110__async_gpgpu_thread_exit_count_xecore6__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext110 :: TASK THREAD EXIT COUNT XECORE6 */
#define mtlgt3__ext110__task_thread_exit_count_xecore6__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext110 :: GPGPU THREADGROUP COUNT XECORE4 */
#define mtlgt3__ext110__gpgpu_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext110 :: TASK THREADGROUP COUNT XECORE4 */
#define mtlgt3__ext110__task_threadgroup_count_xecore4__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext111 :: GPU Time Elapsed */
#define mtlgt3__ext111__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext111 :: GPU Core Clocks */
#define mtlgt3__ext111__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext111 :: AVG GPU Core Frequency */
#define mtlgt3__ext111__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext111 :: AVG GPU Core Frequency */
#define mtlgt3__ext111__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext111 :: ASYNC GPGPU THREAD EXIT COUNT XECORE7 */
#define mtlgt3__ext111__async_gpgpu_thread_exit_count_xecore7__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext111 :: TASK THREAD EXIT COUNT XECORE7 */
#define mtlgt3__ext111__task_thread_exit_count_xecore7__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext111 :: GPGPU THREADGROUP COUNT XECORE5 */
#define mtlgt3__ext111__gpgpu_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext111 :: TASK THREADGROUP COUNT XECORE5 */
#define mtlgt3__ext111__task_threadgroup_count_xecore5__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext113 :: GPU Time Elapsed */
#define mtlgt3__ext113__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext113 :: GPU Core Clocks */
#define mtlgt3__ext113__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext113 :: AVG GPU Core Frequency */
#define mtlgt3__ext113__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext113 :: AVG GPU Core Frequency */
#define mtlgt3__ext113__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext113 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE0 */
#define mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE1 */
#define mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE2 */
#define mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext113 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE3 */
#define mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext113 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE0 */
#define mtlgt3__ext113__thread_dispatch_queue0_active_xecore0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext113 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE0 */
#define mtlgt3__ext113__thread_dispatch_queue1_active_xecore0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext113 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE1 */
#define mtlgt3__ext113__thread_dispatch_queue0_active_xecore1__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE1 */
#define mtlgt3__ext113__thread_dispatch_queue1_active_xecore1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE2 */
#define mtlgt3__ext113__thread_dispatch_queue0_active_xecore2__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE2 */
#define mtlgt3__ext113__thread_dispatch_queue1_active_xecore2__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE3 */
#define mtlgt3__ext113__thread_dispatch_queue0_active_xecore3__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext113 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE3 */
#define mtlgt3__ext113__thread_dispatch_queue1_active_xecore3__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext114 :: GPU Time Elapsed */
#define mtlgt3__ext114__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext114 :: GPU Core Clocks */
#define mtlgt3__ext114__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext114 :: AVG GPU Core Frequency */
#define mtlgt3__ext114__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext114 :: AVG GPU Core Frequency */
#define mtlgt3__ext114__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext114 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE4 */
#define mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext114 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE5 */
#define mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext114 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE6 */
#define mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext114 :: THREAD DISPATCH PS ACTIVE CYCLES XECORE7 */
#define mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE4 */
#define mtlgt3__ext114__thread_dispatch_queue0_active_xecore4__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext114 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE4 */
#define mtlgt3__ext114__thread_dispatch_queue1_active_xecore4__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE5 */
#define mtlgt3__ext114__thread_dispatch_queue0_active_xecore5__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext114 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE5 */
#define mtlgt3__ext114__thread_dispatch_queue1_active_xecore5__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE6 */
#define mtlgt3__ext114__thread_dispatch_queue0_active_xecore6__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext114 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE6 */
#define mtlgt3__ext114__thread_dispatch_queue1_active_xecore6__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext114 :: THREAD DISPATCH QUEUE0 ACTIVE XECORE7 */
#define mtlgt3__ext114__thread_dispatch_queue0_active_xecore7__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext114 :: THREAD DISPATCH QUEUE1 ACTIVE XECORE7 */
#define mtlgt3__ext114__thread_dispatch_queue1_active_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext116 :: GPU Time Elapsed */
#define mtlgt3__ext116__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext116 :: GPU Core Clocks */
#define mtlgt3__ext116__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext116 :: AVG GPU Core Frequency */
#define mtlgt3__ext116__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext116 :: AVG GPU Core Frequency */
#define mtlgt3__ext116__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE0 */
#define mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE1 */
#define mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE2 */
#define mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext116 :: THREADGROUP DISPATCH RESOURCE STALL XECORE3 */
#define mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore3__read \
   bdw__render_basic__sampler0_busy__read

/* Ext117 :: GPU Time Elapsed */
#define mtlgt3__ext117__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext117 :: GPU Core Clocks */
#define mtlgt3__ext117__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext117 :: AVG GPU Core Frequency */
#define mtlgt3__ext117__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext117 :: AVG GPU Core Frequency */
#define mtlgt3__ext117__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext117 :: THREADGROUP DISPATCH RESOURCE STALL XECORE4 */
#define mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext117 :: THREADGROUP DISPATCH RESOURCE STALL XECORE5 */
#define mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext117 :: THREADGROUP DISPATCH RESOURCE STALL XECORE6 */
#define mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext117 :: THREADGROUP DISPATCH RESOURCE STALL XECORE7 */
#define mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext118 :: GPU Time Elapsed */
#define mtlgt3__ext118__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext118 :: GPU Core Clocks */
#define mtlgt3__ext118__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext118 :: AVG GPU Core Frequency */
#define mtlgt3__ext118__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext118 :: AVG GPU Core Frequency */
#define mtlgt3__ext118__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext118 :: AMFS STALL ALL INPUT SLICE0 */
#define mtlgt3__ext118__amfs_stall_all_input_slice0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext118 :: AMFS STALL ANY INPUT SLICE0 */
#define mtlgt3__ext118__amfs_stall_any_input_slice0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext118 :: AMFS CACHE HIT SLICE0 */
#define mtlgt3__ext118__amfs_cache_hit_slice0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext118 :: AMFS CACHE MISS SLICE0 */
#define mtlgt3__ext118__amfs_cache_miss_slice0__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext118 :: RENDER CACHE HIT L3NODE0 */
#define mtlgt3__ext118__render_cache_hit_l3_node0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext118 :: RENDER CACHE READ L3NODE0 */
#define mtlgt3__ext118__render_cache_read_l3_node0__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext118 :: RENDER CACHE WRITE L3NODE0 */
#define mtlgt3__ext118__render_cache_write_l3_node0__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext118 :: RENDER CACHE INPUT AVAILABLE _L3NODE0 */
#define mtlgt3__ext118__render_cache_input_available_l3_node0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext118 :: RENDER CACHE OUTPUT READY _L3NODE0 */
#define mtlgt3__ext118__render_cache_output_ready_l3_node0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext119 :: GPU Time Elapsed */
#define mtlgt3__ext119__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext119 :: GPU Core Clocks */
#define mtlgt3__ext119__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext119 :: AVG GPU Core Frequency */
#define mtlgt3__ext119__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext119 :: AVG GPU Core Frequency */
#define mtlgt3__ext119__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext119 :: AMFS STALL ALL INPUT SLICE1 */
#define mtlgt3__ext119__amfs_stall_all_input_slice1__read \
   bdw__render_basic__sampler0_busy__read

/* Ext119 :: AMFS STALL ANY INPUT SLICE1 */
#define mtlgt3__ext119__amfs_stall_any_input_slice1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext119 :: AMFS CACHE HIT SLICE1 */
#define mtlgt3__ext119__amfs_cache_hit_slice1__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext119 :: AMFS CACHE MISS SLICE1 */
#define mtlgt3__ext119__amfs_cache_miss_slice1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext119 :: RENDER CACHE HIT L3NODE1 */
#define mtlgt3__ext119__render_cache_hit_l3_node1__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext119 :: RENDER CACHE READ L3NODE1 */
#define mtlgt3__ext119__render_cache_read_l3_node1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext119 :: RENDER CACHE WRITE L3NODE1 */
#define mtlgt3__ext119__render_cache_write_l3_node1__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext119 :: RENDER CACHE INPUT AVAILABLE _L3NODE1 */
#define mtlgt3__ext119__render_cache_input_available_l3_node1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext119 :: RENDER CACHE OUTPUT READY _L3NODE1 */
#define mtlgt3__ext119__render_cache_output_ready_l3_node1__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext120 :: GPU Time Elapsed */
#define mtlgt3__ext120__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext120 :: GPU Core Clocks */
#define mtlgt3__ext120__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext120 :: AVG GPU Core Frequency */
#define mtlgt3__ext120__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext120 :: AVG GPU Core Frequency */
#define mtlgt3__ext120__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE0 */
#define mtlgt3__ext120__pixel_post_process_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE1 */
#define mtlgt3__ext120__pixel_post_process_input_available_xecore1__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE2 */
#define mtlgt3__ext120__pixel_post_process_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext120 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE3 */
#define mtlgt3__ext120__pixel_post_process_input_available_xecore3__read \
   bdw__render_basic__sampler1_busy__read

/* Ext121 :: GPU Time Elapsed */
#define mtlgt3__ext121__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext121 :: GPU Core Clocks */
#define mtlgt3__ext121__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext121 :: AVG GPU Core Frequency */
#define mtlgt3__ext121__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext121 :: AVG GPU Core Frequency */
#define mtlgt3__ext121__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext121 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE4 */
#define mtlgt3__ext121__pixel_post_process_input_available_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext121 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE5 */
#define mtlgt3__ext121__pixel_post_process_input_available_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext121 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE6 */
#define mtlgt3__ext121__pixel_post_process_input_available_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext121 :: PIXEL POST PROCESS INPUT AVAILABLE XECORE7 */
#define mtlgt3__ext121__pixel_post_process_input_available_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext122 :: GPU Time Elapsed */
#define mtlgt3__ext122__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext122 :: GPU Core Clocks */
#define mtlgt3__ext122__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext122 :: AVG GPU Core Frequency */
#define mtlgt3__ext122__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext122 :: AVG GPU Core Frequency */
#define mtlgt3__ext122__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext122 :: AMFS 4X4 SHADING REQUEST SLICE0 */
#define mtlgt3__ext122__amfs_4_x4_shading_request_slice0__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE0 */
#define mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE1 */
#define mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe1__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE0 */
#define mtlgt3__ext122__pixel_post_process_output_ready_cpipe0__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE1 */
#define mtlgt3__ext122__pixel_post_process_output_ready_cpipe1__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext122 :: AMFS 4X4 SHADING REQUEST SLICE1 */
#define mtlgt3__ext122__amfs_4_x4_shading_request_slice1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE2 */
#define mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe2__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext122 :: COLOR PIPE CACHE LATENCY1 STALL CPIPE3 */
#define mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe3__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE2 */
#define mtlgt3__ext122__pixel_post_process_output_ready_cpipe2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext122 :: PIXEL POST PROCESS OUTPUT READY CPIPE3 */
#define mtlgt3__ext122__pixel_post_process_output_ready_cpipe3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext123 :: GPU Time Elapsed */
#define mtlgt3__ext123__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext123 :: GPU Core Clocks */
#define mtlgt3__ext123__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext123 :: AVG GPU Core Frequency */
#define mtlgt3__ext123__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext123 :: AVG GPU Core Frequency */
#define mtlgt3__ext123__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext123 :: AMFS L3 ACCESS SLICE0 */
#define mtlgt3__ext123__amfs_l3_access_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext123 :: AMFS L3 ATOMIC SLICE0 */
#define mtlgt3__ext123__amfs_l3_atomic_slice0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext123 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0 */
#define mtlgt3__ext123__clipper_primitive_far_near_clip_slice0__read \
   mtlgt2__ext123__clipper_primitive_far_near_clip_slice0__read

/* Ext123 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE0 */
#define mtlgt3__ext123__color_pipe_cache_latency2_stall_l3_node0__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext123 :: PIXEL BACKEND INPUT AVAILABLE _L3NODE0 */
#define mtlgt3__ext123__pixel_backend_input_available_l3_node0__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext123 :: PIXEL BACKEND OUTPUT READY _L3NODE0 */
#define mtlgt3__ext123__pixel_backend_output_ready_l3_node0__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext123 :: AMFS L3 ACCESS SLICE1 */
#define mtlgt3__ext123__amfs_l3_access_slice1__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext123 :: AMFS L3 ATOMIC SLICE1 */
#define mtlgt3__ext123__amfs_l3_atomic_slice1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext123 :: CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1 */
#define mtlgt3__ext123__clipper_primitive_far_near_clip_slice1__read \
   mtlgt3__ext3__gpu_memory_32_b_transaction_read__read

/* Ext123 :: COLOR PIPE CACHE LATENCY2 STALL L3NODE1 */
#define mtlgt3__ext123__color_pipe_cache_latency2_stall_l3_node1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext123 :: PIXEL BACKEND INPUT AVAILABLE _L3NODE1 */
#define mtlgt3__ext123__pixel_backend_input_available_l3_node1__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext123 :: PIXEL BACKEND OUTPUT READY _L3NODE1 */
#define mtlgt3__ext123__pixel_backend_output_ready_l3_node1__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext124 :: GPU Time Elapsed */
#define mtlgt3__ext124__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext124 :: GPU Core Clocks */
#define mtlgt3__ext124__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext124 :: AVG GPU Core Frequency */
#define mtlgt3__ext124__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext124 :: AVG GPU Core Frequency */
#define mtlgt3__ext124__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext124 :: VERTEX FETCH INPUT AVAILABLE SLICE0 */
#define mtlgt3__ext124__vertex_fetch_input_available_slice0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext124 :: VERTEX FETCH OUTPUT READY SLICE0 */
#define mtlgt3__ext124__vertex_fetch_output_ready_slice0__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext124 :: CLIPPER INPUT VERTEX SLICE0 */
#define mtlgt3__ext124__clipper_input_vertex_slice0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext124 :: STREAMOUT OUTPUT VERTEX COUNT SLICE0 */
#define mtlgt3__ext124__streamout_output_vertex_count_slice0__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext124 :: VS OUTPUT READY SLICE0 */
#define mtlgt3__ext124__vs_output_ready_slice0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext124 :: CLIPPER INPUT AVAILABLE SLICE0 */
#define mtlgt3__ext124__clipper_input_available_slice0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext124 :: CLIPPER OUTPUT READY SLICE0 */
#define mtlgt3__ext124__clipper_output_ready_slice0__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext124 :: CLIPPER PRIMITIVE OUTPUT SLICE0 */
#define mtlgt3__ext124__clipper_primitive_output_slice0__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext124 :: STRIPSFAN OUTPUT READY SLICE0 */
#define mtlgt3__ext124__stripsfan_output_ready_slice0__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext124 :: PS OUTPUT AVAILABLE CPIPE0 */
#define mtlgt3__ext124__ps_output_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext124 :: PS OUTPUT AVAILABLE CPIPE1 */
#define mtlgt3__ext124__ps_output_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext125 :: GPU Time Elapsed */
#define mtlgt3__ext125__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext125 :: GPU Core Clocks */
#define mtlgt3__ext125__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext125 :: AVG GPU Core Frequency */
#define mtlgt3__ext125__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext125 :: AVG GPU Core Frequency */
#define mtlgt3__ext125__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext125 :: VERTEX FETCH INPUT AVAILABLE SLICE1 */
#define mtlgt3__ext125__vertex_fetch_input_available_slice1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext125 :: VERTEX FETCH OUTPUT READY SLICE1 */
#define mtlgt3__ext125__vertex_fetch_output_ready_slice1__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext125 :: CLIPPER INPUT VERTEX SLICE1 */
#define mtlgt3__ext125__clipper_input_vertex_slice1__read \
   mtlgt2__ext123__clipper_primitive_far_near_clip_slice0__read

/* Ext125 :: STREAMOUT OUTPUT VERTEX COUNT SLICE1 */
#define mtlgt3__ext125__streamout_output_vertex_count_slice1__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext125 :: VS OUTPUT READY SLICE1 */
#define mtlgt3__ext125__vs_output_ready_slice1__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext125 :: CLIPPER INPUT AVAILABLE SLICE1 */
#define mtlgt3__ext125__clipper_input_available_slice1__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext125 :: CLIPPER OUTPUT READY SLICE1 */
#define mtlgt3__ext125__clipper_output_ready_slice1__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext125 :: CLIPPER PRIMITIVE OUTPUT SLICE1 */
#define mtlgt3__ext125__clipper_primitive_output_slice1__read \
   hsw__compute_extended__typed_writes0__read

/* Ext125 :: STRIPSFAN OUTPUT READY SLICE1 */
#define mtlgt3__ext125__stripsfan_output_ready_slice1__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext125 :: PS OUTPUT AVAILABLE CPIPE2 */
#define mtlgt3__ext125__ps_output_available_cpipe2__read \
   bdw__render_basic__sampler0_busy__read

/* Ext125 :: PS OUTPUT AVAILABLE CPIPE3 */
#define mtlgt3__ext125__ps_output_available_cpipe3__read \
   bdw__render_basic__sampler1_busy__read

/* Ext126 :: GPU Time Elapsed */
#define mtlgt3__ext126__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext126 :: GPU Core Clocks */
#define mtlgt3__ext126__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext126 :: AVG GPU Core Frequency */
#define mtlgt3__ext126__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext126 :: AVG GPU Core Frequency */
#define mtlgt3__ext126__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext126 :: STRIPSFAN OBJECT COUNT SLICE0 */
#define mtlgt3__ext126__stripsfan_object_count_slice0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext126 :: STRIPSFAN OBJECTS CULL SLICE0 */
#define mtlgt3__ext126__stripsfan_objects_cull_slice0__read \
   mtlgt2__ext123__clipper_primitive_far_near_clip_slice0__read

/* Ext126 :: CLIPPER TRANSACTION OUTPUT SLICE0 */
#define mtlgt3__ext126__clipper_transaction_output_slice0__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext126 :: CLIPPER PRIMITIVE CULL SLICE0 */
#define mtlgt3__ext126__clipper_primitive_cull_slice0__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext126 :: RASTERIZER INPUT AVAILABLE SLICE0 */
#define mtlgt3__ext126__rasterizer_input_available_slice0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext126 :: RASTERIZER OUTPUT READY SLICE0 */
#define mtlgt3__ext126__rasterizer_output_ready_slice0__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext126 :: RASTERIZER TRANSACTION OUTPUT SLICE0 */
#define mtlgt3__ext126__rasterizer_transaction_output_slice0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext127 :: GPU Time Elapsed */
#define mtlgt3__ext127__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext127 :: GPU Core Clocks */
#define mtlgt3__ext127__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext127 :: AVG GPU Core Frequency */
#define mtlgt3__ext127__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext127 :: AVG GPU Core Frequency */
#define mtlgt3__ext127__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext127 :: STRIPSFAN OBJECT COUNT SLICE1 */
#define mtlgt3__ext127__stripsfan_object_count_slice1__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext127 :: STRIPSFAN OBJECTS CULL SLICE1 */
#define mtlgt3__ext127__stripsfan_objects_cull_slice1__read \
   mtlgt2__ext123__clipper_primitive_far_near_clip_slice0__read

/* Ext127 :: CLIPPER TRANSACTION OUTPUT SLICE1 */
#define mtlgt3__ext127__clipper_transaction_output_slice1__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext127 :: RASTERIZER TRANSACTION OUTPUT SLICE1 */
#define mtlgt3__ext127__rasterizer_transaction_output_slice1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext127 :: CLIPPER PRIMITIVE CULL SLICE1 */
#define mtlgt3__ext127__clipper_primitive_cull_slice1__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext127 :: RASTERIZER INPUT AVAILABLE SLICE1 */
#define mtlgt3__ext127__rasterizer_input_available_slice1__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext127 :: RASTERIZER OUTPUT READY SLICE1 */
#define mtlgt3__ext127__rasterizer_output_ready_slice1__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext128 :: GPU Time Elapsed */
#define mtlgt3__ext128__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext128 :: GPU Core Clocks */
#define mtlgt3__ext128__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext128 :: AVG GPU Core Frequency */
#define mtlgt3__ext128__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext128 :: AVG GPU Core Frequency */
#define mtlgt3__ext128__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext128 :: URB READ SLICE0 */
static uint64_t
mtlgt3__ext128__urb_read_slice0__read(UNUSED struct intel_perf_config *perf,
                                      const struct intel_perf_query_info *query,
                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ B 1 READ UADD B 2 READ UADD B 3 READ UADD B 4 READ UADD B 5 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->b_offset + 2];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 3];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 4];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->b_offset + 5];
   uint64_t tmp10 = tmp8 + tmp9;

   return tmp10;
}

/* Ext128 :: URB WRITE SLICE0 */
static uint64_t
mtlgt3__ext128__urb_write_slice0__read(UNUSED struct intel_perf_config *perf,
                                       const struct intel_perf_query_info *query,
                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: B 6 READ B 7 READ UADD C 0 READ UADD C 1 READ UADD C 2 READ UADD C 3 READ UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 6];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 0];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 1];
   uint64_t tmp6 = tmp4 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 2];
   uint64_t tmp8 = tmp6 + tmp7;
   uint64_t tmp9 = results->accumulator[query->c_offset + 3];
   uint64_t tmp10 = tmp8 + tmp9;

   return tmp10;
}

/* Ext128 :: URB CROSS SLICE READ SLICE0 */
static uint64_t
mtlgt3__ext128__urb_cross_slice_read_slice0__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: C 4 READ C 5 READ UADD C 6 READ UADD C 7 READ UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 4];
   uint64_t tmp1 = results->accumulator[query->c_offset + 5];
   uint64_t tmp2 = tmp0 + tmp1;
   uint64_t tmp3 = results->accumulator[query->c_offset + 6];
   uint64_t tmp4 = tmp2 + tmp3;
   uint64_t tmp5 = results->accumulator[query->c_offset + 7];
   uint64_t tmp6 = tmp4 + tmp5;

   return tmp6;
}

/* Ext129 :: GPU Time Elapsed */
#define mtlgt3__ext129__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext129 :: GPU Core Clocks */
#define mtlgt3__ext129__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext129 :: AVG GPU Core Frequency */
#define mtlgt3__ext129__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext129 :: AVG GPU Core Frequency */
#define mtlgt3__ext129__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext129 :: URB READ SLICE1 */
#define mtlgt3__ext129__urb_read_slice1__read \
   acmgt1__ext128__urb_read_slice0__read

/* Ext129 :: URB WRITE SLICE1 */
#define mtlgt3__ext129__urb_write_slice1__read \
   acmgt1__ext128__urb_write_slice0__read

/* Ext129 :: URB CROSS SLICE READ SLICE1 */
#define mtlgt3__ext129__urb_cross_slice_read_slice1__read \
   acmgt1__threads_and_rast1__ds_threads__read

/* Ext130 :: GPU Time Elapsed */
#define mtlgt3__ext130__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext130 :: GPU Core Clocks */
#define mtlgt3__ext130__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext130 :: AVG GPU Core Frequency */
#define mtlgt3__ext130__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext130 :: AVG GPU Core Frequency */
#define mtlgt3__ext130__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext130 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0 */
static uint64_t
mtlgt3__ext130__early_depth_stencil_test_fail_np_zpipe0__read(UNUSED struct intel_perf_config *perf,
                                                              const struct intel_perf_query_info *query,
                                                              const struct intel_perf_query_result *results)
{
   /* RPN equation: C 3 READ 2 C 4 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 6 READ UMUL UADD 16 C 7 READ UMUL UADD B 0 READ 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD 16 B 4 READ UMUL UADD USUB */
   uint64_t tmp0 = results->accumulator[query->c_offset + 3];
   uint64_t tmp1 = results->accumulator[query->c_offset + 4];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 6];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 7];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 0];
   uint64_t tmp14 = results->accumulator[query->b_offset + 1];
   uint64_t tmp15 = 2 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->b_offset + 2];
   uint64_t tmp18 = 4 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = results->accumulator[query->b_offset + 3];
   uint64_t tmp21 = 8 * tmp20;
   uint64_t tmp22 = tmp19 + tmp21;
   uint64_t tmp23 = results->accumulator[query->b_offset + 4];
   uint64_t tmp24 = 16 * tmp23;
   uint64_t tmp25 = tmp22 + tmp24;
   uint64_t tmp26 = tmp12 - tmp25;

   return tmp26;
}

/* Ext130 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE0 */
#define mtlgt3__ext130__early_depth_stencil_test_fail_p_zpipe0__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext131 :: GPU Time Elapsed */
#define mtlgt3__ext131__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext131 :: GPU Core Clocks */
#define mtlgt3__ext131__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext131 :: AVG GPU Core Frequency */
#define mtlgt3__ext131__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext131 :: AVG GPU Core Frequency */
#define mtlgt3__ext131__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext131 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1 */
#define mtlgt3__ext131__early_depth_stencil_test_fail_np_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext131 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE1 */
#define mtlgt3__ext131__early_depth_stencil_test_fail_p_zpipe1__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext132 :: GPU Time Elapsed */
#define mtlgt3__ext132__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext132 :: GPU Core Clocks */
#define mtlgt3__ext132__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext132 :: AVG GPU Core Frequency */
#define mtlgt3__ext132__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext132 :: AVG GPU Core Frequency */
#define mtlgt3__ext132__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext132 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2 */
#define mtlgt3__ext132__early_depth_stencil_test_fail_np_zpipe2__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext132 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE2 */
#define mtlgt3__ext132__early_depth_stencil_test_fail_p_zpipe2__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext133 :: GPU Time Elapsed */
#define mtlgt3__ext133__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext133 :: GPU Core Clocks */
#define mtlgt3__ext133__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext133 :: AVG GPU Core Frequency */
#define mtlgt3__ext133__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext133 :: AVG GPU Core Frequency */
#define mtlgt3__ext133__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext133 :: EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3 */
#define mtlgt3__ext133__early_depth_stencil_test_fail_np_zpipe3__read \
   acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read

/* Ext133 :: EARLY DEPTH STENCIL TEST FAIL P ZPIPE3 */
#define mtlgt3__ext133__early_depth_stencil_test_fail_p_zpipe3__read \
   acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read

/* Ext134 :: GPU Time Elapsed */
#define mtlgt3__ext134__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext134 :: GPU Core Clocks */
#define mtlgt3__ext134__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext134 :: AVG GPU Core Frequency */
#define mtlgt3__ext134__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext134 :: AVG GPU Core Frequency */
#define mtlgt3__ext134__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext134 :: HIZ DEPTH TEST AMBIG NP ZPIPE0 */
static uint64_t
mtlgt3__ext134__hiz_depth_test_ambig_np_zpipe0__read(UNUSED struct intel_perf_config *perf,
                                                     const struct intel_perf_query_info *query,
                                                     const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 C 6 READ UMUL UADD 4 C 5 READ UMUL UADD 8 C 4 READ UMUL UADD 16 C 3 READ UMUL UADD 32 C 2 READ UMUL UADD 64 C 1 READ UMUL UADD 128 C 0 READ UMUL UADD 256 B 5 READ UMUL UADD 512 B 6 READ UMUL UADD 1024 B 7 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->c_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 5];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 3];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 2];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 1];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->c_offset + 0];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;
   uint64_t tmp22 = results->accumulator[query->b_offset + 5];
   uint64_t tmp23 = 256 * tmp22;
   uint64_t tmp24 = tmp21 + tmp23;
   uint64_t tmp25 = results->accumulator[query->b_offset + 6];
   uint64_t tmp26 = 512 * tmp25;
   uint64_t tmp27 = tmp24 + tmp26;
   uint64_t tmp28 = results->accumulator[query->b_offset + 7];
   uint64_t tmp29 = 1024 * tmp28;
   uint64_t tmp30 = tmp27 + tmp29;

   return tmp30;
}

/* Ext135 :: GPU Time Elapsed */
#define mtlgt3__ext135__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext135 :: GPU Core Clocks */
#define mtlgt3__ext135__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext135 :: AVG GPU Core Frequency */
#define mtlgt3__ext135__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext135 :: AVG GPU Core Frequency */
#define mtlgt3__ext135__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext135 :: HIZ DEPTH TEST AMBIG NP ZPIPE1 */
#define mtlgt3__ext135__hiz_depth_test_ambig_np_zpipe1__read \
   mtlgt3__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext136 :: GPU Time Elapsed */
#define mtlgt3__ext136__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext136 :: GPU Core Clocks */
#define mtlgt3__ext136__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext136 :: AVG GPU Core Frequency */
#define mtlgt3__ext136__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext136 :: AVG GPU Core Frequency */
#define mtlgt3__ext136__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext136 :: HIZ DEPTH TEST AMBIG NP ZPIPE2 */
#define mtlgt3__ext136__hiz_depth_test_ambig_np_zpipe2__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext137 :: GPU Time Elapsed */
#define mtlgt3__ext137__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext137 :: GPU Core Clocks */
#define mtlgt3__ext137__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext137 :: AVG GPU Core Frequency */
#define mtlgt3__ext137__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext137 :: AVG GPU Core Frequency */
#define mtlgt3__ext137__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext137 :: HIZ DEPTH TEST AMBIG NP ZPIPE3 */
#define mtlgt3__ext137__hiz_depth_test_ambig_np_zpipe3__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext138 :: GPU Time Elapsed */
#define mtlgt3__ext138__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext138 :: GPU Core Clocks */
#define mtlgt3__ext138__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext138 :: AVG GPU Core Frequency */
#define mtlgt3__ext138__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext138 :: AVG GPU Core Frequency */
#define mtlgt3__ext138__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext138 :: HIZ DEPTH TEST AMBIG P ZPIPE0 */
static uint64_t
mtlgt3__ext138__hiz_depth_test_ambig_p_zpipe0__read(UNUSED struct intel_perf_config *perf,
                                                    const struct intel_perf_query_info *query,
                                                    const struct intel_perf_query_result *results)
{
   /* RPN equation: B 5 READ 2 B 6 READ UMUL UADD 4 B 7 READ UMUL UADD 8 C 0 READ UMUL UADD 16 C 1 READ UMUL UADD 32 C 2 READ UMUL UADD 64 C 3 READ UMUL UADD 128 C 4 READ UMUL UADD 256 C 5 READ UMUL UADD 512 C 6 READ UMUL UADD 1024 C 7 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 5];
   uint64_t tmp1 = results->accumulator[query->b_offset + 6];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 7];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 0];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 1];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 2];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 3];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->c_offset + 4];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;
   uint64_t tmp22 = results->accumulator[query->c_offset + 5];
   uint64_t tmp23 = 256 * tmp22;
   uint64_t tmp24 = tmp21 + tmp23;
   uint64_t tmp25 = results->accumulator[query->c_offset + 6];
   uint64_t tmp26 = 512 * tmp25;
   uint64_t tmp27 = tmp24 + tmp26;
   uint64_t tmp28 = results->accumulator[query->c_offset + 7];
   uint64_t tmp29 = 1024 * tmp28;
   uint64_t tmp30 = tmp27 + tmp29;

   return tmp30;
}

/* Ext139 :: GPU Time Elapsed */
#define mtlgt3__ext139__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext139 :: GPU Core Clocks */
#define mtlgt3__ext139__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext139 :: AVG GPU Core Frequency */
#define mtlgt3__ext139__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext139 :: AVG GPU Core Frequency */
#define mtlgt3__ext139__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext139 :: HIZ DEPTH TEST AMBIG P ZPIPE1 */
#define mtlgt3__ext139__hiz_depth_test_ambig_p_zpipe1__read \
   mtlgt3__ext138__hiz_depth_test_ambig_p_zpipe0__read

/* Ext140 :: GPU Time Elapsed */
#define mtlgt3__ext140__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext140 :: GPU Core Clocks */
#define mtlgt3__ext140__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext140 :: AVG GPU Core Frequency */
#define mtlgt3__ext140__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext140 :: AVG GPU Core Frequency */
#define mtlgt3__ext140__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext140 :: HIZ DEPTH TEST AMBIG P ZPIPE2 */
#define mtlgt3__ext140__hiz_depth_test_ambig_p_zpipe2__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext141 :: GPU Time Elapsed */
#define mtlgt3__ext141__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext141 :: GPU Core Clocks */
#define mtlgt3__ext141__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext141 :: AVG GPU Core Frequency */
#define mtlgt3__ext141__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext141 :: AVG GPU Core Frequency */
#define mtlgt3__ext141__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext141 :: HIZ DEPTH TEST AMBIG P ZPIPE3 */
#define mtlgt3__ext141__hiz_depth_test_ambig_p_zpipe3__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext142 :: GPU Time Elapsed */
#define mtlgt3__ext142__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext142 :: GPU Core Clocks */
#define mtlgt3__ext142__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext142 :: AVG GPU Core Frequency */
#define mtlgt3__ext142__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext142 :: AVG GPU Core Frequency */
#define mtlgt3__ext142__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext142 :: HIZ DEPTH TEST FAIL NP ZPIPE0 */
#define mtlgt3__ext142__hiz_depth_test_fail_np_zpipe0__read \
   mtlgt3__ext138__hiz_depth_test_ambig_p_zpipe0__read

/* Ext143 :: GPU Time Elapsed */
#define mtlgt3__ext143__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext143 :: GPU Core Clocks */
#define mtlgt3__ext143__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext143 :: AVG GPU Core Frequency */
#define mtlgt3__ext143__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext143 :: AVG GPU Core Frequency */
#define mtlgt3__ext143__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext143 :: HIZ DEPTH TEST FAIL NP ZPIPE1 */
#define mtlgt3__ext143__hiz_depth_test_fail_np_zpipe1__read \
   mtlgt3__ext138__hiz_depth_test_ambig_p_zpipe0__read

/* Ext144 :: GPU Time Elapsed */
#define mtlgt3__ext144__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext144 :: GPU Core Clocks */
#define mtlgt3__ext144__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext144 :: AVG GPU Core Frequency */
#define mtlgt3__ext144__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext144 :: AVG GPU Core Frequency */
#define mtlgt3__ext144__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext144 :: HIZ DEPTH TEST FAIL NP ZPIPE2 */
#define mtlgt3__ext144__hiz_depth_test_fail_np_zpipe2__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext145 :: GPU Time Elapsed */
#define mtlgt3__ext145__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext145 :: GPU Core Clocks */
#define mtlgt3__ext145__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext145 :: AVG GPU Core Frequency */
#define mtlgt3__ext145__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext145 :: AVG GPU Core Frequency */
#define mtlgt3__ext145__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext145 :: HIZ DEPTH TEST FAIL NP ZPIPE3 */
#define mtlgt3__ext145__hiz_depth_test_fail_np_zpipe3__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext146 :: GPU Time Elapsed */
#define mtlgt3__ext146__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext146 :: GPU Core Clocks */
#define mtlgt3__ext146__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext146 :: AVG GPU Core Frequency */
#define mtlgt3__ext146__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext146 :: AVG GPU Core Frequency */
#define mtlgt3__ext146__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext146 :: HIZ DEPTH TEST FAIL P ZPIPE0 */
#define mtlgt3__ext146__hiz_depth_test_fail_p_zpipe0__read \
   mtlgt3__ext138__hiz_depth_test_ambig_p_zpipe0__read

/* Ext147 :: GPU Time Elapsed */
#define mtlgt3__ext147__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext147 :: GPU Core Clocks */
#define mtlgt3__ext147__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext147 :: AVG GPU Core Frequency */
#define mtlgt3__ext147__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext147 :: AVG GPU Core Frequency */
#define mtlgt3__ext147__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext147 :: HIZ DEPTH TEST FAIL P ZPIPE1 */
#define mtlgt3__ext147__hiz_depth_test_fail_p_zpipe1__read \
   mtlgt3__ext138__hiz_depth_test_ambig_p_zpipe0__read

/* Ext148 :: GPU Time Elapsed */
#define mtlgt3__ext148__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext148 :: GPU Core Clocks */
#define mtlgt3__ext148__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext148 :: AVG GPU Core Frequency */
#define mtlgt3__ext148__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext148 :: AVG GPU Core Frequency */
#define mtlgt3__ext148__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext148 :: HIZ DEPTH TEST FAIL P ZPIPE2 */
#define mtlgt3__ext148__hiz_depth_test_fail_p_zpipe2__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext149 :: GPU Time Elapsed */
#define mtlgt3__ext149__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext149 :: GPU Core Clocks */
#define mtlgt3__ext149__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext149 :: AVG GPU Core Frequency */
#define mtlgt3__ext149__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext149 :: AVG GPU Core Frequency */
#define mtlgt3__ext149__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext149 :: HIZ DEPTH TEST FAIL P ZPIPE3 */
#define mtlgt3__ext149__hiz_depth_test_fail_p_zpipe3__read \
   mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read

/* Ext150 :: GPU Time Elapsed */
#define mtlgt3__ext150__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext150 :: GPU Core Clocks */
#define mtlgt3__ext150__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext150 :: AVG GPU Core Frequency */
#define mtlgt3__ext150__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext150 :: AVG GPU Core Frequency */
#define mtlgt3__ext150__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext150 :: HIZ DEPTH TEST PASS P ZPIPE0 */
#define mtlgt3__ext150__hiz_depth_test_pass_p_zpipe0__read \
   mtlgt2__ext150__hiz_depth_test_pass_p_zpipe0__read

/* Ext151 :: GPU Time Elapsed */
#define mtlgt3__ext151__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext151 :: GPU Core Clocks */
#define mtlgt3__ext151__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext151 :: AVG GPU Core Frequency */
#define mtlgt3__ext151__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext151 :: AVG GPU Core Frequency */
#define mtlgt3__ext151__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext151 :: HIZ DEPTH TEST PASS P ZPIPE1 */
#define mtlgt3__ext151__hiz_depth_test_pass_p_zpipe1__read \
   mtlgt2__ext150__hiz_depth_test_pass_p_zpipe0__read

/* Ext152 :: GPU Time Elapsed */
#define mtlgt3__ext152__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext152 :: GPU Core Clocks */
#define mtlgt3__ext152__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext152 :: AVG GPU Core Frequency */
#define mtlgt3__ext152__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext152 :: AVG GPU Core Frequency */
#define mtlgt3__ext152__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext152 :: HIZ DEPTH TEST PASS P ZPIPE2 */
#define mtlgt3__ext152__hiz_depth_test_pass_p_zpipe2__read \
   mtlgt2__ext150__hiz_depth_test_pass_p_zpipe0__read

/* Ext153 :: GPU Time Elapsed */
#define mtlgt3__ext153__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext153 :: GPU Core Clocks */
#define mtlgt3__ext153__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext153 :: AVG GPU Core Frequency */
#define mtlgt3__ext153__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext153 :: AVG GPU Core Frequency */
#define mtlgt3__ext153__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext153 :: HIZ DEPTH TEST PASS P ZPIPE3 */
#define mtlgt3__ext153__hiz_depth_test_pass_p_zpipe3__read \
   mtlgt2__ext150__hiz_depth_test_pass_p_zpipe0__read

/* Ext154 :: GPU Time Elapsed */
#define mtlgt3__ext154__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext154 :: GPU Core Clocks */
#define mtlgt3__ext154__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext154 :: AVG GPU Core Frequency */
#define mtlgt3__ext154__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext154 :: AVG GPU Core Frequency */
#define mtlgt3__ext154__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE0 */
#define mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe0__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE1 */
#define mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe1__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext154 :: IZ OUTPUT READY ZPIPE0 */
#define mtlgt3__ext154__iz_output_ready_zpipe0__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext154 :: IZ OUTPUT READY ZPIPE1 */
#define mtlgt3__ext154__iz_output_ready_zpipe1__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2 */
#define mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe2__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext154 :: HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3 */
#define mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe3__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE2 */
#define mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe2__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext154 :: IZ SUBSPAN LATENCY FIFOFULL ZPIPE3 */
#define mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe3__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext154 :: IZ OUTPUT READY ZPIPE2 */
#define mtlgt3__ext154__iz_output_ready_zpipe2__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext154 :: IZ OUTPUT READY ZPIPE3 */
#define mtlgt3__ext154__iz_output_ready_zpipe3__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext155 :: GPU Time Elapsed */
#define mtlgt3__ext155__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext155 :: GPU Core Clocks */
#define mtlgt3__ext155__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext155 :: AVG GPU Core Frequency */
#define mtlgt3__ext155__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext155 :: AVG GPU Core Frequency */
#define mtlgt3__ext155__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext155 :: COMMAND PARSER COMPUTE ENGINE BUSY CCS0 */
#define mtlgt3__ext155__command_parser_compute_engine_busy_ccs0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext155 :: COMMAND PARSER RENDER ENGINE BUSY */
#define mtlgt3__ext155__command_parser_render_engine_busy__read \
   bdw__render_basic__sampler1_busy__read

/* Ext155 :: COMMAND PARSER COPY ENGINE BUSY */
#define mtlgt3__ext155__command_parser_copy_engine_busy__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext156 :: GPU Time Elapsed */
#define mtlgt3__ext156__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext156 :: GPU Core Clocks */
#define mtlgt3__ext156__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext156 :: AVG GPU Core Frequency */
#define mtlgt3__ext156__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext156 :: AVG GPU Core Frequency */
#define mtlgt3__ext156__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext156 :: COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0 */
#define mtlgt3__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext156 :: COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT */
#define mtlgt3__ext156__command_parser_render_engine_dispatch_kernel_count__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext156 :: COMMAND PARSER RENDER ENGINE DRAW COUNT */
#define mtlgt3__ext156__command_parser_render_engine_draw_count__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext156 :: COMMAND PARSER FLUSH COUNT */
#define mtlgt3__ext156__command_parser_flush_count__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext158 :: GPU Time Elapsed */
#define mtlgt3__ext158__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext158 :: GPU Core Clocks */
#define mtlgt3__ext158__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext158 :: AVG GPU Core Frequency */
#define mtlgt3__ext158__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext158 :: AVG GPU Core Frequency */
#define mtlgt3__ext158__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE0 */
#define mtlgt3__ext158__rt_input_message_ray_count_xecore0__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE1 */
#define mtlgt3__ext158__rt_input_message_ray_count_xecore1__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE2 */
#define mtlgt3__ext158__rt_input_message_ray_count_xecore2__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE3 */
#define mtlgt3__ext158__rt_input_message_ray_count_xecore3__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE4 */
#define mtlgt3__ext158__rt_input_message_ray_count_xecore4__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore4__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE5 */
#define mtlgt3__ext158__rt_input_message_ray_count_xecore5__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore5__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE6 */
#define mtlgt3__ext158__rt_input_message_ray_count_xecore6__read \
   acmgt1__ext1__gpu_memory_read_sqidi1__read

/* Ext158 :: RT INPUT MESSAGE RAY COUNT XECORE7 */
#define mtlgt3__ext158__rt_input_message_ray_count_xecore7__read \
   acmgt1__ext27__load_store_cache_l3_read_xecore7__read

/* Ext159 :: GPU Time Elapsed */
#define mtlgt3__ext159__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext159 :: GPU Core Clocks */
#define mtlgt3__ext159__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext159 :: AVG GPU Core Frequency */
#define mtlgt3__ext159__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext159 :: AVG GPU Core Frequency */
#define mtlgt3__ext159__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE0 */
#define mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE1 */
#define mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE2 */
#define mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext159 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE3 */
#define mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext160 :: GPU Time Elapsed */
#define mtlgt3__ext160__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext160 :: GPU Core Clocks */
#define mtlgt3__ext160__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext160 :: AVG GPU Core Frequency */
#define mtlgt3__ext160__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext160 :: AVG GPU Core Frequency */
#define mtlgt3__ext160__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext160 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE4 */
#define mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext160 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE5 */
#define mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext160 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE6 */
#define mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext160 :: RT CLOSEST HIT THREAD RAY DISPATCH XECORE7 */
#define mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext161 :: GPU Time Elapsed */
#define mtlgt3__ext161__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext161 :: GPU Core Clocks */
#define mtlgt3__ext161__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext161 :: AVG GPU Core Frequency */
#define mtlgt3__ext161__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext161 :: AVG GPU Core Frequency */
#define mtlgt3__ext161__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE0 */
#define mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE1 */
#define mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE2 */
#define mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext161 :: RT MISS THREAD RAY DISPATCH XECORE3 */
#define mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext162 :: GPU Time Elapsed */
#define mtlgt3__ext162__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext162 :: GPU Core Clocks */
#define mtlgt3__ext162__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext162 :: AVG GPU Core Frequency */
#define mtlgt3__ext162__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext162 :: AVG GPU Core Frequency */
#define mtlgt3__ext162__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext162 :: RT MISS THREAD RAY DISPATCH XECORE4 */
#define mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext162 :: RT MISS THREAD RAY DISPATCH XECORE5 */
#define mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext162 :: RT MISS THREAD RAY DISPATCH XECORE6 */
#define mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext162 :: RT MISS THREAD RAY DISPATCH XECORE7 */
#define mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext163 :: GPU Time Elapsed */
#define mtlgt3__ext163__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext163 :: GPU Core Clocks */
#define mtlgt3__ext163__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext163 :: AVG GPU Core Frequency */
#define mtlgt3__ext163__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext163 :: AVG GPU Core Frequency */
#define mtlgt3__ext163__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE0 */
#define mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE1 */
#define mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE2 */
#define mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext163 :: RT ANY HIT THREAD RAY DISPATCH XECORE3 */
#define mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext164 :: GPU Time Elapsed */
#define mtlgt3__ext164__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext164 :: GPU Core Clocks */
#define mtlgt3__ext164__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext164 :: AVG GPU Core Frequency */
#define mtlgt3__ext164__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext164 :: AVG GPU Core Frequency */
#define mtlgt3__ext164__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext164 :: RT ANY HIT THREAD RAY DISPATCH XECORE4 */
#define mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext164 :: RT ANY HIT THREAD RAY DISPATCH XECORE5 */
#define mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext164 :: RT ANY HIT THREAD RAY DISPATCH XECORE6 */
#define mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext164 :: RT ANY HIT THREAD RAY DISPATCH XECORE7 */
#define mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext165 :: GPU Time Elapsed */
#define mtlgt3__ext165__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext165 :: GPU Core Clocks */
#define mtlgt3__ext165__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext165 :: AVG GPU Core Frequency */
#define mtlgt3__ext165__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext165 :: AVG GPU Core Frequency */
#define mtlgt3__ext165__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE0 */
#define mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE1 */
#define mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE2 */
#define mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext165 :: RT INTERSECTION THREAD RAY DISPATCH XECORE3 */
#define mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext166 :: GPU Time Elapsed */
#define mtlgt3__ext166__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext166 :: GPU Core Clocks */
#define mtlgt3__ext166__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext166 :: AVG GPU Core Frequency */
#define mtlgt3__ext166__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext166 :: AVG GPU Core Frequency */
#define mtlgt3__ext166__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext166 :: RT INTERSECTION THREAD RAY DISPATCH XECORE4 */
#define mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext166 :: RT INTERSECTION THREAD RAY DISPATCH XECORE5 */
#define mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext166 :: RT INTERSECTION THREAD RAY DISPATCH XECORE6 */
#define mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext166 :: RT INTERSECTION THREAD RAY DISPATCH XECORE7 */
#define mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext167 :: GPU Time Elapsed */
#define mtlgt3__ext167__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext167 :: GPU Core Clocks */
#define mtlgt3__ext167__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext167 :: AVG GPU Core Frequency */
#define mtlgt3__ext167__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext167 :: AVG GPU Core Frequency */
#define mtlgt3__ext167__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE0 */
#define mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE1 */
#define mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE2 */
#define mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext167 :: RT CALLABLE THREAD RAY DISPATCH XECORE3 */
#define mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext168 :: GPU Time Elapsed */
#define mtlgt3__ext168__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext168 :: GPU Core Clocks */
#define mtlgt3__ext168__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext168 :: AVG GPU Core Frequency */
#define mtlgt3__ext168__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext168 :: AVG GPU Core Frequency */
#define mtlgt3__ext168__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext168 :: RT CALLABLE THREAD RAY DISPATCH XECORE4 */
#define mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext168 :: RT CALLABLE THREAD RAY DISPATCH XECORE5 */
#define mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext168 :: RT CALLABLE THREAD RAY DISPATCH XECORE6 */
#define mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext168 :: RT CALLABLE THREAD RAY DISPATCH XECORE7 */
#define mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext169 :: GPU Time Elapsed */
#define mtlgt3__ext169__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext169 :: GPU Core Clocks */
#define mtlgt3__ext169__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext169 :: AVG GPU Core Frequency */
#define mtlgt3__ext169__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext169 :: AVG GPU Core Frequency */
#define mtlgt3__ext169__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE0 */
#define mtlgt3__ext169__rt_traversal_output_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE1 */
#define mtlgt3__ext169__rt_traversal_output_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE2 */
#define mtlgt3__ext169__rt_traversal_output_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext169 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE3 */
#define mtlgt3__ext169__rt_traversal_output_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext170 :: GPU Time Elapsed */
#define mtlgt3__ext170__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext170 :: GPU Core Clocks */
#define mtlgt3__ext170__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext170 :: AVG GPU Core Frequency */
#define mtlgt3__ext170__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext170 :: AVG GPU Core Frequency */
#define mtlgt3__ext170__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext170 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE4 */
#define mtlgt3__ext170__rt_traversal_output_ray_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext170 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE5 */
#define mtlgt3__ext170__rt_traversal_output_ray_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext170 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE6 */
#define mtlgt3__ext170__rt_traversal_output_ray_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext170 :: RT TRAVERSAL OUTPUT RAY COUNT XECORE7 */
#define mtlgt3__ext170__rt_traversal_output_ray_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext171 :: GPU Time Elapsed */
#define mtlgt3__ext171__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext171 :: GPU Core Clocks */
#define mtlgt3__ext171__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext171 :: AVG GPU Core Frequency */
#define mtlgt3__ext171__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext171 :: AVG GPU Core Frequency */
#define mtlgt3__ext171__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE0 */
#define mtlgt3__ext171__rt_quad_test_ray_count_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE1 */
#define mtlgt3__ext171__rt_quad_test_ray_count_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE2 */
#define mtlgt3__ext171__rt_quad_test_ray_count_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext171 :: RT QUAD TEST RAY COUNT XECORE3 */
#define mtlgt3__ext171__rt_quad_test_ray_count_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE0 */
#define mtlgt3__ext171__rt_transform_ray_count_xecore0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE1 */
#define mtlgt3__ext171__rt_transform_ray_count_xecore1__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE2 */
#define mtlgt3__ext171__rt_transform_ray_count_xecore2__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext171 :: RT TRANSFORM RAY COUNT XECORE3 */
#define mtlgt3__ext171__rt_transform_ray_count_xecore3__read \
   hsw__compute_extended__typed_writes0__read

/* Ext171 :: RT REQUEST COLLISION XECORE0 */
#define mtlgt3__ext171__rt_request_collision_xecore0__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext171 :: RT REQUEST COLLISION XECORE1 */
#define mtlgt3__ext171__rt_request_collision_xecore1__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext171 :: RT REQUEST COLLISION XECORE2 */
#define mtlgt3__ext171__rt_request_collision_xecore2__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext171 :: RT REQUEST COLLISION XECORE3 */
#define mtlgt3__ext171__rt_request_collision_xecore3__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext171 :: RT MESSAGE STALL COUNT XECORE0 */
#define mtlgt3__ext171__rt_message_stall_count_xecore0__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext171 :: RT MESSAGE STALL COUNT XECORE1 */
#define mtlgt3__ext171__rt_message_stall_count_xecore1__read \
   bdw__render_basic__sampler0_busy__read

/* Ext171 :: RT MESSAGE STALL COUNT XECORE2 */
#define mtlgt3__ext171__rt_message_stall_count_xecore2__read \
   bdw__render_basic__sampler1_busy__read

/* Ext171 :: RT MESSAGE STALL COUNT XECORE3 */
#define mtlgt3__ext171__rt_message_stall_count_xecore3__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext172 :: GPU Time Elapsed */
#define mtlgt3__ext172__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext172 :: GPU Core Clocks */
#define mtlgt3__ext172__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext172 :: AVG GPU Core Frequency */
#define mtlgt3__ext172__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext172 :: AVG GPU Core Frequency */
#define mtlgt3__ext172__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext172 :: RT QUAD TEST RAY COUNT XECORE4 */
#define mtlgt3__ext172__rt_quad_test_ray_count_xecore4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext172 :: RT QUAD TEST RAY COUNT XECORE5 */
#define mtlgt3__ext172__rt_quad_test_ray_count_xecore5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext172 :: RT QUAD TEST RAY COUNT XECORE6 */
#define mtlgt3__ext172__rt_quad_test_ray_count_xecore6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext172 :: RT QUAD TEST RAY COUNT XECORE7 */
#define mtlgt3__ext172__rt_quad_test_ray_count_xecore7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext172 :: RT TRANSFORM RAY COUNT XECORE4 */
#define mtlgt3__ext172__rt_transform_ray_count_xecore4__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext172 :: RT TRANSFORM RAY COUNT XECORE5 */
#define mtlgt3__ext172__rt_transform_ray_count_xecore5__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext172 :: RT TRANSFORM RAY COUNT XECORE6 */
#define mtlgt3__ext172__rt_transform_ray_count_xecore6__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext172 :: RT TRANSFORM RAY COUNT XECORE7 */
#define mtlgt3__ext172__rt_transform_ray_count_xecore7__read \
   hsw__compute_extended__typed_writes0__read

/* Ext172 :: RT REQUEST COLLISION XECORE4 */
#define mtlgt3__ext172__rt_request_collision_xecore4__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext172 :: RT REQUEST COLLISION XECORE5 */
#define mtlgt3__ext172__rt_request_collision_xecore5__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext172 :: RT REQUEST COLLISION XECORE6 */
#define mtlgt3__ext172__rt_request_collision_xecore6__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext172 :: RT REQUEST COLLISION XECORE7 */
#define mtlgt3__ext172__rt_request_collision_xecore7__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE4 */
#define mtlgt3__ext172__rt_message_stall_count_xecore4__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE5 */
#define mtlgt3__ext172__rt_message_stall_count_xecore5__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE6 */
#define mtlgt3__ext172__rt_message_stall_count_xecore6__read \
   bdw__render_basic__sampler1_busy__read

/* Ext172 :: RT MESSAGE STALL COUNT XECORE7 */
#define mtlgt3__ext172__rt_message_stall_count_xecore7__read \
   bdw__render_basic__sampler0_busy__read

/* Ext173 :: GPU Time Elapsed */
#define mtlgt3__ext173__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext173 :: GPU Core Clocks */
#define mtlgt3__ext173__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext173 :: AVG GPU Core Frequency */
#define mtlgt3__ext173__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext173 :: AVG GPU Core Frequency */
#define mtlgt3__ext173__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext173 :: XVE STALL ALUWR XECORE0 XVE0 THREAD0 */
#define mtlgt3__ext173__xve_stall_aluwr_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext173 :: XVE STALL BARRIER XECORE0 XVE0 THREAD0 */
#define mtlgt3__ext173__xve_stall_barrier_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext173 :: XVE STALL INSTFETCH XECORE0 XVE0 THREAD0 */
#define mtlgt3__ext173__xve_stall_instfetch_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext173 :: XVE STALL OTHER XECORE0 XVE0 THREAD0 */
#define mtlgt3__ext173__xve_stall_other_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext173 :: XVE STALL SBID XECORE0 XVE0 THREAD0 */
#define mtlgt3__ext173__xve_stall_sbid_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext173 :: XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0 */
#define mtlgt3__ext173__xve_shared_function_access_hold_xecore0_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext173 :: XVE STALL CONTROL XECORE0 XVE0 THREAD0 */
#define mtlgt3__ext173__xve_stall_control_xecore0_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext174 :: GPU Time Elapsed */
#define mtlgt3__ext174__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext174 :: GPU Core Clocks */
#define mtlgt3__ext174__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext174 :: AVG GPU Core Frequency */
#define mtlgt3__ext174__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext174 :: AVG GPU Core Frequency */
#define mtlgt3__ext174__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext174 :: XVE STALL ALUWR XECORE1 XVE0 THREAD0 */
#define mtlgt3__ext174__xve_stall_aluwr_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext174 :: XVE STALL BARRIER XECORE1 XVE0 THREAD0 */
#define mtlgt3__ext174__xve_stall_barrier_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext174 :: XVE STALL INSTFETCH XECORE1 XVE0 THREAD0 */
#define mtlgt3__ext174__xve_stall_instfetch_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext174 :: XVE STALL OTHER XECORE1 XVE0 THREAD0 */
#define mtlgt3__ext174__xve_stall_other_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext174 :: XVE STALL SBID XECORE1 XVE0 THREAD0 */
#define mtlgt3__ext174__xve_stall_sbid_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext174 :: XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0 */
#define mtlgt3__ext174__xve_shared_function_access_hold_xecore1_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext174 :: XVE STALL CONTROL XECORE1 XVE0 THREAD0 */
#define mtlgt3__ext174__xve_stall_control_xecore1_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext175 :: GPU Time Elapsed */
#define mtlgt3__ext175__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext175 :: GPU Core Clocks */
#define mtlgt3__ext175__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext175 :: AVG GPU Core Frequency */
#define mtlgt3__ext175__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext175 :: AVG GPU Core Frequency */
#define mtlgt3__ext175__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext175 :: XVE STALL ALUWR XECORE2 XVE0 THREAD0 */
#define mtlgt3__ext175__xve_stall_aluwr_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext175 :: XVE STALL BARRIER XECORE2 XVE0 THREAD0 */
#define mtlgt3__ext175__xve_stall_barrier_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext175 :: XVE STALL INSTFETCH XECORE2 XVE0 THREAD0 */
#define mtlgt3__ext175__xve_stall_instfetch_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext175 :: XVE STALL OTHER XECORE2 XVE0 THREAD0 */
#define mtlgt3__ext175__xve_stall_other_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext175 :: XVE STALL SBID XECORE2 XVE0 THREAD0 */
#define mtlgt3__ext175__xve_stall_sbid_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext175 :: XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0 */
#define mtlgt3__ext175__xve_shared_function_access_hold_xecore2_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext175 :: XVE STALL CONTROL XECORE2 XVE0 THREAD0 */
#define mtlgt3__ext175__xve_stall_control_xecore2_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext176 :: GPU Time Elapsed */
#define mtlgt3__ext176__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext176 :: GPU Core Clocks */
#define mtlgt3__ext176__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext176 :: AVG GPU Core Frequency */
#define mtlgt3__ext176__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext176 :: AVG GPU Core Frequency */
#define mtlgt3__ext176__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext176 :: XVE STALL ALUWR XECORE3 XVE0 THREAD0 */
#define mtlgt3__ext176__xve_stall_aluwr_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext176 :: XVE STALL BARRIER XECORE3 XVE0 THREAD0 */
#define mtlgt3__ext176__xve_stall_barrier_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext176 :: XVE STALL INSTFETCH XECORE3 XVE0 THREAD0 */
#define mtlgt3__ext176__xve_stall_instfetch_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext176 :: XVE STALL OTHER XECORE3 XVE0 THREAD0 */
#define mtlgt3__ext176__xve_stall_other_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext176 :: XVE STALL SBID XECORE3 XVE0 THREAD0 */
#define mtlgt3__ext176__xve_stall_sbid_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext176 :: XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0 */
#define mtlgt3__ext176__xve_shared_function_access_hold_xecore3_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext176 :: XVE STALL CONTROL XECORE3 XVE0 THREAD0 */
#define mtlgt3__ext176__xve_stall_control_xecore3_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext177 :: GPU Time Elapsed */
#define mtlgt3__ext177__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext177 :: GPU Core Clocks */
#define mtlgt3__ext177__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext177 :: AVG GPU Core Frequency */
#define mtlgt3__ext177__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext177 :: AVG GPU Core Frequency */
#define mtlgt3__ext177__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext177 :: XVE STALL ALUWR XECORE4 XVE0 THREAD0 */
#define mtlgt3__ext177__xve_stall_aluwr_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext177 :: XVE STALL BARRIER XECORE4 XVE0 THREAD0 */
#define mtlgt3__ext177__xve_stall_barrier_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext177 :: XVE STALL INSTFETCH XECORE4 XVE0 THREAD0 */
#define mtlgt3__ext177__xve_stall_instfetch_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext177 :: XVE STALL OTHER XECORE4 XVE0 THREAD0 */
#define mtlgt3__ext177__xve_stall_other_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext177 :: XVE STALL SBID XECORE4 XVE0 THREAD0 */
#define mtlgt3__ext177__xve_stall_sbid_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext177 :: XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0 */
#define mtlgt3__ext177__xve_shared_function_access_hold_xecore4_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext177 :: XVE STALL CONTROL XECORE4 XVE0 THREAD0 */
#define mtlgt3__ext177__xve_stall_control_xecore4_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext178 :: GPU Time Elapsed */
#define mtlgt3__ext178__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext178 :: GPU Core Clocks */
#define mtlgt3__ext178__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext178 :: AVG GPU Core Frequency */
#define mtlgt3__ext178__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext178 :: AVG GPU Core Frequency */
#define mtlgt3__ext178__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext178 :: XVE STALL ALUWR XECORE5 XVE0 THREAD0 */
#define mtlgt3__ext178__xve_stall_aluwr_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext178 :: XVE STALL BARRIER XECORE5 XVE0 THREAD0 */
#define mtlgt3__ext178__xve_stall_barrier_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext178 :: XVE STALL INSTFETCH XECORE5 XVE0 THREAD0 */
#define mtlgt3__ext178__xve_stall_instfetch_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext178 :: XVE STALL OTHER XECORE5 XVE0 THREAD0 */
#define mtlgt3__ext178__xve_stall_other_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext178 :: XVE STALL SBID XECORE5 XVE0 THREAD0 */
#define mtlgt3__ext178__xve_stall_sbid_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext178 :: XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0 */
#define mtlgt3__ext178__xve_shared_function_access_hold_xecore5_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext178 :: XVE STALL CONTROL XECORE5 XVE0 THREAD0 */
#define mtlgt3__ext178__xve_stall_control_xecore5_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext179 :: GPU Time Elapsed */
#define mtlgt3__ext179__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext179 :: GPU Core Clocks */
#define mtlgt3__ext179__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext179 :: AVG GPU Core Frequency */
#define mtlgt3__ext179__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext179 :: AVG GPU Core Frequency */
#define mtlgt3__ext179__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext179 :: XVE STALL ALUWR XECORE6 XVE0 THREAD0 */
#define mtlgt3__ext179__xve_stall_aluwr_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext179 :: XVE STALL BARRIER XECORE6 XVE0 THREAD0 */
#define mtlgt3__ext179__xve_stall_barrier_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext179 :: XVE STALL INSTFETCH XECORE6 XVE0 THREAD0 */
#define mtlgt3__ext179__xve_stall_instfetch_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext179 :: XVE STALL OTHER XECORE6 XVE0 THREAD0 */
#define mtlgt3__ext179__xve_stall_other_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext179 :: XVE STALL SBID XECORE6 XVE0 THREAD0 */
#define mtlgt3__ext179__xve_stall_sbid_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext179 :: XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0 */
#define mtlgt3__ext179__xve_shared_function_access_hold_xecore6_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext179 :: XVE STALL CONTROL XECORE6 XVE0 THREAD0 */
#define mtlgt3__ext179__xve_stall_control_xecore6_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext180 :: GPU Time Elapsed */
#define mtlgt3__ext180__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext180 :: GPU Core Clocks */
#define mtlgt3__ext180__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext180 :: AVG GPU Core Frequency */
#define mtlgt3__ext180__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext180 :: AVG GPU Core Frequency */
#define mtlgt3__ext180__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext180 :: XVE STALL ALUWR XECORE7 XVE0 THREAD0 */
#define mtlgt3__ext180__xve_stall_aluwr_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext180 :: XVE STALL BARRIER XECORE7 XVE0 THREAD0 */
#define mtlgt3__ext180__xve_stall_barrier_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext180 :: XVE STALL INSTFETCH XECORE7 XVE0 THREAD0 */
#define mtlgt3__ext180__xve_stall_instfetch_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext180 :: XVE STALL OTHER XECORE7 XVE0 THREAD0 */
#define mtlgt3__ext180__xve_stall_other_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler1_busy__read

/* Ext180 :: XVE STALL SBID XECORE7 XVE0 THREAD0 */
#define mtlgt3__ext180__xve_stall_sbid_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext180 :: XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0 */
#define mtlgt3__ext180__xve_shared_function_access_hold_xecore7_xve0_thread0__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext180 :: XVE STALL CONTROL XECORE7 XVE0 THREAD0 */
#define mtlgt3__ext180__xve_stall_control_xecore7_xve0_thread0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext181 :: GPU Time Elapsed */
#define mtlgt3__ext181__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext181 :: GPU Core Clocks */
#define mtlgt3__ext181__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext181 :: AVG GPU Core Frequency */
#define mtlgt3__ext181__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext181 :: AVG GPU Core Frequency */
#define mtlgt3__ext181__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext181 :: XVE INST ISSUED ALL XECORE0 XVE0 */
#define mtlgt3__ext181__xve_inst_issued_all_xecore0_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext181 :: XVE INST ISSUED ALL XECORE1 XVE0 */
#define mtlgt3__ext181__xve_inst_issued_all_xecore1_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext181 :: XVE INST ISSUED ALL XECORE2 XVE0 */
#define mtlgt3__ext181__xve_inst_issued_all_xecore2_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext182 :: GPU Time Elapsed */
#define mtlgt3__ext182__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext182 :: GPU Core Clocks */
#define mtlgt3__ext182__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext182 :: AVG GPU Core Frequency */
#define mtlgt3__ext182__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext182 :: AVG GPU Core Frequency */
#define mtlgt3__ext182__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext182 :: XVE INST ISSUED ALL XECORE4 XVE0 */
#define mtlgt3__ext182__xve_inst_issued_all_xecore4_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext182 :: XVE INST ISSUED ALL XECORE5 XVE0 */
#define mtlgt3__ext182__xve_inst_issued_all_xecore5_xve0__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext182 :: XVE INST ISSUED ALL XECORE6 XVE0 */
#define mtlgt3__ext182__xve_inst_issued_all_xecore6_xve0__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext183 :: GPU Time Elapsed */
#define mtlgt3__ext183__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext183 :: GPU Core Clocks */
#define mtlgt3__ext183__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext183 :: AVG GPU Core Frequency */
#define mtlgt3__ext183__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext183 :: AVG GPU Core Frequency */
#define mtlgt3__ext183__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext183 :: XVE STALL PIPESTALL XECORE0 XVE0 */
#define mtlgt3__ext183__xve_stall_pipestall_xecore0_xve0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext183 :: XVE STALL PIPESTALL XECORE1 XVE0 */
#define mtlgt3__ext183__xve_stall_pipestall_xecore1_xve0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext183 :: XVE STALL PIPESTALL XECORE2 XVE0 */
#define mtlgt3__ext183__xve_stall_pipestall_xecore2_xve0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext183 :: XVE STALL PIPESTALL XECORE3 XVE0 */
#define mtlgt3__ext183__xve_stall_pipestall_xecore3_xve0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext183 :: XVE INST ISSUED ALL XECORE3 XVE0 */
#define mtlgt3__ext183__xve_inst_issued_all_xecore3_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext183 :: RENDER CACHE ALLOC L3NODE0 */
#define mtlgt3__ext183__render_cache_alloc_l3_node0__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext184 :: GPU Time Elapsed */
#define mtlgt3__ext184__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext184 :: GPU Core Clocks */
#define mtlgt3__ext184__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext184 :: AVG GPU Core Frequency */
#define mtlgt3__ext184__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext184 :: AVG GPU Core Frequency */
#define mtlgt3__ext184__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext184 :: XVE STALL PIPESTALL XECORE4 XVE0 */
#define mtlgt3__ext184__xve_stall_pipestall_xecore4_xve0__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext184 :: XVE STALL PIPESTALL XECORE5 XVE0 */
#define mtlgt3__ext184__xve_stall_pipestall_xecore5_xve0__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext184 :: XVE STALL PIPESTALL XECORE6 XVE0 */
#define mtlgt3__ext184__xve_stall_pipestall_xecore6_xve0__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext184 :: XVE STALL PIPESTALL XECORE7 XVE0 */
#define mtlgt3__ext184__xve_stall_pipestall_xecore7_xve0__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext184 :: XVE INST ISSUED ALL XECORE7 XVE0 */
#define mtlgt3__ext184__xve_inst_issued_all_xecore7_xve0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext184 :: RENDER CACHE ALLOC L3NODE1 */
#define mtlgt3__ext184__render_cache_alloc_l3_node1__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext185 :: GPU Time Elapsed */
#define mtlgt3__ext185__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext185 :: GPU Core Clocks */
#define mtlgt3__ext185__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext185 :: AVG GPU Core Frequency */
#define mtlgt3__ext185__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext185 :: AVG GPU Core Frequency */
#define mtlgt3__ext185__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext185 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0 */
#define mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext185 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1 */
#define mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext185 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2 */
#define mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext185 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3 */
#define mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext186 :: GPU Time Elapsed */
#define mtlgt3__ext186__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext186 :: GPU Core Clocks */
#define mtlgt3__ext186__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext186 :: AVG GPU Core Frequency */
#define mtlgt3__ext186__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext186 :: AVG GPU Core Frequency */
#define mtlgt3__ext186__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext186 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4 */
#define mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext186 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5 */
#define mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext186 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6 */
#define mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext186 :: RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7 */
#define mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext188 :: GPU Time Elapsed */
#define mtlgt3__ext188__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext188 :: GPU Core Clocks */
#define mtlgt3__ext188__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext188 :: AVG GPU Core Frequency */
#define mtlgt3__ext188__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext188 :: AVG GPU Core Frequency */
#define mtlgt3__ext188__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0 */
#define mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1 */
#define mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2 */
#define mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore2__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext188 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3 */
#define mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore3__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext189 :: GPU Time Elapsed */
#define mtlgt3__ext189__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext189 :: GPU Core Clocks */
#define mtlgt3__ext189__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext189 :: AVG GPU Core Frequency */
#define mtlgt3__ext189__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext189 :: AVG GPU Core Frequency */
#define mtlgt3__ext189__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext189 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4 */
#define mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext189 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5 */
#define mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext189 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6 */
#define mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext189 :: RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7 */
#define mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext190 :: GPU Time Elapsed */
#define mtlgt3__ext190__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext190 :: GPU Core Clocks */
#define mtlgt3__ext190__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext190 :: AVG GPU Core Frequency */
#define mtlgt3__ext190__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext190 :: AVG GPU Core Frequency */
#define mtlgt3__ext190__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext190 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE0 */
#define mtlgt3__ext190__pixel_post_process_input_available_cpipe0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext190 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE1 */
#define mtlgt3__ext190__pixel_post_process_input_available_cpipe1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext191 :: GPU Time Elapsed */
#define mtlgt3__ext191__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext191 :: GPU Core Clocks */
#define mtlgt3__ext191__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext191 :: AVG GPU Core Frequency */
#define mtlgt3__ext191__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext191 :: AVG GPU Core Frequency */
#define mtlgt3__ext191__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext191 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE2 */
#define mtlgt3__ext191__pixel_post_process_input_available_cpipe2__read \
   bdw__render_basic__sampler0_busy__read

/* Ext191 :: PIXEL POST PROCESS INPUT AVAILABLE CPIPE3 */
#define mtlgt3__ext191__pixel_post_process_input_available_cpipe3__read \
   bdw__render_basic__sampler1_busy__read

/* Ext192 :: GPU Time Elapsed */
#define mtlgt3__ext192__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext192 :: GPU Core Clocks */
#define mtlgt3__ext192__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext192 :: AVG GPU Core Frequency */
#define mtlgt3__ext192__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext192 :: AVG GPU Core Frequency */
#define mtlgt3__ext192__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext192 :: RT INPUT AVAILABLE XECORE0 */
#define mtlgt3__ext192__rt_input_available_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext192 :: RT INPUT AVAILABLE XECORE1 */
#define mtlgt3__ext192__rt_input_available_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext192 :: RT INPUT AVAILABLE XECORE2 */
#define mtlgt3__ext192__rt_input_available_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext192 :: RT INPUT AVAILABLE XECORE3 */
#define mtlgt3__ext192__rt_input_available_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext192 :: RT TRAVERSAL STEP RAY COUNT XECORE0 */
#define mtlgt3__ext192__rt_traversal_step_ray_count_xecore0__read \
   mtlgt3__ext3__gpu_memory_64_b_transaction_write__read

/* Ext192 :: RT TRAVERSAL STEP RAY COUNT XECORE1 */
#define mtlgt3__ext192__rt_traversal_step_ray_count_xecore1__read \
   bdw__compute_l3_cache__l3_misses__read

/* Ext192 :: RT TRAVERSAL STEP RAY COUNT XECORE2 */
#define mtlgt3__ext192__rt_traversal_step_ray_count_xecore2__read \
   mtlgt3__ext3__gpu_memory_64_b_transaction_read__read

/* Ext192 :: RT TRAVERSAL STEP RAY COUNT XECORE3 */
#define mtlgt3__ext192__rt_traversal_step_ray_count_xecore3__read \
   mtlgt3__ext3__gpu_memory_32_b_transaction_read__read

/* Ext193 :: GPU Time Elapsed */
#define mtlgt3__ext193__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext193 :: GPU Core Clocks */
#define mtlgt3__ext193__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext193 :: AVG GPU Core Frequency */
#define mtlgt3__ext193__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext193 :: AVG GPU Core Frequency */
#define mtlgt3__ext193__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext193 :: RT INPUT AVAILABLE XECORE4 */
#define mtlgt3__ext193__rt_input_available_xecore4__read \
   bdw__render_basic__sampler0_busy__read

/* Ext193 :: RT INPUT AVAILABLE XECORE5 */
#define mtlgt3__ext193__rt_input_available_xecore5__read \
   bdw__render_basic__sampler1_busy__read

/* Ext193 :: RT INPUT AVAILABLE XECORE6 */
#define mtlgt3__ext193__rt_input_available_xecore6__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext193 :: RT INPUT AVAILABLE XECORE7 */
#define mtlgt3__ext193__rt_input_available_xecore7__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext193 :: RT TRAVERSAL STEP RAY COUNT XECORE4 */
#define mtlgt3__ext193__rt_traversal_step_ray_count_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext193 :: RT TRAVERSAL STEP RAY COUNT XECORE5 */
#define mtlgt3__ext193__rt_traversal_step_ray_count_xecore5__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext193 :: RT TRAVERSAL STEP RAY COUNT XECORE6 */
#define mtlgt3__ext193__rt_traversal_step_ray_count_xecore6__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext193 :: RT TRAVERSAL STEP RAY COUNT XECORE7 */
#define mtlgt3__ext193__rt_traversal_step_ray_count_xecore7__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext195 :: GPU Time Elapsed */
#define mtlgt3__ext195__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext195 :: GPU Core Clocks */
#define mtlgt3__ext195__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext195 :: AVG GPU Core Frequency */
#define mtlgt3__ext195__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext195 :: AVG GPU Core Frequency */
#define mtlgt3__ext195__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0 */
#define mtlgt3__ext195__xve_multiple_pipe_active_xecore0_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0 */
#define mtlgt3__ext195__xve_multiple_pipe_active_xecore1_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0 */
#define mtlgt3__ext195__xve_multiple_pipe_active_xecore2_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext195 :: XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0 */
#define mtlgt3__ext195__xve_multiple_pipe_active_xecore3_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext195 :: GPGPU DISPATCH XECORE0 */
#define mtlgt3__ext195__gpgpu_dispatch_xecore0__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext195 :: GPGPU DISPATCH XECORE1 */
#define mtlgt3__ext195__gpgpu_dispatch_xecore1__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext195 :: GPGPU DISPATCH XECORE2 */
#define mtlgt3__ext195__gpgpu_dispatch_xecore2__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext195 :: GPGPU DISPATCH XECORE3 */
#define mtlgt3__ext195__gpgpu_dispatch_xecore3__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext196 :: GPU Time Elapsed */
#define mtlgt3__ext196__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext196 :: GPU Core Clocks */
#define mtlgt3__ext196__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext196 :: AVG GPU Core Frequency */
#define mtlgt3__ext196__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext196 :: AVG GPU Core Frequency */
#define mtlgt3__ext196__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext196 :: XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0 */
#define mtlgt3__ext196__xve_multiple_pipe_active_xecore4_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read

/* Ext196 :: XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0 */
#define mtlgt3__ext196__xve_multiple_pipe_active_xecore5_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read

/* Ext196 :: XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0 */
#define mtlgt3__ext196__xve_multiple_pipe_active_xecore6_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read

/* Ext196 :: XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0 */
#define mtlgt3__ext196__xve_multiple_pipe_active_xecore7_xve0__read \
   acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read

/* Ext196 :: GPGPU DISPATCH XECORE4 */
#define mtlgt3__ext196__gpgpu_dispatch_xecore4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext196 :: GPGPU DISPATCH XECORE5 */
#define mtlgt3__ext196__gpgpu_dispatch_xecore5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext196 :: GPGPU DISPATCH XECORE6 */
#define mtlgt3__ext196__gpgpu_dispatch_xecore6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext196 :: GPGPU DISPATCH XECORE7 */
#define mtlgt3__ext196__gpgpu_dispatch_xecore7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext198 :: GPU Time Elapsed */
#define mtlgt3__ext198__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext198 :: GPU Core Clocks */
#define mtlgt3__ext198__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext198 :: AVG GPU Core Frequency */
#define mtlgt3__ext198__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext198 :: AVG GPU Core Frequency */
#define mtlgt3__ext198__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext198 :: SLM ACCESS COUNT BANK0 XECORE0 */
#define mtlgt3__ext198__slm_access_count_bank0_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext198 :: SLM ACCESS COUNT BANK0 XECORE1 */
#define mtlgt3__ext198__slm_access_count_bank0_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext198 :: SLM ACCESS COUNT BANK0 XECORE2 */
#define mtlgt3__ext198__slm_access_count_bank0_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext198 :: SLM ACCESS COUNT BANK0 XECORE3 */
#define mtlgt3__ext198__slm_access_count_bank0_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext199 :: GPU Time Elapsed */
#define mtlgt3__ext199__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext199 :: GPU Core Clocks */
#define mtlgt3__ext199__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext199 :: AVG GPU Core Frequency */
#define mtlgt3__ext199__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext199 :: AVG GPU Core Frequency */
#define mtlgt3__ext199__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext199 :: SLM ACCESS COUNT BANK1 XECORE0 */
#define mtlgt3__ext199__slm_access_count_bank1_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext199 :: SLM ACCESS COUNT BANK1 XECORE1 */
#define mtlgt3__ext199__slm_access_count_bank1_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext199 :: SLM ACCESS COUNT BANK1 XECORE2 */
#define mtlgt3__ext199__slm_access_count_bank1_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext199 :: SLM ACCESS COUNT BANK1 XECORE3 */
#define mtlgt3__ext199__slm_access_count_bank1_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext200 :: GPU Time Elapsed */
#define mtlgt3__ext200__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext200 :: GPU Core Clocks */
#define mtlgt3__ext200__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext200 :: AVG GPU Core Frequency */
#define mtlgt3__ext200__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext200 :: AVG GPU Core Frequency */
#define mtlgt3__ext200__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext200 :: SLM ACCESS COUNT BANK0 XECORE4 */
#define mtlgt3__ext200__slm_access_count_bank0_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext200 :: SLM ACCESS COUNT BANK0 XECORE5 */
#define mtlgt3__ext200__slm_access_count_bank0_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext200 :: SLM ACCESS COUNT BANK0 XECORE6 */
#define mtlgt3__ext200__slm_access_count_bank0_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext200 :: SLM ACCESS COUNT BANK0 XECORE7 */
#define mtlgt3__ext200__slm_access_count_bank0_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext201 :: GPU Time Elapsed */
#define mtlgt3__ext201__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext201 :: GPU Core Clocks */
#define mtlgt3__ext201__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext201 :: AVG GPU Core Frequency */
#define mtlgt3__ext201__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext201 :: AVG GPU Core Frequency */
#define mtlgt3__ext201__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext201 :: SLM ACCESS COUNT BANK1 XECORE4 */
#define mtlgt3__ext201__slm_access_count_bank1_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext201 :: SLM ACCESS COUNT BANK1 XECORE5 */
#define mtlgt3__ext201__slm_access_count_bank1_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext201 :: SLM ACCESS COUNT BANK1 XECORE6 */
#define mtlgt3__ext201__slm_access_count_bank1_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext201 :: SLM ACCESS COUNT BANK1 XECORE7 */
#define mtlgt3__ext201__slm_access_count_bank1_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext202 :: GPU Time Elapsed */
#define mtlgt3__ext202__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext202 :: GPU Core Clocks */
#define mtlgt3__ext202__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext202 :: AVG GPU Core Frequency */
#define mtlgt3__ext202__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext202 :: AVG GPU Core Frequency */
#define mtlgt3__ext202__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext202 :: GPU MEMORY L3 WRITE SQIDI0 */
#define mtlgt3__ext202__gpu_memory_l3_write_sqidi0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext203 :: GPU Time Elapsed */
#define mtlgt3__ext203__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext203 :: GPU Core Clocks */
#define mtlgt3__ext203__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext203 :: AVG GPU Core Frequency */
#define mtlgt3__ext203__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext203 :: AVG GPU Core Frequency */
#define mtlgt3__ext203__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext203 :: GPU MEMORY L3 WRITE SQIDI1 */
#define mtlgt3__ext203__gpu_memory_l3_write_sqidi1__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext204 :: GPU Time Elapsed */
#define mtlgt3__ext204__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext204 :: GPU Core Clocks */
#define mtlgt3__ext204__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext204 :: AVG GPU Core Frequency */
#define mtlgt3__ext204__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext204 :: AVG GPU Core Frequency */
#define mtlgt3__ext204__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext204 :: RT INTERNAL NODE RAY COUNT XECORE0 */
#define mtlgt3__ext204__rt_internal_node_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext204 :: RT INTERNAL NODE RAY COUNT XECORE1 */
#define mtlgt3__ext204__rt_internal_node_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext204 :: RT INTERNAL NODE RAY COUNT XECORE2 */
#define mtlgt3__ext204__rt_internal_node_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext204 :: RT INTERNAL NODE RAY COUNT XECORE3 */
#define mtlgt3__ext204__rt_internal_node_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext205 :: GPU Time Elapsed */
#define mtlgt3__ext205__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext205 :: GPU Core Clocks */
#define mtlgt3__ext205__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext205 :: AVG GPU Core Frequency */
#define mtlgt3__ext205__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext205 :: AVG GPU Core Frequency */
#define mtlgt3__ext205__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext205 :: RT INSTANCE NODE RAY COUNT XECORE0 */
#define mtlgt3__ext205__rt_instance_node_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext205 :: RT INSTANCE NODE RAY COUNT XECORE1 */
#define mtlgt3__ext205__rt_instance_node_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext205 :: RT INSTANCE NODE RAY COUNT XECORE2 */
#define mtlgt3__ext205__rt_instance_node_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext205 :: RT INSTANCE NODE RAY COUNT XECORE3 */
#define mtlgt3__ext205__rt_instance_node_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext206 :: GPU Time Elapsed */
#define mtlgt3__ext206__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext206 :: GPU Core Clocks */
#define mtlgt3__ext206__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext206 :: AVG GPU Core Frequency */
#define mtlgt3__ext206__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext206 :: AVG GPU Core Frequency */
#define mtlgt3__ext206__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext206 :: RT INTERNAL NODE RAY COUNT XECORE4 */
#define mtlgt3__ext206__rt_internal_node_ray_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext206 :: RT INTERNAL NODE RAY COUNT XECORE5 */
#define mtlgt3__ext206__rt_internal_node_ray_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext206 :: RT INTERNAL NODE RAY COUNT XECORE6 */
#define mtlgt3__ext206__rt_internal_node_ray_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext206 :: RT INTERNAL NODE RAY COUNT XECORE7 */
#define mtlgt3__ext206__rt_internal_node_ray_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext207 :: GPU Time Elapsed */
#define mtlgt3__ext207__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext207 :: GPU Core Clocks */
#define mtlgt3__ext207__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext207 :: AVG GPU Core Frequency */
#define mtlgt3__ext207__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext207 :: AVG GPU Core Frequency */
#define mtlgt3__ext207__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext207 :: RT INSTANCE NODE RAY COUNT XECORE4 */
#define mtlgt3__ext207__rt_instance_node_ray_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext207 :: RT INSTANCE NODE RAY COUNT XECORE5 */
#define mtlgt3__ext207__rt_instance_node_ray_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext207 :: RT INSTANCE NODE RAY COUNT XECORE6 */
#define mtlgt3__ext207__rt_instance_node_ray_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext207 :: RT INSTANCE NODE RAY COUNT XECORE7 */
#define mtlgt3__ext207__rt_instance_node_ray_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext212 :: GPU Time Elapsed */
#define mtlgt3__ext212__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext212 :: GPU Core Clocks */
#define mtlgt3__ext212__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext212 :: AVG GPU Core Frequency */
#define mtlgt3__ext212__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext212 :: AVG GPU Core Frequency */
#define mtlgt3__ext212__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext212 :: RT QUAD LEAF RAY COUNT XECORE0 */
#define mtlgt3__ext212__rt_quad_leaf_ray_count_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext212 :: RT PROCEDURAL NODE RAY COUNT XECORE0 */
#define mtlgt3__ext212__rt_procedural_node_ray_count_xecore0__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext212 :: RT QUAD LEAF RAY COUNT XECORE1 */
#define mtlgt3__ext212__rt_quad_leaf_ray_count_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext212 :: RT PROCEDURAL NODE RAY COUNT XECORE1 */
#define mtlgt3__ext212__rt_procedural_node_ray_count_xecore1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext213 :: GPU Time Elapsed */
#define mtlgt3__ext213__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext213 :: GPU Core Clocks */
#define mtlgt3__ext213__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext213 :: AVG GPU Core Frequency */
#define mtlgt3__ext213__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext213 :: AVG GPU Core Frequency */
#define mtlgt3__ext213__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext213 :: RT QUAD LEAF RAY COUNT XECORE4 */
#define mtlgt3__ext213__rt_quad_leaf_ray_count_xecore4__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext213 :: RT PROCEDURAL NODE RAY COUNT XECORE4 */
#define mtlgt3__ext213__rt_procedural_node_ray_count_xecore4__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext213 :: RT QUAD LEAF RAY COUNT XECORE5 */
#define mtlgt3__ext213__rt_quad_leaf_ray_count_xecore5__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext213 :: RT PROCEDURAL NODE RAY COUNT XECORE5 */
#define mtlgt3__ext213__rt_procedural_node_ray_count_xecore5__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext214 :: GPU Time Elapsed */
#define mtlgt3__ext214__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext214 :: GPU Core Clocks */
#define mtlgt3__ext214__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext214 :: AVG GPU Core Frequency */
#define mtlgt3__ext214__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext214 :: AVG GPU Core Frequency */
#define mtlgt3__ext214__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext214 :: RT QUAD LEAF RAY COUNT XECORE2 */
#define mtlgt3__ext214__rt_quad_leaf_ray_count_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext214 :: RT PROCEDURAL NODE RAY COUNT XECORE2 */
#define mtlgt3__ext214__rt_procedural_node_ray_count_xecore2__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext214 :: RT QUAD LEAF RAY COUNT XECORE3 */
#define mtlgt3__ext214__rt_quad_leaf_ray_count_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext214 :: RT PROCEDURAL NODE RAY COUNT XECORE3 */
#define mtlgt3__ext214__rt_procedural_node_ray_count_xecore3__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext215 :: GPU Time Elapsed */
#define mtlgt3__ext215__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext215 :: GPU Core Clocks */
#define mtlgt3__ext215__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext215 :: AVG GPU Core Frequency */
#define mtlgt3__ext215__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext215 :: AVG GPU Core Frequency */
#define mtlgt3__ext215__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext215 :: RT QUAD LEAF RAY COUNT XECORE6 */
#define mtlgt3__ext215__rt_quad_leaf_ray_count_xecore6__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext215 :: RT PROCEDURAL NODE RAY COUNT XECORE6 */
#define mtlgt3__ext215__rt_procedural_node_ray_count_xecore6__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext215 :: RT QUAD LEAF RAY COUNT XECORE7 */
#define mtlgt3__ext215__rt_quad_leaf_ray_count_xecore7__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext215 :: RT PROCEDURAL NODE RAY COUNT XECORE7 */
#define mtlgt3__ext215__rt_procedural_node_ray_count_xecore7__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext220 :: GPU Time Elapsed */
#define mtlgt3__ext220__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext220 :: GPU Core Clocks */
#define mtlgt3__ext220__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext220 :: AVG GPU Core Frequency */
#define mtlgt3__ext220__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext220 :: AVG GPU Core Frequency */
#define mtlgt3__ext220__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext220 :: RT BVH CACHE MISS XECORE0 */
#define mtlgt3__ext220__rt_bvh_cache_miss_xecore0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext220 :: RT BVH CACHE MISS XECORE1 */
#define mtlgt3__ext220__rt_bvh_cache_miss_xecore1__read \
   acmgt1__ext124__clipper_input_vertex_slice0__read

/* Ext220 :: RT BVH CACHE MISS XECORE2 */
#define mtlgt3__ext220__rt_bvh_cache_miss_xecore2__read \
   acmgt1__ext124__clipper_input_vertex_slice1__read

/* Ext220 :: RT BVH CACHE MISS XECORE3 */
#define mtlgt3__ext220__rt_bvh_cache_miss_xecore3__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read

/* Ext220 :: RT BVH CACHE MISS XECORE4 */
#define mtlgt3__ext220__rt_bvh_cache_miss_xecore4__read \
   hsw__sampler_balance__sampler0_l2_cache_misses__read

/* Ext220 :: RT BVH CACHE MISS XECORE5 */
#define mtlgt3__ext220__rt_bvh_cache_miss_xecore5__read \
   hsw__sampler_balance__sampler1_l2_cache_misses__read

/* Ext220 :: RT BVH CACHE MISS XECORE6 */
#define mtlgt3__ext220__rt_bvh_cache_miss_xecore6__read \
   hsw__sampler_balance__sampler2_l2_cache_misses__read

/* Ext220 :: RT BVH CACHE MISS XECORE7 */
#define mtlgt3__ext220__rt_bvh_cache_miss_xecore7__read \
   hsw__sampler_balance__sampler3_l2_cache_misses__read

/* Ext225 :: GPU Time Elapsed */
#define mtlgt3__ext225__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext225 :: GPU Core Clocks */
#define mtlgt3__ext225__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext225 :: AVG GPU Core Frequency */
#define mtlgt3__ext225__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext225 :: AVG GPU Core Frequency */
#define mtlgt3__ext225__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext225 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0 */
static uint64_t
mtlgt3__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read(UNUSED struct intel_perf_config *perf,
                                                                       const struct intel_perf_query_info *query,
                                                                       const struct intel_perf_query_result *results)
{
   /* RPN equation: 1 C 1 READ UMUL 2 B 0 READ UMUL UADD 4 B 1 READ UMUL UADD 8 B 2 READ UMUL UADD 16 B 3 READ UMUL UADD 32 B 4 READ UMUL UADD 64 B 5 READ UMUL UADD 128 B 6 READ UMUL UADD 256 B 7 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = 1 * tmp0;
   uint64_t tmp2 = results->accumulator[query->b_offset + 0];
   uint64_t tmp3 = 2 * tmp2;
   uint64_t tmp4 = tmp1 + tmp3;
   uint64_t tmp5 = results->accumulator[query->b_offset + 1];
   uint64_t tmp6 = 4 * tmp5;
   uint64_t tmp7 = tmp4 + tmp6;
   uint64_t tmp8 = results->accumulator[query->b_offset + 2];
   uint64_t tmp9 = 8 * tmp8;
   uint64_t tmp10 = tmp7 + tmp9;
   uint64_t tmp11 = results->accumulator[query->b_offset + 3];
   uint64_t tmp12 = 16 * tmp11;
   uint64_t tmp13 = tmp10 + tmp12;
   uint64_t tmp14 = results->accumulator[query->b_offset + 4];
   uint64_t tmp15 = 32 * tmp14;
   uint64_t tmp16 = tmp13 + tmp15;
   uint64_t tmp17 = results->accumulator[query->b_offset + 5];
   uint64_t tmp18 = 64 * tmp17;
   uint64_t tmp19 = tmp16 + tmp18;
   uint64_t tmp20 = results->accumulator[query->b_offset + 6];
   uint64_t tmp21 = 128 * tmp20;
   uint64_t tmp22 = tmp19 + tmp21;
   uint64_t tmp23 = results->accumulator[query->b_offset + 7];
   uint64_t tmp24 = 256 * tmp23;
   uint64_t tmp25 = tmp22 + tmp24;

   return tmp25;
}

/* Ext226 :: GPU Time Elapsed */
#define mtlgt3__ext226__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext226 :: GPU Core Clocks */
#define mtlgt3__ext226__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext226 :: AVG GPU Core Frequency */
#define mtlgt3__ext226__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext226 :: AVG GPU Core Frequency */
#define mtlgt3__ext226__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext226 :: PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1 */
#define mtlgt3__ext226__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read \
   mtlgt2__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext227 :: GPU Time Elapsed */
#define mtlgt3__ext227__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext227 :: GPU Core Clocks */
#define mtlgt3__ext227__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext227 :: AVG GPU Core Frequency */
#define mtlgt3__ext227__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext227 :: AVG GPU Core Frequency */
#define mtlgt3__ext227__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext227 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0 */
#define mtlgt3__ext227__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read \
   mtlgt2__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext228 :: GPU Time Elapsed */
#define mtlgt3__ext228__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext228 :: GPU Core Clocks */
#define mtlgt3__ext228__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext228 :: AVG GPU Core Frequency */
#define mtlgt3__ext228__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext228 :: AVG GPU Core Frequency */
#define mtlgt3__ext228__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext228 :: PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1 */
#define mtlgt3__ext228__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read \
   mtlgt2__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read

/* Ext229 :: GPU Time Elapsed */
#define mtlgt3__ext229__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext229 :: GPU Core Clocks */
#define mtlgt3__ext229__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext229 :: AVG GPU Core Frequency */
#define mtlgt3__ext229__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext229 :: AVG GPU Core Frequency */
#define mtlgt3__ext229__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext229 :: SLM BANK CONFLICT COUNT XECORE0 */
#define mtlgt3__ext229__slm_bank_conflict_count_xecore0__read \
   mtlgt2__ext229__slm_bank_conflict_count_xecore1__read

/* Ext229 :: SLM BANK CONFLICT COUNT XECORE1 */
static uint64_t
mtlgt3__ext229__slm_bank_conflict_count_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ 2 C 1 READ UMUL UADD 4 C 2 READ UMUL UADD 8 C 3 READ UMUL UADD C 4 READ UADD 2 C 5 READ UMUL UADD 4 C 6 READ UMUL UADD 8 C 7 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 1];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 2];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 3];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 4];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->c_offset + 5];
   uint64_t tmp13 = 2 * tmp12;
   uint64_t tmp14 = tmp11 + tmp13;
   uint64_t tmp15 = results->accumulator[query->c_offset + 6];
   uint64_t tmp16 = 4 * tmp15;
   uint64_t tmp17 = tmp14 + tmp16;
   uint64_t tmp18 = results->accumulator[query->c_offset + 7];
   uint64_t tmp19 = 8 * tmp18;
   uint64_t tmp20 = tmp17 + tmp19;

   return tmp20;
}

/* Ext230 :: GPU Time Elapsed */
#define mtlgt3__ext230__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext230 :: GPU Core Clocks */
#define mtlgt3__ext230__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext230 :: AVG GPU Core Frequency */
#define mtlgt3__ext230__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext230 :: AVG GPU Core Frequency */
#define mtlgt3__ext230__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext230 :: SLM BANK CONFLICT COUNT XECORE4 */
#define mtlgt3__ext230__slm_bank_conflict_count_xecore4__read \
   mtlgt2__ext229__slm_bank_conflict_count_xecore0__read

/* Ext230 :: SLM BANK CONFLICT COUNT XECORE5 */
#define mtlgt3__ext230__slm_bank_conflict_count_xecore5__read \
   mtlgt2__ext229__slm_bank_conflict_count_xecore1__read

/* Ext231 :: GPU Time Elapsed */
#define mtlgt3__ext231__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext231 :: GPU Core Clocks */
#define mtlgt3__ext231__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext231 :: AVG GPU Core Frequency */
#define mtlgt3__ext231__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext231 :: AVG GPU Core Frequency */
#define mtlgt3__ext231__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext231 :: SLM BANK CONFLICT COUNT XECORE2 */
static uint64_t
mtlgt3__ext231__slm_bank_conflict_count_xecore2__read(UNUSED struct intel_perf_config *perf,
                                                      const struct intel_perf_query_info *query,
                                                      const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ 2 B 1 READ UMUL UADD 4 B 2 READ UMUL UADD 8 B 3 READ UMUL UADD B 4 READ UADD 2 B 5 READ UMUL UADD 4 B 6 READ UMUL UADD 8 B 7 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 1];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 2];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 3];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 4];
   uint64_t tmp11 = tmp9 + tmp10;
   uint64_t tmp12 = results->accumulator[query->b_offset + 5];
   uint64_t tmp13 = 2 * tmp12;
   uint64_t tmp14 = tmp11 + tmp13;
   uint64_t tmp15 = results->accumulator[query->b_offset + 6];
   uint64_t tmp16 = 4 * tmp15;
   uint64_t tmp17 = tmp14 + tmp16;
   uint64_t tmp18 = results->accumulator[query->b_offset + 7];
   uint64_t tmp19 = 8 * tmp18;
   uint64_t tmp20 = tmp17 + tmp19;

   return tmp20;
}

/* Ext231 :: SLM BANK CONFLICT COUNT XECORE3 */
#define mtlgt3__ext231__slm_bank_conflict_count_xecore3__read \
   mtlgt3__ext229__slm_bank_conflict_count_xecore1__read

/* Ext232 :: GPU Time Elapsed */
#define mtlgt3__ext232__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext232 :: GPU Core Clocks */
#define mtlgt3__ext232__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext232 :: AVG GPU Core Frequency */
#define mtlgt3__ext232__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext232 :: AVG GPU Core Frequency */
#define mtlgt3__ext232__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext232 :: SLM BANK CONFLICT COUNT XECORE6 */
#define mtlgt3__ext232__slm_bank_conflict_count_xecore6__read \
   mtlgt2__ext229__slm_bank_conflict_count_xecore0__read

/* Ext232 :: SLM BANK CONFLICT COUNT XECORE7 */
#define mtlgt3__ext232__slm_bank_conflict_count_xecore7__read \
   mtlgt2__ext229__slm_bank_conflict_count_xecore1__read

/* Ext236 :: GPU Time Elapsed */
#define mtlgt3__ext236__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext236 :: GPU Core Clocks */
#define mtlgt3__ext236__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext236 :: AVG GPU Core Frequency */
#define mtlgt3__ext236__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext236 :: AVG GPU Core Frequency */
#define mtlgt3__ext236__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext236 :: L3 MISS L3BANK0 */
#define mtlgt3__ext236__l3_miss_l3_bank0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext236 :: L3 MISS L3BANK1 */
#define mtlgt3__ext236__l3_miss_l3_bank1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext236 :: L3 MISS L3BANK2 */
#define mtlgt3__ext236__l3_miss_l3_bank2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext236 :: L3 MISS L3BANK3 */
#define mtlgt3__ext236__l3_miss_l3_bank3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext236 :: L3 MISS L3BANK4 */
#define mtlgt3__ext236__l3_miss_l3_bank4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext236 :: L3 MISS L3BANK5 */
#define mtlgt3__ext236__l3_miss_l3_bank5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext236 :: L3 MISS L3BANK6 */
#define mtlgt3__ext236__l3_miss_l3_bank6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext236 :: L3 MISS L3BANK7 */
#define mtlgt3__ext236__l3_miss_l3_bank7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext237 :: GPU Time Elapsed */
#define mtlgt3__ext237__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext237 :: GPU Core Clocks */
#define mtlgt3__ext237__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext237 :: AVG GPU Core Frequency */
#define mtlgt3__ext237__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext237 :: AVG GPU Core Frequency */
#define mtlgt3__ext237__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext237 :: AMFS L3 WRITE SLICE0 */
#define mtlgt3__ext237__amfs_l3_write_slice0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext237 :: AMFS L3 WRITE SLICE1 */
#define mtlgt3__ext237__amfs_l3_write_slice1__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext237 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE0 */
#define mtlgt3__ext237__xve_dataport_fence_message_count_xecore0__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext237 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE1 */
#define mtlgt3__ext237__xve_dataport_fence_message_count_xecore1__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext237 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE2 */
#define mtlgt3__ext237__xve_dataport_fence_message_count_xecore2__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext237 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE3 */
#define mtlgt3__ext237__xve_dataport_fence_message_count_xecore3__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext237 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE4 */
#define mtlgt3__ext237__xve_dataport_fence_message_count_xecore4__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext237 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE5 */
#define mtlgt3__ext237__xve_dataport_fence_message_count_xecore5__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext237 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE6 */
#define mtlgt3__ext237__xve_dataport_fence_message_count_xecore6__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext237 :: XVE DATAPORT FENCE MESSAGE COUNT XECORE7 */
#define mtlgt3__ext237__xve_dataport_fence_message_count_xecore7__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext239 :: GPU Time Elapsed */
#define mtlgt3__ext239__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext239 :: GPU Core Clocks */
#define mtlgt3__ext239__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext239 :: AVG GPU Core Frequency */
#define mtlgt3__ext239__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext239 :: AVG GPU Core Frequency */
#define mtlgt3__ext239__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext239 :: GPU MEMORY L3 READ SQIDI0 */
#define mtlgt3__ext239__gpu_memory_l3_read_sqidi0__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext240 :: GPU Time Elapsed */
#define mtlgt3__ext240__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext240 :: GPU Core Clocks */
#define mtlgt3__ext240__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext240 :: AVG GPU Core Frequency */
#define mtlgt3__ext240__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext240 :: AVG GPU Core Frequency */
#define mtlgt3__ext240__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext240 :: GPU MEMORY L3 READ SQIDI1 */
#define mtlgt3__ext240__gpu_memory_l3_read_sqidi1__read \
   acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read

/* Ext500 :: GPU Time Elapsed */
#define mtlgt3__ext500__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext500 :: GPU Core Clocks */
#define mtlgt3__ext500__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext500 :: AVG GPU Core Frequency */
#define mtlgt3__ext500__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext500 :: AVG GPU Core Frequency */
#define mtlgt3__ext500__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext500 :: ICACHE HIT BANK0 XECORE0 */
#define mtlgt3__ext500__icache_hit_bank0_xecore0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE0 */
#define mtlgt3__ext500__icache_miss_bank0_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext500 :: ICACHE HIT BANK0 XECORE1 */
#define mtlgt3__ext500__icache_hit_bank0_xecore1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE1 */
#define mtlgt3__ext500__icache_miss_bank0_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext500 :: ICACHE HIT BANK0 XECORE2 */
#define mtlgt3__ext500__icache_hit_bank0_xecore2__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE2 */
#define mtlgt3__ext500__icache_miss_bank0_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext500 :: ICACHE HIT BANK0 XECORE3 */
#define mtlgt3__ext500__icache_hit_bank0_xecore3__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext500 :: ICACHE MISS BANK0 XECORE3 */
#define mtlgt3__ext500__icache_miss_bank0_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext500 :: ICACHE HIT BANK0 XECORE4 */
#define mtlgt3__ext500__icache_hit_bank0_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE4 */
#define mtlgt3__ext500__icache_miss_bank0_xecore4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext500 :: ICACHE HIT BANK0 XECORE5 */
#define mtlgt3__ext500__icache_hit_bank0_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE5 */
#define mtlgt3__ext500__icache_miss_bank0_xecore5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext500 :: ICACHE HIT BANK0 XECORE6 */
#define mtlgt3__ext500__icache_hit_bank0_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE6 */
#define mtlgt3__ext500__icache_miss_bank0_xecore6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext500 :: ICACHE HIT BANK0 XECORE7 */
#define mtlgt3__ext500__icache_hit_bank0_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext500 :: ICACHE MISS BANK0 XECORE7 */
#define mtlgt3__ext500__icache_miss_bank0_xecore7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext501 :: GPU Time Elapsed */
#define mtlgt3__ext501__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext501 :: GPU Core Clocks */
#define mtlgt3__ext501__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext501 :: AVG GPU Core Frequency */
#define mtlgt3__ext501__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext501 :: AVG GPU Core Frequency */
#define mtlgt3__ext501__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext501 :: ICACHE HIT BANK1 XECORE0 */
#define mtlgt3__ext501__icache_hit_bank1_xecore0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE0 */
#define mtlgt3__ext501__icache_miss_bank1_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext501 :: ICACHE HIT BANK1 XECORE1 */
#define mtlgt3__ext501__icache_hit_bank1_xecore1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE1 */
#define mtlgt3__ext501__icache_miss_bank1_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext501 :: ICACHE HIT BANK1 XECORE2 */
#define mtlgt3__ext501__icache_hit_bank1_xecore2__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE2 */
#define mtlgt3__ext501__icache_miss_bank1_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext501 :: ICACHE HIT BANK1 XECORE3 */
#define mtlgt3__ext501__icache_hit_bank1_xecore3__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext501 :: ICACHE MISS BANK1 XECORE3 */
#define mtlgt3__ext501__icache_miss_bank1_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext501 :: ICACHE HIT BANK1 XECORE4 */
#define mtlgt3__ext501__icache_hit_bank1_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE4 */
#define mtlgt3__ext501__icache_miss_bank1_xecore4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext501 :: ICACHE HIT BANK1 XECORE5 */
#define mtlgt3__ext501__icache_hit_bank1_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE5 */
#define mtlgt3__ext501__icache_miss_bank1_xecore5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext501 :: ICACHE HIT BANK1 XECORE6 */
#define mtlgt3__ext501__icache_hit_bank1_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE6 */
#define mtlgt3__ext501__icache_miss_bank1_xecore6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext501 :: ICACHE HIT BANK1 XECORE7 */
#define mtlgt3__ext501__icache_hit_bank1_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext501 :: ICACHE MISS BANK1 XECORE7 */
#define mtlgt3__ext501__icache_miss_bank1_xecore7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext502 :: GPU Time Elapsed */
#define mtlgt3__ext502__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext502 :: GPU Core Clocks */
#define mtlgt3__ext502__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext502 :: AVG GPU Core Frequency */
#define mtlgt3__ext502__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext502 :: AVG GPU Core Frequency */
#define mtlgt3__ext502__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext502 :: ICACHE HIT BANK2 XECORE0 */
#define mtlgt3__ext502__icache_hit_bank2_xecore0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE0 */
#define mtlgt3__ext502__icache_miss_bank2_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext502 :: ICACHE HIT BANK2 XECORE1 */
#define mtlgt3__ext502__icache_hit_bank2_xecore1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE1 */
#define mtlgt3__ext502__icache_miss_bank2_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext502 :: ICACHE HIT BANK2 XECORE2 */
#define mtlgt3__ext502__icache_hit_bank2_xecore2__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE2 */
#define mtlgt3__ext502__icache_miss_bank2_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext502 :: ICACHE HIT BANK2 XECORE3 */
#define mtlgt3__ext502__icache_hit_bank2_xecore3__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext502 :: ICACHE MISS BANK2 XECORE3 */
#define mtlgt3__ext502__icache_miss_bank2_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext502 :: ICACHE HIT BANK2 XECORE4 */
#define mtlgt3__ext502__icache_hit_bank2_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE4 */
#define mtlgt3__ext502__icache_miss_bank2_xecore4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext502 :: ICACHE HIT BANK2 XECORE5 */
#define mtlgt3__ext502__icache_hit_bank2_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE5 */
#define mtlgt3__ext502__icache_miss_bank2_xecore5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext502 :: ICACHE HIT BANK2 XECORE6 */
#define mtlgt3__ext502__icache_hit_bank2_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE6 */
#define mtlgt3__ext502__icache_miss_bank2_xecore6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext502 :: ICACHE HIT BANK2 XECORE7 */
#define mtlgt3__ext502__icache_hit_bank2_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext502 :: ICACHE MISS BANK2 XECORE7 */
#define mtlgt3__ext502__icache_miss_bank2_xecore7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext503 :: GPU Time Elapsed */
#define mtlgt3__ext503__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext503 :: GPU Core Clocks */
#define mtlgt3__ext503__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext503 :: AVG GPU Core Frequency */
#define mtlgt3__ext503__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext503 :: AVG GPU Core Frequency */
#define mtlgt3__ext503__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext503 :: ICACHE HIT BANK3 XECORE0 */
#define mtlgt3__ext503__icache_hit_bank3_xecore0__read \
   hsw__compute_extended__eu_untyped_atomics0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE0 */
#define mtlgt3__ext503__icache_miss_bank3_xecore0__read \
   hsw__compute_extended__typed_writes0__read

/* Ext503 :: ICACHE HIT BANK3 XECORE1 */
#define mtlgt3__ext503__icache_hit_bank3_xecore1__read \
   hsw__compute_extended__eu_typed_atomics0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE1 */
#define mtlgt3__ext503__icache_miss_bank3_xecore1__read \
   hsw__compute_extended__untyped_writes0__read

/* Ext503 :: ICACHE HIT BANK3 XECORE2 */
#define mtlgt3__ext503__icache_hit_bank3_xecore2__read \
   hsw__compute_extended__eu_urb_atomics0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE2 */
#define mtlgt3__ext503__icache_miss_bank3_xecore2__read \
   hsw__render_basic__gpu_core_clocks__read

/* Ext503 :: ICACHE HIT BANK3 XECORE3 */
#define mtlgt3__ext503__icache_hit_bank3_xecore3__read \
   hsw__compute_extended__gpu_clocks__read

/* Ext503 :: ICACHE MISS BANK3 XECORE3 */
#define mtlgt3__ext503__icache_miss_bank3_xecore3__read \
   hsw__compute_extended__untyped_reads0__read

/* Ext503 :: ICACHE HIT BANK3 XECORE4 */
#define mtlgt3__ext503__icache_hit_bank3_xecore4__read \
   hsw__compute_extended__eu_untyped_reads0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE4 */
#define mtlgt3__ext503__icache_miss_bank3_xecore4__read \
   hsw__memory_reads__gpu_core_clocks__read

/* Ext503 :: ICACHE HIT BANK3 XECORE5 */
#define mtlgt3__ext503__icache_hit_bank3_xecore5__read \
   hsw__compute_extended__eu_untyped_writes0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE5 */
#define mtlgt3__ext503__icache_miss_bank3_xecore5__read \
   hsw__memory_reads__llc_read_accesses__read

/* Ext503 :: ICACHE HIT BANK3 XECORE6 */
#define mtlgt3__ext503__icache_hit_bank3_xecore6__read \
   hsw__compute_extended__eu_typed_reads0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE6 */
#define mtlgt3__ext503__icache_miss_bank3_xecore6__read \
   hsw__memory_reads__gti_memory_reads__read

/* Ext503 :: ICACHE HIT BANK3 XECORE7 */
#define mtlgt3__ext503__icache_hit_bank3_xecore7__read \
   hsw__compute_extended__eu_typed_writes0__read

/* Ext503 :: ICACHE MISS BANK3 XECORE7 */
#define mtlgt3__ext503__icache_miss_bank3_xecore7__read \
   hsw__compute_extended__typed_atomics0__read

/* Ext508 :: GPU Time Elapsed */
#define mtlgt3__ext508__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext508 :: GPU Core Clocks */
#define mtlgt3__ext508__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext508 :: AVG GPU Core Frequency */
#define mtlgt3__ext508__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext508 :: AVG GPU Core Frequency */
#define mtlgt3__ext508__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext508 :: SLM BYTE READ BANK0 XECORE0 */
static uint64_t
mtlgt3__ext508__slm_byte_read_bank0_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ 2 B 3 READ UMUL UADD 4 B 4 READ UMUL UADD 8 B 5 READ UMUL UADD 16 B 6 READ UMUL UADD 32 B 7 READ UMUL UADD 64 C 0 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->b_offset + 3];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 4];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 5];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 6];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 7];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 0];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;

   return tmp18;
}

/* Ext508 :: SLM BYTE READ BANK0 XECORE1 */
static uint64_t
mtlgt3__ext508__slm_byte_read_bank0_xecore1__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ 2 C 2 READ UMUL UADD 4 C 3 READ UMUL UADD 8 C 4 READ UMUL UADD 16 C 5 READ UMUL UADD 32 C 6 READ UMUL UADD 64 C 7 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 2];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 3];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 4];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 5];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 6];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 7];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;

   return tmp18;
}

/* Ext509 :: GPU Time Elapsed */
#define mtlgt3__ext509__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext509 :: GPU Core Clocks */
#define mtlgt3__ext509__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext509 :: AVG GPU Core Frequency */
#define mtlgt3__ext509__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext509 :: AVG GPU Core Frequency */
#define mtlgt3__ext509__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext509 :: SLM BYTE READ BANK1 XECORE0 */
#define mtlgt3__ext509__slm_byte_read_bank1_xecore0__read \
   mtlgt3__ext508__slm_byte_read_bank0_xecore1__read

/* Ext509 :: SLM BYTE READ BANK1 XECORE1 */
#define mtlgt3__ext509__slm_byte_read_bank1_xecore1__read \
   mtlgt3__ext508__slm_byte_read_bank0_xecore0__read

/* Ext510 :: GPU Time Elapsed */
#define mtlgt3__ext510__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext510 :: GPU Core Clocks */
#define mtlgt3__ext510__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext510 :: AVG GPU Core Frequency */
#define mtlgt3__ext510__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext510 :: AVG GPU Core Frequency */
#define mtlgt3__ext510__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext510 :: SLM BYTE READ BANK0 XECORE2 */
static uint64_t
mtlgt3__ext510__slm_byte_read_bank0_xecore2__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: B 2 READ 2 C 7 READ UMUL UADD 4 C 6 READ UMUL UADD 8 C 5 READ UMUL UADD 16 C 4 READ UMUL UADD 32 C 3 READ UMUL UADD 64 C 2 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 2];
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 6];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 5];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 4];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 3];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 2];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;

   return tmp18;
}

/* Ext510 :: SLM BYTE READ BANK0 XECORE3 */
static uint64_t
mtlgt3__ext510__slm_byte_read_bank0_xecore3__read(UNUSED struct intel_perf_config *perf,
                                                  const struct intel_perf_query_info *query,
                                                  const struct intel_perf_query_result *results)
{
   /* RPN equation: C 1 READ 2 C 0 READ UMUL UADD 4 B 7 READ UMUL UADD 8 B 6 READ UMUL UADD 16 B 5 READ UMUL UADD 32 B 4 READ UMUL UADD 64 B 3 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 1];
   uint64_t tmp1 = results->accumulator[query->c_offset + 0];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 7];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 6];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 5];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 4];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->b_offset + 3];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;

   return tmp18;
}

/* Ext511 :: GPU Time Elapsed */
#define mtlgt3__ext511__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext511 :: GPU Core Clocks */
#define mtlgt3__ext511__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext511 :: AVG GPU Core Frequency */
#define mtlgt3__ext511__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext511 :: AVG GPU Core Frequency */
#define mtlgt3__ext511__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext511 :: SLM BYTE READ BANK1 XECORE2 */
#define mtlgt3__ext511__slm_byte_read_bank1_xecore2__read \
   mtlgt3__ext510__slm_byte_read_bank0_xecore2__read

/* Ext511 :: SLM BYTE READ BANK1 XECORE3 */
#define mtlgt3__ext511__slm_byte_read_bank1_xecore3__read \
   mtlgt3__ext510__slm_byte_read_bank0_xecore3__read

/* Ext512 :: GPU Time Elapsed */
#define mtlgt3__ext512__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext512 :: GPU Core Clocks */
#define mtlgt3__ext512__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext512 :: AVG GPU Core Frequency */
#define mtlgt3__ext512__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext512 :: AVG GPU Core Frequency */
#define mtlgt3__ext512__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext512 :: SLM BYTE READ BANK0 XECORE4 */
#define mtlgt3__ext512__slm_byte_read_bank0_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext512 :: SLM BYTE READ BANK0 XECORE5 */
#define mtlgt3__ext512__slm_byte_read_bank0_xecore5__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext513 :: GPU Time Elapsed */
#define mtlgt3__ext513__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext513 :: GPU Core Clocks */
#define mtlgt3__ext513__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext513 :: AVG GPU Core Frequency */
#define mtlgt3__ext513__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext513 :: AVG GPU Core Frequency */
#define mtlgt3__ext513__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext513 :: SLM BYTE READ BANK1 XECORE4 */
#define mtlgt3__ext513__slm_byte_read_bank1_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext513 :: SLM BYTE READ BANK1 XECORE5 */
#define mtlgt3__ext513__slm_byte_read_bank1_xecore5__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext514 :: GPU Time Elapsed */
#define mtlgt3__ext514__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext514 :: GPU Core Clocks */
#define mtlgt3__ext514__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext514 :: AVG GPU Core Frequency */
#define mtlgt3__ext514__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext514 :: AVG GPU Core Frequency */
#define mtlgt3__ext514__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext514 :: SLM BYTE READ BANK0 XECORE6 */
#define mtlgt3__ext514__slm_byte_read_bank0_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext514 :: SLM BYTE READ BANK0 XECORE7 */
#define mtlgt3__ext514__slm_byte_read_bank0_xecore7__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext515 :: GPU Time Elapsed */
#define mtlgt3__ext515__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext515 :: GPU Core Clocks */
#define mtlgt3__ext515__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext515 :: AVG GPU Core Frequency */
#define mtlgt3__ext515__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext515 :: AVG GPU Core Frequency */
#define mtlgt3__ext515__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext515 :: SLM BYTE READ BANK1 XECORE6 */
#define mtlgt3__ext515__slm_byte_read_bank1_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext515 :: SLM BYTE READ BANK1 XECORE7 */
#define mtlgt3__ext515__slm_byte_read_bank1_xecore7__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext516 :: GPU Time Elapsed */
#define mtlgt3__ext516__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext516 :: GPU Core Clocks */
#define mtlgt3__ext516__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext516 :: AVG GPU Core Frequency */
#define mtlgt3__ext516__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext516 :: AVG GPU Core Frequency */
#define mtlgt3__ext516__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext516 :: LOAD STORE CACHE BYTE READ BANK0 XECORE0 */
static uint64_t
mtlgt3__ext516__load_store_cache_byte_read_bank0_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                               const struct intel_perf_query_info *query,
                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: C 7 READ 2 B 7 READ UMUL UADD 4 C 0 READ UMUL UADD 8 C 1 READ UMUL UADD 16 C 2 READ UMUL UADD 32 C 3 READ UMUL UADD 64 C 4 READ UMUL UADD 128 C 5 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 7];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 0];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 1];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 2];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 3];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 4];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->c_offset + 5];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;

   return tmp21;
}

/* Ext516 :: LOAD STORE CACHE BYTE READ BANK1 XECORE0 */
static uint64_t
mtlgt3__ext516__load_store_cache_byte_read_bank1_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                               const struct intel_perf_query_info *query,
                                                               const struct intel_perf_query_result *results)
{
   /* RPN equation: C 6 READ 2 B 0 READ UMUL UADD 4 B 1 READ UMUL UADD 8 B 2 READ UMUL UADD 16 B 3 READ UMUL UADD 32 B 4 READ UMUL UADD 64 B 5 READ UMUL UADD 128 B 6 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 6];
   uint64_t tmp1 = results->accumulator[query->b_offset + 0];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 1];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 2];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 3];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 4];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->b_offset + 5];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->b_offset + 6];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;

   return tmp21;
}

/* Ext517 :: GPU Time Elapsed */
#define mtlgt3__ext517__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext517 :: GPU Core Clocks */
#define mtlgt3__ext517__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext517 :: AVG GPU Core Frequency */
#define mtlgt3__ext517__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext517 :: AVG GPU Core Frequency */
#define mtlgt3__ext517__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext517 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE0 */
static uint64_t
mtlgt3__ext517__load_store_cache_byte_write_bank0_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                                const struct intel_perf_query_info *query,
                                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: C 0 READ 2 B 7 READ UMUL UADD 4 B 6 READ UMUL UADD 8 B 5 READ UMUL UADD 16 B 4 READ UMUL UADD 32 B 3 READ UMUL UADD 64 B 2 READ UMUL UADD 128 B 1 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->c_offset + 0];
   uint64_t tmp1 = results->accumulator[query->b_offset + 7];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->b_offset + 6];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->b_offset + 5];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->b_offset + 4];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->b_offset + 3];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->b_offset + 2];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->b_offset + 1];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;

   return tmp21;
}

/* Ext517 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE0 */
static uint64_t
mtlgt3__ext517__load_store_cache_byte_write_bank1_xecore0__read(UNUSED struct intel_perf_config *perf,
                                                                const struct intel_perf_query_info *query,
                                                                const struct intel_perf_query_result *results)
{
   /* RPN equation: B 0 READ 2 C 7 READ UMUL UADD 4 C 6 READ UMUL UADD 8 C 5 READ UMUL UADD 16 C 4 READ UMUL UADD 32 C 3 READ UMUL UADD 64 C 2 READ UMUL UADD 128 C 1 READ UMUL UADD */
   uint64_t tmp0 = results->accumulator[query->b_offset + 0];
   uint64_t tmp1 = results->accumulator[query->c_offset + 7];
   uint64_t tmp2 = 2 * tmp1;
   uint64_t tmp3 = tmp0 + tmp2;
   uint64_t tmp4 = results->accumulator[query->c_offset + 6];
   uint64_t tmp5 = 4 * tmp4;
   uint64_t tmp6 = tmp3 + tmp5;
   uint64_t tmp7 = results->accumulator[query->c_offset + 5];
   uint64_t tmp8 = 8 * tmp7;
   uint64_t tmp9 = tmp6 + tmp8;
   uint64_t tmp10 = results->accumulator[query->c_offset + 4];
   uint64_t tmp11 = 16 * tmp10;
   uint64_t tmp12 = tmp9 + tmp11;
   uint64_t tmp13 = results->accumulator[query->c_offset + 3];
   uint64_t tmp14 = 32 * tmp13;
   uint64_t tmp15 = tmp12 + tmp14;
   uint64_t tmp16 = results->accumulator[query->c_offset + 2];
   uint64_t tmp17 = 64 * tmp16;
   uint64_t tmp18 = tmp15 + tmp17;
   uint64_t tmp19 = results->accumulator[query->c_offset + 1];
   uint64_t tmp20 = 128 * tmp19;
   uint64_t tmp21 = tmp18 + tmp20;

   return tmp21;
}

/* Ext518 :: GPU Time Elapsed */
#define mtlgt3__ext518__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext518 :: GPU Core Clocks */
#define mtlgt3__ext518__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext518 :: AVG GPU Core Frequency */
#define mtlgt3__ext518__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext518 :: AVG GPU Core Frequency */
#define mtlgt3__ext518__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext518 :: LOAD STORE CACHE BYTE READ BANK0 XECORE1 */
#define mtlgt3__ext518__load_store_cache_byte_read_bank0_xecore1__read \
   mtlgt3__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext518 :: LOAD STORE CACHE BYTE READ BANK1 XECORE1 */
#define mtlgt3__ext518__load_store_cache_byte_read_bank1_xecore1__read \
   mtlgt3__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext519 :: GPU Time Elapsed */
#define mtlgt3__ext519__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext519 :: GPU Core Clocks */
#define mtlgt3__ext519__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext519 :: AVG GPU Core Frequency */
#define mtlgt3__ext519__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext519 :: AVG GPU Core Frequency */
#define mtlgt3__ext519__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext519 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE1 */
#define mtlgt3__ext519__load_store_cache_byte_write_bank0_xecore1__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext519 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE1 */
#define mtlgt3__ext519__load_store_cache_byte_write_bank1_xecore1__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext520 :: GPU Time Elapsed */
#define mtlgt3__ext520__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext520 :: GPU Core Clocks */
#define mtlgt3__ext520__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext520 :: AVG GPU Core Frequency */
#define mtlgt3__ext520__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext520 :: AVG GPU Core Frequency */
#define mtlgt3__ext520__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext520 :: LOAD STORE CACHE BYTE READ BANK0 XECORE2 */
#define mtlgt3__ext520__load_store_cache_byte_read_bank0_xecore2__read \
   mtlgt3__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext520 :: LOAD STORE CACHE BYTE READ BANK1 XECORE2 */
#define mtlgt3__ext520__load_store_cache_byte_read_bank1_xecore2__read \
   mtlgt3__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext521 :: GPU Time Elapsed */
#define mtlgt3__ext521__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext521 :: GPU Core Clocks */
#define mtlgt3__ext521__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext521 :: AVG GPU Core Frequency */
#define mtlgt3__ext521__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext521 :: AVG GPU Core Frequency */
#define mtlgt3__ext521__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext521 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE2 */
#define mtlgt3__ext521__load_store_cache_byte_write_bank0_xecore2__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext521 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE2 */
#define mtlgt3__ext521__load_store_cache_byte_write_bank1_xecore2__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext522 :: GPU Time Elapsed */
#define mtlgt3__ext522__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext522 :: GPU Core Clocks */
#define mtlgt3__ext522__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext522 :: AVG GPU Core Frequency */
#define mtlgt3__ext522__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext522 :: AVG GPU Core Frequency */
#define mtlgt3__ext522__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext522 :: LOAD STORE CACHE BYTE READ BANK0 XECORE3 */
#define mtlgt3__ext522__load_store_cache_byte_read_bank0_xecore3__read \
   mtlgt3__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext522 :: LOAD STORE CACHE BYTE READ BANK1 XECORE3 */
#define mtlgt3__ext522__load_store_cache_byte_read_bank1_xecore3__read \
   mtlgt3__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext523 :: GPU Time Elapsed */
#define mtlgt3__ext523__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext523 :: GPU Core Clocks */
#define mtlgt3__ext523__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext523 :: AVG GPU Core Frequency */
#define mtlgt3__ext523__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext523 :: AVG GPU Core Frequency */
#define mtlgt3__ext523__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext523 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE3 */
#define mtlgt3__ext523__load_store_cache_byte_write_bank0_xecore3__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext523 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE3 */
#define mtlgt3__ext523__load_store_cache_byte_write_bank1_xecore3__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext524 :: GPU Time Elapsed */
#define mtlgt3__ext524__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext524 :: GPU Core Clocks */
#define mtlgt3__ext524__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext524 :: AVG GPU Core Frequency */
#define mtlgt3__ext524__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext524 :: AVG GPU Core Frequency */
#define mtlgt3__ext524__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext524 :: LOAD STORE CACHE BYTE READ BANK0 XECORE4 */
#define mtlgt3__ext524__load_store_cache_byte_read_bank0_xecore4__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext524 :: LOAD STORE CACHE BYTE READ BANK1 XECORE4 */
#define mtlgt3__ext524__load_store_cache_byte_read_bank1_xecore4__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext525 :: GPU Time Elapsed */
#define mtlgt3__ext525__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext525 :: GPU Core Clocks */
#define mtlgt3__ext525__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext525 :: AVG GPU Core Frequency */
#define mtlgt3__ext525__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext525 :: AVG GPU Core Frequency */
#define mtlgt3__ext525__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext525 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE4 */
#define mtlgt3__ext525__load_store_cache_byte_write_bank0_xecore4__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext525 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE4 */
#define mtlgt3__ext525__load_store_cache_byte_write_bank1_xecore4__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext526 :: GPU Time Elapsed */
#define mtlgt3__ext526__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext526 :: GPU Core Clocks */
#define mtlgt3__ext526__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext526 :: AVG GPU Core Frequency */
#define mtlgt3__ext526__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext526 :: AVG GPU Core Frequency */
#define mtlgt3__ext526__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext526 :: LOAD STORE CACHE BYTE READ BANK0 XECORE5 */
#define mtlgt3__ext526__load_store_cache_byte_read_bank0_xecore5__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext526 :: LOAD STORE CACHE BYTE READ BANK1 XECORE5 */
#define mtlgt3__ext526__load_store_cache_byte_read_bank1_xecore5__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext527 :: GPU Time Elapsed */
#define mtlgt3__ext527__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext527 :: GPU Core Clocks */
#define mtlgt3__ext527__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext527 :: AVG GPU Core Frequency */
#define mtlgt3__ext527__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext527 :: AVG GPU Core Frequency */
#define mtlgt3__ext527__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext527 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE5 */
#define mtlgt3__ext527__load_store_cache_byte_write_bank0_xecore5__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext527 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE5 */
#define mtlgt3__ext527__load_store_cache_byte_write_bank1_xecore5__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext528 :: GPU Time Elapsed */
#define mtlgt3__ext528__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext528 :: GPU Core Clocks */
#define mtlgt3__ext528__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext528 :: AVG GPU Core Frequency */
#define mtlgt3__ext528__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext528 :: AVG GPU Core Frequency */
#define mtlgt3__ext528__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext528 :: LOAD STORE CACHE BYTE READ BANK0 XECORE6 */
#define mtlgt3__ext528__load_store_cache_byte_read_bank0_xecore6__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext528 :: LOAD STORE CACHE BYTE READ BANK1 XECORE6 */
#define mtlgt3__ext528__load_store_cache_byte_read_bank1_xecore6__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext529 :: GPU Time Elapsed */
#define mtlgt3__ext529__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext529 :: GPU Core Clocks */
#define mtlgt3__ext529__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext529 :: AVG GPU Core Frequency */
#define mtlgt3__ext529__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext529 :: AVG GPU Core Frequency */
#define mtlgt3__ext529__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext529 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE6 */
#define mtlgt3__ext529__load_store_cache_byte_write_bank0_xecore6__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext529 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE6 */
#define mtlgt3__ext529__load_store_cache_byte_write_bank1_xecore6__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext530 :: GPU Time Elapsed */
#define mtlgt3__ext530__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext530 :: GPU Core Clocks */
#define mtlgt3__ext530__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext530 :: AVG GPU Core Frequency */
#define mtlgt3__ext530__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext530 :: AVG GPU Core Frequency */
#define mtlgt3__ext530__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext530 :: LOAD STORE CACHE BYTE READ BANK0 XECORE7 */
#define mtlgt3__ext530__load_store_cache_byte_read_bank0_xecore7__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext530 :: LOAD STORE CACHE BYTE READ BANK1 XECORE7 */
#define mtlgt3__ext530__load_store_cache_byte_read_bank1_xecore7__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext531 :: GPU Time Elapsed */
#define mtlgt3__ext531__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext531 :: GPU Core Clocks */
#define mtlgt3__ext531__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext531 :: AVG GPU Core Frequency */
#define mtlgt3__ext531__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext531 :: AVG GPU Core Frequency */
#define mtlgt3__ext531__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext531 :: LOAD STORE CACHE BYTE WRITE BANK0 XECORE7 */
#define mtlgt3__ext531__load_store_cache_byte_write_bank0_xecore7__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read

/* Ext531 :: LOAD STORE CACHE BYTE WRITE BANK1 XECORE7 */
#define mtlgt3__ext531__load_store_cache_byte_write_bank1_xecore7__read \
   mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read

/* Ext540 :: GPU Time Elapsed */
#define mtlgt3__ext540__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext540 :: GPU Core Clocks */
#define mtlgt3__ext540__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext540 :: AVG GPU Core Frequency */
#define mtlgt3__ext540__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext540 :: AVG GPU Core Frequency */
#define mtlgt3__ext540__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext540 :: SLM BYTE WRITE BANK0 XECORE0 */
#define mtlgt3__ext540__slm_byte_write_bank0_xecore0__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext540 :: SLM BYTE WRITE BANK1 XECORE0 */
#define mtlgt3__ext540__slm_byte_write_bank1_xecore0__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext541 :: GPU Time Elapsed */
#define mtlgt3__ext541__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext541 :: GPU Core Clocks */
#define mtlgt3__ext541__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext541 :: AVG GPU Core Frequency */
#define mtlgt3__ext541__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext541 :: AVG GPU Core Frequency */
#define mtlgt3__ext541__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext541 :: SLM BYTE WRITE BANK0 XECORE1 */
#define mtlgt3__ext541__slm_byte_write_bank0_xecore1__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext541 :: SLM BYTE WRITE BANK1 XECORE1 */
#define mtlgt3__ext541__slm_byte_write_bank1_xecore1__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext542 :: GPU Time Elapsed */
#define mtlgt3__ext542__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext542 :: GPU Core Clocks */
#define mtlgt3__ext542__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext542 :: AVG GPU Core Frequency */
#define mtlgt3__ext542__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext542 :: AVG GPU Core Frequency */
#define mtlgt3__ext542__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext542 :: SLM BYTE WRITE BANK0 XECORE2 */
#define mtlgt3__ext542__slm_byte_write_bank0_xecore2__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext542 :: SLM BYTE WRITE BANK1 XECORE2 */
#define mtlgt3__ext542__slm_byte_write_bank1_xecore2__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext543 :: GPU Time Elapsed */
#define mtlgt3__ext543__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext543 :: GPU Core Clocks */
#define mtlgt3__ext543__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext543 :: AVG GPU Core Frequency */
#define mtlgt3__ext543__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext543 :: AVG GPU Core Frequency */
#define mtlgt3__ext543__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext543 :: SLM BYTE WRITE BANK0 XECORE3 */
#define mtlgt3__ext543__slm_byte_write_bank0_xecore3__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext543 :: SLM BYTE WRITE BANK1 XECORE3 */
#define mtlgt3__ext543__slm_byte_write_bank1_xecore3__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext544 :: GPU Time Elapsed */
#define mtlgt3__ext544__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext544 :: GPU Core Clocks */
#define mtlgt3__ext544__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext544 :: AVG GPU Core Frequency */
#define mtlgt3__ext544__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext544 :: AVG GPU Core Frequency */
#define mtlgt3__ext544__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext544 :: SLM BYTE WRITE BANK0 XECORE4 */
#define mtlgt3__ext544__slm_byte_write_bank0_xecore4__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext544 :: SLM BYTE WRITE BANK1 XECORE4 */
#define mtlgt3__ext544__slm_byte_write_bank1_xecore4__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext545 :: GPU Time Elapsed */
#define mtlgt3__ext545__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext545 :: GPU Core Clocks */
#define mtlgt3__ext545__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext545 :: AVG GPU Core Frequency */
#define mtlgt3__ext545__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext545 :: AVG GPU Core Frequency */
#define mtlgt3__ext545__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext545 :: SLM BYTE WRITE BANK0 XECORE5 */
#define mtlgt3__ext545__slm_byte_write_bank0_xecore5__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext545 :: SLM BYTE WRITE BANK1 XECORE5 */
#define mtlgt3__ext545__slm_byte_write_bank1_xecore5__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext546 :: GPU Time Elapsed */
#define mtlgt3__ext546__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext546 :: GPU Core Clocks */
#define mtlgt3__ext546__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext546 :: AVG GPU Core Frequency */
#define mtlgt3__ext546__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext546 :: AVG GPU Core Frequency */
#define mtlgt3__ext546__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext546 :: SLM BYTE WRITE BANK0 XECORE6 */
#define mtlgt3__ext546__slm_byte_write_bank0_xecore6__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext546 :: SLM BYTE WRITE BANK1 XECORE6 */
#define mtlgt3__ext546__slm_byte_write_bank1_xecore6__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext547 :: GPU Time Elapsed */
#define mtlgt3__ext547__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext547 :: GPU Core Clocks */
#define mtlgt3__ext547__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext547 :: AVG GPU Core Frequency */
#define mtlgt3__ext547__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext547 :: AVG GPU Core Frequency */
#define mtlgt3__ext547__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext547 :: SLM BYTE WRITE BANK0 XECORE7 */
#define mtlgt3__ext547__slm_byte_write_bank0_xecore7__read \
   acmgt1__ext508__slm_byte_read_bank0_xecore0__read

/* Ext547 :: SLM BYTE WRITE BANK1 XECORE7 */
#define mtlgt3__ext547__slm_byte_write_bank1_xecore7__read \
   mtlgt2__ext508__slm_byte_read_bank0_xecore1__read

/* Ext604 :: GPU Time Elapsed */
#define mtlgt3__ext604__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext604 :: GPU Core Clocks */
#define mtlgt3__ext604__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext604 :: AVG GPU Core Frequency */
#define mtlgt3__ext604__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext604 :: AVG GPU Core Frequency */
#define mtlgt3__ext604__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE0 */
#define mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore0__read \
   bdw__render_basic__sampler0_busy__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE1 */
#define mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore1__read \
   bdw__render_basic__sampler1_busy__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE2 */
#define mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore2__read \
   bdw__render_basic__sampler0_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE3 */
#define mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore3__read \
   bdw__render_basic__sampler1_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE0 */
#define mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore0__read \
   bdw__render_pipe_profile__so_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE1 */
#define mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore1__read \
   bdw__render_pipe_profile__cl_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE2 */
#define mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore2__read \
   bdw__render_pipe_profile__sf_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE3 */
#define mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore3__read \
   bdw__render_pipe_profile__early_depth_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE4 */
#define mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore4__read \
   bdw__render_pipe_profile__bc_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE5 */
#define mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore5__read \
   bdw__render_pipe_profile__hi_depth_bottleneck__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE6 */
#define mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore6__read \
   bdw__render_pipe_profile__sf_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE7 */
#define mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore7__read \
   bdw__render_pipe_profile__cl_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE4 */
#define mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore4__read \
   bdw__render_pipe_profile__so_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE5 */
#define mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore5__read \
   bdw__render_pipe_profile__ds_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE6 */
#define mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore6__read \
   bdw__render_pipe_profile__hs_stall__read

/* Ext604 :: THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE7 */
#define mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore7__read \
   bdw__render_pipe_profile__vf_bottleneck__read

/* Ext1000 :: GPU Time Elapsed */
#define mtlgt3__ext1000__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1000 :: GPU Core Clocks */
#define mtlgt3__ext1000__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1000 :: AVG GPU Core Frequency */
#define mtlgt3__ext1000__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1000 :: AVG GPU Core Frequency */
#define mtlgt3__ext1000__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1000 :: XVE ACTIVE */
#define mtlgt3__ext1000__xve_active__read \
   bdw__render_basic__eu_active__read

/* Ext1000 :: XVE STALL */
#define mtlgt3__ext1000__xve_stall__read \
   bdw__render_basic__eu_stall__read

/* Ext1000 :: XVE THREADS OCCUPANCY ALL */
#define mtlgt3__ext1000__xve_threads_occupancy_all__read \
   acmgt1__ext1000__xve_threads_occupancy_all__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL */
#define mtlgt3__ext1000__xve_inst_executed_alu0_all__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL */
#define mtlgt3__ext1000__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL */
#define mtlgt3__ext1000__xve_inst_executed_alu1_all__read \
   hsw__render_basic__hs_threads__read

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL */
#define mtlgt3__ext1000__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED XMX ALL */
#define mtlgt3__ext1000__xve_inst_executed_xmx_all__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1000 :: XVE INST EXECUTED XMX ALL */
#define mtlgt3__ext1000__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED SEND ALL */
#define mtlgt3__ext1000__xve_inst_executed_send_all__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1000 :: XVE INST EXECUTED SEND ALL */
#define mtlgt3__ext1000__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL */
#define mtlgt3__ext1000__xve_inst_executed_control_all__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL */
#define mtlgt3__ext1000__xve_inst_executed_control_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE */
#define mtlgt3__ext1000__xve_pipe_alu0_and_alu1_active__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE */
#define mtlgt3__ext1000__xve_pipe_alu0_and_xmx_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1000 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define mtlgt3__ext1000__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1000 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define mtlgt3__ext1000__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1000 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define mtlgt3__ext1000__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1000 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define mtlgt3__ext1000__xve_inst_executed_send_all_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1000 :: XVE INST EXECUTED CONTROL ALL UTILIZATION */
#define mtlgt3__ext1000__xve_inst_executed_control_all_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1000 :: XVE ACTIVE CYCLES */
#define mtlgt3__ext1000__xve_active_cycles__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1000 :: XVE ACTIVE CYCLES */
#define mtlgt3__ext1000__xve_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE STALL CYCLES */
#define mtlgt3__ext1000__xve_stall_cycles__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1000 :: XVE STALL CYCLES */
#define mtlgt3__ext1000__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE THREADS OCCUPANCY CYCLES ALL */
#define mtlgt3__ext1000__xve_threads_occupancy_cycles_all__read \
   acmgt1__ext1000__xve_threads_occupancy_cycles_all__read

/* Ext1000 :: XVE THREADS OCCUPANCY CYCLES ALL */
#define mtlgt3__ext1000__xve_threads_occupancy_cycles_all__max \
   acmgt1__ext1000__xve_threads_occupancy_cycles_all__max

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
#define mtlgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1000 :: XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES */
#define mtlgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define mtlgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read \
   hsw__render_basic__ds_threads__read

/* Ext1000 :: XVE PIPE ALU0 AND XMX ACTIVE CYCLES */
#define mtlgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: GPU Time Elapsed */
#define mtlgt3__ext1001__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1001 :: GPU Core Clocks */
#define mtlgt3__ext1001__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1001 :: AVG GPU Core Frequency */
#define mtlgt3__ext1001__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1001 :: AVG GPU Core Frequency */
#define mtlgt3__ext1001__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1001 :: XVE INST EXECUTED ALU0 VS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU0 VS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 HS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_hs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU0 HS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 DS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_ds__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 DS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 FS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_ps__read \
   hsw__render_basic__hs_threads__read

/* Ext1001 :: XVE INST EXECUTED ALU0 FS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 CS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_cs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 CS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_async_cs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS */
#define mtlgt3__ext1001__xve_inst_executed_alu0_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 VS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_vs__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1001 :: XVE INST EXECUTED ALU1 VS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 HS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_hs__read \
   hsw__render_basic__ds_threads__read

/* Ext1001 :: XVE INST EXECUTED ALU1 HS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 DS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_ds__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1001 :: XVE INST EXECUTED ALU1 DS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 FS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_ps__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1001 :: XVE INST EXECUTED ALU1 FS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 CS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_cs__read \
   acmgt1__ext1001__xve_inst_executed_alu1_cs__read

/* Ext1001 :: XVE INST EXECUTED ALU1 CS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_async_cs__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS */
#define mtlgt3__ext1001__xve_inst_executed_alu1_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1001 :: XVE INST EXECUTED ALU0 VS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu0_vs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 HS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu0_hs_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1001 :: XVE INST EXECUTED ALU0 DS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu0_ds_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 FS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu0_ps_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 CS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu0_cs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1001 :: XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu0_async_cs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 VS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu1_vs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1001 :: XVE INST EXECUTED ALU1 HS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu1_hs_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 DS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu1_ds_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1001 :: XVE INST EXECUTED ALU1 FS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu1_ps_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 CS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu1_cs_utilization__read \
   bdw__render_basic__ps_send_active__read

/* Ext1001 :: XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION */
#define mtlgt3__ext1001__xve_inst_executed_alu1_async_cs_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1002 :: GPU Time Elapsed */
#define mtlgt3__ext1002__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1002 :: GPU Core Clocks */
#define mtlgt3__ext1002__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1002 :: AVG GPU Core Frequency */
#define mtlgt3__ext1002__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1002 :: AVG GPU Core Frequency */
#define mtlgt3__ext1002__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS UTILIZATION */
#define mtlgt3__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS UTILIZATION */
#define mtlgt3__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS UTILIZATION */
#define mtlgt3__ext1002__xve_inst_executed_send_rt_ahs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS UTILIZATION */
#define mtlgt3__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS UTILIZATION */
#define mtlgt3__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS UTILIZATION */
#define mtlgt3__ext1002__xve_inst_executed_send_rt_chs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS UTILIZATION */
#define mtlgt3__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS UTILIZATION */
#define mtlgt3__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1002 :: XVE INST EXECUTED SEND RT MS UTILIZATION */
#define mtlgt3__ext1002__xve_inst_executed_send_rt_ms_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS */
#define mtlgt3__ext1002__xve_inst_executed_alu0_rt_ahs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT AHS */
#define mtlgt3__ext1002__xve_inst_executed_alu0_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS */
#define mtlgt3__ext1002__xve_inst_executed_alu1_rt_ahs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT AHS */
#define mtlgt3__ext1002__xve_inst_executed_alu1_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS */
#define mtlgt3__ext1002__xve_inst_executed_send_rt_ahs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1002 :: XVE INST EXECUTED SEND RT AHS */
#define mtlgt3__ext1002__xve_inst_executed_send_rt_ahs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS */
#define mtlgt3__ext1002__xve_inst_executed_alu0_rt_chs__read \
   hsw__render_basic__hs_threads__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT CHS */
#define mtlgt3__ext1002__xve_inst_executed_alu0_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS */
#define mtlgt3__ext1002__xve_inst_executed_alu1_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT CHS */
#define mtlgt3__ext1002__xve_inst_executed_alu1_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS */
#define mtlgt3__ext1002__xve_inst_executed_send_rt_chs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1002 :: XVE INST EXECUTED SEND RT CHS */
#define mtlgt3__ext1002__xve_inst_executed_send_rt_chs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS */
#define mtlgt3__ext1002__xve_inst_executed_alu0_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1002 :: XVE INST EXECUTED ALU0 RT MS */
#define mtlgt3__ext1002__xve_inst_executed_alu0_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS */
#define mtlgt3__ext1002__xve_inst_executed_alu1_rt_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1002 :: XVE INST EXECUTED ALU1 RT MS */
#define mtlgt3__ext1002__xve_inst_executed_alu1_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1002 :: XVE INST EXECUTED SEND RT MS */
#define mtlgt3__ext1002__xve_inst_executed_send_rt_ms__read \
   hsw__render_basic__ds_threads__read

/* Ext1002 :: XVE INST EXECUTED SEND RT MS */
#define mtlgt3__ext1002__xve_inst_executed_send_rt_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: GPU Time Elapsed */
#define mtlgt3__ext1003__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1003 :: GPU Core Clocks */
#define mtlgt3__ext1003__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1003 :: AVG GPU Core Frequency */
#define mtlgt3__ext1003__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1003 :: AVG GPU Core Frequency */
#define mtlgt3__ext1003__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1003 :: XVE ACTIVE */
#define mtlgt3__ext1003__xve_active__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1003 :: XVE ACTIVE DS */
#define mtlgt3__ext1003__xve_active_ds__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1003 :: XVE ACTIVE HS */
#define mtlgt3__ext1003__xve_active_hs__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1003 :: XVE ACTIVE FS */
#define mtlgt3__ext1003__xve_active_ps__read \
   bdw__render_basic__eu_stall__read

/* Ext1003 :: XVE ACTIVE VS */
#define mtlgt3__ext1003__xve_active_vs__read \
   bdw__render_basic__eu_active__read

/* Ext1003 :: XVE ACTIVE ASYNC CS */
#define mtlgt3__ext1003__xve_active_async_cs__read \
   bdw__render_basic__vs_send_active__read

/* Ext1003 :: XVE ACTIVE CS */
#define mtlgt3__ext1003__xve_active_cs__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1003 :: XVE ACTIVE MS */
#define mtlgt3__ext1003__xve_active_ms__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1003 :: XVE ACTIVE TS */
#define mtlgt3__ext1003__xve_active_ts__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1003 :: XVE ACTIVE RT */
#define mtlgt3__ext1003__xve_active_rt__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1003 :: XVE ACTIVE CYCLES */
#define mtlgt3__ext1003__xve_active_cycles__read \
   hsw__render_basic__ds_threads__read

/* Ext1003 :: XVE ACTIVE CYCLES */
#define mtlgt3__ext1003__xve_active_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES ASYNC CS */
#define mtlgt3__ext1003__xve_active_cycles_async_cs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1003 :: XVE ACTIVE CYCLES ASYNC CS */
#define mtlgt3__ext1003__xve_active_cycles_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES CS */
#define mtlgt3__ext1003__xve_active_cycles_cs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1003 :: XVE ACTIVE CYCLES CS */
#define mtlgt3__ext1003__xve_active_cycles_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES HS */
#define mtlgt3__ext1003__xve_active_cycles_hs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1003 :: XVE ACTIVE CYCLES FS */
#define mtlgt3__ext1003__xve_active_cycles_ps__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1003 :: XVE ACTIVE CYCLES FS */
#define mtlgt3__ext1003__xve_active_cycles_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES VS */
#define mtlgt3__ext1003__xve_active_cycles_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1003 :: XVE ACTIVE CYCLES VS */
#define mtlgt3__ext1003__xve_active_cycles_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES DS */
#define mtlgt3__ext1003__xve_active_cycles_ds__read \
   hsw__render_basic__hs_threads__read

/* Ext1003 :: XVE ACTIVE CYCLES DS */
#define mtlgt3__ext1003__xve_active_cycles_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES MS */
#define mtlgt3__ext1003__xve_active_cycles_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1003 :: XVE ACTIVE CYCLES MS */
#define mtlgt3__ext1003__xve_active_cycles_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES TS */
#define mtlgt3__ext1003__xve_active_cycles_ts__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1003 :: XVE ACTIVE CYCLES TS */
#define mtlgt3__ext1003__xve_active_cycles_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1003 :: XVE ACTIVE CYCLES RT */
#define mtlgt3__ext1003__xve_active_cycles_rt__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1003 :: XVE ACTIVE CYCLES RT */
#define mtlgt3__ext1003__xve_active_cycles_rt__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: GPU Time Elapsed */
#define mtlgt3__ext1004__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1004 :: GPU Core Clocks */
#define mtlgt3__ext1004__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1004 :: AVG GPU Core Frequency */
#define mtlgt3__ext1004__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1004 :: AVG GPU Core Frequency */
#define mtlgt3__ext1004__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1004 :: XVE STALL */
#define mtlgt3__ext1004__xve_stall__read \
   bdw__render_basic__eu_active__read

/* Ext1004 :: XVE STALL ASYNC CS */
#define mtlgt3__ext1004__xve_stall_async_cs__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1004 :: XVE STALL CS */
#define mtlgt3__ext1004__xve_stall_cs__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1004 :: XVE STALL DS */
#define mtlgt3__ext1004__xve_stall_ds__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1004 :: XVE STALL HS */
#define mtlgt3__ext1004__xve_stall_hs__read \
   bdw__render_basic__vs_send_active__read

/* Ext1004 :: XVE STALL MS */
#define mtlgt3__ext1004__xve_stall_ms__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1004 :: XVE STALL FS */
#define mtlgt3__ext1004__xve_stall_ps__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1004 :: XVE STALL TS */
#define mtlgt3__ext1004__xve_stall_ts__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1004 :: XVE STALL VS */
#define mtlgt3__ext1004__xve_stall_vs__read \
   bdw__render_basic__eu_stall__read

/* Ext1004 :: XVE STALL RT */
#define mtlgt3__ext1004__xve_stall_rt__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1004 :: XVE STALL CYCLES */
#define mtlgt3__ext1004__xve_stall_cycles__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1004 :: XVE STALL CYCLES */
#define mtlgt3__ext1004__xve_stall_cycles__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES ASYNC CS */
#define mtlgt3__ext1004__xve_stall_cycles_async_cs__read \
   hsw__render_basic__ds_threads__read

/* Ext1004 :: XVE STALL CYCLES ASYNC CS */
#define mtlgt3__ext1004__xve_stall_cycles_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES CS */
#define mtlgt3__ext1004__xve_stall_cycles_cs__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1004 :: XVE STALL CYCLES CS */
#define mtlgt3__ext1004__xve_stall_cycles_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES DS */
#define mtlgt3__ext1004__xve_stall_cycles_ds__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1004 :: XVE STALL CYCLES DS */
#define mtlgt3__ext1004__xve_stall_cycles_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES HS */
#define mtlgt3__ext1004__xve_stall_cycles_hs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1004 :: XVE STALL CYCLES HS */
#define mtlgt3__ext1004__xve_stall_cycles_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES MS */
#define mtlgt3__ext1004__xve_stall_cycles_ms__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1004 :: XVE STALL CYCLES MS */
#define mtlgt3__ext1004__xve_stall_cycles_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES FS */
#define mtlgt3__ext1004__xve_stall_cycles_ps__read \
   hsw__render_basic__hs_threads__read

/* Ext1004 :: XVE STALL CYCLES FS */
#define mtlgt3__ext1004__xve_stall_cycles_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES TS */
#define mtlgt3__ext1004__xve_stall_cycles_ts__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1004 :: XVE STALL CYCLES TS */
#define mtlgt3__ext1004__xve_stall_cycles_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES VS */
#define mtlgt3__ext1004__xve_stall_cycles_vs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1004 :: XVE STALL CYCLES VS */
#define mtlgt3__ext1004__xve_stall_cycles_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1004 :: XVE STALL CYCLES RT */
#define mtlgt3__ext1004__xve_stall_cycles_rt__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1004 :: XVE STALL CYCLES RT */
#define mtlgt3__ext1004__xve_stall_cycles_rt__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: GPU Time Elapsed */
#define mtlgt3__ext1005__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1005 :: GPU Core Clocks */
#define mtlgt3__ext1005__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1005 :: AVG GPU Core Frequency */
#define mtlgt3__ext1005__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1005 :: AVG GPU Core Frequency */
#define mtlgt3__ext1005__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL */
#define mtlgt3__ext1005__xve_inst_executed_alu0_all__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL */
#define mtlgt3__ext1005__xve_inst_executed_alu0_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP16 */
#define mtlgt3__ext1005__xve_inst_executed_fp16__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1005 :: XVE INST EXECUTED FP16 */
#define mtlgt3__ext1005__xve_inst_executed_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP32 */
#define mtlgt3__ext1005__xve_inst_executed_fp32__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1005 :: XVE INST EXECUTED FP32 */
#define mtlgt3__ext1005__xve_inst_executed_fp32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED FP64 */
#define mtlgt3__ext1005__xve_inst_executed_fp64__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1005 :: XVE INST EXECUTED FP64 */
#define mtlgt3__ext1005__xve_inst_executed_fp64__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL */
#define mtlgt3__ext1005__xve_inst_executed_alu1_all__read \
   acmgt1__ext1001__xve_inst_executed_alu1_cs__read

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL */
#define mtlgt3__ext1005__xve_inst_executed_alu1_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED INT16 */
#define mtlgt3__ext1005__xve_inst_executed_int16__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1005 :: XVE INST EXECUTED INT16 */
#define mtlgt3__ext1005__xve_inst_executed_int16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED INT32 */
#define mtlgt3__ext1005__xve_inst_executed_int32__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1005 :: XVE INST EXECUTED INT32 */
#define mtlgt3__ext1005__xve_inst_executed_int32__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED MATH */
#define mtlgt3__ext1005__xve_inst_executed_math__read \
   hsw__render_basic__hs_threads__read

/* Ext1005 :: XVE INST EXECUTED MATH */
#define mtlgt3__ext1005__xve_inst_executed_math__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX ALL */
#define mtlgt3__ext1005__xve_inst_executed_xmx_all__read \
   acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read

/* Ext1005 :: XVE INST EXECUTED XMX ALL */
#define mtlgt3__ext1005__xve_inst_executed_xmx_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX BF16 */
#define mtlgt3__ext1005__xve_inst_executed_xmx_bf16__read \
   hsw__render_basic__ds_threads__read

/* Ext1005 :: XVE INST EXECUTED XMX BF16 */
#define mtlgt3__ext1005__xve_inst_executed_xmx_bf16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX FP16 */
#define mtlgt3__ext1005__xve_inst_executed_xmx_fp16__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1005 :: XVE INST EXECUTED XMX FP16 */
#define mtlgt3__ext1005__xve_inst_executed_xmx_fp16__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED XMX INT8 */
#define mtlgt3__ext1005__xve_inst_executed_xmx_int8__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1005 :: XVE INST EXECUTED XMX INT8 */
#define mtlgt3__ext1005__xve_inst_executed_xmx_int8__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1005 :: XVE INST EXECUTED ALU0 ALL UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_alu0_all_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1005 :: XVE INST EXECUTED FP16 UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_fp16_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1005 :: XVE INST EXECUTED FP32 UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_fp32_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1005 :: XVE INST EXECUTED FP64 UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_fp64_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1005 :: XVE INST EXECUTED ALU1 ALL UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_alu1_all_utilization__read \
   bdw__render_basic__ps_send_active__read

/* Ext1005 :: XVE INST EXECUTED INT16 UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_int16_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1005 :: XVE INST EXECUTED INT32 UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_int32_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1005 :: XVE INST EXECUTED MATH UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_math_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1005 :: XVE INST EXECUTED XMX ALL UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_xmx_all_utilization__read \
   bdw__render_basic__ps_eu_both_fpu_active__read

/* Ext1005 :: XVE INST EXECUTED XMX BF16 UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_xmx_bf16_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1005 :: XVE INST EXECUTED XMX FP16 UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_xmx_fp16_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1005 :: XVE INST EXECUTED XMX INT8 UTILIZATION */
#define mtlgt3__ext1005__xve_inst_executed_xmx_int8_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1006 :: GPU Time Elapsed */
#define mtlgt3__ext1006__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1006 :: GPU Core Clocks */
#define mtlgt3__ext1006__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1006 :: AVG GPU Core Frequency */
#define mtlgt3__ext1006__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1006 :: AVG GPU Core Frequency */
#define mtlgt3__ext1006__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1006 :: XVE INST EXECUTED SEND ALL */
#define mtlgt3__ext1006__xve_inst_executed_send_all__read \
   acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND ALL */
#define mtlgt3__ext1006__xve_inst_executed_send_all__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS */
#define mtlgt3__ext1006__xve_inst_executed_send_async_cs__read \
   hsw__render_basic__ds_threads__read

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS */
#define mtlgt3__ext1006__xve_inst_executed_send_async_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND CS */
#define mtlgt3__ext1006__xve_inst_executed_send_cs__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1006 :: XVE INST EXECUTED SEND CS */
#define mtlgt3__ext1006__xve_inst_executed_send_cs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND DS */
#define mtlgt3__ext1006__xve_inst_executed_send_ds__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1006 :: XVE INST EXECUTED SEND DS */
#define mtlgt3__ext1006__xve_inst_executed_send_ds__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND GS */
#define mtlgt3__ext1006__xve_inst_executed_send_gs__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1006 :: XVE INST EXECUTED SEND GS */
#define mtlgt3__ext1006__xve_inst_executed_send_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND HS */
#define mtlgt3__ext1006__xve_inst_executed_send_hs__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1006 :: XVE INST EXECUTED SEND HS */
#define mtlgt3__ext1006__xve_inst_executed_send_hs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND MS */
#define mtlgt3__ext1006__xve_inst_executed_send_ms__read \
   hsw__render_basic__hs_threads__read

/* Ext1006 :: XVE INST EXECUTED SEND MS */
#define mtlgt3__ext1006__xve_inst_executed_send_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND FS */
#define mtlgt3__ext1006__xve_inst_executed_send_ps__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1006 :: XVE INST EXECUTED SEND FS */
#define mtlgt3__ext1006__xve_inst_executed_send_ps__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND TS */
#define mtlgt3__ext1006__xve_inst_executed_send_ts__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND TS */
#define mtlgt3__ext1006__xve_inst_executed_send_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND VS */
#define mtlgt3__ext1006__xve_inst_executed_send_vs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1006 :: XVE INST EXECUTED SEND VS */
#define mtlgt3__ext1006__xve_inst_executed_send_vs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1006 :: XVE INST EXECUTED SEND ALL UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_all_utilization__read \
   bdw__render_basic__ps_fpu1_active__read

/* Ext1006 :: XVE INST EXECUTED SEND ASYNC CS UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_async_cs_utilization__read \
   bdw__render_basic__ps_fpu0_active__read

/* Ext1006 :: XVE INST EXECUTED SEND CS UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_cs_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1006 :: XVE INST EXECUTED SEND DS UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_ds_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1006 :: XVE INST EXECUTED SEND GS UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_gs_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1006 :: XVE INST EXECUTED SEND HS UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_hs_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1006 :: XVE INST EXECUTED SEND MS UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_ms_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1006 :: XVE INST EXECUTED SEND FS UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_ps_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1006 :: XVE INST EXECUTED SEND TS UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_ts_utilization__read \
   bdw__render_basic__eu_stall__read

/* Ext1006 :: XVE INST EXECUTED SEND VS UTILIZATION */
#define mtlgt3__ext1006__xve_inst_executed_send_vs_utilization__read \
   bdw__render_basic__eu_active__read

/* Ext1007 :: GPU Time Elapsed */
#define mtlgt3__ext1007__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1007 :: GPU Core Clocks */
#define mtlgt3__ext1007__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1007 :: AVG GPU Core Frequency */
#define mtlgt3__ext1007__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1007 :: AVG GPU Core Frequency */
#define mtlgt3__ext1007__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1007 :: XVE ACTIVE GS */
#define mtlgt3__ext1007__xve_active_gs__read \
   bdw__render_basic__eu_active__read

/* Ext1007 :: XVE STALL GS */
#define mtlgt3__ext1007__xve_stall_gs__read \
   bdw__render_basic__eu_stall__read

/* Ext1007 :: XVE INST EXECUTED ALU0 GS */
#define mtlgt3__ext1007__xve_inst_executed_alu0_gs__read \
   hsw__render_basic__hs_threads__read

/* Ext1007 :: XVE INST EXECUTED ALU0 GS */
#define mtlgt3__ext1007__xve_inst_executed_alu0_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 GS */
#define mtlgt3__ext1007__xve_inst_executed_alu1_gs__read \
   acmgt1__ext1000__xve_inst_executed_alu0_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 GS */
#define mtlgt3__ext1007__xve_inst_executed_alu1_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE ACTIVE CYCLES GS */
#define mtlgt3__ext1007__xve_active_cycles_gs__read \
   acmgt1__ext1000__xve_active_cycles__read

/* Ext1007 :: XVE ACTIVE CYCLES GS */
#define mtlgt3__ext1007__xve_active_cycles_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE STALL CYCLES GS */
#define mtlgt3__ext1007__xve_stall_cycles_gs__read \
   acmgt1__ext1000__xve_stall_cycles__read

/* Ext1007 :: XVE STALL CYCLES GS */
#define mtlgt3__ext1007__xve_stall_cycles_gs__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 MS */
#define mtlgt3__ext1007__xve_inst_executed_alu0_ms__read \
   acmgt1__compute_overview__xve_inst_executed_control_all__read

/* Ext1007 :: XVE INST EXECUTED ALU0 MS */
#define mtlgt3__ext1007__xve_inst_executed_alu0_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 TS */
#define mtlgt3__ext1007__xve_inst_executed_alu0_ts__read \
   acmgt1__compute_overview__xve_inst_executed_send_all__read

/* Ext1007 :: XVE INST EXECUTED ALU0 TS */
#define mtlgt3__ext1007__xve_inst_executed_alu0_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 MS */
#define mtlgt3__ext1007__xve_inst_executed_alu1_ms__read \
   acmgt1__compute_overview__xve_inst_executed_xmx_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 MS */
#define mtlgt3__ext1007__xve_inst_executed_alu1_ms__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU1 TS */
#define mtlgt3__ext1007__xve_inst_executed_alu1_ts__read \
   acmgt1__compute_overview__xve_inst_executed_alu1_all__read

/* Ext1007 :: XVE INST EXECUTED ALU1 TS */
#define mtlgt3__ext1007__xve_inst_executed_alu1_ts__max \
   acmgt1__compute_overview__xve_inst_executed_alu0_all__max

/* Ext1007 :: XVE INST EXECUTED ALU0 GS UTILIZATION */
#define mtlgt3__ext1007__xve_inst_executed_alu0_gs_utilization__read \
   bdw__render_basic__vs_fpu0_active__read

/* Ext1007 :: XVE INST EXECUTED ALU1 GS UTILIZATION */
#define mtlgt3__ext1007__xve_inst_executed_alu1_gs_utilization__read \
   bdw__render_basic__eu_fpu_both_active__read

/* Ext1007 :: XVE INST EXECUTED ALU0 MS UTILIZATION */
#define mtlgt3__ext1007__xve_inst_executed_alu0_ms_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read

/* Ext1007 :: XVE INST EXECUTED ALU0 TS UTILIZATION */
#define mtlgt3__ext1007__xve_inst_executed_alu0_ts_utilization__read \
   bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read

/* Ext1007 :: XVE INST EXECUTED ALU1 MS UTILIZATION */
#define mtlgt3__ext1007__xve_inst_executed_alu1_ms_utilization__read \
   bdw__render_basic__vs_send_active__read

/* Ext1007 :: XVE INST EXECUTED ALU1 TS UTILIZATION */
#define mtlgt3__ext1007__xve_inst_executed_alu1_ts_utilization__read \
   bdw__render_basic__vs_fpu1_active__read

/* Ext1010 :: GPU Time Elapsed */
#define mtlgt3__ext1010__gpu_time__read \
   hsw__render_basic__gpu_time__read

/* Ext1010 :: GPU Core Clocks */
#define mtlgt3__ext1010__gpu_core_clocks__read \
   bdw__render_basic__gpu_core_clocks__read

/* Ext1010 :: AVG GPU Core Frequency */
#define mtlgt3__ext1010__avg_gpu_core_frequency__read \
   bdw__render_basic__avg_gpu_core_frequency__read

/* Ext1010 :: AVG GPU Core Frequency */
#define mtlgt3__ext1010__avg_gpu_core_frequency__max \
   hsw__render_basic__avg_gpu_core_frequency__max

/* Ext1010 :: SAMPLER 2X2 READ */
#define mtlgt3__ext1010__sampler_2_x2_read__read \
   bdw__render_basic__sampler_texels__read

/* Ext1010 :: PIXEL WRITE */
#define mtlgt3__ext1010__pixel_write__read \
   bdw__render_basic__samples_written__read

/* Ext1010 :: PIXEL BLEND */
#define mtlgt3__ext1010__pixel_blend__read \
   bdw__render_basic__samples_blended__read

/* Ext1010 :: RASTERIZER SAMPLE OUTPUT */
#define mtlgt3__ext1010__rasterizer_sample_output__read \
   bdw__render_basic__rasterized_pixels__read

/* Ext1010 :: POSTPS DEPTH STENCIL ALPHA TEST FAIL */
#define mtlgt3__ext1010__postps_depth_stencil_alpha_test_fail__read \
   bdw__render_basic__pixels_failing_post_ps_tests__read

static const struct intel_perf_query_counter_data counters[] = {
   [0] = {
      .name_idx = 27044,
      .desc_idx = 129674,
      .symbol_name_idx = 26572,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_NS,
   },
   [1] = {
      .name_idx = 23205,
      .desc_idx = 120712,
      .symbol_name_idx = 26558,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [2] = {
      .name_idx = 4109,
      .desc_idx = 124,
      .symbol_name_idx = 4155,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_HZ,
   },
   [3] = {
      .name_idx = 154704,
      .desc_idx = 129527,
      .symbol_name_idx = 132480,
      .category_idx = 644,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
   },
   [4] = {
      .name_idx = 127006,
      .desc_idx = 126889,
      .symbol_name_idx = 31222,
      .category_idx = 434,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
   },
   [5] = {
      .name_idx = 127134,
      .desc_idx = 127046,
      .symbol_name_idx = 18440,
      .category_idx = 481,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
   },
   [6] = {
      .name_idx = 27218,
      .desc_idx = 127208,
      .symbol_name_idx = 26812,
      .category_idx = 533,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
   },
   [7] = {
      .name_idx = 21370,
      .desc_idx = 127128,
      .symbol_name_idx = 69132,
      .category_idx = 508,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
   },
   [8] = {
      .name_idx = 9249,
      .desc_idx = 126810,
      .symbol_name_idx = 9369,
      .category_idx = 410,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
   },
   [9] = {
      .name_idx = 23196,
      .desc_idx = 90717,
      .symbol_name_idx = 26540,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [10] = {
      .name_idx = 20009,
      .desc_idx = 90465,
      .symbol_name_idx = 19897,
      .category_idx = 384,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [11] = {
      .name_idx = 20411,
      .desc_idx = 90636,
      .symbol_name_idx = 20399,
      .category_idx = 384,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [12] = {
      .name_idx = 154416,
      .desc_idx = 115099,
      .symbol_name_idx = 132369,
      .category_idx = 644,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [13] = {
      .name_idx = 154323,
      .desc_idx = 42530,
      .symbol_name_idx = 132380,
      .category_idx = 644,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [14] = {
      .name_idx = 154348,
      .desc_idx = 42657,
      .symbol_name_idx = 132410,
      .category_idx = 644,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [15] = {
      .name_idx = 154429,
      .desc_idx = 115197,
      .symbol_name_idx = 132400,
      .category_idx = 644,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [16] = {
      .name_idx = 126979,
      .desc_idx = 60920,
      .symbol_name_idx = 31129,
      .category_idx = 434,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [17] = {
      .name_idx = 126915,
      .desc_idx = 41540,
      .symbol_name_idx = 31140,
      .category_idx = 434,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [18] = {
      .name_idx = 126941,
      .desc_idx = 41668,
      .symbol_name_idx = 31170,
      .category_idx = 434,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [19] = {
      .name_idx = 126993,
      .desc_idx = 61019,
      .symbol_name_idx = 31160,
      .category_idx = 434,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [20] = {
      .name_idx = 127107,
      .desc_idx = 61545,
      .symbol_name_idx = 18347,
      .category_idx = 481,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [21] = {
      .name_idx = 127043,
      .desc_idx = 41785,
      .symbol_name_idx = 18358,
      .category_idx = 481,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [22] = {
      .name_idx = 127069,
      .desc_idx = 41916,
      .symbol_name_idx = 18388,
      .category_idx = 481,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [23] = {
      .name_idx = 127121,
      .desc_idx = 61647,
      .symbol_name_idx = 18378,
      .category_idx = 481,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [24] = {
      .name_idx = 27154,
      .desc_idx = 63160,
      .symbol_name_idx = 26727,
      .category_idx = 533,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [25] = {
      .name_idx = 27061,
      .desc_idx = 42283,
      .symbol_name_idx = 26738,
      .category_idx = 533,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [26] = {
      .name_idx = 27086,
      .desc_idx = 42412,
      .symbol_name_idx = 26768,
      .category_idx = 533,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [27] = {
      .name_idx = 27167,
      .desc_idx = 63260,
      .symbol_name_idx = 26758,
      .category_idx = 533,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [28] = {
      .name_idx = 9121,
      .desc_idx = 60733,
      .symbol_name_idx = 9258,
      .category_idx = 410,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [29] = {
      .name_idx = 9042,
      .desc_idx = 41295,
      .symbol_name_idx = 9269,
      .category_idx = 410,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [30] = {
      .name_idx = 9067,
      .desc_idx = 41423,
      .symbol_name_idx = 9299,
      .category_idx = 410,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [31] = {
      .name_idx = 9134,
      .desc_idx = 60832,
      .symbol_name_idx = 9289,
      .category_idx = 410,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [32] = {
      .name_idx = 21306,
      .desc_idx = 62672,
      .symbol_name_idx = 69003,
      .category_idx = 508,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [33] = {
      .name_idx = 21208,
      .desc_idx = 42036,
      .symbol_name_idx = 69014,
      .category_idx = 508,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [34] = {
      .name_idx = 21233,
      .desc_idx = 42165,
      .symbol_name_idx = 69062,
      .category_idx = 508,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [35] = {
      .name_idx = 21319,
      .desc_idx = 62878,
      .symbol_name_idx = 69052,
      .category_idx = 508,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [36] = {
      .name_idx = 115479,
      .desc_idx = 72775,
      .symbol_name_idx = 110255,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [37] = {
      .name_idx = 115537,
      .desc_idx = 72916,
      .symbol_name_idx = 110504,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [38] = {
      .name_idx = 116016,
      .desc_idx = 73464,
      .symbol_name_idx = 111816,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [39] = {
      .name_idx = 115458,
      .desc_idx = 72701,
      .symbol_name_idx = 110236,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [40] = {
      .name_idx = 115516,
      .desc_idx = 72842,
      .symbol_name_idx = 110485,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [41] = {
      .name_idx = 115494,
      .desc_idx = 128932,
      .symbol_name_idx = 110290,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_TEXELS,
   },
   [42] = {
      .name_idx = 115552,
      .desc_idx = 129008,
      .symbol_name_idx = 110539,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_TEXELS,
   },
   [43] = {
      .name_idx = 115897,
      .desc_idx = 128853,
      .symbol_name_idx = 111802,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_TEXELS,
   },
   [44] = {
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      .desc_idx = 121652,
      .symbol_name_idx = 42378,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [45] = {
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      .desc_idx = 127707,
      .symbol_name_idx = 30893,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
   [46] = {
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      .desc_idx = 127637,
      .symbol_name_idx = 19747,
      .category_idx = 207,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
   [47] = {
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      .desc_idx = 128312,
      .symbol_name_idx = 111844,
      .category_idx = 38,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
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      .desc_idx = 127790,
      .symbol_name_idx = 4060,
      .category_idx = 130,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
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      .desc_idx = 128026,
      .symbol_name_idx = 68958,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
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      .desc_idx = 127954,
      .symbol_name_idx = 68937,
      .category_idx = 130,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
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      .desc_idx = 128393,
      .symbol_name_idx = 111862,
      .category_idx = 130,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
   [52] = {
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      .desc_idx = 126646,
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      .category_idx = 130,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
   [53] = {
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      .desc_idx = 120940,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [54] = {
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      .desc_idx = 121461,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [55] = {
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      .desc_idx = 121553,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [56] = {
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      .desc_idx = 121372,
      .symbol_name_idx = 27120,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [57] = {
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      .desc_idx = 120794,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [58] = {
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      .desc_idx = 122001,
      .symbol_name_idx = 27486,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [59] = {
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      .desc_idx = 125085,
      .symbol_name_idx = 61601,
      .category_idx = 1096,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [60] = {
      .name_idx = 48868,
      .desc_idx = 128670,
      .symbol_name_idx = 61630,
      .category_idx = 1096,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [61] = {
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      .desc_idx = 121084,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [62] = {
      .name_idx = 21276,
      .desc_idx = 129870,
      .symbol_name_idx = 68981,
      .category_idx = 508,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_US,
   },
   [63] = {
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      .desc_idx = 129962,
      .symbol_name_idx = 132347,
      .category_idx = 644,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_US,
   },
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      .desc_idx = 129916,
      .symbol_name_idx = 26705,
      .category_idx = 533,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_US,
   },
   [65] = {
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      .desc_idx = 129822,
      .symbol_name_idx = 18325,
      .category_idx = 481,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_US,
   },
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      .desc_idx = 129777,
      .symbol_name_idx = 31107,
      .category_idx = 434,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_US,
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      .desc_idx = 129732,
      .symbol_name_idx = 9236,
      .category_idx = 410,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_US,
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   [68] = {
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      .desc_idx = 73390,
      .symbol_name_idx = 111728,
      .category_idx = 1135,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
   [69] = {
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      .desc_idx = 90558,
      .symbol_name_idx = 20335,
      .category_idx = 384,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 129303,
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      .category_idx = 1013,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .desc_idx = 129450,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .desc_idx = 129252,
      .symbol_name_idx = 130429,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .desc_idx = 129303,
      .symbol_name_idx = 131116,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [74] = {
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      .desc_idx = 129450,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [75] = {
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      .desc_idx = 120859,
      .symbol_name_idx = 112143,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [76] = {
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      .desc_idx = 126737,
      .symbol_name_idx = 112156,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [77] = {
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      .desc_idx = 120712,
      .symbol_name_idx = 26548,
      .category_idx = 676,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_CYCLES,
   },
   [78] = {
      .name_idx = 21095,
      .desc_idx = 119477,
      .symbol_name_idx = 20586,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [79] = {
      .name_idx = 21048,
      .desc_idx = 119240,
      .symbol_name_idx = 20508,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [80] = {
      .name_idx = 21111,
      .desc_idx = 119537,
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      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [81] = {
      .name_idx = 21062,
      .desc_idx = 119298,
      .symbol_name_idx = 20537,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [82] = {
      .name_idx = 21077,
      .desc_idx = 119415,
      .symbol_name_idx = 20568,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [83] = {
      .name_idx = 21032,
      .desc_idx = 119180,
      .symbol_name_idx = 20475,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [84] = {
      .name_idx = 21128,
      .desc_idx = 119357,
      .symbol_name_idx = 20619,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [85] = {
      .name_idx = 152855,
      .desc_idx = 120485,
      .symbol_name_idx = 130529,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [86] = {
      .name_idx = 152884,
      .desc_idx = 120529,
      .symbol_name_idx = 130577,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [87] = {
      .name_idx = 153494,
      .desc_idx = 120574,
      .symbol_name_idx = 131153,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [88] = {
      .name_idx = 153542,
      .desc_idx = 120642,
      .symbol_name_idx = 131207,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [89] = {
      .name_idx = 152762,
      .desc_idx = 120439,
      .symbol_name_idx = 130442,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [90] = {
      .name_idx = 152940,
      .desc_idx = 118530,
      .symbol_name_idx = 130554,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_SENDS_TO_L3_CACHE_LINES,
   },
   [91] = {
      .name_idx = 152963,
      .desc_idx = 118591,
      .symbol_name_idx = 130604,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_SENDS_TO_L3_CACHE_LINES,
   },
   [92] = {
      .name_idx = 153577,
      .desc_idx = 118654,
      .symbol_name_idx = 131182,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_SENDS_TO_L3_CACHE_LINES,
   },
   [93] = {
      .name_idx = 153602,
      .desc_idx = 118717,
      .symbol_name_idx = 131238,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_SENDS_TO_L3_CACHE_LINES,
   },
   [94] = {
      .name_idx = 152915,
      .desc_idx = 118465,
      .symbol_name_idx = 130471,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_SENDS_TO_L3_CACHE_LINES,
   },
   [95] = {
      .name_idx = 27576,
      .desc_idx = 122132,
      .symbol_name_idx = 26822,
      .category_idx = 844,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [96] = {
      .name_idx = 28001,
      .desc_idx = 123312,
      .symbol_name_idx = 27370,
      .category_idx = 873,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [97] = {
      .name_idx = 28073,
      .desc_idx = 123558,
      .symbol_name_idx = 27453,
      .category_idx = 929,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [98] = {
      .name_idx = 27911,
      .desc_idx = 123022,
      .symbol_name_idx = 27216,
      .category_idx = 954,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [99] = {
      .name_idx = 27874,
      .desc_idx = 122902,
      .symbol_name_idx = 27179,
      .category_idx = 954,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [100] = {
      .name_idx = 27629,
      .desc_idx = 122316,
      .symbol_name_idx = 26918,
      .category_idx = 970,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [101] = {
      .name_idx = 28036,
      .desc_idx = 123485,
      .symbol_name_idx = 27416,
      .category_idx = 970,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [102] = {
      .name_idx = 27948,
      .desc_idx = 123234,
      .symbol_name_idx = 27270,
      .category_idx = 970,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [103] = {
      .name_idx = 27820,
      .desc_idx = 122480,
      .symbol_name_idx = 27109,
      .category_idx = 828,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [104] = {
      .name_idx = 27843,
      .desc_idx = 122067,
      .symbol_name_idx = 27148,
      .category_idx = 828,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [105] = {
      .name_idx = 48881,
      .desc_idx = 125182,
      .symbol_name_idx = 61638,
      .category_idx = 1096,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [106] = {
      .name_idx = 27602,
      .desc_idx = 123750,
      .symbol_name_idx = 26848,
      .category_idx = 844,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [107] = {
      .name_idx = 28018,
      .desc_idx = 124773,
      .symbol_name_idx = 27398,
      .category_idx = 903,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .name_idx = 28054,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .desc_idx = 125265,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .category_idx = 1143,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .category_idx = 1143,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .category_idx = 1143,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
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      .desc_idx = 127428,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
   },
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      .desc_idx = 126968,
      .symbol_name_idx = 18440,
      .category_idx = 458,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
   },
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      .desc_idx = 60451,
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      .category_idx = 579,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .desc_idx = 44691,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 45131,
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      .category_idx = 644,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 46045,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 44575,
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      .category_idx = 622,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 45015,
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      .category_idx = 622,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 622,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1135,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1135,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 129084,
      .symbol_name_idx = 111802,
      .category_idx = 1165,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   [137] = {
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      .desc_idx = 128754,
      .symbol_name_idx = 111783,
      .category_idx = 1143,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_TEXELS,
   },
   [138] = {
      .name_idx = 115610,
      .desc_idx = 128221,
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      .category_idx = 1143,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [139] = {
      .name_idx = 101520,
      .desc_idx = 128100,
      .symbol_name_idx = 96205,
      .category_idx = 152,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [140] = {
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      .desc_idx = 127862,
      .symbol_name_idx = 68763,
      .category_idx = 130,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
   [141] = {
      .name_idx = 113951,
      .desc_idx = 121917,
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      .category_idx = 1047,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [142] = {
      .name_idx = 116154,
      .desc_idx = 128604,
      .symbol_name_idx = 112122,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [143] = {
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      .desc_idx = 128476,
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      .category_idx = 1026,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [144] = {
      .name_idx = 45434,
      .desc_idx = 124969,
      .symbol_name_idx = 42359,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [145] = {
      .name_idx = 45994,
      .desc_idx = 125038,
      .symbol_name_idx = 42369,
      .category_idx = 1081,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [146] = {
      .name_idx = 48244,
      .desc_idx = 121746,
      .symbol_name_idx = 42398,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [147] = {
      .name_idx = 116130,
      .desc_idx = 128543,
      .symbol_name_idx = 112107,
      .category_idx = 393,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [148] = {
      .name_idx = 27407,
      .desc_idx = 121167,
      .symbol_name_idx = 26894,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [149] = {
      .name_idx = 115996,
      .desc_idx = 73073,
      .symbol_name_idx = 111728,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [150] = {
      .name_idx = 20169,
      .desc_idx = 44808,
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      .category_idx = 579,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [151] = {
      .name_idx = 20296,
      .desc_idx = 45371,
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      .category_idx = 579,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [152] = {
      .name_idx = 19993,
      .desc_idx = 42773,
      .symbol_name_idx = 19906,
      .category_idx = 384,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_NUMBER,
   },
   [153] = {
      .name_idx = 20391,
      .desc_idx = 46162,
      .symbol_name_idx = 20386,
      .category_idx = 579,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [154] = {
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      .desc_idx = 63349,
      .symbol_name_idx = 20457,
      .category_idx = 384,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [155] = {
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      .desc_idx = 129375,
      .symbol_name_idx = 130511,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [156] = {
      .name_idx = 115574,
      .desc_idx = 127504,
      .symbol_name_idx = 111712,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [157] = {
      .name_idx = 154180,
      .desc_idx = 114880,
      .symbol_name_idx = 132198,
      .category_idx = 106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [158] = {
      .name_idx = 154372,
      .desc_idx = 114989,
      .symbol_name_idx = 132323,
      .category_idx = 328,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [159] = {
      .name_idx = 31283,
      .desc_idx = 63506,
      .symbol_name_idx = 31094,
      .category_idx = 86,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [160] = {
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      .desc_idx = 61107,
      .symbol_name_idx = 18312,
      .category_idx = 16,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [161] = {
      .name_idx = 27110,
      .desc_idx = 63048,
      .symbol_name_idx = 26692,
      .category_idx = 62,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [162] = {
      .name_idx = 113980,
      .desc_idx = 89964,
      .symbol_name_idx = 112375,
      .category_idx = 306,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [163] = {
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      .desc_idx = 60546,
      .symbol_name_idx = 9037,
      .category_idx = 0,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [164] = {
      .name_idx = 124865,
      .desc_idx = 90163,
      .symbol_name_idx = 112072,
      .category_idx = 276,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [165] = {
      .name_idx = 31585,
      .desc_idx = 61419,
      .symbol_name_idx = 30875,
      .category_idx = 243,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [166] = {
      .name_idx = 20667,
      .desc_idx = 61306,
      .symbol_name_idx = 19726,
      .category_idx = 207,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [167] = {
      .name_idx = 4260,
      .desc_idx = 60319,
      .symbol_name_idx = 4295,
      .category_idx = 171,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [168] = {
      .name_idx = 31354,
      .desc_idx = 63614,
      .symbol_name_idx = 31214,
      .category_idx = 86,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [169] = {
      .name_idx = 18388,
      .desc_idx = 61217,
      .symbol_name_idx = 18432,
      .category_idx = 16,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [170] = {
      .name_idx = 113994,
      .desc_idx = 90074,
      .symbol_name_idx = 112388,
      .category_idx = 306,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [171] = {
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      .desc_idx = 60650,
      .symbol_name_idx = 9050,
      .category_idx = 0,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [172] = {
      .name_idx = 109486,
      .desc_idx = 90270,
      .symbol_name_idx = 112085,
      .category_idx = 276,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [173] = {
      .name_idx = 27651,
      .desc_idx = 122208,
      .symbol_name_idx = 26940,
      .category_idx = 970,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [174] = {
      .name_idx = 28036,
      .desc_idx = 123389,
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      .category_idx = 970,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [175] = {
      .name_idx = 27948,
      .desc_idx = 123128,
      .symbol_name_idx = 27270,
      .category_idx = 970,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [176] = {
      .name_idx = 27843,
      .desc_idx = 123630,
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      .category_idx = 828,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [177] = {
      .name_idx = 27688,
      .desc_idx = 122554,
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      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [178] = {
      .name_idx = 27721,
      .desc_idx = 122641,
      .symbol_name_idx = 27010,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [179] = {
      .name_idx = 27754,
      .desc_idx = 122728,
      .symbol_name_idx = 27043,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [180] = {
      .name_idx = 27787,
      .desc_idx = 122815,
      .symbol_name_idx = 27076,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [181] = {
      .name_idx = 27820,
      .desc_idx = 122400,
      .symbol_name_idx = 27109,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [182] = {
      .name_idx = 27985,
      .desc_idx = 126575,
      .symbol_name_idx = 27325,
      .category_idx = 828,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [183] = {
      .name_idx = 27858,
      .desc_idx = 124847,
      .symbol_name_idx = 27163,
      .category_idx = 828,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [184] = {
      .name_idx = 27704,
      .desc_idx = 123994,
      .symbol_name_idx = 26993,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [185] = {
      .name_idx = 27737,
      .desc_idx = 124090,
      .symbol_name_idx = 27026,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [186] = {
      .name_idx = 27770,
      .desc_idx = 124186,
      .symbol_name_idx = 27059,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [187] = {
      .name_idx = 27803,
      .desc_idx = 124282,
      .symbol_name_idx = 27092,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [188] = {
      .name_idx = 27985,
      .desc_idx = 126509,
      .symbol_name_idx = 27325,
      .category_idx = 828,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [189] = {
      .name_idx = 20893,
      .desc_idx = 119051,
      .symbol_name_idx = 19817,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [190] = {
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      .desc_idx = 119115,
      .symbol_name_idx = 19856,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [191] = {
      .name_idx = 152940,
      .desc_idx = 39611,
      .symbol_name_idx = 130554,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_REQUESTS_TO_L3_CACHE_LINES,
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   [192] = {
      .name_idx = 152963,
      .desc_idx = 39668,
      .symbol_name_idx = 130604,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_REQUESTS_TO_L3_CACHE_LINES,
   },
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      .desc_idx = 39727,
      .symbol_name_idx = 131182,
      .category_idx = 1013,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_REQUESTS_TO_L3_CACHE_LINES,
   },
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      .name_idx = 153602,
      .desc_idx = 39786,
      .symbol_name_idx = 131238,
      .category_idx = 1013,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_REQUESTS_TO_L3_CACHE_LINES,
   },
   [195] = {
      .name_idx = 152915,
      .desc_idx = 39550,
      .symbol_name_idx = 130471,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_ATOMIC_REQUESTS_TO_L3_CACHE_LINES,
   },
   [196] = {
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      .desc_idx = 61972,
      .symbol_name_idx = 20287,
      .category_idx = 594,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [197] = {
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      .desc_idx = 62089,
      .symbol_name_idx = 20311,
      .category_idx = 594,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [198] = {
      .name_idx = 20189,
      .desc_idx = 62436,
      .symbol_name_idx = 20407,
      .category_idx = 594,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [199] = {
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      .desc_idx = 62554,
      .symbol_name_idx = 20432,
      .category_idx = 594,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [200] = {
      .name_idx = 20090,
      .desc_idx = 61738,
      .symbol_name_idx = 19919,
      .category_idx = 594,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [201] = {
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      .desc_idx = 61855,
      .symbol_name_idx = 19943,
      .category_idx = 594,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [202] = {
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      .desc_idx = 62206,
      .symbol_name_idx = 20342,
      .category_idx = 594,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [203] = {
      .name_idx = 20271,
      .desc_idx = 62321,
      .symbol_name_idx = 20364,
      .category_idx = 594,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [204] = {
      .name_idx = 41775,
      .desc_idx = 124902,
      .symbol_name_idx = 42076,
      .category_idx = 1010,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [205] = {
      .name_idx = 48265,
      .desc_idx = 121847,
      .symbol_name_idx = 42417,
      .category_idx = 1010,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [206] = {
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      .desc_idx = 125435,
      .symbol_name_idx = 42087,
      .category_idx = 1010,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [207] = {
      .name_idx = 44534,
      .desc_idx = 125495,
      .symbol_name_idx = 42138,
      .category_idx = 1010,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [208] = {
      .name_idx = 44554,
      .desc_idx = 125555,
      .symbol_name_idx = 42155,
      .category_idx = 1010,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [209] = {
      .name_idx = 44574,
      .desc_idx = 125615,
      .symbol_name_idx = 42172,
      .category_idx = 1010,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [210] = {
      .name_idx = 44594,
      .desc_idx = 125749,
      .symbol_name_idx = 42257,
      .category_idx = 1010,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [211] = {
      .name_idx = 44656,
      .desc_idx = 125809,
      .symbol_name_idx = 42308,
      .category_idx = 1010,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [212] = {
      .name_idx = 44676,
      .desc_idx = 125869,
      .symbol_name_idx = 42325,
      .category_idx = 1010,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [213] = {
      .name_idx = 44696,
      .desc_idx = 125929,
      .symbol_name_idx = 42342,
      .category_idx = 1010,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [214] = {
      .name_idx = 44492,
      .desc_idx = 125361,
      .symbol_name_idx = 42104,
      .category_idx = 1064,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [215] = {
      .name_idx = 44515,
      .desc_idx = 127288,
      .symbol_name_idx = 42123,
      .category_idx = 1064,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [216] = {
      .name_idx = 44614,
      .desc_idx = 125675,
      .symbol_name_idx = 42274,
      .category_idx = 1064,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [217] = {
      .name_idx = 44637,
      .desc_idx = 127358,
      .symbol_name_idx = 42293,
      .category_idx = 1064,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [218] = {
      .name_idx = 20496,
      .desc_idx = 119764,
      .symbol_name_idx = 20129,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [219] = {
      .name_idx = 20523,
      .desc_idx = 119846,
      .symbol_name_idx = 20144,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [220] = {
      .name_idx = 20440,
      .desc_idx = 119598,
      .symbol_name_idx = 20097,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [221] = {
      .name_idx = 20468,
      .desc_idx = 119681,
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      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [222] = {
      .name_idx = 18619,
      .desc_idx = 118782,
      .symbol_name_idx = 30617,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [223] = {
      .name_idx = 18648,
      .desc_idx = 118862,
      .symbol_name_idx = 30633,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [224] = {
      .name_idx = 4132,
      .desc_idx = 118928,
      .symbol_name_idx = 30650,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [225] = {
      .name_idx = 4162,
      .desc_idx = 118990,
      .symbol_name_idx = 30662,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [226] = {
      .name_idx = 20932,
      .desc_idx = 37,
      .symbol_name_idx = 19967,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_BYTES_PER_L3_CACHE_LINE,
   },
   [227] = {
      .name_idx = 20983,
      .desc_idx = 181,
      .symbol_name_idx = 20018,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_UTILIZATION,
   },
   [228] = {
      .name_idx = 20609,
      .desc_idx = 120277,
      .symbol_name_idx = 20239,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [229] = {
      .name_idx = 20638,
      .desc_idx = 120358,
      .symbol_name_idx = 20255,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [230] = {
      .name_idx = 20638,
      .desc_idx = 120358,
      .symbol_name_idx = 20271,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [231] = {
      .name_idx = 20550,
      .desc_idx = 120195,
      .symbol_name_idx = 20159,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [232] = {
      .name_idx = 20550,
      .desc_idx = 120017,
      .symbol_name_idx = 20199,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [233] = {
      .name_idx = 20638,
      .desc_idx = 119928,
      .symbol_name_idx = 20176,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [234] = {
      .name_idx = 20579,
      .desc_idx = 120106,
      .symbol_name_idx = 20216,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
   },
   [235] = {
      .name_idx = 20956,
      .desc_idx = 79,
      .symbol_name_idx = 19991,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_EU_BYTES_PER_L3_CACHE_LINE,
   },
   [236] = {
      .name_idx = 21007,
      .desc_idx = 238,
      .symbol_name_idx = 20042,
      .category_idx = 1013,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_UTILIZATION,
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5862,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_MESSAGES,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 6484,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .desc_idx = 6440,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 3404,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .desc_idx = 10739,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [798] = {
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      .desc_idx = 2224,
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      .category_idx = 1106,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2224,
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      .category_idx = 1106,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .category_idx = 1106,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18762,
      .symbol_name_idx = 109793,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
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      .desc_idx = 368,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [816] = {
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 10577,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 10658,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 10577,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [820] = {
      .name_idx = 23989,
      .desc_idx = 10658,
      .symbol_name_idx = 23256,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [821] = {
      .name_idx = 23598,
      .desc_idx = 10900,
      .symbol_name_idx = 22865,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [822] = {
      .name_idx = 24295,
      .desc_idx = 10982,
      .symbol_name_idx = 23562,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [823] = {
      .name_idx = 23638,
      .desc_idx = 10900,
      .symbol_name_idx = 22905,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [824] = {
      .name_idx = 24335,
      .desc_idx = 10982,
      .symbol_name_idx = 23602,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 14663,
      .symbol_name_idx = 30552,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [826] = {
      .name_idx = 31250,
      .desc_idx = 14737,
      .symbol_name_idx = 30584,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [827] = {
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      .desc_idx = 2874,
      .symbol_name_idx = 46530,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 46810,
      .desc_idx = 2874,
      .symbol_name_idx = 46546,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [829] = {
      .name_idx = 46996,
      .desc_idx = 2874,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 47182,
      .desc_idx = 2874,
      .symbol_name_idx = 46918,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 47232,
      .desc_idx = 2874,
      .symbol_name_idx = 46968,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 47248,
      .desc_idx = 2874,
      .symbol_name_idx = 46984,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [833] = {
      .name_idx = 47264,
      .desc_idx = 2874,
      .symbol_name_idx = 47000,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2874,
      .symbol_name_idx = 47016,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [835] = {
      .name_idx = 48285,
      .desc_idx = 3558,
      .symbol_name_idx = 48388,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [836] = {
      .name_idx = 48302,
      .desc_idx = 3558,
      .symbol_name_idx = 48405,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [837] = {
      .name_idx = 48499,
      .desc_idx = 3558,
      .symbol_name_idx = 48602,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [838] = {
      .name_idx = 48696,
      .desc_idx = 3558,
      .symbol_name_idx = 48799,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [839] = {
      .name_idx = 48749,
      .desc_idx = 3558,
      .symbol_name_idx = 48852,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [840] = {
      .name_idx = 48766,
      .desc_idx = 3558,
      .symbol_name_idx = 48869,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [841] = {
      .name_idx = 48783,
      .desc_idx = 3558,
      .symbol_name_idx = 48886,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 48800,
      .desc_idx = 3558,
      .symbol_name_idx = 48903,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [843] = {
      .name_idx = 13279,
      .desc_idx = 2990,
      .symbol_name_idx = 13090,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [844] = {
      .name_idx = 13304,
      .desc_idx = 2990,
      .symbol_name_idx = 13115,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [845] = {
      .name_idx = 13589,
      .desc_idx = 2990,
      .symbol_name_idx = 13400,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [846] = {
      .name_idx = 13874,
      .desc_idx = 2990,
      .symbol_name_idx = 13685,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [847] = {
      .name_idx = 13951,
      .desc_idx = 2990,
      .symbol_name_idx = 13762,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [848] = {
      .name_idx = 13976,
      .desc_idx = 2990,
      .symbol_name_idx = 13787,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [849] = {
      .name_idx = 14001,
      .desc_idx = 2990,
      .symbol_name_idx = 13812,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [850] = {
      .name_idx = 14026,
      .desc_idx = 2990,
      .symbol_name_idx = 13837,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [851] = {
      .name_idx = 14101,
      .desc_idx = 3600,
      .symbol_name_idx = 13912,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [852] = {
      .name_idx = 14127,
      .desc_idx = 3600,
      .symbol_name_idx = 13938,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [853] = {
      .name_idx = 14423,
      .desc_idx = 3600,
      .symbol_name_idx = 14234,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [854] = {
      .name_idx = 14719,
      .desc_idx = 3600,
      .symbol_name_idx = 14530,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 14799,
      .desc_idx = 3600,
      .symbol_name_idx = 14610,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 14825,
      .desc_idx = 3600,
      .symbol_name_idx = 14636,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [857] = {
      .name_idx = 14851,
      .desc_idx = 3600,
      .symbol_name_idx = 14662,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [858] = {
      .name_idx = 14877,
      .desc_idx = 3600,
      .symbol_name_idx = 14688,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [859] = {
      .name_idx = 44716,
      .desc_idx = 2484,
      .symbol_name_idx = 43818,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [860] = {
      .name_idx = 44731,
      .desc_idx = 2484,
      .symbol_name_idx = 43833,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [861] = {
      .name_idx = 44906,
      .desc_idx = 2484,
      .symbol_name_idx = 44008,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [862] = {
      .name_idx = 45081,
      .desc_idx = 2484,
      .symbol_name_idx = 44183,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [863] = {
      .name_idx = 45128,
      .desc_idx = 2484,
      .symbol_name_idx = 44230,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [864] = {
      .name_idx = 45143,
      .desc_idx = 2484,
      .symbol_name_idx = 44245,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [865] = {
      .name_idx = 45158,
      .desc_idx = 2484,
      .symbol_name_idx = 44260,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [866] = {
      .name_idx = 45173,
      .desc_idx = 2484,
      .symbol_name_idx = 44275,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [867] = {
      .name_idx = 104192,
      .desc_idx = 3404,
      .symbol_name_idx = 99207,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [868] = {
      .name_idx = 104216,
      .desc_idx = 3404,
      .symbol_name_idx = 99231,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [869] = {
      .name_idx = 104490,
      .desc_idx = 3404,
      .symbol_name_idx = 99505,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [870] = {
      .name_idx = 104764,
      .desc_idx = 3404,
      .symbol_name_idx = 99779,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [871] = {
      .name_idx = 104838,
      .desc_idx = 3404,
      .symbol_name_idx = 99853,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [872] = {
      .name_idx = 104862,
      .desc_idx = 3404,
      .symbol_name_idx = 99877,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [873] = {
      .name_idx = 104886,
      .desc_idx = 3404,
      .symbol_name_idx = 99901,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [874] = {
      .name_idx = 104910,
      .desc_idx = 3404,
      .symbol_name_idx = 99925,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [875] = {
      .name_idx = 103418,
      .desc_idx = 2707,
      .symbol_name_idx = 98433,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [876] = {
      .name_idx = 103441,
      .desc_idx = 2707,
      .symbol_name_idx = 98456,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [877] = {
      .name_idx = 103704,
      .desc_idx = 2707,
      .symbol_name_idx = 98719,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [878] = {
      .name_idx = 103967,
      .desc_idx = 2707,
      .symbol_name_idx = 98982,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [879] = {
      .name_idx = 104038,
      .desc_idx = 2707,
      .symbol_name_idx = 99053,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [880] = {
      .name_idx = 104061,
      .desc_idx = 2707,
      .symbol_name_idx = 99076,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [881] = {
      .name_idx = 104084,
      .desc_idx = 2707,
      .symbol_name_idx = 99099,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [882] = {
      .name_idx = 104107,
      .desc_idx = 2707,
      .symbol_name_idx = 99122,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [883] = {
      .name_idx = 35839,
      .desc_idx = 2915,
      .symbol_name_idx = 35246,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [884] = {
      .name_idx = 35862,
      .desc_idx = 2915,
      .symbol_name_idx = 35269,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1402] = {
      .name_idx = 4540,
      .desc_idx = 23665,
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      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1403] = {
      .name_idx = 4981,
      .desc_idx = 23764,
      .symbol_name_idx = 4792,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1404] = {
      .name_idx = 5009,
      .desc_idx = 23764,
      .symbol_name_idx = 4820,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1405] = {
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      .desc_idx = 17305,
      .symbol_name_idx = 5568,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1406] = {
      .name_idx = 5789,
      .desc_idx = 17305,
      .symbol_name_idx = 5600,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1407] = {
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      .desc_idx = 11064,
      .symbol_name_idx = 5824,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1408] = {
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      .desc_idx = 11064,
      .symbol_name_idx = 5858,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1409] = {
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      .desc_idx = 17121,
      .symbol_name_idx = 109278,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1410] = {
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      .desc_idx = 17121,
      .symbol_name_idx = 109308,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1411] = {
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      .desc_idx = 18576,
      .symbol_name_idx = 109038,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1412] = {
      .name_idx = 114924,
      .desc_idx = 18576,
      .symbol_name_idx = 109068,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1413] = {
      .name_idx = 115134,
      .desc_idx = 29476,
      .symbol_name_idx = 109518,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1414] = {
      .name_idx = 115164,
      .desc_idx = 29476,
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      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1415] = {
      .name_idx = 74840,
      .desc_idx = 18919,
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      .category_idx = 1113,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1416] = {
      .name_idx = 74877,
      .desc_idx = 18919,
      .symbol_name_idx = 69724,
      .category_idx = 1113,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1417] = {
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      .desc_idx = 25119,
      .symbol_name_idx = 69142,
      .category_idx = 1113,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1418] = {
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      .desc_idx = 25119,
      .symbol_name_idx = 69176,
      .category_idx = 1113,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1419] = {
      .name_idx = 74567,
      .desc_idx = 25192,
      .symbol_name_idx = 69414,
      .category_idx = 1113,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1420] = {
      .name_idx = 74598,
      .desc_idx = 25192,
      .symbol_name_idx = 69445,
      .category_idx = 1113,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1421] = {
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      .desc_idx = 17228,
      .symbol_name_idx = 5256,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1422] = {
      .name_idx = 5484,
      .desc_idx = 17228,
      .symbol_name_idx = 5295,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1423] = {
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      .desc_idx = 1792,
      .symbol_name_idx = 5016,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1424] = {
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      .desc_idx = 1792,
      .symbol_name_idx = 5046,
      .category_idx = 993,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1425] = {
      .name_idx = 153211,
      .desc_idx = 5141,
      .symbol_name_idx = 130852,
      .category_idx = 1209,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1426] = {
      .name_idx = 153339,
      .desc_idx = 5236,
      .symbol_name_idx = 130980,
      .category_idx = 1209,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1427] = {
      .name_idx = 152987,
      .desc_idx = 5175,
      .symbol_name_idx = 130628,
      .category_idx = 1209,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1428] = {
      .name_idx = 153227,
      .desc_idx = 5141,
      .symbol_name_idx = 130868,
      .category_idx = 1209,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1429] = {
      .name_idx = 153356,
      .desc_idx = 5236,
      .symbol_name_idx = 130997,
      .category_idx = 1209,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1430] = {
      .name_idx = 153015,
      .desc_idx = 5175,
      .symbol_name_idx = 130656,
      .category_idx = 1209,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1431] = {
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      .desc_idx = 16910,
      .symbol_name_idx = 18450,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1432] = {
      .name_idx = 19324,
      .desc_idx = 17695,
      .symbol_name_idx = 19096,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1433] = {
      .name_idx = 18718,
      .desc_idx = 16910,
      .symbol_name_idx = 18490,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1434] = {
      .name_idx = 19363,
      .desc_idx = 17695,
      .symbol_name_idx = 19135,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1435] = {
      .name_idx = 19004,
      .desc_idx = 16910,
      .symbol_name_idx = 18776,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1436] = {
      .name_idx = 19642,
      .desc_idx = 17695,
      .symbol_name_idx = 19414,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1437] = {
      .name_idx = 19044,
      .desc_idx = 16910,
      .symbol_name_idx = 18816,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1438] = {
      .name_idx = 19681,
      .desc_idx = 17695,
      .symbol_name_idx = 19453,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1439] = {
      .name_idx = 28171,
      .desc_idx = 16754,
      .symbol_name_idx = 27505,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1440] = {
      .name_idx = 28202,
      .desc_idx = 16754,
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      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1441] = {
      .name_idx = 28425,
      .desc_idx = 16754,
      .symbol_name_idx = 27759,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1442] = {
      .name_idx = 28456,
      .desc_idx = 16754,
      .symbol_name_idx = 27790,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1443] = {
      .name_idx = 28673,
      .desc_idx = 17547,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1444] = {
      .name_idx = 28703,
      .desc_idx = 17547,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1445] = {
      .name_idx = 28919,
      .desc_idx = 17547,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1446] = {
      .name_idx = 28949,
      .desc_idx = 17547,
      .symbol_name_idx = 28283,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1447] = {
      .name_idx = 29159,
      .desc_idx = 17041,
      .symbol_name_idx = 28493,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1448] = {
      .name_idx = 29189,
      .desc_idx = 17041,
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      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1449] = {
      .name_idx = 29405,
      .desc_idx = 17041,
      .symbol_name_idx = 28739,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1450] = {
      .name_idx = 29435,
      .desc_idx = 17041,
      .symbol_name_idx = 28769,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1451] = {
      .name_idx = 29645,
      .desc_idx = 17798,
      .symbol_name_idx = 28979,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1452] = {
      .name_idx = 29674,
      .desc_idx = 17798,
      .symbol_name_idx = 29008,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1453] = {
      .name_idx = 29883,
      .desc_idx = 17798,
      .symbol_name_idx = 29217,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1454] = {
      .name_idx = 29912,
      .desc_idx = 17798,
      .symbol_name_idx = 29246,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1455] = {
      .name_idx = 30115,
      .desc_idx = 17477,
      .symbol_name_idx = 29449,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1456] = {
      .name_idx = 30144,
      .desc_idx = 17477,
      .symbol_name_idx = 29478,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1457] = {
      .name_idx = 30353,
      .desc_idx = 17477,
      .symbol_name_idx = 29687,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1458] = {
      .name_idx = 30382,
      .desc_idx = 17477,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1459] = {
      .name_idx = 30585,
      .desc_idx = 24214,
      .symbol_name_idx = 29919,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1460] = {
      .name_idx = 30621,
      .desc_idx = 24214,
      .symbol_name_idx = 29955,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1461] = {
      .name_idx = 30879,
      .desc_idx = 24214,
      .symbol_name_idx = 30213,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1462] = {
      .name_idx = 30915,
      .desc_idx = 24214,
      .symbol_name_idx = 30249,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1463] = {
      .name_idx = 40387,
      .desc_idx = 24371,
      .symbol_name_idx = 39794,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1464] = {
      .name_idx = 40422,
      .desc_idx = 24371,
      .symbol_name_idx = 39829,
      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1465] = {
      .name_idx = 40673,
      .desc_idx = 24371,
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      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1467] = {
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1468] = {
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      .desc_idx = 24291,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1469] = {
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      .desc_idx = 24291,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 24291,
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      .category_idx = 374,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 31504,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1472] = {
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1473] = {
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      .desc_idx = 31504,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 667,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1475] = {
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      .desc_idx = 31408,
      .symbol_name_idx = 8466,
      .category_idx = 667,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1478] = {
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      .category_idx = 667,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1479] = {
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      .desc_idx = 7679,
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      .category_idx = 667,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1480] = {
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      .desc_idx = 7607,
      .symbol_name_idx = 8500,
      .category_idx = 667,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1481] = {
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      .desc_idx = 1893,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1482] = {
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      .desc_idx = 4959,
      .symbol_name_idx = 8439,
      .category_idx = 667,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1483] = {
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      .desc_idx = 31703,
      .symbol_name_idx = 8407,
      .category_idx = 667,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1484] = {
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1485] = {
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 31901,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 31901,
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      .category_idx = 667,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 19072,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19072,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19072,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19072,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19072,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1493] = {
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      .desc_idx = 19072,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19072,
      .symbol_name_idx = 78103,
      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1495] = {
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      .desc_idx = 19072,
      .symbol_name_idx = 78138,
      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1496] = {
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      .desc_idx = 3978,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3978,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3978,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1499] = {
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      .desc_idx = 3978,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .name_idx = 98886,
      .desc_idx = 3978,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1501] = {
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      .desc_idx = 3978,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1502] = {
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      .desc_idx = 3978,
      .symbol_name_idx = 93645,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1503] = {
      .name_idx = 98997,
      .desc_idx = 3978,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1504] = {
      .name_idx = 80132,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1505] = {
      .name_idx = 80175,
      .desc_idx = 7466,
      .symbol_name_idx = 74860,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1506] = {
      .name_idx = 80658,
      .desc_idx = 7466,
      .symbol_name_idx = 75343,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1507] = {
      .name_idx = 81141,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1508] = {
      .name_idx = 81272,
      .desc_idx = 7466,
      .symbol_name_idx = 75957,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1509] = {
      .name_idx = 81315,
      .desc_idx = 7466,
      .symbol_name_idx = 76000,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1510] = {
      .name_idx = 81358,
      .desc_idx = 7466,
      .symbol_name_idx = 76043,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1511] = {
      .name_idx = 81401,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1512] = {
      .name_idx = 91530,
      .desc_idx = 16608,
      .symbol_name_idx = 86215,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1513] = {
      .name_idx = 91566,
      .desc_idx = 16608,
      .symbol_name_idx = 86251,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1514] = {
      .name_idx = 91972,
      .desc_idx = 16608,
      .symbol_name_idx = 86657,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1515] = {
      .name_idx = 92378,
      .desc_idx = 16608,
      .symbol_name_idx = 87063,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1516] = {
      .name_idx = 92488,
      .desc_idx = 16608,
      .symbol_name_idx = 87173,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1517] = {
      .name_idx = 92524,
      .desc_idx = 16608,
      .symbol_name_idx = 87209,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1518] = {
      .name_idx = 92560,
      .desc_idx = 16608,
      .symbol_name_idx = 87245,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1519] = {
      .name_idx = 92596,
      .desc_idx = 16608,
      .symbol_name_idx = 87281,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1520] = {
      .name_idx = 76706,
      .desc_idx = 5387,
      .symbol_name_idx = 71391,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1521] = {
      .name_idx = 76745,
      .desc_idx = 5387,
      .symbol_name_idx = 71430,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1522] = {
      .name_idx = 77184,
      .desc_idx = 5387,
      .symbol_name_idx = 71869,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1523] = {
      .name_idx = 77623,
      .desc_idx = 5387,
      .symbol_name_idx = 72308,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1524] = {
      .name_idx = 77742,
      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1525] = {
      .name_idx = 77781,
      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1526] = {
      .name_idx = 77820,
      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1527] = {
      .name_idx = 77859,
      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1528] = {
      .name_idx = 85842,
      .desc_idx = 16205,
      .symbol_name_idx = 80527,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1529] = {
      .name_idx = 85886,
      .desc_idx = 16205,
      .symbol_name_idx = 80571,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1530] = {
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      .desc_idx = 16205,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1531] = {
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1532] = {
      .name_idx = 87008,
      .desc_idx = 16205,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1533] = {
      .name_idx = 87052,
      .desc_idx = 16205,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1535] = {
      .name_idx = 87140,
      .desc_idx = 16205,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1536] = {
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      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1538] = {
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      .desc_idx = 7325,
      .symbol_name_idx = 74005,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1539] = {
      .name_idx = 79770,
      .desc_idx = 7325,
      .symbol_name_idx = 74455,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1540] = {
      .name_idx = 79892,
      .desc_idx = 7325,
      .symbol_name_idx = 74577,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1541] = {
      .name_idx = 79932,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1542] = {
      .name_idx = 79972,
      .desc_idx = 7325,
      .symbol_name_idx = 74657,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1543] = {
      .name_idx = 80012,
      .desc_idx = 7325,
      .symbol_name_idx = 74697,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1544] = {
      .name_idx = 99108,
      .desc_idx = 4035,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1545] = {
      .name_idx = 99146,
      .desc_idx = 4035,
      .symbol_name_idx = 93831,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1546] = {
      .name_idx = 99574,
      .desc_idx = 4035,
      .symbol_name_idx = 94259,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1547] = {
      .name_idx = 100002,
      .desc_idx = 4035,
      .symbol_name_idx = 94687,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1548] = {
      .name_idx = 100118,
      .desc_idx = 4035,
      .symbol_name_idx = 94803,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1549] = {
      .name_idx = 100156,
      .desc_idx = 4035,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1550] = {
      .name_idx = 100194,
      .desc_idx = 4035,
      .symbol_name_idx = 94879,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1551] = {
      .name_idx = 100232,
      .desc_idx = 4035,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1552] = {
      .name_idx = 94924,
      .desc_idx = 16674,
      .symbol_name_idx = 89609,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1553] = {
      .name_idx = 94955,
      .desc_idx = 16674,
      .symbol_name_idx = 89640,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1554] = {
      .name_idx = 95306,
      .desc_idx = 16674,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1555] = {
      .name_idx = 95657,
      .desc_idx = 16674,
      .symbol_name_idx = 90342,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1556] = {
      .name_idx = 95752,
      .desc_idx = 16674,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1557] = {
      .name_idx = 95783,
      .desc_idx = 16674,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1558] = {
      .name_idx = 95814,
      .desc_idx = 16674,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1559] = {
      .name_idx = 95845,
      .desc_idx = 16674,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1560] = {
      .name_idx = 96888,
      .desc_idx = 17177,
      .symbol_name_idx = 91573,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1561] = {
      .name_idx = 96919,
      .desc_idx = 17177,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1562] = {
      .name_idx = 97270,
      .desc_idx = 17177,
      .symbol_name_idx = 91955,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1563] = {
      .name_idx = 97621,
      .desc_idx = 17177,
      .symbol_name_idx = 92306,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1564] = {
      .name_idx = 97716,
      .desc_idx = 17177,
      .symbol_name_idx = 92401,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1565] = {
      .name_idx = 97747,
      .desc_idx = 17177,
      .symbol_name_idx = 92432,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1566] = {
      .name_idx = 97778,
      .desc_idx = 17177,
      .symbol_name_idx = 92463,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1567] = {
      .name_idx = 97809,
      .desc_idx = 17177,
      .symbol_name_idx = 92494,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1568] = {
      .name_idx = 90516,
      .desc_idx = 25262,
      .symbol_name_idx = 85201,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1569] = {
      .name_idx = 90547,
      .desc_idx = 25262,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1570] = {
      .name_idx = 90898,
      .desc_idx = 25262,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1571] = {
      .name_idx = 91249,
      .desc_idx = 25262,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1572] = {
      .name_idx = 91344,
      .desc_idx = 25262,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1573] = {
      .name_idx = 91375,
      .desc_idx = 25262,
      .symbol_name_idx = 86060,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1574] = {
      .name_idx = 91406,
      .desc_idx = 25262,
      .symbol_name_idx = 86091,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1575] = {
      .name_idx = 91437,
      .desc_idx = 25262,
      .symbol_name_idx = 86122,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1576] = {
      .name_idx = 95938,
      .desc_idx = 23064,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1577] = {
      .name_idx = 95967,
      .desc_idx = 23064,
      .symbol_name_idx = 90652,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1578] = {
      .name_idx = 96296,
      .desc_idx = 23064,
      .symbol_name_idx = 90981,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1579] = {
      .name_idx = 96625,
      .desc_idx = 23064,
      .symbol_name_idx = 91310,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1580] = {
      .name_idx = 96714,
      .desc_idx = 23064,
      .symbol_name_idx = 91399,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1581] = {
      .name_idx = 96743,
      .desc_idx = 23064,
      .symbol_name_idx = 91428,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1582] = {
      .name_idx = 96772,
      .desc_idx = 23064,
      .symbol_name_idx = 91457,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1583] = {
      .name_idx = 96801,
      .desc_idx = 23064,
      .symbol_name_idx = 91486,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1584] = {
      .name_idx = 185713,
      .desc_idx = 26758,
      .symbol_name_idx = 163119,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1585] = {
      .name_idx = 186938,
      .desc_idx = 26881,
      .symbol_name_idx = 164344,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1586] = {
      .name_idx = 188808,
      .desc_idx = 27007,
      .symbol_name_idx = 166201,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1587] = {
      .name_idx = 190155,
      .desc_idx = 27492,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1588] = {
      .name_idx = 191638,
      .desc_idx = 27366,
      .symbol_name_idx = 169044,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1589] = {
      .name_idx = 192812,
      .desc_idx = 27246,
      .symbol_name_idx = 170218,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1590] = {
      .name_idx = 179289,
      .desc_idx = 26563,
      .symbol_name_idx = 156695,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1591] = {
      .name_idx = 185750,
      .desc_idx = 26758,
      .symbol_name_idx = 163536,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1592] = {
      .name_idx = 186977,
      .desc_idx = 26881,
      .symbol_name_idx = 164783,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1593] = {
      .name_idx = 188849,
      .desc_idx = 27007,
      .symbol_name_idx = 166662,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1594] = {
      .name_idx = 190192,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 18993,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 17396,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [1752] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [1753] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 3772,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 3772,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 3772,
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      .category_idx = 1002,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1757] = {
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      .desc_idx = 3772,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1758] = {
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      .desc_idx = 3772,
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      .category_idx = 1002,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1759] = {
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      .desc_idx = 3772,
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      .category_idx = 1002,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1760] = {
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      .desc_idx = 24098,
      .symbol_name_idx = 7612,
      .category_idx = 355,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
   [1761] = {
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      .desc_idx = 24098,
      .symbol_name_idx = 7652,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [1762] = {
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      .desc_idx = 17629,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1763] = {
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      .desc_idx = 17629,
      .symbol_name_idx = 64021,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1764] = {
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      .desc_idx = 16840,
      .symbol_name_idx = 64364,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1765] = {
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      .desc_idx = 16840,
      .symbol_name_idx = 64412,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1766] = {
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      .desc_idx = 4462,
      .symbol_name_idx = 105843,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1767] = {
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      .desc_idx = 4462,
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      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1768] = {
      .name_idx = 111431,
      .desc_idx = 4462,
      .symbol_name_idx = 106237,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1769] = {
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      .desc_idx = 4462,
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      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1770] = {
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      .desc_idx = 4462,
      .symbol_name_idx = 106697,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1771] = {
      .name_idx = 111923,
      .desc_idx = 4462,
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      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [1772] = {
      .name_idx = 111955,
      .desc_idx = 4462,
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      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1773] = {
      .name_idx = 111987,
      .desc_idx = 4462,
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      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1774] = {
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      .desc_idx = 2547,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1775] = {
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      .desc_idx = 2547,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1776] = {
      .name_idx = 45662,
      .desc_idx = 2547,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1777] = {
      .name_idx = 45848,
      .desc_idx = 2547,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1778] = {
      .name_idx = 45898,
      .desc_idx = 2547,
      .symbol_name_idx = 45644,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1779] = {
      .name_idx = 45914,
      .desc_idx = 2547,
      .symbol_name_idx = 45660,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1780] = {
      .name_idx = 45930,
      .desc_idx = 2547,
      .symbol_name_idx = 45676,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1781] = {
      .name_idx = 45946,
      .desc_idx = 2547,
      .symbol_name_idx = 45692,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1782] = {
      .name_idx = 968,
      .desc_idx = 1529,
      .symbol_name_idx = 968,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1783] = {
      .name_idx = 989,
      .desc_idx = 1529,
      .symbol_name_idx = 989,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1784] = {
      .name_idx = 156905,
      .desc_idx = 14472,
      .symbol_name_idx = 134331,
      .category_idx = 365,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1785] = {
      .name_idx = 156946,
      .desc_idx = 14472,
      .symbol_name_idx = 134372,
      .category_idx = 365,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1786] = {
      .name_idx = 157407,
      .desc_idx = 14472,
      .symbol_name_idx = 134833,
      .category_idx = 365,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1787] = {
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      .desc_idx = 14472,
      .symbol_name_idx = 135294,
      .category_idx = 365,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1788] = {
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      .desc_idx = 14472,
      .symbol_name_idx = 135419,
      .category_idx = 365,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1789] = {
      .name_idx = 158034,
      .desc_idx = 14472,
      .symbol_name_idx = 135460,
      .category_idx = 365,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1790] = {
      .name_idx = 158075,
      .desc_idx = 14472,
      .symbol_name_idx = 135501,
      .category_idx = 365,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1791] = {
      .name_idx = 158116,
      .desc_idx = 14472,
      .symbol_name_idx = 135542,
      .category_idx = 365,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1792] = {
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      .desc_idx = 2149,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1793] = {
      .name_idx = 25911,
      .desc_idx = 2149,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1794] = {
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      .desc_idx = 2388,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1795] = {
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      .desc_idx = 2435,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1796] = {
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      .desc_idx = 2388,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1797] = {
      .name_idx = 36623,
      .desc_idx = 2435,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1798] = {
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      .desc_idx = 2388,
      .symbol_name_idx = 31542,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1799] = {
      .name_idx = 36919,
      .desc_idx = 2435,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1800] = {
      .name_idx = 32420,
      .desc_idx = 2388,
      .symbol_name_idx = 31827,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1801] = {
      .name_idx = 37215,
      .desc_idx = 2435,
      .symbol_name_idx = 36622,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1802] = {
      .name_idx = 32497,
      .desc_idx = 2388,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1803] = {
      .name_idx = 37295,
      .desc_idx = 2435,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1804] = {
      .name_idx = 32522,
      .desc_idx = 2388,
      .symbol_name_idx = 31929,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1805] = {
      .name_idx = 37321,
      .desc_idx = 2435,
      .symbol_name_idx = 36728,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1806] = {
      .name_idx = 32547,
      .desc_idx = 2388,
      .symbol_name_idx = 31954,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1807] = {
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      .desc_idx = 2435,
      .symbol_name_idx = 36754,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1808] = {
      .name_idx = 32572,
      .desc_idx = 2388,
      .symbol_name_idx = 31979,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1809] = {
      .name_idx = 37373,
      .desc_idx = 2435,
      .symbol_name_idx = 36780,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1810] = {
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      .desc_idx = 2388,
      .symbol_name_idx = 32054,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1811] = {
      .name_idx = 37451,
      .desc_idx = 2435,
      .symbol_name_idx = 36858,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1812] = {
      .name_idx = 32672,
      .desc_idx = 2388,
      .symbol_name_idx = 32079,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1813] = {
      .name_idx = 37477,
      .desc_idx = 2435,
      .symbol_name_idx = 36884,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1814] = {
      .name_idx = 32957,
      .desc_idx = 2388,
      .symbol_name_idx = 32364,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1815] = {
      .name_idx = 37773,
      .desc_idx = 2435,
      .symbol_name_idx = 37180,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1816] = {
      .name_idx = 33242,
      .desc_idx = 2388,
      .symbol_name_idx = 32649,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1817] = {
      .name_idx = 38069,
      .desc_idx = 2435,
      .symbol_name_idx = 37476,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1818] = {
      .name_idx = 33319,
      .desc_idx = 2388,
      .symbol_name_idx = 32726,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1819] = {
      .name_idx = 38149,
      .desc_idx = 2435,
      .symbol_name_idx = 37556,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1820] = {
      .name_idx = 33344,
      .desc_idx = 2388,
      .symbol_name_idx = 32751,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1821] = {
      .name_idx = 38175,
      .desc_idx = 2435,
      .symbol_name_idx = 37582,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1822] = {
      .name_idx = 33369,
      .desc_idx = 2388,
      .symbol_name_idx = 32776,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1823] = {
      .name_idx = 38201,
      .desc_idx = 2435,
      .symbol_name_idx = 37608,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1824] = {
      .name_idx = 33394,
      .desc_idx = 2388,
      .symbol_name_idx = 32801,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1825] = {
      .name_idx = 38227,
      .desc_idx = 2435,
      .symbol_name_idx = 37634,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1826] = {
      .name_idx = 33469,
      .desc_idx = 2388,
      .symbol_name_idx = 32876,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1827] = {
      .name_idx = 38305,
      .desc_idx = 2435,
      .symbol_name_idx = 37712,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1828] = {
      .name_idx = 33494,
      .desc_idx = 2388,
      .symbol_name_idx = 32901,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1829] = {
      .name_idx = 38331,
      .desc_idx = 2435,
      .symbol_name_idx = 37738,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1830] = {
      .name_idx = 33779,
      .desc_idx = 2388,
      .symbol_name_idx = 33186,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1831] = {
      .name_idx = 38627,
      .desc_idx = 2435,
      .symbol_name_idx = 38034,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1832] = {
      .name_idx = 34064,
      .desc_idx = 2388,
      .symbol_name_idx = 33471,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1833] = {
      .name_idx = 38923,
      .desc_idx = 2435,
      .symbol_name_idx = 38330,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1834] = {
      .name_idx = 34141,
      .desc_idx = 2388,
      .symbol_name_idx = 33548,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1835] = {
      .name_idx = 39003,
      .desc_idx = 2435,
      .symbol_name_idx = 38410,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1836] = {
      .name_idx = 34166,
      .desc_idx = 2388,
      .symbol_name_idx = 33573,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1837] = {
      .name_idx = 39029,
      .desc_idx = 2435,
      .symbol_name_idx = 38436,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1838] = {
      .name_idx = 34191,
      .desc_idx = 2388,
      .symbol_name_idx = 33598,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1839] = {
      .name_idx = 39055,
      .desc_idx = 2435,
      .symbol_name_idx = 38462,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1840] = {
      .name_idx = 34216,
      .desc_idx = 2388,
      .symbol_name_idx = 33623,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1841] = {
      .name_idx = 39081,
      .desc_idx = 2435,
      .symbol_name_idx = 38488,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1842] = {
      .name_idx = 34291,
      .desc_idx = 2388,
      .symbol_name_idx = 33698,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1843] = {
      .name_idx = 39159,
      .desc_idx = 2435,
      .symbol_name_idx = 38566,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1844] = {
      .name_idx = 34316,
      .desc_idx = 2388,
      .symbol_name_idx = 33723,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1845] = {
      .name_idx = 39185,
      .desc_idx = 2435,
      .symbol_name_idx = 38592,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1846] = {
      .name_idx = 34601,
      .desc_idx = 2388,
      .symbol_name_idx = 34008,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1847] = {
      .name_idx = 39481,
      .desc_idx = 2435,
      .symbol_name_idx = 38888,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1848] = {
      .name_idx = 34886,
      .desc_idx = 2388,
      .symbol_name_idx = 34293,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1849] = {
      .name_idx = 39777,
      .desc_idx = 2435,
      .symbol_name_idx = 39184,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1850] = {
      .name_idx = 34963,
      .desc_idx = 2388,
      .symbol_name_idx = 34370,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1851] = {
      .name_idx = 39857,
      .desc_idx = 2435,
      .symbol_name_idx = 39264,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1852] = {
      .name_idx = 34988,
      .desc_idx = 2388,
      .symbol_name_idx = 34395,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1853] = {
      .name_idx = 39883,
      .desc_idx = 2435,
      .symbol_name_idx = 39290,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1854] = {
      .name_idx = 35013,
      .desc_idx = 2388,
      .symbol_name_idx = 34420,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1855] = {
      .name_idx = 39909,
      .desc_idx = 2435,
      .symbol_name_idx = 39316,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1856] = {
      .name_idx = 35038,
      .desc_idx = 2388,
      .symbol_name_idx = 34445,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1857] = {
      .name_idx = 39935,
      .desc_idx = 2435,
      .symbol_name_idx = 39342,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1858] = {
      .name_idx = 112097,
      .desc_idx = 5904,
      .symbol_name_idx = 106903,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1859] = {
      .name_idx = 50018,
      .desc_idx = 5947,
      .symbol_name_idx = 50027,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1860] = {
      .name_idx = 112125,
      .desc_idx = 5904,
      .symbol_name_idx = 106931,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1861] = {
      .name_idx = 50059,
      .desc_idx = 5947,
      .symbol_name_idx = 50068,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1862] = {
      .name_idx = 112153,
      .desc_idx = 5904,
      .symbol_name_idx = 106959,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1863] = {
      .name_idx = 50100,
      .desc_idx = 5947,
      .symbol_name_idx = 50109,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1864] = {
      .name_idx = 112181,
      .desc_idx = 5904,
      .symbol_name_idx = 106987,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1865] = {
      .name_idx = 50141,
      .desc_idx = 5947,
      .symbol_name_idx = 50150,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1866] = {
      .name_idx = 112209,
      .desc_idx = 5904,
      .symbol_name_idx = 107015,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1867] = {
      .name_idx = 50182,
      .desc_idx = 5947,
      .symbol_name_idx = 50191,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1868] = {
      .name_idx = 112237,
      .desc_idx = 5904,
      .symbol_name_idx = 107043,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1869] = {
      .name_idx = 50223,
      .desc_idx = 5947,
      .symbol_name_idx = 50232,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1870] = {
      .name_idx = 112265,
      .desc_idx = 5904,
      .symbol_name_idx = 107071,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1871] = {
      .name_idx = 50264,
      .desc_idx = 5947,
      .symbol_name_idx = 50273,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1872] = {
      .name_idx = 112293,
      .desc_idx = 5904,
      .symbol_name_idx = 107099,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1873] = {
      .name_idx = 50305,
      .desc_idx = 5947,
      .symbol_name_idx = 50314,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1874] = {
      .name_idx = 112321,
      .desc_idx = 5904,
      .symbol_name_idx = 107127,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1875] = {
      .name_idx = 50346,
      .desc_idx = 5947,
      .symbol_name_idx = 50355,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1876] = {
      .name_idx = 112349,
      .desc_idx = 5904,
      .symbol_name_idx = 107155,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1877] = {
      .name_idx = 50387,
      .desc_idx = 5947,
      .symbol_name_idx = 50396,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1878] = {
      .name_idx = 112377,
      .desc_idx = 5904,
      .symbol_name_idx = 107183,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1879] = {
      .name_idx = 50428,
      .desc_idx = 5947,
      .symbol_name_idx = 50437,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1880] = {
      .name_idx = 112405,
      .desc_idx = 5904,
      .symbol_name_idx = 107211,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1881] = {
      .name_idx = 50469,
      .desc_idx = 5947,
      .symbol_name_idx = 50478,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1882] = {
      .name_idx = 112433,
      .desc_idx = 5904,
      .symbol_name_idx = 107239,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1883] = {
      .name_idx = 50510,
      .desc_idx = 5947,
      .symbol_name_idx = 50519,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1884] = {
      .name_idx = 112461,
      .desc_idx = 5904,
      .symbol_name_idx = 107267,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1885] = {
      .name_idx = 50551,
      .desc_idx = 5947,
      .symbol_name_idx = 50560,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1886] = {
      .name_idx = 112489,
      .desc_idx = 5904,
      .symbol_name_idx = 107295,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1887] = {
      .name_idx = 50592,
      .desc_idx = 5947,
      .symbol_name_idx = 50601,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1888] = {
      .name_idx = 112517,
      .desc_idx = 5904,
      .symbol_name_idx = 107323,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1889] = {
      .name_idx = 50633,
      .desc_idx = 5947,
      .symbol_name_idx = 50642,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1890] = {
      .name_idx = 112545,
      .desc_idx = 5904,
      .symbol_name_idx = 107351,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1891] = {
      .name_idx = 50674,
      .desc_idx = 5947,
      .symbol_name_idx = 50683,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1892] = {
      .name_idx = 112573,
      .desc_idx = 5904,
      .symbol_name_idx = 107379,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1893] = {
      .name_idx = 50715,
      .desc_idx = 5947,
      .symbol_name_idx = 50724,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1894] = {
      .name_idx = 112601,
      .desc_idx = 5904,
      .symbol_name_idx = 107407,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1895] = {
      .name_idx = 50756,
      .desc_idx = 5947,
      .symbol_name_idx = 50765,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1896] = {
      .name_idx = 112629,
      .desc_idx = 5904,
      .symbol_name_idx = 107435,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1897] = {
      .name_idx = 50797,
      .desc_idx = 5947,
      .symbol_name_idx = 50806,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1898] = {
      .name_idx = 112657,
      .desc_idx = 5904,
      .symbol_name_idx = 107463,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1899] = {
      .name_idx = 50838,
      .desc_idx = 5947,
      .symbol_name_idx = 50847,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1900] = {
      .name_idx = 112685,
      .desc_idx = 5904,
      .symbol_name_idx = 107491,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1901] = {
      .name_idx = 50879,
      .desc_idx = 5947,
      .symbol_name_idx = 50888,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1902] = {
      .name_idx = 112713,
      .desc_idx = 5904,
      .symbol_name_idx = 107519,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1903] = {
      .name_idx = 50920,
      .desc_idx = 5947,
      .symbol_name_idx = 50929,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1904] = {
      .name_idx = 112741,
      .desc_idx = 5904,
      .symbol_name_idx = 107547,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1905] = {
      .name_idx = 50961,
      .desc_idx = 5947,
      .symbol_name_idx = 50970,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1906] = {
      .name_idx = 112769,
      .desc_idx = 5904,
      .symbol_name_idx = 107575,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1907] = {
      .name_idx = 51002,
      .desc_idx = 5947,
      .symbol_name_idx = 51011,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1908] = {
      .name_idx = 112797,
      .desc_idx = 5904,
      .symbol_name_idx = 107603,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1909] = {
      .name_idx = 51043,
      .desc_idx = 5947,
      .symbol_name_idx = 51052,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1910] = {
      .name_idx = 112825,
      .desc_idx = 5904,
      .symbol_name_idx = 107631,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1911] = {
      .name_idx = 51084,
      .desc_idx = 5947,
      .symbol_name_idx = 51093,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1912] = {
      .name_idx = 112853,
      .desc_idx = 5904,
      .symbol_name_idx = 107659,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1913] = {
      .name_idx = 51125,
      .desc_idx = 5947,
      .symbol_name_idx = 51134,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1914] = {
      .name_idx = 112881,
      .desc_idx = 5904,
      .symbol_name_idx = 107687,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1915] = {
      .name_idx = 51166,
      .desc_idx = 5947,
      .symbol_name_idx = 51175,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1916] = {
      .name_idx = 112909,
      .desc_idx = 5904,
      .symbol_name_idx = 107715,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1917] = {
      .name_idx = 51207,
      .desc_idx = 5947,
      .symbol_name_idx = 51216,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1918] = {
      .name_idx = 112937,
      .desc_idx = 5904,
      .symbol_name_idx = 107743,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1919] = {
      .name_idx = 51248,
      .desc_idx = 5947,
      .symbol_name_idx = 51257,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1920] = {
      .name_idx = 112965,
      .desc_idx = 5904,
      .symbol_name_idx = 107771,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1921] = {
      .name_idx = 51289,
      .desc_idx = 5947,
      .symbol_name_idx = 51298,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1922] = {
      .name_idx = 113008,
      .desc_idx = 6440,
      .symbol_name_idx = 107814,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1923] = {
      .name_idx = 51358,
      .desc_idx = 6484,
      .symbol_name_idx = 51367,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1924] = {
      .name_idx = 113037,
      .desc_idx = 6440,
      .symbol_name_idx = 107843,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1925] = {
      .name_idx = 51400,
      .desc_idx = 6484,
      .symbol_name_idx = 51409,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1926] = {
      .name_idx = 113066,
      .desc_idx = 6440,
      .symbol_name_idx = 107872,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1927] = {
      .name_idx = 51442,
      .desc_idx = 6484,
      .symbol_name_idx = 51451,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1928] = {
      .name_idx = 113095,
      .desc_idx = 6440,
      .symbol_name_idx = 107901,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1929] = {
      .name_idx = 51484,
      .desc_idx = 6484,
      .symbol_name_idx = 51493,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1930] = {
      .name_idx = 113124,
      .desc_idx = 6440,
      .symbol_name_idx = 107930,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1931] = {
      .name_idx = 51526,
      .desc_idx = 6484,
      .symbol_name_idx = 51535,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1932] = {
      .name_idx = 113153,
      .desc_idx = 6440,
      .symbol_name_idx = 107959,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1933] = {
      .name_idx = 51568,
      .desc_idx = 6484,
      .symbol_name_idx = 51577,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1934] = {
      .name_idx = 113182,
      .desc_idx = 6440,
      .symbol_name_idx = 107988,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1935] = {
      .name_idx = 51610,
      .desc_idx = 6484,
      .symbol_name_idx = 51619,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1936] = {
      .name_idx = 113211,
      .desc_idx = 6440,
      .symbol_name_idx = 108017,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1937] = {
      .name_idx = 51652,
      .desc_idx = 6484,
      .symbol_name_idx = 51661,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1938] = {
      .name_idx = 113240,
      .desc_idx = 6440,
      .symbol_name_idx = 108046,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1939] = {
      .name_idx = 51694,
      .desc_idx = 6484,
      .symbol_name_idx = 51703,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1940] = {
      .name_idx = 113269,
      .desc_idx = 6440,
      .symbol_name_idx = 108075,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1941] = {
      .name_idx = 51736,
      .desc_idx = 6484,
      .symbol_name_idx = 51745,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1942] = {
      .name_idx = 113298,
      .desc_idx = 6440,
      .symbol_name_idx = 108104,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1943] = {
      .name_idx = 51778,
      .desc_idx = 6484,
      .symbol_name_idx = 51787,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1944] = {
      .name_idx = 113327,
      .desc_idx = 6440,
      .symbol_name_idx = 108133,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1945] = {
      .name_idx = 51820,
      .desc_idx = 6484,
      .symbol_name_idx = 51829,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1946] = {
      .name_idx = 113356,
      .desc_idx = 6440,
      .symbol_name_idx = 108162,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1947] = {
      .name_idx = 51862,
      .desc_idx = 6484,
      .symbol_name_idx = 51871,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1948] = {
      .name_idx = 113385,
      .desc_idx = 6440,
      .symbol_name_idx = 108191,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1949] = {
      .name_idx = 51904,
      .desc_idx = 6484,
      .symbol_name_idx = 51913,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1950] = {
      .name_idx = 113414,
      .desc_idx = 6440,
      .symbol_name_idx = 108220,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1951] = {
      .name_idx = 51946,
      .desc_idx = 6484,
      .symbol_name_idx = 51955,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1952] = {
      .name_idx = 113443,
      .desc_idx = 6440,
      .symbol_name_idx = 108249,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1953] = {
      .name_idx = 51988,
      .desc_idx = 6484,
      .symbol_name_idx = 51997,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1954] = {
      .name_idx = 113472,
      .desc_idx = 6440,
      .symbol_name_idx = 108278,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1955] = {
      .name_idx = 52030,
      .desc_idx = 6484,
      .symbol_name_idx = 52039,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1956] = {
      .name_idx = 113501,
      .desc_idx = 6440,
      .symbol_name_idx = 108307,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1957] = {
      .name_idx = 52072,
      .desc_idx = 6484,
      .symbol_name_idx = 52081,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1958] = {
      .name_idx = 113530,
      .desc_idx = 6440,
      .symbol_name_idx = 108336,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1959] = {
      .name_idx = 52114,
      .desc_idx = 6484,
      .symbol_name_idx = 52123,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1960] = {
      .name_idx = 113559,
      .desc_idx = 6440,
      .symbol_name_idx = 108365,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1961] = {
      .name_idx = 52156,
      .desc_idx = 6484,
      .symbol_name_idx = 52165,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1962] = {
      .name_idx = 113588,
      .desc_idx = 6440,
      .symbol_name_idx = 108394,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1963] = {
      .name_idx = 52198,
      .desc_idx = 6484,
      .symbol_name_idx = 52207,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1964] = {
      .name_idx = 113617,
      .desc_idx = 6440,
      .symbol_name_idx = 108423,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1965] = {
      .name_idx = 52240,
      .desc_idx = 6484,
      .symbol_name_idx = 52249,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1966] = {
      .name_idx = 113646,
      .desc_idx = 6440,
      .symbol_name_idx = 108452,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1967] = {
      .name_idx = 52282,
      .desc_idx = 6484,
      .symbol_name_idx = 52291,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1968] = {
      .name_idx = 113675,
      .desc_idx = 6440,
      .symbol_name_idx = 108481,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1969] = {
      .name_idx = 52324,
      .desc_idx = 6484,
      .symbol_name_idx = 52333,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1970] = {
      .name_idx = 113704,
      .desc_idx = 6440,
      .symbol_name_idx = 108510,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1971] = {
      .name_idx = 52366,
      .desc_idx = 6484,
      .symbol_name_idx = 52375,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1972] = {
      .name_idx = 113733,
      .desc_idx = 6440,
      .symbol_name_idx = 108539,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1973] = {
      .name_idx = 52408,
      .desc_idx = 6484,
      .symbol_name_idx = 52417,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1974] = {
      .name_idx = 113762,
      .desc_idx = 6440,
      .symbol_name_idx = 108568,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1975] = {
      .name_idx = 52450,
      .desc_idx = 6484,
      .symbol_name_idx = 52459,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1976] = {
      .name_idx = 113791,
      .desc_idx = 6440,
      .symbol_name_idx = 108597,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1977] = {
      .name_idx = 52492,
      .desc_idx = 6484,
      .symbol_name_idx = 52501,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1978] = {
      .name_idx = 113820,
      .desc_idx = 6440,
      .symbol_name_idx = 108626,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1979] = {
      .name_idx = 52534,
      .desc_idx = 6484,
      .symbol_name_idx = 52543,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1980] = {
      .name_idx = 113849,
      .desc_idx = 6440,
      .symbol_name_idx = 108655,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1981] = {
      .name_idx = 52576,
      .desc_idx = 6484,
      .symbol_name_idx = 52585,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1982] = {
      .name_idx = 113878,
      .desc_idx = 6440,
      .symbol_name_idx = 108684,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1983] = {
      .name_idx = 52618,
      .desc_idx = 6484,
      .symbol_name_idx = 52627,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1984] = {
      .name_idx = 113907,
      .desc_idx = 6440,
      .symbol_name_idx = 108713,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1985] = {
      .name_idx = 52660,
      .desc_idx = 6484,
      .symbol_name_idx = 52669,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [1986] = {
      .name_idx = 155081,
      .desc_idx = 7954,
      .symbol_name_idx = 132535,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1987] = {
      .name_idx = 188533,
      .desc_idx = 7856,
      .symbol_name_idx = 165939,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1988] = {
      .name_idx = 194112,
      .desc_idx = 18873,
      .symbol_name_idx = 171508,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1989] = {
      .name_idx = 179187,
      .desc_idx = 9142,
      .symbol_name_idx = 156593,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1990] = {
      .name_idx = 179253,
      .desc_idx = 7756,
      .symbol_name_idx = 156659,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1991] = {
      .name_idx = 164591,
      .desc_idx = 14019,
      .symbol_name_idx = 141997,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1992] = {
      .name_idx = 164185,
      .desc_idx = 13425,
      .symbol_name_idx = 141527,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1993] = {
      .name_idx = 163993,
      .desc_idx = 12811,
      .symbol_name_idx = 141399,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1994] = {
      .name_idx = 164057,
      .desc_idx = 13013,
      .symbol_name_idx = 141655,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1995] = {
      .name_idx = 163929,
      .desc_idx = 12565,
      .symbol_name_idx = 141335,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1996] = {
      .name_idx = 163853,
      .desc_idx = 11711,
      .symbol_name_idx = 141259,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1997] = {
      .name_idx = 165459,
      .desc_idx = 14120,
      .symbol_name_idx = 142865,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1998] = {
      .name_idx = 165053,
      .desc_idx = 13524,
      .symbol_name_idx = 142395,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [1999] = {
      .name_idx = 164861,
      .desc_idx = 12912,
      .symbol_name_idx = 142267,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2000] = {
      .name_idx = 164925,
      .desc_idx = 13116,
      .symbol_name_idx = 142523,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2001] = {
      .name_idx = 164797,
      .desc_idx = 12688,
      .symbol_name_idx = 142203,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2002] = {
      .name_idx = 164721,
      .desc_idx = 11819,
      .symbol_name_idx = 142127,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2003] = {
      .name_idx = 164617,
      .desc_idx = 22535,
      .symbol_name_idx = 142023,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2004] = {
      .name_idx = 164211,
      .desc_idx = 21911,
      .symbol_name_idx = 141553,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2005] = {
      .name_idx = 164019,
      .desc_idx = 21267,
      .symbol_name_idx = 141425,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2006] = {
      .name_idx = 164083,
      .desc_idx = 21479,
      .symbol_name_idx = 141681,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2007] = {
      .name_idx = 163955,
      .desc_idx = 21011,
      .symbol_name_idx = 141361,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2008] = {
      .name_idx = 163885,
      .desc_idx = 20117,
      .symbol_name_idx = 141291,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2009] = {
      .name_idx = 165485,
      .desc_idx = 22641,
      .symbol_name_idx = 142891,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2010] = {
      .name_idx = 165079,
      .desc_idx = 22015,
      .symbol_name_idx = 142421,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2011] = {
      .name_idx = 164887,
      .desc_idx = 21373,
      .symbol_name_idx = 142293,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2012] = {
      .name_idx = 164951,
      .desc_idx = 21587,
      .symbol_name_idx = 142549,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2013] = {
      .name_idx = 164823,
      .desc_idx = 21139,
      .symbol_name_idx = 142229,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2014] = {
      .name_idx = 164753,
      .desc_idx = 20230,
      .symbol_name_idx = 142159,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2015] = {
      .name_idx = 164343,
      .desc_idx = 20343,
      .symbol_name_idx = 141749,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2016] = {
      .name_idx = 165211,
      .desc_idx = 20454,
      .symbol_name_idx = 142617,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2017] = {
      .name_idx = 166503,
      .desc_idx = 32195,
      .symbol_name_idx = 143909,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2018] = {
      .name_idx = 164415,
      .desc_idx = 20565,
      .symbol_name_idx = 141821,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2019] = {
      .name_idx = 165283,
      .desc_idx = 20680,
      .symbol_name_idx = 142689,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2020] = {
      .name_idx = 166575,
      .desc_idx = 32303,
      .symbol_name_idx = 143981,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2021] = {
      .name_idx = 164486,
      .desc_idx = 20795,
      .symbol_name_idx = 141892,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2022] = {
      .name_idx = 165354,
      .desc_idx = 20903,
      .symbol_name_idx = 142760,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2023] = {
      .name_idx = 166646,
      .desc_idx = 32415,
      .symbol_name_idx = 144052,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2024] = {
      .name_idx = 164313,
      .desc_idx = 11927,
      .symbol_name_idx = 141719,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2025] = {
      .name_idx = 165181,
      .desc_idx = 12033,
      .symbol_name_idx = 142587,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2026] = {
      .name_idx = 166473,
      .desc_idx = 14982,
      .symbol_name_idx = 143879,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2027] = {
      .name_idx = 164385,
      .desc_idx = 12139,
      .symbol_name_idx = 141791,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2028] = {
      .name_idx = 165253,
      .desc_idx = 12249,
      .symbol_name_idx = 142659,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2029] = {
      .name_idx = 166545,
      .desc_idx = 15071,
      .symbol_name_idx = 143951,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2030] = {
      .name_idx = 164457,
      .desc_idx = 12359,
      .symbol_name_idx = 141863,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2031] = {
      .name_idx = 165325,
      .desc_idx = 12462,
      .symbol_name_idx = 142731,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2032] = {
      .name_idx = 166617,
      .desc_idx = 15164,
      .symbol_name_idx = 144023,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2033] = {
      .name_idx = 186919,
      .desc_idx = 30116,
      .symbol_name_idx = 164325,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2034] = {
      .name_idx = 188520,
      .desc_idx = 30249,
      .symbol_name_idx = 165926,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2035] = {
      .name_idx = 188756,
      .desc_idx = 30397,
      .symbol_name_idx = 166162,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2036] = {
      .name_idx = 188795,
      .desc_idx = 30779,
      .symbol_name_idx = 166188,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2037] = {
      .name_idx = 190142,
      .desc_idx = 30903,
      .symbol_name_idx = 167535,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2038] = {
      .name_idx = 188769,
      .desc_idx = 30523,
      .symbol_name_idx = 169018,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2039] = {
      .name_idx = 194050,
      .desc_idx = 31158,
      .symbol_name_idx = 171456,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2040] = {
      .name_idx = 194063,
      .desc_idx = 31282,
      .symbol_name_idx = 171469,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2041] = {
      .name_idx = 191625,
      .desc_idx = 31027,
      .symbol_name_idx = 169031,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2042] = {
      .name_idx = 188550,
      .desc_idx = 9246,
      .symbol_name_idx = 165956,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2043] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .desc_idx = 21695,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .category_idx = 1222,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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      .category_idx = 1222,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .desc_idx = 1208,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [2103] = {
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      .desc_idx = 5706,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
   [2104] = {
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      .desc_idx = 16279,
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      .category_idx = 1113,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [2105] = {
      .name_idx = 67810,
      .desc_idx = 1336,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_PIXELS,
   },
   [2106] = {
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      .desc_idx = 129527,
      .symbol_name_idx = 132480,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_THREADS,
   },
   [2107] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1192,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .category_idx = 1192,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1192,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2257] = {
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      .desc_idx = 14616,
      .symbol_name_idx = 300,
      .category_idx = 350,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2258] = {
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      .desc_idx = 6679,
      .symbol_name_idx = 478,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2259] = {
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      .desc_idx = 4881,
      .symbol_name_idx = 64,
      .category_idx = 350,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 23380,
      .symbol_name_idx = 1416,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 23467,
      .symbol_name_idx = 1192,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 14616,
      .symbol_name_idx = 322,
      .category_idx = 350,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2263] = {
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      .desc_idx = 6679,
      .symbol_name_idx = 501,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2264] = {
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      .desc_idx = 4881,
      .symbol_name_idx = 96,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2265] = {
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      .desc_idx = 23380,
      .symbol_name_idx = 1444,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2266] = {
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      .desc_idx = 23467,
      .symbol_name_idx = 1220,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2267] = {
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      .desc_idx = 1486,
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      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2268] = {
      .name_idx = 858,
      .desc_idx = 1486,
      .symbol_name_idx = 858,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2269] = {
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      .desc_idx = 1442,
      .symbol_name_idx = 660,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2270] = {
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      .desc_idx = 1442,
      .symbol_name_idx = 682,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2271] = {
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      .desc_idx = 1529,
      .symbol_name_idx = 1010,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2272] = {
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      .desc_idx = 1529,
      .symbol_name_idx = 1031,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2273] = {
      .name_idx = 75402,
      .desc_idx = 4230,
      .symbol_name_idx = 70249,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2274] = {
      .name_idx = 75750,
      .desc_idx = 4272,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2275] = {
      .name_idx = 75960,
      .desc_idx = 4315,
      .symbol_name_idx = 71229,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2276] = {
      .name_idx = 76198,
      .desc_idx = 39309,
      .symbol_name_idx = 70473,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2277] = {
      .name_idx = 76496,
      .desc_idx = 39380,
      .symbol_name_idx = 70763,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2278] = {
      .name_idx = 75427,
      .desc_idx = 4230,
      .symbol_name_idx = 70274,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2279] = {
      .name_idx = 75776,
      .desc_idx = 4272,
      .symbol_name_idx = 71045,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4315,
      .symbol_name_idx = 71256,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2281] = {
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      .desc_idx = 39309,
      .symbol_name_idx = 70510,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2282] = {
      .name_idx = 76531,
      .desc_idx = 39380,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2284] = {
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      .desc_idx = 23975,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2285] = {
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      .desc_idx = 23975,
      .symbol_name_idx = 7456,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2286] = {
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      .desc_idx = 23975,
      .symbol_name_idx = 7495,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2287] = {
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      .desc_idx = 24098,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2288] = {
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      .desc_idx = 24098,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 23828,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2290] = {
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      .desc_idx = 23828,
      .symbol_name_idx = 65374,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2291] = {
      .name_idx = 66656,
      .desc_idx = 23828,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2292] = {
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      .desc_idx = 23828,
      .symbol_name_idx = 65458,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2293] = {
      .name_idx = 68200,
      .desc_idx = 24934,
      .symbol_name_idx = 68073,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2294] = {
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      .desc_idx = 24934,
      .symbol_name_idx = 68100,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2295] = {
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      .desc_idx = 24934,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2296] = {
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      .desc_idx = 24934,
      .symbol_name_idx = 68154,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2297] = {
      .name_idx = 67564,
      .desc_idx = 23898,
      .symbol_name_idx = 66324,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2298] = {
      .name_idx = 67603,
      .desc_idx = 23898,
      .symbol_name_idx = 66363,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2299] = {
      .name_idx = 67642,
      .desc_idx = 23898,
      .symbol_name_idx = 66402,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2300] = {
      .name_idx = 67681,
      .desc_idx = 23898,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2659] = {
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      .desc_idx = 3558,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 48834,
      .desc_idx = 3558,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2661] = {
      .name_idx = 48319,
      .desc_idx = 3558,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 48337,
      .desc_idx = 3558,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2663] = {
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      .desc_idx = 3558,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 48373,
      .desc_idx = 3558,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3558,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2666] = {
      .name_idx = 48409,
      .desc_idx = 3558,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2667] = {
      .name_idx = 45188,
      .desc_idx = 2484,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2668] = {
      .name_idx = 45203,
      .desc_idx = 2484,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 44746,
      .desc_idx = 2484,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2484,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2671] = {
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      .desc_idx = 2484,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2672] = {
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      .desc_idx = 2484,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 44810,
      .desc_idx = 2484,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 44826,
      .desc_idx = 2484,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2675] = {
      .name_idx = 45962,
      .desc_idx = 2547,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2676] = {
      .name_idx = 45978,
      .desc_idx = 2547,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2677] = {
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      .desc_idx = 2547,
      .symbol_name_idx = 45238,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2678] = {
      .name_idx = 45509,
      .desc_idx = 2547,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2679] = {
      .name_idx = 45526,
      .desc_idx = 2547,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2680] = {
      .name_idx = 45543,
      .desc_idx = 2547,
      .symbol_name_idx = 45289,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2681] = {
      .name_idx = 45560,
      .desc_idx = 2547,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2682] = {
      .name_idx = 45577,
      .desc_idx = 2547,
      .symbol_name_idx = 45323,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2683] = {
      .name_idx = 14051,
      .desc_idx = 2990,
      .symbol_name_idx = 13862,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2684] = {
      .name_idx = 14076,
      .desc_idx = 2990,
      .symbol_name_idx = 13887,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2685] = {
      .name_idx = 13329,
      .desc_idx = 2990,
      .symbol_name_idx = 13140,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2686] = {
      .name_idx = 13355,
      .desc_idx = 2990,
      .symbol_name_idx = 13166,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2687] = {
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 24782,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 3404,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2732] = {
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      .desc_idx = 3404,
      .symbol_name_idx = 99973,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3404,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3404,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3404,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3404,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3404,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2738] = {
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      .desc_idx = 3404,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2707,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2707,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2707,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 103488,
      .desc_idx = 2707,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2707,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2707,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2745] = {
      .name_idx = 103560,
      .desc_idx = 2707,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2707,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2747] = {
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      .desc_idx = 27698,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2748] = {
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      .desc_idx = 27698,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2749] = {
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      .desc_idx = 27698,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2750] = {
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      .desc_idx = 27698,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2751] = {
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      .desc_idx = 27698,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2753] = {
      .name_idx = 47606,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2754] = {
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      .desc_idx = 27698,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2755] = {
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      .desc_idx = 3308,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2756] = {
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      .desc_idx = 3308,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3308,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2758] = {
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      .desc_idx = 3308,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3308,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3308,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3308,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2763] = {
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      .desc_idx = 3216,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3216,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3216,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3216,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3216,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3216,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3216,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3216,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2771] = {
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      .desc_idx = 2804,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2772] = {
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      .desc_idx = 2804,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2773] = {
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      .desc_idx = 2804,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2804,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2775] = {
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      .desc_idx = 2804,
      .symbol_name_idx = 12398,
      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2776] = {
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      .desc_idx = 2804,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2777] = {
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      .desc_idx = 2804,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2804,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2779] = {
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      .desc_idx = 5507,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5507,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5507,
      .symbol_name_idx = 42485,
      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2782] = {
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      .desc_idx = 5507,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2783] = {
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      .desc_idx = 5507,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2784] = {
      .name_idx = 41081,
      .desc_idx = 5507,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2785] = {
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      .desc_idx = 5507,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2786] = {
      .name_idx = 41133,
      .desc_idx = 5507,
      .symbol_name_idx = 42615,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2787] = {
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      .desc_idx = 10418,
      .symbol_name_idx = 24449,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .desc_idx = 10418,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .name_idx = 25711,
      .desc_idx = 10739,
      .symbol_name_idx = 24978,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .name_idx = 25740,
      .desc_idx = 10739,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .desc_idx = 296,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .name_idx = 24971,
      .desc_idx = 296,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
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      .desc_idx = 368,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [2794] = {
      .name_idx = 25493,
      .desc_idx = 368,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [2795] = {
      .name_idx = 26371,
      .desc_idx = 2108,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2796] = {
      .name_idx = 26394,
      .desc_idx = 2108,
      .symbol_name_idx = 25661,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2797] = {
      .name_idx = 26900,
      .desc_idx = 2224,
      .symbol_name_idx = 26167,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2798] = {
      .name_idx = 26924,
      .desc_idx = 2224,
      .symbol_name_idx = 26191,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2799] = {
      .name_idx = 23331,
      .desc_idx = 10577,
      .symbol_name_idx = 22598,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2800] = {
      .name_idx = 23370,
      .desc_idx = 10577,
      .symbol_name_idx = 22637,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2801] = {
      .name_idx = 24028,
      .desc_idx = 10658,
      .symbol_name_idx = 23295,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2802] = {
      .name_idx = 24067,
      .desc_idx = 10658,
      .symbol_name_idx = 23334,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2803] = {
      .name_idx = 23678,
      .desc_idx = 10900,
      .symbol_name_idx = 22945,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2804] = {
      .name_idx = 23718,
      .desc_idx = 10900,
      .symbol_name_idx = 22985,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2805] = {
      .name_idx = 24375,
      .desc_idx = 10982,
      .symbol_name_idx = 23642,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2806] = {
      .name_idx = 24415,
      .desc_idx = 10982,
      .symbol_name_idx = 23682,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2807] = {
      .name_idx = 24683,
      .desc_idx = 29378,
      .symbol_name_idx = 23950,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2808] = {
      .name_idx = 24708,
      .desc_idx = 29378,
      .symbol_name_idx = 23975,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2809] = {
      .name_idx = 26613,
      .desc_idx = 25453,
      .symbol_name_idx = 25880,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2810] = {
      .name_idx = 26650,
      .desc_idx = 25453,
      .symbol_name_idx = 25917,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2811] = {
      .name_idx = 24615,
      .desc_idx = 29378,
      .symbol_name_idx = 23882,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2812] = {
      .name_idx = 26509,
      .desc_idx = 25453,
      .symbol_name_idx = 25776,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2813] = {
      .name_idx = 26147,
      .desc_idx = 2266,
      .symbol_name_idx = 25414,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2814] = {
      .name_idx = 26174,
      .desc_idx = 2266,
      .symbol_name_idx = 25441,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2815] = {
      .name_idx = 25937,
      .desc_idx = 2149,
      .symbol_name_idx = 25204,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2816] = {
      .name_idx = 25963,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 23064,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19329,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 3978,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16674,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 23064,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19072,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 25262,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 18016,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 89012,
      .desc_idx = 19329,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 98052,
      .desc_idx = 3978,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 95050,
      .desc_idx = 16674,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 96056,
      .desc_idx = 23064,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 82558,
      .desc_idx = 19072,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 90642,
      .desc_idx = 25262,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 17177,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 87510,
      .desc_idx = 18016,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19329,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3978,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16674,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 23064,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2868] = {
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      .desc_idx = 19072,
      .symbol_name_idx = 77279,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2869] = {
      .name_idx = 90674,
      .desc_idx = 25262,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 17177,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2871] = {
      .name_idx = 87558,
      .desc_idx = 18016,
      .symbol_name_idx = 82243,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2872] = {
      .name_idx = 89120,
      .desc_idx = 19329,
      .symbol_name_idx = 83805,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 98128,
      .desc_idx = 3978,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2874] = {
      .name_idx = 95114,
      .desc_idx = 16674,
      .symbol_name_idx = 89799,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2875] = {
      .name_idx = 96116,
      .desc_idx = 23064,
      .symbol_name_idx = 90801,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 82630,
      .desc_idx = 19072,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2877] = {
      .name_idx = 90706,
      .desc_idx = 25262,
      .symbol_name_idx = 85391,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .name_idx = 97078,
      .desc_idx = 17177,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2879] = {
      .name_idx = 87606,
      .desc_idx = 18016,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2880] = {
      .name_idx = 89174,
      .desc_idx = 19329,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 25262,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
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   },
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 1748,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 1748,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 14812,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16126,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 1748,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 14812,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 1748,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 14812,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 14812,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 14812,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 17396,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 18993,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17396,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2917] = {
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      .desc_idx = 18993,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17396,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18993,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17396,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18993,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17396,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18993,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17396,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18993,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17396,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2934] = {
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      .desc_idx = 4035,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2935] = {
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      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2938] = {
      .name_idx = 76824,
      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2939] = {
      .name_idx = 76864,
      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2940] = {
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      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2941] = {
      .name_idx = 76944,
      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2942] = {
      .name_idx = 76984,
      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2943] = {
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      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2944] = {
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      .desc_idx = 7325,
      .symbol_name_idx = 74777,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2945] = {
      .name_idx = 78910,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2946] = {
      .name_idx = 78951,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2947] = {
      .name_idx = 78992,
      .desc_idx = 7325,
      .symbol_name_idx = 73677,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2948] = {
      .name_idx = 79033,
      .desc_idx = 7325,
      .symbol_name_idx = 73718,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2949] = {
      .name_idx = 79074,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2950] = {
      .name_idx = 79115,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2951] = {
      .name_idx = 81444,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2952] = {
      .name_idx = 81487,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2953] = {
      .name_idx = 80218,
      .desc_idx = 7466,
      .symbol_name_idx = 74903,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2954] = {
      .name_idx = 80262,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2955] = {
      .name_idx = 80306,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2956] = {
      .name_idx = 80350,
      .desc_idx = 7466,
      .symbol_name_idx = 75035,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2957] = {
      .name_idx = 80394,
      .desc_idx = 7466,
      .symbol_name_idx = 75079,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2958] = {
      .name_idx = 80438,
      .desc_idx = 7466,
      .symbol_name_idx = 75123,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2959] = {
      .name_idx = 87184,
      .desc_idx = 16205,
      .symbol_name_idx = 81869,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2960] = {
      .name_idx = 87228,
      .desc_idx = 16205,
      .symbol_name_idx = 81913,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2961] = {
      .name_idx = 85930,
      .desc_idx = 16205,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2962] = {
      .name_idx = 85975,
      .desc_idx = 16205,
      .symbol_name_idx = 80660,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2963] = {
      .name_idx = 86020,
      .desc_idx = 16205,
      .symbol_name_idx = 80705,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2964] = {
      .name_idx = 86065,
      .desc_idx = 16205,
      .symbol_name_idx = 80750,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2965] = {
      .name_idx = 86110,
      .desc_idx = 16205,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2966] = {
      .name_idx = 86155,
      .desc_idx = 16205,
      .symbol_name_idx = 80840,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2967] = {
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      .desc_idx = 16608,
      .symbol_name_idx = 87317,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2968] = {
      .name_idx = 92668,
      .desc_idx = 16608,
      .symbol_name_idx = 87353,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2969] = {
      .name_idx = 91602,
      .desc_idx = 16608,
      .symbol_name_idx = 86287,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2970] = {
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      .desc_idx = 16608,
      .symbol_name_idx = 86324,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2971] = {
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      .desc_idx = 16608,
      .symbol_name_idx = 86361,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2972] = {
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      .desc_idx = 16608,
      .symbol_name_idx = 86398,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2973] = {
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      .desc_idx = 16608,
      .symbol_name_idx = 86435,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2974] = {
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      .desc_idx = 16608,
      .symbol_name_idx = 86472,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2975] = {
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      .desc_idx = 1689,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2976] = {
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      .desc_idx = 1689,
      .symbol_name_idx = 73489,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2977] = {
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      .desc_idx = 1689,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2978] = {
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      .desc_idx = 1689,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2979] = {
      .name_idx = 78082,
      .desc_idx = 1689,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2980] = {
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2981] = {
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      .desc_idx = 1689,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2982] = {
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      .desc_idx = 1689,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [2983] = {
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      .desc_idx = 29562,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2984] = {
      .name_idx = 82389,
      .desc_idx = 29562,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2985] = {
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      .desc_idx = 29562,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2986] = {
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      .desc_idx = 29562,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 29562,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2988] = {
      .name_idx = 81668,
      .desc_idx = 29562,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2989] = {
      .name_idx = 81696,
      .desc_idx = 29562,
      .symbol_name_idx = 76381,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2990] = {
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      .desc_idx = 29562,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2991] = {
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      .desc_idx = 25618,
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2992] = {
      .name_idx = 107109,
      .desc_idx = 25618,
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2993] = {
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      .desc_idx = 25618,
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2994] = {
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      .desc_idx = 25618,
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2995] = {
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      .desc_idx = 25618,
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2996] = {
      .name_idx = 106336,
      .desc_idx = 25618,
      .symbol_name_idx = 101351,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2997] = {
      .name_idx = 106366,
      .desc_idx = 25618,
      .symbol_name_idx = 101381,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2998] = {
      .name_idx = 106396,
      .desc_idx = 25618,
      .symbol_name_idx = 101411,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [2999] = {
      .name_idx = 102330,
      .desc_idx = 25685,
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3000] = {
      .name_idx = 102351,
      .desc_idx = 25685,
      .symbol_name_idx = 97366,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3001] = {
      .name_idx = 101720,
      .desc_idx = 25685,
      .symbol_name_idx = 96735,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3002] = {
      .name_idx = 101742,
      .desc_idx = 25685,
      .symbol_name_idx = 96757,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3003] = {
      .name_idx = 101764,
      .desc_idx = 25685,
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3004] = {
      .name_idx = 101786,
      .desc_idx = 25685,
      .symbol_name_idx = 96801,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3005] = {
      .name_idx = 101808,
      .desc_idx = 25685,
      .symbol_name_idx = 96823,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3006] = {
      .name_idx = 101830,
      .desc_idx = 25685,
      .symbol_name_idx = 96845,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3007] = {
      .name_idx = 106114,
      .desc_idx = 25752,
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3008] = {
      .name_idx = 106151,
      .desc_idx = 25752,
      .symbol_name_idx = 101166,
      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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   },
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   },
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   },
   [3202] = {
      .name_idx = 190381,
      .desc_idx = 27492,
      .symbol_name_idx = 167737,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3203] = {
      .name_idx = 191858,
      .desc_idx = 27366,
      .symbol_name_idx = 169228,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3204] = {
      .name_idx = 193044,
      .desc_idx = 27246,
      .symbol_name_idx = 170412,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3205] = {
      .name_idx = 179611,
      .desc_idx = 26563,
      .symbol_name_idx = 156964,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3206] = {
      .name_idx = 185977,
      .desc_idx = 26758,
      .symbol_name_idx = 163346,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3207] = {
      .name_idx = 187216,
      .desc_idx = 26881,
      .symbol_name_idx = 164583,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3208] = {
      .name_idx = 189100,
      .desc_idx = 27007,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3209] = {
      .name_idx = 190419,
      .desc_idx = 27492,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3210] = {
      .name_idx = 191895,
      .desc_idx = 27366,
      .symbol_name_idx = 169265,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3211] = {
      .name_idx = 193083,
      .desc_idx = 27246,
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      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3212] = {
      .name_idx = 179665,
      .desc_idx = 26563,
      .symbol_name_idx = 157018,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3213] = {
      .name_idx = 32597,
      .desc_idx = 2388,
      .symbol_name_idx = 32004,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3214] = {
      .name_idx = 32622,
      .desc_idx = 2388,
      .symbol_name_idx = 32029,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3215] = {
      .name_idx = 31875,
      .desc_idx = 2388,
      .symbol_name_idx = 31282,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3216] = {
      .name_idx = 31901,
      .desc_idx = 2388,
      .symbol_name_idx = 31308,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3217] = {
      .name_idx = 31927,
      .desc_idx = 2388,
      .symbol_name_idx = 31334,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3218] = {
      .name_idx = 31953,
      .desc_idx = 2388,
      .symbol_name_idx = 31360,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3219] = {
      .name_idx = 31979,
      .desc_idx = 2388,
      .symbol_name_idx = 31386,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3220] = {
      .name_idx = 32005,
      .desc_idx = 2388,
      .symbol_name_idx = 31412,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3221] = {
      .name_idx = 37399,
      .desc_idx = 2435,
      .symbol_name_idx = 36806,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3222] = {
      .name_idx = 37425,
      .desc_idx = 2435,
      .symbol_name_idx = 36832,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3223] = {
      .name_idx = 36649,
      .desc_idx = 2435,
      .symbol_name_idx = 36056,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3224] = {
      .name_idx = 36676,
      .desc_idx = 2435,
      .symbol_name_idx = 36083,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3225] = {
      .name_idx = 36703,
      .desc_idx = 2435,
      .symbol_name_idx = 36110,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3226] = {
      .name_idx = 36730,
      .desc_idx = 2435,
      .symbol_name_idx = 36137,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3227] = {
      .name_idx = 36757,
      .desc_idx = 2435,
      .symbol_name_idx = 36164,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3228] = {
      .name_idx = 36784,
      .desc_idx = 2435,
      .symbol_name_idx = 36191,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3229] = {
      .name_idx = 33419,
      .desc_idx = 2388,
      .symbol_name_idx = 32826,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3230] = {
      .name_idx = 33444,
      .desc_idx = 2388,
      .symbol_name_idx = 32851,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3231] = {
      .name_idx = 32697,
      .desc_idx = 2388,
      .symbol_name_idx = 32104,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3232] = {
      .name_idx = 32723,
      .desc_idx = 2388,
      .symbol_name_idx = 32130,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3233] = {
      .name_idx = 32749,
      .desc_idx = 2388,
      .symbol_name_idx = 32156,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3234] = {
      .name_idx = 32775,
      .desc_idx = 2388,
      .symbol_name_idx = 32182,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3235] = {
      .name_idx = 32801,
      .desc_idx = 2388,
      .symbol_name_idx = 32208,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3236] = {
      .name_idx = 32827,
      .desc_idx = 2388,
      .symbol_name_idx = 32234,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3237] = {
      .name_idx = 38253,
      .desc_idx = 2435,
      .symbol_name_idx = 37660,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3238] = {
      .name_idx = 38279,
      .desc_idx = 2435,
      .symbol_name_idx = 37686,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3239] = {
      .name_idx = 37503,
      .desc_idx = 2435,
      .symbol_name_idx = 36910,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3240] = {
      .name_idx = 37530,
      .desc_idx = 2435,
      .symbol_name_idx = 36937,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3241] = {
      .name_idx = 37557,
      .desc_idx = 2435,
      .symbol_name_idx = 36964,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3242] = {
      .name_idx = 37584,
      .desc_idx = 2435,
      .symbol_name_idx = 36991,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3243] = {
      .name_idx = 37611,
      .desc_idx = 2435,
      .symbol_name_idx = 37018,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3244] = {
      .name_idx = 37638,
      .desc_idx = 2435,
      .symbol_name_idx = 37045,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3245] = {
      .name_idx = 34241,
      .desc_idx = 2388,
      .symbol_name_idx = 33648,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3246] = {
      .name_idx = 34266,
      .desc_idx = 2388,
      .symbol_name_idx = 33673,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3247] = {
      .name_idx = 33519,
      .desc_idx = 2388,
      .symbol_name_idx = 32926,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3248] = {
      .name_idx = 33545,
      .desc_idx = 2388,
      .symbol_name_idx = 32952,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3249] = {
      .name_idx = 33571,
      .desc_idx = 2388,
      .symbol_name_idx = 32978,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3250] = {
      .name_idx = 33597,
      .desc_idx = 2388,
      .symbol_name_idx = 33004,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3251] = {
      .name_idx = 33623,
      .desc_idx = 2388,
      .symbol_name_idx = 33030,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3252] = {
      .name_idx = 33649,
      .desc_idx = 2388,
      .symbol_name_idx = 33056,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3253] = {
      .name_idx = 39107,
      .desc_idx = 2435,
      .symbol_name_idx = 38514,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3254] = {
      .name_idx = 39133,
      .desc_idx = 2435,
      .symbol_name_idx = 38540,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3255] = {
      .name_idx = 38357,
      .desc_idx = 2435,
      .symbol_name_idx = 37764,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3256] = {
      .name_idx = 38384,
      .desc_idx = 2435,
      .symbol_name_idx = 37791,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3257] = {
      .name_idx = 38411,
      .desc_idx = 2435,
      .symbol_name_idx = 37818,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3258] = {
      .name_idx = 38438,
      .desc_idx = 2435,
      .symbol_name_idx = 37845,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3259] = {
      .name_idx = 38465,
      .desc_idx = 2435,
      .symbol_name_idx = 37872,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3260] = {
      .name_idx = 38492,
      .desc_idx = 2435,
      .symbol_name_idx = 37899,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3261] = {
      .name_idx = 35063,
      .desc_idx = 2388,
      .symbol_name_idx = 34470,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3262] = {
      .name_idx = 35088,
      .desc_idx = 2388,
      .symbol_name_idx = 34495,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3263] = {
      .name_idx = 34341,
      .desc_idx = 2388,
      .symbol_name_idx = 33748,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3264] = {
      .name_idx = 34367,
      .desc_idx = 2388,
      .symbol_name_idx = 33774,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3265] = {
      .name_idx = 34393,
      .desc_idx = 2388,
      .symbol_name_idx = 33800,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3266] = {
      .name_idx = 34419,
      .desc_idx = 2388,
      .symbol_name_idx = 33826,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [3588] = {
      .name_idx = 25798,
      .desc_idx = 10739,
      .symbol_name_idx = 25065,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [3589] = {
      .name_idx = 25827,
      .desc_idx = 10739,
      .symbol_name_idx = 25094,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [3590] = {
      .name_idx = 25856,
      .desc_idx = 10739,
      .symbol_name_idx = 25123,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [3591] = {
      .name_idx = 25002,
      .desc_idx = 296,
      .symbol_name_idx = 24269,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [3592] = {
      .name_idx = 25033,
      .desc_idx = 296,
      .symbol_name_idx = 24300,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [3593] = {
      .name_idx = 25064,
      .desc_idx = 296,
      .symbol_name_idx = 24331,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [3594] = {
      .name_idx = 25095,
      .desc_idx = 296,
      .symbol_name_idx = 24362,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [3595] = {
      .name_idx = 25525,
      .desc_idx = 368,
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      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [3596] = {
      .name_idx = 25557,
      .desc_idx = 368,
      .symbol_name_idx = 24824,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [3597] = {
      .name_idx = 25589,
      .desc_idx = 368,
      .symbol_name_idx = 24856,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [3598] = {
      .name_idx = 25621,
      .desc_idx = 368,
      .symbol_name_idx = 24888,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_GBPS,
   },
   [3599] = {
      .name_idx = 23409,
      .desc_idx = 10577,
      .symbol_name_idx = 22676,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3600] = {
      .name_idx = 23448,
      .desc_idx = 10577,
      .symbol_name_idx = 22715,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3601] = {
      .name_idx = 23487,
      .desc_idx = 10577,
      .symbol_name_idx = 22754,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3602] = {
      .name_idx = 23526,
      .desc_idx = 10577,
      .symbol_name_idx = 22793,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3603] = {
      .name_idx = 24106,
      .desc_idx = 10658,
      .symbol_name_idx = 23373,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3604] = {
      .name_idx = 24145,
      .desc_idx = 10658,
      .symbol_name_idx = 23412,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3605] = {
      .name_idx = 24184,
      .desc_idx = 10658,
      .symbol_name_idx = 23451,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3606] = {
      .name_idx = 24223,
      .desc_idx = 10658,
      .symbol_name_idx = 23490,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3607] = {
      .name_idx = 23758,
      .desc_idx = 10900,
      .symbol_name_idx = 23025,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3608] = {
      .name_idx = 23798,
      .desc_idx = 10900,
      .symbol_name_idx = 23065,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3609] = {
      .name_idx = 23838,
      .desc_idx = 10900,
      .symbol_name_idx = 23105,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3610] = {
      .name_idx = 23878,
      .desc_idx = 10900,
      .symbol_name_idx = 23145,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3611] = {
      .name_idx = 24455,
      .desc_idx = 10982,
      .symbol_name_idx = 23722,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3612] = {
      .name_idx = 24495,
      .desc_idx = 10982,
      .symbol_name_idx = 23762,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3613] = {
      .name_idx = 24535,
      .desc_idx = 10982,
      .symbol_name_idx = 23802,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3614] = {
      .name_idx = 24575,
      .desc_idx = 10982,
      .symbol_name_idx = 23842,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3615] = {
      .name_idx = 24733,
      .desc_idx = 29378,
      .symbol_name_idx = 24000,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3616] = {
      .name_idx = 24758,
      .desc_idx = 29378,
      .symbol_name_idx = 24025,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3617] = {
      .name_idx = 24783,
      .desc_idx = 29378,
      .symbol_name_idx = 24050,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3618] = {
      .name_idx = 24808,
      .desc_idx = 29378,
      .symbol_name_idx = 24075,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3619] = {
      .name_idx = 26687,
      .desc_idx = 25453,
      .symbol_name_idx = 25954,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3620] = {
      .name_idx = 26724,
      .desc_idx = 25453,
      .symbol_name_idx = 25991,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3621] = {
      .name_idx = 26761,
      .desc_idx = 25453,
      .symbol_name_idx = 26028,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3622] = {
      .name_idx = 26798,
      .desc_idx = 25453,
      .symbol_name_idx = 26065,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3623] = {
      .name_idx = 44842,
      .desc_idx = 2484,
      .symbol_name_idx = 43944,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3624] = {
      .name_idx = 44858,
      .desc_idx = 2484,
      .symbol_name_idx = 43960,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3625] = {
      .name_idx = 44874,
      .desc_idx = 2484,
      .symbol_name_idx = 43976,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3626] = {
      .name_idx = 44890,
      .desc_idx = 2484,
      .symbol_name_idx = 43992,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3627] = {
      .name_idx = 44921,
      .desc_idx = 2484,
      .symbol_name_idx = 44023,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3628] = {
      .name_idx = 44937,
      .desc_idx = 2484,
      .symbol_name_idx = 44039,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3629] = {
      .name_idx = 44953,
      .desc_idx = 2484,
      .symbol_name_idx = 44055,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3630] = {
      .name_idx = 44969,
      .desc_idx = 2484,
      .symbol_name_idx = 44071,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3631] = {
      .name_idx = 44985,
      .desc_idx = 2484,
      .symbol_name_idx = 44087,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3632] = {
      .name_idx = 45001,
      .desc_idx = 2484,
      .symbol_name_idx = 44103,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3633] = {
      .name_idx = 45017,
      .desc_idx = 2484,
      .symbol_name_idx = 44119,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3634] = {
      .name_idx = 45033,
      .desc_idx = 2484,
      .symbol_name_idx = 44135,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3635] = {
      .name_idx = 45049,
      .desc_idx = 2484,
      .symbol_name_idx = 44151,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3636] = {
      .name_idx = 45065,
      .desc_idx = 2484,
      .symbol_name_idx = 44167,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3637] = {
      .name_idx = 45096,
      .desc_idx = 2484,
      .symbol_name_idx = 44198,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3638] = {
      .name_idx = 45112,
      .desc_idx = 2484,
      .symbol_name_idx = 44214,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3639] = {
      .name_idx = 42807,
      .desc_idx = 24644,
      .symbol_name_idx = 44542,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3640] = {
      .name_idx = 42840,
      .desc_idx = 24644,
      .symbol_name_idx = 44570,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3641] = {
      .name_idx = 42873,
      .desc_idx = 24644,
      .symbol_name_idx = 44598,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3642] = {
      .name_idx = 42906,
      .desc_idx = 24644,
      .symbol_name_idx = 44626,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3643] = {
      .name_idx = 42971,
      .desc_idx = 24644,
      .symbol_name_idx = 44681,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3644] = {
      .name_idx = 43004,
      .desc_idx = 24644,
      .symbol_name_idx = 44709,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3645] = {
      .name_idx = 43037,
      .desc_idx = 24644,
      .symbol_name_idx = 44737,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3646] = {
      .name_idx = 43070,
      .desc_idx = 24644,
      .symbol_name_idx = 44765,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3647] = {
      .name_idx = 43103,
      .desc_idx = 24644,
      .symbol_name_idx = 44793,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3648] = {
      .name_idx = 43136,
      .desc_idx = 24644,
      .symbol_name_idx = 44821,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3649] = {
      .name_idx = 43169,
      .desc_idx = 24644,
      .symbol_name_idx = 44849,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3650] = {
      .name_idx = 43202,
      .desc_idx = 24644,
      .symbol_name_idx = 44877,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3651] = {
      .name_idx = 43235,
      .desc_idx = 24644,
      .symbol_name_idx = 44905,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3717] = {
      .name_idx = 48427,
      .desc_idx = 3558,
      .symbol_name_idx = 48530,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3718] = {
      .name_idx = 48445,
      .desc_idx = 3558,
      .symbol_name_idx = 48548,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3719] = {
      .name_idx = 48463,
      .desc_idx = 3558,
      .symbol_name_idx = 48566,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3720] = {
      .name_idx = 48481,
      .desc_idx = 3558,
      .symbol_name_idx = 48584,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3721] = {
      .name_idx = 48516,
      .desc_idx = 3558,
      .symbol_name_idx = 48619,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3722] = {
      .name_idx = 48534,
      .desc_idx = 3558,
      .symbol_name_idx = 48637,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3723] = {
      .name_idx = 48552,
      .desc_idx = 3558,
      .symbol_name_idx = 48655,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3724] = {
      .name_idx = 48570,
      .desc_idx = 3558,
      .symbol_name_idx = 48673,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3725] = {
      .name_idx = 48588,
      .desc_idx = 3558,
      .symbol_name_idx = 48691,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3726] = {
      .name_idx = 48606,
      .desc_idx = 3558,
      .symbol_name_idx = 48709,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3727] = {
      .name_idx = 48624,
      .desc_idx = 3558,
      .symbol_name_idx = 48727,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3728] = {
      .name_idx = 48642,
      .desc_idx = 3558,
      .symbol_name_idx = 48745,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3729] = {
      .name_idx = 48660,
      .desc_idx = 3558,
      .symbol_name_idx = 48763,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3730] = {
      .name_idx = 48678,
      .desc_idx = 3558,
      .symbol_name_idx = 48781,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3731] = {
      .name_idx = 48713,
      .desc_idx = 3558,
      .symbol_name_idx = 48816,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3732] = {
      .name_idx = 48731,
      .desc_idx = 3558,
      .symbol_name_idx = 48834,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3733] = {
      .name_idx = 45594,
      .desc_idx = 2547,
      .symbol_name_idx = 45340,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3734] = {
      .name_idx = 45611,
      .desc_idx = 2547,
      .symbol_name_idx = 45357,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3735] = {
      .name_idx = 45628,
      .desc_idx = 2547,
      .symbol_name_idx = 45374,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3736] = {
      .name_idx = 45645,
      .desc_idx = 2547,
      .symbol_name_idx = 45391,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3737] = {
      .name_idx = 45678,
      .desc_idx = 2547,
      .symbol_name_idx = 45424,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3738] = {
      .name_idx = 45695,
      .desc_idx = 2547,
      .symbol_name_idx = 45441,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3739] = {
      .name_idx = 45712,
      .desc_idx = 2547,
      .symbol_name_idx = 45458,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3740] = {
      .name_idx = 45729,
      .desc_idx = 2547,
      .symbol_name_idx = 45475,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3741] = {
      .name_idx = 45746,
      .desc_idx = 2547,
      .symbol_name_idx = 45492,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3742] = {
      .name_idx = 45763,
      .desc_idx = 2547,
      .symbol_name_idx = 45509,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3743] = {
      .name_idx = 45780,
      .desc_idx = 2547,
      .symbol_name_idx = 45526,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3744] = {
      .name_idx = 45797,
      .desc_idx = 2547,
      .symbol_name_idx = 45543,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3745] = {
      .name_idx = 45814,
      .desc_idx = 2547,
      .symbol_name_idx = 45560,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3746] = {
      .name_idx = 45831,
      .desc_idx = 2547,
      .symbol_name_idx = 45577,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3747] = {
      .name_idx = 45864,
      .desc_idx = 2547,
      .symbol_name_idx = 45610,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3748] = {
      .name_idx = 45881,
      .desc_idx = 2547,
      .symbol_name_idx = 45627,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3749] = {
      .name_idx = 13485,
      .desc_idx = 2990,
      .symbol_name_idx = 13296,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3750] = {
      .name_idx = 13511,
      .desc_idx = 2990,
      .symbol_name_idx = 13322,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3751] = {
      .name_idx = 13537,
      .desc_idx = 2990,
      .symbol_name_idx = 13348,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3752] = {
      .name_idx = 13563,
      .desc_idx = 2990,
      .symbol_name_idx = 13374,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3753] = {
      .name_idx = 13614,
      .desc_idx = 2990,
      .symbol_name_idx = 13425,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3754] = {
      .name_idx = 13640,
      .desc_idx = 2990,
      .symbol_name_idx = 13451,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3755] = {
      .name_idx = 13666,
      .desc_idx = 2990,
      .symbol_name_idx = 13477,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3756] = {
      .name_idx = 13692,
      .desc_idx = 2990,
      .symbol_name_idx = 13503,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3757] = {
      .name_idx = 13718,
      .desc_idx = 2990,
      .symbol_name_idx = 13529,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3758] = {
      .name_idx = 13744,
      .desc_idx = 2990,
      .symbol_name_idx = 13555,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3759] = {
      .name_idx = 13770,
      .desc_idx = 2990,
      .symbol_name_idx = 13581,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3760] = {
      .name_idx = 13796,
      .desc_idx = 2990,
      .symbol_name_idx = 13607,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3761] = {
      .name_idx = 13822,
      .desc_idx = 2990,
      .symbol_name_idx = 13633,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3762] = {
      .name_idx = 13848,
      .desc_idx = 2990,
      .symbol_name_idx = 13659,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3763] = {
      .name_idx = 13899,
      .desc_idx = 2990,
      .symbol_name_idx = 13710,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3764] = {
      .name_idx = 13925,
      .desc_idx = 2990,
      .symbol_name_idx = 13736,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3765] = {
      .name_idx = 14315,
      .desc_idx = 3600,
      .symbol_name_idx = 14126,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3766] = {
      .name_idx = 14342,
      .desc_idx = 3600,
      .symbol_name_idx = 14153,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3767] = {
      .name_idx = 14369,
      .desc_idx = 3600,
      .symbol_name_idx = 14180,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3768] = {
      .name_idx = 14396,
      .desc_idx = 3600,
      .symbol_name_idx = 14207,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3769] = {
      .name_idx = 14449,
      .desc_idx = 3600,
      .symbol_name_idx = 14260,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3770] = {
      .name_idx = 14476,
      .desc_idx = 3600,
      .symbol_name_idx = 14287,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3771] = {
      .name_idx = 14503,
      .desc_idx = 3600,
      .symbol_name_idx = 14314,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3772] = {
      .name_idx = 14530,
      .desc_idx = 3600,
      .symbol_name_idx = 14341,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3773] = {
      .name_idx = 14557,
      .desc_idx = 3600,
      .symbol_name_idx = 14368,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3774] = {
      .name_idx = 14584,
      .desc_idx = 3600,
      .symbol_name_idx = 14395,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3775] = {
      .name_idx = 14611,
      .desc_idx = 3600,
      .symbol_name_idx = 14422,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3776] = {
      .name_idx = 14638,
      .desc_idx = 3600,
      .symbol_name_idx = 14449,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3777] = {
      .name_idx = 14665,
      .desc_idx = 3600,
      .symbol_name_idx = 14476,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3778] = {
      .name_idx = 14692,
      .desc_idx = 3600,
      .symbol_name_idx = 14503,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3779] = {
      .name_idx = 14745,
      .desc_idx = 3600,
      .symbol_name_idx = 14556,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3780] = {
      .name_idx = 14772,
      .desc_idx = 3600,
      .symbol_name_idx = 14583,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3781] = {
      .name_idx = 36029,
      .desc_idx = 2915,
      .symbol_name_idx = 35436,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 36053,
      .desc_idx = 2915,
      .symbol_name_idx = 35460,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 36077,
      .desc_idx = 2915,
      .symbol_name_idx = 35484,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 36101,
      .desc_idx = 2915,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2915,
      .symbol_name_idx = 35555,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2915,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2915,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 36220,
      .desc_idx = 2915,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 36244,
      .desc_idx = 2915,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 36268,
      .desc_idx = 2915,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2915,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 36316,
      .desc_idx = 2915,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2915,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2915,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2915,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 2915,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3797] = {
      .name_idx = 41159,
      .desc_idx = 5507,
      .symbol_name_idx = 42641,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3798] = {
      .name_idx = 41185,
      .desc_idx = 5507,
      .symbol_name_idx = 42667,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 41211,
      .desc_idx = 5507,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3800] = {
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      .desc_idx = 5507,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3801] = {
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      .desc_idx = 5507,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3802] = {
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      .desc_idx = 5507,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3803] = {
      .name_idx = 41340,
      .desc_idx = 5507,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3804] = {
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      .desc_idx = 5507,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3805] = {
      .name_idx = 41392,
      .desc_idx = 5507,
      .symbol_name_idx = 42874,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3806] = {
      .name_idx = 41418,
      .desc_idx = 5507,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3807] = {
      .name_idx = 41444,
      .desc_idx = 5507,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5507,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3809] = {
      .name_idx = 41496,
      .desc_idx = 5507,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3810] = {
      .name_idx = 41522,
      .desc_idx = 5507,
      .symbol_name_idx = 43004,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3811] = {
      .name_idx = 41573,
      .desc_idx = 5507,
      .symbol_name_idx = 43055,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3812] = {
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      .desc_idx = 5507,
      .symbol_name_idx = 43081,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3813] = {
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      .desc_idx = 3404,
      .symbol_name_idx = 99405,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3814] = {
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      .desc_idx = 3404,
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      .category_idx = 1088,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3815] = {
      .name_idx = 104440,
      .desc_idx = 3404,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3816] = {
      .name_idx = 104465,
      .desc_idx = 3404,
      .symbol_name_idx = 99480,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3817] = {
      .name_idx = 104514,
      .desc_idx = 3404,
      .symbol_name_idx = 99529,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3818] = {
      .name_idx = 104539,
      .desc_idx = 3404,
      .symbol_name_idx = 99554,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3819] = {
      .name_idx = 104564,
      .desc_idx = 3404,
      .symbol_name_idx = 99579,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3820] = {
      .name_idx = 104589,
      .desc_idx = 3404,
      .symbol_name_idx = 99604,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3821] = {
      .name_idx = 104614,
      .desc_idx = 3404,
      .symbol_name_idx = 99629,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3822] = {
      .name_idx = 104639,
      .desc_idx = 3404,
      .symbol_name_idx = 99654,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3823] = {
      .name_idx = 104664,
      .desc_idx = 3404,
      .symbol_name_idx = 99679,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3824] = {
      .name_idx = 104689,
      .desc_idx = 3404,
      .symbol_name_idx = 99704,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 104714,
      .desc_idx = 3404,
      .symbol_name_idx = 99729,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3826] = {
      .name_idx = 104739,
      .desc_idx = 3404,
      .symbol_name_idx = 99754,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3827] = {
      .name_idx = 104788,
      .desc_idx = 3404,
      .symbol_name_idx = 99803,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3404,
      .symbol_name_idx = 99828,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3829] = {
      .name_idx = 6651,
      .desc_idx = 3308,
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      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3830] = {
      .name_idx = 6673,
      .desc_idx = 3308,
      .symbol_name_idx = 6484,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3831] = {
      .name_idx = 6695,
      .desc_idx = 3308,
      .symbol_name_idx = 6506,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3832] = {
      .name_idx = 6717,
      .desc_idx = 3308,
      .symbol_name_idx = 6528,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3833] = {
      .name_idx = 6760,
      .desc_idx = 3308,
      .symbol_name_idx = 6571,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3834] = {
      .name_idx = 6782,
      .desc_idx = 3308,
      .symbol_name_idx = 6593,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3835] = {
      .name_idx = 6804,
      .desc_idx = 3308,
      .symbol_name_idx = 6615,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3836] = {
      .name_idx = 6826,
      .desc_idx = 3308,
      .symbol_name_idx = 6637,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3837] = {
      .name_idx = 6848,
      .desc_idx = 3308,
      .symbol_name_idx = 6659,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3838] = {
      .name_idx = 6870,
      .desc_idx = 3308,
      .symbol_name_idx = 6681,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3839] = {
      .name_idx = 6892,
      .desc_idx = 3308,
      .symbol_name_idx = 6703,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3840] = {
      .name_idx = 6914,
      .desc_idx = 3308,
      .symbol_name_idx = 6725,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3841] = {
      .name_idx = 6936,
      .desc_idx = 3308,
      .symbol_name_idx = 6747,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3842] = {
      .name_idx = 6958,
      .desc_idx = 3308,
      .symbol_name_idx = 6769,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3843] = {
      .name_idx = 7001,
      .desc_idx = 3308,
      .symbol_name_idx = 6812,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3844] = {
      .name_idx = 7023,
      .desc_idx = 3308,
      .symbol_name_idx = 6834,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3845] = {
      .name_idx = 12687,
      .desc_idx = 2804,
      .symbol_name_idx = 12498,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3846] = {
      .name_idx = 12712,
      .desc_idx = 2804,
      .symbol_name_idx = 12523,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3847] = {
      .name_idx = 12737,
      .desc_idx = 2804,
      .symbol_name_idx = 12548,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3848] = {
      .name_idx = 12762,
      .desc_idx = 2804,
      .symbol_name_idx = 12573,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3849] = {
      .name_idx = 12811,
      .desc_idx = 2804,
      .symbol_name_idx = 12622,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3850] = {
      .name_idx = 12836,
      .desc_idx = 2804,
      .symbol_name_idx = 12647,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3851] = {
      .name_idx = 12861,
      .desc_idx = 2804,
      .symbol_name_idx = 12672,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3852] = {
      .name_idx = 12886,
      .desc_idx = 2804,
      .symbol_name_idx = 12697,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3853] = {
      .name_idx = 12911,
      .desc_idx = 2804,
      .symbol_name_idx = 12722,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3854] = {
      .name_idx = 12936,
      .desc_idx = 2804,
      .symbol_name_idx = 12747,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3855] = {
      .name_idx = 12961,
      .desc_idx = 2804,
      .symbol_name_idx = 12772,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3856] = {
      .name_idx = 12986,
      .desc_idx = 2804,
      .symbol_name_idx = 12797,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3857] = {
      .name_idx = 13011,
      .desc_idx = 2804,
      .symbol_name_idx = 12822,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3858] = {
      .name_idx = 13036,
      .desc_idx = 2804,
      .symbol_name_idx = 12847,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3859] = {
      .name_idx = 13085,
      .desc_idx = 2804,
      .symbol_name_idx = 12896,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3860] = {
      .name_idx = 13110,
      .desc_idx = 2804,
      .symbol_name_idx = 12921,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3861] = {
      .name_idx = 35295,
      .desc_idx = 5316,
      .symbol_name_idx = 34702,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3862] = {
      .name_idx = 35318,
      .desc_idx = 5316,
      .symbol_name_idx = 34725,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3863] = {
      .name_idx = 35341,
      .desc_idx = 5316,
      .symbol_name_idx = 34748,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3864] = {
      .name_idx = 35364,
      .desc_idx = 5316,
      .symbol_name_idx = 34771,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3865] = {
      .name_idx = 35409,
      .desc_idx = 5316,
      .symbol_name_idx = 34816,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3866] = {
      .name_idx = 35432,
      .desc_idx = 5316,
      .symbol_name_idx = 34839,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3867] = {
      .name_idx = 35455,
      .desc_idx = 5316,
      .symbol_name_idx = 34862,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3868] = {
      .name_idx = 35478,
      .desc_idx = 5316,
      .symbol_name_idx = 34885,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3869] = {
      .name_idx = 35501,
      .desc_idx = 5316,
      .symbol_name_idx = 34908,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3870] = {
      .name_idx = 35524,
      .desc_idx = 5316,
      .symbol_name_idx = 34931,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3871] = {
      .name_idx = 35547,
      .desc_idx = 5316,
      .symbol_name_idx = 34954,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3872] = {
      .name_idx = 35570,
      .desc_idx = 5316,
      .symbol_name_idx = 34977,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3873] = {
      .name_idx = 35593,
      .desc_idx = 5316,
      .symbol_name_idx = 35000,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3874] = {
      .name_idx = 35616,
      .desc_idx = 5316,
      .symbol_name_idx = 35023,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3875] = {
      .name_idx = 35661,
      .desc_idx = 5316,
      .symbol_name_idx = 35068,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3876] = {
      .name_idx = 35684,
      .desc_idx = 5316,
      .symbol_name_idx = 35091,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3877] = {
      .name_idx = 103608,
      .desc_idx = 2707,
      .symbol_name_idx = 98623,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3878] = {
      .name_idx = 103632,
      .desc_idx = 2707,
      .symbol_name_idx = 98647,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3879] = {
      .name_idx = 103656,
      .desc_idx = 2707,
      .symbol_name_idx = 98671,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3880] = {
      .name_idx = 103680,
      .desc_idx = 2707,
      .symbol_name_idx = 98695,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3881] = {
      .name_idx = 103727,
      .desc_idx = 2707,
      .symbol_name_idx = 98742,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3882] = {
      .name_idx = 103751,
      .desc_idx = 2707,
      .symbol_name_idx = 98766,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3883] = {
      .name_idx = 103775,
      .desc_idx = 2707,
      .symbol_name_idx = 98790,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3884] = {
      .name_idx = 103799,
      .desc_idx = 2707,
      .symbol_name_idx = 98814,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3885] = {
      .name_idx = 103823,
      .desc_idx = 2707,
      .symbol_name_idx = 98838,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3886] = {
      .name_idx = 103847,
      .desc_idx = 2707,
      .symbol_name_idx = 98862,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3887] = {
      .name_idx = 103871,
      .desc_idx = 2707,
      .symbol_name_idx = 98886,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3888] = {
      .name_idx = 103895,
      .desc_idx = 2707,
      .symbol_name_idx = 98910,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3889] = {
      .name_idx = 103919,
      .desc_idx = 2707,
      .symbol_name_idx = 98934,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3890] = {
      .name_idx = 103943,
      .desc_idx = 2707,
      .symbol_name_idx = 98958,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3891] = {
      .name_idx = 103990,
      .desc_idx = 2707,
      .symbol_name_idx = 99005,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3892] = {
      .name_idx = 104014,
      .desc_idx = 2707,
      .symbol_name_idx = 99029,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3893] = {
      .name_idx = 194468,
      .desc_idx = 3216,
      .symbol_name_idx = 171972,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3894] = {
      .name_idx = 194486,
      .desc_idx = 3216,
      .symbol_name_idx = 171990,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3895] = {
      .name_idx = 194504,
      .desc_idx = 3216,
      .symbol_name_idx = 172008,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3896] = {
      .name_idx = 194522,
      .desc_idx = 3216,
      .symbol_name_idx = 172026,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3897] = {
      .name_idx = 194557,
      .desc_idx = 3216,
      .symbol_name_idx = 172061,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3898] = {
      .name_idx = 194575,
      .desc_idx = 3216,
      .symbol_name_idx = 172079,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3899] = {
      .name_idx = 194593,
      .desc_idx = 3216,
      .symbol_name_idx = 172097,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3900] = {
      .name_idx = 194611,
      .desc_idx = 3216,
      .symbol_name_idx = 172115,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3901] = {
      .name_idx = 194629,
      .desc_idx = 3216,
      .symbol_name_idx = 172133,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3902] = {
      .name_idx = 194647,
      .desc_idx = 3216,
      .symbol_name_idx = 172151,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3903] = {
      .name_idx = 194665,
      .desc_idx = 3216,
      .symbol_name_idx = 172169,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3904] = {
      .name_idx = 194683,
      .desc_idx = 3216,
      .symbol_name_idx = 172187,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3905] = {
      .name_idx = 194701,
      .desc_idx = 3216,
      .symbol_name_idx = 172205,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3906] = {
      .name_idx = 194719,
      .desc_idx = 3216,
      .symbol_name_idx = 172223,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3907] = {
      .name_idx = 194754,
      .desc_idx = 3216,
      .symbol_name_idx = 172258,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3908] = {
      .name_idx = 194772,
      .desc_idx = 3216,
      .symbol_name_idx = 172276,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [3909] = {
      .name_idx = 47654,
      .desc_idx = 27698,
      .symbol_name_idx = 47820,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [3910] = {
      .name_idx = 47678,
      .desc_idx = 27698,
      .symbol_name_idx = 47844,
      .category_idx = 1088,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4119] = {
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      .desc_idx = 19419,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19419,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [4159] = {
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      .category_idx = 1002,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16511,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4161] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4162] = {
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4163] = {
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4164] = {
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4165] = {
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      .desc_idx = 29951,
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      .category_idx = 1002,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4166] = {
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      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4167] = {
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .category_idx = 1135,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .category_idx = 1135,
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   },
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   },
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      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19072,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 25262,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16674,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19072,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19329,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 3978,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16674,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 23064,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19072,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4547] = {
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      .desc_idx = 25262,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19329,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3978,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16674,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 23064,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4554] = {
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      .desc_idx = 19072,
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   },
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   },
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   },
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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   },
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   },
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      .desc_idx = 3978,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 23064,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19072,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 25262,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 18016,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19329,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3978,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16674,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 23064,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4594] = {
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      .desc_idx = 19072,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 91185,
      .desc_idx = 25262,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18016,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19329,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3978,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16674,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 23064,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19072,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 25262,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18016,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19329,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3978,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16674,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 96654,
      .desc_idx = 23064,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19072,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4611] = {
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      .desc_idx = 25262,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4613] = {
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      .desc_idx = 18016,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19329,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3978,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 95720,
      .desc_idx = 16674,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4617] = {
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      .desc_idx = 23064,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19072,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 91312,
      .desc_idx = 25262,
      .symbol_name_idx = 85997,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4620] = {
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      .desc_idx = 17177,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 99807,
      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4632] = {
      .name_idx = 99885,
      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4633] = {
      .name_idx = 99924,
      .desc_idx = 4035,
      .symbol_name_idx = 94609,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4634] = {
      .name_idx = 99963,
      .desc_idx = 4035,
      .symbol_name_idx = 94648,
      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4635] = {
      .name_idx = 100040,
      .desc_idx = 4035,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4636] = {
      .name_idx = 100079,
      .desc_idx = 4035,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4637] = {
      .name_idx = 77024,
      .desc_idx = 5387,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4638] = {
      .name_idx = 77064,
      .desc_idx = 5387,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4639] = {
      .name_idx = 77104,
      .desc_idx = 5387,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 77223,
      .desc_idx = 5387,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 77263,
      .desc_idx = 5387,
      .symbol_name_idx = 71948,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4644] = {
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      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 5387,
      .symbol_name_idx = 72268,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4651] = {
      .name_idx = 77662,
      .desc_idx = 5387,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4652] = {
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      .desc_idx = 5387,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4653] = {
      .name_idx = 79156,
      .desc_idx = 7325,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4654] = {
      .name_idx = 79197,
      .desc_idx = 7325,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4655] = {
      .name_idx = 79238,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4656] = {
      .name_idx = 79279,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4657] = {
      .name_idx = 79360,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4658] = {
      .name_idx = 79401,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4659] = {
      .name_idx = 79442,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4660] = {
      .name_idx = 79483,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4661] = {
      .name_idx = 79524,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4662] = {
      .name_idx = 79565,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4663] = {
      .name_idx = 79606,
      .desc_idx = 7325,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 79647,
      .desc_idx = 7325,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4665] = {
      .name_idx = 79688,
      .desc_idx = 7325,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 79729,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4667] = {
      .name_idx = 79810,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4668] = {
      .name_idx = 79851,
      .desc_idx = 7325,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4669] = {
      .name_idx = 80482,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4670] = {
      .name_idx = 80526,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4671] = {
      .name_idx = 80570,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4672] = {
      .name_idx = 80614,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4673] = {
      .name_idx = 80701,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 80745,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4675] = {
      .name_idx = 80789,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4676] = {
      .name_idx = 80833,
      .desc_idx = 7466,
      .symbol_name_idx = 75518,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4677] = {
      .name_idx = 80877,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4678] = {
      .name_idx = 80921,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4679] = {
      .name_idx = 80965,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4680] = {
      .name_idx = 81009,
      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4681] = {
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      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4682] = {
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      .desc_idx = 7466,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16205,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16608,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16608,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16608,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16608,
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      .category_idx = 1124,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16608,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16608,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16608,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16608,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17695,
      .symbol_name_idx = 19687,
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      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17695,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16910,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17695,
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      .category_idx = 374,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16910,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17695,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17695,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16910,
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      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17695,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 16910,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 17695,
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   },
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      .desc_idx = 16754,
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4812] = {
      .name_idx = 68118,
      .desc_idx = 24934,
      .symbol_name_idx = 67991,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4813] = {
      .name_idx = 67720,
      .desc_idx = 23898,
      .symbol_name_idx = 66480,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4814] = {
      .name_idx = 67759,
      .desc_idx = 23898,
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      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4815] = {
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      .desc_idx = 23898,
      .symbol_name_idx = 66006,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4816] = {
      .name_idx = 67286,
      .desc_idx = 23898,
      .symbol_name_idx = 66046,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4817] = {
      .name_idx = 67326,
      .desc_idx = 23898,
      .symbol_name_idx = 66086,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4818] = {
      .name_idx = 67366,
      .desc_idx = 23898,
      .symbol_name_idx = 66126,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4819] = {
      .name_idx = 67406,
      .desc_idx = 23898,
      .symbol_name_idx = 66166,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4820] = {
      .name_idx = 67446,
      .desc_idx = 23898,
      .symbol_name_idx = 66206,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4821] = {
      .name_idx = 66740,
      .desc_idx = 23828,
      .symbol_name_idx = 65500,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4822] = {
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      .desc_idx = 23828,
      .symbol_name_idx = 65542,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4823] = {
      .name_idx = 66230,
      .desc_idx = 23828,
      .symbol_name_idx = 64990,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4824] = {
      .name_idx = 66273,
      .desc_idx = 23828,
      .symbol_name_idx = 65033,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4825] = {
      .name_idx = 66316,
      .desc_idx = 23828,
      .symbol_name_idx = 65076,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4826] = {
      .name_idx = 66359,
      .desc_idx = 23828,
      .symbol_name_idx = 65119,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4827] = {
      .name_idx = 66402,
      .desc_idx = 23828,
      .symbol_name_idx = 65162,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4828] = {
      .name_idx = 66445,
      .desc_idx = 23828,
      .symbol_name_idx = 65205,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4829] = {
      .name_idx = 1248,
      .desc_idx = 23467,
      .symbol_name_idx = 1248,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4830] = {
      .name_idx = 1472,
      .desc_idx = 23380,
      .symbol_name_idx = 1472,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4831] = {
      .name_idx = 344,
      .desc_idx = 14616,
      .symbol_name_idx = 344,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4832] = {
      .name_idx = 524,
      .desc_idx = 6679,
      .symbol_name_idx = 524,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4833] = {
      .name_idx = 75452,
      .desc_idx = 4230,
      .symbol_name_idx = 70299,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4834] = {
      .name_idx = 75802,
      .desc_idx = 4272,
      .symbol_name_idx = 71071,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4835] = {
      .name_idx = 76014,
      .desc_idx = 4315,
      .symbol_name_idx = 71283,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4836] = {
      .name_idx = 76274,
      .desc_idx = 39309,
      .symbol_name_idx = 70547,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4837] = {
      .name_idx = 76566,
      .desc_idx = 39380,
      .symbol_name_idx = 70831,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4838] = {
      .name_idx = 1276,
      .desc_idx = 23467,
      .symbol_name_idx = 1276,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4839] = {
      .name_idx = 1500,
      .desc_idx = 23380,
      .symbol_name_idx = 1500,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4840] = {
      .name_idx = 366,
      .desc_idx = 14616,
      .symbol_name_idx = 366,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4841] = {
      .name_idx = 547,
      .desc_idx = 6679,
      .symbol_name_idx = 547,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4842] = {
      .name_idx = 75477,
      .desc_idx = 4230,
      .symbol_name_idx = 70324,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4843] = {
      .name_idx = 75828,
      .desc_idx = 4272,
      .symbol_name_idx = 71097,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4844] = {
      .name_idx = 76041,
      .desc_idx = 4315,
      .symbol_name_idx = 71310,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4845] = {
      .name_idx = 76312,
      .desc_idx = 39309,
      .symbol_name_idx = 70584,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4846] = {
      .name_idx = 76601,
      .desc_idx = 39380,
      .symbol_name_idx = 70865,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4847] = {
      .name_idx = 1304,
      .desc_idx = 23467,
      .symbol_name_idx = 1304,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4848] = {
      .name_idx = 1528,
      .desc_idx = 23380,
      .symbol_name_idx = 1528,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4849] = {
      .name_idx = 388,
      .desc_idx = 14616,
      .symbol_name_idx = 388,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4850] = {
      .name_idx = 570,
      .desc_idx = 6679,
      .symbol_name_idx = 570,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4851] = {
      .name_idx = 75502,
      .desc_idx = 4230,
      .symbol_name_idx = 70349,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4852] = {
      .name_idx = 75854,
      .desc_idx = 4272,
      .symbol_name_idx = 71123,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4853] = {
      .name_idx = 76068,
      .desc_idx = 4315,
      .symbol_name_idx = 71337,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4854] = {
      .name_idx = 76350,
      .desc_idx = 39309,
      .symbol_name_idx = 70621,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4855] = {
      .name_idx = 76636,
      .desc_idx = 39380,
      .symbol_name_idx = 70899,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4856] = {
      .name_idx = 1332,
      .desc_idx = 23467,
      .symbol_name_idx = 1332,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4857] = {
      .name_idx = 1556,
      .desc_idx = 23380,
      .symbol_name_idx = 1556,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4858] = {
      .name_idx = 410,
      .desc_idx = 14616,
      .symbol_name_idx = 410,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4859] = {
      .name_idx = 593,
      .desc_idx = 6679,
      .symbol_name_idx = 593,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4860] = {
      .name_idx = 75527,
      .desc_idx = 4230,
      .symbol_name_idx = 70374,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4861] = {
      .name_idx = 75880,
      .desc_idx = 4272,
      .symbol_name_idx = 71149,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4862] = {
      .name_idx = 76095,
      .desc_idx = 4315,
      .symbol_name_idx = 71364,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4863] = {
      .name_idx = 76388,
      .desc_idx = 39309,
      .symbol_name_idx = 70658,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4864] = {
      .name_idx = 76671,
      .desc_idx = 39380,
      .symbol_name_idx = 70933,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [4865] = {
      .name_idx = 128,
      .desc_idx = 4881,
      .symbol_name_idx = 128,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4866] = {
      .name_idx = 160,
      .desc_idx = 4881,
      .symbol_name_idx = 160,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4867] = {
      .name_idx = 192,
      .desc_idx = 4881,
      .symbol_name_idx = 192,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4868] = {
      .name_idx = 224,
      .desc_idx = 4881,
      .symbol_name_idx = 224,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4869] = {
      .name_idx = 880,
      .desc_idx = 1486,
      .symbol_name_idx = 880,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4870] = {
      .name_idx = 902,
      .desc_idx = 1486,
      .symbol_name_idx = 902,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4871] = {
      .name_idx = 924,
      .desc_idx = 1486,
      .symbol_name_idx = 924,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4872] = {
      .name_idx = 946,
      .desc_idx = 1486,
      .symbol_name_idx = 946,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4873] = {
      .name_idx = 704,
      .desc_idx = 1442,
      .symbol_name_idx = 704,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4874] = {
      .name_idx = 726,
      .desc_idx = 1442,
      .symbol_name_idx = 726,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4875] = {
      .name_idx = 748,
      .desc_idx = 1442,
      .symbol_name_idx = 748,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [4876] = {
      .name_idx = 770,
      .desc_idx = 1442,
      .symbol_name_idx = 770,
      .category_idx = 350,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 1571,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 1629,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5135] = {
      .name_idx = 22741,
      .desc_idx = 2009,
      .symbol_name_idx = 22033,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5136] = {
      .name_idx = 3726,
      .desc_idx = 1629,
      .symbol_name_idx = 2439,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5137] = {
      .name_idx = 22774,
      .desc_idx = 2009,
      .symbol_name_idx = 22066,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5138] = {
      .name_idx = 3803,
      .desc_idx = 1629,
      .symbol_name_idx = 2516,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5139] = {
      .name_idx = 22807,
      .desc_idx = 2009,
      .symbol_name_idx = 22099,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5140] = {
      .name_idx = 3842,
      .desc_idx = 1629,
      .symbol_name_idx = 2555,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5141] = {
      .name_idx = 22840,
      .desc_idx = 2009,
      .symbol_name_idx = 22132,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5142] = {
      .name_idx = 22873,
      .desc_idx = 2009,
      .symbol_name_idx = 22165,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5143] = {
      .name_idx = 22938,
      .desc_idx = 2009,
      .symbol_name_idx = 22230,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5144] = {
      .name_idx = 22971,
      .desc_idx = 2009,
      .symbol_name_idx = 22263,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5145] = {
      .name_idx = 137885,
      .desc_idx = 26210,
      .symbol_name_idx = 118966,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5146] = {
      .name_idx = 137930,
      .desc_idx = 26210,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5147] = {
      .name_idx = 137975,
      .desc_idx = 26210,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5148] = {
      .name_idx = 138020,
      .desc_idx = 26210,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5149] = {
      .name_idx = 125141,
      .desc_idx = 5023,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5150] = {
      .name_idx = 138109,
      .desc_idx = 26210,
      .symbol_name_idx = 119190,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5151] = {
      .name_idx = 125173,
      .desc_idx = 5023,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5152] = {
      .name_idx = 138154,
      .desc_idx = 26210,
      .symbol_name_idx = 119235,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5153] = {
      .name_idx = 125205,
      .desc_idx = 5023,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5154] = {
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      .desc_idx = 26210,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5155] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5156] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5157] = {
      .name_idx = 126155,
      .desc_idx = 5081,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5158] = {
      .name_idx = 125300,
      .desc_idx = 5023,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5159] = {
      .name_idx = 138289,
      .desc_idx = 26210,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5160] = {
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      .desc_idx = 5081,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5161] = {
      .name_idx = 125332,
      .desc_idx = 5023,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5162] = {
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      .desc_idx = 26210,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5163] = {
      .name_idx = 126219,
      .desc_idx = 5081,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5164] = {
      .name_idx = 125364,
      .desc_idx = 5023,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5165] = {
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      .desc_idx = 26210,
      .symbol_name_idx = 119460,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5166] = {
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5167] = {
      .name_idx = 125396,
      .desc_idx = 5023,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5168] = {
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      .desc_idx = 26210,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5169] = {
      .name_idx = 126314,
      .desc_idx = 5081,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5170] = {
      .name_idx = 125428,
      .desc_idx = 5023,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5171] = {
      .name_idx = 138469,
      .desc_idx = 26210,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5172] = {
      .name_idx = 126346,
      .desc_idx = 5081,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5173] = {
      .name_idx = 125460,
      .desc_idx = 5023,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5174] = {
      .name_idx = 138514,
      .desc_idx = 26210,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5175] = {
      .name_idx = 126378,
      .desc_idx = 5081,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5176] = {
      .name_idx = 125492,
      .desc_idx = 5023,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5177] = {
      .name_idx = 138603,
      .desc_idx = 26210,
      .symbol_name_idx = 119684,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5178] = {
      .name_idx = 126410,
      .desc_idx = 5081,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5179] = {
      .name_idx = 125524,
      .desc_idx = 5023,
      .symbol_name_idx = 114059,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5180] = {
      .name_idx = 138648,
      .desc_idx = 26210,
      .symbol_name_idx = 119729,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5181] = {
      .name_idx = 126442,
      .desc_idx = 5081,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5182] = {
      .name_idx = 125556,
      .desc_idx = 5023,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5183] = {
      .name_idx = 126474,
      .desc_idx = 5081,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5184] = {
      .name_idx = 125588,
      .desc_idx = 5023,
      .symbol_name_idx = 114123,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5185] = {
      .name_idx = 126506,
      .desc_idx = 5081,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5186] = {
      .name_idx = 125651,
      .desc_idx = 5023,
      .symbol_name_idx = 114186,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5187] = {
      .name_idx = 126538,
      .desc_idx = 5081,
      .symbol_name_idx = 113045,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5188] = {
      .name_idx = 125683,
      .desc_idx = 5023,
      .symbol_name_idx = 114218,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5189] = {
      .name_idx = 126570,
      .desc_idx = 5081,
      .symbol_name_idx = 113077,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5190] = {
      .name_idx = 126602,
      .desc_idx = 5081,
      .symbol_name_idx = 113109,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5191] = {
      .name_idx = 126665,
      .desc_idx = 5081,
      .symbol_name_idx = 113172,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5192] = {
      .name_idx = 126697,
      .desc_idx = 5081,
      .symbol_name_idx = 113204,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5193] = {
      .name_idx = 134177,
      .desc_idx = 26032,
      .symbol_name_idx = 115258,
      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5194] = {
      .name_idx = 134230,
      .desc_idx = 26032,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5195] = {
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      .desc_idx = 26032,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5196] = {
      .name_idx = 134336,
      .desc_idx = 26032,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5197] = {
      .name_idx = 134441,
      .desc_idx = 26032,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5198] = {
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      .desc_idx = 26032,
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      .category_idx = 1192,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .category_idx = 1222,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5328] = {
      .name_idx = 178540,
      .desc_idx = 29240,
      .symbol_name_idx = 155908,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5329] = {
      .name_idx = 178579,
      .desc_idx = 29240,
      .symbol_name_idx = 155947,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5330] = {
      .name_idx = 178618,
      .desc_idx = 29240,
      .symbol_name_idx = 155986,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5331] = {
      .name_idx = 178657,
      .desc_idx = 29240,
      .symbol_name_idx = 156025,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5332] = {
      .name_idx = 178696,
      .desc_idx = 29240,
      .symbol_name_idx = 156064,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5333] = {
      .name_idx = 178735,
      .desc_idx = 29240,
      .symbol_name_idx = 156103,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5334] = {
      .name_idx = 178774,
      .desc_idx = 29240,
      .symbol_name_idx = 156142,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5335] = {
      .name_idx = 178851,
      .desc_idx = 29240,
      .symbol_name_idx = 156219,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5336] = {
      .name_idx = 178890,
      .desc_idx = 29240,
      .symbol_name_idx = 156258,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5337] = {
      .name_idx = 65404,
      .desc_idx = 17629,
      .symbol_name_idx = 64168,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5338] = {
      .name_idx = 65453,
      .desc_idx = 17629,
      .symbol_name_idx = 64217,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5339] = {
      .name_idx = 65502,
      .desc_idx = 17629,
      .symbol_name_idx = 64266,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5340] = {
      .name_idx = 65551,
      .desc_idx = 17629,
      .symbol_name_idx = 64315,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5341] = {
      .name_idx = 65792,
      .desc_idx = 16840,
      .symbol_name_idx = 64556,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5342] = {
      .name_idx = 65840,
      .desc_idx = 16840,
      .symbol_name_idx = 64604,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5343] = {
      .name_idx = 65888,
      .desc_idx = 16840,
      .symbol_name_idx = 64652,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5344] = {
      .name_idx = 65936,
      .desc_idx = 16840,
      .symbol_name_idx = 64700,
      .category_idx = 355,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5345] = {
      .name_idx = 83844,
      .desc_idx = 14812,
      .symbol_name_idx = 78529,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5346] = {
      .name_idx = 84986,
      .desc_idx = 16126,
      .symbol_name_idx = 79671,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5347] = {
      .name_idx = 100640,
      .desc_idx = 1748,
      .symbol_name_idx = 95325,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5348] = {
      .name_idx = 83880,
      .desc_idx = 14812,
      .symbol_name_idx = 78565,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5349] = {
      .name_idx = 85022,
      .desc_idx = 16126,
      .symbol_name_idx = 79707,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5350] = {
      .name_idx = 100677,
      .desc_idx = 1748,
      .symbol_name_idx = 95362,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5351] = {
      .name_idx = 83916,
      .desc_idx = 14812,
      .symbol_name_idx = 78601,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5352] = {
      .name_idx = 85058,
      .desc_idx = 16126,
      .symbol_name_idx = 79743,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5353] = {
      .name_idx = 100714,
      .desc_idx = 1748,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5354] = {
      .name_idx = 83952,
      .desc_idx = 14812,
      .symbol_name_idx = 78637,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5355] = {
      .name_idx = 85094,
      .desc_idx = 16126,
      .symbol_name_idx = 79779,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5356] = {
      .name_idx = 100751,
      .desc_idx = 1748,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5357] = {
      .name_idx = 84023,
      .desc_idx = 14812,
      .symbol_name_idx = 78708,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5358] = {
      .name_idx = 85165,
      .desc_idx = 16126,
      .symbol_name_idx = 79850,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5359] = {
      .name_idx = 100824,
      .desc_idx = 1748,
      .symbol_name_idx = 95509,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5360] = {
      .name_idx = 84059,
      .desc_idx = 14812,
      .symbol_name_idx = 78744,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5361] = {
      .name_idx = 85201,
      .desc_idx = 16126,
      .symbol_name_idx = 79886,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5362] = {
      .name_idx = 100861,
      .desc_idx = 1748,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5363] = {
      .name_idx = 84095,
      .desc_idx = 14812,
      .symbol_name_idx = 78780,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5364] = {
      .name_idx = 85237,
      .desc_idx = 16126,
      .symbol_name_idx = 79922,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5365] = {
      .name_idx = 100898,
      .desc_idx = 1748,
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      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5366] = {
      .name_idx = 84131,
      .desc_idx = 14812,
      .symbol_name_idx = 78816,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5367] = {
      .name_idx = 85273,
      .desc_idx = 16126,
      .symbol_name_idx = 79958,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5368] = {
      .name_idx = 100935,
      .desc_idx = 1748,
      .symbol_name_idx = 95620,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5369] = {
      .name_idx = 84167,
      .desc_idx = 14812,
      .symbol_name_idx = 78852,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5370] = {
      .name_idx = 85309,
      .desc_idx = 16126,
      .symbol_name_idx = 79994,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5371] = {
      .name_idx = 100972,
      .desc_idx = 1748,
      .symbol_name_idx = 95657,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5372] = {
      .name_idx = 84203,
      .desc_idx = 14812,
      .symbol_name_idx = 78888,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5373] = {
      .name_idx = 85345,
      .desc_idx = 16126,
      .symbol_name_idx = 80030,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5374] = {
      .name_idx = 101009,
      .desc_idx = 1748,
      .symbol_name_idx = 95694,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5375] = {
      .name_idx = 84239,
      .desc_idx = 14812,
      .symbol_name_idx = 78924,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5376] = {
      .name_idx = 85381,
      .desc_idx = 16126,
      .symbol_name_idx = 80066,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5377] = {
      .name_idx = 101046,
      .desc_idx = 1748,
      .symbol_name_idx = 95731,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5378] = {
      .name_idx = 84275,
      .desc_idx = 14812,
      .symbol_name_idx = 78960,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5379] = {
      .name_idx = 85417,
      .desc_idx = 16126,
      .symbol_name_idx = 80102,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5380] = {
      .name_idx = 101083,
      .desc_idx = 1748,
      .symbol_name_idx = 95768,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5381] = {
      .name_idx = 84311,
      .desc_idx = 14812,
      .symbol_name_idx = 78996,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5382] = {
      .name_idx = 85453,
      .desc_idx = 16126,
      .symbol_name_idx = 80138,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5383] = {
      .name_idx = 101120,
      .desc_idx = 1748,
      .symbol_name_idx = 95805,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5384] = {
      .name_idx = 84347,
      .desc_idx = 14812,
      .symbol_name_idx = 79032,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5385] = {
      .name_idx = 85489,
      .desc_idx = 16126,
      .symbol_name_idx = 80174,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5386] = {
      .name_idx = 101157,
      .desc_idx = 1748,
      .symbol_name_idx = 95842,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5387] = {
      .name_idx = 84418,
      .desc_idx = 14812,
      .symbol_name_idx = 79103,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5388] = {
      .name_idx = 85560,
      .desc_idx = 16126,
      .symbol_name_idx = 80245,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5389] = {
      .name_idx = 101230,
      .desc_idx = 1748,
      .symbol_name_idx = 95915,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5390] = {
      .name_idx = 84454,
      .desc_idx = 14812,
      .symbol_name_idx = 79139,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5391] = {
      .name_idx = 85596,
      .desc_idx = 16126,
      .symbol_name_idx = 80281,
      .category_idx = 1124,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5456] = {
      .name_idx = 110837,
      .desc_idx = 4529,
      .symbol_name_idx = 105643,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5457] = {
      .name_idx = 26201,
      .desc_idx = 2266,
      .symbol_name_idx = 25468,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5458] = {
      .name_idx = 26228,
      .desc_idx = 2266,
      .symbol_name_idx = 25495,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5459] = {
      .name_idx = 26255,
      .desc_idx = 2266,
      .symbol_name_idx = 25522,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5460] = {
      .name_idx = 26282,
      .desc_idx = 2266,
      .symbol_name_idx = 25549,
      .category_idx = 1106,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5461] = {
      .name_idx = 57604,
      .desc_idx = 3772,
      .symbol_name_idx = 57613,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5462] = {
      .name_idx = 57658,
      .desc_idx = 3772,
      .symbol_name_idx = 57667,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5463] = {
      .name_idx = 57712,
      .desc_idx = 3772,
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      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5464] = {
      .name_idx = 57766,
      .desc_idx = 3772,
      .symbol_name_idx = 57775,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5465] = {
      .name_idx = 57873,
      .desc_idx = 3772,
      .symbol_name_idx = 57882,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5466] = {
      .name_idx = 57927,
      .desc_idx = 3772,
      .symbol_name_idx = 57936,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5467] = {
      .name_idx = 57981,
      .desc_idx = 3772,
      .symbol_name_idx = 57990,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5468] = {
      .name_idx = 58035,
      .desc_idx = 3772,
      .symbol_name_idx = 58044,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5469] = {
      .name_idx = 58089,
      .desc_idx = 3772,
      .symbol_name_idx = 58098,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5470] = {
      .name_idx = 58143,
      .desc_idx = 3772,
      .symbol_name_idx = 58152,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5471] = {
      .name_idx = 58197,
      .desc_idx = 3772,
      .symbol_name_idx = 58206,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5472] = {
      .name_idx = 58251,
      .desc_idx = 3772,
      .symbol_name_idx = 58260,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5473] = {
      .name_idx = 58305,
      .desc_idx = 3772,
      .symbol_name_idx = 58314,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5474] = {
      .name_idx = 58359,
      .desc_idx = 3772,
      .symbol_name_idx = 58368,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5475] = {
      .name_idx = 58466,
      .desc_idx = 3772,
      .symbol_name_idx = 58475,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5476] = {
      .name_idx = 58520,
      .desc_idx = 3772,
      .symbol_name_idx = 58529,
      .category_idx = 1002,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5477] = {
      .name_idx = 32031,
      .desc_idx = 2388,
      .symbol_name_idx = 31438,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5478] = {
      .name_idx = 32057,
      .desc_idx = 2388,
      .symbol_name_idx = 31464,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5479] = {
      .name_idx = 32083,
      .desc_idx = 2388,
      .symbol_name_idx = 31490,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5480] = {
      .name_idx = 32109,
      .desc_idx = 2388,
      .symbol_name_idx = 31516,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5481] = {
      .name_idx = 32160,
      .desc_idx = 2388,
      .symbol_name_idx = 31567,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5482] = {
      .name_idx = 32186,
      .desc_idx = 2388,
      .symbol_name_idx = 31593,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5483] = {
      .name_idx = 32212,
      .desc_idx = 2388,
      .symbol_name_idx = 31619,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5484] = {
      .name_idx = 32238,
      .desc_idx = 2388,
      .symbol_name_idx = 31645,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5485] = {
      .name_idx = 36811,
      .desc_idx = 2435,
      .symbol_name_idx = 36218,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5486] = {
      .name_idx = 36838,
      .desc_idx = 2435,
      .symbol_name_idx = 36245,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5487] = {
      .name_idx = 36865,
      .desc_idx = 2435,
      .symbol_name_idx = 36272,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5488] = {
      .name_idx = 36892,
      .desc_idx = 2435,
      .symbol_name_idx = 36299,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5489] = {
      .name_idx = 36945,
      .desc_idx = 2435,
      .symbol_name_idx = 36352,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5490] = {
      .name_idx = 36972,
      .desc_idx = 2435,
      .symbol_name_idx = 36379,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5491] = {
      .name_idx = 36999,
      .desc_idx = 2435,
      .symbol_name_idx = 36406,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5492] = {
      .name_idx = 37026,
      .desc_idx = 2435,
      .symbol_name_idx = 36433,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5493] = {
      .name_idx = 32264,
      .desc_idx = 2388,
      .symbol_name_idx = 31671,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5494] = {
      .name_idx = 32290,
      .desc_idx = 2388,
      .symbol_name_idx = 31697,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5495] = {
      .name_idx = 32316,
      .desc_idx = 2388,
      .symbol_name_idx = 31723,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5496] = {
      .name_idx = 32342,
      .desc_idx = 2388,
      .symbol_name_idx = 31749,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5497] = {
      .name_idx = 32368,
      .desc_idx = 2388,
      .symbol_name_idx = 31775,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5498] = {
      .name_idx = 32394,
      .desc_idx = 2388,
      .symbol_name_idx = 31801,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5499] = {
      .name_idx = 32445,
      .desc_idx = 2388,
      .symbol_name_idx = 31852,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5500] = {
      .name_idx = 32471,
      .desc_idx = 2388,
      .symbol_name_idx = 31878,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5501] = {
      .name_idx = 37053,
      .desc_idx = 2435,
      .symbol_name_idx = 36460,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5502] = {
      .name_idx = 37080,
      .desc_idx = 2435,
      .symbol_name_idx = 36487,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5503] = {
      .name_idx = 37107,
      .desc_idx = 2435,
      .symbol_name_idx = 36514,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5504] = {
      .name_idx = 37134,
      .desc_idx = 2435,
      .symbol_name_idx = 36541,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5505] = {
      .name_idx = 37161,
      .desc_idx = 2435,
      .symbol_name_idx = 36568,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5506] = {
      .name_idx = 37188,
      .desc_idx = 2435,
      .symbol_name_idx = 36595,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5507] = {
      .name_idx = 37241,
      .desc_idx = 2435,
      .symbol_name_idx = 36648,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5508] = {
      .name_idx = 37268,
      .desc_idx = 2435,
      .symbol_name_idx = 36675,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5509] = {
      .name_idx = 32853,
      .desc_idx = 2388,
      .symbol_name_idx = 32260,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5510] = {
      .name_idx = 32879,
      .desc_idx = 2388,
      .symbol_name_idx = 32286,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5511] = {
      .name_idx = 32905,
      .desc_idx = 2388,
      .symbol_name_idx = 32312,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5512] = {
      .name_idx = 32931,
      .desc_idx = 2388,
      .symbol_name_idx = 32338,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5513] = {
      .name_idx = 32982,
      .desc_idx = 2388,
      .symbol_name_idx = 32389,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5514] = {
      .name_idx = 33008,
      .desc_idx = 2388,
      .symbol_name_idx = 32415,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5515] = {
      .name_idx = 33034,
      .desc_idx = 2388,
      .symbol_name_idx = 32441,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5516] = {
      .name_idx = 33060,
      .desc_idx = 2388,
      .symbol_name_idx = 32467,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5517] = {
      .name_idx = 37665,
      .desc_idx = 2435,
      .symbol_name_idx = 37072,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5518] = {
      .name_idx = 37692,
      .desc_idx = 2435,
      .symbol_name_idx = 37099,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5519] = {
      .name_idx = 37719,
      .desc_idx = 2435,
      .symbol_name_idx = 37126,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5520] = {
      .name_idx = 37746,
      .desc_idx = 2435,
      .symbol_name_idx = 37153,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5521] = {
      .name_idx = 37799,
      .desc_idx = 2435,
      .symbol_name_idx = 37206,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5522] = {
      .name_idx = 37826,
      .desc_idx = 2435,
      .symbol_name_idx = 37233,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5523] = {
      .name_idx = 37853,
      .desc_idx = 2435,
      .symbol_name_idx = 37260,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5524] = {
      .name_idx = 37880,
      .desc_idx = 2435,
      .symbol_name_idx = 37287,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5525] = {
      .name_idx = 33086,
      .desc_idx = 2388,
      .symbol_name_idx = 32493,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5526] = {
      .name_idx = 33112,
      .desc_idx = 2388,
      .symbol_name_idx = 32519,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5527] = {
      .name_idx = 33138,
      .desc_idx = 2388,
      .symbol_name_idx = 32545,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5528] = {
      .name_idx = 33164,
      .desc_idx = 2388,
      .symbol_name_idx = 32571,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5529] = {
      .name_idx = 33190,
      .desc_idx = 2388,
      .symbol_name_idx = 32597,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5530] = {
      .name_idx = 33216,
      .desc_idx = 2388,
      .symbol_name_idx = 32623,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5531] = {
      .name_idx = 33267,
      .desc_idx = 2388,
      .symbol_name_idx = 32674,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5532] = {
      .name_idx = 33293,
      .desc_idx = 2388,
      .symbol_name_idx = 32700,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5533] = {
      .name_idx = 37907,
      .desc_idx = 2435,
      .symbol_name_idx = 37314,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5534] = {
      .name_idx = 37934,
      .desc_idx = 2435,
      .symbol_name_idx = 37341,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5535] = {
      .name_idx = 37961,
      .desc_idx = 2435,
      .symbol_name_idx = 37368,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5536] = {
      .name_idx = 37988,
      .desc_idx = 2435,
      .symbol_name_idx = 37395,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5537] = {
      .name_idx = 38015,
      .desc_idx = 2435,
      .symbol_name_idx = 37422,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5538] = {
      .name_idx = 38042,
      .desc_idx = 2435,
      .symbol_name_idx = 37449,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5539] = {
      .name_idx = 38095,
      .desc_idx = 2435,
      .symbol_name_idx = 37502,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5540] = {
      .name_idx = 38122,
      .desc_idx = 2435,
      .symbol_name_idx = 37529,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5541] = {
      .name_idx = 33675,
      .desc_idx = 2388,
      .symbol_name_idx = 33082,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5542] = {
      .name_idx = 33701,
      .desc_idx = 2388,
      .symbol_name_idx = 33108,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5543] = {
      .name_idx = 33727,
      .desc_idx = 2388,
      .symbol_name_idx = 33134,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5544] = {
      .name_idx = 33753,
      .desc_idx = 2388,
      .symbol_name_idx = 33160,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5545] = {
      .name_idx = 33804,
      .desc_idx = 2388,
      .symbol_name_idx = 33211,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5546] = {
      .name_idx = 33830,
      .desc_idx = 2388,
      .symbol_name_idx = 33237,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5547] = {
      .name_idx = 33856,
      .desc_idx = 2388,
      .symbol_name_idx = 33263,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5548] = {
      .name_idx = 33882,
      .desc_idx = 2388,
      .symbol_name_idx = 33289,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5549] = {
      .name_idx = 38519,
      .desc_idx = 2435,
      .symbol_name_idx = 37926,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5550] = {
      .name_idx = 38546,
      .desc_idx = 2435,
      .symbol_name_idx = 37953,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5551] = {
      .name_idx = 38573,
      .desc_idx = 2435,
      .symbol_name_idx = 37980,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5552] = {
      .name_idx = 38600,
      .desc_idx = 2435,
      .symbol_name_idx = 38007,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5553] = {
      .name_idx = 38653,
      .desc_idx = 2435,
      .symbol_name_idx = 38060,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5554] = {
      .name_idx = 38680,
      .desc_idx = 2435,
      .symbol_name_idx = 38087,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5555] = {
      .name_idx = 38707,
      .desc_idx = 2435,
      .symbol_name_idx = 38114,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5556] = {
      .name_idx = 38734,
      .desc_idx = 2435,
      .symbol_name_idx = 38141,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5557] = {
      .name_idx = 33908,
      .desc_idx = 2388,
      .symbol_name_idx = 33315,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5558] = {
      .name_idx = 33934,
      .desc_idx = 2388,
      .symbol_name_idx = 33341,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5559] = {
      .name_idx = 33960,
      .desc_idx = 2388,
      .symbol_name_idx = 33367,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5560] = {
      .name_idx = 33986,
      .desc_idx = 2388,
      .symbol_name_idx = 33393,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5561] = {
      .name_idx = 34012,
      .desc_idx = 2388,
      .symbol_name_idx = 33419,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5562] = {
      .name_idx = 34038,
      .desc_idx = 2388,
      .symbol_name_idx = 33445,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5563] = {
      .name_idx = 34089,
      .desc_idx = 2388,
      .symbol_name_idx = 33496,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5564] = {
      .name_idx = 34115,
      .desc_idx = 2388,
      .symbol_name_idx = 33522,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5565] = {
      .name_idx = 38761,
      .desc_idx = 2435,
      .symbol_name_idx = 38168,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5566] = {
      .name_idx = 38788,
      .desc_idx = 2435,
      .symbol_name_idx = 38195,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5567] = {
      .name_idx = 38815,
      .desc_idx = 2435,
      .symbol_name_idx = 38222,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5568] = {
      .name_idx = 38842,
      .desc_idx = 2435,
      .symbol_name_idx = 38249,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5569] = {
      .name_idx = 38869,
      .desc_idx = 2435,
      .symbol_name_idx = 38276,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5570] = {
      .name_idx = 38896,
      .desc_idx = 2435,
      .symbol_name_idx = 38303,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5571] = {
      .name_idx = 38949,
      .desc_idx = 2435,
      .symbol_name_idx = 38356,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5572] = {
      .name_idx = 38976,
      .desc_idx = 2435,
      .symbol_name_idx = 38383,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5573] = {
      .name_idx = 34497,
      .desc_idx = 2388,
      .symbol_name_idx = 33904,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5574] = {
      .name_idx = 34523,
      .desc_idx = 2388,
      .symbol_name_idx = 33930,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5575] = {
      .name_idx = 34549,
      .desc_idx = 2388,
      .symbol_name_idx = 33956,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5576] = {
      .name_idx = 34575,
      .desc_idx = 2388,
      .symbol_name_idx = 33982,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5577] = {
      .name_idx = 34626,
      .desc_idx = 2388,
      .symbol_name_idx = 34033,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5578] = {
      .name_idx = 34652,
      .desc_idx = 2388,
      .symbol_name_idx = 34059,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5579] = {
      .name_idx = 34678,
      .desc_idx = 2388,
      .symbol_name_idx = 34085,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5580] = {
      .name_idx = 34704,
      .desc_idx = 2388,
      .symbol_name_idx = 34111,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5581] = {
      .name_idx = 39373,
      .desc_idx = 2435,
      .symbol_name_idx = 38780,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5582] = {
      .name_idx = 39400,
      .desc_idx = 2435,
      .symbol_name_idx = 38807,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5583] = {
      .name_idx = 39427,
      .desc_idx = 2435,
      .symbol_name_idx = 38834,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5584] = {
      .name_idx = 39454,
      .desc_idx = 2435,
      .symbol_name_idx = 38861,
      .category_idx = 1222,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5585] = {
      .name_idx = 39507,
      .desc_idx = 2435,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5648] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 29951,
      .symbol_name_idx = 54624,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5844] = {
      .name_idx = 58892,
      .desc_idx = 30035,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5845] = {
      .name_idx = 58930,
      .desc_idx = 30035,
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      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5846] = {
      .name_idx = 59358,
      .desc_idx = 30035,
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5847] = {
      .name_idx = 59786,
      .desc_idx = 30035,
      .symbol_name_idx = 59795,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5848] = {
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      .desc_idx = 3671,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5849] = {
      .name_idx = 48977,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5850] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5851] = {
      .name_idx = 49701,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5852] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 6937,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5854] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 6937,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 3840,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5857] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5858] = {
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      .desc_idx = 3840,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 7244,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5865] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19419,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [5907] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .desc_idx = 29868,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 6724,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 19185,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 19185,
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      .category_idx = 676,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 5558,
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16427,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16427,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 16427,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 25618,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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   },
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      .desc_idx = 25752,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .desc_idx = 25548,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .desc_idx = 25548,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5967] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5968] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5969] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5970] = {
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [5971] = {
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      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 7395,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 4359,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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   },
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      .desc_idx = 4359,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 4359,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 2266,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 14812,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 14812,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6207] = {
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      .desc_idx = 14812,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 84383,
      .desc_idx = 14812,
      .symbol_name_idx = 79068,
      .category_idx = 676,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18993,
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      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17396,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18993,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .name_idx = 92741,
      .desc_idx = 17396,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .desc_idx = 18993,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [6214] = {
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      .desc_idx = 17396,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 18993,
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      .category_idx = 676,
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 17396,
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      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
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      .desc_idx = 1689,
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      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6218] = {
      .name_idx = 78002,
      .desc_idx = 1689,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [6219] = {
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      .desc_idx = 1689,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
   [6220] = {
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      .desc_idx = 1689,
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      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6221] = {
      .name_idx = 65208,
      .desc_idx = 17629,
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      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6222] = {
      .name_idx = 65600,
      .desc_idx = 16840,
      .symbol_name_idx = 64364,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6223] = {
      .name_idx = 111037,
      .desc_idx = 4396,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6224] = {
      .name_idx = 111069,
      .desc_idx = 4396,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6225] = {
      .name_idx = 111431,
      .desc_idx = 4396,
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      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6226] = {
      .name_idx = 111793,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6227] = {
      .name_idx = 45460,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6228] = {
      .name_idx = 45476,
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      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6229] = {
      .name_idx = 45662,
      .desc_idx = 2547,
      .symbol_name_idx = 45408,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6230] = {
      .name_idx = 45848,
      .desc_idx = 2547,
      .symbol_name_idx = 45594,
      .category_idx = 986,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6231] = {
      .name_idx = 968,
      .desc_idx = 1529,
      .symbol_name_idx = 968,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6232] = {
      .name_idx = 156905,
      .desc_idx = 14472,
      .symbol_name_idx = 134331,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6233] = {
      .name_idx = 156946,
      .desc_idx = 14472,
      .symbol_name_idx = 134372,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6234] = {
      .name_idx = 157407,
      .desc_idx = 14472,
      .symbol_name_idx = 134833,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6235] = {
      .name_idx = 157868,
      .desc_idx = 14472,
      .symbol_name_idx = 135294,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6236] = {
      .name_idx = 25885,
      .desc_idx = 2149,
      .symbol_name_idx = 25152,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6237] = {
      .name_idx = 25911,
      .desc_idx = 2149,
      .symbol_name_idx = 25178,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6238] = {
      .name_idx = 31825,
      .desc_idx = 2388,
      .symbol_name_idx = 31232,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6239] = {
      .name_idx = 36597,
      .desc_idx = 2435,
      .symbol_name_idx = 36004,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6240] = {
      .name_idx = 31850,
      .desc_idx = 2388,
      .symbol_name_idx = 31257,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6241] = {
      .name_idx = 36623,
      .desc_idx = 2435,
      .symbol_name_idx = 36030,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6242] = {
      .name_idx = 32135,
      .desc_idx = 2388,
      .symbol_name_idx = 31542,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6243] = {
      .name_idx = 36919,
      .desc_idx = 2435,
      .symbol_name_idx = 36326,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6244] = {
      .name_idx = 32420,
      .desc_idx = 2388,
      .symbol_name_idx = 31827,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6245] = {
      .name_idx = 37215,
      .desc_idx = 2435,
      .symbol_name_idx = 36622,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6246] = {
      .name_idx = 32647,
      .desc_idx = 2388,
      .symbol_name_idx = 32054,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6247] = {
      .name_idx = 37451,
      .desc_idx = 2435,
      .symbol_name_idx = 36858,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6248] = {
      .name_idx = 32672,
      .desc_idx = 2388,
      .symbol_name_idx = 32079,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6249] = {
      .name_idx = 37477,
      .desc_idx = 2435,
      .symbol_name_idx = 36884,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6250] = {
      .name_idx = 32957,
      .desc_idx = 2388,
      .symbol_name_idx = 32364,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6251] = {
      .name_idx = 37773,
      .desc_idx = 2435,
      .symbol_name_idx = 37180,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6252] = {
      .name_idx = 33242,
      .desc_idx = 2388,
      .symbol_name_idx = 32649,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6253] = {
      .name_idx = 38069,
      .desc_idx = 2435,
      .symbol_name_idx = 37476,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6254] = {
      .name_idx = 33469,
      .desc_idx = 2388,
      .symbol_name_idx = 32876,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6255] = {
      .name_idx = 38305,
      .desc_idx = 2435,
      .symbol_name_idx = 37712,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6256] = {
      .name_idx = 33494,
      .desc_idx = 2388,
      .symbol_name_idx = 32901,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6257] = {
      .name_idx = 38331,
      .desc_idx = 2435,
      .symbol_name_idx = 37738,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6258] = {
      .name_idx = 33779,
      .desc_idx = 2388,
      .symbol_name_idx = 33186,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6259] = {
      .name_idx = 38627,
      .desc_idx = 2435,
      .symbol_name_idx = 38034,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6260] = {
      .name_idx = 34064,
      .desc_idx = 2388,
      .symbol_name_idx = 33471,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6261] = {
      .name_idx = 38923,
      .desc_idx = 2435,
      .symbol_name_idx = 38330,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6262] = {
      .name_idx = 34291,
      .desc_idx = 2388,
      .symbol_name_idx = 33698,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6263] = {
      .name_idx = 39159,
      .desc_idx = 2435,
      .symbol_name_idx = 38566,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6264] = {
      .name_idx = 34316,
      .desc_idx = 2388,
      .symbol_name_idx = 33723,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6265] = {
      .name_idx = 39185,
      .desc_idx = 2435,
      .symbol_name_idx = 38592,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6266] = {
      .name_idx = 34601,
      .desc_idx = 2388,
      .symbol_name_idx = 34008,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6267] = {
      .name_idx = 39481,
      .desc_idx = 2435,
      .symbol_name_idx = 38888,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6268] = {
      .name_idx = 34886,
      .desc_idx = 2388,
      .symbol_name_idx = 34293,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6269] = {
      .name_idx = 39777,
      .desc_idx = 2435,
      .symbol_name_idx = 39184,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_EVENT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_EVENTS,
   },
   [6270] = {
      .name_idx = 112097,
      .desc_idx = 5904,
      .symbol_name_idx = 106903,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6271] = {
      .name_idx = 112125,
      .desc_idx = 5904,
      .symbol_name_idx = 106931,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6272] = {
      .name_idx = 112321,
      .desc_idx = 5904,
      .symbol_name_idx = 107127,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6273] = {
      .name_idx = 112349,
      .desc_idx = 5904,
      .symbol_name_idx = 107155,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6274] = {
      .name_idx = 112153,
      .desc_idx = 5904,
      .symbol_name_idx = 106959,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6275] = {
      .name_idx = 112181,
      .desc_idx = 5904,
      .symbol_name_idx = 106987,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6276] = {
      .name_idx = 112377,
      .desc_idx = 5904,
      .symbol_name_idx = 107183,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6277] = {
      .name_idx = 112405,
      .desc_idx = 5904,
      .symbol_name_idx = 107211,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6278] = {
      .name_idx = 50018,
      .desc_idx = 6034,
      .symbol_name_idx = 50027,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6279] = {
      .name_idx = 50346,
      .desc_idx = 6034,
      .symbol_name_idx = 50355,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6280] = {
      .name_idx = 51358,
      .desc_idx = 6570,
      .symbol_name_idx = 51367,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6281] = {
      .name_idx = 51694,
      .desc_idx = 6570,
      .symbol_name_idx = 51703,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6282] = {
      .name_idx = 50059,
      .desc_idx = 6034,
      .symbol_name_idx = 50068,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6283] = {
      .name_idx = 50387,
      .desc_idx = 6034,
      .symbol_name_idx = 50396,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6284] = {
      .name_idx = 51400,
      .desc_idx = 6570,
      .symbol_name_idx = 51409,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6285] = {
      .name_idx = 51736,
      .desc_idx = 6570,
      .symbol_name_idx = 51745,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6286] = {
      .name_idx = 50100,
      .desc_idx = 6034,
      .symbol_name_idx = 50109,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6287] = {
      .name_idx = 50428,
      .desc_idx = 6034,
      .symbol_name_idx = 50437,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6288] = {
      .name_idx = 51442,
      .desc_idx = 6570,
      .symbol_name_idx = 51451,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6289] = {
      .name_idx = 51778,
      .desc_idx = 6570,
      .symbol_name_idx = 51787,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6290] = {
      .name_idx = 50141,
      .desc_idx = 6034,
      .symbol_name_idx = 50150,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6291] = {
      .name_idx = 50469,
      .desc_idx = 6034,
      .symbol_name_idx = 50478,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [6292] = {
      .name_idx = 51484,
      .desc_idx = 6570,
      .symbol_name_idx = 51493,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
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   },
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   },
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   },
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   },
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   },
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   },
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   },
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      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7065] = {
      .name_idx = 51652,
      .desc_idx = 6570,
      .symbol_name_idx = 51661,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7066] = {
      .name_idx = 51988,
      .desc_idx = 6570,
      .symbol_name_idx = 51997,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7067] = {
      .name_idx = 113124,
      .desc_idx = 6440,
      .symbol_name_idx = 107930,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7068] = {
      .name_idx = 113356,
      .desc_idx = 6440,
      .symbol_name_idx = 108162,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7069] = {
      .name_idx = 113153,
      .desc_idx = 6440,
      .symbol_name_idx = 107959,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7070] = {
      .name_idx = 113385,
      .desc_idx = 6440,
      .symbol_name_idx = 108191,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7071] = {
      .name_idx = 113182,
      .desc_idx = 6440,
      .symbol_name_idx = 107988,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7072] = {
      .name_idx = 113414,
      .desc_idx = 6440,
      .symbol_name_idx = 108220,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7073] = {
      .name_idx = 113211,
      .desc_idx = 6440,
      .symbol_name_idx = 108017,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7074] = {
      .name_idx = 113443,
      .desc_idx = 6440,
      .symbol_name_idx = 108249,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_THROUGHPUT,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
      .units = INTEL_PERF_COUNTER_UNITS_BYTES,
   },
   [7075] = {
      .name_idx = 133555,
      .desc_idx = 29653,
      .symbol_name_idx = 114636,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [7076] = {
      .name_idx = 133605,
      .desc_idx = 29653,
      .symbol_name_idx = 114686,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [7077] = {
      .name_idx = 133655,
      .desc_idx = 29653,
      .symbol_name_idx = 114736,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [7078] = {
      .name_idx = 133705,
      .desc_idx = 29653,
      .symbol_name_idx = 114786,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [7079] = {
      .name_idx = 135641,
      .desc_idx = 29653,
      .symbol_name_idx = 116722,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [7080] = {
      .name_idx = 135691,
      .desc_idx = 29653,
      .symbol_name_idx = 116772,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [7081] = {
      .name_idx = 135741,
      .desc_idx = 29653,
      .symbol_name_idx = 116822,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
   [7082] = {
      .name_idx = 135791,
      .desc_idx = 29653,
      .symbol_name_idx = 116872,
      .category_idx = 676,
      .type = INTEL_PERF_COUNTER_TYPE_RAW,
      .data_type = INTEL_PERF_COUNTER_DATA_TYPE_FLOAT,
      .units = INTEL_PERF_COUNTER_UNITS_PERCENT,
   },
};

static void ATTRIBUTE_NOINLINE
intel_perf_query_add_counter_uint64(struct intel_perf_query_info *query,
                                    int counter_idx, size_t offset,
                                    intel_counter_read_uint64_t oa_counter_max,
                                    intel_counter_read_uint64_t oa_counter_read)
{
   struct intel_perf_query_counter *dest = &query->counters[query->n_counters++];
   const struct intel_perf_query_counter_data *counter = &counters[counter_idx];

   dest->name = &name[counter->name_idx];
   dest->desc = &desc[counter->desc_idx];
   dest->symbol_name = &symbol_name[counter->symbol_name_idx];
   dest->category = &category[counter->category_idx];

   dest->offset = offset;
   dest->type = counter->type;
   dest->data_type = counter->data_type;
   dest->units = counter->units;
   dest->oa_counter_max_uint64 = oa_counter_max;
   dest->oa_counter_read_uint64 = oa_counter_read;
}

static void ATTRIBUTE_NOINLINE
intel_perf_query_add_counter_float(struct intel_perf_query_info *query,
                                   int counter_idx, size_t offset,
                                   intel_counter_read_float_t oa_counter_max,
                                   intel_counter_read_float_t oa_counter_read)
{
   struct intel_perf_query_counter *dest = &query->counters[query->n_counters++];
   const struct intel_perf_query_counter_data *counter = &counters[counter_idx];

   dest->name = &name[counter->name_idx];
   dest->desc = &desc[counter->desc_idx];
   dest->symbol_name = &symbol_name[counter->symbol_name_idx];
   dest->category = &category[counter->category_idx];

   dest->offset = offset;
   dest->type = counter->type;
   dest->data_type = counter->data_type;
   dest->units = counter->units;
   dest->oa_counter_max_float = oa_counter_max;
   dest->oa_counter_read_float = oa_counter_read;
}

static float ATTRIBUTE_NOINLINE
percentage_max_float(struct intel_perf_config *perf,
                     const struct intel_perf_query_info *query,
                     const struct intel_perf_query_result *results)
{
   return 100;
}

static uint64_t ATTRIBUTE_NOINLINE
percentage_max_uint64(struct intel_perf_config *perf,
                      const struct intel_perf_query_info *query,
                      const struct intel_perf_query_result *results)
{
   return 100;
}


static void
hsw_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 70);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "a490e9d2-55b3-4db0-8dab-53011032c5f3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000253A4, .val = 0x01600000 },
         { .reg = 0x00025440, .val = 0x00100000 },
         { .reg = 0x00025128, .val = 0x00000000 },
         { .reg = 0x0002691C, .val = 0x00000800 },
         { .reg = 0x00026AA0, .val = 0x01500000 },
         { .reg = 0x00026B9C, .val = 0x00006000 },
         { .reg = 0x0002791C, .val = 0x00000800 },
         { .reg = 0x00027AA0, .val = 0x01500000 },
         { .reg = 0x00027B9C, .val = 0x00006000 },
         { .reg = 0x0002641C, .val = 0x00000400 },
         { .reg = 0x00025380, .val = 0x00000010 },
         { .reg = 0x0002538C, .val = 0x00000000 },
         { .reg = 0x00025384, .val = 0x0800AAAA },
         { .reg = 0x00025400, .val = 0x00000004 },
         { .reg = 0x0002540C, .val = 0x06029000 },
         { .reg = 0x00025410, .val = 0x00000002 },
         { .reg = 0x00025404, .val = 0x5C30FFFF },
         { .reg = 0x00025100, .val = 0x00000016 },
         { .reg = 0x00025110, .val = 0x00000400 },
         { .reg = 0x00025104, .val = 0x00000000 },
         { .reg = 0x00026804, .val = 0x00001211 },
         { .reg = 0x00026884, .val = 0x00000100 },
         { .reg = 0x00026900, .val = 0x00000002 },
         { .reg = 0x00026908, .val = 0x00700000 },
         { .reg = 0x00026904, .val = 0x00000000 },
         { .reg = 0x00026984, .val = 0x00001022 },
         { .reg = 0x00026A04, .val = 0x00000011 },
         { .reg = 0x00026A80, .val = 0x00000006 },
         { .reg = 0x00026A88, .val = 0x00000C02 },
         { .reg = 0x00026A84, .val = 0x00000000 },
         { .reg = 0x00026B04, .val = 0x00001000 },
         { .reg = 0x00026B80, .val = 0x00000002 },
         { .reg = 0x00026B8C, .val = 0x00000007 },
         { .reg = 0x00026B84, .val = 0x00000000 },
         { .reg = 0x00027804, .val = 0x00004844 },
         { .reg = 0x00027884, .val = 0x00000400 },
         { .reg = 0x00027900, .val = 0x00000002 },
         { .reg = 0x00027908, .val = 0x0E000000 },
         { .reg = 0x00027904, .val = 0x00000000 },
         { .reg = 0x00027984, .val = 0x00004088 },
         { .reg = 0x00027A04, .val = 0x00000044 },
         { .reg = 0x00027A80, .val = 0x00000006 },
         { .reg = 0x00027A88, .val = 0x00018040 },
         { .reg = 0x00027A84, .val = 0x00000000 },
         { .reg = 0x00027B04, .val = 0x00004000 },
         { .reg = 0x00027B80, .val = 0x00000002 },
         { .reg = 0x00027B8C, .val = 0x000000E0 },
         { .reg = 0x00027B84, .val = 0x00000000 },
         { .reg = 0x00026104, .val = 0x00002222 },
         { .reg = 0x00026184, .val = 0x0C006666 },
         { .reg = 0x00026284, .val = 0x04000000 },
         { .reg = 0x00026304, .val = 0x04000000 },
         { .reg = 0x00026400, .val = 0x00000002 },
         { .reg = 0x00026410, .val = 0x000000A0 },
         { .reg = 0x00026404, .val = 0x00000000 },
         { .reg = 0x00025420, .val = 0x04108020 },
         { .reg = 0x00025424, .val = 0x1284A420 },
         { .reg = 0x0002541C, .val = 0x00000000 },
         { .reg = 0x00025428, .val = 0x00042049 },
         { .reg = 0x000091BC, .val = 0xE0400000 },
         { .reg = 0x000091C4, .val = 0xE4500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,hsw__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,hsw__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, hsw__render_basic__avg_gpu_core_frequency__max,hsw__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,hsw__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 4, 32, NULL,hsw__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 5, 40, NULL,hsw__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,hsw__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,hsw__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,hsw__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,hsw__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,hsw__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,hsw__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 12, 84, percentage_max_float,hsw__render_basic__vs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 13, 88, percentage_max_uint64,hsw__render_basic__vs_eu_active_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 14, 96, NULL,hsw__render_basic__vs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 15, 104, percentage_max_float,hsw__render_basic__vs_eu_stall__read);

      intel_perf_query_add_counter_float(query, 16, 108, percentage_max_float,hsw__render_basic__hs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 17, 112, percentage_max_uint64,hsw__render_basic__hs_eu_active_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 18, 120, NULL,hsw__render_basic__hs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 19, 128, percentage_max_float,hsw__render_basic__hs_eu_stall__read);

      intel_perf_query_add_counter_float(query, 20, 132, percentage_max_float,hsw__render_basic__ds_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 21, 136, percentage_max_uint64,hsw__render_basic__ds_eu_active_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 22, 144, NULL,hsw__render_basic__ds_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 23, 152, percentage_max_float,hsw__render_basic__ds_eu_stall__read);

      intel_perf_query_add_counter_float(query, 24, 156, percentage_max_float,hsw__render_basic__gs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 25, 160, percentage_max_uint64,hsw__render_basic__gs_eu_active_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 26, 168, NULL,hsw__render_basic__gs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 27, 176, percentage_max_float,hsw__render_basic__gs_eu_stall__read);

      intel_perf_query_add_counter_float(query, 28, 180, percentage_max_float,hsw__render_basic__cs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 29, 184, percentage_max_uint64,hsw__render_basic__cs_eu_active_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 30, 192, NULL,hsw__render_basic__cs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 31, 200, percentage_max_float,hsw__render_basic__cs_eu_stall__read);

      intel_perf_query_add_counter_float(query, 32, 204, percentage_max_float,hsw__render_basic__ps_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 33, 208, percentage_max_uint64,hsw__render_basic__ps_eu_active_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 34, 216, NULL,hsw__render_basic__ps_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 35, 224, percentage_max_float,hsw__render_basic__ps_eu_stall__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 36, 228, percentage_max_float,hsw__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 37, 232, percentage_max_float,hsw__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 38, 236, percentage_max_float,hsw__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 39, 240, percentage_max_float,hsw__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 40, 244, percentage_max_float,hsw__render_basic__sampler1_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_uint64(query, 41, 248, NULL,hsw__render_basic__sampler0_texels__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_uint64(query, 42, 256, NULL,hsw__render_basic__sampler1_texels__read);
      }

      intel_perf_query_add_counter_uint64(query, 43, 264, NULL,hsw__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, hsw__render_basic__l3_sampler_throughput__max,hsw__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 45, 280, NULL,hsw__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 288, NULL,hsw__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 296, NULL,hsw__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 48, 304, NULL,hsw__render_basic__alpha_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 49, 312, NULL,hsw__render_basic__post_ps_stencil_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 50, 320, NULL,hsw__render_basic__post_ps_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 51, 328, NULL,hsw__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 336, NULL,hsw__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 53, 344, hsw__render_basic__gti_vf_throughput__max,hsw__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 352, hsw__render_basic__gti_depth_throughput__max,hsw__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 360, hsw__render_basic__gti_rcc_throughput__max,hsw__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 368, hsw__render_basic__gti_l3_throughput__max,hsw__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 376, hsw__render_basic__gti_read_throughput__max,hsw__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 384, hsw__render_basic__gti_write_throughput__max,hsw__render_basic__gti_write_throughput__read);

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 59, 392, NULL,hsw__render_basic__llc_accesses__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 60, 400, NULL,hsw__render_basic__llc_hits__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 61, 408, hsw__render_basic__llc_gpu_throughput__max,hsw__render_basic__llc_gpu_throughput__read);
      }

      intel_perf_query_add_counter_uint64(query, 62, 416, NULL,hsw__render_basic__ps_duration__read);

      intel_perf_query_add_counter_uint64(query, 63, 424, NULL,hsw__render_basic__vs_duration__read);

      intel_perf_query_add_counter_uint64(query, 64, 432, NULL,hsw__render_basic__gs_duration__read);

      intel_perf_query_add_counter_uint64(query, 65, 440, NULL,hsw__render_basic__ds_duration__read);

      intel_perf_query_add_counter_uint64(query, 66, 448, NULL,hsw__render_basic__hs_duration__read);

      intel_perf_query_add_counter_uint64(query, 67, 456, NULL,hsw__render_basic__cs_duration__read);

      intel_perf_query_add_counter_float(query, 68, 464, percentage_max_float,hsw__render_basic__sampler_bottleneck__read);

      intel_perf_query_add_counter_float(query, 69, 468, percentage_max_float,hsw__render_basic__eu_idle__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
hsw_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "b344c8cb-a291-4cbf-aa9c-b40213bfc96f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000253A4, .val = 0x00000000 },
         { .reg = 0x0002681C, .val = 0x01F00800 },
         { .reg = 0x00026820, .val = 0x00001000 },
         { .reg = 0x0002781C, .val = 0x01F00800 },
         { .reg = 0x00026520, .val = 0x00000007 },
         { .reg = 0x000265A0, .val = 0x00000007 },
         { .reg = 0x00025380, .val = 0x00000010 },
         { .reg = 0x0002538C, .val = 0x00300000 },
         { .reg = 0x00025384, .val = 0xAA8AAAAA },
         { .reg = 0x00025404, .val = 0xFFFFFFFF },
         { .reg = 0x00026800, .val = 0x00004202 },
         { .reg = 0x00026808, .val = 0x00605817 },
         { .reg = 0x0002680C, .val = 0x10001005 },
         { .reg = 0x00026804, .val = 0x00000000 },
         { .reg = 0x00027800, .val = 0x00000102 },
         { .reg = 0x00027808, .val = 0x0C0701E0 },
         { .reg = 0x0002780C, .val = 0x000200A0 },
         { .reg = 0x00027804, .val = 0x00000000 },
         { .reg = 0x00026484, .val = 0x44000000 },
         { .reg = 0x00026704, .val = 0x44000000 },
         { .reg = 0x00026500, .val = 0x00000006 },
         { .reg = 0x00026510, .val = 0x00000001 },
         { .reg = 0x00026504, .val = 0x88000000 },
         { .reg = 0x00026580, .val = 0x00000006 },
         { .reg = 0x00026590, .val = 0x00000020 },
         { .reg = 0x00026584, .val = 0x00000000 },
         { .reg = 0x00026104, .val = 0x55822222 },
         { .reg = 0x00026184, .val = 0xAA866666 },
         { .reg = 0x00025420, .val = 0x08320C83 },
         { .reg = 0x00025424, .val = 0x06820C83 },
         { .reg = 0x0002541C, .val = 0x00000000 },
         { .reg = 0x00025428, .val = 0x00000C03 },
         { .reg = 0x000091BC, .val = 0xE0400000 },
         { .reg = 0x000091C4, .val = 0xE4500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002718, .val = 0xAAAAAAAA },
         { .reg = 0x0000271C, .val = 0xAAAAAAAA },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002728, .val = 0xAAAAAAAA },
         { .reg = 0x0000272C, .val = 0xAAAAAAAA },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00000000 },
         { .reg = 0x00002748, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x00000000 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002754, .val = 0x00000000 },
         { .reg = 0x00002758, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,hsw__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,hsw__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, hsw__compute_basic__avg_gpu_core_frequency__max,hsw__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,hsw__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,hsw__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 4, 40, NULL,hsw__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 5, 48, NULL,hsw__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,hsw__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,hsw__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,hsw__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,hsw__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,hsw__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 12, 88, percentage_max_float,hsw__compute_basic__vs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 13, 96, percentage_max_uint64,hsw__compute_basic__vs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 15, 104, percentage_max_float,hsw__compute_basic__vs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 14, 112, NULL,hsw__compute_basic__vs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 32, 120, percentage_max_float,hsw__compute_basic__ps_eu_active__read);

      intel_perf_query_add_counter_float(query, 16, 124, percentage_max_float,hsw__compute_basic__hs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 17, 128, percentage_max_uint64,hsw__compute_basic__hs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 19, 136, percentage_max_float,hsw__compute_basic__hs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 18, 144, NULL,hsw__compute_basic__hs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 20, 152, percentage_max_float,hsw__compute_basic__ds_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 21, 160, percentage_max_uint64,hsw__compute_basic__ds_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 23, 168, percentage_max_float,hsw__compute_basic__ds_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 22, 176, NULL,hsw__compute_basic__ds_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 24, 184, percentage_max_float,hsw__compute_basic__gs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 25, 192, percentage_max_uint64,hsw__compute_basic__gs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 27, 200, percentage_max_float,hsw__compute_basic__gs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 26, 208, NULL,hsw__compute_basic__gs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 28, 216, percentage_max_float,hsw__compute_basic__cs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 29, 224, percentage_max_uint64,hsw__compute_basic__cs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 31, 232, percentage_max_float,hsw__compute_basic__cs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 30, 240, NULL,hsw__compute_basic__cs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 33, 248, percentage_max_uint64,hsw__compute_basic__ps_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 35, 256, percentage_max_float,hsw__compute_basic__ps_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 34, 264, NULL,hsw__compute_basic__ps_eu_stall_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 45, 272, NULL,hsw__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 280, NULL,hsw__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 288, NULL,hsw__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 48, 296, NULL,hsw__compute_basic__alpha_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 49, 304, NULL,hsw__compute_basic__post_ps_stencil_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 50, 312, NULL,hsw__compute_basic__post_ps_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 51, 320, NULL,hsw__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 70, 328, hsw__compute_basic__typed_bytes_read__max,hsw__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 336, hsw__compute_basic__typed_bytes_written__max,hsw__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 72, 344, NULL,hsw__compute_basic__typed_atomics__read);

      intel_perf_query_add_counter_uint64(query, 73, 352, hsw__compute_basic__untyped_bytes_read__max,hsw__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 360, hsw__compute_basic__untyped_bytes_written__max,hsw__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 75, 368, hsw__compute_basic__slm_bytes_read__max,hsw__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 76, 376, hsw__compute_basic__slm_bytes_written__max,hsw__compute_basic__slm_bytes_written__read);

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 59, 384, NULL,hsw__compute_basic__llc_accesses__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 60, 392, NULL,hsw__compute_basic__llc_hits__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
hsw_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 22);

   query->name = "Compute Metrics Extended set";
   query->symbol_name = "ComputeExtended";
   query->guid = "480f9795-cf6a-4204-a9e3-cd7015515f8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x0002681C, .val = 0x3EB00800 },
         { .reg = 0x00026820, .val = 0x00900000 },
         { .reg = 0x00025384, .val = 0x02AAAAAA },
         { .reg = 0x00025404, .val = 0x03FFFFFF },
         { .reg = 0x00026800, .val = 0x00142284 },
         { .reg = 0x00026808, .val = 0x0E629062 },
         { .reg = 0x0002680C, .val = 0x3F6F55CB },
         { .reg = 0x00026810, .val = 0x00000014 },
         { .reg = 0x00026804, .val = 0x00000000 },
         { .reg = 0x00026104, .val = 0x02AAAAAA },
         { .reg = 0x00026184, .val = 0x02AAAAAA },
         { .reg = 0x00025420, .val = 0x00000000 },
         { .reg = 0x00025424, .val = 0x00000000 },
         { .reg = 0x0002541C, .val = 0x00000000 },
         { .reg = 0x00025428, .val = 0x00000000 },
         { .reg = 0x000091BC, .val = 0xE0400000 },
         { .reg = 0x000091C4, .val = 0xE4500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FE2A },
         { .reg = 0x00002774, .val = 0x0000FF00 },
         { .reg = 0x00002778, .val = 0x0007FE6A },
         { .reg = 0x0000277C, .val = 0x0000FF00 },
         { .reg = 0x00002780, .val = 0x0007FE92 },
         { .reg = 0x00002784, .val = 0x0000FF00 },
         { .reg = 0x00002788, .val = 0x0007FEA2 },
         { .reg = 0x0000278C, .val = 0x0000FF00 },
         { .reg = 0x00002790, .val = 0x0007FE32 },
         { .reg = 0x00002794, .val = 0x0000FF00 },
         { .reg = 0x00002798, .val = 0x0007FE9A },
         { .reg = 0x0000279C, .val = 0x0000FF00 },
         { .reg = 0x000027A0, .val = 0x0007FF23 },
         { .reg = 0x000027A4, .val = 0x0000FF00 },
         { .reg = 0x000027A8, .val = 0x0007FFF3 },
         { .reg = 0x000027AC, .val = 0x0000FFFE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,hsw__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 77, 8, NULL,hsw__compute_extended__gpu_clocks__read);

      intel_perf_query_add_counter_uint64(query, 8, 16, NULL,hsw__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 78, 24, NULL,hsw__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 32, NULL,hsw__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 40, NULL,hsw__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 48, NULL,hsw__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 56, NULL,hsw__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 64, NULL,hsw__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 84, 72, NULL,hsw__compute_extended__eu_urb_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 85, 80, NULL,hsw__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 88, NULL,hsw__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 96, NULL,hsw__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 104, NULL,hsw__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 112, NULL,hsw__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 120, NULL,hsw__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 124, NULL,hsw__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 128, NULL,hsw__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 132, NULL,hsw__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 136, NULL,hsw__compute_extended__typed_atomics_per_cache_line__read);

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 59, 144, NULL,hsw__compute_extended__llc_accesses__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 60, 152, NULL,hsw__compute_extended__llc_hits__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
hsw_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 56);

   query->name = "Memory Reads Distribution set";
   query->symbol_name = "MemoryReads";
   query->guid = "399d3001-97d6-4240-b065-4fb843138e17";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000253A4, .val = 0x34300000 },
         { .reg = 0x00025440, .val = 0x2D800000 },
         { .reg = 0x00025444, .val = 0x00000008 },
         { .reg = 0x00025128, .val = 0x0E600000 },
         { .reg = 0x00025380, .val = 0x00000450 },
         { .reg = 0x00025390, .val = 0x00052C43 },
         { .reg = 0x00025384, .val = 0x00000000 },
         { .reg = 0x00025400, .val = 0x00006144 },
         { .reg = 0x00025408, .val = 0x0A418820 },
         { .reg = 0x0002540C, .val = 0x000820E6 },
         { .reg = 0x00025404, .val = 0xFF500000 },
         { .reg = 0x00025100, .val = 0x000005D6 },
         { .reg = 0x0002510C, .val = 0x0EF00000 },
         { .reg = 0x00025104, .val = 0x00000000 },
         { .reg = 0x00025420, .val = 0x02108421 },
         { .reg = 0x00025424, .val = 0x00008421 },
         { .reg = 0x0002541C, .val = 0x00000000 },
         { .reg = 0x00025428, .val = 0x00000000 },
         { .reg = 0x000091BC, .val = 0xE0400000 },
         { .reg = 0x000091C4, .val = 0xE4500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x76543298 },
         { .reg = 0x00002748, .val = 0x98989898 },
         { .reg = 0x00002744, .val = 0x000000E4 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x98A98A98 },
         { .reg = 0x00002758, .val = 0x88888888 },
         { .reg = 0x00002754, .val = 0x000C5500 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FC00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FC00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FC00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FC00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FC00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FC00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FC00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FC00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,hsw__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,hsw__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, hsw__memory_reads__avg_gpu_core_frequency__max,hsw__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,hsw__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,hsw__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 4, 40, NULL,hsw__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 5, 48, NULL,hsw__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,hsw__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,hsw__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,hsw__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,hsw__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,hsw__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_float(query, 12, 88, percentage_max_float,hsw__memory_reads__vs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 13, 96, percentage_max_uint64,hsw__memory_reads__vs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 15, 104, percentage_max_float,hsw__memory_reads__vs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 14, 112, NULL,hsw__memory_reads__vs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 16, 120, percentage_max_float,hsw__memory_reads__hs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 17, 128, percentage_max_uint64,hsw__memory_reads__hs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 19, 136, percentage_max_float,hsw__memory_reads__hs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 18, 144, NULL,hsw__memory_reads__hs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 20, 152, percentage_max_float,hsw__memory_reads__ds_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 21, 160, percentage_max_uint64,hsw__memory_reads__ds_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 23, 168, percentage_max_float,hsw__memory_reads__ds_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 22, 176, NULL,hsw__memory_reads__ds_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 24, 184, percentage_max_float,hsw__memory_reads__gs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 25, 192, percentage_max_uint64,hsw__memory_reads__gs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 27, 200, percentage_max_float,hsw__memory_reads__gs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 26, 208, NULL,hsw__memory_reads__gs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 28, 216, percentage_max_float,hsw__memory_reads__cs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 29, 224, percentage_max_uint64,hsw__memory_reads__cs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 31, 232, percentage_max_float,hsw__memory_reads__cs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 30, 240, NULL,hsw__memory_reads__cs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 32, 248, percentage_max_float,hsw__memory_reads__ps_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 33, 256, percentage_max_uint64,hsw__memory_reads__ps_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 35, 264, percentage_max_float,hsw__memory_reads__ps_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 34, 272, NULL,hsw__memory_reads__ps_eu_stall_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 45, 280, NULL,hsw__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 288, NULL,hsw__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 296, NULL,hsw__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 48, 304, NULL,hsw__memory_reads__alpha_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 49, 312, NULL,hsw__memory_reads__post_ps_stencil_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 50, 320, NULL,hsw__memory_reads__post_ps_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 51, 328, NULL,hsw__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 95, 336, NULL,hsw__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 344, NULL,hsw__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 352, NULL,hsw__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 360, NULL,hsw__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 368, NULL,hsw__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 100, 376, NULL,hsw__memory_reads__gti_hi_depth_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 101, 384, NULL,hsw__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 102, 392, NULL,hsw__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 103, 400, NULL,hsw__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 104, 408, NULL,hsw__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 105, 416, NULL,hsw__memory_reads__llc_read_accesses__read);

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 59, 424, NULL,hsw__memory_reads__llc_accesses__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 60, 432, NULL,hsw__memory_reads__llc_hits__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
hsw_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 56);

   query->name = "Memory Writes Distribution set";
   query->symbol_name = "MemoryWrites";
   query->guid = "f3c1ff4b-d0da-4ffa-8780-2c6b98f3f2d5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000253A4, .val = 0x34300000 },
         { .reg = 0x00025440, .val = 0x01500000 },
         { .reg = 0x00025444, .val = 0x00000120 },
         { .reg = 0x00025128, .val = 0x0C200000 },
         { .reg = 0x00025380, .val = 0x00000450 },
         { .reg = 0x00025390, .val = 0x00052C43 },
         { .reg = 0x00025384, .val = 0x00000000 },
         { .reg = 0x00025400, .val = 0x00007184 },
         { .reg = 0x00025408, .val = 0x0A418820 },
         { .reg = 0x0002540C, .val = 0x000820E6 },
         { .reg = 0x00025404, .val = 0xFF500000 },
         { .reg = 0x00025100, .val = 0x000005D6 },
         { .reg = 0x0002510C, .val = 0x1E700000 },
         { .reg = 0x00025104, .val = 0x00000000 },
         { .reg = 0x00025420, .val = 0x02108421 },
         { .reg = 0x00025424, .val = 0x00008421 },
         { .reg = 0x0002541C, .val = 0x00000000 },
         { .reg = 0x00025428, .val = 0x00000000 },
         { .reg = 0x000091BC, .val = 0xE0400000 },
         { .reg = 0x000091C4, .val = 0xE4500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x76543298 },
         { .reg = 0x00002748, .val = 0x98989898 },
         { .reg = 0x00002744, .val = 0x000000E4 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0xBABABABA },
         { .reg = 0x00002758, .val = 0x88888888 },
         { .reg = 0x00002754, .val = 0x000C5500 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FC00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FC00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FC00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FC00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FC00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FC00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FC00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FC00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,hsw__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,hsw__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, hsw__memory_writes__avg_gpu_core_frequency__max,hsw__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,hsw__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,hsw__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 4, 40, NULL,hsw__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 5, 48, NULL,hsw__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,hsw__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,hsw__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,hsw__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,hsw__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,hsw__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_float(query, 12, 88, percentage_max_float,hsw__memory_writes__vs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 13, 96, percentage_max_uint64,hsw__memory_writes__vs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 15, 104, percentage_max_float,hsw__memory_writes__vs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 14, 112, NULL,hsw__memory_writes__vs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 16, 120, percentage_max_float,hsw__memory_writes__hs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 17, 128, percentage_max_uint64,hsw__memory_writes__hs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 19, 136, percentage_max_float,hsw__memory_writes__hs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 18, 144, NULL,hsw__memory_writes__hs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 20, 152, percentage_max_float,hsw__memory_writes__ds_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 21, 160, percentage_max_uint64,hsw__memory_writes__ds_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 23, 168, percentage_max_float,hsw__memory_writes__ds_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 22, 176, NULL,hsw__memory_writes__ds_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 24, 184, percentage_max_float,hsw__memory_writes__gs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 25, 192, percentage_max_uint64,hsw__memory_writes__gs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 27, 200, percentage_max_float,hsw__memory_writes__gs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 26, 208, NULL,hsw__memory_writes__gs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 28, 216, percentage_max_float,hsw__memory_writes__cs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 29, 224, percentage_max_uint64,hsw__memory_writes__cs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 31, 232, percentage_max_float,hsw__memory_writes__cs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 30, 240, NULL,hsw__memory_writes__cs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 32, 248, percentage_max_float,hsw__memory_writes__ps_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 33, 256, percentage_max_uint64,hsw__memory_writes__ps_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 35, 264, percentage_max_float,hsw__memory_writes__ps_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 34, 272, NULL,hsw__memory_writes__ps_eu_stall_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 45, 280, NULL,hsw__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 288, NULL,hsw__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 296, NULL,hsw__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 48, 304, NULL,hsw__memory_writes__alpha_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 49, 312, NULL,hsw__memory_writes__post_ps_stencil_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 50, 320, NULL,hsw__memory_writes__post_ps_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 51, 328, NULL,hsw__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 106, 336, NULL,hsw__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 344, NULL,hsw__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 352, NULL,hsw__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 360, NULL,hsw__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 368, NULL,hsw__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 376, NULL,hsw__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 384, NULL,hsw__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 392, NULL,hsw__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 114, 400, NULL,hsw__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 115, 408, NULL,hsw__memory_writes__llc_wr_accesses__read);

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 59, 416, NULL,hsw__memory_writes__llc_accesses__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 60, 424, NULL,hsw__memory_writes__llc_hits__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 61, 432, hsw__memory_writes__llc_gpu_throughput__max,hsw__memory_writes__llc_gpu_throughput__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
hsw_register_sampler_balance_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 57);

   query->name = "Metric set SamplerBalance";
   query->symbol_name = "SamplerBalance";
   query->guid = "e111cda4-19c3-41ee-b326-f99ac44ebf78";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x0002EB9C, .val = 0x01906400 },
         { .reg = 0x0002FB9C, .val = 0x01906400 },
         { .reg = 0x000253A4, .val = 0x00000000 },
         { .reg = 0x00026B9C, .val = 0x01906400 },
         { .reg = 0x00027B9C, .val = 0x01906400 },
         { .reg = 0x00027104, .val = 0x00A00000 },
         { .reg = 0x00027184, .val = 0x00A50000 },
         { .reg = 0x0002E804, .val = 0x00500000 },
         { .reg = 0x0002E984, .val = 0x00500000 },
         { .reg = 0x0002EB04, .val = 0x00500000 },
         { .reg = 0x0002EB80, .val = 0x00000084 },
         { .reg = 0x0002EB8C, .val = 0x14200000 },
         { .reg = 0x0002EB84, .val = 0x00000000 },
         { .reg = 0x0002F804, .val = 0x00050000 },
         { .reg = 0x0002F984, .val = 0x00050000 },
         { .reg = 0x0002FB04, .val = 0x00050000 },
         { .reg = 0x0002FB80, .val = 0x00000084 },
         { .reg = 0x0002FB8C, .val = 0x00050800 },
         { .reg = 0x0002FB84, .val = 0x00000000 },
         { .reg = 0x00025380, .val = 0x00000010 },
         { .reg = 0x0002538C, .val = 0x000000C0 },
         { .reg = 0x00025384, .val = 0xAA550000 },
         { .reg = 0x00025404, .val = 0xFFFFC000 },
         { .reg = 0x00026804, .val = 0x50000000 },
         { .reg = 0x00026984, .val = 0x50000000 },
         { .reg = 0x00026B04, .val = 0x50000000 },
         { .reg = 0x00026B80, .val = 0x00000084 },
         { .reg = 0x00026B90, .val = 0x00050800 },
         { .reg = 0x00026B84, .val = 0x00000000 },
         { .reg = 0x00027804, .val = 0x05000000 },
         { .reg = 0x00027984, .val = 0x05000000 },
         { .reg = 0x00027B04, .val = 0x05000000 },
         { .reg = 0x00027B80, .val = 0x00000084 },
         { .reg = 0x00027B90, .val = 0x00000142 },
         { .reg = 0x00027B84, .val = 0x00000000 },
         { .reg = 0x00026104, .val = 0xA0000000 },
         { .reg = 0x00026184, .val = 0xA5000000 },
         { .reg = 0x00025424, .val = 0x00008620 },
         { .reg = 0x0002541C, .val = 0x00000000 },
         { .reg = 0x00025428, .val = 0x0004A54A },
         { .reg = 0x000091BC, .val = 0xE0400000 },
         { .reg = 0x000091C4, .val = 0xE4500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,hsw__sampler_balance__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,hsw__sampler_balance__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, hsw__sampler_balance__avg_gpu_core_frequency__max,hsw__sampler_balance__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,hsw__sampler_balance__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,hsw__sampler_balance__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 4, 40, NULL,hsw__sampler_balance__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 5, 48, NULL,hsw__sampler_balance__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,hsw__sampler_balance__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,hsw__sampler_balance__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,hsw__sampler_balance__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,hsw__sampler_balance__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,hsw__sampler_balance__eu_stall__read);

      intel_perf_query_add_counter_float(query, 12, 88, percentage_max_float,hsw__sampler_balance__vs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 13, 96, percentage_max_uint64,hsw__sampler_balance__vs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 15, 104, percentage_max_float,hsw__sampler_balance__vs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 14, 112, NULL,hsw__sampler_balance__vs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 16, 120, percentage_max_float,hsw__sampler_balance__hs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 17, 128, percentage_max_uint64,hsw__sampler_balance__hs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 19, 136, percentage_max_float,hsw__sampler_balance__hs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 18, 144, NULL,hsw__sampler_balance__hs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 20, 152, percentage_max_float,hsw__sampler_balance__ds_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 21, 160, percentage_max_uint64,hsw__sampler_balance__ds_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 23, 168, percentage_max_float,hsw__sampler_balance__ds_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 22, 176, NULL,hsw__sampler_balance__ds_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 24, 184, percentage_max_float,hsw__sampler_balance__gs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 25, 192, percentage_max_uint64,hsw__sampler_balance__gs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 27, 200, percentage_max_float,hsw__sampler_balance__gs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 26, 208, NULL,hsw__sampler_balance__gs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 28, 216, percentage_max_float,hsw__sampler_balance__cs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 29, 224, percentage_max_uint64,hsw__sampler_balance__cs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 31, 232, percentage_max_float,hsw__sampler_balance__cs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 30, 240, NULL,hsw__sampler_balance__cs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 32, 248, percentage_max_float,hsw__sampler_balance__ps_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 33, 256, percentage_max_uint64,hsw__sampler_balance__ps_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 35, 264, percentage_max_float,hsw__sampler_balance__ps_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 34, 272, NULL,hsw__sampler_balance__ps_eu_stall_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 45, 280, NULL,hsw__sampler_balance__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 288, NULL,hsw__sampler_balance__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 296, NULL,hsw__sampler_balance__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 48, 304, NULL,hsw__sampler_balance__alpha_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 49, 312, NULL,hsw__sampler_balance__post_ps_stencil_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 50, 320, NULL,hsw__sampler_balance__post_ps_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 51, 328, NULL,hsw__sampler_balance__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 62, 336, NULL,hsw__sampler_balance__ps_duration__read);

      intel_perf_query_add_counter_uint64(query, 63, 344, NULL,hsw__sampler_balance__vs_duration__read);

      intel_perf_query_add_counter_uint64(query, 64, 352, NULL,hsw__sampler_balance__gs_duration__read);

      intel_perf_query_add_counter_uint64(query, 65, 360, NULL,hsw__sampler_balance__ds_duration__read);

      intel_perf_query_add_counter_uint64(query, 66, 368, NULL,hsw__sampler_balance__hs_duration__read);

      intel_perf_query_add_counter_uint64(query, 67, 376, NULL,hsw__sampler_balance__cs_duration__read);

      intel_perf_query_add_counter_float(query, 69, 384, percentage_max_float,hsw__sampler_balance__eu_idle__read);

      intel_perf_query_add_counter_uint64(query, 116, 392, NULL,hsw__sampler_balance__sampler_l2_cache_misses__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_uint64(query, 117, 400, NULL,hsw__sampler_balance__sampler0_l2_cache_misses__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_uint64(query, 118, 408, NULL,hsw__sampler_balance__sampler1_l2_cache_misses__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_uint64(query, 119, 416, NULL,hsw__sampler_balance__sampler2_l2_cache_misses__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_uint64(query, 120, 424, NULL,hsw__sampler_balance__sampler3_l2_cache_misses__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 59, 432, NULL,hsw__sampler_balance__llc_accesses__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_uint64(query, 60, 440, NULL,hsw__sampler_balance__llc_hits__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_hsw(struct intel_perf_config *perf)
{
   hsw_register_render_basic_counter_query(perf);
   hsw_register_compute_basic_counter_query(perf);
   hsw_register_compute_extended_counter_query(perf);
   hsw_register_memory_reads_counter_query(perf);
   hsw_register_memory_writes_counter_query(perf);
   hsw_register_sampler_balance_counter_query(perf);
}


static void
bdw_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "b541bd57-0e0f-4154-b4c0-5858010a2bf7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->sys_vars.slice_mask & 0x01) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x143F000F },
            { .reg = 0x00009888, .val = 0x14110014 },
            { .reg = 0x00009888, .val = 0x14310014 },
            { .reg = 0x00009888, .val = 0x14BF000F },
            { .reg = 0x00009888, .val = 0x118A0317 },
            { .reg = 0x00009888, .val = 0x13837BE0 },
            { .reg = 0x00009888, .val = 0x3B800060 },
            { .reg = 0x00009888, .val = 0x3D800005 },
            { .reg = 0x00009888, .val = 0x005C4000 },
            { .reg = 0x00009888, .val = 0x065C8000 },
            { .reg = 0x00009888, .val = 0x085CC000 },
            { .reg = 0x00009888, .val = 0x003D8000 },
            { .reg = 0x00009888, .val = 0x183D0800 },
            { .reg = 0x00009888, .val = 0x0A3F0023 },
            { .reg = 0x00009888, .val = 0x103F0000 },
            { .reg = 0x00009888, .val = 0x00584000 },
            { .reg = 0x00009888, .val = 0x08584000 },
            { .reg = 0x00009888, .val = 0x0A5A4000 },
            { .reg = 0x00009888, .val = 0x005B4000 },
            { .reg = 0x00009888, .val = 0x0E5B8000 },
            { .reg = 0x00009888, .val = 0x185B2400 },
            { .reg = 0x00009888, .val = 0x0A1D4000 },
            { .reg = 0x00009888, .val = 0x0C1F0800 },
            { .reg = 0x00009888, .val = 0x0E1FAA00 },
            { .reg = 0x00009888, .val = 0x00384000 },
            { .reg = 0x00009888, .val = 0x0E384000 },
            { .reg = 0x00009888, .val = 0x16384000 },
            { .reg = 0x00009888, .val = 0x18380001 },
            { .reg = 0x00009888, .val = 0x00392000 },
            { .reg = 0x00009888, .val = 0x06398000 },
            { .reg = 0x00009888, .val = 0x0839A000 },
            { .reg = 0x00009888, .val = 0x0A391000 },
            { .reg = 0x00009888, .val = 0x00104000 },
            { .reg = 0x00009888, .val = 0x08104000 },
            { .reg = 0x00009888, .val = 0x00110030 },
            { .reg = 0x00009888, .val = 0x08110031 },
            { .reg = 0x00009888, .val = 0x10110000 },
            { .reg = 0x00009888, .val = 0x00134000 },
            { .reg = 0x00009888, .val = 0x16130020 },
            { .reg = 0x00009888, .val = 0x06308000 },
            { .reg = 0x00009888, .val = 0x08308000 },
            { .reg = 0x00009888, .val = 0x06311800 },
            { .reg = 0x00009888, .val = 0x08311880 },
            { .reg = 0x00009888, .val = 0x10310000 },
            { .reg = 0x00009888, .val = 0x0E334000 },
            { .reg = 0x00009888, .val = 0x16330080 },
            { .reg = 0x00009888, .val = 0x0ABF1180 },
            { .reg = 0x00009888, .val = 0x10BF0000 },
            { .reg = 0x00009888, .val = 0x0ADA8000 },
            { .reg = 0x00009888, .val = 0x0A9D8000 },
            { .reg = 0x00009888, .val = 0x109F0002 },
            { .reg = 0x00009888, .val = 0x0AB94000 },
            { .reg = 0x00009888, .val = 0x0D888000 },
            { .reg = 0x00009888, .val = 0x038A0380 },
            { .reg = 0x00009888, .val = 0x058A000E },
            { .reg = 0x00009888, .val = 0x018A8000 },
            { .reg = 0x00009888, .val = 0x0F8A8000 },
            { .reg = 0x00009888, .val = 0x198A8000 },
            { .reg = 0x00009888, .val = 0x1B8A00A0 },
            { .reg = 0x00009888, .val = 0x078A0000 },
            { .reg = 0x00009888, .val = 0x098A0000 },
            { .reg = 0x00009888, .val = 0x238B2820 },
            { .reg = 0x00009888, .val = 0x258B2550 },
            { .reg = 0x00009888, .val = 0x198C1000 },
            { .reg = 0x00009888, .val = 0x0B8D8000 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x2185AAA0 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x0D831021 },
            { .reg = 0x00009888, .val = 0x0F83572F },
            { .reg = 0x00009888, .val = 0x01835680 },
            { .reg = 0x00009888, .val = 0x0383002C },
            { .reg = 0x00009888, .val = 0x11830000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830001 },
            { .reg = 0x00009888, .val = 0x05830000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x05844000 },
            { .reg = 0x00009888, .val = 0x1B80C137 },
            { .reg = 0x00009888, .val = 0x1D80C147 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x17808000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x15804000 },
            { .reg = 0x00009888, .val = 0x4D801110 },
            { .reg = 0x00009888, .val = 0x4F800331 },
            { .reg = 0x00009888, .val = 0x43800802 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45801465 },
            { .reg = 0x00009888, .val = 0x53801111 },
            { .reg = 0x00009888, .val = 0x478014A5 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F800CA5 },
            { .reg = 0x00009888, .val = 0x41800003 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->sys_vars.slice_mask & 0x02) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x143F000F },
            { .reg = 0x00009888, .val = 0x14BF000F },
            { .reg = 0x00009888, .val = 0x14910014 },
            { .reg = 0x00009888, .val = 0x14B10014 },
            { .reg = 0x00009888, .val = 0x118A0317 },
            { .reg = 0x00009888, .val = 0x13837BE0 },
            { .reg = 0x00009888, .val = 0x3B800060 },
            { .reg = 0x00009888, .val = 0x3D800005 },
            { .reg = 0x00009888, .val = 0x0A3F0023 },
            { .reg = 0x00009888, .val = 0x103F0000 },
            { .reg = 0x00009888, .val = 0x0A5A4000 },
            { .reg = 0x00009888, .val = 0x0A1D4000 },
            { .reg = 0x00009888, .val = 0x0E1F8000 },
            { .reg = 0x00009888, .val = 0x0A391000 },
            { .reg = 0x00009888, .val = 0x00DC4000 },
            { .reg = 0x00009888, .val = 0x06DC8000 },
            { .reg = 0x00009888, .val = 0x08DCC000 },
            { .reg = 0x00009888, .val = 0x00BD8000 },
            { .reg = 0x00009888, .val = 0x18BD0800 },
            { .reg = 0x00009888, .val = 0x0ABF1180 },
            { .reg = 0x00009888, .val = 0x10BF0000 },
            { .reg = 0x00009888, .val = 0x00D84000 },
            { .reg = 0x00009888, .val = 0x08D84000 },
            { .reg = 0x00009888, .val = 0x0ADA8000 },
            { .reg = 0x00009888, .val = 0x00DB4000 },
            { .reg = 0x00009888, .val = 0x0EDB8000 },
            { .reg = 0x00009888, .val = 0x18DB2400 },
            { .reg = 0x00009888, .val = 0x0A9D8000 },
            { .reg = 0x00009888, .val = 0x0C9F0800 },
            { .reg = 0x00009888, .val = 0x0E9F2A00 },
            { .reg = 0x00009888, .val = 0x109F0002 },
            { .reg = 0x00009888, .val = 0x00B84000 },
            { .reg = 0x00009888, .val = 0x0EB84000 },
            { .reg = 0x00009888, .val = 0x16B84000 },
            { .reg = 0x00009888, .val = 0x18B80001 },
            { .reg = 0x00009888, .val = 0x00B92000 },
            { .reg = 0x00009888, .val = 0x06B98000 },
            { .reg = 0x00009888, .val = 0x08B9A000 },
            { .reg = 0x00009888, .val = 0x0AB94000 },
            { .reg = 0x00009888, .val = 0x00904000 },
            { .reg = 0x00009888, .val = 0x08904000 },
            { .reg = 0x00009888, .val = 0x00910030 },
            { .reg = 0x00009888, .val = 0x08910031 },
            { .reg = 0x00009888, .val = 0x10910000 },
            { .reg = 0x00009888, .val = 0x00934000 },
            { .reg = 0x00009888, .val = 0x16930020 },
            { .reg = 0x00009888, .val = 0x06B08000 },
            { .reg = 0x00009888, .val = 0x08B08000 },
            { .reg = 0x00009888, .val = 0x06B11800 },
            { .reg = 0x00009888, .val = 0x08B11880 },
            { .reg = 0x00009888, .val = 0x10B10000 },
            { .reg = 0x00009888, .val = 0x0EB34000 },
            { .reg = 0x00009888, .val = 0x16B30080 },
            { .reg = 0x00009888, .val = 0x01888000 },
            { .reg = 0x00009888, .val = 0x0D88B800 },
            { .reg = 0x00009888, .val = 0x038A0380 },
            { .reg = 0x00009888, .val = 0x058A000E },
            { .reg = 0x00009888, .val = 0x1B8A0080 },
            { .reg = 0x00009888, .val = 0x078A0000 },
            { .reg = 0x00009888, .val = 0x098A0000 },
            { .reg = 0x00009888, .val = 0x238B2840 },
            { .reg = 0x00009888, .val = 0x258B26A0 },
            { .reg = 0x00009888, .val = 0x018C4000 },
            { .reg = 0x00009888, .val = 0x0F8C4000 },
            { .reg = 0x00009888, .val = 0x178C2000 },
            { .reg = 0x00009888, .val = 0x198C1100 },
            { .reg = 0x00009888, .val = 0x018D2000 },
            { .reg = 0x00009888, .val = 0x078D8000 },
            { .reg = 0x00009888, .val = 0x098DA000 },
            { .reg = 0x00009888, .val = 0x0B8D8000 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x2185AAA0 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x0D831021 },
            { .reg = 0x00009888, .val = 0x0F83572F },
            { .reg = 0x00009888, .val = 0x01835680 },
            { .reg = 0x00009888, .val = 0x0383002C },
            { .reg = 0x00009888, .val = 0x11830000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830001 },
            { .reg = 0x00009888, .val = 0x05830000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x05844000 },
            { .reg = 0x00009888, .val = 0x1B80C137 },
            { .reg = 0x00009888, .val = 0x1D80C147 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x17808000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x15804000 },
            { .reg = 0x00009888, .val = 0x4D801550 },
            { .reg = 0x00009888, .val = 0x4F800331 },
            { .reg = 0x00009888, .val = 0x43800802 },
            { .reg = 0x00009888, .val = 0x51800400 },
            { .reg = 0x00009888, .val = 0x458004A1 },
            { .reg = 0x00009888, .val = 0x53805555 },
            { .reg = 0x00009888, .val = 0x47800421 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F801421 },
            { .reg = 0x00009888, .val = 0x41800845 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__render_basic__avg_gpu_core_frequency__max,bdw__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,bdw__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,bdw__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,bdw__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,bdw__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,bdw__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,bdw__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,bdw__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,bdw__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,bdw__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,bdw__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,bdw__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,bdw__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,bdw__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,bdw__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,bdw__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,bdw__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,bdw__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,bdw__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,bdw__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,bdw__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,bdw__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,bdw__render_basic__sampler1_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,bdw__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,bdw__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,bdw__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,bdw__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 168, NULL,bdw__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 139, 176, NULL,bdw__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 184, NULL,bdw__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 192, NULL,bdw__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 200, NULL,bdw__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 208, NULL,bdw__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, bdw__render_basic__slm_bytes_read__max,bdw__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, bdw__render_basic__slm_bytes_written__max,bdw__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,bdw__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,bdw__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,bdw__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,bdw__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, bdw__render_basic__l3_sampler_throughput__max,bdw__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, bdw__render_basic__l3_shader_throughput__max,bdw__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,bdw__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, bdw__render_basic__gti_vf_throughput__max,bdw__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, bdw__render_basic__gti_depth_throughput__max,bdw__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, bdw__render_basic__gti_rcc_throughput__max,bdw__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, bdw__render_basic__gti_l3_throughput__max,bdw__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, bdw__render_basic__gti_hdc_lookups_throughput__max,bdw__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, bdw__render_basic__gti_read_throughput__max,bdw__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, bdw__render_basic__gti_write_throughput__max,bdw__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,bdw__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "35fbc9b2-a891-40a6-a38d-022bb7057552";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->sys_vars.slice_mask & 0x01) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x105C00E0 },
            { .reg = 0x00009888, .val = 0x105800E0 },
            { .reg = 0x00009888, .val = 0x103800E0 },
            { .reg = 0x00009888, .val = 0x3580001A },
            { .reg = 0x00009888, .val = 0x3B800060 },
            { .reg = 0x00009888, .val = 0x3D800005 },
            { .reg = 0x00009888, .val = 0x065C2100 },
            { .reg = 0x00009888, .val = 0x0A5C0041 },
            { .reg = 0x00009888, .val = 0x0C5C6600 },
            { .reg = 0x00009888, .val = 0x005C6580 },
            { .reg = 0x00009888, .val = 0x085C8000 },
            { .reg = 0x00009888, .val = 0x0E5C8000 },
            { .reg = 0x00009888, .val = 0x00580042 },
            { .reg = 0x00009888, .val = 0x08582080 },
            { .reg = 0x00009888, .val = 0x0C58004C },
            { .reg = 0x00009888, .val = 0x0E582580 },
            { .reg = 0x00009888, .val = 0x005B4000 },
            { .reg = 0x00009888, .val = 0x185B1000 },
            { .reg = 0x00009888, .val = 0x1A5B0104 },
            { .reg = 0x00009888, .val = 0x0C1FA800 },
            { .reg = 0x00009888, .val = 0x0E1FAA00 },
            { .reg = 0x00009888, .val = 0x101F02AA },
            { .reg = 0x00009888, .val = 0x08380042 },
            { .reg = 0x00009888, .val = 0x0A382080 },
            { .reg = 0x00009888, .val = 0x0E38404C },
            { .reg = 0x00009888, .val = 0x0238404B },
            { .reg = 0x00009888, .val = 0x00384000 },
            { .reg = 0x00009888, .val = 0x16380000 },
            { .reg = 0x00009888, .val = 0x18381145 },
            { .reg = 0x00009888, .val = 0x04380000 },
            { .reg = 0x00009888, .val = 0x0039A000 },
            { .reg = 0x00009888, .val = 0x06398000 },
            { .reg = 0x00009888, .val = 0x0839A000 },
            { .reg = 0x00009888, .val = 0x0A39A000 },
            { .reg = 0x00009888, .val = 0x0C39A000 },
            { .reg = 0x00009888, .val = 0x0E39A000 },
            { .reg = 0x00009888, .val = 0x02392000 },
            { .reg = 0x00009888, .val = 0x018A8000 },
            { .reg = 0x00009888, .val = 0x0F8A8000 },
            { .reg = 0x00009888, .val = 0x198A8000 },
            { .reg = 0x00009888, .val = 0x1B8AAAA0 },
            { .reg = 0x00009888, .val = 0x1D8A0002 },
            { .reg = 0x00009888, .val = 0x038A8000 },
            { .reg = 0x00009888, .val = 0x058A8000 },
            { .reg = 0x00009888, .val = 0x238B02A0 },
            { .reg = 0x00009888, .val = 0x258B5550 },
            { .reg = 0x00009888, .val = 0x278B0015 },
            { .reg = 0x00009888, .val = 0x1F850A80 },
            { .reg = 0x00009888, .val = 0x2185AAA0 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830155 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x03844000 },
            { .reg = 0x00009888, .val = 0x17808137 },
            { .reg = 0x00009888, .val = 0x1980C147 },
            { .reg = 0x00009888, .val = 0x1B80C0E5 },
            { .reg = 0x00009888, .val = 0x1D80C0E3 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x13804000 },
            { .reg = 0x00009888, .val = 0x15800000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D801000 },
            { .reg = 0x00009888, .val = 0x4F800111 },
            { .reg = 0x00009888, .val = 0x43800062 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800062 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800062 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F801062 },
            { .reg = 0x00009888, .val = 0x41801084 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->sys_vars.slice_mask & 0x02) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x10DC00E0 },
            { .reg = 0x00009888, .val = 0x10D800E0 },
            { .reg = 0x00009888, .val = 0x10B800E0 },
            { .reg = 0x00009888, .val = 0x3580001A },
            { .reg = 0x00009888, .val = 0x3B800060 },
            { .reg = 0x00009888, .val = 0x3D800005 },
            { .reg = 0x00009888, .val = 0x06DC2100 },
            { .reg = 0x00009888, .val = 0x0ADC0041 },
            { .reg = 0x00009888, .val = 0x0CDC6600 },
            { .reg = 0x00009888, .val = 0x00DC6580 },
            { .reg = 0x00009888, .val = 0x08DC8000 },
            { .reg = 0x00009888, .val = 0x0EDC8000 },
            { .reg = 0x00009888, .val = 0x00D80042 },
            { .reg = 0x00009888, .val = 0x08D82080 },
            { .reg = 0x00009888, .val = 0x0CD8004C },
            { .reg = 0x00009888, .val = 0x0ED82580 },
            { .reg = 0x00009888, .val = 0x00DB4000 },
            { .reg = 0x00009888, .val = 0x18DB1000 },
            { .reg = 0x00009888, .val = 0x1ADB0104 },
            { .reg = 0x00009888, .val = 0x0C9FA800 },
            { .reg = 0x00009888, .val = 0x0E9FAA00 },
            { .reg = 0x00009888, .val = 0x109F02AA },
            { .reg = 0x00009888, .val = 0x08B80042 },
            { .reg = 0x00009888, .val = 0x0AB82080 },
            { .reg = 0x00009888, .val = 0x0EB8404C },
            { .reg = 0x00009888, .val = 0x02B8404B },
            { .reg = 0x00009888, .val = 0x00B84000 },
            { .reg = 0x00009888, .val = 0x16B80000 },
            { .reg = 0x00009888, .val = 0x18B81145 },
            { .reg = 0x00009888, .val = 0x04B80000 },
            { .reg = 0x00009888, .val = 0x00B9A000 },
            { .reg = 0x00009888, .val = 0x06B98000 },
            { .reg = 0x00009888, .val = 0x08B9A000 },
            { .reg = 0x00009888, .val = 0x0AB9A000 },
            { .reg = 0x00009888, .val = 0x0CB9A000 },
            { .reg = 0x00009888, .val = 0x0EB9A000 },
            { .reg = 0x00009888, .val = 0x02B92000 },
            { .reg = 0x00009888, .val = 0x01888000 },
            { .reg = 0x00009888, .val = 0x0D88F800 },
            { .reg = 0x00009888, .val = 0x0F88000F },
            { .reg = 0x00009888, .val = 0x03888000 },
            { .reg = 0x00009888, .val = 0x05888000 },
            { .reg = 0x00009888, .val = 0x238B0540 },
            { .reg = 0x00009888, .val = 0x258BAAA0 },
            { .reg = 0x00009888, .val = 0x278B002A },
            { .reg = 0x00009888, .val = 0x018C4000 },
            { .reg = 0x00009888, .val = 0x0F8C4000 },
            { .reg = 0x00009888, .val = 0x178C2000 },
            { .reg = 0x00009888, .val = 0x198C5500 },
            { .reg = 0x00009888, .val = 0x1B8C0015 },
            { .reg = 0x00009888, .val = 0x038C4000 },
            { .reg = 0x00009888, .val = 0x058C4000 },
            { .reg = 0x00009888, .val = 0x018DA000 },
            { .reg = 0x00009888, .val = 0x078D8000 },
            { .reg = 0x00009888, .val = 0x098DA000 },
            { .reg = 0x00009888, .val = 0x0B8DA000 },
            { .reg = 0x00009888, .val = 0x0D8DA000 },
            { .reg = 0x00009888, .val = 0x0F8DA000 },
            { .reg = 0x00009888, .val = 0x038D2000 },
            { .reg = 0x00009888, .val = 0x1F850A80 },
            { .reg = 0x00009888, .val = 0x2185AAA0 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830155 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x03844000 },
            { .reg = 0x00009888, .val = 0x17808137 },
            { .reg = 0x00009888, .val = 0x1980C147 },
            { .reg = 0x00009888, .val = 0x1B80C0E5 },
            { .reg = 0x00009888, .val = 0x1D80C0E3 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x13804000 },
            { .reg = 0x00009888, .val = 0x15800000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D805000 },
            { .reg = 0x00009888, .val = 0x4F800555 },
            { .reg = 0x00009888, .val = 0x43800062 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800062 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800062 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F800062 },
            { .reg = 0x00009888, .val = 0x41800000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__compute_basic__avg_gpu_core_frequency__max,bdw__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,bdw__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,bdw__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, bdw__compute_basic__eu_avg_ipc_rate__max,bdw__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,bdw__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,bdw__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,bdw__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,bdw__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,bdw__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,bdw__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,bdw__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,bdw__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,bdw__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,bdw__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,bdw__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, bdw__compute_basic__slm_bytes_read__max,bdw__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, bdw__compute_basic__slm_bytes_written__max,bdw__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,bdw__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,bdw__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, bdw__compute_basic__l3_shader_throughput__max,bdw__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,bdw__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, bdw__compute_basic__typed_bytes_read__max,bdw__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 155, 240, bdw__compute_basic__typed_bytes_written__max,bdw__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, bdw__compute_basic__untyped_bytes_read__max,bdw__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, bdw__compute_basic__untyped_bytes_written__max,bdw__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, bdw__compute_basic__gti_read_throughput__max,bdw__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, bdw__compute_basic__gti_write_throughput__max,bdw__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "233d0544-fff7-4281-8291-e02f222aff72";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x0A1E0000 },
         { .reg = 0x00009888, .val = 0x0C1F000F },
         { .reg = 0x00009888, .val = 0x10176800 },
         { .reg = 0x00009888, .val = 0x1191001F },
         { .reg = 0x00009888, .val = 0x0B880320 },
         { .reg = 0x00009888, .val = 0x01890C40 },
         { .reg = 0x00009888, .val = 0x118A1C00 },
         { .reg = 0x00009888, .val = 0x118D7C00 },
         { .reg = 0x00009888, .val = 0x118E0020 },
         { .reg = 0x00009888, .val = 0x118F4C00 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x13900001 },
         { .reg = 0x00009888, .val = 0x065C4000 },
         { .reg = 0x00009888, .val = 0x0C3D8000 },
         { .reg = 0x00009888, .val = 0x06584000 },
         { .reg = 0x00009888, .val = 0x0C5B4000 },
         { .reg = 0x00009888, .val = 0x081E0040 },
         { .reg = 0x00009888, .val = 0x0E1E0000 },
         { .reg = 0x00009888, .val = 0x021F5400 },
         { .reg = 0x00009888, .val = 0x001F0000 },
         { .reg = 0x00009888, .val = 0x101F0010 },
         { .reg = 0x00009888, .val = 0x0E1F0080 },
         { .reg = 0x00009888, .val = 0x0C384000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x0C13C000 },
         { .reg = 0x00009888, .val = 0x06164000 },
         { .reg = 0x00009888, .val = 0x06170012 },
         { .reg = 0x00009888, .val = 0x00170000 },
         { .reg = 0x00009888, .val = 0x01910005 },
         { .reg = 0x00009888, .val = 0x07880002 },
         { .reg = 0x00009888, .val = 0x01880C00 },
         { .reg = 0x00009888, .val = 0x0F880000 },
         { .reg = 0x00009888, .val = 0x0D880000 },
         { .reg = 0x00009888, .val = 0x05880000 },
         { .reg = 0x00009888, .val = 0x09890032 },
         { .reg = 0x00009888, .val = 0x078A0800 },
         { .reg = 0x00009888, .val = 0x0F8A0A00 },
         { .reg = 0x00009888, .val = 0x198A4000 },
         { .reg = 0x00009888, .val = 0x1B8A2000 },
         { .reg = 0x00009888, .val = 0x1D8A0000 },
         { .reg = 0x00009888, .val = 0x038A4000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x238B54C0 },
         { .reg = 0x00009888, .val = 0x258BAA55 },
         { .reg = 0x00009888, .val = 0x278B0019 },
         { .reg = 0x00009888, .val = 0x198C0100 },
         { .reg = 0x00009888, .val = 0x058C4000 },
         { .reg = 0x00009888, .val = 0x0F8D0015 },
         { .reg = 0x00009888, .val = 0x018D1000 },
         { .reg = 0x00009888, .val = 0x098D8000 },
         { .reg = 0x00009888, .val = 0x0B8DF000 },
         { .reg = 0x00009888, .val = 0x0D8D3000 },
         { .reg = 0x00009888, .val = 0x038DE000 },
         { .reg = 0x00009888, .val = 0x058D3000 },
         { .reg = 0x00009888, .val = 0x0D8E0004 },
         { .reg = 0x00009888, .val = 0x058E000C },
         { .reg = 0x00009888, .val = 0x098E0000 },
         { .reg = 0x00009888, .val = 0x078E0000 },
         { .reg = 0x00009888, .val = 0x038E0000 },
         { .reg = 0x00009888, .val = 0x0B8F0020 },
         { .reg = 0x00009888, .val = 0x198F0C00 },
         { .reg = 0x00009888, .val = 0x078F8000 },
         { .reg = 0x00009888, .val = 0x098F4000 },
         { .reg = 0x00009888, .val = 0x0B900980 },
         { .reg = 0x00009888, .val = 0x03900D80 },
         { .reg = 0x00009888, .val = 0x01900000 },
         { .reg = 0x00009888, .val = 0x1F85AA80 },
         { .reg = 0x00009888, .val = 0x2185AAAA },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x01834000 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0184C000 },
         { .reg = 0x00009888, .val = 0x0784C000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x1180C000 },
         { .reg = 0x00009888, .val = 0x1780C000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00000D24, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x4D801111 },
         { .reg = 0x00009888, .val = 0x3D800800 },
         { .reg = 0x00009888, .val = 0x4F801011 },
         { .reg = 0x00009888, .val = 0x43800443 },
         { .reg = 0x00009888, .val = 0x51801111 },
         { .reg = 0x00009888, .val = 0x45800422 },
         { .reg = 0x00009888, .val = 0x53801111 },
         { .reg = 0x00009888, .val = 0x47800C60 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x3F800422 },
         { .reg = 0x00009888, .val = 0x41800021 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__render_pipe_profile__avg_gpu_core_frequency__max,bdw__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,bdw__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,bdw__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,bdw__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,bdw__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,bdw__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,bdw__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,bdw__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 144, NULL,bdw__render_pipe_profile__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,bdw__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,bdw__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, bdw__render_pipe_profile__slm_bytes_read__max,bdw__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, bdw__render_pipe_profile__slm_bytes_written__max,bdw__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,bdw__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,bdw__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, bdw__render_pipe_profile__l3_shader_throughput__max,bdw__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,bdw__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 216, NULL,bdw__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 220, NULL,bdw__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 224, NULL,bdw__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 228, NULL,bdw__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 232, NULL,bdw__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 236, NULL,bdw__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 240, NULL,bdw__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 244, NULL,bdw__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 248, NULL,bdw__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 252, NULL,bdw__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 256, NULL,bdw__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 260, NULL,bdw__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 264, NULL,bdw__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 268, NULL,bdw__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 272, NULL,bdw__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 276, NULL,bdw__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Memory Reads Distribution metric set";
   query->symbol_name = "MemoryReads";
   query->guid = "2b255d48-2117-4fef-a8f7-f151e1d25a2c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x198B0343 },
         { .reg = 0x00009888, .val = 0x13845800 },
         { .reg = 0x00009888, .val = 0x15840018 },
         { .reg = 0x00009888, .val = 0x3580001A },
         { .reg = 0x00009888, .val = 0x038B6300 },
         { .reg = 0x00009888, .val = 0x058B6B62 },
         { .reg = 0x00009888, .val = 0x078B006A },
         { .reg = 0x00009888, .val = 0x118B0000 },
         { .reg = 0x00009888, .val = 0x238B0000 },
         { .reg = 0x00009888, .val = 0x258B0000 },
         { .reg = 0x00009888, .val = 0x1F85A080 },
         { .reg = 0x00009888, .val = 0x2185AAAA },
         { .reg = 0x00009888, .val = 0x2385000A },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x01840018 },
         { .reg = 0x00009888, .val = 0x07844C80 },
         { .reg = 0x00009888, .val = 0x09840D9A },
         { .reg = 0x00009888, .val = 0x0B840E9C },
         { .reg = 0x00009888, .val = 0x0D840F9E },
         { .reg = 0x00009888, .val = 0x0F840010 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x03848000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x2F8000E5 },
         { .reg = 0x00009888, .val = 0x138080E3 },
         { .reg = 0x00009888, .val = 0x1580C0E1 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x11804000 },
         { .reg = 0x00009888, .val = 0x1780C000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F804000 },
         { .reg = 0x00000D24, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3D800800 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x43800842 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45800842 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47801042 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x3F800084 },
         { .reg = 0x00009888, .val = 0x41800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__memory_reads__avg_gpu_core_frequency__max,bdw__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,bdw__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,bdw__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,bdw__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,bdw__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,bdw__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,bdw__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,bdw__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,bdw__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,bdw__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, bdw__memory_reads__slm_bytes_read__max,bdw__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, bdw__memory_reads__slm_bytes_written__max,bdw__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,bdw__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,bdw__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,bdw__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, bdw__memory_reads__l3_shader_throughput__max,bdw__memory_reads__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 95, 208, NULL,bdw__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 216, NULL,bdw__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 224, NULL,bdw__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 232, NULL,bdw__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 240, NULL,bdw__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 248, NULL,bdw__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 256, NULL,bdw__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 264, NULL,bdw__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 272, NULL,bdw__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 280, NULL,bdw__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 288, NULL,bdw__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 296, NULL,bdw__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 304, NULL,bdw__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 312, NULL,bdw__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 320, NULL,bdw__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metric set";
   query->symbol_name = "MemoryWrites";
   query->guid = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x198B0343 },
         { .reg = 0x00009888, .val = 0x13845400 },
         { .reg = 0x00009888, .val = 0x3580001A },
         { .reg = 0x00009888, .val = 0x3D800805 },
         { .reg = 0x00009888, .val = 0x038B6300 },
         { .reg = 0x00009888, .val = 0x058B6B62 },
         { .reg = 0x00009888, .val = 0x078B006A },
         { .reg = 0x00009888, .val = 0x118B0000 },
         { .reg = 0x00009888, .val = 0x238B0000 },
         { .reg = 0x00009888, .val = 0x258B0000 },
         { .reg = 0x00009888, .val = 0x1F85A080 },
         { .reg = 0x00009888, .val = 0x2185AAAA },
         { .reg = 0x00009888, .val = 0x23850002 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x07844880 },
         { .reg = 0x00009888, .val = 0x09840992 },
         { .reg = 0x00009888, .val = 0x0B840A94 },
         { .reg = 0x00009888, .val = 0x0D840B96 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x03848000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x2D800147 },
         { .reg = 0x00009888, .val = 0x2F8000E5 },
         { .reg = 0x00009888, .val = 0x138080E3 },
         { .reg = 0x00009888, .val = 0x1580C0E1 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x11804000 },
         { .reg = 0x00009888, .val = 0x1780C000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F800000 },
         { .reg = 0x00000D24, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x43800842 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45800842 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47801082 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x3F800084 },
         { .reg = 0x00009888, .val = 0x41800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__memory_writes__avg_gpu_core_frequency__max,bdw__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,bdw__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,bdw__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,bdw__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,bdw__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,bdw__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,bdw__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,bdw__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,bdw__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,bdw__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, bdw__memory_writes__slm_bytes_read__max,bdw__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, bdw__memory_writes__slm_bytes_written__max,bdw__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,bdw__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,bdw__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, bdw__memory_writes__l3_shader_throughput__max,bdw__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,bdw__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,bdw__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,bdw__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,bdw__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,bdw__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,bdw__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,bdw__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,bdw__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,bdw__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,bdw__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,bdw__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,bdw__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,bdw__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,bdw__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,bdw__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended metric set";
   query->symbol_name = "ComputeExtended";
   query->guid = "e99ccaca-821c-4df9-97a7-96bdb7204e43";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->sys_vars.subslice_mask & 0x01) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x143D0160 },
            { .reg = 0x00009888, .val = 0x163D2800 },
            { .reg = 0x00009888, .val = 0x183D0120 },
            { .reg = 0x00009888, .val = 0x105800E0 },
            { .reg = 0x00009888, .val = 0x005CC000 },
            { .reg = 0x00009888, .val = 0x065C8000 },
            { .reg = 0x00009888, .val = 0x085CC000 },
            { .reg = 0x00009888, .val = 0x0A5CC000 },
            { .reg = 0x00009888, .val = 0x0C5CC000 },
            { .reg = 0x00009888, .val = 0x0E5CC000 },
            { .reg = 0x00009888, .val = 0x025CC000 },
            { .reg = 0x00009888, .val = 0x045CC000 },
            { .reg = 0x00009888, .val = 0x003D0011 },
            { .reg = 0x00009888, .val = 0x063D0900 },
            { .reg = 0x00009888, .val = 0x083D0A13 },
            { .reg = 0x00009888, .val = 0x0A3D0B15 },
            { .reg = 0x00009888, .val = 0x0C3D2317 },
            { .reg = 0x00009888, .val = 0x043D21B7 },
            { .reg = 0x00009888, .val = 0x103D0000 },
            { .reg = 0x00009888, .val = 0x0E3D0000 },
            { .reg = 0x00009888, .val = 0x1A3D0000 },
            { .reg = 0x00009888, .val = 0x0E5825C1 },
            { .reg = 0x00009888, .val = 0x00586100 },
            { .reg = 0x00009888, .val = 0x0258204C },
            { .reg = 0x00009888, .val = 0x06588000 },
            { .reg = 0x00009888, .val = 0x0858C000 },
            { .reg = 0x00009888, .val = 0x0A58C000 },
            { .reg = 0x00009888, .val = 0x0C58C000 },
            { .reg = 0x00009888, .val = 0x0458C000 },
            { .reg = 0x00009888, .val = 0x005B4000 },
            { .reg = 0x00009888, .val = 0x0E5B4000 },
            { .reg = 0x00009888, .val = 0x185B5400 },
            { .reg = 0x00009888, .val = 0x1A5B0155 },
            { .reg = 0x00009888, .val = 0x025B4000 },
            { .reg = 0x00009888, .val = 0x045B4000 },
            { .reg = 0x00009888, .val = 0x065B4000 },
            { .reg = 0x00009888, .val = 0x085B4000 },
            { .reg = 0x00009888, .val = 0x0A5B4000 },
            { .reg = 0x00009888, .val = 0x0C1FA800 },
            { .reg = 0x00009888, .val = 0x0E1FAA2A },
            { .reg = 0x00009888, .val = 0x101F02AA },
            { .reg = 0x00009888, .val = 0x00384000 },
            { .reg = 0x00009888, .val = 0x0E384000 },
            { .reg = 0x00009888, .val = 0x16384000 },
            { .reg = 0x00009888, .val = 0x18381555 },
            { .reg = 0x00009888, .val = 0x02384000 },
            { .reg = 0x00009888, .val = 0x04384000 },
            { .reg = 0x00009888, .val = 0x06384000 },
            { .reg = 0x00009888, .val = 0x08384000 },
            { .reg = 0x00009888, .val = 0x0A384000 },
            { .reg = 0x00009888, .val = 0x0039A000 },
            { .reg = 0x00009888, .val = 0x06398000 },
            { .reg = 0x00009888, .val = 0x0839A000 },
            { .reg = 0x00009888, .val = 0x0A39A000 },
            { .reg = 0x00009888, .val = 0x0C39A000 },
            { .reg = 0x00009888, .val = 0x0E39A000 },
            { .reg = 0x00009888, .val = 0x0239A000 },
            { .reg = 0x00009888, .val = 0x0439A000 },
            { .reg = 0x00009888, .val = 0x018A8000 },
            { .reg = 0x00009888, .val = 0x0F8A8000 },
            { .reg = 0x00009888, .val = 0x198A8000 },
            { .reg = 0x00009888, .val = 0x1B8AAAA0 },
            { .reg = 0x00009888, .val = 0x1D8A0002 },
            { .reg = 0x00009888, .val = 0x038A8000 },
            { .reg = 0x00009888, .val = 0x058A8000 },
            { .reg = 0x00009888, .val = 0x078A8000 },
            { .reg = 0x00009888, .val = 0x098A8000 },
            { .reg = 0x00009888, .val = 0x0B8A8000 },
            { .reg = 0x00009888, .val = 0x238B2AA0 },
            { .reg = 0x00009888, .val = 0x258B5551 },
            { .reg = 0x00009888, .val = 0x278B0015 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x2185AAA2 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830155 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0B834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x0584C000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x17808000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1B80C000 },
            { .reg = 0x00009888, .val = 0x1D80C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x1580C000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D800000 },
            { .reg = 0x00009888, .val = 0x3D800000 },
            { .reg = 0x00009888, .val = 0x4F800000 },
            { .reg = 0x00009888, .val = 0x43800000 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800000 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800420 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F800421 },
            { .reg = 0x00009888, .val = 0x41800000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->sys_vars.subslice_mask & 0x02) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x105C00E0 },
            { .reg = 0x00009888, .val = 0x145B0160 },
            { .reg = 0x00009888, .val = 0x165B2800 },
            { .reg = 0x00009888, .val = 0x185B0120 },
            { .reg = 0x00009888, .val = 0x0E5C25C1 },
            { .reg = 0x00009888, .val = 0x005C6100 },
            { .reg = 0x00009888, .val = 0x025C204C },
            { .reg = 0x00009888, .val = 0x065C8000 },
            { .reg = 0x00009888, .val = 0x085CC000 },
            { .reg = 0x00009888, .val = 0x0A5CC000 },
            { .reg = 0x00009888, .val = 0x0C5CC000 },
            { .reg = 0x00009888, .val = 0x045CC000 },
            { .reg = 0x00009888, .val = 0x005B0011 },
            { .reg = 0x00009888, .val = 0x065B0900 },
            { .reg = 0x00009888, .val = 0x085B0A13 },
            { .reg = 0x00009888, .val = 0x0A5B0B15 },
            { .reg = 0x00009888, .val = 0x0C5B2317 },
            { .reg = 0x00009888, .val = 0x045B21B7 },
            { .reg = 0x00009888, .val = 0x105B0000 },
            { .reg = 0x00009888, .val = 0x0E5B0000 },
            { .reg = 0x00009888, .val = 0x1A5B0000 },
            { .reg = 0x00009888, .val = 0x0C1FA800 },
            { .reg = 0x00009888, .val = 0x0E1FAA2A },
            { .reg = 0x00009888, .val = 0x101F02AA },
            { .reg = 0x00009888, .val = 0x00384000 },
            { .reg = 0x00009888, .val = 0x0E384000 },
            { .reg = 0x00009888, .val = 0x16384000 },
            { .reg = 0x00009888, .val = 0x18381555 },
            { .reg = 0x00009888, .val = 0x02384000 },
            { .reg = 0x00009888, .val = 0x04384000 },
            { .reg = 0x00009888, .val = 0x06384000 },
            { .reg = 0x00009888, .val = 0x08384000 },
            { .reg = 0x00009888, .val = 0x0A384000 },
            { .reg = 0x00009888, .val = 0x0039A000 },
            { .reg = 0x00009888, .val = 0x06398000 },
            { .reg = 0x00009888, .val = 0x0839A000 },
            { .reg = 0x00009888, .val = 0x0A39A000 },
            { .reg = 0x00009888, .val = 0x0C39A000 },
            { .reg = 0x00009888, .val = 0x0E39A000 },
            { .reg = 0x00009888, .val = 0x0239A000 },
            { .reg = 0x00009888, .val = 0x0439A000 },
            { .reg = 0x00009888, .val = 0x018A8000 },
            { .reg = 0x00009888, .val = 0x0F8A8000 },
            { .reg = 0x00009888, .val = 0x198A8000 },
            { .reg = 0x00009888, .val = 0x1B8AAAA0 },
            { .reg = 0x00009888, .val = 0x1D8A0002 },
            { .reg = 0x00009888, .val = 0x038A8000 },
            { .reg = 0x00009888, .val = 0x058A8000 },
            { .reg = 0x00009888, .val = 0x078A8000 },
            { .reg = 0x00009888, .val = 0x098A8000 },
            { .reg = 0x00009888, .val = 0x0B8A8000 },
            { .reg = 0x00009888, .val = 0x238B2AA0 },
            { .reg = 0x00009888, .val = 0x258B5551 },
            { .reg = 0x00009888, .val = 0x278B0015 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x2185AAA2 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830155 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0B834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x0584C000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x17808000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1B80C000 },
            { .reg = 0x00009888, .val = 0x1D80C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x1580C000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D800000 },
            { .reg = 0x00009888, .val = 0x3D800000 },
            { .reg = 0x00009888, .val = 0x4F800000 },
            { .reg = 0x00009888, .val = 0x43800000 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800000 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800420 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F800421 },
            { .reg = 0x00009888, .val = 0x41800000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->sys_vars.subslice_mask & 0x04) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x103800E0 },
            { .reg = 0x00009888, .val = 0x143A0160 },
            { .reg = 0x00009888, .val = 0x163A2800 },
            { .reg = 0x00009888, .val = 0x183A0120 },
            { .reg = 0x00009888, .val = 0x0C1FA800 },
            { .reg = 0x00009888, .val = 0x0E1FAA2A },
            { .reg = 0x00009888, .val = 0x101F02AA },
            { .reg = 0x00009888, .val = 0x0E38A5C1 },
            { .reg = 0x00009888, .val = 0x0038A100 },
            { .reg = 0x00009888, .val = 0x0238204C },
            { .reg = 0x00009888, .val = 0x16388000 },
            { .reg = 0x00009888, .val = 0x183802AA },
            { .reg = 0x00009888, .val = 0x04380000 },
            { .reg = 0x00009888, .val = 0x06380000 },
            { .reg = 0x00009888, .val = 0x08388000 },
            { .reg = 0x00009888, .val = 0x0A388000 },
            { .reg = 0x00009888, .val = 0x0039A000 },
            { .reg = 0x00009888, .val = 0x06398000 },
            { .reg = 0x00009888, .val = 0x0839A000 },
            { .reg = 0x00009888, .val = 0x0A39A000 },
            { .reg = 0x00009888, .val = 0x0C39A000 },
            { .reg = 0x00009888, .val = 0x0E39A000 },
            { .reg = 0x00009888, .val = 0x0239A000 },
            { .reg = 0x00009888, .val = 0x0439A000 },
            { .reg = 0x00009888, .val = 0x003A0011 },
            { .reg = 0x00009888, .val = 0x063A0900 },
            { .reg = 0x00009888, .val = 0x083A0A13 },
            { .reg = 0x00009888, .val = 0x0A3A0B15 },
            { .reg = 0x00009888, .val = 0x0C3A2317 },
            { .reg = 0x00009888, .val = 0x043A21B7 },
            { .reg = 0x00009888, .val = 0x103A0000 },
            { .reg = 0x00009888, .val = 0x0E3A0000 },
            { .reg = 0x00009888, .val = 0x1A3A0000 },
            { .reg = 0x00009888, .val = 0x018A8000 },
            { .reg = 0x00009888, .val = 0x0F8A8000 },
            { .reg = 0x00009888, .val = 0x198A8000 },
            { .reg = 0x00009888, .val = 0x1B8AAAA0 },
            { .reg = 0x00009888, .val = 0x1D8A0002 },
            { .reg = 0x00009888, .val = 0x038A8000 },
            { .reg = 0x00009888, .val = 0x058A8000 },
            { .reg = 0x00009888, .val = 0x078A8000 },
            { .reg = 0x00009888, .val = 0x098A8000 },
            { .reg = 0x00009888, .val = 0x0B8A8000 },
            { .reg = 0x00009888, .val = 0x238B2AA0 },
            { .reg = 0x00009888, .val = 0x258B5551 },
            { .reg = 0x00009888, .val = 0x278B0015 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x2185AAA2 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830155 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0B834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x0584C000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x17808000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1B80C000 },
            { .reg = 0x00009888, .val = 0x1D80C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x1580C000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D800000 },
            { .reg = 0x00009888, .val = 0x3D800000 },
            { .reg = 0x00009888, .val = 0x4F800000 },
            { .reg = 0x00009888, .val = 0x43800000 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800000 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800420 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F800421 },
            { .reg = 0x00009888, .val = 0x41800000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->sys_vars.subslice_mask & 0x08) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x14BD0160 },
            { .reg = 0x00009888, .val = 0x16BD2800 },
            { .reg = 0x00009888, .val = 0x18BD0120 },
            { .reg = 0x00009888, .val = 0x10D800E0 },
            { .reg = 0x00009888, .val = 0x00DCC000 },
            { .reg = 0x00009888, .val = 0x06DC8000 },
            { .reg = 0x00009888, .val = 0x08DCC000 },
            { .reg = 0x00009888, .val = 0x0ADCC000 },
            { .reg = 0x00009888, .val = 0x0CDCC000 },
            { .reg = 0x00009888, .val = 0x0EDCC000 },
            { .reg = 0x00009888, .val = 0x02DCC000 },
            { .reg = 0x00009888, .val = 0x04DCC000 },
            { .reg = 0x00009888, .val = 0x00BD0011 },
            { .reg = 0x00009888, .val = 0x06BD0900 },
            { .reg = 0x00009888, .val = 0x08BD0A13 },
            { .reg = 0x00009888, .val = 0x0ABD0B15 },
            { .reg = 0x00009888, .val = 0x0CBD2317 },
            { .reg = 0x00009888, .val = 0x04BD21B7 },
            { .reg = 0x00009888, .val = 0x10BD0000 },
            { .reg = 0x00009888, .val = 0x0EBD0000 },
            { .reg = 0x00009888, .val = 0x1ABD0000 },
            { .reg = 0x00009888, .val = 0x0ED825C1 },
            { .reg = 0x00009888, .val = 0x00D86100 },
            { .reg = 0x00009888, .val = 0x02D8204C },
            { .reg = 0x00009888, .val = 0x06D88000 },
            { .reg = 0x00009888, .val = 0x08D8C000 },
            { .reg = 0x00009888, .val = 0x0AD8C000 },
            { .reg = 0x00009888, .val = 0x0CD8C000 },
            { .reg = 0x00009888, .val = 0x04D8C000 },
            { .reg = 0x00009888, .val = 0x00DB4000 },
            { .reg = 0x00009888, .val = 0x0EDB4000 },
            { .reg = 0x00009888, .val = 0x18DB5400 },
            { .reg = 0x00009888, .val = 0x1ADB0155 },
            { .reg = 0x00009888, .val = 0x02DB4000 },
            { .reg = 0x00009888, .val = 0x04DB4000 },
            { .reg = 0x00009888, .val = 0x06DB4000 },
            { .reg = 0x00009888, .val = 0x08DB4000 },
            { .reg = 0x00009888, .val = 0x0ADB4000 },
            { .reg = 0x00009888, .val = 0x0C9FA800 },
            { .reg = 0x00009888, .val = 0x0E9FAA2A },
            { .reg = 0x00009888, .val = 0x109F02AA },
            { .reg = 0x00009888, .val = 0x00B84000 },
            { .reg = 0x00009888, .val = 0x0EB84000 },
            { .reg = 0x00009888, .val = 0x16B84000 },
            { .reg = 0x00009888, .val = 0x18B81555 },
            { .reg = 0x00009888, .val = 0x02B84000 },
            { .reg = 0x00009888, .val = 0x04B84000 },
            { .reg = 0x00009888, .val = 0x06B84000 },
            { .reg = 0x00009888, .val = 0x08B84000 },
            { .reg = 0x00009888, .val = 0x0AB84000 },
            { .reg = 0x00009888, .val = 0x00B9A000 },
            { .reg = 0x00009888, .val = 0x06B98000 },
            { .reg = 0x00009888, .val = 0x08B9A000 },
            { .reg = 0x00009888, .val = 0x0AB9A000 },
            { .reg = 0x00009888, .val = 0x0CB9A000 },
            { .reg = 0x00009888, .val = 0x0EB9A000 },
            { .reg = 0x00009888, .val = 0x02B9A000 },
            { .reg = 0x00009888, .val = 0x04B9A000 },
            { .reg = 0x00009888, .val = 0x01888000 },
            { .reg = 0x00009888, .val = 0x0D88F800 },
            { .reg = 0x00009888, .val = 0x0F88000F },
            { .reg = 0x00009888, .val = 0x03888000 },
            { .reg = 0x00009888, .val = 0x05888000 },
            { .reg = 0x00009888, .val = 0x07888000 },
            { .reg = 0x00009888, .val = 0x09888000 },
            { .reg = 0x00009888, .val = 0x0B888000 },
            { .reg = 0x00009888, .val = 0x238B5540 },
            { .reg = 0x00009888, .val = 0x258BAAA2 },
            { .reg = 0x00009888, .val = 0x278B002A },
            { .reg = 0x00009888, .val = 0x018C4000 },
            { .reg = 0x00009888, .val = 0x0F8C4000 },
            { .reg = 0x00009888, .val = 0x178C2000 },
            { .reg = 0x00009888, .val = 0x198C5500 },
            { .reg = 0x00009888, .val = 0x1B8C0015 },
            { .reg = 0x00009888, .val = 0x038C4000 },
            { .reg = 0x00009888, .val = 0x058C4000 },
            { .reg = 0x00009888, .val = 0x078C4000 },
            { .reg = 0x00009888, .val = 0x098C4000 },
            { .reg = 0x00009888, .val = 0x0B8C4000 },
            { .reg = 0x00009888, .val = 0x018DA000 },
            { .reg = 0x00009888, .val = 0x078D8000 },
            { .reg = 0x00009888, .val = 0x098DA000 },
            { .reg = 0x00009888, .val = 0x0B8DA000 },
            { .reg = 0x00009888, .val = 0x0D8DA000 },
            { .reg = 0x00009888, .val = 0x0F8DA000 },
            { .reg = 0x00009888, .val = 0x038DA000 },
            { .reg = 0x00009888, .val = 0x058DA000 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x2185AAA2 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830155 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0B834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x0584C000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x17808000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1B80C000 },
            { .reg = 0x00009888, .val = 0x1D80C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x1580C000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D800000 },
            { .reg = 0x00009888, .val = 0x3D800000 },
            { .reg = 0x00009888, .val = 0x4F800000 },
            { .reg = 0x00009888, .val = 0x43800000 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800000 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800420 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F800421 },
            { .reg = 0x00009888, .val = 0x41800000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x10DC00E0 },
            { .reg = 0x00009888, .val = 0x14DB0160 },
            { .reg = 0x00009888, .val = 0x16DB2800 },
            { .reg = 0x00009888, .val = 0x18DB0120 },
            { .reg = 0x00009888, .val = 0x0EDC25C1 },
            { .reg = 0x00009888, .val = 0x00DC6100 },
            { .reg = 0x00009888, .val = 0x02DC204C },
            { .reg = 0x00009888, .val = 0x06DC8000 },
            { .reg = 0x00009888, .val = 0x08DCC000 },
            { .reg = 0x00009888, .val = 0x0ADCC000 },
            { .reg = 0x00009888, .val = 0x0CDCC000 },
            { .reg = 0x00009888, .val = 0x04DCC000 },
            { .reg = 0x00009888, .val = 0x00DB0011 },
            { .reg = 0x00009888, .val = 0x06DB0900 },
            { .reg = 0x00009888, .val = 0x08DB0A13 },
            { .reg = 0x00009888, .val = 0x0ADB0B15 },
            { .reg = 0x00009888, .val = 0x0CDB2317 },
            { .reg = 0x00009888, .val = 0x04DB21B7 },
            { .reg = 0x00009888, .val = 0x10DB0000 },
            { .reg = 0x00009888, .val = 0x0EDB0000 },
            { .reg = 0x00009888, .val = 0x1ADB0000 },
            { .reg = 0x00009888, .val = 0x0C9FA800 },
            { .reg = 0x00009888, .val = 0x0E9FAA2A },
            { .reg = 0x00009888, .val = 0x109F02AA },
            { .reg = 0x00009888, .val = 0x00B84000 },
            { .reg = 0x00009888, .val = 0x0EB84000 },
            { .reg = 0x00009888, .val = 0x16B84000 },
            { .reg = 0x00009888, .val = 0x18B81555 },
            { .reg = 0x00009888, .val = 0x02B84000 },
            { .reg = 0x00009888, .val = 0x04B84000 },
            { .reg = 0x00009888, .val = 0x06B84000 },
            { .reg = 0x00009888, .val = 0x08B84000 },
            { .reg = 0x00009888, .val = 0x0AB84000 },
            { .reg = 0x00009888, .val = 0x00B9A000 },
            { .reg = 0x00009888, .val = 0x06B98000 },
            { .reg = 0x00009888, .val = 0x08B9A000 },
            { .reg = 0x00009888, .val = 0x0AB9A000 },
            { .reg = 0x00009888, .val = 0x0CB9A000 },
            { .reg = 0x00009888, .val = 0x0EB9A000 },
            { .reg = 0x00009888, .val = 0x02B9A000 },
            { .reg = 0x00009888, .val = 0x04B9A000 },
            { .reg = 0x00009888, .val = 0x01888000 },
            { .reg = 0x00009888, .val = 0x0D88F800 },
            { .reg = 0x00009888, .val = 0x0F88000F },
            { .reg = 0x00009888, .val = 0x03888000 },
            { .reg = 0x00009888, .val = 0x05888000 },
            { .reg = 0x00009888, .val = 0x07888000 },
            { .reg = 0x00009888, .val = 0x09888000 },
            { .reg = 0x00009888, .val = 0x0B888000 },
            { .reg = 0x00009888, .val = 0x238B5540 },
            { .reg = 0x00009888, .val = 0x258BAAA2 },
            { .reg = 0x00009888, .val = 0x278B002A },
            { .reg = 0x00009888, .val = 0x018C4000 },
            { .reg = 0x00009888, .val = 0x0F8C4000 },
            { .reg = 0x00009888, .val = 0x178C2000 },
            { .reg = 0x00009888, .val = 0x198C5500 },
            { .reg = 0x00009888, .val = 0x1B8C0015 },
            { .reg = 0x00009888, .val = 0x038C4000 },
            { .reg = 0x00009888, .val = 0x058C4000 },
            { .reg = 0x00009888, .val = 0x078C4000 },
            { .reg = 0x00009888, .val = 0x098C4000 },
            { .reg = 0x00009888, .val = 0x0B8C4000 },
            { .reg = 0x00009888, .val = 0x018DA000 },
            { .reg = 0x00009888, .val = 0x078D8000 },
            { .reg = 0x00009888, .val = 0x098DA000 },
            { .reg = 0x00009888, .val = 0x0B8DA000 },
            { .reg = 0x00009888, .val = 0x0D8DA000 },
            { .reg = 0x00009888, .val = 0x0F8DA000 },
            { .reg = 0x00009888, .val = 0x038DA000 },
            { .reg = 0x00009888, .val = 0x058DA000 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x2185AAA2 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830155 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0B834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x0584C000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x17808000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1B80C000 },
            { .reg = 0x00009888, .val = 0x1D80C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x1580C000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D800000 },
            { .reg = 0x00009888, .val = 0x3D800000 },
            { .reg = 0x00009888, .val = 0x4F800000 },
            { .reg = 0x00009888, .val = 0x43800000 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800000 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800420 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F800421 },
            { .reg = 0x00009888, .val = 0x41800000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x10B800E0 },
            { .reg = 0x00009888, .val = 0x14BA0160 },
            { .reg = 0x00009888, .val = 0x16BA2800 },
            { .reg = 0x00009888, .val = 0x18BA0120 },
            { .reg = 0x00009888, .val = 0x0C9FA800 },
            { .reg = 0x00009888, .val = 0x0E9FAA2A },
            { .reg = 0x00009888, .val = 0x109F02AA },
            { .reg = 0x00009888, .val = 0x0EB8A5C1 },
            { .reg = 0x00009888, .val = 0x00B8A100 },
            { .reg = 0x00009888, .val = 0x02B8204C },
            { .reg = 0x00009888, .val = 0x16B88000 },
            { .reg = 0x00009888, .val = 0x18B802AA },
            { .reg = 0x00009888, .val = 0x04B80000 },
            { .reg = 0x00009888, .val = 0x06B80000 },
            { .reg = 0x00009888, .val = 0x08B88000 },
            { .reg = 0x00009888, .val = 0x0AB88000 },
            { .reg = 0x00009888, .val = 0x00B9A000 },
            { .reg = 0x00009888, .val = 0x06B98000 },
            { .reg = 0x00009888, .val = 0x08B9A000 },
            { .reg = 0x00009888, .val = 0x0AB9A000 },
            { .reg = 0x00009888, .val = 0x0CB9A000 },
            { .reg = 0x00009888, .val = 0x0EB9A000 },
            { .reg = 0x00009888, .val = 0x02B9A000 },
            { .reg = 0x00009888, .val = 0x04B9A000 },
            { .reg = 0x00009888, .val = 0x00BA0011 },
            { .reg = 0x00009888, .val = 0x06BA0900 },
            { .reg = 0x00009888, .val = 0x08BA0A13 },
            { .reg = 0x00009888, .val = 0x0ABA0B15 },
            { .reg = 0x00009888, .val = 0x0CBA2317 },
            { .reg = 0x00009888, .val = 0x04BA21B7 },
            { .reg = 0x00009888, .val = 0x10BA0000 },
            { .reg = 0x00009888, .val = 0x0EBA0000 },
            { .reg = 0x00009888, .val = 0x1ABA0000 },
            { .reg = 0x00009888, .val = 0x01888000 },
            { .reg = 0x00009888, .val = 0x0D88F800 },
            { .reg = 0x00009888, .val = 0x0F88000F },
            { .reg = 0x00009888, .val = 0x03888000 },
            { .reg = 0x00009888, .val = 0x05888000 },
            { .reg = 0x00009888, .val = 0x07888000 },
            { .reg = 0x00009888, .val = 0x09888000 },
            { .reg = 0x00009888, .val = 0x0B888000 },
            { .reg = 0x00009888, .val = 0x238B5540 },
            { .reg = 0x00009888, .val = 0x258BAAA2 },
            { .reg = 0x00009888, .val = 0x278B002A },
            { .reg = 0x00009888, .val = 0x018C4000 },
            { .reg = 0x00009888, .val = 0x0F8C4000 },
            { .reg = 0x00009888, .val = 0x178C2000 },
            { .reg = 0x00009888, .val = 0x198C5500 },
            { .reg = 0x00009888, .val = 0x1B8C0015 },
            { .reg = 0x00009888, .val = 0x038C4000 },
            { .reg = 0x00009888, .val = 0x058C4000 },
            { .reg = 0x00009888, .val = 0x078C4000 },
            { .reg = 0x00009888, .val = 0x098C4000 },
            { .reg = 0x00009888, .val = 0x0B8C4000 },
            { .reg = 0x00009888, .val = 0x018DA000 },
            { .reg = 0x00009888, .val = 0x078D8000 },
            { .reg = 0x00009888, .val = 0x098DA000 },
            { .reg = 0x00009888, .val = 0x0B8DA000 },
            { .reg = 0x00009888, .val = 0x0D8DA000 },
            { .reg = 0x00009888, .val = 0x0F8DA000 },
            { .reg = 0x00009888, .val = 0x038DA000 },
            { .reg = 0x00009888, .val = 0x058DA000 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x2185AAA2 },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830155 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0B834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x07848000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x0584C000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x17808000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1B80C000 },
            { .reg = 0x00009888, .val = 0x1D80C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x1580C000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D800000 },
            { .reg = 0x00009888, .val = 0x3D800000 },
            { .reg = 0x00009888, .val = 0x4F800000 },
            { .reg = 0x00009888, .val = 0x43800000 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800000 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800420 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F800421 },
            { .reg = 0x00009888, .val = 0x41800000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__compute_extended__avg_gpu_core_frequency__max,bdw__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,bdw__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,bdw__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,bdw__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,bdw__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,bdw__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,bdw__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, bdw__compute_extended__eu_avg_ipc_rate__max,bdw__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,bdw__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,bdw__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,bdw__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,bdw__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, bdw__compute_extended__slm_bytes_read__max,bdw__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, bdw__compute_extended__slm_bytes_written__max,bdw__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,bdw__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,bdw__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, bdw__compute_extended__l3_shader_throughput__max,bdw__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,bdw__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,bdw__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,bdw__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,bdw__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,bdw__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,bdw__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,bdw__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,bdw__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,bdw__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,bdw__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,bdw__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,bdw__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,bdw__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,bdw__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 191, 232, NULL,bdw__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 192, 236, NULL,bdw__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 193, 240, NULL,bdw__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 194, 244, NULL,bdw__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 195, 248, NULL,bdw__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 58);

   query->name = "Compute Metrics L3 Cache metric set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "27a364dc-8225-4ecb-b607-d6f1925598d9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x143F00B3 },
         { .reg = 0x00009888, .val = 0x14BF00B3 },
         { .reg = 0x00009888, .val = 0x138303C0 },
         { .reg = 0x00009888, .val = 0x3B800060 },
         { .reg = 0x00009888, .val = 0x3D800805 },
         { .reg = 0x00009888, .val = 0x003F0029 },
         { .reg = 0x00009888, .val = 0x063F1400 },
         { .reg = 0x00009888, .val = 0x083F1225 },
         { .reg = 0x00009888, .val = 0x0E3F1327 },
         { .reg = 0x00009888, .val = 0x103F0000 },
         { .reg = 0x00009888, .val = 0x005A4000 },
         { .reg = 0x00009888, .val = 0x065A8000 },
         { .reg = 0x00009888, .val = 0x085AC000 },
         { .reg = 0x00009888, .val = 0x0E5AC000 },
         { .reg = 0x00009888, .val = 0x001D4000 },
         { .reg = 0x00009888, .val = 0x061D8000 },
         { .reg = 0x00009888, .val = 0x081DC000 },
         { .reg = 0x00009888, .val = 0x0E1DC000 },
         { .reg = 0x00009888, .val = 0x0C1F0800 },
         { .reg = 0x00009888, .val = 0x0E1F2A00 },
         { .reg = 0x00009888, .val = 0x101F0280 },
         { .reg = 0x00009888, .val = 0x00391000 },
         { .reg = 0x00009888, .val = 0x06394000 },
         { .reg = 0x00009888, .val = 0x08395000 },
         { .reg = 0x00009888, .val = 0x0E395000 },
         { .reg = 0x00009888, .val = 0x0ABF1429 },
         { .reg = 0x00009888, .val = 0x0CBF1225 },
         { .reg = 0x00009888, .val = 0x00BF1380 },
         { .reg = 0x00009888, .val = 0x02BF0026 },
         { .reg = 0x00009888, .val = 0x10BF0000 },
         { .reg = 0x00009888, .val = 0x0ADAC000 },
         { .reg = 0x00009888, .val = 0x0CDAC000 },
         { .reg = 0x00009888, .val = 0x00DA8000 },
         { .reg = 0x00009888, .val = 0x02DA4000 },
         { .reg = 0x00009888, .val = 0x0A9DC000 },
         { .reg = 0x00009888, .val = 0x0C9DC000 },
         { .reg = 0x00009888, .val = 0x009D8000 },
         { .reg = 0x00009888, .val = 0x029D4000 },
         { .reg = 0x00009888, .val = 0x0E9F8000 },
         { .reg = 0x00009888, .val = 0x109F002A },
         { .reg = 0x00009888, .val = 0x0C9FA000 },
         { .reg = 0x00009888, .val = 0x0AB95000 },
         { .reg = 0x00009888, .val = 0x0CB95000 },
         { .reg = 0x00009888, .val = 0x00B94000 },
         { .reg = 0x00009888, .val = 0x02B91000 },
         { .reg = 0x00009888, .val = 0x0D88C000 },
         { .reg = 0x00009888, .val = 0x0F880003 },
         { .reg = 0x00009888, .val = 0x03888000 },
         { .reg = 0x00009888, .val = 0x05888000 },
         { .reg = 0x00009888, .val = 0x018A8000 },
         { .reg = 0x00009888, .val = 0x0F8A8000 },
         { .reg = 0x00009888, .val = 0x198A8000 },
         { .reg = 0x00009888, .val = 0x1B8A8020 },
         { .reg = 0x00009888, .val = 0x1D8A0002 },
         { .reg = 0x00009888, .val = 0x238B0520 },
         { .reg = 0x00009888, .val = 0x258BA950 },
         { .reg = 0x00009888, .val = 0x278B0016 },
         { .reg = 0x00009888, .val = 0x198C5400 },
         { .reg = 0x00009888, .val = 0x1B8C0001 },
         { .reg = 0x00009888, .val = 0x038C4000 },
         { .reg = 0x00009888, .val = 0x058C4000 },
         { .reg = 0x00009888, .val = 0x0B8DA000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x018D8000 },
         { .reg = 0x00009888, .val = 0x038D2000 },
         { .reg = 0x00009888, .val = 0x1F85AA80 },
         { .reg = 0x00009888, .val = 0x2185AAA0 },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x03835180 },
         { .reg = 0x00009888, .val = 0x05834022 },
         { .reg = 0x00009888, .val = 0x11830000 },
         { .reg = 0x00009888, .val = 0x01834000 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x07830000 },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x0184C000 },
         { .reg = 0x00009888, .val = 0x07848000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x05844000 },
         { .reg = 0x00009888, .val = 0x1B80C137 },
         { .reg = 0x00009888, .val = 0x1D80C147 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x1180C000 },
         { .reg = 0x00009888, .val = 0x17808000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x15804000 },
         { .reg = 0x00000D24, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x4D801000 },
         { .reg = 0x00009888, .val = 0x4F800111 },
         { .reg = 0x00009888, .val = 0x43800842 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45800000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47800840 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x3F800800 },
         { .reg = 0x00009888, .val = 0x418014A2 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__compute_l3_cache__avg_gpu_core_frequency__max,bdw__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,bdw__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,bdw__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, bdw__compute_l3_cache__eu_avg_ipc_rate__max,bdw__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,bdw__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,bdw__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,bdw__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,bdw__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,bdw__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,bdw__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,bdw__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,bdw__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,bdw__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,bdw__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,bdw__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,bdw__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,bdw__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,bdw__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 200, NULL,bdw__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 208, NULL,bdw__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, bdw__compute_l3_cache__slm_bytes_read__max,bdw__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, bdw__compute_l3_cache__slm_bytes_written__max,bdw__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,bdw__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,bdw__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 248, NULL,bdw__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,bdw__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 146, 264, bdw__compute_l3_cache__l3_shader_throughput__max,bdw__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 272, bdw__compute_l3_cache__l3_total_throughput__max,bdw__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,bdw__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 288, NULL,bdw__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 296, NULL,bdw__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 304, NULL,bdw__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 312, NULL,bdw__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x02) {
         intel_perf_query_add_counter_uint64(query, 210, 320, NULL,bdw__compute_l3_cache__l3_bank10_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x02) {
         intel_perf_query_add_counter_uint64(query, 211, 328, NULL,bdw__compute_l3_cache__l3_bank11_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x02) {
         intel_perf_query_add_counter_uint64(query, 212, 336, NULL,bdw__compute_l3_cache__l3_bank12_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x02) {
         intel_perf_query_add_counter_uint64(query, 213, 344, NULL,bdw__compute_l3_cache__l3_bank13_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 352, NULL,bdw__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 360, NULL,bdw__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      if (perf->sys_vars.slice_mask & 0x02) {
         intel_perf_query_add_counter_uint64(query, 216, 368, NULL,bdw__compute_l3_cache__l3_bank10_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x02) {
         intel_perf_query_add_counter_uint64(query, 217, 376, NULL,bdw__compute_l3_cache__l3_bank10_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 384, bdw__compute_l3_cache__gti_l3_throughput__max,bdw__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 392, bdw__compute_l3_cache__gti_read_throughput__max,bdw__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 400, bdw__compute_l3_cache__gti_write_throughput__max,bdw__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_data_port_reads_coalescing_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 35);

   query->name = "Data Port Reads Coalescing metric set";
   query->symbol_name = "DataPortReadsCoalescing";
   query->guid = "857fc630-2f09-4804-85f1-084adfadd5ab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->sys_vars.subslice_mask & 0x01) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x103D0005 },
            { .reg = 0x00009888, .val = 0x163D240B },
            { .reg = 0x00009888, .val = 0x1058022F },
            { .reg = 0x00009888, .val = 0x185B5520 },
            { .reg = 0x00009888, .val = 0x198B0003 },
            { .reg = 0x00009888, .val = 0x005CC000 },
            { .reg = 0x00009888, .val = 0x065CC000 },
            { .reg = 0x00009888, .val = 0x085CC000 },
            { .reg = 0x00009888, .val = 0x0A5CC000 },
            { .reg = 0x00009888, .val = 0x0C5CC000 },
            { .reg = 0x00009888, .val = 0x0E5CC000 },
            { .reg = 0x00009888, .val = 0x025C4000 },
            { .reg = 0x00009888, .val = 0x045C8000 },
            { .reg = 0x00009888, .val = 0x003D0000 },
            { .reg = 0x00009888, .val = 0x063D00B0 },
            { .reg = 0x00009888, .val = 0x083D0182 },
            { .reg = 0x00009888, .val = 0x0A3D10A0 },
            { .reg = 0x00009888, .val = 0x0C3D11A2 },
            { .reg = 0x00009888, .val = 0x0E3D0000 },
            { .reg = 0x00009888, .val = 0x183D0000 },
            { .reg = 0x00009888, .val = 0x1A3D0000 },
            { .reg = 0x00009888, .val = 0x0E582242 },
            { .reg = 0x00009888, .val = 0x00586700 },
            { .reg = 0x00009888, .val = 0x0258004F },
            { .reg = 0x00009888, .val = 0x0658C000 },
            { .reg = 0x00009888, .val = 0x0858C000 },
            { .reg = 0x00009888, .val = 0x0A58C000 },
            { .reg = 0x00009888, .val = 0x0C58C000 },
            { .reg = 0x00009888, .val = 0x045B6300 },
            { .reg = 0x00009888, .val = 0x105B0000 },
            { .reg = 0x00009888, .val = 0x005B4000 },
            { .reg = 0x00009888, .val = 0x0E5B4000 },
            { .reg = 0x00009888, .val = 0x1A5B0155 },
            { .reg = 0x00009888, .val = 0x025B4000 },
            { .reg = 0x00009888, .val = 0x0A5B0000 },
            { .reg = 0x00009888, .val = 0x0C5B4000 },
            { .reg = 0x00009888, .val = 0x0C1FA800 },
            { .reg = 0x00009888, .val = 0x0E1FAAA0 },
            { .reg = 0x00009888, .val = 0x101F02AA },
            { .reg = 0x00009888, .val = 0x00384000 },
            { .reg = 0x00009888, .val = 0x0E384000 },
            { .reg = 0x00009888, .val = 0x16384000 },
            { .reg = 0x00009888, .val = 0x18381555 },
            { .reg = 0x00009888, .val = 0x02384000 },
            { .reg = 0x00009888, .val = 0x04384000 },
            { .reg = 0x00009888, .val = 0x0A384000 },
            { .reg = 0x00009888, .val = 0x0C384000 },
            { .reg = 0x00009888, .val = 0x0039A000 },
            { .reg = 0x00009888, .val = 0x0639A000 },
            { .reg = 0x00009888, .val = 0x0839A000 },
            { .reg = 0x00009888, .val = 0x0A39A000 },
            { .reg = 0x00009888, .val = 0x0C39A000 },
            { .reg = 0x00009888, .val = 0x0E39A000 },
            { .reg = 0x00009888, .val = 0x02392000 },
            { .reg = 0x00009888, .val = 0x04398000 },
            { .reg = 0x00009888, .val = 0x018A8000 },
            { .reg = 0x00009888, .val = 0x0F8A8000 },
            { .reg = 0x00009888, .val = 0x198A8000 },
            { .reg = 0x00009888, .val = 0x1B8AAAA0 },
            { .reg = 0x00009888, .val = 0x1D8A0002 },
            { .reg = 0x00009888, .val = 0x038A8000 },
            { .reg = 0x00009888, .val = 0x058A8000 },
            { .reg = 0x00009888, .val = 0x0B8A8000 },
            { .reg = 0x00009888, .val = 0x0D8A8000 },
            { .reg = 0x00009888, .val = 0x038B6300 },
            { .reg = 0x00009888, .val = 0x058B0062 },
            { .reg = 0x00009888, .val = 0x118B0000 },
            { .reg = 0x00009888, .val = 0x238B02A0 },
            { .reg = 0x00009888, .val = 0x258B5555 },
            { .reg = 0x00009888, .val = 0x278B0015 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x2185AAAA },
            { .reg = 0x00009888, .val = 0x2385002A },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830155 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0B834000 },
            { .reg = 0x00009888, .val = 0x0D834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x0784C000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0D84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x0584C000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x1780C000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1B80C000 },
            { .reg = 0x00009888, .val = 0x1D80C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x1580C000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D801000 },
            { .reg = 0x00009888, .val = 0x3D800000 },
            { .reg = 0x00009888, .val = 0x4F800001 },
            { .reg = 0x00009888, .val = 0x43800000 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800000 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800420 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x3F800421 },
            { .reg = 0x00009888, .val = 0x41800041 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0xBA98BA98 },
         { .reg = 0x00002748, .val = 0xBA98BA98 },
         { .reg = 0x00002744, .val = 0x00003377 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFF2 },
         { .reg = 0x00002774, .val = 0x00007FF0 },
         { .reg = 0x00002778, .val = 0x0007FFE2 },
         { .reg = 0x0000277C, .val = 0x00007FF0 },
         { .reg = 0x00002780, .val = 0x0007FFC2 },
         { .reg = 0x00002784, .val = 0x00007FF0 },
         { .reg = 0x00002788, .val = 0x0007FF82 },
         { .reg = 0x0000278C, .val = 0x00007FF0 },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000BFEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000BFDF },
         { .reg = 0x000027A0, .val = 0x0007FFFA },
         { .reg = 0x000027A4, .val = 0x0000BFBF },
         { .reg = 0x000027A8, .val = 0x0007FFFA },
         { .reg = 0x000027AC, .val = 0x0000BF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__data_port_reads_coalescing__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__data_port_reads_coalescing__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__data_port_reads_coalescing__avg_gpu_core_frequency__max,bdw__data_port_reads_coalescing__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,bdw__data_port_reads_coalescing__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,bdw__data_port_reads_coalescing__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,bdw__data_port_reads_coalescing__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,bdw__data_port_reads_coalescing__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,bdw__data_port_reads_coalescing__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,bdw__data_port_reads_coalescing__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 72, percentage_max_float,bdw__data_port_reads_coalescing__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 76, percentage_max_float,bdw__data_port_reads_coalescing__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 80, percentage_max_float,bdw__data_port_reads_coalescing__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 84, percentage_max_float,bdw__data_port_reads_coalescing__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 88, percentage_max_float,bdw__data_port_reads_coalescing__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 92, bdw__data_port_reads_coalescing__eu_avg_ipc_rate__max,bdw__data_port_reads_coalescing__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 96, percentage_max_float,bdw__data_port_reads_coalescing__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 100, percentage_max_float,bdw__data_port_reads_coalescing__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 104, NULL,bdw__data_port_reads_coalescing__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 112, NULL,bdw__data_port_reads_coalescing__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 120, bdw__data_port_reads_coalescing__slm_bytes_read__max,bdw__data_port_reads_coalescing__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 128, bdw__data_port_reads_coalescing__slm_bytes_written__max,bdw__data_port_reads_coalescing__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 136, NULL,bdw__data_port_reads_coalescing__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 144, NULL,bdw__data_port_reads_coalescing__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 152, bdw__data_port_reads_coalescing__l3_shader_throughput__max,bdw__data_port_reads_coalescing__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 160, NULL,bdw__data_port_reads_coalescing__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 218, 168, NULL,bdw__data_port_reads_coalescing__eu_hdc0_reads32_b__read);

      intel_perf_query_add_counter_uint64(query, 219, 176, NULL,bdw__data_port_reads_coalescing__eu_hdc0_reads64_b__read);

      intel_perf_query_add_counter_uint64(query, 220, 184, NULL,bdw__data_port_reads_coalescing__eu_hdc0_reads128_b__read);

      intel_perf_query_add_counter_uint64(query, 221, 192, NULL,bdw__data_port_reads_coalescing__eu_hdc0_reads256_b__read);

      intel_perf_query_add_counter_uint64(query, 222, 200, NULL,bdw__data_port_reads_coalescing__hdc0_l3_data_reads__read);

      intel_perf_query_add_counter_uint64(query, 223, 208, NULL,bdw__data_port_reads_coalescing__hdc0_l3_data_writes__read);

      intel_perf_query_add_counter_uint64(query, 224, 216, NULL,bdw__data_port_reads_coalescing__hdc0_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 225, 224, NULL,bdw__data_port_reads_coalescing__hdc0_l3_writes__read);

      intel_perf_query_add_counter_float(query, 226, 232, NULL,bdw__data_port_reads_coalescing__eu_bytes_read_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 227, 236, NULL,bdw__data_port_reads_coalescing__eu_data_reads_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_data_port_writes_coalescing_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Data Port Writes Coalescing metric set";
   query->symbol_name = "DataPortWritesCoalescing";
   query->guid = "343ebc99-4a55-414c-8c17-d8e259cf5e20";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->sys_vars.subslice_mask & 0x01) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x103D0005 },
            { .reg = 0x00009888, .val = 0x143D0120 },
            { .reg = 0x00009888, .val = 0x163D2400 },
            { .reg = 0x00009888, .val = 0x1058022F },
            { .reg = 0x00009888, .val = 0x105B0000 },
            { .reg = 0x00009888, .val = 0x198B0003 },
            { .reg = 0x00009888, .val = 0x005CC000 },
            { .reg = 0x00009888, .val = 0x065CC000 },
            { .reg = 0x00009888, .val = 0x085CC000 },
            { .reg = 0x00009888, .val = 0x0A5CC000 },
            { .reg = 0x00009888, .val = 0x0E5CC000 },
            { .reg = 0x00009888, .val = 0x025C4000 },
            { .reg = 0x00009888, .val = 0x045C8000 },
            { .reg = 0x00009888, .val = 0x003D0000 },
            { .reg = 0x00009888, .val = 0x063D0094 },
            { .reg = 0x00009888, .val = 0x083D0182 },
            { .reg = 0x00009888, .val = 0x0A3D1814 },
            { .reg = 0x00009888, .val = 0x0E3D0000 },
            { .reg = 0x00009888, .val = 0x183D0000 },
            { .reg = 0x00009888, .val = 0x1A3D0000 },
            { .reg = 0x00009888, .val = 0x0C3D0000 },
            { .reg = 0x00009888, .val = 0x0E582242 },
            { .reg = 0x00009888, .val = 0x00586700 },
            { .reg = 0x00009888, .val = 0x0258004F },
            { .reg = 0x00009888, .val = 0x0658C000 },
            { .reg = 0x00009888, .val = 0x0858C000 },
            { .reg = 0x00009888, .val = 0x0A58C000 },
            { .reg = 0x00009888, .val = 0x045B6A80 },
            { .reg = 0x00009888, .val = 0x005B4000 },
            { .reg = 0x00009888, .val = 0x0E5B4000 },
            { .reg = 0x00009888, .val = 0x185B5400 },
            { .reg = 0x00009888, .val = 0x1A5B0141 },
            { .reg = 0x00009888, .val = 0x025B4000 },
            { .reg = 0x00009888, .val = 0x0A5B0000 },
            { .reg = 0x00009888, .val = 0x0C5B4000 },
            { .reg = 0x00009888, .val = 0x0C1FA800 },
            { .reg = 0x00009888, .val = 0x0E1FAAA0 },
            { .reg = 0x00009888, .val = 0x101F0282 },
            { .reg = 0x00009888, .val = 0x00384000 },
            { .reg = 0x00009888, .val = 0x0E384000 },
            { .reg = 0x00009888, .val = 0x16384000 },
            { .reg = 0x00009888, .val = 0x18381415 },
            { .reg = 0x00009888, .val = 0x02384000 },
            { .reg = 0x00009888, .val = 0x04384000 },
            { .reg = 0x00009888, .val = 0x0A384000 },
            { .reg = 0x00009888, .val = 0x0C384000 },
            { .reg = 0x00009888, .val = 0x0039A000 },
            { .reg = 0x00009888, .val = 0x0639A000 },
            { .reg = 0x00009888, .val = 0x0839A000 },
            { .reg = 0x00009888, .val = 0x0A39A000 },
            { .reg = 0x00009888, .val = 0x0E39A000 },
            { .reg = 0x00009888, .val = 0x02392000 },
            { .reg = 0x00009888, .val = 0x04398000 },
            { .reg = 0x00009888, .val = 0x018A8000 },
            { .reg = 0x00009888, .val = 0x0F8A8000 },
            { .reg = 0x00009888, .val = 0x198A8000 },
            { .reg = 0x00009888, .val = 0x1B8A82A0 },
            { .reg = 0x00009888, .val = 0x1D8A0002 },
            { .reg = 0x00009888, .val = 0x038A8000 },
            { .reg = 0x00009888, .val = 0x058A8000 },
            { .reg = 0x00009888, .val = 0x0B8A8000 },
            { .reg = 0x00009888, .val = 0x0D8A8000 },
            { .reg = 0x00009888, .val = 0x038B6300 },
            { .reg = 0x00009888, .val = 0x058B0062 },
            { .reg = 0x00009888, .val = 0x118B0000 },
            { .reg = 0x00009888, .val = 0x238B02A0 },
            { .reg = 0x00009888, .val = 0x258B1555 },
            { .reg = 0x00009888, .val = 0x278B0014 },
            { .reg = 0x00009888, .val = 0x1F85AA80 },
            { .reg = 0x00009888, .val = 0x21852AAA },
            { .reg = 0x00009888, .val = 0x23850028 },
            { .reg = 0x00009888, .val = 0x01834000 },
            { .reg = 0x00009888, .val = 0x0F834000 },
            { .reg = 0x00009888, .val = 0x19835400 },
            { .reg = 0x00009888, .val = 0x1B830141 },
            { .reg = 0x00009888, .val = 0x03834000 },
            { .reg = 0x00009888, .val = 0x05834000 },
            { .reg = 0x00009888, .val = 0x07834000 },
            { .reg = 0x00009888, .val = 0x09834000 },
            { .reg = 0x00009888, .val = 0x0B834000 },
            { .reg = 0x00009888, .val = 0x0D834000 },
            { .reg = 0x00009888, .val = 0x0184C000 },
            { .reg = 0x00009888, .val = 0x0784C000 },
            { .reg = 0x00009888, .val = 0x0984C000 },
            { .reg = 0x00009888, .val = 0x0B84C000 },
            { .reg = 0x00009888, .val = 0x0F84C000 },
            { .reg = 0x00009888, .val = 0x0384C000 },
            { .reg = 0x00009888, .val = 0x0584C000 },
            { .reg = 0x00009888, .val = 0x1180C000 },
            { .reg = 0x00009888, .val = 0x1780C000 },
            { .reg = 0x00009888, .val = 0x1980C000 },
            { .reg = 0x00009888, .val = 0x1B80C000 },
            { .reg = 0x00009888, .val = 0x1F80C000 },
            { .reg = 0x00009888, .val = 0x1380C000 },
            { .reg = 0x00009888, .val = 0x1580C000 },
            { .reg = 0x00000D24, .val = 0x00000000 },
            { .reg = 0x00009888, .val = 0x4D801000 },
            { .reg = 0x00009888, .val = 0x3D800000 },
            { .reg = 0x00009888, .val = 0x4F800001 },
            { .reg = 0x00009888, .val = 0x43800000 },
            { .reg = 0x00009888, .val = 0x51800000 },
            { .reg = 0x00009888, .val = 0x45800000 },
            { .reg = 0x00009888, .val = 0x21800000 },
            { .reg = 0x00009888, .val = 0x31800000 },
            { .reg = 0x00009888, .val = 0x53800000 },
            { .reg = 0x00009888, .val = 0x47800420 },
            { .reg = 0x00009888, .val = 0x3F800421 },
            { .reg = 0x00009888, .val = 0x41800041 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0xBA98BA98 },
         { .reg = 0x00002748, .val = 0xBA98BA98 },
         { .reg = 0x00002744, .val = 0x00003377 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FF72 },
         { .reg = 0x00002774, .val = 0x0000BFD0 },
         { .reg = 0x00002778, .val = 0x0007FF62 },
         { .reg = 0x0000277C, .val = 0x0000BFD0 },
         { .reg = 0x00002780, .val = 0x0007FF42 },
         { .reg = 0x00002784, .val = 0x0000BFD0 },
         { .reg = 0x00002788, .val = 0x0007FF02 },
         { .reg = 0x0000278C, .val = 0x0000BFD0 },
         { .reg = 0x00002790, .val = 0x0005FFF2 },
         { .reg = 0x00002794, .val = 0x0000BFD0 },
         { .reg = 0x00002798, .val = 0x0005FFE2 },
         { .reg = 0x0000279C, .val = 0x0000BFD0 },
         { .reg = 0x000027A0, .val = 0x0005FFC2 },
         { .reg = 0x000027A4, .val = 0x0000BFD0 },
         { .reg = 0x000027A8, .val = 0x0005FF82 },
         { .reg = 0x000027AC, .val = 0x0000BFD0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__data_port_writes_coalescing__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__data_port_writes_coalescing__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__data_port_writes_coalescing__avg_gpu_core_frequency__max,bdw__data_port_writes_coalescing__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,bdw__data_port_writes_coalescing__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,bdw__data_port_writes_coalescing__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,bdw__data_port_writes_coalescing__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,bdw__data_port_writes_coalescing__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,bdw__data_port_writes_coalescing__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,bdw__data_port_writes_coalescing__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 72, percentage_max_float,bdw__data_port_writes_coalescing__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 76, percentage_max_float,bdw__data_port_writes_coalescing__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 80, percentage_max_float,bdw__data_port_writes_coalescing__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 84, percentage_max_float,bdw__data_port_writes_coalescing__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 88, percentage_max_float,bdw__data_port_writes_coalescing__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 92, bdw__data_port_writes_coalescing__eu_avg_ipc_rate__max,bdw__data_port_writes_coalescing__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 96, percentage_max_float,bdw__data_port_writes_coalescing__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 100, percentage_max_float,bdw__data_port_writes_coalescing__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 104, NULL,bdw__data_port_writes_coalescing__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 112, NULL,bdw__data_port_writes_coalescing__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 120, bdw__data_port_writes_coalescing__slm_bytes_read__max,bdw__data_port_writes_coalescing__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 128, bdw__data_port_writes_coalescing__slm_bytes_written__max,bdw__data_port_writes_coalescing__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 136, NULL,bdw__data_port_writes_coalescing__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 144, NULL,bdw__data_port_writes_coalescing__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 152, bdw__data_port_writes_coalescing__l3_shader_throughput__max,bdw__data_port_writes_coalescing__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 160, NULL,bdw__data_port_writes_coalescing__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 228, 168, NULL,bdw__data_port_writes_coalescing__eu_hdc0_writes32_b__read);

      intel_perf_query_add_counter_uint64(query, 229, 176, NULL,bdw__data_port_writes_coalescing__eu_hdc0_writes64_b__read);

      intel_perf_query_add_counter_uint64(query, 230, 184, NULL,bdw__data_port_writes_coalescing__eu_hdc0_writes96_b__read);

      intel_perf_query_add_counter_uint64(query, 231, 192, NULL,bdw__data_port_writes_coalescing__eu_hdc0_writes128_b__read);

      intel_perf_query_add_counter_uint64(query, 232, 200, NULL,bdw__data_port_writes_coalescing__eu_hdc0_writes192_b__read);

      intel_perf_query_add_counter_uint64(query, 233, 208, NULL,bdw__data_port_writes_coalescing__eu_hdc0_writes128_b_simd16__read);

      intel_perf_query_add_counter_uint64(query, 234, 216, NULL,bdw__data_port_writes_coalescing__eu_hdc0_writes256_b_simd16__read);

      intel_perf_query_add_counter_uint64(query, 222, 224, NULL,bdw__data_port_writes_coalescing__hdc0_l3_data_reads__read);

      intel_perf_query_add_counter_uint64(query, 223, 232, NULL,bdw__data_port_writes_coalescing__hdc0_l3_data_writes__read);

      intel_perf_query_add_counter_uint64(query, 224, 240, NULL,bdw__data_port_writes_coalescing__hdc0_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 225, 248, NULL,bdw__data_port_writes_coalescing__hdc0_l3_writes__read);

      intel_perf_query_add_counter_float(query, 235, 256, NULL,bdw__data_port_writes_coalescing__eu_bytes_written_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 236, 260, NULL,bdw__data_port_writes_coalescing__eu_data_writes_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "78490af2-10fa-430b-ae3c-94ec04d5214e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x105C0232 },
         { .reg = 0x00009888, .val = 0x10580232 },
         { .reg = 0x00009888, .val = 0x10380232 },
         { .reg = 0x00009888, .val = 0x10DC0232 },
         { .reg = 0x00009888, .val = 0x10D80232 },
         { .reg = 0x00009888, .val = 0x10B80232 },
         { .reg = 0x00009888, .val = 0x118E4400 },
         { .reg = 0x00009888, .val = 0x025C6080 },
         { .reg = 0x00009888, .val = 0x045C004B },
         { .reg = 0x00009888, .val = 0x005C8000 },
         { .reg = 0x00009888, .val = 0x00582080 },
         { .reg = 0x00009888, .val = 0x0258004B },
         { .reg = 0x00009888, .val = 0x025B4000 },
         { .reg = 0x00009888, .val = 0x045B4000 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F00AA },
         { .reg = 0x00009888, .val = 0x04386080 },
         { .reg = 0x00009888, .val = 0x0638404B },
         { .reg = 0x00009888, .val = 0x02384000 },
         { .reg = 0x00009888, .val = 0x08384000 },
         { .reg = 0x00009888, .val = 0x0A380000 },
         { .reg = 0x00009888, .val = 0x0C380000 },
         { .reg = 0x00009888, .val = 0x00398000 },
         { .reg = 0x00009888, .val = 0x0239A000 },
         { .reg = 0x00009888, .val = 0x0439A000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x0CDC25C1 },
         { .reg = 0x00009888, .val = 0x0ADCC000 },
         { .reg = 0x00009888, .val = 0x0AD825C1 },
         { .reg = 0x00009888, .val = 0x18DB4000 },
         { .reg = 0x00009888, .val = 0x1ADB0001 },
         { .reg = 0x00009888, .val = 0x0E9F8000 },
         { .reg = 0x00009888, .val = 0x109F02AA },
         { .reg = 0x00009888, .val = 0x0EB825C1 },
         { .reg = 0x00009888, .val = 0x18B80154 },
         { .reg = 0x00009888, .val = 0x0AB9A000 },
         { .reg = 0x00009888, .val = 0x0CB9A000 },
         { .reg = 0x00009888, .val = 0x0EB9A000 },
         { .reg = 0x00009888, .val = 0x0D88C000 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x258BAA05 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x198C5400 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x098DC000 },
         { .reg = 0x00009888, .val = 0x0B8DA000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x098E05C0 },
         { .reg = 0x00009888, .val = 0x058E0000 },
         { .reg = 0x00009888, .val = 0x198F0020 },
         { .reg = 0x00009888, .val = 0x2185AA0A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x19835000 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x09848000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x19808000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x51800040 },
         { .reg = 0x00009888, .val = 0x43800400 },
         { .reg = 0x00009888, .val = 0x45800800 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47800C62 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F801042 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x418014A4 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FFF7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__hdc_and_sf__avg_gpu_core_frequency__max,bdw__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__hdc_and_sf__slm_bytes_read__max,bdw__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__hdc_and_sf__slm_bytes_written__max,bdw__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__hdc_and_sf__l3_shader_throughput__max,bdw__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,bdw__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 238, 244, percentage_max_float,bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 252, percentage_max_float,bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 241, 256, percentage_max_float,bdw__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 242, 260, percentage_max_float,bdw__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 243, 264, percentage_max_float,bdw__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 268, percentage_max_float,bdw__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "c0abdd97-3b13-4cad-814c-bd178804e02c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x10BF03DA },
         { .reg = 0x00009888, .val = 0x14BF0001 },
         { .reg = 0x00009888, .val = 0x12980340 },
         { .reg = 0x00009888, .val = 0x12990340 },
         { .reg = 0x00009888, .val = 0x0CBF1187 },
         { .reg = 0x00009888, .val = 0x0EBF1205 },
         { .reg = 0x00009888, .val = 0x00BF0500 },
         { .reg = 0x00009888, .val = 0x02BF042B },
         { .reg = 0x00009888, .val = 0x04BF002C },
         { .reg = 0x00009888, .val = 0x0CDAC000 },
         { .reg = 0x00009888, .val = 0x0EDAC000 },
         { .reg = 0x00009888, .val = 0x00DA8000 },
         { .reg = 0x00009888, .val = 0x02DAC000 },
         { .reg = 0x00009888, .val = 0x04DA4000 },
         { .reg = 0x00009888, .val = 0x04983400 },
         { .reg = 0x00009888, .val = 0x10980000 },
         { .reg = 0x00009888, .val = 0x06990034 },
         { .reg = 0x00009888, .val = 0x10990000 },
         { .reg = 0x00009888, .val = 0x0C9DC000 },
         { .reg = 0x00009888, .val = 0x0E9DC000 },
         { .reg = 0x00009888, .val = 0x009D8000 },
         { .reg = 0x00009888, .val = 0x029DC000 },
         { .reg = 0x00009888, .val = 0x049D4000 },
         { .reg = 0x00009888, .val = 0x109F02A8 },
         { .reg = 0x00009888, .val = 0x0C9FA000 },
         { .reg = 0x00009888, .val = 0x0E9F00BA },
         { .reg = 0x00009888, .val = 0x0CB88000 },
         { .reg = 0x00009888, .val = 0x0CB95000 },
         { .reg = 0x00009888, .val = 0x0EB95000 },
         { .reg = 0x00009888, .val = 0x00B94000 },
         { .reg = 0x00009888, .val = 0x02B95000 },
         { .reg = 0x00009888, .val = 0x04B91000 },
         { .reg = 0x00009888, .val = 0x06B92000 },
         { .reg = 0x00009888, .val = 0x0CBA4000 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x03888000 },
         { .reg = 0x00009888, .val = 0x05888000 },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x09888000 },
         { .reg = 0x00009888, .val = 0x0B888000 },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x258B800A },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B5500 },
         { .reg = 0x00009888, .val = 0x198C4000 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x038C4000 },
         { .reg = 0x00009888, .val = 0x058C4000 },
         { .reg = 0x00009888, .val = 0x078C4000 },
         { .reg = 0x00009888, .val = 0x098C4000 },
         { .reg = 0x00009888, .val = 0x0B8C4000 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x018D8000 },
         { .reg = 0x00009888, .val = 0x038DA000 },
         { .reg = 0x00009888, .val = 0x058DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2185800A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x1B830154 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x45800000 },
         { .reg = 0x00009888, .val = 0x47800000 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800060 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__l3_1__avg_gpu_core_frequency__max,bdw__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__l3_1__slm_bytes_read__max,bdw__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__l3_1__slm_bytes_written__max,bdw__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__l3_1__l3_shader_throughput__max,bdw__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 245, 240, percentage_max_float,bdw__l3_1__l31_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 246, 244, percentage_max_float,bdw__l3_1__l31_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 247, 248, percentage_max_float,bdw__l3_1__l31_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 248, 252, percentage_max_float,bdw__l3_1__l31_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,bdw__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_2";
   query->symbol_name = "L3_2";
   query->guid = "ad665281-a7cf-483a-bd10-0e07c43f61c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x103F03DA },
         { .reg = 0x00009888, .val = 0x143F0001 },
         { .reg = 0x00009888, .val = 0x12180340 },
         { .reg = 0x00009888, .val = 0x12190340 },
         { .reg = 0x00009888, .val = 0x0C3F1187 },
         { .reg = 0x00009888, .val = 0x0E3F1205 },
         { .reg = 0x00009888, .val = 0x003F0500 },
         { .reg = 0x00009888, .val = 0x023F042B },
         { .reg = 0x00009888, .val = 0x043F002C },
         { .reg = 0x00009888, .val = 0x0C5AC000 },
         { .reg = 0x00009888, .val = 0x0E5AC000 },
         { .reg = 0x00009888, .val = 0x005A8000 },
         { .reg = 0x00009888, .val = 0x025AC000 },
         { .reg = 0x00009888, .val = 0x045A4000 },
         { .reg = 0x00009888, .val = 0x04183400 },
         { .reg = 0x00009888, .val = 0x10180000 },
         { .reg = 0x00009888, .val = 0x06190034 },
         { .reg = 0x00009888, .val = 0x10190000 },
         { .reg = 0x00009888, .val = 0x0C1DC000 },
         { .reg = 0x00009888, .val = 0x0E1DC000 },
         { .reg = 0x00009888, .val = 0x001D8000 },
         { .reg = 0x00009888, .val = 0x021DC000 },
         { .reg = 0x00009888, .val = 0x041D4000 },
         { .reg = 0x00009888, .val = 0x101F02A8 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F00BA },
         { .reg = 0x00009888, .val = 0x0C388000 },
         { .reg = 0x00009888, .val = 0x0C395000 },
         { .reg = 0x00009888, .val = 0x0E395000 },
         { .reg = 0x00009888, .val = 0x00394000 },
         { .reg = 0x00009888, .val = 0x02395000 },
         { .reg = 0x00009888, .val = 0x04391000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x0C3A4000 },
         { .reg = 0x00009888, .val = 0x1B8AA800 },
         { .reg = 0x00009888, .val = 0x1D8A0002 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x258B4005 },
         { .reg = 0x00009888, .val = 0x278B0015 },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x2185800A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x1B830154 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x45800000 },
         { .reg = 0x00009888, .val = 0x47800000 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800060 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__l3_2__avg_gpu_core_frequency__max,bdw__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__l3_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__l3_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__l3_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__l3_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__l3_2__slm_bytes_read__max,bdw__l3_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__l3_2__slm_bytes_written__max,bdw__l3_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__l3_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__l3_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__l3_2__l3_shader_throughput__max,bdw__l3_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__l3_2__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,bdw__l3_2__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,bdw__l3_2__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,bdw__l3_2__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,bdw__l3_2__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,bdw__l3_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_3";
   query->symbol_name = "L3_3";
   query->guid = "930a15aa-4300-4fce-a9ba-edb0b9e880be";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x121B0340 },
         { .reg = 0x00009888, .val = 0x103F0274 },
         { .reg = 0x00009888, .val = 0x123F0000 },
         { .reg = 0x00009888, .val = 0x129B0340 },
         { .reg = 0x00009888, .val = 0x10BF0274 },
         { .reg = 0x00009888, .val = 0x12BF0000 },
         { .reg = 0x00009888, .val = 0x041B3400 },
         { .reg = 0x00009888, .val = 0x101B0000 },
         { .reg = 0x00009888, .val = 0x045C8000 },
         { .reg = 0x00009888, .val = 0x0A3D4000 },
         { .reg = 0x00009888, .val = 0x003F0080 },
         { .reg = 0x00009888, .val = 0x023F0793 },
         { .reg = 0x00009888, .val = 0x043F0014 },
         { .reg = 0x00009888, .val = 0x04588000 },
         { .reg = 0x00009888, .val = 0x005A8000 },
         { .reg = 0x00009888, .val = 0x025AC000 },
         { .reg = 0x00009888, .val = 0x045A4000 },
         { .reg = 0x00009888, .val = 0x0A5B4000 },
         { .reg = 0x00009888, .val = 0x001D8000 },
         { .reg = 0x00009888, .val = 0x021DC000 },
         { .reg = 0x00009888, .val = 0x041D4000 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F002A },
         { .reg = 0x00009888, .val = 0x0A384000 },
         { .reg = 0x00009888, .val = 0x00394000 },
         { .reg = 0x00009888, .val = 0x02395000 },
         { .reg = 0x00009888, .val = 0x04399000 },
         { .reg = 0x00009888, .val = 0x069B0034 },
         { .reg = 0x00009888, .val = 0x109B0000 },
         { .reg = 0x00009888, .val = 0x06DC4000 },
         { .reg = 0x00009888, .val = 0x0CBD4000 },
         { .reg = 0x00009888, .val = 0x0CBF0981 },
         { .reg = 0x00009888, .val = 0x0EBF0A0F },
         { .reg = 0x00009888, .val = 0x06D84000 },
         { .reg = 0x00009888, .val = 0x0CDAC000 },
         { .reg = 0x00009888, .val = 0x0EDAC000 },
         { .reg = 0x00009888, .val = 0x0CDB4000 },
         { .reg = 0x00009888, .val = 0x0C9DC000 },
         { .reg = 0x00009888, .val = 0x0E9DC000 },
         { .reg = 0x00009888, .val = 0x109F02A8 },
         { .reg = 0x00009888, .val = 0x0E9F0080 },
         { .reg = 0x00009888, .val = 0x0CB84000 },
         { .reg = 0x00009888, .val = 0x0CB95000 },
         { .reg = 0x00009888, .val = 0x0EB95000 },
         { .reg = 0x00009888, .val = 0x06B92000 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x258B8009 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x198C4000 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2185800A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x1B830154 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x45800C00 },
         { .reg = 0x00009888, .val = 0x47800C63 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F8014A5 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800045 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__l3_3__avg_gpu_core_frequency__max,bdw__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__l3_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__l3_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__l3_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__l3_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__l3_3__slm_bytes_read__max,bdw__l3_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__l3_3__slm_bytes_written__max,bdw__l3_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__l3_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__l3_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__l3_3__l3_shader_throughput__max,bdw__l3_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__l3_3__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 253, 240, percentage_max_float,bdw__l3_3__l30_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 254, 244, percentage_max_float,bdw__l3_3__l31_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 255, 248, percentage_max_float,bdw__l3_3__l31_bank3_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 256, 252, percentage_max_float,bdw__l3_3__l30_bank3_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,bdw__l3_3__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_l3_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_4";
   query->symbol_name = "L3_4";
   query->guid = "d7793b26-b5e3-4f0f-ad78-7ebc9d0b4c7d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x121A0340 },
         { .reg = 0x00009888, .val = 0x103F0017 },
         { .reg = 0x00009888, .val = 0x123F0020 },
         { .reg = 0x00009888, .val = 0x129A0340 },
         { .reg = 0x00009888, .val = 0x10BF0017 },
         { .reg = 0x00009888, .val = 0x12BF0020 },
         { .reg = 0x00009888, .val = 0x041A3400 },
         { .reg = 0x00009888, .val = 0x101A0000 },
         { .reg = 0x00009888, .val = 0x043B8000 },
         { .reg = 0x00009888, .val = 0x0A3E0010 },
         { .reg = 0x00009888, .val = 0x003F0200 },
         { .reg = 0x00009888, .val = 0x023F0113 },
         { .reg = 0x00009888, .val = 0x043F0014 },
         { .reg = 0x00009888, .val = 0x02592000 },
         { .reg = 0x00009888, .val = 0x005A8000 },
         { .reg = 0x00009888, .val = 0x025AC000 },
         { .reg = 0x00009888, .val = 0x045A4000 },
         { .reg = 0x00009888, .val = 0x0A1C8000 },
         { .reg = 0x00009888, .val = 0x001D8000 },
         { .reg = 0x00009888, .val = 0x021DC000 },
         { .reg = 0x00009888, .val = 0x041D4000 },
         { .reg = 0x00009888, .val = 0x0A1E8000 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F001A },
         { .reg = 0x00009888, .val = 0x00394000 },
         { .reg = 0x00009888, .val = 0x02395000 },
         { .reg = 0x00009888, .val = 0x04391000 },
         { .reg = 0x00009888, .val = 0x069A0034 },
         { .reg = 0x00009888, .val = 0x109A0000 },
         { .reg = 0x00009888, .val = 0x06BB4000 },
         { .reg = 0x00009888, .val = 0x0ABE0040 },
         { .reg = 0x00009888, .val = 0x0CBF0984 },
         { .reg = 0x00009888, .val = 0x0EBF0A02 },
         { .reg = 0x00009888, .val = 0x02D94000 },
         { .reg = 0x00009888, .val = 0x0CDAC000 },
         { .reg = 0x00009888, .val = 0x0EDAC000 },
         { .reg = 0x00009888, .val = 0x0C9C0400 },
         { .reg = 0x00009888, .val = 0x0C9DC000 },
         { .reg = 0x00009888, .val = 0x0E9DC000 },
         { .reg = 0x00009888, .val = 0x0C9E0400 },
         { .reg = 0x00009888, .val = 0x109F02A8 },
         { .reg = 0x00009888, .val = 0x0E9F0040 },
         { .reg = 0x00009888, .val = 0x0CB95000 },
         { .reg = 0x00009888, .val = 0x0EB95000 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x258B8009 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x198C4000 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2185800A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x1B830154 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x45800800 },
         { .reg = 0x00009888, .val = 0x47800842 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F801084 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800044 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__l3_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__l3_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__l3_4__avg_gpu_core_frequency__max,bdw__l3_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__l3_4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__l3_4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__l3_4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__l3_4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__l3_4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__l3_4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__l3_4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__l3_4__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__l3_4__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__l3_4__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__l3_4__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__l3_4__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__l3_4__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__l3_4__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__l3_4__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__l3_4__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__l3_4__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__l3_4__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__l3_4__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__l3_4__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__l3_4__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__l3_4__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__l3_4__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__l3_4__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__l3_4__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__l3_4__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__l3_4__slm_bytes_read__max,bdw__l3_4__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__l3_4__slm_bytes_written__max,bdw__l3_4__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__l3_4__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__l3_4__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__l3_4__l3_shader_throughput__max,bdw__l3_4__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__l3_4__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 257, 240, percentage_max_float,bdw__l3_4__l30_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 258, 244, percentage_max_float,bdw__l3_4__l31_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 259, 248, percentage_max_float,bdw__l3_4__l31_bank2_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 260, 252, percentage_max_float,bdw__l3_4__l30_bank2_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,bdw__l3_4__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 46);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "da0f7875-1143-4d73-a39c-9128a951c46a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x143B000E },
         { .reg = 0x00009888, .val = 0x043C55C0 },
         { .reg = 0x00009888, .val = 0x0A1E0280 },
         { .reg = 0x00009888, .val = 0x0C1E0408 },
         { .reg = 0x00009888, .val = 0x10390000 },
         { .reg = 0x00009888, .val = 0x12397A1F },
         { .reg = 0x00009888, .val = 0x14BB000E },
         { .reg = 0x00009888, .val = 0x04BC5000 },
         { .reg = 0x00009888, .val = 0x0A9E0296 },
         { .reg = 0x00009888, .val = 0x0C9E0008 },
         { .reg = 0x00009888, .val = 0x10B90000 },
         { .reg = 0x00009888, .val = 0x12B97A1F },
         { .reg = 0x00009888, .val = 0x063B0042 },
         { .reg = 0x00009888, .val = 0x103B0000 },
         { .reg = 0x00009888, .val = 0x083C0000 },
         { .reg = 0x00009888, .val = 0x0A3E0040 },
         { .reg = 0x00009888, .val = 0x043F8000 },
         { .reg = 0x00009888, .val = 0x02594000 },
         { .reg = 0x00009888, .val = 0x045A8000 },
         { .reg = 0x00009888, .val = 0x0C1C0400 },
         { .reg = 0x00009888, .val = 0x041D8000 },
         { .reg = 0x00009888, .val = 0x081E02C0 },
         { .reg = 0x00009888, .val = 0x0E1E0000 },
         { .reg = 0x00009888, .val = 0x0C1FA800 },
         { .reg = 0x00009888, .val = 0x0E1F0260 },
         { .reg = 0x00009888, .val = 0x101F0014 },
         { .reg = 0x00009888, .val = 0x003905E0 },
         { .reg = 0x00009888, .val = 0x06390BC0 },
         { .reg = 0x00009888, .val = 0x02390018 },
         { .reg = 0x00009888, .val = 0x04394000 },
         { .reg = 0x00009888, .val = 0x04BB0042 },
         { .reg = 0x00009888, .val = 0x10BB0000 },
         { .reg = 0x00009888, .val = 0x02BC05C0 },
         { .reg = 0x00009888, .val = 0x08BC0000 },
         { .reg = 0x00009888, .val = 0x0ABE0004 },
         { .reg = 0x00009888, .val = 0x02BF8000 },
         { .reg = 0x00009888, .val = 0x02D91000 },
         { .reg = 0x00009888, .val = 0x02DA8000 },
         { .reg = 0x00009888, .val = 0x089C8000 },
         { .reg = 0x00009888, .val = 0x029D8000 },
         { .reg = 0x00009888, .val = 0x089E8000 },
         { .reg = 0x00009888, .val = 0x0E9E0000 },
         { .reg = 0x00009888, .val = 0x0E9FA806 },
         { .reg = 0x00009888, .val = 0x109F0142 },
         { .reg = 0x00009888, .val = 0x08B90617 },
         { .reg = 0x00009888, .val = 0x0AB90BE0 },
         { .reg = 0x00009888, .val = 0x02B94000 },
         { .reg = 0x00009888, .val = 0x0D88F000 },
         { .reg = 0x00009888, .val = 0x0F88000C },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x09888000 },
         { .reg = 0x00009888, .val = 0x018A8000 },
         { .reg = 0x00009888, .val = 0x0F8A8000 },
         { .reg = 0x00009888, .val = 0x1B8A2800 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x238B52A0 },
         { .reg = 0x00009888, .val = 0x258B6A95 },
         { .reg = 0x00009888, .val = 0x278B0029 },
         { .reg = 0x00009888, .val = 0x178C2000 },
         { .reg = 0x00009888, .val = 0x198C1500 },
         { .reg = 0x00009888, .val = 0x1B8C0014 },
         { .reg = 0x00009888, .val = 0x078C4000 },
         { .reg = 0x00009888, .val = 0x098C4000 },
         { .reg = 0x00009888, .val = 0x098DA000 },
         { .reg = 0x00009888, .val = 0x0B8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x038D8000 },
         { .reg = 0x00009888, .val = 0x058D2000 },
         { .reg = 0x00009888, .val = 0x1F85AA80 },
         { .reg = 0x00009888, .val = 0x2185AAAA },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x01834000 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0184C000 },
         { .reg = 0x00009888, .val = 0x0784C000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x1180C000 },
         { .reg = 0x00009888, .val = 0x1780C000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x4D800444 },
         { .reg = 0x00009888, .val = 0x3D800000 },
         { .reg = 0x00009888, .val = 0x4F804000 },
         { .reg = 0x00009888, .val = 0x43801080 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45800084 },
         { .reg = 0x00009888, .val = 0x53800044 },
         { .reg = 0x00009888, .val = 0x47801080 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x3F800000 },
         { .reg = 0x00009888, .val = 0x41800840 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00006000 },
         { .reg = 0x00002774, .val = 0x0000F3FF },
         { .reg = 0x00002778, .val = 0x00001800 },
         { .reg = 0x0000277C, .val = 0x0000FCFF },
         { .reg = 0x00002780, .val = 0x00000600 },
         { .reg = 0x00002784, .val = 0x0000FF3F },
         { .reg = 0x00002788, .val = 0x00000180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000060 },
         { .reg = 0x00002794, .val = 0x0000FFF3 },
         { .reg = 0x00002798, .val = 0x00000018 },
         { .reg = 0x0000279C, .val = 0x0000FFFC },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__rasterizer_and_pixel_backend__slm_bytes_read__max,bdw__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__rasterizer_and_pixel_backend__slm_bytes_written__max,bdw__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__rasterizer_and_pixel_backend__l3_shader_throughput__max,bdw__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 240, percentage_max_float,bdw__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 262, 244, percentage_max_float,bdw__rasterizer_and_pixel_backend__pixel_data1_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 248, percentage_max_float,bdw__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 264, 252, percentage_max_float,bdw__rasterizer_and_pixel_backend__rasterizer1_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 265, 256, percentage_max_float,bdw__rasterizer_and_pixel_backend__rasterizer1_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 260, percentage_max_float,bdw__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 264, percentage_max_float,bdw__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 268, percentage_max_float,bdw__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 269, 272, percentage_max_float,bdw__rasterizer_and_pixel_backend__pixel_values1_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 270, 276, percentage_max_float,bdw__rasterizer_and_pixel_backend__ps_output1_available__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 280, percentage_max_float,bdw__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler_1";
   query->symbol_name = "Sampler_1";
   query->guid = "52c186e4-39e3-4534-87cd-41bd47763df9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x18921400 },
         { .reg = 0x00009888, .val = 0x149500AB },
         { .reg = 0x00009888, .val = 0x18B21400 },
         { .reg = 0x00009888, .val = 0x14B500AB },
         { .reg = 0x00009888, .val = 0x18D21400 },
         { .reg = 0x00009888, .val = 0x14D500AB },
         { .reg = 0x00009888, .val = 0x0CDC8000 },
         { .reg = 0x00009888, .val = 0x0EDC4000 },
         { .reg = 0x00009888, .val = 0x02DCC000 },
         { .reg = 0x00009888, .val = 0x04DCC000 },
         { .reg = 0x00009888, .val = 0x1ABD00A0 },
         { .reg = 0x00009888, .val = 0x0ABD8000 },
         { .reg = 0x00009888, .val = 0x0CD88000 },
         { .reg = 0x00009888, .val = 0x0ED84000 },
         { .reg = 0x00009888, .val = 0x04D88000 },
         { .reg = 0x00009888, .val = 0x1ADB0050 },
         { .reg = 0x00009888, .val = 0x04DB8000 },
         { .reg = 0x00009888, .val = 0x06DB8000 },
         { .reg = 0x00009888, .val = 0x08DB8000 },
         { .reg = 0x00009888, .val = 0x0ADB4000 },
         { .reg = 0x00009888, .val = 0x109F02A0 },
         { .reg = 0x00009888, .val = 0x0C9FA000 },
         { .reg = 0x00009888, .val = 0x0E9F00AA },
         { .reg = 0x00009888, .val = 0x18B82500 },
         { .reg = 0x00009888, .val = 0x02B88000 },
         { .reg = 0x00009888, .val = 0x04B84000 },
         { .reg = 0x00009888, .val = 0x06B84000 },
         { .reg = 0x00009888, .val = 0x08B84000 },
         { .reg = 0x00009888, .val = 0x0AB84000 },
         { .reg = 0x00009888, .val = 0x0CB88000 },
         { .reg = 0x00009888, .val = 0x0CB98000 },
         { .reg = 0x00009888, .val = 0x0EB9A000 },
         { .reg = 0x00009888, .val = 0x00B98000 },
         { .reg = 0x00009888, .val = 0x02B9A000 },
         { .reg = 0x00009888, .val = 0x04B9A000 },
         { .reg = 0x00009888, .val = 0x06B92000 },
         { .reg = 0x00009888, .val = 0x1ABA0200 },
         { .reg = 0x00009888, .val = 0x02BA8000 },
         { .reg = 0x00009888, .val = 0x0CBA8000 },
         { .reg = 0x00009888, .val = 0x04908000 },
         { .reg = 0x00009888, .val = 0x04918000 },
         { .reg = 0x00009888, .val = 0x04927300 },
         { .reg = 0x00009888, .val = 0x10920000 },
         { .reg = 0x00009888, .val = 0x1893000A },
         { .reg = 0x00009888, .val = 0x0A934000 },
         { .reg = 0x00009888, .val = 0x0A946000 },
         { .reg = 0x00009888, .val = 0x0C959000 },
         { .reg = 0x00009888, .val = 0x0E950098 },
         { .reg = 0x00009888, .val = 0x10950000 },
         { .reg = 0x00009888, .val = 0x04B04000 },
         { .reg = 0x00009888, .val = 0x04B14000 },
         { .reg = 0x00009888, .val = 0x04B20073 },
         { .reg = 0x00009888, .val = 0x10B20000 },
         { .reg = 0x00009888, .val = 0x04B38000 },
         { .reg = 0x00009888, .val = 0x06B38000 },
         { .reg = 0x00009888, .val = 0x08B34000 },
         { .reg = 0x00009888, .val = 0x04B4C000 },
         { .reg = 0x00009888, .val = 0x02B59890 },
         { .reg = 0x00009888, .val = 0x10B50000 },
         { .reg = 0x00009888, .val = 0x06D04000 },
         { .reg = 0x00009888, .val = 0x06D14000 },
         { .reg = 0x00009888, .val = 0x06D20073 },
         { .reg = 0x00009888, .val = 0x10D20000 },
         { .reg = 0x00009888, .val = 0x18D30020 },
         { .reg = 0x00009888, .val = 0x02D38000 },
         { .reg = 0x00009888, .val = 0x0CD34000 },
         { .reg = 0x00009888, .val = 0x0AD48000 },
         { .reg = 0x00009888, .val = 0x04D42000 },
         { .reg = 0x00009888, .val = 0x0ED59000 },
         { .reg = 0x00009888, .val = 0x00D59800 },
         { .reg = 0x00009888, .val = 0x10D50000 },
         { .reg = 0x00009888, .val = 0x0F88000E },
         { .reg = 0x00009888, .val = 0x03888000 },
         { .reg = 0x00009888, .val = 0x05888000 },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x09888000 },
         { .reg = 0x00009888, .val = 0x0B888000 },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B5500 },
         { .reg = 0x00009888, .val = 0x258B000A },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x038C4000 },
         { .reg = 0x00009888, .val = 0x058C4000 },
         { .reg = 0x00009888, .val = 0x078C4000 },
         { .reg = 0x00009888, .val = 0x098C4000 },
         { .reg = 0x00009888, .val = 0x0B8C4000 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x0D8D8000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x018D8000 },
         { .reg = 0x00009888, .val = 0x038DA000 },
         { .reg = 0x00009888, .val = 0x058DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x2185000A },
         { .reg = 0x00009888, .val = 0x1B830150 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D848000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D808000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47801021 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800C64 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800C02 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__sampler_1__avg_gpu_core_frequency__max,bdw__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__sampler_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__sampler_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__sampler_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__sampler_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__sampler_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__sampler_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__sampler_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__sampler_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__sampler_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__sampler_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__sampler_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__sampler_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__sampler_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__sampler_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__sampler_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__sampler_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__sampler_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__sampler_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__sampler_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__sampler_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__sampler_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__sampler_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__sampler_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__sampler_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__sampler_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__sampler_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__sampler_1__slm_bytes_read__max,bdw__sampler_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__sampler_1__slm_bytes_written__max,bdw__sampler_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__sampler_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__sampler_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__sampler_1__l3_shader_throughput__max,bdw__sampler_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__sampler_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 271, 240, percentage_max_float,bdw__sampler_1__sampler11_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 272, 244, percentage_max_float,bdw__sampler_1__sampler12_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 273, 248, percentage_max_float,bdw__sampler_1__sampler10_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 274, 252, percentage_max_float,bdw__sampler_1__sampler12_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 275, 256, percentage_max_float,bdw__sampler_1__sampler10_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 276, 260, percentage_max_float,bdw__sampler_1__sampler11_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,bdw__sampler_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_sampler_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler_2";
   query->symbol_name = "Sampler_2";
   query->guid = "edcb8c31-764d-451a-9ecd-c9c89fb54f8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x18121400 },
         { .reg = 0x00009888, .val = 0x141500AB },
         { .reg = 0x00009888, .val = 0x18321400 },
         { .reg = 0x00009888, .val = 0x143500AB },
         { .reg = 0x00009888, .val = 0x18521400 },
         { .reg = 0x00009888, .val = 0x145500AB },
         { .reg = 0x00009888, .val = 0x0C5C8000 },
         { .reg = 0x00009888, .val = 0x0E5C4000 },
         { .reg = 0x00009888, .val = 0x025CC000 },
         { .reg = 0x00009888, .val = 0x045CC000 },
         { .reg = 0x00009888, .val = 0x1A3D00A0 },
         { .reg = 0x00009888, .val = 0x0A3D8000 },
         { .reg = 0x00009888, .val = 0x0C588000 },
         { .reg = 0x00009888, .val = 0x0E584000 },
         { .reg = 0x00009888, .val = 0x04588000 },
         { .reg = 0x00009888, .val = 0x1A5B0050 },
         { .reg = 0x00009888, .val = 0x045B8000 },
         { .reg = 0x00009888, .val = 0x065B8000 },
         { .reg = 0x00009888, .val = 0x085B8000 },
         { .reg = 0x00009888, .val = 0x0A5B4000 },
         { .reg = 0x00009888, .val = 0x101F02A0 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F00AA },
         { .reg = 0x00009888, .val = 0x18382500 },
         { .reg = 0x00009888, .val = 0x02388000 },
         { .reg = 0x00009888, .val = 0x04384000 },
         { .reg = 0x00009888, .val = 0x06384000 },
         { .reg = 0x00009888, .val = 0x08384000 },
         { .reg = 0x00009888, .val = 0x0A384000 },
         { .reg = 0x00009888, .val = 0x0C388000 },
         { .reg = 0x00009888, .val = 0x0C398000 },
         { .reg = 0x00009888, .val = 0x0E39A000 },
         { .reg = 0x00009888, .val = 0x00398000 },
         { .reg = 0x00009888, .val = 0x0239A000 },
         { .reg = 0x00009888, .val = 0x0439A000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x1A3A0200 },
         { .reg = 0x00009888, .val = 0x023A8000 },
         { .reg = 0x00009888, .val = 0x0C3A8000 },
         { .reg = 0x00009888, .val = 0x04108000 },
         { .reg = 0x00009888, .val = 0x04118000 },
         { .reg = 0x00009888, .val = 0x04127300 },
         { .reg = 0x00009888, .val = 0x10120000 },
         { .reg = 0x00009888, .val = 0x1813000A },
         { .reg = 0x00009888, .val = 0x0A134000 },
         { .reg = 0x00009888, .val = 0x0A146000 },
         { .reg = 0x00009888, .val = 0x0C159000 },
         { .reg = 0x00009888, .val = 0x0E150098 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x04304000 },
         { .reg = 0x00009888, .val = 0x04314000 },
         { .reg = 0x00009888, .val = 0x04320073 },
         { .reg = 0x00009888, .val = 0x10320000 },
         { .reg = 0x00009888, .val = 0x04338000 },
         { .reg = 0x00009888, .val = 0x06338000 },
         { .reg = 0x00009888, .val = 0x08334000 },
         { .reg = 0x00009888, .val = 0x0434C000 },
         { .reg = 0x00009888, .val = 0x02359890 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x06504000 },
         { .reg = 0x00009888, .val = 0x06514000 },
         { .reg = 0x00009888, .val = 0x06520073 },
         { .reg = 0x00009888, .val = 0x10520000 },
         { .reg = 0x00009888, .val = 0x18530020 },
         { .reg = 0x00009888, .val = 0x02538000 },
         { .reg = 0x00009888, .val = 0x0C534000 },
         { .reg = 0x00009888, .val = 0x0A548000 },
         { .reg = 0x00009888, .val = 0x04542000 },
         { .reg = 0x00009888, .val = 0x0E559000 },
         { .reg = 0x00009888, .val = 0x00559800 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x1B8AA000 },
         { .reg = 0x00009888, .val = 0x1D8A0002 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x278B0015 },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x258B0005 },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x2185000A },
         { .reg = 0x00009888, .val = 0x1B830150 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D848000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D808000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47801021 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800C64 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800C02 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__sampler_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__sampler_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__sampler_2__avg_gpu_core_frequency__max,bdw__sampler_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__sampler_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__sampler_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__sampler_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__sampler_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__sampler_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__sampler_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__sampler_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__sampler_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__sampler_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__sampler_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__sampler_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__sampler_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__sampler_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__sampler_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__sampler_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__sampler_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__sampler_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__sampler_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__sampler_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__sampler_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__sampler_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__sampler_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__sampler_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__sampler_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__sampler_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__sampler_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__sampler_2__slm_bytes_read__max,bdw__sampler_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__sampler_2__slm_bytes_written__max,bdw__sampler_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__sampler_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__sampler_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__sampler_2__l3_shader_throughput__max,bdw__sampler_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__sampler_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,bdw__sampler_2__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,bdw__sampler_2__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,bdw__sampler_2__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,bdw__sampler_2__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,bdw__sampler_2__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,bdw__sampler_2__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,bdw__sampler_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 48);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "729fc3f4-ccff-4902-be6b-f1a22cc92c02";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x16154D60 },
         { .reg = 0x00009888, .val = 0x16352E60 },
         { .reg = 0x00009888, .val = 0x16554D60 },
         { .reg = 0x00009888, .val = 0x16950000 },
         { .reg = 0x00009888, .val = 0x16B50000 },
         { .reg = 0x00009888, .val = 0x16D50000 },
         { .reg = 0x00009888, .val = 0x005C8000 },
         { .reg = 0x00009888, .val = 0x045CC000 },
         { .reg = 0x00009888, .val = 0x065C4000 },
         { .reg = 0x00009888, .val = 0x083D8000 },
         { .reg = 0x00009888, .val = 0x0A3D8000 },
         { .reg = 0x00009888, .val = 0x0458C000 },
         { .reg = 0x00009888, .val = 0x025B8000 },
         { .reg = 0x00009888, .val = 0x085B4000 },
         { .reg = 0x00009888, .val = 0x0A5B4000 },
         { .reg = 0x00009888, .val = 0x0C5B8000 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F00AA },
         { .reg = 0x00009888, .val = 0x02384000 },
         { .reg = 0x00009888, .val = 0x04388000 },
         { .reg = 0x00009888, .val = 0x06388000 },
         { .reg = 0x00009888, .val = 0x08384000 },
         { .reg = 0x00009888, .val = 0x0A384000 },
         { .reg = 0x00009888, .val = 0x0C384000 },
         { .reg = 0x00009888, .val = 0x00398000 },
         { .reg = 0x00009888, .val = 0x0239A000 },
         { .reg = 0x00009888, .val = 0x0439A000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x043A8000 },
         { .reg = 0x00009888, .val = 0x063A8000 },
         { .reg = 0x00009888, .val = 0x08138000 },
         { .reg = 0x00009888, .val = 0x0A138000 },
         { .reg = 0x00009888, .val = 0x06143000 },
         { .reg = 0x00009888, .val = 0x0415CFC7 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x02338000 },
         { .reg = 0x00009888, .val = 0x0C338000 },
         { .reg = 0x00009888, .val = 0x04342000 },
         { .reg = 0x00009888, .val = 0x06344000 },
         { .reg = 0x00009888, .val = 0x0035C700 },
         { .reg = 0x00009888, .val = 0x063500CF },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x04538000 },
         { .reg = 0x00009888, .val = 0x06538000 },
         { .reg = 0x00009888, .val = 0x0454C000 },
         { .reg = 0x00009888, .val = 0x0255CFC7 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x06DC8000 },
         { .reg = 0x00009888, .val = 0x08DC4000 },
         { .reg = 0x00009888, .val = 0x0CDCC000 },
         { .reg = 0x00009888, .val = 0x0EDCC000 },
         { .reg = 0x00009888, .val = 0x1ABD00A8 },
         { .reg = 0x00009888, .val = 0x0CD8C000 },
         { .reg = 0x00009888, .val = 0x0ED84000 },
         { .reg = 0x00009888, .val = 0x0EDB8000 },
         { .reg = 0x00009888, .val = 0x18DB0800 },
         { .reg = 0x00009888, .val = 0x1ADB0254 },
         { .reg = 0x00009888, .val = 0x0E9FAA00 },
         { .reg = 0x00009888, .val = 0x109F02AA },
         { .reg = 0x00009888, .val = 0x0EB84000 },
         { .reg = 0x00009888, .val = 0x16B84000 },
         { .reg = 0x00009888, .val = 0x18B8156A },
         { .reg = 0x00009888, .val = 0x06B98000 },
         { .reg = 0x00009888, .val = 0x08B9A000 },
         { .reg = 0x00009888, .val = 0x0AB9A000 },
         { .reg = 0x00009888, .val = 0x0CB9A000 },
         { .reg = 0x00009888, .val = 0x0EB9A000 },
         { .reg = 0x00009888, .val = 0x18BAA000 },
         { .reg = 0x00009888, .val = 0x1ABA0002 },
         { .reg = 0x00009888, .val = 0x16934000 },
         { .reg = 0x00009888, .val = 0x1893000A },
         { .reg = 0x00009888, .val = 0x0A947000 },
         { .reg = 0x00009888, .val = 0x0C95C5C1 },
         { .reg = 0x00009888, .val = 0x0E9500C3 },
         { .reg = 0x00009888, .val = 0x10950000 },
         { .reg = 0x00009888, .val = 0x0EB38000 },
         { .reg = 0x00009888, .val = 0x16B30040 },
         { .reg = 0x00009888, .val = 0x18B30020 },
         { .reg = 0x00009888, .val = 0x06B48000 },
         { .reg = 0x00009888, .val = 0x08B41000 },
         { .reg = 0x00009888, .val = 0x0AB48000 },
         { .reg = 0x00009888, .val = 0x06B5C500 },
         { .reg = 0x00009888, .val = 0x08B500C3 },
         { .reg = 0x00009888, .val = 0x0EB5C100 },
         { .reg = 0x00009888, .val = 0x10B50000 },
         { .reg = 0x00009888, .val = 0x16D31500 },
         { .reg = 0x00009888, .val = 0x08D4E000 },
         { .reg = 0x00009888, .val = 0x08D5C100 },
         { .reg = 0x00009888, .val = 0x0AD5C3C5 },
         { .reg = 0x00009888, .val = 0x10D50000 },
         { .reg = 0x00009888, .val = 0x0D88F800 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x258BAAA5 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x0F8C4000 },
         { .reg = 0x00009888, .val = 0x178C2000 },
         { .reg = 0x00009888, .val = 0x198C5500 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x078D8000 },
         { .reg = 0x00009888, .val = 0x098DA000 },
         { .reg = 0x00009888, .val = 0x0B8DA000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x2185AAAA },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0784C000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x1780C000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x43800C42 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45800063 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47800800 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F8014A4 },
         { .reg = 0x00009888, .val = 0x41801042 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x0000FE7F },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFBF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFF7 },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FFF9 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__tdl_1__avg_gpu_core_frequency__max,bdw__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__tdl_1__slm_bytes_read__max,bdw__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__tdl_1__slm_bytes_written__max,bdw__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__tdl_1__l3_shader_throughput__max,bdw__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 283, 240, percentage_max_float,bdw__tdl_1__non_ps_thread11_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 284, 244, percentage_max_float,bdw__tdl_1__ps_thread10_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 285, 248, percentage_max_float,bdw__tdl_1__non_ps_thread10_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 286, 252, percentage_max_float,bdw__tdl_1__ps_thread12_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 287, 256, percentage_max_float,bdw__tdl_1__non_ps_thread12_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 288, 260, percentage_max_float,bdw__tdl_1__ps_thread11_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 264, percentage_max_float,bdw__tdl_1__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 268, percentage_max_float,bdw__tdl_1__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 272, percentage_max_float,bdw__tdl_1__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 276, percentage_max_float,bdw__tdl_1__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 280, percentage_max_float,bdw__tdl_1__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 284, percentage_max_float,bdw__tdl_1__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 288, percentage_max_float,bdw__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 48);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "29598975-4785-43ab-a981-1dfa58d0e835";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x16150000 },
         { .reg = 0x00009888, .val = 0x16350000 },
         { .reg = 0x00009888, .val = 0x16550000 },
         { .reg = 0x00009888, .val = 0x16952E60 },
         { .reg = 0x00009888, .val = 0x16B54D60 },
         { .reg = 0x00009888, .val = 0x16D52E60 },
         { .reg = 0x00009888, .val = 0x065C8000 },
         { .reg = 0x00009888, .val = 0x085CC000 },
         { .reg = 0x00009888, .val = 0x0A5CC000 },
         { .reg = 0x00009888, .val = 0x0C5C4000 },
         { .reg = 0x00009888, .val = 0x0E3D8000 },
         { .reg = 0x00009888, .val = 0x183DA000 },
         { .reg = 0x00009888, .val = 0x06588000 },
         { .reg = 0x00009888, .val = 0x08588000 },
         { .reg = 0x00009888, .val = 0x0A584000 },
         { .reg = 0x00009888, .val = 0x0E5B4000 },
         { .reg = 0x00009888, .val = 0x185B5800 },
         { .reg = 0x00009888, .val = 0x1A5B000A },
         { .reg = 0x00009888, .val = 0x0E1FAA00 },
         { .reg = 0x00009888, .val = 0x101F02AA },
         { .reg = 0x00009888, .val = 0x0E384000 },
         { .reg = 0x00009888, .val = 0x16384000 },
         { .reg = 0x00009888, .val = 0x18382A55 },
         { .reg = 0x00009888, .val = 0x06398000 },
         { .reg = 0x00009888, .val = 0x0839A000 },
         { .reg = 0x00009888, .val = 0x0A39A000 },
         { .reg = 0x00009888, .val = 0x0C39A000 },
         { .reg = 0x00009888, .val = 0x0E39A000 },
         { .reg = 0x00009888, .val = 0x1A3A02A0 },
         { .reg = 0x00009888, .val = 0x0E138000 },
         { .reg = 0x00009888, .val = 0x16130500 },
         { .reg = 0x00009888, .val = 0x06148000 },
         { .reg = 0x00009888, .val = 0x08146000 },
         { .reg = 0x00009888, .val = 0x0615C100 },
         { .reg = 0x00009888, .val = 0x0815C500 },
         { .reg = 0x00009888, .val = 0x0A1500C3 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x16335040 },
         { .reg = 0x00009888, .val = 0x08349000 },
         { .reg = 0x00009888, .val = 0x0A341000 },
         { .reg = 0x00009888, .val = 0x083500C1 },
         { .reg = 0x00009888, .val = 0x0A35C500 },
         { .reg = 0x00009888, .val = 0x0C3500C3 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x1853002A },
         { .reg = 0x00009888, .val = 0x0A54E000 },
         { .reg = 0x00009888, .val = 0x0C55C500 },
         { .reg = 0x00009888, .val = 0x0E55C1C3 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x00DC8000 },
         { .reg = 0x00009888, .val = 0x02DCC000 },
         { .reg = 0x00009888, .val = 0x04DC4000 },
         { .reg = 0x00009888, .val = 0x04BD8000 },
         { .reg = 0x00009888, .val = 0x06BD8000 },
         { .reg = 0x00009888, .val = 0x02D8C000 },
         { .reg = 0x00009888, .val = 0x02DB8000 },
         { .reg = 0x00009888, .val = 0x04DB4000 },
         { .reg = 0x00009888, .val = 0x06DB4000 },
         { .reg = 0x00009888, .val = 0x08DB8000 },
         { .reg = 0x00009888, .val = 0x0C9FA000 },
         { .reg = 0x00009888, .val = 0x0E9F00AA },
         { .reg = 0x00009888, .val = 0x02B84000 },
         { .reg = 0x00009888, .val = 0x04B84000 },
         { .reg = 0x00009888, .val = 0x06B84000 },
         { .reg = 0x00009888, .val = 0x08B84000 },
         { .reg = 0x00009888, .val = 0x0AB88000 },
         { .reg = 0x00009888, .val = 0x0CB88000 },
         { .reg = 0x00009888, .val = 0x00B98000 },
         { .reg = 0x00009888, .val = 0x02B9A000 },
         { .reg = 0x00009888, .val = 0x04B9A000 },
         { .reg = 0x00009888, .val = 0x06B92000 },
         { .reg = 0x00009888, .val = 0x0ABA8000 },
         { .reg = 0x00009888, .val = 0x0CBA8000 },
         { .reg = 0x00009888, .val = 0x04938000 },
         { .reg = 0x00009888, .val = 0x06938000 },
         { .reg = 0x00009888, .val = 0x0494C000 },
         { .reg = 0x00009888, .val = 0x0295CFC7 },
         { .reg = 0x00009888, .val = 0x10950000 },
         { .reg = 0x00009888, .val = 0x02B38000 },
         { .reg = 0x00009888, .val = 0x08B38000 },
         { .reg = 0x00009888, .val = 0x04B42000 },
         { .reg = 0x00009888, .val = 0x06B41000 },
         { .reg = 0x00009888, .val = 0x00B5C700 },
         { .reg = 0x00009888, .val = 0x04B500CF },
         { .reg = 0x00009888, .val = 0x10B50000 },
         { .reg = 0x00009888, .val = 0x0AD38000 },
         { .reg = 0x00009888, .val = 0x0CD38000 },
         { .reg = 0x00009888, .val = 0x06D46000 },
         { .reg = 0x00009888, .val = 0x04D5C700 },
         { .reg = 0x00009888, .val = 0x06D500CF },
         { .reg = 0x00009888, .val = 0x10D50000 },
         { .reg = 0x00009888, .val = 0x03888000 },
         { .reg = 0x00009888, .val = 0x05888000 },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x09888000 },
         { .reg = 0x00009888, .val = 0x0B888000 },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x0F8A8000 },
         { .reg = 0x00009888, .val = 0x198A8000 },
         { .reg = 0x00009888, .val = 0x1B8AAAA0 },
         { .reg = 0x00009888, .val = 0x1D8A0002 },
         { .reg = 0x00009888, .val = 0x258B555A },
         { .reg = 0x00009888, .val = 0x278B0015 },
         { .reg = 0x00009888, .val = 0x238B5500 },
         { .reg = 0x00009888, .val = 0x038C4000 },
         { .reg = 0x00009888, .val = 0x058C4000 },
         { .reg = 0x00009888, .val = 0x078C4000 },
         { .reg = 0x00009888, .val = 0x098C4000 },
         { .reg = 0x00009888, .val = 0x0B8C4000 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x018D8000 },
         { .reg = 0x00009888, .val = 0x038DA000 },
         { .reg = 0x00009888, .val = 0x058DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2185AAAA },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0784C000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x1780C000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x43800882 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45801082 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x478014A5 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800002 },
         { .reg = 0x00009888, .val = 0x41800C62 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x0000FE7F },
         { .reg = 0x00002780, .val = 0x00000000 },
         { .reg = 0x00002784, .val = 0x0000FF9F },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000FFE7 },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFFB },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FFFD },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__tdl_2__avg_gpu_core_frequency__max,bdw__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bdw__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bdw__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bdw__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bdw__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bdw__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bdw__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bdw__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bdw__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bdw__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bdw__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bdw__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bdw__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bdw__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bdw__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bdw__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bdw__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bdw__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bdw__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bdw__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bdw__tdl_2__slm_bytes_read__max,bdw__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bdw__tdl_2__slm_bytes_written__max,bdw__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bdw__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bdw__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bdw__tdl_2__l3_shader_throughput__max,bdw__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bdw__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 240, percentage_max_float,bdw__tdl_2__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 244, percentage_max_float,bdw__tdl_2__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 248, percentage_max_float,bdw__tdl_2__ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 252, percentage_max_float,bdw__tdl_2__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 256, percentage_max_float,bdw__tdl_2__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 260, percentage_max_float,bdw__tdl_2__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 301, 264, percentage_max_float,bdw__tdl_2__thread_header12_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 302, 268, percentage_max_float,bdw__tdl_2__thread_header12_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 303, 272, percentage_max_float,bdw__tdl_2__thread_header11_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 304, 276, percentage_max_float,bdw__tdl_2__thread_header10_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 305, 280, percentage_max_float,bdw__tdl_2__thread_header10_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 306, 284, percentage_max_float,bdw__tdl_2__thread_header11_ready_port0__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 288, percentage_max_float,bdw__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "8fb61ba2-2fbb-454c-a136-2dec5a8a595e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x161503E0 },
         { .reg = 0x00009888, .val = 0x163503E0 },
         { .reg = 0x00009888, .val = 0x165503E0 },
         { .reg = 0x00009888, .val = 0x169503E0 },
         { .reg = 0x00009888, .val = 0x16B503E0 },
         { .reg = 0x00009888, .val = 0x16D503E0 },
         { .reg = 0x00009888, .val = 0x045CC000 },
         { .reg = 0x00009888, .val = 0x083D8000 },
         { .reg = 0x00009888, .val = 0x04584000 },
         { .reg = 0x00009888, .val = 0x085B4000 },
         { .reg = 0x00009888, .val = 0x0A5B8000 },
         { .reg = 0x00009888, .val = 0x0E1F00A8 },
         { .reg = 0x00009888, .val = 0x08384000 },
         { .reg = 0x00009888, .val = 0x0A384000 },
         { .reg = 0x00009888, .val = 0x0C388000 },
         { .reg = 0x00009888, .val = 0x0439A000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x0C3A8000 },
         { .reg = 0x00009888, .val = 0x08138000 },
         { .reg = 0x00009888, .val = 0x06141000 },
         { .reg = 0x00009888, .val = 0x041500C3 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x0A338000 },
         { .reg = 0x00009888, .val = 0x06342000 },
         { .reg = 0x00009888, .val = 0x0435C300 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x0C538000 },
         { .reg = 0x00009888, .val = 0x06544000 },
         { .reg = 0x00009888, .val = 0x065500C3 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x00DC8000 },
         { .reg = 0x00009888, .val = 0x02DC4000 },
         { .reg = 0x00009888, .val = 0x02BD8000 },
         { .reg = 0x00009888, .val = 0x00D88000 },
         { .reg = 0x00009888, .val = 0x02DB4000 },
         { .reg = 0x00009888, .val = 0x04DB8000 },
         { .reg = 0x00009888, .val = 0x0C9FA000 },
         { .reg = 0x00009888, .val = 0x0E9F0002 },
         { .reg = 0x00009888, .val = 0x02B84000 },
         { .reg = 0x00009888, .val = 0x04B84000 },
         { .reg = 0x00009888, .val = 0x06B88000 },
         { .reg = 0x00009888, .val = 0x00B98000 },
         { .reg = 0x00009888, .val = 0x02B9A000 },
         { .reg = 0x00009888, .val = 0x06BA8000 },
         { .reg = 0x00009888, .val = 0x02938000 },
         { .reg = 0x00009888, .val = 0x04942000 },
         { .reg = 0x00009888, .val = 0x0095C300 },
         { .reg = 0x00009888, .val = 0x10950000 },
         { .reg = 0x00009888, .val = 0x04B38000 },
         { .reg = 0x00009888, .val = 0x04B44000 },
         { .reg = 0x00009888, .val = 0x02B500C3 },
         { .reg = 0x00009888, .val = 0x10B50000 },
         { .reg = 0x00009888, .val = 0x06D38000 },
         { .reg = 0x00009888, .val = 0x04D48000 },
         { .reg = 0x00009888, .val = 0x02D5C300 },
         { .reg = 0x00009888, .val = 0x10D50000 },
         { .reg = 0x00009888, .val = 0x03888000 },
         { .reg = 0x00009888, .val = 0x05888000 },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x238B3500 },
         { .reg = 0x00009888, .val = 0x258B0005 },
         { .reg = 0x00009888, .val = 0x038C4000 },
         { .reg = 0x00009888, .val = 0x058C4000 },
         { .reg = 0x00009888, .val = 0x078C4000 },
         { .reg = 0x00009888, .val = 0x018D8000 },
         { .reg = 0x00009888, .val = 0x038DA000 },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x2185000A },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800C40 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41801482 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00001000 },
         { .reg = 0x0000E558, .val = 0x00003002 },
         { .reg = 0x0000E658, .val = 0x00005004 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00050012 },
         { .reg = 0x0000E55C, .val = 0x00052051 },
         { .reg = 0x0000E65C, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__compute_extra__avg_gpu_core_frequency__max,bdw__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,bdw__compute_extra__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 307, 28, percentage_max_float,bdw__compute_extra__fpu1_active_adjusted__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_vme_pipe_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Media Vme Pipe metric set";
   query->symbol_name = "VMEPipe";
   query->guid = "e1743ca0-7fc8-410b-a066-de7bbb9280b7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x14100812 },
         { .reg = 0x00009888, .val = 0x14125800 },
         { .reg = 0x00009888, .val = 0x161200C0 },
         { .reg = 0x00009888, .val = 0x14300812 },
         { .reg = 0x00009888, .val = 0x14325800 },
         { .reg = 0x00009888, .val = 0x163200C0 },
         { .reg = 0x00009888, .val = 0x005C4000 },
         { .reg = 0x00009888, .val = 0x065C8000 },
         { .reg = 0x00009888, .val = 0x085CC000 },
         { .reg = 0x00009888, .val = 0x0A5CC000 },
         { .reg = 0x00009888, .val = 0x0C5CC000 },
         { .reg = 0x00009888, .val = 0x003D8000 },
         { .reg = 0x00009888, .val = 0x0E3D8000 },
         { .reg = 0x00009888, .val = 0x183D2800 },
         { .reg = 0x00009888, .val = 0x00584000 },
         { .reg = 0x00009888, .val = 0x06588000 },
         { .reg = 0x00009888, .val = 0x0858C000 },
         { .reg = 0x00009888, .val = 0x005B4000 },
         { .reg = 0x00009888, .val = 0x0E5B4000 },
         { .reg = 0x00009888, .val = 0x185B9400 },
         { .reg = 0x00009888, .val = 0x1A5B002A },
         { .reg = 0x00009888, .val = 0x0C1F0800 },
         { .reg = 0x00009888, .val = 0x0E1FAA00 },
         { .reg = 0x00009888, .val = 0x101F002A },
         { .reg = 0x00009888, .val = 0x00384000 },
         { .reg = 0x00009888, .val = 0x0E384000 },
         { .reg = 0x00009888, .val = 0x16384000 },
         { .reg = 0x00009888, .val = 0x18380155 },
         { .reg = 0x00009888, .val = 0x00392000 },
         { .reg = 0x00009888, .val = 0x06398000 },
         { .reg = 0x00009888, .val = 0x0839A000 },
         { .reg = 0x00009888, .val = 0x0A39A000 },
         { .reg = 0x00009888, .val = 0x0C39A000 },
         { .reg = 0x00009888, .val = 0x00100047 },
         { .reg = 0x00009888, .val = 0x06101A80 },
         { .reg = 0x00009888, .val = 0x10100000 },
         { .reg = 0x00009888, .val = 0x0810C000 },
         { .reg = 0x00009888, .val = 0x0811C000 },
         { .reg = 0x00009888, .val = 0x08126151 },
         { .reg = 0x00009888, .val = 0x10120000 },
         { .reg = 0x00009888, .val = 0x00134000 },
         { .reg = 0x00009888, .val = 0x0E134000 },
         { .reg = 0x00009888, .val = 0x161300A0 },
         { .reg = 0x00009888, .val = 0x0A301AC7 },
         { .reg = 0x00009888, .val = 0x10300000 },
         { .reg = 0x00009888, .val = 0x0C30C000 },
         { .reg = 0x00009888, .val = 0x0C31C000 },
         { .reg = 0x00009888, .val = 0x0C326151 },
         { .reg = 0x00009888, .val = 0x10320000 },
         { .reg = 0x00009888, .val = 0x16332A00 },
         { .reg = 0x00009888, .val = 0x18330001 },
         { .reg = 0x00009888, .val = 0x018A8000 },
         { .reg = 0x00009888, .val = 0x0F8A8000 },
         { .reg = 0x00009888, .val = 0x198A8000 },
         { .reg = 0x00009888, .val = 0x1B8A2AA0 },
         { .reg = 0x00009888, .val = 0x238B0020 },
         { .reg = 0x00009888, .val = 0x258B5550 },
         { .reg = 0x00009888, .val = 0x278B0001 },
         { .reg = 0x00009888, .val = 0x1F850080 },
         { .reg = 0x00009888, .val = 0x2185AAA0 },
         { .reg = 0x00009888, .val = 0x23850002 },
         { .reg = 0x00009888, .val = 0x01834000 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x1B830015 },
         { .reg = 0x00009888, .val = 0x01844000 },
         { .reg = 0x00009888, .val = 0x07848000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x11804000 },
         { .reg = 0x00009888, .val = 0x17808000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3D800800 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x43800002 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45800884 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47800002 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00100030 },
         { .reg = 0x00002774, .val = 0x0000FFF9 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFFC },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFF3 },
         { .reg = 0x00002788, .val = 0x00100180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__vme_pipe__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__vme_pipe__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__vme_pipe__avg_gpu_core_frequency__max,bdw__vme_pipe__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__vme_pipe__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,bdw__vme_pipe__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 40, percentage_max_float,bdw__vme_pipe__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 44, percentage_max_float,bdw__vme_pipe__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 48, percentage_max_float,bdw__vme_pipe__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 52, percentage_max_float,bdw__vme_pipe__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 308, 56, percentage_max_float,bdw__vme_pipe__vme_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Gpu Rings Busyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "0a9eb7be-feee-4275-a139-6d9cedf0fdb0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x1AF00100 },
         { .reg = 0x00009888, .val = 0x118B0000 },
         { .reg = 0x00009888, .val = 0x11850008 },
         { .reg = 0x00009888, .val = 0x17830100 },
         { .reg = 0x00009888, .val = 0x1A700100 },
         { .reg = 0x00009888, .val = 0x1D940040 },
         { .reg = 0x00009888, .val = 0x02F00085 },
         { .reg = 0x00009888, .val = 0x10F00000 },
         { .reg = 0x00009888, .val = 0x24F00000 },
         { .reg = 0x00009888, .val = 0x078B0003 },
         { .reg = 0x00009888, .val = 0x238B0400 },
         { .reg = 0x00009888, .val = 0x258B0000 },
         { .reg = 0x00009888, .val = 0x058C8000 },
         { .reg = 0x00009888, .val = 0x038D2000 },
         { .reg = 0x00009888, .val = 0x03850500 },
         { .reg = 0x00009888, .val = 0x1F858800 },
         { .reg = 0x00009888, .val = 0x2185000A },
         { .reg = 0x00009888, .val = 0x05834055 },
         { .reg = 0x00009888, .val = 0x11830000 },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x0B838000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x03844000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x04708500 },
         { .reg = 0x00009888, .val = 0x10700000 },
         { .reg = 0x00009888, .val = 0x24700000 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x4D801000 },
         { .reg = 0x00009888, .val = 0x3F800000 },
         { .reg = 0x00009888, .val = 0x4F800004 },
         { .reg = 0x00009888, .val = 0x418014A0 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0007C000 },
         { .reg = 0x00002774, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__gpu_busyness__avg_gpu_core_frequency__max,bdw__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 309, 24, percentage_max_float,bdw__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 28, percentage_max_float,bdw__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 32, percentage_max_float,bdw__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 312, 36, percentage_max_float,bdw__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 40, percentage_max_float,bdw__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 44, percentage_max_float,bdw__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "d6de6f55-e526-4f79-a6a6-d7315c09044e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x198B0000 },
         { .reg = 0x00009888, .val = 0x078B0066 },
         { .reg = 0x00009888, .val = 0x118B0000 },
         { .reg = 0x00009888, .val = 0x258B0000 },
         { .reg = 0x00009888, .val = 0x21850008 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__test_oa__avg_gpu_core_frequency__max,bdw__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,bdw__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,bdw__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,bdw__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,bdw__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,bdw__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,bdw__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,bdw__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,bdw__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,bdw__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bdw_register_stc__pma_stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "STC_PmaStall";
   query->guid = "e713f347-953e-4d8c-b02f-6be31df2db2b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x0C1F0001 },
         { .reg = 0x00009888, .val = 0x001F0015 },
         { .reg = 0x00009888, .val = 0x041F4AC0 },
         { .reg = 0x00009888, .val = 0x061F03D8 },
         { .reg = 0x00009888, .val = 0x0E1F0000 },
         { .reg = 0x00009888, .val = 0x018A8000 },
         { .reg = 0x00009888, .val = 0x0F8A8000 },
         { .reg = 0x00009888, .val = 0x198A8000 },
         { .reg = 0x00009888, .val = 0x1B8A00A0 },
         { .reg = 0x00009888, .val = 0x238B0020 },
         { .reg = 0x00009888, .val = 0x258B0550 },
         { .reg = 0x00009888, .val = 0x1F850080 },
         { .reg = 0x00009888, .val = 0x21850AA0 },
         { .reg = 0x00009888, .val = 0x01834000 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x01844000 },
         { .reg = 0x00009888, .val = 0x07848000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B844000 },
         { .reg = 0x00009888, .val = 0x11804000 },
         { .reg = 0x00009888, .val = 0x17808000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B804000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3D800000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x43800000 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45800000 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x008000E1 },
         { .reg = 0x00002774, .val = 0x001FFFE0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bdw__stc__pma_stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bdw__stc__pma_stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bdw__stc__pma_stall__avg_gpu_core_frequency__max,bdw__stc__pma_stall__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bdw__stc__pma_stall__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bdw__stc__pma_stall__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bdw__stc__pma_stall__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bdw__stc__pma_stall__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bdw__stc__pma_stall__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bdw__stc__pma_stall__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bdw__stc__pma_stall__cs_threads__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 80, percentage_max_float,bdw__stc__pma_stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_bdw(struct intel_perf_config *perf)
{
   bdw_register_render_basic_counter_query(perf);
   bdw_register_compute_basic_counter_query(perf);
   bdw_register_render_pipe_profile_counter_query(perf);
   bdw_register_memory_reads_counter_query(perf);
   bdw_register_memory_writes_counter_query(perf);
   bdw_register_compute_extended_counter_query(perf);
   bdw_register_compute_l3_cache_counter_query(perf);
   bdw_register_data_port_reads_coalescing_counter_query(perf);
   bdw_register_data_port_writes_coalescing_counter_query(perf);
   bdw_register_hdc_and_sf_counter_query(perf);
   bdw_register_l3_1_counter_query(perf);
   bdw_register_l3_2_counter_query(perf);
   bdw_register_l3_3_counter_query(perf);
   bdw_register_l3_4_counter_query(perf);
   bdw_register_rasterizer_and_pixel_backend_counter_query(perf);
   bdw_register_sampler_1_counter_query(perf);
   bdw_register_sampler_2_counter_query(perf);
   bdw_register_tdl_1_counter_query(perf);
   bdw_register_tdl_2_counter_query(perf);
   bdw_register_compute_extra_counter_query(perf);
   bdw_register_vme_pipe_counter_query(perf);
   bdw_register_gpu_busyness_counter_query(perf);
   bdw_register_test_oa_counter_query(perf);
   bdw_register_stc__pma_stall_counter_query(perf);
}


static void
chv_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 50);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x59800000 },
         { .reg = 0x00009888, .val = 0x59800001 },
         { .reg = 0x00009888, .val = 0x285A0006 },
         { .reg = 0x00009888, .val = 0x2C110014 },
         { .reg = 0x00009888, .val = 0x2E110000 },
         { .reg = 0x00009888, .val = 0x2C310014 },
         { .reg = 0x00009888, .val = 0x2E310000 },
         { .reg = 0x00009888, .val = 0x2B8303DF },
         { .reg = 0x00009888, .val = 0x3580024F },
         { .reg = 0x00009888, .val = 0x00580888 },
         { .reg = 0x00009888, .val = 0x1E5A0015 },
         { .reg = 0x00009888, .val = 0x205A0014 },
         { .reg = 0x00009888, .val = 0x045A0000 },
         { .reg = 0x00009888, .val = 0x025A0000 },
         { .reg = 0x00009888, .val = 0x02180500 },
         { .reg = 0x00009888, .val = 0x00190555 },
         { .reg = 0x00009888, .val = 0x021D0500 },
         { .reg = 0x00009888, .val = 0x021F0A00 },
         { .reg = 0x00009888, .val = 0x00380444 },
         { .reg = 0x00009888, .val = 0x02390500 },
         { .reg = 0x00009888, .val = 0x003A0666 },
         { .reg = 0x00009888, .val = 0x00100111 },
         { .reg = 0x00009888, .val = 0x06110030 },
         { .reg = 0x00009888, .val = 0x0A110031 },
         { .reg = 0x00009888, .val = 0x0E110046 },
         { .reg = 0x00009888, .val = 0x04110000 },
         { .reg = 0x00009888, .val = 0x00110000 },
         { .reg = 0x00009888, .val = 0x00130111 },
         { .reg = 0x00009888, .val = 0x00300444 },
         { .reg = 0x00009888, .val = 0x08310030 },
         { .reg = 0x00009888, .val = 0x0C310031 },
         { .reg = 0x00009888, .val = 0x10310046 },
         { .reg = 0x00009888, .val = 0x04310000 },
         { .reg = 0x00009888, .val = 0x00310000 },
         { .reg = 0x00009888, .val = 0x00330444 },
         { .reg = 0x00009888, .val = 0x038A0A00 },
         { .reg = 0x00009888, .val = 0x018B0FFF },
         { .reg = 0x00009888, .val = 0x038B0A00 },
         { .reg = 0x00009888, .val = 0x01855000 },
         { .reg = 0x00009888, .val = 0x03850055 },
         { .reg = 0x00009888, .val = 0x13830021 },
         { .reg = 0x00009888, .val = 0x15830020 },
         { .reg = 0x00009888, .val = 0x1783002F },
         { .reg = 0x00009888, .val = 0x1983002E },
         { .reg = 0x00009888, .val = 0x1B83002D },
         { .reg = 0x00009888, .val = 0x1D83002C },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01840555 },
         { .reg = 0x00009888, .val = 0x03840500 },
         { .reg = 0x00009888, .val = 0x23800074 },
         { .reg = 0x00009888, .val = 0x2580007D },
         { .reg = 0x00009888, .val = 0x05800000 },
         { .reg = 0x00009888, .val = 0x01805000 },
         { .reg = 0x00009888, .val = 0x03800055 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x01875000 },
         { .reg = 0x00009888, .val = 0x03870055 },
         { .reg = 0x00009888, .val = 0x418000AA },
         { .reg = 0x00009888, .val = 0x4380000A },
         { .reg = 0x00009888, .val = 0x45800000 },
         { .reg = 0x00009888, .val = 0x4780000A },
         { .reg = 0x00009888, .val = 0x49800000 },
         { .reg = 0x00009888, .val = 0x4B800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x55800000 },
         { .reg = 0x00009888, .val = 0x57800000 },
         { .reg = 0x00009888, .val = 0x59800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__render_basic__avg_gpu_core_frequency__max,chv__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,chv__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,chv__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,chv__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,chv__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,chv__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,chv__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,chv__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,chv__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,chv__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,chv__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,chv__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,chv__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,chv__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,chv__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,chv__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,chv__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,chv__render_basic__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,chv__render_basic__sampler0_busy__read);

      intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,chv__render_basic__sampler1_busy__read);

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,chv__render_basic__samplers_busy__read);

      intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,chv__render_basic__sampler0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,chv__render_basic__sampler1_bottleneck__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,chv__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,chv__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,chv__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,chv__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 139, 168, NULL,chv__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 176, NULL,chv__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 184, NULL,chv__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 192, NULL,chv__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 200, NULL,chv__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 75, 208, chv__render_basic__slm_bytes_read__max,chv__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 216, chv__render_basic__slm_bytes_written__max,chv__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 224, NULL,chv__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 232, NULL,chv__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 145, 240, NULL,chv__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 248, chv__render_basic__l3_sampler_throughput__max,chv__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 256, chv__render_basic__l3_shader_throughput__max,chv__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 264, NULL,chv__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 272, chv__render_basic__gti_vf_throughput__max,chv__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 280, chv__render_basic__gti_depth_throughput__max,chv__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 288, chv__render_basic__gti_rcc_throughput__max,chv__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 296, chv__render_basic__gti_l3_throughput__max,chv__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 304, chv__render_basic__gti_hdc_lookups_throughput__max,chv__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 312, chv__render_basic__gti_read_throughput__max,chv__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 320, chv__render_basic__gti_write_throughput__max,chv__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 328, percentage_max_float,chv__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "f522a89c-ecd1-4522-8331-3383c54af5f5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x59800000 },
         { .reg = 0x00009888, .val = 0x59800001 },
         { .reg = 0x00009888, .val = 0x2E5800E0 },
         { .reg = 0x00009888, .val = 0x2E3800E0 },
         { .reg = 0x00009888, .val = 0x3580024F },
         { .reg = 0x00009888, .val = 0x3D800140 },
         { .reg = 0x00009888, .val = 0x08580042 },
         { .reg = 0x00009888, .val = 0x0C580040 },
         { .reg = 0x00009888, .val = 0x1058004C },
         { .reg = 0x00009888, .val = 0x1458004B },
         { .reg = 0x00009888, .val = 0x04580000 },
         { .reg = 0x00009888, .val = 0x00580000 },
         { .reg = 0x00009888, .val = 0x00195555 },
         { .reg = 0x00009888, .val = 0x06380042 },
         { .reg = 0x00009888, .val = 0x0A380040 },
         { .reg = 0x00009888, .val = 0x0E38004C },
         { .reg = 0x00009888, .val = 0x1238004B },
         { .reg = 0x00009888, .val = 0x04380000 },
         { .reg = 0x00009888, .val = 0x00384444 },
         { .reg = 0x00009888, .val = 0x003A5555 },
         { .reg = 0x00009888, .val = 0x018BFFFF },
         { .reg = 0x00009888, .val = 0x01845555 },
         { .reg = 0x00009888, .val = 0x17800074 },
         { .reg = 0x00009888, .val = 0x1980007D },
         { .reg = 0x00009888, .val = 0x1B80007C },
         { .reg = 0x00009888, .val = 0x1D8000B6 },
         { .reg = 0x00009888, .val = 0x1F8000B7 },
         { .reg = 0x00009888, .val = 0x05800000 },
         { .reg = 0x00009888, .val = 0x03800000 },
         { .reg = 0x00009888, .val = 0x418000AA },
         { .reg = 0x00009888, .val = 0x438000AA },
         { .reg = 0x00009888, .val = 0x45800000 },
         { .reg = 0x00009888, .val = 0x47800000 },
         { .reg = 0x00009888, .val = 0x4980012A },
         { .reg = 0x00009888, .val = 0x4B80012A },
         { .reg = 0x00009888, .val = 0x4D80012A },
         { .reg = 0x00009888, .val = 0x4F80012A },
         { .reg = 0x00009888, .val = 0x518001CE },
         { .reg = 0x00009888, .val = 0x538001CE },
         { .reg = 0x00009888, .val = 0x5580000E },
         { .reg = 0x00009888, .val = 0x59800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__compute_basic__avg_gpu_core_frequency__max,chv__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,chv__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,chv__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, chv__compute_basic__eu_avg_ipc_rate__max,chv__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,chv__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,chv__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,chv__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,chv__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,chv__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,chv__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,chv__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,chv__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,chv__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,chv__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,chv__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, chv__compute_basic__slm_bytes_read__max,chv__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, chv__compute_basic__slm_bytes_written__max,chv__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,chv__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,chv__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, chv__compute_basic__l3_shader_throughput__max,chv__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,chv__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, chv__compute_basic__typed_bytes_read__max,chv__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, chv__compute_basic__typed_bytes_written__max,chv__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, chv__compute_basic__untyped_bytes_read__max,chv__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, chv__compute_basic__untyped_bytes_written__max,chv__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, chv__compute_basic__gti_read_throughput__max,chv__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, chv__compute_basic__gti_write_throughput__max,chv__compute_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_uint64(query, 325, 280, chv__compute_basic__gti_ring_throughput__max,chv__compute_basic__gti_ring_throughput__read);

      intel_perf_query_add_counter_float(query, 326, 288, percentage_max_float,chv__compute_basic__gti_ro_stall__read);

      intel_perf_query_add_counter_float(query, 327, 292, percentage_max_float,chv__compute_basic__gti_rw_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "a9ccc03d-a943-4e6b-9cd6-13e063075927";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x59800000 },
         { .reg = 0x00009888, .val = 0x59800001 },
         { .reg = 0x00009888, .val = 0x261E0000 },
         { .reg = 0x00009888, .val = 0x281F000F },
         { .reg = 0x00009888, .val = 0x2817001A },
         { .reg = 0x00009888, .val = 0x2791001F },
         { .reg = 0x00009888, .val = 0x27880019 },
         { .reg = 0x00009888, .val = 0x2D890000 },
         { .reg = 0x00009888, .val = 0x278A0007 },
         { .reg = 0x00009888, .val = 0x298D001F },
         { .reg = 0x00009888, .val = 0x278E0020 },
         { .reg = 0x00009888, .val = 0x2B8F0012 },
         { .reg = 0x00009888, .val = 0x29900000 },
         { .reg = 0x00009888, .val = 0x00184000 },
         { .reg = 0x00009888, .val = 0x02181000 },
         { .reg = 0x00009888, .val = 0x02194000 },
         { .reg = 0x00009888, .val = 0x141E0002 },
         { .reg = 0x00009888, .val = 0x041E0000 },
         { .reg = 0x00009888, .val = 0x001E0000 },
         { .reg = 0x00009888, .val = 0x221F0015 },
         { .reg = 0x00009888, .val = 0x041F0000 },
         { .reg = 0x00009888, .val = 0x001F4000 },
         { .reg = 0x00009888, .val = 0x021F0000 },
         { .reg = 0x00009888, .val = 0x023A8000 },
         { .reg = 0x00009888, .val = 0x0213C000 },
         { .reg = 0x00009888, .val = 0x02164000 },
         { .reg = 0x00009888, .val = 0x24170012 },
         { .reg = 0x00009888, .val = 0x04170000 },
         { .reg = 0x00009888, .val = 0x07910005 },
         { .reg = 0x00009888, .val = 0x05910000 },
         { .reg = 0x00009888, .val = 0x01911500 },
         { .reg = 0x00009888, .val = 0x03910501 },
         { .reg = 0x00009888, .val = 0x0D880002 },
         { .reg = 0x00009888, .val = 0x1D880003 },
         { .reg = 0x00009888, .val = 0x05880000 },
         { .reg = 0x00009888, .val = 0x0B890032 },
         { .reg = 0x00009888, .val = 0x1B890031 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890040 },
         { .reg = 0x00009888, .val = 0x03890040 },
         { .reg = 0x00009888, .val = 0x098A0000 },
         { .reg = 0x00009888, .val = 0x198A0004 },
         { .reg = 0x00009888, .val = 0x058A0000 },
         { .reg = 0x00009888, .val = 0x018A8050 },
         { .reg = 0x00009888, .val = 0x038A2050 },
         { .reg = 0x00009888, .val = 0x018B95A9 },
         { .reg = 0x00009888, .val = 0x038BE5A9 },
         { .reg = 0x00009888, .val = 0x018C1500 },
         { .reg = 0x00009888, .val = 0x038C0501 },
         { .reg = 0x00009888, .val = 0x178D0015 },
         { .reg = 0x00009888, .val = 0x058D0000 },
         { .reg = 0x00009888, .val = 0x138E0004 },
         { .reg = 0x00009888, .val = 0x218E000C },
         { .reg = 0x00009888, .val = 0x058E0000 },
         { .reg = 0x00009888, .val = 0x018E0500 },
         { .reg = 0x00009888, .val = 0x038E0101 },
         { .reg = 0x00009888, .val = 0x0F8F0027 },
         { .reg = 0x00009888, .val = 0x058F0000 },
         { .reg = 0x00009888, .val = 0x018F0000 },
         { .reg = 0x00009888, .val = 0x038F0001 },
         { .reg = 0x00009888, .val = 0x11900013 },
         { .reg = 0x00009888, .val = 0x1F900017 },
         { .reg = 0x00009888, .val = 0x05900000 },
         { .reg = 0x00009888, .val = 0x01900100 },
         { .reg = 0x00009888, .val = 0x03900001 },
         { .reg = 0x00009888, .val = 0x01845555 },
         { .reg = 0x00009888, .val = 0x03845555 },
         { .reg = 0x00009888, .val = 0x418000AA },
         { .reg = 0x00009888, .val = 0x438000AA },
         { .reg = 0x00009888, .val = 0x458000AA },
         { .reg = 0x00009888, .val = 0x478000AA },
         { .reg = 0x00009888, .val = 0x4980018C },
         { .reg = 0x00009888, .val = 0x4B80014B },
         { .reg = 0x00009888, .val = 0x4D800128 },
         { .reg = 0x00009888, .val = 0x4F80012A },
         { .reg = 0x00009888, .val = 0x51800187 },
         { .reg = 0x00009888, .val = 0x5380014B },
         { .reg = 0x00009888, .val = 0x55800149 },
         { .reg = 0x00009888, .val = 0x5780010A },
         { .reg = 0x00009888, .val = 0x59800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__render_pipe_profile__avg_gpu_core_frequency__max,chv__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,chv__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,chv__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,chv__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,chv__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,chv__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,chv__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,chv__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 144, NULL,chv__render_pipe_profile__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,chv__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,chv__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, chv__render_pipe_profile__slm_bytes_read__max,chv__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, chv__render_pipe_profile__slm_bytes_written__max,chv__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,chv__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,chv__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, chv__render_pipe_profile__l3_shader_throughput__max,chv__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,chv__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 216, NULL,chv__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 220, NULL,chv__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 224, NULL,chv__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 228, NULL,chv__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 232, NULL,chv__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 236, NULL,chv__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 240, NULL,chv__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 244, NULL,chv__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 248, NULL,chv__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 252, NULL,chv__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 256, NULL,chv__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 260, NULL,chv__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 264, NULL,chv__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 268, NULL,chv__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 272, NULL,chv__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 276, NULL,chv__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "33af8252-7a51-4aa3-b0ba-1b946f209d7b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x105C0232 },
         { .reg = 0x00009888, .val = 0x10580232 },
         { .reg = 0x00009888, .val = 0x10380232 },
         { .reg = 0x00009888, .val = 0x10DC0232 },
         { .reg = 0x00009888, .val = 0x10D80232 },
         { .reg = 0x00009888, .val = 0x10B80232 },
         { .reg = 0x00009888, .val = 0x118E4400 },
         { .reg = 0x00009888, .val = 0x025C6080 },
         { .reg = 0x00009888, .val = 0x045C004B },
         { .reg = 0x00009888, .val = 0x005C8000 },
         { .reg = 0x00009888, .val = 0x00582080 },
         { .reg = 0x00009888, .val = 0x0258004B },
         { .reg = 0x00009888, .val = 0x025B4000 },
         { .reg = 0x00009888, .val = 0x045B4000 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F00AA },
         { .reg = 0x00009888, .val = 0x04386080 },
         { .reg = 0x00009888, .val = 0x0638404B },
         { .reg = 0x00009888, .val = 0x02384000 },
         { .reg = 0x00009888, .val = 0x08384000 },
         { .reg = 0x00009888, .val = 0x0A380000 },
         { .reg = 0x00009888, .val = 0x0C380000 },
         { .reg = 0x00009888, .val = 0x00398000 },
         { .reg = 0x00009888, .val = 0x0239A000 },
         { .reg = 0x00009888, .val = 0x0439A000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x0CDC25C1 },
         { .reg = 0x00009888, .val = 0x0ADCC000 },
         { .reg = 0x00009888, .val = 0x0AD825C1 },
         { .reg = 0x00009888, .val = 0x18DB4000 },
         { .reg = 0x00009888, .val = 0x1ADB0001 },
         { .reg = 0x00009888, .val = 0x0E9F8000 },
         { .reg = 0x00009888, .val = 0x109F02AA },
         { .reg = 0x00009888, .val = 0x0EB825C1 },
         { .reg = 0x00009888, .val = 0x18B80154 },
         { .reg = 0x00009888, .val = 0x0AB9A000 },
         { .reg = 0x00009888, .val = 0x0CB9A000 },
         { .reg = 0x00009888, .val = 0x0EB9A000 },
         { .reg = 0x00009888, .val = 0x0D88C000 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x258BAA05 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x198C5400 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x098DC000 },
         { .reg = 0x00009888, .val = 0x0B8DA000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x098E05C0 },
         { .reg = 0x00009888, .val = 0x058E0000 },
         { .reg = 0x00009888, .val = 0x198F0020 },
         { .reg = 0x00009888, .val = 0x2185AA0A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x19835000 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x09848000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x19808000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x51800040 },
         { .reg = 0x00009888, .val = 0x43800400 },
         { .reg = 0x00009888, .val = 0x45800800 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47800C62 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F801042 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x418014A4 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FFF7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__hdc_and_sf__avg_gpu_core_frequency__max,chv__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__hdc_and_sf__slm_bytes_read__max,chv__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__hdc_and_sf__slm_bytes_written__max,chv__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__hdc_and_sf__l3_shader_throughput__max,chv__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,chv__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 238, 244, percentage_max_float,chv__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,chv__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 252, percentage_max_float,chv__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 241, 256, percentage_max_float,chv__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 242, 260, percentage_max_float,chv__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 243, 264, percentage_max_float,chv__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 268, percentage_max_float,chv__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "78f52900-5317-4417-8067-966fbf215a1f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x10BF03DA },
         { .reg = 0x00009888, .val = 0x14BF0001 },
         { .reg = 0x00009888, .val = 0x12980340 },
         { .reg = 0x00009888, .val = 0x12990340 },
         { .reg = 0x00009888, .val = 0x0CBF1187 },
         { .reg = 0x00009888, .val = 0x0EBF1205 },
         { .reg = 0x00009888, .val = 0x00BF0500 },
         { .reg = 0x00009888, .val = 0x02BF042B },
         { .reg = 0x00009888, .val = 0x04BF002C },
         { .reg = 0x00009888, .val = 0x0CDAC000 },
         { .reg = 0x00009888, .val = 0x0EDAC000 },
         { .reg = 0x00009888, .val = 0x00DA8000 },
         { .reg = 0x00009888, .val = 0x02DAC000 },
         { .reg = 0x00009888, .val = 0x04DA4000 },
         { .reg = 0x00009888, .val = 0x04983400 },
         { .reg = 0x00009888, .val = 0x10980000 },
         { .reg = 0x00009888, .val = 0x06990034 },
         { .reg = 0x00009888, .val = 0x10990000 },
         { .reg = 0x00009888, .val = 0x0C9DC000 },
         { .reg = 0x00009888, .val = 0x0E9DC000 },
         { .reg = 0x00009888, .val = 0x009D8000 },
         { .reg = 0x00009888, .val = 0x029DC000 },
         { .reg = 0x00009888, .val = 0x049D4000 },
         { .reg = 0x00009888, .val = 0x109F02A8 },
         { .reg = 0x00009888, .val = 0x0C9FA000 },
         { .reg = 0x00009888, .val = 0x0E9F00BA },
         { .reg = 0x00009888, .val = 0x0CB88000 },
         { .reg = 0x00009888, .val = 0x0CB95000 },
         { .reg = 0x00009888, .val = 0x0EB95000 },
         { .reg = 0x00009888, .val = 0x00B94000 },
         { .reg = 0x00009888, .val = 0x02B95000 },
         { .reg = 0x00009888, .val = 0x04B91000 },
         { .reg = 0x00009888, .val = 0x06B92000 },
         { .reg = 0x00009888, .val = 0x0CBA4000 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x03888000 },
         { .reg = 0x00009888, .val = 0x05888000 },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x09888000 },
         { .reg = 0x00009888, .val = 0x0B888000 },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x258B800A },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B5500 },
         { .reg = 0x00009888, .val = 0x198C4000 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x038C4000 },
         { .reg = 0x00009888, .val = 0x058C4000 },
         { .reg = 0x00009888, .val = 0x078C4000 },
         { .reg = 0x00009888, .val = 0x098C4000 },
         { .reg = 0x00009888, .val = 0x0B8C4000 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x018D8000 },
         { .reg = 0x00009888, .val = 0x038DA000 },
         { .reg = 0x00009888, .val = 0x058DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2185800A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x1B830154 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x45800000 },
         { .reg = 0x00009888, .val = 0x47800000 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800060 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__l3_1__avg_gpu_core_frequency__max,chv__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__l3_1__slm_bytes_read__max,chv__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__l3_1__slm_bytes_written__max,chv__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__l3_1__l3_shader_throughput__max,chv__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 245, 240, percentage_max_float,chv__l3_1__l31_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 246, 244, percentage_max_float,chv__l3_1__l31_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 247, 248, percentage_max_float,chv__l3_1__l31_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 248, 252, percentage_max_float,chv__l3_1__l31_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,chv__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_2";
   query->symbol_name = "L3_2";
   query->guid = "0db4fe4a-2648-4064-bd6a-89c06d0c27b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x103F03DA },
         { .reg = 0x00009888, .val = 0x143F0001 },
         { .reg = 0x00009888, .val = 0x12180340 },
         { .reg = 0x00009888, .val = 0x12190340 },
         { .reg = 0x00009888, .val = 0x0C3F1187 },
         { .reg = 0x00009888, .val = 0x0E3F1205 },
         { .reg = 0x00009888, .val = 0x003F0500 },
         { .reg = 0x00009888, .val = 0x023F042B },
         { .reg = 0x00009888, .val = 0x043F002C },
         { .reg = 0x00009888, .val = 0x0C5AC000 },
         { .reg = 0x00009888, .val = 0x0E5AC000 },
         { .reg = 0x00009888, .val = 0x005A8000 },
         { .reg = 0x00009888, .val = 0x025AC000 },
         { .reg = 0x00009888, .val = 0x045A4000 },
         { .reg = 0x00009888, .val = 0x04183400 },
         { .reg = 0x00009888, .val = 0x10180000 },
         { .reg = 0x00009888, .val = 0x06190034 },
         { .reg = 0x00009888, .val = 0x10190000 },
         { .reg = 0x00009888, .val = 0x0C1DC000 },
         { .reg = 0x00009888, .val = 0x0E1DC000 },
         { .reg = 0x00009888, .val = 0x001D8000 },
         { .reg = 0x00009888, .val = 0x021DC000 },
         { .reg = 0x00009888, .val = 0x041D4000 },
         { .reg = 0x00009888, .val = 0x101F02A8 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F00BA },
         { .reg = 0x00009888, .val = 0x0C388000 },
         { .reg = 0x00009888, .val = 0x0C395000 },
         { .reg = 0x00009888, .val = 0x0E395000 },
         { .reg = 0x00009888, .val = 0x00394000 },
         { .reg = 0x00009888, .val = 0x02395000 },
         { .reg = 0x00009888, .val = 0x04391000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x0C3A4000 },
         { .reg = 0x00009888, .val = 0x1B8AA800 },
         { .reg = 0x00009888, .val = 0x1D8A0002 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x258B4005 },
         { .reg = 0x00009888, .val = 0x278B0015 },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x2185800A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x1B830154 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x45800000 },
         { .reg = 0x00009888, .val = 0x47800000 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800060 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__l3_2__avg_gpu_core_frequency__max,chv__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__l3_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__l3_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__l3_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__l3_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__l3_2__slm_bytes_read__max,chv__l3_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__l3_2__slm_bytes_written__max,chv__l3_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__l3_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__l3_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__l3_2__l3_shader_throughput__max,chv__l3_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__l3_2__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,chv__l3_2__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,chv__l3_2__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,chv__l3_2__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,chv__l3_2__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,chv__l3_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_3";
   query->symbol_name = "L3_3";
   query->guid = "0de6539e-33b4-4aee-83c4-9ab45a579b94";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x121B0340 },
         { .reg = 0x00009888, .val = 0x103F0274 },
         { .reg = 0x00009888, .val = 0x123F0000 },
         { .reg = 0x00009888, .val = 0x129B0340 },
         { .reg = 0x00009888, .val = 0x10BF0274 },
         { .reg = 0x00009888, .val = 0x12BF0000 },
         { .reg = 0x00009888, .val = 0x041B3400 },
         { .reg = 0x00009888, .val = 0x101B0000 },
         { .reg = 0x00009888, .val = 0x045C8000 },
         { .reg = 0x00009888, .val = 0x0A3D4000 },
         { .reg = 0x00009888, .val = 0x003F0080 },
         { .reg = 0x00009888, .val = 0x023F0793 },
         { .reg = 0x00009888, .val = 0x043F0014 },
         { .reg = 0x00009888, .val = 0x04588000 },
         { .reg = 0x00009888, .val = 0x005A8000 },
         { .reg = 0x00009888, .val = 0x025AC000 },
         { .reg = 0x00009888, .val = 0x045A4000 },
         { .reg = 0x00009888, .val = 0x0A5B4000 },
         { .reg = 0x00009888, .val = 0x001D8000 },
         { .reg = 0x00009888, .val = 0x021DC000 },
         { .reg = 0x00009888, .val = 0x041D4000 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F002A },
         { .reg = 0x00009888, .val = 0x0A384000 },
         { .reg = 0x00009888, .val = 0x00394000 },
         { .reg = 0x00009888, .val = 0x02395000 },
         { .reg = 0x00009888, .val = 0x04399000 },
         { .reg = 0x00009888, .val = 0x069B0034 },
         { .reg = 0x00009888, .val = 0x109B0000 },
         { .reg = 0x00009888, .val = 0x06DC4000 },
         { .reg = 0x00009888, .val = 0x0CBD4000 },
         { .reg = 0x00009888, .val = 0x0CBF0981 },
         { .reg = 0x00009888, .val = 0x0EBF0A0F },
         { .reg = 0x00009888, .val = 0x06D84000 },
         { .reg = 0x00009888, .val = 0x0CDAC000 },
         { .reg = 0x00009888, .val = 0x0EDAC000 },
         { .reg = 0x00009888, .val = 0x0CDB4000 },
         { .reg = 0x00009888, .val = 0x0C9DC000 },
         { .reg = 0x00009888, .val = 0x0E9DC000 },
         { .reg = 0x00009888, .val = 0x109F02A8 },
         { .reg = 0x00009888, .val = 0x0E9F0080 },
         { .reg = 0x00009888, .val = 0x0CB84000 },
         { .reg = 0x00009888, .val = 0x0CB95000 },
         { .reg = 0x00009888, .val = 0x0EB95000 },
         { .reg = 0x00009888, .val = 0x06B92000 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x258B8009 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x198C4000 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2185800A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x1B830154 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x45800C00 },
         { .reg = 0x00009888, .val = 0x47800C63 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F8014A5 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800045 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__l3_3__avg_gpu_core_frequency__max,chv__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__l3_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__l3_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__l3_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__l3_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__l3_3__slm_bytes_read__max,chv__l3_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__l3_3__slm_bytes_written__max,chv__l3_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__l3_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__l3_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__l3_3__l3_shader_throughput__max,chv__l3_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__l3_3__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 253, 240, percentage_max_float,chv__l3_3__l30_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 254, 244, percentage_max_float,chv__l3_3__l31_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 255, 248, percentage_max_float,chv__l3_3__l31_bank3_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 256, 252, percentage_max_float,chv__l3_3__l30_bank3_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,chv__l3_3__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_l3_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_4";
   query->symbol_name = "L3_4";
   query->guid = "be74c9d6-268f-4d7f-b2e8-8d91d4441883";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x121A0340 },
         { .reg = 0x00009888, .val = 0x103F0017 },
         { .reg = 0x00009888, .val = 0x123F0020 },
         { .reg = 0x00009888, .val = 0x129A0340 },
         { .reg = 0x00009888, .val = 0x10BF0017 },
         { .reg = 0x00009888, .val = 0x12BF0020 },
         { .reg = 0x00009888, .val = 0x041A3400 },
         { .reg = 0x00009888, .val = 0x101A0000 },
         { .reg = 0x00009888, .val = 0x043B8000 },
         { .reg = 0x00009888, .val = 0x0A3E0010 },
         { .reg = 0x00009888, .val = 0x003F0200 },
         { .reg = 0x00009888, .val = 0x023F0113 },
         { .reg = 0x00009888, .val = 0x043F0014 },
         { .reg = 0x00009888, .val = 0x02592000 },
         { .reg = 0x00009888, .val = 0x005A8000 },
         { .reg = 0x00009888, .val = 0x025AC000 },
         { .reg = 0x00009888, .val = 0x045A4000 },
         { .reg = 0x00009888, .val = 0x0A1C8000 },
         { .reg = 0x00009888, .val = 0x001D8000 },
         { .reg = 0x00009888, .val = 0x021DC000 },
         { .reg = 0x00009888, .val = 0x041D4000 },
         { .reg = 0x00009888, .val = 0x0A1E8000 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F001A },
         { .reg = 0x00009888, .val = 0x00394000 },
         { .reg = 0x00009888, .val = 0x02395000 },
         { .reg = 0x00009888, .val = 0x04391000 },
         { .reg = 0x00009888, .val = 0x069A0034 },
         { .reg = 0x00009888, .val = 0x109A0000 },
         { .reg = 0x00009888, .val = 0x06BB4000 },
         { .reg = 0x00009888, .val = 0x0ABE0040 },
         { .reg = 0x00009888, .val = 0x0CBF0984 },
         { .reg = 0x00009888, .val = 0x0EBF0A02 },
         { .reg = 0x00009888, .val = 0x02D94000 },
         { .reg = 0x00009888, .val = 0x0CDAC000 },
         { .reg = 0x00009888, .val = 0x0EDAC000 },
         { .reg = 0x00009888, .val = 0x0C9C0400 },
         { .reg = 0x00009888, .val = 0x0C9DC000 },
         { .reg = 0x00009888, .val = 0x0E9DC000 },
         { .reg = 0x00009888, .val = 0x0C9E0400 },
         { .reg = 0x00009888, .val = 0x109F02A8 },
         { .reg = 0x00009888, .val = 0x0E9F0040 },
         { .reg = 0x00009888, .val = 0x0CB95000 },
         { .reg = 0x00009888, .val = 0x0EB95000 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x258B8009 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x198C4000 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2185800A },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x1B830154 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x45800800 },
         { .reg = 0x00009888, .val = 0x47800842 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F801084 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800044 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__l3_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__l3_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__l3_4__avg_gpu_core_frequency__max,chv__l3_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__l3_4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__l3_4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__l3_4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__l3_4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__l3_4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__l3_4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__l3_4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__l3_4__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__l3_4__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__l3_4__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__l3_4__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__l3_4__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__l3_4__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__l3_4__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__l3_4__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__l3_4__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__l3_4__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__l3_4__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__l3_4__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__l3_4__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__l3_4__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__l3_4__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__l3_4__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__l3_4__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__l3_4__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__l3_4__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__l3_4__slm_bytes_read__max,chv__l3_4__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__l3_4__slm_bytes_written__max,chv__l3_4__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__l3_4__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__l3_4__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__l3_4__l3_shader_throughput__max,chv__l3_4__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__l3_4__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 257, 240, percentage_max_float,chv__l3_4__l30_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 258, 244, percentage_max_float,chv__l3_4__l31_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 259, 248, percentage_max_float,chv__l3_4__l31_bank2_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 260, 252, percentage_max_float,chv__l3_4__l30_bank2_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,chv__l3_4__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 46);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "31bc1ff3-8d09-4497-9d79-59c4f943b502";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x143B000E },
         { .reg = 0x00009888, .val = 0x043C55C0 },
         { .reg = 0x00009888, .val = 0x0A1E0280 },
         { .reg = 0x00009888, .val = 0x0C1E0408 },
         { .reg = 0x00009888, .val = 0x10390000 },
         { .reg = 0x00009888, .val = 0x12397A1F },
         { .reg = 0x00009888, .val = 0x14BB000E },
         { .reg = 0x00009888, .val = 0x04BC5000 },
         { .reg = 0x00009888, .val = 0x0A9E0296 },
         { .reg = 0x00009888, .val = 0x0C9E0008 },
         { .reg = 0x00009888, .val = 0x10B90000 },
         { .reg = 0x00009888, .val = 0x12B97A1F },
         { .reg = 0x00009888, .val = 0x063B0042 },
         { .reg = 0x00009888, .val = 0x103B0000 },
         { .reg = 0x00009888, .val = 0x083C0000 },
         { .reg = 0x00009888, .val = 0x0A3E0040 },
         { .reg = 0x00009888, .val = 0x043F8000 },
         { .reg = 0x00009888, .val = 0x02594000 },
         { .reg = 0x00009888, .val = 0x045A8000 },
         { .reg = 0x00009888, .val = 0x0C1C0400 },
         { .reg = 0x00009888, .val = 0x041D8000 },
         { .reg = 0x00009888, .val = 0x081E02C0 },
         { .reg = 0x00009888, .val = 0x0E1E0000 },
         { .reg = 0x00009888, .val = 0x0C1FA800 },
         { .reg = 0x00009888, .val = 0x0E1F0260 },
         { .reg = 0x00009888, .val = 0x101F0014 },
         { .reg = 0x00009888, .val = 0x003905E0 },
         { .reg = 0x00009888, .val = 0x06390BC0 },
         { .reg = 0x00009888, .val = 0x02390018 },
         { .reg = 0x00009888, .val = 0x04394000 },
         { .reg = 0x00009888, .val = 0x04BB0042 },
         { .reg = 0x00009888, .val = 0x10BB0000 },
         { .reg = 0x00009888, .val = 0x02BC05C0 },
         { .reg = 0x00009888, .val = 0x08BC0000 },
         { .reg = 0x00009888, .val = 0x0ABE0004 },
         { .reg = 0x00009888, .val = 0x02BF8000 },
         { .reg = 0x00009888, .val = 0x02D91000 },
         { .reg = 0x00009888, .val = 0x02DA8000 },
         { .reg = 0x00009888, .val = 0x089C8000 },
         { .reg = 0x00009888, .val = 0x029D8000 },
         { .reg = 0x00009888, .val = 0x089E8000 },
         { .reg = 0x00009888, .val = 0x0E9E0000 },
         { .reg = 0x00009888, .val = 0x0E9FA806 },
         { .reg = 0x00009888, .val = 0x109F0142 },
         { .reg = 0x00009888, .val = 0x08B90617 },
         { .reg = 0x00009888, .val = 0x0AB90BE0 },
         { .reg = 0x00009888, .val = 0x02B94000 },
         { .reg = 0x00009888, .val = 0x0D88F000 },
         { .reg = 0x00009888, .val = 0x0F88000C },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x09888000 },
         { .reg = 0x00009888, .val = 0x018A8000 },
         { .reg = 0x00009888, .val = 0x0F8A8000 },
         { .reg = 0x00009888, .val = 0x1B8A2800 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x238B52A0 },
         { .reg = 0x00009888, .val = 0x258B6A95 },
         { .reg = 0x00009888, .val = 0x278B0029 },
         { .reg = 0x00009888, .val = 0x178C2000 },
         { .reg = 0x00009888, .val = 0x198C1500 },
         { .reg = 0x00009888, .val = 0x1B8C0014 },
         { .reg = 0x00009888, .val = 0x078C4000 },
         { .reg = 0x00009888, .val = 0x098C4000 },
         { .reg = 0x00009888, .val = 0x098DA000 },
         { .reg = 0x00009888, .val = 0x0B8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x038D8000 },
         { .reg = 0x00009888, .val = 0x058D2000 },
         { .reg = 0x00009888, .val = 0x1F85AA80 },
         { .reg = 0x00009888, .val = 0x2185AAAA },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x01834000 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0184C000 },
         { .reg = 0x00009888, .val = 0x0784C000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x1180C000 },
         { .reg = 0x00009888, .val = 0x1780C000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x4D800444 },
         { .reg = 0x00009888, .val = 0x3D800000 },
         { .reg = 0x00009888, .val = 0x4F804000 },
         { .reg = 0x00009888, .val = 0x43801080 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45800084 },
         { .reg = 0x00009888, .val = 0x53800044 },
         { .reg = 0x00009888, .val = 0x47801080 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x3F800000 },
         { .reg = 0x00009888, .val = 0x41800840 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00006000 },
         { .reg = 0x00002774, .val = 0x0000F3FF },
         { .reg = 0x00002778, .val = 0x00001800 },
         { .reg = 0x0000277C, .val = 0x0000FCFF },
         { .reg = 0x00002780, .val = 0x00000600 },
         { .reg = 0x00002784, .val = 0x0000FF3F },
         { .reg = 0x00002788, .val = 0x00000180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000060 },
         { .reg = 0x00002794, .val = 0x0000FFF3 },
         { .reg = 0x00002798, .val = 0x00000018 },
         { .reg = 0x0000279C, .val = 0x0000FFFC },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__rasterizer_and_pixel_backend__slm_bytes_read__max,chv__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__rasterizer_and_pixel_backend__slm_bytes_written__max,chv__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__rasterizer_and_pixel_backend__l3_shader_throughput__max,chv__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 240, percentage_max_float,chv__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 262, 244, percentage_max_float,chv__rasterizer_and_pixel_backend__pixel_data1_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 328, 248, percentage_max_float,chv__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 264, 252, percentage_max_float,chv__rasterizer_and_pixel_backend__rasterizer1_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 265, 256, percentage_max_float,chv__rasterizer_and_pixel_backend__rasterizer1_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 260, percentage_max_float,chv__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 264, percentage_max_float,chv__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 268, percentage_max_float,chv__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 269, 272, percentage_max_float,chv__rasterizer_and_pixel_backend__pixel_values1_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 270, 276, percentage_max_float,chv__rasterizer_and_pixel_backend__ps_output1_available__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 280, percentage_max_float,chv__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler_1";
   query->symbol_name = "Sampler_1";
   query->guid = "05450fec-bb5c-4b0a-8995-e03631168a34";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x18921400 },
         { .reg = 0x00009888, .val = 0x149500AB },
         { .reg = 0x00009888, .val = 0x18B21400 },
         { .reg = 0x00009888, .val = 0x14B500AB },
         { .reg = 0x00009888, .val = 0x18D21400 },
         { .reg = 0x00009888, .val = 0x14D500AB },
         { .reg = 0x00009888, .val = 0x0CDC8000 },
         { .reg = 0x00009888, .val = 0x0EDC4000 },
         { .reg = 0x00009888, .val = 0x02DCC000 },
         { .reg = 0x00009888, .val = 0x04DCC000 },
         { .reg = 0x00009888, .val = 0x1ABD00A0 },
         { .reg = 0x00009888, .val = 0x0ABD8000 },
         { .reg = 0x00009888, .val = 0x0CD88000 },
         { .reg = 0x00009888, .val = 0x0ED84000 },
         { .reg = 0x00009888, .val = 0x04D88000 },
         { .reg = 0x00009888, .val = 0x1ADB0050 },
         { .reg = 0x00009888, .val = 0x04DB8000 },
         { .reg = 0x00009888, .val = 0x06DB8000 },
         { .reg = 0x00009888, .val = 0x08DB8000 },
         { .reg = 0x00009888, .val = 0x0ADB4000 },
         { .reg = 0x00009888, .val = 0x109F02A0 },
         { .reg = 0x00009888, .val = 0x0C9FA000 },
         { .reg = 0x00009888, .val = 0x0E9F00AA },
         { .reg = 0x00009888, .val = 0x18B82500 },
         { .reg = 0x00009888, .val = 0x02B88000 },
         { .reg = 0x00009888, .val = 0x04B84000 },
         { .reg = 0x00009888, .val = 0x06B84000 },
         { .reg = 0x00009888, .val = 0x08B84000 },
         { .reg = 0x00009888, .val = 0x0AB84000 },
         { .reg = 0x00009888, .val = 0x0CB88000 },
         { .reg = 0x00009888, .val = 0x0CB98000 },
         { .reg = 0x00009888, .val = 0x0EB9A000 },
         { .reg = 0x00009888, .val = 0x00B98000 },
         { .reg = 0x00009888, .val = 0x02B9A000 },
         { .reg = 0x00009888, .val = 0x04B9A000 },
         { .reg = 0x00009888, .val = 0x06B92000 },
         { .reg = 0x00009888, .val = 0x1ABA0200 },
         { .reg = 0x00009888, .val = 0x02BA8000 },
         { .reg = 0x00009888, .val = 0x0CBA8000 },
         { .reg = 0x00009888, .val = 0x04908000 },
         { .reg = 0x00009888, .val = 0x04918000 },
         { .reg = 0x00009888, .val = 0x04927300 },
         { .reg = 0x00009888, .val = 0x10920000 },
         { .reg = 0x00009888, .val = 0x1893000A },
         { .reg = 0x00009888, .val = 0x0A934000 },
         { .reg = 0x00009888, .val = 0x0A946000 },
         { .reg = 0x00009888, .val = 0x0C959000 },
         { .reg = 0x00009888, .val = 0x0E950098 },
         { .reg = 0x00009888, .val = 0x10950000 },
         { .reg = 0x00009888, .val = 0x04B04000 },
         { .reg = 0x00009888, .val = 0x04B14000 },
         { .reg = 0x00009888, .val = 0x04B20073 },
         { .reg = 0x00009888, .val = 0x10B20000 },
         { .reg = 0x00009888, .val = 0x04B38000 },
         { .reg = 0x00009888, .val = 0x06B38000 },
         { .reg = 0x00009888, .val = 0x08B34000 },
         { .reg = 0x00009888, .val = 0x04B4C000 },
         { .reg = 0x00009888, .val = 0x02B59890 },
         { .reg = 0x00009888, .val = 0x10B50000 },
         { .reg = 0x00009888, .val = 0x06D04000 },
         { .reg = 0x00009888, .val = 0x06D14000 },
         { .reg = 0x00009888, .val = 0x06D20073 },
         { .reg = 0x00009888, .val = 0x10D20000 },
         { .reg = 0x00009888, .val = 0x18D30020 },
         { .reg = 0x00009888, .val = 0x02D38000 },
         { .reg = 0x00009888, .val = 0x0CD34000 },
         { .reg = 0x00009888, .val = 0x0AD48000 },
         { .reg = 0x00009888, .val = 0x04D42000 },
         { .reg = 0x00009888, .val = 0x0ED59000 },
         { .reg = 0x00009888, .val = 0x00D59800 },
         { .reg = 0x00009888, .val = 0x10D50000 },
         { .reg = 0x00009888, .val = 0x0F88000E },
         { .reg = 0x00009888, .val = 0x03888000 },
         { .reg = 0x00009888, .val = 0x05888000 },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x09888000 },
         { .reg = 0x00009888, .val = 0x0B888000 },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B5500 },
         { .reg = 0x00009888, .val = 0x258B000A },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x038C4000 },
         { .reg = 0x00009888, .val = 0x058C4000 },
         { .reg = 0x00009888, .val = 0x078C4000 },
         { .reg = 0x00009888, .val = 0x098C4000 },
         { .reg = 0x00009888, .val = 0x0B8C4000 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x0D8D8000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x018D8000 },
         { .reg = 0x00009888, .val = 0x038DA000 },
         { .reg = 0x00009888, .val = 0x058DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x2185000A },
         { .reg = 0x00009888, .val = 0x1B830150 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D848000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D808000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47801021 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800C64 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800C02 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__sampler_1__avg_gpu_core_frequency__max,chv__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__sampler_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__sampler_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__sampler_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__sampler_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__sampler_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__sampler_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__sampler_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__sampler_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__sampler_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__sampler_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__sampler_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__sampler_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__sampler_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__sampler_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__sampler_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__sampler_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__sampler_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__sampler_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__sampler_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__sampler_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__sampler_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__sampler_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__sampler_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__sampler_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__sampler_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__sampler_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__sampler_1__slm_bytes_read__max,chv__sampler_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__sampler_1__slm_bytes_written__max,chv__sampler_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__sampler_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__sampler_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__sampler_1__l3_shader_throughput__max,chv__sampler_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__sampler_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 271, 240, percentage_max_float,chv__sampler_1__sampler11_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 272, 244, percentage_max_float,chv__sampler_1__sampler12_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 273, 248, percentage_max_float,chv__sampler_1__sampler10_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 274, 252, percentage_max_float,chv__sampler_1__sampler12_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 275, 256, percentage_max_float,chv__sampler_1__sampler10_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 276, 260, percentage_max_float,chv__sampler_1__sampler11_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,chv__sampler_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_sampler_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler_2";
   query->symbol_name = "Sampler_2";
   query->guid = "883c8a56-8767-4de8-beec-a99462c6674b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x18121400 },
         { .reg = 0x00009888, .val = 0x141500AB },
         { .reg = 0x00009888, .val = 0x18321400 },
         { .reg = 0x00009888, .val = 0x143500AB },
         { .reg = 0x00009888, .val = 0x18521400 },
         { .reg = 0x00009888, .val = 0x145500AB },
         { .reg = 0x00009888, .val = 0x0C5C8000 },
         { .reg = 0x00009888, .val = 0x0E5C4000 },
         { .reg = 0x00009888, .val = 0x025CC000 },
         { .reg = 0x00009888, .val = 0x045CC000 },
         { .reg = 0x00009888, .val = 0x1A3D00A0 },
         { .reg = 0x00009888, .val = 0x0A3D8000 },
         { .reg = 0x00009888, .val = 0x0C588000 },
         { .reg = 0x00009888, .val = 0x0E584000 },
         { .reg = 0x00009888, .val = 0x04588000 },
         { .reg = 0x00009888, .val = 0x1A5B0050 },
         { .reg = 0x00009888, .val = 0x045B8000 },
         { .reg = 0x00009888, .val = 0x065B8000 },
         { .reg = 0x00009888, .val = 0x085B8000 },
         { .reg = 0x00009888, .val = 0x0A5B4000 },
         { .reg = 0x00009888, .val = 0x101F02A0 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F00AA },
         { .reg = 0x00009888, .val = 0x18382500 },
         { .reg = 0x00009888, .val = 0x02388000 },
         { .reg = 0x00009888, .val = 0x04384000 },
         { .reg = 0x00009888, .val = 0x06384000 },
         { .reg = 0x00009888, .val = 0x08384000 },
         { .reg = 0x00009888, .val = 0x0A384000 },
         { .reg = 0x00009888, .val = 0x0C388000 },
         { .reg = 0x00009888, .val = 0x0C398000 },
         { .reg = 0x00009888, .val = 0x0E39A000 },
         { .reg = 0x00009888, .val = 0x00398000 },
         { .reg = 0x00009888, .val = 0x0239A000 },
         { .reg = 0x00009888, .val = 0x0439A000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x1A3A0200 },
         { .reg = 0x00009888, .val = 0x023A8000 },
         { .reg = 0x00009888, .val = 0x0C3A8000 },
         { .reg = 0x00009888, .val = 0x04108000 },
         { .reg = 0x00009888, .val = 0x04118000 },
         { .reg = 0x00009888, .val = 0x04127300 },
         { .reg = 0x00009888, .val = 0x10120000 },
         { .reg = 0x00009888, .val = 0x1813000A },
         { .reg = 0x00009888, .val = 0x0A134000 },
         { .reg = 0x00009888, .val = 0x0A146000 },
         { .reg = 0x00009888, .val = 0x0C159000 },
         { .reg = 0x00009888, .val = 0x0E150098 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x04304000 },
         { .reg = 0x00009888, .val = 0x04314000 },
         { .reg = 0x00009888, .val = 0x04320073 },
         { .reg = 0x00009888, .val = 0x10320000 },
         { .reg = 0x00009888, .val = 0x04338000 },
         { .reg = 0x00009888, .val = 0x06338000 },
         { .reg = 0x00009888, .val = 0x08334000 },
         { .reg = 0x00009888, .val = 0x0434C000 },
         { .reg = 0x00009888, .val = 0x02359890 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x06504000 },
         { .reg = 0x00009888, .val = 0x06514000 },
         { .reg = 0x00009888, .val = 0x06520073 },
         { .reg = 0x00009888, .val = 0x10520000 },
         { .reg = 0x00009888, .val = 0x18530020 },
         { .reg = 0x00009888, .val = 0x02538000 },
         { .reg = 0x00009888, .val = 0x0C534000 },
         { .reg = 0x00009888, .val = 0x0A548000 },
         { .reg = 0x00009888, .val = 0x04542000 },
         { .reg = 0x00009888, .val = 0x0E559000 },
         { .reg = 0x00009888, .val = 0x00559800 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x1B8AA000 },
         { .reg = 0x00009888, .val = 0x1D8A0002 },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x278B0015 },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x258B0005 },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x2185000A },
         { .reg = 0x00009888, .val = 0x1B830150 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0D848000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x07844000 },
         { .reg = 0x00009888, .val = 0x1D808000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x17804000 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47801021 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800C64 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x41800C02 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__sampler_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__sampler_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__sampler_2__avg_gpu_core_frequency__max,chv__sampler_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__sampler_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__sampler_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__sampler_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__sampler_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__sampler_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__sampler_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__sampler_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__sampler_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__sampler_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__sampler_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__sampler_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__sampler_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__sampler_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__sampler_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__sampler_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__sampler_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__sampler_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__sampler_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__sampler_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__sampler_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__sampler_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__sampler_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__sampler_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__sampler_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__sampler_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__sampler_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__sampler_2__slm_bytes_read__max,chv__sampler_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__sampler_2__slm_bytes_written__max,chv__sampler_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__sampler_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__sampler_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__sampler_2__l3_shader_throughput__max,chv__sampler_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__sampler_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,chv__sampler_2__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,chv__sampler_2__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,chv__sampler_2__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,chv__sampler_2__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,chv__sampler_2__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,chv__sampler_2__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,chv__sampler_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 48);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "eb97e523-d9ac-48a9-b7f8-9cc909ddbf14";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x16154D60 },
         { .reg = 0x00009888, .val = 0x16352E60 },
         { .reg = 0x00009888, .val = 0x16554D60 },
         { .reg = 0x00009888, .val = 0x16950000 },
         { .reg = 0x00009888, .val = 0x16B50000 },
         { .reg = 0x00009888, .val = 0x16D50000 },
         { .reg = 0x00009888, .val = 0x005C8000 },
         { .reg = 0x00009888, .val = 0x045CC000 },
         { .reg = 0x00009888, .val = 0x065C4000 },
         { .reg = 0x00009888, .val = 0x083D8000 },
         { .reg = 0x00009888, .val = 0x0A3D8000 },
         { .reg = 0x00009888, .val = 0x0458C000 },
         { .reg = 0x00009888, .val = 0x025B8000 },
         { .reg = 0x00009888, .val = 0x085B4000 },
         { .reg = 0x00009888, .val = 0x0A5B4000 },
         { .reg = 0x00009888, .val = 0x0C5B8000 },
         { .reg = 0x00009888, .val = 0x0C1FA000 },
         { .reg = 0x00009888, .val = 0x0E1F00AA },
         { .reg = 0x00009888, .val = 0x02384000 },
         { .reg = 0x00009888, .val = 0x04388000 },
         { .reg = 0x00009888, .val = 0x06388000 },
         { .reg = 0x00009888, .val = 0x08384000 },
         { .reg = 0x00009888, .val = 0x0A384000 },
         { .reg = 0x00009888, .val = 0x0C384000 },
         { .reg = 0x00009888, .val = 0x00398000 },
         { .reg = 0x00009888, .val = 0x0239A000 },
         { .reg = 0x00009888, .val = 0x0439A000 },
         { .reg = 0x00009888, .val = 0x06392000 },
         { .reg = 0x00009888, .val = 0x043A8000 },
         { .reg = 0x00009888, .val = 0x063A8000 },
         { .reg = 0x00009888, .val = 0x08138000 },
         { .reg = 0x00009888, .val = 0x0A138000 },
         { .reg = 0x00009888, .val = 0x06143000 },
         { .reg = 0x00009888, .val = 0x0415CFC7 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x02338000 },
         { .reg = 0x00009888, .val = 0x0C338000 },
         { .reg = 0x00009888, .val = 0x04342000 },
         { .reg = 0x00009888, .val = 0x06344000 },
         { .reg = 0x00009888, .val = 0x0035C700 },
         { .reg = 0x00009888, .val = 0x063500CF },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x04538000 },
         { .reg = 0x00009888, .val = 0x06538000 },
         { .reg = 0x00009888, .val = 0x0454C000 },
         { .reg = 0x00009888, .val = 0x0255CFC7 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x06DC8000 },
         { .reg = 0x00009888, .val = 0x08DC4000 },
         { .reg = 0x00009888, .val = 0x0CDCC000 },
         { .reg = 0x00009888, .val = 0x0EDCC000 },
         { .reg = 0x00009888, .val = 0x1ABD00A8 },
         { .reg = 0x00009888, .val = 0x0CD8C000 },
         { .reg = 0x00009888, .val = 0x0ED84000 },
         { .reg = 0x00009888, .val = 0x0EDB8000 },
         { .reg = 0x00009888, .val = 0x18DB0800 },
         { .reg = 0x00009888, .val = 0x1ADB0254 },
         { .reg = 0x00009888, .val = 0x0E9FAA00 },
         { .reg = 0x00009888, .val = 0x109F02AA },
         { .reg = 0x00009888, .val = 0x0EB84000 },
         { .reg = 0x00009888, .val = 0x16B84000 },
         { .reg = 0x00009888, .val = 0x18B8156A },
         { .reg = 0x00009888, .val = 0x06B98000 },
         { .reg = 0x00009888, .val = 0x08B9A000 },
         { .reg = 0x00009888, .val = 0x0AB9A000 },
         { .reg = 0x00009888, .val = 0x0CB9A000 },
         { .reg = 0x00009888, .val = 0x0EB9A000 },
         { .reg = 0x00009888, .val = 0x18BAA000 },
         { .reg = 0x00009888, .val = 0x1ABA0002 },
         { .reg = 0x00009888, .val = 0x16934000 },
         { .reg = 0x00009888, .val = 0x1893000A },
         { .reg = 0x00009888, .val = 0x0A947000 },
         { .reg = 0x00009888, .val = 0x0C95C5C1 },
         { .reg = 0x00009888, .val = 0x0E9500C3 },
         { .reg = 0x00009888, .val = 0x10950000 },
         { .reg = 0x00009888, .val = 0x0EB38000 },
         { .reg = 0x00009888, .val = 0x16B30040 },
         { .reg = 0x00009888, .val = 0x18B30020 },
         { .reg = 0x00009888, .val = 0x06B48000 },
         { .reg = 0x00009888, .val = 0x08B41000 },
         { .reg = 0x00009888, .val = 0x0AB48000 },
         { .reg = 0x00009888, .val = 0x06B5C500 },
         { .reg = 0x00009888, .val = 0x08B500C3 },
         { .reg = 0x00009888, .val = 0x0EB5C100 },
         { .reg = 0x00009888, .val = 0x10B50000 },
         { .reg = 0x00009888, .val = 0x16D31500 },
         { .reg = 0x00009888, .val = 0x08D4E000 },
         { .reg = 0x00009888, .val = 0x08D5C100 },
         { .reg = 0x00009888, .val = 0x0AD5C3C5 },
         { .reg = 0x00009888, .val = 0x10D50000 },
         { .reg = 0x00009888, .val = 0x0D88F800 },
         { .reg = 0x00009888, .val = 0x0F88000F },
         { .reg = 0x00009888, .val = 0x038A8000 },
         { .reg = 0x00009888, .val = 0x058A8000 },
         { .reg = 0x00009888, .val = 0x078A8000 },
         { .reg = 0x00009888, .val = 0x098A8000 },
         { .reg = 0x00009888, .val = 0x0B8A8000 },
         { .reg = 0x00009888, .val = 0x0D8A8000 },
         { .reg = 0x00009888, .val = 0x258BAAA5 },
         { .reg = 0x00009888, .val = 0x278B002A },
         { .reg = 0x00009888, .val = 0x238B2A80 },
         { .reg = 0x00009888, .val = 0x0F8C4000 },
         { .reg = 0x00009888, .val = 0x178C2000 },
         { .reg = 0x00009888, .val = 0x198C5500 },
         { .reg = 0x00009888, .val = 0x1B8C0015 },
         { .reg = 0x00009888, .val = 0x078D8000 },
         { .reg = 0x00009888, .val = 0x098DA000 },
         { .reg = 0x00009888, .val = 0x0B8DA000 },
         { .reg = 0x00009888, .val = 0x0D8DA000 },
         { .reg = 0x00009888, .val = 0x0F8DA000 },
         { .reg = 0x00009888, .val = 0x2185AAAA },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0784C000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x1780C000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x43800C42 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45800063 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x47800800 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F8014A4 },
         { .reg = 0x00009888, .val = 0x41801042 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x0000FE7F },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFBF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFF7 },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FFF9 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__tdl_1__avg_gpu_core_frequency__max,chv__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__tdl_1__slm_bytes_read__max,chv__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__tdl_1__slm_bytes_written__max,chv__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__tdl_1__l3_shader_throughput__max,chv__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 283, 240, percentage_max_float,chv__tdl_1__non_ps_thread11_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 284, 244, percentage_max_float,chv__tdl_1__ps_thread10_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 285, 248, percentage_max_float,chv__tdl_1__non_ps_thread10_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 286, 252, percentage_max_float,chv__tdl_1__ps_thread12_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 287, 256, percentage_max_float,chv__tdl_1__non_ps_thread12_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 288, 260, percentage_max_float,chv__tdl_1__ps_thread11_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 264, percentage_max_float,chv__tdl_1__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 268, percentage_max_float,chv__tdl_1__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 272, percentage_max_float,chv__tdl_1__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 276, percentage_max_float,chv__tdl_1__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 280, percentage_max_float,chv__tdl_1__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 284, percentage_max_float,chv__tdl_1__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 288, percentage_max_float,chv__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 48);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "dff6158e-8409-452c-be76-91c9946330bd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x16150000 },
         { .reg = 0x00009888, .val = 0x16350000 },
         { .reg = 0x00009888, .val = 0x16550000 },
         { .reg = 0x00009888, .val = 0x16952E60 },
         { .reg = 0x00009888, .val = 0x16B54D60 },
         { .reg = 0x00009888, .val = 0x16D52E60 },
         { .reg = 0x00009888, .val = 0x065C8000 },
         { .reg = 0x00009888, .val = 0x085CC000 },
         { .reg = 0x00009888, .val = 0x0A5CC000 },
         { .reg = 0x00009888, .val = 0x0C5C4000 },
         { .reg = 0x00009888, .val = 0x0E3D8000 },
         { .reg = 0x00009888, .val = 0x183DA000 },
         { .reg = 0x00009888, .val = 0x06588000 },
         { .reg = 0x00009888, .val = 0x08588000 },
         { .reg = 0x00009888, .val = 0x0A584000 },
         { .reg = 0x00009888, .val = 0x0E5B4000 },
         { .reg = 0x00009888, .val = 0x185B5800 },
         { .reg = 0x00009888, .val = 0x1A5B000A },
         { .reg = 0x00009888, .val = 0x0E1FAA00 },
         { .reg = 0x00009888, .val = 0x101F02AA },
         { .reg = 0x00009888, .val = 0x0E384000 },
         { .reg = 0x00009888, .val = 0x16384000 },
         { .reg = 0x00009888, .val = 0x18382A55 },
         { .reg = 0x00009888, .val = 0x06398000 },
         { .reg = 0x00009888, .val = 0x0839A000 },
         { .reg = 0x00009888, .val = 0x0A39A000 },
         { .reg = 0x00009888, .val = 0x0C39A000 },
         { .reg = 0x00009888, .val = 0x0E39A000 },
         { .reg = 0x00009888, .val = 0x1A3A02A0 },
         { .reg = 0x00009888, .val = 0x0E138000 },
         { .reg = 0x00009888, .val = 0x16130500 },
         { .reg = 0x00009888, .val = 0x06148000 },
         { .reg = 0x00009888, .val = 0x08146000 },
         { .reg = 0x00009888, .val = 0x0615C100 },
         { .reg = 0x00009888, .val = 0x0815C500 },
         { .reg = 0x00009888, .val = 0x0A1500C3 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x16335040 },
         { .reg = 0x00009888, .val = 0x08349000 },
         { .reg = 0x00009888, .val = 0x0A341000 },
         { .reg = 0x00009888, .val = 0x083500C1 },
         { .reg = 0x00009888, .val = 0x0A35C500 },
         { .reg = 0x00009888, .val = 0x0C3500C3 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x1853002A },
         { .reg = 0x00009888, .val = 0x0A54E000 },
         { .reg = 0x00009888, .val = 0x0C55C500 },
         { .reg = 0x00009888, .val = 0x0E55C1C3 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x00DC8000 },
         { .reg = 0x00009888, .val = 0x02DCC000 },
         { .reg = 0x00009888, .val = 0x04DC4000 },
         { .reg = 0x00009888, .val = 0x04BD8000 },
         { .reg = 0x00009888, .val = 0x06BD8000 },
         { .reg = 0x00009888, .val = 0x02D8C000 },
         { .reg = 0x00009888, .val = 0x02DB8000 },
         { .reg = 0x00009888, .val = 0x04DB4000 },
         { .reg = 0x00009888, .val = 0x06DB4000 },
         { .reg = 0x00009888, .val = 0x08DB8000 },
         { .reg = 0x00009888, .val = 0x0C9FA000 },
         { .reg = 0x00009888, .val = 0x0E9F00AA },
         { .reg = 0x00009888, .val = 0x02B84000 },
         { .reg = 0x00009888, .val = 0x04B84000 },
         { .reg = 0x00009888, .val = 0x06B84000 },
         { .reg = 0x00009888, .val = 0x08B84000 },
         { .reg = 0x00009888, .val = 0x0AB88000 },
         { .reg = 0x00009888, .val = 0x0CB88000 },
         { .reg = 0x00009888, .val = 0x00B98000 },
         { .reg = 0x00009888, .val = 0x02B9A000 },
         { .reg = 0x00009888, .val = 0x04B9A000 },
         { .reg = 0x00009888, .val = 0x06B92000 },
         { .reg = 0x00009888, .val = 0x0ABA8000 },
         { .reg = 0x00009888, .val = 0x0CBA8000 },
         { .reg = 0x00009888, .val = 0x04938000 },
         { .reg = 0x00009888, .val = 0x06938000 },
         { .reg = 0x00009888, .val = 0x0494C000 },
         { .reg = 0x00009888, .val = 0x0295CFC7 },
         { .reg = 0x00009888, .val = 0x10950000 },
         { .reg = 0x00009888, .val = 0x02B38000 },
         { .reg = 0x00009888, .val = 0x08B38000 },
         { .reg = 0x00009888, .val = 0x04B42000 },
         { .reg = 0x00009888, .val = 0x06B41000 },
         { .reg = 0x00009888, .val = 0x00B5C700 },
         { .reg = 0x00009888, .val = 0x04B500CF },
         { .reg = 0x00009888, .val = 0x10B50000 },
         { .reg = 0x00009888, .val = 0x0AD38000 },
         { .reg = 0x00009888, .val = 0x0CD38000 },
         { .reg = 0x00009888, .val = 0x06D46000 },
         { .reg = 0x00009888, .val = 0x04D5C700 },
         { .reg = 0x00009888, .val = 0x06D500CF },
         { .reg = 0x00009888, .val = 0x10D50000 },
         { .reg = 0x00009888, .val = 0x03888000 },
         { .reg = 0x00009888, .val = 0x05888000 },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x09888000 },
         { .reg = 0x00009888, .val = 0x0B888000 },
         { .reg = 0x00009888, .val = 0x0D880400 },
         { .reg = 0x00009888, .val = 0x0F8A8000 },
         { .reg = 0x00009888, .val = 0x198A8000 },
         { .reg = 0x00009888, .val = 0x1B8AAAA0 },
         { .reg = 0x00009888, .val = 0x1D8A0002 },
         { .reg = 0x00009888, .val = 0x258B555A },
         { .reg = 0x00009888, .val = 0x278B0015 },
         { .reg = 0x00009888, .val = 0x238B5500 },
         { .reg = 0x00009888, .val = 0x038C4000 },
         { .reg = 0x00009888, .val = 0x058C4000 },
         { .reg = 0x00009888, .val = 0x078C4000 },
         { .reg = 0x00009888, .val = 0x098C4000 },
         { .reg = 0x00009888, .val = 0x0B8C4000 },
         { .reg = 0x00009888, .val = 0x0D8C4000 },
         { .reg = 0x00009888, .val = 0x018D8000 },
         { .reg = 0x00009888, .val = 0x038DA000 },
         { .reg = 0x00009888, .val = 0x058DA000 },
         { .reg = 0x00009888, .val = 0x078D2000 },
         { .reg = 0x00009888, .val = 0x2185AAAA },
         { .reg = 0x00009888, .val = 0x2385002A },
         { .reg = 0x00009888, .val = 0x1F85AA00 },
         { .reg = 0x00009888, .val = 0x0F834000 },
         { .reg = 0x00009888, .val = 0x19835400 },
         { .reg = 0x00009888, .val = 0x1B830155 },
         { .reg = 0x00009888, .val = 0x03834000 },
         { .reg = 0x00009888, .val = 0x05834000 },
         { .reg = 0x00009888, .val = 0x07834000 },
         { .reg = 0x00009888, .val = 0x09834000 },
         { .reg = 0x00009888, .val = 0x0B834000 },
         { .reg = 0x00009888, .val = 0x0D834000 },
         { .reg = 0x00009888, .val = 0x0784C000 },
         { .reg = 0x00009888, .val = 0x0984C000 },
         { .reg = 0x00009888, .val = 0x0B84C000 },
         { .reg = 0x00009888, .val = 0x0D84C000 },
         { .reg = 0x00009888, .val = 0x0F84C000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x0384C000 },
         { .reg = 0x00009888, .val = 0x0584C000 },
         { .reg = 0x00009888, .val = 0x1780C000 },
         { .reg = 0x00009888, .val = 0x1980C000 },
         { .reg = 0x00009888, .val = 0x1B80C000 },
         { .reg = 0x00009888, .val = 0x1D80C000 },
         { .reg = 0x00009888, .val = 0x1F80C000 },
         { .reg = 0x00009888, .val = 0x11808000 },
         { .reg = 0x00009888, .val = 0x1380C000 },
         { .reg = 0x00009888, .val = 0x1580C000 },
         { .reg = 0x00009888, .val = 0x4F800000 },
         { .reg = 0x00009888, .val = 0x43800882 },
         { .reg = 0x00009888, .val = 0x51800000 },
         { .reg = 0x00009888, .val = 0x45801082 },
         { .reg = 0x00009888, .val = 0x53800000 },
         { .reg = 0x00009888, .val = 0x478014A5 },
         { .reg = 0x00009888, .val = 0x21800000 },
         { .reg = 0x00009888, .val = 0x31800000 },
         { .reg = 0x00009888, .val = 0x4D800000 },
         { .reg = 0x00009888, .val = 0x3F800002 },
         { .reg = 0x00009888, .val = 0x41800C62 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x0000FE7F },
         { .reg = 0x00002780, .val = 0x00000000 },
         { .reg = 0x00002784, .val = 0x0000FF9F },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000FFE7 },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFFB },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FFFD },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__tdl_2__avg_gpu_core_frequency__max,chv__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,chv__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,chv__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,chv__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,chv__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,chv__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,chv__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,chv__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,chv__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,chv__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,chv__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,chv__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,chv__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,chv__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,chv__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,chv__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,chv__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,chv__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,chv__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,chv__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,chv__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,chv__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,chv__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,chv__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,chv__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,chv__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,chv__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, chv__tdl_2__slm_bytes_read__max,chv__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, chv__tdl_2__slm_bytes_written__max,chv__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,chv__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,chv__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, chv__tdl_2__l3_shader_throughput__max,chv__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,chv__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 240, percentage_max_float,chv__tdl_2__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 244, percentage_max_float,chv__tdl_2__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 248, percentage_max_float,chv__tdl_2__ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 252, percentage_max_float,chv__tdl_2__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 256, percentage_max_float,chv__tdl_2__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 260, percentage_max_float,chv__tdl_2__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 301, 264, percentage_max_float,chv__tdl_2__thread_header12_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x20) {
         intel_perf_query_add_counter_float(query, 302, 268, percentage_max_float,chv__tdl_2__thread_header12_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 303, 272, percentage_max_float,chv__tdl_2__thread_header11_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 304, 276, percentage_max_float,chv__tdl_2__thread_header10_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x8) {
         intel_perf_query_add_counter_float(query, 305, 280, percentage_max_float,chv__tdl_2__thread_header10_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x10) {
         intel_perf_query_add_counter_float(query, 306, 284, percentage_max_float,chv__tdl_2__thread_header11_ready_port0__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 288, percentage_max_float,chv__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
chv_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "4a534b07-cba3-414d-8d60-874830e883aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x59800000 },
         { .reg = 0x00009888, .val = 0x59800001 },
         { .reg = 0x00009888, .val = 0x338B0000 },
         { .reg = 0x00009888, .val = 0x258B0066 },
         { .reg = 0x00009888, .val = 0x058B0000 },
         { .reg = 0x00009888, .val = 0x038B0000 },
         { .reg = 0x00009888, .val = 0x03844000 },
         { .reg = 0x00009888, .val = 0x47800080 },
         { .reg = 0x00009888, .val = 0x57800000 },
         { .reg = 0x001823A4, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x59800000 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,chv__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,chv__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, chv__test_oa__avg_gpu_core_frequency__max,chv__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,chv__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,chv__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,chv__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,chv__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,chv__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,chv__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,chv__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,chv__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,chv__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_chv(struct intel_perf_config *perf)
{
   chv_register_render_basic_counter_query(perf);
   chv_register_compute_basic_counter_query(perf);
   chv_register_render_pipe_profile_counter_query(perf);
   chv_register_hdc_and_sf_counter_query(perf);
   chv_register_l3_1_counter_query(perf);
   chv_register_l3_2_counter_query(perf);
   chv_register_l3_3_counter_query(perf);
   chv_register_l3_4_counter_query(perf);
   chv_register_rasterizer_and_pixel_backend_counter_query(perf);
   chv_register_sampler_1_counter_query(perf);
   chv_register_sampler_2_counter_query(perf);
   chv_register_tdl_1_counter_query(perf);
   chv_register_tdl_2_counter_query(perf);
   chv_register_test_oa_counter_query(perf);
}


static void
sklgt2_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "07b25942-d9fd-4fce-bd58-e29abd66b7de";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->devinfo.revision >= 0x02) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x00000080 },
            { .reg = 0x00009888, .val = 0x166C01E0 },
            { .reg = 0x00009888, .val = 0x12170280 },
            { .reg = 0x00009888, .val = 0x12370280 },
            { .reg = 0x00009888, .val = 0x11930317 },
            { .reg = 0x00009888, .val = 0x159303DF },
            { .reg = 0x00009888, .val = 0x3F900003 },
            { .reg = 0x00009888, .val = 0x1A4E0080 },
            { .reg = 0x00009888, .val = 0x0A6C0053 },
            { .reg = 0x00009888, .val = 0x106C0000 },
            { .reg = 0x00009888, .val = 0x1C6C0000 },
            { .reg = 0x00009888, .val = 0x0A1B4000 },
            { .reg = 0x00009888, .val = 0x1C1C0001 },
            { .reg = 0x00009888, .val = 0x002F1000 },
            { .reg = 0x00009888, .val = 0x042F1000 },
            { .reg = 0x00009888, .val = 0x004C4000 },
            { .reg = 0x00009888, .val = 0x0A4C8400 },
            { .reg = 0x00009888, .val = 0x000D2000 },
            { .reg = 0x00009888, .val = 0x060D8000 },
            { .reg = 0x00009888, .val = 0x080DA000 },
            { .reg = 0x00009888, .val = 0x0A0D2000 },
            { .reg = 0x00009888, .val = 0x0C0F0400 },
            { .reg = 0x00009888, .val = 0x0E0F6600 },
            { .reg = 0x00009888, .val = 0x002C8000 },
            { .reg = 0x00009888, .val = 0x162C2200 },
            { .reg = 0x00009888, .val = 0x062D8000 },
            { .reg = 0x00009888, .val = 0x082D8000 },
            { .reg = 0x00009888, .val = 0x00133000 },
            { .reg = 0x00009888, .val = 0x08133000 },
            { .reg = 0x00009888, .val = 0x00170020 },
            { .reg = 0x00009888, .val = 0x08170021 },
            { .reg = 0x00009888, .val = 0x10170000 },
            { .reg = 0x00009888, .val = 0x0633C000 },
            { .reg = 0x00009888, .val = 0x0833C000 },
            { .reg = 0x00009888, .val = 0x06370800 },
            { .reg = 0x00009888, .val = 0x08370840 },
            { .reg = 0x00009888, .val = 0x10370000 },
            { .reg = 0x00009888, .val = 0x0D933031 },
            { .reg = 0x00009888, .val = 0x0F933E3F },
            { .reg = 0x00009888, .val = 0x01933D00 },
            { .reg = 0x00009888, .val = 0x0393073C },
            { .reg = 0x00009888, .val = 0x0593000E },
            { .reg = 0x00009888, .val = 0x1D930000 },
            { .reg = 0x00009888, .val = 0x19930000 },
            { .reg = 0x00009888, .val = 0x1B930000 },
            { .reg = 0x00009888, .val = 0x1D900157 },
            { .reg = 0x00009888, .val = 0x1F900158 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x2B908000 },
            { .reg = 0x00009888, .val = 0x2D908000 },
            { .reg = 0x00009888, .val = 0x2F908000 },
            { .reg = 0x00009888, .val = 0x31908000 },
            { .reg = 0x00009888, .val = 0x15908000 },
            { .reg = 0x00009888, .val = 0x17908000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B908000 },
            { .reg = 0x00009888, .val = 0x1190001F },
            { .reg = 0x00009888, .val = 0x51904400 },
            { .reg = 0x00009888, .val = 0x41900020 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900C21 },
            { .reg = 0x00009888, .val = 0x47900061 },
            { .reg = 0x00009888, .val = 0x57904440 },
            { .reg = 0x00009888, .val = 0x49900000 },
            { .reg = 0x00009888, .val = 0x37900000 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900000 },
            { .reg = 0x00009888, .val = 0x59900004 },
            { .reg = 0x00009888, .val = 0x43900000 },
            { .reg = 0x00009888, .val = 0x53904444 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__render_basic__avg_gpu_core_frequency__max,sklgt2__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,sklgt2__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,sklgt2__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,sklgt2__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,sklgt2__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,sklgt2__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,sklgt2__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,sklgt2__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,sklgt2__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,sklgt2__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,sklgt2__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,sklgt2__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,sklgt2__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,sklgt2__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,sklgt2__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,sklgt2__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,sklgt2__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,sklgt2__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,sklgt2__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,sklgt2__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,sklgt2__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,sklgt2__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,sklgt2__render_basic__sampler1_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,sklgt2__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,sklgt2__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,sklgt2__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,sklgt2__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,sklgt2__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,sklgt2__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,sklgt2__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,sklgt2__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,sklgt2__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 208, NULL,sklgt2__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, sklgt2__render_basic__slm_bytes_read__max,sklgt2__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, sklgt2__render_basic__slm_bytes_written__max,sklgt2__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,sklgt2__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,sklgt2__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,sklgt2__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,sklgt2__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, sklgt2__render_basic__l3_sampler_throughput__max,sklgt2__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, sklgt2__render_basic__l3_shader_throughput__max,sklgt2__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,sklgt2__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, sklgt2__render_basic__gti_vf_throughput__max,sklgt2__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, sklgt2__render_basic__gti_depth_throughput__max,sklgt2__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, sklgt2__render_basic__gti_rcc_throughput__max,sklgt2__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, sklgt2__render_basic__gti_l3_throughput__max,sklgt2__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, sklgt2__render_basic__gti_hdc_lookups_throughput__max,sklgt2__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, sklgt2__render_basic__gti_read_throughput__max,sklgt2__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, sklgt2__render_basic__gti_write_throughput__max,sklgt2__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,sklgt2__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "00b80b4c-d215-4378-9015-da3dda3b61ea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if ((perf->sys_vars.slice_mask & 0x01) &&
          (perf->devinfo.revision < 0x02)) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x104F00E0 },
            { .reg = 0x00009888, .val = 0x124F1C00 },
            { .reg = 0x00009888, .val = 0x106C00E0 },
            { .reg = 0x00009888, .val = 0x37906800 },
            { .reg = 0x00009888, .val = 0x3F901403 },
            { .reg = 0x00009888, .val = 0x184E8000 },
            { .reg = 0x00009888, .val = 0x1A4E8200 },
            { .reg = 0x00009888, .val = 0x044E8000 },
            { .reg = 0x00009888, .val = 0x004F0DB2 },
            { .reg = 0x00009888, .val = 0x064F0900 },
            { .reg = 0x00009888, .val = 0x084F1880 },
            { .reg = 0x00009888, .val = 0x0A4F0011 },
            { .reg = 0x00009888, .val = 0x0C4F0E3C },
            { .reg = 0x00009888, .val = 0x0E4F1D80 },
            { .reg = 0x00009888, .val = 0x086C0002 },
            { .reg = 0x00009888, .val = 0x0A6C0100 },
            { .reg = 0x00009888, .val = 0x0E6C000C },
            { .reg = 0x00009888, .val = 0x026C000B },
            { .reg = 0x00009888, .val = 0x1C6C0000 },
            { .reg = 0x00009888, .val = 0x1A6C0000 },
            { .reg = 0x00009888, .val = 0x081B4000 },
            { .reg = 0x00009888, .val = 0x0A1B8000 },
            { .reg = 0x00009888, .val = 0x0E1B4000 },
            { .reg = 0x00009888, .val = 0x021B4000 },
            { .reg = 0x00009888, .val = 0x1A1C4000 },
            { .reg = 0x00009888, .val = 0x1C1C0012 },
            { .reg = 0x00009888, .val = 0x141C8000 },
            { .reg = 0x00009888, .val = 0x005BC000 },
            { .reg = 0x00009888, .val = 0x065B8000 },
            { .reg = 0x00009888, .val = 0x085B8000 },
            { .reg = 0x00009888, .val = 0x0A5B4000 },
            { .reg = 0x00009888, .val = 0x0C5BC000 },
            { .reg = 0x00009888, .val = 0x0E5B8000 },
            { .reg = 0x00009888, .val = 0x105C8000 },
            { .reg = 0x00009888, .val = 0x1A5CA000 },
            { .reg = 0x00009888, .val = 0x1C5C002D },
            { .reg = 0x00009888, .val = 0x125C8000 },
            { .reg = 0x00009888, .val = 0x0A4C0800 },
            { .reg = 0x00009888, .val = 0x0C4C0082 },
            { .reg = 0x00009888, .val = 0x084C8000 },
            { .reg = 0x00009888, .val = 0x000DA000 },
            { .reg = 0x00009888, .val = 0x060D8000 },
            { .reg = 0x00009888, .val = 0x080DA000 },
            { .reg = 0x00009888, .val = 0x0A0DA000 },
            { .reg = 0x00009888, .val = 0x0C0DA000 },
            { .reg = 0x00009888, .val = 0x0E0DA000 },
            { .reg = 0x00009888, .val = 0x020D2000 },
            { .reg = 0x00009888, .val = 0x0C0F5400 },
            { .reg = 0x00009888, .val = 0x0E0F5500 },
            { .reg = 0x00009888, .val = 0x100F0155 },
            { .reg = 0x00009888, .val = 0x002CC000 },
            { .reg = 0x00009888, .val = 0x0E2CC000 },
            { .reg = 0x00009888, .val = 0x162CBE00 },
            { .reg = 0x00009888, .val = 0x182C00EF },
            { .reg = 0x00009888, .val = 0x022CC000 },
            { .reg = 0x00009888, .val = 0x042C8000 },
            { .reg = 0x00009888, .val = 0x19900157 },
            { .reg = 0x00009888, .val = 0x1B900167 },
            { .reg = 0x00009888, .val = 0x1D900105 },
            { .reg = 0x00009888, .val = 0x1F900103 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x11900FFF },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900840 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900842 },
            { .reg = 0x00009888, .val = 0x47900840 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900840 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900040 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900840 },
            { .reg = 0x00009888, .val = 0x53901111 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if ((perf->sys_vars.slice_mask & 0x01) &&
          (perf->devinfo.revision >= 0x02)) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x104F00E0 },
            { .reg = 0x00009888, .val = 0x124F1C00 },
            { .reg = 0x00009888, .val = 0x106C00E0 },
            { .reg = 0x00009888, .val = 0x37906800 },
            { .reg = 0x00009888, .val = 0x3F901403 },
            { .reg = 0x00009888, .val = 0x004E8000 },
            { .reg = 0x00009888, .val = 0x1A4E0820 },
            { .reg = 0x00009888, .val = 0x1C4E0002 },
            { .reg = 0x00009888, .val = 0x064F0900 },
            { .reg = 0x00009888, .val = 0x084F0032 },
            { .reg = 0x00009888, .val = 0x0A4F1810 },
            { .reg = 0x00009888, .val = 0x0C4F0E00 },
            { .reg = 0x00009888, .val = 0x0E4F003C },
            { .reg = 0x00009888, .val = 0x004F0D80 },
            { .reg = 0x00009888, .val = 0x024F003B },
            { .reg = 0x00009888, .val = 0x006C0002 },
            { .reg = 0x00009888, .val = 0x086C0000 },
            { .reg = 0x00009888, .val = 0x0C6C000C },
            { .reg = 0x00009888, .val = 0x0E6C0B00 },
            { .reg = 0x00009888, .val = 0x186C0000 },
            { .reg = 0x00009888, .val = 0x1C6C0000 },
            { .reg = 0x00009888, .val = 0x1E6C0000 },
            { .reg = 0x00009888, .val = 0x001B4000 },
            { .reg = 0x00009888, .val = 0x081B8000 },
            { .reg = 0x00009888, .val = 0x0C1B4000 },
            { .reg = 0x00009888, .val = 0x0E1B8000 },
            { .reg = 0x00009888, .val = 0x101C8000 },
            { .reg = 0x00009888, .val = 0x1A1C8000 },
            { .reg = 0x00009888, .val = 0x1C1C0024 },
            { .reg = 0x00009888, .val = 0x065B8000 },
            { .reg = 0x00009888, .val = 0x085B4000 },
            { .reg = 0x00009888, .val = 0x0A5BC000 },
            { .reg = 0x00009888, .val = 0x0C5B8000 },
            { .reg = 0x00009888, .val = 0x0E5B4000 },
            { .reg = 0x00009888, .val = 0x005B8000 },
            { .reg = 0x00009888, .val = 0x025B4000 },
            { .reg = 0x00009888, .val = 0x1A5C6000 },
            { .reg = 0x00009888, .val = 0x1C5C001B },
            { .reg = 0x00009888, .val = 0x125C8000 },
            { .reg = 0x00009888, .val = 0x145C8000 },
            { .reg = 0x00009888, .val = 0x004C8000 },
            { .reg = 0x00009888, .val = 0x0A4C2000 },
            { .reg = 0x00009888, .val = 0x0C4C0208 },
            { .reg = 0x00009888, .val = 0x000DA000 },
            { .reg = 0x00009888, .val = 0x060D8000 },
            { .reg = 0x00009888, .val = 0x080DA000 },
            { .reg = 0x00009888, .val = 0x0A0DA000 },
            { .reg = 0x00009888, .val = 0x0C0DA000 },
            { .reg = 0x00009888, .val = 0x0E0DA000 },
            { .reg = 0x00009888, .val = 0x020D2000 },
            { .reg = 0x00009888, .val = 0x0C0F5400 },
            { .reg = 0x00009888, .val = 0x0E0F5500 },
            { .reg = 0x00009888, .val = 0x100F0155 },
            { .reg = 0x00009888, .val = 0x002C8000 },
            { .reg = 0x00009888, .val = 0x0E2CC000 },
            { .reg = 0x00009888, .val = 0x162CFB00 },
            { .reg = 0x00009888, .val = 0x182C00BE },
            { .reg = 0x00009888, .val = 0x022CC000 },
            { .reg = 0x00009888, .val = 0x042CC000 },
            { .reg = 0x00009888, .val = 0x19900157 },
            { .reg = 0x00009888, .val = 0x1B900167 },
            { .reg = 0x00009888, .val = 0x1D900105 },
            { .reg = 0x00009888, .val = 0x1F900103 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x11900FFF },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900800 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900842 },
            { .reg = 0x00009888, .val = 0x47900802 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900802 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900002 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900842 },
            { .reg = 0x00009888, .val = 0x53901111 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__compute_basic__avg_gpu_core_frequency__max,sklgt2__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,sklgt2__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,sklgt2__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, sklgt2__compute_basic__eu_avg_ipc_rate__max,sklgt2__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,sklgt2__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,sklgt2__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,sklgt2__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,sklgt2__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,sklgt2__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,sklgt2__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,sklgt2__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,sklgt2__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,sklgt2__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,sklgt2__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,sklgt2__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, sklgt2__compute_basic__slm_bytes_read__max,sklgt2__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, sklgt2__compute_basic__slm_bytes_written__max,sklgt2__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,sklgt2__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,sklgt2__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, sklgt2__compute_basic__l3_shader_throughput__max,sklgt2__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,sklgt2__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, sklgt2__compute_basic__typed_bytes_read__max,sklgt2__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, sklgt2__compute_basic__typed_bytes_written__max,sklgt2__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, sklgt2__compute_basic__untyped_bytes_read__max,sklgt2__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, sklgt2__compute_basic__untyped_bytes_written__max,sklgt2__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, sklgt2__compute_basic__gti_read_throughput__max,sklgt2__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, sklgt2__compute_basic__gti_write_throughput__max,sklgt2__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "2a0c0933-37e7-427c-9951-ded42a78bb27";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->devinfo.revision < 0x02) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x0C0E001F },
            { .reg = 0x00009888, .val = 0x0A0F0000 },
            { .reg = 0x00009888, .val = 0x10116800 },
            { .reg = 0x00009888, .val = 0x178A03E0 },
            { .reg = 0x00009888, .val = 0x11824C00 },
            { .reg = 0x00009888, .val = 0x11830020 },
            { .reg = 0x00009888, .val = 0x13840020 },
            { .reg = 0x00009888, .val = 0x11850019 },
            { .reg = 0x00009888, .val = 0x11860007 },
            { .reg = 0x00009888, .val = 0x01870C40 },
            { .reg = 0x00009888, .val = 0x17880000 },
            { .reg = 0x00009888, .val = 0x022F4000 },
            { .reg = 0x00009888, .val = 0x0A4C0040 },
            { .reg = 0x00009888, .val = 0x0C0D8000 },
            { .reg = 0x00009888, .val = 0x040D4000 },
            { .reg = 0x00009888, .val = 0x060D2000 },
            { .reg = 0x00009888, .val = 0x020E5400 },
            { .reg = 0x00009888, .val = 0x000E0000 },
            { .reg = 0x00009888, .val = 0x080F0040 },
            { .reg = 0x00009888, .val = 0x000F0000 },
            { .reg = 0x00009888, .val = 0x100F0000 },
            { .reg = 0x00009888, .val = 0x0E0F0040 },
            { .reg = 0x00009888, .val = 0x0C2C8000 },
            { .reg = 0x00009888, .val = 0x06104000 },
            { .reg = 0x00009888, .val = 0x06110012 },
            { .reg = 0x00009888, .val = 0x06131000 },
            { .reg = 0x00009888, .val = 0x01898000 },
            { .reg = 0x00009888, .val = 0x0D890100 },
            { .reg = 0x00009888, .val = 0x03898000 },
            { .reg = 0x00009888, .val = 0x09808000 },
            { .reg = 0x00009888, .val = 0x0B808000 },
            { .reg = 0x00009888, .val = 0x0380C000 },
            { .reg = 0x00009888, .val = 0x0F8A0075 },
            { .reg = 0x00009888, .val = 0x1D8A0000 },
            { .reg = 0x00009888, .val = 0x118A8000 },
            { .reg = 0x00009888, .val = 0x1B8A4000 },
            { .reg = 0x00009888, .val = 0x138A8000 },
            { .reg = 0x00009888, .val = 0x1D81A000 },
            { .reg = 0x00009888, .val = 0x15818000 },
            { .reg = 0x00009888, .val = 0x17818000 },
            { .reg = 0x00009888, .val = 0x0B820030 },
            { .reg = 0x00009888, .val = 0x07828000 },
            { .reg = 0x00009888, .val = 0x0D824000 },
            { .reg = 0x00009888, .val = 0x0F828000 },
            { .reg = 0x00009888, .val = 0x05824000 },
            { .reg = 0x00009888, .val = 0x0D830003 },
            { .reg = 0x00009888, .val = 0x0583000C },
            { .reg = 0x00009888, .val = 0x09830000 },
            { .reg = 0x00009888, .val = 0x03838000 },
            { .reg = 0x00009888, .val = 0x07838000 },
            { .reg = 0x00009888, .val = 0x0B840980 },
            { .reg = 0x00009888, .val = 0x03844D80 },
            { .reg = 0x00009888, .val = 0x11840000 },
            { .reg = 0x00009888, .val = 0x09848000 },
            { .reg = 0x00009888, .val = 0x09850080 },
            { .reg = 0x00009888, .val = 0x03850003 },
            { .reg = 0x00009888, .val = 0x01850000 },
            { .reg = 0x00009888, .val = 0x07860000 },
            { .reg = 0x00009888, .val = 0x0F860400 },
            { .reg = 0x00009888, .val = 0x09870032 },
            { .reg = 0x00009888, .val = 0x01888052 },
            { .reg = 0x00009888, .val = 0x11880000 },
            { .reg = 0x00009888, .val = 0x09884000 },
            { .reg = 0x00009888, .val = 0x15968000 },
            { .reg = 0x00009888, .val = 0x17968000 },
            { .reg = 0x00009888, .val = 0x0F96C000 },
            { .reg = 0x00009888, .val = 0x1F950011 },
            { .reg = 0x00009888, .val = 0x1D950014 },
            { .reg = 0x00009888, .val = 0x0592C000 },
            { .reg = 0x00009888, .val = 0x0B928000 },
            { .reg = 0x00009888, .val = 0x0D924000 },
            { .reg = 0x00009888, .val = 0x0F924000 },
            { .reg = 0x00009888, .val = 0x11928000 },
            { .reg = 0x00009888, .val = 0x1392C000 },
            { .reg = 0x00009888, .val = 0x09924000 },
            { .reg = 0x00009888, .val = 0x01985000 },
            { .reg = 0x00009888, .val = 0x07988000 },
            { .reg = 0x00009888, .val = 0x09981000 },
            { .reg = 0x00009888, .val = 0x0B982000 },
            { .reg = 0x00009888, .val = 0x0D982000 },
            { .reg = 0x00009888, .val = 0x0F989000 },
            { .reg = 0x00009888, .val = 0x05982000 },
            { .reg = 0x00009888, .val = 0x13904000 },
            { .reg = 0x00009888, .val = 0x21904000 },
            { .reg = 0x00009888, .val = 0x23904000 },
            { .reg = 0x00009888, .val = 0x25908000 },
            { .reg = 0x00009888, .val = 0x27904000 },
            { .reg = 0x00009888, .val = 0x29908000 },
            { .reg = 0x00009888, .val = 0x2B904000 },
            { .reg = 0x00009888, .val = 0x2F904000 },
            { .reg = 0x00009888, .val = 0x31904000 },
            { .reg = 0x00009888, .val = 0x15904000 },
            { .reg = 0x00009888, .val = 0x17908000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B904000 },
            { .reg = 0x00009888, .val = 0x0B978000 },
            { .reg = 0x00009888, .val = 0x0F974000 },
            { .reg = 0x00009888, .val = 0x11974000 },
            { .reg = 0x00009888, .val = 0x13978000 },
            { .reg = 0x00009888, .val = 0x09974000 },
            { .reg = 0x00009888, .val = 0x1190C080 },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x419010A0 },
            { .reg = 0x00009888, .val = 0x55904000 },
            { .reg = 0x00009888, .val = 0x45901000 },
            { .reg = 0x00009888, .val = 0x47900084 },
            { .reg = 0x00009888, .val = 0x57904400 },
            { .reg = 0x00009888, .val = 0x499000A5 },
            { .reg = 0x00009888, .val = 0x37900000 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900081 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x439014A4 },
            { .reg = 0x00009888, .val = 0x53900400 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->devinfo.revision >= 0x02) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x0C0E001F },
            { .reg = 0x00009888, .val = 0x0A0F0000 },
            { .reg = 0x00009888, .val = 0x10116800 },
            { .reg = 0x00009888, .val = 0x178A03E0 },
            { .reg = 0x00009888, .val = 0x11824C00 },
            { .reg = 0x00009888, .val = 0x11830020 },
            { .reg = 0x00009888, .val = 0x13840020 },
            { .reg = 0x00009888, .val = 0x11850019 },
            { .reg = 0x00009888, .val = 0x11860007 },
            { .reg = 0x00009888, .val = 0x01870C40 },
            { .reg = 0x00009888, .val = 0x17880000 },
            { .reg = 0x00009888, .val = 0x022F4000 },
            { .reg = 0x00009888, .val = 0x0A4C0040 },
            { .reg = 0x00009888, .val = 0x0C0D8000 },
            { .reg = 0x00009888, .val = 0x040D4000 },
            { .reg = 0x00009888, .val = 0x060D2000 },
            { .reg = 0x00009888, .val = 0x020E5400 },
            { .reg = 0x00009888, .val = 0x000E0000 },
            { .reg = 0x00009888, .val = 0x080F0040 },
            { .reg = 0x00009888, .val = 0x000F0000 },
            { .reg = 0x00009888, .val = 0x100F0000 },
            { .reg = 0x00009888, .val = 0x0E0F0040 },
            { .reg = 0x00009888, .val = 0x0C2C8000 },
            { .reg = 0x00009888, .val = 0x06104000 },
            { .reg = 0x00009888, .val = 0x06110012 },
            { .reg = 0x00009888, .val = 0x06131000 },
            { .reg = 0x00009888, .val = 0x01898000 },
            { .reg = 0x00009888, .val = 0x0D890100 },
            { .reg = 0x00009888, .val = 0x03898000 },
            { .reg = 0x00009888, .val = 0x09808000 },
            { .reg = 0x00009888, .val = 0x0B808000 },
            { .reg = 0x00009888, .val = 0x0380C000 },
            { .reg = 0x00009888, .val = 0x0F8A0075 },
            { .reg = 0x00009888, .val = 0x1D8A0000 },
            { .reg = 0x00009888, .val = 0x118A8000 },
            { .reg = 0x00009888, .val = 0x1B8A4000 },
            { .reg = 0x00009888, .val = 0x138A8000 },
            { .reg = 0x00009888, .val = 0x1D81A000 },
            { .reg = 0x00009888, .val = 0x15818000 },
            { .reg = 0x00009888, .val = 0x17818000 },
            { .reg = 0x00009888, .val = 0x0B820030 },
            { .reg = 0x00009888, .val = 0x07828000 },
            { .reg = 0x00009888, .val = 0x0D824000 },
            { .reg = 0x00009888, .val = 0x0F828000 },
            { .reg = 0x00009888, .val = 0x05824000 },
            { .reg = 0x00009888, .val = 0x0D830003 },
            { .reg = 0x00009888, .val = 0x0583000C },
            { .reg = 0x00009888, .val = 0x09830000 },
            { .reg = 0x00009888, .val = 0x03838000 },
            { .reg = 0x00009888, .val = 0x07838000 },
            { .reg = 0x00009888, .val = 0x0B840980 },
            { .reg = 0x00009888, .val = 0x03844D80 },
            { .reg = 0x00009888, .val = 0x11840000 },
            { .reg = 0x00009888, .val = 0x09848000 },
            { .reg = 0x00009888, .val = 0x09850080 },
            { .reg = 0x00009888, .val = 0x03850003 },
            { .reg = 0x00009888, .val = 0x01850000 },
            { .reg = 0x00009888, .val = 0x07860000 },
            { .reg = 0x00009888, .val = 0x0F860400 },
            { .reg = 0x00009888, .val = 0x09870032 },
            { .reg = 0x00009888, .val = 0x01888052 },
            { .reg = 0x00009888, .val = 0x11880000 },
            { .reg = 0x00009888, .val = 0x09884000 },
            { .reg = 0x00009888, .val = 0x1B931001 },
            { .reg = 0x00009888, .val = 0x1D930001 },
            { .reg = 0x00009888, .val = 0x19934000 },
            { .reg = 0x00009888, .val = 0x1B958000 },
            { .reg = 0x00009888, .val = 0x1D950094 },
            { .reg = 0x00009888, .val = 0x19958000 },
            { .reg = 0x00009888, .val = 0x05E5A000 },
            { .reg = 0x00009888, .val = 0x01E5C000 },
            { .reg = 0x00009888, .val = 0x0592C000 },
            { .reg = 0x00009888, .val = 0x0B928000 },
            { .reg = 0x00009888, .val = 0x0D924000 },
            { .reg = 0x00009888, .val = 0x0F924000 },
            { .reg = 0x00009888, .val = 0x11928000 },
            { .reg = 0x00009888, .val = 0x1392C000 },
            { .reg = 0x00009888, .val = 0x09924000 },
            { .reg = 0x00009888, .val = 0x01985000 },
            { .reg = 0x00009888, .val = 0x07988000 },
            { .reg = 0x00009888, .val = 0x09981000 },
            { .reg = 0x00009888, .val = 0x0B982000 },
            { .reg = 0x00009888, .val = 0x0D982000 },
            { .reg = 0x00009888, .val = 0x0F989000 },
            { .reg = 0x00009888, .val = 0x05982000 },
            { .reg = 0x00009888, .val = 0x13904000 },
            { .reg = 0x00009888, .val = 0x21904000 },
            { .reg = 0x00009888, .val = 0x23904000 },
            { .reg = 0x00009888, .val = 0x25908000 },
            { .reg = 0x00009888, .val = 0x27904000 },
            { .reg = 0x00009888, .val = 0x29908000 },
            { .reg = 0x00009888, .val = 0x2B904000 },
            { .reg = 0x00009888, .val = 0x2F904000 },
            { .reg = 0x00009888, .val = 0x31904000 },
            { .reg = 0x00009888, .val = 0x15904000 },
            { .reg = 0x00009888, .val = 0x17908000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B904000 },
            { .reg = 0x00009888, .val = 0x1190C080 },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x419010A0 },
            { .reg = 0x00009888, .val = 0x55904000 },
            { .reg = 0x00009888, .val = 0x45901000 },
            { .reg = 0x00009888, .val = 0x47900084 },
            { .reg = 0x00009888, .val = 0x57904400 },
            { .reg = 0x00009888, .val = 0x499000A5 },
            { .reg = 0x00009888, .val = 0x37900000 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900081 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x439014A4 },
            { .reg = 0x00009888, .val = 0x53900400 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__render_pipe_profile__avg_gpu_core_frequency__max,sklgt2__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,sklgt2__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,sklgt2__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,sklgt2__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,sklgt2__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,sklgt2__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,sklgt2__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,sklgt2__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,sklgt2__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,sklgt2__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, sklgt2__render_pipe_profile__slm_bytes_read__max,sklgt2__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, sklgt2__render_pipe_profile__slm_bytes_written__max,sklgt2__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,sklgt2__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,sklgt2__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, sklgt2__render_pipe_profile__l3_shader_throughput__max,sklgt2__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,sklgt2__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, NULL,sklgt2__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, NULL,sklgt2__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, NULL,sklgt2__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, NULL,sklgt2__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, NULL,sklgt2__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, NULL,sklgt2__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, NULL,sklgt2__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, NULL,sklgt2__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, NULL,sklgt2__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, NULL,sklgt2__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, NULL,sklgt2__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, NULL,sklgt2__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, NULL,sklgt2__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, NULL,sklgt2__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, NULL,sklgt2__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, NULL,sklgt2__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Reads Distribution metrics set";
   query->symbol_name = "MemoryReads";
   query->guid = "246b35f1-44e0-4d03-8936-e452e291d064";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if ((perf->sys_vars.slice_mask & 0x01) &&
          (perf->devinfo.revision < 0x02)) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x11810C00 },
            { .reg = 0x00009888, .val = 0x1381001A },
            { .reg = 0x00009888, .val = 0x13946000 },
            { .reg = 0x00009888, .val = 0x37906800 },
            { .reg = 0x00009888, .val = 0x3F900003 },
            { .reg = 0x00009888, .val = 0x03811300 },
            { .reg = 0x00009888, .val = 0x05811B12 },
            { .reg = 0x00009888, .val = 0x0781001A },
            { .reg = 0x00009888, .val = 0x1F810000 },
            { .reg = 0x00009888, .val = 0x17810000 },
            { .reg = 0x00009888, .val = 0x19810000 },
            { .reg = 0x00009888, .val = 0x1B810000 },
            { .reg = 0x00009888, .val = 0x1D810000 },
            { .reg = 0x00009888, .val = 0x0F968000 },
            { .reg = 0x00009888, .val = 0x1196C000 },
            { .reg = 0x00009888, .val = 0x13964000 },
            { .reg = 0x00009888, .val = 0x11938000 },
            { .reg = 0x00009888, .val = 0x1B93FE00 },
            { .reg = 0x00009888, .val = 0x01940010 },
            { .reg = 0x00009888, .val = 0x07941100 },
            { .reg = 0x00009888, .val = 0x09941312 },
            { .reg = 0x00009888, .val = 0x0B941514 },
            { .reg = 0x00009888, .val = 0x0D941716 },
            { .reg = 0x00009888, .val = 0x11940000 },
            { .reg = 0x00009888, .val = 0x19940000 },
            { .reg = 0x00009888, .val = 0x1B940000 },
            { .reg = 0x00009888, .val = 0x1D940000 },
            { .reg = 0x00009888, .val = 0x1B954000 },
            { .reg = 0x00009888, .val = 0x1D95A550 },
            { .reg = 0x00009888, .val = 0x1F9502AA },
            { .reg = 0x00009888, .val = 0x2F900157 },
            { .reg = 0x00009888, .val = 0x31900105 },
            { .reg = 0x00009888, .val = 0x15900103 },
            { .reg = 0x00009888, .val = 0x17900101 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x13908000 },
            { .reg = 0x00009888, .val = 0x21908000 },
            { .reg = 0x00009888, .val = 0x23908000 },
            { .reg = 0x00009888, .val = 0x25908000 },
            { .reg = 0x00009888, .val = 0x27908000 },
            { .reg = 0x00009888, .val = 0x29908000 },
            { .reg = 0x00009888, .val = 0x2B908000 },
            { .reg = 0x00009888, .val = 0x2D908000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B908000 },
            { .reg = 0x00009888, .val = 0x1D908000 },
            { .reg = 0x00009888, .val = 0x1F908000 },
            { .reg = 0x00009888, .val = 0x11900000 },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900C00 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900000 },
            { .reg = 0x00009888, .val = 0x47900000 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900000 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900063 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900003 },
            { .reg = 0x00009888, .val = 0x53900000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if ((perf->devinfo.revision < 0x05) &&
          (perf->devinfo.revision >= 0x02)) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x11810C00 },
            { .reg = 0x00009888, .val = 0x1381001A },
            { .reg = 0x00009888, .val = 0x13946000 },
            { .reg = 0x00009888, .val = 0x15940016 },
            { .reg = 0x00009888, .val = 0x37906800 },
            { .reg = 0x00009888, .val = 0x03811300 },
            { .reg = 0x00009888, .val = 0x05811B12 },
            { .reg = 0x00009888, .val = 0x0781001A },
            { .reg = 0x00009888, .val = 0x1F810000 },
            { .reg = 0x00009888, .val = 0x17810000 },
            { .reg = 0x00009888, .val = 0x19810000 },
            { .reg = 0x00009888, .val = 0x1B810000 },
            { .reg = 0x00009888, .val = 0x1D810000 },
            { .reg = 0x00009888, .val = 0x19930800 },
            { .reg = 0x00009888, .val = 0x1B93AA55 },
            { .reg = 0x00009888, .val = 0x1D9300AA },
            { .reg = 0x00009888, .val = 0x01940010 },
            { .reg = 0x00009888, .val = 0x07941100 },
            { .reg = 0x00009888, .val = 0x09941312 },
            { .reg = 0x00009888, .val = 0x0B941514 },
            { .reg = 0x00009888, .val = 0x0D941716 },
            { .reg = 0x00009888, .val = 0x0F940018 },
            { .reg = 0x00009888, .val = 0x1B940000 },
            { .reg = 0x00009888, .val = 0x11940000 },
            { .reg = 0x00009888, .val = 0x01E58000 },
            { .reg = 0x00009888, .val = 0x03E57000 },
            { .reg = 0x00009888, .val = 0x31900105 },
            { .reg = 0x00009888, .val = 0x15900103 },
            { .reg = 0x00009888, .val = 0x17900101 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x13908000 },
            { .reg = 0x00009888, .val = 0x21908000 },
            { .reg = 0x00009888, .val = 0x23908000 },
            { .reg = 0x00009888, .val = 0x25908000 },
            { .reg = 0x00009888, .val = 0x27908000 },
            { .reg = 0x00009888, .val = 0x29908000 },
            { .reg = 0x00009888, .val = 0x2B908000 },
            { .reg = 0x00009888, .val = 0x2D908000 },
            { .reg = 0x00009888, .val = 0x2F908000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B908000 },
            { .reg = 0x00009888, .val = 0x1D908000 },
            { .reg = 0x00009888, .val = 0x1F908000 },
            { .reg = 0x00009888, .val = 0x11900000 },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900C20 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900400 },
            { .reg = 0x00009888, .val = 0x47900421 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900421 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900061 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900003 },
            { .reg = 0x00009888, .val = 0x53900000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->devinfo.revision >= 0x05) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x00000080 },
            { .reg = 0x00009888, .val = 0x11810C00 },
            { .reg = 0x00009888, .val = 0x1381001A },
            { .reg = 0x00009888, .val = 0x37906800 },
            { .reg = 0x00009888, .val = 0x3F900064 },
            { .reg = 0x00009888, .val = 0x03811300 },
            { .reg = 0x00009888, .val = 0x05811B12 },
            { .reg = 0x00009888, .val = 0x0781001A },
            { .reg = 0x00009888, .val = 0x1F810000 },
            { .reg = 0x00009888, .val = 0x17810000 },
            { .reg = 0x00009888, .val = 0x19810000 },
            { .reg = 0x00009888, .val = 0x1B810000 },
            { .reg = 0x00009888, .val = 0x1D810000 },
            { .reg = 0x00009888, .val = 0x1B930055 },
            { .reg = 0x00009888, .val = 0x03E58000 },
            { .reg = 0x00009888, .val = 0x05E5C000 },
            { .reg = 0x00009888, .val = 0x07E54000 },
            { .reg = 0x00009888, .val = 0x13900150 },
            { .reg = 0x00009888, .val = 0x21900151 },
            { .reg = 0x00009888, .val = 0x23900152 },
            { .reg = 0x00009888, .val = 0x25900153 },
            { .reg = 0x00009888, .val = 0x27900154 },
            { .reg = 0x00009888, .val = 0x29900155 },
            { .reg = 0x00009888, .val = 0x2B900156 },
            { .reg = 0x00009888, .val = 0x2D900157 },
            { .reg = 0x00009888, .val = 0x2F90015F },
            { .reg = 0x00009888, .val = 0x31900105 },
            { .reg = 0x00009888, .val = 0x15900103 },
            { .reg = 0x00009888, .val = 0x17900101 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B908000 },
            { .reg = 0x00009888, .val = 0x1D908000 },
            { .reg = 0x00009888, .val = 0x1F908000 },
            { .reg = 0x00009888, .val = 0x11900000 },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900C60 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900C00 },
            { .reg = 0x00009888, .val = 0x47900C63 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900C63 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900063 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900003 },
            { .reg = 0x00009888, .val = 0x53900000 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__memory_reads__avg_gpu_core_frequency__max,sklgt2__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,sklgt2__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,sklgt2__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,sklgt2__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,sklgt2__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,sklgt2__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,sklgt2__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,sklgt2__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,sklgt2__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,sklgt2__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, sklgt2__memory_reads__slm_bytes_read__max,sklgt2__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, sklgt2__memory_reads__slm_bytes_written__max,sklgt2__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,sklgt2__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,sklgt2__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,sklgt2__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 95, 200, NULL,sklgt2__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 208, NULL,sklgt2__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 216, NULL,sklgt2__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 224, NULL,sklgt2__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 232, NULL,sklgt2__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 240, NULL,sklgt2__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 248, NULL,sklgt2__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 256, NULL,sklgt2__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 264, NULL,sklgt2__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 272, NULL,sklgt2__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 280, NULL,sklgt2__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 288, NULL,sklgt2__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 296, NULL,sklgt2__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 304, NULL,sklgt2__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 312, NULL,sklgt2__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metrics set";
   query->symbol_name = "MemoryWrites";
   query->guid = "e0d3da02-00bf-4a96-9795-b48158c73a68";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if ((perf->sys_vars.slice_mask & 0x01) &&
          (perf->devinfo.revision < 0x02)) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x11810C00 },
            { .reg = 0x00009888, .val = 0x1381001A },
            { .reg = 0x00009888, .val = 0x13945400 },
            { .reg = 0x00009888, .val = 0x37906800 },
            { .reg = 0x00009888, .val = 0x3F901400 },
            { .reg = 0x00009888, .val = 0x03811300 },
            { .reg = 0x00009888, .val = 0x05811B12 },
            { .reg = 0x00009888, .val = 0x0781001A },
            { .reg = 0x00009888, .val = 0x1F810000 },
            { .reg = 0x00009888, .val = 0x17810000 },
            { .reg = 0x00009888, .val = 0x19810000 },
            { .reg = 0x00009888, .val = 0x1B810000 },
            { .reg = 0x00009888, .val = 0x1D810000 },
            { .reg = 0x00009888, .val = 0x0F968000 },
            { .reg = 0x00009888, .val = 0x1196C000 },
            { .reg = 0x00009888, .val = 0x13964000 },
            { .reg = 0x00009888, .val = 0x11938000 },
            { .reg = 0x00009888, .val = 0x1B93FE00 },
            { .reg = 0x00009888, .val = 0x01940010 },
            { .reg = 0x00009888, .val = 0x07941100 },
            { .reg = 0x00009888, .val = 0x09941312 },
            { .reg = 0x00009888, .val = 0x0B941514 },
            { .reg = 0x00009888, .val = 0x0D941716 },
            { .reg = 0x00009888, .val = 0x11940000 },
            { .reg = 0x00009888, .val = 0x19940000 },
            { .reg = 0x00009888, .val = 0x1B940000 },
            { .reg = 0x00009888, .val = 0x1D940000 },
            { .reg = 0x00009888, .val = 0x1B954000 },
            { .reg = 0x00009888, .val = 0x1D95A550 },
            { .reg = 0x00009888, .val = 0x1F9502AA },
            { .reg = 0x00009888, .val = 0x2F900167 },
            { .reg = 0x00009888, .val = 0x31900105 },
            { .reg = 0x00009888, .val = 0x15900103 },
            { .reg = 0x00009888, .val = 0x17900101 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x13908000 },
            { .reg = 0x00009888, .val = 0x21908000 },
            { .reg = 0x00009888, .val = 0x23908000 },
            { .reg = 0x00009888, .val = 0x25908000 },
            { .reg = 0x00009888, .val = 0x27908000 },
            { .reg = 0x00009888, .val = 0x29908000 },
            { .reg = 0x00009888, .val = 0x2B908000 },
            { .reg = 0x00009888, .val = 0x2D908000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B908000 },
            { .reg = 0x00009888, .val = 0x1D908000 },
            { .reg = 0x00009888, .val = 0x1F908000 },
            { .reg = 0x00009888, .val = 0x11900000 },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900C00 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900000 },
            { .reg = 0x00009888, .val = 0x47900000 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900000 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900063 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900003 },
            { .reg = 0x00009888, .val = 0x53900000 },
            { .reg = 0x00009840, .val = 0x00000080 },
            { .reg = 0x00009840, .val = 0x00000080 },
            { .reg = 0x00009888, .val = 0x11810C00 },
            { .reg = 0x00009888, .val = 0x1381001A },
            { .reg = 0x00009888, .val = 0x37906800 },
            { .reg = 0x00009888, .val = 0x3F901000 },
            { .reg = 0x00009888, .val = 0x03811300 },
            { .reg = 0x00009888, .val = 0x05811B12 },
            { .reg = 0x00009888, .val = 0x0781001A },
            { .reg = 0x00009888, .val = 0x1F810000 },
            { .reg = 0x00009888, .val = 0x17810000 },
            { .reg = 0x00009888, .val = 0x19810000 },
            { .reg = 0x00009888, .val = 0x1B810000 },
            { .reg = 0x00009888, .val = 0x1D810000 },
            { .reg = 0x00009888, .val = 0x1B930055 },
            { .reg = 0x00009888, .val = 0x03E58000 },
            { .reg = 0x00009888, .val = 0x05E5C000 },
            { .reg = 0x00009888, .val = 0x07E54000 },
            { .reg = 0x00009888, .val = 0x13900160 },
            { .reg = 0x00009888, .val = 0x21900161 },
            { .reg = 0x00009888, .val = 0x23900162 },
            { .reg = 0x00009888, .val = 0x25900163 },
            { .reg = 0x00009888, .val = 0x27900164 },
            { .reg = 0x00009888, .val = 0x29900165 },
            { .reg = 0x00009888, .val = 0x2B900166 },
            { .reg = 0x00009888, .val = 0x2D900167 },
            { .reg = 0x00009888, .val = 0x2F900150 },
            { .reg = 0x00009888, .val = 0x31900105 },
            { .reg = 0x00009888, .val = 0x15900103 },
            { .reg = 0x00009888, .val = 0x17900101 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B908000 },
            { .reg = 0x00009888, .val = 0x1D908000 },
            { .reg = 0x00009888, .val = 0x1F908000 },
            { .reg = 0x00009888, .val = 0x11900000 },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900C60 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900C00 },
            { .reg = 0x00009888, .val = 0x47900C63 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900C63 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900063 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900003 },
            { .reg = 0x00009888, .val = 0x53900000 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if ((perf->devinfo.revision < 0x05) &&
          (perf->devinfo.revision >= 0x02)) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x11810C00 },
            { .reg = 0x00009888, .val = 0x1381001A },
            { .reg = 0x00009888, .val = 0x13945400 },
            { .reg = 0x00009888, .val = 0x37906800 },
            { .reg = 0x00009888, .val = 0x3F901400 },
            { .reg = 0x00009888, .val = 0x03811300 },
            { .reg = 0x00009888, .val = 0x05811B12 },
            { .reg = 0x00009888, .val = 0x0781001A },
            { .reg = 0x00009888, .val = 0x1F810000 },
            { .reg = 0x00009888, .val = 0x17810000 },
            { .reg = 0x00009888, .val = 0x19810000 },
            { .reg = 0x00009888, .val = 0x1B810000 },
            { .reg = 0x00009888, .val = 0x1D810000 },
            { .reg = 0x00009888, .val = 0x19930800 },
            { .reg = 0x00009888, .val = 0x1B93AA55 },
            { .reg = 0x00009888, .val = 0x1D93002A },
            { .reg = 0x00009888, .val = 0x01940010 },
            { .reg = 0x00009888, .val = 0x07941100 },
            { .reg = 0x00009888, .val = 0x09941312 },
            { .reg = 0x00009888, .val = 0x0B941514 },
            { .reg = 0x00009888, .val = 0x0D941716 },
            { .reg = 0x00009888, .val = 0x1B940000 },
            { .reg = 0x00009888, .val = 0x11940000 },
            { .reg = 0x00009888, .val = 0x01E58000 },
            { .reg = 0x00009888, .val = 0x03E57000 },
            { .reg = 0x00009888, .val = 0x2F900167 },
            { .reg = 0x00009888, .val = 0x31900105 },
            { .reg = 0x00009888, .val = 0x15900103 },
            { .reg = 0x00009888, .val = 0x17900101 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x13908000 },
            { .reg = 0x00009888, .val = 0x21908000 },
            { .reg = 0x00009888, .val = 0x23908000 },
            { .reg = 0x00009888, .val = 0x25908000 },
            { .reg = 0x00009888, .val = 0x27908000 },
            { .reg = 0x00009888, .val = 0x29908000 },
            { .reg = 0x00009888, .val = 0x2B908000 },
            { .reg = 0x00009888, .val = 0x2D908000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B908000 },
            { .reg = 0x00009888, .val = 0x1D908000 },
            { .reg = 0x00009888, .val = 0x1F908000 },
            { .reg = 0x00009888, .val = 0x11900000 },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900C20 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900400 },
            { .reg = 0x00009888, .val = 0x47900421 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900421 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900063 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900003 },
            { .reg = 0x00009888, .val = 0x53900000 },
            { .reg = 0x00009840, .val = 0x00000080 },
            { .reg = 0x00009840, .val = 0x00000080 },
            { .reg = 0x00009888, .val = 0x11810C00 },
            { .reg = 0x00009888, .val = 0x1381001A },
            { .reg = 0x00009888, .val = 0x37906800 },
            { .reg = 0x00009888, .val = 0x3F901000 },
            { .reg = 0x00009888, .val = 0x03811300 },
            { .reg = 0x00009888, .val = 0x05811B12 },
            { .reg = 0x00009888, .val = 0x0781001A },
            { .reg = 0x00009888, .val = 0x1F810000 },
            { .reg = 0x00009888, .val = 0x17810000 },
            { .reg = 0x00009888, .val = 0x19810000 },
            { .reg = 0x00009888, .val = 0x1B810000 },
            { .reg = 0x00009888, .val = 0x1D810000 },
            { .reg = 0x00009888, .val = 0x1B930055 },
            { .reg = 0x00009888, .val = 0x03E58000 },
            { .reg = 0x00009888, .val = 0x05E5C000 },
            { .reg = 0x00009888, .val = 0x07E54000 },
            { .reg = 0x00009888, .val = 0x13900160 },
            { .reg = 0x00009888, .val = 0x21900161 },
            { .reg = 0x00009888, .val = 0x23900162 },
            { .reg = 0x00009888, .val = 0x25900163 },
            { .reg = 0x00009888, .val = 0x27900164 },
            { .reg = 0x00009888, .val = 0x29900165 },
            { .reg = 0x00009888, .val = 0x2B900166 },
            { .reg = 0x00009888, .val = 0x2D900167 },
            { .reg = 0x00009888, .val = 0x2F900150 },
            { .reg = 0x00009888, .val = 0x31900105 },
            { .reg = 0x00009888, .val = 0x15900103 },
            { .reg = 0x00009888, .val = 0x17900101 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x19908000 },
            { .reg = 0x00009888, .val = 0x1B908000 },
            { .reg = 0x00009888, .val = 0x1D908000 },
            { .reg = 0x00009888, .val = 0x1F908000 },
            { .reg = 0x00009888, .val = 0x11900000 },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900C60 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900C00 },
            { .reg = 0x00009888, .val = 0x47900C63 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900C63 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900063 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900003 },
            { .reg = 0x00009888, .val = 0x53900000 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__memory_writes__avg_gpu_core_frequency__max,sklgt2__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,sklgt2__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,sklgt2__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,sklgt2__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,sklgt2__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,sklgt2__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,sklgt2__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,sklgt2__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,sklgt2__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,sklgt2__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, sklgt2__memory_writes__slm_bytes_read__max,sklgt2__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, sklgt2__memory_writes__slm_bytes_written__max,sklgt2__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,sklgt2__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,sklgt2__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, sklgt2__memory_writes__l3_shader_throughput__max,sklgt2__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,sklgt2__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,sklgt2__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,sklgt2__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,sklgt2__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,sklgt2__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,sklgt2__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,sklgt2__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,sklgt2__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,sklgt2__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,sklgt2__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,sklgt2__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,sklgt2__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,sklgt2__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,sklgt2__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,sklgt2__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended metrics set";
   query->symbol_name = "ComputeExtended";
   query->guid = "c26b1fda-2752-4a33-a448-4c8718366846";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->sys_vars.subslice_mask & 0x01) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x000000A0 },
            { .reg = 0x00009888, .val = 0x106C00E0 },
            { .reg = 0x00009888, .val = 0x141C8160 },
            { .reg = 0x00009888, .val = 0x161C8015 },
            { .reg = 0x00009888, .val = 0x181C0120 },
            { .reg = 0x00009888, .val = 0x004E8000 },
            { .reg = 0x00009888, .val = 0x0E4E8000 },
            { .reg = 0x00009888, .val = 0x184E8000 },
            { .reg = 0x00009888, .val = 0x1A4EAAA0 },
            { .reg = 0x00009888, .val = 0x1C4E0002 },
            { .reg = 0x00009888, .val = 0x024E8000 },
            { .reg = 0x00009888, .val = 0x044E8000 },
            { .reg = 0x00009888, .val = 0x064E8000 },
            { .reg = 0x00009888, .val = 0x084E8000 },
            { .reg = 0x00009888, .val = 0x0A4E8000 },
            { .reg = 0x00009888, .val = 0x0E6C0B01 },
            { .reg = 0x00009888, .val = 0x006C0200 },
            { .reg = 0x00009888, .val = 0x026C000C },
            { .reg = 0x00009888, .val = 0x1C6C0000 },
            { .reg = 0x00009888, .val = 0x1E6C0000 },
            { .reg = 0x00009888, .val = 0x1A6C0000 },
            { .reg = 0x00009888, .val = 0x0E1BC000 },
            { .reg = 0x00009888, .val = 0x001B8000 },
            { .reg = 0x00009888, .val = 0x021BC000 },
            { .reg = 0x00009888, .val = 0x001C0041 },
            { .reg = 0x00009888, .val = 0x061C4200 },
            { .reg = 0x00009888, .val = 0x081C4443 },
            { .reg = 0x00009888, .val = 0x0A1C4645 },
            { .reg = 0x00009888, .val = 0x0C1C7647 },
            { .reg = 0x00009888, .val = 0x041C7357 },
            { .reg = 0x00009888, .val = 0x1C1C0030 },
            { .reg = 0x00009888, .val = 0x101C0000 },
            { .reg = 0x00009888, .val = 0x1A1C0000 },
            { .reg = 0x00009888, .val = 0x121C8000 },
            { .reg = 0x00009888, .val = 0x004C8000 },
            { .reg = 0x00009888, .val = 0x0A4CAA2A },
            { .reg = 0x00009888, .val = 0x0C4C02AA },
            { .reg = 0x00009888, .val = 0x084CA000 },
            { .reg = 0x00009888, .val = 0x000DA000 },
            { .reg = 0x00009888, .val = 0x060D8000 },
            { .reg = 0x00009888, .val = 0x080DA000 },
            { .reg = 0x00009888, .val = 0x0A0DA000 },
            { .reg = 0x00009888, .val = 0x0C0DA000 },
            { .reg = 0x00009888, .val = 0x0E0DA000 },
            { .reg = 0x00009888, .val = 0x020DA000 },
            { .reg = 0x00009888, .val = 0x040DA000 },
            { .reg = 0x00009888, .val = 0x0C0F5400 },
            { .reg = 0x00009888, .val = 0x0E0F5515 },
            { .reg = 0x00009888, .val = 0x100F0155 },
            { .reg = 0x00009888, .val = 0x002C8000 },
            { .reg = 0x00009888, .val = 0x0E2C8000 },
            { .reg = 0x00009888, .val = 0x162CAA00 },
            { .reg = 0x00009888, .val = 0x182C00AA },
            { .reg = 0x00009888, .val = 0x022C8000 },
            { .reg = 0x00009888, .val = 0x042C8000 },
            { .reg = 0x00009888, .val = 0x062C8000 },
            { .reg = 0x00009888, .val = 0x082C8000 },
            { .reg = 0x00009888, .val = 0x0A2C8000 },
            { .reg = 0x00009888, .val = 0x11907FFF },
            { .reg = 0x00009888, .val = 0x51900000 },
            { .reg = 0x00009888, .val = 0x41900040 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x45900802 },
            { .reg = 0x00009888, .val = 0x47900842 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900842 },
            { .reg = 0x00009888, .val = 0x37900000 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4B900000 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x43900800 },
            { .reg = 0x00009888, .val = 0x53900000 },
            { .reg = 0x00009840, .val = 0x00000080 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__compute_extended__avg_gpu_core_frequency__max,sklgt2__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,sklgt2__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,sklgt2__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,sklgt2__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,sklgt2__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,sklgt2__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,sklgt2__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, sklgt2__compute_extended__eu_avg_ipc_rate__max,sklgt2__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,sklgt2__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,sklgt2__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,sklgt2__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,sklgt2__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, sklgt2__compute_extended__slm_bytes_read__max,sklgt2__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, sklgt2__compute_extended__slm_bytes_written__max,sklgt2__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,sklgt2__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,sklgt2__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, sklgt2__compute_extended__l3_shader_throughput__max,sklgt2__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,sklgt2__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,sklgt2__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,sklgt2__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,sklgt2__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,sklgt2__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,sklgt2__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,sklgt2__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,sklgt2__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,sklgt2__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,sklgt2__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,sklgt2__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,sklgt2__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,sklgt2__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,sklgt2__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 232, NULL,sklgt2__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 236, NULL,sklgt2__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 240, NULL,sklgt2__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 244, NULL,sklgt2__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 248, NULL,sklgt2__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 54);

   query->name = "Compute Metrics L3 Cache metrics set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "9fb22842-e708-43f7-9752-e0e41670c39e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x166C0760 },
         { .reg = 0x00009888, .val = 0x1593001E },
         { .reg = 0x00009888, .val = 0x3F901403 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4E8020 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x006C0051 },
         { .reg = 0x00009888, .val = 0x066C5000 },
         { .reg = 0x00009888, .val = 0x086C5C5D },
         { .reg = 0x00009888, .val = 0x0E6C5E5F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x061B8000 },
         { .reg = 0x00009888, .val = 0x081BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1CE000 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2A00 },
         { .reg = 0x00009888, .val = 0x0C4C0280 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F1500 },
         { .reg = 0x00009888, .val = 0x100F0140 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x182C00A0 },
         { .reg = 0x00009888, .val = 0x03933300 },
         { .reg = 0x00009888, .val = 0x05930032 },
         { .reg = 0x00009888, .val = 0x11930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900167 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190030F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900042 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x53901111 },
         { .reg = 0x00009888, .val = 0x43900420 },
         { .reg = 0x00009840, .val = 0x00000080 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__compute_l3_cache__avg_gpu_core_frequency__max,sklgt2__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,sklgt2__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,sklgt2__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, sklgt2__compute_l3_cache__eu_avg_ipc_rate__max,sklgt2__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,sklgt2__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,sklgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,sklgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,sklgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,sklgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,sklgt2__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,sklgt2__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,sklgt2__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,sklgt2__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,sklgt2__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,sklgt2__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,sklgt2__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,sklgt2__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,sklgt2__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,sklgt2__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,sklgt2__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,sklgt2__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,sklgt2__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,sklgt2__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, sklgt2__compute_l3_cache__slm_bytes_read__max,sklgt2__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, sklgt2__compute_l3_cache__slm_bytes_written__max,sklgt2__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,sklgt2__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,sklgt2__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 256, NULL,sklgt2__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 264, NULL,sklgt2__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, sklgt2__compute_l3_cache__l3_sampler_throughput__max,sklgt2__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 280, sklgt2__compute_l3_cache__l3_shader_throughput__max,sklgt2__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 288, sklgt2__compute_l3_cache__l3_total_throughput__max,sklgt2__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,sklgt2__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 304, NULL,sklgt2__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 312, NULL,sklgt2__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 320, NULL,sklgt2__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 328, NULL,sklgt2__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 336, NULL,sklgt2__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 344, NULL,sklgt2__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 352, sklgt2__compute_l3_cache__gti_l3_throughput__max,sklgt2__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 360, sklgt2__compute_l3_cache__gti_read_throughput__max,sklgt2__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 368, sklgt2__compute_l3_cache__gti_write_throughput__max,sklgt2__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "b4aa5e13-2d25-418f-827d-421f5cc4c43b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x104F0232 },
         { .reg = 0x00009888, .val = 0x124F4640 },
         { .reg = 0x00009888, .val = 0x106C0232 },
         { .reg = 0x00009888, .val = 0x11834400 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x004F1880 },
         { .reg = 0x00009888, .val = 0x024F08BB },
         { .reg = 0x00009888, .val = 0x044F001B },
         { .reg = 0x00009888, .val = 0x046C0100 },
         { .reg = 0x00009888, .val = 0x066C000B },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x041B8000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025BC000 },
         { .reg = 0x00009888, .val = 0x045B4000 },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x165C8000 },
         { .reg = 0x00009888, .val = 0x185C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00A0 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x062CC000 },
         { .reg = 0x00009888, .val = 0x082CC000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x0F8305C0 },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x07830000 },
         { .reg = 0x00009888, .val = 0x1D950080 },
         { .reg = 0x00009888, .val = 0x13928000 },
         { .reg = 0x00009888, .val = 0x0F988000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B9000A0 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__hdc_and_sf__avg_gpu_core_frequency__max,sklgt2__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt2__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt2__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt2__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt2__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt2__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt2__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt2__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt2__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt2__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt2__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt2__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt2__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt2__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt2__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt2__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt2__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt2__hdc_and_sf__slm_bytes_read__max,sklgt2__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt2__hdc_and_sf__slm_bytes_written__max,sklgt2__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt2__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt2__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt2__hdc_and_sf__l3_shader_throughput__max,sklgt2__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt2__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,sklgt2__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 244, percentage_max_float,sklgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,sklgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 238, 252, percentage_max_float,sklgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,sklgt2__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "504000e8-64f2-4aac-8301-51b81aa60d45";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x126C7B40 },
         { .reg = 0x00009888, .val = 0x166C0020 },
         { .reg = 0x00009888, .val = 0x0A603444 },
         { .reg = 0x00009888, .val = 0x0A613400 },
         { .reg = 0x00009888, .val = 0x1A4EA800 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x0C6C5327 },
         { .reg = 0x00009888, .val = 0x0E6C5425 },
         { .reg = 0x00009888, .val = 0x006C2A00 },
         { .reg = 0x00009888, .val = 0x026C285B },
         { .reg = 0x00009888, .val = 0x046C005C },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0800 },
         { .reg = 0x00009888, .val = 0x0C1BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x1C1C003C },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x10600000 },
         { .reg = 0x00009888, .val = 0x04600000 },
         { .reg = 0x00009888, .val = 0x0C610044 },
         { .reg = 0x00009888, .val = 0x10610000 },
         { .reg = 0x00009888, .val = 0x06610000 },
         { .reg = 0x00009888, .val = 0x0C4C02A8 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0154 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190FFC0 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900420 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900021 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900400 },
         { .reg = 0x00009888, .val = 0x43900421 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__l3_1__avg_gpu_core_frequency__max,sklgt2__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt2__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt2__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt2__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt2__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt2__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt2__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt2__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt2__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt2__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt2__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt2__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt2__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt2__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt2__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt2__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt2__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt2__l3_1__slm_bytes_read__max,sklgt2__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt2__l3_1__slm_bytes_written__max,sklgt2__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt2__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt2__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt2__l3_1__l3_shader_throughput__max,sklgt2__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt2__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,sklgt2__l3_1__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,sklgt2__l3_1__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,sklgt2__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,sklgt2__l3_1__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,sklgt2__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_2";
   query->symbol_name = "L3_2";
   query->guid = "f542479b-6685-4670-ad8e-9fe282a2eb5b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x126C02E0 },
         { .reg = 0x00009888, .val = 0x146C0001 },
         { .reg = 0x00009888, .val = 0x0A623400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x026C3324 },
         { .reg = 0x00009888, .val = 0x046C3422 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x06614000 },
         { .reg = 0x00009888, .val = 0x0C620044 },
         { .reg = 0x00009888, .val = 0x10620000 },
         { .reg = 0x00009888, .val = 0x06620000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__l3_2__avg_gpu_core_frequency__max,sklgt2__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt2__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt2__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt2__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt2__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt2__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt2__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt2__l3_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt2__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt2__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt2__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt2__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt2__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt2__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt2__l3_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt2__l3_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt2__l3_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt2__l3_2__slm_bytes_read__max,sklgt2__l3_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt2__l3_2__slm_bytes_written__max,sklgt2__l3_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt2__l3_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt2__l3_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt2__l3_2__l3_shader_throughput__max,sklgt2__l3_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt2__l3_2__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 257, 240, percentage_max_float,sklgt2__l3_2__l30_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 260, 244, percentage_max_float,sklgt2__l3_2__l30_bank2_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,sklgt2__l3_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_3";
   query->symbol_name = "L3_3";
   query->guid = "1cbf1e9f-c2de-4cc2-8d1c-2c33c25a2332";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x126C4E80 },
         { .reg = 0x00009888, .val = 0x146C0000 },
         { .reg = 0x00009888, .val = 0x0A633400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x026C3321 },
         { .reg = 0x00009888, .val = 0x046C342F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C2000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x06604000 },
         { .reg = 0x00009888, .val = 0x0C630044 },
         { .reg = 0x00009888, .val = 0x10630000 },
         { .reg = 0x00009888, .val = 0x06630000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00AA },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__l3_3__avg_gpu_core_frequency__max,sklgt2__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt2__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt2__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt2__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt2__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt2__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt2__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt2__l3_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt2__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt2__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt2__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt2__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt2__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt2__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt2__l3_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt2__l3_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt2__l3_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt2__l3_3__slm_bytes_read__max,sklgt2__l3_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt2__l3_3__slm_bytes_written__max,sklgt2__l3_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt2__l3_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt2__l3_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt2__l3_3__l3_shader_throughput__max,sklgt2__l3_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt2__l3_3__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 253, 240, percentage_max_float,sklgt2__l3_3__l30_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 256, 244, percentage_max_float,sklgt2__l3_3__l30_bank3_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,sklgt2__l3_3__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "b4e54cc8-a3a0-4ccd-9990-65d3184e5a38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x102F3800 },
         { .reg = 0x00009888, .val = 0x144D0500 },
         { .reg = 0x00009888, .val = 0x120D03C0 },
         { .reg = 0x00009888, .val = 0x140D03CF },
         { .reg = 0x00009888, .val = 0x0C0F0004 },
         { .reg = 0x00009888, .val = 0x0C4E4000 },
         { .reg = 0x00009888, .val = 0x042F0480 },
         { .reg = 0x00009888, .val = 0x082F0000 },
         { .reg = 0x00009888, .val = 0x022F0000 },
         { .reg = 0x00009888, .val = 0x0A4C0090 },
         { .reg = 0x00009888, .val = 0x064D0027 },
         { .reg = 0x00009888, .val = 0x004D0000 },
         { .reg = 0x00009888, .val = 0x000D0D40 },
         { .reg = 0x00009888, .val = 0x020D803F },
         { .reg = 0x00009888, .val = 0x040D8023 },
         { .reg = 0x00009888, .val = 0x100D0000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020F0010 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0050 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41901400 },
         { .reg = 0x00009888, .val = 0x43901485 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000EFFF },
         { .reg = 0x00002778, .val = 0x00006000 },
         { .reg = 0x0000277C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt2__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt2__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt2__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt2__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt2__rasterizer_and_pixel_backend__slm_bytes_read__max,sklgt2__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt2__rasterizer_and_pixel_backend__slm_bytes_written__max,sklgt2__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt2__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt2__rasterizer_and_pixel_backend__l3_shader_throughput__max,sklgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt2__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 240, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 244, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 248, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 252, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 256, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,sklgt2__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler";
   query->symbol_name = "Sampler";
   query->guid = "efe7eba4-fd9e-4a09-a92b-334970b5de57";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x14152C00 },
         { .reg = 0x00009888, .val = 0x16150005 },
         { .reg = 0x00009888, .val = 0x121600A0 },
         { .reg = 0x00009888, .val = 0x14352C00 },
         { .reg = 0x00009888, .val = 0x16350005 },
         { .reg = 0x00009888, .val = 0x123600A0 },
         { .reg = 0x00009888, .val = 0x14552C00 },
         { .reg = 0x00009888, .val = 0x16550005 },
         { .reg = 0x00009888, .val = 0x125600A0 },
         { .reg = 0x00009888, .val = 0x062F6000 },
         { .reg = 0x00009888, .val = 0x022F2000 },
         { .reg = 0x00009888, .val = 0x0C4C0050 },
         { .reg = 0x00009888, .val = 0x0A4C0010 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0350 },
         { .reg = 0x00009888, .val = 0x0C0FB000 },
         { .reg = 0x00009888, .val = 0x0E0F00DA },
         { .reg = 0x00009888, .val = 0x182C0028 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x022DC000 },
         { .reg = 0x00009888, .val = 0x042D4000 },
         { .reg = 0x00009888, .val = 0x0C138000 },
         { .reg = 0x00009888, .val = 0x0E132000 },
         { .reg = 0x00009888, .val = 0x0413C000 },
         { .reg = 0x00009888, .val = 0x1C140018 },
         { .reg = 0x00009888, .val = 0x0C157000 },
         { .reg = 0x00009888, .val = 0x0E150078 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x04162180 },
         { .reg = 0x00009888, .val = 0x02160000 },
         { .reg = 0x00009888, .val = 0x04174000 },
         { .reg = 0x00009888, .val = 0x0233A000 },
         { .reg = 0x00009888, .val = 0x04333000 },
         { .reg = 0x00009888, .val = 0x14348000 },
         { .reg = 0x00009888, .val = 0x16348000 },
         { .reg = 0x00009888, .val = 0x02357870 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x04360043 },
         { .reg = 0x00009888, .val = 0x02360000 },
         { .reg = 0x00009888, .val = 0x04371000 },
         { .reg = 0x00009888, .val = 0x0E538000 },
         { .reg = 0x00009888, .val = 0x00538000 },
         { .reg = 0x00009888, .val = 0x06533000 },
         { .reg = 0x00009888, .val = 0x1C540020 },
         { .reg = 0x00009888, .val = 0x12548000 },
         { .reg = 0x00009888, .val = 0x0E557000 },
         { .reg = 0x00009888, .val = 0x00557800 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x06560043 },
         { .reg = 0x00009888, .val = 0x02560000 },
         { .reg = 0x00009888, .val = 0x06571000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900060 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900060 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__sampler__avg_gpu_core_frequency__max,sklgt2__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__sampler__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__sampler__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__sampler__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__sampler__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__sampler__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__sampler__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__sampler__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__sampler__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__sampler__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__sampler__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt2__sampler__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt2__sampler__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt2__sampler__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt2__sampler__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt2__sampler__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt2__sampler__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt2__sampler__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt2__sampler__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt2__sampler__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt2__sampler__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt2__sampler__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt2__sampler__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt2__sampler__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt2__sampler__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt2__sampler__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt2__sampler__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt2__sampler__slm_bytes_read__max,sklgt2__sampler__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt2__sampler__slm_bytes_written__max,sklgt2__sampler__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt2__sampler__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt2__sampler__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt2__sampler__l3_shader_throughput__max,sklgt2__sampler__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt2__sampler__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,sklgt2__sampler__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,sklgt2__sampler__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,sklgt2__sampler__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,sklgt2__sampler__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,sklgt2__sampler__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,sklgt2__sampler__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,sklgt2__sampler__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "e9bd0bbb-c7b7-4a26-a27a-246987354776";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x12120000 },
         { .reg = 0x00009888, .val = 0x12320000 },
         { .reg = 0x00009888, .val = 0x12520000 },
         { .reg = 0x00009888, .val = 0x002F8000 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0015 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F03A0 },
         { .reg = 0x00009888, .val = 0x0C0FF000 },
         { .reg = 0x00009888, .val = 0x0E0F0095 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2D8000 },
         { .reg = 0x00009888, .val = 0x0E2D4000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x02108000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x02118000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x02121880 },
         { .reg = 0x00009888, .val = 0x041219B5 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x02134000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x0C308000 },
         { .reg = 0x00009888, .val = 0x0E304000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x0C318000 },
         { .reg = 0x00009888, .val = 0x0E314000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x0C321A80 },
         { .reg = 0x00009888, .val = 0x0E320033 },
         { .reg = 0x00009888, .val = 0x06320031 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x0C334000 },
         { .reg = 0x00009888, .val = 0x0E331000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0E508000 },
         { .reg = 0x00009888, .val = 0x00508000 },
         { .reg = 0x00009888, .val = 0x02504000 },
         { .reg = 0x00009888, .val = 0x0E518000 },
         { .reg = 0x00009888, .val = 0x00518000 },
         { .reg = 0x00009888, .val = 0x02514000 },
         { .reg = 0x00009888, .val = 0x0E521880 },
         { .reg = 0x00009888, .val = 0x00521A80 },
         { .reg = 0x00009888, .val = 0x02520033 },
         { .reg = 0x00009888, .val = 0x0E534000 },
         { .reg = 0x00009888, .val = 0x00534000 },
         { .reg = 0x00009888, .val = 0x02531000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900062 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x00007FFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x00009FFF },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000EFFF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000F3FF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FDFF },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__tdl_1__avg_gpu_core_frequency__max,sklgt2__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt2__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt2__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt2__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt2__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt2__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt2__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt2__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt2__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt2__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt2__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt2__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt2__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt2__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt2__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt2__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt2__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt2__tdl_1__slm_bytes_read__max,sklgt2__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt2__tdl_1__slm_bytes_written__max,sklgt2__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt2__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt2__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt2__tdl_1__l3_shader_throughput__max,sklgt2__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt2__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 240, percentage_max_float,sklgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 244, percentage_max_float,sklgt2__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 248, percentage_max_float,sklgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 252, percentage_max_float,sklgt2__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 256, percentage_max_float,sklgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 260, percentage_max_float,sklgt2__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,sklgt2__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "0a7accbf-8c55-455f-9984-23e9fb0b826d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x000000A0 },
         { .reg = 0x00009888, .val = 0x12124D60 },
         { .reg = 0x00009888, .val = 0x12322E60 },
         { .reg = 0x00009888, .val = 0x12524D60 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0014 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0FE000 },
         { .reg = 0x00009888, .val = 0x0E0F0097 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x002D8000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x04121FB7 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x00308000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x00318000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x00321B80 },
         { .reg = 0x00009888, .val = 0x0632003F },
         { .reg = 0x00009888, .val = 0x00334000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0250C000 },
         { .reg = 0x00009888, .val = 0x0251C000 },
         { .reg = 0x00009888, .val = 0x02521FB7 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x02535000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900063 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x000091BC, .val = 0xE0500000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__tdl_2__avg_gpu_core_frequency__max,sklgt2__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt2__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt2__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt2__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt2__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt2__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt2__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt2__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt2__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt2__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt2__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt2__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt2__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt2__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt2__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt2__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt2__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt2__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt2__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt2__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt2__tdl_2__slm_bytes_read__max,sklgt2__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt2__tdl_2__slm_bytes_written__max,sklgt2__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt2__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt2__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt2__tdl_2__l3_shader_throughput__max,sklgt2__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt2__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 240, percentage_max_float,sklgt2__tdl_2__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 244, percentage_max_float,sklgt2__tdl_2__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 248, percentage_max_float,sklgt2__tdl_2__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 252, percentage_max_float,sklgt2__tdl_2__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 256, percentage_max_float,sklgt2__tdl_2__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 260, percentage_max_float,sklgt2__tdl_2__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,sklgt2__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "41a24047-7484-4ead-ae37-de907e5ff2b2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x121203E0 },
         { .reg = 0x00009888, .val = 0x123203E0 },
         { .reg = 0x00009888, .val = 0x125203E0 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0A4C0040 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0E0F006C },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x042D8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06114000 },
         { .reg = 0x00009888, .val = 0x06120033 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x04308000 },
         { .reg = 0x00009888, .val = 0x04318000 },
         { .reg = 0x00009888, .val = 0x04321980 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x04334000 },
         { .reg = 0x00009888, .val = 0x04504000 },
         { .reg = 0x00009888, .val = 0x04514000 },
         { .reg = 0x00009888, .val = 0x04520033 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x04531000 },
         { .reg = 0x00009888, .val = 0x1190E000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900C00 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00001000 },
         { .reg = 0x0000E558, .val = 0x00003002 },
         { .reg = 0x0000E658, .val = 0x00005004 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00050012 },
         { .reg = 0x0000E55C, .val = 0x00052051 },
         { .reg = 0x0000E65C, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__compute_extra__avg_gpu_core_frequency__max,sklgt2__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,sklgt2__compute_extra__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 307, 28, percentage_max_float,sklgt2__compute_extra__fpu1_active_adjusted__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_vme_pipe_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Media Vme Pipe metrics set";
   query->symbol_name = "VMEPipe";
   query->guid = "95910492-943f-44bd-9461-390240f243fd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A5800 },
         { .reg = 0x00009888, .val = 0x161A00C0 },
         { .reg = 0x00009888, .val = 0x12180240 },
         { .reg = 0x00009888, .val = 0x14180002 },
         { .reg = 0x00009888, .val = 0x143A5800 },
         { .reg = 0x00009888, .val = 0x163A00C0 },
         { .reg = 0x00009888, .val = 0x12380240 },
         { .reg = 0x00009888, .val = 0x14380002 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x022F8000 },
         { .reg = 0x00009888, .val = 0x042F3000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C1500 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F9500 },
         { .reg = 0x00009888, .val = 0x100F002A },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x0A2DC000 },
         { .reg = 0x00009888, .val = 0x0C2DC000 },
         { .reg = 0x00009888, .val = 0x04193000 },
         { .reg = 0x00009888, .val = 0x081A28C1 },
         { .reg = 0x00009888, .val = 0x001A0000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x0613C000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x00172000 },
         { .reg = 0x00009888, .val = 0x06178000 },
         { .reg = 0x00009888, .val = 0x0817A000 },
         { .reg = 0x00009888, .val = 0x00180037 },
         { .reg = 0x00009888, .val = 0x06180940 },
         { .reg = 0x00009888, .val = 0x08180000 },
         { .reg = 0x00009888, .val = 0x02180000 },
         { .reg = 0x00009888, .val = 0x04183000 },
         { .reg = 0x00009888, .val = 0x06393000 },
         { .reg = 0x00009888, .val = 0x0C3A28C1 },
         { .reg = 0x00009888, .val = 0x003A0000 },
         { .reg = 0x00009888, .val = 0x0A33F000 },
         { .reg = 0x00009888, .val = 0x0C33F000 },
         { .reg = 0x00009888, .val = 0x0A37A000 },
         { .reg = 0x00009888, .val = 0x0C37A000 },
         { .reg = 0x00009888, .val = 0x0A380977 },
         { .reg = 0x00009888, .val = 0x08380000 },
         { .reg = 0x00009888, .val = 0x04380000 },
         { .reg = 0x00009888, .val = 0x06383000 },
         { .reg = 0x00009888, .val = 0x119000FF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900040 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900800 },
         { .reg = 0x00009888, .val = 0x47901000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900844 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00100030 },
         { .reg = 0x00002774, .val = 0x0000FFF9 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFFC },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFF3 },
         { .reg = 0x00002788, .val = 0x00100180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__vme_pipe__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__vme_pipe__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__vme_pipe__avg_gpu_core_frequency__max,sklgt2__vme_pipe__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__vme_pipe__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,sklgt2__vme_pipe__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 40, percentage_max_float,sklgt2__vme_pipe__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 44, percentage_max_float,sklgt2__vme_pipe__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 48, percentage_max_float,sklgt2__vme_pipe__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 52, percentage_max_float,sklgt2__vme_pipe__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 308, 56, percentage_max_float,sklgt2__vme_pipe__vme_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Gpu Rings Busyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "c44a5cf7-886d-477b-bebd-2d738923e4c3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x13805800 },
         { .reg = 0x00009888, .val = 0x05962C00 },
         { .reg = 0x00009888, .val = 0x19950016 },
         { .reg = 0x00009888, .val = 0x21C05800 },
         { .reg = 0x00009888, .val = 0x07800035 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x1D810400 },
         { .reg = 0x00009888, .val = 0x07960025 },
         { .reg = 0x00009888, .val = 0x21960000 },
         { .reg = 0x00009888, .val = 0x0B964000 },
         { .reg = 0x00009888, .val = 0x1B930062 },
         { .reg = 0x00009888, .val = 0x17948000 },
         { .reg = 0x00009888, .val = 0x1B940008 },
         { .reg = 0x00009888, .val = 0x05950075 },
         { .reg = 0x00009888, .val = 0x1D950000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x09924000 },
         { .reg = 0x00009888, .val = 0x05982000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x09978000 },
         { .reg = 0x00009888, .val = 0x0BC000A5 },
         { .reg = 0x00009888, .val = 0x11C00000 },
         { .reg = 0x00009888, .val = 0x05C00000 },
         { .reg = 0x00009888, .val = 0x0BC54000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900C60 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00078000 },
         { .reg = 0x00002774, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__gpu_busyness__avg_gpu_core_frequency__max,sklgt2__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 309, 24, percentage_max_float,sklgt2__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 28, percentage_max_float,sklgt2__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 312, 32, percentage_max_float,sklgt2__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 36, percentage_max_float,sklgt2__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 40, percentage_max_float,sklgt2__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_ff_bottlenecks_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 30);

   query->name = "FF Bottlenecks";
   query->symbol_name = "FfBottlenecks";
   query->guid = "e0b2aae4-9b8f-4211-8df0-f8e8cb203209";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11850019 },
         { .reg = 0x00009888, .val = 0x11860007 },
         { .reg = 0x00009888, .val = 0x19867C00 },
         { .reg = 0x00009888, .val = 0x01870000 },
         { .reg = 0x00009888, .val = 0x15880000 },
         { .reg = 0x00009888, .val = 0x01898000 },
         { .reg = 0x00009888, .val = 0x0B898000 },
         { .reg = 0x00009888, .val = 0x0D890C00 },
         { .reg = 0x00009888, .val = 0x0D808000 },
         { .reg = 0x00009888, .val = 0x118A8000 },
         { .reg = 0x00009888, .val = 0x1B8A2000 },
         { .reg = 0x00009888, .val = 0x1D8A0003 },
         { .reg = 0x00009888, .val = 0x1F810002 },
         { .reg = 0x00009888, .val = 0x0982C000 },
         { .reg = 0x00009888, .val = 0x0D824000 },
         { .reg = 0x00009888, .val = 0x05833000 },
         { .reg = 0x00009888, .val = 0x07831000 },
         { .reg = 0x00009888, .val = 0x0D848000 },
         { .reg = 0x00009888, .val = 0x0D850080 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x09860080 },
         { .reg = 0x00009888, .val = 0x0D860080 },
         { .reg = 0x00009888, .val = 0x07870C80 },
         { .reg = 0x00009888, .val = 0x0B870C80 },
         { .reg = 0x00009888, .val = 0x01880032 },
         { .reg = 0x00009888, .val = 0x0B888032 },
         { .reg = 0x00009888, .val = 0x11880000 },
         { .reg = 0x00009888, .val = 0x07888000 },
         { .reg = 0x00009888, .val = 0x1D930010 },
         { .reg = 0x00009888, .val = 0x1D950013 },
         { .reg = 0x00009888, .val = 0x0DE58000 },
         { .reg = 0x00009888, .val = 0x05924000 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D92C000 },
         { .reg = 0x00009888, .val = 0x0F92C000 },
         { .reg = 0x00009888, .val = 0x11928000 },
         { .reg = 0x00009888, .val = 0x01981000 },
         { .reg = 0x00009888, .val = 0x07984000 },
         { .reg = 0x00009888, .val = 0x0998A000 },
         { .reg = 0x00009888, .val = 0x0B985000 },
         { .reg = 0x00009888, .val = 0x0D982000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29904000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2D908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900020 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x47900400 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00000011 },
         { .reg = 0x0000E758, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__ff_bottlenecks__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__ff_bottlenecks__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__ff_bottlenecks__avg_gpu_core_frequency__max,sklgt2__ff_bottlenecks__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__ff_bottlenecks__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__ff_bottlenecks__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__ff_bottlenecks__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__ff_bottlenecks__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__ff_bottlenecks__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__ff_bottlenecks__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__ff_bottlenecks__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 139, 80, NULL,sklgt2__ff_bottlenecks__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 88, NULL,sklgt2__ff_bottlenecks__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 96, NULL,sklgt2__ff_bottlenecks__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 104, NULL,sklgt2__ff_bottlenecks__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 112, NULL,sklgt2__ff_bottlenecks__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 120, NULL,sklgt2__ff_bottlenecks__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 128, NULL,sklgt2__ff_bottlenecks__samples_blended__read);

      intel_perf_query_add_counter_float(query, 10, 136, percentage_max_float,sklgt2__ff_bottlenecks__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 140, percentage_max_float,sklgt2__ff_bottlenecks__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 144, percentage_max_float,sklgt2__ff_bottlenecks__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 148, percentage_max_float,sklgt2__ff_bottlenecks__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 124, 152, percentage_max_float,sklgt2__ff_bottlenecks__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 156, percentage_max_float,sklgt2__ff_bottlenecks__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 127, 160, percentage_max_float,sklgt2__ff_bottlenecks__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 164, percentage_max_float,sklgt2__ff_bottlenecks__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 329, 168, percentage_max_float,sklgt2__ff_bottlenecks__vs_cl_bypass__read);

      intel_perf_query_add_counter_float(query, 159, 172, percentage_max_float,sklgt2__ff_bottlenecks__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 176, percentage_max_float,sklgt2__ff_bottlenecks__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 330, 180, percentage_max_float,sklgt2__ff_bottlenecks__te_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 184, percentage_max_float,sklgt2__ff_bottlenecks__gs_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "c5384091-ce4c-406c-ab4d-4c530f71c7ae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810000 },
         { .reg = 0x00009888, .val = 0x07810016 },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930040 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__test_oa__avg_gpu_core_frequency__max,sklgt2__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,sklgt2__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,sklgt2__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,sklgt2__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,sklgt2__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,sklgt2__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,sklgt2__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,sklgt2__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,sklgt2__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,sklgt2__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_pma__stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "PMA_Stall";
   query->guid = "27871149-2fa9-40ba-aa73-350d60c03a09";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x122D3080 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0800 },
         { .reg = 0x00009888, .val = 0x0E0FAA00 },
         { .reg = 0x00009888, .val = 0x100F0002 },
         { .reg = 0x00009888, .val = 0x002D0025 },
         { .reg = 0x00009888, .val = 0x062D1300 },
         { .reg = 0x00009888, .val = 0x082D16A4 },
         { .reg = 0x00009888, .val = 0x0A2D162E },
         { .reg = 0x00009888, .val = 0x102D0000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00E00021 },
         { .reg = 0x00002774, .val = 0x0007FFF8 },
         { .reg = 0x00002778, .val = 0x07000101 },
         { .reg = 0x0000277C, .val = 0x0038FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__pma__stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__pma__stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__pma__stall__avg_gpu_core_frequency__max,sklgt2__pma__stall__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 24, percentage_max_float,sklgt2__pma__stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt2_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "04769cac-6809-4f2a-af5d-40022435a8b2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00051050 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00061060 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt2__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt2__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt2__async_compute__avg_gpu_core_frequency__max,sklgt2__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt2__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt2__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt2__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt2__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt2__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt2__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt2__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 150, 80, percentage_max_float,sklgt2__async_compute__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 124, 84, percentage_max_float,sklgt2__async_compute__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 127, 88, percentage_max_float,sklgt2__async_compute__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 331, 92, percentage_max_float,sklgt2__async_compute__cs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,sklgt2__async_compute__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 125, 100, percentage_max_float,sklgt2__async_compute__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,sklgt2__async_compute__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 332, 108, percentage_max_float,sklgt2__async_compute__cs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 154, 112, percentage_max_float,sklgt2__async_compute__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 10, 116, percentage_max_float,sklgt2__async_compute__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 120, percentage_max_float,sklgt2__async_compute__eu_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_sklgt2(struct intel_perf_config *perf)
{
   sklgt2_register_render_basic_counter_query(perf);
   sklgt2_register_compute_basic_counter_query(perf);
   sklgt2_register_render_pipe_profile_counter_query(perf);
   sklgt2_register_memory_reads_counter_query(perf);
   sklgt2_register_memory_writes_counter_query(perf);
   sklgt2_register_compute_extended_counter_query(perf);
   sklgt2_register_compute_l3_cache_counter_query(perf);
   sklgt2_register_hdc_and_sf_counter_query(perf);
   sklgt2_register_l3_1_counter_query(perf);
   sklgt2_register_l3_2_counter_query(perf);
   sklgt2_register_l3_3_counter_query(perf);
   sklgt2_register_rasterizer_and_pixel_backend_counter_query(perf);
   sklgt2_register_sampler_counter_query(perf);
   sklgt2_register_tdl_1_counter_query(perf);
   sklgt2_register_tdl_2_counter_query(perf);
   sklgt2_register_compute_extra_counter_query(perf);
   sklgt2_register_vme_pipe_counter_query(perf);
   sklgt2_register_gpu_busyness_counter_query(perf);
   sklgt2_register_ff_bottlenecks_counter_query(perf);
   sklgt2_register_test_oa_counter_query(perf);
   sklgt2_register_pma__stall_counter_query(perf);
   sklgt2_register_async_compute_counter_query(perf);
}


static void
sklgt3_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "21fef15a-83f4-4ffa-bb81-7da6e38b8e4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C01E0 },
         { .reg = 0x00009888, .val = 0x12170280 },
         { .reg = 0x00009888, .val = 0x12370280 },
         { .reg = 0x00009888, .val = 0x16EC01E0 },
         { .reg = 0x00009888, .val = 0x11930317 },
         { .reg = 0x00009888, .val = 0x159303DF },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x1A4E0380 },
         { .reg = 0x00009888, .val = 0x0A6C0053 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x0A1B4000 },
         { .reg = 0x00009888, .val = 0x1C1C0001 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x042F1000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C8400 },
         { .reg = 0x00009888, .val = 0x0C4C0002 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F6600 },
         { .reg = 0x00009888, .val = 0x100F0001 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x162CA200 },
         { .reg = 0x00009888, .val = 0x062D8000 },
         { .reg = 0x00009888, .val = 0x082D8000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x08133000 },
         { .reg = 0x00009888, .val = 0x00170020 },
         { .reg = 0x00009888, .val = 0x08170021 },
         { .reg = 0x00009888, .val = 0x10170000 },
         { .reg = 0x00009888, .val = 0x0633C000 },
         { .reg = 0x00009888, .val = 0x0833C000 },
         { .reg = 0x00009888, .val = 0x06370800 },
         { .reg = 0x00009888, .val = 0x08370840 },
         { .reg = 0x00009888, .val = 0x10370000 },
         { .reg = 0x00009888, .val = 0x1ACE0200 },
         { .reg = 0x00009888, .val = 0x0AEC5300 },
         { .reg = 0x00009888, .val = 0x10EC0000 },
         { .reg = 0x00009888, .val = 0x1CEC0000 },
         { .reg = 0x00009888, .val = 0x0A9B8000 },
         { .reg = 0x00009888, .val = 0x1C9C0002 },
         { .reg = 0x00009888, .val = 0x0CCC0002 },
         { .reg = 0x00009888, .val = 0x0A8D8000 },
         { .reg = 0x00009888, .val = 0x108F0001 },
         { .reg = 0x00009888, .val = 0x16AC8000 },
         { .reg = 0x00009888, .val = 0x0D933031 },
         { .reg = 0x00009888, .val = 0x0F933E3F },
         { .reg = 0x00009888, .val = 0x01933D00 },
         { .reg = 0x00009888, .val = 0x0393073C },
         { .reg = 0x00009888, .val = 0x0593000E },
         { .reg = 0x00009888, .val = 0x1D930000 },
         { .reg = 0x00009888, .val = 0x19930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x2B908000 },
         { .reg = 0x00009888, .val = 0x2D908000 },
         { .reg = 0x00009888, .val = 0x2F908000 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x15908000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51907710 },
         { .reg = 0x00009888, .val = 0x419020A0 },
         { .reg = 0x00009888, .val = 0x55901515 },
         { .reg = 0x00009888, .val = 0x45900529 },
         { .reg = 0x00009888, .val = 0x47901025 },
         { .reg = 0x00009888, .val = 0x57907770 },
         { .reg = 0x00009888, .val = 0x49902100 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900108 },
         { .reg = 0x00009888, .val = 0x59900007 },
         { .reg = 0x00009888, .val = 0x43902108 },
         { .reg = 0x00009888, .val = 0x53907777 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__render_basic__avg_gpu_core_frequency__max,sklgt3__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,sklgt3__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,sklgt3__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,sklgt3__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,sklgt3__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,sklgt3__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,sklgt3__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,sklgt3__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,sklgt3__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,sklgt3__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,sklgt3__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,sklgt3__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,sklgt3__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,sklgt3__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,sklgt3__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,sklgt3__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,sklgt3__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,sklgt3__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,sklgt3__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,sklgt3__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,sklgt3__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,sklgt3__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,sklgt3__render_basic__sampler1_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,sklgt3__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,sklgt3__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,sklgt3__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,sklgt3__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,sklgt3__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,sklgt3__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,sklgt3__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,sklgt3__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,sklgt3__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 208, NULL,sklgt3__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, sklgt3__render_basic__slm_bytes_read__max,sklgt3__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, sklgt3__render_basic__slm_bytes_written__max,sklgt3__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,sklgt3__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,sklgt3__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,sklgt3__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,sklgt3__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, sklgt3__render_basic__l3_sampler_throughput__max,sklgt3__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, sklgt3__render_basic__l3_shader_throughput__max,sklgt3__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,sklgt3__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, sklgt3__render_basic__gti_vf_throughput__max,sklgt3__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, sklgt3__render_basic__gti_depth_throughput__max,sklgt3__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, sklgt3__render_basic__gti_rcc_throughput__max,sklgt3__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, sklgt3__render_basic__gti_l3_throughput__max,sklgt3__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, sklgt3__render_basic__gti_hdc_lookups_throughput__max,sklgt3__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, sklgt3__render_basic__gti_read_throughput__max,sklgt3__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, sklgt3__render_basic__gti_write_throughput__max,sklgt3__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,sklgt3__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "4320492b-fd03-42ac-922f-dbe1ef3b7b58";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x124F1C00 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x1A4E0820 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x064F0900 },
         { .reg = 0x00009888, .val = 0x084F0032 },
         { .reg = 0x00009888, .val = 0x0A4F1891 },
         { .reg = 0x00009888, .val = 0x0C4F0E00 },
         { .reg = 0x00009888, .val = 0x0E4F003C },
         { .reg = 0x00009888, .val = 0x004F0D80 },
         { .reg = 0x00009888, .val = 0x024F003B },
         { .reg = 0x00009888, .val = 0x006C0002 },
         { .reg = 0x00009888, .val = 0x086C0100 },
         { .reg = 0x00009888, .val = 0x0C6C000C },
         { .reg = 0x00009888, .val = 0x0E6C0B00 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x081B8000 },
         { .reg = 0x00009888, .val = 0x0C1B4000 },
         { .reg = 0x00009888, .val = 0x0E1B8000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1C8000 },
         { .reg = 0x00009888, .val = 0x1C1C0024 },
         { .reg = 0x00009888, .val = 0x065B8000 },
         { .reg = 0x00009888, .val = 0x085B4000 },
         { .reg = 0x00009888, .val = 0x0A5BC000 },
         { .reg = 0x00009888, .val = 0x0C5B8000 },
         { .reg = 0x00009888, .val = 0x0E5B4000 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025B4000 },
         { .reg = 0x00009888, .val = 0x1A5C6000 },
         { .reg = 0x00009888, .val = 0x1C5C001B },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2000 },
         { .reg = 0x00009888, .val = 0x0C4C0208 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2CC000 },
         { .reg = 0x00009888, .val = 0x162CFB00 },
         { .reg = 0x00009888, .val = 0x182C00BE },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x19900157 },
         { .reg = 0x00009888, .val = 0x1B900158 },
         { .reg = 0x00009888, .val = 0x1D900105 },
         { .reg = 0x00009888, .val = 0x1F900103 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x11900FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900863 },
         { .reg = 0x00009888, .val = 0x47900802 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900802 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900002 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900C62 },
         { .reg = 0x00009888, .val = 0x53903333 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__compute_basic__avg_gpu_core_frequency__max,sklgt3__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,sklgt3__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,sklgt3__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, sklgt3__compute_basic__eu_avg_ipc_rate__max,sklgt3__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,sklgt3__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,sklgt3__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,sklgt3__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,sklgt3__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,sklgt3__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,sklgt3__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,sklgt3__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,sklgt3__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,sklgt3__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,sklgt3__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,sklgt3__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, sklgt3__compute_basic__slm_bytes_read__max,sklgt3__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, sklgt3__compute_basic__slm_bytes_written__max,sklgt3__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,sklgt3__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,sklgt3__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, sklgt3__compute_basic__l3_shader_throughput__max,sklgt3__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,sklgt3__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, sklgt3__compute_basic__typed_bytes_read__max,sklgt3__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, sklgt3__compute_basic__typed_bytes_written__max,sklgt3__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, sklgt3__compute_basic__untyped_bytes_read__max,sklgt3__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, sklgt3__compute_basic__untyped_bytes_written__max,sklgt3__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, sklgt3__compute_basic__gti_read_throughput__max,sklgt3__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, sklgt3__compute_basic__gti_write_throughput__max,sklgt3__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x0C0E001F },
         { .reg = 0x00009888, .val = 0x0A0F0000 },
         { .reg = 0x00009888, .val = 0x10116800 },
         { .reg = 0x00009888, .val = 0x178A03E0 },
         { .reg = 0x00009888, .val = 0x11824C00 },
         { .reg = 0x00009888, .val = 0x11830020 },
         { .reg = 0x00009888, .val = 0x13840020 },
         { .reg = 0x00009888, .val = 0x11850019 },
         { .reg = 0x00009888, .val = 0x11860007 },
         { .reg = 0x00009888, .val = 0x01870C40 },
         { .reg = 0x00009888, .val = 0x17880000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0A4C0040 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020E5400 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x080F0040 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0040 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06110012 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x01898000 },
         { .reg = 0x00009888, .val = 0x0D890100 },
         { .reg = 0x00009888, .val = 0x03898000 },
         { .reg = 0x00009888, .val = 0x09808000 },
         { .reg = 0x00009888, .val = 0x0B808000 },
         { .reg = 0x00009888, .val = 0x0380C000 },
         { .reg = 0x00009888, .val = 0x0F8A0075 },
         { .reg = 0x00009888, .val = 0x1D8A0000 },
         { .reg = 0x00009888, .val = 0x118A8000 },
         { .reg = 0x00009888, .val = 0x1B8A4000 },
         { .reg = 0x00009888, .val = 0x138A8000 },
         { .reg = 0x00009888, .val = 0x1D81A000 },
         { .reg = 0x00009888, .val = 0x15818000 },
         { .reg = 0x00009888, .val = 0x17818000 },
         { .reg = 0x00009888, .val = 0x0B820030 },
         { .reg = 0x00009888, .val = 0x07828000 },
         { .reg = 0x00009888, .val = 0x0D824000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0D830003 },
         { .reg = 0x00009888, .val = 0x0583000C },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x03838000 },
         { .reg = 0x00009888, .val = 0x07838000 },
         { .reg = 0x00009888, .val = 0x0B840980 },
         { .reg = 0x00009888, .val = 0x03844D80 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x09848000 },
         { .reg = 0x00009888, .val = 0x09850080 },
         { .reg = 0x00009888, .val = 0x03850003 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x07860000 },
         { .reg = 0x00009888, .val = 0x0F860400 },
         { .reg = 0x00009888, .val = 0x09870032 },
         { .reg = 0x00009888, .val = 0x01888052 },
         { .reg = 0x00009888, .val = 0x11880000 },
         { .reg = 0x00009888, .val = 0x09884000 },
         { .reg = 0x00009888, .val = 0x1B931001 },
         { .reg = 0x00009888, .val = 0x1D930001 },
         { .reg = 0x00009888, .val = 0x19934000 },
         { .reg = 0x00009888, .val = 0x1B958000 },
         { .reg = 0x00009888, .val = 0x1D950094 },
         { .reg = 0x00009888, .val = 0x19958000 },
         { .reg = 0x00009888, .val = 0x09E58000 },
         { .reg = 0x00009888, .val = 0x0BE58000 },
         { .reg = 0x00009888, .val = 0x03E5C000 },
         { .reg = 0x00009888, .val = 0x0592C000 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D924000 },
         { .reg = 0x00009888, .val = 0x0F924000 },
         { .reg = 0x00009888, .val = 0x11928000 },
         { .reg = 0x00009888, .val = 0x1392C000 },
         { .reg = 0x00009888, .val = 0x09924000 },
         { .reg = 0x00009888, .val = 0x01985000 },
         { .reg = 0x00009888, .val = 0x07988000 },
         { .reg = 0x00009888, .val = 0x09981000 },
         { .reg = 0x00009888, .val = 0x0B982000 },
         { .reg = 0x00009888, .val = 0x0D982000 },
         { .reg = 0x00009888, .val = 0x0F989000 },
         { .reg = 0x00009888, .val = 0x05982000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25908000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29908000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1190C080 },
         { .reg = 0x00009888, .val = 0x51901150 },
         { .reg = 0x00009888, .val = 0x41901400 },
         { .reg = 0x00009888, .val = 0x55905111 },
         { .reg = 0x00009888, .val = 0x45901400 },
         { .reg = 0x00009888, .val = 0x479004A5 },
         { .reg = 0x00009888, .val = 0x57903455 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B9000A0 },
         { .reg = 0x00009888, .val = 0x59900001 },
         { .reg = 0x00009888, .val = 0x43900005 },
         { .reg = 0x00009888, .val = 0x53900455 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__render_pipe_profile__avg_gpu_core_frequency__max,sklgt3__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,sklgt3__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,sklgt3__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,sklgt3__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,sklgt3__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,sklgt3__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,sklgt3__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,sklgt3__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,sklgt3__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,sklgt3__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, sklgt3__render_pipe_profile__slm_bytes_read__max,sklgt3__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, sklgt3__render_pipe_profile__slm_bytes_written__max,sklgt3__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,sklgt3__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,sklgt3__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, sklgt3__render_pipe_profile__l3_shader_throughput__max,sklgt3__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,sklgt3__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, NULL,sklgt3__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, NULL,sklgt3__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, NULL,sklgt3__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, NULL,sklgt3__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, NULL,sklgt3__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, NULL,sklgt3__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, NULL,sklgt3__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, NULL,sklgt3__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, NULL,sklgt3__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, NULL,sklgt3__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, NULL,sklgt3__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, NULL,sklgt3__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, NULL,sklgt3__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, NULL,sklgt3__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, NULL,sklgt3__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, NULL,sklgt3__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Reads Distribution metrics set";
   query->symbol_name = "MemoryReads";
   query->guid = "4ca0f3fe-7fd3-4924-98cb-1807d9879767";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900064 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900150 },
         { .reg = 0x00009888, .val = 0x21900151 },
         { .reg = 0x00009888, .val = 0x23900152 },
         { .reg = 0x00009888, .val = 0x25900153 },
         { .reg = 0x00009888, .val = 0x27900154 },
         { .reg = 0x00009888, .val = 0x29900155 },
         { .reg = 0x00009888, .val = 0x2B900156 },
         { .reg = 0x00009888, .val = 0x2D900157 },
         { .reg = 0x00009888, .val = 0x2F90015F },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__memory_reads__avg_gpu_core_frequency__max,sklgt3__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,sklgt3__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,sklgt3__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,sklgt3__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,sklgt3__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,sklgt3__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,sklgt3__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,sklgt3__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,sklgt3__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,sklgt3__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, sklgt3__memory_reads__slm_bytes_read__max,sklgt3__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, sklgt3__memory_reads__slm_bytes_written__max,sklgt3__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,sklgt3__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,sklgt3__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,sklgt3__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 95, 200, NULL,sklgt3__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 208, NULL,sklgt3__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 216, NULL,sklgt3__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 224, NULL,sklgt3__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 232, NULL,sklgt3__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 240, NULL,sklgt3__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 248, NULL,sklgt3__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 256, NULL,sklgt3__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 264, NULL,sklgt3__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 272, NULL,sklgt3__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 280, NULL,sklgt3__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 288, NULL,sklgt3__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 296, NULL,sklgt3__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 304, NULL,sklgt3__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 312, NULL,sklgt3__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metrics set";
   query->symbol_name = "MemoryWrites";
   query->guid = "a0c0172c-ee13-403d-99ff-2bdf6936cf14";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F901000 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900160 },
         { .reg = 0x00009888, .val = 0x21900161 },
         { .reg = 0x00009888, .val = 0x23900162 },
         { .reg = 0x00009888, .val = 0x25900163 },
         { .reg = 0x00009888, .val = 0x27900164 },
         { .reg = 0x00009888, .val = 0x29900165 },
         { .reg = 0x00009888, .val = 0x2B900166 },
         { .reg = 0x00009888, .val = 0x2D900167 },
         { .reg = 0x00009888, .val = 0x2F900150 },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__memory_writes__avg_gpu_core_frequency__max,sklgt3__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,sklgt3__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,sklgt3__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,sklgt3__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,sklgt3__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,sklgt3__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,sklgt3__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,sklgt3__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,sklgt3__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,sklgt3__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, sklgt3__memory_writes__slm_bytes_read__max,sklgt3__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, sklgt3__memory_writes__slm_bytes_written__max,sklgt3__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,sklgt3__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,sklgt3__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, sklgt3__memory_writes__l3_shader_throughput__max,sklgt3__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,sklgt3__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,sklgt3__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,sklgt3__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,sklgt3__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,sklgt3__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,sklgt3__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,sklgt3__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,sklgt3__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,sklgt3__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,sklgt3__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,sklgt3__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,sklgt3__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,sklgt3__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,sklgt3__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,sklgt3__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended set";
   query->symbol_name = "ComputeExtended";
   query->guid = "52435e0b-f188-42ea-8680-21a56ee20dee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x141C8160 },
         { .reg = 0x00009888, .val = 0x161C8015 },
         { .reg = 0x00009888, .val = 0x181C0120 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4EAAA0 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0E6C0B01 },
         { .reg = 0x00009888, .val = 0x006C0200 },
         { .reg = 0x00009888, .val = 0x026C000C },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x001C0041 },
         { .reg = 0x00009888, .val = 0x061C4200 },
         { .reg = 0x00009888, .val = 0x081C4443 },
         { .reg = 0x00009888, .val = 0x0A1C4645 },
         { .reg = 0x00009888, .val = 0x0C1C7647 },
         { .reg = 0x00009888, .val = 0x041C7357 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x1A1C0000 },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4CAA2A },
         { .reg = 0x00009888, .val = 0x0C4C02AA },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5515 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x11907FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900040 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900802 },
         { .reg = 0x00009888, .val = 0x47900842 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900842 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900800 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__compute_extended__avg_gpu_core_frequency__max,sklgt3__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,sklgt3__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,sklgt3__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,sklgt3__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,sklgt3__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,sklgt3__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,sklgt3__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, sklgt3__compute_extended__eu_avg_ipc_rate__max,sklgt3__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,sklgt3__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,sklgt3__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,sklgt3__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,sklgt3__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, sklgt3__compute_extended__slm_bytes_read__max,sklgt3__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, sklgt3__compute_extended__slm_bytes_written__max,sklgt3__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,sklgt3__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,sklgt3__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, sklgt3__compute_extended__l3_shader_throughput__max,sklgt3__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,sklgt3__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,sklgt3__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,sklgt3__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,sklgt3__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,sklgt3__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,sklgt3__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,sklgt3__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,sklgt3__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,sklgt3__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,sklgt3__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,sklgt3__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,sklgt3__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,sklgt3__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,sklgt3__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 232, NULL,sklgt3__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 236, NULL,sklgt3__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 240, NULL,sklgt3__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 244, NULL,sklgt3__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 248, NULL,sklgt3__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 54);

   query->name = "Compute Metrics L3 Cache set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "27076eeb-49f3-4fed-8423-c66506005c63";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C0760 },
         { .reg = 0x00009888, .val = 0x1593001E },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4E8020 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x006C0051 },
         { .reg = 0x00009888, .val = 0x066C5000 },
         { .reg = 0x00009888, .val = 0x086C5C5D },
         { .reg = 0x00009888, .val = 0x0E6C5E5F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x061B8000 },
         { .reg = 0x00009888, .val = 0x081BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1CE000 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2A00 },
         { .reg = 0x00009888, .val = 0x0C4C0280 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F1500 },
         { .reg = 0x00009888, .val = 0x100F0140 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x182C00A0 },
         { .reg = 0x00009888, .val = 0x03933300 },
         { .reg = 0x00009888, .val = 0x05930032 },
         { .reg = 0x00009888, .val = 0x11930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190030F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900063 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x53903333 },
         { .reg = 0x00009888, .val = 0x43900840 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__compute_l3_cache__avg_gpu_core_frequency__max,sklgt3__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,sklgt3__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,sklgt3__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, sklgt3__compute_l3_cache__eu_avg_ipc_rate__max,sklgt3__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,sklgt3__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,sklgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,sklgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,sklgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,sklgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,sklgt3__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,sklgt3__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,sklgt3__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,sklgt3__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,sklgt3__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,sklgt3__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,sklgt3__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,sklgt3__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,sklgt3__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,sklgt3__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,sklgt3__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,sklgt3__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,sklgt3__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,sklgt3__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, sklgt3__compute_l3_cache__slm_bytes_read__max,sklgt3__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, sklgt3__compute_l3_cache__slm_bytes_written__max,sklgt3__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,sklgt3__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,sklgt3__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 256, NULL,sklgt3__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 264, NULL,sklgt3__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, sklgt3__compute_l3_cache__l3_sampler_throughput__max,sklgt3__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 280, sklgt3__compute_l3_cache__l3_shader_throughput__max,sklgt3__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 288, sklgt3__compute_l3_cache__l3_total_throughput__max,sklgt3__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,sklgt3__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 304, NULL,sklgt3__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 312, NULL,sklgt3__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 320, NULL,sklgt3__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 328, NULL,sklgt3__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 336, NULL,sklgt3__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 344, NULL,sklgt3__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 352, sklgt3__compute_l3_cache__gti_l3_throughput__max,sklgt3__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 360, sklgt3__compute_l3_cache__gti_read_throughput__max,sklgt3__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 368, sklgt3__compute_l3_cache__gti_write_throughput__max,sklgt3__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "a1b8363b-b986-47b6-929a-847afde3dec8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F0232 },
         { .reg = 0x00009888, .val = 0x124F4640 },
         { .reg = 0x00009888, .val = 0x106C0232 },
         { .reg = 0x00009888, .val = 0x11834400 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x004F1880 },
         { .reg = 0x00009888, .val = 0x024F08BB },
         { .reg = 0x00009888, .val = 0x044F001B },
         { .reg = 0x00009888, .val = 0x046C0100 },
         { .reg = 0x00009888, .val = 0x066C000B },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x041B8000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025BC000 },
         { .reg = 0x00009888, .val = 0x045B4000 },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x165C8000 },
         { .reg = 0x00009888, .val = 0x185C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00A0 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x062CC000 },
         { .reg = 0x00009888, .val = 0x082CC000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x0F8305C0 },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x07830000 },
         { .reg = 0x00009888, .val = 0x1D950080 },
         { .reg = 0x00009888, .val = 0x13928000 },
         { .reg = 0x00009888, .val = 0x0F988000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x59900005 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__hdc_and_sf__avg_gpu_core_frequency__max,sklgt3__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt3__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt3__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt3__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt3__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt3__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt3__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt3__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt3__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt3__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt3__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt3__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt3__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt3__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt3__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt3__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt3__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt3__hdc_and_sf__slm_bytes_read__max,sklgt3__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt3__hdc_and_sf__slm_bytes_written__max,sklgt3__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt3__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt3__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt3__hdc_and_sf__l3_shader_throughput__max,sklgt3__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt3__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,sklgt3__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 244, percentage_max_float,sklgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,sklgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 238, 252, percentage_max_float,sklgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,sklgt3__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "fa857069-7f95-44c9-a3e0-cb8ccbc35abb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C7B40 },
         { .reg = 0x00009888, .val = 0x166C0020 },
         { .reg = 0x00009888, .val = 0x0A603444 },
         { .reg = 0x00009888, .val = 0x0A613400 },
         { .reg = 0x00009888, .val = 0x1A4EA800 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x0C6C5327 },
         { .reg = 0x00009888, .val = 0x0E6C5425 },
         { .reg = 0x00009888, .val = 0x006C2A00 },
         { .reg = 0x00009888, .val = 0x026C285B },
         { .reg = 0x00009888, .val = 0x046C005C },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0800 },
         { .reg = 0x00009888, .val = 0x0C1BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x1C1C003C },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x10600000 },
         { .reg = 0x00009888, .val = 0x04600000 },
         { .reg = 0x00009888, .val = 0x0C610044 },
         { .reg = 0x00009888, .val = 0x10610000 },
         { .reg = 0x00009888, .val = 0x06610000 },
         { .reg = 0x00009888, .val = 0x0C4C02A8 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0154 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190FFC0 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900420 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900021 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900400 },
         { .reg = 0x00009888, .val = 0x43900421 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__l3_1__avg_gpu_core_frequency__max,sklgt3__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt3__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt3__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt3__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt3__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt3__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt3__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt3__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt3__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt3__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt3__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt3__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt3__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt3__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt3__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt3__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt3__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt3__l3_1__slm_bytes_read__max,sklgt3__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt3__l3_1__slm_bytes_written__max,sklgt3__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt3__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt3__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt3__l3_1__l3_shader_throughput__max,sklgt3__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt3__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,sklgt3__l3_1__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,sklgt3__l3_1__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,sklgt3__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,sklgt3__l3_1__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,sklgt3__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_2";
   query->symbol_name = "L3_2";
   query->guid = "9830a5f3-a5e2-4773-a49d-6371407c382a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C02E0 },
         { .reg = 0x00009888, .val = 0x146C0001 },
         { .reg = 0x00009888, .val = 0x0A623400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x026C3324 },
         { .reg = 0x00009888, .val = 0x046C3422 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x06614000 },
         { .reg = 0x00009888, .val = 0x0C620044 },
         { .reg = 0x00009888, .val = 0x10620000 },
         { .reg = 0x00009888, .val = 0x06620000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__l3_2__avg_gpu_core_frequency__max,sklgt3__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt3__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt3__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt3__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt3__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt3__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt3__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt3__l3_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt3__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt3__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt3__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt3__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt3__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt3__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt3__l3_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt3__l3_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt3__l3_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt3__l3_2__slm_bytes_read__max,sklgt3__l3_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt3__l3_2__slm_bytes_written__max,sklgt3__l3_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt3__l3_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt3__l3_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt3__l3_2__l3_shader_throughput__max,sklgt3__l3_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt3__l3_2__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 257, 240, percentage_max_float,sklgt3__l3_2__l30_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 260, 244, percentage_max_float,sklgt3__l3_2__l30_bank2_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,sklgt3__l3_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_3";
   query->symbol_name = "L3_3";
   query->guid = "59452ceb-24bb-4878-87ec-87aab7b4f9db";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C4E80 },
         { .reg = 0x00009888, .val = 0x146C0000 },
         { .reg = 0x00009888, .val = 0x0A633400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x026C3321 },
         { .reg = 0x00009888, .val = 0x046C342F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C2000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x06604000 },
         { .reg = 0x00009888, .val = 0x0C630044 },
         { .reg = 0x00009888, .val = 0x10630000 },
         { .reg = 0x00009888, .val = 0x06630000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00AA },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__l3_3__avg_gpu_core_frequency__max,sklgt3__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt3__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt3__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt3__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt3__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt3__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt3__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt3__l3_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt3__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt3__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt3__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt3__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt3__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt3__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt3__l3_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt3__l3_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt3__l3_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt3__l3_3__slm_bytes_read__max,sklgt3__l3_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt3__l3_3__slm_bytes_written__max,sklgt3__l3_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt3__l3_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt3__l3_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt3__l3_3__l3_shader_throughput__max,sklgt3__l3_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt3__l3_3__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 253, 240, percentage_max_float,sklgt3__l3_3__l30_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 256, 244, percentage_max_float,sklgt3__l3_3__l30_bank3_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,sklgt3__l3_3__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "d2249ff7-34b4-4203-b474-7c11546f9dae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x102F3800 },
         { .reg = 0x00009888, .val = 0x144D0500 },
         { .reg = 0x00009888, .val = 0x120D03C0 },
         { .reg = 0x00009888, .val = 0x140D03CF },
         { .reg = 0x00009888, .val = 0x0C0F0004 },
         { .reg = 0x00009888, .val = 0x0C4E4000 },
         { .reg = 0x00009888, .val = 0x042F0480 },
         { .reg = 0x00009888, .val = 0x082F0000 },
         { .reg = 0x00009888, .val = 0x022F0000 },
         { .reg = 0x00009888, .val = 0x0A4C0090 },
         { .reg = 0x00009888, .val = 0x064D0027 },
         { .reg = 0x00009888, .val = 0x004D0000 },
         { .reg = 0x00009888, .val = 0x000D0D40 },
         { .reg = 0x00009888, .val = 0x020D803F },
         { .reg = 0x00009888, .val = 0x040D8023 },
         { .reg = 0x00009888, .val = 0x100D0000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020F0010 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0050 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41901400 },
         { .reg = 0x00009888, .val = 0x43901485 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000EFFF },
         { .reg = 0x00002778, .val = 0x00006000 },
         { .reg = 0x0000277C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt3__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt3__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt3__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt3__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt3__rasterizer_and_pixel_backend__slm_bytes_read__max,sklgt3__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt3__rasterizer_and_pixel_backend__slm_bytes_written__max,sklgt3__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt3__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt3__rasterizer_and_pixel_backend__l3_shader_throughput__max,sklgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt3__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 240, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 244, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 248, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 252, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 256, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,sklgt3__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler";
   query->symbol_name = "Sampler";
   query->guid = "c9cf7c63-0065-4226-941e-98590bad8f75";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x14152C00 },
         { .reg = 0x00009888, .val = 0x16150005 },
         { .reg = 0x00009888, .val = 0x121600A0 },
         { .reg = 0x00009888, .val = 0x14352C00 },
         { .reg = 0x00009888, .val = 0x16350005 },
         { .reg = 0x00009888, .val = 0x123600A0 },
         { .reg = 0x00009888, .val = 0x14552C00 },
         { .reg = 0x00009888, .val = 0x16550005 },
         { .reg = 0x00009888, .val = 0x125600A0 },
         { .reg = 0x00009888, .val = 0x062F6000 },
         { .reg = 0x00009888, .val = 0x022F2000 },
         { .reg = 0x00009888, .val = 0x0C4C0050 },
         { .reg = 0x00009888, .val = 0x0A4C0010 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0350 },
         { .reg = 0x00009888, .val = 0x0C0FB000 },
         { .reg = 0x00009888, .val = 0x0E0F00DA },
         { .reg = 0x00009888, .val = 0x182C0028 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x022DC000 },
         { .reg = 0x00009888, .val = 0x042D4000 },
         { .reg = 0x00009888, .val = 0x0C138000 },
         { .reg = 0x00009888, .val = 0x0E132000 },
         { .reg = 0x00009888, .val = 0x0413C000 },
         { .reg = 0x00009888, .val = 0x1C140018 },
         { .reg = 0x00009888, .val = 0x0C157000 },
         { .reg = 0x00009888, .val = 0x0E150078 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x04162180 },
         { .reg = 0x00009888, .val = 0x02160000 },
         { .reg = 0x00009888, .val = 0x04174000 },
         { .reg = 0x00009888, .val = 0x0233A000 },
         { .reg = 0x00009888, .val = 0x04333000 },
         { .reg = 0x00009888, .val = 0x14348000 },
         { .reg = 0x00009888, .val = 0x16348000 },
         { .reg = 0x00009888, .val = 0x02357870 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x04360043 },
         { .reg = 0x00009888, .val = 0x02360000 },
         { .reg = 0x00009888, .val = 0x04371000 },
         { .reg = 0x00009888, .val = 0x0E538000 },
         { .reg = 0x00009888, .val = 0x00538000 },
         { .reg = 0x00009888, .val = 0x06533000 },
         { .reg = 0x00009888, .val = 0x1C540020 },
         { .reg = 0x00009888, .val = 0x12548000 },
         { .reg = 0x00009888, .val = 0x0E557000 },
         { .reg = 0x00009888, .val = 0x00557800 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x06560043 },
         { .reg = 0x00009888, .val = 0x02560000 },
         { .reg = 0x00009888, .val = 0x06571000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900060 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900060 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__sampler__avg_gpu_core_frequency__max,sklgt3__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__sampler__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__sampler__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__sampler__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__sampler__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__sampler__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__sampler__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__sampler__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__sampler__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__sampler__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__sampler__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt3__sampler__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt3__sampler__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt3__sampler__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt3__sampler__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt3__sampler__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt3__sampler__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt3__sampler__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt3__sampler__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt3__sampler__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt3__sampler__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt3__sampler__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt3__sampler__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt3__sampler__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt3__sampler__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt3__sampler__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt3__sampler__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt3__sampler__slm_bytes_read__max,sklgt3__sampler__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt3__sampler__slm_bytes_written__max,sklgt3__sampler__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt3__sampler__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt3__sampler__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt3__sampler__l3_shader_throughput__max,sklgt3__sampler__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt3__sampler__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,sklgt3__sampler__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,sklgt3__sampler__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,sklgt3__sampler__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,sklgt3__sampler__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,sklgt3__sampler__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,sklgt3__sampler__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,sklgt3__sampler__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "e3bb1501-89ca-43fb-8668-9d96159e10a2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12120000 },
         { .reg = 0x00009888, .val = 0x12320000 },
         { .reg = 0x00009888, .val = 0x12520000 },
         { .reg = 0x00009888, .val = 0x002F8000 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0015 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F03A0 },
         { .reg = 0x00009888, .val = 0x0C0FF000 },
         { .reg = 0x00009888, .val = 0x0E0F0095 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2D8000 },
         { .reg = 0x00009888, .val = 0x0E2D4000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x02108000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x02118000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x02121880 },
         { .reg = 0x00009888, .val = 0x041219B5 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x02134000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x0C308000 },
         { .reg = 0x00009888, .val = 0x0E304000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x0C318000 },
         { .reg = 0x00009888, .val = 0x0E314000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x0C321A80 },
         { .reg = 0x00009888, .val = 0x0E320033 },
         { .reg = 0x00009888, .val = 0x06320031 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x0C334000 },
         { .reg = 0x00009888, .val = 0x0E331000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0E508000 },
         { .reg = 0x00009888, .val = 0x00508000 },
         { .reg = 0x00009888, .val = 0x02504000 },
         { .reg = 0x00009888, .val = 0x0E518000 },
         { .reg = 0x00009888, .val = 0x00518000 },
         { .reg = 0x00009888, .val = 0x02514000 },
         { .reg = 0x00009888, .val = 0x0E521880 },
         { .reg = 0x00009888, .val = 0x00521A80 },
         { .reg = 0x00009888, .val = 0x02520033 },
         { .reg = 0x00009888, .val = 0x0E534000 },
         { .reg = 0x00009888, .val = 0x00534000 },
         { .reg = 0x00009888, .val = 0x02531000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900062 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x00007FFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x00009FFF },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000EFFF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000F3FF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FDFF },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__tdl_1__avg_gpu_core_frequency__max,sklgt3__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt3__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt3__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt3__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt3__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt3__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt3__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt3__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt3__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt3__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt3__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt3__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt3__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt3__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt3__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt3__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt3__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt3__tdl_1__slm_bytes_read__max,sklgt3__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt3__tdl_1__slm_bytes_written__max,sklgt3__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt3__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt3__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt3__tdl_1__l3_shader_throughput__max,sklgt3__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt3__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 240, percentage_max_float,sklgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 244, percentage_max_float,sklgt3__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 248, percentage_max_float,sklgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 252, percentage_max_float,sklgt3__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 256, percentage_max_float,sklgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 260, percentage_max_float,sklgt3__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,sklgt3__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "29194a55-7e75-4152-a71f-ef34b1ae4cca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12124D60 },
         { .reg = 0x00009888, .val = 0x12322E60 },
         { .reg = 0x00009888, .val = 0x12524D60 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0014 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0FE000 },
         { .reg = 0x00009888, .val = 0x0E0F0097 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x002D8000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x04121FB7 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x00308000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x00318000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x00321B80 },
         { .reg = 0x00009888, .val = 0x0632003F },
         { .reg = 0x00009888, .val = 0x00334000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0250C000 },
         { .reg = 0x00009888, .val = 0x0251C000 },
         { .reg = 0x00009888, .val = 0x02521FB7 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x02535000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900063 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__tdl_2__avg_gpu_core_frequency__max,sklgt3__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt3__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt3__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt3__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt3__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt3__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt3__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt3__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt3__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt3__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt3__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt3__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt3__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt3__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt3__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt3__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt3__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt3__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt3__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt3__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt3__tdl_2__slm_bytes_read__max,sklgt3__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt3__tdl_2__slm_bytes_written__max,sklgt3__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt3__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt3__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt3__tdl_2__l3_shader_throughput__max,sklgt3__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt3__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 240, percentage_max_float,sklgt3__tdl_2__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 244, percentage_max_float,sklgt3__tdl_2__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 248, percentage_max_float,sklgt3__tdl_2__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 252, percentage_max_float,sklgt3__tdl_2__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 256, percentage_max_float,sklgt3__tdl_2__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 260, percentage_max_float,sklgt3__tdl_2__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,sklgt3__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "2d80a648-7b5a-4e92-bbe7-3b5c76f2e221";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x121203E0 },
         { .reg = 0x00009888, .val = 0x123203E0 },
         { .reg = 0x00009888, .val = 0x125203E0 },
         { .reg = 0x00009888, .val = 0x129203E0 },
         { .reg = 0x00009888, .val = 0x12B203E0 },
         { .reg = 0x00009888, .val = 0x12D203E0 },
         { .reg = 0x00009888, .val = 0x024EC000 },
         { .reg = 0x00009888, .val = 0x044EC000 },
         { .reg = 0x00009888, .val = 0x064EC000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C0042 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F006D },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x042D8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06114000 },
         { .reg = 0x00009888, .val = 0x06120033 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x04308000 },
         { .reg = 0x00009888, .val = 0x04318000 },
         { .reg = 0x00009888, .val = 0x04321980 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x04334000 },
         { .reg = 0x00009888, .val = 0x04504000 },
         { .reg = 0x00009888, .val = 0x04514000 },
         { .reg = 0x00009888, .val = 0x04520033 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x04531000 },
         { .reg = 0x00009888, .val = 0x00AF8000 },
         { .reg = 0x00009888, .val = 0x0ACC0001 },
         { .reg = 0x00009888, .val = 0x008D8000 },
         { .reg = 0x00009888, .val = 0x028DA000 },
         { .reg = 0x00009888, .val = 0x0C8FB000 },
         { .reg = 0x00009888, .val = 0x0E8F0001 },
         { .reg = 0x00009888, .val = 0x06AC8000 },
         { .reg = 0x00009888, .val = 0x02AD4000 },
         { .reg = 0x00009888, .val = 0x02908000 },
         { .reg = 0x00009888, .val = 0x02918000 },
         { .reg = 0x00009888, .val = 0x02921980 },
         { .reg = 0x00009888, .val = 0x00920000 },
         { .reg = 0x00009888, .val = 0x02934000 },
         { .reg = 0x00009888, .val = 0x02B04000 },
         { .reg = 0x00009888, .val = 0x02B14000 },
         { .reg = 0x00009888, .val = 0x02B20033 },
         { .reg = 0x00009888, .val = 0x00B20000 },
         { .reg = 0x00009888, .val = 0x02B31000 },
         { .reg = 0x00009888, .val = 0x00D08000 },
         { .reg = 0x00009888, .val = 0x00D18000 },
         { .reg = 0x00009888, .val = 0x00D21980 },
         { .reg = 0x00009888, .val = 0x00D34000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900402 },
         { .reg = 0x00009888, .val = 0x53901550 },
         { .reg = 0x00009888, .val = 0x45900080 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__compute_extra__avg_gpu_core_frequency__max,sklgt3__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,sklgt3__compute_extra__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 307, 28, percentage_max_float,sklgt3__compute_extra__fpu1_active_adjusted__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_vme_pipe_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Media Vme Pipe metrics set";
   query->symbol_name = "VMEPipe";
   query->guid = "cfae9232-6ffc-42cc-a703-9790016925f0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A5800 },
         { .reg = 0x00009888, .val = 0x161A00C0 },
         { .reg = 0x00009888, .val = 0x12180240 },
         { .reg = 0x00009888, .val = 0x14180002 },
         { .reg = 0x00009888, .val = 0x149A5800 },
         { .reg = 0x00009888, .val = 0x169A00C0 },
         { .reg = 0x00009888, .val = 0x12980240 },
         { .reg = 0x00009888, .val = 0x14980002 },
         { .reg = 0x00009888, .val = 0x1A4E3FC0 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x022F8000 },
         { .reg = 0x00009888, .val = 0x042F3000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C9500 },
         { .reg = 0x00009888, .val = 0x0C4C002A },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0015 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C000A },
         { .reg = 0x00009888, .val = 0x04193000 },
         { .reg = 0x00009888, .val = 0x081A28C1 },
         { .reg = 0x00009888, .val = 0x001A0000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x0613C000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x00172000 },
         { .reg = 0x00009888, .val = 0x06178000 },
         { .reg = 0x00009888, .val = 0x0817A000 },
         { .reg = 0x00009888, .val = 0x00180037 },
         { .reg = 0x00009888, .val = 0x06180940 },
         { .reg = 0x00009888, .val = 0x08180000 },
         { .reg = 0x00009888, .val = 0x02180000 },
         { .reg = 0x00009888, .val = 0x04183000 },
         { .reg = 0x00009888, .val = 0x04AFC000 },
         { .reg = 0x00009888, .val = 0x06AF3000 },
         { .reg = 0x00009888, .val = 0x0ACC4000 },
         { .reg = 0x00009888, .val = 0x0CCC0015 },
         { .reg = 0x00009888, .val = 0x0A8DA000 },
         { .reg = 0x00009888, .val = 0x0C8DA000 },
         { .reg = 0x00009888, .val = 0x0E8F4000 },
         { .reg = 0x00009888, .val = 0x108F0015 },
         { .reg = 0x00009888, .val = 0x16ACA000 },
         { .reg = 0x00009888, .val = 0x18AC000A },
         { .reg = 0x00009888, .val = 0x06993000 },
         { .reg = 0x00009888, .val = 0x0C9A28C1 },
         { .reg = 0x00009888, .val = 0x009A0000 },
         { .reg = 0x00009888, .val = 0x0A93F000 },
         { .reg = 0x00009888, .val = 0x0C93F000 },
         { .reg = 0x00009888, .val = 0x0A97A000 },
         { .reg = 0x00009888, .val = 0x0C97A000 },
         { .reg = 0x00009888, .val = 0x0A980977 },
         { .reg = 0x00009888, .val = 0x08980000 },
         { .reg = 0x00009888, .val = 0x04980000 },
         { .reg = 0x00009888, .val = 0x06983000 },
         { .reg = 0x00009888, .val = 0x119000FF },
         { .reg = 0x00009888, .val = 0x51900050 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900115 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x47900884 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900002 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00100030 },
         { .reg = 0x00002774, .val = 0x0000FFF9 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFFC },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFF3 },
         { .reg = 0x00002788, .val = 0x00100180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__vme_pipe__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__vme_pipe__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__vme_pipe__avg_gpu_core_frequency__max,sklgt3__vme_pipe__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__vme_pipe__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,sklgt3__vme_pipe__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 40, percentage_max_float,sklgt3__vme_pipe__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 44, percentage_max_float,sklgt3__vme_pipe__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 48, percentage_max_float,sklgt3__vme_pipe__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 52, percentage_max_float,sklgt3__vme_pipe__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 308, 56, percentage_max_float,sklgt3__vme_pipe__vme_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Gpu Rings Busyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "0c5058ff-fdf4-4e0d-81fb-c0310fb76525";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x21D05800 },
         { .reg = 0x00009888, .val = 0x13805800 },
         { .reg = 0x00009888, .val = 0x05962C25 },
         { .reg = 0x00009888, .val = 0x19950016 },
         { .reg = 0x00009888, .val = 0x21C05800 },
         { .reg = 0x00009888, .val = 0x09D000A5 },
         { .reg = 0x00009888, .val = 0x11D00000 },
         { .reg = 0x00009888, .val = 0x05D00000 },
         { .reg = 0x00009888, .val = 0x09D54000 },
         { .reg = 0x00009888, .val = 0x07800035 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x1D810400 },
         { .reg = 0x00009888, .val = 0x21960000 },
         { .reg = 0x00009888, .val = 0x0996C000 },
         { .reg = 0x00009888, .val = 0x0B964000 },
         { .reg = 0x00009888, .val = 0x19938000 },
         { .reg = 0x00009888, .val = 0x1B930068 },
         { .reg = 0x00009888, .val = 0x15948000 },
         { .reg = 0x00009888, .val = 0x1B94000C },
         { .reg = 0x00009888, .val = 0x03957500 },
         { .reg = 0x00009888, .val = 0x1D950000 },
         { .reg = 0x00009888, .val = 0x17950000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x07928000 },
         { .reg = 0x00009888, .val = 0x03988000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x09978000 },
         { .reg = 0x00009888, .val = 0x0BC000A5 },
         { .reg = 0x00009888, .val = 0x11C00000 },
         { .reg = 0x00009888, .val = 0x05C00000 },
         { .reg = 0x00009888, .val = 0x0BC54000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900463 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0007C000 },
         { .reg = 0x00002774, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__gpu_busyness__avg_gpu_core_frequency__max,sklgt3__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 309, 24, percentage_max_float,sklgt3__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 28, percentage_max_float,sklgt3__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 32, percentage_max_float,sklgt3__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 312, 36, percentage_max_float,sklgt3__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 40, percentage_max_float,sklgt3__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 44, percentage_max_float,sklgt3__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "14cadcfd-fb3a-46a3-8c13-0a4f850a4b18";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810000 },
         { .reg = 0x00009888, .val = 0x07810013 },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930040 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__test_oa__avg_gpu_core_frequency__max,sklgt3__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,sklgt3__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,sklgt3__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,sklgt3__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,sklgt3__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,sklgt3__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,sklgt3__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,sklgt3__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,sklgt3__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,sklgt3__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_pma__stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "PMA_Stall";
   query->guid = "c889fd93-8dc7-4ba5-9451-de34a8b5ea3f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x122D3080 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0800 },
         { .reg = 0x00009888, .val = 0x0E0FAA00 },
         { .reg = 0x00009888, .val = 0x100F0002 },
         { .reg = 0x00009888, .val = 0x002D0025 },
         { .reg = 0x00009888, .val = 0x062D1300 },
         { .reg = 0x00009888, .val = 0x082D16A4 },
         { .reg = 0x00009888, .val = 0x0A2D162E },
         { .reg = 0x00009888, .val = 0x102D0000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00E00021 },
         { .reg = 0x00002774, .val = 0x0007FFF8 },
         { .reg = 0x00002778, .val = 0x07000101 },
         { .reg = 0x0000277C, .val = 0x0038FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__pma__stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__pma__stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__pma__stall__avg_gpu_core_frequency__max,sklgt3__pma__stall__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 24, percentage_max_float,sklgt3__pma__stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt3_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "9d8e6b6c-c6ec-4591-99b5-7d9983e10d64";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00051050 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00061060 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt3__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt3__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt3__async_compute__avg_gpu_core_frequency__max,sklgt3__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt3__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt3__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt3__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt3__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt3__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt3__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt3__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 150, 80, percentage_max_float,sklgt3__async_compute__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 124, 84, percentage_max_float,sklgt3__async_compute__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 127, 88, percentage_max_float,sklgt3__async_compute__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 331, 92, percentage_max_float,sklgt3__async_compute__cs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,sklgt3__async_compute__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 125, 100, percentage_max_float,sklgt3__async_compute__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,sklgt3__async_compute__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 332, 108, percentage_max_float,sklgt3__async_compute__cs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 154, 112, percentage_max_float,sklgt3__async_compute__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 10, 116, percentage_max_float,sklgt3__async_compute__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 120, percentage_max_float,sklgt3__async_compute__eu_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_sklgt3(struct intel_perf_config *perf)
{
   sklgt3_register_render_basic_counter_query(perf);
   sklgt3_register_compute_basic_counter_query(perf);
   sklgt3_register_render_pipe_profile_counter_query(perf);
   sklgt3_register_memory_reads_counter_query(perf);
   sklgt3_register_memory_writes_counter_query(perf);
   sklgt3_register_compute_extended_counter_query(perf);
   sklgt3_register_compute_l3_cache_counter_query(perf);
   sklgt3_register_hdc_and_sf_counter_query(perf);
   sklgt3_register_l3_1_counter_query(perf);
   sklgt3_register_l3_2_counter_query(perf);
   sklgt3_register_l3_3_counter_query(perf);
   sklgt3_register_rasterizer_and_pixel_backend_counter_query(perf);
   sklgt3_register_sampler_counter_query(perf);
   sklgt3_register_tdl_1_counter_query(perf);
   sklgt3_register_tdl_2_counter_query(perf);
   sklgt3_register_compute_extra_counter_query(perf);
   sklgt3_register_vme_pipe_counter_query(perf);
   sklgt3_register_gpu_busyness_counter_query(perf);
   sklgt3_register_test_oa_counter_query(perf);
   sklgt3_register_pma__stall_counter_query(perf);
   sklgt3_register_async_compute_counter_query(perf);
}


static void
sklgt4_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 51);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "95322a71-bb05-4437-bc27-f7dd7b27d136";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C01E0 },
         { .reg = 0x00009888, .val = 0x12170280 },
         { .reg = 0x00009888, .val = 0x12370280 },
         { .reg = 0x00009888, .val = 0x16EC01E0 },
         { .reg = 0x00009888, .val = 0x176C01E0 },
         { .reg = 0x00009888, .val = 0x11930317 },
         { .reg = 0x00009888, .val = 0x159303DF },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x1A4E03B0 },
         { .reg = 0x00009888, .val = 0x0A6C0053 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x0A1B4000 },
         { .reg = 0x00009888, .val = 0x1C1C0001 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x042F1000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4CA400 },
         { .reg = 0x00009888, .val = 0x0C4C0002 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F5600 },
         { .reg = 0x00009888, .val = 0x100F0001 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x062D8000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x08133000 },
         { .reg = 0x00009888, .val = 0x00170020 },
         { .reg = 0x00009888, .val = 0x08170021 },
         { .reg = 0x00009888, .val = 0x10170000 },
         { .reg = 0x00009888, .val = 0x0633C000 },
         { .reg = 0x00009888, .val = 0x06370800 },
         { .reg = 0x00009888, .val = 0x10370000 },
         { .reg = 0x00009888, .val = 0x1ACE0230 },
         { .reg = 0x00009888, .val = 0x0AEC5300 },
         { .reg = 0x00009888, .val = 0x10EC0000 },
         { .reg = 0x00009888, .val = 0x1CEC0000 },
         { .reg = 0x00009888, .val = 0x0A9B8000 },
         { .reg = 0x00009888, .val = 0x1C9C0002 },
         { .reg = 0x00009888, .val = 0x0ACC2000 },
         { .reg = 0x00009888, .val = 0x0CCC0002 },
         { .reg = 0x00009888, .val = 0x088D8000 },
         { .reg = 0x00009888, .val = 0x0A8D8000 },
         { .reg = 0x00009888, .val = 0x0E8F1000 },
         { .reg = 0x00009888, .val = 0x108F0001 },
         { .reg = 0x00009888, .val = 0x16AC8800 },
         { .reg = 0x00009888, .val = 0x1B4E0020 },
         { .reg = 0x00009888, .val = 0x096C5300 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x1D6C0000 },
         { .reg = 0x00009888, .val = 0x091B8000 },
         { .reg = 0x00009888, .val = 0x1B1C8000 },
         { .reg = 0x00009888, .val = 0x0B4C2000 },
         { .reg = 0x00009888, .val = 0x090D8000 },
         { .reg = 0x00009888, .val = 0x0F0F1000 },
         { .reg = 0x00009888, .val = 0x172C0800 },
         { .reg = 0x00009888, .val = 0x0D933031 },
         { .reg = 0x00009888, .val = 0x0F933E3F },
         { .reg = 0x00009888, .val = 0x01933D00 },
         { .reg = 0x00009888, .val = 0x0393073C },
         { .reg = 0x00009888, .val = 0x0593000E },
         { .reg = 0x00009888, .val = 0x1D930000 },
         { .reg = 0x00009888, .val = 0x19930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x2B908000 },
         { .reg = 0x00009888, .val = 0x2D908000 },
         { .reg = 0x00009888, .val = 0x2F908000 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x15908000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x5190FF30 },
         { .reg = 0x00009888, .val = 0x41900060 },
         { .reg = 0x00009888, .val = 0x55903033 },
         { .reg = 0x00009888, .val = 0x45901421 },
         { .reg = 0x00009888, .val = 0x47900803 },
         { .reg = 0x00009888, .val = 0x5790FFF1 },
         { .reg = 0x00009888, .val = 0x49900001 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x5990000F },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x5390FFFF },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__render_basic__avg_gpu_core_frequency__max,sklgt4__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,sklgt4__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,sklgt4__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,sklgt4__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,sklgt4__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,sklgt4__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,sklgt4__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,sklgt4__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,sklgt4__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,sklgt4__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,sklgt4__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,sklgt4__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,sklgt4__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,sklgt4__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,sklgt4__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,sklgt4__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,sklgt4__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,sklgt4__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,sklgt4__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,sklgt4__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,sklgt4__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,sklgt4__render_basic__sampler0_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,sklgt4__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,sklgt4__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,sklgt4__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,sklgt4__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,sklgt4__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,sklgt4__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,sklgt4__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,sklgt4__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,sklgt4__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 208, NULL,sklgt4__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, sklgt4__render_basic__slm_bytes_read__max,sklgt4__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, sklgt4__render_basic__slm_bytes_written__max,sklgt4__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,sklgt4__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,sklgt4__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,sklgt4__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,sklgt4__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, sklgt4__render_basic__l3_sampler_throughput__max,sklgt4__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, sklgt4__render_basic__l3_shader_throughput__max,sklgt4__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,sklgt4__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, sklgt4__render_basic__gti_vf_throughput__max,sklgt4__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, sklgt4__render_basic__gti_depth_throughput__max,sklgt4__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, sklgt4__render_basic__gti_rcc_throughput__max,sklgt4__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, sklgt4__render_basic__gti_l3_throughput__max,sklgt4__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, sklgt4__render_basic__gti_hdc_lookups_throughput__max,sklgt4__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, sklgt4__render_basic__gti_read_throughput__max,sklgt4__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, sklgt4__render_basic__gti_write_throughput__max,sklgt4__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,sklgt4__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "7277228f-e7f3-4743-945a-6a2049d11377";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x124F1C00 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x1A4E0820 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x064F0900 },
         { .reg = 0x00009888, .val = 0x084F0032 },
         { .reg = 0x00009888, .val = 0x0A4F1891 },
         { .reg = 0x00009888, .val = 0x0C4F0E00 },
         { .reg = 0x00009888, .val = 0x0E4F003C },
         { .reg = 0x00009888, .val = 0x004F0D80 },
         { .reg = 0x00009888, .val = 0x024F003B },
         { .reg = 0x00009888, .val = 0x006C0002 },
         { .reg = 0x00009888, .val = 0x086C0100 },
         { .reg = 0x00009888, .val = 0x0C6C000C },
         { .reg = 0x00009888, .val = 0x0E6C0B00 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x081B8000 },
         { .reg = 0x00009888, .val = 0x0C1B4000 },
         { .reg = 0x00009888, .val = 0x0E1B8000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1C8000 },
         { .reg = 0x00009888, .val = 0x1C1C0024 },
         { .reg = 0x00009888, .val = 0x065B8000 },
         { .reg = 0x00009888, .val = 0x085B4000 },
         { .reg = 0x00009888, .val = 0x0A5BC000 },
         { .reg = 0x00009888, .val = 0x0C5B8000 },
         { .reg = 0x00009888, .val = 0x0E5B4000 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025B4000 },
         { .reg = 0x00009888, .val = 0x1A5C6000 },
         { .reg = 0x00009888, .val = 0x1C5C001B },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2000 },
         { .reg = 0x00009888, .val = 0x0C4C0208 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2CC000 },
         { .reg = 0x00009888, .val = 0x162CFB00 },
         { .reg = 0x00009888, .val = 0x182C00BE },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x19900157 },
         { .reg = 0x00009888, .val = 0x1B900158 },
         { .reg = 0x00009888, .val = 0x1D900105 },
         { .reg = 0x00009888, .val = 0x1F900103 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x11900FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900821 },
         { .reg = 0x00009888, .val = 0x47900802 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900802 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900002 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900422 },
         { .reg = 0x00009888, .val = 0x53905555 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__compute_basic__avg_gpu_core_frequency__max,sklgt4__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,sklgt4__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,sklgt4__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, sklgt4__compute_basic__eu_avg_ipc_rate__max,sklgt4__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,sklgt4__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,sklgt4__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,sklgt4__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,sklgt4__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,sklgt4__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,sklgt4__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,sklgt4__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,sklgt4__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,sklgt4__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,sklgt4__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,sklgt4__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, sklgt4__compute_basic__slm_bytes_read__max,sklgt4__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, sklgt4__compute_basic__slm_bytes_written__max,sklgt4__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,sklgt4__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,sklgt4__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, sklgt4__compute_basic__l3_shader_throughput__max,sklgt4__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,sklgt4__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, sklgt4__compute_basic__typed_bytes_read__max,sklgt4__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, sklgt4__compute_basic__typed_bytes_written__max,sklgt4__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, sklgt4__compute_basic__untyped_bytes_read__max,sklgt4__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, sklgt4__compute_basic__untyped_bytes_written__max,sklgt4__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, sklgt4__compute_basic__gti_read_throughput__max,sklgt4__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, sklgt4__compute_basic__gti_write_throughput__max,sklgt4__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "463c668c-3f60-49b6-8f85-d995b635b3b2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x0C0E001F },
         { .reg = 0x00009888, .val = 0x0A0F0000 },
         { .reg = 0x00009888, .val = 0x10116800 },
         { .reg = 0x00009888, .val = 0x178A03E0 },
         { .reg = 0x00009888, .val = 0x11824C00 },
         { .reg = 0x00009888, .val = 0x11830020 },
         { .reg = 0x00009888, .val = 0x13840020 },
         { .reg = 0x00009888, .val = 0x11850019 },
         { .reg = 0x00009888, .val = 0x11860007 },
         { .reg = 0x00009888, .val = 0x01870C40 },
         { .reg = 0x00009888, .val = 0x17880000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0A4C0040 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020E5400 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x080F0040 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0040 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06110012 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x01898000 },
         { .reg = 0x00009888, .val = 0x0D890100 },
         { .reg = 0x00009888, .val = 0x03898000 },
         { .reg = 0x00009888, .val = 0x09808000 },
         { .reg = 0x00009888, .val = 0x0B808000 },
         { .reg = 0x00009888, .val = 0x0380C000 },
         { .reg = 0x00009888, .val = 0x0F8A0075 },
         { .reg = 0x00009888, .val = 0x1D8A0000 },
         { .reg = 0x00009888, .val = 0x118A8000 },
         { .reg = 0x00009888, .val = 0x1B8A4000 },
         { .reg = 0x00009888, .val = 0x138A8000 },
         { .reg = 0x00009888, .val = 0x1D81A000 },
         { .reg = 0x00009888, .val = 0x15818000 },
         { .reg = 0x00009888, .val = 0x17818000 },
         { .reg = 0x00009888, .val = 0x0B820030 },
         { .reg = 0x00009888, .val = 0x07828000 },
         { .reg = 0x00009888, .val = 0x0D824000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0D830003 },
         { .reg = 0x00009888, .val = 0x0583000C },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x03838000 },
         { .reg = 0x00009888, .val = 0x07838000 },
         { .reg = 0x00009888, .val = 0x0B840980 },
         { .reg = 0x00009888, .val = 0x03844D80 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x09848000 },
         { .reg = 0x00009888, .val = 0x09850080 },
         { .reg = 0x00009888, .val = 0x03850003 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x07860000 },
         { .reg = 0x00009888, .val = 0x0F860400 },
         { .reg = 0x00009888, .val = 0x09870032 },
         { .reg = 0x00009888, .val = 0x01888052 },
         { .reg = 0x00009888, .val = 0x11880000 },
         { .reg = 0x00009888, .val = 0x09884000 },
         { .reg = 0x00009888, .val = 0x1B931001 },
         { .reg = 0x00009888, .val = 0x1D930001 },
         { .reg = 0x00009888, .val = 0x19934000 },
         { .reg = 0x00009888, .val = 0x1B958000 },
         { .reg = 0x00009888, .val = 0x1D950094 },
         { .reg = 0x00009888, .val = 0x19958000 },
         { .reg = 0x00009888, .val = 0x09E58000 },
         { .reg = 0x00009888, .val = 0x0BE58000 },
         { .reg = 0x00009888, .val = 0x03E5C000 },
         { .reg = 0x00009888, .val = 0x0592C000 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D924000 },
         { .reg = 0x00009888, .val = 0x0F924000 },
         { .reg = 0x00009888, .val = 0x11928000 },
         { .reg = 0x00009888, .val = 0x1392C000 },
         { .reg = 0x00009888, .val = 0x09924000 },
         { .reg = 0x00009888, .val = 0x01985000 },
         { .reg = 0x00009888, .val = 0x07988000 },
         { .reg = 0x00009888, .val = 0x09981000 },
         { .reg = 0x00009888, .val = 0x0B982000 },
         { .reg = 0x00009888, .val = 0x0D982000 },
         { .reg = 0x00009888, .val = 0x0F989000 },
         { .reg = 0x00009888, .val = 0x05982000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25908000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29908000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1190C080 },
         { .reg = 0x00009888, .val = 0x51901110 },
         { .reg = 0x00009888, .val = 0x41900440 },
         { .reg = 0x00009888, .val = 0x55901111 },
         { .reg = 0x00009888, .val = 0x45900400 },
         { .reg = 0x00009888, .val = 0x47900C21 },
         { .reg = 0x00009888, .val = 0x57901411 },
         { .reg = 0x00009888, .val = 0x49900042 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900024 },
         { .reg = 0x00009888, .val = 0x59900001 },
         { .reg = 0x00009888, .val = 0x43900841 },
         { .reg = 0x00009888, .val = 0x53900411 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__render_pipe_profile__avg_gpu_core_frequency__max,sklgt4__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,sklgt4__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,sklgt4__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,sklgt4__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,sklgt4__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,sklgt4__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,sklgt4__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,sklgt4__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,sklgt4__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,sklgt4__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, sklgt4__render_pipe_profile__slm_bytes_read__max,sklgt4__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, sklgt4__render_pipe_profile__slm_bytes_written__max,sklgt4__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,sklgt4__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,sklgt4__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, sklgt4__render_pipe_profile__l3_shader_throughput__max,sklgt4__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,sklgt4__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, NULL,sklgt4__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, NULL,sklgt4__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, NULL,sklgt4__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, NULL,sklgt4__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, NULL,sklgt4__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, NULL,sklgt4__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, NULL,sklgt4__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, NULL,sklgt4__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, NULL,sklgt4__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, NULL,sklgt4__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, NULL,sklgt4__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, NULL,sklgt4__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, NULL,sklgt4__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, NULL,sklgt4__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, NULL,sklgt4__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, NULL,sklgt4__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Reads Distribution metrics set";
   query->symbol_name = "MemoryReads";
   query->guid = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900064 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900150 },
         { .reg = 0x00009888, .val = 0x21900151 },
         { .reg = 0x00009888, .val = 0x23900152 },
         { .reg = 0x00009888, .val = 0x25900153 },
         { .reg = 0x00009888, .val = 0x27900154 },
         { .reg = 0x00009888, .val = 0x29900155 },
         { .reg = 0x00009888, .val = 0x2B900156 },
         { .reg = 0x00009888, .val = 0x2D900157 },
         { .reg = 0x00009888, .val = 0x2F90015F },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__memory_reads__avg_gpu_core_frequency__max,sklgt4__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,sklgt4__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,sklgt4__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,sklgt4__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,sklgt4__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,sklgt4__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,sklgt4__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,sklgt4__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,sklgt4__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,sklgt4__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, sklgt4__memory_reads__slm_bytes_read__max,sklgt4__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, sklgt4__memory_reads__slm_bytes_written__max,sklgt4__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,sklgt4__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,sklgt4__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,sklgt4__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 95, 200, NULL,sklgt4__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 208, NULL,sklgt4__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 216, NULL,sklgt4__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 224, NULL,sklgt4__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 232, NULL,sklgt4__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 240, NULL,sklgt4__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 248, NULL,sklgt4__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 256, NULL,sklgt4__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 264, NULL,sklgt4__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 272, NULL,sklgt4__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 280, NULL,sklgt4__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 288, NULL,sklgt4__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 296, NULL,sklgt4__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 304, NULL,sklgt4__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 312, NULL,sklgt4__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metrics set";
   query->symbol_name = "MemoryWrites";
   query->guid = "055f256d-4052-467c-8dec-6064a4806433";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F901000 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900160 },
         { .reg = 0x00009888, .val = 0x21900161 },
         { .reg = 0x00009888, .val = 0x23900162 },
         { .reg = 0x00009888, .val = 0x25900163 },
         { .reg = 0x00009888, .val = 0x27900164 },
         { .reg = 0x00009888, .val = 0x29900165 },
         { .reg = 0x00009888, .val = 0x2B900166 },
         { .reg = 0x00009888, .val = 0x2D900167 },
         { .reg = 0x00009888, .val = 0x2F900150 },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__memory_writes__avg_gpu_core_frequency__max,sklgt4__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,sklgt4__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,sklgt4__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,sklgt4__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,sklgt4__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,sklgt4__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,sklgt4__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,sklgt4__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,sklgt4__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,sklgt4__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, sklgt4__memory_writes__slm_bytes_read__max,sklgt4__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, sklgt4__memory_writes__slm_bytes_written__max,sklgt4__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,sklgt4__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,sklgt4__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, sklgt4__memory_writes__l3_shader_throughput__max,sklgt4__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,sklgt4__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,sklgt4__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,sklgt4__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,sklgt4__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,sklgt4__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,sklgt4__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,sklgt4__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,sklgt4__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,sklgt4__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,sklgt4__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,sklgt4__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,sklgt4__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,sklgt4__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,sklgt4__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,sklgt4__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended set";
   query->symbol_name = "ComputeExtended";
   query->guid = "753972d4-87cd-4460-824d-754463ac5054";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x141C8160 },
         { .reg = 0x00009888, .val = 0x161C8015 },
         { .reg = 0x00009888, .val = 0x181C0120 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4EAAA0 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0E6C0B01 },
         { .reg = 0x00009888, .val = 0x006C0200 },
         { .reg = 0x00009888, .val = 0x026C000C },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x001C0041 },
         { .reg = 0x00009888, .val = 0x061C4200 },
         { .reg = 0x00009888, .val = 0x081C4443 },
         { .reg = 0x00009888, .val = 0x0A1C4645 },
         { .reg = 0x00009888, .val = 0x0C1C7647 },
         { .reg = 0x00009888, .val = 0x041C7357 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x1A1C0000 },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4CAA2A },
         { .reg = 0x00009888, .val = 0x0C4C02AA },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5515 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x11907FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900040 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900802 },
         { .reg = 0x00009888, .val = 0x47900842 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900842 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900800 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__compute_extended__avg_gpu_core_frequency__max,sklgt4__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,sklgt4__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,sklgt4__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,sklgt4__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,sklgt4__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,sklgt4__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,sklgt4__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, sklgt4__compute_extended__eu_avg_ipc_rate__max,sklgt4__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,sklgt4__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,sklgt4__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,sklgt4__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,sklgt4__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, sklgt4__compute_extended__slm_bytes_read__max,sklgt4__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, sklgt4__compute_extended__slm_bytes_written__max,sklgt4__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,sklgt4__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,sklgt4__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, sklgt4__compute_extended__l3_shader_throughput__max,sklgt4__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,sklgt4__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,sklgt4__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,sklgt4__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,sklgt4__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,sklgt4__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,sklgt4__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,sklgt4__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,sklgt4__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,sklgt4__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,sklgt4__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,sklgt4__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,sklgt4__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,sklgt4__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,sklgt4__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 232, NULL,sklgt4__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 236, NULL,sklgt4__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 240, NULL,sklgt4__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 244, NULL,sklgt4__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 248, NULL,sklgt4__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 54);

   query->name = "Compute Metrics L3 Cache set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "4e4392e9-8f73-457b-ab44-b49f7a0c733b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C0760 },
         { .reg = 0x00009888, .val = 0x1593001E },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4E8020 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x006C0051 },
         { .reg = 0x00009888, .val = 0x066C5000 },
         { .reg = 0x00009888, .val = 0x086C5C5D },
         { .reg = 0x00009888, .val = 0x0E6C5E5F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x061B8000 },
         { .reg = 0x00009888, .val = 0x081BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1CE000 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2A00 },
         { .reg = 0x00009888, .val = 0x0C4C0280 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F1500 },
         { .reg = 0x00009888, .val = 0x100F0140 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x182C00A0 },
         { .reg = 0x00009888, .val = 0x03933300 },
         { .reg = 0x00009888, .val = 0x05930032 },
         { .reg = 0x00009888, .val = 0x11930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190030F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900021 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x53905555 },
         { .reg = 0x00009888, .val = 0x43900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__compute_l3_cache__avg_gpu_core_frequency__max,sklgt4__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,sklgt4__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,sklgt4__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, sklgt4__compute_l3_cache__eu_avg_ipc_rate__max,sklgt4__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,sklgt4__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,sklgt4__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,sklgt4__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,sklgt4__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,sklgt4__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,sklgt4__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,sklgt4__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,sklgt4__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,sklgt4__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,sklgt4__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,sklgt4__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,sklgt4__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,sklgt4__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,sklgt4__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,sklgt4__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,sklgt4__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,sklgt4__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,sklgt4__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,sklgt4__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, sklgt4__compute_l3_cache__slm_bytes_read__max,sklgt4__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, sklgt4__compute_l3_cache__slm_bytes_written__max,sklgt4__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,sklgt4__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,sklgt4__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 256, NULL,sklgt4__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 264, NULL,sklgt4__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, sklgt4__compute_l3_cache__l3_sampler_throughput__max,sklgt4__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 280, sklgt4__compute_l3_cache__l3_shader_throughput__max,sklgt4__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 288, sklgt4__compute_l3_cache__l3_total_throughput__max,sklgt4__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,sklgt4__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 304, NULL,sklgt4__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 312, NULL,sklgt4__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 320, NULL,sklgt4__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 328, NULL,sklgt4__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 336, NULL,sklgt4__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 344, NULL,sklgt4__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 352, sklgt4__compute_l3_cache__gti_l3_throughput__max,sklgt4__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 360, sklgt4__compute_l3_cache__gti_read_throughput__max,sklgt4__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 368, sklgt4__compute_l3_cache__gti_write_throughput__max,sklgt4__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "75f56991-b149-4122-ade9-d9c0c80c733b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F0232 },
         { .reg = 0x00009888, .val = 0x124F4640 },
         { .reg = 0x00009888, .val = 0x106C0232 },
         { .reg = 0x00009888, .val = 0x11834400 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x004F1880 },
         { .reg = 0x00009888, .val = 0x024F08BB },
         { .reg = 0x00009888, .val = 0x044F001B },
         { .reg = 0x00009888, .val = 0x046C0100 },
         { .reg = 0x00009888, .val = 0x066C000B },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x041B8000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025BC000 },
         { .reg = 0x00009888, .val = 0x045B4000 },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x165C8000 },
         { .reg = 0x00009888, .val = 0x185C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00A0 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x062CC000 },
         { .reg = 0x00009888, .val = 0x082CC000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x0F8305C0 },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x07830000 },
         { .reg = 0x00009888, .val = 0x1D950080 },
         { .reg = 0x00009888, .val = 0x13928000 },
         { .reg = 0x00009888, .val = 0x0F988000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x59900001 },
         { .reg = 0x00009888, .val = 0x4B900040 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__hdc_and_sf__avg_gpu_core_frequency__max,sklgt4__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt4__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt4__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt4__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt4__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt4__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt4__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt4__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt4__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt4__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt4__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt4__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt4__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt4__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt4__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt4__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt4__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt4__hdc_and_sf__slm_bytes_read__max,sklgt4__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt4__hdc_and_sf__slm_bytes_written__max,sklgt4__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt4__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt4__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt4__hdc_and_sf__l3_shader_throughput__max,sklgt4__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt4__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,sklgt4__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 244, percentage_max_float,sklgt4__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,sklgt4__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 238, 252, percentage_max_float,sklgt4__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,sklgt4__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "0d4cda70-da83-466f-b61e-7a064fe6a232";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C7B40 },
         { .reg = 0x00009888, .val = 0x166C0020 },
         { .reg = 0x00009888, .val = 0x0A603444 },
         { .reg = 0x00009888, .val = 0x0A613400 },
         { .reg = 0x00009888, .val = 0x1A4EA800 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x0C6C5327 },
         { .reg = 0x00009888, .val = 0x0E6C5425 },
         { .reg = 0x00009888, .val = 0x006C2A00 },
         { .reg = 0x00009888, .val = 0x026C285B },
         { .reg = 0x00009888, .val = 0x046C005C },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0800 },
         { .reg = 0x00009888, .val = 0x0C1BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x1C1C003C },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x10600000 },
         { .reg = 0x00009888, .val = 0x04600000 },
         { .reg = 0x00009888, .val = 0x0C610044 },
         { .reg = 0x00009888, .val = 0x10610000 },
         { .reg = 0x00009888, .val = 0x06610000 },
         { .reg = 0x00009888, .val = 0x0C4C02A8 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0154 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190FFC0 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900420 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900021 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900400 },
         { .reg = 0x00009888, .val = 0x43900421 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__l3_1__avg_gpu_core_frequency__max,sklgt4__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt4__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt4__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt4__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt4__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt4__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt4__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt4__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt4__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt4__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt4__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt4__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt4__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt4__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt4__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt4__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt4__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt4__l3_1__slm_bytes_read__max,sklgt4__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt4__l3_1__slm_bytes_written__max,sklgt4__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt4__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt4__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt4__l3_1__l3_shader_throughput__max,sklgt4__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt4__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,sklgt4__l3_1__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,sklgt4__l3_1__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,sklgt4__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,sklgt4__l3_1__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,sklgt4__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_2";
   query->symbol_name = "L3_2";
   query->guid = "20137ace-b110-4341-883f-1094c820093c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C02E0 },
         { .reg = 0x00009888, .val = 0x146C0001 },
         { .reg = 0x00009888, .val = 0x0A623400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x026C3324 },
         { .reg = 0x00009888, .val = 0x046C3422 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x06614000 },
         { .reg = 0x00009888, .val = 0x0C620044 },
         { .reg = 0x00009888, .val = 0x10620000 },
         { .reg = 0x00009888, .val = 0x06620000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__l3_2__avg_gpu_core_frequency__max,sklgt4__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt4__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt4__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt4__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt4__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt4__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt4__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt4__l3_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt4__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt4__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt4__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt4__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt4__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt4__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt4__l3_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt4__l3_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt4__l3_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt4__l3_2__slm_bytes_read__max,sklgt4__l3_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt4__l3_2__slm_bytes_written__max,sklgt4__l3_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt4__l3_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt4__l3_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt4__l3_2__l3_shader_throughput__max,sklgt4__l3_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt4__l3_2__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 257, 240, percentage_max_float,sklgt4__l3_2__l30_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 260, 244, percentage_max_float,sklgt4__l3_2__l30_bank2_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,sklgt4__l3_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_3";
   query->symbol_name = "L3_3";
   query->guid = "d3a6b05e-46ef-44a8-96c3-9bd3e58acbe6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C4E80 },
         { .reg = 0x00009888, .val = 0x146C0000 },
         { .reg = 0x00009888, .val = 0x0A633400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x026C3321 },
         { .reg = 0x00009888, .val = 0x046C342F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C2000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x06604000 },
         { .reg = 0x00009888, .val = 0x0C630044 },
         { .reg = 0x00009888, .val = 0x10630000 },
         { .reg = 0x00009888, .val = 0x06630000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00AA },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__l3_3__avg_gpu_core_frequency__max,sklgt4__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt4__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt4__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt4__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt4__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt4__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt4__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt4__l3_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt4__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt4__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt4__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt4__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt4__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt4__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt4__l3_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt4__l3_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt4__l3_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt4__l3_3__slm_bytes_read__max,sklgt4__l3_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt4__l3_3__slm_bytes_written__max,sklgt4__l3_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt4__l3_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt4__l3_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt4__l3_3__l3_shader_throughput__max,sklgt4__l3_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt4__l3_3__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 253, 240, percentage_max_float,sklgt4__l3_3__l30_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 256, 244, percentage_max_float,sklgt4__l3_3__l30_bank3_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,sklgt4__l3_3__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "4081b948-63f1-4b1a-abaa-6017cb77a63b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x102F3800 },
         { .reg = 0x00009888, .val = 0x144D0500 },
         { .reg = 0x00009888, .val = 0x120D03C0 },
         { .reg = 0x00009888, .val = 0x140D03CF },
         { .reg = 0x00009888, .val = 0x0C0F0004 },
         { .reg = 0x00009888, .val = 0x0C4E4000 },
         { .reg = 0x00009888, .val = 0x042F0480 },
         { .reg = 0x00009888, .val = 0x082F0000 },
         { .reg = 0x00009888, .val = 0x022F0000 },
         { .reg = 0x00009888, .val = 0x0A4C0090 },
         { .reg = 0x00009888, .val = 0x064D0027 },
         { .reg = 0x00009888, .val = 0x004D0000 },
         { .reg = 0x00009888, .val = 0x000D0D40 },
         { .reg = 0x00009888, .val = 0x020D803F },
         { .reg = 0x00009888, .val = 0x040D8023 },
         { .reg = 0x00009888, .val = 0x100D0000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020F0010 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0050 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41901400 },
         { .reg = 0x00009888, .val = 0x43901485 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000EFFF },
         { .reg = 0x00002778, .val = 0x00006000 },
         { .reg = 0x0000277C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt4__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt4__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt4__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt4__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt4__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt4__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt4__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt4__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt4__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt4__rasterizer_and_pixel_backend__slm_bytes_read__max,sklgt4__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt4__rasterizer_and_pixel_backend__slm_bytes_written__max,sklgt4__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt4__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt4__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt4__rasterizer_and_pixel_backend__l3_shader_throughput__max,sklgt4__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt4__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 240, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 244, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 248, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 252, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 256, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,sklgt4__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler";
   query->symbol_name = "Sampler";
   query->guid = "eae6bbb1-0e2b-478d-bd9e-f10ded2178f9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x14152C00 },
         { .reg = 0x00009888, .val = 0x16150005 },
         { .reg = 0x00009888, .val = 0x121600A0 },
         { .reg = 0x00009888, .val = 0x14352C00 },
         { .reg = 0x00009888, .val = 0x16350005 },
         { .reg = 0x00009888, .val = 0x123600A0 },
         { .reg = 0x00009888, .val = 0x14552C00 },
         { .reg = 0x00009888, .val = 0x16550005 },
         { .reg = 0x00009888, .val = 0x125600A0 },
         { .reg = 0x00009888, .val = 0x062F6000 },
         { .reg = 0x00009888, .val = 0x022F2000 },
         { .reg = 0x00009888, .val = 0x0C4C0050 },
         { .reg = 0x00009888, .val = 0x0A4C0010 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0350 },
         { .reg = 0x00009888, .val = 0x0C0FB000 },
         { .reg = 0x00009888, .val = 0x0E0F00DA },
         { .reg = 0x00009888, .val = 0x182C0028 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x022DC000 },
         { .reg = 0x00009888, .val = 0x042D4000 },
         { .reg = 0x00009888, .val = 0x0C138000 },
         { .reg = 0x00009888, .val = 0x0E132000 },
         { .reg = 0x00009888, .val = 0x0413C000 },
         { .reg = 0x00009888, .val = 0x1C140018 },
         { .reg = 0x00009888, .val = 0x0C157000 },
         { .reg = 0x00009888, .val = 0x0E150078 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x04162180 },
         { .reg = 0x00009888, .val = 0x02160000 },
         { .reg = 0x00009888, .val = 0x04174000 },
         { .reg = 0x00009888, .val = 0x0233A000 },
         { .reg = 0x00009888, .val = 0x04333000 },
         { .reg = 0x00009888, .val = 0x14348000 },
         { .reg = 0x00009888, .val = 0x16348000 },
         { .reg = 0x00009888, .val = 0x02357870 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x04360043 },
         { .reg = 0x00009888, .val = 0x02360000 },
         { .reg = 0x00009888, .val = 0x04371000 },
         { .reg = 0x00009888, .val = 0x0E538000 },
         { .reg = 0x00009888, .val = 0x00538000 },
         { .reg = 0x00009888, .val = 0x06533000 },
         { .reg = 0x00009888, .val = 0x1C540020 },
         { .reg = 0x00009888, .val = 0x12548000 },
         { .reg = 0x00009888, .val = 0x0E557000 },
         { .reg = 0x00009888, .val = 0x00557800 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x06560043 },
         { .reg = 0x00009888, .val = 0x02560000 },
         { .reg = 0x00009888, .val = 0x06571000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900060 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900060 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__sampler__avg_gpu_core_frequency__max,sklgt4__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__sampler__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__sampler__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__sampler__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__sampler__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__sampler__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__sampler__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__sampler__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__sampler__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__sampler__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__sampler__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt4__sampler__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt4__sampler__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt4__sampler__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt4__sampler__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt4__sampler__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt4__sampler__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt4__sampler__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt4__sampler__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt4__sampler__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt4__sampler__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt4__sampler__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt4__sampler__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt4__sampler__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt4__sampler__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt4__sampler__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt4__sampler__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt4__sampler__slm_bytes_read__max,sklgt4__sampler__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt4__sampler__slm_bytes_written__max,sklgt4__sampler__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt4__sampler__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt4__sampler__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt4__sampler__l3_shader_throughput__max,sklgt4__sampler__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt4__sampler__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,sklgt4__sampler__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,sklgt4__sampler__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,sklgt4__sampler__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,sklgt4__sampler__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,sklgt4__sampler__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,sklgt4__sampler__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,sklgt4__sampler__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "1bba4bd2-81d4-45ec-847f-bc363e17e14d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12120000 },
         { .reg = 0x00009888, .val = 0x12320000 },
         { .reg = 0x00009888, .val = 0x12520000 },
         { .reg = 0x00009888, .val = 0x002F8000 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0015 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F03A0 },
         { .reg = 0x00009888, .val = 0x0C0FF000 },
         { .reg = 0x00009888, .val = 0x0E0F0095 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2D8000 },
         { .reg = 0x00009888, .val = 0x0E2D4000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x02108000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x02118000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x02121880 },
         { .reg = 0x00009888, .val = 0x041219B5 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x02134000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x0C308000 },
         { .reg = 0x00009888, .val = 0x0E304000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x0C318000 },
         { .reg = 0x00009888, .val = 0x0E314000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x0C321A80 },
         { .reg = 0x00009888, .val = 0x0E320033 },
         { .reg = 0x00009888, .val = 0x06320031 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x0C334000 },
         { .reg = 0x00009888, .val = 0x0E331000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0E508000 },
         { .reg = 0x00009888, .val = 0x00508000 },
         { .reg = 0x00009888, .val = 0x02504000 },
         { .reg = 0x00009888, .val = 0x0E518000 },
         { .reg = 0x00009888, .val = 0x00518000 },
         { .reg = 0x00009888, .val = 0x02514000 },
         { .reg = 0x00009888, .val = 0x0E521880 },
         { .reg = 0x00009888, .val = 0x00521A80 },
         { .reg = 0x00009888, .val = 0x02520033 },
         { .reg = 0x00009888, .val = 0x0E534000 },
         { .reg = 0x00009888, .val = 0x00534000 },
         { .reg = 0x00009888, .val = 0x02531000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900062 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x00007FFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x00009FFF },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000EFFF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000F3FF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FDFF },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__tdl_1__avg_gpu_core_frequency__max,sklgt4__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt4__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt4__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt4__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt4__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt4__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt4__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt4__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt4__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt4__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt4__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt4__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt4__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt4__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt4__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt4__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt4__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt4__tdl_1__slm_bytes_read__max,sklgt4__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt4__tdl_1__slm_bytes_written__max,sklgt4__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt4__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt4__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt4__tdl_1__l3_shader_throughput__max,sklgt4__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt4__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 240, percentage_max_float,sklgt4__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 244, percentage_max_float,sklgt4__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 248, percentage_max_float,sklgt4__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 252, percentage_max_float,sklgt4__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 256, percentage_max_float,sklgt4__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 260, percentage_max_float,sklgt4__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,sklgt4__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "a4b3106c-cfec-49f5-8e26-470470379e66";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12124D60 },
         { .reg = 0x00009888, .val = 0x12322E60 },
         { .reg = 0x00009888, .val = 0x12524D60 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0014 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0FE000 },
         { .reg = 0x00009888, .val = 0x0E0F0097 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x002D8000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x04121FB7 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x00308000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x00318000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x00321B80 },
         { .reg = 0x00009888, .val = 0x0632003F },
         { .reg = 0x00009888, .val = 0x00334000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0250C000 },
         { .reg = 0x00009888, .val = 0x0251C000 },
         { .reg = 0x00009888, .val = 0x02521FB7 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x02535000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900063 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__tdl_2__avg_gpu_core_frequency__max,sklgt4__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,sklgt4__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,sklgt4__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,sklgt4__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,sklgt4__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,sklgt4__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,sklgt4__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,sklgt4__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,sklgt4__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,sklgt4__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,sklgt4__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,sklgt4__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,sklgt4__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,sklgt4__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,sklgt4__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,sklgt4__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,sklgt4__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,sklgt4__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,sklgt4__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,sklgt4__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, sklgt4__tdl_2__slm_bytes_read__max,sklgt4__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, sklgt4__tdl_2__slm_bytes_written__max,sklgt4__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,sklgt4__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,sklgt4__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, sklgt4__tdl_2__l3_shader_throughput__max,sklgt4__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,sklgt4__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 240, percentage_max_float,sklgt4__tdl_2__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 244, percentage_max_float,sklgt4__tdl_2__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 248, percentage_max_float,sklgt4__tdl_2__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 252, percentage_max_float,sklgt4__tdl_2__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 256, percentage_max_float,sklgt4__tdl_2__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 260, percentage_max_float,sklgt4__tdl_2__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,sklgt4__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "a5aa857d-e8f0-4dfa-8981-ce340fa748fd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x121203E0 },
         { .reg = 0x00009888, .val = 0x123203E0 },
         { .reg = 0x00009888, .val = 0x125203E0 },
         { .reg = 0x00009888, .val = 0x129203E0 },
         { .reg = 0x00009888, .val = 0x12B203E0 },
         { .reg = 0x00009888, .val = 0x12D203E0 },
         { .reg = 0x00009888, .val = 0x131203E0 },
         { .reg = 0x00009888, .val = 0x133203E0 },
         { .reg = 0x00009888, .val = 0x135203E0 },
         { .reg = 0x00009888, .val = 0x1A4EF000 },
         { .reg = 0x00009888, .val = 0x1C4E0003 },
         { .reg = 0x00009888, .val = 0x024EC000 },
         { .reg = 0x00009888, .val = 0x044EC000 },
         { .reg = 0x00009888, .val = 0x064EC000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0C4C02A0 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C0042 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0150 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F006D },
         { .reg = 0x00009888, .val = 0x182C00A8 },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x042D8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06114000 },
         { .reg = 0x00009888, .val = 0x06120033 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x04308000 },
         { .reg = 0x00009888, .val = 0x04318000 },
         { .reg = 0x00009888, .val = 0x04321980 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x04334000 },
         { .reg = 0x00009888, .val = 0x04504000 },
         { .reg = 0x00009888, .val = 0x04514000 },
         { .reg = 0x00009888, .val = 0x04520033 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x04531000 },
         { .reg = 0x00009888, .val = 0x1ACEF000 },
         { .reg = 0x00009888, .val = 0x1CCE0003 },
         { .reg = 0x00009888, .val = 0x00AF8000 },
         { .reg = 0x00009888, .val = 0x0CCC02A0 },
         { .reg = 0x00009888, .val = 0x0ACC0001 },
         { .reg = 0x00009888, .val = 0x0C8D8000 },
         { .reg = 0x00009888, .val = 0x0E8DA000 },
         { .reg = 0x00009888, .val = 0x008D8000 },
         { .reg = 0x00009888, .val = 0x028DA000 },
         { .reg = 0x00009888, .val = 0x108F0150 },
         { .reg = 0x00009888, .val = 0x0C8FB000 },
         { .reg = 0x00009888, .val = 0x0E8F0001 },
         { .reg = 0x00009888, .val = 0x18AC00A8 },
         { .reg = 0x00009888, .val = 0x06AC8000 },
         { .reg = 0x00009888, .val = 0x02AD4000 },
         { .reg = 0x00009888, .val = 0x02908000 },
         { .reg = 0x00009888, .val = 0x02918000 },
         { .reg = 0x00009888, .val = 0x02921980 },
         { .reg = 0x00009888, .val = 0x00920000 },
         { .reg = 0x00009888, .val = 0x02934000 },
         { .reg = 0x00009888, .val = 0x02B04000 },
         { .reg = 0x00009888, .val = 0x02B14000 },
         { .reg = 0x00009888, .val = 0x02B20033 },
         { .reg = 0x00009888, .val = 0x00B20000 },
         { .reg = 0x00009888, .val = 0x02B31000 },
         { .reg = 0x00009888, .val = 0x00D08000 },
         { .reg = 0x00009888, .val = 0x00D18000 },
         { .reg = 0x00009888, .val = 0x00D21980 },
         { .reg = 0x00009888, .val = 0x00D34000 },
         { .reg = 0x00009888, .val = 0x072F8000 },
         { .reg = 0x00009888, .val = 0x0D4C0100 },
         { .reg = 0x00009888, .val = 0x0D0D8000 },
         { .reg = 0x00009888, .val = 0x0F0DA000 },
         { .reg = 0x00009888, .val = 0x110F01B0 },
         { .reg = 0x00009888, .val = 0x192C0080 },
         { .reg = 0x00009888, .val = 0x0F2D4000 },
         { .reg = 0x00009888, .val = 0x0F108000 },
         { .reg = 0x00009888, .val = 0x0F118000 },
         { .reg = 0x00009888, .val = 0x0F121980 },
         { .reg = 0x00009888, .val = 0x01120000 },
         { .reg = 0x00009888, .val = 0x0F134000 },
         { .reg = 0x00009888, .val = 0x0F304000 },
         { .reg = 0x00009888, .val = 0x0F314000 },
         { .reg = 0x00009888, .val = 0x0F320033 },
         { .reg = 0x00009888, .val = 0x01320000 },
         { .reg = 0x00009888, .val = 0x0F331000 },
         { .reg = 0x00009888, .val = 0x0D508000 },
         { .reg = 0x00009888, .val = 0x0D518000 },
         { .reg = 0x00009888, .val = 0x0D521980 },
         { .reg = 0x00009888, .val = 0x01520000 },
         { .reg = 0x00009888, .val = 0x0D534000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900002 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51901100 },
         { .reg = 0x00009888, .val = 0x41901000 },
         { .reg = 0x00009888, .val = 0x43901423 },
         { .reg = 0x00009888, .val = 0x53903331 },
         { .reg = 0x00009888, .val = 0x45900044 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__compute_extra__avg_gpu_core_frequency__max,sklgt4__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,sklgt4__compute_extra__fpu1_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_vme_pipe_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Media Vme Pipe metrics set";
   query->symbol_name = "VMEPipe";
   query->guid = "0e8d8b86-4ee7-4cdd-aaaa-58adc92cb29e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A5800 },
         { .reg = 0x00009888, .val = 0x161A00C0 },
         { .reg = 0x00009888, .val = 0x12180240 },
         { .reg = 0x00009888, .val = 0x14180002 },
         { .reg = 0x00009888, .val = 0x149A5800 },
         { .reg = 0x00009888, .val = 0x169A00C0 },
         { .reg = 0x00009888, .val = 0x12980240 },
         { .reg = 0x00009888, .val = 0x14980002 },
         { .reg = 0x00009888, .val = 0x1A4E3FC0 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x022F8000 },
         { .reg = 0x00009888, .val = 0x042F3000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C9500 },
         { .reg = 0x00009888, .val = 0x0C4C002A },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0015 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C000A },
         { .reg = 0x00009888, .val = 0x04193000 },
         { .reg = 0x00009888, .val = 0x081A28C1 },
         { .reg = 0x00009888, .val = 0x001A0000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x0613C000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x00172000 },
         { .reg = 0x00009888, .val = 0x06178000 },
         { .reg = 0x00009888, .val = 0x0817A000 },
         { .reg = 0x00009888, .val = 0x00180037 },
         { .reg = 0x00009888, .val = 0x06180940 },
         { .reg = 0x00009888, .val = 0x08180000 },
         { .reg = 0x00009888, .val = 0x02180000 },
         { .reg = 0x00009888, .val = 0x04183000 },
         { .reg = 0x00009888, .val = 0x04AFC000 },
         { .reg = 0x00009888, .val = 0x06AF3000 },
         { .reg = 0x00009888, .val = 0x0ACC4000 },
         { .reg = 0x00009888, .val = 0x0CCC0015 },
         { .reg = 0x00009888, .val = 0x0A8DA000 },
         { .reg = 0x00009888, .val = 0x0C8DA000 },
         { .reg = 0x00009888, .val = 0x0E8F4000 },
         { .reg = 0x00009888, .val = 0x108F0015 },
         { .reg = 0x00009888, .val = 0x16ACA000 },
         { .reg = 0x00009888, .val = 0x18AC000A },
         { .reg = 0x00009888, .val = 0x06993000 },
         { .reg = 0x00009888, .val = 0x0C9A28C1 },
         { .reg = 0x00009888, .val = 0x009A0000 },
         { .reg = 0x00009888, .val = 0x0A93F000 },
         { .reg = 0x00009888, .val = 0x0C93F000 },
         { .reg = 0x00009888, .val = 0x0A97A000 },
         { .reg = 0x00009888, .val = 0x0C97A000 },
         { .reg = 0x00009888, .val = 0x0A980977 },
         { .reg = 0x00009888, .val = 0x08980000 },
         { .reg = 0x00009888, .val = 0x04980000 },
         { .reg = 0x00009888, .val = 0x06983000 },
         { .reg = 0x00009888, .val = 0x119000FF },
         { .reg = 0x00009888, .val = 0x51900010 },
         { .reg = 0x00009888, .val = 0x41900060 },
         { .reg = 0x00009888, .val = 0x55900111 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900821 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900002 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00100030 },
         { .reg = 0x00002774, .val = 0x0000FFF9 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFFC },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFF3 },
         { .reg = 0x00002788, .val = 0x00100180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__vme_pipe__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__vme_pipe__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__vme_pipe__avg_gpu_core_frequency__max,sklgt4__vme_pipe__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__vme_pipe__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,sklgt4__vme_pipe__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 40, percentage_max_float,sklgt4__vme_pipe__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 44, percentage_max_float,sklgt4__vme_pipe__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 48, percentage_max_float,sklgt4__vme_pipe__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 52, percentage_max_float,sklgt4__vme_pipe__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 308, 56, percentage_max_float,sklgt4__vme_pipe__vme_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Gpu Rings Busyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "4e5b1599-5b01-4b3d-89fa-6b26a25fe02b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x21D05800 },
         { .reg = 0x00009888, .val = 0x13805800 },
         { .reg = 0x00009888, .val = 0x05962C25 },
         { .reg = 0x00009888, .val = 0x19950016 },
         { .reg = 0x00009888, .val = 0x21C05800 },
         { .reg = 0x00009888, .val = 0x09D000A5 },
         { .reg = 0x00009888, .val = 0x11D00000 },
         { .reg = 0x00009888, .val = 0x05D00000 },
         { .reg = 0x00009888, .val = 0x09D54000 },
         { .reg = 0x00009888, .val = 0x07800035 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x1D810400 },
         { .reg = 0x00009888, .val = 0x21960000 },
         { .reg = 0x00009888, .val = 0x0996C000 },
         { .reg = 0x00009888, .val = 0x0B964000 },
         { .reg = 0x00009888, .val = 0x19938000 },
         { .reg = 0x00009888, .val = 0x1B930068 },
         { .reg = 0x00009888, .val = 0x15948000 },
         { .reg = 0x00009888, .val = 0x1B94000C },
         { .reg = 0x00009888, .val = 0x03957500 },
         { .reg = 0x00009888, .val = 0x1D950000 },
         { .reg = 0x00009888, .val = 0x17950000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x07928000 },
         { .reg = 0x00009888, .val = 0x03988000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x09978000 },
         { .reg = 0x00009888, .val = 0x0BC000A5 },
         { .reg = 0x00009888, .val = 0x11C00000 },
         { .reg = 0x00009888, .val = 0x05C00000 },
         { .reg = 0x00009888, .val = 0x0BC54000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900463 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0007C000 },
         { .reg = 0x00002774, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__gpu_busyness__avg_gpu_core_frequency__max,sklgt4__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 309, 24, percentage_max_float,sklgt4__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 28, percentage_max_float,sklgt4__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 32, percentage_max_float,sklgt4__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 312, 36, percentage_max_float,sklgt4__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 40, percentage_max_float,sklgt4__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 44, percentage_max_float,sklgt4__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "c1c2d40e-652a-482c-98fc-28bdb7c6ee44";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810000 },
         { .reg = 0x00009888, .val = 0x07810013 },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930040 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__test_oa__avg_gpu_core_frequency__max,sklgt4__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,sklgt4__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,sklgt4__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,sklgt4__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,sklgt4__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,sklgt4__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,sklgt4__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,sklgt4__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,sklgt4__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,sklgt4__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_pma__stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "PMA_Stall";
   query->guid = "befe9fd6-474e-4a3d-b98e-cd793715cf91";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x122D3080 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0800 },
         { .reg = 0x00009888, .val = 0x0E0FAA00 },
         { .reg = 0x00009888, .val = 0x100F0002 },
         { .reg = 0x00009888, .val = 0x002D0025 },
         { .reg = 0x00009888, .val = 0x062D1300 },
         { .reg = 0x00009888, .val = 0x082D16A4 },
         { .reg = 0x00009888, .val = 0x0A2D162E },
         { .reg = 0x00009888, .val = 0x102D0000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00E00021 },
         { .reg = 0x00002774, .val = 0x0007FFF8 },
         { .reg = 0x00002778, .val = 0x07000101 },
         { .reg = 0x0000277C, .val = 0x0038FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__pma__stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__pma__stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__pma__stall__avg_gpu_core_frequency__max,sklgt4__pma__stall__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 24, percentage_max_float,sklgt4__pma__stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
sklgt4_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "796044f3-8f9d-4439-ab2c-aca5b046a1ef";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00051050 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00061060 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,sklgt4__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,sklgt4__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, sklgt4__async_compute__avg_gpu_core_frequency__max,sklgt4__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,sklgt4__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,sklgt4__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,sklgt4__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,sklgt4__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,sklgt4__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,sklgt4__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,sklgt4__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 150, 80, percentage_max_float,sklgt4__async_compute__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 124, 84, percentage_max_float,sklgt4__async_compute__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 127, 88, percentage_max_float,sklgt4__async_compute__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 331, 92, percentage_max_float,sklgt4__async_compute__cs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,sklgt4__async_compute__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 125, 100, percentage_max_float,sklgt4__async_compute__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,sklgt4__async_compute__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 332, 108, percentage_max_float,sklgt4__async_compute__cs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 154, 112, percentage_max_float,sklgt4__async_compute__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 10, 116, percentage_max_float,sklgt4__async_compute__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 120, percentage_max_float,sklgt4__async_compute__eu_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_sklgt4(struct intel_perf_config *perf)
{
   sklgt4_register_render_basic_counter_query(perf);
   sklgt4_register_compute_basic_counter_query(perf);
   sklgt4_register_render_pipe_profile_counter_query(perf);
   sklgt4_register_memory_reads_counter_query(perf);
   sklgt4_register_memory_writes_counter_query(perf);
   sklgt4_register_compute_extended_counter_query(perf);
   sklgt4_register_compute_l3_cache_counter_query(perf);
   sklgt4_register_hdc_and_sf_counter_query(perf);
   sklgt4_register_l3_1_counter_query(perf);
   sklgt4_register_l3_2_counter_query(perf);
   sklgt4_register_l3_3_counter_query(perf);
   sklgt4_register_rasterizer_and_pixel_backend_counter_query(perf);
   sklgt4_register_sampler_counter_query(perf);
   sklgt4_register_tdl_1_counter_query(perf);
   sklgt4_register_tdl_2_counter_query(perf);
   sklgt4_register_compute_extra_counter_query(perf);
   sklgt4_register_vme_pipe_counter_query(perf);
   sklgt4_register_gpu_busyness_counter_query(perf);
   sklgt4_register_test_oa_counter_query(perf);
   sklgt4_register_pma__stall_counter_query(perf);
   sklgt4_register_async_compute_counter_query(perf);
}


static void
kblgt2_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "99c1a40e-a090-4354-86e3-4d068bb1917e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C01E0 },
         { .reg = 0x00009888, .val = 0x12170280 },
         { .reg = 0x00009888, .val = 0x12370280 },
         { .reg = 0x00009888, .val = 0x11930317 },
         { .reg = 0x00009888, .val = 0x159303DF },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x1A4E0080 },
         { .reg = 0x00009888, .val = 0x0A6C0053 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x0A1B4000 },
         { .reg = 0x00009888, .val = 0x1C1C0001 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x042F1000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C8400 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0D2000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F6600 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x162C2200 },
         { .reg = 0x00009888, .val = 0x062D8000 },
         { .reg = 0x00009888, .val = 0x082D8000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x08133000 },
         { .reg = 0x00009888, .val = 0x00170020 },
         { .reg = 0x00009888, .val = 0x08170021 },
         { .reg = 0x00009888, .val = 0x10170000 },
         { .reg = 0x00009888, .val = 0x0633C000 },
         { .reg = 0x00009888, .val = 0x0833C000 },
         { .reg = 0x00009888, .val = 0x06370800 },
         { .reg = 0x00009888, .val = 0x08370840 },
         { .reg = 0x00009888, .val = 0x10370000 },
         { .reg = 0x00009888, .val = 0x0D933031 },
         { .reg = 0x00009888, .val = 0x0F933E3F },
         { .reg = 0x00009888, .val = 0x01933D00 },
         { .reg = 0x00009888, .val = 0x0393073C },
         { .reg = 0x00009888, .val = 0x0593000E },
         { .reg = 0x00009888, .val = 0x1D930000 },
         { .reg = 0x00009888, .val = 0x19930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x2B908000 },
         { .reg = 0x00009888, .val = 0x2D908000 },
         { .reg = 0x00009888, .val = 0x2F908000 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x15908000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190001F },
         { .reg = 0x00009888, .val = 0x51904400 },
         { .reg = 0x00009888, .val = 0x41900020 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C21 },
         { .reg = 0x00009888, .val = 0x47900061 },
         { .reg = 0x00009888, .val = 0x57904440 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900004 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x53904444 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__render_basic__avg_gpu_core_frequency__max,kblgt2__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,kblgt2__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,kblgt2__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,kblgt2__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,kblgt2__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,kblgt2__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,kblgt2__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,kblgt2__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,kblgt2__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,kblgt2__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,kblgt2__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,kblgt2__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,kblgt2__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,kblgt2__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,kblgt2__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,kblgt2__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,kblgt2__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,kblgt2__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,kblgt2__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,kblgt2__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,kblgt2__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,kblgt2__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,kblgt2__render_basic__sampler1_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,kblgt2__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,kblgt2__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,kblgt2__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,kblgt2__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,kblgt2__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,kblgt2__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,kblgt2__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,kblgt2__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,kblgt2__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 208, NULL,kblgt2__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, kblgt2__render_basic__slm_bytes_read__max,kblgt2__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, kblgt2__render_basic__slm_bytes_written__max,kblgt2__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,kblgt2__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,kblgt2__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,kblgt2__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,kblgt2__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, kblgt2__render_basic__l3_sampler_throughput__max,kblgt2__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, kblgt2__render_basic__l3_shader_throughput__max,kblgt2__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,kblgt2__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, kblgt2__render_basic__gti_vf_throughput__max,kblgt2__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, kblgt2__render_basic__gti_depth_throughput__max,kblgt2__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, kblgt2__render_basic__gti_rcc_throughput__max,kblgt2__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, kblgt2__render_basic__gti_l3_throughput__max,kblgt2__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, kblgt2__render_basic__gti_hdc_lookups_throughput__max,kblgt2__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, kblgt2__render_basic__gti_read_throughput__max,kblgt2__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, kblgt2__render_basic__gti_write_throughput__max,kblgt2__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,kblgt2__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "12994724-3a5a-4303-bb3c-ba0175d2c200";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x124F1C00 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x1A4E0820 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x064F0900 },
         { .reg = 0x00009888, .val = 0x084F0032 },
         { .reg = 0x00009888, .val = 0x0A4F1891 },
         { .reg = 0x00009888, .val = 0x0C4F0E00 },
         { .reg = 0x00009888, .val = 0x0E4F003C },
         { .reg = 0x00009888, .val = 0x004F0D80 },
         { .reg = 0x00009888, .val = 0x024F003B },
         { .reg = 0x00009888, .val = 0x006C0002 },
         { .reg = 0x00009888, .val = 0x086C0100 },
         { .reg = 0x00009888, .val = 0x0C6C000C },
         { .reg = 0x00009888, .val = 0x0E6C0B00 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x081B8000 },
         { .reg = 0x00009888, .val = 0x0C1B4000 },
         { .reg = 0x00009888, .val = 0x0E1B8000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1C8000 },
         { .reg = 0x00009888, .val = 0x1C1C0024 },
         { .reg = 0x00009888, .val = 0x065B8000 },
         { .reg = 0x00009888, .val = 0x085B4000 },
         { .reg = 0x00009888, .val = 0x0A5BC000 },
         { .reg = 0x00009888, .val = 0x0C5B8000 },
         { .reg = 0x00009888, .val = 0x0E5B4000 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025B4000 },
         { .reg = 0x00009888, .val = 0x1A5C6000 },
         { .reg = 0x00009888, .val = 0x1C5C001B },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2000 },
         { .reg = 0x00009888, .val = 0x0C4C0208 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2CC000 },
         { .reg = 0x00009888, .val = 0x162CFB00 },
         { .reg = 0x00009888, .val = 0x182C00BE },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x19900157 },
         { .reg = 0x00009888, .val = 0x1B900158 },
         { .reg = 0x00009888, .val = 0x1D900105 },
         { .reg = 0x00009888, .val = 0x1F900103 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x11900FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900821 },
         { .reg = 0x00009888, .val = 0x47900802 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900802 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900002 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900422 },
         { .reg = 0x00009888, .val = 0x53904444 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__compute_basic__avg_gpu_core_frequency__max,kblgt2__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,kblgt2__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,kblgt2__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, kblgt2__compute_basic__eu_avg_ipc_rate__max,kblgt2__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,kblgt2__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,kblgt2__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,kblgt2__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,kblgt2__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,kblgt2__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,kblgt2__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,kblgt2__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,kblgt2__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,kblgt2__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,kblgt2__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,kblgt2__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, kblgt2__compute_basic__slm_bytes_read__max,kblgt2__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, kblgt2__compute_basic__slm_bytes_written__max,kblgt2__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,kblgt2__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,kblgt2__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, kblgt2__compute_basic__l3_shader_throughput__max,kblgt2__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,kblgt2__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, kblgt2__compute_basic__typed_bytes_read__max,kblgt2__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, kblgt2__compute_basic__typed_bytes_written__max,kblgt2__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, kblgt2__compute_basic__untyped_bytes_read__max,kblgt2__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, kblgt2__compute_basic__untyped_bytes_written__max,kblgt2__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, kblgt2__compute_basic__gti_read_throughput__max,kblgt2__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, kblgt2__compute_basic__gti_write_throughput__max,kblgt2__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "d7a17a3a-ca71-40d2-a919-ace80d50633f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x0C0E001F },
         { .reg = 0x00009888, .val = 0x0A0F0000 },
         { .reg = 0x00009888, .val = 0x10116800 },
         { .reg = 0x00009888, .val = 0x178A03E0 },
         { .reg = 0x00009888, .val = 0x11824C00 },
         { .reg = 0x00009888, .val = 0x11830020 },
         { .reg = 0x00009888, .val = 0x13840020 },
         { .reg = 0x00009888, .val = 0x11850019 },
         { .reg = 0x00009888, .val = 0x11860007 },
         { .reg = 0x00009888, .val = 0x01870C40 },
         { .reg = 0x00009888, .val = 0x17880000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0A4C0040 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020E5400 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x080F0040 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0040 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06110012 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x01898000 },
         { .reg = 0x00009888, .val = 0x0D890100 },
         { .reg = 0x00009888, .val = 0x03898000 },
         { .reg = 0x00009888, .val = 0x09808000 },
         { .reg = 0x00009888, .val = 0x0B808000 },
         { .reg = 0x00009888, .val = 0x0380C000 },
         { .reg = 0x00009888, .val = 0x0F8A0075 },
         { .reg = 0x00009888, .val = 0x1D8A0000 },
         { .reg = 0x00009888, .val = 0x118A8000 },
         { .reg = 0x00009888, .val = 0x1B8A4000 },
         { .reg = 0x00009888, .val = 0x138A8000 },
         { .reg = 0x00009888, .val = 0x1D81A000 },
         { .reg = 0x00009888, .val = 0x15818000 },
         { .reg = 0x00009888, .val = 0x17818000 },
         { .reg = 0x00009888, .val = 0x0B820030 },
         { .reg = 0x00009888, .val = 0x07828000 },
         { .reg = 0x00009888, .val = 0x0D824000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0D830003 },
         { .reg = 0x00009888, .val = 0x0583000C },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x03838000 },
         { .reg = 0x00009888, .val = 0x07838000 },
         { .reg = 0x00009888, .val = 0x0B840980 },
         { .reg = 0x00009888, .val = 0x03844D80 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x09848000 },
         { .reg = 0x00009888, .val = 0x09850080 },
         { .reg = 0x00009888, .val = 0x03850003 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x07860000 },
         { .reg = 0x00009888, .val = 0x0F860400 },
         { .reg = 0x00009888, .val = 0x09870032 },
         { .reg = 0x00009888, .val = 0x01888052 },
         { .reg = 0x00009888, .val = 0x11880000 },
         { .reg = 0x00009888, .val = 0x09884000 },
         { .reg = 0x00009888, .val = 0x1B931001 },
         { .reg = 0x00009888, .val = 0x1D930001 },
         { .reg = 0x00009888, .val = 0x19934000 },
         { .reg = 0x00009888, .val = 0x1B958000 },
         { .reg = 0x00009888, .val = 0x1D950094 },
         { .reg = 0x00009888, .val = 0x19958000 },
         { .reg = 0x00009888, .val = 0x09E58000 },
         { .reg = 0x00009888, .val = 0x0BE58000 },
         { .reg = 0x00009888, .val = 0x03E5C000 },
         { .reg = 0x00009888, .val = 0x0592C000 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D924000 },
         { .reg = 0x00009888, .val = 0x0F924000 },
         { .reg = 0x00009888, .val = 0x11928000 },
         { .reg = 0x00009888, .val = 0x1392C000 },
         { .reg = 0x00009888, .val = 0x09924000 },
         { .reg = 0x00009888, .val = 0x01985000 },
         { .reg = 0x00009888, .val = 0x07988000 },
         { .reg = 0x00009888, .val = 0x09981000 },
         { .reg = 0x00009888, .val = 0x0B982000 },
         { .reg = 0x00009888, .val = 0x0D982000 },
         { .reg = 0x00009888, .val = 0x0F989000 },
         { .reg = 0x00009888, .val = 0x05982000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25908000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29908000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1190C080 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900440 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900400 },
         { .reg = 0x00009888, .val = 0x47900C21 },
         { .reg = 0x00009888, .val = 0x57900400 },
         { .reg = 0x00009888, .val = 0x49900042 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900024 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900841 },
         { .reg = 0x00009888, .val = 0x53900400 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__render_pipe_profile__avg_gpu_core_frequency__max,kblgt2__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,kblgt2__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,kblgt2__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,kblgt2__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,kblgt2__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,kblgt2__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,kblgt2__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,kblgt2__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,kblgt2__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,kblgt2__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, kblgt2__render_pipe_profile__slm_bytes_read__max,kblgt2__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, kblgt2__render_pipe_profile__slm_bytes_written__max,kblgt2__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,kblgt2__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,kblgt2__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, kblgt2__render_pipe_profile__l3_shader_throughput__max,kblgt2__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,kblgt2__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, NULL,kblgt2__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, NULL,kblgt2__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, NULL,kblgt2__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, NULL,kblgt2__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, NULL,kblgt2__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, NULL,kblgt2__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, NULL,kblgt2__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, NULL,kblgt2__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, NULL,kblgt2__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, NULL,kblgt2__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, NULL,kblgt2__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, NULL,kblgt2__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, NULL,kblgt2__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, NULL,kblgt2__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, NULL,kblgt2__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, NULL,kblgt2__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Reads Distribution metrics set";
   query->symbol_name = "MemoryReads";
   query->guid = "57b59202-172b-477a-87de-33f85572c589";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900064 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900150 },
         { .reg = 0x00009888, .val = 0x21900151 },
         { .reg = 0x00009888, .val = 0x23900152 },
         { .reg = 0x00009888, .val = 0x25900153 },
         { .reg = 0x00009888, .val = 0x27900154 },
         { .reg = 0x00009888, .val = 0x29900155 },
         { .reg = 0x00009888, .val = 0x2B900156 },
         { .reg = 0x00009888, .val = 0x2D900157 },
         { .reg = 0x00009888, .val = 0x2F90015F },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__memory_reads__avg_gpu_core_frequency__max,kblgt2__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,kblgt2__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,kblgt2__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,kblgt2__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,kblgt2__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,kblgt2__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,kblgt2__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,kblgt2__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,kblgt2__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,kblgt2__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, kblgt2__memory_reads__slm_bytes_read__max,kblgt2__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, kblgt2__memory_reads__slm_bytes_written__max,kblgt2__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,kblgt2__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,kblgt2__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,kblgt2__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 95, 200, NULL,kblgt2__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 208, NULL,kblgt2__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 216, NULL,kblgt2__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 224, NULL,kblgt2__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 232, NULL,kblgt2__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 240, NULL,kblgt2__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 248, NULL,kblgt2__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 256, NULL,kblgt2__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 264, NULL,kblgt2__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 272, NULL,kblgt2__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 280, NULL,kblgt2__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 288, NULL,kblgt2__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 296, NULL,kblgt2__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 304, NULL,kblgt2__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 312, NULL,kblgt2__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metrics set";
   query->symbol_name = "MemoryWrites";
   query->guid = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F901000 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900160 },
         { .reg = 0x00009888, .val = 0x21900161 },
         { .reg = 0x00009888, .val = 0x23900162 },
         { .reg = 0x00009888, .val = 0x25900163 },
         { .reg = 0x00009888, .val = 0x27900164 },
         { .reg = 0x00009888, .val = 0x29900165 },
         { .reg = 0x00009888, .val = 0x2B900166 },
         { .reg = 0x00009888, .val = 0x2D900167 },
         { .reg = 0x00009888, .val = 0x2F900150 },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__memory_writes__avg_gpu_core_frequency__max,kblgt2__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,kblgt2__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,kblgt2__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,kblgt2__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,kblgt2__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,kblgt2__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,kblgt2__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,kblgt2__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,kblgt2__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,kblgt2__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, kblgt2__memory_writes__slm_bytes_read__max,kblgt2__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, kblgt2__memory_writes__slm_bytes_written__max,kblgt2__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,kblgt2__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,kblgt2__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, kblgt2__memory_writes__l3_shader_throughput__max,kblgt2__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,kblgt2__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,kblgt2__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,kblgt2__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,kblgt2__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,kblgt2__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,kblgt2__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,kblgt2__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,kblgt2__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,kblgt2__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,kblgt2__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,kblgt2__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,kblgt2__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,kblgt2__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,kblgt2__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,kblgt2__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended set";
   query->symbol_name = "ComputeExtended";
   query->guid = "4af0400a-81c3-47db-a6b6-deddbd75680e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x141C8160 },
         { .reg = 0x00009888, .val = 0x161C8015 },
         { .reg = 0x00009888, .val = 0x181C0120 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4EAAA0 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0E6C0B01 },
         { .reg = 0x00009888, .val = 0x006C0200 },
         { .reg = 0x00009888, .val = 0x026C000C },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x001C0041 },
         { .reg = 0x00009888, .val = 0x061C4200 },
         { .reg = 0x00009888, .val = 0x081C4443 },
         { .reg = 0x00009888, .val = 0x0A1C4645 },
         { .reg = 0x00009888, .val = 0x0C1C7647 },
         { .reg = 0x00009888, .val = 0x041C7357 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x1A1C0000 },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4CAA2A },
         { .reg = 0x00009888, .val = 0x0C4C02AA },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5515 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x11907FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900040 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900802 },
         { .reg = 0x00009888, .val = 0x47900842 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900842 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900800 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__compute_extended__avg_gpu_core_frequency__max,kblgt2__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,kblgt2__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,kblgt2__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,kblgt2__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,kblgt2__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,kblgt2__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,kblgt2__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, kblgt2__compute_extended__eu_avg_ipc_rate__max,kblgt2__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,kblgt2__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,kblgt2__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,kblgt2__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,kblgt2__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, kblgt2__compute_extended__slm_bytes_read__max,kblgt2__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, kblgt2__compute_extended__slm_bytes_written__max,kblgt2__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,kblgt2__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,kblgt2__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, kblgt2__compute_extended__l3_shader_throughput__max,kblgt2__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,kblgt2__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,kblgt2__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,kblgt2__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,kblgt2__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,kblgt2__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,kblgt2__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,kblgt2__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,kblgt2__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,kblgt2__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,kblgt2__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,kblgt2__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,kblgt2__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,kblgt2__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,kblgt2__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 232, NULL,kblgt2__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 236, NULL,kblgt2__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 240, NULL,kblgt2__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 244, NULL,kblgt2__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 248, NULL,kblgt2__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 54);

   query->name = "Compute Metrics L3 Cache set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "0e22f995-79ca-4f67-83ab-e9d9772488d8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C0760 },
         { .reg = 0x00009888, .val = 0x1593001E },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4E8020 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x006C0051 },
         { .reg = 0x00009888, .val = 0x066C5000 },
         { .reg = 0x00009888, .val = 0x086C5C5D },
         { .reg = 0x00009888, .val = 0x0E6C5E5F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x061B8000 },
         { .reg = 0x00009888, .val = 0x081BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1CE000 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2A00 },
         { .reg = 0x00009888, .val = 0x0C4C0280 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F1500 },
         { .reg = 0x00009888, .val = 0x100F0140 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x182C00A0 },
         { .reg = 0x00009888, .val = 0x03933300 },
         { .reg = 0x00009888, .val = 0x05930032 },
         { .reg = 0x00009888, .val = 0x11930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190030F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900021 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x53904444 },
         { .reg = 0x00009888, .val = 0x43900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__compute_l3_cache__avg_gpu_core_frequency__max,kblgt2__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,kblgt2__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,kblgt2__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, kblgt2__compute_l3_cache__eu_avg_ipc_rate__max,kblgt2__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,kblgt2__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,kblgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,kblgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,kblgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,kblgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,kblgt2__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,kblgt2__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,kblgt2__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,kblgt2__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,kblgt2__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,kblgt2__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,kblgt2__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,kblgt2__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,kblgt2__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,kblgt2__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,kblgt2__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,kblgt2__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,kblgt2__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,kblgt2__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, kblgt2__compute_l3_cache__slm_bytes_read__max,kblgt2__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, kblgt2__compute_l3_cache__slm_bytes_written__max,kblgt2__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,kblgt2__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,kblgt2__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 256, NULL,kblgt2__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 264, NULL,kblgt2__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, kblgt2__compute_l3_cache__l3_sampler_throughput__max,kblgt2__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 280, kblgt2__compute_l3_cache__l3_shader_throughput__max,kblgt2__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 288, kblgt2__compute_l3_cache__l3_total_throughput__max,kblgt2__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,kblgt2__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 304, NULL,kblgt2__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 312, NULL,kblgt2__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 320, NULL,kblgt2__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 328, NULL,kblgt2__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 336, NULL,kblgt2__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 344, NULL,kblgt2__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 352, kblgt2__compute_l3_cache__gti_l3_throughput__max,kblgt2__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 360, kblgt2__compute_l3_cache__gti_read_throughput__max,kblgt2__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 368, kblgt2__compute_l3_cache__gti_write_throughput__max,kblgt2__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "fb149d66-fad2-4230-b0d7-4d689b9116d3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F0232 },
         { .reg = 0x00009888, .val = 0x124F4640 },
         { .reg = 0x00009888, .val = 0x106C0232 },
         { .reg = 0x00009888, .val = 0x11834400 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x004F1880 },
         { .reg = 0x00009888, .val = 0x024F08BB },
         { .reg = 0x00009888, .val = 0x044F001B },
         { .reg = 0x00009888, .val = 0x046C0100 },
         { .reg = 0x00009888, .val = 0x066C000B },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x041B8000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025BC000 },
         { .reg = 0x00009888, .val = 0x045B4000 },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x165C8000 },
         { .reg = 0x00009888, .val = 0x185C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00A0 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x062CC000 },
         { .reg = 0x00009888, .val = 0x082CC000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x0F8305C0 },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x07830000 },
         { .reg = 0x00009888, .val = 0x1D950080 },
         { .reg = 0x00009888, .val = 0x13928000 },
         { .reg = 0x00009888, .val = 0x0F988000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900040 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__hdc_and_sf__avg_gpu_core_frequency__max,kblgt2__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt2__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt2__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt2__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt2__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt2__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt2__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt2__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt2__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt2__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt2__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt2__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt2__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt2__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt2__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt2__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt2__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt2__hdc_and_sf__slm_bytes_read__max,kblgt2__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt2__hdc_and_sf__slm_bytes_written__max,kblgt2__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt2__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt2__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt2__hdc_and_sf__l3_shader_throughput__max,kblgt2__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt2__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,kblgt2__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 244, percentage_max_float,kblgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,kblgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 238, 252, percentage_max_float,kblgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,kblgt2__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "f889f8cc-4c93-4ac8-b75f-551c0b9b87f7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C7B40 },
         { .reg = 0x00009888, .val = 0x166C0020 },
         { .reg = 0x00009888, .val = 0x0A603444 },
         { .reg = 0x00009888, .val = 0x0A613400 },
         { .reg = 0x00009888, .val = 0x1A4EA800 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x0C6C5327 },
         { .reg = 0x00009888, .val = 0x0E6C5425 },
         { .reg = 0x00009888, .val = 0x006C2A00 },
         { .reg = 0x00009888, .val = 0x026C285B },
         { .reg = 0x00009888, .val = 0x046C005C },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0800 },
         { .reg = 0x00009888, .val = 0x0C1BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x1C1C003C },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x10600000 },
         { .reg = 0x00009888, .val = 0x04600000 },
         { .reg = 0x00009888, .val = 0x0C610044 },
         { .reg = 0x00009888, .val = 0x10610000 },
         { .reg = 0x00009888, .val = 0x06610000 },
         { .reg = 0x00009888, .val = 0x0C4C02A8 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0154 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190FFC0 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900420 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900021 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900400 },
         { .reg = 0x00009888, .val = 0x43900421 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__l3_1__avg_gpu_core_frequency__max,kblgt2__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt2__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt2__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt2__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt2__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt2__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt2__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt2__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt2__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt2__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt2__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt2__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt2__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt2__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt2__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt2__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt2__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt2__l3_1__slm_bytes_read__max,kblgt2__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt2__l3_1__slm_bytes_written__max,kblgt2__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt2__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt2__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt2__l3_1__l3_shader_throughput__max,kblgt2__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt2__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,kblgt2__l3_1__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,kblgt2__l3_1__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,kblgt2__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,kblgt2__l3_1__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,kblgt2__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_2";
   query->symbol_name = "L3_2";
   query->guid = "6d344efd-8e9e-42d4-a29e-1011c29f82c2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C02E0 },
         { .reg = 0x00009888, .val = 0x146C0001 },
         { .reg = 0x00009888, .val = 0x0A623400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x026C3324 },
         { .reg = 0x00009888, .val = 0x046C3422 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x06614000 },
         { .reg = 0x00009888, .val = 0x0C620044 },
         { .reg = 0x00009888, .val = 0x10620000 },
         { .reg = 0x00009888, .val = 0x06620000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__l3_2__avg_gpu_core_frequency__max,kblgt2__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt2__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt2__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt2__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt2__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt2__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt2__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt2__l3_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt2__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt2__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt2__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt2__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt2__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt2__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt2__l3_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt2__l3_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt2__l3_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt2__l3_2__slm_bytes_read__max,kblgt2__l3_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt2__l3_2__slm_bytes_written__max,kblgt2__l3_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt2__l3_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt2__l3_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt2__l3_2__l3_shader_throughput__max,kblgt2__l3_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt2__l3_2__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 257, 240, percentage_max_float,kblgt2__l3_2__l30_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 260, 244, percentage_max_float,kblgt2__l3_2__l30_bank2_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,kblgt2__l3_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_3";
   query->symbol_name = "L3_3";
   query->guid = "e3b386ae-c195-47d5-af29-8a1afa0ae2bf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C4E80 },
         { .reg = 0x00009888, .val = 0x146C0000 },
         { .reg = 0x00009888, .val = 0x0A633400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x026C3321 },
         { .reg = 0x00009888, .val = 0x046C342F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C2000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x06604000 },
         { .reg = 0x00009888, .val = 0x0C630044 },
         { .reg = 0x00009888, .val = 0x10630000 },
         { .reg = 0x00009888, .val = 0x06630000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00AA },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__l3_3__avg_gpu_core_frequency__max,kblgt2__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt2__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt2__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt2__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt2__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt2__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt2__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt2__l3_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt2__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt2__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt2__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt2__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt2__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt2__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt2__l3_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt2__l3_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt2__l3_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt2__l3_3__slm_bytes_read__max,kblgt2__l3_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt2__l3_3__slm_bytes_written__max,kblgt2__l3_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt2__l3_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt2__l3_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt2__l3_3__l3_shader_throughput__max,kblgt2__l3_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt2__l3_3__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 253, 240, percentage_max_float,kblgt2__l3_3__l30_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 256, 244, percentage_max_float,kblgt2__l3_3__l30_bank3_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,kblgt2__l3_3__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "f9954679-a055-4862-9f57-9d66e3ebf81c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x102F3800 },
         { .reg = 0x00009888, .val = 0x144D0500 },
         { .reg = 0x00009888, .val = 0x120D03C0 },
         { .reg = 0x00009888, .val = 0x140D03CF },
         { .reg = 0x00009888, .val = 0x0C0F0004 },
         { .reg = 0x00009888, .val = 0x0C4E4000 },
         { .reg = 0x00009888, .val = 0x042F0480 },
         { .reg = 0x00009888, .val = 0x082F0000 },
         { .reg = 0x00009888, .val = 0x022F0000 },
         { .reg = 0x00009888, .val = 0x0A4C0090 },
         { .reg = 0x00009888, .val = 0x064D0027 },
         { .reg = 0x00009888, .val = 0x004D0000 },
         { .reg = 0x00009888, .val = 0x000D0D40 },
         { .reg = 0x00009888, .val = 0x020D803F },
         { .reg = 0x00009888, .val = 0x040D8023 },
         { .reg = 0x00009888, .val = 0x100D0000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020F0010 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0050 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41901400 },
         { .reg = 0x00009888, .val = 0x43901485 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000EFFF },
         { .reg = 0x00002778, .val = 0x00006000 },
         { .reg = 0x0000277C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt2__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt2__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt2__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt2__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt2__rasterizer_and_pixel_backend__slm_bytes_read__max,kblgt2__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt2__rasterizer_and_pixel_backend__slm_bytes_written__max,kblgt2__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt2__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt2__rasterizer_and_pixel_backend__l3_shader_throughput__max,kblgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt2__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 240, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 244, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 248, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 252, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 256, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,kblgt2__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler";
   query->symbol_name = "Sampler";
   query->guid = "4ed5e27e-fd1a-4f11-ad8f-9374e128c697";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x14152C00 },
         { .reg = 0x00009888, .val = 0x16150005 },
         { .reg = 0x00009888, .val = 0x121600A0 },
         { .reg = 0x00009888, .val = 0x14352C00 },
         { .reg = 0x00009888, .val = 0x16350005 },
         { .reg = 0x00009888, .val = 0x123600A0 },
         { .reg = 0x00009888, .val = 0x14552C00 },
         { .reg = 0x00009888, .val = 0x16550005 },
         { .reg = 0x00009888, .val = 0x125600A0 },
         { .reg = 0x00009888, .val = 0x062F6000 },
         { .reg = 0x00009888, .val = 0x022F2000 },
         { .reg = 0x00009888, .val = 0x0C4C0050 },
         { .reg = 0x00009888, .val = 0x0A4C0010 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0350 },
         { .reg = 0x00009888, .val = 0x0C0FB000 },
         { .reg = 0x00009888, .val = 0x0E0F00DA },
         { .reg = 0x00009888, .val = 0x182C0028 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x022DC000 },
         { .reg = 0x00009888, .val = 0x042D4000 },
         { .reg = 0x00009888, .val = 0x0C138000 },
         { .reg = 0x00009888, .val = 0x0E132000 },
         { .reg = 0x00009888, .val = 0x0413C000 },
         { .reg = 0x00009888, .val = 0x1C140018 },
         { .reg = 0x00009888, .val = 0x0C157000 },
         { .reg = 0x00009888, .val = 0x0E150078 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x04162180 },
         { .reg = 0x00009888, .val = 0x02160000 },
         { .reg = 0x00009888, .val = 0x04174000 },
         { .reg = 0x00009888, .val = 0x0233A000 },
         { .reg = 0x00009888, .val = 0x04333000 },
         { .reg = 0x00009888, .val = 0x14348000 },
         { .reg = 0x00009888, .val = 0x16348000 },
         { .reg = 0x00009888, .val = 0x02357870 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x04360043 },
         { .reg = 0x00009888, .val = 0x02360000 },
         { .reg = 0x00009888, .val = 0x04371000 },
         { .reg = 0x00009888, .val = 0x0E538000 },
         { .reg = 0x00009888, .val = 0x00538000 },
         { .reg = 0x00009888, .val = 0x06533000 },
         { .reg = 0x00009888, .val = 0x1C540020 },
         { .reg = 0x00009888, .val = 0x12548000 },
         { .reg = 0x00009888, .val = 0x0E557000 },
         { .reg = 0x00009888, .val = 0x00557800 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x06560043 },
         { .reg = 0x00009888, .val = 0x02560000 },
         { .reg = 0x00009888, .val = 0x06571000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900060 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900060 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__sampler__avg_gpu_core_frequency__max,kblgt2__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__sampler__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__sampler__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__sampler__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__sampler__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__sampler__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__sampler__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__sampler__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__sampler__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__sampler__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__sampler__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt2__sampler__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt2__sampler__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt2__sampler__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt2__sampler__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt2__sampler__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt2__sampler__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt2__sampler__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt2__sampler__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt2__sampler__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt2__sampler__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt2__sampler__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt2__sampler__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt2__sampler__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt2__sampler__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt2__sampler__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt2__sampler__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt2__sampler__slm_bytes_read__max,kblgt2__sampler__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt2__sampler__slm_bytes_written__max,kblgt2__sampler__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt2__sampler__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt2__sampler__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt2__sampler__l3_shader_throughput__max,kblgt2__sampler__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt2__sampler__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,kblgt2__sampler__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,kblgt2__sampler__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,kblgt2__sampler__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,kblgt2__sampler__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,kblgt2__sampler__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,kblgt2__sampler__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,kblgt2__sampler__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "9eaf384d-8f53-41b8-a71d-108308780fbc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12120000 },
         { .reg = 0x00009888, .val = 0x12320000 },
         { .reg = 0x00009888, .val = 0x12520000 },
         { .reg = 0x00009888, .val = 0x002F8000 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0015 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F03A0 },
         { .reg = 0x00009888, .val = 0x0C0FF000 },
         { .reg = 0x00009888, .val = 0x0E0F0095 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2D8000 },
         { .reg = 0x00009888, .val = 0x0E2D4000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x02108000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x02118000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x02121880 },
         { .reg = 0x00009888, .val = 0x041219B5 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x02134000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x0C308000 },
         { .reg = 0x00009888, .val = 0x0E304000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x0C318000 },
         { .reg = 0x00009888, .val = 0x0E314000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x0C321A80 },
         { .reg = 0x00009888, .val = 0x0E320033 },
         { .reg = 0x00009888, .val = 0x06320031 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x0C334000 },
         { .reg = 0x00009888, .val = 0x0E331000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0E508000 },
         { .reg = 0x00009888, .val = 0x00508000 },
         { .reg = 0x00009888, .val = 0x02504000 },
         { .reg = 0x00009888, .val = 0x0E518000 },
         { .reg = 0x00009888, .val = 0x00518000 },
         { .reg = 0x00009888, .val = 0x02514000 },
         { .reg = 0x00009888, .val = 0x0E521880 },
         { .reg = 0x00009888, .val = 0x00521A80 },
         { .reg = 0x00009888, .val = 0x02520033 },
         { .reg = 0x00009888, .val = 0x0E534000 },
         { .reg = 0x00009888, .val = 0x00534000 },
         { .reg = 0x00009888, .val = 0x02531000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900062 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x00007FFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x00009FFF },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000EFFF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000F3FF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FDFF },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__tdl_1__avg_gpu_core_frequency__max,kblgt2__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt2__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt2__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt2__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt2__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt2__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt2__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt2__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt2__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt2__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt2__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt2__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt2__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt2__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt2__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt2__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt2__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt2__tdl_1__slm_bytes_read__max,kblgt2__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt2__tdl_1__slm_bytes_written__max,kblgt2__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt2__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt2__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt2__tdl_1__l3_shader_throughput__max,kblgt2__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt2__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 240, percentage_max_float,kblgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 244, percentage_max_float,kblgt2__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 248, percentage_max_float,kblgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 252, percentage_max_float,kblgt2__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 256, percentage_max_float,kblgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 260, percentage_max_float,kblgt2__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,kblgt2__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "a00cbdf2-eabd-4240-9a89-86e2ac1ca1e4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12124D60 },
         { .reg = 0x00009888, .val = 0x12322E60 },
         { .reg = 0x00009888, .val = 0x12524D60 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0014 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0FE000 },
         { .reg = 0x00009888, .val = 0x0E0F0097 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x002D8000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x04121FB7 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x00308000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x00318000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x00321B80 },
         { .reg = 0x00009888, .val = 0x0632003F },
         { .reg = 0x00009888, .val = 0x00334000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0250C000 },
         { .reg = 0x00009888, .val = 0x0251C000 },
         { .reg = 0x00009888, .val = 0x02521FB7 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x02535000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900063 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__tdl_2__avg_gpu_core_frequency__max,kblgt2__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt2__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt2__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt2__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt2__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt2__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt2__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt2__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt2__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt2__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt2__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt2__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt2__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt2__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt2__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt2__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt2__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt2__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt2__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt2__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt2__tdl_2__slm_bytes_read__max,kblgt2__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt2__tdl_2__slm_bytes_written__max,kblgt2__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt2__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt2__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt2__tdl_2__l3_shader_throughput__max,kblgt2__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt2__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 240, percentage_max_float,kblgt2__tdl_2__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 244, percentage_max_float,kblgt2__tdl_2__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 248, percentage_max_float,kblgt2__tdl_2__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 252, percentage_max_float,kblgt2__tdl_2__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 256, percentage_max_float,kblgt2__tdl_2__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 260, percentage_max_float,kblgt2__tdl_2__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,kblgt2__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "aa7a3fb9-22fb-43ff-a32d-0ab6c13bbd16";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x121203E0 },
         { .reg = 0x00009888, .val = 0x123203E0 },
         { .reg = 0x00009888, .val = 0x125203E0 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0A4C0040 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0E0F006C },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x042D8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06114000 },
         { .reg = 0x00009888, .val = 0x06120033 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x04308000 },
         { .reg = 0x00009888, .val = 0x04318000 },
         { .reg = 0x00009888, .val = 0x04321980 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x04334000 },
         { .reg = 0x00009888, .val = 0x04504000 },
         { .reg = 0x00009888, .val = 0x04514000 },
         { .reg = 0x00009888, .val = 0x04520033 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x04531000 },
         { .reg = 0x00009888, .val = 0x1190E000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900C00 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00001000 },
         { .reg = 0x0000E558, .val = 0x00003002 },
         { .reg = 0x0000E658, .val = 0x00005004 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00050012 },
         { .reg = 0x0000E55C, .val = 0x00052051 },
         { .reg = 0x0000E65C, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__compute_extra__avg_gpu_core_frequency__max,kblgt2__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,kblgt2__compute_extra__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 307, 28, percentage_max_float,kblgt2__compute_extra__fpu1_active_adjusted__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_vme_pipe_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Media Vme Pipe metrics set";
   query->symbol_name = "VMEPipe";
   query->guid = "398a4268-ef6f-4ffc-b55f-3c7b5363ce61";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A5800 },
         { .reg = 0x00009888, .val = 0x161A00C0 },
         { .reg = 0x00009888, .val = 0x12180240 },
         { .reg = 0x00009888, .val = 0x14180002 },
         { .reg = 0x00009888, .val = 0x143A5800 },
         { .reg = 0x00009888, .val = 0x163A00C0 },
         { .reg = 0x00009888, .val = 0x12380240 },
         { .reg = 0x00009888, .val = 0x14380002 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x022F8000 },
         { .reg = 0x00009888, .val = 0x042F3000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C1500 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F9500 },
         { .reg = 0x00009888, .val = 0x100F002A },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x0A2DC000 },
         { .reg = 0x00009888, .val = 0x0C2DC000 },
         { .reg = 0x00009888, .val = 0x04193000 },
         { .reg = 0x00009888, .val = 0x081A28C1 },
         { .reg = 0x00009888, .val = 0x001A0000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x0613C000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x00172000 },
         { .reg = 0x00009888, .val = 0x06178000 },
         { .reg = 0x00009888, .val = 0x0817A000 },
         { .reg = 0x00009888, .val = 0x00180037 },
         { .reg = 0x00009888, .val = 0x06180940 },
         { .reg = 0x00009888, .val = 0x08180000 },
         { .reg = 0x00009888, .val = 0x02180000 },
         { .reg = 0x00009888, .val = 0x04183000 },
         { .reg = 0x00009888, .val = 0x06393000 },
         { .reg = 0x00009888, .val = 0x0C3A28C1 },
         { .reg = 0x00009888, .val = 0x003A0000 },
         { .reg = 0x00009888, .val = 0x0A33F000 },
         { .reg = 0x00009888, .val = 0x0C33F000 },
         { .reg = 0x00009888, .val = 0x0A37A000 },
         { .reg = 0x00009888, .val = 0x0C37A000 },
         { .reg = 0x00009888, .val = 0x0A380977 },
         { .reg = 0x00009888, .val = 0x08380000 },
         { .reg = 0x00009888, .val = 0x04380000 },
         { .reg = 0x00009888, .val = 0x06383000 },
         { .reg = 0x00009888, .val = 0x119000FF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900040 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900800 },
         { .reg = 0x00009888, .val = 0x47901000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900844 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00100030 },
         { .reg = 0x00002774, .val = 0x0000FFF9 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFFC },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFF3 },
         { .reg = 0x00002788, .val = 0x00100180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__vme_pipe__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__vme_pipe__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__vme_pipe__avg_gpu_core_frequency__max,kblgt2__vme_pipe__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__vme_pipe__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,kblgt2__vme_pipe__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 40, percentage_max_float,kblgt2__vme_pipe__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 44, percentage_max_float,kblgt2__vme_pipe__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 48, percentage_max_float,kblgt2__vme_pipe__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 52, percentage_max_float,kblgt2__vme_pipe__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 308, 56, percentage_max_float,kblgt2__vme_pipe__vme_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Gpu Rings Busyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "6c66fe6e-2988-454a-bfae-7fca3bbcbec2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x13805800 },
         { .reg = 0x00009888, .val = 0x05962C00 },
         { .reg = 0x00009888, .val = 0x19950016 },
         { .reg = 0x00009888, .val = 0x19C05800 },
         { .reg = 0x00009888, .val = 0x07800035 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x1D810400 },
         { .reg = 0x00009888, .val = 0x07960025 },
         { .reg = 0x00009888, .val = 0x21960000 },
         { .reg = 0x00009888, .val = 0x0B964000 },
         { .reg = 0x00009888, .val = 0x1B930062 },
         { .reg = 0x00009888, .val = 0x17948000 },
         { .reg = 0x00009888, .val = 0x1B940008 },
         { .reg = 0x00009888, .val = 0x05950075 },
         { .reg = 0x00009888, .val = 0x1D950000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x09924000 },
         { .reg = 0x00009888, .val = 0x05982000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x09978000 },
         { .reg = 0x00009888, .val = 0x05C08500 },
         { .reg = 0x00009888, .val = 0x25C00000 },
         { .reg = 0x00009888, .val = 0x1BC00000 },
         { .reg = 0x00009888, .val = 0x0BC54000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900C60 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00078000 },
         { .reg = 0x00002774, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__gpu_busyness__avg_gpu_core_frequency__max,kblgt2__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 309, 24, percentage_max_float,kblgt2__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 28, percentage_max_float,kblgt2__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 312, 32, percentage_max_float,kblgt2__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 36, percentage_max_float,kblgt2__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 40, percentage_max_float,kblgt2__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "cd4b577b-073a-423f-a948-e198dd818c71";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810000 },
         { .reg = 0x00009888, .val = 0x07810013 },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930040 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__test_oa__avg_gpu_core_frequency__max,kblgt2__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,kblgt2__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,kblgt2__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,kblgt2__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,kblgt2__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,kblgt2__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,kblgt2__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,kblgt2__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,kblgt2__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,kblgt2__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_pma__stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "PMA_Stall";
   query->guid = "b49aa434-4958-4d98-9e6f-443ff27ca74d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x122D3080 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0800 },
         { .reg = 0x00009888, .val = 0x0E0FAA00 },
         { .reg = 0x00009888, .val = 0x100F0002 },
         { .reg = 0x00009888, .val = 0x002D0025 },
         { .reg = 0x00009888, .val = 0x062D1300 },
         { .reg = 0x00009888, .val = 0x082D16A4 },
         { .reg = 0x00009888, .val = 0x0A2D162E },
         { .reg = 0x00009888, .val = 0x102D0000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00E00021 },
         { .reg = 0x00002774, .val = 0x0007FFF8 },
         { .reg = 0x00002778, .val = 0x07000101 },
         { .reg = 0x0000277C, .val = 0x0038FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__pma__stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__pma__stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__pma__stall__avg_gpu_core_frequency__max,kblgt2__pma__stall__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 24, percentage_max_float,kblgt2__pma__stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt2_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "4032137b-8dcc-4f3f-912d-c0bb14a123bc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00051050 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00061060 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt2__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt2__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt2__async_compute__avg_gpu_core_frequency__max,kblgt2__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt2__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt2__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt2__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt2__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt2__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt2__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt2__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 150, 80, percentage_max_float,kblgt2__async_compute__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 124, 84, percentage_max_float,kblgt2__async_compute__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 127, 88, percentage_max_float,kblgt2__async_compute__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 331, 92, percentage_max_float,kblgt2__async_compute__cs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,kblgt2__async_compute__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 125, 100, percentage_max_float,kblgt2__async_compute__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,kblgt2__async_compute__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 332, 108, percentage_max_float,kblgt2__async_compute__cs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 154, 112, percentage_max_float,kblgt2__async_compute__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 10, 116, percentage_max_float,kblgt2__async_compute__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 120, percentage_max_float,kblgt2__async_compute__eu_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_kblgt2(struct intel_perf_config *perf)
{
   kblgt2_register_render_basic_counter_query(perf);
   kblgt2_register_compute_basic_counter_query(perf);
   kblgt2_register_render_pipe_profile_counter_query(perf);
   kblgt2_register_memory_reads_counter_query(perf);
   kblgt2_register_memory_writes_counter_query(perf);
   kblgt2_register_compute_extended_counter_query(perf);
   kblgt2_register_compute_l3_cache_counter_query(perf);
   kblgt2_register_hdc_and_sf_counter_query(perf);
   kblgt2_register_l3_1_counter_query(perf);
   kblgt2_register_l3_2_counter_query(perf);
   kblgt2_register_l3_3_counter_query(perf);
   kblgt2_register_rasterizer_and_pixel_backend_counter_query(perf);
   kblgt2_register_sampler_counter_query(perf);
   kblgt2_register_tdl_1_counter_query(perf);
   kblgt2_register_tdl_2_counter_query(perf);
   kblgt2_register_compute_extra_counter_query(perf);
   kblgt2_register_vme_pipe_counter_query(perf);
   kblgt2_register_gpu_busyness_counter_query(perf);
   kblgt2_register_test_oa_counter_query(perf);
   kblgt2_register_pma__stall_counter_query(perf);
   kblgt2_register_async_compute_counter_query(perf);
}


static void
kblgt3_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "17b4f3e0-d578-4ae3-b7a8-98d756d1e0df";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C01E0 },
         { .reg = 0x00009888, .val = 0x12170280 },
         { .reg = 0x00009888, .val = 0x12370280 },
         { .reg = 0x00009888, .val = 0x16EC01E0 },
         { .reg = 0x00009888, .val = 0x11930317 },
         { .reg = 0x00009888, .val = 0x159303DF },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x1A4E0380 },
         { .reg = 0x00009888, .val = 0x0A6C0053 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x0A1B4000 },
         { .reg = 0x00009888, .val = 0x1C1C0001 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x042F1000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C8400 },
         { .reg = 0x00009888, .val = 0x0C4C0002 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F6600 },
         { .reg = 0x00009888, .val = 0x100F0001 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x162CA200 },
         { .reg = 0x00009888, .val = 0x062D8000 },
         { .reg = 0x00009888, .val = 0x082D8000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x08133000 },
         { .reg = 0x00009888, .val = 0x00170020 },
         { .reg = 0x00009888, .val = 0x08170021 },
         { .reg = 0x00009888, .val = 0x10170000 },
         { .reg = 0x00009888, .val = 0x0633C000 },
         { .reg = 0x00009888, .val = 0x0833C000 },
         { .reg = 0x00009888, .val = 0x06370800 },
         { .reg = 0x00009888, .val = 0x08370840 },
         { .reg = 0x00009888, .val = 0x10370000 },
         { .reg = 0x00009888, .val = 0x1ACE0200 },
         { .reg = 0x00009888, .val = 0x0AEC5300 },
         { .reg = 0x00009888, .val = 0x10EC0000 },
         { .reg = 0x00009888, .val = 0x1CEC0000 },
         { .reg = 0x00009888, .val = 0x0A9B8000 },
         { .reg = 0x00009888, .val = 0x1C9C0002 },
         { .reg = 0x00009888, .val = 0x0CCC0002 },
         { .reg = 0x00009888, .val = 0x0A8D8000 },
         { .reg = 0x00009888, .val = 0x108F0001 },
         { .reg = 0x00009888, .val = 0x16AC8000 },
         { .reg = 0x00009888, .val = 0x0D933031 },
         { .reg = 0x00009888, .val = 0x0F933E3F },
         { .reg = 0x00009888, .val = 0x01933D00 },
         { .reg = 0x00009888, .val = 0x0393073C },
         { .reg = 0x00009888, .val = 0x0593000E },
         { .reg = 0x00009888, .val = 0x1D930000 },
         { .reg = 0x00009888, .val = 0x19930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x2B908000 },
         { .reg = 0x00009888, .val = 0x2D908000 },
         { .reg = 0x00009888, .val = 0x2F908000 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x15908000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51902240 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x55900242 },
         { .reg = 0x00009888, .val = 0x45900084 },
         { .reg = 0x00009888, .val = 0x47901400 },
         { .reg = 0x00009888, .val = 0x57902220 },
         { .reg = 0x00009888, .val = 0x49900C60 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900002 },
         { .reg = 0x00009888, .val = 0x43900C63 },
         { .reg = 0x00009888, .val = 0x53902222 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__render_basic__avg_gpu_core_frequency__max,kblgt3__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,kblgt3__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,kblgt3__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,kblgt3__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,kblgt3__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,kblgt3__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,kblgt3__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,kblgt3__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,kblgt3__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,kblgt3__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,kblgt3__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,kblgt3__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,kblgt3__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,kblgt3__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,kblgt3__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,kblgt3__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,kblgt3__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,kblgt3__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,kblgt3__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,kblgt3__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,kblgt3__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,kblgt3__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,kblgt3__render_basic__sampler1_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,kblgt3__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,kblgt3__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,kblgt3__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,kblgt3__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,kblgt3__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,kblgt3__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,kblgt3__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,kblgt3__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,kblgt3__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 208, NULL,kblgt3__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, kblgt3__render_basic__slm_bytes_read__max,kblgt3__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, kblgt3__render_basic__slm_bytes_written__max,kblgt3__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,kblgt3__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,kblgt3__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,kblgt3__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,kblgt3__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, kblgt3__render_basic__l3_sampler_throughput__max,kblgt3__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, kblgt3__render_basic__l3_shader_throughput__max,kblgt3__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,kblgt3__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, kblgt3__render_basic__gti_vf_throughput__max,kblgt3__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, kblgt3__render_basic__gti_depth_throughput__max,kblgt3__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, kblgt3__render_basic__gti_rcc_throughput__max,kblgt3__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, kblgt3__render_basic__gti_l3_throughput__max,kblgt3__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, kblgt3__render_basic__gti_hdc_lookups_throughput__max,kblgt3__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, kblgt3__render_basic__gti_read_throughput__max,kblgt3__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, kblgt3__render_basic__gti_write_throughput__max,kblgt3__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,kblgt3__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "a5dc0bc5-d6fa-4f3a-9979-d3248c786042";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x124F1C00 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x1A4E0820 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x064F0900 },
         { .reg = 0x00009888, .val = 0x084F0032 },
         { .reg = 0x00009888, .val = 0x0A4F1891 },
         { .reg = 0x00009888, .val = 0x0C4F0E00 },
         { .reg = 0x00009888, .val = 0x0E4F003C },
         { .reg = 0x00009888, .val = 0x004F0D80 },
         { .reg = 0x00009888, .val = 0x024F003B },
         { .reg = 0x00009888, .val = 0x006C0002 },
         { .reg = 0x00009888, .val = 0x086C0100 },
         { .reg = 0x00009888, .val = 0x0C6C000C },
         { .reg = 0x00009888, .val = 0x0E6C0B00 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x081B8000 },
         { .reg = 0x00009888, .val = 0x0C1B4000 },
         { .reg = 0x00009888, .val = 0x0E1B8000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1C8000 },
         { .reg = 0x00009888, .val = 0x1C1C0024 },
         { .reg = 0x00009888, .val = 0x065B8000 },
         { .reg = 0x00009888, .val = 0x085B4000 },
         { .reg = 0x00009888, .val = 0x0A5BC000 },
         { .reg = 0x00009888, .val = 0x0C5B8000 },
         { .reg = 0x00009888, .val = 0x0E5B4000 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025B4000 },
         { .reg = 0x00009888, .val = 0x1A5C6000 },
         { .reg = 0x00009888, .val = 0x1C5C001B },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2000 },
         { .reg = 0x00009888, .val = 0x0C4C0208 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2CC000 },
         { .reg = 0x00009888, .val = 0x162CFB00 },
         { .reg = 0x00009888, .val = 0x182C00BE },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x19900157 },
         { .reg = 0x00009888, .val = 0x1B900158 },
         { .reg = 0x00009888, .val = 0x1D900105 },
         { .reg = 0x00009888, .val = 0x1F900103 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x11900FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900821 },
         { .reg = 0x00009888, .val = 0x47900802 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900802 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900002 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900422 },
         { .reg = 0x00009888, .val = 0x53904444 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__compute_basic__avg_gpu_core_frequency__max,kblgt3__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,kblgt3__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,kblgt3__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, kblgt3__compute_basic__eu_avg_ipc_rate__max,kblgt3__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,kblgt3__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,kblgt3__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,kblgt3__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,kblgt3__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,kblgt3__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,kblgt3__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,kblgt3__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,kblgt3__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,kblgt3__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,kblgt3__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,kblgt3__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, kblgt3__compute_basic__slm_bytes_read__max,kblgt3__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, kblgt3__compute_basic__slm_bytes_written__max,kblgt3__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,kblgt3__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,kblgt3__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, kblgt3__compute_basic__l3_shader_throughput__max,kblgt3__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,kblgt3__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, kblgt3__compute_basic__typed_bytes_read__max,kblgt3__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, kblgt3__compute_basic__typed_bytes_written__max,kblgt3__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, kblgt3__compute_basic__untyped_bytes_read__max,kblgt3__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, kblgt3__compute_basic__untyped_bytes_written__max,kblgt3__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, kblgt3__compute_basic__gti_read_throughput__max,kblgt3__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, kblgt3__compute_basic__gti_write_throughput__max,kblgt3__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "c7c735f3-ce58-45cf-aa04-30b183f1faff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x0C0E001F },
         { .reg = 0x00009888, .val = 0x0A0F0000 },
         { .reg = 0x00009888, .val = 0x10116800 },
         { .reg = 0x00009888, .val = 0x178A03E0 },
         { .reg = 0x00009888, .val = 0x11824C00 },
         { .reg = 0x00009888, .val = 0x11830020 },
         { .reg = 0x00009888, .val = 0x13840020 },
         { .reg = 0x00009888, .val = 0x11850019 },
         { .reg = 0x00009888, .val = 0x11860007 },
         { .reg = 0x00009888, .val = 0x01870C40 },
         { .reg = 0x00009888, .val = 0x17880000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0A4C0040 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020E5400 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x080F0040 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0040 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06110012 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x01898000 },
         { .reg = 0x00009888, .val = 0x0D890100 },
         { .reg = 0x00009888, .val = 0x03898000 },
         { .reg = 0x00009888, .val = 0x09808000 },
         { .reg = 0x00009888, .val = 0x0B808000 },
         { .reg = 0x00009888, .val = 0x0380C000 },
         { .reg = 0x00009888, .val = 0x0F8A0075 },
         { .reg = 0x00009888, .val = 0x1D8A0000 },
         { .reg = 0x00009888, .val = 0x118A8000 },
         { .reg = 0x00009888, .val = 0x1B8A4000 },
         { .reg = 0x00009888, .val = 0x138A8000 },
         { .reg = 0x00009888, .val = 0x1D81A000 },
         { .reg = 0x00009888, .val = 0x15818000 },
         { .reg = 0x00009888, .val = 0x17818000 },
         { .reg = 0x00009888, .val = 0x0B820030 },
         { .reg = 0x00009888, .val = 0x07828000 },
         { .reg = 0x00009888, .val = 0x0D824000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0D830003 },
         { .reg = 0x00009888, .val = 0x0583000C },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x03838000 },
         { .reg = 0x00009888, .val = 0x07838000 },
         { .reg = 0x00009888, .val = 0x0B840980 },
         { .reg = 0x00009888, .val = 0x03844D80 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x09848000 },
         { .reg = 0x00009888, .val = 0x09850080 },
         { .reg = 0x00009888, .val = 0x03850003 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x07860000 },
         { .reg = 0x00009888, .val = 0x0F860400 },
         { .reg = 0x00009888, .val = 0x09870032 },
         { .reg = 0x00009888, .val = 0x01888052 },
         { .reg = 0x00009888, .val = 0x11880000 },
         { .reg = 0x00009888, .val = 0x09884000 },
         { .reg = 0x00009888, .val = 0x1B931001 },
         { .reg = 0x00009888, .val = 0x1D930001 },
         { .reg = 0x00009888, .val = 0x19934000 },
         { .reg = 0x00009888, .val = 0x1B958000 },
         { .reg = 0x00009888, .val = 0x1D950094 },
         { .reg = 0x00009888, .val = 0x19958000 },
         { .reg = 0x00009888, .val = 0x09E58000 },
         { .reg = 0x00009888, .val = 0x0BE58000 },
         { .reg = 0x00009888, .val = 0x03E5C000 },
         { .reg = 0x00009888, .val = 0x0592C000 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D924000 },
         { .reg = 0x00009888, .val = 0x0F924000 },
         { .reg = 0x00009888, .val = 0x11928000 },
         { .reg = 0x00009888, .val = 0x1392C000 },
         { .reg = 0x00009888, .val = 0x09924000 },
         { .reg = 0x00009888, .val = 0x01985000 },
         { .reg = 0x00009888, .val = 0x07988000 },
         { .reg = 0x00009888, .val = 0x09981000 },
         { .reg = 0x00009888, .val = 0x0B982000 },
         { .reg = 0x00009888, .val = 0x0D982000 },
         { .reg = 0x00009888, .val = 0x0F989000 },
         { .reg = 0x00009888, .val = 0x05982000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25908000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29908000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1190C080 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900440 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900400 },
         { .reg = 0x00009888, .val = 0x47900C21 },
         { .reg = 0x00009888, .val = 0x57900400 },
         { .reg = 0x00009888, .val = 0x49900042 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900024 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900841 },
         { .reg = 0x00009888, .val = 0x53900400 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__render_pipe_profile__avg_gpu_core_frequency__max,kblgt3__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,kblgt3__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,kblgt3__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,kblgt3__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,kblgt3__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,kblgt3__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,kblgt3__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,kblgt3__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,kblgt3__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,kblgt3__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, kblgt3__render_pipe_profile__slm_bytes_read__max,kblgt3__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, kblgt3__render_pipe_profile__slm_bytes_written__max,kblgt3__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,kblgt3__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,kblgt3__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, kblgt3__render_pipe_profile__l3_shader_throughput__max,kblgt3__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,kblgt3__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, NULL,kblgt3__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, NULL,kblgt3__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, NULL,kblgt3__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, NULL,kblgt3__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, NULL,kblgt3__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, NULL,kblgt3__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, NULL,kblgt3__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, NULL,kblgt3__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, NULL,kblgt3__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, NULL,kblgt3__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, NULL,kblgt3__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, NULL,kblgt3__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, NULL,kblgt3__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, NULL,kblgt3__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, NULL,kblgt3__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, NULL,kblgt3__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Reads Distribution metrics set";
   query->symbol_name = "MemoryReads";
   query->guid = "96ec2219-040b-428a-856a-6bc03363a057";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900064 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900150 },
         { .reg = 0x00009888, .val = 0x21900151 },
         { .reg = 0x00009888, .val = 0x23900152 },
         { .reg = 0x00009888, .val = 0x25900153 },
         { .reg = 0x00009888, .val = 0x27900154 },
         { .reg = 0x00009888, .val = 0x29900155 },
         { .reg = 0x00009888, .val = 0x2B900156 },
         { .reg = 0x00009888, .val = 0x2D900157 },
         { .reg = 0x00009888, .val = 0x2F90015F },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__memory_reads__avg_gpu_core_frequency__max,kblgt3__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,kblgt3__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,kblgt3__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,kblgt3__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,kblgt3__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,kblgt3__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,kblgt3__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,kblgt3__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,kblgt3__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,kblgt3__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, kblgt3__memory_reads__slm_bytes_read__max,kblgt3__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, kblgt3__memory_reads__slm_bytes_written__max,kblgt3__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,kblgt3__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,kblgt3__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,kblgt3__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 95, 200, NULL,kblgt3__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 208, NULL,kblgt3__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 216, NULL,kblgt3__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 224, NULL,kblgt3__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 232, NULL,kblgt3__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 240, NULL,kblgt3__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 248, NULL,kblgt3__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 256, NULL,kblgt3__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 264, NULL,kblgt3__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 272, NULL,kblgt3__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 280, NULL,kblgt3__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 288, NULL,kblgt3__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 296, NULL,kblgt3__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 304, NULL,kblgt3__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 312, NULL,kblgt3__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metrics set";
   query->symbol_name = "MemoryWrites";
   query->guid = "03372b64-4996-4d3b-aa18-790e75eeb9c2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F901000 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900160 },
         { .reg = 0x00009888, .val = 0x21900161 },
         { .reg = 0x00009888, .val = 0x23900162 },
         { .reg = 0x00009888, .val = 0x25900163 },
         { .reg = 0x00009888, .val = 0x27900164 },
         { .reg = 0x00009888, .val = 0x29900165 },
         { .reg = 0x00009888, .val = 0x2B900166 },
         { .reg = 0x00009888, .val = 0x2D900167 },
         { .reg = 0x00009888, .val = 0x2F900150 },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__memory_writes__avg_gpu_core_frequency__max,kblgt3__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,kblgt3__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,kblgt3__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,kblgt3__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,kblgt3__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,kblgt3__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,kblgt3__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,kblgt3__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,kblgt3__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,kblgt3__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, kblgt3__memory_writes__slm_bytes_read__max,kblgt3__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, kblgt3__memory_writes__slm_bytes_written__max,kblgt3__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,kblgt3__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,kblgt3__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, kblgt3__memory_writes__l3_shader_throughput__max,kblgt3__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,kblgt3__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,kblgt3__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,kblgt3__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,kblgt3__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,kblgt3__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,kblgt3__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,kblgt3__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,kblgt3__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,kblgt3__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,kblgt3__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,kblgt3__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,kblgt3__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,kblgt3__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,kblgt3__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,kblgt3__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended set";
   query->symbol_name = "ComputeExtended";
   query->guid = "31b4ce5a-bd61-4c1f-bb5d-f2e731412150";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x141C8160 },
         { .reg = 0x00009888, .val = 0x161C8015 },
         { .reg = 0x00009888, .val = 0x181C0120 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4EAAA0 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0E6C0B01 },
         { .reg = 0x00009888, .val = 0x006C0200 },
         { .reg = 0x00009888, .val = 0x026C000C },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x001C0041 },
         { .reg = 0x00009888, .val = 0x061C4200 },
         { .reg = 0x00009888, .val = 0x081C4443 },
         { .reg = 0x00009888, .val = 0x0A1C4645 },
         { .reg = 0x00009888, .val = 0x0C1C7647 },
         { .reg = 0x00009888, .val = 0x041C7357 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x1A1C0000 },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4CAA2A },
         { .reg = 0x00009888, .val = 0x0C4C02AA },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5515 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x11907FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900040 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900802 },
         { .reg = 0x00009888, .val = 0x47900842 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900842 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900800 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__compute_extended__avg_gpu_core_frequency__max,kblgt3__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,kblgt3__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,kblgt3__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,kblgt3__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,kblgt3__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,kblgt3__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,kblgt3__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, kblgt3__compute_extended__eu_avg_ipc_rate__max,kblgt3__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,kblgt3__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,kblgt3__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,kblgt3__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,kblgt3__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, kblgt3__compute_extended__slm_bytes_read__max,kblgt3__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, kblgt3__compute_extended__slm_bytes_written__max,kblgt3__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,kblgt3__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,kblgt3__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, kblgt3__compute_extended__l3_shader_throughput__max,kblgt3__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,kblgt3__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,kblgt3__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,kblgt3__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,kblgt3__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,kblgt3__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,kblgt3__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,kblgt3__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,kblgt3__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,kblgt3__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,kblgt3__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,kblgt3__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,kblgt3__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,kblgt3__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,kblgt3__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 232, NULL,kblgt3__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 236, NULL,kblgt3__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 240, NULL,kblgt3__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 244, NULL,kblgt3__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 248, NULL,kblgt3__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 54);

   query->name = "Compute Metrics L3 Cache set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "2ce0911a-27fc-4887-96f0-11084fa807c3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C0760 },
         { .reg = 0x00009888, .val = 0x1593001E },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4E8020 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x006C0051 },
         { .reg = 0x00009888, .val = 0x066C5000 },
         { .reg = 0x00009888, .val = 0x086C5C5D },
         { .reg = 0x00009888, .val = 0x0E6C5E5F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x061B8000 },
         { .reg = 0x00009888, .val = 0x081BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1CE000 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2A00 },
         { .reg = 0x00009888, .val = 0x0C4C0280 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F1500 },
         { .reg = 0x00009888, .val = 0x100F0140 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x182C00A0 },
         { .reg = 0x00009888, .val = 0x03933300 },
         { .reg = 0x00009888, .val = 0x05930032 },
         { .reg = 0x00009888, .val = 0x11930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190030F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900021 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x53904444 },
         { .reg = 0x00009888, .val = 0x43900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__compute_l3_cache__avg_gpu_core_frequency__max,kblgt3__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,kblgt3__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,kblgt3__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, kblgt3__compute_l3_cache__eu_avg_ipc_rate__max,kblgt3__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,kblgt3__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,kblgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,kblgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,kblgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,kblgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,kblgt3__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,kblgt3__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,kblgt3__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,kblgt3__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,kblgt3__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,kblgt3__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,kblgt3__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,kblgt3__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,kblgt3__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,kblgt3__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,kblgt3__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,kblgt3__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,kblgt3__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,kblgt3__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, kblgt3__compute_l3_cache__slm_bytes_read__max,kblgt3__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, kblgt3__compute_l3_cache__slm_bytes_written__max,kblgt3__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,kblgt3__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,kblgt3__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 256, NULL,kblgt3__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 264, NULL,kblgt3__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, kblgt3__compute_l3_cache__l3_sampler_throughput__max,kblgt3__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 280, kblgt3__compute_l3_cache__l3_shader_throughput__max,kblgt3__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 288, kblgt3__compute_l3_cache__l3_total_throughput__max,kblgt3__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,kblgt3__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 304, NULL,kblgt3__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 312, NULL,kblgt3__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 320, NULL,kblgt3__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 328, NULL,kblgt3__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 336, NULL,kblgt3__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 344, NULL,kblgt3__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 352, kblgt3__compute_l3_cache__gti_l3_throughput__max,kblgt3__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 360, kblgt3__compute_l3_cache__gti_read_throughput__max,kblgt3__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 368, kblgt3__compute_l3_cache__gti_write_throughput__max,kblgt3__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "b128f45f-bfa2-4991-aadc-05be7898e398";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F0232 },
         { .reg = 0x00009888, .val = 0x124F4640 },
         { .reg = 0x00009888, .val = 0x106C0232 },
         { .reg = 0x00009888, .val = 0x11834400 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x004F1880 },
         { .reg = 0x00009888, .val = 0x024F08BB },
         { .reg = 0x00009888, .val = 0x044F001B },
         { .reg = 0x00009888, .val = 0x046C0100 },
         { .reg = 0x00009888, .val = 0x066C000B },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x041B8000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025BC000 },
         { .reg = 0x00009888, .val = 0x045B4000 },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x165C8000 },
         { .reg = 0x00009888, .val = 0x185C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00A0 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x062CC000 },
         { .reg = 0x00009888, .val = 0x082CC000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x0F8305C0 },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x07830000 },
         { .reg = 0x00009888, .val = 0x1D950080 },
         { .reg = 0x00009888, .val = 0x13928000 },
         { .reg = 0x00009888, .val = 0x0F988000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900040 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__hdc_and_sf__avg_gpu_core_frequency__max,kblgt3__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt3__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt3__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt3__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt3__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt3__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt3__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt3__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt3__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt3__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt3__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt3__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt3__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt3__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt3__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt3__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt3__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt3__hdc_and_sf__slm_bytes_read__max,kblgt3__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt3__hdc_and_sf__slm_bytes_written__max,kblgt3__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt3__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt3__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt3__hdc_and_sf__l3_shader_throughput__max,kblgt3__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt3__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,kblgt3__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 244, percentage_max_float,kblgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,kblgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 238, 252, percentage_max_float,kblgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,kblgt3__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "f3566b55-9c13-47bf-8327-4a887af75262";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C7B40 },
         { .reg = 0x00009888, .val = 0x166C0020 },
         { .reg = 0x00009888, .val = 0x0A603444 },
         { .reg = 0x00009888, .val = 0x0A613400 },
         { .reg = 0x00009888, .val = 0x1A4EA800 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x0C6C5327 },
         { .reg = 0x00009888, .val = 0x0E6C5425 },
         { .reg = 0x00009888, .val = 0x006C2A00 },
         { .reg = 0x00009888, .val = 0x026C285B },
         { .reg = 0x00009888, .val = 0x046C005C },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0800 },
         { .reg = 0x00009888, .val = 0x0C1BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x1C1C003C },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x10600000 },
         { .reg = 0x00009888, .val = 0x04600000 },
         { .reg = 0x00009888, .val = 0x0C610044 },
         { .reg = 0x00009888, .val = 0x10610000 },
         { .reg = 0x00009888, .val = 0x06610000 },
         { .reg = 0x00009888, .val = 0x0C4C02A8 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0154 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190FFC0 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900420 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900021 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900400 },
         { .reg = 0x00009888, .val = 0x43900421 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__l3_1__avg_gpu_core_frequency__max,kblgt3__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt3__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt3__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt3__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt3__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt3__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt3__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt3__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt3__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt3__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt3__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt3__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt3__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt3__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt3__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt3__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt3__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt3__l3_1__slm_bytes_read__max,kblgt3__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt3__l3_1__slm_bytes_written__max,kblgt3__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt3__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt3__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt3__l3_1__l3_shader_throughput__max,kblgt3__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt3__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,kblgt3__l3_1__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,kblgt3__l3_1__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,kblgt3__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,kblgt3__l3_1__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,kblgt3__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_2";
   query->symbol_name = "L3_2";
   query->guid = "7b21aa68-9076-4ab4-8a84-e45a06c8eac6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C02E0 },
         { .reg = 0x00009888, .val = 0x146C0001 },
         { .reg = 0x00009888, .val = 0x0A623400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x026C3324 },
         { .reg = 0x00009888, .val = 0x046C3422 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x06614000 },
         { .reg = 0x00009888, .val = 0x0C620044 },
         { .reg = 0x00009888, .val = 0x10620000 },
         { .reg = 0x00009888, .val = 0x06620000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__l3_2__avg_gpu_core_frequency__max,kblgt3__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt3__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt3__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt3__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt3__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt3__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt3__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt3__l3_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt3__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt3__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt3__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt3__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt3__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt3__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt3__l3_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt3__l3_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt3__l3_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt3__l3_2__slm_bytes_read__max,kblgt3__l3_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt3__l3_2__slm_bytes_written__max,kblgt3__l3_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt3__l3_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt3__l3_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt3__l3_2__l3_shader_throughput__max,kblgt3__l3_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt3__l3_2__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 257, 240, percentage_max_float,kblgt3__l3_2__l30_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 260, 244, percentage_max_float,kblgt3__l3_2__l30_bank2_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,kblgt3__l3_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_3";
   query->symbol_name = "L3_3";
   query->guid = "71b4b9dd-ae28-48ce-9a1a-5431e1f23afd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C4E80 },
         { .reg = 0x00009888, .val = 0x146C0000 },
         { .reg = 0x00009888, .val = 0x0A633400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x026C3321 },
         { .reg = 0x00009888, .val = 0x046C342F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C2000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x06604000 },
         { .reg = 0x00009888, .val = 0x0C630044 },
         { .reg = 0x00009888, .val = 0x10630000 },
         { .reg = 0x00009888, .val = 0x06630000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00AA },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__l3_3__avg_gpu_core_frequency__max,kblgt3__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt3__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt3__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt3__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt3__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt3__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt3__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt3__l3_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt3__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt3__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt3__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt3__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt3__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt3__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt3__l3_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt3__l3_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt3__l3_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt3__l3_3__slm_bytes_read__max,kblgt3__l3_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt3__l3_3__slm_bytes_written__max,kblgt3__l3_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt3__l3_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt3__l3_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt3__l3_3__l3_shader_throughput__max,kblgt3__l3_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt3__l3_3__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 253, 240, percentage_max_float,kblgt3__l3_3__l30_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 256, 244, percentage_max_float,kblgt3__l3_3__l30_bank3_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,kblgt3__l3_3__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "52c646ca-52da-4853-877e-8645e73ed330";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x102F3800 },
         { .reg = 0x00009888, .val = 0x144D0500 },
         { .reg = 0x00009888, .val = 0x120D03C0 },
         { .reg = 0x00009888, .val = 0x140D03CF },
         { .reg = 0x00009888, .val = 0x0C0F0004 },
         { .reg = 0x00009888, .val = 0x0C4E4000 },
         { .reg = 0x00009888, .val = 0x042F0480 },
         { .reg = 0x00009888, .val = 0x082F0000 },
         { .reg = 0x00009888, .val = 0x022F0000 },
         { .reg = 0x00009888, .val = 0x0A4C0090 },
         { .reg = 0x00009888, .val = 0x064D0027 },
         { .reg = 0x00009888, .val = 0x004D0000 },
         { .reg = 0x00009888, .val = 0x000D0D40 },
         { .reg = 0x00009888, .val = 0x020D803F },
         { .reg = 0x00009888, .val = 0x040D8023 },
         { .reg = 0x00009888, .val = 0x100D0000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020F0010 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0050 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41901400 },
         { .reg = 0x00009888, .val = 0x43901485 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000EFFF },
         { .reg = 0x00002778, .val = 0x00006000 },
         { .reg = 0x0000277C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt3__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt3__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt3__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt3__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt3__rasterizer_and_pixel_backend__slm_bytes_read__max,kblgt3__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt3__rasterizer_and_pixel_backend__slm_bytes_written__max,kblgt3__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt3__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt3__rasterizer_and_pixel_backend__l3_shader_throughput__max,kblgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt3__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 240, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 244, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 248, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 252, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 256, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,kblgt3__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler";
   query->symbol_name = "Sampler";
   query->guid = "c4bb682f-677c-4875-990b-005230be87b4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x14152C00 },
         { .reg = 0x00009888, .val = 0x16150005 },
         { .reg = 0x00009888, .val = 0x121600A0 },
         { .reg = 0x00009888, .val = 0x14352C00 },
         { .reg = 0x00009888, .val = 0x16350005 },
         { .reg = 0x00009888, .val = 0x123600A0 },
         { .reg = 0x00009888, .val = 0x14552C00 },
         { .reg = 0x00009888, .val = 0x16550005 },
         { .reg = 0x00009888, .val = 0x125600A0 },
         { .reg = 0x00009888, .val = 0x062F6000 },
         { .reg = 0x00009888, .val = 0x022F2000 },
         { .reg = 0x00009888, .val = 0x0C4C0050 },
         { .reg = 0x00009888, .val = 0x0A4C0010 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0350 },
         { .reg = 0x00009888, .val = 0x0C0FB000 },
         { .reg = 0x00009888, .val = 0x0E0F00DA },
         { .reg = 0x00009888, .val = 0x182C0028 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x022DC000 },
         { .reg = 0x00009888, .val = 0x042D4000 },
         { .reg = 0x00009888, .val = 0x0C138000 },
         { .reg = 0x00009888, .val = 0x0E132000 },
         { .reg = 0x00009888, .val = 0x0413C000 },
         { .reg = 0x00009888, .val = 0x1C140018 },
         { .reg = 0x00009888, .val = 0x0C157000 },
         { .reg = 0x00009888, .val = 0x0E150078 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x04162180 },
         { .reg = 0x00009888, .val = 0x02160000 },
         { .reg = 0x00009888, .val = 0x04174000 },
         { .reg = 0x00009888, .val = 0x0233A000 },
         { .reg = 0x00009888, .val = 0x04333000 },
         { .reg = 0x00009888, .val = 0x14348000 },
         { .reg = 0x00009888, .val = 0x16348000 },
         { .reg = 0x00009888, .val = 0x02357870 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x04360043 },
         { .reg = 0x00009888, .val = 0x02360000 },
         { .reg = 0x00009888, .val = 0x04371000 },
         { .reg = 0x00009888, .val = 0x0E538000 },
         { .reg = 0x00009888, .val = 0x00538000 },
         { .reg = 0x00009888, .val = 0x06533000 },
         { .reg = 0x00009888, .val = 0x1C540020 },
         { .reg = 0x00009888, .val = 0x12548000 },
         { .reg = 0x00009888, .val = 0x0E557000 },
         { .reg = 0x00009888, .val = 0x00557800 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x06560043 },
         { .reg = 0x00009888, .val = 0x02560000 },
         { .reg = 0x00009888, .val = 0x06571000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900060 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900060 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__sampler__avg_gpu_core_frequency__max,kblgt3__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__sampler__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__sampler__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__sampler__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__sampler__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__sampler__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__sampler__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__sampler__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__sampler__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__sampler__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__sampler__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt3__sampler__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt3__sampler__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt3__sampler__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt3__sampler__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt3__sampler__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt3__sampler__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt3__sampler__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt3__sampler__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt3__sampler__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt3__sampler__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt3__sampler__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt3__sampler__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt3__sampler__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt3__sampler__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt3__sampler__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt3__sampler__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt3__sampler__slm_bytes_read__max,kblgt3__sampler__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt3__sampler__slm_bytes_written__max,kblgt3__sampler__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt3__sampler__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt3__sampler__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt3__sampler__l3_shader_throughput__max,kblgt3__sampler__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt3__sampler__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,kblgt3__sampler__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,kblgt3__sampler__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,kblgt3__sampler__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,kblgt3__sampler__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,kblgt3__sampler__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,kblgt3__sampler__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,kblgt3__sampler__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "ade8521b-5e72-45d4-8c25-d9f0da774899";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12120000 },
         { .reg = 0x00009888, .val = 0x12320000 },
         { .reg = 0x00009888, .val = 0x12520000 },
         { .reg = 0x00009888, .val = 0x002F8000 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0015 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F03A0 },
         { .reg = 0x00009888, .val = 0x0C0FF000 },
         { .reg = 0x00009888, .val = 0x0E0F0095 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2D8000 },
         { .reg = 0x00009888, .val = 0x0E2D4000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x02108000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x02118000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x02121880 },
         { .reg = 0x00009888, .val = 0x041219B5 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x02134000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x0C308000 },
         { .reg = 0x00009888, .val = 0x0E304000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x0C318000 },
         { .reg = 0x00009888, .val = 0x0E314000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x0C321A80 },
         { .reg = 0x00009888, .val = 0x0E320033 },
         { .reg = 0x00009888, .val = 0x06320031 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x0C334000 },
         { .reg = 0x00009888, .val = 0x0E331000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0E508000 },
         { .reg = 0x00009888, .val = 0x00508000 },
         { .reg = 0x00009888, .val = 0x02504000 },
         { .reg = 0x00009888, .val = 0x0E518000 },
         { .reg = 0x00009888, .val = 0x00518000 },
         { .reg = 0x00009888, .val = 0x02514000 },
         { .reg = 0x00009888, .val = 0x0E521880 },
         { .reg = 0x00009888, .val = 0x00521A80 },
         { .reg = 0x00009888, .val = 0x02520033 },
         { .reg = 0x00009888, .val = 0x0E534000 },
         { .reg = 0x00009888, .val = 0x00534000 },
         { .reg = 0x00009888, .val = 0x02531000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900062 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x00007FFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x00009FFF },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000EFFF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000F3FF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FDFF },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__tdl_1__avg_gpu_core_frequency__max,kblgt3__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt3__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt3__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt3__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt3__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt3__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt3__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt3__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt3__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt3__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt3__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt3__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt3__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt3__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt3__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt3__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt3__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt3__tdl_1__slm_bytes_read__max,kblgt3__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt3__tdl_1__slm_bytes_written__max,kblgt3__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt3__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt3__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt3__tdl_1__l3_shader_throughput__max,kblgt3__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt3__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 240, percentage_max_float,kblgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 244, percentage_max_float,kblgt3__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 248, percentage_max_float,kblgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 252, percentage_max_float,kblgt3__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 256, percentage_max_float,kblgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 260, percentage_max_float,kblgt3__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,kblgt3__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "9df2815d-4e9e-417f-bde1-3788dc6e1ea1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12124D60 },
         { .reg = 0x00009888, .val = 0x12322E60 },
         { .reg = 0x00009888, .val = 0x12524D60 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0014 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0FE000 },
         { .reg = 0x00009888, .val = 0x0E0F0097 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x002D8000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x04121FB7 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x00308000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x00318000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x00321B80 },
         { .reg = 0x00009888, .val = 0x0632003F },
         { .reg = 0x00009888, .val = 0x00334000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0250C000 },
         { .reg = 0x00009888, .val = 0x0251C000 },
         { .reg = 0x00009888, .val = 0x02521FB7 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x02535000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900063 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__tdl_2__avg_gpu_core_frequency__max,kblgt3__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,kblgt3__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,kblgt3__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,kblgt3__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,kblgt3__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,kblgt3__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,kblgt3__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,kblgt3__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,kblgt3__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,kblgt3__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,kblgt3__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,kblgt3__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,kblgt3__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,kblgt3__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,kblgt3__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,kblgt3__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,kblgt3__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,kblgt3__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,kblgt3__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,kblgt3__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, kblgt3__tdl_2__slm_bytes_read__max,kblgt3__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, kblgt3__tdl_2__slm_bytes_written__max,kblgt3__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,kblgt3__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,kblgt3__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, kblgt3__tdl_2__l3_shader_throughput__max,kblgt3__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,kblgt3__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 240, percentage_max_float,kblgt3__tdl_2__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 244, percentage_max_float,kblgt3__tdl_2__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 248, percentage_max_float,kblgt3__tdl_2__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 252, percentage_max_float,kblgt3__tdl_2__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 256, percentage_max_float,kblgt3__tdl_2__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 260, percentage_max_float,kblgt3__tdl_2__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,kblgt3__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "efc497ac-884e-4ee4-a4a8-15fba22aaf21";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x121203E0 },
         { .reg = 0x00009888, .val = 0x123203E0 },
         { .reg = 0x00009888, .val = 0x125203E0 },
         { .reg = 0x00009888, .val = 0x129203E0 },
         { .reg = 0x00009888, .val = 0x12B203E0 },
         { .reg = 0x00009888, .val = 0x12D203E0 },
         { .reg = 0x00009888, .val = 0x024EC000 },
         { .reg = 0x00009888, .val = 0x044EC000 },
         { .reg = 0x00009888, .val = 0x064EC000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C0042 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F006D },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x042D8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06114000 },
         { .reg = 0x00009888, .val = 0x06120033 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x04308000 },
         { .reg = 0x00009888, .val = 0x04318000 },
         { .reg = 0x00009888, .val = 0x04321980 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x04334000 },
         { .reg = 0x00009888, .val = 0x04504000 },
         { .reg = 0x00009888, .val = 0x04514000 },
         { .reg = 0x00009888, .val = 0x04520033 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x04531000 },
         { .reg = 0x00009888, .val = 0x00AF8000 },
         { .reg = 0x00009888, .val = 0x0ACC0001 },
         { .reg = 0x00009888, .val = 0x008D8000 },
         { .reg = 0x00009888, .val = 0x028DA000 },
         { .reg = 0x00009888, .val = 0x0C8FB000 },
         { .reg = 0x00009888, .val = 0x0E8F0001 },
         { .reg = 0x00009888, .val = 0x06AC8000 },
         { .reg = 0x00009888, .val = 0x02AD4000 },
         { .reg = 0x00009888, .val = 0x02908000 },
         { .reg = 0x00009888, .val = 0x02918000 },
         { .reg = 0x00009888, .val = 0x02921980 },
         { .reg = 0x00009888, .val = 0x00920000 },
         { .reg = 0x00009888, .val = 0x02934000 },
         { .reg = 0x00009888, .val = 0x02B04000 },
         { .reg = 0x00009888, .val = 0x02B14000 },
         { .reg = 0x00009888, .val = 0x02B20033 },
         { .reg = 0x00009888, .val = 0x00B20000 },
         { .reg = 0x00009888, .val = 0x02B31000 },
         { .reg = 0x00009888, .val = 0x00D08000 },
         { .reg = 0x00009888, .val = 0x00D18000 },
         { .reg = 0x00009888, .val = 0x00D21980 },
         { .reg = 0x00009888, .val = 0x00D34000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900002 },
         { .reg = 0x00009888, .val = 0x53900420 },
         { .reg = 0x00009888, .val = 0x459000A1 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__compute_extra__avg_gpu_core_frequency__max,kblgt3__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,kblgt3__compute_extra__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 307, 28, percentage_max_float,kblgt3__compute_extra__fpu1_active_adjusted__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_vme_pipe_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Media Vme Pipe metrics set";
   query->symbol_name = "VMEPipe";
   query->guid = "bfd9764d-2c5b-4c16-bfc1-89de3ca10917";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A5800 },
         { .reg = 0x00009888, .val = 0x161A00C0 },
         { .reg = 0x00009888, .val = 0x12180240 },
         { .reg = 0x00009888, .val = 0x14180002 },
         { .reg = 0x00009888, .val = 0x149A5800 },
         { .reg = 0x00009888, .val = 0x169A00C0 },
         { .reg = 0x00009888, .val = 0x12980240 },
         { .reg = 0x00009888, .val = 0x14980002 },
         { .reg = 0x00009888, .val = 0x1A4E3FC0 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x022F8000 },
         { .reg = 0x00009888, .val = 0x042F3000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C9500 },
         { .reg = 0x00009888, .val = 0x0C4C002A },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0015 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C000A },
         { .reg = 0x00009888, .val = 0x04193000 },
         { .reg = 0x00009888, .val = 0x081A28C1 },
         { .reg = 0x00009888, .val = 0x001A0000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x0613C000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x00172000 },
         { .reg = 0x00009888, .val = 0x06178000 },
         { .reg = 0x00009888, .val = 0x0817A000 },
         { .reg = 0x00009888, .val = 0x00180037 },
         { .reg = 0x00009888, .val = 0x06180940 },
         { .reg = 0x00009888, .val = 0x08180000 },
         { .reg = 0x00009888, .val = 0x02180000 },
         { .reg = 0x00009888, .val = 0x04183000 },
         { .reg = 0x00009888, .val = 0x04AFC000 },
         { .reg = 0x00009888, .val = 0x06AF3000 },
         { .reg = 0x00009888, .val = 0x0ACC4000 },
         { .reg = 0x00009888, .val = 0x0CCC0015 },
         { .reg = 0x00009888, .val = 0x0A8DA000 },
         { .reg = 0x00009888, .val = 0x0C8DA000 },
         { .reg = 0x00009888, .val = 0x0E8F4000 },
         { .reg = 0x00009888, .val = 0x108F0015 },
         { .reg = 0x00009888, .val = 0x16ACA000 },
         { .reg = 0x00009888, .val = 0x18AC000A },
         { .reg = 0x00009888, .val = 0x06993000 },
         { .reg = 0x00009888, .val = 0x0C9A28C1 },
         { .reg = 0x00009888, .val = 0x009A0000 },
         { .reg = 0x00009888, .val = 0x0A93F000 },
         { .reg = 0x00009888, .val = 0x0C93F000 },
         { .reg = 0x00009888, .val = 0x0A97A000 },
         { .reg = 0x00009888, .val = 0x0C97A000 },
         { .reg = 0x00009888, .val = 0x0A980977 },
         { .reg = 0x00009888, .val = 0x08980000 },
         { .reg = 0x00009888, .val = 0x04980000 },
         { .reg = 0x00009888, .val = 0x06983000 },
         { .reg = 0x00009888, .val = 0x119000FF },
         { .reg = 0x00009888, .val = 0x51900040 },
         { .reg = 0x00009888, .val = 0x41900020 },
         { .reg = 0x00009888, .val = 0x55900004 },
         { .reg = 0x00009888, .val = 0x45900400 },
         { .reg = 0x00009888, .val = 0x479008A5 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900002 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00100030 },
         { .reg = 0x00002774, .val = 0x0000FFF9 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFFC },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFF3 },
         { .reg = 0x00002788, .val = 0x00100180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__vme_pipe__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__vme_pipe__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__vme_pipe__avg_gpu_core_frequency__max,kblgt3__vme_pipe__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__vme_pipe__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,kblgt3__vme_pipe__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 40, percentage_max_float,kblgt3__vme_pipe__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 44, percentage_max_float,kblgt3__vme_pipe__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 48, percentage_max_float,kblgt3__vme_pipe__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 52, percentage_max_float,kblgt3__vme_pipe__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 308, 56, percentage_max_float,kblgt3__vme_pipe__vme_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Gpu Rings Busyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "b55ecba1-2aa9-422e-89ff-b9e30f03d447";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x19D05800 },
         { .reg = 0x00009888, .val = 0x13805800 },
         { .reg = 0x00009888, .val = 0x05962C25 },
         { .reg = 0x00009888, .val = 0x19950016 },
         { .reg = 0x00009888, .val = 0x19C05800 },
         { .reg = 0x00009888, .val = 0x05D00085 },
         { .reg = 0x00009888, .val = 0x25D00000 },
         { .reg = 0x00009888, .val = 0x09D54000 },
         { .reg = 0x00009888, .val = 0x07800035 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x1D810400 },
         { .reg = 0x00009888, .val = 0x21960000 },
         { .reg = 0x00009888, .val = 0x0996C000 },
         { .reg = 0x00009888, .val = 0x0B964000 },
         { .reg = 0x00009888, .val = 0x19938000 },
         { .reg = 0x00009888, .val = 0x1B930068 },
         { .reg = 0x00009888, .val = 0x15948000 },
         { .reg = 0x00009888, .val = 0x1B94000C },
         { .reg = 0x00009888, .val = 0x03957500 },
         { .reg = 0x00009888, .val = 0x1D950000 },
         { .reg = 0x00009888, .val = 0x17950000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x07928000 },
         { .reg = 0x00009888, .val = 0x03988000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x09978000 },
         { .reg = 0x00009888, .val = 0x05C08500 },
         { .reg = 0x00009888, .val = 0x25C00000 },
         { .reg = 0x00009888, .val = 0x1BC00000 },
         { .reg = 0x00009888, .val = 0x0BC54000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900463 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0007C000 },
         { .reg = 0x00002774, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__gpu_busyness__avg_gpu_core_frequency__max,kblgt3__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 309, 24, percentage_max_float,kblgt3__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 28, percentage_max_float,kblgt3__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 32, percentage_max_float,kblgt3__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 312, 36, percentage_max_float,kblgt3__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 40, percentage_max_float,kblgt3__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 44, percentage_max_float,kblgt3__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "bb3344bf-2551-40f7-b75f-cbf29e4195f7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810000 },
         { .reg = 0x00009888, .val = 0x07810013 },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930040 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__test_oa__avg_gpu_core_frequency__max,kblgt3__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,kblgt3__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,kblgt3__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,kblgt3__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,kblgt3__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,kblgt3__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,kblgt3__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,kblgt3__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,kblgt3__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,kblgt3__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_pma__stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "PMA_Stall";
   query->guid = "85bc2e4f-2563-4388-921b-dc0dad879cf3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x122D3080 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0800 },
         { .reg = 0x00009888, .val = 0x0E0FAA00 },
         { .reg = 0x00009888, .val = 0x100F0002 },
         { .reg = 0x00009888, .val = 0x002D0025 },
         { .reg = 0x00009888, .val = 0x062D1300 },
         { .reg = 0x00009888, .val = 0x082D16A4 },
         { .reg = 0x00009888, .val = 0x0A2D162E },
         { .reg = 0x00009888, .val = 0x102D0000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00E00021 },
         { .reg = 0x00002774, .val = 0x0007FFF8 },
         { .reg = 0x00002778, .val = 0x07000101 },
         { .reg = 0x0000277C, .val = 0x0038FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__pma__stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__pma__stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__pma__stall__avg_gpu_core_frequency__max,kblgt3__pma__stall__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 24, percentage_max_float,kblgt3__pma__stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
kblgt3_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "8d6d28f5-f699-4eec-89f7-216956bf2ed5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00051050 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00061060 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,kblgt3__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,kblgt3__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, kblgt3__async_compute__avg_gpu_core_frequency__max,kblgt3__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,kblgt3__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,kblgt3__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,kblgt3__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,kblgt3__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,kblgt3__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,kblgt3__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,kblgt3__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 150, 80, percentage_max_float,kblgt3__async_compute__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 124, 84, percentage_max_float,kblgt3__async_compute__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 127, 88, percentage_max_float,kblgt3__async_compute__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 331, 92, percentage_max_float,kblgt3__async_compute__cs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,kblgt3__async_compute__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 125, 100, percentage_max_float,kblgt3__async_compute__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,kblgt3__async_compute__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 332, 108, percentage_max_float,kblgt3__async_compute__cs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 154, 112, percentage_max_float,kblgt3__async_compute__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 10, 116, percentage_max_float,kblgt3__async_compute__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 120, percentage_max_float,kblgt3__async_compute__eu_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_kblgt3(struct intel_perf_config *perf)
{
   kblgt3_register_render_basic_counter_query(perf);
   kblgt3_register_compute_basic_counter_query(perf);
   kblgt3_register_render_pipe_profile_counter_query(perf);
   kblgt3_register_memory_reads_counter_query(perf);
   kblgt3_register_memory_writes_counter_query(perf);
   kblgt3_register_compute_extended_counter_query(perf);
   kblgt3_register_compute_l3_cache_counter_query(perf);
   kblgt3_register_hdc_and_sf_counter_query(perf);
   kblgt3_register_l3_1_counter_query(perf);
   kblgt3_register_l3_2_counter_query(perf);
   kblgt3_register_l3_3_counter_query(perf);
   kblgt3_register_rasterizer_and_pixel_backend_counter_query(perf);
   kblgt3_register_sampler_counter_query(perf);
   kblgt3_register_tdl_1_counter_query(perf);
   kblgt3_register_tdl_2_counter_query(perf);
   kblgt3_register_compute_extra_counter_query(perf);
   kblgt3_register_vme_pipe_counter_query(perf);
   kblgt3_register_gpu_busyness_counter_query(perf);
   kblgt3_register_test_oa_counter_query(perf);
   kblgt3_register_pma__stall_counter_query(perf);
   kblgt3_register_async_compute_counter_query(perf);
}


static void
cflgt2_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "7fa796a4-0c7a-4201-afc6-cff0b2f528a2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C01E0 },
         { .reg = 0x00009888, .val = 0x12170280 },
         { .reg = 0x00009888, .val = 0x12370280 },
         { .reg = 0x00009888, .val = 0x11930317 },
         { .reg = 0x00009888, .val = 0x159303DF },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x1A4E0080 },
         { .reg = 0x00009888, .val = 0x0A6C0053 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x0A1B4000 },
         { .reg = 0x00009888, .val = 0x1C1C0001 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x042F1000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C8400 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0D2000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F6600 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x162C2200 },
         { .reg = 0x00009888, .val = 0x062D8000 },
         { .reg = 0x00009888, .val = 0x082D8000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x08133000 },
         { .reg = 0x00009888, .val = 0x00170020 },
         { .reg = 0x00009888, .val = 0x08170021 },
         { .reg = 0x00009888, .val = 0x10170000 },
         { .reg = 0x00009888, .val = 0x0633C000 },
         { .reg = 0x00009888, .val = 0x0833C000 },
         { .reg = 0x00009888, .val = 0x06370800 },
         { .reg = 0x00009888, .val = 0x08370840 },
         { .reg = 0x00009888, .val = 0x10370000 },
         { .reg = 0x00009888, .val = 0x0D933031 },
         { .reg = 0x00009888, .val = 0x0F933E3F },
         { .reg = 0x00009888, .val = 0x01933D00 },
         { .reg = 0x00009888, .val = 0x0393073C },
         { .reg = 0x00009888, .val = 0x0593000E },
         { .reg = 0x00009888, .val = 0x1D930000 },
         { .reg = 0x00009888, .val = 0x19930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x2B908000 },
         { .reg = 0x00009888, .val = 0x2D908000 },
         { .reg = 0x00009888, .val = 0x2F908000 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x15908000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190001F },
         { .reg = 0x00009888, .val = 0x51904400 },
         { .reg = 0x00009888, .val = 0x41900020 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C21 },
         { .reg = 0x00009888, .val = 0x47900061 },
         { .reg = 0x00009888, .val = 0x57904440 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900004 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x53904444 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__render_basic__avg_gpu_core_frequency__max,cflgt2__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,cflgt2__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,cflgt2__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,cflgt2__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,cflgt2__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,cflgt2__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,cflgt2__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,cflgt2__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,cflgt2__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,cflgt2__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,cflgt2__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,cflgt2__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,cflgt2__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,cflgt2__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,cflgt2__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,cflgt2__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,cflgt2__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,cflgt2__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,cflgt2__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,cflgt2__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,cflgt2__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,cflgt2__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,cflgt2__render_basic__sampler1_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,cflgt2__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,cflgt2__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,cflgt2__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,cflgt2__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,cflgt2__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,cflgt2__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,cflgt2__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,cflgt2__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,cflgt2__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 208, NULL,cflgt2__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, cflgt2__render_basic__slm_bytes_read__max,cflgt2__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, cflgt2__render_basic__slm_bytes_written__max,cflgt2__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,cflgt2__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,cflgt2__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,cflgt2__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,cflgt2__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, cflgt2__render_basic__l3_sampler_throughput__max,cflgt2__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, cflgt2__render_basic__l3_shader_throughput__max,cflgt2__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,cflgt2__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, cflgt2__render_basic__gti_vf_throughput__max,cflgt2__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, cflgt2__render_basic__gti_depth_throughput__max,cflgt2__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, cflgt2__render_basic__gti_rcc_throughput__max,cflgt2__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, cflgt2__render_basic__gti_l3_throughput__max,cflgt2__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, cflgt2__render_basic__gti_hdc_lookups_throughput__max,cflgt2__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, cflgt2__render_basic__gti_read_throughput__max,cflgt2__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, cflgt2__render_basic__gti_write_throughput__max,cflgt2__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,cflgt2__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "a4985100-5f76-4822-8ca7-67908cb26274";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x124F1C00 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x1A4E0820 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x064F0900 },
         { .reg = 0x00009888, .val = 0x084F0032 },
         { .reg = 0x00009888, .val = 0x0A4F1891 },
         { .reg = 0x00009888, .val = 0x0C4F0E00 },
         { .reg = 0x00009888, .val = 0x0E4F003C },
         { .reg = 0x00009888, .val = 0x004F0D80 },
         { .reg = 0x00009888, .val = 0x024F003B },
         { .reg = 0x00009888, .val = 0x006C0002 },
         { .reg = 0x00009888, .val = 0x086C0100 },
         { .reg = 0x00009888, .val = 0x0C6C000C },
         { .reg = 0x00009888, .val = 0x0E6C0B00 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x081B8000 },
         { .reg = 0x00009888, .val = 0x0C1B4000 },
         { .reg = 0x00009888, .val = 0x0E1B8000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1C8000 },
         { .reg = 0x00009888, .val = 0x1C1C0024 },
         { .reg = 0x00009888, .val = 0x065B8000 },
         { .reg = 0x00009888, .val = 0x085B4000 },
         { .reg = 0x00009888, .val = 0x0A5BC000 },
         { .reg = 0x00009888, .val = 0x0C5B8000 },
         { .reg = 0x00009888, .val = 0x0E5B4000 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025B4000 },
         { .reg = 0x00009888, .val = 0x1A5C6000 },
         { .reg = 0x00009888, .val = 0x1C5C001B },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2000 },
         { .reg = 0x00009888, .val = 0x0C4C0208 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2CC000 },
         { .reg = 0x00009888, .val = 0x162CFB00 },
         { .reg = 0x00009888, .val = 0x182C00BE },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x19900157 },
         { .reg = 0x00009888, .val = 0x1B900158 },
         { .reg = 0x00009888, .val = 0x1D900105 },
         { .reg = 0x00009888, .val = 0x1F900103 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x11900FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900821 },
         { .reg = 0x00009888, .val = 0x47900802 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900802 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900002 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900422 },
         { .reg = 0x00009888, .val = 0x53904444 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__compute_basic__avg_gpu_core_frequency__max,cflgt2__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,cflgt2__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,cflgt2__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, cflgt2__compute_basic__eu_avg_ipc_rate__max,cflgt2__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,cflgt2__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,cflgt2__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,cflgt2__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,cflgt2__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,cflgt2__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,cflgt2__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,cflgt2__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,cflgt2__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,cflgt2__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,cflgt2__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,cflgt2__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, cflgt2__compute_basic__slm_bytes_read__max,cflgt2__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, cflgt2__compute_basic__slm_bytes_written__max,cflgt2__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,cflgt2__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,cflgt2__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, cflgt2__compute_basic__l3_shader_throughput__max,cflgt2__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,cflgt2__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, cflgt2__compute_basic__typed_bytes_read__max,cflgt2__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, cflgt2__compute_basic__typed_bytes_written__max,cflgt2__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, cflgt2__compute_basic__untyped_bytes_read__max,cflgt2__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, cflgt2__compute_basic__untyped_bytes_written__max,cflgt2__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, cflgt2__compute_basic__gti_read_throughput__max,cflgt2__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, cflgt2__compute_basic__gti_write_throughput__max,cflgt2__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "2221e4d5-ed7b-445e-b2cc-3de1b97f4d42";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x0C0E001F },
         { .reg = 0x00009888, .val = 0x0A0F0000 },
         { .reg = 0x00009888, .val = 0x10116800 },
         { .reg = 0x00009888, .val = 0x178A03E0 },
         { .reg = 0x00009888, .val = 0x11824C00 },
         { .reg = 0x00009888, .val = 0x11830020 },
         { .reg = 0x00009888, .val = 0x13840020 },
         { .reg = 0x00009888, .val = 0x11850019 },
         { .reg = 0x00009888, .val = 0x11860007 },
         { .reg = 0x00009888, .val = 0x01870C40 },
         { .reg = 0x00009888, .val = 0x17880000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0A4C0040 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020E5400 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x080F0040 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0040 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06110012 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x01898000 },
         { .reg = 0x00009888, .val = 0x0D890100 },
         { .reg = 0x00009888, .val = 0x03898000 },
         { .reg = 0x00009888, .val = 0x09808000 },
         { .reg = 0x00009888, .val = 0x0B808000 },
         { .reg = 0x00009888, .val = 0x0380C000 },
         { .reg = 0x00009888, .val = 0x0F8A0075 },
         { .reg = 0x00009888, .val = 0x1D8A0000 },
         { .reg = 0x00009888, .val = 0x118A8000 },
         { .reg = 0x00009888, .val = 0x1B8A4000 },
         { .reg = 0x00009888, .val = 0x138A8000 },
         { .reg = 0x00009888, .val = 0x1D81A000 },
         { .reg = 0x00009888, .val = 0x15818000 },
         { .reg = 0x00009888, .val = 0x17818000 },
         { .reg = 0x00009888, .val = 0x0B820030 },
         { .reg = 0x00009888, .val = 0x07828000 },
         { .reg = 0x00009888, .val = 0x0D824000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0D830003 },
         { .reg = 0x00009888, .val = 0x0583000C },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x03838000 },
         { .reg = 0x00009888, .val = 0x07838000 },
         { .reg = 0x00009888, .val = 0x0B840980 },
         { .reg = 0x00009888, .val = 0x03844D80 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x09848000 },
         { .reg = 0x00009888, .val = 0x09850080 },
         { .reg = 0x00009888, .val = 0x03850003 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x07860000 },
         { .reg = 0x00009888, .val = 0x0F860400 },
         { .reg = 0x00009888, .val = 0x09870032 },
         { .reg = 0x00009888, .val = 0x01888052 },
         { .reg = 0x00009888, .val = 0x11880000 },
         { .reg = 0x00009888, .val = 0x09884000 },
         { .reg = 0x00009888, .val = 0x1B931001 },
         { .reg = 0x00009888, .val = 0x1D930001 },
         { .reg = 0x00009888, .val = 0x19934000 },
         { .reg = 0x00009888, .val = 0x1B958000 },
         { .reg = 0x00009888, .val = 0x1D950094 },
         { .reg = 0x00009888, .val = 0x19958000 },
         { .reg = 0x00009888, .val = 0x09E58000 },
         { .reg = 0x00009888, .val = 0x0BE58000 },
         { .reg = 0x00009888, .val = 0x03E5C000 },
         { .reg = 0x00009888, .val = 0x0592C000 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D924000 },
         { .reg = 0x00009888, .val = 0x0F924000 },
         { .reg = 0x00009888, .val = 0x11928000 },
         { .reg = 0x00009888, .val = 0x1392C000 },
         { .reg = 0x00009888, .val = 0x09924000 },
         { .reg = 0x00009888, .val = 0x01985000 },
         { .reg = 0x00009888, .val = 0x07988000 },
         { .reg = 0x00009888, .val = 0x09981000 },
         { .reg = 0x00009888, .val = 0x0B982000 },
         { .reg = 0x00009888, .val = 0x0D982000 },
         { .reg = 0x00009888, .val = 0x0F989000 },
         { .reg = 0x00009888, .val = 0x05982000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25908000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29908000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1190C080 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900440 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900400 },
         { .reg = 0x00009888, .val = 0x47900C21 },
         { .reg = 0x00009888, .val = 0x57900400 },
         { .reg = 0x00009888, .val = 0x49900042 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900024 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900841 },
         { .reg = 0x00009888, .val = 0x53900400 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__render_pipe_profile__avg_gpu_core_frequency__max,cflgt2__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,cflgt2__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,cflgt2__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,cflgt2__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,cflgt2__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,cflgt2__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,cflgt2__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,cflgt2__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,cflgt2__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,cflgt2__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, cflgt2__render_pipe_profile__slm_bytes_read__max,cflgt2__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, cflgt2__render_pipe_profile__slm_bytes_written__max,cflgt2__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,cflgt2__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,cflgt2__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, cflgt2__render_pipe_profile__l3_shader_throughput__max,cflgt2__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,cflgt2__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, NULL,cflgt2__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, NULL,cflgt2__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, NULL,cflgt2__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, NULL,cflgt2__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, NULL,cflgt2__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, NULL,cflgt2__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, NULL,cflgt2__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, NULL,cflgt2__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, NULL,cflgt2__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, NULL,cflgt2__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, NULL,cflgt2__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, NULL,cflgt2__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, NULL,cflgt2__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, NULL,cflgt2__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, NULL,cflgt2__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, NULL,cflgt2__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Reads Distribution metrics set";
   query->symbol_name = "MemoryReads";
   query->guid = "82096a90-e2fa-4f38-ac14-562b2496933a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900064 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900150 },
         { .reg = 0x00009888, .val = 0x21900151 },
         { .reg = 0x00009888, .val = 0x23900152 },
         { .reg = 0x00009888, .val = 0x25900153 },
         { .reg = 0x00009888, .val = 0x27900154 },
         { .reg = 0x00009888, .val = 0x29900155 },
         { .reg = 0x00009888, .val = 0x2B900156 },
         { .reg = 0x00009888, .val = 0x2D900157 },
         { .reg = 0x00009888, .val = 0x2F90015F },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__memory_reads__avg_gpu_core_frequency__max,cflgt2__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,cflgt2__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,cflgt2__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,cflgt2__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,cflgt2__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,cflgt2__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,cflgt2__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,cflgt2__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,cflgt2__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,cflgt2__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, cflgt2__memory_reads__slm_bytes_read__max,cflgt2__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, cflgt2__memory_reads__slm_bytes_written__max,cflgt2__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,cflgt2__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,cflgt2__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,cflgt2__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 95, 200, NULL,cflgt2__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 208, NULL,cflgt2__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 216, NULL,cflgt2__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 224, NULL,cflgt2__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 232, NULL,cflgt2__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 240, NULL,cflgt2__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 248, NULL,cflgt2__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 256, NULL,cflgt2__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 264, NULL,cflgt2__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 272, NULL,cflgt2__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 280, NULL,cflgt2__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 288, NULL,cflgt2__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 296, NULL,cflgt2__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 304, NULL,cflgt2__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 312, NULL,cflgt2__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metrics set";
   query->symbol_name = "MemoryWrites";
   query->guid = "9f638880-02e9-4a8d-896a-7670a3bf0d35";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F901000 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900160 },
         { .reg = 0x00009888, .val = 0x21900161 },
         { .reg = 0x00009888, .val = 0x23900162 },
         { .reg = 0x00009888, .val = 0x25900163 },
         { .reg = 0x00009888, .val = 0x27900164 },
         { .reg = 0x00009888, .val = 0x29900165 },
         { .reg = 0x00009888, .val = 0x2B900166 },
         { .reg = 0x00009888, .val = 0x2D900167 },
         { .reg = 0x00009888, .val = 0x2F900150 },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__memory_writes__avg_gpu_core_frequency__max,cflgt2__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,cflgt2__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,cflgt2__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,cflgt2__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,cflgt2__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,cflgt2__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,cflgt2__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,cflgt2__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,cflgt2__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,cflgt2__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, cflgt2__memory_writes__slm_bytes_read__max,cflgt2__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, cflgt2__memory_writes__slm_bytes_written__max,cflgt2__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,cflgt2__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,cflgt2__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, cflgt2__memory_writes__l3_shader_throughput__max,cflgt2__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,cflgt2__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,cflgt2__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,cflgt2__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,cflgt2__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,cflgt2__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,cflgt2__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,cflgt2__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,cflgt2__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,cflgt2__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,cflgt2__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,cflgt2__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,cflgt2__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,cflgt2__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,cflgt2__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,cflgt2__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended set";
   query->symbol_name = "ComputeExtended";
   query->guid = "8d4ad934-7c16-43d5-845a-51067a4c8e2f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x141C8160 },
         { .reg = 0x00009888, .val = 0x161C8015 },
         { .reg = 0x00009888, .val = 0x181C0120 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4EAAA0 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0E6C0B01 },
         { .reg = 0x00009888, .val = 0x006C0200 },
         { .reg = 0x00009888, .val = 0x026C000C },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x001C0041 },
         { .reg = 0x00009888, .val = 0x061C4200 },
         { .reg = 0x00009888, .val = 0x081C4443 },
         { .reg = 0x00009888, .val = 0x0A1C4645 },
         { .reg = 0x00009888, .val = 0x0C1C7647 },
         { .reg = 0x00009888, .val = 0x041C7357 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x1A1C0000 },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4CAA2A },
         { .reg = 0x00009888, .val = 0x0C4C02AA },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5515 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x11907FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900040 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900802 },
         { .reg = 0x00009888, .val = 0x47900842 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900842 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900800 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__compute_extended__avg_gpu_core_frequency__max,cflgt2__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,cflgt2__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,cflgt2__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,cflgt2__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,cflgt2__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,cflgt2__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,cflgt2__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, cflgt2__compute_extended__eu_avg_ipc_rate__max,cflgt2__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,cflgt2__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,cflgt2__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,cflgt2__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,cflgt2__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, cflgt2__compute_extended__slm_bytes_read__max,cflgt2__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, cflgt2__compute_extended__slm_bytes_written__max,cflgt2__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,cflgt2__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,cflgt2__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, cflgt2__compute_extended__l3_shader_throughput__max,cflgt2__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,cflgt2__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,cflgt2__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,cflgt2__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,cflgt2__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,cflgt2__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,cflgt2__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,cflgt2__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,cflgt2__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,cflgt2__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,cflgt2__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,cflgt2__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,cflgt2__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,cflgt2__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,cflgt2__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 232, NULL,cflgt2__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 236, NULL,cflgt2__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 240, NULL,cflgt2__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 244, NULL,cflgt2__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 248, NULL,cflgt2__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 54);

   query->name = "Compute Metrics L3 Cache set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "4389cf07-1424-4963-b2d2-64fcec75406d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C0760 },
         { .reg = 0x00009888, .val = 0x1593001E },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4E8020 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x006C0051 },
         { .reg = 0x00009888, .val = 0x066C5000 },
         { .reg = 0x00009888, .val = 0x086C5C5D },
         { .reg = 0x00009888, .val = 0x0E6C5E5F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x061B8000 },
         { .reg = 0x00009888, .val = 0x081BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1CE000 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2A00 },
         { .reg = 0x00009888, .val = 0x0C4C0280 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F1500 },
         { .reg = 0x00009888, .val = 0x100F0140 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x182C00A0 },
         { .reg = 0x00009888, .val = 0x03933300 },
         { .reg = 0x00009888, .val = 0x05930032 },
         { .reg = 0x00009888, .val = 0x11930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190030F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900021 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x53904444 },
         { .reg = 0x00009888, .val = 0x43900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__compute_l3_cache__avg_gpu_core_frequency__max,cflgt2__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,cflgt2__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,cflgt2__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, cflgt2__compute_l3_cache__eu_avg_ipc_rate__max,cflgt2__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,cflgt2__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,cflgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,cflgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,cflgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,cflgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,cflgt2__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,cflgt2__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,cflgt2__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,cflgt2__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,cflgt2__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,cflgt2__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,cflgt2__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,cflgt2__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,cflgt2__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,cflgt2__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,cflgt2__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,cflgt2__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,cflgt2__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,cflgt2__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, cflgt2__compute_l3_cache__slm_bytes_read__max,cflgt2__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, cflgt2__compute_l3_cache__slm_bytes_written__max,cflgt2__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,cflgt2__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,cflgt2__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 256, NULL,cflgt2__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 264, NULL,cflgt2__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, cflgt2__compute_l3_cache__l3_sampler_throughput__max,cflgt2__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 280, cflgt2__compute_l3_cache__l3_shader_throughput__max,cflgt2__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 288, cflgt2__compute_l3_cache__l3_total_throughput__max,cflgt2__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,cflgt2__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 304, NULL,cflgt2__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 312, NULL,cflgt2__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 320, NULL,cflgt2__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 328, NULL,cflgt2__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 336, NULL,cflgt2__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 344, NULL,cflgt2__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 352, cflgt2__compute_l3_cache__gti_l3_throughput__max,cflgt2__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 360, cflgt2__compute_l3_cache__gti_read_throughput__max,cflgt2__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 368, cflgt2__compute_l3_cache__gti_write_throughput__max,cflgt2__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "ac544b3a-ff78-46ea-9808-ee6fef0978b4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F0232 },
         { .reg = 0x00009888, .val = 0x124F4640 },
         { .reg = 0x00009888, .val = 0x106C0232 },
         { .reg = 0x00009888, .val = 0x11834400 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x004F1880 },
         { .reg = 0x00009888, .val = 0x024F08BB },
         { .reg = 0x00009888, .val = 0x044F001B },
         { .reg = 0x00009888, .val = 0x046C0100 },
         { .reg = 0x00009888, .val = 0x066C000B },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x041B8000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025BC000 },
         { .reg = 0x00009888, .val = 0x045B4000 },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x165C8000 },
         { .reg = 0x00009888, .val = 0x185C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00A0 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x062CC000 },
         { .reg = 0x00009888, .val = 0x082CC000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x0F8305C0 },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x07830000 },
         { .reg = 0x00009888, .val = 0x1D950080 },
         { .reg = 0x00009888, .val = 0x13928000 },
         { .reg = 0x00009888, .val = 0x0F988000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900040 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__hdc_and_sf__avg_gpu_core_frequency__max,cflgt2__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt2__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt2__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt2__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt2__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt2__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt2__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt2__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt2__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt2__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt2__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt2__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt2__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt2__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt2__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt2__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt2__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt2__hdc_and_sf__slm_bytes_read__max,cflgt2__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt2__hdc_and_sf__slm_bytes_written__max,cflgt2__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt2__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt2__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt2__hdc_and_sf__l3_shader_throughput__max,cflgt2__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt2__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,cflgt2__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 244, percentage_max_float,cflgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,cflgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 238, 252, percentage_max_float,cflgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,cflgt2__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "a35c5867-0ab8-4d45-8fc1-eb0906f0eff5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C7B40 },
         { .reg = 0x00009888, .val = 0x166C0020 },
         { .reg = 0x00009888, .val = 0x0A603444 },
         { .reg = 0x00009888, .val = 0x0A613400 },
         { .reg = 0x00009888, .val = 0x1A4EA800 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x0C6C5327 },
         { .reg = 0x00009888, .val = 0x0E6C5425 },
         { .reg = 0x00009888, .val = 0x006C2A00 },
         { .reg = 0x00009888, .val = 0x026C285B },
         { .reg = 0x00009888, .val = 0x046C005C },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0800 },
         { .reg = 0x00009888, .val = 0x0C1BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x1C1C003C },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x10600000 },
         { .reg = 0x00009888, .val = 0x04600000 },
         { .reg = 0x00009888, .val = 0x0C610044 },
         { .reg = 0x00009888, .val = 0x10610000 },
         { .reg = 0x00009888, .val = 0x06610000 },
         { .reg = 0x00009888, .val = 0x0C4C02A8 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0154 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190FFC0 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900420 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900021 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900400 },
         { .reg = 0x00009888, .val = 0x43900421 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__l3_1__avg_gpu_core_frequency__max,cflgt2__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt2__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt2__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt2__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt2__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt2__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt2__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt2__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt2__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt2__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt2__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt2__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt2__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt2__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt2__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt2__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt2__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt2__l3_1__slm_bytes_read__max,cflgt2__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt2__l3_1__slm_bytes_written__max,cflgt2__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt2__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt2__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt2__l3_1__l3_shader_throughput__max,cflgt2__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt2__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,cflgt2__l3_1__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,cflgt2__l3_1__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,cflgt2__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,cflgt2__l3_1__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,cflgt2__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_2";
   query->symbol_name = "L3_2";
   query->guid = "bb4bcce9-2cbb-4818-9e49-67ce2c99cd25";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C02E0 },
         { .reg = 0x00009888, .val = 0x146C0001 },
         { .reg = 0x00009888, .val = 0x0A623400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x026C3324 },
         { .reg = 0x00009888, .val = 0x046C3422 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x06614000 },
         { .reg = 0x00009888, .val = 0x0C620044 },
         { .reg = 0x00009888, .val = 0x10620000 },
         { .reg = 0x00009888, .val = 0x06620000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__l3_2__avg_gpu_core_frequency__max,cflgt2__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt2__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt2__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt2__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt2__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt2__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt2__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt2__l3_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt2__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt2__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt2__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt2__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt2__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt2__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt2__l3_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt2__l3_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt2__l3_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt2__l3_2__slm_bytes_read__max,cflgt2__l3_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt2__l3_2__slm_bytes_written__max,cflgt2__l3_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt2__l3_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt2__l3_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt2__l3_2__l3_shader_throughput__max,cflgt2__l3_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt2__l3_2__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 257, 240, percentage_max_float,cflgt2__l3_2__l30_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 260, 244, percentage_max_float,cflgt2__l3_2__l30_bank2_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,cflgt2__l3_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_3";
   query->symbol_name = "L3_3";
   query->guid = "9e1229f8-d87f-4f44-b067-3544e17195aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C4E80 },
         { .reg = 0x00009888, .val = 0x146C0000 },
         { .reg = 0x00009888, .val = 0x0A633400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x026C3321 },
         { .reg = 0x00009888, .val = 0x046C342F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C2000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x06604000 },
         { .reg = 0x00009888, .val = 0x0C630044 },
         { .reg = 0x00009888, .val = 0x10630000 },
         { .reg = 0x00009888, .val = 0x06630000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00AA },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__l3_3__avg_gpu_core_frequency__max,cflgt2__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt2__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt2__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt2__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt2__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt2__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt2__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt2__l3_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt2__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt2__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt2__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt2__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt2__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt2__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt2__l3_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt2__l3_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt2__l3_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt2__l3_3__slm_bytes_read__max,cflgt2__l3_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt2__l3_3__slm_bytes_written__max,cflgt2__l3_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt2__l3_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt2__l3_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt2__l3_3__l3_shader_throughput__max,cflgt2__l3_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt2__l3_3__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 253, 240, percentage_max_float,cflgt2__l3_3__l30_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 256, 244, percentage_max_float,cflgt2__l3_3__l30_bank3_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,cflgt2__l3_3__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "3e91908a-1c70-4004-b2ab-a10ef14f24f9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x102F3800 },
         { .reg = 0x00009888, .val = 0x144D0500 },
         { .reg = 0x00009888, .val = 0x120D03C0 },
         { .reg = 0x00009888, .val = 0x140D03CF },
         { .reg = 0x00009888, .val = 0x0C0F0004 },
         { .reg = 0x00009888, .val = 0x0C4E4000 },
         { .reg = 0x00009888, .val = 0x042F0480 },
         { .reg = 0x00009888, .val = 0x082F0000 },
         { .reg = 0x00009888, .val = 0x022F0000 },
         { .reg = 0x00009888, .val = 0x0A4C0090 },
         { .reg = 0x00009888, .val = 0x064D0027 },
         { .reg = 0x00009888, .val = 0x004D0000 },
         { .reg = 0x00009888, .val = 0x000D0D40 },
         { .reg = 0x00009888, .val = 0x020D803F },
         { .reg = 0x00009888, .val = 0x040D8023 },
         { .reg = 0x00009888, .val = 0x100D0000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020F0010 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0050 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41901400 },
         { .reg = 0x00009888, .val = 0x43901485 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000EFFF },
         { .reg = 0x00002778, .val = 0x00006000 },
         { .reg = 0x0000277C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt2__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt2__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt2__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt2__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt2__rasterizer_and_pixel_backend__slm_bytes_read__max,cflgt2__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt2__rasterizer_and_pixel_backend__slm_bytes_written__max,cflgt2__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt2__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt2__rasterizer_and_pixel_backend__l3_shader_throughput__max,cflgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt2__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 240, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 244, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 248, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 252, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 256, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,cflgt2__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler";
   query->symbol_name = "Sampler";
   query->guid = "9a6ba957-7955-4a09-a8ce-083030ba3c1f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x14152C00 },
         { .reg = 0x00009888, .val = 0x16150005 },
         { .reg = 0x00009888, .val = 0x121600A0 },
         { .reg = 0x00009888, .val = 0x14352C00 },
         { .reg = 0x00009888, .val = 0x16350005 },
         { .reg = 0x00009888, .val = 0x123600A0 },
         { .reg = 0x00009888, .val = 0x14552C00 },
         { .reg = 0x00009888, .val = 0x16550005 },
         { .reg = 0x00009888, .val = 0x125600A0 },
         { .reg = 0x00009888, .val = 0x062F6000 },
         { .reg = 0x00009888, .val = 0x022F2000 },
         { .reg = 0x00009888, .val = 0x0C4C0050 },
         { .reg = 0x00009888, .val = 0x0A4C0010 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0350 },
         { .reg = 0x00009888, .val = 0x0C0FB000 },
         { .reg = 0x00009888, .val = 0x0E0F00DA },
         { .reg = 0x00009888, .val = 0x182C0028 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x022DC000 },
         { .reg = 0x00009888, .val = 0x042D4000 },
         { .reg = 0x00009888, .val = 0x0C138000 },
         { .reg = 0x00009888, .val = 0x0E132000 },
         { .reg = 0x00009888, .val = 0x0413C000 },
         { .reg = 0x00009888, .val = 0x1C140018 },
         { .reg = 0x00009888, .val = 0x0C157000 },
         { .reg = 0x00009888, .val = 0x0E150078 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x04162180 },
         { .reg = 0x00009888, .val = 0x02160000 },
         { .reg = 0x00009888, .val = 0x04174000 },
         { .reg = 0x00009888, .val = 0x0233A000 },
         { .reg = 0x00009888, .val = 0x04333000 },
         { .reg = 0x00009888, .val = 0x14348000 },
         { .reg = 0x00009888, .val = 0x16348000 },
         { .reg = 0x00009888, .val = 0x02357870 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x04360043 },
         { .reg = 0x00009888, .val = 0x02360000 },
         { .reg = 0x00009888, .val = 0x04371000 },
         { .reg = 0x00009888, .val = 0x0E538000 },
         { .reg = 0x00009888, .val = 0x00538000 },
         { .reg = 0x00009888, .val = 0x06533000 },
         { .reg = 0x00009888, .val = 0x1C540020 },
         { .reg = 0x00009888, .val = 0x12548000 },
         { .reg = 0x00009888, .val = 0x0E557000 },
         { .reg = 0x00009888, .val = 0x00557800 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x06560043 },
         { .reg = 0x00009888, .val = 0x02560000 },
         { .reg = 0x00009888, .val = 0x06571000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900060 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900060 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__sampler__avg_gpu_core_frequency__max,cflgt2__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__sampler__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__sampler__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__sampler__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__sampler__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__sampler__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__sampler__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__sampler__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__sampler__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__sampler__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__sampler__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt2__sampler__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt2__sampler__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt2__sampler__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt2__sampler__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt2__sampler__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt2__sampler__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt2__sampler__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt2__sampler__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt2__sampler__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt2__sampler__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt2__sampler__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt2__sampler__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt2__sampler__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt2__sampler__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt2__sampler__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt2__sampler__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt2__sampler__slm_bytes_read__max,cflgt2__sampler__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt2__sampler__slm_bytes_written__max,cflgt2__sampler__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt2__sampler__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt2__sampler__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt2__sampler__l3_shader_throughput__max,cflgt2__sampler__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt2__sampler__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,cflgt2__sampler__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,cflgt2__sampler__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,cflgt2__sampler__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,cflgt2__sampler__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,cflgt2__sampler__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,cflgt2__sampler__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,cflgt2__sampler__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "c54e7ca3-c60c-4396-ac3d-f9899c9a6ee4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12120000 },
         { .reg = 0x00009888, .val = 0x12320000 },
         { .reg = 0x00009888, .val = 0x12520000 },
         { .reg = 0x00009888, .val = 0x002F8000 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0015 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F03A0 },
         { .reg = 0x00009888, .val = 0x0C0FF000 },
         { .reg = 0x00009888, .val = 0x0E0F0095 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2D8000 },
         { .reg = 0x00009888, .val = 0x0E2D4000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x02108000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x02118000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x02121880 },
         { .reg = 0x00009888, .val = 0x041219B5 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x02134000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x0C308000 },
         { .reg = 0x00009888, .val = 0x0E304000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x0C318000 },
         { .reg = 0x00009888, .val = 0x0E314000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x0C321A80 },
         { .reg = 0x00009888, .val = 0x0E320033 },
         { .reg = 0x00009888, .val = 0x06320031 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x0C334000 },
         { .reg = 0x00009888, .val = 0x0E331000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0E508000 },
         { .reg = 0x00009888, .val = 0x00508000 },
         { .reg = 0x00009888, .val = 0x02504000 },
         { .reg = 0x00009888, .val = 0x0E518000 },
         { .reg = 0x00009888, .val = 0x00518000 },
         { .reg = 0x00009888, .val = 0x02514000 },
         { .reg = 0x00009888, .val = 0x0E521880 },
         { .reg = 0x00009888, .val = 0x00521A80 },
         { .reg = 0x00009888, .val = 0x02520033 },
         { .reg = 0x00009888, .val = 0x0E534000 },
         { .reg = 0x00009888, .val = 0x00534000 },
         { .reg = 0x00009888, .val = 0x02531000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900062 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x00007FFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x00009FFF },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000EFFF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000F3FF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FDFF },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__tdl_1__avg_gpu_core_frequency__max,cflgt2__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt2__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt2__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt2__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt2__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt2__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt2__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt2__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt2__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt2__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt2__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt2__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt2__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt2__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt2__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt2__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt2__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt2__tdl_1__slm_bytes_read__max,cflgt2__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt2__tdl_1__slm_bytes_written__max,cflgt2__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt2__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt2__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt2__tdl_1__l3_shader_throughput__max,cflgt2__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt2__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 240, percentage_max_float,cflgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 244, percentage_max_float,cflgt2__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 248, percentage_max_float,cflgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 252, percentage_max_float,cflgt2__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 256, percentage_max_float,cflgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 260, percentage_max_float,cflgt2__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,cflgt2__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "e438cd5d-1da7-46c6-9823-4780f370d11d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12124D60 },
         { .reg = 0x00009888, .val = 0x12322E60 },
         { .reg = 0x00009888, .val = 0x12524D60 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0014 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0FE000 },
         { .reg = 0x00009888, .val = 0x0E0F0097 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x002D8000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x04121FB7 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x00308000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x00318000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x00321B80 },
         { .reg = 0x00009888, .val = 0x0632003F },
         { .reg = 0x00009888, .val = 0x00334000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0250C000 },
         { .reg = 0x00009888, .val = 0x0251C000 },
         { .reg = 0x00009888, .val = 0x02521FB7 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x02535000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900063 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__tdl_2__avg_gpu_core_frequency__max,cflgt2__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt2__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt2__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt2__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt2__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt2__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt2__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt2__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt2__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt2__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt2__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt2__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt2__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt2__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt2__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt2__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt2__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt2__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt2__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt2__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt2__tdl_2__slm_bytes_read__max,cflgt2__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt2__tdl_2__slm_bytes_written__max,cflgt2__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt2__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt2__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt2__tdl_2__l3_shader_throughput__max,cflgt2__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt2__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 240, percentage_max_float,cflgt2__tdl_2__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 244, percentage_max_float,cflgt2__tdl_2__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 248, percentage_max_float,cflgt2__tdl_2__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 252, percentage_max_float,cflgt2__tdl_2__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 256, percentage_max_float,cflgt2__tdl_2__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 260, percentage_max_float,cflgt2__tdl_2__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,cflgt2__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "5f679fb0-909e-4c0e-b4b2-8e801f83e71b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x121203E0 },
         { .reg = 0x00009888, .val = 0x123203E0 },
         { .reg = 0x00009888, .val = 0x125203E0 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0A4C0040 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0E0F006C },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x042D8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06114000 },
         { .reg = 0x00009888, .val = 0x06120033 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x04308000 },
         { .reg = 0x00009888, .val = 0x04318000 },
         { .reg = 0x00009888, .val = 0x04321980 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x04334000 },
         { .reg = 0x00009888, .val = 0x04504000 },
         { .reg = 0x00009888, .val = 0x04514000 },
         { .reg = 0x00009888, .val = 0x04520033 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x04531000 },
         { .reg = 0x00009888, .val = 0x1190E000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900C00 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00001000 },
         { .reg = 0x0000E558, .val = 0x00003002 },
         { .reg = 0x0000E658, .val = 0x00005004 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00050012 },
         { .reg = 0x0000E55C, .val = 0x00052051 },
         { .reg = 0x0000E65C, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__compute_extra__avg_gpu_core_frequency__max,cflgt2__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,cflgt2__compute_extra__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 307, 28, percentage_max_float,cflgt2__compute_extra__fpu1_active_adjusted__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_vme_pipe_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Media Vme Pipe metrics set";
   query->symbol_name = "VMEPipe";
   query->guid = "0d09ba9a-1d1c-457d-83e2-74ac448014d6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A5800 },
         { .reg = 0x00009888, .val = 0x161A00C0 },
         { .reg = 0x00009888, .val = 0x12180240 },
         { .reg = 0x00009888, .val = 0x14180002 },
         { .reg = 0x00009888, .val = 0x143A5800 },
         { .reg = 0x00009888, .val = 0x163A00C0 },
         { .reg = 0x00009888, .val = 0x12380240 },
         { .reg = 0x00009888, .val = 0x14380002 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x022F8000 },
         { .reg = 0x00009888, .val = 0x042F3000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C1500 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F9500 },
         { .reg = 0x00009888, .val = 0x100F002A },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x0A2DC000 },
         { .reg = 0x00009888, .val = 0x0C2DC000 },
         { .reg = 0x00009888, .val = 0x04193000 },
         { .reg = 0x00009888, .val = 0x081A28C1 },
         { .reg = 0x00009888, .val = 0x001A0000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x0613C000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x00172000 },
         { .reg = 0x00009888, .val = 0x06178000 },
         { .reg = 0x00009888, .val = 0x0817A000 },
         { .reg = 0x00009888, .val = 0x00180037 },
         { .reg = 0x00009888, .val = 0x06180940 },
         { .reg = 0x00009888, .val = 0x08180000 },
         { .reg = 0x00009888, .val = 0x02180000 },
         { .reg = 0x00009888, .val = 0x04183000 },
         { .reg = 0x00009888, .val = 0x06393000 },
         { .reg = 0x00009888, .val = 0x0C3A28C1 },
         { .reg = 0x00009888, .val = 0x003A0000 },
         { .reg = 0x00009888, .val = 0x0A33F000 },
         { .reg = 0x00009888, .val = 0x0C33F000 },
         { .reg = 0x00009888, .val = 0x0A37A000 },
         { .reg = 0x00009888, .val = 0x0C37A000 },
         { .reg = 0x00009888, .val = 0x0A380977 },
         { .reg = 0x00009888, .val = 0x08380000 },
         { .reg = 0x00009888, .val = 0x04380000 },
         { .reg = 0x00009888, .val = 0x06383000 },
         { .reg = 0x00009888, .val = 0x119000FF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900040 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900800 },
         { .reg = 0x00009888, .val = 0x47901000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900844 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00100030 },
         { .reg = 0x00002774, .val = 0x0000FFF9 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFFC },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFF3 },
         { .reg = 0x00002788, .val = 0x00100180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__vme_pipe__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__vme_pipe__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__vme_pipe__avg_gpu_core_frequency__max,cflgt2__vme_pipe__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__vme_pipe__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,cflgt2__vme_pipe__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 40, percentage_max_float,cflgt2__vme_pipe__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 44, percentage_max_float,cflgt2__vme_pipe__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 48, percentage_max_float,cflgt2__vme_pipe__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 52, percentage_max_float,cflgt2__vme_pipe__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 308, 56, percentage_max_float,cflgt2__vme_pipe__vme_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Gpu Rings Busyness metrics set";
   query->symbol_name = "GpuBusyness";
   query->guid = "e2f162ae-5732-4af0-8b11-69510f57094a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x13805800 },
         { .reg = 0x00009888, .val = 0x05962C00 },
         { .reg = 0x00009888, .val = 0x19950016 },
         { .reg = 0x00009888, .val = 0x19C05800 },
         { .reg = 0x00009888, .val = 0x07800035 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x1D810400 },
         { .reg = 0x00009888, .val = 0x07960025 },
         { .reg = 0x00009888, .val = 0x21960000 },
         { .reg = 0x00009888, .val = 0x0B964000 },
         { .reg = 0x00009888, .val = 0x1B930062 },
         { .reg = 0x00009888, .val = 0x17948000 },
         { .reg = 0x00009888, .val = 0x1B940008 },
         { .reg = 0x00009888, .val = 0x05950075 },
         { .reg = 0x00009888, .val = 0x1D950000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x09924000 },
         { .reg = 0x00009888, .val = 0x05982000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x09978000 },
         { .reg = 0x00009888, .val = 0x05C08500 },
         { .reg = 0x00009888, .val = 0x25C00000 },
         { .reg = 0x00009888, .val = 0x1BC00000 },
         { .reg = 0x00009888, .val = 0x0BC54000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900C60 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00078000 },
         { .reg = 0x00002774, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__gpu_busyness__avg_gpu_core_frequency__max,cflgt2__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 309, 24, percentage_max_float,cflgt2__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 28, percentage_max_float,cflgt2__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 312, 32, percentage_max_float,cflgt2__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 36, percentage_max_float,cflgt2__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 40, percentage_max_float,cflgt2__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "d3c99326-e161-4e44-9745-7772bdc579c5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810000 },
         { .reg = 0x00009888, .val = 0x07810013 },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930040 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__test_oa__avg_gpu_core_frequency__max,cflgt2__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,cflgt2__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,cflgt2__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,cflgt2__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,cflgt2__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,cflgt2__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,cflgt2__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,cflgt2__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,cflgt2__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,cflgt2__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_pma__stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "PMA_Stall";
   query->guid = "5ccbf9fb-6bf2-456b-a749-bdff7b1aff13";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x122D3080 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0800 },
         { .reg = 0x00009888, .val = 0x0E0FAA00 },
         { .reg = 0x00009888, .val = 0x100F0002 },
         { .reg = 0x00009888, .val = 0x002D0025 },
         { .reg = 0x00009888, .val = 0x062D1300 },
         { .reg = 0x00009888, .val = 0x082D16A4 },
         { .reg = 0x00009888, .val = 0x0A2D162E },
         { .reg = 0x00009888, .val = 0x102D0000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00E00021 },
         { .reg = 0x00002774, .val = 0x0007FFF8 },
         { .reg = 0x00002778, .val = 0x07000101 },
         { .reg = 0x0000277C, .val = 0x0038FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__pma__stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__pma__stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__pma__stall__avg_gpu_core_frequency__max,cflgt2__pma__stall__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 24, percentage_max_float,cflgt2__pma__stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt2_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "AsyncCompute metrics set";
   query->symbol_name = "AsyncCompute";
   query->guid = "9802484e-5e21-4ad3-8060-12b7f3bb81fe";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00051050 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00061060 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt2__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt2__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt2__async_compute__avg_gpu_core_frequency__max,cflgt2__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt2__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt2__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt2__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt2__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt2__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt2__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt2__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 150, 80, percentage_max_float,cflgt2__async_compute__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 124, 84, percentage_max_float,cflgt2__async_compute__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 127, 88, percentage_max_float,cflgt2__async_compute__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 331, 92, percentage_max_float,cflgt2__async_compute__cs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,cflgt2__async_compute__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 125, 100, percentage_max_float,cflgt2__async_compute__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,cflgt2__async_compute__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 332, 108, percentage_max_float,cflgt2__async_compute__cs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 154, 112, percentage_max_float,cflgt2__async_compute__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 10, 116, percentage_max_float,cflgt2__async_compute__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 120, percentage_max_float,cflgt2__async_compute__eu_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_cflgt2(struct intel_perf_config *perf)
{
   cflgt2_register_render_basic_counter_query(perf);
   cflgt2_register_compute_basic_counter_query(perf);
   cflgt2_register_render_pipe_profile_counter_query(perf);
   cflgt2_register_memory_reads_counter_query(perf);
   cflgt2_register_memory_writes_counter_query(perf);
   cflgt2_register_compute_extended_counter_query(perf);
   cflgt2_register_compute_l3_cache_counter_query(perf);
   cflgt2_register_hdc_and_sf_counter_query(perf);
   cflgt2_register_l3_1_counter_query(perf);
   cflgt2_register_l3_2_counter_query(perf);
   cflgt2_register_l3_3_counter_query(perf);
   cflgt2_register_rasterizer_and_pixel_backend_counter_query(perf);
   cflgt2_register_sampler_counter_query(perf);
   cflgt2_register_tdl_1_counter_query(perf);
   cflgt2_register_tdl_2_counter_query(perf);
   cflgt2_register_compute_extra_counter_query(perf);
   cflgt2_register_vme_pipe_counter_query(perf);
   cflgt2_register_gpu_busyness_counter_query(perf);
   cflgt2_register_test_oa_counter_query(perf);
   cflgt2_register_pma__stall_counter_query(perf);
   cflgt2_register_async_compute_counter_query(perf);
}


static void
cflgt3_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "b316bcab-212f-4228-97de-af6b5a1a2ea1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C01E0 },
         { .reg = 0x00009888, .val = 0x12170280 },
         { .reg = 0x00009888, .val = 0x12370280 },
         { .reg = 0x00009888, .val = 0x16EC01E0 },
         { .reg = 0x00009888, .val = 0x11930317 },
         { .reg = 0x00009888, .val = 0x159303DF },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x1A4E0380 },
         { .reg = 0x00009888, .val = 0x0A6C0053 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x0A1B4000 },
         { .reg = 0x00009888, .val = 0x1C1C0001 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x042F1000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C8400 },
         { .reg = 0x00009888, .val = 0x0C4C0002 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F6600 },
         { .reg = 0x00009888, .val = 0x100F0001 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x162CA200 },
         { .reg = 0x00009888, .val = 0x062D8000 },
         { .reg = 0x00009888, .val = 0x082D8000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x08133000 },
         { .reg = 0x00009888, .val = 0x00170020 },
         { .reg = 0x00009888, .val = 0x08170021 },
         { .reg = 0x00009888, .val = 0x10170000 },
         { .reg = 0x00009888, .val = 0x0633C000 },
         { .reg = 0x00009888, .val = 0x0833C000 },
         { .reg = 0x00009888, .val = 0x06370800 },
         { .reg = 0x00009888, .val = 0x08370840 },
         { .reg = 0x00009888, .val = 0x10370000 },
         { .reg = 0x00009888, .val = 0x1ACE0200 },
         { .reg = 0x00009888, .val = 0x0AEC5300 },
         { .reg = 0x00009888, .val = 0x10EC0000 },
         { .reg = 0x00009888, .val = 0x1CEC0000 },
         { .reg = 0x00009888, .val = 0x0A9B8000 },
         { .reg = 0x00009888, .val = 0x1C9C0002 },
         { .reg = 0x00009888, .val = 0x0CCC0002 },
         { .reg = 0x00009888, .val = 0x0A8D8000 },
         { .reg = 0x00009888, .val = 0x108F0001 },
         { .reg = 0x00009888, .val = 0x16AC8000 },
         { .reg = 0x00009888, .val = 0x0D933031 },
         { .reg = 0x00009888, .val = 0x0F933E3F },
         { .reg = 0x00009888, .val = 0x01933D00 },
         { .reg = 0x00009888, .val = 0x0393073C },
         { .reg = 0x00009888, .val = 0x0593000E },
         { .reg = 0x00009888, .val = 0x1D930000 },
         { .reg = 0x00009888, .val = 0x19930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x2B908000 },
         { .reg = 0x00009888, .val = 0x2D908000 },
         { .reg = 0x00009888, .val = 0x2F908000 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x15908000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51902240 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x55900242 },
         { .reg = 0x00009888, .val = 0x45900084 },
         { .reg = 0x00009888, .val = 0x47901400 },
         { .reg = 0x00009888, .val = 0x57902220 },
         { .reg = 0x00009888, .val = 0x49900C60 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900002 },
         { .reg = 0x00009888, .val = 0x43900C63 },
         { .reg = 0x00009888, .val = 0x53902222 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__render_basic__avg_gpu_core_frequency__max,cflgt3__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,cflgt3__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,cflgt3__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,cflgt3__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,cflgt3__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,cflgt3__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,cflgt3__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,cflgt3__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,cflgt3__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,cflgt3__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,cflgt3__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,cflgt3__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,cflgt3__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,cflgt3__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,cflgt3__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,cflgt3__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,cflgt3__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,cflgt3__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,cflgt3__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,cflgt3__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,cflgt3__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,cflgt3__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,cflgt3__render_basic__sampler1_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,cflgt3__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,cflgt3__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,cflgt3__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,cflgt3__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,cflgt3__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,cflgt3__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,cflgt3__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,cflgt3__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,cflgt3__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 208, NULL,cflgt3__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, cflgt3__render_basic__slm_bytes_read__max,cflgt3__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, cflgt3__render_basic__slm_bytes_written__max,cflgt3__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,cflgt3__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,cflgt3__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,cflgt3__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,cflgt3__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, cflgt3__render_basic__l3_sampler_throughput__max,cflgt3__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, cflgt3__render_basic__l3_shader_throughput__max,cflgt3__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,cflgt3__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, cflgt3__render_basic__gti_vf_throughput__max,cflgt3__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, cflgt3__render_basic__gti_depth_throughput__max,cflgt3__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, cflgt3__render_basic__gti_rcc_throughput__max,cflgt3__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, cflgt3__render_basic__gti_l3_throughput__max,cflgt3__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, cflgt3__render_basic__gti_hdc_lookups_throughput__max,cflgt3__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, cflgt3__render_basic__gti_read_throughput__max,cflgt3__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, cflgt3__render_basic__gti_write_throughput__max,cflgt3__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,cflgt3__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "d2eec5b1-4dd8-4170-ae83-9531abd0692f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x124F1C00 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x1A4E0820 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x064F0900 },
         { .reg = 0x00009888, .val = 0x084F0032 },
         { .reg = 0x00009888, .val = 0x0A4F1891 },
         { .reg = 0x00009888, .val = 0x0C4F0E00 },
         { .reg = 0x00009888, .val = 0x0E4F003C },
         { .reg = 0x00009888, .val = 0x004F0D80 },
         { .reg = 0x00009888, .val = 0x024F003B },
         { .reg = 0x00009888, .val = 0x006C0002 },
         { .reg = 0x00009888, .val = 0x086C0100 },
         { .reg = 0x00009888, .val = 0x0C6C000C },
         { .reg = 0x00009888, .val = 0x0E6C0B00 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x081B8000 },
         { .reg = 0x00009888, .val = 0x0C1B4000 },
         { .reg = 0x00009888, .val = 0x0E1B8000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1C8000 },
         { .reg = 0x00009888, .val = 0x1C1C0024 },
         { .reg = 0x00009888, .val = 0x065B8000 },
         { .reg = 0x00009888, .val = 0x085B4000 },
         { .reg = 0x00009888, .val = 0x0A5BC000 },
         { .reg = 0x00009888, .val = 0x0C5B8000 },
         { .reg = 0x00009888, .val = 0x0E5B4000 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025B4000 },
         { .reg = 0x00009888, .val = 0x1A5C6000 },
         { .reg = 0x00009888, .val = 0x1C5C001B },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2000 },
         { .reg = 0x00009888, .val = 0x0C4C0208 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2CC000 },
         { .reg = 0x00009888, .val = 0x162CFB00 },
         { .reg = 0x00009888, .val = 0x182C00BE },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x19900157 },
         { .reg = 0x00009888, .val = 0x1B900158 },
         { .reg = 0x00009888, .val = 0x1D900105 },
         { .reg = 0x00009888, .val = 0x1F900103 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x11900FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900821 },
         { .reg = 0x00009888, .val = 0x47900802 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900802 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900002 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900422 },
         { .reg = 0x00009888, .val = 0x53904444 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__compute_basic__avg_gpu_core_frequency__max,cflgt3__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,cflgt3__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,cflgt3__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, cflgt3__compute_basic__eu_avg_ipc_rate__max,cflgt3__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,cflgt3__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,cflgt3__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,cflgt3__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,cflgt3__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,cflgt3__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,cflgt3__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,cflgt3__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,cflgt3__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,cflgt3__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,cflgt3__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,cflgt3__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, cflgt3__compute_basic__slm_bytes_read__max,cflgt3__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, cflgt3__compute_basic__slm_bytes_written__max,cflgt3__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,cflgt3__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,cflgt3__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, cflgt3__compute_basic__l3_shader_throughput__max,cflgt3__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,cflgt3__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, cflgt3__compute_basic__typed_bytes_read__max,cflgt3__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, cflgt3__compute_basic__typed_bytes_written__max,cflgt3__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, cflgt3__compute_basic__untyped_bytes_read__max,cflgt3__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, cflgt3__compute_basic__untyped_bytes_written__max,cflgt3__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, cflgt3__compute_basic__gti_read_throughput__max,cflgt3__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, cflgt3__compute_basic__gti_write_throughput__max,cflgt3__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "9875e050-b1bc-45e6-a6ab-665594601df9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x0C0E001F },
         { .reg = 0x00009888, .val = 0x0A0F0000 },
         { .reg = 0x00009888, .val = 0x10116800 },
         { .reg = 0x00009888, .val = 0x178A03E0 },
         { .reg = 0x00009888, .val = 0x11824C00 },
         { .reg = 0x00009888, .val = 0x11830020 },
         { .reg = 0x00009888, .val = 0x13840020 },
         { .reg = 0x00009888, .val = 0x11850019 },
         { .reg = 0x00009888, .val = 0x11860007 },
         { .reg = 0x00009888, .val = 0x01870C40 },
         { .reg = 0x00009888, .val = 0x17880000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x0A4C0040 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020E5400 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x080F0040 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0040 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06110012 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x01898000 },
         { .reg = 0x00009888, .val = 0x0D890100 },
         { .reg = 0x00009888, .val = 0x03898000 },
         { .reg = 0x00009888, .val = 0x09808000 },
         { .reg = 0x00009888, .val = 0x0B808000 },
         { .reg = 0x00009888, .val = 0x0380C000 },
         { .reg = 0x00009888, .val = 0x0F8A0075 },
         { .reg = 0x00009888, .val = 0x1D8A0000 },
         { .reg = 0x00009888, .val = 0x118A8000 },
         { .reg = 0x00009888, .val = 0x1B8A4000 },
         { .reg = 0x00009888, .val = 0x138A8000 },
         { .reg = 0x00009888, .val = 0x1D81A000 },
         { .reg = 0x00009888, .val = 0x15818000 },
         { .reg = 0x00009888, .val = 0x17818000 },
         { .reg = 0x00009888, .val = 0x0B820030 },
         { .reg = 0x00009888, .val = 0x07828000 },
         { .reg = 0x00009888, .val = 0x0D824000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0D830003 },
         { .reg = 0x00009888, .val = 0x0583000C },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x03838000 },
         { .reg = 0x00009888, .val = 0x07838000 },
         { .reg = 0x00009888, .val = 0x0B840980 },
         { .reg = 0x00009888, .val = 0x03844D80 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x09848000 },
         { .reg = 0x00009888, .val = 0x09850080 },
         { .reg = 0x00009888, .val = 0x03850003 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x07860000 },
         { .reg = 0x00009888, .val = 0x0F860400 },
         { .reg = 0x00009888, .val = 0x09870032 },
         { .reg = 0x00009888, .val = 0x01888052 },
         { .reg = 0x00009888, .val = 0x11880000 },
         { .reg = 0x00009888, .val = 0x09884000 },
         { .reg = 0x00009888, .val = 0x1B931001 },
         { .reg = 0x00009888, .val = 0x1D930001 },
         { .reg = 0x00009888, .val = 0x19934000 },
         { .reg = 0x00009888, .val = 0x1B958000 },
         { .reg = 0x00009888, .val = 0x1D950094 },
         { .reg = 0x00009888, .val = 0x19958000 },
         { .reg = 0x00009888, .val = 0x09E58000 },
         { .reg = 0x00009888, .val = 0x0BE58000 },
         { .reg = 0x00009888, .val = 0x03E5C000 },
         { .reg = 0x00009888, .val = 0x0592C000 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D924000 },
         { .reg = 0x00009888, .val = 0x0F924000 },
         { .reg = 0x00009888, .val = 0x11928000 },
         { .reg = 0x00009888, .val = 0x1392C000 },
         { .reg = 0x00009888, .val = 0x09924000 },
         { .reg = 0x00009888, .val = 0x01985000 },
         { .reg = 0x00009888, .val = 0x07988000 },
         { .reg = 0x00009888, .val = 0x09981000 },
         { .reg = 0x00009888, .val = 0x0B982000 },
         { .reg = 0x00009888, .val = 0x0D982000 },
         { .reg = 0x00009888, .val = 0x0F989000 },
         { .reg = 0x00009888, .val = 0x05982000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25908000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29908000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1190C080 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900440 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900400 },
         { .reg = 0x00009888, .val = 0x47900C21 },
         { .reg = 0x00009888, .val = 0x57900400 },
         { .reg = 0x00009888, .val = 0x49900042 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900024 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900841 },
         { .reg = 0x00009888, .val = 0x53900400 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__render_pipe_profile__avg_gpu_core_frequency__max,cflgt3__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,cflgt3__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,cflgt3__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,cflgt3__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,cflgt3__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,cflgt3__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,cflgt3__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,cflgt3__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,cflgt3__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,cflgt3__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, cflgt3__render_pipe_profile__slm_bytes_read__max,cflgt3__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, cflgt3__render_pipe_profile__slm_bytes_written__max,cflgt3__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,cflgt3__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,cflgt3__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, cflgt3__render_pipe_profile__l3_shader_throughput__max,cflgt3__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,cflgt3__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, NULL,cflgt3__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, NULL,cflgt3__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, NULL,cflgt3__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, NULL,cflgt3__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, NULL,cflgt3__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, NULL,cflgt3__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, NULL,cflgt3__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, NULL,cflgt3__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, NULL,cflgt3__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, NULL,cflgt3__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, NULL,cflgt3__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, NULL,cflgt3__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, NULL,cflgt3__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, NULL,cflgt3__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, NULL,cflgt3__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, NULL,cflgt3__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Reads Distribution metrics set";
   query->symbol_name = "MemoryReads";
   query->guid = "49c65f34-e625-4ca4-86b7-88693e624d4c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F900064 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900150 },
         { .reg = 0x00009888, .val = 0x21900151 },
         { .reg = 0x00009888, .val = 0x23900152 },
         { .reg = 0x00009888, .val = 0x25900153 },
         { .reg = 0x00009888, .val = 0x27900154 },
         { .reg = 0x00009888, .val = 0x29900155 },
         { .reg = 0x00009888, .val = 0x2B900156 },
         { .reg = 0x00009888, .val = 0x2D900157 },
         { .reg = 0x00009888, .val = 0x2F90015F },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__memory_reads__avg_gpu_core_frequency__max,cflgt3__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,cflgt3__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,cflgt3__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,cflgt3__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,cflgt3__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,cflgt3__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,cflgt3__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,cflgt3__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,cflgt3__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,cflgt3__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, cflgt3__memory_reads__slm_bytes_read__max,cflgt3__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, cflgt3__memory_reads__slm_bytes_written__max,cflgt3__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,cflgt3__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,cflgt3__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,cflgt3__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 95, 200, NULL,cflgt3__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 208, NULL,cflgt3__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 216, NULL,cflgt3__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 224, NULL,cflgt3__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 232, NULL,cflgt3__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 240, NULL,cflgt3__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 248, NULL,cflgt3__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 256, NULL,cflgt3__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 264, NULL,cflgt3__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 272, NULL,cflgt3__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 280, NULL,cflgt3__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 288, NULL,cflgt3__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 296, NULL,cflgt3__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 304, NULL,cflgt3__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 312, NULL,cflgt3__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metrics set";
   query->symbol_name = "MemoryWrites";
   query->guid = "45c9e8ee-2998-4d83-88e8-9cb7e03287bf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x1381001A },
         { .reg = 0x00009888, .val = 0x37906800 },
         { .reg = 0x00009888, .val = 0x3F901000 },
         { .reg = 0x00009888, .val = 0x03811300 },
         { .reg = 0x00009888, .val = 0x05811B12 },
         { .reg = 0x00009888, .val = 0x0781001A },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x17810000 },
         { .reg = 0x00009888, .val = 0x19810000 },
         { .reg = 0x00009888, .val = 0x1B810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930055 },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E5C000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x13900160 },
         { .reg = 0x00009888, .val = 0x21900161 },
         { .reg = 0x00009888, .val = 0x23900162 },
         { .reg = 0x00009888, .val = 0x25900163 },
         { .reg = 0x00009888, .val = 0x27900164 },
         { .reg = 0x00009888, .val = 0x29900165 },
         { .reg = 0x00009888, .val = 0x2B900166 },
         { .reg = 0x00009888, .val = 0x2D900167 },
         { .reg = 0x00009888, .val = 0x2F900150 },
         { .reg = 0x00009888, .val = 0x31900105 },
         { .reg = 0x00009888, .val = 0x15900103 },
         { .reg = 0x00009888, .val = 0x17900101 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C60 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900C00 },
         { .reg = 0x00009888, .val = 0x47900C63 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900C63 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900063 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__memory_writes__avg_gpu_core_frequency__max,cflgt3__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,cflgt3__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,cflgt3__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,cflgt3__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,cflgt3__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,cflgt3__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,cflgt3__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,cflgt3__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,cflgt3__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,cflgt3__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, cflgt3__memory_writes__slm_bytes_read__max,cflgt3__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, cflgt3__memory_writes__slm_bytes_written__max,cflgt3__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,cflgt3__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,cflgt3__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, cflgt3__memory_writes__l3_shader_throughput__max,cflgt3__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,cflgt3__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,cflgt3__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,cflgt3__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,cflgt3__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,cflgt3__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,cflgt3__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,cflgt3__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,cflgt3__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,cflgt3__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,cflgt3__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,cflgt3__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,cflgt3__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,cflgt3__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,cflgt3__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,cflgt3__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended metrics set";
   query->symbol_name = "ComputeExtended";
   query->guid = "bac415ce-d7a2-4f8d-9b16-834deba7330e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x106C00E0 },
         { .reg = 0x00009888, .val = 0x141C8160 },
         { .reg = 0x00009888, .val = 0x161C8015 },
         { .reg = 0x00009888, .val = 0x181C0120 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4EAAA0 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0E6C0B01 },
         { .reg = 0x00009888, .val = 0x006C0200 },
         { .reg = 0x00009888, .val = 0x026C000C },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x001C0041 },
         { .reg = 0x00009888, .val = 0x061C4200 },
         { .reg = 0x00009888, .val = 0x081C4443 },
         { .reg = 0x00009888, .val = 0x0A1C4645 },
         { .reg = 0x00009888, .val = 0x0C1C7647 },
         { .reg = 0x00009888, .val = 0x041C7357 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x1A1C0000 },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4CAA2A },
         { .reg = 0x00009888, .val = 0x0C4C02AA },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x0C0F5400 },
         { .reg = 0x00009888, .val = 0x0E0F5515 },
         { .reg = 0x00009888, .val = 0x100F0155 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x11907FFF },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900040 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900802 },
         { .reg = 0x00009888, .val = 0x47900842 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900842 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x43900800 },
         { .reg = 0x00009888, .val = 0x53900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__compute_extended__avg_gpu_core_frequency__max,cflgt3__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,cflgt3__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,cflgt3__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,cflgt3__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,cflgt3__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,cflgt3__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,cflgt3__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, cflgt3__compute_extended__eu_avg_ipc_rate__max,cflgt3__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,cflgt3__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,cflgt3__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,cflgt3__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,cflgt3__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, cflgt3__compute_extended__slm_bytes_read__max,cflgt3__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, cflgt3__compute_extended__slm_bytes_written__max,cflgt3__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,cflgt3__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,cflgt3__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, cflgt3__compute_extended__l3_shader_throughput__max,cflgt3__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,cflgt3__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,cflgt3__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,cflgt3__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,cflgt3__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,cflgt3__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,cflgt3__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,cflgt3__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,cflgt3__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,cflgt3__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,cflgt3__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,cflgt3__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,cflgt3__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,cflgt3__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,cflgt3__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 232, NULL,cflgt3__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 236, NULL,cflgt3__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 240, NULL,cflgt3__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 244, NULL,cflgt3__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 248, NULL,cflgt3__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 54);

   query->name = "Compute Metrics L3 Cache metrics set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "a8cfca44-0e74-4338-9e57-3daad98957dd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C0760 },
         { .reg = 0x00009888, .val = 0x1593001E },
         { .reg = 0x00009888, .val = 0x3F900003 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x184E8000 },
         { .reg = 0x00009888, .val = 0x1A4E8020 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x006C0051 },
         { .reg = 0x00009888, .val = 0x066C5000 },
         { .reg = 0x00009888, .val = 0x086C5C5D },
         { .reg = 0x00009888, .val = 0x0E6C5E5F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x186C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x061B8000 },
         { .reg = 0x00009888, .val = 0x081BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x101C8000 },
         { .reg = 0x00009888, .val = 0x1A1CE000 },
         { .reg = 0x00009888, .val = 0x1C1C0030 },
         { .reg = 0x00009888, .val = 0x004C8000 },
         { .reg = 0x00009888, .val = 0x0A4C2A00 },
         { .reg = 0x00009888, .val = 0x0C4C0280 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F1500 },
         { .reg = 0x00009888, .val = 0x100F0140 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162C0A00 },
         { .reg = 0x00009888, .val = 0x182C00A0 },
         { .reg = 0x00009888, .val = 0x03933300 },
         { .reg = 0x00009888, .val = 0x05930032 },
         { .reg = 0x00009888, .val = 0x11930000 },
         { .reg = 0x00009888, .val = 0x1B930000 },
         { .reg = 0x00009888, .val = 0x1D900157 },
         { .reg = 0x00009888, .val = 0x1F900158 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1190030F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900021 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x53904444 },
         { .reg = 0x00009888, .val = 0x43900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__compute_l3_cache__avg_gpu_core_frequency__max,cflgt3__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,cflgt3__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,cflgt3__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, cflgt3__compute_l3_cache__eu_avg_ipc_rate__max,cflgt3__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,cflgt3__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,cflgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,cflgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,cflgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,cflgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,cflgt3__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,cflgt3__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,cflgt3__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,cflgt3__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,cflgt3__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,cflgt3__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,cflgt3__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,cflgt3__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,cflgt3__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,cflgt3__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,cflgt3__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,cflgt3__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,cflgt3__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,cflgt3__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, cflgt3__compute_l3_cache__slm_bytes_read__max,cflgt3__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, cflgt3__compute_l3_cache__slm_bytes_written__max,cflgt3__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,cflgt3__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,cflgt3__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 256, NULL,cflgt3__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 264, NULL,cflgt3__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, cflgt3__compute_l3_cache__l3_sampler_throughput__max,cflgt3__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 280, cflgt3__compute_l3_cache__l3_shader_throughput__max,cflgt3__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 288, cflgt3__compute_l3_cache__l3_total_throughput__max,cflgt3__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,cflgt3__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 304, NULL,cflgt3__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 312, NULL,cflgt3__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 320, NULL,cflgt3__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 328, NULL,cflgt3__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 336, NULL,cflgt3__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 344, NULL,cflgt3__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 352, cflgt3__compute_l3_cache__gti_l3_throughput__max,cflgt3__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 360, cflgt3__compute_l3_cache__gti_read_throughput__max,cflgt3__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 368, cflgt3__compute_l3_cache__gti_write_throughput__max,cflgt3__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "c4bee67c-0de6-4bc2-9900-5388dcc8adca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F0232 },
         { .reg = 0x00009888, .val = 0x124F4640 },
         { .reg = 0x00009888, .val = 0x106C0232 },
         { .reg = 0x00009888, .val = 0x11834400 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x004F1880 },
         { .reg = 0x00009888, .val = 0x024F08BB },
         { .reg = 0x00009888, .val = 0x044F001B },
         { .reg = 0x00009888, .val = 0x046C0100 },
         { .reg = 0x00009888, .val = 0x066C000B },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x041B8000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x005B8000 },
         { .reg = 0x00009888, .val = 0x025BC000 },
         { .reg = 0x00009888, .val = 0x045B4000 },
         { .reg = 0x00009888, .val = 0x125C8000 },
         { .reg = 0x00009888, .val = 0x145C8000 },
         { .reg = 0x00009888, .val = 0x165C8000 },
         { .reg = 0x00009888, .val = 0x185C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00A0 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x022CC000 },
         { .reg = 0x00009888, .val = 0x042CC000 },
         { .reg = 0x00009888, .val = 0x062CC000 },
         { .reg = 0x00009888, .val = 0x082CC000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x0F8305C0 },
         { .reg = 0x00009888, .val = 0x09830000 },
         { .reg = 0x00009888, .val = 0x07830000 },
         { .reg = 0x00009888, .val = 0x1D950080 },
         { .reg = 0x00009888, .val = 0x13928000 },
         { .reg = 0x00009888, .val = 0x0F988000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900040 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__hdc_and_sf__avg_gpu_core_frequency__max,cflgt3__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt3__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt3__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt3__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt3__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt3__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt3__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt3__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt3__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt3__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt3__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt3__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt3__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt3__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt3__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt3__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt3__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt3__hdc_and_sf__slm_bytes_read__max,cflgt3__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt3__hdc_and_sf__slm_bytes_written__max,cflgt3__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt3__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt3__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt3__hdc_and_sf__l3_shader_throughput__max,cflgt3__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt3__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,cflgt3__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 244, percentage_max_float,cflgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,cflgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 238, 252, percentage_max_float,cflgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,cflgt3__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "2f77a650-54a6-4777-98dc-e49000c13ceb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C7B40 },
         { .reg = 0x00009888, .val = 0x166C0020 },
         { .reg = 0x00009888, .val = 0x0A603444 },
         { .reg = 0x00009888, .val = 0x0A613400 },
         { .reg = 0x00009888, .val = 0x1A4EA800 },
         { .reg = 0x00009888, .val = 0x1C4E0002 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x0C6C5327 },
         { .reg = 0x00009888, .val = 0x0E6C5425 },
         { .reg = 0x00009888, .val = 0x006C2A00 },
         { .reg = 0x00009888, .val = 0x026C285B },
         { .reg = 0x00009888, .val = 0x046C005C },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1E6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0800 },
         { .reg = 0x00009888, .val = 0x0C1BC000 },
         { .reg = 0x00009888, .val = 0x0E1BC000 },
         { .reg = 0x00009888, .val = 0x001B8000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x1C1C003C },
         { .reg = 0x00009888, .val = 0x121C8000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x10600000 },
         { .reg = 0x00009888, .val = 0x04600000 },
         { .reg = 0x00009888, .val = 0x0C610044 },
         { .reg = 0x00009888, .val = 0x10610000 },
         { .reg = 0x00009888, .val = 0x06610000 },
         { .reg = 0x00009888, .val = 0x0C4C02A8 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0154 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x182C00AA },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190FFC0 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900420 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900021 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900400 },
         { .reg = 0x00009888, .val = 0x43900421 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__l3_1__avg_gpu_core_frequency__max,cflgt3__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt3__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt3__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt3__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt3__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt3__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt3__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt3__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt3__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt3__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt3__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt3__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt3__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt3__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt3__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt3__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt3__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt3__l3_1__slm_bytes_read__max,cflgt3__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt3__l3_1__slm_bytes_written__max,cflgt3__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt3__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt3__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt3__l3_1__l3_shader_throughput__max,cflgt3__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt3__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,cflgt3__l3_1__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,cflgt3__l3_1__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,cflgt3__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,cflgt3__l3_1__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,cflgt3__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_2";
   query->symbol_name = "L3_2";
   query->guid = "61cf6b31-9ddd-4deb-bae5-7339dd1f63b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C02E0 },
         { .reg = 0x00009888, .val = 0x146C0001 },
         { .reg = 0x00009888, .val = 0x0A623400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x064F4000 },
         { .reg = 0x00009888, .val = 0x026C3324 },
         { .reg = 0x00009888, .val = 0x046C3422 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C0800 },
         { .reg = 0x00009888, .val = 0x065B4000 },
         { .reg = 0x00009888, .val = 0x1A5C1000 },
         { .reg = 0x00009888, .val = 0x06614000 },
         { .reg = 0x00009888, .val = 0x0C620044 },
         { .reg = 0x00009888, .val = 0x10620000 },
         { .reg = 0x00009888, .val = 0x06620000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C002A },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2CC000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__l3_2__avg_gpu_core_frequency__max,cflgt3__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt3__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt3__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt3__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt3__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt3__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt3__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt3__l3_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt3__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt3__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt3__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt3__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt3__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt3__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt3__l3_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt3__l3_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt3__l3_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt3__l3_2__slm_bytes_read__max,cflgt3__l3_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt3__l3_2__slm_bytes_written__max,cflgt3__l3_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt3__l3_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt3__l3_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt3__l3_2__l3_shader_throughput__max,cflgt3__l3_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt3__l3_2__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 257, 240, percentage_max_float,cflgt3__l3_2__l30_bank2_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 260, 244, percentage_max_float,cflgt3__l3_2__l30_bank2_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,cflgt3__l3_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set L3_3";
   query->symbol_name = "L3_3";
   query->guid = "1421ea8b-a4c9-4383-922a-60ba96c42f24";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x126C4E80 },
         { .reg = 0x00009888, .val = 0x146C0000 },
         { .reg = 0x00009888, .val = 0x0A633400 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E8000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x026C3321 },
         { .reg = 0x00009888, .val = 0x046C342F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1A6C2000 },
         { .reg = 0x00009888, .val = 0x021BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x061B4000 },
         { .reg = 0x00009888, .val = 0x141C8000 },
         { .reg = 0x00009888, .val = 0x161C8000 },
         { .reg = 0x00009888, .val = 0x181C8000 },
         { .reg = 0x00009888, .val = 0x1A1C1800 },
         { .reg = 0x00009888, .val = 0x06604000 },
         { .reg = 0x00009888, .val = 0x0C630044 },
         { .reg = 0x00009888, .val = 0x10630000 },
         { .reg = 0x00009888, .val = 0x06630000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C00AA },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E0F0055 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190F800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900002 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00028002 },
         { .reg = 0x0000277C, .val = 0x000087FF },
         { .reg = 0x00002780, .val = 0x00020002 },
         { .reg = 0x00002784, .val = 0x00008FFF },
         { .reg = 0x00002788, .val = 0x00008002 },
         { .reg = 0x0000278C, .val = 0x0000A7FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__l3_3__avg_gpu_core_frequency__max,cflgt3__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt3__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt3__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt3__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt3__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt3__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt3__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt3__l3_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt3__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt3__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt3__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt3__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt3__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt3__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt3__l3_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt3__l3_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt3__l3_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt3__l3_3__slm_bytes_read__max,cflgt3__l3_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt3__l3_3__slm_bytes_written__max,cflgt3__l3_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt3__l3_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt3__l3_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt3__l3_3__l3_shader_throughput__max,cflgt3__l3_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt3__l3_3__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 253, 240, percentage_max_float,cflgt3__l3_3__l30_bank3_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 256, 244, percentage_max_float,cflgt3__l3_3__l30_bank3_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 248, percentage_max_float,cflgt3__l3_3__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "6e1f0a90-c65f-4da9-86d0-c79b3c0063f6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x102F3800 },
         { .reg = 0x00009888, .val = 0x144D0500 },
         { .reg = 0x00009888, .val = 0x120D03C0 },
         { .reg = 0x00009888, .val = 0x140D03CF },
         { .reg = 0x00009888, .val = 0x0C0F0004 },
         { .reg = 0x00009888, .val = 0x0C4E4000 },
         { .reg = 0x00009888, .val = 0x042F0480 },
         { .reg = 0x00009888, .val = 0x082F0000 },
         { .reg = 0x00009888, .val = 0x022F0000 },
         { .reg = 0x00009888, .val = 0x0A4C0090 },
         { .reg = 0x00009888, .val = 0x064D0027 },
         { .reg = 0x00009888, .val = 0x004D0000 },
         { .reg = 0x00009888, .val = 0x000D0D40 },
         { .reg = 0x00009888, .val = 0x020D803F },
         { .reg = 0x00009888, .val = 0x040D8023 },
         { .reg = 0x00009888, .val = 0x100D0000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x020F0010 },
         { .reg = 0x00009888, .val = 0x000F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0050 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41901400 },
         { .reg = 0x00009888, .val = 0x43901485 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000EFFF },
         { .reg = 0x00002778, .val = 0x00006000 },
         { .reg = 0x0000277C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt3__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt3__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt3__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt3__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt3__rasterizer_and_pixel_backend__slm_bytes_read__max,cflgt3__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt3__rasterizer_and_pixel_backend__slm_bytes_written__max,cflgt3__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt3__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt3__rasterizer_and_pixel_backend__l3_shader_throughput__max,cflgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt3__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 240, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 244, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 248, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 252, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 256, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,cflgt3__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler";
   query->symbol_name = "Sampler";
   query->guid = "7cb05eab-0857-4189-93bc-09326d298637";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x14152C00 },
         { .reg = 0x00009888, .val = 0x16150005 },
         { .reg = 0x00009888, .val = 0x121600A0 },
         { .reg = 0x00009888, .val = 0x14352C00 },
         { .reg = 0x00009888, .val = 0x16350005 },
         { .reg = 0x00009888, .val = 0x123600A0 },
         { .reg = 0x00009888, .val = 0x14552C00 },
         { .reg = 0x00009888, .val = 0x16550005 },
         { .reg = 0x00009888, .val = 0x125600A0 },
         { .reg = 0x00009888, .val = 0x062F6000 },
         { .reg = 0x00009888, .val = 0x022F2000 },
         { .reg = 0x00009888, .val = 0x0C4C0050 },
         { .reg = 0x00009888, .val = 0x0A4C0010 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F0350 },
         { .reg = 0x00009888, .val = 0x0C0FB000 },
         { .reg = 0x00009888, .val = 0x0E0F00DA },
         { .reg = 0x00009888, .val = 0x182C0028 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x022DC000 },
         { .reg = 0x00009888, .val = 0x042D4000 },
         { .reg = 0x00009888, .val = 0x0C138000 },
         { .reg = 0x00009888, .val = 0x0E132000 },
         { .reg = 0x00009888, .val = 0x0413C000 },
         { .reg = 0x00009888, .val = 0x1C140018 },
         { .reg = 0x00009888, .val = 0x0C157000 },
         { .reg = 0x00009888, .val = 0x0E150078 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x04162180 },
         { .reg = 0x00009888, .val = 0x02160000 },
         { .reg = 0x00009888, .val = 0x04174000 },
         { .reg = 0x00009888, .val = 0x0233A000 },
         { .reg = 0x00009888, .val = 0x04333000 },
         { .reg = 0x00009888, .val = 0x14348000 },
         { .reg = 0x00009888, .val = 0x16348000 },
         { .reg = 0x00009888, .val = 0x02357870 },
         { .reg = 0x00009888, .val = 0x10350000 },
         { .reg = 0x00009888, .val = 0x04360043 },
         { .reg = 0x00009888, .val = 0x02360000 },
         { .reg = 0x00009888, .val = 0x04371000 },
         { .reg = 0x00009888, .val = 0x0E538000 },
         { .reg = 0x00009888, .val = 0x00538000 },
         { .reg = 0x00009888, .val = 0x06533000 },
         { .reg = 0x00009888, .val = 0x1C540020 },
         { .reg = 0x00009888, .val = 0x12548000 },
         { .reg = 0x00009888, .val = 0x0E557000 },
         { .reg = 0x00009888, .val = 0x00557800 },
         { .reg = 0x00009888, .val = 0x10550000 },
         { .reg = 0x00009888, .val = 0x06560043 },
         { .reg = 0x00009888, .val = 0x02560000 },
         { .reg = 0x00009888, .val = 0x06571000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900060 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900842 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900060 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__sampler__avg_gpu_core_frequency__max,cflgt3__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__sampler__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__sampler__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__sampler__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__sampler__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__sampler__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__sampler__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__sampler__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__sampler__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__sampler__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__sampler__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt3__sampler__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt3__sampler__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt3__sampler__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt3__sampler__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt3__sampler__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt3__sampler__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt3__sampler__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt3__sampler__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt3__sampler__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt3__sampler__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt3__sampler__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt3__sampler__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt3__sampler__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt3__sampler__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt3__sampler__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt3__sampler__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt3__sampler__slm_bytes_read__max,cflgt3__sampler__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt3__sampler__slm_bytes_written__max,cflgt3__sampler__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt3__sampler__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt3__sampler__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt3__sampler__l3_shader_throughput__max,cflgt3__sampler__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt3__sampler__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,cflgt3__sampler__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,cflgt3__sampler__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,cflgt3__sampler__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,cflgt3__sampler__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,cflgt3__sampler__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,cflgt3__sampler__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,cflgt3__sampler__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "05a06d02-0c12-486b-bb1d-9be053848980";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12120000 },
         { .reg = 0x00009888, .val = 0x12320000 },
         { .reg = 0x00009888, .val = 0x12520000 },
         { .reg = 0x00009888, .val = 0x002F8000 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0015 },
         { .reg = 0x00009888, .val = 0x0C0D8000 },
         { .reg = 0x00009888, .val = 0x0E0DA000 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x100F03A0 },
         { .reg = 0x00009888, .val = 0x0C0FF000 },
         { .reg = 0x00009888, .val = 0x0E0F0095 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2D8000 },
         { .reg = 0x00009888, .val = 0x0E2D4000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x02108000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x02118000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x02121880 },
         { .reg = 0x00009888, .val = 0x041219B5 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x02134000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x0C308000 },
         { .reg = 0x00009888, .val = 0x0E304000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x0C318000 },
         { .reg = 0x00009888, .val = 0x0E314000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x0C321A80 },
         { .reg = 0x00009888, .val = 0x0E320033 },
         { .reg = 0x00009888, .val = 0x06320031 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x0C334000 },
         { .reg = 0x00009888, .val = 0x0E331000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0E508000 },
         { .reg = 0x00009888, .val = 0x00508000 },
         { .reg = 0x00009888, .val = 0x02504000 },
         { .reg = 0x00009888, .val = 0x0E518000 },
         { .reg = 0x00009888, .val = 0x00518000 },
         { .reg = 0x00009888, .val = 0x02514000 },
         { .reg = 0x00009888, .val = 0x0E521880 },
         { .reg = 0x00009888, .val = 0x00521A80 },
         { .reg = 0x00009888, .val = 0x02520033 },
         { .reg = 0x00009888, .val = 0x0E534000 },
         { .reg = 0x00009888, .val = 0x00534000 },
         { .reg = 0x00009888, .val = 0x02531000 },
         { .reg = 0x00009888, .val = 0x1190FF80 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900800 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4B900062 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x00007FFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x00009FFF },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000EFFF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000F3FF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FDFF },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__tdl_1__avg_gpu_core_frequency__max,cflgt3__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt3__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt3__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt3__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt3__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt3__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt3__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt3__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt3__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt3__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt3__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt3__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt3__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt3__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt3__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt3__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt3__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt3__tdl_1__slm_bytes_read__max,cflgt3__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt3__tdl_1__slm_bytes_written__max,cflgt3__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt3__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt3__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt3__tdl_1__l3_shader_throughput__max,cflgt3__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt3__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 240, percentage_max_float,cflgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 244, percentage_max_float,cflgt3__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 248, percentage_max_float,cflgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 252, percentage_max_float,cflgt3__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 256, percentage_max_float,cflgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 260, percentage_max_float,cflgt3__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,cflgt3__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "cddbd1dc-41a2-4fe4-8b05-3d2773120814";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12124D60 },
         { .reg = 0x00009888, .val = 0x12322E60 },
         { .reg = 0x00009888, .val = 0x12524D60 },
         { .reg = 0x00009888, .val = 0x022F3000 },
         { .reg = 0x00009888, .val = 0x0A4C0014 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0FE000 },
         { .reg = 0x00009888, .val = 0x0E0F0097 },
         { .reg = 0x00009888, .val = 0x082C8000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x002D8000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x0410C000 },
         { .reg = 0x00009888, .val = 0x0411C000 },
         { .reg = 0x00009888, .val = 0x04121FB7 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x04135000 },
         { .reg = 0x00009888, .val = 0x00308000 },
         { .reg = 0x00009888, .val = 0x06304000 },
         { .reg = 0x00009888, .val = 0x00318000 },
         { .reg = 0x00009888, .val = 0x06314000 },
         { .reg = 0x00009888, .val = 0x00321B80 },
         { .reg = 0x00009888, .val = 0x0632003F },
         { .reg = 0x00009888, .val = 0x00334000 },
         { .reg = 0x00009888, .val = 0x06331000 },
         { .reg = 0x00009888, .val = 0x0250C000 },
         { .reg = 0x00009888, .val = 0x0251C000 },
         { .reg = 0x00009888, .val = 0x02521FB7 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x02535000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900800 },
         { .reg = 0x00009888, .val = 0x43900063 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__tdl_2__avg_gpu_core_frequency__max,cflgt3__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,cflgt3__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,cflgt3__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,cflgt3__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,cflgt3__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,cflgt3__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,cflgt3__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,cflgt3__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,cflgt3__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,cflgt3__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,cflgt3__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,cflgt3__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,cflgt3__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,cflgt3__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,cflgt3__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,cflgt3__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,cflgt3__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,cflgt3__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,cflgt3__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,cflgt3__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, cflgt3__tdl_2__slm_bytes_read__max,cflgt3__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, cflgt3__tdl_2__slm_bytes_written__max,cflgt3__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,cflgt3__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,cflgt3__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, cflgt3__tdl_2__l3_shader_throughput__max,cflgt3__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,cflgt3__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 240, percentage_max_float,cflgt3__tdl_2__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 244, percentage_max_float,cflgt3__tdl_2__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 248, percentage_max_float,cflgt3__tdl_2__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 252, percentage_max_float,cflgt3__tdl_2__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 256, percentage_max_float,cflgt3__tdl_2__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 260, percentage_max_float,cflgt3__tdl_2__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,cflgt3__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "e61ae394-9d9e-4204-a735-1dad7e44d953";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x121203E0 },
         { .reg = 0x00009888, .val = 0x123203E0 },
         { .reg = 0x00009888, .val = 0x125203E0 },
         { .reg = 0x00009888, .val = 0x129203E0 },
         { .reg = 0x00009888, .val = 0x12B203E0 },
         { .reg = 0x00009888, .val = 0x12D203E0 },
         { .reg = 0x00009888, .val = 0x024EC000 },
         { .reg = 0x00009888, .val = 0x044EC000 },
         { .reg = 0x00009888, .val = 0x064EC000 },
         { .reg = 0x00009888, .val = 0x022F4000 },
         { .reg = 0x00009888, .val = 0x084CA000 },
         { .reg = 0x00009888, .val = 0x0A4C0042 },
         { .reg = 0x00009888, .val = 0x000D8000 },
         { .reg = 0x00009888, .val = 0x020DA000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x0C0F5000 },
         { .reg = 0x00009888, .val = 0x0E0F006D },
         { .reg = 0x00009888, .val = 0x022C8000 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x062C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x042D8000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x06114000 },
         { .reg = 0x00009888, .val = 0x06120033 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x04308000 },
         { .reg = 0x00009888, .val = 0x04318000 },
         { .reg = 0x00009888, .val = 0x04321980 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x04334000 },
         { .reg = 0x00009888, .val = 0x04504000 },
         { .reg = 0x00009888, .val = 0x04514000 },
         { .reg = 0x00009888, .val = 0x04520033 },
         { .reg = 0x00009888, .val = 0x00520000 },
         { .reg = 0x00009888, .val = 0x04531000 },
         { .reg = 0x00009888, .val = 0x00AF8000 },
         { .reg = 0x00009888, .val = 0x0ACC0001 },
         { .reg = 0x00009888, .val = 0x008D8000 },
         { .reg = 0x00009888, .val = 0x028DA000 },
         { .reg = 0x00009888, .val = 0x0C8FB000 },
         { .reg = 0x00009888, .val = 0x0E8F0001 },
         { .reg = 0x00009888, .val = 0x06AC8000 },
         { .reg = 0x00009888, .val = 0x02AD4000 },
         { .reg = 0x00009888, .val = 0x02908000 },
         { .reg = 0x00009888, .val = 0x02918000 },
         { .reg = 0x00009888, .val = 0x02921980 },
         { .reg = 0x00009888, .val = 0x00920000 },
         { .reg = 0x00009888, .val = 0x02934000 },
         { .reg = 0x00009888, .val = 0x02B04000 },
         { .reg = 0x00009888, .val = 0x02B14000 },
         { .reg = 0x00009888, .val = 0x02B20033 },
         { .reg = 0x00009888, .val = 0x00B20000 },
         { .reg = 0x00009888, .val = 0x02B31000 },
         { .reg = 0x00009888, .val = 0x00D08000 },
         { .reg = 0x00009888, .val = 0x00D18000 },
         { .reg = 0x00009888, .val = 0x00D21980 },
         { .reg = 0x00009888, .val = 0x00D34000 },
         { .reg = 0x00009888, .val = 0x1190FC00 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900C00 },
         { .reg = 0x00009888, .val = 0x43900002 },
         { .reg = 0x00009888, .val = 0x53900420 },
         { .reg = 0x00009888, .val = 0x459000A1 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__compute_extra__avg_gpu_core_frequency__max,cflgt3__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,cflgt3__compute_extra__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 307, 28, percentage_max_float,cflgt3__compute_extra__fpu1_active_adjusted__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_vme_pipe_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Media Vme Pipe metrics set";
   query->symbol_name = "VMEPipe";
   query->guid = "94272ad9-45ee-4e34-b7a7-51546cd6405c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A5800 },
         { .reg = 0x00009888, .val = 0x161A00C0 },
         { .reg = 0x00009888, .val = 0x12180240 },
         { .reg = 0x00009888, .val = 0x14180002 },
         { .reg = 0x00009888, .val = 0x149A5800 },
         { .reg = 0x00009888, .val = 0x169A00C0 },
         { .reg = 0x00009888, .val = 0x12980240 },
         { .reg = 0x00009888, .val = 0x14980002 },
         { .reg = 0x00009888, .val = 0x1A4E3FC0 },
         { .reg = 0x00009888, .val = 0x002F1000 },
         { .reg = 0x00009888, .val = 0x022F8000 },
         { .reg = 0x00009888, .val = 0x042F3000 },
         { .reg = 0x00009888, .val = 0x004C4000 },
         { .reg = 0x00009888, .val = 0x0A4C9500 },
         { .reg = 0x00009888, .val = 0x0C4C002A },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0400 },
         { .reg = 0x00009888, .val = 0x0E0F5500 },
         { .reg = 0x00009888, .val = 0x100F0015 },
         { .reg = 0x00009888, .val = 0x002C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x162CAA00 },
         { .reg = 0x00009888, .val = 0x182C000A },
         { .reg = 0x00009888, .val = 0x04193000 },
         { .reg = 0x00009888, .val = 0x081A28C1 },
         { .reg = 0x00009888, .val = 0x001A0000 },
         { .reg = 0x00009888, .val = 0x00133000 },
         { .reg = 0x00009888, .val = 0x0613C000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x00172000 },
         { .reg = 0x00009888, .val = 0x06178000 },
         { .reg = 0x00009888, .val = 0x0817A000 },
         { .reg = 0x00009888, .val = 0x00180037 },
         { .reg = 0x00009888, .val = 0x06180940 },
         { .reg = 0x00009888, .val = 0x08180000 },
         { .reg = 0x00009888, .val = 0x02180000 },
         { .reg = 0x00009888, .val = 0x04183000 },
         { .reg = 0x00009888, .val = 0x04AFC000 },
         { .reg = 0x00009888, .val = 0x06AF3000 },
         { .reg = 0x00009888, .val = 0x0ACC4000 },
         { .reg = 0x00009888, .val = 0x0CCC0015 },
         { .reg = 0x00009888, .val = 0x0A8DA000 },
         { .reg = 0x00009888, .val = 0x0C8DA000 },
         { .reg = 0x00009888, .val = 0x0E8F4000 },
         { .reg = 0x00009888, .val = 0x108F0015 },
         { .reg = 0x00009888, .val = 0x16ACA000 },
         { .reg = 0x00009888, .val = 0x18AC000A },
         { .reg = 0x00009888, .val = 0x06993000 },
         { .reg = 0x00009888, .val = 0x0C9A28C1 },
         { .reg = 0x00009888, .val = 0x009A0000 },
         { .reg = 0x00009888, .val = 0x0A93F000 },
         { .reg = 0x00009888, .val = 0x0C93F000 },
         { .reg = 0x00009888, .val = 0x0A97A000 },
         { .reg = 0x00009888, .val = 0x0C97A000 },
         { .reg = 0x00009888, .val = 0x0A980977 },
         { .reg = 0x00009888, .val = 0x08980000 },
         { .reg = 0x00009888, .val = 0x04980000 },
         { .reg = 0x00009888, .val = 0x06983000 },
         { .reg = 0x00009888, .val = 0x119000FF },
         { .reg = 0x00009888, .val = 0x51900040 },
         { .reg = 0x00009888, .val = 0x41900020 },
         { .reg = 0x00009888, .val = 0x55900004 },
         { .reg = 0x00009888, .val = 0x45900400 },
         { .reg = 0x00009888, .val = 0x479008A5 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900002 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00100030 },
         { .reg = 0x00002774, .val = 0x0000FFF9 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFFC },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFF3 },
         { .reg = 0x00002788, .val = 0x00100180 },
         { .reg = 0x0000278C, .val = 0x0000FFCF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00000002 },
         { .reg = 0x0000279C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__vme_pipe__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__vme_pipe__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__vme_pipe__avg_gpu_core_frequency__max,cflgt3__vme_pipe__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__vme_pipe__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,cflgt3__vme_pipe__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 40, percentage_max_float,cflgt3__vme_pipe__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 44, percentage_max_float,cflgt3__vme_pipe__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 48, percentage_max_float,cflgt3__vme_pipe__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 52, percentage_max_float,cflgt3__vme_pipe__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 308, 56, percentage_max_float,cflgt3__vme_pipe__vme_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Gpu Rings Busyness metrics set";
   query->symbol_name = "GpuBusyness";
   query->guid = "22b7e0c2-cade-425f-b099-34479768c72a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x19D05800 },
         { .reg = 0x00009888, .val = 0x13805800 },
         { .reg = 0x00009888, .val = 0x05962C25 },
         { .reg = 0x00009888, .val = 0x19950016 },
         { .reg = 0x00009888, .val = 0x19C05800 },
         { .reg = 0x00009888, .val = 0x05D00085 },
         { .reg = 0x00009888, .val = 0x25D00000 },
         { .reg = 0x00009888, .val = 0x09D54000 },
         { .reg = 0x00009888, .val = 0x07800035 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x1D810400 },
         { .reg = 0x00009888, .val = 0x21960000 },
         { .reg = 0x00009888, .val = 0x0996C000 },
         { .reg = 0x00009888, .val = 0x0B964000 },
         { .reg = 0x00009888, .val = 0x19938000 },
         { .reg = 0x00009888, .val = 0x1B930068 },
         { .reg = 0x00009888, .val = 0x15948000 },
         { .reg = 0x00009888, .val = 0x1B94000C },
         { .reg = 0x00009888, .val = 0x03957500 },
         { .reg = 0x00009888, .val = 0x1D950000 },
         { .reg = 0x00009888, .val = 0x17950000 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x07928000 },
         { .reg = 0x00009888, .val = 0x03988000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x09978000 },
         { .reg = 0x00009888, .val = 0x05C08500 },
         { .reg = 0x00009888, .val = 0x25C00000 },
         { .reg = 0x00009888, .val = 0x1BC00000 },
         { .reg = 0x00009888, .val = 0x0BC54000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x43900463 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900040 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0007C000 },
         { .reg = 0x00002774, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__gpu_busyness__avg_gpu_core_frequency__max,cflgt3__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 309, 24, percentage_max_float,cflgt3__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 28, percentage_max_float,cflgt3__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 32, percentage_max_float,cflgt3__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 312, 36, percentage_max_float,cflgt3__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 40, percentage_max_float,cflgt3__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 44, percentage_max_float,cflgt3__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "f240ef8d-4a2e-4961-a63c-cc43b01ed923";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x11810000 },
         { .reg = 0x00009888, .val = 0x07810013 },
         { .reg = 0x00009888, .val = 0x1F810000 },
         { .reg = 0x00009888, .val = 0x1D810000 },
         { .reg = 0x00009888, .val = 0x1B930040 },
         { .reg = 0x00009888, .val = 0x07E54000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x11900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__test_oa__avg_gpu_core_frequency__max,cflgt3__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,cflgt3__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,cflgt3__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,cflgt3__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,cflgt3__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,cflgt3__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,cflgt3__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,cflgt3__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,cflgt3__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,cflgt3__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_pma__stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "PMA_Stall";
   query->guid = "c11af8d1-858b-4f8b-98fb-8d683ba8bda0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x122D3080 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x0A0DA000 },
         { .reg = 0x00009888, .val = 0x0C0F0800 },
         { .reg = 0x00009888, .val = 0x0E0FAA00 },
         { .reg = 0x00009888, .val = 0x100F0002 },
         { .reg = 0x00009888, .val = 0x002D0025 },
         { .reg = 0x00009888, .val = 0x062D1300 },
         { .reg = 0x00009888, .val = 0x082D16A4 },
         { .reg = 0x00009888, .val = 0x0A2D162E },
         { .reg = 0x00009888, .val = 0x102D0000 },
         { .reg = 0x00009888, .val = 0x1190003F },
         { .reg = 0x00009888, .val = 0x51900000 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00E00021 },
         { .reg = 0x00002774, .val = 0x0007FFF8 },
         { .reg = 0x00002778, .val = 0x07000101 },
         { .reg = 0x0000277C, .val = 0x0038FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__pma__stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__pma__stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__pma__stall__avg_gpu_core_frequency__max,cflgt3__pma__stall__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 24, percentage_max_float,cflgt3__pma__stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
cflgt3_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "AsyncCompute metrics set";
   query->symbol_name = "AsyncCompute";
   query->guid = "0c824ec1-af53-4545-84a3-ede5e3572fc1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00051050 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00061060 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0x00222222 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,cflgt3__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,cflgt3__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, cflgt3__async_compute__avg_gpu_core_frequency__max,cflgt3__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,cflgt3__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,cflgt3__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,cflgt3__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,cflgt3__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,cflgt3__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,cflgt3__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,cflgt3__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 150, 80, percentage_max_float,cflgt3__async_compute__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 124, 84, percentage_max_float,cflgt3__async_compute__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 127, 88, percentage_max_float,cflgt3__async_compute__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 331, 92, percentage_max_float,cflgt3__async_compute__cs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,cflgt3__async_compute__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 125, 100, percentage_max_float,cflgt3__async_compute__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,cflgt3__async_compute__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 332, 108, percentage_max_float,cflgt3__async_compute__cs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 154, 112, percentage_max_float,cflgt3__async_compute__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 10, 116, percentage_max_float,cflgt3__async_compute__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 120, percentage_max_float,cflgt3__async_compute__eu_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_cflgt3(struct intel_perf_config *perf)
{
   cflgt3_register_render_basic_counter_query(perf);
   cflgt3_register_compute_basic_counter_query(perf);
   cflgt3_register_render_pipe_profile_counter_query(perf);
   cflgt3_register_memory_reads_counter_query(perf);
   cflgt3_register_memory_writes_counter_query(perf);
   cflgt3_register_compute_extended_counter_query(perf);
   cflgt3_register_compute_l3_cache_counter_query(perf);
   cflgt3_register_hdc_and_sf_counter_query(perf);
   cflgt3_register_l3_1_counter_query(perf);
   cflgt3_register_l3_2_counter_query(perf);
   cflgt3_register_l3_3_counter_query(perf);
   cflgt3_register_rasterizer_and_pixel_backend_counter_query(perf);
   cflgt3_register_sampler_counter_query(perf);
   cflgt3_register_tdl_1_counter_query(perf);
   cflgt3_register_tdl_2_counter_query(perf);
   cflgt3_register_compute_extra_counter_query(perf);
   cflgt3_register_vme_pipe_counter_query(perf);
   cflgt3_register_gpu_busyness_counter_query(perf);
   cflgt3_register_test_oa_counter_query(perf);
   cflgt3_register_pma__stall_counter_query(perf);
   cflgt3_register_async_compute_counter_query(perf);
}


static void
bxt_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->devinfo.revision >= 0x03) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x00009840, .val = 0x00000080 },
            { .reg = 0x00009888, .val = 0x166C00F0 },
            { .reg = 0x00009888, .val = 0x12120280 },
            { .reg = 0x00009888, .val = 0x12320280 },
            { .reg = 0x00009888, .val = 0x11930317 },
            { .reg = 0x00009888, .val = 0x159303DF },
            { .reg = 0x00009888, .val = 0x3F900C00 },
            { .reg = 0x00009888, .val = 0x419000A0 },
            { .reg = 0x00009888, .val = 0x002D1000 },
            { .reg = 0x00009888, .val = 0x062D4000 },
            { .reg = 0x00009888, .val = 0x082D5000 },
            { .reg = 0x00009888, .val = 0x0A2D1000 },
            { .reg = 0x00009888, .val = 0x0C2E0800 },
            { .reg = 0x00009888, .val = 0x0E2E5900 },
            { .reg = 0x00009888, .val = 0x0A4C8000 },
            { .reg = 0x00009888, .val = 0x0C4C8000 },
            { .reg = 0x00009888, .val = 0x0E4C4000 },
            { .reg = 0x00009888, .val = 0x064E8000 },
            { .reg = 0x00009888, .val = 0x084E8000 },
            { .reg = 0x00009888, .val = 0x0A4E2000 },
            { .reg = 0x00009888, .val = 0x1C4F0010 },
            { .reg = 0x00009888, .val = 0x0A6C0053 },
            { .reg = 0x00009888, .val = 0x106C0000 },
            { .reg = 0x00009888, .val = 0x1C6C0000 },
            { .reg = 0x00009888, .val = 0x1A0FCC00 },
            { .reg = 0x00009888, .val = 0x1C0F0002 },
            { .reg = 0x00009888, .val = 0x1C2C0040 },
            { .reg = 0x00009888, .val = 0x00101000 },
            { .reg = 0x00009888, .val = 0x04101000 },
            { .reg = 0x00009888, .val = 0x00114000 },
            { .reg = 0x00009888, .val = 0x08114000 },
            { .reg = 0x00009888, .val = 0x00120020 },
            { .reg = 0x00009888, .val = 0x08120021 },
            { .reg = 0x00009888, .val = 0x00141000 },
            { .reg = 0x00009888, .val = 0x08141000 },
            { .reg = 0x00009888, .val = 0x02308000 },
            { .reg = 0x00009888, .val = 0x04302000 },
            { .reg = 0x00009888, .val = 0x06318000 },
            { .reg = 0x00009888, .val = 0x08318000 },
            { .reg = 0x00009888, .val = 0x06320800 },
            { .reg = 0x00009888, .val = 0x08320840 },
            { .reg = 0x00009888, .val = 0x00320000 },
            { .reg = 0x00009888, .val = 0x06344000 },
            { .reg = 0x00009888, .val = 0x08344000 },
            { .reg = 0x00009888, .val = 0x0D931831 },
            { .reg = 0x00009888, .val = 0x0F939F3F },
            { .reg = 0x00009888, .val = 0x01939E80 },
            { .reg = 0x00009888, .val = 0x039303BC },
            { .reg = 0x00009888, .val = 0x0593000E },
            { .reg = 0x00009888, .val = 0x1993002A },
            { .reg = 0x00009888, .val = 0x07930000 },
            { .reg = 0x00009888, .val = 0x09930000 },
            { .reg = 0x00009888, .val = 0x1D900177 },
            { .reg = 0x00009888, .val = 0x1F900187 },
            { .reg = 0x00009888, .val = 0x35900000 },
            { .reg = 0x00009888, .val = 0x13904000 },
            { .reg = 0x00009888, .val = 0x21904000 },
            { .reg = 0x00009888, .val = 0x23904000 },
            { .reg = 0x00009888, .val = 0x25904000 },
            { .reg = 0x00009888, .val = 0x27904000 },
            { .reg = 0x00009888, .val = 0x2B904000 },
            { .reg = 0x00009888, .val = 0x2D904000 },
            { .reg = 0x00009888, .val = 0x2F904000 },
            { .reg = 0x00009888, .val = 0x31904000 },
            { .reg = 0x00009888, .val = 0x15904000 },
            { .reg = 0x00009888, .val = 0x17904000 },
            { .reg = 0x00009888, .val = 0x19904000 },
            { .reg = 0x00009888, .val = 0x1B904000 },
            { .reg = 0x00009888, .val = 0x53901110 },
            { .reg = 0x00009888, .val = 0x43900423 },
            { .reg = 0x00009888, .val = 0x55900111 },
            { .reg = 0x00009888, .val = 0x47900C02 },
            { .reg = 0x00009888, .val = 0x57900000 },
            { .reg = 0x00009888, .val = 0x49900020 },
            { .reg = 0x00009888, .val = 0x59901111 },
            { .reg = 0x00009888, .val = 0x4B900421 },
            { .reg = 0x00009888, .val = 0x37900000 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4D900001 },
            { .reg = 0x00009888, .val = 0x45900821 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__render_basic__avg_gpu_core_frequency__max,bxt__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,bxt__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,bxt__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,bxt__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,bxt__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,bxt__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,bxt__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,bxt__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,bxt__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,bxt__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,bxt__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,bxt__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,bxt__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,bxt__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,bxt__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,bxt__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,bxt__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,bxt__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,bxt__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,bxt__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,bxt__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,bxt__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,bxt__render_basic__sampler1_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,bxt__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,bxt__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,bxt__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,bxt__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,bxt__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,bxt__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,bxt__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,bxt__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,bxt__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 208, NULL,bxt__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, bxt__render_basic__slm_bytes_read__max,bxt__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, bxt__render_basic__slm_bytes_written__max,bxt__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,bxt__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,bxt__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,bxt__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,bxt__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, bxt__render_basic__l3_sampler_throughput__max,bxt__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, bxt__render_basic__l3_shader_throughput__max,bxt__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,bxt__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, bxt__render_basic__gti_vf_throughput__max,bxt__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, bxt__render_basic__gti_depth_throughput__max,bxt__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, bxt__render_basic__gti_rcc_throughput__max,bxt__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, bxt__render_basic__gti_l3_throughput__max,bxt__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, bxt__render_basic__gti_hdc_lookups_throughput__max,bxt__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, bxt__render_basic__gti_read_throughput__max,bxt__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, bxt__render_basic__gti_write_throughput__max,bxt__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,bxt__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "012d72cf-82a9-4d25-8ddf-74076fd30797";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x124F1C00 },
         { .reg = 0x00009888, .val = 0x39900340 },
         { .reg = 0x00009888, .val = 0x3F900C00 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x002D5000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x082D4000 },
         { .reg = 0x00009888, .val = 0x0A2D1000 },
         { .reg = 0x00009888, .val = 0x0C2D5000 },
         { .reg = 0x00009888, .val = 0x0E2D4000 },
         { .reg = 0x00009888, .val = 0x0C2E1400 },
         { .reg = 0x00009888, .val = 0x0E2E5100 },
         { .reg = 0x00009888, .val = 0x102E0114 },
         { .reg = 0x00009888, .val = 0x044CC000 },
         { .reg = 0x00009888, .val = 0x0A4C8000 },
         { .reg = 0x00009888, .val = 0x0C4C8000 },
         { .reg = 0x00009888, .val = 0x0E4C4000 },
         { .reg = 0x00009888, .val = 0x104C8000 },
         { .reg = 0x00009888, .val = 0x124C8000 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x004EA000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E2000 },
         { .reg = 0x00009888, .val = 0x0C4EA000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x004F6B42 },
         { .reg = 0x00009888, .val = 0x064F6200 },
         { .reg = 0x00009888, .val = 0x084F4100 },
         { .reg = 0x00009888, .val = 0x0A4F0061 },
         { .reg = 0x00009888, .val = 0x0C4F6C4C },
         { .reg = 0x00009888, .val = 0x0E4F4B00 },
         { .reg = 0x00009888, .val = 0x1A4F0000 },
         { .reg = 0x00009888, .val = 0x1C4F0000 },
         { .reg = 0x00009888, .val = 0x180F5000 },
         { .reg = 0x00009888, .val = 0x1A0F8800 },
         { .reg = 0x00009888, .val = 0x1C0F08A2 },
         { .reg = 0x00009888, .val = 0x182C4000 },
         { .reg = 0x00009888, .val = 0x1C2C1451 },
         { .reg = 0x00009888, .val = 0x1E2C0001 },
         { .reg = 0x00009888, .val = 0x1A2C0010 },
         { .reg = 0x00009888, .val = 0x01938000 },
         { .reg = 0x00009888, .val = 0x0F938000 },
         { .reg = 0x00009888, .val = 0x19938A28 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x19900177 },
         { .reg = 0x00009888, .val = 0x1B900178 },
         { .reg = 0x00009888, .val = 0x1D900125 },
         { .reg = 0x00009888, .val = 0x1F900123 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x53901000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x55900111 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__compute_basic__avg_gpu_core_frequency__max,bxt__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bxt__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,bxt__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,bxt__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, bxt__compute_basic__eu_avg_ipc_rate__max,bxt__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,bxt__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,bxt__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,bxt__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,bxt__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,bxt__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,bxt__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,bxt__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,bxt__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,bxt__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,bxt__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,bxt__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, bxt__compute_basic__slm_bytes_read__max,bxt__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, bxt__compute_basic__slm_bytes_written__max,bxt__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,bxt__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,bxt__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, bxt__compute_basic__l3_shader_throughput__max,bxt__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,bxt__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, bxt__compute_basic__typed_bytes_read__max,bxt__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, bxt__compute_basic__typed_bytes_written__max,bxt__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, bxt__compute_basic__untyped_bytes_read__max,bxt__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, bxt__compute_basic__untyped_bytes_written__max,bxt__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, bxt__compute_basic__gti_read_throughput__max,bxt__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, bxt__compute_basic__gti_write_throughput__max,bxt__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "ce416533-e49e-4211-80af-ec513590a914";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x0C2E001F },
         { .reg = 0x00009888, .val = 0x0A2F0000 },
         { .reg = 0x00009888, .val = 0x10186800 },
         { .reg = 0x00009888, .val = 0x11810019 },
         { .reg = 0x00009888, .val = 0x15810013 },
         { .reg = 0x00009888, .val = 0x13820020 },
         { .reg = 0x00009888, .val = 0x11830020 },
         { .reg = 0x00009888, .val = 0x17840000 },
         { .reg = 0x00009888, .val = 0x11860007 },
         { .reg = 0x00009888, .val = 0x21860000 },
         { .reg = 0x00009888, .val = 0x178703E0 },
         { .reg = 0x00009888, .val = 0x0C2D8000 },
         { .reg = 0x00009888, .val = 0x042D4000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x022E5400 },
         { .reg = 0x00009888, .val = 0x002E0000 },
         { .reg = 0x00009888, .val = 0x0E2E0080 },
         { .reg = 0x00009888, .val = 0x082F0040 },
         { .reg = 0x00009888, .val = 0x002F0000 },
         { .reg = 0x00009888, .val = 0x06143000 },
         { .reg = 0x00009888, .val = 0x06174000 },
         { .reg = 0x00009888, .val = 0x06180012 },
         { .reg = 0x00009888, .val = 0x00180000 },
         { .reg = 0x00009888, .val = 0x0D804000 },
         { .reg = 0x00009888, .val = 0x0F804000 },
         { .reg = 0x00009888, .val = 0x05804000 },
         { .reg = 0x00009888, .val = 0x09810200 },
         { .reg = 0x00009888, .val = 0x0B810030 },
         { .reg = 0x00009888, .val = 0x03810003 },
         { .reg = 0x00009888, .val = 0x21819140 },
         { .reg = 0x00009888, .val = 0x23819050 },
         { .reg = 0x00009888, .val = 0x25810018 },
         { .reg = 0x00009888, .val = 0x0B820980 },
         { .reg = 0x00009888, .val = 0x03820D80 },
         { .reg = 0x00009888, .val = 0x11820000 },
         { .reg = 0x00009888, .val = 0x0182C000 },
         { .reg = 0x00009888, .val = 0x07828000 },
         { .reg = 0x00009888, .val = 0x09824000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x0D830004 },
         { .reg = 0x00009888, .val = 0x0583000C },
         { .reg = 0x00009888, .val = 0x0F831000 },
         { .reg = 0x00009888, .val = 0x01848072 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x07848000 },
         { .reg = 0x00009888, .val = 0x09844000 },
         { .reg = 0x00009888, .val = 0x0F848000 },
         { .reg = 0x00009888, .val = 0x07860000 },
         { .reg = 0x00009888, .val = 0x09860092 },
         { .reg = 0x00009888, .val = 0x0F860400 },
         { .reg = 0x00009888, .val = 0x01869100 },
         { .reg = 0x00009888, .val = 0x0F870065 },
         { .reg = 0x00009888, .val = 0x01870000 },
         { .reg = 0x00009888, .val = 0x19930800 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x1B952000 },
         { .reg = 0x00009888, .val = 0x1D955055 },
         { .reg = 0x00009888, .val = 0x1F951455 },
         { .reg = 0x00009888, .val = 0x0992A000 },
         { .reg = 0x00009888, .val = 0x0F928000 },
         { .reg = 0x00009888, .val = 0x1192A800 },
         { .reg = 0x00009888, .val = 0x1392028A },
         { .reg = 0x00009888, .val = 0x0B92A000 },
         { .reg = 0x00009888, .val = 0x0D922000 },
         { .reg = 0x00009888, .val = 0x13908000 },
         { .reg = 0x00009888, .val = 0x21908000 },
         { .reg = 0x00009888, .val = 0x23908000 },
         { .reg = 0x00009888, .val = 0x25908000 },
         { .reg = 0x00009888, .val = 0x27908000 },
         { .reg = 0x00009888, .val = 0x29908000 },
         { .reg = 0x00009888, .val = 0x2B908000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F908000 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x15908000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900C01 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900863 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900061 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900000 },
         { .reg = 0x00009888, .val = 0x45900C22 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__render_pipe_profile__avg_gpu_core_frequency__max,bxt__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,bxt__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,bxt__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,bxt__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,bxt__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,bxt__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,bxt__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,bxt__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,bxt__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,bxt__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, bxt__render_pipe_profile__slm_bytes_read__max,bxt__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, bxt__render_pipe_profile__slm_bytes_written__max,bxt__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,bxt__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,bxt__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, bxt__render_pipe_profile__l3_shader_throughput__max,bxt__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,bxt__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, NULL,bxt__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, NULL,bxt__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, NULL,bxt__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, NULL,bxt__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, NULL,bxt__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, NULL,bxt__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, NULL,bxt__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, NULL,bxt__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, NULL,bxt__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, NULL,bxt__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, NULL,bxt__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, NULL,bxt__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, NULL,bxt__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, NULL,bxt__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, NULL,bxt__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, NULL,bxt__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Reads Distribution metric set";
   query->symbol_name = "MemoryReads";
   query->guid = "398e2452-18d7-42d0-b241-e4d0a9148ada";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x19800343 },
         { .reg = 0x00009888, .val = 0x39900340 },
         { .reg = 0x00009888, .val = 0x3F901000 },
         { .reg = 0x00009888, .val = 0x41900003 },
         { .reg = 0x00009888, .val = 0x03803180 },
         { .reg = 0x00009888, .val = 0x058035E2 },
         { .reg = 0x00009888, .val = 0x0780006A },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x2181A000 },
         { .reg = 0x00009888, .val = 0x2381000A },
         { .reg = 0x00009888, .val = 0x1D950550 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D92A000 },
         { .reg = 0x00009888, .val = 0x0F922000 },
         { .reg = 0x00009888, .val = 0x13900170 },
         { .reg = 0x00009888, .val = 0x21900171 },
         { .reg = 0x00009888, .val = 0x23900172 },
         { .reg = 0x00009888, .val = 0x25900173 },
         { .reg = 0x00009888, .val = 0x27900174 },
         { .reg = 0x00009888, .val = 0x29900175 },
         { .reg = 0x00009888, .val = 0x2B900176 },
         { .reg = 0x00009888, .val = 0x2D900177 },
         { .reg = 0x00009888, .val = 0x2F90017F },
         { .reg = 0x00009888, .val = 0x31900125 },
         { .reg = 0x00009888, .val = 0x15900123 },
         { .reg = 0x00009888, .val = 0x17900121 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43901084 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47901080 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49901084 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B901084 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900004 },
         { .reg = 0x00009888, .val = 0x45900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__memory_reads__avg_gpu_core_frequency__max,bxt__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,bxt__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,bxt__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,bxt__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,bxt__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,bxt__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,bxt__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,bxt__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,bxt__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,bxt__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, bxt__memory_reads__slm_bytes_read__max,bxt__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, bxt__memory_reads__slm_bytes_written__max,bxt__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,bxt__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,bxt__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,bxt__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 95, 200, NULL,bxt__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 208, NULL,bxt__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 216, NULL,bxt__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 224, NULL,bxt__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 232, NULL,bxt__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 240, NULL,bxt__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 248, NULL,bxt__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 256, NULL,bxt__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 264, NULL,bxt__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 272, NULL,bxt__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 280, NULL,bxt__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 288, NULL,bxt__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 296, NULL,bxt__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 304, NULL,bxt__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 312, NULL,bxt__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metric set";
   query->symbol_name = "MemoryWrites";
   query->guid = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x19800343 },
         { .reg = 0x00009888, .val = 0x39900340 },
         { .reg = 0x00009888, .val = 0x3F900000 },
         { .reg = 0x00009888, .val = 0x41900080 },
         { .reg = 0x00009888, .val = 0x03803180 },
         { .reg = 0x00009888, .val = 0x058035E2 },
         { .reg = 0x00009888, .val = 0x0780006A },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x2181A000 },
         { .reg = 0x00009888, .val = 0x2381000A },
         { .reg = 0x00009888, .val = 0x1D950550 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D92A000 },
         { .reg = 0x00009888, .val = 0x0F922000 },
         { .reg = 0x00009888, .val = 0x13900180 },
         { .reg = 0x00009888, .val = 0x21900181 },
         { .reg = 0x00009888, .val = 0x23900182 },
         { .reg = 0x00009888, .val = 0x25900183 },
         { .reg = 0x00009888, .val = 0x27900184 },
         { .reg = 0x00009888, .val = 0x29900185 },
         { .reg = 0x00009888, .val = 0x2B900186 },
         { .reg = 0x00009888, .val = 0x2D900187 },
         { .reg = 0x00009888, .val = 0x2F900170 },
         { .reg = 0x00009888, .val = 0x31900125 },
         { .reg = 0x00009888, .val = 0x15900123 },
         { .reg = 0x00009888, .val = 0x17900121 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43901084 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47901080 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49901084 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B901084 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900004 },
         { .reg = 0x00009888, .val = 0x45900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__memory_writes__avg_gpu_core_frequency__max,bxt__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,bxt__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,bxt__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,bxt__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,bxt__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,bxt__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,bxt__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,bxt__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,bxt__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,bxt__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, bxt__memory_writes__slm_bytes_read__max,bxt__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, bxt__memory_writes__slm_bytes_written__max,bxt__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,bxt__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,bxt__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, bxt__memory_writes__l3_shader_throughput__max,bxt__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,bxt__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,bxt__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,bxt__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,bxt__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,bxt__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,bxt__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,bxt__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,bxt__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,bxt__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,bxt__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,bxt__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,bxt__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,bxt__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,bxt__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,bxt__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended metric set";
   query->symbol_name = "ComputeExtended";
   query->guid = "caf3596a-7bb1-4dec-b3b3-2a080d283b49";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x141C0160 },
         { .reg = 0x00009888, .val = 0x161C0015 },
         { .reg = 0x00009888, .val = 0x181C0120 },
         { .reg = 0x00009888, .val = 0x002D5000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x082D5000 },
         { .reg = 0x00009888, .val = 0x0A2D5000 },
         { .reg = 0x00009888, .val = 0x0C2D5000 },
         { .reg = 0x00009888, .val = 0x0E2D5000 },
         { .reg = 0x00009888, .val = 0x022D5000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x0C2E5400 },
         { .reg = 0x00009888, .val = 0x0E2E5515 },
         { .reg = 0x00009888, .val = 0x102E0155 },
         { .reg = 0x00009888, .val = 0x044CC000 },
         { .reg = 0x00009888, .val = 0x0A4C8000 },
         { .reg = 0x00009888, .val = 0x0C4CC000 },
         { .reg = 0x00009888, .val = 0x0E4CC000 },
         { .reg = 0x00009888, .val = 0x104C8000 },
         { .reg = 0x00009888, .val = 0x124C8000 },
         { .reg = 0x00009888, .val = 0x144C8000 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x064CC000 },
         { .reg = 0x00009888, .val = 0x084CC000 },
         { .reg = 0x00009888, .val = 0x004EA000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084EA000 },
         { .reg = 0x00009888, .val = 0x0A4EA000 },
         { .reg = 0x00009888, .val = 0x0C4EA000 },
         { .reg = 0x00009888, .val = 0x0E4EA000 },
         { .reg = 0x00009888, .val = 0x024EA000 },
         { .reg = 0x00009888, .val = 0x044EA000 },
         { .reg = 0x00009888, .val = 0x0E4F4B41 },
         { .reg = 0x00009888, .val = 0x004F4200 },
         { .reg = 0x00009888, .val = 0x024F404C },
         { .reg = 0x00009888, .val = 0x1C4F0000 },
         { .reg = 0x00009888, .val = 0x1A4F0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x061B8000 },
         { .reg = 0x00009888, .val = 0x081BC000 },
         { .reg = 0x00009888, .val = 0x0A1BC000 },
         { .reg = 0x00009888, .val = 0x0C1BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x001C0031 },
         { .reg = 0x00009888, .val = 0x061C1900 },
         { .reg = 0x00009888, .val = 0x081C1A33 },
         { .reg = 0x00009888, .val = 0x0A1C1B35 },
         { .reg = 0x00009888, .val = 0x0C1C3337 },
         { .reg = 0x00009888, .val = 0x041C31C7 },
         { .reg = 0x00009888, .val = 0x180F5000 },
         { .reg = 0x00009888, .val = 0x1A0FA8AA },
         { .reg = 0x00009888, .val = 0x1C0F0AAA },
         { .reg = 0x00009888, .val = 0x182C8000 },
         { .reg = 0x00009888, .val = 0x1C2C6AAA },
         { .reg = 0x00009888, .val = 0x1E2C0001 },
         { .reg = 0x00009888, .val = 0x1A2C2950 },
         { .reg = 0x00009888, .val = 0x01938000 },
         { .reg = 0x00009888, .val = 0x0F938000 },
         { .reg = 0x00009888, .val = 0x1993AAAA },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29904000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900420 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900400 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900001 },
         { .reg = 0x00009888, .val = 0x45900001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__compute_extended__avg_gpu_core_frequency__max,bxt__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,bxt__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,bxt__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,bxt__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,bxt__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,bxt__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,bxt__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, bxt__compute_extended__eu_avg_ipc_rate__max,bxt__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,bxt__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,bxt__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,bxt__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,bxt__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, bxt__compute_extended__slm_bytes_read__max,bxt__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, bxt__compute_extended__slm_bytes_written__max,bxt__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,bxt__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,bxt__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, bxt__compute_extended__l3_shader_throughput__max,bxt__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,bxt__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,bxt__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,bxt__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,bxt__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,bxt__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,bxt__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,bxt__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,bxt__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,bxt__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,bxt__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,bxt__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,bxt__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,bxt__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,bxt__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 232, NULL,bxt__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 236, NULL,bxt__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 240, NULL,bxt__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 244, NULL,bxt__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 248, NULL,bxt__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 54);

   query->name = "Compute Metrics L3 Cache metric set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C03B0 },
         { .reg = 0x00009888, .val = 0x1593001E },
         { .reg = 0x00009888, .val = 0x3F900C00 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x002D1000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x082D5000 },
         { .reg = 0x00009888, .val = 0x0E2D5000 },
         { .reg = 0x00009888, .val = 0x0C2E0400 },
         { .reg = 0x00009888, .val = 0x0E2E1500 },
         { .reg = 0x00009888, .val = 0x102E0140 },
         { .reg = 0x00009888, .val = 0x044C4000 },
         { .reg = 0x00009888, .val = 0x0A4C8000 },
         { .reg = 0x00009888, .val = 0x0C4CC000 },
         { .reg = 0x00009888, .val = 0x144C8000 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x004E2000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084EA000 },
         { .reg = 0x00009888, .val = 0x0E4EA000 },
         { .reg = 0x00009888, .val = 0x1A4F4001 },
         { .reg = 0x00009888, .val = 0x1C4F5005 },
         { .reg = 0x00009888, .val = 0x006C0051 },
         { .reg = 0x00009888, .val = 0x066C5000 },
         { .reg = 0x00009888, .val = 0x086C5C5D },
         { .reg = 0x00009888, .val = 0x0E6C5E5F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x146C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x180F1000 },
         { .reg = 0x00009888, .val = 0x1A0FA800 },
         { .reg = 0x00009888, .val = 0x1C0F0A00 },
         { .reg = 0x00009888, .val = 0x182C4000 },
         { .reg = 0x00009888, .val = 0x1C2C4015 },
         { .reg = 0x00009888, .val = 0x1E2C0001 },
         { .reg = 0x00009888, .val = 0x03931980 },
         { .reg = 0x00009888, .val = 0x05930032 },
         { .reg = 0x00009888, .val = 0x11930000 },
         { .reg = 0x00009888, .val = 0x01938000 },
         { .reg = 0x00009888, .val = 0x0F938000 },
         { .reg = 0x00009888, .val = 0x1993A00A },
         { .reg = 0x00009888, .val = 0x07930000 },
         { .reg = 0x00009888, .val = 0x09930000 },
         { .reg = 0x00009888, .val = 0x1D900177 },
         { .reg = 0x00009888, .val = 0x1F900178 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x53901000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x55900111 },
         { .reg = 0x00009888, .val = 0x47900001 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x4D900000 },
         { .reg = 0x00009888, .val = 0x45900400 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__compute_l3_cache__avg_gpu_core_frequency__max,bxt__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bxt__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,bxt__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,bxt__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, bxt__compute_l3_cache__eu_avg_ipc_rate__max,bxt__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,bxt__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,bxt__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,bxt__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,bxt__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,bxt__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,bxt__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,bxt__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,bxt__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,bxt__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,bxt__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,bxt__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,bxt__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,bxt__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,bxt__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,bxt__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,bxt__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,bxt__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,bxt__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,bxt__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, bxt__compute_l3_cache__slm_bytes_read__max,bxt__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, bxt__compute_l3_cache__slm_bytes_written__max,bxt__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,bxt__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,bxt__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 256, NULL,bxt__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 264, NULL,bxt__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, bxt__compute_l3_cache__l3_sampler_throughput__max,bxt__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 280, bxt__compute_l3_cache__l3_shader_throughput__max,bxt__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 288, bxt__compute_l3_cache__l3_total_throughput__max,bxt__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,bxt__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 304, NULL,bxt__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 312, NULL,bxt__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 320, NULL,bxt__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 328, NULL,bxt__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 336, NULL,bxt__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 344, NULL,bxt__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 352, bxt__compute_l3_cache__gti_l3_throughput__max,bxt__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 360, bxt__compute_l3_cache__gti_read_throughput__max,bxt__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 368, bxt__compute_l3_cache__gti_write_throughput__max,bxt__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "ad9d9bc2-ccb7-4f5d-adbb-b4e67e615efd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F0232 },
         { .reg = 0x00009888, .val = 0x124F4640 },
         { .reg = 0x00009888, .val = 0x11834400 },
         { .reg = 0x00009888, .val = 0x022D4000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x0E2E0055 },
         { .reg = 0x00009888, .val = 0x064C8000 },
         { .reg = 0x00009888, .val = 0x084CC000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044EA000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x024F6100 },
         { .reg = 0x00009888, .val = 0x044F416B },
         { .reg = 0x00009888, .val = 0x064F004B },
         { .reg = 0x00009888, .val = 0x1A4F0000 },
         { .reg = 0x00009888, .val = 0x1A0F02A8 },
         { .reg = 0x00009888, .val = 0x1A2C5500 },
         { .reg = 0x00009888, .val = 0x0F808000 },
         { .reg = 0x00009888, .val = 0x25810020 },
         { .reg = 0x00009888, .val = 0x0F8305C0 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x1F951000 },
         { .reg = 0x00009888, .val = 0x13920200 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4D900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__hdc_and_sf__avg_gpu_core_frequency__max,bxt__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bxt__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bxt__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bxt__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bxt__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bxt__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bxt__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bxt__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bxt__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bxt__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bxt__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bxt__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bxt__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bxt__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bxt__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bxt__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bxt__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bxt__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bxt__hdc_and_sf__slm_bytes_read__max,bxt__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bxt__hdc_and_sf__slm_bytes_written__max,bxt__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bxt__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bxt__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bxt__hdc_and_sf__l3_shader_throughput__max,bxt__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bxt__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,bxt__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 244, percentage_max_float,bxt__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,bxt__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 252, percentage_max_float,bxt__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "bde7b434-349c-4aad-8596-eb23c0352168";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      if (perf->devinfo.revision >= 0x03) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x000091BC, .val = 0xE0500000 },
            { .reg = 0x00009840, .val = 0x00000080 },
            { .reg = 0x00009888, .val = 0x12643400 },
            { .reg = 0x00009888, .val = 0x12653400 },
            { .reg = 0x00009888, .val = 0x106C6800 },
            { .reg = 0x00009888, .val = 0x126C001E },
            { .reg = 0x00009888, .val = 0x166C0010 },
            { .reg = 0x00009888, .val = 0x0C2D5000 },
            { .reg = 0x00009888, .val = 0x0E2D5000 },
            { .reg = 0x00009888, .val = 0x002D4000 },
            { .reg = 0x00009888, .val = 0x022D5000 },
            { .reg = 0x00009888, .val = 0x042D5000 },
            { .reg = 0x00009888, .val = 0x062D1000 },
            { .reg = 0x00009888, .val = 0x102E0154 },
            { .reg = 0x00009888, .val = 0x0C2E5000 },
            { .reg = 0x00009888, .val = 0x0E2E0055 },
            { .reg = 0x00009888, .val = 0x104C8000 },
            { .reg = 0x00009888, .val = 0x124C8000 },
            { .reg = 0x00009888, .val = 0x144C8000 },
            { .reg = 0x00009888, .val = 0x164C2000 },
            { .reg = 0x00009888, .val = 0x044C8000 },
            { .reg = 0x00009888, .val = 0x064CC000 },
            { .reg = 0x00009888, .val = 0x084CC000 },
            { .reg = 0x00009888, .val = 0x0A4C4000 },
            { .reg = 0x00009888, .val = 0x0C4EA000 },
            { .reg = 0x00009888, .val = 0x0E4EA000 },
            { .reg = 0x00009888, .val = 0x004E8000 },
            { .reg = 0x00009888, .val = 0x024EA000 },
            { .reg = 0x00009888, .val = 0x044EA000 },
            { .reg = 0x00009888, .val = 0x064E2000 },
            { .reg = 0x00009888, .val = 0x1C4F5500 },
            { .reg = 0x00009888, .val = 0x1A4F1554 },
            { .reg = 0x00009888, .val = 0x0A640024 },
            { .reg = 0x00009888, .val = 0x10640000 },
            { .reg = 0x00009888, .val = 0x04640000 },
            { .reg = 0x00009888, .val = 0x0C650024 },
            { .reg = 0x00009888, .val = 0x10650000 },
            { .reg = 0x00009888, .val = 0x06650000 },
            { .reg = 0x00009888, .val = 0x0C6C5327 },
            { .reg = 0x00009888, .val = 0x0E6C5425 },
            { .reg = 0x00009888, .val = 0x006C2A00 },
            { .reg = 0x00009888, .val = 0x026C285B },
            { .reg = 0x00009888, .val = 0x046C005C },
            { .reg = 0x00009888, .val = 0x1C6C0000 },
            { .reg = 0x00009888, .val = 0x1A6C0900 },
            { .reg = 0x00009888, .val = 0x1C0F0AA0 },
            { .reg = 0x00009888, .val = 0x180F4000 },
            { .reg = 0x00009888, .val = 0x1A0F02AA },
            { .reg = 0x00009888, .val = 0x1C2C5400 },
            { .reg = 0x00009888, .val = 0x1E2C0001 },
            { .reg = 0x00009888, .val = 0x1A2C5550 },
            { .reg = 0x00009888, .val = 0x1993AA00 },
            { .reg = 0x00009888, .val = 0x03938000 },
            { .reg = 0x00009888, .val = 0x05938000 },
            { .reg = 0x00009888, .val = 0x07938000 },
            { .reg = 0x00009888, .val = 0x09938000 },
            { .reg = 0x00009888, .val = 0x0B938000 },
            { .reg = 0x00009888, .val = 0x0D938000 },
            { .reg = 0x00009888, .val = 0x2B904000 },
            { .reg = 0x00009888, .val = 0x2D904000 },
            { .reg = 0x00009888, .val = 0x2F904000 },
            { .reg = 0x00009888, .val = 0x31904000 },
            { .reg = 0x00009888, .val = 0x15904000 },
            { .reg = 0x00009888, .val = 0x17904000 },
            { .reg = 0x00009888, .val = 0x19904000 },
            { .reg = 0x00009888, .val = 0x1B904000 },
            { .reg = 0x00009888, .val = 0x1D904000 },
            { .reg = 0x00009888, .val = 0x1F904000 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x4B900421 },
            { .reg = 0x00009888, .val = 0x37900000 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4D900001 },
            { .reg = 0x00009888, .val = 0x53900000 },
            { .reg = 0x00009888, .val = 0x43900420 },
            { .reg = 0x00009888, .val = 0x45900021 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x47900000 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      if (perf->devinfo.revision < 0x03) {
         static const struct intel_perf_query_register_prog mux_regs[] = {
            { .reg = 0x000091BC, .val = 0xE0500000 },
            { .reg = 0x00009840, .val = 0x00000080 },
            { .reg = 0x00009888, .val = 0x14640340 },
            { .reg = 0x00009888, .val = 0x14650340 },
            { .reg = 0x00009888, .val = 0x106C6800 },
            { .reg = 0x00009888, .val = 0x126C001E },
            { .reg = 0x00009888, .val = 0x166C0010 },
            { .reg = 0x00009888, .val = 0x0C2D5000 },
            { .reg = 0x00009888, .val = 0x0E2D5000 },
            { .reg = 0x00009888, .val = 0x002D4000 },
            { .reg = 0x00009888, .val = 0x022D5000 },
            { .reg = 0x00009888, .val = 0x042D5000 },
            { .reg = 0x00009888, .val = 0x062D1000 },
            { .reg = 0x00009888, .val = 0x102E0154 },
            { .reg = 0x00009888, .val = 0x0C2E5000 },
            { .reg = 0x00009888, .val = 0x0E2E0055 },
            { .reg = 0x00009888, .val = 0x104C8000 },
            { .reg = 0x00009888, .val = 0x124C8000 },
            { .reg = 0x00009888, .val = 0x144C8000 },
            { .reg = 0x00009888, .val = 0x164C2000 },
            { .reg = 0x00009888, .val = 0x044C8000 },
            { .reg = 0x00009888, .val = 0x064CC000 },
            { .reg = 0x00009888, .val = 0x084CC000 },
            { .reg = 0x00009888, .val = 0x0A4C4000 },
            { .reg = 0x00009888, .val = 0x0C4EA000 },
            { .reg = 0x00009888, .val = 0x0E4EA000 },
            { .reg = 0x00009888, .val = 0x004E8000 },
            { .reg = 0x00009888, .val = 0x024EA000 },
            { .reg = 0x00009888, .val = 0x044EA000 },
            { .reg = 0x00009888, .val = 0x064E2000 },
            { .reg = 0x00009888, .val = 0x1C4F5500 },
            { .reg = 0x00009888, .val = 0x1A4F1554 },
            { .reg = 0x00009888, .val = 0x04642400 },
            { .reg = 0x00009888, .val = 0x22640000 },
            { .reg = 0x00009888, .val = 0x1A640000 },
            { .reg = 0x00009888, .val = 0x06650024 },
            { .reg = 0x00009888, .val = 0x22650000 },
            { .reg = 0x00009888, .val = 0x1C650000 },
            { .reg = 0x00009888, .val = 0x0C6C5327 },
            { .reg = 0x00009888, .val = 0x0E6C5425 },
            { .reg = 0x00009888, .val = 0x006C2A00 },
            { .reg = 0x00009888, .val = 0x026C285B },
            { .reg = 0x00009888, .val = 0x046C005C },
            { .reg = 0x00009888, .val = 0x1C6C0000 },
            { .reg = 0x00009888, .val = 0x1A6C0900 },
            { .reg = 0x00009888, .val = 0x1C0F0AA0 },
            { .reg = 0x00009888, .val = 0x180F4000 },
            { .reg = 0x00009888, .val = 0x1A0F02AA },
            { .reg = 0x00009888, .val = 0x1C2C5400 },
            { .reg = 0x00009888, .val = 0x1E2C0001 },
            { .reg = 0x00009888, .val = 0x1A2C5550 },
            { .reg = 0x00009888, .val = 0x1993AA00 },
            { .reg = 0x00009888, .val = 0x03938000 },
            { .reg = 0x00009888, .val = 0x05938000 },
            { .reg = 0x00009888, .val = 0x07938000 },
            { .reg = 0x00009888, .val = 0x09938000 },
            { .reg = 0x00009888, .val = 0x0B938000 },
            { .reg = 0x00009888, .val = 0x0D938000 },
            { .reg = 0x00009888, .val = 0x2B904000 },
            { .reg = 0x00009888, .val = 0x2D904000 },
            { .reg = 0x00009888, .val = 0x2F904000 },
            { .reg = 0x00009888, .val = 0x31904000 },
            { .reg = 0x00009888, .val = 0x15904000 },
            { .reg = 0x00009888, .val = 0x17904000 },
            { .reg = 0x00009888, .val = 0x19904000 },
            { .reg = 0x00009888, .val = 0x1B904000 },
            { .reg = 0x00009888, .val = 0x1D904000 },
            { .reg = 0x00009888, .val = 0x1F904000 },
            { .reg = 0x00009888, .val = 0x59900000 },
            { .reg = 0x00009888, .val = 0x4B900421 },
            { .reg = 0x00009888, .val = 0x37900000 },
            { .reg = 0x00009888, .val = 0x33900000 },
            { .reg = 0x00009888, .val = 0x4D900001 },
            { .reg = 0x00009888, .val = 0x53900000 },
            { .reg = 0x00009888, .val = 0x43900420 },
            { .reg = 0x00009888, .val = 0x45900021 },
            { .reg = 0x00009888, .val = 0x55900000 },
            { .reg = 0x00009888, .val = 0x47900000 },
         };
         query->config.mux_regs = mux_regs;
         query->config.n_mux_regs = ARRAY_SIZE(mux_regs);
      }

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__l3_1__avg_gpu_core_frequency__max,bxt__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bxt__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bxt__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bxt__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bxt__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bxt__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bxt__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bxt__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bxt__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bxt__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bxt__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bxt__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bxt__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bxt__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bxt__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bxt__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bxt__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bxt__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bxt__l3_1__slm_bytes_read__max,bxt__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bxt__l3_1__slm_bytes_written__max,bxt__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bxt__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bxt__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bxt__l3_1__l3_shader_throughput__max,bxt__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bxt__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,bxt__l3_1__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,bxt__l3_1__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,bxt__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,bxt__l3_1__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,bxt__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "f3d845e6-bfc3-4ffe-b0e5-dddc80c21f07";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x102D7800 },
         { .reg = 0x00009888, .val = 0x122D79E0 },
         { .reg = 0x00009888, .val = 0x0C2F0004 },
         { .reg = 0x00009888, .val = 0x100E3800 },
         { .reg = 0x00009888, .val = 0x180F0005 },
         { .reg = 0x00009888, .val = 0x002D0940 },
         { .reg = 0x00009888, .val = 0x022D802F },
         { .reg = 0x00009888, .val = 0x042D4013 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x0E2E0050 },
         { .reg = 0x00009888, .val = 0x022F0010 },
         { .reg = 0x00009888, .val = 0x002F0000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x040E0480 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x060F0027 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x1A0F0040 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x439014A0 },
         { .reg = 0x00009888, .val = 0x459000A4 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000EFFF },
         { .reg = 0x00002778, .val = 0x00006000 },
         { .reg = 0x0000277C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bxt__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bxt__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bxt__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bxt__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bxt__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bxt__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bxt__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bxt__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bxt__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bxt__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bxt__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bxt__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bxt__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bxt__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bxt__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bxt__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bxt__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bxt__rasterizer_and_pixel_backend__slm_bytes_read__max,bxt__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bxt__rasterizer_and_pixel_backend__slm_bytes_written__max,bxt__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bxt__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bxt__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bxt__rasterizer_and_pixel_backend__l3_shader_throughput__max,bxt__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bxt__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 240, percentage_max_float,bxt__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 244, percentage_max_float,bxt__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 248, percentage_max_float,bxt__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 252, percentage_max_float,bxt__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 256, percentage_max_float,bxt__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,bxt__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler";
   query->symbol_name = "Sampler";
   query->guid = "a53d620b-c14e-49df-bd27-e076b3fb98f3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x121300A0 },
         { .reg = 0x00009888, .val = 0x141600AB },
         { .reg = 0x00009888, .val = 0x123300A0 },
         { .reg = 0x00009888, .val = 0x143600AB },
         { .reg = 0x00009888, .val = 0x125300A0 },
         { .reg = 0x00009888, .val = 0x145600AB },
         { .reg = 0x00009888, .val = 0x0C2D4000 },
         { .reg = 0x00009888, .val = 0x0E2D5000 },
         { .reg = 0x00009888, .val = 0x002D4000 },
         { .reg = 0x00009888, .val = 0x022D5000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x102E01A0 },
         { .reg = 0x00009888, .val = 0x0C2E5000 },
         { .reg = 0x00009888, .val = 0x0E2E0065 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x044C8000 },
         { .reg = 0x00009888, .val = 0x064CC000 },
         { .reg = 0x00009888, .val = 0x084C4000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x024EA000 },
         { .reg = 0x00009888, .val = 0x044E2000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x1C0F0800 },
         { .reg = 0x00009888, .val = 0x180F4000 },
         { .reg = 0x00009888, .val = 0x1A0F023F },
         { .reg = 0x00009888, .val = 0x1E2C0003 },
         { .reg = 0x00009888, .val = 0x1A2CC030 },
         { .reg = 0x00009888, .val = 0x04132180 },
         { .reg = 0x00009888, .val = 0x02130000 },
         { .reg = 0x00009888, .val = 0x0C148000 },
         { .reg = 0x00009888, .val = 0x0E142000 },
         { .reg = 0x00009888, .val = 0x04148000 },
         { .reg = 0x00009888, .val = 0x1E150140 },
         { .reg = 0x00009888, .val = 0x1C150040 },
         { .reg = 0x00009888, .val = 0x0C163000 },
         { .reg = 0x00009888, .val = 0x0E160068 },
         { .reg = 0x00009888, .val = 0x10160000 },
         { .reg = 0x00009888, .val = 0x18160000 },
         { .reg = 0x00009888, .val = 0x0A164000 },
         { .reg = 0x00009888, .val = 0x04330043 },
         { .reg = 0x00009888, .val = 0x02330000 },
         { .reg = 0x00009888, .val = 0x0234A000 },
         { .reg = 0x00009888, .val = 0x04342000 },
         { .reg = 0x00009888, .val = 0x1C350015 },
         { .reg = 0x00009888, .val = 0x02363460 },
         { .reg = 0x00009888, .val = 0x10360000 },
         { .reg = 0x00009888, .val = 0x04360000 },
         { .reg = 0x00009888, .val = 0x06360000 },
         { .reg = 0x00009888, .val = 0x08364000 },
         { .reg = 0x00009888, .val = 0x06530043 },
         { .reg = 0x00009888, .val = 0x02530000 },
         { .reg = 0x00009888, .val = 0x0E548000 },
         { .reg = 0x00009888, .val = 0x00548000 },
         { .reg = 0x00009888, .val = 0x06542000 },
         { .reg = 0x00009888, .val = 0x1E550400 },
         { .reg = 0x00009888, .val = 0x1A552000 },
         { .reg = 0x00009888, .val = 0x1C550100 },
         { .reg = 0x00009888, .val = 0x0E563000 },
         { .reg = 0x00009888, .val = 0x00563400 },
         { .reg = 0x00009888, .val = 0x10560000 },
         { .reg = 0x00009888, .val = 0x18560000 },
         { .reg = 0x00009888, .val = 0x02560000 },
         { .reg = 0x00009888, .val = 0x0C564000 },
         { .reg = 0x00009888, .val = 0x1993A800 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B9014A0 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900001 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900820 },
         { .reg = 0x00009888, .val = 0x45901022 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__sampler__avg_gpu_core_frequency__max,bxt__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__sampler__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__sampler__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__sampler__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__sampler__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__sampler__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__sampler__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__sampler__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__sampler__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__sampler__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bxt__sampler__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bxt__sampler__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bxt__sampler__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bxt__sampler__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bxt__sampler__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bxt__sampler__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bxt__sampler__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bxt__sampler__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bxt__sampler__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bxt__sampler__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bxt__sampler__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bxt__sampler__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bxt__sampler__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bxt__sampler__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bxt__sampler__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bxt__sampler__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bxt__sampler__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bxt__sampler__slm_bytes_read__max,bxt__sampler__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bxt__sampler__slm_bytes_written__max,bxt__sampler__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bxt__sampler__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bxt__sampler__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bxt__sampler__l3_shader_throughput__max,bxt__sampler__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bxt__sampler__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,bxt__sampler__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,bxt__sampler__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,bxt__sampler__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,bxt__sampler__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,bxt__sampler__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,bxt__sampler__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,bxt__sampler__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "8a44b172-6e1d-445f-8937-c06cc487ba39";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A0000 },
         { .reg = 0x00009888, .val = 0x143A0000 },
         { .reg = 0x00009888, .val = 0x145A0000 },
         { .reg = 0x00009888, .val = 0x0C2D4000 },
         { .reg = 0x00009888, .val = 0x0E2D5000 },
         { .reg = 0x00009888, .val = 0x002D4000 },
         { .reg = 0x00009888, .val = 0x022D5000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x102E0150 },
         { .reg = 0x00009888, .val = 0x0C2E5000 },
         { .reg = 0x00009888, .val = 0x0E2E006A },
         { .reg = 0x00009888, .val = 0x124C8000 },
         { .reg = 0x00009888, .val = 0x144C8000 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x044C8000 },
         { .reg = 0x00009888, .val = 0x064C4000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x0E4EA000 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x024E2000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x1C0F0BC0 },
         { .reg = 0x00009888, .val = 0x180F4000 },
         { .reg = 0x00009888, .val = 0x1A0F0302 },
         { .reg = 0x00009888, .val = 0x1E2C0003 },
         { .reg = 0x00009888, .val = 0x1A2C00F0 },
         { .reg = 0x00009888, .val = 0x021A3080 },
         { .reg = 0x00009888, .val = 0x041A31E5 },
         { .reg = 0x00009888, .val = 0x02148000 },
         { .reg = 0x00009888, .val = 0x0414A000 },
         { .reg = 0x00009888, .val = 0x1C150054 },
         { .reg = 0x00009888, .val = 0x06168000 },
         { .reg = 0x00009888, .val = 0x08168000 },
         { .reg = 0x00009888, .val = 0x0A168000 },
         { .reg = 0x00009888, .val = 0x0C3A3280 },
         { .reg = 0x00009888, .val = 0x0E3A0063 },
         { .reg = 0x00009888, .val = 0x063A0061 },
         { .reg = 0x00009888, .val = 0x023A0000 },
         { .reg = 0x00009888, .val = 0x0C348000 },
         { .reg = 0x00009888, .val = 0x0E342000 },
         { .reg = 0x00009888, .val = 0x06342000 },
         { .reg = 0x00009888, .val = 0x1E350140 },
         { .reg = 0x00009888, .val = 0x1C350100 },
         { .reg = 0x00009888, .val = 0x18360028 },
         { .reg = 0x00009888, .val = 0x0C368000 },
         { .reg = 0x00009888, .val = 0x0E5A3080 },
         { .reg = 0x00009888, .val = 0x005A3280 },
         { .reg = 0x00009888, .val = 0x025A0063 },
         { .reg = 0x00009888, .val = 0x0E548000 },
         { .reg = 0x00009888, .val = 0x00548000 },
         { .reg = 0x00009888, .val = 0x02542000 },
         { .reg = 0x00009888, .val = 0x1E550400 },
         { .reg = 0x00009888, .val = 0x1A552000 },
         { .reg = 0x00009888, .val = 0x1C550001 },
         { .reg = 0x00009888, .val = 0x18560080 },
         { .reg = 0x00009888, .val = 0x02568000 },
         { .reg = 0x00009888, .val = 0x04568000 },
         { .reg = 0x00009888, .val = 0x1993A800 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900420 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x45901084 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x00007FFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x00009FFF },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000EFFF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000F3FF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FDFF },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__tdl_1__avg_gpu_core_frequency__max,bxt__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bxt__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bxt__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bxt__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bxt__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bxt__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bxt__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bxt__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bxt__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bxt__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bxt__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bxt__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bxt__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bxt__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bxt__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bxt__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bxt__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bxt__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bxt__tdl_1__slm_bytes_read__max,bxt__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bxt__tdl_1__slm_bytes_written__max,bxt__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bxt__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bxt__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bxt__tdl_1__l3_shader_throughput__max,bxt__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bxt__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 240, percentage_max_float,bxt__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 244, percentage_max_float,bxt__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 248, percentage_max_float,bxt__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 252, percentage_max_float,bxt__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 256, percentage_max_float,bxt__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 260, percentage_max_float,bxt__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,bxt__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "9d4643f8-aa05-482e-8193-070a8ab0d117";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A026B },
         { .reg = 0x00009888, .val = 0x143A0173 },
         { .reg = 0x00009888, .val = 0x145A026B },
         { .reg = 0x00009888, .val = 0x002D4000 },
         { .reg = 0x00009888, .val = 0x022D5000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x0C2E5000 },
         { .reg = 0x00009888, .val = 0x0E2E0069 },
         { .reg = 0x00009888, .val = 0x044C8000 },
         { .reg = 0x00009888, .val = 0x064CC000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x024EA000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x180F6000 },
         { .reg = 0x00009888, .val = 0x1A0F030A },
         { .reg = 0x00009888, .val = 0x1A2C03C0 },
         { .reg = 0x00009888, .val = 0x041A37E7 },
         { .reg = 0x00009888, .val = 0x021A0000 },
         { .reg = 0x00009888, .val = 0x0414A000 },
         { .reg = 0x00009888, .val = 0x1C150050 },
         { .reg = 0x00009888, .val = 0x08168000 },
         { .reg = 0x00009888, .val = 0x0A168000 },
         { .reg = 0x00009888, .val = 0x003A3380 },
         { .reg = 0x00009888, .val = 0x063A006F },
         { .reg = 0x00009888, .val = 0x023A0000 },
         { .reg = 0x00009888, .val = 0x00348000 },
         { .reg = 0x00009888, .val = 0x06342000 },
         { .reg = 0x00009888, .val = 0x1A352000 },
         { .reg = 0x00009888, .val = 0x1C350100 },
         { .reg = 0x00009888, .val = 0x02368000 },
         { .reg = 0x00009888, .val = 0x0C368000 },
         { .reg = 0x00009888, .val = 0x025A37E7 },
         { .reg = 0x00009888, .val = 0x0254A000 },
         { .reg = 0x00009888, .val = 0x1C550005 },
         { .reg = 0x00009888, .val = 0x04568000 },
         { .reg = 0x00009888, .val = 0x06568000 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900020 },
         { .reg = 0x00009888, .val = 0x45901080 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__tdl_2__avg_gpu_core_frequency__max,bxt__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,bxt__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,bxt__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,bxt__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,bxt__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,bxt__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,bxt__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,bxt__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,bxt__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,bxt__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,bxt__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,bxt__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,bxt__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,bxt__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,bxt__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,bxt__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,bxt__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,bxt__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,bxt__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,bxt__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, bxt__tdl_2__slm_bytes_read__max,bxt__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, bxt__tdl_2__slm_bytes_written__max,bxt__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,bxt__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,bxt__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, bxt__tdl_2__l3_shader_throughput__max,bxt__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,bxt__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 240, percentage_max_float,bxt__tdl_2__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 244, percentage_max_float,bxt__tdl_2__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 248, percentage_max_float,bxt__tdl_2__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 252, percentage_max_float,bxt__tdl_2__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 256, percentage_max_float,bxt__tdl_2__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 260, percentage_max_float,bxt__tdl_2__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,bxt__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "fa6ecf21-2cb8-4d0b-9308-6e4a7b4ca87a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A001F },
         { .reg = 0x00009888, .val = 0x143A001F },
         { .reg = 0x00009888, .val = 0x145A001F },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x0E2E0094 },
         { .reg = 0x00009888, .val = 0x084CC000 },
         { .reg = 0x00009888, .val = 0x044EA000 },
         { .reg = 0x00009888, .val = 0x1A0F00E0 },
         { .reg = 0x00009888, .val = 0x1A2C0C00 },
         { .reg = 0x00009888, .val = 0x061A0063 },
         { .reg = 0x00009888, .val = 0x021A0000 },
         { .reg = 0x00009888, .val = 0x06142000 },
         { .reg = 0x00009888, .val = 0x1C150100 },
         { .reg = 0x00009888, .val = 0x0C168000 },
         { .reg = 0x00009888, .val = 0x043A3180 },
         { .reg = 0x00009888, .val = 0x023A0000 },
         { .reg = 0x00009888, .val = 0x04348000 },
         { .reg = 0x00009888, .val = 0x1C350040 },
         { .reg = 0x00009888, .val = 0x0A368000 },
         { .reg = 0x00009888, .val = 0x045A0063 },
         { .reg = 0x00009888, .val = 0x025A0000 },
         { .reg = 0x00009888, .val = 0x04542000 },
         { .reg = 0x00009888, .val = 0x1C550010 },
         { .reg = 0x00009888, .val = 0x08568000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900400 },
         { .reg = 0x00009888, .val = 0x47900004 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00001000 },
         { .reg = 0x0000E558, .val = 0x00003002 },
         { .reg = 0x0000E658, .val = 0x00005004 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00050012 },
         { .reg = 0x0000E55C, .val = 0x00052051 },
         { .reg = 0x0000E65C, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__compute_extra__avg_gpu_core_frequency__max,bxt__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,bxt__compute_extra__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 307, 28, percentage_max_float,bxt__compute_extra__fpu1_active_adjusted__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Gpu Rings Busyness metrics set";
   query->symbol_name = "GpuBusyness";
   query->guid = "c9f5fa3a-d14f-400c-a89a-211206b00ee7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x13805800 },
         { .reg = 0x00009888, .val = 0x05962C00 },
         { .reg = 0x00009888, .val = 0x19950016 },
         { .reg = 0x00009888, .val = 0x21C05800 },
         { .reg = 0x00009888, .val = 0x07800035 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x23810008 },
         { .reg = 0x00009888, .val = 0x07960025 },
         { .reg = 0x00009888, .val = 0x1D960000 },
         { .reg = 0x00009888, .val = 0x0F960000 },
         { .reg = 0x00009888, .val = 0x0B934000 },
         { .reg = 0x00009888, .val = 0x09948000 },
         { .reg = 0x00009888, .val = 0x05950085 },
         { .reg = 0x00009888, .val = 0x11950000 },
         { .reg = 0x00009888, .val = 0x1D950400 },
         { .reg = 0x00009888, .val = 0x0B924000 },
         { .reg = 0x00009888, .val = 0x0D922000 },
         { .reg = 0x00009888, .val = 0x0F922000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x0BC000A5 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900442 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00078000 },
         { .reg = 0x00002774, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__gpu_busyness__avg_gpu_core_frequency__max,bxt__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 309, 24, percentage_max_float,bxt__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 28, percentage_max_float,bxt__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 312, 32, percentage_max_float,bxt__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 36, percentage_max_float,bxt__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 40, percentage_max_float,bxt__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "5ee72f5c-092f-421e-8b70-225f7c3e9612";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x19800000 },
         { .reg = 0x00009888, .val = 0x07800063 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x23810008 },
         { .reg = 0x00009888, .val = 0x1D950400 },
         { .reg = 0x00009888, .val = 0x0F922000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__test_oa__avg_gpu_core_frequency__max,bxt__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,bxt__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,bxt__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,bxt__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,bxt__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,bxt__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,bxt__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,bxt__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,bxt__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,bxt__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_pma__stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "PMA_Stall";
   query->guid = "d49cd0d8-8c7f-4465-94fc-51e08c9050bc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x124C3080 },
         { .reg = 0x00009888, .val = 0x002D1000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x082D5000 },
         { .reg = 0x00009888, .val = 0x0A2D5000 },
         { .reg = 0x00009888, .val = 0x0C2E0400 },
         { .reg = 0x00009888, .val = 0x0E2E5500 },
         { .reg = 0x00009888, .val = 0x102E0001 },
         { .reg = 0x00009888, .val = 0x004C0045 },
         { .reg = 0x00009888, .val = 0x064C2300 },
         { .reg = 0x00009888, .val = 0x084C26C4 },
         { .reg = 0x00009888, .val = 0x0A4C264E },
         { .reg = 0x00009888, .val = 0x164C0000 },
         { .reg = 0x00009888, .val = 0x044C0000 },
         { .reg = 0x00009888, .val = 0x0C4C0000 },
         { .reg = 0x00009888, .val = 0x0E4C0000 },
         { .reg = 0x00009888, .val = 0x01938000 },
         { .reg = 0x00009888, .val = 0x0F938000 },
         { .reg = 0x00009888, .val = 0x199300AA },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29904000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00E00021 },
         { .reg = 0x00002774, .val = 0x0007FFF8 },
         { .reg = 0x00002778, .val = 0x07000101 },
         { .reg = 0x0000277C, .val = 0x0038FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__pma__stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__pma__stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__pma__stall__avg_gpu_core_frequency__max,bxt__pma__stall__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 24, percentage_max_float,bxt__pma__stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
bxt_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "AsyncCompute metrics set";
   query->symbol_name = "AsyncCompute";
   query->guid = "b890cb09-42f7-4644-8aac-a7beca4b9181";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00051050 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00061060 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,bxt__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,bxt__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, bxt__async_compute__avg_gpu_core_frequency__max,bxt__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,bxt__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,bxt__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,bxt__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,bxt__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,bxt__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,bxt__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,bxt__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 150, 80, percentage_max_float,bxt__async_compute__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 124, 84, percentage_max_float,bxt__async_compute__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 127, 88, percentage_max_float,bxt__async_compute__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 331, 92, percentage_max_float,bxt__async_compute__cs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,bxt__async_compute__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 125, 100, percentage_max_float,bxt__async_compute__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,bxt__async_compute__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 332, 108, percentage_max_float,bxt__async_compute__cs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 154, 112, percentage_max_float,bxt__async_compute__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 10, 116, percentage_max_float,bxt__async_compute__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 120, percentage_max_float,bxt__async_compute__eu_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_bxt(struct intel_perf_config *perf)
{
   bxt_register_render_basic_counter_query(perf);
   bxt_register_compute_basic_counter_query(perf);
   bxt_register_render_pipe_profile_counter_query(perf);
   bxt_register_memory_reads_counter_query(perf);
   bxt_register_memory_writes_counter_query(perf);
   bxt_register_compute_extended_counter_query(perf);
   bxt_register_compute_l3_cache_counter_query(perf);
   bxt_register_hdc_and_sf_counter_query(perf);
   bxt_register_l3_1_counter_query(perf);
   bxt_register_rasterizer_and_pixel_backend_counter_query(perf);
   bxt_register_sampler_counter_query(perf);
   bxt_register_tdl_1_counter_query(perf);
   bxt_register_tdl_2_counter_query(perf);
   bxt_register_compute_extra_counter_query(perf);
   bxt_register_gpu_busyness_counter_query(perf);
   bxt_register_test_oa_counter_query(perf);
   bxt_register_pma__stall_counter_query(perf);
   bxt_register_async_compute_counter_query(perf);
}


static void
glk_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 52);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "d72df5c7-5b4a-4274-a43f-00b0fd51fc68";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C00F0 },
         { .reg = 0x00009888, .val = 0x12120280 },
         { .reg = 0x00009888, .val = 0x12320280 },
         { .reg = 0x00009888, .val = 0x11930317 },
         { .reg = 0x00009888, .val = 0x159303DF },
         { .reg = 0x00009888, .val = 0x3F900C00 },
         { .reg = 0x00009888, .val = 0x419000A0 },
         { .reg = 0x00009888, .val = 0x002D1000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x082D5000 },
         { .reg = 0x00009888, .val = 0x0A2D1000 },
         { .reg = 0x00009888, .val = 0x0C2E0800 },
         { .reg = 0x00009888, .val = 0x0E2E5900 },
         { .reg = 0x00009888, .val = 0x0A4C8000 },
         { .reg = 0x00009888, .val = 0x0C4C8000 },
         { .reg = 0x00009888, .val = 0x0E4C4000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E2000 },
         { .reg = 0x00009888, .val = 0x1C4F0010 },
         { .reg = 0x00009888, .val = 0x0A6C0053 },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1A0FCC00 },
         { .reg = 0x00009888, .val = 0x1C0F0002 },
         { .reg = 0x00009888, .val = 0x1C2C0040 },
         { .reg = 0x00009888, .val = 0x00101000 },
         { .reg = 0x00009888, .val = 0x04101000 },
         { .reg = 0x00009888, .val = 0x00114000 },
         { .reg = 0x00009888, .val = 0x08114000 },
         { .reg = 0x00009888, .val = 0x00120020 },
         { .reg = 0x00009888, .val = 0x08120021 },
         { .reg = 0x00009888, .val = 0x00141000 },
         { .reg = 0x00009888, .val = 0x08141000 },
         { .reg = 0x00009888, .val = 0x02308000 },
         { .reg = 0x00009888, .val = 0x04302000 },
         { .reg = 0x00009888, .val = 0x06318000 },
         { .reg = 0x00009888, .val = 0x08318000 },
         { .reg = 0x00009888, .val = 0x06320800 },
         { .reg = 0x00009888, .val = 0x08320840 },
         { .reg = 0x00009888, .val = 0x00320000 },
         { .reg = 0x00009888, .val = 0x06344000 },
         { .reg = 0x00009888, .val = 0x08344000 },
         { .reg = 0x00009888, .val = 0x0D931831 },
         { .reg = 0x00009888, .val = 0x0F939F3F },
         { .reg = 0x00009888, .val = 0x01939E80 },
         { .reg = 0x00009888, .val = 0x039303BC },
         { .reg = 0x00009888, .val = 0x0593000E },
         { .reg = 0x00009888, .val = 0x1993002A },
         { .reg = 0x00009888, .val = 0x07930000 },
         { .reg = 0x00009888, .val = 0x09930000 },
         { .reg = 0x00009888, .val = 0x1D900177 },
         { .reg = 0x00009888, .val = 0x1F900187 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x53901110 },
         { .reg = 0x00009888, .val = 0x43900423 },
         { .reg = 0x00009888, .val = 0x55900111 },
         { .reg = 0x00009888, .val = 0x47900C02 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900020 },
         { .reg = 0x00009888, .val = 0x59901111 },
         { .reg = 0x00009888, .val = 0x4B900421 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900001 },
         { .reg = 0x00009888, .val = 0x45900821 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__render_basic__avg_gpu_core_frequency__max,glk__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,glk__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,glk__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,glk__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,glk__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,glk__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,glk__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,glk__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,glk__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,glk__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,glk__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,glk__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,glk__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,glk__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,glk__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,glk__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,glk__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 112, percentage_max_float,glk__render_basic__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 131, 116, percentage_max_float,glk__render_basic__sampler0_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 132, 120, percentage_max_float,glk__render_basic__sampler1_busy__read);
      }

      intel_perf_query_add_counter_float(query, 133, 124, percentage_max_float,glk__render_basic__samplers_busy__read);

      if (perf->sys_vars.subslice_mask & 0x09) {
         intel_perf_query_add_counter_float(query, 134, 128, percentage_max_float,glk__render_basic__sampler0_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 0x12) {
         intel_perf_query_add_counter_float(query, 135, 132, percentage_max_float,glk__render_basic__sampler1_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,glk__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,glk__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,glk__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,glk__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,glk__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,glk__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,glk__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,glk__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,glk__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 208, NULL,glk__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 216, glk__render_basic__slm_bytes_read__max,glk__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 224, glk__render_basic__slm_bytes_written__max,glk__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 232, NULL,glk__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 240, NULL,glk__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 144, 248, NULL,glk__render_basic__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 256, NULL,glk__render_basic__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 264, glk__render_basic__l3_sampler_throughput__max,glk__render_basic__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 272, glk__render_basic__l3_shader_throughput__max,glk__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 280, NULL,glk__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 53, 288, glk__render_basic__gti_vf_throughput__max,glk__render_basic__gti_vf_throughput__read);

      intel_perf_query_add_counter_uint64(query, 54, 296, glk__render_basic__gti_depth_throughput__max,glk__render_basic__gti_depth_throughput__read);

      intel_perf_query_add_counter_uint64(query, 55, 304, glk__render_basic__gti_rcc_throughput__max,glk__render_basic__gti_rcc_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 312, glk__render_basic__gti_l3_throughput__max,glk__render_basic__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 148, 320, glk__render_basic__gti_hdc_lookups_throughput__max,glk__render_basic__gti_hdc_lookups_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 328, glk__render_basic__gti_read_throughput__max,glk__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 336, glk__render_basic__gti_write_throughput__max,glk__render_basic__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 149, 344, percentage_max_float,glk__render_basic__sampler_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "814285f6-354d-41d2-ba49-e24e622714a0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x124F1C00 },
         { .reg = 0x00009888, .val = 0x39900340 },
         { .reg = 0x00009888, .val = 0x3F900C00 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x002D5000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x082D4000 },
         { .reg = 0x00009888, .val = 0x0A2D1000 },
         { .reg = 0x00009888, .val = 0x0C2D5000 },
         { .reg = 0x00009888, .val = 0x0E2D4000 },
         { .reg = 0x00009888, .val = 0x0C2E1400 },
         { .reg = 0x00009888, .val = 0x0E2E5100 },
         { .reg = 0x00009888, .val = 0x102E0114 },
         { .reg = 0x00009888, .val = 0x044CC000 },
         { .reg = 0x00009888, .val = 0x0A4C8000 },
         { .reg = 0x00009888, .val = 0x0C4C8000 },
         { .reg = 0x00009888, .val = 0x0E4C4000 },
         { .reg = 0x00009888, .val = 0x104C8000 },
         { .reg = 0x00009888, .val = 0x124C8000 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x004EA000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084E8000 },
         { .reg = 0x00009888, .val = 0x0A4E2000 },
         { .reg = 0x00009888, .val = 0x0C4EA000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x004F6B42 },
         { .reg = 0x00009888, .val = 0x064F6200 },
         { .reg = 0x00009888, .val = 0x084F4100 },
         { .reg = 0x00009888, .val = 0x0A4F0061 },
         { .reg = 0x00009888, .val = 0x0C4F6C4C },
         { .reg = 0x00009888, .val = 0x0E4F4B00 },
         { .reg = 0x00009888, .val = 0x1A4F0000 },
         { .reg = 0x00009888, .val = 0x1C4F0000 },
         { .reg = 0x00009888, .val = 0x180F5000 },
         { .reg = 0x00009888, .val = 0x1A0F8800 },
         { .reg = 0x00009888, .val = 0x1C0F08A2 },
         { .reg = 0x00009888, .val = 0x182C4000 },
         { .reg = 0x00009888, .val = 0x1C2C1451 },
         { .reg = 0x00009888, .val = 0x1E2C0001 },
         { .reg = 0x00009888, .val = 0x1A2C0010 },
         { .reg = 0x00009888, .val = 0x01938000 },
         { .reg = 0x00009888, .val = 0x0F938000 },
         { .reg = 0x00009888, .val = 0x19938A28 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x19900177 },
         { .reg = 0x00009888, .val = 0x1B900178 },
         { .reg = 0x00009888, .val = 0x1D900125 },
         { .reg = 0x00009888, .val = 0x1F900123 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x53901000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x55900111 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__compute_basic__avg_gpu_core_frequency__max,glk__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,glk__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,glk__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,glk__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, glk__compute_basic__eu_avg_ipc_rate__max,glk__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,glk__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,glk__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,glk__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,glk__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,glk__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,glk__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,glk__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,glk__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,glk__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,glk__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,glk__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, glk__compute_basic__slm_bytes_read__max,glk__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, glk__compute_basic__slm_bytes_written__max,glk__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,glk__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,glk__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, glk__compute_basic__l3_shader_throughput__max,glk__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,glk__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, glk__compute_basic__typed_bytes_read__max,glk__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, glk__compute_basic__typed_bytes_written__max,glk__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, glk__compute_basic__untyped_bytes_read__max,glk__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, glk__compute_basic__untyped_bytes_written__max,glk__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 57, 264, glk__compute_basic__gti_read_throughput__max,glk__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 272, glk__compute_basic__gti_write_throughput__max,glk__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "07d397a6-b3e6-49f6-9433-a4f293d55978";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x0C2E001F },
         { .reg = 0x00009888, .val = 0x0A2F0000 },
         { .reg = 0x00009888, .val = 0x10186800 },
         { .reg = 0x00009888, .val = 0x11810019 },
         { .reg = 0x00009888, .val = 0x15810013 },
         { .reg = 0x00009888, .val = 0x13820020 },
         { .reg = 0x00009888, .val = 0x11830020 },
         { .reg = 0x00009888, .val = 0x17840000 },
         { .reg = 0x00009888, .val = 0x11860007 },
         { .reg = 0x00009888, .val = 0x21860000 },
         { .reg = 0x00009888, .val = 0x178703E0 },
         { .reg = 0x00009888, .val = 0x0C2D8000 },
         { .reg = 0x00009888, .val = 0x042D4000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x022E5400 },
         { .reg = 0x00009888, .val = 0x002E0000 },
         { .reg = 0x00009888, .val = 0x0E2E0080 },
         { .reg = 0x00009888, .val = 0x082F0040 },
         { .reg = 0x00009888, .val = 0x002F0000 },
         { .reg = 0x00009888, .val = 0x06143000 },
         { .reg = 0x00009888, .val = 0x06174000 },
         { .reg = 0x00009888, .val = 0x06180012 },
         { .reg = 0x00009888, .val = 0x00180000 },
         { .reg = 0x00009888, .val = 0x0D804000 },
         { .reg = 0x00009888, .val = 0x0F804000 },
         { .reg = 0x00009888, .val = 0x05804000 },
         { .reg = 0x00009888, .val = 0x09810200 },
         { .reg = 0x00009888, .val = 0x0B810030 },
         { .reg = 0x00009888, .val = 0x03810003 },
         { .reg = 0x00009888, .val = 0x21819140 },
         { .reg = 0x00009888, .val = 0x23819050 },
         { .reg = 0x00009888, .val = 0x25810018 },
         { .reg = 0x00009888, .val = 0x0B820980 },
         { .reg = 0x00009888, .val = 0x03820D80 },
         { .reg = 0x00009888, .val = 0x11820000 },
         { .reg = 0x00009888, .val = 0x0182C000 },
         { .reg = 0x00009888, .val = 0x07828000 },
         { .reg = 0x00009888, .val = 0x09824000 },
         { .reg = 0x00009888, .val = 0x0F828000 },
         { .reg = 0x00009888, .val = 0x0D830004 },
         { .reg = 0x00009888, .val = 0x0583000C },
         { .reg = 0x00009888, .val = 0x0F831000 },
         { .reg = 0x00009888, .val = 0x01848072 },
         { .reg = 0x00009888, .val = 0x11840000 },
         { .reg = 0x00009888, .val = 0x07848000 },
         { .reg = 0x00009888, .val = 0x09844000 },
         { .reg = 0x00009888, .val = 0x0F848000 },
         { .reg = 0x00009888, .val = 0x07860000 },
         { .reg = 0x00009888, .val = 0x09860092 },
         { .reg = 0x00009888, .val = 0x0F860400 },
         { .reg = 0x00009888, .val = 0x01869100 },
         { .reg = 0x00009888, .val = 0x0F870065 },
         { .reg = 0x00009888, .val = 0x01870000 },
         { .reg = 0x00009888, .val = 0x19930800 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x1B952000 },
         { .reg = 0x00009888, .val = 0x1D955055 },
         { .reg = 0x00009888, .val = 0x1F951455 },
         { .reg = 0x00009888, .val = 0x0992A000 },
         { .reg = 0x00009888, .val = 0x0F928000 },
         { .reg = 0x00009888, .val = 0x1192A800 },
         { .reg = 0x00009888, .val = 0x1392028A },
         { .reg = 0x00009888, .val = 0x0B92A000 },
         { .reg = 0x00009888, .val = 0x0D922000 },
         { .reg = 0x00009888, .val = 0x13908000 },
         { .reg = 0x00009888, .val = 0x21908000 },
         { .reg = 0x00009888, .val = 0x23908000 },
         { .reg = 0x00009888, .val = 0x25908000 },
         { .reg = 0x00009888, .val = 0x27908000 },
         { .reg = 0x00009888, .val = 0x29908000 },
         { .reg = 0x00009888, .val = 0x2B908000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F908000 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x15908000 },
         { .reg = 0x00009888, .val = 0x17908000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900C01 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900863 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900061 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900000 },
         { .reg = 0x00009888, .val = 0x45900C22 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFEA },
         { .reg = 0x00002774, .val = 0x00007FFC },
         { .reg = 0x00002778, .val = 0x0007AFFA },
         { .reg = 0x0000277C, .val = 0x0000F5FD },
         { .reg = 0x00002780, .val = 0x00079FFA },
         { .reg = 0x00002784, .val = 0x0000F3FB },
         { .reg = 0x00002788, .val = 0x0007BF7A },
         { .reg = 0x0000278C, .val = 0x0000F7E7 },
         { .reg = 0x00002790, .val = 0x0007FEFA },
         { .reg = 0x00002794, .val = 0x0000F7CF },
         { .reg = 0x00002798, .val = 0x00077FFA },
         { .reg = 0x0000279C, .val = 0x0000EFDF },
         { .reg = 0x000027A0, .val = 0x0006FFFA },
         { .reg = 0x000027A4, .val = 0x0000CFBF },
         { .reg = 0x000027A8, .val = 0x0003FFFA },
         { .reg = 0x000027AC, .val = 0x00005F7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__render_pipe_profile__avg_gpu_core_frequency__max,glk__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,glk__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,glk__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,glk__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,glk__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,glk__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,glk__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,glk__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,glk__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,glk__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, glk__render_pipe_profile__slm_bytes_read__max,glk__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, glk__render_pipe_profile__slm_bytes_written__max,glk__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,glk__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,glk__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, glk__render_pipe_profile__l3_shader_throughput__max,glk__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,glk__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, NULL,glk__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, NULL,glk__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, NULL,glk__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, NULL,glk__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, NULL,glk__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, NULL,glk__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, NULL,glk__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, NULL,glk__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, NULL,glk__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, NULL,glk__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, NULL,glk__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, NULL,glk__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, NULL,glk__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, NULL,glk__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, NULL,glk__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, NULL,glk__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_memory_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Reads Distribution metrics set";
   query->symbol_name = "MemoryReads";
   query->guid = "1a356946-5428-450b-a2f0-89f8783a302d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x19800343 },
         { .reg = 0x00009888, .val = 0x39900340 },
         { .reg = 0x00009888, .val = 0x3F901000 },
         { .reg = 0x00009888, .val = 0x41900003 },
         { .reg = 0x00009888, .val = 0x03803180 },
         { .reg = 0x00009888, .val = 0x058035E2 },
         { .reg = 0x00009888, .val = 0x0780006A },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x2181A000 },
         { .reg = 0x00009888, .val = 0x2381000A },
         { .reg = 0x00009888, .val = 0x1D950550 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D92A000 },
         { .reg = 0x00009888, .val = 0x0F922000 },
         { .reg = 0x00009888, .val = 0x13900170 },
         { .reg = 0x00009888, .val = 0x21900171 },
         { .reg = 0x00009888, .val = 0x23900172 },
         { .reg = 0x00009888, .val = 0x25900173 },
         { .reg = 0x00009888, .val = 0x27900174 },
         { .reg = 0x00009888, .val = 0x29900175 },
         { .reg = 0x00009888, .val = 0x2B900176 },
         { .reg = 0x00009888, .val = 0x2D900177 },
         { .reg = 0x00009888, .val = 0x2F90017F },
         { .reg = 0x00009888, .val = 0x31900125 },
         { .reg = 0x00009888, .val = 0x15900123 },
         { .reg = 0x00009888, .val = 0x17900121 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43901084 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47901080 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49901084 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B901084 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900004 },
         { .reg = 0x00009888, .val = 0x45900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F872 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__memory_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__memory_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__memory_reads__avg_gpu_core_frequency__max,glk__memory_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__memory_reads__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__memory_reads__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__memory_reads__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__memory_reads__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__memory_reads__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__memory_reads__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__memory_reads__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__memory_reads__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__memory_reads__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,glk__memory_reads__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,glk__memory_reads__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,glk__memory_reads__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,glk__memory_reads__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,glk__memory_reads__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,glk__memory_reads__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,glk__memory_reads__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,glk__memory_reads__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,glk__memory_reads__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, glk__memory_reads__slm_bytes_read__max,glk__memory_reads__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, glk__memory_reads__slm_bytes_written__max,glk__memory_reads__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,glk__memory_reads__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,glk__memory_reads__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 192, NULL,glk__memory_reads__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 95, 200, NULL,glk__memory_reads__gti_cmd_streamer_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 96, 208, NULL,glk__memory_reads__gti_rs_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 97, 216, NULL,glk__memory_reads__gti_vf_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 98, 224, NULL,glk__memory_reads__gti_rcc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 99, 232, NULL,glk__memory_reads__gti_msc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 173, 240, NULL,glk__memory_reads__gti_hiz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 174, 248, NULL,glk__memory_reads__gti_stc_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 175, 256, NULL,glk__memory_reads__gti_rcz_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 176, 264, NULL,glk__memory_reads__gti_memory_reads__read);

      intel_perf_query_add_counter_uint64(query, 177, 272, NULL,glk__memory_reads__gti_l3_bank0_reads__read);

      intel_perf_query_add_counter_uint64(query, 178, 280, NULL,glk__memory_reads__gti_l3_bank1_reads__read);

      intel_perf_query_add_counter_uint64(query, 179, 288, NULL,glk__memory_reads__gti_l3_bank2_reads__read);

      intel_perf_query_add_counter_uint64(query, 180, 296, NULL,glk__memory_reads__gti_l3_bank3_reads__read);

      intel_perf_query_add_counter_uint64(query, 181, 304, NULL,glk__memory_reads__gti_l3_reads__read);

      intel_perf_query_add_counter_uint64(query, 182, 312, NULL,glk__memory_reads__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_memory_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Memory Writes Distribution metrics set";
   query->symbol_name = "MemoryWrites";
   query->guid = "5299be9d-7a61-4c99-9f81-f87e6c5aaca9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x19800343 },
         { .reg = 0x00009888, .val = 0x39900340 },
         { .reg = 0x00009888, .val = 0x3F900000 },
         { .reg = 0x00009888, .val = 0x41900080 },
         { .reg = 0x00009888, .val = 0x03803180 },
         { .reg = 0x00009888, .val = 0x058035E2 },
         { .reg = 0x00009888, .val = 0x0780006A },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x2181A000 },
         { .reg = 0x00009888, .val = 0x2381000A },
         { .reg = 0x00009888, .val = 0x1D950550 },
         { .reg = 0x00009888, .val = 0x0B928000 },
         { .reg = 0x00009888, .val = 0x0D92A000 },
         { .reg = 0x00009888, .val = 0x0F922000 },
         { .reg = 0x00009888, .val = 0x13900180 },
         { .reg = 0x00009888, .val = 0x21900181 },
         { .reg = 0x00009888, .val = 0x23900182 },
         { .reg = 0x00009888, .val = 0x25900183 },
         { .reg = 0x00009888, .val = 0x27900184 },
         { .reg = 0x00009888, .val = 0x29900185 },
         { .reg = 0x00009888, .val = 0x2B900186 },
         { .reg = 0x00009888, .val = 0x2D900187 },
         { .reg = 0x00009888, .val = 0x2F900170 },
         { .reg = 0x00009888, .val = 0x31900125 },
         { .reg = 0x00009888, .val = 0x15900123 },
         { .reg = 0x00009888, .val = 0x17900121 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x19908000 },
         { .reg = 0x00009888, .val = 0x1B908000 },
         { .reg = 0x00009888, .val = 0x1D908000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43901084 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47901080 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49901084 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B901084 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900004 },
         { .reg = 0x00009888, .val = 0x45900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000272C, .val = 0xFFFFFFFF },
         { .reg = 0x00002728, .val = 0xFFFFFFFF },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x0000271C, .val = 0xFFFFFFFF },
         { .reg = 0x00002718, .val = 0xFFFFFFFF },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x0000274C, .val = 0x86543210 },
         { .reg = 0x00002748, .val = 0x86543210 },
         { .reg = 0x00002744, .val = 0x00006667 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x0000275C, .val = 0x86543210 },
         { .reg = 0x00002758, .val = 0x86543210 },
         { .reg = 0x00002754, .val = 0x00006465 },
         { .reg = 0x00002750, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007F81A },
         { .reg = 0x00002774, .val = 0x0000FE00 },
         { .reg = 0x00002778, .val = 0x0007F82A },
         { .reg = 0x0000277C, .val = 0x0000FE00 },
         { .reg = 0x00002780, .val = 0x0007F822 },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x0007F8BA },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x0007F87A },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x0007F8EA },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x0007F8E2 },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x0007F8F2 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00015014 },
         { .reg = 0x0000E658, .val = 0x00025024 },
         { .reg = 0x0000E758, .val = 0x00035034 },
         { .reg = 0x0000E45C, .val = 0x00045044 },
         { .reg = 0x0000E55C, .val = 0x00055054 },
         { .reg = 0x0000E65C, .val = 0x00065064 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__memory_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__memory_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__memory_writes__avg_gpu_core_frequency__max,glk__memory_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__memory_writes__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__memory_writes__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__memory_writes__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__memory_writes__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__memory_writes__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__memory_writes__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__memory_writes__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__memory_writes__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__memory_writes__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,glk__memory_writes__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,glk__memory_writes__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,glk__memory_writes__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,glk__memory_writes__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,glk__memory_writes__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,glk__memory_writes__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,glk__memory_writes__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,glk__memory_writes__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,glk__memory_writes__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, glk__memory_writes__slm_bytes_read__max,glk__memory_writes__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, glk__memory_writes__slm_bytes_written__max,glk__memory_writes__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,glk__memory_writes__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,glk__memory_writes__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, glk__memory_writes__l3_shader_throughput__max,glk__memory_writes__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,glk__memory_writes__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 106, 208, NULL,glk__memory_writes__gti_cmd_streamer_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 107, 216, NULL,glk__memory_writes__gti_so_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 108, 224, NULL,glk__memory_writes__gti_rcc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 109, 232, NULL,glk__memory_writes__gti_msc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 110, 240, NULL,glk__memory_writes__gti_hiz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 111, 248, NULL,glk__memory_writes__gti_stc_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 112, 256, NULL,glk__memory_writes__gti_rcz_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 183, 264, NULL,glk__memory_writes__gti_memory_writes__read);

      intel_perf_query_add_counter_uint64(query, 184, 272, NULL,glk__memory_writes__gti_l3_bank0_writes__read);

      intel_perf_query_add_counter_uint64(query, 185, 280, NULL,glk__memory_writes__gti_l3_bank1_writes__read);

      intel_perf_query_add_counter_uint64(query, 186, 288, NULL,glk__memory_writes__gti_l3_bank2_writes__read);

      intel_perf_query_add_counter_uint64(query, 187, 296, NULL,glk__memory_writes__gti_l3_bank3_writes__read);

      intel_perf_query_add_counter_uint64(query, 113, 304, NULL,glk__memory_writes__gti_l3_writes__read);

      intel_perf_query_add_counter_uint64(query, 188, 312, NULL,glk__memory_writes__gti_ring_accesses__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Compute Metrics Extended set";
   query->symbol_name = "ComputeExtended";
   query->guid = "bc9bcff2-459a-4cbc-986d-a84b077153f3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F00E0 },
         { .reg = 0x00009888, .val = 0x141C0160 },
         { .reg = 0x00009888, .val = 0x161C0015 },
         { .reg = 0x00009888, .val = 0x181C0120 },
         { .reg = 0x00009888, .val = 0x002D5000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x082D5000 },
         { .reg = 0x00009888, .val = 0x0A2D5000 },
         { .reg = 0x00009888, .val = 0x0C2D5000 },
         { .reg = 0x00009888, .val = 0x0E2D5000 },
         { .reg = 0x00009888, .val = 0x022D5000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x0C2E5400 },
         { .reg = 0x00009888, .val = 0x0E2E5515 },
         { .reg = 0x00009888, .val = 0x102E0155 },
         { .reg = 0x00009888, .val = 0x044CC000 },
         { .reg = 0x00009888, .val = 0x0A4C8000 },
         { .reg = 0x00009888, .val = 0x0C4CC000 },
         { .reg = 0x00009888, .val = 0x0E4CC000 },
         { .reg = 0x00009888, .val = 0x104C8000 },
         { .reg = 0x00009888, .val = 0x124C8000 },
         { .reg = 0x00009888, .val = 0x144C8000 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x064CC000 },
         { .reg = 0x00009888, .val = 0x084CC000 },
         { .reg = 0x00009888, .val = 0x004EA000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084EA000 },
         { .reg = 0x00009888, .val = 0x0A4EA000 },
         { .reg = 0x00009888, .val = 0x0C4EA000 },
         { .reg = 0x00009888, .val = 0x0E4EA000 },
         { .reg = 0x00009888, .val = 0x024EA000 },
         { .reg = 0x00009888, .val = 0x044EA000 },
         { .reg = 0x00009888, .val = 0x0E4F4B41 },
         { .reg = 0x00009888, .val = 0x004F4200 },
         { .reg = 0x00009888, .val = 0x024F404C },
         { .reg = 0x00009888, .val = 0x1C4F0000 },
         { .reg = 0x00009888, .val = 0x1A4F0000 },
         { .reg = 0x00009888, .val = 0x001B4000 },
         { .reg = 0x00009888, .val = 0x061B8000 },
         { .reg = 0x00009888, .val = 0x081BC000 },
         { .reg = 0x00009888, .val = 0x0A1BC000 },
         { .reg = 0x00009888, .val = 0x0C1BC000 },
         { .reg = 0x00009888, .val = 0x041BC000 },
         { .reg = 0x00009888, .val = 0x001C0031 },
         { .reg = 0x00009888, .val = 0x061C1900 },
         { .reg = 0x00009888, .val = 0x081C1A33 },
         { .reg = 0x00009888, .val = 0x0A1C1B35 },
         { .reg = 0x00009888, .val = 0x0C1C3337 },
         { .reg = 0x00009888, .val = 0x041C31C7 },
         { .reg = 0x00009888, .val = 0x180F5000 },
         { .reg = 0x00009888, .val = 0x1A0FA8AA },
         { .reg = 0x00009888, .val = 0x1C0F0AAA },
         { .reg = 0x00009888, .val = 0x182C8000 },
         { .reg = 0x00009888, .val = 0x1C2C6AAA },
         { .reg = 0x00009888, .val = 0x1E2C0001 },
         { .reg = 0x00009888, .val = 0x1A2C2950 },
         { .reg = 0x00009888, .val = 0x01938000 },
         { .reg = 0x00009888, .val = 0x0F938000 },
         { .reg = 0x00009888, .val = 0x1993AAAA },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29904000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900420 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900400 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900001 },
         { .reg = 0x00009888, .val = 0x45900001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FC2A },
         { .reg = 0x00002774, .val = 0x0000BF00 },
         { .reg = 0x00002778, .val = 0x0007FC6A },
         { .reg = 0x0000277C, .val = 0x0000BF00 },
         { .reg = 0x00002780, .val = 0x0007FC92 },
         { .reg = 0x00002784, .val = 0x0000BF00 },
         { .reg = 0x00002788, .val = 0x0007FCA2 },
         { .reg = 0x0000278C, .val = 0x0000BF00 },
         { .reg = 0x00002790, .val = 0x0007FC32 },
         { .reg = 0x00002794, .val = 0x0000BF00 },
         { .reg = 0x00002798, .val = 0x0007FC9A },
         { .reg = 0x0000279C, .val = 0x0000BF00 },
         { .reg = 0x000027A0, .val = 0x0007FE6A },
         { .reg = 0x000027A4, .val = 0x0000BF00 },
         { .reg = 0x000027A8, .val = 0x0007FE7A },
         { .reg = 0x000027AC, .val = 0x0000BF00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00778008 },
         { .reg = 0x0000E45C, .val = 0x00088078 },
         { .reg = 0x0000E55C, .val = 0x00808708 },
         { .reg = 0x0000E65C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__compute_extended__avg_gpu_core_frequency__max,glk__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 8, 24, NULL,glk__compute_extended__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 32, percentage_max_float,glk__compute_extended__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 36, percentage_max_float,glk__compute_extended__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 40, percentage_max_float,glk__compute_extended__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 44, percentage_max_float,glk__compute_extended__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 48, percentage_max_float,glk__compute_extended__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 52, glk__compute_extended__eu_avg_ipc_rate__max,glk__compute_extended__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 56, percentage_max_float,glk__compute_extended__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 60, percentage_max_float,glk__compute_extended__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 136, 64, NULL,glk__compute_extended__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 72, NULL,glk__compute_extended__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 80, glk__compute_extended__slm_bytes_read__max,glk__compute_extended__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 88, glk__compute_extended__slm_bytes_written__max,glk__compute_extended__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 96, NULL,glk__compute_extended__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 104, NULL,glk__compute_extended__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 112, glk__compute_extended__l3_shader_throughput__max,glk__compute_extended__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 120, NULL,glk__compute_extended__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 78, 128, NULL,glk__compute_extended__eu_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 79, 136, NULL,glk__compute_extended__eu_typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 80, 144, NULL,glk__compute_extended__eu_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 81, 152, NULL,glk__compute_extended__eu_typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 82, 160, NULL,glk__compute_extended__eu_untyped_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 83, 168, NULL,glk__compute_extended__eu_typed_atomics0__read);

      intel_perf_query_add_counter_uint64(query, 189, 176, NULL,glk__compute_extended__eu_a64_untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 190, 184, NULL,glk__compute_extended__eu_a64_untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 85, 192, NULL,glk__compute_extended__typed_reads0__read);

      intel_perf_query_add_counter_uint64(query, 86, 200, NULL,glk__compute_extended__typed_writes0__read);

      intel_perf_query_add_counter_uint64(query, 87, 208, NULL,glk__compute_extended__untyped_reads0__read);

      intel_perf_query_add_counter_uint64(query, 88, 216, NULL,glk__compute_extended__untyped_writes0__read);

      intel_perf_query_add_counter_uint64(query, 89, 224, NULL,glk__compute_extended__typed_atomics0__read);

      intel_perf_query_add_counter_float(query, 90, 232, NULL,glk__compute_extended__typed_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 91, 236, NULL,glk__compute_extended__typed_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 92, 240, NULL,glk__compute_extended__untyped_reads_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 93, 244, NULL,glk__compute_extended__untyped_writes_per_cache_line__read);

      intel_perf_query_add_counter_float(query, 94, 248, NULL,glk__compute_extended__typed_atomics_per_cache_line__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 54);

   query->name = "Compute Metrics L3 Cache set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "88ec931f-5b4a-453a-9db6-a61232b6143d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x166C03B0 },
         { .reg = 0x00009888, .val = 0x1593001E },
         { .reg = 0x00009888, .val = 0x3F900C00 },
         { .reg = 0x00009888, .val = 0x41900000 },
         { .reg = 0x00009888, .val = 0x002D1000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x082D5000 },
         { .reg = 0x00009888, .val = 0x0E2D5000 },
         { .reg = 0x00009888, .val = 0x0C2E0400 },
         { .reg = 0x00009888, .val = 0x0E2E1500 },
         { .reg = 0x00009888, .val = 0x102E0140 },
         { .reg = 0x00009888, .val = 0x044C4000 },
         { .reg = 0x00009888, .val = 0x0A4C8000 },
         { .reg = 0x00009888, .val = 0x0C4CC000 },
         { .reg = 0x00009888, .val = 0x144C8000 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x004E2000 },
         { .reg = 0x00009888, .val = 0x064E8000 },
         { .reg = 0x00009888, .val = 0x084EA000 },
         { .reg = 0x00009888, .val = 0x0E4EA000 },
         { .reg = 0x00009888, .val = 0x1A4F4001 },
         { .reg = 0x00009888, .val = 0x1C4F5005 },
         { .reg = 0x00009888, .val = 0x006C0051 },
         { .reg = 0x00009888, .val = 0x066C5000 },
         { .reg = 0x00009888, .val = 0x086C5C5D },
         { .reg = 0x00009888, .val = 0x0E6C5E5F },
         { .reg = 0x00009888, .val = 0x106C0000 },
         { .reg = 0x00009888, .val = 0x146C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0000 },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x180F1000 },
         { .reg = 0x00009888, .val = 0x1A0FA800 },
         { .reg = 0x00009888, .val = 0x1C0F0A00 },
         { .reg = 0x00009888, .val = 0x182C4000 },
         { .reg = 0x00009888, .val = 0x1C2C4015 },
         { .reg = 0x00009888, .val = 0x1E2C0001 },
         { .reg = 0x00009888, .val = 0x03931980 },
         { .reg = 0x00009888, .val = 0x05930032 },
         { .reg = 0x00009888, .val = 0x11930000 },
         { .reg = 0x00009888, .val = 0x01938000 },
         { .reg = 0x00009888, .val = 0x0F938000 },
         { .reg = 0x00009888, .val = 0x1993A00A },
         { .reg = 0x00009888, .val = 0x07930000 },
         { .reg = 0x00009888, .val = 0x09930000 },
         { .reg = 0x00009888, .val = 0x1D900177 },
         { .reg = 0x00009888, .val = 0x1F900178 },
         { .reg = 0x00009888, .val = 0x35900000 },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x53901000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x55900111 },
         { .reg = 0x00009888, .val = 0x47900001 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900000 },
         { .reg = 0x00009888, .val = 0x4D900000 },
         { .reg = 0x00009888, .val = 0x45900400 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x0007FFFA },
         { .reg = 0x00002774, .val = 0x0000FEFE },
         { .reg = 0x00002778, .val = 0x0007FFFA },
         { .reg = 0x0000277C, .val = 0x0000FEFD },
         { .reg = 0x00002790, .val = 0x0007FFFA },
         { .reg = 0x00002794, .val = 0x0000FBEF },
         { .reg = 0x00002798, .val = 0x0007FFFA },
         { .reg = 0x0000279C, .val = 0x0000FBDF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__compute_l3_cache__avg_gpu_core_frequency__max,glk__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,glk__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,glk__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,glk__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, glk__compute_l3_cache__eu_avg_ipc_rate__max,glk__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,glk__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,glk__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,glk__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,glk__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,glk__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,glk__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,glk__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,glk__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,glk__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,glk__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,glk__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,glk__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,glk__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,glk__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,glk__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,glk__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,glk__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,glk__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,glk__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, glk__compute_l3_cache__slm_bytes_read__max,glk__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, glk__compute_l3_cache__slm_bytes_written__max,glk__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,glk__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,glk__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 204, 256, NULL,glk__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 145, 264, NULL,glk__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 272, glk__compute_l3_cache__l3_sampler_throughput__max,glk__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 280, glk__compute_l3_cache__l3_shader_throughput__max,glk__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 288, glk__compute_l3_cache__l3_total_throughput__max,glk__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,glk__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 206, 304, NULL,glk__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 207, 312, NULL,glk__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 208, 320, NULL,glk__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 209, 328, NULL,glk__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 214, 336, NULL,glk__compute_l3_cache__l3_bank00_ic_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 0x01) {
         intel_perf_query_add_counter_uint64(query, 215, 344, NULL,glk__compute_l3_cache__l3_bank00_ic_hits__read);
      }

      intel_perf_query_add_counter_uint64(query, 56, 352, glk__compute_l3_cache__gti_l3_throughput__max,glk__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 360, glk__compute_l3_cache__gti_read_throughput__max,glk__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 368, glk__compute_l3_cache__gti_write_throughput__max,glk__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "0329ea02-ebb8-43f1-bf89-c5bdcccd3eb4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x104F0232 },
         { .reg = 0x00009888, .val = 0x124F4640 },
         { .reg = 0x00009888, .val = 0x11834400 },
         { .reg = 0x00009888, .val = 0x022D4000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x0E2E0055 },
         { .reg = 0x00009888, .val = 0x064C8000 },
         { .reg = 0x00009888, .val = 0x084CC000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x024E8000 },
         { .reg = 0x00009888, .val = 0x044EA000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x024F6100 },
         { .reg = 0x00009888, .val = 0x044F416B },
         { .reg = 0x00009888, .val = 0x064F004B },
         { .reg = 0x00009888, .val = 0x1A4F0000 },
         { .reg = 0x00009888, .val = 0x1A0F02A8 },
         { .reg = 0x00009888, .val = 0x1A2C5500 },
         { .reg = 0x00009888, .val = 0x0F808000 },
         { .reg = 0x00009888, .val = 0x25810020 },
         { .reg = 0x00009888, .val = 0x0F8305C0 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x1F951000 },
         { .reg = 0x00009888, .val = 0x13920200 },
         { .reg = 0x00009888, .val = 0x31908000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4D900003 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x45900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__hdc_and_sf__avg_gpu_core_frequency__max,glk__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,glk__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,glk__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,glk__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,glk__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,glk__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,glk__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,glk__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,glk__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,glk__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,glk__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,glk__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,glk__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,glk__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,glk__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,glk__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,glk__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,glk__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, glk__hdc_and_sf__slm_bytes_read__max,glk__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, glk__hdc_and_sf__slm_bytes_written__max,glk__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,glk__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,glk__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, glk__hdc_and_sf__l3_shader_throughput__max,glk__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,glk__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,glk__hdc_and_sf__poly_data_ready__read);

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 240, 244, percentage_max_float,glk__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 239, 248, percentage_max_float,glk__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 252, percentage_max_float,glk__hdc_and_sf__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "5e57a25a-1d18-4e94-b84b-08ea66751b8c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x12643400 },
         { .reg = 0x00009888, .val = 0x12653400 },
         { .reg = 0x00009888, .val = 0x106C6800 },
         { .reg = 0x00009888, .val = 0x126C001E },
         { .reg = 0x00009888, .val = 0x166C0010 },
         { .reg = 0x00009888, .val = 0x0C2D5000 },
         { .reg = 0x00009888, .val = 0x0E2D5000 },
         { .reg = 0x00009888, .val = 0x002D4000 },
         { .reg = 0x00009888, .val = 0x022D5000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x102E0154 },
         { .reg = 0x00009888, .val = 0x0C2E5000 },
         { .reg = 0x00009888, .val = 0x0E2E0055 },
         { .reg = 0x00009888, .val = 0x104C8000 },
         { .reg = 0x00009888, .val = 0x124C8000 },
         { .reg = 0x00009888, .val = 0x144C8000 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x044C8000 },
         { .reg = 0x00009888, .val = 0x064CC000 },
         { .reg = 0x00009888, .val = 0x084CC000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x0C4EA000 },
         { .reg = 0x00009888, .val = 0x0E4EA000 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x024EA000 },
         { .reg = 0x00009888, .val = 0x044EA000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x1C4F5500 },
         { .reg = 0x00009888, .val = 0x1A4F1554 },
         { .reg = 0x00009888, .val = 0x0A640024 },
         { .reg = 0x00009888, .val = 0x10640000 },
         { .reg = 0x00009888, .val = 0x04640000 },
         { .reg = 0x00009888, .val = 0x0C650024 },
         { .reg = 0x00009888, .val = 0x10650000 },
         { .reg = 0x00009888, .val = 0x06650000 },
         { .reg = 0x00009888, .val = 0x0C6C5327 },
         { .reg = 0x00009888, .val = 0x0E6C5425 },
         { .reg = 0x00009888, .val = 0x006C2A00 },
         { .reg = 0x00009888, .val = 0x026C285B },
         { .reg = 0x00009888, .val = 0x046C005C },
         { .reg = 0x00009888, .val = 0x1C6C0000 },
         { .reg = 0x00009888, .val = 0x1A6C0900 },
         { .reg = 0x00009888, .val = 0x1C0F0AA0 },
         { .reg = 0x00009888, .val = 0x180F4000 },
         { .reg = 0x00009888, .val = 0x1A0F02AA },
         { .reg = 0x00009888, .val = 0x1C2C5400 },
         { .reg = 0x00009888, .val = 0x1E2C0001 },
         { .reg = 0x00009888, .val = 0x1A2C5550 },
         { .reg = 0x00009888, .val = 0x1993AA00 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x2B904000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900421 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900001 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900420 },
         { .reg = 0x00009888, .val = 0x45900021 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00100070 },
         { .reg = 0x00002774, .val = 0x0000FFF1 },
         { .reg = 0x00002778, .val = 0x00014002 },
         { .reg = 0x0000277C, .val = 0x0000C3FF },
         { .reg = 0x00002780, .val = 0x00010002 },
         { .reg = 0x00002784, .val = 0x0000C7FF },
         { .reg = 0x00002788, .val = 0x00004002 },
         { .reg = 0x0000278C, .val = 0x0000D3FF },
         { .reg = 0x00002790, .val = 0x00100700 },
         { .reg = 0x00002794, .val = 0x0000FF1F },
         { .reg = 0x00002798, .val = 0x00001402 },
         { .reg = 0x0000279C, .val = 0x0000FC3F },
         { .reg = 0x000027A0, .val = 0x00001002 },
         { .reg = 0x000027A4, .val = 0x0000FC7F },
         { .reg = 0x000027A8, .val = 0x00000402 },
         { .reg = 0x000027AC, .val = 0x0000FD3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__l3_1__avg_gpu_core_frequency__max,glk__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,glk__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,glk__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,glk__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,glk__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,glk__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,glk__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,glk__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,glk__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,glk__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,glk__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,glk__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,glk__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,glk__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,glk__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,glk__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,glk__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,glk__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, glk__l3_1__slm_bytes_read__max,glk__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, glk__l3_1__slm_bytes_written__max,glk__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,glk__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,glk__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, glk__l3_1__l3_shader_throughput__max,glk__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,glk__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 249, 240, percentage_max_float,glk__l3_1__l30_bank0_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 250, 244, percentage_max_float,glk__l3_1__l30_bank1_stalled__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 251, 248, percentage_max_float,glk__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 252, 252, percentage_max_float,glk__l3_1__l30_bank0_active__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 256, percentage_max_float,glk__l3_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "f0652373-d361-426f-b36d-9ffec288bdc6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x102D7800 },
         { .reg = 0x00009888, .val = 0x122D79E0 },
         { .reg = 0x00009888, .val = 0x0C2F0004 },
         { .reg = 0x00009888, .val = 0x100E3800 },
         { .reg = 0x00009888, .val = 0x180F0005 },
         { .reg = 0x00009888, .val = 0x002D0940 },
         { .reg = 0x00009888, .val = 0x022D802F },
         { .reg = 0x00009888, .val = 0x042D4013 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x0E2E0050 },
         { .reg = 0x00009888, .val = 0x022F0010 },
         { .reg = 0x00009888, .val = 0x002F0000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x044E8000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x040E0480 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x060F0027 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x1A0F0040 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x439014A0 },
         { .reg = 0x00009888, .val = 0x459000A4 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000EFFF },
         { .reg = 0x00002778, .val = 0x00006000 },
         { .reg = 0x0000277C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,glk__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,glk__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,glk__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,glk__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,glk__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,glk__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,glk__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,glk__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,glk__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,glk__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,glk__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,glk__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,glk__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,glk__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,glk__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,glk__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,glk__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, glk__rasterizer_and_pixel_backend__slm_bytes_read__max,glk__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, glk__rasterizer_and_pixel_backend__slm_bytes_written__max,glk__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,glk__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,glk__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, glk__rasterizer_and_pixel_backend__l3_shader_throughput__max,glk__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,glk__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 263, 240, percentage_max_float,glk__rasterizer_and_pixel_backend__pixel_data0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 266, 244, percentage_max_float,glk__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 268, 248, percentage_max_float,glk__rasterizer_and_pixel_backend__ps_output0_available__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 267, 252, percentage_max_float,glk__rasterizer_and_pixel_backend__pixel_values0_ready__read);
      }

      if (perf->sys_vars.slice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 261, 256, percentage_max_float,glk__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,glk__rasterizer_and_pixel_backend__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set Sampler";
   query->symbol_name = "Sampler";
   query->guid = "6ac97d12-ce13-428a-b20c-6902bde2608b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x121300A0 },
         { .reg = 0x00009888, .val = 0x141600AB },
         { .reg = 0x00009888, .val = 0x123300A0 },
         { .reg = 0x00009888, .val = 0x143600AB },
         { .reg = 0x00009888, .val = 0x125300A0 },
         { .reg = 0x00009888, .val = 0x145600AB },
         { .reg = 0x00009888, .val = 0x0C2D4000 },
         { .reg = 0x00009888, .val = 0x0E2D5000 },
         { .reg = 0x00009888, .val = 0x002D4000 },
         { .reg = 0x00009888, .val = 0x022D5000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x102E01A0 },
         { .reg = 0x00009888, .val = 0x0C2E5000 },
         { .reg = 0x00009888, .val = 0x0E2E0065 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x044C8000 },
         { .reg = 0x00009888, .val = 0x064CC000 },
         { .reg = 0x00009888, .val = 0x084C4000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x0E4E8000 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x024EA000 },
         { .reg = 0x00009888, .val = 0x044E2000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x1C0F0800 },
         { .reg = 0x00009888, .val = 0x180F4000 },
         { .reg = 0x00009888, .val = 0x1A0F023F },
         { .reg = 0x00009888, .val = 0x1E2C0003 },
         { .reg = 0x00009888, .val = 0x1A2CC030 },
         { .reg = 0x00009888, .val = 0x04132180 },
         { .reg = 0x00009888, .val = 0x02130000 },
         { .reg = 0x00009888, .val = 0x0C148000 },
         { .reg = 0x00009888, .val = 0x0E142000 },
         { .reg = 0x00009888, .val = 0x04148000 },
         { .reg = 0x00009888, .val = 0x1E150140 },
         { .reg = 0x00009888, .val = 0x1C150040 },
         { .reg = 0x00009888, .val = 0x0C163000 },
         { .reg = 0x00009888, .val = 0x0E160068 },
         { .reg = 0x00009888, .val = 0x10160000 },
         { .reg = 0x00009888, .val = 0x18160000 },
         { .reg = 0x00009888, .val = 0x0A164000 },
         { .reg = 0x00009888, .val = 0x04330043 },
         { .reg = 0x00009888, .val = 0x02330000 },
         { .reg = 0x00009888, .val = 0x0234A000 },
         { .reg = 0x00009888, .val = 0x04342000 },
         { .reg = 0x00009888, .val = 0x1C350015 },
         { .reg = 0x00009888, .val = 0x02363460 },
         { .reg = 0x00009888, .val = 0x10360000 },
         { .reg = 0x00009888, .val = 0x04360000 },
         { .reg = 0x00009888, .val = 0x06360000 },
         { .reg = 0x00009888, .val = 0x08364000 },
         { .reg = 0x00009888, .val = 0x06530043 },
         { .reg = 0x00009888, .val = 0x02530000 },
         { .reg = 0x00009888, .val = 0x0E548000 },
         { .reg = 0x00009888, .val = 0x00548000 },
         { .reg = 0x00009888, .val = 0x06542000 },
         { .reg = 0x00009888, .val = 0x1E550400 },
         { .reg = 0x00009888, .val = 0x1A552000 },
         { .reg = 0x00009888, .val = 0x1C550100 },
         { .reg = 0x00009888, .val = 0x0E563000 },
         { .reg = 0x00009888, .val = 0x00563400 },
         { .reg = 0x00009888, .val = 0x10560000 },
         { .reg = 0x00009888, .val = 0x18560000 },
         { .reg = 0x00009888, .val = 0x02560000 },
         { .reg = 0x00009888, .val = 0x0C564000 },
         { .reg = 0x00009888, .val = 0x1993A800 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B9014A0 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900001 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900820 },
         { .reg = 0x00009888, .val = 0x45901022 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0000C000 },
         { .reg = 0x00002774, .val = 0x0000E7FF },
         { .reg = 0x00002778, .val = 0x00003000 },
         { .reg = 0x0000277C, .val = 0x0000F9FF },
         { .reg = 0x00002780, .val = 0x00000C00 },
         { .reg = 0x00002784, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__sampler__avg_gpu_core_frequency__max,glk__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__sampler__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__sampler__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__sampler__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__sampler__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__sampler__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__sampler__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__sampler__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__sampler__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__sampler__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,glk__sampler__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,glk__sampler__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,glk__sampler__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,glk__sampler__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,glk__sampler__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,glk__sampler__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,glk__sampler__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,glk__sampler__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,glk__sampler__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,glk__sampler__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,glk__sampler__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,glk__sampler__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,glk__sampler__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,glk__sampler__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,glk__sampler__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,glk__sampler__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,glk__sampler__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, glk__sampler__slm_bytes_read__max,glk__sampler__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, glk__sampler__slm_bytes_written__max,glk__sampler__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,glk__sampler__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,glk__sampler__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, glk__sampler__l3_shader_throughput__max,glk__sampler__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,glk__sampler__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 277, 240, percentage_max_float,glk__sampler__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 278, 244, percentage_max_float,glk__sampler__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 279, 248, percentage_max_float,glk__sampler__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 280, 252, percentage_max_float,glk__sampler__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 281, 256, percentage_max_float,glk__sampler__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 282, 260, percentage_max_float,glk__sampler__sampler01_output_ready__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,glk__sampler__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "59ea703a-9a35-4aed-a985-0d9ab7aceaba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A0000 },
         { .reg = 0x00009888, .val = 0x143A0000 },
         { .reg = 0x00009888, .val = 0x145A0000 },
         { .reg = 0x00009888, .val = 0x0C2D4000 },
         { .reg = 0x00009888, .val = 0x0E2D5000 },
         { .reg = 0x00009888, .val = 0x002D4000 },
         { .reg = 0x00009888, .val = 0x022D5000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x102E0150 },
         { .reg = 0x00009888, .val = 0x0C2E5000 },
         { .reg = 0x00009888, .val = 0x0E2E006A },
         { .reg = 0x00009888, .val = 0x124C8000 },
         { .reg = 0x00009888, .val = 0x144C8000 },
         { .reg = 0x00009888, .val = 0x164C2000 },
         { .reg = 0x00009888, .val = 0x044C8000 },
         { .reg = 0x00009888, .val = 0x064C4000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x0C4E8000 },
         { .reg = 0x00009888, .val = 0x0E4EA000 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x024E2000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x1C0F0BC0 },
         { .reg = 0x00009888, .val = 0x180F4000 },
         { .reg = 0x00009888, .val = 0x1A0F0302 },
         { .reg = 0x00009888, .val = 0x1E2C0003 },
         { .reg = 0x00009888, .val = 0x1A2C00F0 },
         { .reg = 0x00009888, .val = 0x021A3080 },
         { .reg = 0x00009888, .val = 0x041A31E5 },
         { .reg = 0x00009888, .val = 0x02148000 },
         { .reg = 0x00009888, .val = 0x0414A000 },
         { .reg = 0x00009888, .val = 0x1C150054 },
         { .reg = 0x00009888, .val = 0x06168000 },
         { .reg = 0x00009888, .val = 0x08168000 },
         { .reg = 0x00009888, .val = 0x0A168000 },
         { .reg = 0x00009888, .val = 0x0C3A3280 },
         { .reg = 0x00009888, .val = 0x0E3A0063 },
         { .reg = 0x00009888, .val = 0x063A0061 },
         { .reg = 0x00009888, .val = 0x023A0000 },
         { .reg = 0x00009888, .val = 0x0C348000 },
         { .reg = 0x00009888, .val = 0x0E342000 },
         { .reg = 0x00009888, .val = 0x06342000 },
         { .reg = 0x00009888, .val = 0x1E350140 },
         { .reg = 0x00009888, .val = 0x1C350100 },
         { .reg = 0x00009888, .val = 0x18360028 },
         { .reg = 0x00009888, .val = 0x0C368000 },
         { .reg = 0x00009888, .val = 0x0E5A3080 },
         { .reg = 0x00009888, .val = 0x005A3280 },
         { .reg = 0x00009888, .val = 0x025A0063 },
         { .reg = 0x00009888, .val = 0x0E548000 },
         { .reg = 0x00009888, .val = 0x00548000 },
         { .reg = 0x00009888, .val = 0x02542000 },
         { .reg = 0x00009888, .val = 0x1E550400 },
         { .reg = 0x00009888, .val = 0x1A552000 },
         { .reg = 0x00009888, .val = 0x1C550001 },
         { .reg = 0x00009888, .val = 0x18560080 },
         { .reg = 0x00009888, .val = 0x02568000 },
         { .reg = 0x00009888, .val = 0x04568000 },
         { .reg = 0x00009888, .val = 0x1993A800 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x2D904000 },
         { .reg = 0x00009888, .val = 0x2F904000 },
         { .reg = 0x00009888, .val = 0x31904000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x59900000 },
         { .reg = 0x00009888, .val = 0x4B900420 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
         { .reg = 0x00009888, .val = 0x4D900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x45901084 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x30800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x00007FFF },
         { .reg = 0x00002778, .val = 0x00000000 },
         { .reg = 0x0000277C, .val = 0x00009FFF },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000EFFF },
         { .reg = 0x00002788, .val = 0x00000000 },
         { .reg = 0x0000278C, .val = 0x0000F3FF },
         { .reg = 0x00002790, .val = 0x00000002 },
         { .reg = 0x00002794, .val = 0x0000FDFF },
         { .reg = 0x00002798, .val = 0x00000000 },
         { .reg = 0x0000279C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__tdl_1__avg_gpu_core_frequency__max,glk__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,glk__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,glk__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,glk__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,glk__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,glk__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,glk__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,glk__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,glk__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,glk__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,glk__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,glk__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,glk__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,glk__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,glk__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,glk__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,glk__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,glk__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, glk__tdl_1__slm_bytes_read__max,glk__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, glk__tdl_1__slm_bytes_written__max,glk__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,glk__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,glk__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, glk__tdl_1__l3_shader_throughput__max,glk__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,glk__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 299, 240, percentage_max_float,glk__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 298, 244, percentage_max_float,glk__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 300, 248, percentage_max_float,glk__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 296, 252, percentage_max_float,glk__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 295, 256, percentage_max_float,glk__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 297, 260, percentage_max_float,glk__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,glk__tdl_1__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 42);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "f2d6d718-e7b1-48f4-9624-45230d2fe2a0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x000091BC, .val = 0xE0500000 },
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A026B },
         { .reg = 0x00009888, .val = 0x143A0173 },
         { .reg = 0x00009888, .val = 0x145A026B },
         { .reg = 0x00009888, .val = 0x002D4000 },
         { .reg = 0x00009888, .val = 0x022D5000 },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x0C2E5000 },
         { .reg = 0x00009888, .val = 0x0E2E0069 },
         { .reg = 0x00009888, .val = 0x044C8000 },
         { .reg = 0x00009888, .val = 0x064CC000 },
         { .reg = 0x00009888, .val = 0x0A4C4000 },
         { .reg = 0x00009888, .val = 0x004E8000 },
         { .reg = 0x00009888, .val = 0x024EA000 },
         { .reg = 0x00009888, .val = 0x064E2000 },
         { .reg = 0x00009888, .val = 0x180F6000 },
         { .reg = 0x00009888, .val = 0x1A0F030A },
         { .reg = 0x00009888, .val = 0x1A2C03C0 },
         { .reg = 0x00009888, .val = 0x041A37E7 },
         { .reg = 0x00009888, .val = 0x021A0000 },
         { .reg = 0x00009888, .val = 0x0414A000 },
         { .reg = 0x00009888, .val = 0x1C150050 },
         { .reg = 0x00009888, .val = 0x08168000 },
         { .reg = 0x00009888, .val = 0x0A168000 },
         { .reg = 0x00009888, .val = 0x003A3380 },
         { .reg = 0x00009888, .val = 0x063A006F },
         { .reg = 0x00009888, .val = 0x023A0000 },
         { .reg = 0x00009888, .val = 0x00348000 },
         { .reg = 0x00009888, .val = 0x06342000 },
         { .reg = 0x00009888, .val = 0x1A352000 },
         { .reg = 0x00009888, .val = 0x1C350100 },
         { .reg = 0x00009888, .val = 0x02368000 },
         { .reg = 0x00009888, .val = 0x0C368000 },
         { .reg = 0x00009888, .val = 0x025A37E7 },
         { .reg = 0x00009888, .val = 0x0254A000 },
         { .reg = 0x00009888, .val = 0x1C550005 },
         { .reg = 0x00009888, .val = 0x04568000 },
         { .reg = 0x00009888, .val = 0x06568000 },
         { .reg = 0x00009888, .val = 0x03938000 },
         { .reg = 0x00009888, .val = 0x05938000 },
         { .reg = 0x00009888, .val = 0x07938000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x15904000 },
         { .reg = 0x00009888, .val = 0x17904000 },
         { .reg = 0x00009888, .val = 0x19904000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900020 },
         { .reg = 0x00009888, .val = 0x45901080 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900001 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__tdl_2__avg_gpu_core_frequency__max,glk__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,glk__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,glk__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,glk__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,glk__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,glk__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,glk__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,glk__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,glk__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,glk__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,glk__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,glk__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,glk__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,glk__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,glk__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,glk__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,glk__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,glk__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,glk__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,glk__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,glk__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,glk__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,glk__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,glk__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,glk__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,glk__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,glk__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, glk__tdl_2__slm_bytes_read__max,glk__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, glk__tdl_2__slm_bytes_written__max,glk__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,glk__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,glk__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, glk__tdl_2__l3_shader_throughput__max,glk__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,glk__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 289, 240, percentage_max_float,glk__tdl_2__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 290, 244, percentage_max_float,glk__tdl_2__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x1) {
         intel_perf_query_add_counter_float(query, 291, 248, percentage_max_float,glk__tdl_2__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 292, 252, percentage_max_float,glk__tdl_2__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 0x4) {
         intel_perf_query_add_counter_float(query, 293, 256, percentage_max_float,glk__tdl_2__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 0x2) {
         intel_perf_query_add_counter_float(query, 294, 260, percentage_max_float,glk__tdl_2__thread_header01_ready_port1__read);
      }

      if (true &&
          perf->sys_vars.query_mode) {
         intel_perf_query_add_counter_float(query, 244, 264, percentage_max_float,glk__tdl_2__gt_request_queue_full__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_compute_extra_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Compute Metrics Extra set";
   query->symbol_name = "ComputeExtra";
   query->guid = "15274c82-27d2-4819-876a-7cb1a2c59ba4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x141A001F },
         { .reg = 0x00009888, .val = 0x143A001F },
         { .reg = 0x00009888, .val = 0x145A001F },
         { .reg = 0x00009888, .val = 0x042D5000 },
         { .reg = 0x00009888, .val = 0x062D1000 },
         { .reg = 0x00009888, .val = 0x0E2E0094 },
         { .reg = 0x00009888, .val = 0x084CC000 },
         { .reg = 0x00009888, .val = 0x044EA000 },
         { .reg = 0x00009888, .val = 0x1A0F00E0 },
         { .reg = 0x00009888, .val = 0x1A2C0C00 },
         { .reg = 0x00009888, .val = 0x061A0063 },
         { .reg = 0x00009888, .val = 0x021A0000 },
         { .reg = 0x00009888, .val = 0x06142000 },
         { .reg = 0x00009888, .val = 0x1C150100 },
         { .reg = 0x00009888, .val = 0x0C168000 },
         { .reg = 0x00009888, .val = 0x043A3180 },
         { .reg = 0x00009888, .val = 0x023A0000 },
         { .reg = 0x00009888, .val = 0x04348000 },
         { .reg = 0x00009888, .val = 0x1C350040 },
         { .reg = 0x00009888, .val = 0x0A368000 },
         { .reg = 0x00009888, .val = 0x045A0063 },
         { .reg = 0x00009888, .val = 0x025A0000 },
         { .reg = 0x00009888, .val = 0x04542000 },
         { .reg = 0x00009888, .val = 0x1C550010 },
         { .reg = 0x00009888, .val = 0x08568000 },
         { .reg = 0x00009888, .val = 0x09938000 },
         { .reg = 0x00009888, .val = 0x0B938000 },
         { .reg = 0x00009888, .val = 0x0D938000 },
         { .reg = 0x00009888, .val = 0x1B904000 },
         { .reg = 0x00009888, .val = 0x1D904000 },
         { .reg = 0x00009888, .val = 0x1F904000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x45900400 },
         { .reg = 0x00009888, .val = 0x47900004 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00001000 },
         { .reg = 0x0000E558, .val = 0x00003002 },
         { .reg = 0x0000E658, .val = 0x00005004 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00050012 },
         { .reg = 0x0000E55C, .val = 0x00052051 },
         { .reg = 0x0000E65C, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__compute_extra__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__compute_extra__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__compute_extra__avg_gpu_core_frequency__max,glk__compute_extra__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 151, 24, percentage_max_float,glk__compute_extra__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 307, 28, percentage_max_float,glk__compute_extra__fpu1_active_adjusted__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "MDAPI testing set";
   query->symbol_name = "TestOa";
   query->guid = "dd3fd789-e783-4204-8cd0-b671bbccb0cf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x19800000 },
         { .reg = 0x00009888, .val = 0x07800063 },
         { .reg = 0x00009888, .val = 0x11800000 },
         { .reg = 0x00009888, .val = 0x23810008 },
         { .reg = 0x00009888, .val = 0x1D950400 },
         { .reg = 0x00009888, .val = 0x0F922000 },
         { .reg = 0x00009888, .val = 0x1F908000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002744, .val = 0x00800000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x00000000 },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x00000000 },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x00000000 },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__test_oa__avg_gpu_core_frequency__max,glk__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,glk__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,glk__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,glk__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,glk__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 319, 56, NULL,glk__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 320, 64, NULL,glk__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 321, 72, NULL,glk__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 322, 80, NULL,glk__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,glk__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
glk_register_pma__stall_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Metric set PMA Stall";
   query->symbol_name = "PMA_Stall";
   query->guid = "e6868953-fb47-431d-a060-f785916558fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009840, .val = 0x00000080 },
         { .reg = 0x00009888, .val = 0x124C3080 },
         { .reg = 0x00009888, .val = 0x002D1000 },
         { .reg = 0x00009888, .val = 0x062D4000 },
         { .reg = 0x00009888, .val = 0x082D5000 },
         { .reg = 0x00009888, .val = 0x0A2D5000 },
         { .reg = 0x00009888, .val = 0x0C2E0400 },
         { .reg = 0x00009888, .val = 0x0E2E5500 },
         { .reg = 0x00009888, .val = 0x102E0001 },
         { .reg = 0x00009888, .val = 0x004C0045 },
         { .reg = 0x00009888, .val = 0x064C2300 },
         { .reg = 0x00009888, .val = 0x084C26C4 },
         { .reg = 0x00009888, .val = 0x0A4C264E },
         { .reg = 0x00009888, .val = 0x164C0000 },
         { .reg = 0x00009888, .val = 0x044C0000 },
         { .reg = 0x00009888, .val = 0x0C4C0000 },
         { .reg = 0x00009888, .val = 0x0E4C0000 },
         { .reg = 0x00009888, .val = 0x01938000 },
         { .reg = 0x00009888, .val = 0x0F938000 },
         { .reg = 0x00009888, .val = 0x199300AA },
         { .reg = 0x00009888, .val = 0x13904000 },
         { .reg = 0x00009888, .val = 0x21904000 },
         { .reg = 0x00009888, .val = 0x23904000 },
         { .reg = 0x00009888, .val = 0x25904000 },
         { .reg = 0x00009888, .val = 0x27904000 },
         { .reg = 0x00009888, .val = 0x29904000 },
         { .reg = 0x00009888, .val = 0x53900000 },
         { .reg = 0x00009888, .val = 0x43900000 },
         { .reg = 0x00009888, .val = 0x55900000 },
         { .reg = 0x00009888, .val = 0x47900000 },
         { .reg = 0x00009888, .val = 0x57900000 },
         { .reg = 0x00009888, .val = 0x49900000 },
         { .reg = 0x00009888, .val = 0x37900000 },
         { .reg = 0x00009888, .val = 0x33900000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x30800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00E00021 },
         { .reg = 0x00002774, .val = 0x0007FFF8 },
         { .reg = 0x00002778, .val = 0x07000101 },
         { .reg = 0x0000277C, .val = 0x0038FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,glk__pma__stall__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,glk__pma__stall__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, glk__pma__stall__avg_gpu_core_frequency__max,glk__pma__stall__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 324, 24, percentage_max_float,glk__pma__stall__stc_pma_stall__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_glk(struct intel_perf_config *perf)
{
   glk_register_render_basic_counter_query(perf);
   glk_register_compute_basic_counter_query(perf);
   glk_register_render_pipe_profile_counter_query(perf);
   glk_register_memory_reads_counter_query(perf);
   glk_register_memory_writes_counter_query(perf);
   glk_register_compute_extended_counter_query(perf);
   glk_register_compute_l3_cache_counter_query(perf);
   glk_register_hdc_and_sf_counter_query(perf);
   glk_register_l3_1_counter_query(perf);
   glk_register_rasterizer_and_pixel_backend_counter_query(perf);
   glk_register_sampler_counter_query(perf);
   glk_register_tdl_1_counter_query(perf);
   glk_register_tdl_2_counter_query(perf);
   glk_register_compute_extra_counter_query(perf);
   glk_register_test_oa_counter_query(perf);
   glk_register_pma__stall_counter_query(perf);
}


static void
icl_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "e3cd52cf-c6b0-4019-b369-3bc9c75a0cbc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x142C0014 },
         { .reg = 0x00009888, .val = 0x14120700 },
         { .reg = 0x00009888, .val = 0x121500E0 },
         { .reg = 0x00009888, .val = 0x1C1E000C },
         { .reg = 0x00009888, .val = 0x0E1F000C },
         { .reg = 0x00009888, .val = 0x1C200014 },
         { .reg = 0x00009888, .val = 0x16212800 },
         { .reg = 0x00009888, .val = 0x0E2C2041 },
         { .reg = 0x00009888, .val = 0x102C0000 },
         { .reg = 0x00009888, .val = 0x1A2C0000 },
         { .reg = 0x00009888, .val = 0x10040140 },
         { .reg = 0x00009888, .val = 0x0E040005 },
         { .reg = 0x00009888, .val = 0x14050050 },
         { .reg = 0x00009888, .val = 0x06054000 },
         { .reg = 0x00009888, .val = 0x08051000 },
         { .reg = 0x00009888, .val = 0x260600C0 },
         { .reg = 0x00009888, .val = 0x24061800 },
         { .reg = 0x00009888, .val = 0x04120023 },
         { .reg = 0x00009888, .val = 0x10120000 },
         { .reg = 0x00009888, .val = 0x08120000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x04144000 },
         { .reg = 0x00009888, .val = 0x02150980 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x1815000F },
         { .reg = 0x00009888, .val = 0x06150000 },
         { .reg = 0x00009888, .val = 0x08154000 },
         { .reg = 0x00009888, .val = 0x0E18A000 },
         { .reg = 0x00009888, .val = 0x14190028 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1A1C01C0 },
         { .reg = 0x00009888, .val = 0x1C1C000A },
         { .reg = 0x00009888, .val = 0x1A5C01C0 },
         { .reg = 0x00009888, .val = 0x1C5C000A },
         { .reg = 0x00009888, .val = 0x001C0097 },
         { .reg = 0x00009888, .val = 0x061C9400 },
         { .reg = 0x00009888, .val = 0x0A1C00A7 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x081D8100 },
         { .reg = 0x00009888, .val = 0x0A1D0004 },
         { .reg = 0x00009888, .val = 0x085C9497 },
         { .reg = 0x00009888, .val = 0x0A5CA700 },
         { .reg = 0x00009888, .val = 0x105C0000 },
         { .reg = 0x00009888, .val = 0x0A5D000B },
         { .reg = 0x00009888, .val = 0x181E8000 },
         { .reg = 0x00009888, .val = 0x1E1EEF80 },
         { .reg = 0x00009888, .val = 0x301F4000 },
         { .reg = 0x00009888, .val = 0x501F2404 },
         { .reg = 0x00009888, .val = 0x521F0092 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x4E1F2000 },
         { .reg = 0x00009888, .val = 0x3E1F0300 },
         { .reg = 0x00009888, .val = 0x461F0303 },
         { .reg = 0x00009888, .val = 0x481F0303 },
         { .reg = 0x00009888, .val = 0x4A1F0003 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x421F4001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00051050 },
         { .reg = 0x0000E45C, .val = 0x00000052 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__render_basic__avg_gpu_core_frequency__max,icl__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,icl__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,icl__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,icl__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,icl__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,icl__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,icl__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,icl__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,icl__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,icl__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,icl__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,icl__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,icl__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,icl__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,icl__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,icl__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,icl__render_basic__ps_send_active__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 333, 112, percentage_max_float,icl__render_basic__sampler00_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 9) {
         intel_perf_query_add_counter_float(query, 133, 116, percentage_max_float,icl__render_basic__samplers_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 334, 120, percentage_max_float,icl__render_basic__sampler00_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 128, NULL,icl__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 136, NULL,icl__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 144, NULL,icl__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 152, NULL,icl__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 160, NULL,icl__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 168, NULL,icl__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 176, NULL,icl__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 184, NULL,icl__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 192, NULL,icl__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 200, NULL,icl__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 208, icl__render_basic__slm_bytes_read__max,icl__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 216, icl__render_basic__slm_bytes_written__max,icl__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 224, NULL,icl__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 232, NULL,icl__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 240, icl__render_basic__l3_shader_throughput__max,icl__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 248, NULL,icl__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 256, icl__render_basic__gti_read_throughput__max,icl__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 264, icl__render_basic__gti_write_throughput__max,icl__render_basic__gti_write_throughput__read);

      if (perf->sys_vars.subslice_mask & 9) {
         intel_perf_query_add_counter_float(query, 149, 272, percentage_max_float,icl__render_basic__sampler_bottleneck__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "04546170-d541-4804-96f8-007a454a3f2c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x12230012 },
         { .reg = 0x00009888, .val = 0x10230019 },
         { .reg = 0x00009888, .val = 0x12A30012 },
         { .reg = 0x00009888, .val = 0x10A30019 },
         { .reg = 0x00009888, .val = 0x1A200400 },
         { .reg = 0x00009888, .val = 0x1C200020 },
         { .reg = 0x00009888, .val = 0x04208000 },
         { .reg = 0x00009888, .val = 0x08208000 },
         { .reg = 0x00009888, .val = 0x0C208000 },
         { .reg = 0x00009888, .val = 0x0A230031 },
         { .reg = 0x00009888, .val = 0x0E231E00 },
         { .reg = 0x00009888, .val = 0x0223003D },
         { .reg = 0x00009888, .val = 0x04230032 },
         { .reg = 0x00009888, .val = 0x06230033 },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x1AA01000 },
         { .reg = 0x00009888, .val = 0x1CA00008 },
         { .reg = 0x00009888, .val = 0x02A08000 },
         { .reg = 0x00009888, .val = 0x06A08000 },
         { .reg = 0x00009888, .val = 0x0AA08000 },
         { .reg = 0x00009888, .val = 0x0AA31880 },
         { .reg = 0x00009888, .val = 0x0EA3003C },
         { .reg = 0x00009888, .val = 0x00A31E80 },
         { .reg = 0x00009888, .val = 0x02A31900 },
         { .reg = 0x00009888, .val = 0x04A31980 },
         { .reg = 0x00009888, .val = 0x0E044055 },
         { .reg = 0x00009888, .val = 0x10040141 },
         { .reg = 0x00009888, .val = 0x0C045000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050050 },
         { .reg = 0x00009888, .val = 0x04054000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x0A051000 },
         { .reg = 0x00009888, .val = 0x260600CC },
         { .reg = 0x00009888, .val = 0x24067E00 },
         { .reg = 0x00009888, .val = 0x18123000 },
         { .reg = 0x00009888, .val = 0x1A12000C },
         { .reg = 0x00009888, .val = 0x0212C000 },
         { .reg = 0x00009888, .val = 0x0612C000 },
         { .reg = 0x00009888, .val = 0x0A12C000 },
         { .reg = 0x00009888, .val = 0x08138000 },
         { .reg = 0x00009888, .val = 0x0A134000 },
         { .reg = 0x00009888, .val = 0x0413A000 },
         { .reg = 0x00009888, .val = 0x06132000 },
         { .reg = 0x00009888, .val = 0x0A148000 },
         { .reg = 0x00009888, .val = 0x0E144000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02148000 },
         { .reg = 0x00009888, .val = 0x04148000 },
         { .reg = 0x00009888, .val = 0x16150380 },
         { .reg = 0x00009888, .val = 0x1815000D },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x0415C000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x0815C000 },
         { .reg = 0x00009888, .val = 0x0A154000 },
         { .reg = 0x00009888, .val = 0x0C15C000 },
         { .reg = 0x00009888, .val = 0x0A182000 },
         { .reg = 0x00009888, .val = 0x0E188000 },
         { .reg = 0x00009888, .val = 0x02182000 },
         { .reg = 0x00009888, .val = 0x04182000 },
         { .reg = 0x00009888, .val = 0x06182000 },
         { .reg = 0x00009888, .val = 0x12190400 },
         { .reg = 0x00009888, .val = 0x14190020 },
         { .reg = 0x00009888, .val = 0x0A192000 },
         { .reg = 0x00009888, .val = 0x0C192000 },
         { .reg = 0x00009888, .val = 0x0E192000 },
         { .reg = 0x00009888, .val = 0x0A1C8000 },
         { .reg = 0x00009888, .val = 0x0E1C2000 },
         { .reg = 0x00009888, .val = 0x001C8000 },
         { .reg = 0x00009888, .val = 0x021C8000 },
         { .reg = 0x00009888, .val = 0x041C8000 },
         { .reg = 0x00009888, .val = 0x121D1000 },
         { .reg = 0x00009888, .val = 0x141D0008 },
         { .reg = 0x00009888, .val = 0x081D8000 },
         { .reg = 0x00009888, .val = 0x0A1D8000 },
         { .reg = 0x00009888, .val = 0x0C1D8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1A1C01C0 },
         { .reg = 0x00009888, .val = 0x1C1C000A },
         { .reg = 0x00009888, .val = 0x1A5C01C0 },
         { .reg = 0x00009888, .val = 0x1C5C000A },
         { .reg = 0x00009888, .val = 0x001C0097 },
         { .reg = 0x00009888, .val = 0x061C9400 },
         { .reg = 0x00009888, .val = 0x0C1C00A7 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x081D8100 },
         { .reg = 0x00009888, .val = 0x0A1D0010 },
         { .reg = 0x00009888, .val = 0x085C9497 },
         { .reg = 0x00009888, .val = 0x0C5CA700 },
         { .reg = 0x00009888, .val = 0x105C0000 },
         { .reg = 0x00009888, .val = 0x0A5D0023 },
         { .reg = 0x00009888, .val = 0x181E8000 },
         { .reg = 0x00009888, .val = 0x1E1E0F80 },
         { .reg = 0x00009888, .val = 0x201E000E },
         { .reg = 0x00009888, .val = 0x301F4000 },
         { .reg = 0x00009888, .val = 0x501F2524 },
         { .reg = 0x00009888, .val = 0x521F2522 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2430 },
         { .reg = 0x00009888, .val = 0x3E1F0300 },
         { .reg = 0x00009888, .val = 0x461F0303 },
         { .reg = 0x00009888, .val = 0x481F3003 },
         { .reg = 0x00009888, .val = 0x4A1F0300 },
         { .reg = 0x00009888, .val = 0x4C1F0003 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x401F3000 },
         { .reg = 0x00009888, .val = 0x421F3000 },
         { .reg = 0x00009888, .val = 0x441F3000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__compute_basic__avg_gpu_core_frequency__max,icl__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,icl__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 92, percentage_max_float,icl__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,icl__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 152, 100, icl__compute_basic__eu_avg_ipc_rate__max,icl__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,icl__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,icl__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,icl__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,icl__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,icl__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,icl__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,icl__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,icl__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,icl__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,icl__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,icl__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, icl__compute_basic__slm_bytes_read__max,icl__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, icl__compute_basic__slm_bytes_written__max,icl__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,icl__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,icl__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, icl__compute_basic__l3_shader_throughput__max,icl__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,icl__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, icl__compute_basic__typed_bytes_read__max,icl__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, icl__compute_basic__typed_bytes_written__max,icl__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, icl__compute_basic__untyped_bytes_read__max,icl__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, icl__compute_basic__untyped_bytes_written__max,icl__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 335, 264, icl__compute_basic__typed_atomics__max,icl__compute_basic__typed_atomics__read);

      intel_perf_query_add_counter_uint64(query, 57, 272, icl__compute_basic__gti_read_throughput__max,icl__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 280, icl__compute_basic__gti_write_throughput__max,icl__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 22);

   query->name = "Compute Extended metrics set";
   query->symbol_name = "ComputeExtended";
   query->guid = "43eb7fc1-dc5e-45e2-a90a-0053f5397271";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1222000B },
         { .reg = 0x00009888, .val = 0x16220009 },
         { .reg = 0x00009888, .val = 0x12230019 },
         { .reg = 0x00009888, .val = 0x10230012 },
         { .reg = 0x00009888, .val = 0x101E8000 },
         { .reg = 0x00009888, .val = 0x1A1EF800 },
         { .reg = 0x00009888, .val = 0x1C1E0007 },
         { .reg = 0x00009888, .val = 0x001F8000 },
         { .reg = 0x00009888, .val = 0x0C1FF800 },
         { .reg = 0x00009888, .val = 0x0E1F0007 },
         { .reg = 0x00009888, .val = 0x00204000 },
         { .reg = 0x00009888, .val = 0x0E204000 },
         { .reg = 0x00009888, .val = 0x1A202AA0 },
         { .reg = 0x00009888, .val = 0x1C200005 },
         { .reg = 0x00009888, .val = 0x04208000 },
         { .reg = 0x00009888, .val = 0x06208000 },
         { .reg = 0x00009888, .val = 0x08208000 },
         { .reg = 0x00009888, .val = 0x0A208000 },
         { .reg = 0x00009888, .val = 0x0C208000 },
         { .reg = 0x00009888, .val = 0x00214000 },
         { .reg = 0x00009888, .val = 0x0E214000 },
         { .reg = 0x00009888, .val = 0x14214000 },
         { .reg = 0x00009888, .val = 0x16210555 },
         { .reg = 0x00009888, .val = 0x00220011 },
         { .reg = 0x00009888, .val = 0x06220900 },
         { .reg = 0x00009888, .val = 0x08220A13 },
         { .reg = 0x00009888, .val = 0x0A220B15 },
         { .reg = 0x00009888, .val = 0x0C222317 },
         { .reg = 0x00009888, .val = 0x0E220043 },
         { .reg = 0x00009888, .val = 0x02231AB4 },
         { .reg = 0x00009888, .val = 0x04231DBA },
         { .reg = 0x00009888, .val = 0x06230039 },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x0C044400 },
         { .reg = 0x00009888, .val = 0x0E045555 },
         { .reg = 0x00009888, .val = 0x10040055 },
         { .reg = 0x00009888, .val = 0x04051000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050015 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x2406FD00 },
         { .reg = 0x00009888, .val = 0x2606007F },
         { .reg = 0x00009888, .val = 0x0015C000 },
         { .reg = 0x00009888, .val = 0x0E15C000 },
         { .reg = 0x00009888, .val = 0x16157FF8 },
         { .reg = 0x00009888, .val = 0x18150003 },
         { .reg = 0x00009888, .val = 0x0415C000 },
         { .reg = 0x00009888, .val = 0x0615C000 },
         { .reg = 0x00009888, .val = 0x0815C000 },
         { .reg = 0x00009888, .val = 0x0A15C000 },
         { .reg = 0x00009888, .val = 0x0C15C000 },
         { .reg = 0x00009888, .val = 0x00182000 },
         { .reg = 0x00009888, .val = 0x0618A000 },
         { .reg = 0x00009888, .val = 0x0818A000 },
         { .reg = 0x00009888, .val = 0x0A18A000 },
         { .reg = 0x00009888, .val = 0x0C18A000 },
         { .reg = 0x00009888, .val = 0x0E182000 },
         { .reg = 0x00009888, .val = 0x0218A000 },
         { .reg = 0x00009888, .val = 0x0418A000 },
         { .reg = 0x00009888, .val = 0x08192000 },
         { .reg = 0x00009888, .val = 0x0E19A000 },
         { .reg = 0x00009888, .val = 0x12195540 },
         { .reg = 0x00009888, .val = 0x1419000A },
         { .reg = 0x00009888, .val = 0x0A19A000 },
         { .reg = 0x00009888, .val = 0x0C19A000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x16136860 },
         { .reg = 0x00009888, .val = 0x24000004 },
         { .reg = 0x00009888, .val = 0x20000040 },
         { .reg = 0x00009888, .val = 0x0E132980 },
         { .reg = 0x00009888, .val = 0x00132D80 },
         { .reg = 0x00009888, .val = 0x10130000 },
         { .reg = 0x00009888, .val = 0x1A130000 },
         { .reg = 0x00009888, .val = 0x02130000 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4924 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F000C },
         { .reg = 0x00009888, .val = 0x3A1F2000 },
         { .reg = 0x00009888, .val = 0x4E1F2413 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x401F3013 },
         { .reg = 0x00009888, .val = 0x421F3030 },
         { .reg = 0x00009888, .val = 0x441F3030 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x30000036 },
         { .reg = 0x00002774, .val = 0x01FFFE00 },
         { .reg = 0x00002778, .val = 0x31000034 },
         { .reg = 0x0000277C, .val = 0x01FFFE00 },
         { .reg = 0x00002780, .val = 0x00000C9A },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x00000C92 },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x00000CA2 },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x00000E42 },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x00000E6A },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x00000C32 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
         { .reg = 0x0000274C, .val = 0x87643210 },
         { .reg = 0x00002744, .val = 0x00001811 },
         { .reg = 0x00002748, .val = 0x87654310 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__compute_extended__avg_gpu_core_frequency__max,icl__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__compute_extended__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,icl__compute_extended__cs_threads__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 336, 40, NULL,icl__compute_extended__typed_atomics00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 337, 48, NULL,icl__compute_extended__typed_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 338, 56, NULL,icl__compute_extended__typed_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 339, 64, NULL,icl__compute_extended__untyped_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 340, 72, NULL,icl__compute_extended__untyped_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 341, 80, NULL,icl__compute_extended__eu_typed_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 342, 88, NULL,icl__compute_extended__eu_typed_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 343, 96, NULL,icl__compute_extended__eu_typed_atomics00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 344, 104, NULL,icl__compute_extended__eu_a32_untyped_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 345, 112, NULL,icl__compute_extended__eu_a32_untyped_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 346, 120, NULL,icl__compute_extended__eu_a64_untyped_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 347, 128, NULL,icl__compute_extended__eu_a64_untyped_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 94, 136, NULL,icl__compute_extended__typed_atomics_per_cache_line__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 90, 140, NULL,icl__compute_extended__typed_reads_per_cache_line__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 91, 144, NULL,icl__compute_extended__typed_writes_per_cache_line__read);
      }

      intel_perf_query_add_counter_float(query, 92, 148, NULL,icl__compute_extended__untyped_reads_per_cache_line__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 93, 152, NULL,icl__compute_extended__untyped_writes_per_cache_line__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 55);

   query->name = "Compute Metrics L3 Cache metrics set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "05d5e01f-0800-4975-b36b-7b169cad3fab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14120700 },
         { .reg = 0x00009888, .val = 0x121500E0 },
         { .reg = 0x00009888, .val = 0x10040154 },
         { .reg = 0x00009888, .val = 0x0C045000 },
         { .reg = 0x00009888, .val = 0x0E040055 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x04054000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x0A051000 },
         { .reg = 0x00009888, .val = 0x260600F0 },
         { .reg = 0x00009888, .val = 0x24067E00 },
         { .reg = 0x00009888, .val = 0x0C120023 },
         { .reg = 0x00009888, .val = 0x0E12152B },
         { .reg = 0x00009888, .val = 0x00121480 },
         { .reg = 0x00009888, .val = 0x02120028 },
         { .reg = 0x00009888, .val = 0x10120000 },
         { .reg = 0x00009888, .val = 0x18120000 },
         { .reg = 0x00009888, .val = 0x1A120000 },
         { .reg = 0x00009888, .val = 0x04120000 },
         { .reg = 0x00009888, .val = 0x0A13D000 },
         { .reg = 0x00009888, .val = 0x04136000 },
         { .reg = 0x00009888, .val = 0x0C144000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02144000 },
         { .reg = 0x00009888, .val = 0x0C150980 },
         { .reg = 0x00009888, .val = 0x02154D80 },
         { .reg = 0x00009888, .val = 0x04154C9A },
         { .reg = 0x00009888, .val = 0x06150018 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x16150800 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009888, .val = 0x08150000 },
         { .reg = 0x00009888, .val = 0x0A150000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1217241C },
         { .reg = 0x00009888, .val = 0x22000050 },
         { .reg = 0x00009888, .val = 0x18133C00 },
         { .reg = 0x00009888, .val = 0x081710B0 },
         { .reg = 0x00009888, .val = 0x10170000 },
         { .reg = 0x00009888, .val = 0x501F1124 },
         { .reg = 0x00009888, .val = 0x521F4801 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x461F3100 },
         { .reg = 0x00009888, .val = 0x481F0031 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0030 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009888, .val = 0x401F0000 },
         { .reg = 0x00009888, .val = 0x421F3030 },
         { .reg = 0x00009888, .val = 0x441F3030 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__compute_l3_cache__avg_gpu_core_frequency__max,icl__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 152, 88, icl__compute_l3_cache__eu_avg_ipc_rate__max,icl__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 123, 92, percentage_max_float,icl__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 96, percentage_max_float,icl__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 100, percentage_max_float,icl__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,icl__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,icl__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,icl__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,icl__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,icl__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,icl__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,icl__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,icl__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,icl__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,icl__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,icl__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,icl__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,icl__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,icl__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,icl__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,icl__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,icl__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,icl__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,icl__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, icl__compute_l3_cache__slm_bytes_read__max,icl__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, icl__compute_l3_cache__slm_bytes_written__max,icl__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,icl__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,icl__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 256, NULL,icl__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 348, 264, NULL,icl__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 349, 272, NULL,icl__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 350, 280, NULL,icl__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 351, 288, NULL,icl__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 352, 296, NULL,icl__compute_l3_cache__l3_bank04_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 353, 304, NULL,icl__compute_l3_cache__l3_bank05_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 354, 312, NULL,icl__compute_l3_cache__l3_bank06_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 355, 320, NULL,icl__compute_l3_cache__l3_bank07_accesses__read);
      }

      intel_perf_query_add_counter_uint64(query, 204, 328, NULL,icl__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 144, 336, NULL,icl__compute_l3_cache__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 44, 344, icl__compute_l3_cache__l3_sampler_throughput__max,icl__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 352, icl__compute_l3_cache__l3_shader_throughput__max,icl__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 360, icl__compute_l3_cache__l3_total_throughput__max,icl__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 368, icl__compute_l3_cache__gti_read_throughput__max,icl__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 376, icl__compute_l3_cache__gti_write_throughput__max,icl__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "03c7a167-2abc-4ba6-878a-f1d80082abca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x001F001E },
         { .reg = 0x00009888, .val = 0x10160000 },
         { .reg = 0x00009888, .val = 0x1017001F },
         { .reg = 0x00009888, .val = 0x0A1F0005 },
         { .reg = 0x00009888, .val = 0x0E1F0000 },
         { .reg = 0x00009888, .val = 0x0C1F0000 },
         { .reg = 0x00009888, .val = 0x1A200800 },
         { .reg = 0x00009888, .val = 0x10040015 },
         { .reg = 0x00009888, .val = 0x0E054000 },
         { .reg = 0x00009888, .val = 0x14050005 },
         { .reg = 0x00009888, .val = 0x26060038 },
         { .reg = 0x00009888, .val = 0x16157E00 },
         { .reg = 0x00009888, .val = 0x0C160022 },
         { .reg = 0x00009888, .val = 0x08160000 },
         { .reg = 0x00009888, .val = 0x0C170540 },
         { .reg = 0x00009888, .val = 0x04170000 },
         { .reg = 0x00009888, .val = 0x0A188000 },
         { .reg = 0x00009888, .val = 0x0C181000 },
         { .reg = 0x00009888, .val = 0x12195000 },
         { .reg = 0x00009888, .val = 0x14190001 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x12010000 },
         { .reg = 0x00009888, .val = 0x100B7C00 },
         { .reg = 0x00009888, .val = 0x100F0019 },
         { .reg = 0x00009888, .val = 0x10107C00 },
         { .reg = 0x00009888, .val = 0x16100000 },
         { .reg = 0x00009888, .val = 0x00110000 },
         { .reg = 0x00009888, .val = 0x120703C0 },
         { .reg = 0x00009888, .val = 0x10090000 },
         { .reg = 0x00009888, .val = 0x06010080 },
         { .reg = 0x00009888, .val = 0x0E014180 },
         { .reg = 0x00009888, .val = 0x10010000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x060B0015 },
         { .reg = 0x00009888, .val = 0x080B8000 },
         { .reg = 0x00009888, .val = 0x0A0B2000 },
         { .reg = 0x00009888, .val = 0x020BA000 },
         { .reg = 0x00009888, .val = 0x040BA000 },
         { .reg = 0x00009888, .val = 0x0E0E0A02 },
         { .reg = 0x00009888, .val = 0x0C0EA800 },
         { .reg = 0x00009888, .val = 0x020F0002 },
         { .reg = 0x00009888, .val = 0x180F0800 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x060F8000 },
         { .reg = 0x00009888, .val = 0x0A100017 },
         { .reg = 0x00009888, .val = 0x04107113 },
         { .reg = 0x00009888, .val = 0x18100020 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x08100000 },
         { .reg = 0x00009888, .val = 0x08110C40 },
         { .reg = 0x00009888, .val = 0x02110C80 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x06028000 },
         { .reg = 0x00009888, .val = 0x0E02C000 },
         { .reg = 0x00009888, .val = 0x00039000 },
         { .reg = 0x00009888, .val = 0x06036000 },
         { .reg = 0x00009888, .val = 0x0803A000 },
         { .reg = 0x00009888, .val = 0x0A032000 },
         { .reg = 0x00009888, .val = 0x0E035000 },
         { .reg = 0x00009888, .val = 0x0203A000 },
         { .reg = 0x00009888, .val = 0x0403A000 },
         { .reg = 0x00009888, .val = 0x00044000 },
         { .reg = 0x00009888, .val = 0x0E044000 },
         { .reg = 0x00009888, .val = 0x10068000 },
         { .reg = 0x00009888, .val = 0x12068000 },
         { .reg = 0x00009888, .val = 0x14068000 },
         { .reg = 0x00009888, .val = 0x02068000 },
         { .reg = 0x00009888, .val = 0x04068000 },
         { .reg = 0x00009888, .val = 0x06068000 },
         { .reg = 0x00009888, .val = 0x08068000 },
         { .reg = 0x00009888, .val = 0x0A068000 },
         { .reg = 0x00009888, .val = 0x0C068000 },
         { .reg = 0x00009888, .val = 0x00070032 },
         { .reg = 0x00009888, .val = 0x0E070033 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x08098011 },
         { .reg = 0x00009888, .val = 0x00090980 },
         { .reg = 0x00009888, .val = 0x18090A00 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x04098000 },
         { .reg = 0x00009888, .val = 0x06098000 },
         { .reg = 0x00009888, .val = 0x0A098000 },
         { .reg = 0x00009888, .val = 0x0C098000 },
         { .reg = 0x00009888, .val = 0x301F6000 },
         { .reg = 0x00009888, .val = 0x501F36DB },
         { .reg = 0x00009888, .val = 0x521F491B },
         { .reg = 0x00009888, .val = 0x541F001B },
         { .reg = 0x00009888, .val = 0x3A1F6000 },
         { .reg = 0x00009888, .val = 0x4E1F1B41 },
         { .reg = 0x00009888, .val = 0x3E1F2100 },
         { .reg = 0x00009888, .val = 0x461F4141 },
         { .reg = 0x00009888, .val = 0x481F1160 },
         { .reg = 0x00009888, .val = 0x4A1F1000 },
         { .reg = 0x00009888, .val = 0x4C1F2120 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x401F0141 },
         { .reg = 0x00009888, .val = 0x421F1160 },
         { .reg = 0x00009888, .val = 0x441F3111 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__render_pipe_profile__avg_gpu_core_frequency__max,icl__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,icl__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,icl__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,icl__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,icl__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,icl__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,icl__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,icl__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,icl__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,icl__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, icl__render_pipe_profile__slm_bytes_read__max,icl__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, icl__render_pipe_profile__slm_bytes_written__max,icl__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,icl__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,icl__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, icl__render_pipe_profile__l3_shader_throughput__max,icl__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,icl__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, percentage_max_float,icl__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, percentage_max_float,icl__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, percentage_max_float,icl__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, percentage_max_float,icl__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, percentage_max_float,icl__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, percentage_max_float,icl__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, percentage_max_float,icl__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, percentage_max_float,icl__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, percentage_max_float,icl__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, percentage_max_float,icl__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, percentage_max_float,icl__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, percentage_max_float,icl__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, percentage_max_float,icl__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, percentage_max_float,icl__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, percentage_max_float,icl__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, percentage_max_float,icl__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "c5cbc488-6569-41dd-9128-42bf6f0d317c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1223000A },
         { .reg = 0x00009888, .val = 0x10230009 },
         { .reg = 0x00009888, .val = 0x1263000A },
         { .reg = 0x00009888, .val = 0x10630009 },
         { .reg = 0x00009888, .val = 0x12A3000A },
         { .reg = 0x00009888, .val = 0x10A30009 },
         { .reg = 0x00009888, .val = 0x12E3000A },
         { .reg = 0x00009888, .val = 0x10E30009 },
         { .reg = 0x00009888, .val = 0x10150019 },
         { .reg = 0x00009888, .val = 0x1C20000A },
         { .reg = 0x00009888, .val = 0x0C231900 },
         { .reg = 0x00009888, .val = 0x0E23003C },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x1C600020 },
         { .reg = 0x00009888, .val = 0x02608000 },
         { .reg = 0x00009888, .val = 0x0E631900 },
         { .reg = 0x00009888, .val = 0x00631E00 },
         { .reg = 0x00009888, .val = 0x04A08000 },
         { .reg = 0x00009888, .val = 0x06A08000 },
         { .reg = 0x00009888, .val = 0x02A31E32 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x08E08000 },
         { .reg = 0x00009888, .val = 0x0AE08000 },
         { .reg = 0x00009888, .val = 0x04E31E32 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x10040150 },
         { .reg = 0x00009888, .val = 0x0E040015 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x14050054 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x24063F00 },
         { .reg = 0x00009888, .val = 0x260600E0 },
         { .reg = 0x00009888, .val = 0x0E088000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x14090040 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x080E5000 },
         { .reg = 0x00009888, .val = 0x1A120020 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x0412C000 },
         { .reg = 0x00009888, .val = 0x0612C000 },
         { .reg = 0x00009888, .val = 0x0A138000 },
         { .reg = 0x00009888, .val = 0x0413E000 },
         { .reg = 0x00009888, .val = 0x0E148000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x0214C000 },
         { .reg = 0x00009888, .val = 0x00150047 },
         { .reg = 0x00009888, .val = 0x16156000 },
         { .reg = 0x00009888, .val = 0x18150007 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08158000 },
         { .reg = 0x00009888, .val = 0x0A158000 },
         { .reg = 0x00009888, .val = 0x0C188000 },
         { .reg = 0x00009888, .val = 0x0E182000 },
         { .reg = 0x00009888, .val = 0x1419000A },
         { .reg = 0x00009888, .val = 0x021CA000 },
         { .reg = 0x00009888, .val = 0x0A1DA000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3061 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x521F4000 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x501F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0100 },
         { .reg = 0x00009888, .val = 0x4C1F3030 },
         { .reg = 0x00009888, .val = 0x401F0000 },
         { .reg = 0x00009888, .val = 0x421F3000 },
         { .reg = 0x00009888, .val = 0x441F3330 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FFFE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__hdc_and_sf__avg_gpu_core_frequency__max,icl__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,icl__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,icl__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,icl__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,icl__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,icl__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,icl__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,icl__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,icl__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,icl__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,icl__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,icl__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,icl__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,icl__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,icl__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,icl__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,icl__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,icl__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, icl__hdc_and_sf__slm_bytes_read__max,icl__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, icl__hdc_and_sf__slm_bytes_written__max,icl__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,icl__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,icl__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, icl__hdc_and_sf__l3_shader_throughput__max,icl__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,icl__hdc_and_sf__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 356, 240, percentage_max_float,icl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);

      intel_perf_query_add_counter_float(query, 357, 244, percentage_max_float,icl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);

      intel_perf_query_add_counter_float(query, 358, 248, percentage_max_float,icl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);

      intel_perf_query_add_counter_float(query, 359, 252, percentage_max_float,icl__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read);

      intel_perf_query_add_counter_float(query, 237, 256, percentage_max_float,icl__hdc_and_sf__poly_data_ready__read);

      intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,icl__hdc_and_sf__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "0316ce4f-e03f-4738-8262-13528fce8eea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x140A001F },
         { .reg = 0x00009888, .val = 0x040C5000 },
         { .reg = 0x00009888, .val = 0x140F001F },
         { .reg = 0x00009888, .val = 0x04115017 },
         { .reg = 0x00009888, .val = 0x10136000 },
         { .reg = 0x00009888, .val = 0x1213001C },
         { .reg = 0x00009888, .val = 0x16140000 },
         { .reg = 0x00009888, .val = 0x10160018 },
         { .reg = 0x00009888, .val = 0x101A0018 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x0E045545 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E051000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08051000 },
         { .reg = 0x00009888, .val = 0x2406DF00 },
         { .reg = 0x00009888, .val = 0x26060007 },
         { .reg = 0x00009888, .val = 0x00084000 },
         { .reg = 0x00009888, .val = 0x02084000 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x06094000 },
         { .reg = 0x00009888, .val = 0x000A3080 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x080A0000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x020C05C0 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020D1000 },
         { .reg = 0x00009888, .val = 0x040D1000 },
         { .reg = 0x00009888, .val = 0x060E1000 },
         { .reg = 0x00009888, .val = 0x080E1000 },
         { .reg = 0x00009888, .val = 0x020F0061 },
         { .reg = 0x00009888, .val = 0x160F0000 },
         { .reg = 0x00009888, .val = 0x0A0F0000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x08110000 },
         { .reg = 0x00009888, .val = 0x18120C00 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x06128000 },
         { .reg = 0x00009888, .val = 0x0613092F },
         { .reg = 0x00009888, .val = 0x08134025 },
         { .reg = 0x00009888, .val = 0x0C130000 },
         { .reg = 0x00009888, .val = 0x0413A000 },
         { .reg = 0x00009888, .val = 0x00148066 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x0614C000 },
         { .reg = 0x00009888, .val = 0x08144000 },
         { .reg = 0x00009888, .val = 0x0A144000 },
         { .reg = 0x00009888, .val = 0x02148000 },
         { .reg = 0x00009888, .val = 0x00154000 },
         { .reg = 0x00009888, .val = 0x0E154000 },
         { .reg = 0x00009888, .val = 0x161500E8 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04158000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08158000 },
         { .reg = 0x00009888, .val = 0x0C154000 },
         { .reg = 0x00009888, .val = 0x08161000 },
         { .reg = 0x00009888, .val = 0x08184000 },
         { .reg = 0x00009888, .val = 0x12190100 },
         { .reg = 0x00009888, .val = 0x0A1A0020 },
         { .reg = 0x00009888, .val = 0x081A0000 },
         { .reg = 0x00009888, .val = 0x0A1C1000 },
         { .reg = 0x00009888, .val = 0x121D0400 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3000 },
         { .reg = 0x00009888, .val = 0x1A1F0061 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4904 },
         { .reg = 0x00009888, .val = 0x521F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x3E1F6000 },
         { .reg = 0x00009888, .val = 0x461F5050 },
         { .reg = 0x00009888, .val = 0x481F1040 },
         { .reg = 0x00009888, .val = 0x401F4010 },
         { .reg = 0x00009888, .val = 0x421F3000 },
         { .reg = 0x00009888, .val = 0x441F5033 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000038 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFF7 },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFEF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,icl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,icl__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,icl__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,icl__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,icl__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,icl__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,icl__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,icl__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,icl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,icl__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,icl__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,icl__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,icl__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,icl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,icl__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,icl__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,icl__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,icl__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, icl__rasterizer_and_pixel_backend__slm_bytes_read__max,icl__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, icl__rasterizer_and_pixel_backend__slm_bytes_written__max,icl__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,icl__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,icl__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, icl__rasterizer_and_pixel_backend__l3_shader_throughput__max,icl__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,icl__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 266, 240, percentage_max_float,icl__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 261, 244, percentage_max_float,icl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 360, 248, percentage_max_float,icl__rasterizer_and_pixel_backend__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 361, 252, percentage_max_float,icl__rasterizer_and_pixel_backend__pixel_data01_ready__read);

      intel_perf_query_add_counter_float(query, 362, 256, percentage_max_float,icl__rasterizer_and_pixel_backend__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 363, 260, percentage_max_float,icl__rasterizer_and_pixel_backend__ps_output01_available__read);

      intel_perf_query_add_counter_float(query, 364, 264, percentage_max_float,icl__rasterizer_and_pixel_backend__pixel_values00_ready__read);

      intel_perf_query_add_counter_float(query, 365, 268, percentage_max_float,icl__rasterizer_and_pixel_backend__pixel_values01_ready__read);

      intel_perf_query_add_counter_float(query, 244, 272, percentage_max_float,icl__rasterizer_and_pixel_backend__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "21d69ec3-91e1-48a8-acd6-c0c4ec6e819a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x17340000 },
         { .reg = 0x00009888, .val = 0x17740000 },
         { .reg = 0x00009888, .val = 0x17B40000 },
         { .reg = 0x00009888, .val = 0x17F40000 },
         { .reg = 0x00009888, .val = 0x16340000 },
         { .reg = 0x00009888, .val = 0x16740000 },
         { .reg = 0x00009888, .val = 0x16B40000 },
         { .reg = 0x00009888, .val = 0x16F40000 },
         { .reg = 0x00009888, .val = 0x07340037 },
         { .reg = 0x00009888, .val = 0x21340000 },
         { .reg = 0x00009888, .val = 0x09740037 },
         { .reg = 0x00009888, .val = 0x21740000 },
         { .reg = 0x00009888, .val = 0x0BB40037 },
         { .reg = 0x00009888, .val = 0x21B40000 },
         { .reg = 0x00009888, .val = 0x0DF40037 },
         { .reg = 0x00009888, .val = 0x21F40000 },
         { .reg = 0x00009888, .val = 0x0E0000A7 },
         { .reg = 0x00009888, .val = 0x08012000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x0C038000 },
         { .reg = 0x00009888, .val = 0x1C340037 },
         { .reg = 0x00009888, .val = 0x20340000 },
         { .reg = 0x00009888, .val = 0x1E740037 },
         { .reg = 0x00009888, .val = 0x20740000 },
         { .reg = 0x00009888, .val = 0x02B40037 },
         { .reg = 0x00009888, .val = 0x20B40000 },
         { .reg = 0x00009888, .val = 0x04F40037 },
         { .reg = 0x00009888, .val = 0x20F40000 },
         { .reg = 0x00009888, .val = 0x10040200 },
         { .reg = 0x00009888, .val = 0x0E040055 },
         { .reg = 0x00009888, .val = 0x14050070 },
         { .reg = 0x00009888, .val = 0x04058000 },
         { .reg = 0x00009888, .val = 0x06056000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x0A051000 },
         { .reg = 0x00009888, .val = 0x260600C0 },
         { .reg = 0x00009888, .val = 0x24067E00 },
         { .reg = 0x00009888, .val = 0x02074000 },
         { .reg = 0x00009888, .val = 0x04078000 },
         { .reg = 0x00009888, .val = 0x06124000 },
         { .reg = 0x00009888, .val = 0x08124000 },
         { .reg = 0x00009888, .val = 0x0A124000 },
         { .reg = 0x00009888, .val = 0x0C124000 },
         { .reg = 0x00009888, .val = 0x04138000 },
         { .reg = 0x00009888, .val = 0x06137000 },
         { .reg = 0x00009888, .val = 0x02148000 },
         { .reg = 0x00009888, .val = 0x0414C000 },
         { .reg = 0x00009888, .val = 0x06144000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08154000 },
         { .reg = 0x00009888, .val = 0x0A154000 },
         { .reg = 0x00009888, .val = 0x0C154000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3000 },
         { .reg = 0x00009888, .val = 0x2A1F0061 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x521F0000 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2460 },
         { .reg = 0x00009888, .val = 0x501F0124 },
         { .reg = 0x00009888, .val = 0x4C1F0133 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009888, .val = 0x401F6060 },
         { .reg = 0x00009888, .val = 0x421F0010 },
         { .reg = 0x00009888, .val = 0x441F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__l3_1__avg_gpu_core_frequency__max,icl__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,icl__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,icl__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,icl__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,icl__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,icl__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,icl__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,icl__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,icl__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,icl__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,icl__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,icl__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,icl__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,icl__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,icl__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,icl__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,icl__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,icl__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, icl__l3_1__slm_bytes_read__max,icl__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, icl__l3_1__slm_bytes_written__max,icl__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,icl__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,icl__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, icl__l3_1__l3_shader_throughput__max,icl__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,icl__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 252, 240, percentage_max_float,icl__l3_1__l30_bank0_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 251, 244, percentage_max_float,icl__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 260, 248, percentage_max_float,icl__l3_1__l30_bank2_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 256, 252, percentage_max_float,icl__l3_1__l30_bank3_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 366, 256, percentage_max_float,icl__l3_1__l30_bank4_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 367, 260, percentage_max_float,icl__l3_1__l30_bank5_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 368, 264, percentage_max_float,icl__l3_1__l30_bank6_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 369, 268, percentage_max_float,icl__l3_1__l30_bank7_active__read);
      }

      intel_perf_query_add_counter_float(query, 244, 272, percentage_max_float,icl__l3_1__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "L2Bank0 stalled metric set";
   query->symbol_name = "L3_2";
   query->guid = "e60e9155-6830-4aec-baf2-1c3c15a73869";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x10050C00 },
         { .reg = 0x00009888, .val = 0x12050002 },
         { .reg = 0x00009888, .val = 0x00050025 },
         { .reg = 0x00009888, .val = 0x06050900 },
         { .reg = 0x00009888, .val = 0x080508EA },
         { .reg = 0x00009888, .val = 0x0A0508AB },
         { .reg = 0x00009888, .val = 0x0C050A21 },
         { .reg = 0x00009888, .val = 0x0E050A60 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x14050000 },
         { .reg = 0x00009888, .val = 0x24068100 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4800 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x4E1F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000022 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000082 },
         { .reg = 0x0000277C, .val = 0x0000FFE7 },
         { .reg = 0x00002780, .val = 0x00000402 },
         { .reg = 0x00002784, .val = 0x0000FF1F },
         { .reg = 0x00002788, .val = 0x00001002 },
         { .reg = 0x0000278C, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
         { .reg = 0x0000E55C, .val = 0x00000053 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__l3_2__avg_gpu_core_frequency__max,icl__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__l3_2__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 139, 80, NULL,icl__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 88, NULL,icl__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 96, NULL,icl__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 104, NULL,icl__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 112, NULL,icl__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 120, NULL,icl__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 128, NULL,icl__l3_2__samples_blended__read);

      intel_perf_query_add_counter_float(query, 10, 136, percentage_max_float,icl__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 140, percentage_max_float,icl__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 144, percentage_max_float,icl__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 148, percentage_max_float,icl__l3_2__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 124, 152, percentage_max_float,icl__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 156, percentage_max_float,icl__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 160, percentage_max_float,icl__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 164, percentage_max_float,icl__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 168, percentage_max_float,icl__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 172, percentage_max_float,icl__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 176, percentage_max_float,icl__l3_2__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 249, 180, percentage_max_float,icl__l3_2__l30_bank0_stalled__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "L2Bank1 stalled metric set";
   query->symbol_name = "L3_3";
   query->guid = "47c364d5-1799-4d17-9447-add9358c6451";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x10050400 },
         { .reg = 0x00009888, .val = 0x12050000 },
         { .reg = 0x00009888, .val = 0x00050025 },
         { .reg = 0x00009888, .val = 0x06050900 },
         { .reg = 0x00009888, .val = 0x080508EA },
         { .reg = 0x00009888, .val = 0x0A0508AB },
         { .reg = 0x00009888, .val = 0x0C050A21 },
         { .reg = 0x00009888, .val = 0x0E050A60 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x14050000 },
         { .reg = 0x00009888, .val = 0x24068100 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4800 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x4E1F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000022 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000082 },
         { .reg = 0x0000277C, .val = 0x0000FFE7 },
         { .reg = 0x00002780, .val = 0x00000402 },
         { .reg = 0x00002784, .val = 0x0000FF1F },
         { .reg = 0x00002788, .val = 0x00001002 },
         { .reg = 0x0000278C, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
         { .reg = 0x0000E55C, .val = 0x00000053 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__l3_3__avg_gpu_core_frequency__max,icl__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__l3_3__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 139, 80, NULL,icl__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 88, NULL,icl__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 96, NULL,icl__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 104, NULL,icl__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 112, NULL,icl__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 120, NULL,icl__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 128, NULL,icl__l3_3__samples_blended__read);

      intel_perf_query_add_counter_float(query, 10, 136, percentage_max_float,icl__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 140, percentage_max_float,icl__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 144, percentage_max_float,icl__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 148, percentage_max_float,icl__l3_3__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 124, 152, percentage_max_float,icl__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 156, percentage_max_float,icl__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 160, percentage_max_float,icl__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 164, percentage_max_float,icl__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 168, percentage_max_float,icl__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 172, percentage_max_float,icl__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 176, percentage_max_float,icl__l3_3__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 250, 180, percentage_max_float,icl__l3_3__l30_bank1_stalled__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_l3_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "L2Bank4 stalled metric set";
   query->symbol_name = "L3_4";
   query->guid = "e5ab5c08-3130-4469-8eaf-b23d3dc817d4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x10010C00 },
         { .reg = 0x00009888, .val = 0x12010002 },
         { .reg = 0x00009888, .val = 0x0C000400 },
         { .reg = 0x00009888, .val = 0x0E005500 },
         { .reg = 0x00009888, .val = 0x10000155 },
         { .reg = 0x00009888, .val = 0x00010025 },
         { .reg = 0x00009888, .val = 0x06010900 },
         { .reg = 0x00009888, .val = 0x080108EA },
         { .reg = 0x00009888, .val = 0x0A0108AB },
         { .reg = 0x00009888, .val = 0x0C010A21 },
         { .reg = 0x00009888, .val = 0x0E010A60 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x14010000 },
         { .reg = 0x00009888, .val = 0x0C040400 },
         { .reg = 0x00009888, .val = 0x0E045500 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04051000 },
         { .reg = 0x00009888, .val = 0x0A054000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x24068100 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0E124000 },
         { .reg = 0x00009888, .val = 0x18125540 },
         { .reg = 0x00009888, .val = 0x1A120015 },
         { .reg = 0x00009888, .val = 0x04131000 },
         { .reg = 0x00009888, .val = 0x06138000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x00144000 },
         { .reg = 0x00009888, .val = 0x06148000 },
         { .reg = 0x00009888, .val = 0x0814C000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00154000 },
         { .reg = 0x00009888, .val = 0x0E154000 },
         { .reg = 0x00009888, .val = 0x16152AA8 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4800 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x4E1F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000022 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000082 },
         { .reg = 0x0000277C, .val = 0x0000FFE7 },
         { .reg = 0x00002780, .val = 0x00000402 },
         { .reg = 0x00002784, .val = 0x0000FF1F },
         { .reg = 0x00002788, .val = 0x00001002 },
         { .reg = 0x0000278C, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
         { .reg = 0x0000E55C, .val = 0x00000053 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__l3_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__l3_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__l3_4__avg_gpu_core_frequency__max,icl__l3_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__l3_4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__l3_4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__l3_4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__l3_4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__l3_4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__l3_4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__l3_4__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 139, 80, NULL,icl__l3_4__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 88, NULL,icl__l3_4__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 96, NULL,icl__l3_4__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 104, NULL,icl__l3_4__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 112, NULL,icl__l3_4__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 120, NULL,icl__l3_4__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 128, NULL,icl__l3_4__samples_blended__read);

      intel_perf_query_add_counter_float(query, 10, 136, percentage_max_float,icl__l3_4__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 140, percentage_max_float,icl__l3_4__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 144, percentage_max_float,icl__l3_4__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 148, percentage_max_float,icl__l3_4__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 124, 152, percentage_max_float,icl__l3_4__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 156, percentage_max_float,icl__l3_4__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 160, percentage_max_float,icl__l3_4__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 164, percentage_max_float,icl__l3_4__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 168, percentage_max_float,icl__l3_4__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 172, percentage_max_float,icl__l3_4__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 176, percentage_max_float,icl__l3_4__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 370, 180, percentage_max_float,icl__l3_4__l30_bank4_stalled__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_l3_5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "L2Bank5 stalled metric set";
   query->symbol_name = "L3_5";
   query->guid = "6cdf23c1-f725-414c-959a-c90fa5571b1f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x10010400 },
         { .reg = 0x00009888, .val = 0x12010000 },
         { .reg = 0x00009888, .val = 0x0C000400 },
         { .reg = 0x00009888, .val = 0x0E005500 },
         { .reg = 0x00009888, .val = 0x10000155 },
         { .reg = 0x00009888, .val = 0x00010022 },
         { .reg = 0x00009888, .val = 0x06010840 },
         { .reg = 0x00009888, .val = 0x08010828 },
         { .reg = 0x00009888, .val = 0x0A010969 },
         { .reg = 0x00009888, .val = 0x0C010AA4 },
         { .reg = 0x00009888, .val = 0x0E010AE3 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x14010000 },
         { .reg = 0x00009888, .val = 0x0C040400 },
         { .reg = 0x00009888, .val = 0x0E045500 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04051000 },
         { .reg = 0x00009888, .val = 0x0A054000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x24068100 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0E124000 },
         { .reg = 0x00009888, .val = 0x18125540 },
         { .reg = 0x00009888, .val = 0x1A120015 },
         { .reg = 0x00009888, .val = 0x04131000 },
         { .reg = 0x00009888, .val = 0x06138000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x00144000 },
         { .reg = 0x00009888, .val = 0x06148000 },
         { .reg = 0x00009888, .val = 0x0814C000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00154000 },
         { .reg = 0x00009888, .val = 0x0E154000 },
         { .reg = 0x00009888, .val = 0x16152AA8 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4800 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x4E1F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000022 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000082 },
         { .reg = 0x0000277C, .val = 0x0000FFE7 },
         { .reg = 0x00002780, .val = 0x00000402 },
         { .reg = 0x00002784, .val = 0x0000FF1F },
         { .reg = 0x00002788, .val = 0x00001002 },
         { .reg = 0x0000278C, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
         { .reg = 0x0000E55C, .val = 0x00000053 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__l3_5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__l3_5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__l3_5__avg_gpu_core_frequency__max,icl__l3_5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__l3_5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__l3_5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__l3_5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__l3_5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__l3_5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__l3_5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__l3_5__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 139, 80, NULL,icl__l3_5__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 88, NULL,icl__l3_5__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 96, NULL,icl__l3_5__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 104, NULL,icl__l3_5__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 112, NULL,icl__l3_5__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 120, NULL,icl__l3_5__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 128, NULL,icl__l3_5__samples_blended__read);

      intel_perf_query_add_counter_float(query, 10, 136, percentage_max_float,icl__l3_5__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 140, percentage_max_float,icl__l3_5__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 144, percentage_max_float,icl__l3_5__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 148, percentage_max_float,icl__l3_5__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 124, 152, percentage_max_float,icl__l3_5__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 156, percentage_max_float,icl__l3_5__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 160, percentage_max_float,icl__l3_5__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 164, percentage_max_float,icl__l3_5__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 168, percentage_max_float,icl__l3_5__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 172, percentage_max_float,icl__l3_5__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 176, percentage_max_float,icl__l3_5__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 371, 180, percentage_max_float,icl__l3_5__l30_bank5_stalled__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Metric set Sampler 1";
   query->symbol_name = "Sampler_1";
   query->guid = "51a2eb6d-9fad-4489-8f22-ab845fe7882a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x142A0165 },
         { .reg = 0x00009888, .val = 0x142F0165 },
         { .reg = 0x00009888, .val = 0x146A0165 },
         { .reg = 0x00009888, .val = 0x146F0165 },
         { .reg = 0x00009888, .val = 0x14AA0165 },
         { .reg = 0x00009888, .val = 0x14AF0165 },
         { .reg = 0x00009888, .val = 0x14EA0165 },
         { .reg = 0x00009888, .val = 0x14EF0165 },
         { .reg = 0x00009888, .val = 0x161E8000 },
         { .reg = 0x00009888, .val = 0x181EC000 },
         { .reg = 0x00009888, .val = 0x1A1E0400 },
         { .reg = 0x00009888, .val = 0x061F8000 },
         { .reg = 0x00009888, .val = 0x081F8000 },
         { .reg = 0x00009888, .val = 0x0A1F8000 },
         { .reg = 0x00009888, .val = 0x0C1F0400 },
         { .reg = 0x00009888, .val = 0x06204000 },
         { .reg = 0x00009888, .val = 0x08204000 },
         { .reg = 0x00009888, .val = 0x0A204000 },
         { .reg = 0x00009888, .val = 0x0C204000 },
         { .reg = 0x00009888, .val = 0x06218000 },
         { .reg = 0x00009888, .val = 0x08218000 },
         { .reg = 0x00009888, .val = 0x0A218000 },
         { .reg = 0x00009888, .val = 0x0C218000 },
         { .reg = 0x00009888, .val = 0x042A1800 },
         { .reg = 0x00009888, .val = 0x062AC038 },
         { .reg = 0x00009888, .val = 0x102A0000 },
         { .reg = 0x00009888, .val = 0x082AC000 },
         { .reg = 0x00009888, .val = 0x0A2A0000 },
         { .reg = 0x00009888, .val = 0x0C2A0000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x182C0002 },
         { .reg = 0x00009888, .val = 0x022F2000 },
         { .reg = 0x00009888, .val = 0x042F0048 },
         { .reg = 0x00009888, .val = 0x102F0000 },
         { .reg = 0x00009888, .val = 0x1C5E000C },
         { .reg = 0x00009888, .val = 0x125E8000 },
         { .reg = 0x00009888, .val = 0x145E8000 },
         { .reg = 0x00009888, .val = 0x0E5F000C },
         { .reg = 0x00009888, .val = 0x025F8000 },
         { .reg = 0x00009888, .val = 0x045F8000 },
         { .reg = 0x00009888, .val = 0x1C600014 },
         { .reg = 0x00009888, .val = 0x02604000 },
         { .reg = 0x00009888, .val = 0x04604000 },
         { .reg = 0x00009888, .val = 0x16612800 },
         { .reg = 0x00009888, .val = 0x02618000 },
         { .reg = 0x00009888, .val = 0x04618000 },
         { .reg = 0x00009888, .val = 0x006A1800 },
         { .reg = 0x00009888, .val = 0x026A0038 },
         { .reg = 0x00009888, .val = 0x106A0000 },
         { .reg = 0x00009888, .val = 0x1A6A00F0 },
         { .reg = 0x00009888, .val = 0x046A0000 },
         { .reg = 0x00009888, .val = 0x1A6C000A },
         { .reg = 0x00009888, .val = 0x066C8000 },
         { .reg = 0x00009888, .val = 0x086C8000 },
         { .reg = 0x00009888, .val = 0x0E6F2440 },
         { .reg = 0x00009888, .val = 0x106F0000 },
         { .reg = 0x00009888, .val = 0x1A9EC000 },
         { .reg = 0x00009888, .val = 0x1C9E0003 },
         { .reg = 0x00009888, .val = 0x0C9FC000 },
         { .reg = 0x00009888, .val = 0x0E9F0003 },
         { .reg = 0x00009888, .val = 0x1AA02A00 },
         { .reg = 0x00009888, .val = 0x1CA00001 },
         { .reg = 0x00009888, .val = 0x16A102A8 },
         { .reg = 0x00009888, .val = 0x0CAA1C30 },
         { .reg = 0x00009888, .val = 0x10AA0000 },
         { .reg = 0x00009888, .val = 0x18AAF000 },
         { .reg = 0x00009888, .val = 0x1AAA0000 },
         { .reg = 0x00009888, .val = 0x18ACAA00 },
         { .reg = 0x00009888, .val = 0x0AAF2440 },
         { .reg = 0x00009888, .val = 0x10AF0000 },
         { .reg = 0x00009888, .val = 0x10DE8000 },
         { .reg = 0x00009888, .val = 0x1ADE3800 },
         { .reg = 0x00009888, .val = 0x00DF8000 },
         { .reg = 0x00009888, .val = 0x0CDF3800 },
         { .reg = 0x00009888, .val = 0x00E04000 },
         { .reg = 0x00009888, .val = 0x0EE04000 },
         { .reg = 0x00009888, .val = 0x1AE000A0 },
         { .reg = 0x00009888, .val = 0x00E18000 },
         { .reg = 0x00009888, .val = 0x0EE18000 },
         { .reg = 0x00009888, .val = 0x14E18000 },
         { .reg = 0x00009888, .val = 0x16E10002 },
         { .reg = 0x00009888, .val = 0x08EA1C30 },
         { .reg = 0x00009888, .val = 0x10EA0000 },
         { .reg = 0x00009888, .val = 0x00EAC000 },
         { .reg = 0x00009888, .val = 0x0EEAC000 },
         { .reg = 0x00009888, .val = 0x18EA0000 },
         { .reg = 0x00009888, .val = 0x04EC8000 },
         { .reg = 0x00009888, .val = 0x18EC00A8 },
         { .reg = 0x00009888, .val = 0x00EF0040 },
         { .reg = 0x00009888, .val = 0x06EF2400 },
         { .reg = 0x00009888, .val = 0x10EF0000 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x0E045555 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x2406FF00 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x0E08A000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009888, .val = 0x14090050 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x06091000 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x040E1000 },
         { .reg = 0x00009888, .val = 0x0A0E4000 },
         { .reg = 0x00009888, .val = 0x0C0E5000 },
         { .reg = 0x00009888, .val = 0x1812FC00 },
         { .reg = 0x00009888, .val = 0x1A12002B },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x0813C000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x04136000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02144000 },
         { .reg = 0x00009888, .val = 0x00158000 },
         { .reg = 0x00009888, .val = 0x0E158000 },
         { .reg = 0x00009888, .val = 0x16152AD0 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x0615C000 },
         { .reg = 0x00009888, .val = 0x0815C000 },
         { .reg = 0x00009888, .val = 0x0A15C000 },
         { .reg = 0x00009888, .val = 0x0C15C000 },
         { .reg = 0x00009888, .val = 0x02188000 },
         { .reg = 0x00009888, .val = 0x0418A000 },
         { .reg = 0x00009888, .val = 0x06182000 },
         { .reg = 0x00009888, .val = 0x0A198000 },
         { .reg = 0x00009888, .val = 0x0C19A000 },
         { .reg = 0x00009888, .val = 0x0E192000 },
         { .reg = 0x00009888, .val = 0x0A1CA000 },
         { .reg = 0x00009888, .val = 0x0C1CA000 },
         { .reg = 0x00009888, .val = 0x121D5400 },
         { .reg = 0x00009888, .val = 0x141D0002 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4924 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x3E1F3000 },
         { .reg = 0x00009888, .val = 0x461F4030 },
         { .reg = 0x00009888, .val = 0x481F0040 },
         { .reg = 0x00009888, .val = 0x4A1F1000 },
         { .reg = 0x00009888, .val = 0x4C1F0010 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x401F1010 },
         { .reg = 0x00009888, .val = 0x421F3030 },
         { .reg = 0x00009888, .val = 0x441F4040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00000018 },
         { .reg = 0x00002774, .val = 0x0000FFFC },
         { .reg = 0x00002778, .val = 0x00000060 },
         { .reg = 0x0000277C, .val = 0x0000FFF3 },
         { .reg = 0x00002780, .val = 0x00000180 },
         { .reg = 0x00002784, .val = 0x0000FFCF },
         { .reg = 0x00002788, .val = 0x00000600 },
         { .reg = 0x0000278C, .val = 0x0000FF3F },
         { .reg = 0x00002790, .val = 0x00001800 },
         { .reg = 0x00002794, .val = 0x0000FCFF },
         { .reg = 0x00002798, .val = 0x00006000 },
         { .reg = 0x0000279C, .val = 0x0000F3FF },
         { .reg = 0x000027A0, .val = 0x00018000 },
         { .reg = 0x000027A4, .val = 0x0000CFFF },
         { .reg = 0x000027A8, .val = 0x00060000 },
         { .reg = 0x000027AC, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__sampler_1__avg_gpu_core_frequency__max,icl__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__sampler_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__sampler_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__sampler_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__sampler_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__sampler_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__sampler_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__sampler_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__sampler_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__sampler_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,icl__sampler_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,icl__sampler_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,icl__sampler_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,icl__sampler_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,icl__sampler_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,icl__sampler_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,icl__sampler_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,icl__sampler_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,icl__sampler_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,icl__sampler_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,icl__sampler_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,icl__sampler_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,icl__sampler_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,icl__sampler_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,icl__sampler_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,icl__sampler_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,icl__sampler_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, icl__sampler_1__slm_bytes_read__max,icl__sampler_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, icl__sampler_1__slm_bytes_written__max,icl__sampler_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,icl__sampler_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,icl__sampler_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, icl__sampler_1__l3_shader_throughput__max,icl__sampler_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,icl__sampler_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 279, 240, percentage_max_float,icl__sampler_1__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 277, 244, percentage_max_float,icl__sampler_1__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 278, 248, percentage_max_float,icl__sampler_1__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 372, 252, percentage_max_float,icl__sampler_1__sampler03_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 373, 256, percentage_max_float,icl__sampler_1__sampler04_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 374, 260, percentage_max_float,icl__sampler_1__sampler05_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 375, 264, percentage_max_float,icl__sampler_1__sampler06_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 376, 268, percentage_max_float,icl__sampler_1__sampler07_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_sampler_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Metric set Sampler 2";
   query->symbol_name = "Sampler_2";
   query->guid = "afc0f021-8c33-4d60-803d-93487f96c7c1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x142D0005 },
         { .reg = 0x00009888, .val = 0x14320005 },
         { .reg = 0x00009888, .val = 0x146D0005 },
         { .reg = 0x00009888, .val = 0x14720005 },
         { .reg = 0x00009888, .val = 0x14AD0005 },
         { .reg = 0x00009888, .val = 0x14B20005 },
         { .reg = 0x00009888, .val = 0x14ED0005 },
         { .reg = 0x00009888, .val = 0x14F20005 },
         { .reg = 0x00009888, .val = 0x1C1E000C },
         { .reg = 0x00009888, .val = 0x0E1F000C },
         { .reg = 0x00009888, .val = 0x1C200014 },
         { .reg = 0x00009888, .val = 0x16212800 },
         { .reg = 0x00009888, .val = 0x22290010 },
         { .reg = 0x00009888, .val = 0x1A2A00D0 },
         { .reg = 0x00009888, .val = 0x1A2C000A },
         { .reg = 0x00009888, .val = 0x0E2D0033 },
         { .reg = 0x00009888, .val = 0x022D0000 },
         { .reg = 0x00009888, .val = 0x0E2F8000 },
         { .reg = 0x00009888, .val = 0x1E300080 },
         { .reg = 0x00009888, .val = 0x1A310008 },
         { .reg = 0x00009888, .val = 0x0E321980 },
         { .reg = 0x00009888, .val = 0x02320000 },
         { .reg = 0x00009888, .val = 0x125E8000 },
         { .reg = 0x00009888, .val = 0x145E8000 },
         { .reg = 0x00009888, .val = 0x025F8000 },
         { .reg = 0x00009888, .val = 0x045F8000 },
         { .reg = 0x00009888, .val = 0x02604000 },
         { .reg = 0x00009888, .val = 0x04604000 },
         { .reg = 0x00009888, .val = 0x02618000 },
         { .reg = 0x00009888, .val = 0x04618000 },
         { .reg = 0x00009888, .val = 0x12698000 },
         { .reg = 0x00009888, .val = 0x026A4000 },
         { .reg = 0x00009888, .val = 0x046AC000 },
         { .reg = 0x00009888, .val = 0x066C8000 },
         { .reg = 0x00009888, .val = 0x086C8000 },
         { .reg = 0x00009888, .val = 0x006D1980 },
         { .reg = 0x00009888, .val = 0x026D0000 },
         { .reg = 0x00009888, .val = 0x026F4000 },
         { .reg = 0x00009888, .val = 0x1A702000 },
         { .reg = 0x00009888, .val = 0x08718000 },
         { .reg = 0x00009888, .val = 0x02720033 },
         { .reg = 0x00009888, .val = 0x169E8000 },
         { .reg = 0x00009888, .val = 0x189E4000 },
         { .reg = 0x00009888, .val = 0x069F8000 },
         { .reg = 0x00009888, .val = 0x089F8000 },
         { .reg = 0x00009888, .val = 0x06A04000 },
         { .reg = 0x00009888, .val = 0x08A04000 },
         { .reg = 0x00009888, .val = 0x06A18000 },
         { .reg = 0x00009888, .val = 0x08A18000 },
         { .reg = 0x00009888, .val = 0x16A98000 },
         { .reg = 0x00009888, .val = 0x06AA4000 },
         { .reg = 0x00009888, .val = 0x08AAC000 },
         { .reg = 0x00009888, .val = 0x0AAC8000 },
         { .reg = 0x00009888, .val = 0x0CAC8000 },
         { .reg = 0x00009888, .val = 0x02AD1980 },
         { .reg = 0x00009888, .val = 0x04AF4000 },
         { .reg = 0x00009888, .val = 0x1CB00002 },
         { .reg = 0x00009888, .val = 0x0CB18000 },
         { .reg = 0x00009888, .val = 0x04B20033 },
         { .reg = 0x00009888, .val = 0x02B20000 },
         { .reg = 0x00009888, .val = 0x18DE8000 },
         { .reg = 0x00009888, .val = 0x1ADE0400 },
         { .reg = 0x00009888, .val = 0x0ADF8000 },
         { .reg = 0x00009888, .val = 0x0CDF0400 },
         { .reg = 0x00009888, .val = 0x0AE04000 },
         { .reg = 0x00009888, .val = 0x0CE04000 },
         { .reg = 0x00009888, .val = 0x0AE18000 },
         { .reg = 0x00009888, .val = 0x0CE18000 },
         { .reg = 0x00009888, .val = 0x1EE98000 },
         { .reg = 0x00009888, .val = 0x0AEA4000 },
         { .reg = 0x00009888, .val = 0x0CEAC000 },
         { .reg = 0x00009888, .val = 0x0EEC8000 },
         { .reg = 0x00009888, .val = 0x18EC0002 },
         { .reg = 0x00009888, .val = 0x04ED1980 },
         { .reg = 0x00009888, .val = 0x02ED0000 },
         { .reg = 0x00009888, .val = 0x06EF4000 },
         { .reg = 0x00009888, .val = 0x1CF00020 },
         { .reg = 0x00009888, .val = 0x18F10002 },
         { .reg = 0x00009888, .val = 0x06F20033 },
         { .reg = 0x00009888, .val = 0x02F20000 },
         { .reg = 0x00009888, .val = 0x10040140 },
         { .reg = 0x00009888, .val = 0x0C045000 },
         { .reg = 0x00009888, .val = 0x0E040055 },
         { .reg = 0x00009888, .val = 0x14050050 },
         { .reg = 0x00009888, .val = 0x04054000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x0A051000 },
         { .reg = 0x00009888, .val = 0x260600C0 },
         { .reg = 0x00009888, .val = 0x24067E00 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x06091000 },
         { .reg = 0x00009888, .val = 0x040D8000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x080E4000 },
         { .reg = 0x00009888, .val = 0x0A0E1000 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x0612C000 },
         { .reg = 0x00009888, .val = 0x0812C000 },
         { .reg = 0x00009888, .val = 0x0413E000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x0214C000 },
         { .reg = 0x00009888, .val = 0x04144000 },
         { .reg = 0x00009888, .val = 0x1815000F },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08154000 },
         { .reg = 0x00009888, .val = 0x0A158000 },
         { .reg = 0x00009888, .val = 0x0C158000 },
         { .reg = 0x00009888, .val = 0x0E18A000 },
         { .reg = 0x00009888, .val = 0x14190028 },
         { .reg = 0x00009888, .val = 0x021C8000 },
         { .reg = 0x00009888, .val = 0x041C2000 },
         { .reg = 0x00009888, .val = 0x0A1D8000 },
         { .reg = 0x00009888, .val = 0x0C1D2000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3000 },
         { .reg = 0x00009888, .val = 0x2A1F0061 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x521F0000 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2430 },
         { .reg = 0x00009888, .val = 0x501F0124 },
         { .reg = 0x00009888, .val = 0x4C1F5047 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009888, .val = 0x401F0020 },
         { .reg = 0x00009888, .val = 0x421F0020 },
         { .reg = 0x00009888, .val = 0x441F3050 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__sampler_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__sampler_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__sampler_2__avg_gpu_core_frequency__max,icl__sampler_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__sampler_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__sampler_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__sampler_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__sampler_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__sampler_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__sampler_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__sampler_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__sampler_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__sampler_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,icl__sampler_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,icl__sampler_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,icl__sampler_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,icl__sampler_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,icl__sampler_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,icl__sampler_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,icl__sampler_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,icl__sampler_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,icl__sampler_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,icl__sampler_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,icl__sampler_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,icl__sampler_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,icl__sampler_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,icl__sampler_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,icl__sampler_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,icl__sampler_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,icl__sampler_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, icl__sampler_2__slm_bytes_read__max,icl__sampler_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, icl__sampler_2__slm_bytes_written__max,icl__sampler_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,icl__sampler_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,icl__sampler_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, icl__sampler_2__l3_shader_throughput__max,icl__sampler_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,icl__sampler_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 281, 240, percentage_max_float,icl__sampler_2__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 282, 244, percentage_max_float,icl__sampler_2__sampler01_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 280, 248, percentage_max_float,icl__sampler_2__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 377, 252, percentage_max_float,icl__sampler_2__sampler03_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 378, 256, percentage_max_float,icl__sampler_2__sampler04_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 379, 260, percentage_max_float,icl__sampler_2__sampler05_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 380, 264, percentage_max_float,icl__sampler_2__sampler06_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 381, 268, percentage_max_float,icl__sampler_2__sampler07_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 244, 272, percentage_max_float,icl__sampler_2__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 51);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "eddc2f32-b196-4a72-9bf8-21770e35f8bd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14290000 },
         { .reg = 0x00009888, .val = 0x142E0000 },
         { .reg = 0x00009888, .val = 0x14690000 },
         { .reg = 0x00009888, .val = 0x146E0000 },
         { .reg = 0x00009888, .val = 0x14A90000 },
         { .reg = 0x00009888, .val = 0x14AE0000 },
         { .reg = 0x00009888, .val = 0x14E90000 },
         { .reg = 0x00009888, .val = 0x14EE0000 },
         { .reg = 0x00009888, .val = 0x161E8000 },
         { .reg = 0x00009888, .val = 0x181EC000 },
         { .reg = 0x00009888, .val = 0x1A1E0400 },
         { .reg = 0x00009888, .val = 0x061F8000 },
         { .reg = 0x00009888, .val = 0x081F8000 },
         { .reg = 0x00009888, .val = 0x0A1F8000 },
         { .reg = 0x00009888, .val = 0x0C1F0400 },
         { .reg = 0x00009888, .val = 0x06204000 },
         { .reg = 0x00009888, .val = 0x08204000 },
         { .reg = 0x00009888, .val = 0x0A204000 },
         { .reg = 0x00009888, .val = 0x0C204000 },
         { .reg = 0x00009888, .val = 0x06218000 },
         { .reg = 0x00009888, .val = 0x08218000 },
         { .reg = 0x00009888, .val = 0x0A218000 },
         { .reg = 0x00009888, .val = 0x0C218000 },
         { .reg = 0x00009888, .val = 0x0429C300 },
         { .reg = 0x00009888, .val = 0x062900C5 },
         { .reg = 0x00009888, .val = 0x22290000 },
         { .reg = 0x00009888, .val = 0x1E290000 },
         { .reg = 0x00009888, .val = 0x20290000 },
         { .reg = 0x00009888, .val = 0x062AC000 },
         { .reg = 0x00009888, .val = 0x082AC000 },
         { .reg = 0x00009888, .val = 0x0A2A4000 },
         { .reg = 0x00009888, .val = 0x0C2A4000 },
         { .reg = 0x00009888, .val = 0x0A2C8000 },
         { .reg = 0x00009888, .val = 0x0C2C8000 },
         { .reg = 0x00009888, .val = 0x0E2C8000 },
         { .reg = 0x00009888, .val = 0x182C0002 },
         { .reg = 0x00009888, .val = 0x022EC300 },
         { .reg = 0x00009888, .val = 0x042E00C5 },
         { .reg = 0x00009888, .val = 0x102E0000 },
         { .reg = 0x00009888, .val = 0x022F8000 },
         { .reg = 0x00009888, .val = 0x042F4000 },
         { .reg = 0x00009888, .val = 0x1A304000 },
         { .reg = 0x00009888, .val = 0x1C300001 },
         { .reg = 0x00009888, .val = 0x1C5E000C },
         { .reg = 0x00009888, .val = 0x125E8000 },
         { .reg = 0x00009888, .val = 0x145E8000 },
         { .reg = 0x00009888, .val = 0x0E5F000C },
         { .reg = 0x00009888, .val = 0x025F8000 },
         { .reg = 0x00009888, .val = 0x045F8000 },
         { .reg = 0x00009888, .val = 0x1C600014 },
         { .reg = 0x00009888, .val = 0x02604000 },
         { .reg = 0x00009888, .val = 0x04604000 },
         { .reg = 0x00009888, .val = 0x16612800 },
         { .reg = 0x00009888, .val = 0x02618000 },
         { .reg = 0x00009888, .val = 0x04618000 },
         { .reg = 0x00009888, .val = 0x0069C300 },
         { .reg = 0x00009888, .val = 0x026900C5 },
         { .reg = 0x00009888, .val = 0x22690000 },
         { .reg = 0x00009888, .val = 0x12690000 },
         { .reg = 0x00009888, .val = 0x1A6A00F0 },
         { .reg = 0x00009888, .val = 0x026A4000 },
         { .reg = 0x00009888, .val = 0x046A4000 },
         { .reg = 0x00009888, .val = 0x1A6C000A },
         { .reg = 0x00009888, .val = 0x066C8000 },
         { .reg = 0x00009888, .val = 0x086C8000 },
         { .reg = 0x00009888, .val = 0x0E6EC5C3 },
         { .reg = 0x00009888, .val = 0x106E0000 },
         { .reg = 0x00009888, .val = 0x0E6FC000 },
         { .reg = 0x00009888, .val = 0x1E700050 },
         { .reg = 0x00009888, .val = 0x1A9EC000 },
         { .reg = 0x00009888, .val = 0x1C9E0003 },
         { .reg = 0x00009888, .val = 0x0C9FC000 },
         { .reg = 0x00009888, .val = 0x0E9F0003 },
         { .reg = 0x00009888, .val = 0x1AA02A00 },
         { .reg = 0x00009888, .val = 0x1CA00001 },
         { .reg = 0x00009888, .val = 0x16A102A8 },
         { .reg = 0x00009888, .val = 0x0CA9C5C3 },
         { .reg = 0x00009888, .val = 0x22A90000 },
         { .reg = 0x00009888, .val = 0x18AAF000 },
         { .reg = 0x00009888, .val = 0x1AAA0005 },
         { .reg = 0x00009888, .val = 0x18ACAA00 },
         { .reg = 0x00009888, .val = 0x0AAEC5C3 },
         { .reg = 0x00009888, .val = 0x10AE0000 },
         { .reg = 0x00009888, .val = 0x0AAFC000 },
         { .reg = 0x00009888, .val = 0x1CB05000 },
         { .reg = 0x00009888, .val = 0x10DE8000 },
         { .reg = 0x00009888, .val = 0x1ADE3800 },
         { .reg = 0x00009888, .val = 0x00DF8000 },
         { .reg = 0x00009888, .val = 0x0CDF3800 },
         { .reg = 0x00009888, .val = 0x00E04000 },
         { .reg = 0x00009888, .val = 0x0EE04000 },
         { .reg = 0x00009888, .val = 0x1AE000A0 },
         { .reg = 0x00009888, .val = 0x00E18000 },
         { .reg = 0x00009888, .val = 0x0EE18000 },
         { .reg = 0x00009888, .val = 0x14E18000 },
         { .reg = 0x00009888, .val = 0x16E10002 },
         { .reg = 0x00009888, .val = 0x08E9C5C3 },
         { .reg = 0x00009888, .val = 0x22E90000 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x00EAC000 },
         { .reg = 0x00009888, .val = 0x0EEAC000 },
         { .reg = 0x00009888, .val = 0x18EA0500 },
         { .reg = 0x00009888, .val = 0x04EC8000 },
         { .reg = 0x00009888, .val = 0x18EC00A8 },
         { .reg = 0x00009888, .val = 0x00EE00C3 },
         { .reg = 0x00009888, .val = 0x06EEC500 },
         { .reg = 0x00009888, .val = 0x10EE0000 },
         { .reg = 0x00009888, .val = 0x00EF4000 },
         { .reg = 0x00009888, .val = 0x06EF8000 },
         { .reg = 0x00009888, .val = 0x18F04000 },
         { .reg = 0x00009888, .val = 0x1CF00040 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x0E045555 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x2406FF00 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x0E08A000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009888, .val = 0x14090050 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x06091000 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x040E1000 },
         { .reg = 0x00009888, .val = 0x0A0E4000 },
         { .reg = 0x00009888, .val = 0x0C0E5000 },
         { .reg = 0x00009888, .val = 0x1812FC00 },
         { .reg = 0x00009888, .val = 0x1A12002B },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x0813C000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x04136000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02144000 },
         { .reg = 0x00009888, .val = 0x00158000 },
         { .reg = 0x00009888, .val = 0x0E158000 },
         { .reg = 0x00009888, .val = 0x16152AD0 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x0615C000 },
         { .reg = 0x00009888, .val = 0x0815C000 },
         { .reg = 0x00009888, .val = 0x0A15C000 },
         { .reg = 0x00009888, .val = 0x0C15C000 },
         { .reg = 0x00009888, .val = 0x02188000 },
         { .reg = 0x00009888, .val = 0x0418A000 },
         { .reg = 0x00009888, .val = 0x06182000 },
         { .reg = 0x00009888, .val = 0x0A198000 },
         { .reg = 0x00009888, .val = 0x0C19A000 },
         { .reg = 0x00009888, .val = 0x0E192000 },
         { .reg = 0x00009888, .val = 0x0A1CA000 },
         { .reg = 0x00009888, .val = 0x0C1CA000 },
         { .reg = 0x00009888, .val = 0x121D5400 },
         { .reg = 0x00009888, .val = 0x141D0002 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4924 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x3E1F3000 },
         { .reg = 0x00009888, .val = 0x461F5030 },
         { .reg = 0x00009888, .val = 0x481F0050 },
         { .reg = 0x00009888, .val = 0x4A1F2000 },
         { .reg = 0x00009888, .val = 0x4C1F0020 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x401F2020 },
         { .reg = 0x00009888, .val = 0x421F3030 },
         { .reg = 0x00009888, .val = 0x441F5050 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00000018 },
         { .reg = 0x00002774, .val = 0x0000FFFC },
         { .reg = 0x00002778, .val = 0x00000060 },
         { .reg = 0x0000277C, .val = 0x0000FFF3 },
         { .reg = 0x00002780, .val = 0x00000180 },
         { .reg = 0x00002784, .val = 0x0000FFCF },
         { .reg = 0x00002788, .val = 0x00000600 },
         { .reg = 0x0000278C, .val = 0x0000FF3F },
         { .reg = 0x00002790, .val = 0x00001800 },
         { .reg = 0x00002794, .val = 0x0000FCFF },
         { .reg = 0x00002798, .val = 0x00006000 },
         { .reg = 0x0000279C, .val = 0x0000F3FF },
         { .reg = 0x000027A0, .val = 0x00018000 },
         { .reg = 0x000027A4, .val = 0x0000CFFF },
         { .reg = 0x000027A8, .val = 0x00060000 },
         { .reg = 0x000027AC, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__tdl_1__avg_gpu_core_frequency__max,icl__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,icl__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,icl__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,icl__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,icl__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 12, 104, percentage_max_float,icl__tdl_1__vs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 13, 112, NULL,icl__tdl_1__vs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 15, 120, percentage_max_float,icl__tdl_1__vs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 14, 128, NULL,icl__tdl_1__vs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 127, 136, percentage_max_float,icl__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 140, percentage_max_float,icl__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 144, percentage_max_float,icl__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 148, percentage_max_float,icl__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_float(query, 32, 152, percentage_max_float,icl__tdl_1__ps_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 33, 160, NULL,icl__tdl_1__ps_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 35, 168, percentage_max_float,icl__tdl_1__ps_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 34, 176, NULL,icl__tdl_1__ps_eu_stall_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 139, 184, NULL,icl__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 192, NULL,icl__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 200, NULL,icl__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 208, NULL,icl__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 216, NULL,icl__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 224, NULL,icl__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 232, NULL,icl__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 240, NULL,icl__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 248, NULL,icl__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 256, icl__tdl_1__slm_bytes_read__max,icl__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 264, icl__tdl_1__slm_bytes_written__max,icl__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 272, NULL,icl__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 280, NULL,icl__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 288, icl__tdl_1__l3_shader_throughput__max,icl__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,icl__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 382, 304, percentage_max_float,icl__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 383, 308, percentage_max_float,icl__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 384, 312, percentage_max_float,icl__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 385, 316, percentage_max_float,icl__tdl_1__ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 386, 320, percentage_max_float,icl__tdl_1__ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 387, 324, percentage_max_float,icl__tdl_1__ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 388, 328, percentage_max_float,icl__tdl_1__ps_thread06_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 389, 332, percentage_max_float,icl__tdl_1__ps_thread07_ready_for_dispatch__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "c6d3af7b-037b-4656-95e1-4f838f0a2c14";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14290000 },
         { .reg = 0x00009888, .val = 0x142E0000 },
         { .reg = 0x00009888, .val = 0x14690000 },
         { .reg = 0x00009888, .val = 0x146E0000 },
         { .reg = 0x00009888, .val = 0x14A90000 },
         { .reg = 0x00009888, .val = 0x14AE0000 },
         { .reg = 0x00009888, .val = 0x14E90000 },
         { .reg = 0x00009888, .val = 0x14EE0000 },
         { .reg = 0x00009888, .val = 0x1C1E0006 },
         { .reg = 0x00009888, .val = 0x0E1F0006 },
         { .reg = 0x00009888, .val = 0x1C200005 },
         { .reg = 0x00009888, .val = 0x16210A00 },
         { .reg = 0x00009888, .val = 0x0C29C100 },
         { .reg = 0x00009888, .val = 0x22290000 },
         { .reg = 0x00009888, .val = 0x1A2A0034 },
         { .reg = 0x00009888, .val = 0x182C8000 },
         { .reg = 0x00009888, .val = 0x1A2C0002 },
         { .reg = 0x00009888, .val = 0x0E2E00C1 },
         { .reg = 0x00009888, .val = 0x102E0000 },
         { .reg = 0x00009888, .val = 0x0E2F4000 },
         { .reg = 0x00009888, .val = 0x1E300010 },
         { .reg = 0x00009888, .val = 0x1C5E0008 },
         { .reg = 0x00009888, .val = 0x125E8000 },
         { .reg = 0x00009888, .val = 0x0E5F0008 },
         { .reg = 0x00009888, .val = 0x025F8000 },
         { .reg = 0x00009888, .val = 0x1C600010 },
         { .reg = 0x00009888, .val = 0x02604000 },
         { .reg = 0x00009888, .val = 0x16612000 },
         { .reg = 0x00009888, .val = 0x02618000 },
         { .reg = 0x00009888, .val = 0x0E69C100 },
         { .reg = 0x00009888, .val = 0x22690000 },
         { .reg = 0x00009888, .val = 0x1A6A0040 },
         { .reg = 0x00009888, .val = 0x026AC000 },
         { .reg = 0x00009888, .val = 0x1A6C0008 },
         { .reg = 0x00009888, .val = 0x066C8000 },
         { .reg = 0x00009888, .val = 0x006EC100 },
         { .reg = 0x00009888, .val = 0x106E0000 },
         { .reg = 0x00009888, .val = 0x006F8000 },
         { .reg = 0x00009888, .val = 0x1A700400 },
         { .reg = 0x00009888, .val = 0x149E8000 },
         { .reg = 0x00009888, .val = 0x169E8000 },
         { .reg = 0x00009888, .val = 0x049F8000 },
         { .reg = 0x00009888, .val = 0x069F8000 },
         { .reg = 0x00009888, .val = 0x04A04000 },
         { .reg = 0x00009888, .val = 0x06A04000 },
         { .reg = 0x00009888, .val = 0x04A18000 },
         { .reg = 0x00009888, .val = 0x06A18000 },
         { .reg = 0x00009888, .val = 0x02A900C1 },
         { .reg = 0x00009888, .val = 0x22A90000 },
         { .reg = 0x00009888, .val = 0x04AA4000 },
         { .reg = 0x00009888, .val = 0x06AAC000 },
         { .reg = 0x00009888, .val = 0x08AC8000 },
         { .reg = 0x00009888, .val = 0x0AAC8000 },
         { .reg = 0x00009888, .val = 0x02AEC100 },
         { .reg = 0x00009888, .val = 0x10AE0000 },
         { .reg = 0x00009888, .val = 0x02AF8000 },
         { .reg = 0x00009888, .val = 0x1AB04000 },
         { .reg = 0x00009888, .val = 0x18DEC000 },
         { .reg = 0x00009888, .val = 0x08DF8000 },
         { .reg = 0x00009888, .val = 0x0ADF8000 },
         { .reg = 0x00009888, .val = 0x08E04000 },
         { .reg = 0x00009888, .val = 0x0AE04000 },
         { .reg = 0x00009888, .val = 0x08E18000 },
         { .reg = 0x00009888, .val = 0x0AE18000 },
         { .reg = 0x00009888, .val = 0x04E900C1 },
         { .reg = 0x00009888, .val = 0x22E90000 },
         { .reg = 0x00009888, .val = 0x1CE90000 },
         { .reg = 0x00009888, .val = 0x08EA4000 },
         { .reg = 0x00009888, .val = 0x0AEAC000 },
         { .reg = 0x00009888, .val = 0x0CEC8000 },
         { .reg = 0x00009888, .val = 0x0EEC8000 },
         { .reg = 0x00009888, .val = 0x04EEC100 },
         { .reg = 0x00009888, .val = 0x10EE0000 },
         { .reg = 0x00009888, .val = 0x04EF8000 },
         { .reg = 0x00009888, .val = 0x1CF00004 },
         { .reg = 0x00009888, .val = 0x10040150 },
         { .reg = 0x00009888, .val = 0x0C045000 },
         { .reg = 0x00009888, .val = 0x0E040015 },
         { .reg = 0x00009888, .val = 0x14050054 },
         { .reg = 0x00009888, .val = 0x04054000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x260600E0 },
         { .reg = 0x00009888, .val = 0x24063E00 },
         { .reg = 0x00009888, .val = 0x0E088000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x14090040 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x080E5000 },
         { .reg = 0x00009888, .val = 0x1A120020 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x0412C000 },
         { .reg = 0x00009888, .val = 0x0612C000 },
         { .reg = 0x00009888, .val = 0x0A138000 },
         { .reg = 0x00009888, .val = 0x0413E000 },
         { .reg = 0x00009888, .val = 0x0E148000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x0214C000 },
         { .reg = 0x00009888, .val = 0x16156000 },
         { .reg = 0x00009888, .val = 0x18150007 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08158000 },
         { .reg = 0x00009888, .val = 0x0A158000 },
         { .reg = 0x00009888, .val = 0x0C188000 },
         { .reg = 0x00009888, .val = 0x0E182000 },
         { .reg = 0x00009888, .val = 0x1419000A },
         { .reg = 0x00009888, .val = 0x021CA000 },
         { .reg = 0x00009888, .val = 0x0A1DA000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3061 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x521F4000 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2420 },
         { .reg = 0x00009888, .val = 0x501F0024 },
         { .reg = 0x00009888, .val = 0x4C1F3050 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009888, .val = 0x401F2000 },
         { .reg = 0x00009888, .val = 0x421F5000 },
         { .reg = 0x00009888, .val = 0x441F3730 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__tdl_2__avg_gpu_core_frequency__max,icl__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,icl__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,icl__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,icl__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,icl__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,icl__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,icl__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,icl__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,icl__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,icl__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,icl__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,icl__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,icl__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,icl__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,icl__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,icl__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,icl__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,icl__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, icl__tdl_2__slm_bytes_read__max,icl__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, icl__tdl_2__slm_bytes_written__max,icl__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,icl__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,icl__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, icl__tdl_2__l3_shader_throughput__max,icl__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,icl__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 390, 240, percentage_max_float,icl__tdl_2__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 391, 244, percentage_max_float,icl__tdl_2__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 392, 248, percentage_max_float,icl__tdl_2__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 393, 252, percentage_max_float,icl__tdl_2__non_ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 394, 256, percentage_max_float,icl__tdl_2__non_ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 395, 260, percentage_max_float,icl__tdl_2__non_ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 396, 264, percentage_max_float,icl__tdl_2__non_ps_thread06_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 397, 268, percentage_max_float,icl__tdl_2__non_ps_thread07_ready_for_dispatch__read);
      }

      intel_perf_query_add_counter_float(query, 244, 272, percentage_max_float,icl__tdl_2__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_tdl_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 51);

   query->name = "Metric set TDL_3";
   query->symbol_name = "TDL_3";
   query->guid = "fd25ec19-3ed1-40c9-8648-1d2387449a92";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14292C00 },
         { .reg = 0x00009888, .val = 0x16290013 },
         { .reg = 0x00009888, .val = 0x142E2C00 },
         { .reg = 0x00009888, .val = 0x162E0013 },
         { .reg = 0x00009888, .val = 0x14692C00 },
         { .reg = 0x00009888, .val = 0x16690013 },
         { .reg = 0x00009888, .val = 0x146E2C00 },
         { .reg = 0x00009888, .val = 0x166E0013 },
         { .reg = 0x00009888, .val = 0x14A92C00 },
         { .reg = 0x00009888, .val = 0x16A90013 },
         { .reg = 0x00009888, .val = 0x14AE2C00 },
         { .reg = 0x00009888, .val = 0x16AE0013 },
         { .reg = 0x00009888, .val = 0x14E92C00 },
         { .reg = 0x00009888, .val = 0x16E90013 },
         { .reg = 0x00009888, .val = 0x14EE2C00 },
         { .reg = 0x00009888, .val = 0x16EE0013 },
         { .reg = 0x00009888, .val = 0x101E8000 },
         { .reg = 0x00009888, .val = 0x1A1E3800 },
         { .reg = 0x00009888, .val = 0x001F8000 },
         { .reg = 0x00009888, .val = 0x0C1F3800 },
         { .reg = 0x00009888, .val = 0x00204000 },
         { .reg = 0x00009888, .val = 0x0E204000 },
         { .reg = 0x00009888, .val = 0x1A2000A0 },
         { .reg = 0x00009888, .val = 0x00218000 },
         { .reg = 0x00009888, .val = 0x0E218000 },
         { .reg = 0x00009888, .val = 0x14218000 },
         { .reg = 0x00009888, .val = 0x16210002 },
         { .reg = 0x00009888, .val = 0x002900C7 },
         { .reg = 0x00009888, .val = 0x0629CF00 },
         { .reg = 0x00009888, .val = 0x22290000 },
         { .reg = 0x00009888, .val = 0x10290000 },
         { .reg = 0x00009888, .val = 0x20290000 },
         { .reg = 0x00009888, .val = 0x002A4000 },
         { .reg = 0x00009888, .val = 0x0E2A4000 },
         { .reg = 0x00009888, .val = 0x182A0F00 },
         { .reg = 0x00009888, .val = 0x042C8000 },
         { .reg = 0x00009888, .val = 0x182C00A8 },
         { .reg = 0x00009888, .val = 0x082ECFC7 },
         { .reg = 0x00009888, .val = 0x102E0000 },
         { .reg = 0x00009888, .val = 0x082FC000 },
         { .reg = 0x00009888, .val = 0x1C300500 },
         { .reg = 0x00009888, .val = 0x1A5EC000 },
         { .reg = 0x00009888, .val = 0x1C5E0003 },
         { .reg = 0x00009888, .val = 0x0C5FC000 },
         { .reg = 0x00009888, .val = 0x0E5F0003 },
         { .reg = 0x00009888, .val = 0x1A602A00 },
         { .reg = 0x00009888, .val = 0x1C600001 },
         { .reg = 0x00009888, .val = 0x166102A8 },
         { .reg = 0x00009888, .val = 0x0A69CFC7 },
         { .reg = 0x00009888, .val = 0x22690000 },
         { .reg = 0x00009888, .val = 0x186A5000 },
         { .reg = 0x00009888, .val = 0x1A6A000F },
         { .reg = 0x00009888, .val = 0x186CAA00 },
         { .reg = 0x00009888, .val = 0x0C6ECFC7 },
         { .reg = 0x00009888, .val = 0x106E0000 },
         { .reg = 0x00009888, .val = 0x0C6FC000 },
         { .reg = 0x00009888, .val = 0x1E700005 },
         { .reg = 0x00009888, .val = 0x1C9E000C },
         { .reg = 0x00009888, .val = 0x129E8000 },
         { .reg = 0x00009888, .val = 0x149E8000 },
         { .reg = 0x00009888, .val = 0x0E9F000C },
         { .reg = 0x00009888, .val = 0x029F8000 },
         { .reg = 0x00009888, .val = 0x049F8000 },
         { .reg = 0x00009888, .val = 0x1CA00014 },
         { .reg = 0x00009888, .val = 0x02A04000 },
         { .reg = 0x00009888, .val = 0x04A04000 },
         { .reg = 0x00009888, .val = 0x16A12800 },
         { .reg = 0x00009888, .val = 0x02A18000 },
         { .reg = 0x00009888, .val = 0x04A18000 },
         { .reg = 0x00009888, .val = 0x0EA9CFC7 },
         { .reg = 0x00009888, .val = 0x22A90000 },
         { .reg = 0x00009888, .val = 0x1AAA0050 },
         { .reg = 0x00009888, .val = 0x02AAC000 },
         { .reg = 0x00009888, .val = 0x04AAC000 },
         { .reg = 0x00009888, .val = 0x1AAC000A },
         { .reg = 0x00009888, .val = 0x06AC8000 },
         { .reg = 0x00009888, .val = 0x08AC8000 },
         { .reg = 0x00009888, .val = 0x00AEC700 },
         { .reg = 0x00009888, .val = 0x02AE00CF },
         { .reg = 0x00009888, .val = 0x10AE0000 },
         { .reg = 0x00009888, .val = 0x00AF8000 },
         { .reg = 0x00009888, .val = 0x02AF4000 },
         { .reg = 0x00009888, .val = 0x1AB01400 },
         { .reg = 0x00009888, .val = 0x16DE8000 },
         { .reg = 0x00009888, .val = 0x18DEC000 },
         { .reg = 0x00009888, .val = 0x1ADE0400 },
         { .reg = 0x00009888, .val = 0x06DF8000 },
         { .reg = 0x00009888, .val = 0x08DF8000 },
         { .reg = 0x00009888, .val = 0x0ADF8000 },
         { .reg = 0x00009888, .val = 0x0CDF0400 },
         { .reg = 0x00009888, .val = 0x06E04000 },
         { .reg = 0x00009888, .val = 0x08E04000 },
         { .reg = 0x00009888, .val = 0x0AE04000 },
         { .reg = 0x00009888, .val = 0x0CE04000 },
         { .reg = 0x00009888, .val = 0x06E18000 },
         { .reg = 0x00009888, .val = 0x08E18000 },
         { .reg = 0x00009888, .val = 0x0AE18000 },
         { .reg = 0x00009888, .val = 0x0CE18000 },
         { .reg = 0x00009888, .val = 0x02E9C700 },
         { .reg = 0x00009888, .val = 0x04E900CF },
         { .reg = 0x00009888, .val = 0x22E90000 },
         { .reg = 0x00009888, .val = 0x1CE90000 },
         { .reg = 0x00009888, .val = 0x06EA4000 },
         { .reg = 0x00009888, .val = 0x08EA4000 },
         { .reg = 0x00009888, .val = 0x0AEAC000 },
         { .reg = 0x00009888, .val = 0x0CEAC000 },
         { .reg = 0x00009888, .val = 0x0AEC8000 },
         { .reg = 0x00009888, .val = 0x0CEC8000 },
         { .reg = 0x00009888, .val = 0x0EEC8000 },
         { .reg = 0x00009888, .val = 0x18EC0002 },
         { .reg = 0x00009888, .val = 0x04EEC700 },
         { .reg = 0x00009888, .val = 0x06EE00CF },
         { .reg = 0x00009888, .val = 0x10EE0000 },
         { .reg = 0x00009888, .val = 0x04EF8000 },
         { .reg = 0x00009888, .val = 0x06EF4000 },
         { .reg = 0x00009888, .val = 0x1CF00014 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x0E045555 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x2406FF00 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x0A08A000 },
         { .reg = 0x00009888, .val = 0x0C08A000 },
         { .reg = 0x00009888, .val = 0x0E095000 },
         { .reg = 0x00009888, .val = 0x14090005 },
         { .reg = 0x00009888, .val = 0x020D8000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x060E4000 },
         { .reg = 0x00009888, .val = 0x080E5000 },
         { .reg = 0x00009888, .val = 0x0A0E1000 },
         { .reg = 0x00009888, .val = 0x1812A800 },
         { .reg = 0x00009888, .val = 0x1A12003E },
         { .reg = 0x00009888, .val = 0x0212C000 },
         { .reg = 0x00009888, .val = 0x0412C000 },
         { .reg = 0x00009888, .val = 0x0813C000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x04136000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02144000 },
         { .reg = 0x00009888, .val = 0x0015C000 },
         { .reg = 0x00009888, .val = 0x0E15C000 },
         { .reg = 0x00009888, .val = 0x16152AF8 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x06158000 },
         { .reg = 0x00009888, .val = 0x08158000 },
         { .reg = 0x00009888, .val = 0x0A158000 },
         { .reg = 0x00009888, .val = 0x0C158000 },
         { .reg = 0x00009888, .val = 0x00182000 },
         { .reg = 0x00009888, .val = 0x06188000 },
         { .reg = 0x00009888, .val = 0x0818A000 },
         { .reg = 0x00009888, .val = 0x08192000 },
         { .reg = 0x00009888, .val = 0x0E198000 },
         { .reg = 0x00009888, .val = 0x12190140 },
         { .reg = 0x00009888, .val = 0x0E1CA000 },
         { .reg = 0x00009888, .val = 0x001C8000 },
         { .reg = 0x00009888, .val = 0x021C2000 },
         { .reg = 0x00009888, .val = 0x141D0028 },
         { .reg = 0x00009888, .val = 0x081D8000 },
         { .reg = 0x00009888, .val = 0x0A1D2000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4924 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2420 },
         { .reg = 0x00009888, .val = 0x3E1F5000 },
         { .reg = 0x00009888, .val = 0x461F3050 },
         { .reg = 0x00009888, .val = 0x481F2030 },
         { .reg = 0x00009888, .val = 0x4A1F0020 },
         { .reg = 0x00009888, .val = 0x4C1F2000 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x401F0000 },
         { .reg = 0x00009888, .val = 0x421F5050 },
         { .reg = 0x00009888, .val = 0x441F3030 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__tdl_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__tdl_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__tdl_3__avg_gpu_core_frequency__max,icl__tdl_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__tdl_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__tdl_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__tdl_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__tdl_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__tdl_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__tdl_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__tdl_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,icl__tdl_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,icl__tdl_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,icl__tdl_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,icl__tdl_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,icl__tdl_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,icl__tdl_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,icl__tdl_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,icl__tdl_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,icl__tdl_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,icl__tdl_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,icl__tdl_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,icl__tdl_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,icl__tdl_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,icl__tdl_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,icl__tdl_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,icl__tdl_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,icl__tdl_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,icl__tdl_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,icl__tdl_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, icl__tdl_3__slm_bytes_read__max,icl__tdl_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, icl__tdl_3__slm_bytes_written__max,icl__tdl_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,icl__tdl_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,icl__tdl_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, icl__tdl_3__l3_shader_throughput__max,icl__tdl_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,icl__tdl_3__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 398, 240, percentage_max_float,icl__tdl_3__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 399, 244, percentage_max_float,icl__tdl_3__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 400, 248, percentage_max_float,icl__tdl_3__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 401, 252, percentage_max_float,icl__tdl_3__thread_header01_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 402, 256, percentage_max_float,icl__tdl_3__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 403, 260, percentage_max_float,icl__tdl_3__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 404, 264, percentage_max_float,icl__tdl_3__thread_header03_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 405, 268, percentage_max_float,icl__tdl_3__thread_header03_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 406, 272, percentage_max_float,icl__tdl_3__thread_header04_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 407, 276, percentage_max_float,icl__tdl_3__thread_header04_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 408, 280, percentage_max_float,icl__tdl_3__thread_header05_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 409, 284, percentage_max_float,icl__tdl_3__thread_header05_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 410, 288, percentage_max_float,icl__tdl_3__thread_header06_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 411, 292, percentage_max_float,icl__tdl_3__thread_header06_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 412, 296, percentage_max_float,icl__tdl_3__thread_header07_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 413, 300, percentage_max_float,icl__tdl_3__thread_header07_ready_port1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Gpu Rings Busyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "40dc79f2-88c8-47c6-8f86-f509e39fbe5d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x0E061200 },
         { .reg = 0x00009888, .val = 0x22062400 },
         { .reg = 0x00009888, .val = 0x10002400 },
         { .reg = 0x00009888, .val = 0x00038000 },
         { .reg = 0x00009888, .val = 0x06032000 },
         { .reg = 0x00009888, .val = 0x020600F3 },
         { .reg = 0x00009888, .val = 0x0C060043 },
         { .reg = 0x00009888, .val = 0x20060000 },
         { .reg = 0x00009888, .val = 0x02000023 },
         { .reg = 0x00009888, .val = 0x20002000 },
         { .reg = 0x00009888, .val = 0x081A8000 },
         { .reg = 0x00009888, .val = 0x3A1F6000 },
         { .reg = 0x00009888, .val = 0x4E1F2900 },
         { .reg = 0x00009888, .val = 0x501F00E9 },
         { .reg = 0x00009888, .val = 0x10204000 },
         { .reg = 0x00009888, .val = 0x0C214000 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x401F4131 },
         { .reg = 0x00009888, .val = 0x421F1021 },
         { .reg = 0x00009888, .val = 0x441F3100 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009884, .val = 0x00000002 },
         { .reg = 0x00009888, .val = 0x181B2400 },
         { .reg = 0x00009888, .val = 0x185B2400 },
         { .reg = 0x00009888, .val = 0x12240120 },
         { .reg = 0x00009888, .val = 0x06218000 },
         { .reg = 0x00009888, .val = 0x08212000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x180B8000 },
         { .reg = 0x00009888, .val = 0x0A0C8000 },
         { .reg = 0x00009888, .val = 0x040F8000 },
         { .reg = 0x00009888, .val = 0x0E080010 },
         { .reg = 0x00009888, .val = 0x041B8300 },
         { .reg = 0x00009888, .val = 0x101B0000 },
         { .reg = 0x00009888, .val = 0x221B0000 },
         { .reg = 0x00009888, .val = 0x041E4000 },
         { .reg = 0x00009888, .val = 0x084A8000 },
         { .reg = 0x00009888, .val = 0x184B4000 },
         { .reg = 0x00009888, .val = 0x084C8000 },
         { .reg = 0x00009888, .val = 0x044F2000 },
         { .reg = 0x00009888, .val = 0x0E480004 },
         { .reg = 0x00009888, .val = 0x045B0083 },
         { .reg = 0x00009888, .val = 0x105B0000 },
         { .reg = 0x00009888, .val = 0x225B0000 },
         { .reg = 0x00009888, .val = 0x045E1000 },
         { .reg = 0x00009888, .val = 0x0823A000 },
         { .reg = 0x00009888, .val = 0x02242980 },
         { .reg = 0x00009888, .val = 0x10240000 },
         { .reg = 0x00009888, .val = 0x06240000 },
         { .reg = 0x00009888, .val = 0x0A244000 },
         { .reg = 0x00009888, .val = 0x1C250004 },
         { .reg = 0x00009888, .val = 0x08268000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0007C000 },
         { .reg = 0x00002774, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__gpu_busyness__avg_gpu_core_frequency__max,icl__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 309, 28, percentage_max_float,icl__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 32, percentage_max_float,icl__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 36, percentage_max_float,icl__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 312, 40, percentage_max_float,icl__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 44, percentage_max_float,icl__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 414, 48, percentage_max_float,icl__gpu_busyness__posh_engine_busy__read);

      intel_perf_query_add_counter_float(query, 314, 52, percentage_max_float,icl__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "e617cfd5-6cc5-4143-8994-cd36cebb921f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x16130000 },
         { .reg = 0x00009888, .val = 0x24000001 },
         { .reg = 0x00009888, .val = 0x0E130056 },
         { .reg = 0x00009888, .val = 0x10130000 },
         { .reg = 0x00009888, .val = 0x1A130000 },
         { .reg = 0x00009888, .val = 0x541F0001 },
         { .reg = 0x00009888, .val = 0x181F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x301F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x0000FFFF },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x0000FFFF },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x0000FFFF },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__test_oa__avg_gpu_core_frequency__max,icl__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,icl__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,icl__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,icl__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,icl__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 415, 56, NULL,icl__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 416, 64, NULL,icl__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 417, 72, NULL,icl__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 418, 80, NULL,icl__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,icl__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
icl_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "eca4858e-27a4-4bcf-a57f-2616e2f08950";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00051050 },
         { .reg = 0x0000E758, .val = 0x00011010 },
         { .reg = 0x0000E45C, .val = 0x00061060 },
         { .reg = 0x0000E55C, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,icl__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,icl__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, icl__async_compute__avg_gpu_core_frequency__max,icl__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,icl__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,icl__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,icl__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,icl__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,icl__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,icl__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,icl__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 150, 80, percentage_max_float,icl__async_compute__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 124, 84, percentage_max_float,icl__async_compute__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 127, 88, percentage_max_float,icl__async_compute__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 331, 92, percentage_max_float,icl__async_compute__cs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 96, percentage_max_float,icl__async_compute__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 125, 100, percentage_max_float,icl__async_compute__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,icl__async_compute__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 332, 108, percentage_max_float,icl__async_compute__cs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 154, 112, percentage_max_float,icl__async_compute__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 10, 116, percentage_max_float,icl__async_compute__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 120, percentage_max_float,icl__async_compute__eu_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_icl(struct intel_perf_config *perf)
{
   icl_register_render_basic_counter_query(perf);
   icl_register_compute_basic_counter_query(perf);
   icl_register_compute_extended_counter_query(perf);
   icl_register_compute_l3_cache_counter_query(perf);
   icl_register_render_pipe_profile_counter_query(perf);
   icl_register_hdc_and_sf_counter_query(perf);
   icl_register_rasterizer_and_pixel_backend_counter_query(perf);
   icl_register_l3_1_counter_query(perf);
   icl_register_l3_2_counter_query(perf);
   icl_register_l3_3_counter_query(perf);
   icl_register_l3_4_counter_query(perf);
   icl_register_l3_5_counter_query(perf);
   icl_register_sampler_1_counter_query(perf);
   icl_register_sampler_2_counter_query(perf);
   icl_register_tdl_1_counter_query(perf);
   icl_register_tdl_2_counter_query(perf);
   icl_register_tdl_3_counter_query(perf);
   icl_register_gpu_busyness_counter_query(perf);
   icl_register_test_oa_counter_query(perf);
   icl_register_async_compute_counter_query(perf);
}


static void
ehl_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "c693e665-867f-4362-91b6-85337f932010";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x142C0014 },
         { .reg = 0x00009888, .val = 0x14120700 },
         { .reg = 0x00009888, .val = 0x121500E0 },
         { .reg = 0x00009888, .val = 0x1E1E0030 },
         { .reg = 0x00009888, .val = 0x1A204000 },
         { .reg = 0x00009888, .val = 0x1C200001 },
         { .reg = 0x00009888, .val = 0x1E213000 },
         { .reg = 0x00009888, .val = 0x0E2C1831 },
         { .reg = 0x00009888, .val = 0x102C0000 },
         { .reg = 0x00009888, .val = 0x182C0000 },
         { .reg = 0x00009888, .val = 0x10040140 },
         { .reg = 0x00009888, .val = 0x0E040005 },
         { .reg = 0x00009888, .val = 0x14050050 },
         { .reg = 0x00009888, .val = 0x06054000 },
         { .reg = 0x00009888, .val = 0x08051000 },
         { .reg = 0x00009888, .val = 0x260600C0 },
         { .reg = 0x00009888, .val = 0x24061800 },
         { .reg = 0x00009888, .val = 0x04120023 },
         { .reg = 0x00009888, .val = 0x10120000 },
         { .reg = 0x00009888, .val = 0x08120000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x04144000 },
         { .reg = 0x00009888, .val = 0x02150980 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x1815000F },
         { .reg = 0x00009888, .val = 0x06150000 },
         { .reg = 0x00009888, .val = 0x08154000 },
         { .reg = 0x00009888, .val = 0x0E18A000 },
         { .reg = 0x00009888, .val = 0x14190028 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1A1C01C0 },
         { .reg = 0x00009888, .val = 0x1C1C000A },
         { .reg = 0x00009888, .val = 0x1A5C01C0 },
         { .reg = 0x00009888, .val = 0x1C5C000A },
         { .reg = 0x00009888, .val = 0x001C0097 },
         { .reg = 0x00009888, .val = 0x0A1CA700 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x081D0100 },
         { .reg = 0x00009888, .val = 0x0A1D0008 },
         { .reg = 0x00009888, .val = 0x085C0097 },
         { .reg = 0x00009888, .val = 0x0A5C00A7 },
         { .reg = 0x00009888, .val = 0x105C0000 },
         { .reg = 0x00009888, .val = 0x0A5D0005 },
         { .reg = 0x00009888, .val = 0x181E8000 },
         { .reg = 0x00009888, .val = 0x1E1EB300 },
         { .reg = 0x00009888, .val = 0x301F4000 },
         { .reg = 0x00009888, .val = 0x501F2004 },
         { .reg = 0x00009888, .val = 0x521F0090 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x4E1F2000 },
         { .reg = 0x00009888, .val = 0x3E1F6100 },
         { .reg = 0x00009888, .val = 0x461F6100 },
         { .reg = 0x00009888, .val = 0x481F6100 },
         { .reg = 0x00009888, .val = 0x4A1F0061 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x421F3060 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00051050 },
         { .reg = 0x0000E45C, .val = 0x00000052 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__render_basic__avg_gpu_core_frequency__max,ehl__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,ehl__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,ehl__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,ehl__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,ehl__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,ehl__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,ehl__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,ehl__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,ehl__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,ehl__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 84, percentage_max_float,ehl__render_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 88, percentage_max_float,ehl__render_basic__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 92, percentage_max_float,ehl__render_basic__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 96, percentage_max_float,ehl__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 100, percentage_max_float,ehl__render_basic__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 104, percentage_max_float,ehl__render_basic__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 108, percentage_max_float,ehl__render_basic__ps_send_active__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 333, 112, percentage_max_float,ehl__render_basic__sampler00_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 9) {
         intel_perf_query_add_counter_float(query, 133, 116, percentage_max_float,ehl__render_basic__samplers_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 334, 120, percentage_max_float,ehl__render_basic__sampler00_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 128, NULL,ehl__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 136, NULL,ehl__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 144, NULL,ehl__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 152, NULL,ehl__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 160, NULL,ehl__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 168, NULL,ehl__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 176, NULL,ehl__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 184, NULL,ehl__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 192, NULL,ehl__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 138, 200, NULL,ehl__render_basic__sampler_l1_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 208, ehl__render_basic__slm_bytes_read__max,ehl__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 216, ehl__render_basic__slm_bytes_written__max,ehl__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 224, NULL,ehl__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 232, NULL,ehl__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 240, ehl__render_basic__l3_shader_throughput__max,ehl__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 248, NULL,ehl__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 256, ehl__render_basic__gti_read_throughput__max,ehl__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 264, ehl__render_basic__gti_write_throughput__max,ehl__render_basic__gti_write_throughput__read);

      if (perf->sys_vars.subslice_mask & 9) {
         intel_perf_query_add_counter_float(query, 149, 272, percentage_max_float,ehl__render_basic__sampler_bottleneck__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "ae4d01a9-fe55-453c-8c7a-036acd5eacff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x12230012 },
         { .reg = 0x00009888, .val = 0x10230019 },
         { .reg = 0x00009888, .val = 0x12A30012 },
         { .reg = 0x00009888, .val = 0x10A30019 },
         { .reg = 0x00009888, .val = 0x1A200080 },
         { .reg = 0x00009888, .val = 0x1C200002 },
         { .reg = 0x00009888, .val = 0x04208000 },
         { .reg = 0x00009888, .val = 0x08208000 },
         { .reg = 0x00009888, .val = 0x0C208000 },
         { .reg = 0x00009888, .val = 0x0A230031 },
         { .reg = 0x00009888, .val = 0x0E231E00 },
         { .reg = 0x00009888, .val = 0x0223003D },
         { .reg = 0x00009888, .val = 0x04230032 },
         { .reg = 0x00009888, .val = 0x06230033 },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x1AA08200 },
         { .reg = 0x00009888, .val = 0x02A08000 },
         { .reg = 0x00009888, .val = 0x06A08000 },
         { .reg = 0x00009888, .val = 0x0AA08000 },
         { .reg = 0x00009888, .val = 0x0AA31880 },
         { .reg = 0x00009888, .val = 0x0EA3003C },
         { .reg = 0x00009888, .val = 0x00A31E80 },
         { .reg = 0x00009888, .val = 0x02A31900 },
         { .reg = 0x00009888, .val = 0x04A31980 },
         { .reg = 0x00009888, .val = 0x0E044055 },
         { .reg = 0x00009888, .val = 0x10040141 },
         { .reg = 0x00009888, .val = 0x0C045000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050050 },
         { .reg = 0x00009888, .val = 0x04054000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x0A051000 },
         { .reg = 0x00009888, .val = 0x260600CC },
         { .reg = 0x00009888, .val = 0x24067E00 },
         { .reg = 0x00009888, .val = 0x18123000 },
         { .reg = 0x00009888, .val = 0x1A12000C },
         { .reg = 0x00009888, .val = 0x0212C000 },
         { .reg = 0x00009888, .val = 0x0612C000 },
         { .reg = 0x00009888, .val = 0x0A12C000 },
         { .reg = 0x00009888, .val = 0x08138000 },
         { .reg = 0x00009888, .val = 0x0A134000 },
         { .reg = 0x00009888, .val = 0x0413A000 },
         { .reg = 0x00009888, .val = 0x06132000 },
         { .reg = 0x00009888, .val = 0x0A148000 },
         { .reg = 0x00009888, .val = 0x0E144000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02148000 },
         { .reg = 0x00009888, .val = 0x04148000 },
         { .reg = 0x00009888, .val = 0x16150380 },
         { .reg = 0x00009888, .val = 0x1815000D },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x0415C000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x0815C000 },
         { .reg = 0x00009888, .val = 0x0A154000 },
         { .reg = 0x00009888, .val = 0x0C15C000 },
         { .reg = 0x00009888, .val = 0x0A182000 },
         { .reg = 0x00009888, .val = 0x0E188000 },
         { .reg = 0x00009888, .val = 0x02182000 },
         { .reg = 0x00009888, .val = 0x04182000 },
         { .reg = 0x00009888, .val = 0x06182000 },
         { .reg = 0x00009888, .val = 0x12190400 },
         { .reg = 0x00009888, .val = 0x14190020 },
         { .reg = 0x00009888, .val = 0x0A192000 },
         { .reg = 0x00009888, .val = 0x0C192000 },
         { .reg = 0x00009888, .val = 0x0E192000 },
         { .reg = 0x00009888, .val = 0x0A1C8000 },
         { .reg = 0x00009888, .val = 0x0E1C2000 },
         { .reg = 0x00009888, .val = 0x001C8000 },
         { .reg = 0x00009888, .val = 0x021C8000 },
         { .reg = 0x00009888, .val = 0x041C8000 },
         { .reg = 0x00009888, .val = 0x121D1000 },
         { .reg = 0x00009888, .val = 0x141D0008 },
         { .reg = 0x00009888, .val = 0x081D8000 },
         { .reg = 0x00009888, .val = 0x0A1D8000 },
         { .reg = 0x00009888, .val = 0x0C1D8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1A1C01C0 },
         { .reg = 0x00009888, .val = 0x1C1C000A },
         { .reg = 0x00009888, .val = 0x1A5C01C0 },
         { .reg = 0x00009888, .val = 0x1C5C000A },
         { .reg = 0x00009888, .val = 0x001C0097 },
         { .reg = 0x00009888, .val = 0x0C1CA700 },
         { .reg = 0x00009888, .val = 0x101C0000 },
         { .reg = 0x00009888, .val = 0x081D0100 },
         { .reg = 0x00009888, .val = 0x0A1D0020 },
         { .reg = 0x00009888, .val = 0x085C0097 },
         { .reg = 0x00009888, .val = 0x0C5C00A7 },
         { .reg = 0x00009888, .val = 0x105C0000 },
         { .reg = 0x00009888, .val = 0x0A5D0011 },
         { .reg = 0x00009888, .val = 0x181E8000 },
         { .reg = 0x00009888, .val = 0x1E1E0300 },
         { .reg = 0x00009888, .val = 0x201E000B },
         { .reg = 0x00009888, .val = 0x301F4000 },
         { .reg = 0x00009888, .val = 0x501F2124 },
         { .reg = 0x00009888, .val = 0x521F2520 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2430 },
         { .reg = 0x00009888, .val = 0x3E1F0300 },
         { .reg = 0x00009888, .val = 0x461F0300 },
         { .reg = 0x00009888, .val = 0x481F3000 },
         { .reg = 0x00009888, .val = 0x4A1F0300 },
         { .reg = 0x00009888, .val = 0x4C1F0003 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x401F3000 },
         { .reg = 0x00009888, .val = 0x421F3000 },
         { .reg = 0x00009888, .val = 0x441F3000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00000008 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__compute_basic__avg_gpu_core_frequency__max,ehl__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 152, 88, ehl__compute_basic__eu_avg_ipc_rate__max,ehl__compute_basic__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 123, 92, percentage_max_float,ehl__compute_basic__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 96, percentage_max_float,ehl__compute_basic__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 100, percentage_max_float,ehl__compute_basic__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,ehl__compute_basic__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 154, 108, percentage_max_float,ehl__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 112, NULL,ehl__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 120, NULL,ehl__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 128, NULL,ehl__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 136, NULL,ehl__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 144, NULL,ehl__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 152, NULL,ehl__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 160, NULL,ehl__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 168, NULL,ehl__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 176, NULL,ehl__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 184, ehl__compute_basic__slm_bytes_read__max,ehl__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 192, ehl__compute_basic__slm_bytes_written__max,ehl__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 200, NULL,ehl__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 208, NULL,ehl__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 216, ehl__compute_basic__l3_shader_throughput__max,ehl__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,ehl__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 70, 232, ehl__compute_basic__typed_bytes_read__max,ehl__compute_basic__typed_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 71, 240, ehl__compute_basic__typed_bytes_written__max,ehl__compute_basic__typed_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 73, 248, ehl__compute_basic__untyped_bytes_read__max,ehl__compute_basic__untyped_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 74, 256, ehl__compute_basic__untyped_bytes_written__max,ehl__compute_basic__untyped_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 335, 264, ehl__compute_basic__typed_atomics__max,ehl__compute_basic__typed_atomics__read);

      intel_perf_query_add_counter_uint64(query, 57, 272, ehl__compute_basic__gti_read_throughput__max,ehl__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 280, ehl__compute_basic__gti_write_throughput__max,ehl__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_compute_extended_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 22);

   query->name = "ComputeExtended metrics set";
   query->symbol_name = "ComputeExtended";
   query->guid = "05700b63-f044-4c79-b8ae-676972114745";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14210160 },
         { .reg = 0x00009888, .val = 0x18210120 },
         { .reg = 0x00009888, .val = 0x12230019 },
         { .reg = 0x00009888, .val = 0x10230012 },
         { .reg = 0x00009888, .val = 0x101E8000 },
         { .reg = 0x00009888, .val = 0x1C1EE000 },
         { .reg = 0x00009888, .val = 0x1E1E001F },
         { .reg = 0x00009888, .val = 0x00204000 },
         { .reg = 0x00009888, .val = 0x0E204000 },
         { .reg = 0x00009888, .val = 0x18204000 },
         { .reg = 0x00009888, .val = 0x1A205550 },
         { .reg = 0x00009888, .val = 0x04208000 },
         { .reg = 0x00009888, .val = 0x06208000 },
         { .reg = 0x00009888, .val = 0x08208000 },
         { .reg = 0x00009888, .val = 0x0A208000 },
         { .reg = 0x00009888, .val = 0x0C208000 },
         { .reg = 0x00009888, .val = 0x00210041 },
         { .reg = 0x00009888, .val = 0x06214200 },
         { .reg = 0x00009888, .val = 0x08214443 },
         { .reg = 0x00009888, .val = 0x0A214645 },
         { .reg = 0x00009888, .val = 0x0C217647 },
         { .reg = 0x00009888, .val = 0x0E210073 },
         { .reg = 0x00009888, .val = 0x1E210000 },
         { .reg = 0x00009888, .val = 0x10210000 },
         { .reg = 0x00009888, .val = 0x02231AB4 },
         { .reg = 0x00009888, .val = 0x04231DBA },
         { .reg = 0x00009888, .val = 0x06230039 },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x0C044400 },
         { .reg = 0x00009888, .val = 0x0E045555 },
         { .reg = 0x00009888, .val = 0x10040055 },
         { .reg = 0x00009888, .val = 0x04051000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050015 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x2406FD00 },
         { .reg = 0x00009888, .val = 0x2606007F },
         { .reg = 0x00009888, .val = 0x0015C000 },
         { .reg = 0x00009888, .val = 0x0E15C000 },
         { .reg = 0x00009888, .val = 0x16157FF8 },
         { .reg = 0x00009888, .val = 0x18150003 },
         { .reg = 0x00009888, .val = 0x0415C000 },
         { .reg = 0x00009888, .val = 0x0615C000 },
         { .reg = 0x00009888, .val = 0x0815C000 },
         { .reg = 0x00009888, .val = 0x0A15C000 },
         { .reg = 0x00009888, .val = 0x0C15C000 },
         { .reg = 0x00009888, .val = 0x00182000 },
         { .reg = 0x00009888, .val = 0x0618A000 },
         { .reg = 0x00009888, .val = 0x0818A000 },
         { .reg = 0x00009888, .val = 0x0A18A000 },
         { .reg = 0x00009888, .val = 0x0C18A000 },
         { .reg = 0x00009888, .val = 0x0E182000 },
         { .reg = 0x00009888, .val = 0x0218A000 },
         { .reg = 0x00009888, .val = 0x0418A000 },
         { .reg = 0x00009888, .val = 0x08192000 },
         { .reg = 0x00009888, .val = 0x0E19A000 },
         { .reg = 0x00009888, .val = 0x12195540 },
         { .reg = 0x00009888, .val = 0x1419000A },
         { .reg = 0x00009888, .val = 0x0A19A000 },
         { .reg = 0x00009888, .val = 0x0C19A000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x18130343 },
         { .reg = 0x00009888, .val = 0x22000008 },
         { .reg = 0x00009888, .val = 0x12008000 },
         { .reg = 0x00009888, .val = 0x0E137300 },
         { .reg = 0x00009888, .val = 0x00137B00 },
         { .reg = 0x00009888, .val = 0x10130000 },
         { .reg = 0x00009888, .val = 0x1E130000 },
         { .reg = 0x00009888, .val = 0x1C130000 },
         { .reg = 0x00009888, .val = 0x0E168000 },
         { .reg = 0x00009888, .val = 0x00168000 },
         { .reg = 0x00009888, .val = 0x1A1A0010 },
         { .reg = 0x00009888, .val = 0x021A4000 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4924 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F000C },
         { .reg = 0x00009888, .val = 0x3A1F2000 },
         { .reg = 0x00009888, .val = 0x4E1F2441 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x401F1041 },
         { .reg = 0x00009888, .val = 0x421F1010 },
         { .reg = 0x00009888, .val = 0x441F1010 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x30000036 },
         { .reg = 0x00002774, .val = 0x01FFFE00 },
         { .reg = 0x00002778, .val = 0x31000034 },
         { .reg = 0x0000277C, .val = 0x01FFFE00 },
         { .reg = 0x00002780, .val = 0x00000C9A },
         { .reg = 0x00002784, .val = 0x0000FE00 },
         { .reg = 0x00002788, .val = 0x00000C92 },
         { .reg = 0x0000278C, .val = 0x0000FE00 },
         { .reg = 0x00002790, .val = 0x00000CA2 },
         { .reg = 0x00002794, .val = 0x0000FE00 },
         { .reg = 0x00002798, .val = 0x00000E42 },
         { .reg = 0x0000279C, .val = 0x0000FE00 },
         { .reg = 0x000027A0, .val = 0x00000E6A },
         { .reg = 0x000027A4, .val = 0x0000FE00 },
         { .reg = 0x000027A8, .val = 0x00000C32 },
         { .reg = 0x000027AC, .val = 0x0000FE00 },
         { .reg = 0x0000274C, .val = 0x87643210 },
         { .reg = 0x00002744, .val = 0x00001811 },
         { .reg = 0x00002748, .val = 0x87654310 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__compute_extended__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__compute_extended__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__compute_extended__avg_gpu_core_frequency__max,ehl__compute_extended__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__compute_extended__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 8, 32, NULL,ehl__compute_extended__cs_threads__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 419, 40, NULL,ehl__compute_extended__typed_atomics00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 420, 48, NULL,ehl__compute_extended__typed_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 421, 56, NULL,ehl__compute_extended__typed_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 422, 64, NULL,ehl__compute_extended__untyped_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 423, 72, NULL,ehl__compute_extended__untyped_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 424, 80, NULL,ehl__compute_extended__eu_typed_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 425, 88, NULL,ehl__compute_extended__eu_typed_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 426, 96, NULL,ehl__compute_extended__eu_typed_atomics00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 427, 104, NULL,ehl__compute_extended__eu_a32_untyped_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 428, 112, NULL,ehl__compute_extended__eu_a32_untyped_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 429, 120, NULL,ehl__compute_extended__eu_a64_untyped_reads00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 430, 128, NULL,ehl__compute_extended__eu_a64_untyped_writes00__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 94, 136, NULL,ehl__compute_extended__typed_atomics_per_cache_line__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 90, 140, NULL,ehl__compute_extended__typed_reads_per_cache_line__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 91, 144, NULL,ehl__compute_extended__typed_writes_per_cache_line__read);
      }

      intel_perf_query_add_counter_float(query, 92, 148, NULL,ehl__compute_extended__untyped_reads_per_cache_line__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 93, 152, NULL,ehl__compute_extended__untyped_writes_per_cache_line__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_compute_l3_cache_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 57);

   query->name = "Compute Metrics L3 Cache set";
   query->symbol_name = "ComputeL3Cache";
   query->guid = "89e1f7ae-1100-4b4f-92f3-0caf88e3d833";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14120700 },
         { .reg = 0x00009888, .val = 0x121500E0 },
         { .reg = 0x00009888, .val = 0x10040154 },
         { .reg = 0x00009888, .val = 0x0C045000 },
         { .reg = 0x00009888, .val = 0x0E040055 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x04054000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x0A051000 },
         { .reg = 0x00009888, .val = 0x260600F0 },
         { .reg = 0x00009888, .val = 0x24067E00 },
         { .reg = 0x00009888, .val = 0x0C120023 },
         { .reg = 0x00009888, .val = 0x0E12152B },
         { .reg = 0x00009888, .val = 0x00121480 },
         { .reg = 0x00009888, .val = 0x02120028 },
         { .reg = 0x00009888, .val = 0x10120000 },
         { .reg = 0x00009888, .val = 0x18120000 },
         { .reg = 0x00009888, .val = 0x1A120000 },
         { .reg = 0x00009888, .val = 0x04120000 },
         { .reg = 0x00009888, .val = 0x0A13D000 },
         { .reg = 0x00009888, .val = 0x04136000 },
         { .reg = 0x00009888, .val = 0x0C144000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02144000 },
         { .reg = 0x00009888, .val = 0x0C150980 },
         { .reg = 0x00009888, .val = 0x02154D80 },
         { .reg = 0x00009888, .val = 0x04154C9A },
         { .reg = 0x00009888, .val = 0x06150018 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x16150800 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009888, .val = 0x08150000 },
         { .reg = 0x00009888, .val = 0x0A150000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x0A1473A0 },
         { .reg = 0x00009888, .val = 0x1217241C },
         { .reg = 0x00009888, .val = 0x2000F000 },
         { .reg = 0x00009888, .val = 0x1C134000 },
         { .reg = 0x00009888, .val = 0x1E130015 },
         { .reg = 0x00009888, .val = 0x061434A0 },
         { .reg = 0x00009888, .val = 0x0E140000 },
         { .reg = 0x00009888, .val = 0x0C143000 },
         { .reg = 0x00009888, .val = 0x0816C000 },
         { .reg = 0x00009888, .val = 0x0A16C000 },
         { .reg = 0x00009888, .val = 0x081710B0 },
         { .reg = 0x00009888, .val = 0x00170000 },
         { .reg = 0x00009888, .val = 0x161A2000 },
         { .reg = 0x00009888, .val = 0x181A1500 },
         { .reg = 0x00009888, .val = 0x501F1124 },
         { .reg = 0x00009888, .val = 0x521F4849 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x461F0100 },
         { .reg = 0x00009888, .val = 0x481F1101 },
         { .reg = 0x00009888, .val = 0x4A1F0011 },
         { .reg = 0x00009888, .val = 0x4C1F0030 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009888, .val = 0x401F0000 },
         { .reg = 0x00009888, .val = 0x421F3030 },
         { .reg = 0x00009888, .val = 0x441F3030 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000003 },
         { .reg = 0x0000E658, .val = 0x00002001 },
         { .reg = 0x0000E758, .val = 0x00101100 },
         { .reg = 0x0000E45C, .val = 0x00201200 },
         { .reg = 0x0000E55C, .val = 0x00301300 },
         { .reg = 0x0000E65C, .val = 0x00401400 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__compute_l3_cache__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__compute_l3_cache__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__compute_l3_cache__avg_gpu_core_frequency__max,ehl__compute_l3_cache__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__compute_l3_cache__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__compute_l3_cache__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__compute_l3_cache__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__compute_l3_cache__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__compute_l3_cache__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__compute_l3_cache__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__compute_l3_cache__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__compute_l3_cache__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__compute_l3_cache__eu_stall__read);

      intel_perf_query_add_counter_float(query, 152, 88, ehl__compute_l3_cache__eu_avg_ipc_rate__max,ehl__compute_l3_cache__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 123, 92, percentage_max_float,ehl__compute_l3_cache__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 150, 96, percentage_max_float,ehl__compute_l3_cache__fpu0_active__read);

      intel_perf_query_add_counter_float(query, 151, 100, percentage_max_float,ehl__compute_l3_cache__fpu1_active__read);

      intel_perf_query_add_counter_float(query, 153, 104, percentage_max_float,ehl__compute_l3_cache__eu_send_active__read);

      intel_perf_query_add_counter_float(query, 196, 108, percentage_max_float,ehl__compute_l3_cache__eu_hybrid_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 197, 112, percentage_max_float,ehl__compute_l3_cache__eu_hybrid_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 198, 116, percentage_max_float,ehl__compute_l3_cache__eu_ternary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 199, 120, percentage_max_float,ehl__compute_l3_cache__eu_ternary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 200, 124, percentage_max_float,ehl__compute_l3_cache__eu_binary_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 201, 128, percentage_max_float,ehl__compute_l3_cache__eu_binary_fpu1_instruction__read);

      intel_perf_query_add_counter_float(query, 202, 132, percentage_max_float,ehl__compute_l3_cache__eu_move_fpu0_instruction__read);

      intel_perf_query_add_counter_float(query, 203, 136, percentage_max_float,ehl__compute_l3_cache__eu_move_fpu1_instruction__read);

      intel_perf_query_add_counter_uint64(query, 139, 144, NULL,ehl__compute_l3_cache__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 152, NULL,ehl__compute_l3_cache__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 160, NULL,ehl__compute_l3_cache__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 168, NULL,ehl__compute_l3_cache__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 176, NULL,ehl__compute_l3_cache__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 184, NULL,ehl__compute_l3_cache__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 192, NULL,ehl__compute_l3_cache__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 156, 200, NULL,ehl__compute_l3_cache__sampler_accesses__read);

      intel_perf_query_add_counter_uint64(query, 136, 208, NULL,ehl__compute_l3_cache__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 216, NULL,ehl__compute_l3_cache__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 224, ehl__compute_l3_cache__slm_bytes_read__max,ehl__compute_l3_cache__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 232, ehl__compute_l3_cache__slm_bytes_written__max,ehl__compute_l3_cache__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 240, NULL,ehl__compute_l3_cache__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 248, NULL,ehl__compute_l3_cache__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 256, NULL,ehl__compute_l3_cache__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 348, 264, NULL,ehl__compute_l3_cache__l3_bank00_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 349, 272, NULL,ehl__compute_l3_cache__l3_bank01_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 350, 280, NULL,ehl__compute_l3_cache__l3_bank02_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 351, 288, NULL,ehl__compute_l3_cache__l3_bank03_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 352, 296, NULL,ehl__compute_l3_cache__l3_bank04_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 353, 304, NULL,ehl__compute_l3_cache__l3_bank05_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 354, 312, NULL,ehl__compute_l3_cache__l3_bank06_accesses__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_uint64(query, 355, 320, NULL,ehl__compute_l3_cache__l3_bank07_accesses__read);
      }

      intel_perf_query_add_counter_uint64(query, 204, 328, NULL,ehl__compute_l3_cache__l3_accesses__read);

      intel_perf_query_add_counter_uint64(query, 144, 336, NULL,ehl__compute_l3_cache__l3_lookups__read);

      intel_perf_query_add_counter_uint64(query, 145, 344, NULL,ehl__compute_l3_cache__l3_misses__read);

      intel_perf_query_add_counter_uint64(query, 44, 352, ehl__compute_l3_cache__l3_sampler_throughput__max,ehl__compute_l3_cache__l3_sampler_throughput__read);

      intel_perf_query_add_counter_uint64(query, 146, 360, ehl__compute_l3_cache__l3_shader_throughput__max,ehl__compute_l3_cache__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 205, 368, ehl__compute_l3_cache__l3_total_throughput__max,ehl__compute_l3_cache__l3_total_throughput__read);

      intel_perf_query_add_counter_uint64(query, 56, 376, ehl__compute_l3_cache__gti_l3_throughput__max,ehl__compute_l3_cache__gti_l3_throughput__read);

      intel_perf_query_add_counter_uint64(query, 57, 384, ehl__compute_l3_cache__gti_read_throughput__max,ehl__compute_l3_cache__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 392, ehl__compute_l3_cache__gti_write_throughput__max,ehl__compute_l3_cache__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "7bfa0a68-c327-46e8-a556-cfa7b4651071";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x101E001E },
         { .reg = 0x00009888, .val = 0x10160000 },
         { .reg = 0x00009888, .val = 0x1017001F },
         { .reg = 0x00009888, .val = 0x0A1E0500 },
         { .reg = 0x00009888, .val = 0x1E1E0000 },
         { .reg = 0x00009888, .val = 0x1A200100 },
         { .reg = 0x00009888, .val = 0x10040015 },
         { .reg = 0x00009888, .val = 0x0E054000 },
         { .reg = 0x00009888, .val = 0x14050005 },
         { .reg = 0x00009888, .val = 0x26060038 },
         { .reg = 0x00009888, .val = 0x16157E00 },
         { .reg = 0x00009888, .val = 0x0C160022 },
         { .reg = 0x00009888, .val = 0x08160000 },
         { .reg = 0x00009888, .val = 0x0C170540 },
         { .reg = 0x00009888, .val = 0x04170000 },
         { .reg = 0x00009888, .val = 0x0A188000 },
         { .reg = 0x00009888, .val = 0x0C181000 },
         { .reg = 0x00009888, .val = 0x12195000 },
         { .reg = 0x00009888, .val = 0x14190001 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x100A0019 },
         { .reg = 0x00009888, .val = 0x140A001F },
         { .reg = 0x00009888, .val = 0x180B0000 },
         { .reg = 0x00009888, .val = 0x160C0000 },
         { .reg = 0x00009888, .val = 0x1C020000 },
         { .reg = 0x00009888, .val = 0x1806801F },
         { .reg = 0x00009888, .val = 0x1007001E },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x0A0A0047 },
         { .reg = 0x00009888, .val = 0x020A0002 },
         { .reg = 0x00009888, .val = 0x040A0043 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009888, .val = 0x080B3100 },
         { .reg = 0x00009888, .val = 0x020B3200 },
         { .reg = 0x00009888, .val = 0x100B0000 },
         { .reg = 0x00009888, .val = 0x040C2900 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x100200B1 },
         { .reg = 0x00009888, .val = 0x020200B3 },
         { .reg = 0x00009888, .val = 0x08020000 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00034000 },
         { .reg = 0x00009888, .val = 0x08038000 },
         { .reg = 0x00009888, .val = 0x0E034000 },
         { .reg = 0x00009888, .val = 0x02038000 },
         { .reg = 0x00009888, .val = 0x1C04FFB6 },
         { .reg = 0x00009888, .val = 0x1E04E039 },
         { .reg = 0x00009888, .val = 0x0C059000 },
         { .reg = 0x00009888, .val = 0x10050042 },
         { .reg = 0x00009888, .val = 0x06060095 },
         { .reg = 0x00009888, .val = 0x1E060084 },
         { .reg = 0x00009888, .val = 0x1C068000 },
         { .reg = 0x00009888, .val = 0x14068000 },
         { .reg = 0x00009888, .val = 0x1A068000 },
         { .reg = 0x00009888, .val = 0x00070022 },
         { .reg = 0x00009888, .val = 0x0E070023 },
         { .reg = 0x00009888, .val = 0x08078000 },
         { .reg = 0x00009888, .val = 0x02078000 },
         { .reg = 0x00009888, .val = 0x06080100 },
         { .reg = 0x00009888, .val = 0x0E080300 },
         { .reg = 0x00009888, .val = 0x1C080004 },
         { .reg = 0x00009888, .val = 0x1A082000 },
         { .reg = 0x00009888, .val = 0x14088000 },
         { .reg = 0x00009888, .val = 0x18088000 },
         { .reg = 0x00009888, .val = 0x1C090800 },
         { .reg = 0x00009888, .val = 0x16098000 },
         { .reg = 0x00009888, .val = 0x301F6000 },
         { .reg = 0x00009888, .val = 0x501F36DB },
         { .reg = 0x00009888, .val = 0x521F491B },
         { .reg = 0x00009888, .val = 0x541F001B },
         { .reg = 0x00009888, .val = 0x3A1F6000 },
         { .reg = 0x00009888, .val = 0x4E1F1B41 },
         { .reg = 0x00009888, .val = 0x3E1F3100 },
         { .reg = 0x00009888, .val = 0x461F5141 },
         { .reg = 0x00009888, .val = 0x481F3111 },
         { .reg = 0x00009888, .val = 0x4A1F1000 },
         { .reg = 0x00009888, .val = 0x4C1F3120 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x401F3151 },
         { .reg = 0x00009888, .val = 0x421F3111 },
         { .reg = 0x00009888, .val = 0x441F5121 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__render_pipe_profile__avg_gpu_core_frequency__max,ehl__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 139, 88, NULL,ehl__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 96, NULL,ehl__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 104, NULL,ehl__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 112, NULL,ehl__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 120, NULL,ehl__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 128, NULL,ehl__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 136, NULL,ehl__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 144, NULL,ehl__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 152, NULL,ehl__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 160, ehl__render_pipe_profile__slm_bytes_read__max,ehl__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 168, ehl__render_pipe_profile__slm_bytes_written__max,ehl__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 176, NULL,ehl__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 184, NULL,ehl__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 192, ehl__render_pipe_profile__l3_shader_throughput__max,ehl__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 200, NULL,ehl__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 208, percentage_max_float,ehl__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 212, percentage_max_float,ehl__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 216, percentage_max_float,ehl__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 220, percentage_max_float,ehl__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 224, percentage_max_float,ehl__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 228, percentage_max_float,ehl__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 232, percentage_max_float,ehl__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 236, percentage_max_float,ehl__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 240, percentage_max_float,ehl__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 166, 244, percentage_max_float,ehl__render_pipe_profile__early_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 248, percentage_max_float,ehl__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 252, percentage_max_float,ehl__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 256, percentage_max_float,ehl__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 260, percentage_max_float,ehl__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 264, percentage_max_float,ehl__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 268, percentage_max_float,ehl__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "697eadd2-bc54-459f-b634-fcb3d4a2d627";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1223000A },
         { .reg = 0x00009888, .val = 0x10230009 },
         { .reg = 0x00009888, .val = 0x1263000A },
         { .reg = 0x00009888, .val = 0x10630009 },
         { .reg = 0x00009888, .val = 0x12A3000A },
         { .reg = 0x00009888, .val = 0x10A30009 },
         { .reg = 0x00009888, .val = 0x12E3000A },
         { .reg = 0x00009888, .val = 0x10E30009 },
         { .reg = 0x00009888, .val = 0x10150019 },
         { .reg = 0x00009888, .val = 0x1A20A000 },
         { .reg = 0x00009888, .val = 0x0C231900 },
         { .reg = 0x00009888, .val = 0x0E23003C },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x1C600002 },
         { .reg = 0x00009888, .val = 0x02608000 },
         { .reg = 0x00009888, .val = 0x0E631900 },
         { .reg = 0x00009888, .val = 0x00631E00 },
         { .reg = 0x00009888, .val = 0x04A08000 },
         { .reg = 0x00009888, .val = 0x06A08000 },
         { .reg = 0x00009888, .val = 0x02A31E32 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x08E08000 },
         { .reg = 0x00009888, .val = 0x0AE08000 },
         { .reg = 0x00009888, .val = 0x04E31E32 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x10040150 },
         { .reg = 0x00009888, .val = 0x0E040015 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x14050054 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x24063F00 },
         { .reg = 0x00009888, .val = 0x260600E0 },
         { .reg = 0x00009888, .val = 0x0E088000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x14090040 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x080E5000 },
         { .reg = 0x00009888, .val = 0x1A120020 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x0412C000 },
         { .reg = 0x00009888, .val = 0x0612C000 },
         { .reg = 0x00009888, .val = 0x0A138000 },
         { .reg = 0x00009888, .val = 0x0413E000 },
         { .reg = 0x00009888, .val = 0x0E148000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x0214C000 },
         { .reg = 0x00009888, .val = 0x00150047 },
         { .reg = 0x00009888, .val = 0x16156000 },
         { .reg = 0x00009888, .val = 0x18150007 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08158000 },
         { .reg = 0x00009888, .val = 0x0A158000 },
         { .reg = 0x00009888, .val = 0x0C188000 },
         { .reg = 0x00009888, .val = 0x0E182000 },
         { .reg = 0x00009888, .val = 0x1419000A },
         { .reg = 0x00009888, .val = 0x021CA000 },
         { .reg = 0x00009888, .val = 0x0A1DA000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3061 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x521F4000 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x501F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0100 },
         { .reg = 0x00009888, .val = 0x4C1F3030 },
         { .reg = 0x00009888, .val = 0x401F0000 },
         { .reg = 0x00009888, .val = 0x421F3000 },
         { .reg = 0x00009888, .val = 0x441F3330 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000002 },
         { .reg = 0x00002774, .val = 0x0000FFFE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__hdc_and_sf__avg_gpu_core_frequency__max,ehl__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,ehl__hdc_and_sf__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,ehl__hdc_and_sf__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,ehl__hdc_and_sf__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,ehl__hdc_and_sf__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,ehl__hdc_and_sf__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,ehl__hdc_and_sf__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,ehl__hdc_and_sf__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,ehl__hdc_and_sf__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,ehl__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,ehl__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,ehl__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,ehl__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,ehl__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,ehl__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,ehl__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,ehl__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,ehl__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, ehl__hdc_and_sf__slm_bytes_read__max,ehl__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, ehl__hdc_and_sf__slm_bytes_written__max,ehl__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,ehl__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,ehl__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, ehl__hdc_and_sf__l3_shader_throughput__max,ehl__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,ehl__hdc_and_sf__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 3) {
         intel_perf_query_add_counter_float(query, 431, 240, percentage_max_float,ehl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 12) {
         intel_perf_query_add_counter_float(query, 432, 244, percentage_max_float,ehl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 48) {
         intel_perf_query_add_counter_float(query, 433, 248, percentage_max_float,ehl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 192) {
         intel_perf_query_add_counter_float(query, 434, 252, percentage_max_float,ehl__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read);
      }

      intel_perf_query_add_counter_float(query, 237, 256, percentage_max_float,ehl__hdc_and_sf__poly_data_ready__read);

      intel_perf_query_add_counter_float(query, 244, 260, percentage_max_float,ehl__hdc_and_sf__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "5cda6ba5-f3b7-43a4-8027-8d0958a263c4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x120A03E0 },
         { .reg = 0x00009888, .val = 0x140C0500 },
         { .reg = 0x00009888, .val = 0x120F03E0 },
         { .reg = 0x00009888, .val = 0x14110500 },
         { .reg = 0x00009888, .val = 0x10136000 },
         { .reg = 0x00009888, .val = 0x1213001C },
         { .reg = 0x00009888, .val = 0x16140000 },
         { .reg = 0x00009888, .val = 0x10160018 },
         { .reg = 0x00009888, .val = 0x101A0018 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x0E045545 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E051000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08051000 },
         { .reg = 0x00009888, .val = 0x2406DF00 },
         { .reg = 0x00009888, .val = 0x26060007 },
         { .reg = 0x00009888, .val = 0x02084000 },
         { .reg = 0x00009888, .val = 0x04098000 },
         { .reg = 0x00009888, .val = 0x06094000 },
         { .reg = 0x00009888, .val = 0x000A0C40 },
         { .reg = 0x00009888, .val = 0x0C0A0000 },
         { .reg = 0x00009888, .val = 0x040A0000 },
         { .reg = 0x00009888, .val = 0x020C0B80 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x040D1000 },
         { .reg = 0x00009888, .val = 0x060E2000 },
         { .reg = 0x00009888, .val = 0x080E1000 },
         { .reg = 0x00009888, .val = 0x020F0031 },
         { .reg = 0x00009888, .val = 0x0C0F0000 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x04110017 },
         { .reg = 0x00009888, .val = 0x08110000 },
         { .reg = 0x00009888, .val = 0x18120C00 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x06128000 },
         { .reg = 0x00009888, .val = 0x0613092F },
         { .reg = 0x00009888, .val = 0x08134025 },
         { .reg = 0x00009888, .val = 0x0C130000 },
         { .reg = 0x00009888, .val = 0x0413A000 },
         { .reg = 0x00009888, .val = 0x00148066 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x0614C000 },
         { .reg = 0x00009888, .val = 0x08144000 },
         { .reg = 0x00009888, .val = 0x0A144000 },
         { .reg = 0x00009888, .val = 0x02148000 },
         { .reg = 0x00009888, .val = 0x00154000 },
         { .reg = 0x00009888, .val = 0x0E154000 },
         { .reg = 0x00009888, .val = 0x161500E8 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04158000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08158000 },
         { .reg = 0x00009888, .val = 0x0C154000 },
         { .reg = 0x00009888, .val = 0x08161000 },
         { .reg = 0x00009888, .val = 0x08184000 },
         { .reg = 0x00009888, .val = 0x12190100 },
         { .reg = 0x00009888, .val = 0x0A1A0020 },
         { .reg = 0x00009888, .val = 0x081A0000 },
         { .reg = 0x00009888, .val = 0x0A1C1000 },
         { .reg = 0x00009888, .val = 0x121D0400 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3000 },
         { .reg = 0x00009888, .val = 0x1A1F0061 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4904 },
         { .reg = 0x00009888, .val = 0x521F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x3E1F5000 },
         { .reg = 0x00009888, .val = 0x461F4040 },
         { .reg = 0x00009888, .val = 0x481F0030 },
         { .reg = 0x00009888, .val = 0x401F4010 },
         { .reg = 0x00009888, .val = 0x421F3000 },
         { .reg = 0x00009888, .val = 0x441F4023 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x70800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000038 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000002 },
         { .reg = 0x0000277C, .val = 0x0000FFF7 },
         { .reg = 0x00002780, .val = 0x00000002 },
         { .reg = 0x00002784, .val = 0x0000FFEF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,ehl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,ehl__rasterizer_and_pixel_backend__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,ehl__rasterizer_and_pixel_backend__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,ehl__rasterizer_and_pixel_backend__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,ehl__rasterizer_and_pixel_backend__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,ehl__rasterizer_and_pixel_backend__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,ehl__rasterizer_and_pixel_backend__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,ehl__rasterizer_and_pixel_backend__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,ehl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,ehl__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,ehl__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,ehl__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,ehl__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,ehl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,ehl__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,ehl__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,ehl__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,ehl__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, ehl__rasterizer_and_pixel_backend__slm_bytes_read__max,ehl__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, ehl__rasterizer_and_pixel_backend__slm_bytes_written__max,ehl__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,ehl__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,ehl__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, ehl__rasterizer_and_pixel_backend__l3_shader_throughput__max,ehl__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,ehl__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 266, 240, percentage_max_float,ehl__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 261, 244, percentage_max_float,ehl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 360, 248, percentage_max_float,ehl__rasterizer_and_pixel_backend__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 361, 252, percentage_max_float,ehl__rasterizer_and_pixel_backend__pixel_data01_ready__read);

      intel_perf_query_add_counter_float(query, 362, 256, percentage_max_float,ehl__rasterizer_and_pixel_backend__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 363, 260, percentage_max_float,ehl__rasterizer_and_pixel_backend__ps_output01_available__read);

      intel_perf_query_add_counter_float(query, 364, 264, percentage_max_float,ehl__rasterizer_and_pixel_backend__pixel_values00_ready__read);

      intel_perf_query_add_counter_float(query, 365, 268, percentage_max_float,ehl__rasterizer_and_pixel_backend__pixel_values01_ready__read);

      intel_perf_query_add_counter_float(query, 244, 272, percentage_max_float,ehl__rasterizer_and_pixel_backend__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Metric set L3_1";
   query->symbol_name = "L3_1";
   query->guid = "834bfd76-48d7-4552-81fa-ba1f21d6014c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x17340000 },
         { .reg = 0x00009888, .val = 0x17740000 },
         { .reg = 0x00009888, .val = 0x17B40000 },
         { .reg = 0x00009888, .val = 0x17F40000 },
         { .reg = 0x00009888, .val = 0x16340000 },
         { .reg = 0x00009888, .val = 0x16740000 },
         { .reg = 0x00009888, .val = 0x16B40000 },
         { .reg = 0x00009888, .val = 0x16F40000 },
         { .reg = 0x00009888, .val = 0x07340017 },
         { .reg = 0x00009888, .val = 0x27340000 },
         { .reg = 0x00009888, .val = 0x09740017 },
         { .reg = 0x00009888, .val = 0x27740000 },
         { .reg = 0x00009888, .val = 0x0BB40017 },
         { .reg = 0x00009888, .val = 0x27B40000 },
         { .reg = 0x00009888, .val = 0x0DF40017 },
         { .reg = 0x00009888, .val = 0x27F40000 },
         { .reg = 0x00009888, .val = 0x0E0000A7 },
         { .reg = 0x00009888, .val = 0x08012000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x0C038000 },
         { .reg = 0x00009888, .val = 0x1C340017 },
         { .reg = 0x00009888, .val = 0x26340000 },
         { .reg = 0x00009888, .val = 0x1E740017 },
         { .reg = 0x00009888, .val = 0x26740000 },
         { .reg = 0x00009888, .val = 0x02B40017 },
         { .reg = 0x00009888, .val = 0x26B40000 },
         { .reg = 0x00009888, .val = 0x04F40017 },
         { .reg = 0x00009888, .val = 0x26F40000 },
         { .reg = 0x00009888, .val = 0x10040200 },
         { .reg = 0x00009888, .val = 0x0E040055 },
         { .reg = 0x00009888, .val = 0x14050070 },
         { .reg = 0x00009888, .val = 0x04058000 },
         { .reg = 0x00009888, .val = 0x06056000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x0A051000 },
         { .reg = 0x00009888, .val = 0x260600C0 },
         { .reg = 0x00009888, .val = 0x24067E00 },
         { .reg = 0x00009888, .val = 0x02074000 },
         { .reg = 0x00009888, .val = 0x04078000 },
         { .reg = 0x00009888, .val = 0x06124000 },
         { .reg = 0x00009888, .val = 0x08124000 },
         { .reg = 0x00009888, .val = 0x0A124000 },
         { .reg = 0x00009888, .val = 0x0C124000 },
         { .reg = 0x00009888, .val = 0x04138000 },
         { .reg = 0x00009888, .val = 0x06137000 },
         { .reg = 0x00009888, .val = 0x02148000 },
         { .reg = 0x00009888, .val = 0x0414C000 },
         { .reg = 0x00009888, .val = 0x06144000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08154000 },
         { .reg = 0x00009888, .val = 0x0A154000 },
         { .reg = 0x00009888, .val = 0x0C154000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3000 },
         { .reg = 0x00009888, .val = 0x2A1F0061 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x521F0000 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2460 },
         { .reg = 0x00009888, .val = 0x501F0124 },
         { .reg = 0x00009888, .val = 0x4C1F0133 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009888, .val = 0x401F6060 },
         { .reg = 0x00009888, .val = 0x421F0010 },
         { .reg = 0x00009888, .val = 0x441F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__l3_1__avg_gpu_core_frequency__max,ehl__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__l3_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,ehl__l3_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,ehl__l3_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,ehl__l3_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,ehl__l3_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,ehl__l3_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,ehl__l3_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,ehl__l3_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,ehl__l3_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,ehl__l3_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,ehl__l3_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,ehl__l3_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,ehl__l3_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,ehl__l3_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,ehl__l3_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,ehl__l3_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,ehl__l3_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,ehl__l3_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, ehl__l3_1__slm_bytes_read__max,ehl__l3_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, ehl__l3_1__slm_bytes_written__max,ehl__l3_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,ehl__l3_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,ehl__l3_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, ehl__l3_1__l3_shader_throughput__max,ehl__l3_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,ehl__l3_1__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 252, 240, percentage_max_float,ehl__l3_1__l30_bank0_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 251, 244, percentage_max_float,ehl__l3_1__l30_bank1_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 260, 248, percentage_max_float,ehl__l3_1__l30_bank2_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 256, 252, percentage_max_float,ehl__l3_1__l30_bank3_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 366, 256, percentage_max_float,ehl__l3_1__l30_bank4_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 367, 260, percentage_max_float,ehl__l3_1__l30_bank5_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 368, 264, percentage_max_float,ehl__l3_1__l30_bank6_active__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 369, 268, percentage_max_float,ehl__l3_1__l30_bank7_active__read);
      }

      intel_perf_query_add_counter_float(query, 244, 272, percentage_max_float,ehl__l3_1__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "L2Bank0 stalled metric set";
   query->symbol_name = "L3_2";
   query->guid = "f3da54bc-da93-4008-bafc-daebdd79ab40";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x10050C00 },
         { .reg = 0x00009888, .val = 0x12050002 },
         { .reg = 0x00009888, .val = 0x00050025 },
         { .reg = 0x00009888, .val = 0x06050900 },
         { .reg = 0x00009888, .val = 0x080508EA },
         { .reg = 0x00009888, .val = 0x0A0508AB },
         { .reg = 0x00009888, .val = 0x0C050A21 },
         { .reg = 0x00009888, .val = 0x0E050A60 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x14050000 },
         { .reg = 0x00009888, .val = 0x24068100 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4800 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x4E1F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000022 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000082 },
         { .reg = 0x0000277C, .val = 0x0000FFE7 },
         { .reg = 0x00002780, .val = 0x00000402 },
         { .reg = 0x00002784, .val = 0x0000FF1F },
         { .reg = 0x00002788, .val = 0x00001002 },
         { .reg = 0x0000278C, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
         { .reg = 0x0000E55C, .val = 0x00000053 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__l3_2__avg_gpu_core_frequency__max,ehl__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__l3_2__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 139, 80, NULL,ehl__l3_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 88, NULL,ehl__l3_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 96, NULL,ehl__l3_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 104, NULL,ehl__l3_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 112, NULL,ehl__l3_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 120, NULL,ehl__l3_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 128, NULL,ehl__l3_2__samples_blended__read);

      intel_perf_query_add_counter_float(query, 10, 136, percentage_max_float,ehl__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 140, percentage_max_float,ehl__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 144, percentage_max_float,ehl__l3_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 148, percentage_max_float,ehl__l3_2__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 124, 152, percentage_max_float,ehl__l3_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 156, percentage_max_float,ehl__l3_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 160, percentage_max_float,ehl__l3_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 164, percentage_max_float,ehl__l3_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 168, percentage_max_float,ehl__l3_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 172, percentage_max_float,ehl__l3_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 176, percentage_max_float,ehl__l3_2__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 249, 180, percentage_max_float,ehl__l3_2__l30_bank0_stalled__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "L2Bank1 stalled metric set";
   query->symbol_name = "L3_3";
   query->guid = "fb4664db-4a4b-4d45-8f38-ceab6eac078c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x10050400 },
         { .reg = 0x00009888, .val = 0x12050000 },
         { .reg = 0x00009888, .val = 0x00050025 },
         { .reg = 0x00009888, .val = 0x06050900 },
         { .reg = 0x00009888, .val = 0x080508EA },
         { .reg = 0x00009888, .val = 0x0A0508AB },
         { .reg = 0x00009888, .val = 0x0C050A21 },
         { .reg = 0x00009888, .val = 0x0E050A60 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x14050000 },
         { .reg = 0x00009888, .val = 0x24068100 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4800 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x4E1F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000022 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000082 },
         { .reg = 0x0000277C, .val = 0x0000FFE7 },
         { .reg = 0x00002780, .val = 0x00000402 },
         { .reg = 0x00002784, .val = 0x0000FF1F },
         { .reg = 0x00002788, .val = 0x00001002 },
         { .reg = 0x0000278C, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
         { .reg = 0x0000E55C, .val = 0x00000053 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__l3_3__avg_gpu_core_frequency__max,ehl__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__l3_3__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 139, 80, NULL,ehl__l3_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 88, NULL,ehl__l3_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 96, NULL,ehl__l3_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 104, NULL,ehl__l3_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 112, NULL,ehl__l3_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 120, NULL,ehl__l3_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 128, NULL,ehl__l3_3__samples_blended__read);

      intel_perf_query_add_counter_float(query, 10, 136, percentage_max_float,ehl__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 140, percentage_max_float,ehl__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 144, percentage_max_float,ehl__l3_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 148, percentage_max_float,ehl__l3_3__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 124, 152, percentage_max_float,ehl__l3_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 156, percentage_max_float,ehl__l3_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 160, percentage_max_float,ehl__l3_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 164, percentage_max_float,ehl__l3_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 168, percentage_max_float,ehl__l3_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 172, percentage_max_float,ehl__l3_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 176, percentage_max_float,ehl__l3_3__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 250, 180, percentage_max_float,ehl__l3_3__l30_bank1_stalled__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_l3_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "L2Bank4 stalled metric set";
   query->symbol_name = "L3_4";
   query->guid = "0092ff25-7595-4671-b21a-d7d94a19a38b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x10010C00 },
         { .reg = 0x00009888, .val = 0x12010002 },
         { .reg = 0x00009888, .val = 0x0C000400 },
         { .reg = 0x00009888, .val = 0x0E005500 },
         { .reg = 0x00009888, .val = 0x10000155 },
         { .reg = 0x00009888, .val = 0x00010025 },
         { .reg = 0x00009888, .val = 0x06010900 },
         { .reg = 0x00009888, .val = 0x080108EA },
         { .reg = 0x00009888, .val = 0x0A0108AB },
         { .reg = 0x00009888, .val = 0x0C010A21 },
         { .reg = 0x00009888, .val = 0x0E010A60 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x14010000 },
         { .reg = 0x00009888, .val = 0x0C040400 },
         { .reg = 0x00009888, .val = 0x0E045500 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04051000 },
         { .reg = 0x00009888, .val = 0x0A054000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x24068100 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0E124000 },
         { .reg = 0x00009888, .val = 0x18125540 },
         { .reg = 0x00009888, .val = 0x1A120015 },
         { .reg = 0x00009888, .val = 0x04131000 },
         { .reg = 0x00009888, .val = 0x06138000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x00144000 },
         { .reg = 0x00009888, .val = 0x06148000 },
         { .reg = 0x00009888, .val = 0x0814C000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00154000 },
         { .reg = 0x00009888, .val = 0x0E154000 },
         { .reg = 0x00009888, .val = 0x16152AA8 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4800 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x4E1F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000022 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000082 },
         { .reg = 0x0000277C, .val = 0x0000FFE7 },
         { .reg = 0x00002780, .val = 0x00000402 },
         { .reg = 0x00002784, .val = 0x0000FF1F },
         { .reg = 0x00002788, .val = 0x00001002 },
         { .reg = 0x0000278C, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
         { .reg = 0x0000E55C, .val = 0x00000053 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__l3_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__l3_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__l3_4__avg_gpu_core_frequency__max,ehl__l3_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__l3_4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__l3_4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__l3_4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__l3_4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__l3_4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__l3_4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__l3_4__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 139, 80, NULL,ehl__l3_4__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 88, NULL,ehl__l3_4__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 96, NULL,ehl__l3_4__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 104, NULL,ehl__l3_4__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 112, NULL,ehl__l3_4__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 120, NULL,ehl__l3_4__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 128, NULL,ehl__l3_4__samples_blended__read);

      intel_perf_query_add_counter_float(query, 10, 136, percentage_max_float,ehl__l3_4__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 140, percentage_max_float,ehl__l3_4__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 144, percentage_max_float,ehl__l3_4__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 148, percentage_max_float,ehl__l3_4__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 124, 152, percentage_max_float,ehl__l3_4__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 156, percentage_max_float,ehl__l3_4__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 160, percentage_max_float,ehl__l3_4__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 164, percentage_max_float,ehl__l3_4__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 168, percentage_max_float,ehl__l3_4__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 172, percentage_max_float,ehl__l3_4__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 176, percentage_max_float,ehl__l3_4__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 370, 180, percentage_max_float,ehl__l3_4__l30_bank4_stalled__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_l3_5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "L2Bank5 stalled metric set";
   query->symbol_name = "L3_5";
   query->guid = "079c833a-21cb-4832-bc9a-3ea6fc42f516";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x10010400 },
         { .reg = 0x00009888, .val = 0x12010000 },
         { .reg = 0x00009888, .val = 0x0C000400 },
         { .reg = 0x00009888, .val = 0x0E005500 },
         { .reg = 0x00009888, .val = 0x10000155 },
         { .reg = 0x00009888, .val = 0x00010022 },
         { .reg = 0x00009888, .val = 0x06010840 },
         { .reg = 0x00009888, .val = 0x08010828 },
         { .reg = 0x00009888, .val = 0x0A010969 },
         { .reg = 0x00009888, .val = 0x0C010AA4 },
         { .reg = 0x00009888, .val = 0x0E010AE3 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x14010000 },
         { .reg = 0x00009888, .val = 0x0C040400 },
         { .reg = 0x00009888, .val = 0x0E045500 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04051000 },
         { .reg = 0x00009888, .val = 0x0A054000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x24068100 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0E124000 },
         { .reg = 0x00009888, .val = 0x18125540 },
         { .reg = 0x00009888, .val = 0x1A120015 },
         { .reg = 0x00009888, .val = 0x04131000 },
         { .reg = 0x00009888, .val = 0x06138000 },
         { .reg = 0x00009888, .val = 0x0813F000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x00144000 },
         { .reg = 0x00009888, .val = 0x06148000 },
         { .reg = 0x00009888, .val = 0x0814C000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00154000 },
         { .reg = 0x00009888, .val = 0x0E154000 },
         { .reg = 0x00009888, .val = 0x16152AA8 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4800 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3E1F0000 },
         { .reg = 0x00009888, .val = 0x461F0000 },
         { .reg = 0x00009888, .val = 0x481F0000 },
         { .reg = 0x00009888, .val = 0x4A1F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x4E1F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x00000022 },
         { .reg = 0x00002774, .val = 0x0000FFF8 },
         { .reg = 0x00002778, .val = 0x00000082 },
         { .reg = 0x0000277C, .val = 0x0000FFE7 },
         { .reg = 0x00002780, .val = 0x00000402 },
         { .reg = 0x00002784, .val = 0x0000FF1F },
         { .reg = 0x00002788, .val = 0x00001002 },
         { .reg = 0x0000278C, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00008003 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
         { .reg = 0x0000E55C, .val = 0x00000053 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__l3_5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__l3_5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__l3_5__avg_gpu_core_frequency__max,ehl__l3_5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__l3_5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__l3_5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__l3_5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__l3_5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__l3_5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__l3_5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__l3_5__cs_threads__read);

      intel_perf_query_add_counter_uint64(query, 139, 80, NULL,ehl__l3_5__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 88, NULL,ehl__l3_5__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 96, NULL,ehl__l3_5__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 104, NULL,ehl__l3_5__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 112, NULL,ehl__l3_5__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 120, NULL,ehl__l3_5__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 128, NULL,ehl__l3_5__samples_blended__read);

      intel_perf_query_add_counter_float(query, 10, 136, percentage_max_float,ehl__l3_5__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 140, percentage_max_float,ehl__l3_5__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 144, percentage_max_float,ehl__l3_5__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 154, 148, percentage_max_float,ehl__l3_5__eu_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 124, 152, percentage_max_float,ehl__l3_5__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 156, percentage_max_float,ehl__l3_5__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 160, percentage_max_float,ehl__l3_5__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 164, percentage_max_float,ehl__l3_5__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 168, percentage_max_float,ehl__l3_5__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 172, percentage_max_float,ehl__l3_5__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 176, percentage_max_float,ehl__l3_5__ps_eu_both_fpu_active__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 371, 180, percentage_max_float,ehl__l3_5__l30_bank5_stalled__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Metric set Sampler 1";
   query->symbol_name = "Sampler_1";
   query->guid = "bf151068-b27b-4851-b46c-627c132f1cb4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x142A0165 },
         { .reg = 0x00009888, .val = 0x142F0165 },
         { .reg = 0x00009888, .val = 0x146A0165 },
         { .reg = 0x00009888, .val = 0x146F0165 },
         { .reg = 0x00009888, .val = 0x14AA0165 },
         { .reg = 0x00009888, .val = 0x14AF0165 },
         { .reg = 0x00009888, .val = 0x14EA0165 },
         { .reg = 0x00009888, .val = 0x14EF0165 },
         { .reg = 0x00009888, .val = 0x161E8000 },
         { .reg = 0x00009888, .val = 0x181E8000 },
         { .reg = 0x00009888, .val = 0x1C1E1800 },
         { .reg = 0x00009888, .val = 0x06204000 },
         { .reg = 0x00009888, .val = 0x08204000 },
         { .reg = 0x00009888, .val = 0x0A204000 },
         { .reg = 0x00009888, .val = 0x0C204000 },
         { .reg = 0x00009888, .val = 0x16218000 },
         { .reg = 0x00009888, .val = 0x18218000 },
         { .reg = 0x00009888, .val = 0x1E210018 },
         { .reg = 0x00009888, .val = 0x042A1800 },
         { .reg = 0x00009888, .val = 0x062AC038 },
         { .reg = 0x00009888, .val = 0x102A0000 },
         { .reg = 0x00009888, .val = 0x082AC000 },
         { .reg = 0x00009888, .val = 0x0A2A0000 },
         { .reg = 0x00009888, .val = 0x0C2A0000 },
         { .reg = 0x00009888, .val = 0x062C4000 },
         { .reg = 0x00009888, .val = 0x082C4000 },
         { .reg = 0x00009888, .val = 0x0A2C4000 },
         { .reg = 0x00009888, .val = 0x0C2C4000 },
         { .reg = 0x00009888, .val = 0x022F2000 },
         { .reg = 0x00009888, .val = 0x042F0048 },
         { .reg = 0x00009888, .val = 0x102F0000 },
         { .reg = 0x00009888, .val = 0x062F0000 },
         { .reg = 0x00009888, .val = 0x082F0000 },
         { .reg = 0x00009888, .val = 0x1E5E0030 },
         { .reg = 0x00009888, .val = 0x125E8000 },
         { .reg = 0x00009888, .val = 0x145E8000 },
         { .reg = 0x00009888, .val = 0x1A604000 },
         { .reg = 0x00009888, .val = 0x1C600001 },
         { .reg = 0x00009888, .val = 0x02604000 },
         { .reg = 0x00009888, .val = 0x04604000 },
         { .reg = 0x00009888, .val = 0x1E613000 },
         { .reg = 0x00009888, .val = 0x12618000 },
         { .reg = 0x00009888, .val = 0x14618000 },
         { .reg = 0x00009888, .val = 0x006A1800 },
         { .reg = 0x00009888, .val = 0x026A0038 },
         { .reg = 0x00009888, .val = 0x106A0000 },
         { .reg = 0x00009888, .val = 0x1A6A00F0 },
         { .reg = 0x00009888, .val = 0x046A0000 },
         { .reg = 0x00009888, .val = 0x186C5000 },
         { .reg = 0x00009888, .val = 0x026C4000 },
         { .reg = 0x00009888, .val = 0x046C4000 },
         { .reg = 0x00009888, .val = 0x0E6F2440 },
         { .reg = 0x00009888, .val = 0x106F0000 },
         { .reg = 0x00009888, .val = 0x1A6F0000 },
         { .reg = 0x00009888, .val = 0x1E9E000F },
         { .reg = 0x00009888, .val = 0x1AA01540 },
         { .reg = 0x00009888, .val = 0x1EA10F00 },
         { .reg = 0x00009888, .val = 0x0CAA1C30 },
         { .reg = 0x00009888, .val = 0x10AA0000 },
         { .reg = 0x00009888, .val = 0x18AAF000 },
         { .reg = 0x00009888, .val = 0x1AAA0000 },
         { .reg = 0x00009888, .val = 0x18AC0550 },
         { .reg = 0x00009888, .val = 0x0AAF2440 },
         { .reg = 0x00009888, .val = 0x10AF0000 },
         { .reg = 0x00009888, .val = 0x1AAF0000 },
         { .reg = 0x00009888, .val = 0x10DE8000 },
         { .reg = 0x00009888, .val = 0x1CDEE000 },
         { .reg = 0x00009888, .val = 0x00E04000 },
         { .reg = 0x00009888, .val = 0x0EE04000 },
         { .reg = 0x00009888, .val = 0x18E04000 },
         { .reg = 0x00009888, .val = 0x1AE00010 },
         { .reg = 0x00009888, .val = 0x10E18000 },
         { .reg = 0x00009888, .val = 0x1EE100E0 },
         { .reg = 0x00009888, .val = 0x08EA1C30 },
         { .reg = 0x00009888, .val = 0x10EA0000 },
         { .reg = 0x00009888, .val = 0x00EAC000 },
         { .reg = 0x00009888, .val = 0x0EEAC000 },
         { .reg = 0x00009888, .val = 0x18EA0000 },
         { .reg = 0x00009888, .val = 0x00EC4000 },
         { .reg = 0x00009888, .val = 0x0EEC4000 },
         { .reg = 0x00009888, .val = 0x18EC0005 },
         { .reg = 0x00009888, .val = 0x00EF0040 },
         { .reg = 0x00009888, .val = 0x06EF2400 },
         { .reg = 0x00009888, .val = 0x10EF0000 },
         { .reg = 0x00009888, .val = 0x0EEF0000 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x0E045555 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x2406FF00 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x0E08A000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009888, .val = 0x14090050 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x06091000 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x040E1000 },
         { .reg = 0x00009888, .val = 0x0A0E4000 },
         { .reg = 0x00009888, .val = 0x0C0E5000 },
         { .reg = 0x00009888, .val = 0x1812FC00 },
         { .reg = 0x00009888, .val = 0x1A12002B },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x0813C000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x04136000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02144000 },
         { .reg = 0x00009888, .val = 0x00158000 },
         { .reg = 0x00009888, .val = 0x0E158000 },
         { .reg = 0x00009888, .val = 0x16152AD0 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x0615C000 },
         { .reg = 0x00009888, .val = 0x0815C000 },
         { .reg = 0x00009888, .val = 0x0A15C000 },
         { .reg = 0x00009888, .val = 0x0C15C000 },
         { .reg = 0x00009888, .val = 0x02188000 },
         { .reg = 0x00009888, .val = 0x0418A000 },
         { .reg = 0x00009888, .val = 0x06182000 },
         { .reg = 0x00009888, .val = 0x0A198000 },
         { .reg = 0x00009888, .val = 0x0C19A000 },
         { .reg = 0x00009888, .val = 0x0E192000 },
         { .reg = 0x00009888, .val = 0x0A1CA000 },
         { .reg = 0x00009888, .val = 0x0C1CA000 },
         { .reg = 0x00009888, .val = 0x121D5400 },
         { .reg = 0x00009888, .val = 0x141D0002 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4924 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x3E1F3000 },
         { .reg = 0x00009888, .val = 0x461F4030 },
         { .reg = 0x00009888, .val = 0x481F0040 },
         { .reg = 0x00009888, .val = 0x4A1F1000 },
         { .reg = 0x00009888, .val = 0x4C1F0010 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x401F1010 },
         { .reg = 0x00009888, .val = 0x421F3030 },
         { .reg = 0x00009888, .val = 0x441F4040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00000018 },
         { .reg = 0x00002774, .val = 0x0000FFFC },
         { .reg = 0x00002778, .val = 0x00000060 },
         { .reg = 0x0000277C, .val = 0x0000FFF3 },
         { .reg = 0x00002780, .val = 0x00000180 },
         { .reg = 0x00002784, .val = 0x0000FFCF },
         { .reg = 0x00002788, .val = 0x00000600 },
         { .reg = 0x0000278C, .val = 0x0000FF3F },
         { .reg = 0x00002790, .val = 0x00001800 },
         { .reg = 0x00002794, .val = 0x0000FCFF },
         { .reg = 0x00002798, .val = 0x00006000 },
         { .reg = 0x0000279C, .val = 0x0000F3FF },
         { .reg = 0x000027A0, .val = 0x00018000 },
         { .reg = 0x000027A4, .val = 0x0000CFFF },
         { .reg = 0x000027A8, .val = 0x00060000 },
         { .reg = 0x000027AC, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__sampler_1__avg_gpu_core_frequency__max,ehl__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__sampler_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__sampler_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__sampler_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__sampler_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__sampler_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__sampler_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__sampler_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__sampler_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__sampler_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,ehl__sampler_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,ehl__sampler_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,ehl__sampler_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,ehl__sampler_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,ehl__sampler_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,ehl__sampler_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,ehl__sampler_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,ehl__sampler_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,ehl__sampler_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,ehl__sampler_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,ehl__sampler_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,ehl__sampler_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,ehl__sampler_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,ehl__sampler_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,ehl__sampler_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,ehl__sampler_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,ehl__sampler_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, ehl__sampler_1__slm_bytes_read__max,ehl__sampler_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, ehl__sampler_1__slm_bytes_written__max,ehl__sampler_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,ehl__sampler_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,ehl__sampler_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, ehl__sampler_1__l3_shader_throughput__max,ehl__sampler_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,ehl__sampler_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 279, 240, percentage_max_float,ehl__sampler_1__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 277, 244, percentage_max_float,ehl__sampler_1__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 278, 248, percentage_max_float,ehl__sampler_1__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 372, 252, percentage_max_float,ehl__sampler_1__sampler03_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 373, 256, percentage_max_float,ehl__sampler_1__sampler04_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 374, 260, percentage_max_float,ehl__sampler_1__sampler05_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 375, 264, percentage_max_float,ehl__sampler_1__sampler06_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 376, 268, percentage_max_float,ehl__sampler_1__sampler07_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_sampler_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Metric set Sampler 2";
   query->symbol_name = "Sampler_2";
   query->guid = "5e64ae48-92a7-49b3-b7d8-af36b32ee866";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x142D0005 },
         { .reg = 0x00009888, .val = 0x14320005 },
         { .reg = 0x00009888, .val = 0x146D0005 },
         { .reg = 0x00009888, .val = 0x14720005 },
         { .reg = 0x00009888, .val = 0x14AD0005 },
         { .reg = 0x00009888, .val = 0x14B20005 },
         { .reg = 0x00009888, .val = 0x14ED0005 },
         { .reg = 0x00009888, .val = 0x14F20005 },
         { .reg = 0x00009888, .val = 0x1E1E0030 },
         { .reg = 0x00009888, .val = 0x1A204000 },
         { .reg = 0x00009888, .val = 0x1C200001 },
         { .reg = 0x00009888, .val = 0x1E213000 },
         { .reg = 0x00009888, .val = 0x1A2A00C0 },
         { .reg = 0x00009888, .val = 0x182C6000 },
         { .reg = 0x00009888, .val = 0x0E2D0033 },
         { .reg = 0x00009888, .val = 0x022D0000 },
         { .reg = 0x00009888, .val = 0x1A2F8000 },
         { .reg = 0x00009888, .val = 0x1C300008 },
         { .reg = 0x00009888, .val = 0x0E318000 },
         { .reg = 0x00009888, .val = 0x0E321980 },
         { .reg = 0x00009888, .val = 0x02320000 },
         { .reg = 0x00009888, .val = 0x125E8000 },
         { .reg = 0x00009888, .val = 0x145E8000 },
         { .reg = 0x00009888, .val = 0x02604000 },
         { .reg = 0x00009888, .val = 0x04604000 },
         { .reg = 0x00009888, .val = 0x12618000 },
         { .reg = 0x00009888, .val = 0x14618000 },
         { .reg = 0x00009888, .val = 0x046AC000 },
         { .reg = 0x00009888, .val = 0x026C8000 },
         { .reg = 0x00009888, .val = 0x046C4000 },
         { .reg = 0x00009888, .val = 0x006D1980 },
         { .reg = 0x00009888, .val = 0x026D0000 },
         { .reg = 0x00009888, .val = 0x046F8000 },
         { .reg = 0x00009888, .val = 0x14708000 },
         { .reg = 0x00009888, .val = 0x02714000 },
         { .reg = 0x00009888, .val = 0x02720033 },
         { .reg = 0x00009888, .val = 0x169E8000 },
         { .reg = 0x00009888, .val = 0x189E8000 },
         { .reg = 0x00009888, .val = 0x06A04000 },
         { .reg = 0x00009888, .val = 0x08A04000 },
         { .reg = 0x00009888, .val = 0x16A18000 },
         { .reg = 0x00009888, .val = 0x18A18000 },
         { .reg = 0x00009888, .val = 0x08AAC000 },
         { .reg = 0x00009888, .val = 0x06AC8000 },
         { .reg = 0x00009888, .val = 0x08AC4000 },
         { .reg = 0x00009888, .val = 0x02AD1980 },
         { .reg = 0x00009888, .val = 0x08AF8000 },
         { .reg = 0x00009888, .val = 0x18B04000 },
         { .reg = 0x00009888, .val = 0x04B14000 },
         { .reg = 0x00009888, .val = 0x04B20033 },
         { .reg = 0x00009888, .val = 0x02B20000 },
         { .reg = 0x00009888, .val = 0x1CDE1800 },
         { .reg = 0x00009888, .val = 0x0AE04000 },
         { .reg = 0x00009888, .val = 0x0CE04000 },
         { .reg = 0x00009888, .val = 0x1EE10018 },
         { .reg = 0x00009888, .val = 0x0CEAC000 },
         { .reg = 0x00009888, .val = 0x0AEC8000 },
         { .reg = 0x00009888, .val = 0x0CEC4000 },
         { .reg = 0x00009888, .val = 0x04ED1980 },
         { .reg = 0x00009888, .val = 0x02ED0000 },
         { .reg = 0x00009888, .val = 0x0CEF8000 },
         { .reg = 0x00009888, .val = 0x1AF00400 },
         { .reg = 0x00009888, .val = 0x06F14000 },
         { .reg = 0x00009888, .val = 0x06F20033 },
         { .reg = 0x00009888, .val = 0x02F20000 },
         { .reg = 0x00009888, .val = 0x10040140 },
         { .reg = 0x00009888, .val = 0x0C045000 },
         { .reg = 0x00009888, .val = 0x0E040055 },
         { .reg = 0x00009888, .val = 0x14050050 },
         { .reg = 0x00009888, .val = 0x04054000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x0A051000 },
         { .reg = 0x00009888, .val = 0x260600C0 },
         { .reg = 0x00009888, .val = 0x24067E00 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x06091000 },
         { .reg = 0x00009888, .val = 0x040D8000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x080E4000 },
         { .reg = 0x00009888, .val = 0x0A0E1000 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x0612C000 },
         { .reg = 0x00009888, .val = 0x0812C000 },
         { .reg = 0x00009888, .val = 0x0413E000 },
         { .reg = 0x00009888, .val = 0x06131000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x0214C000 },
         { .reg = 0x00009888, .val = 0x04144000 },
         { .reg = 0x00009888, .val = 0x1815000F },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08154000 },
         { .reg = 0x00009888, .val = 0x0A158000 },
         { .reg = 0x00009888, .val = 0x0C158000 },
         { .reg = 0x00009888, .val = 0x0E18A000 },
         { .reg = 0x00009888, .val = 0x14190028 },
         { .reg = 0x00009888, .val = 0x021C8000 },
         { .reg = 0x00009888, .val = 0x041C2000 },
         { .reg = 0x00009888, .val = 0x0A1D8000 },
         { .reg = 0x00009888, .val = 0x0C1D2000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3000 },
         { .reg = 0x00009888, .val = 0x2A1F0061 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x521F0000 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2430 },
         { .reg = 0x00009888, .val = 0x501F0124 },
         { .reg = 0x00009888, .val = 0x4C1F0137 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009888, .val = 0x401F0040 },
         { .reg = 0x00009888, .val = 0x421F0040 },
         { .reg = 0x00009888, .val = 0x441F3001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__sampler_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__sampler_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__sampler_2__avg_gpu_core_frequency__max,ehl__sampler_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__sampler_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__sampler_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__sampler_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__sampler_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__sampler_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__sampler_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__sampler_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__sampler_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__sampler_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,ehl__sampler_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,ehl__sampler_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,ehl__sampler_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,ehl__sampler_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,ehl__sampler_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,ehl__sampler_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,ehl__sampler_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,ehl__sampler_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,ehl__sampler_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,ehl__sampler_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,ehl__sampler_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,ehl__sampler_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,ehl__sampler_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,ehl__sampler_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,ehl__sampler_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,ehl__sampler_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,ehl__sampler_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, ehl__sampler_2__slm_bytes_read__max,ehl__sampler_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, ehl__sampler_2__slm_bytes_written__max,ehl__sampler_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,ehl__sampler_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,ehl__sampler_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, ehl__sampler_2__l3_shader_throughput__max,ehl__sampler_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,ehl__sampler_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 281, 240, percentage_max_float,ehl__sampler_2__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 282, 244, percentage_max_float,ehl__sampler_2__sampler01_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 280, 248, percentage_max_float,ehl__sampler_2__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 377, 252, percentage_max_float,ehl__sampler_2__sampler03_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 378, 256, percentage_max_float,ehl__sampler_2__sampler04_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 379, 260, percentage_max_float,ehl__sampler_2__sampler05_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 380, 264, percentage_max_float,ehl__sampler_2__sampler06_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 381, 268, percentage_max_float,ehl__sampler_2__sampler07_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 244, 272, percentage_max_float,ehl__sampler_2__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 51);

   query->name = "Metric set TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "d1725c84-80c6-4488-9867-82b44c88fea6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14290000 },
         { .reg = 0x00009888, .val = 0x142E0000 },
         { .reg = 0x00009888, .val = 0x14690000 },
         { .reg = 0x00009888, .val = 0x146E0000 },
         { .reg = 0x00009888, .val = 0x14A90000 },
         { .reg = 0x00009888, .val = 0x14AE0000 },
         { .reg = 0x00009888, .val = 0x14E90000 },
         { .reg = 0x00009888, .val = 0x14EE0000 },
         { .reg = 0x00009888, .val = 0x161E8000 },
         { .reg = 0x00009888, .val = 0x181E8000 },
         { .reg = 0x00009888, .val = 0x1C1E1800 },
         { .reg = 0x00009888, .val = 0x06204000 },
         { .reg = 0x00009888, .val = 0x08204000 },
         { .reg = 0x00009888, .val = 0x0A204000 },
         { .reg = 0x00009888, .val = 0x0C204000 },
         { .reg = 0x00009888, .val = 0x16218000 },
         { .reg = 0x00009888, .val = 0x18218000 },
         { .reg = 0x00009888, .val = 0x1E210018 },
         { .reg = 0x00009888, .val = 0x0429C300 },
         { .reg = 0x00009888, .val = 0x062900C5 },
         { .reg = 0x00009888, .val = 0x10290000 },
         { .reg = 0x00009888, .val = 0x062AC000 },
         { .reg = 0x00009888, .val = 0x082AC000 },
         { .reg = 0x00009888, .val = 0x0A2A4000 },
         { .reg = 0x00009888, .val = 0x0C2A4000 },
         { .reg = 0x00009888, .val = 0x062C4000 },
         { .reg = 0x00009888, .val = 0x082C4000 },
         { .reg = 0x00009888, .val = 0x0A2C4000 },
         { .reg = 0x00009888, .val = 0x0C2C4000 },
         { .reg = 0x00009888, .val = 0x022EC300 },
         { .reg = 0x00009888, .val = 0x042E00C5 },
         { .reg = 0x00009888, .val = 0x102E0000 },
         { .reg = 0x00009888, .val = 0x062F4000 },
         { .reg = 0x00009888, .val = 0x082F4000 },
         { .reg = 0x00009888, .val = 0x1E5E0030 },
         { .reg = 0x00009888, .val = 0x125E8000 },
         { .reg = 0x00009888, .val = 0x145E8000 },
         { .reg = 0x00009888, .val = 0x1A604000 },
         { .reg = 0x00009888, .val = 0x1C600001 },
         { .reg = 0x00009888, .val = 0x02604000 },
         { .reg = 0x00009888, .val = 0x04604000 },
         { .reg = 0x00009888, .val = 0x1E613000 },
         { .reg = 0x00009888, .val = 0x12618000 },
         { .reg = 0x00009888, .val = 0x14618000 },
         { .reg = 0x00009888, .val = 0x0069C300 },
         { .reg = 0x00009888, .val = 0x026900C5 },
         { .reg = 0x00009888, .val = 0x10690000 },
         { .reg = 0x00009888, .val = 0x1A6A00F0 },
         { .reg = 0x00009888, .val = 0x026A4000 },
         { .reg = 0x00009888, .val = 0x046A4000 },
         { .reg = 0x00009888, .val = 0x186C5000 },
         { .reg = 0x00009888, .val = 0x026C4000 },
         { .reg = 0x00009888, .val = 0x046C4000 },
         { .reg = 0x00009888, .val = 0x0E6EC5C3 },
         { .reg = 0x00009888, .val = 0x106E0000 },
         { .reg = 0x00009888, .val = 0x1A6F5000 },
         { .reg = 0x00009888, .val = 0x1E9E000F },
         { .reg = 0x00009888, .val = 0x1AA01540 },
         { .reg = 0x00009888, .val = 0x1EA10F00 },
         { .reg = 0x00009888, .val = 0x0CA9C5C3 },
         { .reg = 0x00009888, .val = 0x10A90000 },
         { .reg = 0x00009888, .val = 0x18AAF000 },
         { .reg = 0x00009888, .val = 0x1AAA0005 },
         { .reg = 0x00009888, .val = 0x18AC0550 },
         { .reg = 0x00009888, .val = 0x0AAEC5C3 },
         { .reg = 0x00009888, .val = 0x10AE0000 },
         { .reg = 0x00009888, .val = 0x1AAF0050 },
         { .reg = 0x00009888, .val = 0x10DE8000 },
         { .reg = 0x00009888, .val = 0x1CDEE000 },
         { .reg = 0x00009888, .val = 0x00E04000 },
         { .reg = 0x00009888, .val = 0x0EE04000 },
         { .reg = 0x00009888, .val = 0x18E04000 },
         { .reg = 0x00009888, .val = 0x1AE00010 },
         { .reg = 0x00009888, .val = 0x10E18000 },
         { .reg = 0x00009888, .val = 0x1EE100E0 },
         { .reg = 0x00009888, .val = 0x08E9C5C3 },
         { .reg = 0x00009888, .val = 0x10E90000 },
         { .reg = 0x00009888, .val = 0x00EAC000 },
         { .reg = 0x00009888, .val = 0x0EEAC000 },
         { .reg = 0x00009888, .val = 0x18EA0500 },
         { .reg = 0x00009888, .val = 0x00EC4000 },
         { .reg = 0x00009888, .val = 0x0EEC4000 },
         { .reg = 0x00009888, .val = 0x18EC0005 },
         { .reg = 0x00009888, .val = 0x00EE00C3 },
         { .reg = 0x00009888, .val = 0x06EEC500 },
         { .reg = 0x00009888, .val = 0x10EE0000 },
         { .reg = 0x00009888, .val = 0x00EF4000 },
         { .reg = 0x00009888, .val = 0x0EEF4000 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x0E045555 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x2406FF00 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x0E08A000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009888, .val = 0x14090050 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x06091000 },
         { .reg = 0x00009888, .val = 0x000D2000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DA000 },
         { .reg = 0x00009888, .val = 0x040E1000 },
         { .reg = 0x00009888, .val = 0x0A0E4000 },
         { .reg = 0x00009888, .val = 0x0C0E5000 },
         { .reg = 0x00009888, .val = 0x1812FC00 },
         { .reg = 0x00009888, .val = 0x1A12002B },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x0813C000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x04136000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02144000 },
         { .reg = 0x00009888, .val = 0x00158000 },
         { .reg = 0x00009888, .val = 0x0E158000 },
         { .reg = 0x00009888, .val = 0x16152AD0 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x0615C000 },
         { .reg = 0x00009888, .val = 0x0815C000 },
         { .reg = 0x00009888, .val = 0x0A15C000 },
         { .reg = 0x00009888, .val = 0x0C15C000 },
         { .reg = 0x00009888, .val = 0x02188000 },
         { .reg = 0x00009888, .val = 0x0418A000 },
         { .reg = 0x00009888, .val = 0x06182000 },
         { .reg = 0x00009888, .val = 0x0A198000 },
         { .reg = 0x00009888, .val = 0x0C19A000 },
         { .reg = 0x00009888, .val = 0x0E192000 },
         { .reg = 0x00009888, .val = 0x0A1CA000 },
         { .reg = 0x00009888, .val = 0x0C1CA000 },
         { .reg = 0x00009888, .val = 0x121D5400 },
         { .reg = 0x00009888, .val = 0x141D0002 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4924 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2400 },
         { .reg = 0x00009888, .val = 0x3E1F3000 },
         { .reg = 0x00009888, .val = 0x461F4030 },
         { .reg = 0x00009888, .val = 0x481F0040 },
         { .reg = 0x00009888, .val = 0x4A1F1000 },
         { .reg = 0x00009888, .val = 0x4C1F0010 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x401F1010 },
         { .reg = 0x00009888, .val = 0x421F3030 },
         { .reg = 0x00009888, .val = 0x441F4040 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00000018 },
         { .reg = 0x00002774, .val = 0x0000FFFC },
         { .reg = 0x00002778, .val = 0x00000060 },
         { .reg = 0x0000277C, .val = 0x0000FFF3 },
         { .reg = 0x00002780, .val = 0x00000180 },
         { .reg = 0x00002784, .val = 0x0000FFCF },
         { .reg = 0x00002788, .val = 0x00000600 },
         { .reg = 0x0000278C, .val = 0x0000FF3F },
         { .reg = 0x00002790, .val = 0x00001800 },
         { .reg = 0x00002794, .val = 0x0000FCFF },
         { .reg = 0x00002798, .val = 0x00006000 },
         { .reg = 0x0000279C, .val = 0x0000F3FF },
         { .reg = 0x000027A0, .val = 0x00018000 },
         { .reg = 0x000027A4, .val = 0x0000CFFF },
         { .reg = 0x000027A8, .val = 0x00060000 },
         { .reg = 0x000027AC, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E758, .val = 0x00015014 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
         { .reg = 0x0000E65C, .val = 0x00055054 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__tdl_1__avg_gpu_core_frequency__max,ehl__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,ehl__tdl_1__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,ehl__tdl_1__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,ehl__tdl_1__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,ehl__tdl_1__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 12, 104, percentage_max_float,ehl__tdl_1__vs_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 13, 112, NULL,ehl__tdl_1__vs_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 15, 120, percentage_max_float,ehl__tdl_1__vs_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 14, 128, NULL,ehl__tdl_1__vs_eu_stall_per_thread__read);

      intel_perf_query_add_counter_float(query, 127, 136, percentage_max_float,ehl__tdl_1__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 140, percentage_max_float,ehl__tdl_1__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 144, percentage_max_float,ehl__tdl_1__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 148, percentage_max_float,ehl__tdl_1__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_float(query, 32, 152, percentage_max_float,ehl__tdl_1__ps_eu_active__read);

      intel_perf_query_add_counter_uint64(query, 33, 160, NULL,ehl__tdl_1__ps_eu_active_per_thread__read);

      intel_perf_query_add_counter_float(query, 35, 168, percentage_max_float,ehl__tdl_1__ps_eu_stall__read);

      intel_perf_query_add_counter_uint64(query, 34, 176, NULL,ehl__tdl_1__ps_eu_stall_per_thread__read);

      intel_perf_query_add_counter_uint64(query, 139, 184, NULL,ehl__tdl_1__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 192, NULL,ehl__tdl_1__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 200, NULL,ehl__tdl_1__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 208, NULL,ehl__tdl_1__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 216, NULL,ehl__tdl_1__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 224, NULL,ehl__tdl_1__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 232, NULL,ehl__tdl_1__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 240, NULL,ehl__tdl_1__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 248, NULL,ehl__tdl_1__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 256, ehl__tdl_1__slm_bytes_read__max,ehl__tdl_1__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 264, ehl__tdl_1__slm_bytes_written__max,ehl__tdl_1__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 272, NULL,ehl__tdl_1__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 280, NULL,ehl__tdl_1__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 288, ehl__tdl_1__l3_shader_throughput__max,ehl__tdl_1__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 296, NULL,ehl__tdl_1__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 382, 304, percentage_max_float,ehl__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 383, 308, percentage_max_float,ehl__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 384, 312, percentage_max_float,ehl__tdl_1__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 385, 316, percentage_max_float,ehl__tdl_1__ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 386, 320, percentage_max_float,ehl__tdl_1__ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 387, 324, percentage_max_float,ehl__tdl_1__ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 388, 328, percentage_max_float,ehl__tdl_1__ps_thread06_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 389, 332, percentage_max_float,ehl__tdl_1__ps_thread07_ready_for_dispatch__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 44);

   query->name = "Metric set TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "47e27fcf-9904-4fc0-a661-636dffeafe7d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14290000 },
         { .reg = 0x00009888, .val = 0x142E0000 },
         { .reg = 0x00009888, .val = 0x14690000 },
         { .reg = 0x00009888, .val = 0x146E0000 },
         { .reg = 0x00009888, .val = 0x14A90000 },
         { .reg = 0x00009888, .val = 0x14AE0000 },
         { .reg = 0x00009888, .val = 0x14E90000 },
         { .reg = 0x00009888, .val = 0x14EE0000 },
         { .reg = 0x00009888, .val = 0x1E1E0018 },
         { .reg = 0x00009888, .val = 0x1A205000 },
         { .reg = 0x00009888, .val = 0x1E211800 },
         { .reg = 0x00009888, .val = 0x0C29C100 },
         { .reg = 0x00009888, .val = 0x10290000 },
         { .reg = 0x00009888, .val = 0x1A2A0034 },
         { .reg = 0x00009888, .val = 0x182C1400 },
         { .reg = 0x00009888, .val = 0x0E2E00C1 },
         { .reg = 0x00009888, .val = 0x102E0000 },
         { .reg = 0x00009888, .val = 0x1A2F1000 },
         { .reg = 0x00009888, .val = 0x1E5E0020 },
         { .reg = 0x00009888, .val = 0x125E8000 },
         { .reg = 0x00009888, .val = 0x1C600001 },
         { .reg = 0x00009888, .val = 0x02604000 },
         { .reg = 0x00009888, .val = 0x1E612000 },
         { .reg = 0x00009888, .val = 0x12618000 },
         { .reg = 0x00009888, .val = 0x0E69C100 },
         { .reg = 0x00009888, .val = 0x10690000 },
         { .reg = 0x00009888, .val = 0x1A6A0040 },
         { .reg = 0x00009888, .val = 0x026AC000 },
         { .reg = 0x00009888, .val = 0x186C4000 },
         { .reg = 0x00009888, .val = 0x026C4000 },
         { .reg = 0x00009888, .val = 0x006EC100 },
         { .reg = 0x00009888, .val = 0x106E0000 },
         { .reg = 0x00009888, .val = 0x026F4000 },
         { .reg = 0x00009888, .val = 0x149E8000 },
         { .reg = 0x00009888, .val = 0x169E8000 },
         { .reg = 0x00009888, .val = 0x04A04000 },
         { .reg = 0x00009888, .val = 0x06A04000 },
         { .reg = 0x00009888, .val = 0x14A18000 },
         { .reg = 0x00009888, .val = 0x16A18000 },
         { .reg = 0x00009888, .val = 0x02A900C1 },
         { .reg = 0x00009888, .val = 0x10A90000 },
         { .reg = 0x00009888, .val = 0x04AA4000 },
         { .reg = 0x00009888, .val = 0x06AAC000 },
         { .reg = 0x00009888, .val = 0x04AC4000 },
         { .reg = 0x00009888, .val = 0x06AC4000 },
         { .reg = 0x00009888, .val = 0x02AEC100 },
         { .reg = 0x00009888, .val = 0x10AE0000 },
         { .reg = 0x00009888, .val = 0x06AF4000 },
         { .reg = 0x00009888, .val = 0x18DE8000 },
         { .reg = 0x00009888, .val = 0x1CDE0800 },
         { .reg = 0x00009888, .val = 0x08E04000 },
         { .reg = 0x00009888, .val = 0x0AE04000 },
         { .reg = 0x00009888, .val = 0x18E18000 },
         { .reg = 0x00009888, .val = 0x1EE10008 },
         { .reg = 0x00009888, .val = 0x04E900C1 },
         { .reg = 0x00009888, .val = 0x10E90000 },
         { .reg = 0x00009888, .val = 0x08EA4000 },
         { .reg = 0x00009888, .val = 0x0AEAC000 },
         { .reg = 0x00009888, .val = 0x08EC4000 },
         { .reg = 0x00009888, .val = 0x0AEC4000 },
         { .reg = 0x00009888, .val = 0x04EEC100 },
         { .reg = 0x00009888, .val = 0x10EE0000 },
         { .reg = 0x00009888, .val = 0x0AEF4000 },
         { .reg = 0x00009888, .val = 0x10040150 },
         { .reg = 0x00009888, .val = 0x0C045000 },
         { .reg = 0x00009888, .val = 0x0E040015 },
         { .reg = 0x00009888, .val = 0x14050054 },
         { .reg = 0x00009888, .val = 0x04054000 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x260600E0 },
         { .reg = 0x00009888, .val = 0x24063E00 },
         { .reg = 0x00009888, .val = 0x0E088000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x14090040 },
         { .reg = 0x00009888, .val = 0x04094000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x080E5000 },
         { .reg = 0x00009888, .val = 0x1A120020 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x0412C000 },
         { .reg = 0x00009888, .val = 0x0612C000 },
         { .reg = 0x00009888, .val = 0x0A138000 },
         { .reg = 0x00009888, .val = 0x0413E000 },
         { .reg = 0x00009888, .val = 0x0E148000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x0214C000 },
         { .reg = 0x00009888, .val = 0x16156000 },
         { .reg = 0x00009888, .val = 0x18150007 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x06154000 },
         { .reg = 0x00009888, .val = 0x08158000 },
         { .reg = 0x00009888, .val = 0x0A158000 },
         { .reg = 0x00009888, .val = 0x0C188000 },
         { .reg = 0x00009888, .val = 0x0E182000 },
         { .reg = 0x00009888, .val = 0x1419000A },
         { .reg = 0x00009888, .val = 0x021CA000 },
         { .reg = 0x00009888, .val = 0x0A1DA000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x1C1F3061 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x521F4000 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2410 },
         { .reg = 0x00009888, .val = 0x501F0024 },
         { .reg = 0x00009888, .val = 0x4C1F3040 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009888, .val = 0x401F1000 },
         { .reg = 0x00009888, .val = 0x421F4000 },
         { .reg = 0x00009888, .val = 0x441F1730 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__tdl_2__avg_gpu_core_frequency__max,ehl__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,ehl__tdl_2__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,ehl__tdl_2__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,ehl__tdl_2__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,ehl__tdl_2__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,ehl__tdl_2__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,ehl__tdl_2__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,ehl__tdl_2__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,ehl__tdl_2__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,ehl__tdl_2__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,ehl__tdl_2__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,ehl__tdl_2__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,ehl__tdl_2__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,ehl__tdl_2__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,ehl__tdl_2__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,ehl__tdl_2__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,ehl__tdl_2__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,ehl__tdl_2__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, ehl__tdl_2__slm_bytes_read__max,ehl__tdl_2__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, ehl__tdl_2__slm_bytes_written__max,ehl__tdl_2__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,ehl__tdl_2__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,ehl__tdl_2__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, ehl__tdl_2__l3_shader_throughput__max,ehl__tdl_2__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,ehl__tdl_2__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 390, 240, percentage_max_float,ehl__tdl_2__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 391, 244, percentage_max_float,ehl__tdl_2__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 392, 248, percentage_max_float,ehl__tdl_2__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 393, 252, percentage_max_float,ehl__tdl_2__non_ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 394, 256, percentage_max_float,ehl__tdl_2__non_ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 395, 260, percentage_max_float,ehl__tdl_2__non_ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 396, 264, percentage_max_float,ehl__tdl_2__non_ps_thread06_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 397, 268, percentage_max_float,ehl__tdl_2__non_ps_thread07_ready_for_dispatch__read);
      }

      intel_perf_query_add_counter_float(query, 244, 272, percentage_max_float,ehl__tdl_2__gt_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_tdl_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 51);

   query->name = "Metric set TDL_3";
   query->symbol_name = "TDL_3";
   query->guid = "98154f5e-cf17-423c-a096-e696f87c2906";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14292C00 },
         { .reg = 0x00009888, .val = 0x16290013 },
         { .reg = 0x00009888, .val = 0x142E2C00 },
         { .reg = 0x00009888, .val = 0x162E0013 },
         { .reg = 0x00009888, .val = 0x14692C00 },
         { .reg = 0x00009888, .val = 0x16690013 },
         { .reg = 0x00009888, .val = 0x146E2C00 },
         { .reg = 0x00009888, .val = 0x166E0013 },
         { .reg = 0x00009888, .val = 0x14A92C00 },
         { .reg = 0x00009888, .val = 0x16A90013 },
         { .reg = 0x00009888, .val = 0x14AE2C00 },
         { .reg = 0x00009888, .val = 0x16AE0013 },
         { .reg = 0x00009888, .val = 0x14E92C00 },
         { .reg = 0x00009888, .val = 0x16E90013 },
         { .reg = 0x00009888, .val = 0x14EE2C00 },
         { .reg = 0x00009888, .val = 0x16EE0013 },
         { .reg = 0x00009888, .val = 0x101E8000 },
         { .reg = 0x00009888, .val = 0x1C1EE000 },
         { .reg = 0x00009888, .val = 0x00204000 },
         { .reg = 0x00009888, .val = 0x0E204000 },
         { .reg = 0x00009888, .val = 0x18204000 },
         { .reg = 0x00009888, .val = 0x1A200010 },
         { .reg = 0x00009888, .val = 0x10218000 },
         { .reg = 0x00009888, .val = 0x1E2100E0 },
         { .reg = 0x00009888, .val = 0x002900C7 },
         { .reg = 0x00009888, .val = 0x0629CF00 },
         { .reg = 0x00009888, .val = 0x10290000 },
         { .reg = 0x00009888, .val = 0x002A4000 },
         { .reg = 0x00009888, .val = 0x0E2A4000 },
         { .reg = 0x00009888, .val = 0x182A0F00 },
         { .reg = 0x00009888, .val = 0x002C4000 },
         { .reg = 0x00009888, .val = 0x0E2C4000 },
         { .reg = 0x00009888, .val = 0x182C0005 },
         { .reg = 0x00009888, .val = 0x082ECFC7 },
         { .reg = 0x00009888, .val = 0x102E0000 },
         { .reg = 0x00009888, .val = 0x1A2F0005 },
         { .reg = 0x00009888, .val = 0x1E5E000F },
         { .reg = 0x00009888, .val = 0x1A601540 },
         { .reg = 0x00009888, .val = 0x1E610F00 },
         { .reg = 0x00009888, .val = 0x0A69CFC7 },
         { .reg = 0x00009888, .val = 0x10690000 },
         { .reg = 0x00009888, .val = 0x186A5000 },
         { .reg = 0x00009888, .val = 0x1A6A000F },
         { .reg = 0x00009888, .val = 0x186C0550 },
         { .reg = 0x00009888, .val = 0x0C6ECFC7 },
         { .reg = 0x00009888, .val = 0x106E0000 },
         { .reg = 0x00009888, .val = 0x1A6F0500 },
         { .reg = 0x00009888, .val = 0x1E9E0030 },
         { .reg = 0x00009888, .val = 0x129E8000 },
         { .reg = 0x00009888, .val = 0x149E8000 },
         { .reg = 0x00009888, .val = 0x1AA04000 },
         { .reg = 0x00009888, .val = 0x1CA00001 },
         { .reg = 0x00009888, .val = 0x02A04000 },
         { .reg = 0x00009888, .val = 0x04A04000 },
         { .reg = 0x00009888, .val = 0x1EA13000 },
         { .reg = 0x00009888, .val = 0x12A18000 },
         { .reg = 0x00009888, .val = 0x14A18000 },
         { .reg = 0x00009888, .val = 0x0EA9CFC7 },
         { .reg = 0x00009888, .val = 0x10A90000 },
         { .reg = 0x00009888, .val = 0x1AAA0050 },
         { .reg = 0x00009888, .val = 0x02AAC000 },
         { .reg = 0x00009888, .val = 0x04AAC000 },
         { .reg = 0x00009888, .val = 0x18AC5000 },
         { .reg = 0x00009888, .val = 0x02AC4000 },
         { .reg = 0x00009888, .val = 0x04AC4000 },
         { .reg = 0x00009888, .val = 0x00AEC700 },
         { .reg = 0x00009888, .val = 0x02AE00CF },
         { .reg = 0x00009888, .val = 0x10AE0000 },
         { .reg = 0x00009888, .val = 0x02AF4000 },
         { .reg = 0x00009888, .val = 0x04AF4000 },
         { .reg = 0x00009888, .val = 0x16DE8000 },
         { .reg = 0x00009888, .val = 0x18DE8000 },
         { .reg = 0x00009888, .val = 0x1CDE1800 },
         { .reg = 0x00009888, .val = 0x06E04000 },
         { .reg = 0x00009888, .val = 0x08E04000 },
         { .reg = 0x00009888, .val = 0x0AE04000 },
         { .reg = 0x00009888, .val = 0x0CE04000 },
         { .reg = 0x00009888, .val = 0x16E18000 },
         { .reg = 0x00009888, .val = 0x18E18000 },
         { .reg = 0x00009888, .val = 0x1EE10018 },
         { .reg = 0x00009888, .val = 0x02E9C700 },
         { .reg = 0x00009888, .val = 0x04E900CF },
         { .reg = 0x00009888, .val = 0x10E90000 },
         { .reg = 0x00009888, .val = 0x06EA4000 },
         { .reg = 0x00009888, .val = 0x08EA4000 },
         { .reg = 0x00009888, .val = 0x0AEAC000 },
         { .reg = 0x00009888, .val = 0x0CEAC000 },
         { .reg = 0x00009888, .val = 0x06EC4000 },
         { .reg = 0x00009888, .val = 0x08EC4000 },
         { .reg = 0x00009888, .val = 0x0AEC4000 },
         { .reg = 0x00009888, .val = 0x0CEC4000 },
         { .reg = 0x00009888, .val = 0x04EEC700 },
         { .reg = 0x00009888, .val = 0x06EE00CF },
         { .reg = 0x00009888, .val = 0x10EE0000 },
         { .reg = 0x00009888, .val = 0x0AEF4000 },
         { .reg = 0x00009888, .val = 0x0CEF4000 },
         { .reg = 0x00009888, .val = 0x0C045400 },
         { .reg = 0x00009888, .val = 0x0E045555 },
         { .reg = 0x00009888, .val = 0x10040155 },
         { .reg = 0x00009888, .val = 0x04055000 },
         { .reg = 0x00009888, .val = 0x0A055000 },
         { .reg = 0x00009888, .val = 0x0C055000 },
         { .reg = 0x00009888, .val = 0x0E055000 },
         { .reg = 0x00009888, .val = 0x14050055 },
         { .reg = 0x00009888, .val = 0x06055000 },
         { .reg = 0x00009888, .val = 0x08055000 },
         { .reg = 0x00009888, .val = 0x2406FF00 },
         { .reg = 0x00009888, .val = 0x260600FF },
         { .reg = 0x00009888, .val = 0x0A08A000 },
         { .reg = 0x00009888, .val = 0x0C08A000 },
         { .reg = 0x00009888, .val = 0x0E095000 },
         { .reg = 0x00009888, .val = 0x14090005 },
         { .reg = 0x00009888, .val = 0x020D8000 },
         { .reg = 0x00009888, .val = 0x040DA000 },
         { .reg = 0x00009888, .val = 0x060D2000 },
         { .reg = 0x00009888, .val = 0x060E4000 },
         { .reg = 0x00009888, .val = 0x080E5000 },
         { .reg = 0x00009888, .val = 0x0A0E1000 },
         { .reg = 0x00009888, .val = 0x1812A800 },
         { .reg = 0x00009888, .val = 0x1A12003E },
         { .reg = 0x00009888, .val = 0x0212C000 },
         { .reg = 0x00009888, .val = 0x0412C000 },
         { .reg = 0x00009888, .val = 0x0813C000 },
         { .reg = 0x00009888, .val = 0x0A13F000 },
         { .reg = 0x00009888, .val = 0x04136000 },
         { .reg = 0x00009888, .val = 0x0A14C000 },
         { .reg = 0x00009888, .val = 0x0C14C000 },
         { .reg = 0x00009888, .val = 0x0E14C000 },
         { .reg = 0x00009888, .val = 0x00148000 },
         { .reg = 0x00009888, .val = 0x02144000 },
         { .reg = 0x00009888, .val = 0x0015C000 },
         { .reg = 0x00009888, .val = 0x0E15C000 },
         { .reg = 0x00009888, .val = 0x16152AF8 },
         { .reg = 0x00009888, .val = 0x18150005 },
         { .reg = 0x00009888, .val = 0x02154000 },
         { .reg = 0x00009888, .val = 0x04154000 },
         { .reg = 0x00009888, .val = 0x06158000 },
         { .reg = 0x00009888, .val = 0x08158000 },
         { .reg = 0x00009888, .val = 0x0A158000 },
         { .reg = 0x00009888, .val = 0x0C158000 },
         { .reg = 0x00009888, .val = 0x00182000 },
         { .reg = 0x00009888, .val = 0x06188000 },
         { .reg = 0x00009888, .val = 0x0818A000 },
         { .reg = 0x00009888, .val = 0x08192000 },
         { .reg = 0x00009888, .val = 0x0E198000 },
         { .reg = 0x00009888, .val = 0x12190140 },
         { .reg = 0x00009888, .val = 0x0E1CA000 },
         { .reg = 0x00009888, .val = 0x001C8000 },
         { .reg = 0x00009888, .val = 0x021C2000 },
         { .reg = 0x00009888, .val = 0x141D0028 },
         { .reg = 0x00009888, .val = 0x081D8000 },
         { .reg = 0x00009888, .val = 0x0A1D2000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x301F8000 },
         { .reg = 0x00009888, .val = 0x501F4924 },
         { .reg = 0x00009888, .val = 0x521F4924 },
         { .reg = 0x00009888, .val = 0x541F0024 },
         { .reg = 0x00009888, .val = 0x3A1F8000 },
         { .reg = 0x00009888, .val = 0x4E1F2410 },
         { .reg = 0x00009888, .val = 0x3E1F4000 },
         { .reg = 0x00009888, .val = 0x461F3040 },
         { .reg = 0x00009888, .val = 0x481F1030 },
         { .reg = 0x00009888, .val = 0x4A1F0010 },
         { .reg = 0x00009888, .val = 0x4C1F1000 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x401F0000 },
         { .reg = 0x00009888, .val = 0x421F4040 },
         { .reg = 0x00009888, .val = 0x441F3030 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x00800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00010003 },
         { .reg = 0x0000E658, .val = 0x00012011 },
         { .reg = 0x0000E45C, .val = 0x00051050 },
         { .reg = 0x0000E55C, .val = 0x00053052 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__tdl_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__tdl_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__tdl_3__avg_gpu_core_frequency__max,ehl__tdl_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__tdl_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,ehl__tdl_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,ehl__tdl_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,ehl__tdl_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,ehl__tdl_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,ehl__tdl_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,ehl__tdl_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,ehl__tdl_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,ehl__tdl_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 123, 88, percentage_max_float,ehl__tdl_3__eu_fpu_both_active__read);

      intel_perf_query_add_counter_float(query, 124, 92, percentage_max_float,ehl__tdl_3__vs_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 125, 96, percentage_max_float,ehl__tdl_3__vs_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 126, 100, percentage_max_float,ehl__tdl_3__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 127, 104, percentage_max_float,ehl__tdl_3__ps_fpu0_active__read);

      intel_perf_query_add_counter_float(query, 128, 108, percentage_max_float,ehl__tdl_3__ps_fpu1_active__read);

      intel_perf_query_add_counter_float(query, 129, 112, percentage_max_float,ehl__tdl_3__ps_send_active__read);

      intel_perf_query_add_counter_float(query, 130, 116, percentage_max_float,ehl__tdl_3__ps_eu_both_fpu_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,ehl__tdl_3__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,ehl__tdl_3__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,ehl__tdl_3__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,ehl__tdl_3__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,ehl__tdl_3__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,ehl__tdl_3__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,ehl__tdl_3__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,ehl__tdl_3__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,ehl__tdl_3__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 192, ehl__tdl_3__slm_bytes_read__max,ehl__tdl_3__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 200, ehl__tdl_3__slm_bytes_written__max,ehl__tdl_3__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,ehl__tdl_3__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,ehl__tdl_3__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 224, ehl__tdl_3__l3_shader_throughput__max,ehl__tdl_3__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 232, NULL,ehl__tdl_3__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 398, 240, percentage_max_float,ehl__tdl_3__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 399, 244, percentage_max_float,ehl__tdl_3__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 400, 248, percentage_max_float,ehl__tdl_3__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 401, 252, percentage_max_float,ehl__tdl_3__thread_header01_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 402, 256, percentage_max_float,ehl__tdl_3__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 403, 260, percentage_max_float,ehl__tdl_3__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 404, 264, percentage_max_float,ehl__tdl_3__thread_header03_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 405, 268, percentage_max_float,ehl__tdl_3__thread_header03_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 406, 272, percentage_max_float,ehl__tdl_3__thread_header04_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 407, 276, percentage_max_float,ehl__tdl_3__thread_header04_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 408, 280, percentage_max_float,ehl__tdl_3__thread_header05_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 409, 284, percentage_max_float,ehl__tdl_3__thread_header05_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 410, 288, percentage_max_float,ehl__tdl_3__thread_header06_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 64) {
         intel_perf_query_add_counter_float(query, 411, 292, percentage_max_float,ehl__tdl_3__thread_header06_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 412, 296, percentage_max_float,ehl__tdl_3__thread_header07_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 128) {
         intel_perf_query_add_counter_float(query, 413, 300, percentage_max_float,ehl__tdl_3__thread_header07_ready_port1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Gpu Rings Busyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "85254749-e937-4205-9b40-5df8847c9ee8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x12021200 },
         { .reg = 0x00009888, .val = 0x14040120 },
         { .reg = 0x00009888, .val = 0x10002400 },
         { .reg = 0x00009888, .val = 0x02020083 },
         { .reg = 0x00009888, .val = 0x10020000 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x06040043 },
         { .reg = 0x00009888, .val = 0x10040000 },
         { .reg = 0x00009888, .val = 0x1C040004 },
         { .reg = 0x00009888, .val = 0x02000023 },
         { .reg = 0x00009888, .val = 0x22000000 },
         { .reg = 0x00009888, .val = 0x14000000 },
         { .reg = 0x00009888, .val = 0x18008000 },
         { .reg = 0x00009888, .val = 0x04194000 },
         { .reg = 0x00009888, .val = 0x081A8000 },
         { .reg = 0x00009888, .val = 0x3A1F6000 },
         { .reg = 0x00009888, .val = 0x4E1F2900 },
         { .reg = 0x00009888, .val = 0x501F00E9 },
         { .reg = 0x00009888, .val = 0x04218000 },
         { .reg = 0x00009888, .val = 0x06212000 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x401F0160 },
         { .reg = 0x00009888, .val = 0x421F0050 },
         { .reg = 0x00009888, .val = 0x441F0100 },
         { .reg = 0x00009888, .val = 0x301F0000 },
         { .reg = 0x00009884, .val = 0x00000002 },
         { .reg = 0x00009888, .val = 0x181B2400 },
         { .reg = 0x00009888, .val = 0x185B2400 },
         { .reg = 0x00009888, .val = 0x14231200 },
         { .reg = 0x00009888, .val = 0x06218000 },
         { .reg = 0x00009888, .val = 0x08212000 },
         { .reg = 0x00009888, .val = 0x080D8000 },
         { .reg = 0x00009888, .val = 0x040F4000 },
         { .reg = 0x00009888, .val = 0x0828C000 },
         { .reg = 0x00009888, .val = 0x041B8300 },
         { .reg = 0x00009888, .val = 0x221B0000 },
         { .reg = 0x00009888, .val = 0x1A1B0000 },
         { .reg = 0x00009888, .val = 0x22162000 },
         { .reg = 0x00009888, .val = 0x084D4000 },
         { .reg = 0x00009888, .val = 0x044F1000 },
         { .reg = 0x00009888, .val = 0x08683000 },
         { .reg = 0x00009888, .val = 0x045B0083 },
         { .reg = 0x00009888, .val = 0x225B0000 },
         { .reg = 0x00009888, .val = 0x22560800 },
         { .reg = 0x00009888, .val = 0x06230093 },
         { .reg = 0x00009888, .val = 0x20230000 },
         { .reg = 0x00009888, .val = 0x0A238000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0x10800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0x00800000 },
         { .reg = 0x00002770, .val = 0x0007C000 },
         { .reg = 0x00002774, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__gpu_busyness__avg_gpu_core_frequency__max,ehl__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,ehl__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 309, 28, percentage_max_float,ehl__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 310, 32, percentage_max_float,ehl__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 36, percentage_max_float,ehl__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 312, 40, percentage_max_float,ehl__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 313, 44, percentage_max_float,ehl__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 314, 48, percentage_max_float,ehl__gpu_busyness__any_ring_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
ehl_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "4cbcfaf7-3c0c-42b8-a324-b1e58329c732";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x18130000 },
         { .reg = 0x00009888, .val = 0x22000004 },
         { .reg = 0x00009888, .val = 0x0E130076 },
         { .reg = 0x00009888, .val = 0x10130000 },
         { .reg = 0x00009888, .val = 0x1E130000 },
         { .reg = 0x00009888, .val = 0x0E164000 },
         { .reg = 0x00009888, .val = 0x1A1A0004 },
         { .reg = 0x00009888, .val = 0x541F0001 },
         { .reg = 0x00009888, .val = 0x141F0000 },
         { .reg = 0x00009888, .val = 0x4C1F0000 },
         { .reg = 0x00009888, .val = 0x301F0000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x00002740, .val = 0x00000000 },
         { .reg = 0x00002710, .val = 0x00000000 },
         { .reg = 0x00002714, .val = 0xF0800000 },
         { .reg = 0x00002720, .val = 0x00000000 },
         { .reg = 0x00002724, .val = 0xF0800000 },
         { .reg = 0x00002770, .val = 0x00000004 },
         { .reg = 0x00002774, .val = 0x0000FFFF },
         { .reg = 0x00002778, .val = 0x00000003 },
         { .reg = 0x0000277C, .val = 0x0000FFFF },
         { .reg = 0x00002780, .val = 0x00000007 },
         { .reg = 0x00002784, .val = 0x0000FFFF },
         { .reg = 0x00002788, .val = 0x00100002 },
         { .reg = 0x0000278C, .val = 0x0000FFF7 },
         { .reg = 0x00002790, .val = 0x00100002 },
         { .reg = 0x00002794, .val = 0x0000FFCF },
         { .reg = 0x00002798, .val = 0x00100082 },
         { .reg = 0x0000279C, .val = 0x0000FFEF },
         { .reg = 0x000027A0, .val = 0x001000C2 },
         { .reg = 0x000027A4, .val = 0x0000FFE7 },
         { .reg = 0x000027A8, .val = 0x00100001 },
         { .reg = 0x000027AC, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,ehl__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,ehl__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, ehl__test_oa__avg_gpu_core_frequency__max,ehl__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,ehl__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,ehl__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,ehl__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,ehl__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 415, 56, NULL,ehl__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 416, 64, NULL,ehl__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 417, 72, NULL,ehl__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 418, 80, NULL,ehl__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 323, 88, NULL,ehl__test_oa__counter8__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_ehl(struct intel_perf_config *perf)
{
   ehl_register_render_basic_counter_query(perf);
   ehl_register_compute_basic_counter_query(perf);
   ehl_register_compute_extended_counter_query(perf);
   ehl_register_compute_l3_cache_counter_query(perf);
   ehl_register_render_pipe_profile_counter_query(perf);
   ehl_register_hdc_and_sf_counter_query(perf);
   ehl_register_rasterizer_and_pixel_backend_counter_query(perf);
   ehl_register_l3_1_counter_query(perf);
   ehl_register_l3_2_counter_query(perf);
   ehl_register_l3_3_counter_query(perf);
   ehl_register_l3_4_counter_query(perf);
   ehl_register_l3_5_counter_query(perf);
   ehl_register_sampler_1_counter_query(perf);
   ehl_register_sampler_2_counter_query(perf);
   ehl_register_tdl_1_counter_query(perf);
   ehl_register_tdl_2_counter_query(perf);
   ehl_register_tdl_3_counter_query(perf);
   ehl_register_gpu_busyness_counter_query(perf);
   ehl_register_test_oa_counter_query(perf);
}


static void
tglgt1_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 34);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "c17af13d-3953-432b-9bd1-81346b4c2092";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14150001 },
         { .reg = 0x00009888, .val = 0x16150020 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0E124000 },
         { .reg = 0x00009888, .val = 0x10124000 },
         { .reg = 0x00009888, .val = 0x12124000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x1C130E00 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x06157000 },
         { .reg = 0x00009888, .val = 0x08157151 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x18150000 },
         { .reg = 0x00009888, .val = 0x1C150000 },
         { .reg = 0x00009888, .val = 0x0000C000 },
         { .reg = 0x00009888, .val = 0x0E00C000 },
         { .reg = 0x00009888, .val = 0x1000C000 },
         { .reg = 0x00009888, .val = 0x1200C000 },
         { .reg = 0x00009888, .val = 0x10058000 },
         { .reg = 0x00009888, .val = 0x1C058000 },
         { .reg = 0x00009888, .val = 0x22050030 },
         { .reg = 0x00009888, .val = 0x040A4000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0AC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D47 },
         { .reg = 0x00009888, .val = 0x09151536 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B1050BB },
         { .reg = 0x00009888, .val = 0x5D102C01 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x61110001 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x1F150137 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x0F168000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x1D350137 },
         { .reg = 0x00009888, .val = 0x03350147 },
         { .reg = 0x00009888, .val = 0x07350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x0F364000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55101710 },
         { .reg = 0x00009888, .val = 0x57100007 },
         { .reg = 0x00009888, .val = 0x49101717 },
         { .reg = 0x00009888, .val = 0x4B100717 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__render_basic__avg_gpu_core_frequency__max,tglgt1__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,tglgt1__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,tglgt1__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,tglgt1__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,tglgt1__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,tglgt1__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,tglgt1__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,tglgt1__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,tglgt1__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,tglgt1__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 84, percentage_max_float,tglgt1__render_basic__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 333, 88, percentage_max_float,tglgt1__render_basic__sampler00_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 435, 92, percentage_max_float,tglgt1__render_basic__sampler00_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 133, 96, percentage_max_float,tglgt1__render_basic__samplers_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 149, 100, percentage_max_float,tglgt1__render_basic__sampler_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 104, NULL,tglgt1__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 112, NULL,tglgt1__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 120, NULL,tglgt1__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 128, NULL,tglgt1__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 136, NULL,tglgt1__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 144, NULL,tglgt1__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 152, NULL,tglgt1__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 160, NULL,tglgt1__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 168, NULL,tglgt1__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 176, tglgt1__render_basic__slm_bytes_read__max,tglgt1__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 184, tglgt1__render_basic__slm_bytes_written__max,tglgt1__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 192, NULL,tglgt1__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 200, NULL,tglgt1__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 208, tglgt1__render_basic__l3_shader_throughput__max,tglgt1__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 216, NULL,tglgt1__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 224, tglgt1__render_basic__gti_read_throughput__max,tglgt1__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 232, tglgt1__render_basic__gti_write_throughput__max,tglgt1__render_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 30);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "79a0514e-40d7-437a-90cf-33e02857adc6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__compute_basic__avg_gpu_core_frequency__max,tglgt1__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,tglgt1__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,tglgt1__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,tglgt1__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,tglgt1__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,tglgt1__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,tglgt1__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,tglgt1__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,tglgt1__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,tglgt1__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, tglgt1__compute_basic__slm_bytes_read__max,tglgt1__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, tglgt1__compute_basic__slm_bytes_written__max,tglgt1__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,tglgt1__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,tglgt1__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, tglgt1__compute_basic__l3_shader_throughput__max,tglgt1__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,tglgt1__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 216, tglgt1__compute_basic__gti_read_throughput__max,tglgt1__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 224, tglgt1__compute_basic__gti_write_throughput__max,tglgt1__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "619eabea-0191-4d75-aaca-4217837215aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00123E00 },
         { .reg = 0x00009888, .val = 0x060B00B3 },
         { .reg = 0x00009888, .val = 0x140B3C00 },
         { .reg = 0x00009888, .val = 0x1C0B0000 },
         { .reg = 0x00009888, .val = 0x120C8320 },
         { .reg = 0x00009888, .val = 0x040D7E00 },
         { .reg = 0x00009888, .val = 0x280D0000 },
         { .reg = 0x00009888, .val = 0x2C0E001F },
         { .reg = 0x00009888, .val = 0x10087C00 },
         { .reg = 0x00009888, .val = 0x1E120002 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x1E130002 },
         { .reg = 0x00009888, .val = 0x0E0B0031 },
         { .reg = 0x00009888, .val = 0x180B0092 },
         { .reg = 0x00009888, .val = 0x1A0B00B1 },
         { .reg = 0x00009888, .val = 0x020B0093 },
         { .reg = 0x00009888, .val = 0x040B0033 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x0A0C0022 },
         { .reg = 0x00009888, .val = 0x1E0C00C2 },
         { .reg = 0x00009888, .val = 0x140C8000 },
         { .reg = 0x00009888, .val = 0x160C8000 },
         { .reg = 0x00009888, .val = 0x100D0017 },
         { .reg = 0x00009888, .val = 0x160D0013 },
         { .reg = 0x00009888, .val = 0x1C0D0081 },
         { .reg = 0x00009888, .val = 0x080D0082 },
         { .reg = 0x00009888, .val = 0x0A0D0102 },
         { .reg = 0x00009888, .val = 0x200D0000 },
         { .reg = 0x00009888, .val = 0x0E0D4000 },
         { .reg = 0x00009888, .val = 0x140D4000 },
         { .reg = 0x00009888, .val = 0x180D4000 },
         { .reg = 0x00009888, .val = 0x1A0D4000 },
         { .reg = 0x00009888, .val = 0x020D4000 },
         { .reg = 0x00009888, .val = 0x060D4000 },
         { .reg = 0x00009888, .val = 0x0C0E0225 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x0E0E8000 },
         { .reg = 0x00009888, .val = 0x100E8000 },
         { .reg = 0x00009888, .val = 0x140E8000 },
         { .reg = 0x00009888, .val = 0x160E8000 },
         { .reg = 0x00009888, .val = 0x180E8000 },
         { .reg = 0x00009888, .val = 0x1A0E8000 },
         { .reg = 0x00009888, .val = 0x1C0E8000 },
         { .reg = 0x00009888, .val = 0x020E8000 },
         { .reg = 0x00009888, .val = 0x040E8000 },
         { .reg = 0x00009888, .val = 0x060E8000 },
         { .reg = 0x00009888, .val = 0x080E8000 },
         { .reg = 0x00009888, .val = 0x0A0E8000 },
         { .reg = 0x00009888, .val = 0x0E0F4000 },
         { .reg = 0x00009888, .val = 0x100F4000 },
         { .reg = 0x00009888, .val = 0x140F4000 },
         { .reg = 0x00009888, .val = 0x160F4000 },
         { .reg = 0x00009888, .val = 0x180F4000 },
         { .reg = 0x00009888, .val = 0x1A0F4000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x020F4000 },
         { .reg = 0x00009888, .val = 0x040F4000 },
         { .reg = 0x00009888, .val = 0x060F4000 },
         { .reg = 0x00009888, .val = 0x080F4000 },
         { .reg = 0x00009888, .val = 0x0A0F4000 },
         { .reg = 0x00009888, .val = 0x0C0F4000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12008000 },
         { .reg = 0x00009888, .val = 0x34005540 },
         { .reg = 0x00009888, .val = 0x36000003 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x06004000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x0601C000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A01C000 },
         { .reg = 0x00009888, .val = 0x1801E000 },
         { .reg = 0x00009888, .val = 0x00018000 },
         { .reg = 0x00009888, .val = 0x0201C000 },
         { .reg = 0x00009888, .val = 0x0401C000 },
         { .reg = 0x00009888, .val = 0x22050800 },
         { .reg = 0x00009888, .val = 0x120A8000 },
         { .reg = 0x00009888, .val = 0x08081000 },
         { .reg = 0x00009888, .val = 0x16080000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x5F115555 },
         { .reg = 0x00009888, .val = 0x61111555 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x4D100604 },
         { .reg = 0x00009888, .val = 0x4F100400 },
         { .reg = 0x00009888, .val = 0x5110020A },
         { .reg = 0x00009888, .val = 0x53100004 },
         { .reg = 0x00009888, .val = 0x55100400 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100004 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100400 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__render_pipe_profile__avg_gpu_core_frequency__max,tglgt1__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__render_pipe_profile__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,tglgt1__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,tglgt1__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,tglgt1__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,tglgt1__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,tglgt1__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,tglgt1__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,tglgt1__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,tglgt1__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,tglgt1__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, tglgt1__render_pipe_profile__slm_bytes_read__max,tglgt1__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, tglgt1__render_pipe_profile__slm_bytes_written__max,tglgt1__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,tglgt1__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,tglgt1__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, tglgt1__render_pipe_profile__l3_shader_throughput__max,tglgt1__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,tglgt1__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 216, percentage_max_float,tglgt1__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 220, percentage_max_float,tglgt1__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 224, percentage_max_float,tglgt1__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 228, percentage_max_float,tglgt1__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 232, percentage_max_float,tglgt1__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 236, percentage_max_float,tglgt1__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 240, percentage_max_float,tglgt1__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 244, percentage_max_float,tglgt1__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 248, percentage_max_float,tglgt1__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 252, percentage_max_float,tglgt1__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 256, percentage_max_float,tglgt1__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 260, percentage_max_float,tglgt1__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 264, percentage_max_float,tglgt1__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 268, percentage_max_float,tglgt1__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 272, percentage_max_float,tglgt1__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 31);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "b1560378-cb32-4d4b-af30-ffeb163655e6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14112400 },
         { .reg = 0x00009888, .val = 0x14312400 },
         { .reg = 0x00009888, .val = 0x240A0019 },
         { .reg = 0x00009888, .val = 0x00110074 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x00128000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x0E310074 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x06310000 },
         { .reg = 0x00009888, .val = 0x0E328000 },
         { .reg = 0x00009888, .val = 0x1C330200 },
         { .reg = 0x00009888, .val = 0x0E0D8000 },
         { .reg = 0x00009888, .val = 0x0E0E8000 },
         { .reg = 0x00009888, .val = 0x0E0F4000 },
         { .reg = 0x00009888, .val = 0x0000C000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x1000C000 },
         { .reg = 0x00009888, .val = 0x06018000 },
         { .reg = 0x00009888, .val = 0x10058000 },
         { .reg = 0x00009888, .val = 0x100A00F7 },
         { .reg = 0x00009888, .val = 0x140A0000 },
         { .reg = 0x00009888, .val = 0x040A4000 },
         { .reg = 0x00009888, .val = 0x0C0A0000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105000 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B146000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x47100400 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100110 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00070000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000DC00, .val = 0x00000002 },
         { .reg = 0x0000DC04, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000DC08, .val = 0x00000002 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000DC10, .val = 0x00000002 },
         { .reg = 0x0000DC14, .val = 0x0000FFFB },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__hdc_and_sf__avg_gpu_core_frequency__max,tglgt1__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__hdc_and_sf__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,tglgt1__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,tglgt1__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,tglgt1__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,tglgt1__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,tglgt1__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,tglgt1__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,tglgt1__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,tglgt1__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,tglgt1__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, tglgt1__hdc_and_sf__slm_bytes_read__max,tglgt1__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, tglgt1__hdc_and_sf__slm_bytes_written__max,tglgt1__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,tglgt1__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,tglgt1__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, tglgt1__hdc_and_sf__l3_shader_throughput__max,tglgt1__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,tglgt1__hdc_and_sf__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 356, 216, percentage_max_float,tglgt1__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 357, 220, percentage_max_float,tglgt1__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      intel_perf_query_add_counter_float(query, 237, 224, percentage_max_float,tglgt1__hdc_and_sf__poly_data_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 37);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "36e7fc09-3fb7-4b46-a6ff-ba1ce767db7c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1E055000 },
         { .reg = 0x00009888, .val = 0x1A0500C0 },
         { .reg = 0x00009888, .val = 0x2A0A7300 },
         { .reg = 0x00009888, .val = 0x2C0A0000 },
         { .reg = 0x00009888, .val = 0x120800A0 },
         { .reg = 0x00009888, .val = 0x0000C000 },
         { .reg = 0x00009888, .val = 0x0E00C000 },
         { .reg = 0x00009888, .val = 0x1000C000 },
         { .reg = 0x00009888, .val = 0x12008000 },
         { .reg = 0x00009888, .val = 0x34000080 },
         { .reg = 0x00009888, .val = 0x0800C000 },
         { .reg = 0x00009888, .val = 0x0A00C000 },
         { .reg = 0x00009888, .val = 0x0C00C000 },
         { .reg = 0x00009888, .val = 0x04052700 },
         { .reg = 0x00009888, .val = 0x060500C0 },
         { .reg = 0x00009888, .val = 0x22050000 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x000A0144 },
         { .reg = 0x00009888, .val = 0x0E0A0145 },
         { .reg = 0x00009888, .val = 0x100A0156 },
         { .reg = 0x00009888, .val = 0x080A814F },
         { .reg = 0x00009888, .val = 0x140A0000 },
         { .reg = 0x00009888, .val = 0x040A0000 },
         { .reg = 0x00009888, .val = 0x0A0A4000 },
         { .reg = 0x00009888, .val = 0x0C0A0000 },
         { .reg = 0x00009888, .val = 0x08081980 },
         { .reg = 0x00009888, .val = 0x0A080032 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x16080000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x31152800 },
         { .reg = 0x00009888, .val = 0x331500A0 },
         { .reg = 0x00009888, .val = 0x31352800 },
         { .reg = 0x00009888, .val = 0x333500A0 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B10556B },
         { .reg = 0x00009888, .val = 0x5D103005 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D140001 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115540 },
         { .reg = 0x00009888, .val = 0x61110005 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x05150096 },
         { .reg = 0x00009888, .val = 0x07150016 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x0316C000 },
         { .reg = 0x00009888, .val = 0x1F350096 },
         { .reg = 0x00009888, .val = 0x03350016 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x0F368000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x47101200 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100202 },
         { .reg = 0x00009888, .val = 0x51100202 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55101000 },
         { .reg = 0x00009888, .val = 0x57100001 },
         { .reg = 0x00009888, .val = 0x49101111 },
         { .reg = 0x00009888, .val = 0x4B100201 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000DC00, .val = 0x00000038 },
         { .reg = 0x0000DC04, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000DC08, .val = 0x000000C0 },
         { .reg = 0x0000DC0C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,tglgt1__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,tglgt1__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,tglgt1__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,tglgt1__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,tglgt1__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,tglgt1__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,tglgt1__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,tglgt1__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,tglgt1__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,tglgt1__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, tglgt1__rasterizer_and_pixel_backend__slm_bytes_read__max,tglgt1__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, tglgt1__rasterizer_and_pixel_backend__slm_bytes_written__max,tglgt1__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,tglgt1__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,tglgt1__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, tglgt1__rasterizer_and_pixel_backend__l3_shader_throughput__max,tglgt1__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,tglgt1__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 266, 216, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 261, 220, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 360, 224, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 362, 228, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 364, 232, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__pixel_values00_ready__read);

      intel_perf_query_add_counter_float(query, 436, 236, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__gt_request_queue00_full__read);

      intel_perf_query_add_counter_float(query, 437, 240, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__gt_request_queue01_full__read);

      intel_perf_query_add_counter_float(query, 438, 244, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__gt_request_queue10_full__read);

      intel_perf_query_add_counter_float(query, 439, 248, percentage_max_float,tglgt1__rasterizer_and_pixel_backend__gt_request_queue11_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_1";
   query->symbol_name = "L3_1";
   query->guid = "4a46a4ee-437d-4726-ac61-31e47072f706";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04002024 },
         { .reg = 0x00009888, .val = 0x0600282F },
         { .reg = 0x00009888, .val = 0x1C000027 },
         { .reg = 0x00009888, .val = 0x1E000026 },
         { .reg = 0x00009888, .val = 0x02000025 },
         { .reg = 0x00009888, .val = 0x0800002E },
         { .reg = 0x00009888, .val = 0x0A00002D },
         { .reg = 0x00009888, .val = 0x0C00002C },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009888, .val = 0x34000000 },
         { .reg = 0x00009888, .val = 0x36000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100555 },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x5F110555 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__l3_1__avg_gpu_core_frequency__max,tglgt1__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,tglgt1__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,tglgt1__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,tglgt1__l3_1__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,tglgt1__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,tglgt1__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,tglgt1__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,tglgt1__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,tglgt1__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,tglgt1__l3_1__cs_threads__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 440, 88, percentage_max_float,tglgt1__l3_1__l30_bank0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 441, 92, percentage_max_float,tglgt1__l3_1__l30_bank1_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_2";
   query->symbol_name = "L3_2";
   query->guid = "2456d8be-5c99-430c-8172-8294fdc39331";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04003000 },
         { .reg = 0x00009888, .val = 0x06003800 },
         { .reg = 0x00009888, .val = 0x00000024 },
         { .reg = 0x00009888, .val = 0x0E000025 },
         { .reg = 0x00009888, .val = 0x10000026 },
         { .reg = 0x00009888, .val = 0x12000027 },
         { .reg = 0x00009888, .val = 0x1400002C },
         { .reg = 0x00009888, .val = 0x1600002D },
         { .reg = 0x00009888, .val = 0x1800002E },
         { .reg = 0x00009888, .val = 0x1A00002F },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009888, .val = 0x34000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105000 },
         { .reg = 0x00009888, .val = 0x5D100155 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x1D14000F },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x61110155 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x53100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__l3_2__avg_gpu_core_frequency__max,tglgt1__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__l3_2__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 442, 92, percentage_max_float,tglgt1__l3_2__l30_bank2_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 443, 96, percentage_max_float,tglgt1__l3_2__l30_bank3_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "L3_3";
   query->symbol_name = "L3_3";
   query->guid = "71e2a606-810c-4252-bf7e-16fed118f4b5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04000200 },
         { .reg = 0x00009888, .val = 0x06000000 },
         { .reg = 0x00009888, .val = 0x0A000020 },
         { .reg = 0x00009888, .val = 0x0C000028 },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100500 },
         { .reg = 0x00009888, .val = 0x1B141800 },
         { .reg = 0x00009888, .val = 0x5F110500 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__l3_3__avg_gpu_core_frequency__max,tglgt1__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__l3_3__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 444, 92, percentage_max_float,tglgt1__l3_3__l30_bank0_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_l3_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "L3_4";
   query->symbol_name = "L3_4";
   query->guid = "327a91a5-f93c-449d-b5e1-ab92cb1180a1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04000A00 },
         { .reg = 0x00009888, .val = 0x06000820 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100050 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B140400 },
         { .reg = 0x00009888, .val = 0x5F110050 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__l3_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__l3_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__l3_4__avg_gpu_core_frequency__max,tglgt1__l3_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__l3_4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__l3_4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__l3_4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__l3_4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__l3_4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__l3_4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__l3_4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__l3_4__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__l3_4__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__l3_4__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 445, 92, percentage_max_float,tglgt1__l3_4__l30_bank1_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_l3_5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "L3_5";
   query->symbol_name = "L3_5";
   query->guid = "a8de84ca-1624-4e0c-8046-d5265566c15b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04001200 },
         { .reg = 0x00009888, .val = 0x06001020 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100050 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B140400 },
         { .reg = 0x00009888, .val = 0x5F110050 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__l3_5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__l3_5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__l3_5__avg_gpu_core_frequency__max,tglgt1__l3_5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__l3_5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__l3_5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__l3_5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__l3_5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__l3_5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__l3_5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__l3_5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__l3_5__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__l3_5__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__l3_5__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 446, 92, percentage_max_float,tglgt1__l3_5__l30_bank2_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_l3_6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "L3_6";
   query->symbol_name = "L3_6";
   query->guid = "6f376729-c56a-4560-a0eb-f4a17ec6df84";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04001A00 },
         { .reg = 0x00009888, .val = 0x06001820 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100050 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B140400 },
         { .reg = 0x00009888, .val = 0x5F110050 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__l3_6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__l3_6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__l3_6__avg_gpu_core_frequency__max,tglgt1__l3_6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__l3_6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__l3_6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__l3_6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__l3_6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__l3_6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__l3_6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__l3_6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__l3_6__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__l3_6__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__l3_6__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 447, 92, percentage_max_float,tglgt1__l3_6__l30_bank3_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "Sampler_1";
   query->symbol_name = "Sampler_1";
   query->guid = "4876283b-1889-4cef-880f-58de9dc676cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C123E00 },
         { .reg = 0x00009888, .val = 0x1C121600 },
         { .reg = 0x00009888, .val = 0x04143E00 },
         { .reg = 0x00009888, .val = 0x18141613 },
         { .reg = 0x00009888, .val = 0x0C323E00 },
         { .reg = 0x00009888, .val = 0x1C321600 },
         { .reg = 0x00009888, .val = 0x04343E00 },
         { .reg = 0x00009888, .val = 0x18341600 },
         { .reg = 0x00009888, .val = 0x0E120086 },
         { .reg = 0x00009888, .val = 0x1A120033 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x18124000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x1C13C200 },
         { .reg = 0x00009888, .val = 0x001400A6 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x0C140000 },
         { .reg = 0x00009888, .val = 0x18158000 },
         { .reg = 0x00009888, .val = 0x1C150800 },
         { .reg = 0x00009888, .val = 0x12320086 },
         { .reg = 0x00009888, .val = 0x16320033 },
         { .reg = 0x00009888, .val = 0x20320000 },
         { .reg = 0x00009888, .val = 0x10324000 },
         { .reg = 0x00009888, .val = 0x14324000 },
         { .reg = 0x00009888, .val = 0x1C333C00 },
         { .reg = 0x00009888, .val = 0x103400A6 },
         { .reg = 0x00009888, .val = 0x14340013 },
         { .reg = 0x00009888, .val = 0x08340000 },
         { .reg = 0x00009888, .val = 0x0A340000 },
         { .reg = 0x00009888, .val = 0x1C350088 },
         { .reg = 0x00009888, .val = 0x100D8000 },
         { .reg = 0x00009888, .val = 0x120D8000 },
         { .reg = 0x00009888, .val = 0x140D8000 },
         { .reg = 0x00009888, .val = 0x160D8000 },
         { .reg = 0x00009888, .val = 0x100E8000 },
         { .reg = 0x00009888, .val = 0x120E8000 },
         { .reg = 0x00009888, .val = 0x140E8000 },
         { .reg = 0x00009888, .val = 0x160E8000 },
         { .reg = 0x00009888, .val = 0x100F4000 },
         { .reg = 0x00009888, .val = 0x120F4000 },
         { .reg = 0x00009888, .val = 0x140F4000 },
         { .reg = 0x00009888, .val = 0x160F4000 },
         { .reg = 0x00009888, .val = 0x0000C000 },
         { .reg = 0x00009888, .val = 0x0E00C000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x34003D40 },
         { .reg = 0x00009888, .val = 0x0801C000 },
         { .reg = 0x00009888, .val = 0x0A01C000 },
         { .reg = 0x00009888, .val = 0x10058000 },
         { .reg = 0x00009888, .val = 0x1C058000 },
         { .reg = 0x00009888, .val = 0x22050300 },
         { .reg = 0x00009888, .val = 0x040A4000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x100AC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105000 },
         { .reg = 0x00009888, .val = 0x5D100155 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x1D14000F },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x61110155 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x47100400 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100008 },
         { .reg = 0x00009888, .val = 0x51100004 },
         { .reg = 0x00009888, .val = 0x53100404 },
         { .reg = 0x00009888, .val = 0x55100008 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x000F0000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000180 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000600 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__sampler_1__avg_gpu_core_frequency__max,tglgt1__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__sampler_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__sampler_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__sampler_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__sampler_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__sampler_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__sampler_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__sampler_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__sampler_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__sampler_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__sampler_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 448, 92, percentage_max_float,tglgt1__sampler_1__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 449, 96, percentage_max_float,tglgt1__sampler_1__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 450, 100, percentage_max_float,tglgt1__sampler_1__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 451, 104, percentage_max_float,tglgt1__sampler_1__sampler01_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "aeddd71b-2f93-48de-9e69-1cba5865473f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x24110340 },
         { .reg = 0x00009888, .val = 0x2611001C },
         { .reg = 0x00009888, .val = 0x24310340 },
         { .reg = 0x00009888, .val = 0x2631001C },
         { .reg = 0x00009888, .val = 0x001100F3 },
         { .reg = 0x00009888, .val = 0x0E1100F2 },
         { .reg = 0x00009888, .val = 0x16110103 },
         { .reg = 0x00009888, .val = 0x06110107 },
         { .reg = 0x00009888, .val = 0x08110106 },
         { .reg = 0x00009888, .val = 0x0A110105 },
         { .reg = 0x00009888, .val = 0x0C110104 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x02110000 },
         { .reg = 0x00009888, .val = 0x04110000 },
         { .reg = 0x00009888, .val = 0x00128000 },
         { .reg = 0x00009888, .val = 0x0E128000 },
         { .reg = 0x00009888, .val = 0x16128000 },
         { .reg = 0x00009888, .val = 0x06128000 },
         { .reg = 0x00009888, .val = 0x08128000 },
         { .reg = 0x00009888, .val = 0x0A128000 },
         { .reg = 0x00009888, .val = 0x0C128000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x1C132300 },
         { .reg = 0x00009888, .val = 0x16138000 },
         { .reg = 0x00009888, .val = 0x18138000 },
         { .reg = 0x00009888, .val = 0x1A138000 },
         { .reg = 0x00009888, .val = 0x103100F3 },
         { .reg = 0x00009888, .val = 0x123100F2 },
         { .reg = 0x00009888, .val = 0x14310103 },
         { .reg = 0x00009888, .val = 0x1C310107 },
         { .reg = 0x00009888, .val = 0x1E310106 },
         { .reg = 0x00009888, .val = 0x02310105 },
         { .reg = 0x00009888, .val = 0x04310104 },
         { .reg = 0x00009888, .val = 0x08310000 },
         { .reg = 0x00009888, .val = 0x0A310000 },
         { .reg = 0x00009888, .val = 0x0E310000 },
         { .reg = 0x00009888, .val = 0x00310000 },
         { .reg = 0x00009888, .val = 0x10328000 },
         { .reg = 0x00009888, .val = 0x12328000 },
         { .reg = 0x00009888, .val = 0x14328000 },
         { .reg = 0x00009888, .val = 0x1C328000 },
         { .reg = 0x00009888, .val = 0x1E328000 },
         { .reg = 0x00009888, .val = 0x02328000 },
         { .reg = 0x00009888, .val = 0x04328000 },
         { .reg = 0x00009888, .val = 0x1C331C00 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x12338000 },
         { .reg = 0x00009888, .val = 0x14338000 },
         { .reg = 0x00009888, .val = 0x100D8000 },
         { .reg = 0x00009888, .val = 0x120D8000 },
         { .reg = 0x00009888, .val = 0x140D8000 },
         { .reg = 0x00009888, .val = 0x1C0D8000 },
         { .reg = 0x00009888, .val = 0x1E0D8000 },
         { .reg = 0x00009888, .val = 0x020D8000 },
         { .reg = 0x00009888, .val = 0x040D8000 },
         { .reg = 0x00009888, .val = 0x100E8000 },
         { .reg = 0x00009888, .val = 0x120E8000 },
         { .reg = 0x00009888, .val = 0x140E8000 },
         { .reg = 0x00009888, .val = 0x1C0E8000 },
         { .reg = 0x00009888, .val = 0x1E0E8000 },
         { .reg = 0x00009888, .val = 0x020E8000 },
         { .reg = 0x00009888, .val = 0x040E8000 },
         { .reg = 0x00009888, .val = 0x100F4000 },
         { .reg = 0x00009888, .val = 0x120F4000 },
         { .reg = 0x00009888, .val = 0x140F4000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x1E0F4000 },
         { .reg = 0x00009888, .val = 0x020F4000 },
         { .reg = 0x00009888, .val = 0x040F4000 },
         { .reg = 0x00009888, .val = 0x0000C000 },
         { .reg = 0x00009888, .val = 0x0E00C000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x34004340 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x0600C000 },
         { .reg = 0x00009888, .val = 0x0800C000 },
         { .reg = 0x00009888, .val = 0x0A00C000 },
         { .reg = 0x00009888, .val = 0x0C00C000 },
         { .reg = 0x00009888, .val = 0x0801C000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18018000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x00018000 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x10058000 },
         { .reg = 0x00009888, .val = 0x1C05C000 },
         { .reg = 0x00009888, .val = 0x22050080 },
         { .reg = 0x00009888, .val = 0x16058000 },
         { .reg = 0x00009888, .val = 0x18058000 },
         { .reg = 0x00009888, .val = 0x1A058000 },
         { .reg = 0x00009888, .val = 0x040A4000 },
         { .reg = 0x00009888, .val = 0x0A0AC000 },
         { .reg = 0x00009888, .val = 0x0E0A8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080AC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101415 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D140033 },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115555 },
         { .reg = 0x00009888, .val = 0x61111415 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x47100400 },
         { .reg = 0x00009888, .val = 0x4D100404 },
         { .reg = 0x00009888, .val = 0x4F100004 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x53100004 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100404 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000DC40, .val = 0x003F0000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000000 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000000 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFEF },
         { .reg = 0x0000DC10, .val = 0x00000002 },
         { .reg = 0x0000DC14, .val = 0x0000FFEF },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFDF },
         { .reg = 0x0000DC18, .val = 0x00000002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFDF },
         { .reg = 0x0000D960, .val = 0x00078000 },
         { .reg = 0x0000D964, .val = 0x00000FFF },
         { .reg = 0x0000DC20, .val = 0x00078000 },
         { .reg = 0x0000DC24, .val = 0x00000FFF },
         { .reg = 0x0000D968, .val = 0x00007800 },
         { .reg = 0x0000D96C, .val = 0x0000F0FF },
         { .reg = 0x0000DC28, .val = 0x00007800 },
         { .reg = 0x0000DC2C, .val = 0x0000F0FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__tdl_1__avg_gpu_core_frequency__max,tglgt1__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt1__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt1__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt1__tdl_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 452, 92, percentage_max_float,tglgt1__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 453, 96, percentage_max_float,tglgt1__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 454, 100, percentage_max_float,tglgt1__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 455, 104, percentage_max_float,tglgt1__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 456, 108, percentage_max_float,tglgt1__tdl_1__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 457, 112, percentage_max_float,tglgt1__tdl_1__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 458, 116, percentage_max_float,tglgt1__tdl_1__thread_header00_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 459, 120, percentage_max_float,tglgt1__tdl_1__thread_header00_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 460, 124, percentage_max_float,tglgt1__tdl_1__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 461, 128, percentage_max_float,tglgt1__tdl_1__thread_header01_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 462, 132, percentage_max_float,tglgt1__tdl_1__thread_header01_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 463, 136, percentage_max_float,tglgt1__tdl_1__thread_header01_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 464, 140, percentage_max_float,tglgt1__tdl_1__thread_header00_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 465, 144, percentage_max_float,tglgt1__tdl_1__thread_header01_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 22);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "a4089c3f-a697-4213-a58b-70e150969226";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x040E0043 },
         { .reg = 0x00009888, .val = 0x0A0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x080F00A3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x040F4000 },
         { .reg = 0x00009888, .val = 0x0A0F4000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x0401C000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x15102400 },
         { .reg = 0x00009888, .val = 0x230B0120 },
         { .reg = 0x00009888, .val = 0x15182400 },
         { .reg = 0x00009888, .val = 0x232B0120 },
         { .reg = 0x00009888, .val = 0x17100023 },
         { .reg = 0x00009888, .val = 0x11100000 },
         { .reg = 0x00009888, .val = 0x5D101000 },
         { .reg = 0x00009888, .val = 0x5B100545 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x1B140C00 },
         { .reg = 0x00009888, .val = 0x61112000 },
         { .reg = 0x00009888, .val = 0x5F110945 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x13138000 },
         { .reg = 0x00009888, .val = 0x1B0D0040 },
         { .reg = 0x00009888, .val = 0x1F0B00D3 },
         { .reg = 0x00009888, .val = 0x190B0000 },
         { .reg = 0x00009888, .val = 0x170B0000 },
         { .reg = 0x00009888, .val = 0x1B170002 },
         { .reg = 0x00009888, .val = 0x0D174000 },
         { .reg = 0x00009888, .val = 0x071800A3 },
         { .reg = 0x00009888, .val = 0x11180000 },
         { .reg = 0x00009888, .val = 0x032D4000 },
         { .reg = 0x00009888, .val = 0x032B00D3 },
         { .reg = 0x00009888, .val = 0x192B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100009 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49101005 },
         { .reg = 0x00009888, .val = 0x4B100207 },
         { .reg = 0x00009888, .val = 0x4D100010 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00024002 },
         { .reg = 0x0000D944, .val = 0x0000B7FF },
         { .reg = 0x0000DC00, .val = 0x00024002 },
         { .reg = 0x0000DC04, .val = 0x0000B7FF },
         { .reg = 0x0000D948, .val = 0x0007F000 },
         { .reg = 0x0000D94C, .val = 0x000001FF },
         { .reg = 0x0000DC08, .val = 0x0007F000 },
         { .reg = 0x0000DC0C, .val = 0x000001FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__gpu_busyness__avg_gpu_core_frequency__max,tglgt1__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,tglgt1__gpu_busyness__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,tglgt1__gpu_busyness__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,tglgt1__gpu_busyness__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,tglgt1__gpu_busyness__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,tglgt1__gpu_busyness__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,tglgt1__gpu_busyness__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,tglgt1__gpu_busyness__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,tglgt1__gpu_busyness__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,tglgt1__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 88, percentage_max_float,tglgt1__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 92, percentage_max_float,tglgt1__gpu_busyness__compute_busy__read);

      intel_perf_query_add_counter_float(query, 414, 96, percentage_max_float,tglgt1__gpu_busyness__posh_engine_busy__read);

      intel_perf_query_add_counter_float(query, 313, 100, percentage_max_float,tglgt1__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 312, 104, percentage_max_float,tglgt1__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 310, 108, percentage_max_float,tglgt1__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 112, percentage_max_float,tglgt1__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 467, 116, percentage_max_float,tglgt1__gpu_busyness__render_and_compute_busy__read);

      intel_perf_query_add_counter_float(query, 468, 120, percentage_max_float,tglgt1__gpu_busyness__any_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_eu_activity1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity1";
   query->symbol_name = "EuActivity1";
   query->guid = "ffde7a80-6d78-42c8-8603-838de28d07da";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x1E0F4000 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x18018000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101313 },
         { .reg = 0x00009888, .val = 0x4B101313 },
         { .reg = 0x00009888, .val = 0x4D100313 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00810710 },
         { .reg = 0x0000E558, .val = 0x00A10910 },
         { .reg = 0x0000E658, .val = 0x00850750 },
         { .reg = 0x0000E758, .val = 0x00A50950 },
         { .reg = 0x0000E45C, .val = 0x00802702 },
         { .reg = 0x0000E55C, .val = 0x00A02902 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__eu_activity1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__eu_activity1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__eu_activity1__avg_gpu_core_frequency__max,tglgt1__eu_activity1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__eu_activity1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__eu_activity1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__eu_activity1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__eu_activity1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__eu_activity1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__eu_activity1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__eu_activity1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt1__eu_activity1__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt1__eu_activity1__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt1__eu_activity1__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt1__eu_activity1__gti_read_throughput__max,tglgt1__eu_activity1__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt1__eu_activity1__gti_write_throughput__max,tglgt1__eu_activity1__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 469, 112, percentage_max_float,tglgt1__eu_activity1__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 470, 116, percentage_max_float,tglgt1__eu_activity1__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 153, 120, percentage_max_float,tglgt1__eu_activity1__eu_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_eu_activity2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity2";
   query->symbol_name = "EuActivity2";
   query->guid = "bd3186a3-6e96-4c70-a5d9-65d4bea6f668";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x1E0F4000 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x18018000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101313 },
         { .reg = 0x00009888, .val = 0x4B101313 },
         { .reg = 0x00009888, .val = 0x4D100313 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00862762 },
         { .reg = 0x0000E558, .val = 0x00A62962 },
         { .reg = 0x0000E658, .val = 0x00860760 },
         { .reg = 0x0000E758, .val = 0x00A60960 },
         { .reg = 0x0000E45C, .val = 0x00861761 },
         { .reg = 0x0000E55C, .val = 0x00A61961 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__eu_activity2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__eu_activity2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__eu_activity2__avg_gpu_core_frequency__max,tglgt1__eu_activity2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__eu_activity2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__eu_activity2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__eu_activity2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__eu_activity2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__eu_activity2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__eu_activity2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__eu_activity2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt1__eu_activity2__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt1__eu_activity2__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt1__eu_activity2__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt1__eu_activity2__gti_read_throughput__max,tglgt1__eu_activity2__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt1__eu_activity2__gti_write_throughput__max,tglgt1__eu_activity2__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 471, 112, percentage_max_float,tglgt1__eu_activity2__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 472, 116, percentage_max_float,tglgt1__eu_activity2__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 473, 120, percentage_max_float,tglgt1__eu_activity2__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_eu_activity3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity3";
   query->symbol_name = "EuActivity3";
   query->guid = "b59e975f-044c-4e0c-afcd-46aee1107b81";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x1E0F4000 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x18018000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101313 },
         { .reg = 0x00009888, .val = 0x4B101313 },
         { .reg = 0x00009888, .val = 0x4D100313 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00811711 },
         { .reg = 0x0000E558, .val = 0x00A11911 },
         { .reg = 0x0000E658, .val = 0x00851751 },
         { .reg = 0x0000E758, .val = 0x00A51951 },
         { .reg = 0x0000E45C, .val = 0x00852752 },
         { .reg = 0x0000E55C, .val = 0x00A52952 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__eu_activity3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__eu_activity3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__eu_activity3__avg_gpu_core_frequency__max,tglgt1__eu_activity3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__eu_activity3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__eu_activity3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__eu_activity3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__eu_activity3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__eu_activity3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__eu_activity3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__eu_activity3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt1__eu_activity3__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt1__eu_activity3__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt1__eu_activity3__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt1__eu_activity3__gti_read_throughput__max,tglgt1__eu_activity3__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt1__eu_activity3__gti_write_throughput__max,tglgt1__eu_activity3__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 474, 112, percentage_max_float,tglgt1__eu_activity3__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 475, 116, percentage_max_float,tglgt1__eu_activity3__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 129, 120, percentage_max_float,tglgt1__eu_activity3__ps_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_eu_activity4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity4";
   query->symbol_name = "EuActivity4";
   query->guid = "948f1627-f642-42a6-8304-801d7db112d2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x1E0F4000 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x18018000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101313 },
         { .reg = 0x00009888, .val = 0x4B101313 },
         { .reg = 0x00009888, .val = 0x4D100313 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00820720 },
         { .reg = 0x0000E558, .val = 0x00A20920 },
         { .reg = 0x0000E658, .val = 0x00830730 },
         { .reg = 0x0000E758, .val = 0x00A30930 },
         { .reg = 0x0000E45C, .val = 0x00812712 },
         { .reg = 0x0000E55C, .val = 0x00A12912 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__eu_activity4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__eu_activity4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__eu_activity4__avg_gpu_core_frequency__max,tglgt1__eu_activity4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__eu_activity4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__eu_activity4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__eu_activity4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__eu_activity4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__eu_activity4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__eu_activity4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__eu_activity4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt1__eu_activity4__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt1__eu_activity4__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt1__eu_activity4__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt1__eu_activity4__gti_read_throughput__max,tglgt1__eu_activity4__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt1__eu_activity4__gti_write_throughput__max,tglgt1__eu_activity4__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 476, 112, percentage_max_float,tglgt1__eu_activity4__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 477, 116, percentage_max_float,tglgt1__eu_activity4__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 126, 120, percentage_max_float,tglgt1__eu_activity4__vs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_eu_activity5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity5";
   query->symbol_name = "EuActivity5";
   query->guid = "243ffad2-626e-4d05-94a0-af7068e18a84";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x1E0F4000 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x18018000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101313 },
         { .reg = 0x00009888, .val = 0x4B101313 },
         { .reg = 0x00009888, .val = 0x4D100313 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00821721 },
         { .reg = 0x0000E558, .val = 0x00A21921 },
         { .reg = 0x0000E658, .val = 0x00831731 },
         { .reg = 0x0000E758, .val = 0x00A31931 },
         { .reg = 0x0000E45C, .val = 0x00822722 },
         { .reg = 0x0000E55C, .val = 0x00A22922 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__eu_activity5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__eu_activity5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__eu_activity5__avg_gpu_core_frequency__max,tglgt1__eu_activity5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__eu_activity5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__eu_activity5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__eu_activity5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__eu_activity5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__eu_activity5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__eu_activity5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__eu_activity5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt1__eu_activity5__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt1__eu_activity5__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt1__eu_activity5__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt1__eu_activity5__gti_read_throughput__max,tglgt1__eu_activity5__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt1__eu_activity5__gti_write_throughput__max,tglgt1__eu_activity5__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 478, 112, percentage_max_float,tglgt1__eu_activity5__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 479, 116, percentage_max_float,tglgt1__eu_activity5__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 480, 120, percentage_max_float,tglgt1__eu_activity5__hs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_eu_activity6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity6";
   query->symbol_name = "EuActivity6";
   query->guid = "1f367b67-1f45-469b-97fd-eac88aeb1f7c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x1E0F4000 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x18018000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101313 },
         { .reg = 0x00009888, .val = 0x4B101313 },
         { .reg = 0x00009888, .val = 0x4D100313 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00840740 },
         { .reg = 0x0000E558, .val = 0x00A40940 },
         { .reg = 0x0000E658, .val = 0x00841741 },
         { .reg = 0x0000E758, .val = 0x00A41941 },
         { .reg = 0x0000E45C, .val = 0x00842742 },
         { .reg = 0x0000E55C, .val = 0x00A42942 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__eu_activity6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__eu_activity6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__eu_activity6__avg_gpu_core_frequency__max,tglgt1__eu_activity6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__eu_activity6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__eu_activity6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__eu_activity6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__eu_activity6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__eu_activity6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__eu_activity6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__eu_activity6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt1__eu_activity6__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt1__eu_activity6__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt1__eu_activity6__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt1__eu_activity6__gti_read_throughput__max,tglgt1__eu_activity6__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt1__eu_activity6__gti_write_throughput__max,tglgt1__eu_activity6__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 481, 112, percentage_max_float,tglgt1__eu_activity6__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 482, 116, percentage_max_float,tglgt1__eu_activity6__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 483, 120, percentage_max_float,tglgt1__eu_activity6__gs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_eu_activity7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "EuActivity7";
   query->symbol_name = "EuActivity7";
   query->guid = "7c2db23c-1fb4-45df-a5d5-2345d23c10fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x1E0F4000 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x18018000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101313 },
         { .reg = 0x00009888, .val = 0x4B101313 },
         { .reg = 0x00009888, .val = 0x4D100313 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00803703 },
         { .reg = 0x0000E558, .val = 0x00A03903 },
         { .reg = 0x0000E658, .val = 0x00800700 },
         { .reg = 0x0000E758, .val = 0x00A00900 },
         { .reg = 0x0000E45C, .val = 0x00801701 },
         { .reg = 0x0000E55C, .val = 0x00A01901 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__eu_activity7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__eu_activity7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__eu_activity7__avg_gpu_core_frequency__max,tglgt1__eu_activity7__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__eu_activity7__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__eu_activity7__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__eu_activity7__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__eu_activity7__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__eu_activity7__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__eu_activity7__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__eu_activity7__cs_threads__read);

      intel_perf_query_add_counter_float(query, 484, 80, percentage_max_float,tglgt1__eu_activity7__fpu_active__read);

      intel_perf_query_add_counter_float(query, 485, 84, percentage_max_float,tglgt1__eu_activity7__em_active__read);

      intel_perf_query_add_counter_float(query, 486, 88, percentage_max_float,tglgt1__eu_activity7__eu_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 152, 92, tglgt1__eu_activity7__eu_avg_ipc_rate__max,tglgt1__eu_activity7__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 309, 96, percentage_max_float,tglgt1__eu_activity7__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 100, percentage_max_float,tglgt1__eu_activity7__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 104, percentage_max_float,tglgt1__eu_activity7__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 112, tglgt1__eu_activity7__gti_read_throughput__max,tglgt1__eu_activity7__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 120, tglgt1__eu_activity7__gti_write_throughput__max,tglgt1__eu_activity7__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_eu_activity8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 16);

   query->name = "EuActivity8";
   query->symbol_name = "EuActivity8";
   query->guid = "b4c81162-2c96-4cf1-86ae-ecff3d57ee4d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x1C0F4000 },
         { .reg = 0x00009888, .val = 0x1E0F4000 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x18018000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101313 },
         { .reg = 0x00009888, .val = 0x4B101313 },
         { .reg = 0x00009888, .val = 0x4D100313 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00832732 },
         { .reg = 0x0000E558, .val = 0x00A32932 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__eu_activity8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__eu_activity8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__eu_activity8__avg_gpu_core_frequency__max,tglgt1__eu_activity8__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt1__eu_activity8__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt1__eu_activity8__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt1__eu_activity8__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt1__eu_activity8__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt1__eu_activity8__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt1__eu_activity8__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt1__eu_activity8__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt1__eu_activity8__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt1__eu_activity8__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt1__eu_activity8__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt1__eu_activity8__gti_read_throughput__max,tglgt1__eu_activity8__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt1__eu_activity8__gti_write_throughput__max,tglgt1__eu_activity8__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 487, 112, percentage_max_float,tglgt1__eu_activity8__ds_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt1_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "6f27aaed-4f08-4e0f-95a9-231d9b4fa111";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x1E0F0017 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x49110000 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x1D140020 },
         { .reg = 0x00009888, .val = 0x1D1103A3 },
         { .reg = 0x00009888, .val = 0x01110000 },
         { .reg = 0x00009888, .val = 0x61111000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100210 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000DC00, .val = 0x00000004 },
         { .reg = 0x0000DC04, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000DC08, .val = 0x00000003 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000DC10, .val = 0x00000007 },
         { .reg = 0x0000DC14, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00100002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000DC20, .val = 0x00100002 },
         { .reg = 0x0000DC24, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000DC28, .val = 0x00100082 },
         { .reg = 0x0000DC2C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000DC30, .val = 0x001000C2 },
         { .reg = 0x0000DC34, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
         { .reg = 0x0000DC38, .val = 0x00100001 },
         { .reg = 0x0000DC3C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt1__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt1__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt1__test_oa__avg_gpu_core_frequency__max,tglgt1__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,tglgt1__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,tglgt1__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,tglgt1__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,tglgt1__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 415, 56, NULL,tglgt1__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 416, 64, NULL,tglgt1__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 417, 72, NULL,tglgt1__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 418, 80, NULL,tglgt1__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 488, 88, NULL,tglgt1__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 489, 96, NULL,tglgt1__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_tglgt1(struct intel_perf_config *perf)
{
   tglgt1_register_render_basic_counter_query(perf);
   tglgt1_register_compute_basic_counter_query(perf);
   tglgt1_register_render_pipe_profile_counter_query(perf);
   tglgt1_register_hdc_and_sf_counter_query(perf);
   tglgt1_register_rasterizer_and_pixel_backend_counter_query(perf);
   tglgt1_register_l3_1_counter_query(perf);
   tglgt1_register_l3_2_counter_query(perf);
   tglgt1_register_l3_3_counter_query(perf);
   tglgt1_register_l3_4_counter_query(perf);
   tglgt1_register_l3_5_counter_query(perf);
   tglgt1_register_l3_6_counter_query(perf);
   tglgt1_register_sampler_1_counter_query(perf);
   tglgt1_register_tdl_1_counter_query(perf);
   tglgt1_register_gpu_busyness_counter_query(perf);
   tglgt1_register_eu_activity1_counter_query(perf);
   tglgt1_register_eu_activity2_counter_query(perf);
   tglgt1_register_eu_activity3_counter_query(perf);
   tglgt1_register_eu_activity4_counter_query(perf);
   tglgt1_register_eu_activity5_counter_query(perf);
   tglgt1_register_eu_activity6_counter_query(perf);
   tglgt1_register_eu_activity7_counter_query(perf);
   tglgt1_register_eu_activity8_counter_query(perf);
   tglgt1_register_test_oa_counter_query(perf);
}


static void
tglgt2_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 34);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "0fc397c0-4833-492c-9ccd-4929d574d5b8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14150001 },
         { .reg = 0x00009888, .val = 0x16150020 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0E124000 },
         { .reg = 0x00009888, .val = 0x10124000 },
         { .reg = 0x00009888, .val = 0x12124000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x1C130E00 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x06157000 },
         { .reg = 0x00009888, .val = 0x08157151 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x18150000 },
         { .reg = 0x00009888, .val = 0x1C150000 },
         { .reg = 0x00009888, .val = 0x18004000 },
         { .reg = 0x00009888, .val = 0x36000490 },
         { .reg = 0x00009888, .val = 0x1C058000 },
         { .reg = 0x00009888, .val = 0x2405002A },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D47 },
         { .reg = 0x00009888, .val = 0x09151536 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B1050BB },
         { .reg = 0x00009888, .val = 0x5D102C01 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x61110001 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x1F150137 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x0F168000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x1D350137 },
         { .reg = 0x00009888, .val = 0x03350147 },
         { .reg = 0x00009888, .val = 0x07350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x0F364000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x47103000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55103130 },
         { .reg = 0x00009888, .val = 0x57100001 },
         { .reg = 0x00009888, .val = 0x49103131 },
         { .reg = 0x00009888, .val = 0x4B100131 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__render_basic__avg_gpu_core_frequency__max,tglgt2__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,tglgt2__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,tglgt2__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,tglgt2__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,tglgt2__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,tglgt2__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,tglgt2__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,tglgt2__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,tglgt2__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,tglgt2__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 84, percentage_max_float,tglgt2__render_basic__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 333, 88, percentage_max_float,tglgt2__render_basic__sampler00_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 435, 92, percentage_max_float,tglgt2__render_basic__sampler00_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 133, 96, percentage_max_float,tglgt2__render_basic__samplers_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 149, 100, percentage_max_float,tglgt2__render_basic__sampler_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 104, NULL,tglgt2__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 112, NULL,tglgt2__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 120, NULL,tglgt2__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 128, NULL,tglgt2__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 136, NULL,tglgt2__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 144, NULL,tglgt2__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 152, NULL,tglgt2__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 160, NULL,tglgt2__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 168, NULL,tglgt2__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 176, tglgt2__render_basic__slm_bytes_read__max,tglgt2__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 184, tglgt2__render_basic__slm_bytes_written__max,tglgt2__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 192, NULL,tglgt2__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 200, NULL,tglgt2__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 208, tglgt2__render_basic__l3_shader_throughput__max,tglgt2__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 216, NULL,tglgt2__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 224, tglgt2__render_basic__gti_read_throughput__max,tglgt2__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 232, tglgt2__render_basic__gti_write_throughput__max,tglgt2__render_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 30);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "397a46d9-03dd-4696-8196-270362e1c575";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__compute_basic__avg_gpu_core_frequency__max,tglgt2__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,tglgt2__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,tglgt2__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,tglgt2__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,tglgt2__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,tglgt2__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,tglgt2__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,tglgt2__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,tglgt2__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,tglgt2__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, tglgt2__compute_basic__slm_bytes_read__max,tglgt2__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, tglgt2__compute_basic__slm_bytes_written__max,tglgt2__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,tglgt2__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,tglgt2__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, tglgt2__compute_basic__l3_shader_throughput__max,tglgt2__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,tglgt2__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 216, tglgt2__compute_basic__gti_read_throughput__max,tglgt2__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 224, tglgt2__compute_basic__gti_write_throughput__max,tglgt2__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "684ed715-a0ca-499b-89e0-25d1cdf0c737";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00123E00 },
         { .reg = 0x00009888, .val = 0x060B00B3 },
         { .reg = 0x00009888, .val = 0x140B3C00 },
         { .reg = 0x00009888, .val = 0x1C0B0000 },
         { .reg = 0x00009888, .val = 0x120C8320 },
         { .reg = 0x00009888, .val = 0x040DBE00 },
         { .reg = 0x00009888, .val = 0x000D0000 },
         { .reg = 0x00009888, .val = 0x280D0000 },
         { .reg = 0x00009888, .val = 0x2C0E7C00 },
         { .reg = 0x00009888, .val = 0x10087C00 },
         { .reg = 0x00009888, .val = 0x1E120002 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x1E130002 },
         { .reg = 0x00009888, .val = 0x0E0B0031 },
         { .reg = 0x00009888, .val = 0x180B0092 },
         { .reg = 0x00009888, .val = 0x1A0B00B1 },
         { .reg = 0x00009888, .val = 0x020B0093 },
         { .reg = 0x00009888, .val = 0x040B0033 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x0A0C0022 },
         { .reg = 0x00009888, .val = 0x1E0C0030 },
         { .reg = 0x00009888, .val = 0x1C0C8000 },
         { .reg = 0x00009888, .val = 0x140C8000 },
         { .reg = 0x00009888, .val = 0x160C8000 },
         { .reg = 0x00009888, .val = 0x100DC017 },
         { .reg = 0x00009888, .val = 0x160D0013 },
         { .reg = 0x00009888, .val = 0x1C0D0081 },
         { .reg = 0x00009888, .val = 0x080D0082 },
         { .reg = 0x00009888, .val = 0x0A0D8102 },
         { .reg = 0x00009888, .val = 0x140D0000 },
         { .reg = 0x00009888, .val = 0x0C0D0000 },
         { .reg = 0x00009888, .val = 0x0E0D4000 },
         { .reg = 0x00009888, .val = 0x120D0000 },
         { .reg = 0x00009888, .val = 0x060DC000 },
         { .reg = 0x00009888, .val = 0x0C0EC1C5 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x0E0E8000 },
         { .reg = 0x00009888, .val = 0x100E4000 },
         { .reg = 0x00009888, .val = 0x120EC000 },
         { .reg = 0x00009888, .val = 0x140EC000 },
         { .reg = 0x00009888, .val = 0x160E4000 },
         { .reg = 0x00009888, .val = 0x080E8000 },
         { .reg = 0x00009888, .val = 0x0A0EC000 },
         { .reg = 0x00009888, .val = 0x1C0F5555 },
         { .reg = 0x00009888, .val = 0x1E0F0554 },
         { .reg = 0x00009888, .val = 0x0E104000 },
         { .reg = 0x00009888, .val = 0x10104000 },
         { .reg = 0x00009888, .val = 0x14104000 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x18104000 },
         { .reg = 0x00009888, .val = 0x1A104000 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x02104000 },
         { .reg = 0x00009888, .val = 0x04104000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x08104000 },
         { .reg = 0x00009888, .val = 0x0A104000 },
         { .reg = 0x00009888, .val = 0x0C104000 },
         { .reg = 0x00009888, .val = 0x0E024000 },
         { .reg = 0x00009888, .val = 0x10024000 },
         { .reg = 0x00009888, .val = 0x2C024000 },
         { .reg = 0x00009888, .val = 0x2E020055 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x06024000 },
         { .reg = 0x00009888, .val = 0x08024000 },
         { .reg = 0x00009888, .val = 0x0A024000 },
         { .reg = 0x00009888, .val = 0x0C024000 },
         { .reg = 0x00009888, .val = 0x1A032000 },
         { .reg = 0x00009888, .val = 0x1C032000 },
         { .reg = 0x00009888, .val = 0x2A035500 },
         { .reg = 0x00009888, .val = 0x2C030001 },
         { .reg = 0x00009888, .val = 0x02034000 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08034000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x360036DB },
         { .reg = 0x00009888, .val = 0x380026DB },
         { .reg = 0x00009888, .val = 0x1A006000 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x1E006000 },
         { .reg = 0x00009888, .val = 0x34001B00 },
         { .reg = 0x00009888, .val = 0x26050002 },
         { .reg = 0x00009888, .val = 0x0E0A8000 },
         { .reg = 0x00009888, .val = 0x100A8000 },
         { .reg = 0x00009888, .val = 0x120A4000 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x020A8000 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009888, .val = 0x08081000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x5F115555 },
         { .reg = 0x00009888, .val = 0x61111555 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x4D100604 },
         { .reg = 0x00009888, .val = 0x4F103400 },
         { .reg = 0x00009888, .val = 0x51100200 },
         { .reg = 0x00009888, .val = 0x53100004 },
         { .reg = 0x00009888, .val = 0x55101400 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100005 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100400 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__render_pipe_profile__avg_gpu_core_frequency__max,tglgt2__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__render_pipe_profile__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,tglgt2__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,tglgt2__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,tglgt2__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,tglgt2__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,tglgt2__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,tglgt2__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,tglgt2__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,tglgt2__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,tglgt2__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, tglgt2__render_pipe_profile__slm_bytes_read__max,tglgt2__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, tglgt2__render_pipe_profile__slm_bytes_written__max,tglgt2__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,tglgt2__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,tglgt2__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, tglgt2__render_pipe_profile__l3_shader_throughput__max,tglgt2__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,tglgt2__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 216, percentage_max_float,tglgt2__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 220, percentage_max_float,tglgt2__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 224, percentage_max_float,tglgt2__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 228, percentage_max_float,tglgt2__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 232, percentage_max_float,tglgt2__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 236, percentage_max_float,tglgt2__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 240, percentage_max_float,tglgt2__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 244, percentage_max_float,tglgt2__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 248, percentage_max_float,tglgt2__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 252, percentage_max_float,tglgt2__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 256, percentage_max_float,tglgt2__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 260, percentage_max_float,tglgt2__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 264, percentage_max_float,tglgt2__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 268, percentage_max_float,tglgt2__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 272, percentage_max_float,tglgt2__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 35);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "3a4c7510-7725-4bf8-9eae-59115a2431c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14112400 },
         { .reg = 0x00009888, .val = 0x14312400 },
         { .reg = 0x00009888, .val = 0x14512474 },
         { .reg = 0x00009888, .val = 0x14712400 },
         { .reg = 0x00009888, .val = 0x14912400 },
         { .reg = 0x00009888, .val = 0x14B12400 },
         { .reg = 0x00009888, .val = 0x240A0019 },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x24070002 },
         { .reg = 0x00009888, .val = 0x10110074 },
         { .reg = 0x00009888, .val = 0x08110000 },
         { .reg = 0x00009888, .val = 0x10128000 },
         { .reg = 0x00009888, .val = 0x1C130400 },
         { .reg = 0x00009888, .val = 0x12310074 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x08310000 },
         { .reg = 0x00009888, .val = 0x12328000 },
         { .reg = 0x00009888, .val = 0x1C330800 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x0A510000 },
         { .reg = 0x00009888, .val = 0x14528000 },
         { .reg = 0x00009888, .val = 0x1C531000 },
         { .reg = 0x00009888, .val = 0x16710074 },
         { .reg = 0x00009888, .val = 0x10710000 },
         { .reg = 0x00009888, .val = 0x0A710000 },
         { .reg = 0x00009888, .val = 0x16728000 },
         { .reg = 0x00009888, .val = 0x1C732000 },
         { .reg = 0x00009888, .val = 0x0E910074 },
         { .reg = 0x00009888, .val = 0x10910000 },
         { .reg = 0x00009888, .val = 0x06910000 },
         { .reg = 0x00009888, .val = 0x0E928000 },
         { .reg = 0x00009888, .val = 0x1C930200 },
         { .reg = 0x00009888, .val = 0x00B10074 },
         { .reg = 0x00009888, .val = 0x10B10000 },
         { .reg = 0x00009888, .val = 0x00B28000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1E0F0020 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x2E020001 },
         { .reg = 0x00009888, .val = 0x2A030600 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x36003488 },
         { .reg = 0x00009888, .val = 0x3800001B },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x24050038 },
         { .reg = 0x00009888, .val = 0x24060080 },
         { .reg = 0x00009888, .val = 0x180A00F7 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105000 },
         { .reg = 0x00009888, .val = 0x5D100055 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x1D140007 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x61110055 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x47100600 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F101116 },
         { .reg = 0x00009888, .val = 0x51100401 },
         { .reg = 0x00009888, .val = 0x53100030 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000DC00, .val = 0x00000002 },
         { .reg = 0x0000DC04, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000DC08, .val = 0x00000002 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000DC10, .val = 0x00000002 },
         { .reg = 0x0000DC14, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00000002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000DC20, .val = 0x00000002 },
         { .reg = 0x0000DC24, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000DC28, .val = 0x00000002 },
         { .reg = 0x0000DC2C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000DC30, .val = 0x00000002 },
         { .reg = 0x0000DC34, .val = 0x0000FFBF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__hdc_and_sf__avg_gpu_core_frequency__max,tglgt2__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__hdc_and_sf__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,tglgt2__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,tglgt2__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,tglgt2__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,tglgt2__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,tglgt2__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,tglgt2__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,tglgt2__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,tglgt2__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,tglgt2__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, tglgt2__hdc_and_sf__slm_bytes_read__max,tglgt2__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, tglgt2__hdc_and_sf__slm_bytes_written__max,tglgt2__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,tglgt2__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,tglgt2__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, tglgt2__hdc_and_sf__l3_shader_throughput__max,tglgt2__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,tglgt2__hdc_and_sf__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 356, 216, percentage_max_float,tglgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 357, 220, percentage_max_float,tglgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 358, 224, percentage_max_float,tglgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 359, 228, percentage_max_float,tglgt2__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 490, 232, percentage_max_float,tglgt2__hdc_and_sf__non_sampler_shader04_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 491, 236, percentage_max_float,tglgt2__hdc_and_sf__non_sampler_shader05_access_stalled_on_l3__read);
      }

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,tglgt2__hdc_and_sf__poly_data_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "6f02479c-e9ca-4c2b-b1e6-216a9e1c5ef7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1E075000 },
         { .reg = 0x00009888, .val = 0x1A0700C0 },
         { .reg = 0x00009888, .val = 0x1E055000 },
         { .reg = 0x00009888, .val = 0x1A0500C0 },
         { .reg = 0x00009888, .val = 0x1E065000 },
         { .reg = 0x00009888, .val = 0x1A0600C0 },
         { .reg = 0x00009888, .val = 0x2A0A7300 },
         { .reg = 0x00009888, .val = 0x2C0A0000 },
         { .reg = 0x00009888, .val = 0x120800A0 },
         { .reg = 0x00009888, .val = 0x0A07C000 },
         { .reg = 0x00009888, .val = 0x0E070027 },
         { .reg = 0x00009888, .val = 0x10070000 },
         { .reg = 0x00009888, .val = 0x24070000 },
         { .reg = 0x00009888, .val = 0x2A032000 },
         { .reg = 0x00009888, .val = 0x2C030008 },
         { .reg = 0x00009888, .val = 0x18006000 },
         { .reg = 0x00009888, .val = 0x360036D8 },
         { .reg = 0x00009888, .val = 0x38003299 },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x2A010400 },
         { .reg = 0x00009888, .val = 0x2C010001 },
         { .reg = 0x00009888, .val = 0x0C05C000 },
         { .reg = 0x00009888, .val = 0x00052700 },
         { .reg = 0x00009888, .val = 0x10050000 },
         { .reg = 0x00009888, .val = 0x24050000 },
         { .reg = 0x00009888, .val = 0x22050000 },
         { .reg = 0x00009888, .val = 0x0C0600C0 },
         { .reg = 0x00009888, .val = 0x0E062700 },
         { .reg = 0x00009888, .val = 0x10060000 },
         { .reg = 0x00009888, .val = 0x24060000 },
         { .reg = 0x00009888, .val = 0x26060000 },
         { .reg = 0x00009888, .val = 0x000A0144 },
         { .reg = 0x00009888, .val = 0x0E0A0145 },
         { .reg = 0x00009888, .val = 0x100A0156 },
         { .reg = 0x00009888, .val = 0x040A014F },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x120A4000 },
         { .reg = 0x00009888, .val = 0x140A4000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009888, .val = 0x08081980 },
         { .reg = 0x00009888, .val = 0x0A080032 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x31152800 },
         { .reg = 0x00009888, .val = 0x331500A0 },
         { .reg = 0x00009888, .val = 0x31352800 },
         { .reg = 0x00009888, .val = 0x333500A0 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105FA5 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115005 },
         { .reg = 0x00009888, .val = 0x61111555 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07150016 },
         { .reg = 0x00009888, .val = 0x09150096 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03168000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x0B350016 },
         { .reg = 0x00009888, .val = 0x0D350096 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x07364000 },
         { .reg = 0x00009888, .val = 0x47100400 },
         { .reg = 0x00009888, .val = 0x4D100616 },
         { .reg = 0x00009888, .val = 0x4F100404 },
         { .reg = 0x00009888, .val = 0x51100202 },
         { .reg = 0x00009888, .val = 0x53100002 },
         { .reg = 0x00009888, .val = 0x55100204 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x49101404 },
         { .reg = 0x00009888, .val = 0x4B101616 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000DC00, .val = 0x00000038 },
         { .reg = 0x0000DC04, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000DC08, .val = 0x000000C0 },
         { .reg = 0x0000DC0C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,tglgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,tglgt2__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,tglgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,tglgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,tglgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,tglgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,tglgt2__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,tglgt2__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,tglgt2__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,tglgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, tglgt2__rasterizer_and_pixel_backend__slm_bytes_read__max,tglgt2__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, tglgt2__rasterizer_and_pixel_backend__slm_bytes_written__max,tglgt2__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,tglgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,tglgt2__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, tglgt2__rasterizer_and_pixel_backend__l3_shader_throughput__max,tglgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,tglgt2__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 266, 216, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 261, 220, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 360, 224, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 362, 228, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 363, 232, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__ps_output01_available__read);

      intel_perf_query_add_counter_float(query, 492, 236, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__ps_output02_available__read);

      intel_perf_query_add_counter_float(query, 364, 240, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__pixel_values00_ready__read);

      intel_perf_query_add_counter_float(query, 365, 244, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__pixel_values01_ready__read);

      intel_perf_query_add_counter_float(query, 493, 248, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__pixel_values02_ready__read);

      intel_perf_query_add_counter_float(query, 436, 252, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__gt_request_queue00_full__read);

      intel_perf_query_add_counter_float(query, 437, 256, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__gt_request_queue01_full__read);

      intel_perf_query_add_counter_float(query, 438, 260, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__gt_request_queue10_full__read);

      intel_perf_query_add_counter_float(query, 439, 264, percentage_max_float,tglgt2__rasterizer_and_pixel_backend__gt_request_queue11_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "L3_1";
   query->symbol_name = "L3_1";
   query->guid = "7e809cb4-6e90-44cc-9c57-6eff58ad360a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04022000 },
         { .reg = 0x00009888, .val = 0x06022800 },
         { .reg = 0x00009888, .val = 0x04002827 },
         { .reg = 0x00009888, .val = 0x0600202C },
         { .reg = 0x00009888, .val = 0x00020024 },
         { .reg = 0x00009888, .val = 0x0E020025 },
         { .reg = 0x00009888, .val = 0x10020026 },
         { .reg = 0x00009888, .val = 0x12020027 },
         { .reg = 0x00009888, .val = 0x1402002C },
         { .reg = 0x00009888, .val = 0x1602002D },
         { .reg = 0x00009888, .val = 0x1802002E },
         { .reg = 0x00009888, .val = 0x1A02002F },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x2C020000 },
         { .reg = 0x00009888, .val = 0x00034000 },
         { .reg = 0x00009888, .val = 0x1A032000 },
         { .reg = 0x00009888, .val = 0x1C032000 },
         { .reg = 0x00009888, .val = 0x1E032000 },
         { .reg = 0x00009888, .val = 0x2A035500 },
         { .reg = 0x00009888, .val = 0x1C000024 },
         { .reg = 0x00009888, .val = 0x1E000025 },
         { .reg = 0x00009888, .val = 0x02000026 },
         { .reg = 0x00009888, .val = 0x0800002D },
         { .reg = 0x00009888, .val = 0x0A00002E },
         { .reg = 0x00009888, .val = 0x0C00002F },
         { .reg = 0x00009888, .val = 0x360036D8 },
         { .reg = 0x00009888, .val = 0x18006000 },
         { .reg = 0x00009888, .val = 0x380000DB },
         { .reg = 0x00009888, .val = 0x1A000000 },
         { .reg = 0x00009888, .val = 0x34000000 },
         { .reg = 0x00009888, .val = 0x000A8000 },
         { .reg = 0x00009888, .val = 0x0E0A8000 },
         { .reg = 0x00009888, .val = 0x100A8000 },
         { .reg = 0x00009888, .val = 0x120A8000 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115555 },
         { .reg = 0x00009888, .val = 0x61111555 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x4D100606 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x53100000 },
         { .reg = 0x00009888, .val = 0x55100600 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100006 },
         { .reg = 0x00009888, .val = 0x49100606 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__l3_1__avg_gpu_core_frequency__max,tglgt2__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,tglgt2__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,tglgt2__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,tglgt2__l3_1__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,tglgt2__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,tglgt2__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,tglgt2__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,tglgt2__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,tglgt2__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,tglgt2__l3_1__cs_threads__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 440, 88, percentage_max_float,tglgt2__l3_1__l30_bank0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 441, 92, percentage_max_float,tglgt2__l3_1__l30_bank1_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 494, 96, percentage_max_float,tglgt2__l3_1__l30_bank4_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 495, 100, percentage_max_float,tglgt2__l3_1__l30_bank5_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "L3_2";
   query->symbol_name = "L3_2";
   query->guid = "0dde1bb6-340f-4350-b398-2b0228573967";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04023027 },
         { .reg = 0x00009888, .val = 0x0602382C },
         { .reg = 0x00009888, .val = 0x04003000 },
         { .reg = 0x00009888, .val = 0x06003800 },
         { .reg = 0x00009888, .val = 0x1C020024 },
         { .reg = 0x00009888, .val = 0x1E020025 },
         { .reg = 0x00009888, .val = 0x02020026 },
         { .reg = 0x00009888, .val = 0x0802002D },
         { .reg = 0x00009888, .val = 0x0A02002E },
         { .reg = 0x00009888, .val = 0x0C02002F },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x02034000 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08034000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x00000024 },
         { .reg = 0x00009888, .val = 0x0E000025 },
         { .reg = 0x00009888, .val = 0x10000026 },
         { .reg = 0x00009888, .val = 0x12000027 },
         { .reg = 0x00009888, .val = 0x1400002C },
         { .reg = 0x00009888, .val = 0x1600002D },
         { .reg = 0x00009888, .val = 0x1800002E },
         { .reg = 0x00009888, .val = 0x1A00602F },
         { .reg = 0x00009888, .val = 0x36000003 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x1E006000 },
         { .reg = 0x00009888, .val = 0x34001B00 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009888, .val = 0x020A8000 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115555 },
         { .reg = 0x00009888, .val = 0x61111555 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x47100600 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100606 },
         { .reg = 0x00009888, .val = 0x51100606 },
         { .reg = 0x00009888, .val = 0x53100606 },
         { .reg = 0x00009888, .val = 0x55100006 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__l3_2__avg_gpu_core_frequency__max,tglgt2__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__l3_2__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 442, 92, percentage_max_float,tglgt2__l3_2__l30_bank2_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 443, 96, percentage_max_float,tglgt2__l3_2__l30_bank3_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 496, 100, percentage_max_float,tglgt2__l3_2__l30_bank6_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 497, 104, percentage_max_float,tglgt2__l3_2__l30_bank7_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_3";
   query->symbol_name = "L3_3";
   query->guid = "8ecaeff2-78f4-4e29-b331-d757e6a74ed0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04020200 },
         { .reg = 0x00009888, .val = 0x06020020 },
         { .reg = 0x00009888, .val = 0x04000200 },
         { .reg = 0x00009888, .val = 0x06000000 },
         { .reg = 0x00009888, .val = 0x08020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08034000 },
         { .reg = 0x00009888, .val = 0x0A000020 },
         { .reg = 0x00009888, .val = 0x0C000028 },
         { .reg = 0x00009888, .val = 0x36000000 },
         { .reg = 0x00009888, .val = 0x1E006000 },
         { .reg = 0x00009888, .val = 0x34000300 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x5F110550 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100606 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__l3_3__avg_gpu_core_frequency__max,tglgt2__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__l3_3__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 444, 92, percentage_max_float,tglgt2__l3_3__l30_bank0_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 498, 96, percentage_max_float,tglgt2__l3_3__l30_bank4_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_l3_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_4";
   query->symbol_name = "L3_4";
   query->guid = "30cd8433-f679-401e-b578-19e22975e84f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04020A00 },
         { .reg = 0x00009888, .val = 0x06020800 },
         { .reg = 0x00009888, .val = 0x04000A00 },
         { .reg = 0x00009888, .val = 0x06000820 },
         { .reg = 0x00009888, .val = 0x0A020020 },
         { .reg = 0x00009888, .val = 0x0C020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x36000003 },
         { .reg = 0x00009888, .val = 0x1E000000 },
         { .reg = 0x00009888, .val = 0x34001800 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x5F110550 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__l3_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__l3_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__l3_4__avg_gpu_core_frequency__max,tglgt2__l3_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__l3_4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__l3_4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__l3_4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__l3_4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__l3_4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__l3_4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__l3_4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__l3_4__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__l3_4__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__l3_4__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 445, 92, percentage_max_float,tglgt2__l3_4__l30_bank1_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 499, 96, percentage_max_float,tglgt2__l3_4__l30_bank5_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_l3_5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_5";
   query->symbol_name = "L3_5";
   query->guid = "e0efab61-c904-4354-9fc5-35e8b8bc7d20";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04021200 },
         { .reg = 0x00009888, .val = 0x06021000 },
         { .reg = 0x00009888, .val = 0x04001200 },
         { .reg = 0x00009888, .val = 0x06001020 },
         { .reg = 0x00009888, .val = 0x0A020020 },
         { .reg = 0x00009888, .val = 0x0C020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x36000003 },
         { .reg = 0x00009888, .val = 0x1E000000 },
         { .reg = 0x00009888, .val = 0x34001800 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x5F110550 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__l3_5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__l3_5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__l3_5__avg_gpu_core_frequency__max,tglgt2__l3_5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__l3_5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__l3_5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__l3_5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__l3_5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__l3_5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__l3_5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__l3_5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__l3_5__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__l3_5__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__l3_5__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 446, 92, percentage_max_float,tglgt2__l3_5__l30_bank2_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 500, 96, percentage_max_float,tglgt2__l3_5__l30_bank6_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_l3_6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_6";
   query->symbol_name = "L3_6";
   query->guid = "4066ad45-4a68-4acf-86b2-fa5a6a914db7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04021A00 },
         { .reg = 0x00009888, .val = 0x06021800 },
         { .reg = 0x00009888, .val = 0x04001A00 },
         { .reg = 0x00009888, .val = 0x06001820 },
         { .reg = 0x00009888, .val = 0x0A020020 },
         { .reg = 0x00009888, .val = 0x0C020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x36000003 },
         { .reg = 0x00009888, .val = 0x1E000000 },
         { .reg = 0x00009888, .val = 0x34001800 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x5F110550 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__l3_6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__l3_6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__l3_6__avg_gpu_core_frequency__max,tglgt2__l3_6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__l3_6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__l3_6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__l3_6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__l3_6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__l3_6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__l3_6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__l3_6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__l3_6__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__l3_6__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__l3_6__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 447, 92, percentage_max_float,tglgt2__l3_6__l30_bank3_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 501, 96, percentage_max_float,tglgt2__l3_6__l30_bank7_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Sampler_1";
   query->symbol_name = "Sampler_1";
   query->guid = "17e2be13-39fe-45f0-867c-0f83fcc51654";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C121600 },
         { .reg = 0x00009888, .val = 0x18141600 },
         { .reg = 0x00009888, .val = 0x1C325600 },
         { .reg = 0x00009888, .val = 0x18341600 },
         { .reg = 0x00009888, .val = 0x1C521600 },
         { .reg = 0x00009888, .val = 0x185416A6 },
         { .reg = 0x00009888, .val = 0x1C721600 },
         { .reg = 0x00009888, .val = 0x18741600 },
         { .reg = 0x00009888, .val = 0x1C921600 },
         { .reg = 0x00009888, .val = 0x18941600 },
         { .reg = 0x00009888, .val = 0x1CB21600 },
         { .reg = 0x00009888, .val = 0x18B41600 },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x2407002B },
         { .reg = 0x00009888, .val = 0x04120086 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x02124000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x021400A6 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x00140000 },
         { .reg = 0x00009888, .val = 0x1A150020 },
         { .reg = 0x00009888, .val = 0x1E320086 },
         { .reg = 0x00009888, .val = 0x20320000 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x1C3400A6 },
         { .reg = 0x00009888, .val = 0x10340000 },
         { .reg = 0x00009888, .val = 0x0E340000 },
         { .reg = 0x00009888, .val = 0x1C358000 },
         { .reg = 0x00009888, .val = 0x1A520086 },
         { .reg = 0x00009888, .val = 0x20520000 },
         { .reg = 0x00009888, .val = 0x18524000 },
         { .reg = 0x00009888, .val = 0x1C53C000 },
         { .reg = 0x00009888, .val = 0x10540000 },
         { .reg = 0x00009888, .val = 0x0C540000 },
         { .reg = 0x00009888, .val = 0x1C550800 },
         { .reg = 0x00009888, .val = 0x16720086 },
         { .reg = 0x00009888, .val = 0x20720000 },
         { .reg = 0x00009888, .val = 0x14724000 },
         { .reg = 0x00009888, .val = 0x1C733000 },
         { .reg = 0x00009888, .val = 0x147400A6 },
         { .reg = 0x00009888, .val = 0x10740000 },
         { .reg = 0x00009888, .val = 0x0A740000 },
         { .reg = 0x00009888, .val = 0x1C750080 },
         { .reg = 0x00009888, .val = 0x12920086 },
         { .reg = 0x00009888, .val = 0x20920000 },
         { .reg = 0x00009888, .val = 0x10924000 },
         { .reg = 0x00009888, .val = 0x1C930C00 },
         { .reg = 0x00009888, .val = 0x109400A6 },
         { .reg = 0x00009888, .val = 0x08940000 },
         { .reg = 0x00009888, .val = 0x1C950008 },
         { .reg = 0x00009888, .val = 0x0EB20086 },
         { .reg = 0x00009888, .val = 0x20B20000 },
         { .reg = 0x00009888, .val = 0x00B24000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1CB30200 },
         { .reg = 0x00009888, .val = 0x00B400A6 },
         { .reg = 0x00009888, .val = 0x10B40000 },
         { .reg = 0x00009888, .val = 0x18B58000 },
         { .reg = 0x00009888, .val = 0x1E0F0028 },
         { .reg = 0x00009888, .val = 0x14104000 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x2C024000 },
         { .reg = 0x00009888, .val = 0x2E020001 },
         { .reg = 0x00009888, .val = 0x2A03A500 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x36003248 },
         { .reg = 0x00009888, .val = 0x380024DB },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x220500A0 },
         { .reg = 0x00009888, .val = 0x24062800 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105005 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115005 },
         { .reg = 0x00009888, .val = 0x61111555 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x47101600 },
         { .reg = 0x00009888, .val = 0x4D101000 },
         { .reg = 0x00009888, .val = 0x4F101603 },
         { .reg = 0x00009888, .val = 0x51100003 },
         { .reg = 0x00009888, .val = 0x53101404 },
         { .reg = 0x00009888, .val = 0x55101111 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100005 },
         { .reg = 0x00009888, .val = 0x49100511 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000DC40, .val = 0x003F0000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000180 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000600 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000DC20, .val = 0x00001800 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000DC28, .val = 0x00006000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__sampler_1__avg_gpu_core_frequency__max,tglgt2__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__sampler_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__sampler_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__sampler_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__sampler_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__sampler_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__sampler_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__sampler_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__sampler_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__sampler_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__sampler_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 448, 92, percentage_max_float,tglgt2__sampler_1__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 449, 96, percentage_max_float,tglgt2__sampler_1__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 502, 100, percentage_max_float,tglgt2__sampler_1__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 503, 104, percentage_max_float,tglgt2__sampler_1__sampler03_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 504, 108, percentage_max_float,tglgt2__sampler_1__sampler04_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 505, 112, percentage_max_float,tglgt2__sampler_1__sampler05_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_sampler_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Sampler_2";
   query->symbol_name = "Sampler_2";
   query->guid = "0c3c3235-2e91-4ef0-8562-4ea1501e8612";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C123E00 },
         { .reg = 0x00009888, .val = 0x04143E00 },
         { .reg = 0x00009888, .val = 0x0C323E00 },
         { .reg = 0x00009888, .val = 0x04343E00 },
         { .reg = 0x00009888, .val = 0x0C523E00 },
         { .reg = 0x00009888, .val = 0x04543E00 },
         { .reg = 0x00009888, .val = 0x0C723E00 },
         { .reg = 0x00009888, .val = 0x04743E00 },
         { .reg = 0x00009888, .val = 0x0C923E00 },
         { .reg = 0x00009888, .val = 0x04943E00 },
         { .reg = 0x00009888, .val = 0x0CB23E00 },
         { .reg = 0x00009888, .val = 0x04B43E00 },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x2407002B },
         { .reg = 0x00009888, .val = 0x04120033 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x02124000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x02140013 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x00140000 },
         { .reg = 0x00009888, .val = 0x1A150020 },
         { .reg = 0x00009888, .val = 0x1E320033 },
         { .reg = 0x00009888, .val = 0x20320000 },
         { .reg = 0x00009888, .val = 0x1C324000 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x1C340013 },
         { .reg = 0x00009888, .val = 0x10340000 },
         { .reg = 0x00009888, .val = 0x0E340000 },
         { .reg = 0x00009888, .val = 0x1C358000 },
         { .reg = 0x00009888, .val = 0x1A520033 },
         { .reg = 0x00009888, .val = 0x20520000 },
         { .reg = 0x00009888, .val = 0x18524000 },
         { .reg = 0x00009888, .val = 0x1C53C000 },
         { .reg = 0x00009888, .val = 0x18540013 },
         { .reg = 0x00009888, .val = 0x10540000 },
         { .reg = 0x00009888, .val = 0x0C540000 },
         { .reg = 0x00009888, .val = 0x1C550800 },
         { .reg = 0x00009888, .val = 0x16720033 },
         { .reg = 0x00009888, .val = 0x20720000 },
         { .reg = 0x00009888, .val = 0x14724000 },
         { .reg = 0x00009888, .val = 0x1C733000 },
         { .reg = 0x00009888, .val = 0x14740013 },
         { .reg = 0x00009888, .val = 0x10740000 },
         { .reg = 0x00009888, .val = 0x0A740000 },
         { .reg = 0x00009888, .val = 0x1C750080 },
         { .reg = 0x00009888, .val = 0x12920033 },
         { .reg = 0x00009888, .val = 0x20920000 },
         { .reg = 0x00009888, .val = 0x10924000 },
         { .reg = 0x00009888, .val = 0x1C930C00 },
         { .reg = 0x00009888, .val = 0x10940013 },
         { .reg = 0x00009888, .val = 0x08940000 },
         { .reg = 0x00009888, .val = 0x1C950008 },
         { .reg = 0x00009888, .val = 0x0EB20033 },
         { .reg = 0x00009888, .val = 0x20B20000 },
         { .reg = 0x00009888, .val = 0x00B24000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1CB30200 },
         { .reg = 0x00009888, .val = 0x00B40013 },
         { .reg = 0x00009888, .val = 0x10B40000 },
         { .reg = 0x00009888, .val = 0x18B58000 },
         { .reg = 0x00009888, .val = 0x1E0F0028 },
         { .reg = 0x00009888, .val = 0x14104000 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x2C024000 },
         { .reg = 0x00009888, .val = 0x2E020001 },
         { .reg = 0x00009888, .val = 0x2A03A500 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x36003248 },
         { .reg = 0x00009888, .val = 0x380024DB },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x220500A0 },
         { .reg = 0x00009888, .val = 0x24062800 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105005 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115005 },
         { .reg = 0x00009888, .val = 0x61111555 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x47101600 },
         { .reg = 0x00009888, .val = 0x4D101000 },
         { .reg = 0x00009888, .val = 0x4F101603 },
         { .reg = 0x00009888, .val = 0x51100003 },
         { .reg = 0x00009888, .val = 0x53101404 },
         { .reg = 0x00009888, .val = 0x55101111 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100005 },
         { .reg = 0x00009888, .val = 0x49100511 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000DC40, .val = 0x003F0000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000180 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000600 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000DC20, .val = 0x00001800 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000DC28, .val = 0x00006000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__sampler_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__sampler_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__sampler_2__avg_gpu_core_frequency__max,tglgt2__sampler_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__sampler_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__sampler_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__sampler_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__sampler_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__sampler_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__sampler_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__sampler_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__sampler_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__sampler_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__sampler_2__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 450, 92, percentage_max_float,tglgt2__sampler_2__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 451, 96, percentage_max_float,tglgt2__sampler_2__sampler01_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 506, 100, percentage_max_float,tglgt2__sampler_2__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 507, 104, percentage_max_float,tglgt2__sampler_2__sampler03_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 508, 108, percentage_max_float,tglgt2__sampler_2__sampler04_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 509, 112, percentage_max_float,tglgt2__sampler_2__sampler05_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "ee6f5fa3-13a8-4842-8b34-f7541a0f76a3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2611001C },
         { .reg = 0x00009888, .val = 0x2631001C },
         { .reg = 0x00009888, .val = 0x2651001C },
         { .reg = 0x00009888, .val = 0x2671001C },
         { .reg = 0x00009888, .val = 0x2691001C },
         { .reg = 0x00009888, .val = 0x26B1001C },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x24070002 },
         { .reg = 0x00009888, .val = 0x16110103 },
         { .reg = 0x00009888, .val = 0x1C110104 },
         { .reg = 0x00009888, .val = 0x1E110105 },
         { .reg = 0x00009888, .val = 0x02110106 },
         { .reg = 0x00009888, .val = 0x04110107 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x0A110000 },
         { .reg = 0x00009888, .val = 0x0E110000 },
         { .reg = 0x00009888, .val = 0x00110000 },
         { .reg = 0x00009888, .val = 0x16128000 },
         { .reg = 0x00009888, .val = 0x1C128000 },
         { .reg = 0x00009888, .val = 0x1E128000 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x1C132000 },
         { .reg = 0x00009888, .val = 0x1E130003 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x14310103 },
         { .reg = 0x00009888, .val = 0x06310104 },
         { .reg = 0x00009888, .val = 0x08310105 },
         { .reg = 0x00009888, .val = 0x0A310106 },
         { .reg = 0x00009888, .val = 0x0C310107 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x02310000 },
         { .reg = 0x00009888, .val = 0x04310000 },
         { .reg = 0x00009888, .val = 0x14328000 },
         { .reg = 0x00009888, .val = 0x06328000 },
         { .reg = 0x00009888, .val = 0x08328000 },
         { .reg = 0x00009888, .val = 0x0A328000 },
         { .reg = 0x00009888, .val = 0x0C328000 },
         { .reg = 0x00009888, .val = 0x1C331100 },
         { .reg = 0x00009888, .val = 0x16338000 },
         { .reg = 0x00009888, .val = 0x18338000 },
         { .reg = 0x00009888, .val = 0x1A338000 },
         { .reg = 0x00009888, .val = 0x12510103 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x08510000 },
         { .reg = 0x00009888, .val = 0x12528000 },
         { .reg = 0x00009888, .val = 0x1C530800 },
         { .reg = 0x00009888, .val = 0x10710103 },
         { .reg = 0x00009888, .val = 0x08710000 },
         { .reg = 0x00009888, .val = 0x10728000 },
         { .reg = 0x00009888, .val = 0x1C730400 },
         { .reg = 0x00009888, .val = 0x0E910103 },
         { .reg = 0x00009888, .val = 0x10910000 },
         { .reg = 0x00009888, .val = 0x06910000 },
         { .reg = 0x00009888, .val = 0x0E928000 },
         { .reg = 0x00009888, .val = 0x1C930200 },
         { .reg = 0x00009888, .val = 0x00B10103 },
         { .reg = 0x00009888, .val = 0x10B10000 },
         { .reg = 0x00009888, .val = 0x00B28000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1C0F8000 },
         { .reg = 0x00009888, .val = 0x10104000 },
         { .reg = 0x00009888, .val = 0x10024000 },
         { .reg = 0x00009888, .val = 0x1C032000 },
         { .reg = 0x00009888, .val = 0x1E034000 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x360026CA },
         { .reg = 0x00009888, .val = 0x38002402 },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C004000 },
         { .reg = 0x00009888, .val = 0x1E004000 },
         { .reg = 0x00009888, .val = 0x34001200 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x240582C0 },
         { .reg = 0x00009888, .val = 0x26050002 },
         { .reg = 0x00009888, .val = 0x2205FFA0 },
         { .reg = 0x00009888, .val = 0x24060020 },
         { .reg = 0x00009888, .val = 0x100A8000 },
         { .reg = 0x00009888, .val = 0x120A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101415 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D140033 },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115555 },
         { .reg = 0x00009888, .val = 0x61111415 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x47101600 },
         { .reg = 0x00009888, .val = 0x4D100111 },
         { .reg = 0x00009888, .val = 0x4F100006 },
         { .reg = 0x00009888, .val = 0x51101114 },
         { .reg = 0x00009888, .val = 0x53100001 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55101110 },
         { .reg = 0x00009888, .val = 0x57100001 },
         { .reg = 0x00009888, .val = 0x49101111 },
         { .reg = 0x00009888, .val = 0x4B101111 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000DC00, .val = 0x00000002 },
         { .reg = 0x0000DC04, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000DC08, .val = 0x00000002 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000DC10, .val = 0x00000002 },
         { .reg = 0x0000DC14, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00000002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000DC20, .val = 0x00000002 },
         { .reg = 0x0000DC24, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000DC28, .val = 0x00000002 },
         { .reg = 0x0000DC2C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00007800 },
         { .reg = 0x0000D974, .val = 0x0000F0FF },
         { .reg = 0x0000DC30, .val = 0x00007800 },
         { .reg = 0x0000DC34, .val = 0x0000F0FF },
         { .reg = 0x0000D978, .val = 0x00078000 },
         { .reg = 0x0000D97C, .val = 0x00000FFF },
         { .reg = 0x0000DC38, .val = 0x00078000 },
         { .reg = 0x0000DC3C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__tdl_1__avg_gpu_core_frequency__max,tglgt2__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__tdl_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 452, 92, percentage_max_float,tglgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 453, 96, percentage_max_float,tglgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 510, 100, percentage_max_float,tglgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 511, 104, percentage_max_float,tglgt2__tdl_1__non_ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 512, 108, percentage_max_float,tglgt2__tdl_1__non_ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 513, 112, percentage_max_float,tglgt2__tdl_1__non_ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 456, 116, percentage_max_float,tglgt2__tdl_1__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 457, 120, percentage_max_float,tglgt2__tdl_1__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 458, 124, percentage_max_float,tglgt2__tdl_1__thread_header00_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 459, 128, percentage_max_float,tglgt2__tdl_1__thread_header00_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 460, 132, percentage_max_float,tglgt2__tdl_1__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 461, 136, percentage_max_float,tglgt2__tdl_1__thread_header01_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 462, 140, percentage_max_float,tglgt2__tdl_1__thread_header01_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 463, 144, percentage_max_float,tglgt2__tdl_1__thread_header01_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 464, 148, percentage_max_float,tglgt2__tdl_1__thread_header00_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 465, 152, percentage_max_float,tglgt2__tdl_1__thread_header01_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 24);

   query->name = "TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "f1577929-9215-488b-9899-d12b6e799743";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x24110340 },
         { .reg = 0x00009888, .val = 0x24310340 },
         { .reg = 0x00009888, .val = 0x24510340 },
         { .reg = 0x00009888, .val = 0x24710340 },
         { .reg = 0x00009888, .val = 0x24910340 },
         { .reg = 0x00009888, .val = 0x24B10340 },
         { .reg = 0x00009888, .val = 0x26B1001C },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x2407002B },
         { .reg = 0x00009888, .val = 0x2207FF00 },
         { .reg = 0x00009888, .val = 0x021100F3 },
         { .reg = 0x00009888, .val = 0x041100F2 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x00110000 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x1C3100F3 },
         { .reg = 0x00009888, .val = 0x1E3100F2 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x0E310000 },
         { .reg = 0x00009888, .val = 0x1C328000 },
         { .reg = 0x00009888, .val = 0x1E328000 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x185100F3 },
         { .reg = 0x00009888, .val = 0x1A5100F2 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x0C510000 },
         { .reg = 0x00009888, .val = 0x18528000 },
         { .reg = 0x00009888, .val = 0x1A528000 },
         { .reg = 0x00009888, .val = 0x1C53C000 },
         { .reg = 0x00009888, .val = 0x147100F3 },
         { .reg = 0x00009888, .val = 0x167100F2 },
         { .reg = 0x00009888, .val = 0x10710000 },
         { .reg = 0x00009888, .val = 0x0A710000 },
         { .reg = 0x00009888, .val = 0x14728000 },
         { .reg = 0x00009888, .val = 0x16728000 },
         { .reg = 0x00009888, .val = 0x1C733000 },
         { .reg = 0x00009888, .val = 0x109100F3 },
         { .reg = 0x00009888, .val = 0x129100F2 },
         { .reg = 0x00009888, .val = 0x08910000 },
         { .reg = 0x00009888, .val = 0x10928000 },
         { .reg = 0x00009888, .val = 0x12928000 },
         { .reg = 0x00009888, .val = 0x1C930C00 },
         { .reg = 0x00009888, .val = 0x00B100F3 },
         { .reg = 0x00009888, .val = 0x0EB100F2 },
         { .reg = 0x00009888, .val = 0x06B10104 },
         { .reg = 0x00009888, .val = 0x08B10105 },
         { .reg = 0x00009888, .val = 0x0AB10106 },
         { .reg = 0x00009888, .val = 0x0CB10107 },
         { .reg = 0x00009888, .val = 0x10B10000 },
         { .reg = 0x00009888, .val = 0x02B10000 },
         { .reg = 0x00009888, .val = 0x04B10000 },
         { .reg = 0x00009888, .val = 0x00B28000 },
         { .reg = 0x00009888, .val = 0x0EB28000 },
         { .reg = 0x00009888, .val = 0x06B28000 },
         { .reg = 0x00009888, .val = 0x08B28000 },
         { .reg = 0x00009888, .val = 0x0AB28000 },
         { .reg = 0x00009888, .val = 0x0CB28000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1CB30300 },
         { .reg = 0x00009888, .val = 0x16B38000 },
         { .reg = 0x00009888, .val = 0x18B38000 },
         { .reg = 0x00009888, .val = 0x1AB38000 },
         { .reg = 0x00009888, .val = 0x1E0F0028 },
         { .reg = 0x00009888, .val = 0x14104000 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x2C024000 },
         { .reg = 0x00009888, .val = 0x2E020001 },
         { .reg = 0x00009888, .val = 0x2A03A500 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x36003249 },
         { .reg = 0x00009888, .val = 0x380024DB },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C004000 },
         { .reg = 0x00009888, .val = 0x1E002000 },
         { .reg = 0x00009888, .val = 0x34000900 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x06014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x220500A0 },
         { .reg = 0x00009888, .val = 0x24062800 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115555 },
         { .reg = 0x00009888, .val = 0x61111555 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x47101600 },
         { .reg = 0x00009888, .val = 0x4D100606 },
         { .reg = 0x00009888, .val = 0x4F100606 },
         { .reg = 0x00009888, .val = 0x51100006 },
         { .reg = 0x00009888, .val = 0x53100400 },
         { .reg = 0x00009888, .val = 0x55101114 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100001 },
         { .reg = 0x00009888, .val = 0x49100111 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000000 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000000 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000000 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000000 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000DC20, .val = 0x00000000 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000DC28, .val = 0x00000000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00078000 },
         { .reg = 0x0000D974, .val = 0x00000FFF },
         { .reg = 0x0000DC30, .val = 0x00078000 },
         { .reg = 0x0000DC34, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__tdl_2__avg_gpu_core_frequency__max,tglgt2__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__tdl_2__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 454, 92, percentage_max_float,tglgt2__tdl_2__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 455, 96, percentage_max_float,tglgt2__tdl_2__ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 514, 100, percentage_max_float,tglgt2__tdl_2__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 515, 104, percentage_max_float,tglgt2__tdl_2__ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 516, 108, percentage_max_float,tglgt2__tdl_2__ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 517, 112, percentage_max_float,tglgt2__tdl_2__ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 518, 116, percentage_max_float,tglgt2__tdl_2__thread_header05_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 519, 120, percentage_max_float,tglgt2__tdl_2__thread_header05_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 520, 124, percentage_max_float,tglgt2__tdl_2__thread_header05_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 521, 128, percentage_max_float,tglgt2__tdl_2__thread_header05_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 522, 132, percentage_max_float,tglgt2__tdl_2__thread_header05_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_tdl_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 28);

   query->name = "TDL_3";
   query->symbol_name = "TDL_3";
   query->guid = "d5890d02-b2be-4742-a16e-17190a92a301";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2651001C },
         { .reg = 0x00009888, .val = 0x2671001C },
         { .reg = 0x00009888, .val = 0x2691001C },
         { .reg = 0x00009888, .val = 0x24072A80 },
         { .reg = 0x00009888, .val = 0x06510107 },
         { .reg = 0x00009888, .val = 0x08510106 },
         { .reg = 0x00009888, .val = 0x0A510105 },
         { .reg = 0x00009888, .val = 0x0C510104 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x02510000 },
         { .reg = 0x00009888, .val = 0x04510000 },
         { .reg = 0x00009888, .val = 0x06528000 },
         { .reg = 0x00009888, .val = 0x08528000 },
         { .reg = 0x00009888, .val = 0x0A528000 },
         { .reg = 0x00009888, .val = 0x0C528000 },
         { .reg = 0x00009888, .val = 0x16538000 },
         { .reg = 0x00009888, .val = 0x18538000 },
         { .reg = 0x00009888, .val = 0x1A538000 },
         { .reg = 0x00009888, .val = 0x1C530100 },
         { .reg = 0x00009888, .val = 0x1C710107 },
         { .reg = 0x00009888, .val = 0x1E710106 },
         { .reg = 0x00009888, .val = 0x02710105 },
         { .reg = 0x00009888, .val = 0x04710104 },
         { .reg = 0x00009888, .val = 0x10710000 },
         { .reg = 0x00009888, .val = 0x0E710000 },
         { .reg = 0x00009888, .val = 0x00710000 },
         { .reg = 0x00009888, .val = 0x1C728000 },
         { .reg = 0x00009888, .val = 0x1E728000 },
         { .reg = 0x00009888, .val = 0x02728000 },
         { .reg = 0x00009888, .val = 0x04728000 },
         { .reg = 0x00009888, .val = 0x1E730003 },
         { .reg = 0x00009888, .val = 0x12738000 },
         { .reg = 0x00009888, .val = 0x14738000 },
         { .reg = 0x00009888, .val = 0x14910107 },
         { .reg = 0x00009888, .val = 0x16910106 },
         { .reg = 0x00009888, .val = 0x18910105 },
         { .reg = 0x00009888, .val = 0x1A910104 },
         { .reg = 0x00009888, .val = 0x10910000 },
         { .reg = 0x00009888, .val = 0x0A910000 },
         { .reg = 0x00009888, .val = 0x0C910000 },
         { .reg = 0x00009888, .val = 0x14928000 },
         { .reg = 0x00009888, .val = 0x16928000 },
         { .reg = 0x00009888, .val = 0x18928000 },
         { .reg = 0x00009888, .val = 0x1A928000 },
         { .reg = 0x00009888, .val = 0x1C93F000 },
         { .reg = 0x00009888, .val = 0x1E0F2800 },
         { .reg = 0x00009888, .val = 0x1C0F000A },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x02104000 },
         { .reg = 0x00009888, .val = 0x04104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x02034000 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x06038000 },
         { .reg = 0x00009888, .val = 0x08038000 },
         { .reg = 0x00009888, .val = 0x0A038000 },
         { .reg = 0x00009888, .val = 0x18034000 },
         { .reg = 0x00009888, .val = 0x36001003 },
         { .reg = 0x00009888, .val = 0x38003649 },
         { .reg = 0x00009888, .val = 0x1A006000 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x1E006000 },
         { .reg = 0x00009888, .val = 0x34001B00 },
         { .reg = 0x00009888, .val = 0x2A015500 },
         { .reg = 0x00009888, .val = 0x2206AA00 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009888, .val = 0x020A8000 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5D101554 },
         { .reg = 0x00009888, .val = 0x5B100555 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x61111554 },
         { .reg = 0x00009888, .val = 0x5F110555 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x51100600 },
         { .reg = 0x00009888, .val = 0x53100606 },
         { .reg = 0x00009888, .val = 0x55100006 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100404 },
         { .reg = 0x00009888, .val = 0x4D100404 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00070000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000DC00, .val = 0x00078000 },
         { .reg = 0x0000DC04, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000DC08, .val = 0x00007800 },
         { .reg = 0x0000DC0C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000DC10, .val = 0x00000780 },
         { .reg = 0x0000DC14, .val = 0x0000FF0F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__tdl_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__tdl_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__tdl_3__avg_gpu_core_frequency__max,tglgt2__tdl_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__tdl_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__tdl_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__tdl_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__tdl_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__tdl_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__tdl_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__tdl_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,tglgt2__tdl_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,tglgt2__tdl_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,tglgt2__tdl_3__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 523, 92, percentage_max_float,tglgt2__tdl_3__thread_header02_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 524, 96, percentage_max_float,tglgt2__tdl_3__thread_header03_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 525, 100, percentage_max_float,tglgt2__tdl_3__thread_header04_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 526, 104, percentage_max_float,tglgt2__tdl_3__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 527, 108, percentage_max_float,tglgt2__tdl_3__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 528, 112, percentage_max_float,tglgt2__tdl_3__thread_header02_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 529, 116, percentage_max_float,tglgt2__tdl_3__thread_header02_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 530, 120, percentage_max_float,tglgt2__tdl_3__thread_header03_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 531, 124, percentage_max_float,tglgt2__tdl_3__thread_header03_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 532, 128, percentage_max_float,tglgt2__tdl_3__thread_header03_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 533, 132, percentage_max_float,tglgt2__tdl_3__thread_header03_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 534, 136, percentage_max_float,tglgt2__tdl_3__thread_header04_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 535, 140, percentage_max_float,tglgt2__tdl_3__thread_header04_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 536, 144, percentage_max_float,tglgt2__tdl_3__thread_header04_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 537, 148, percentage_max_float,tglgt2__tdl_3__thread_header04_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 22);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "19fe64eb-ac4f-45c6-b2b9-af728b21753b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x0E101200 },
         { .reg = 0x00009888, .val = 0x040E0043 },
         { .reg = 0x00009888, .val = 0x0A0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x0C0E0000 },
         { .reg = 0x00009888, .val = 0x1C0F0104 },
         { .reg = 0x00009888, .val = 0x08100053 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x04104000 },
         { .reg = 0x00009888, .val = 0x0A104000 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08024000 },
         { .reg = 0x00009888, .val = 0x0A024000 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x08034000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x34001B00 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x15102400 },
         { .reg = 0x00009888, .val = 0x230B0120 },
         { .reg = 0x00009888, .val = 0x15182400 },
         { .reg = 0x00009888, .val = 0x232B0120 },
         { .reg = 0x00009888, .val = 0x17100023 },
         { .reg = 0x00009888, .val = 0x11100000 },
         { .reg = 0x00009888, .val = 0x5D101000 },
         { .reg = 0x00009888, .val = 0x5B100545 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x1B140C00 },
         { .reg = 0x00009888, .val = 0x61112000 },
         { .reg = 0x00009888, .val = 0x5F110945 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x13138000 },
         { .reg = 0x00009888, .val = 0x1B0D0040 },
         { .reg = 0x00009888, .val = 0x1F0B00D3 },
         { .reg = 0x00009888, .val = 0x190B0000 },
         { .reg = 0x00009888, .val = 0x170B0000 },
         { .reg = 0x00009888, .val = 0x1B170002 },
         { .reg = 0x00009888, .val = 0x0D174000 },
         { .reg = 0x00009888, .val = 0x071800A3 },
         { .reg = 0x00009888, .val = 0x11180000 },
         { .reg = 0x00009888, .val = 0x032D4000 },
         { .reg = 0x00009888, .val = 0x032B00D3 },
         { .reg = 0x00009888, .val = 0x192B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x55103000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49107003 },
         { .reg = 0x00009888, .val = 0x4B100402 },
         { .reg = 0x00009888, .val = 0x4D100230 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00024002 },
         { .reg = 0x0000D944, .val = 0x0000B7FF },
         { .reg = 0x0000DC00, .val = 0x00024002 },
         { .reg = 0x0000DC04, .val = 0x0000B7FF },
         { .reg = 0x0000D948, .val = 0x0007F000 },
         { .reg = 0x0000D94C, .val = 0x000001FF },
         { .reg = 0x0000DC08, .val = 0x0007F000 },
         { .reg = 0x0000DC0C, .val = 0x000001FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__gpu_busyness__avg_gpu_core_frequency__max,tglgt2__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,tglgt2__gpu_busyness__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,tglgt2__gpu_busyness__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,tglgt2__gpu_busyness__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,tglgt2__gpu_busyness__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,tglgt2__gpu_busyness__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,tglgt2__gpu_busyness__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,tglgt2__gpu_busyness__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,tglgt2__gpu_busyness__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,tglgt2__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 88, percentage_max_float,tglgt2__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 92, percentage_max_float,tglgt2__gpu_busyness__compute_busy__read);

      intel_perf_query_add_counter_float(query, 414, 96, percentage_max_float,tglgt2__gpu_busyness__posh_engine_busy__read);

      intel_perf_query_add_counter_float(query, 313, 100, percentage_max_float,tglgt2__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 312, 104, percentage_max_float,tglgt2__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 310, 108, percentage_max_float,tglgt2__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 112, percentage_max_float,tglgt2__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 467, 116, percentage_max_float,tglgt2__gpu_busyness__render_and_compute_busy__read);

      intel_perf_query_add_counter_float(query, 468, 120, percentage_max_float,tglgt2__gpu_busyness__any_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_eu_activity1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity1";
   query->symbol_name = "EuActivity1";
   query->guid = "414ff049-80d3-48c0-b79a-bd8eed097a06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47103000 },
         { .reg = 0x00009888, .val = 0x49103535 },
         { .reg = 0x00009888, .val = 0x4B103535 },
         { .reg = 0x00009888, .val = 0x4D100535 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00810710 },
         { .reg = 0x0000E558, .val = 0x00A10910 },
         { .reg = 0x0000E658, .val = 0x00850750 },
         { .reg = 0x0000E758, .val = 0x00A50950 },
         { .reg = 0x0000E45C, .val = 0x00802702 },
         { .reg = 0x0000E55C, .val = 0x00A02902 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__eu_activity1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__eu_activity1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__eu_activity1__avg_gpu_core_frequency__max,tglgt2__eu_activity1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__eu_activity1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__eu_activity1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__eu_activity1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__eu_activity1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__eu_activity1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__eu_activity1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__eu_activity1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt2__eu_activity1__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt2__eu_activity1__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt2__eu_activity1__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt2__eu_activity1__gti_read_throughput__max,tglgt2__eu_activity1__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt2__eu_activity1__gti_write_throughput__max,tglgt2__eu_activity1__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 469, 112, percentage_max_float,tglgt2__eu_activity1__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 470, 116, percentage_max_float,tglgt2__eu_activity1__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 153, 120, percentage_max_float,tglgt2__eu_activity1__eu_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_eu_activity2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity2";
   query->symbol_name = "EuActivity2";
   query->guid = "fb65c819-7ac2-4c69-aa9d-b72a18440705";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47103000 },
         { .reg = 0x00009888, .val = 0x49103535 },
         { .reg = 0x00009888, .val = 0x4B103535 },
         { .reg = 0x00009888, .val = 0x4D100535 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00862762 },
         { .reg = 0x0000E558, .val = 0x00A62962 },
         { .reg = 0x0000E658, .val = 0x00860760 },
         { .reg = 0x0000E758, .val = 0x00A60960 },
         { .reg = 0x0000E45C, .val = 0x00861761 },
         { .reg = 0x0000E55C, .val = 0x00A61961 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__eu_activity2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__eu_activity2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__eu_activity2__avg_gpu_core_frequency__max,tglgt2__eu_activity2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__eu_activity2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__eu_activity2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__eu_activity2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__eu_activity2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__eu_activity2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__eu_activity2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__eu_activity2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt2__eu_activity2__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt2__eu_activity2__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt2__eu_activity2__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt2__eu_activity2__gti_read_throughput__max,tglgt2__eu_activity2__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt2__eu_activity2__gti_write_throughput__max,tglgt2__eu_activity2__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 471, 112, percentage_max_float,tglgt2__eu_activity2__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 472, 116, percentage_max_float,tglgt2__eu_activity2__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 473, 120, percentage_max_float,tglgt2__eu_activity2__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_eu_activity3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity3";
   query->symbol_name = "EuActivity3";
   query->guid = "7e1c6469-9de7-491a-a7c5-1bd8f9966826";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47103000 },
         { .reg = 0x00009888, .val = 0x49103535 },
         { .reg = 0x00009888, .val = 0x4B103535 },
         { .reg = 0x00009888, .val = 0x4D100535 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00811711 },
         { .reg = 0x0000E558, .val = 0x00A11911 },
         { .reg = 0x0000E658, .val = 0x00851751 },
         { .reg = 0x0000E758, .val = 0x00A51951 },
         { .reg = 0x0000E45C, .val = 0x00852752 },
         { .reg = 0x0000E55C, .val = 0x00A52952 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__eu_activity3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__eu_activity3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__eu_activity3__avg_gpu_core_frequency__max,tglgt2__eu_activity3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__eu_activity3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__eu_activity3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__eu_activity3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__eu_activity3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__eu_activity3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__eu_activity3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__eu_activity3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt2__eu_activity3__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt2__eu_activity3__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt2__eu_activity3__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt2__eu_activity3__gti_read_throughput__max,tglgt2__eu_activity3__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt2__eu_activity3__gti_write_throughput__max,tglgt2__eu_activity3__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 474, 112, percentage_max_float,tglgt2__eu_activity3__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 475, 116, percentage_max_float,tglgt2__eu_activity3__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 129, 120, percentage_max_float,tglgt2__eu_activity3__ps_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_eu_activity4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity4";
   query->symbol_name = "EuActivity4";
   query->guid = "a43f80cd-5cc1-4a2c-a750-40594af2b661";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47103000 },
         { .reg = 0x00009888, .val = 0x49103535 },
         { .reg = 0x00009888, .val = 0x4B103535 },
         { .reg = 0x00009888, .val = 0x4D100535 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00820720 },
         { .reg = 0x0000E558, .val = 0x00A20920 },
         { .reg = 0x0000E658, .val = 0x00830730 },
         { .reg = 0x0000E758, .val = 0x00A30930 },
         { .reg = 0x0000E45C, .val = 0x00812712 },
         { .reg = 0x0000E55C, .val = 0x00A12912 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__eu_activity4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__eu_activity4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__eu_activity4__avg_gpu_core_frequency__max,tglgt2__eu_activity4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__eu_activity4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__eu_activity4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__eu_activity4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__eu_activity4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__eu_activity4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__eu_activity4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__eu_activity4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt2__eu_activity4__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt2__eu_activity4__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt2__eu_activity4__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt2__eu_activity4__gti_read_throughput__max,tglgt2__eu_activity4__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt2__eu_activity4__gti_write_throughput__max,tglgt2__eu_activity4__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 476, 112, percentage_max_float,tglgt2__eu_activity4__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 477, 116, percentage_max_float,tglgt2__eu_activity4__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 126, 120, percentage_max_float,tglgt2__eu_activity4__vs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_eu_activity5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity5";
   query->symbol_name = "EuActivity5";
   query->guid = "7e6e555c-aa5b-4c8d-992a-454a5a335c6e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47103000 },
         { .reg = 0x00009888, .val = 0x49103535 },
         { .reg = 0x00009888, .val = 0x4B103535 },
         { .reg = 0x00009888, .val = 0x4D100535 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00821721 },
         { .reg = 0x0000E558, .val = 0x00A21921 },
         { .reg = 0x0000E658, .val = 0x00831731 },
         { .reg = 0x0000E758, .val = 0x00A31931 },
         { .reg = 0x0000E45C, .val = 0x00822722 },
         { .reg = 0x0000E55C, .val = 0x00A22922 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__eu_activity5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__eu_activity5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__eu_activity5__avg_gpu_core_frequency__max,tglgt2__eu_activity5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__eu_activity5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__eu_activity5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__eu_activity5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__eu_activity5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__eu_activity5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__eu_activity5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__eu_activity5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt2__eu_activity5__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt2__eu_activity5__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt2__eu_activity5__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt2__eu_activity5__gti_read_throughput__max,tglgt2__eu_activity5__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt2__eu_activity5__gti_write_throughput__max,tglgt2__eu_activity5__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 478, 112, percentage_max_float,tglgt2__eu_activity5__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 479, 116, percentage_max_float,tglgt2__eu_activity5__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 480, 120, percentage_max_float,tglgt2__eu_activity5__hs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_eu_activity6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity6";
   query->symbol_name = "EuActivity6";
   query->guid = "f3723f39-ecf4-4ff2-a4c4-80e87876b86f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47103000 },
         { .reg = 0x00009888, .val = 0x49103535 },
         { .reg = 0x00009888, .val = 0x4B103535 },
         { .reg = 0x00009888, .val = 0x4D100535 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00840740 },
         { .reg = 0x0000E558, .val = 0x00A40940 },
         { .reg = 0x0000E658, .val = 0x00841741 },
         { .reg = 0x0000E758, .val = 0x00A41941 },
         { .reg = 0x0000E45C, .val = 0x00842742 },
         { .reg = 0x0000E55C, .val = 0x00A42942 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__eu_activity6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__eu_activity6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__eu_activity6__avg_gpu_core_frequency__max,tglgt2__eu_activity6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__eu_activity6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__eu_activity6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__eu_activity6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__eu_activity6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__eu_activity6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__eu_activity6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__eu_activity6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt2__eu_activity6__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt2__eu_activity6__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt2__eu_activity6__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt2__eu_activity6__gti_read_throughput__max,tglgt2__eu_activity6__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt2__eu_activity6__gti_write_throughput__max,tglgt2__eu_activity6__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 481, 112, percentage_max_float,tglgt2__eu_activity6__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 482, 116, percentage_max_float,tglgt2__eu_activity6__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 483, 120, percentage_max_float,tglgt2__eu_activity6__gs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_eu_activity7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "EuActivity7";
   query->symbol_name = "EuActivity7";
   query->guid = "c0d2cd0a-e2be-4b12-916d-2f3aba0ebf9e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47103000 },
         { .reg = 0x00009888, .val = 0x49103535 },
         { .reg = 0x00009888, .val = 0x4B103535 },
         { .reg = 0x00009888, .val = 0x4D100535 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00803703 },
         { .reg = 0x0000E558, .val = 0x00A03903 },
         { .reg = 0x0000E658, .val = 0x00800700 },
         { .reg = 0x0000E758, .val = 0x00A00900 },
         { .reg = 0x0000E45C, .val = 0x00801701 },
         { .reg = 0x0000E55C, .val = 0x00A01901 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__eu_activity7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__eu_activity7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__eu_activity7__avg_gpu_core_frequency__max,tglgt2__eu_activity7__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__eu_activity7__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__eu_activity7__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__eu_activity7__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__eu_activity7__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__eu_activity7__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__eu_activity7__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__eu_activity7__cs_threads__read);

      intel_perf_query_add_counter_float(query, 484, 80, percentage_max_float,tglgt2__eu_activity7__fpu_active__read);

      intel_perf_query_add_counter_float(query, 485, 84, percentage_max_float,tglgt2__eu_activity7__em_active__read);

      intel_perf_query_add_counter_float(query, 486, 88, percentage_max_float,tglgt2__eu_activity7__eu_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 152, 92, tglgt2__eu_activity7__eu_avg_ipc_rate__max,tglgt2__eu_activity7__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 309, 96, percentage_max_float,tglgt2__eu_activity7__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 100, percentage_max_float,tglgt2__eu_activity7__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 104, percentage_max_float,tglgt2__eu_activity7__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 112, tglgt2__eu_activity7__gti_read_throughput__max,tglgt2__eu_activity7__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 120, tglgt2__eu_activity7__gti_write_throughput__max,tglgt2__eu_activity7__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_eu_activity8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 16);

   query->name = "EuActivity8";
   query->symbol_name = "EuActivity8";
   query->guid = "1fbbd218-693c-4035-b4c0-ce4dd139d828";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47103000 },
         { .reg = 0x00009888, .val = 0x49103535 },
         { .reg = 0x00009888, .val = 0x4B103535 },
         { .reg = 0x00009888, .val = 0x4D100535 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00832732 },
         { .reg = 0x0000E558, .val = 0x00A32932 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__eu_activity8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__eu_activity8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__eu_activity8__avg_gpu_core_frequency__max,tglgt2__eu_activity8__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,tglgt2__eu_activity8__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,tglgt2__eu_activity8__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,tglgt2__eu_activity8__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,tglgt2__eu_activity8__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,tglgt2__eu_activity8__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,tglgt2__eu_activity8__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,tglgt2__eu_activity8__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,tglgt2__eu_activity8__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,tglgt2__eu_activity8__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,tglgt2__eu_activity8__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, tglgt2__eu_activity8__gti_read_throughput__max,tglgt2__eu_activity8__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, tglgt2__eu_activity8__gti_write_throughput__max,tglgt2__eu_activity8__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 487, 112, percentage_max_float,tglgt2__eu_activity8__ds_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
tglgt2_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "6607f034-d053-40d1-8215-67c07f3041bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x280E0000 },
         { .reg = 0x00009888, .val = 0x1E0E0147 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020100 },
         { .reg = 0x00009888, .val = 0x2C030004 },
         { .reg = 0x00009888, .val = 0x38003000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x49110000 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x1D140020 },
         { .reg = 0x00009888, .val = 0x1D1103A3 },
         { .reg = 0x00009888, .val = 0x01110000 },
         { .reg = 0x00009888, .val = 0x61111000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100630 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000DC00, .val = 0x00000004 },
         { .reg = 0x0000DC04, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000DC08, .val = 0x00000003 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000DC10, .val = 0x00000007 },
         { .reg = 0x0000DC14, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00100002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000DC20, .val = 0x00100002 },
         { .reg = 0x0000DC24, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000DC28, .val = 0x00100082 },
         { .reg = 0x0000DC2C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000DC30, .val = 0x001000C2 },
         { .reg = 0x0000DC34, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
         { .reg = 0x0000DC38, .val = 0x00100001 },
         { .reg = 0x0000DC3C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,tglgt2__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,tglgt2__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, tglgt2__test_oa__avg_gpu_core_frequency__max,tglgt2__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,tglgt2__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,tglgt2__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,tglgt2__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,tglgt2__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 415, 56, NULL,tglgt2__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 416, 64, NULL,tglgt2__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 417, 72, NULL,tglgt2__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 418, 80, NULL,tglgt2__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 488, 88, NULL,tglgt2__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 489, 96, NULL,tglgt2__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_tglgt2(struct intel_perf_config *perf)
{
   tglgt2_register_render_basic_counter_query(perf);
   tglgt2_register_compute_basic_counter_query(perf);
   tglgt2_register_render_pipe_profile_counter_query(perf);
   tglgt2_register_hdc_and_sf_counter_query(perf);
   tglgt2_register_rasterizer_and_pixel_backend_counter_query(perf);
   tglgt2_register_l3_1_counter_query(perf);
   tglgt2_register_l3_2_counter_query(perf);
   tglgt2_register_l3_3_counter_query(perf);
   tglgt2_register_l3_4_counter_query(perf);
   tglgt2_register_l3_5_counter_query(perf);
   tglgt2_register_l3_6_counter_query(perf);
   tglgt2_register_sampler_1_counter_query(perf);
   tglgt2_register_sampler_2_counter_query(perf);
   tglgt2_register_tdl_1_counter_query(perf);
   tglgt2_register_tdl_2_counter_query(perf);
   tglgt2_register_tdl_3_counter_query(perf);
   tglgt2_register_gpu_busyness_counter_query(perf);
   tglgt2_register_eu_activity1_counter_query(perf);
   tglgt2_register_eu_activity2_counter_query(perf);
   tglgt2_register_eu_activity3_counter_query(perf);
   tglgt2_register_eu_activity4_counter_query(perf);
   tglgt2_register_eu_activity5_counter_query(perf);
   tglgt2_register_eu_activity6_counter_query(perf);
   tglgt2_register_eu_activity7_counter_query(perf);
   tglgt2_register_eu_activity8_counter_query(perf);
   tglgt2_register_test_oa_counter_query(perf);
}


static void
rkl_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 34);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "5b492c36-73f7-4827-83b3-c6863697ec51";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14150001 },
         { .reg = 0x00009888, .val = 0x16150020 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0E124000 },
         { .reg = 0x00009888, .val = 0x10124000 },
         { .reg = 0x00009888, .val = 0x12124000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x1C130E00 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x06157000 },
         { .reg = 0x00009888, .val = 0x08157151 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x18150000 },
         { .reg = 0x00009888, .val = 0x1C150000 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x100B4000 },
         { .reg = 0x00009888, .val = 0x120B4000 },
         { .reg = 0x00009888, .val = 0x100C8000 },
         { .reg = 0x00009888, .val = 0x1E0C000E },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x0A0D8000 },
         { .reg = 0x00009888, .val = 0x0C0DC000 },
         { .reg = 0x00009888, .val = 0x000E8000 },
         { .reg = 0x00009888, .val = 0x0E0E8000 },
         { .reg = 0x00009888, .val = 0x100E8000 },
         { .reg = 0x00009888, .val = 0x120E8000 },
         { .reg = 0x00009888, .val = 0x000F4000 },
         { .reg = 0x00009888, .val = 0x060F8000 },
         { .reg = 0x00009888, .val = 0x080FC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D47 },
         { .reg = 0x00009888, .val = 0x09151536 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B1050BB },
         { .reg = 0x00009888, .val = 0x5D102C01 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x61110001 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x1F150137 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x0F168000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x1D350137 },
         { .reg = 0x00009888, .val = 0x03350147 },
         { .reg = 0x00009888, .val = 0x07350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x0F364000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55101810 },
         { .reg = 0x00009888, .val = 0x57100008 },
         { .reg = 0x00009888, .val = 0x49101818 },
         { .reg = 0x00009888, .val = 0x4B100818 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__render_basic__avg_gpu_core_frequency__max,rkl__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,rkl__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,rkl__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,rkl__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,rkl__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,rkl__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,rkl__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,rkl__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,rkl__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,rkl__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 84, percentage_max_float,rkl__render_basic__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 333, 88, percentage_max_float,rkl__render_basic__sampler00_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 435, 92, percentage_max_float,rkl__render_basic__sampler00_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 133, 96, percentage_max_float,rkl__render_basic__samplers_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 149, 100, percentage_max_float,rkl__render_basic__sampler_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 104, NULL,rkl__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 112, NULL,rkl__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 120, NULL,rkl__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 128, NULL,rkl__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 136, NULL,rkl__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 144, NULL,rkl__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 152, NULL,rkl__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 160, NULL,rkl__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 168, NULL,rkl__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 176, rkl__render_basic__slm_bytes_read__max,rkl__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 184, rkl__render_basic__slm_bytes_written__max,rkl__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 192, NULL,rkl__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 200, NULL,rkl__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 208, rkl__render_basic__l3_shader_throughput__max,rkl__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 216, NULL,rkl__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 224, rkl__render_basic__gti_read_throughput__max,rkl__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 232, rkl__render_basic__gti_write_throughput__max,rkl__render_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 30);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "09740672-ccc3-48da-a5bc-64994fe3a0a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__compute_basic__avg_gpu_core_frequency__max,rkl__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,rkl__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,rkl__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,rkl__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,rkl__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,rkl__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,rkl__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,rkl__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,rkl__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,rkl__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, rkl__compute_basic__slm_bytes_read__max,rkl__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, rkl__compute_basic__slm_bytes_written__max,rkl__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,rkl__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,rkl__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, rkl__compute_basic__l3_shader_throughput__max,rkl__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,rkl__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 216, rkl__compute_basic__gti_read_throughput__max,rkl__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 224, rkl__compute_basic__gti_write_throughput__max,rkl__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "833bb0f2-9483-498e-b3bf-ebf026a6301a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00123E00 },
         { .reg = 0x00009888, .val = 0x060B00B3 },
         { .reg = 0x00009888, .val = 0x140B7C00 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x120C0320 },
         { .reg = 0x00009888, .val = 0x040D3E00 },
         { .reg = 0x00009888, .val = 0x000D0000 },
         { .reg = 0x00009888, .val = 0x280D0000 },
         { .reg = 0x00009888, .val = 0x2A0E03E0 },
         { .reg = 0x00009888, .val = 0x10087C00 },
         { .reg = 0x00009888, .val = 0x1E120002 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x1E130002 },
         { .reg = 0x00009888, .val = 0x0E0B0031 },
         { .reg = 0x00009888, .val = 0x180B0092 },
         { .reg = 0x00009888, .val = 0x1A0B00B1 },
         { .reg = 0x00009888, .val = 0x020B0093 },
         { .reg = 0x00009888, .val = 0x040B0033 },
         { .reg = 0x00009888, .val = 0x200B0000 },
         { .reg = 0x00009888, .val = 0x100B4000 },
         { .reg = 0x00009888, .val = 0x120B8000 },
         { .reg = 0x00009888, .val = 0x160B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x080B4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x0C0B4000 },
         { .reg = 0x00009888, .val = 0x0A0C0022 },
         { .reg = 0x00009888, .val = 0x1E0C0325 },
         { .reg = 0x00009888, .val = 0x180C8000 },
         { .reg = 0x00009888, .val = 0x1A0C8000 },
         { .reg = 0x00009888, .val = 0x100D0017 },
         { .reg = 0x00009888, .val = 0x160D0013 },
         { .reg = 0x00009888, .val = 0x1C0D0081 },
         { .reg = 0x00009888, .val = 0x080D0082 },
         { .reg = 0x00009888, .val = 0x0A0D4102 },
         { .reg = 0x00009888, .val = 0x140D0000 },
         { .reg = 0x00009888, .val = 0x0C0D0000 },
         { .reg = 0x00009888, .val = 0x0E0D0000 },
         { .reg = 0x00009888, .val = 0x120D8000 },
         { .reg = 0x00009888, .val = 0x0C0E0215 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x1E0E8000 },
         { .reg = 0x00009888, .val = 0x0E0F8000 },
         { .reg = 0x00009888, .val = 0x060F4000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009888, .val = 0x08081000 },
         { .reg = 0x00009888, .val = 0x16080000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x5F115555 },
         { .reg = 0x00009888, .val = 0x61111555 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x4D101408 },
         { .reg = 0x00009888, .val = 0x4F100801 },
         { .reg = 0x00009888, .val = 0x51100A08 },
         { .reg = 0x00009888, .val = 0x53101118 },
         { .reg = 0x00009888, .val = 0x55100801 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101111 },
         { .reg = 0x00009888, .val = 0x4B100801 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__render_pipe_profile__avg_gpu_core_frequency__max,rkl__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__render_pipe_profile__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,rkl__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,rkl__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,rkl__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,rkl__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,rkl__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,rkl__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,rkl__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,rkl__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,rkl__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, rkl__render_pipe_profile__slm_bytes_read__max,rkl__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, rkl__render_pipe_profile__slm_bytes_written__max,rkl__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,rkl__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,rkl__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, rkl__render_pipe_profile__l3_shader_throughput__max,rkl__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,rkl__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 216, percentage_max_float,rkl__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 220, percentage_max_float,rkl__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 224, percentage_max_float,rkl__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 228, percentage_max_float,rkl__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 232, percentage_max_float,rkl__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 236, percentage_max_float,rkl__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 240, percentage_max_float,rkl__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 244, percentage_max_float,rkl__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 248, percentage_max_float,rkl__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 252, percentage_max_float,rkl__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 256, percentage_max_float,rkl__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 260, percentage_max_float,rkl__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 264, percentage_max_float,rkl__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 268, percentage_max_float,rkl__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 272, percentage_max_float,rkl__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 31);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "40ef13ef-25d9-4ac6-8582-ce97c47fc900";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14112400 },
         { .reg = 0x00009888, .val = 0x14312400 },
         { .reg = 0x00009888, .val = 0x240A0019 },
         { .reg = 0x00009888, .val = 0x00110074 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x00128000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x0E310074 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x06310000 },
         { .reg = 0x00009888, .val = 0x0E328000 },
         { .reg = 0x00009888, .val = 0x1C330200 },
         { .reg = 0x00009888, .val = 0x1C058000 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x0E0B8000 },
         { .reg = 0x00009888, .val = 0x100B8000 },
         { .reg = 0x00009888, .val = 0x100C8000 },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x000E8000 },
         { .reg = 0x00009888, .val = 0x000F4000 },
         { .reg = 0x00009888, .val = 0x100A00F7 },
         { .reg = 0x00009888, .val = 0x140A0000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A0000 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x14092000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105000 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100110 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00070000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000DC00, .val = 0x00000002 },
         { .reg = 0x0000DC04, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000DC08, .val = 0x00000002 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000DC10, .val = 0x00000002 },
         { .reg = 0x0000DC14, .val = 0x0000FFFB },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__hdc_and_sf__avg_gpu_core_frequency__max,rkl__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__hdc_and_sf__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,rkl__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,rkl__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,rkl__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,rkl__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,rkl__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,rkl__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,rkl__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,rkl__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,rkl__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, rkl__hdc_and_sf__slm_bytes_read__max,rkl__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, rkl__hdc_and_sf__slm_bytes_written__max,rkl__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,rkl__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,rkl__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, rkl__hdc_and_sf__l3_shader_throughput__max,rkl__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,rkl__hdc_and_sf__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 356, 216, percentage_max_float,rkl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 357, 220, percentage_max_float,rkl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      intel_perf_query_add_counter_float(query, 237, 224, percentage_max_float,rkl__hdc_and_sf__poly_data_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 37);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "bf60f7bd-9029-4edf-8311-f6e86599395e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1E055000 },
         { .reg = 0x00009888, .val = 0x1A0500C0 },
         { .reg = 0x00009888, .val = 0x2A0A7300 },
         { .reg = 0x00009888, .val = 0x2C0A0000 },
         { .reg = 0x00009888, .val = 0x120800A0 },
         { .reg = 0x00009888, .val = 0x04052700 },
         { .reg = 0x00009888, .val = 0x060500C0 },
         { .reg = 0x00009888, .val = 0x22050000 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x000B8000 },
         { .reg = 0x00009888, .val = 0x0E0B8000 },
         { .reg = 0x00009888, .val = 0x100B8000 },
         { .reg = 0x00009888, .val = 0x120B8000 },
         { .reg = 0x00009888, .val = 0x140B8000 },
         { .reg = 0x00009888, .val = 0x080B8000 },
         { .reg = 0x00009888, .val = 0x0A0B8000 },
         { .reg = 0x00009888, .val = 0x0C0B8000 },
         { .reg = 0x00009888, .val = 0x000A0144 },
         { .reg = 0x00009888, .val = 0x0E0A4145 },
         { .reg = 0x00009888, .val = 0x100A0156 },
         { .reg = 0x00009888, .val = 0x080A814F },
         { .reg = 0x00009888, .val = 0x140A0000 },
         { .reg = 0x00009888, .val = 0x040A0000 },
         { .reg = 0x00009888, .val = 0x0A0A4000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009888, .val = 0x08081980 },
         { .reg = 0x00009888, .val = 0x0A084032 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x16080000 },
         { .reg = 0x00009888, .val = 0x0C084000 },
         { .reg = 0x00009888, .val = 0x14091800 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x31152800 },
         { .reg = 0x00009888, .val = 0x331500A0 },
         { .reg = 0x00009888, .val = 0x31352800 },
         { .reg = 0x00009888, .val = 0x333500A0 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B10556B },
         { .reg = 0x00009888, .val = 0x5D103005 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115540 },
         { .reg = 0x00009888, .val = 0x61110005 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x05150096 },
         { .reg = 0x00009888, .val = 0x07150016 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x0316C000 },
         { .reg = 0x00009888, .val = 0x1F350096 },
         { .reg = 0x00009888, .val = 0x03350016 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x0F368000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x47101600 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100606 },
         { .reg = 0x00009888, .val = 0x51100404 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55101000 },
         { .reg = 0x00009888, .val = 0x57100002 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B100602 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000DC00, .val = 0x00000038 },
         { .reg = 0x0000DC04, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000DC08, .val = 0x000000C0 },
         { .reg = 0x0000DC0C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,rkl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__rasterizer_and_pixel_backend__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,rkl__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,rkl__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,rkl__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,rkl__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,rkl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,rkl__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,rkl__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,rkl__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,rkl__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, rkl__rasterizer_and_pixel_backend__slm_bytes_read__max,rkl__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, rkl__rasterizer_and_pixel_backend__slm_bytes_written__max,rkl__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,rkl__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,rkl__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, rkl__rasterizer_and_pixel_backend__l3_shader_throughput__max,rkl__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,rkl__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 266, 216, percentage_max_float,rkl__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 261, 220, percentage_max_float,rkl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 360, 224, percentage_max_float,rkl__rasterizer_and_pixel_backend__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 362, 228, percentage_max_float,rkl__rasterizer_and_pixel_backend__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 364, 232, percentage_max_float,rkl__rasterizer_and_pixel_backend__pixel_values00_ready__read);

      intel_perf_query_add_counter_float(query, 436, 236, percentage_max_float,rkl__rasterizer_and_pixel_backend__gt_request_queue00_full__read);

      intel_perf_query_add_counter_float(query, 437, 240, percentage_max_float,rkl__rasterizer_and_pixel_backend__gt_request_queue01_full__read);

      intel_perf_query_add_counter_float(query, 438, 244, percentage_max_float,rkl__rasterizer_and_pixel_backend__gt_request_queue10_full__read);

      intel_perf_query_add_counter_float(query, 439, 248, percentage_max_float,rkl__rasterizer_and_pixel_backend__gt_request_queue11_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_1";
   query->symbol_name = "L3_1";
   query->guid = "a5f6ac3d-853f-42a4-a038-c4a09e8075be";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04002024 },
         { .reg = 0x00009888, .val = 0x0600282F },
         { .reg = 0x00009888, .val = 0x1C0B8000 },
         { .reg = 0x00009888, .val = 0x1E0B8000 },
         { .reg = 0x00009888, .val = 0x020B8000 },
         { .reg = 0x00009888, .val = 0x040B8000 },
         { .reg = 0x00009888, .val = 0x060B8000 },
         { .reg = 0x00009888, .val = 0x080B8000 },
         { .reg = 0x00009888, .val = 0x0A0B8000 },
         { .reg = 0x00009888, .val = 0x0C0B8000 },
         { .reg = 0x00009888, .val = 0x120AC000 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x060AC000 },
         { .reg = 0x00009888, .val = 0x080AC000 },
         { .reg = 0x00009888, .val = 0x0A0A4000 },
         { .reg = 0x00009888, .val = 0x1608A000 },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009888, .val = 0x04088000 },
         { .reg = 0x00009888, .val = 0x06088000 },
         { .reg = 0x00009888, .val = 0x08088000 },
         { .reg = 0x00009888, .val = 0x0A088000 },
         { .reg = 0x00009888, .val = 0x0C088000 },
         { .reg = 0x00009888, .val = 0x1C000027 },
         { .reg = 0x00009888, .val = 0x1E000026 },
         { .reg = 0x00009888, .val = 0x02000025 },
         { .reg = 0x00009888, .val = 0x0800002E },
         { .reg = 0x00009888, .val = 0x0A00002D },
         { .reg = 0x00009888, .val = 0x0C00002C },
         { .reg = 0x00009888, .val = 0x2E000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100555 },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x5F110555 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__l3_1__avg_gpu_core_frequency__max,rkl__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,rkl__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,rkl__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,rkl__l3_1__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,rkl__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,rkl__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,rkl__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,rkl__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,rkl__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,rkl__l3_1__cs_threads__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 440, 88, percentage_max_float,rkl__l3_1__l30_bank0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 441, 92, percentage_max_float,rkl__l3_1__l30_bank1_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_2";
   query->symbol_name = "L3_2";
   query->guid = "bb080384-a01f-442f-8be2-3eae2c7394cd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04003000 },
         { .reg = 0x00009888, .val = 0x06003800 },
         { .reg = 0x00009888, .val = 0x000B8000 },
         { .reg = 0x00009888, .val = 0x0E0B8000 },
         { .reg = 0x00009888, .val = 0x100B8000 },
         { .reg = 0x00009888, .val = 0x120B8000 },
         { .reg = 0x00009888, .val = 0x140B8000 },
         { .reg = 0x00009888, .val = 0x160B8000 },
         { .reg = 0x00009888, .val = 0x180B8000 },
         { .reg = 0x00009888, .val = 0x1A0B8000 },
         { .reg = 0x00009888, .val = 0x040A4000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0AC000 },
         { .reg = 0x00009888, .val = 0x0E0AC000 },
         { .reg = 0x00009888, .val = 0x100AC000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x0E088000 },
         { .reg = 0x00009888, .val = 0x16080AAA },
         { .reg = 0x00009888, .val = 0x00000024 },
         { .reg = 0x00009888, .val = 0x0E000025 },
         { .reg = 0x00009888, .val = 0x10000026 },
         { .reg = 0x00009888, .val = 0x12000027 },
         { .reg = 0x00009888, .val = 0x1400002C },
         { .reg = 0x00009888, .val = 0x1600002D },
         { .reg = 0x00009888, .val = 0x1800002E },
         { .reg = 0x00009888, .val = 0x1A00002F },
         { .reg = 0x00009888, .val = 0x2E000000 },
         { .reg = 0x00009888, .val = 0x2C000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105000 },
         { .reg = 0x00009888, .val = 0x5D100155 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x61110155 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x53100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__l3_2__avg_gpu_core_frequency__max,rkl__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__l3_2__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 442, 92, percentage_max_float,rkl__l3_2__l30_bank2_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 443, 96, percentage_max_float,rkl__l3_2__l30_bank3_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "L3_3";
   query->symbol_name = "L3_3";
   query->guid = "9f39ce80-0463-484e-b797-3135b7e0ab0a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04000200 },
         { .reg = 0x00009888, .val = 0x06000000 },
         { .reg = 0x00009888, .val = 0x0A0B8000 },
         { .reg = 0x00009888, .val = 0x0C0B8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009888, .val = 0x0A0A4000 },
         { .reg = 0x00009888, .val = 0x0A088000 },
         { .reg = 0x00009888, .val = 0x0C088000 },
         { .reg = 0x00009888, .val = 0x0A000020 },
         { .reg = 0x00009888, .val = 0x0C000028 },
         { .reg = 0x00009888, .val = 0x2E000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100500 },
         { .reg = 0x00009888, .val = 0x5F110500 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__l3_3__avg_gpu_core_frequency__max,rkl__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__l3_3__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 444, 92, percentage_max_float,rkl__l3_3__l30_bank0_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_l3_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "L3_4";
   query->symbol_name = "L3_4";
   query->guid = "11e091e1-bbd3-4bd6-9ce8-8982d2d3a3b2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04000A00 },
         { .reg = 0x00009888, .val = 0x06000820 },
         { .reg = 0x00009888, .val = 0x060B8000 },
         { .reg = 0x00009888, .val = 0x080B8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A4000 },
         { .reg = 0x00009888, .val = 0x06088000 },
         { .reg = 0x00009888, .val = 0x08088000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x2E000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100050 },
         { .reg = 0x00009888, .val = 0x5F110050 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__l3_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__l3_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__l3_4__avg_gpu_core_frequency__max,rkl__l3_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__l3_4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__l3_4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__l3_4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__l3_4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__l3_4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__l3_4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__l3_4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__l3_4__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__l3_4__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__l3_4__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 445, 92, percentage_max_float,rkl__l3_4__l30_bank1_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_l3_5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "L3_5";
   query->symbol_name = "L3_5";
   query->guid = "0f2e1818-c190-494a-a828-2ed4422d71f3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04001200 },
         { .reg = 0x00009888, .val = 0x06001020 },
         { .reg = 0x00009888, .val = 0x060B8000 },
         { .reg = 0x00009888, .val = 0x080B8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A4000 },
         { .reg = 0x00009888, .val = 0x06088000 },
         { .reg = 0x00009888, .val = 0x08088000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x2E000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100050 },
         { .reg = 0x00009888, .val = 0x5F110050 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__l3_5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__l3_5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__l3_5__avg_gpu_core_frequency__max,rkl__l3_5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__l3_5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__l3_5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__l3_5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__l3_5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__l3_5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__l3_5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__l3_5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__l3_5__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__l3_5__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__l3_5__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 446, 92, percentage_max_float,rkl__l3_5__l30_bank2_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_l3_6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "L3_6";
   query->symbol_name = "L3_6";
   query->guid = "ebd91ba3-4d01-4bdf-8752-384cd0a4e139";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04001A00 },
         { .reg = 0x00009888, .val = 0x06001820 },
         { .reg = 0x00009888, .val = 0x060B8000 },
         { .reg = 0x00009888, .val = 0x080B8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A4000 },
         { .reg = 0x00009888, .val = 0x06088000 },
         { .reg = 0x00009888, .val = 0x08088000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x2E000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100050 },
         { .reg = 0x00009888, .val = 0x5F110050 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__l3_6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__l3_6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__l3_6__avg_gpu_core_frequency__max,rkl__l3_6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__l3_6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__l3_6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__l3_6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__l3_6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__l3_6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__l3_6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__l3_6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__l3_6__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__l3_6__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__l3_6__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 447, 92, percentage_max_float,rkl__l3_6__l30_bank3_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "Sampler_1";
   query->symbol_name = "Sampler_1";
   query->guid = "5102fa66-b5f3-45f2-a16d-0a13a4cbb6c9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C123E00 },
         { .reg = 0x00009888, .val = 0x1C121600 },
         { .reg = 0x00009888, .val = 0x04143E00 },
         { .reg = 0x00009888, .val = 0x18141613 },
         { .reg = 0x00009888, .val = 0x0C323E00 },
         { .reg = 0x00009888, .val = 0x1C321600 },
         { .reg = 0x00009888, .val = 0x04343E00 },
         { .reg = 0x00009888, .val = 0x18341600 },
         { .reg = 0x00009888, .val = 0x0E120086 },
         { .reg = 0x00009888, .val = 0x1A120033 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x18124000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x1C13C200 },
         { .reg = 0x00009888, .val = 0x001400A6 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x0C140000 },
         { .reg = 0x00009888, .val = 0x18158000 },
         { .reg = 0x00009888, .val = 0x1C150800 },
         { .reg = 0x00009888, .val = 0x12320086 },
         { .reg = 0x00009888, .val = 0x16320033 },
         { .reg = 0x00009888, .val = 0x20320000 },
         { .reg = 0x00009888, .val = 0x10324000 },
         { .reg = 0x00009888, .val = 0x14324000 },
         { .reg = 0x00009888, .val = 0x1C333C00 },
         { .reg = 0x00009888, .val = 0x103400A6 },
         { .reg = 0x00009888, .val = 0x14340013 },
         { .reg = 0x00009888, .val = 0x08340000 },
         { .reg = 0x00009888, .val = 0x0A340000 },
         { .reg = 0x00009888, .val = 0x1C350088 },
         { .reg = 0x00009888, .val = 0x220500F0 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x100B8000 },
         { .reg = 0x00009888, .val = 0x120B8000 },
         { .reg = 0x00009888, .val = 0x140B8000 },
         { .reg = 0x00009888, .val = 0x160B8000 },
         { .reg = 0x00009888, .val = 0x180B4000 },
         { .reg = 0x00009888, .val = 0x1A0B4000 },
         { .reg = 0x00009888, .val = 0x100C8000 },
         { .reg = 0x00009888, .val = 0x1E0C00C2 },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x0A0D8000 },
         { .reg = 0x00009888, .val = 0x100DC000 },
         { .reg = 0x00009888, .val = 0x000E8000 },
         { .reg = 0x00009888, .val = 0x0E0E8000 },
         { .reg = 0x00009888, .val = 0x180E8000 },
         { .reg = 0x00009888, .val = 0x1A0E8000 },
         { .reg = 0x00009888, .val = 0x000F4000 },
         { .reg = 0x00009888, .val = 0x060F8000 },
         { .reg = 0x00009888, .val = 0x0C0FC000 },
         { .reg = 0x00009888, .val = 0x0C0AC000 },
         { .reg = 0x00009888, .val = 0x0E0AC000 },
         { .reg = 0x00009888, .val = 0x16080055 },
         { .reg = 0x00009888, .val = 0x1409C000 },
         { .reg = 0x00009888, .val = 0x16090003 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105000 },
         { .reg = 0x00009888, .val = 0x5D100155 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115000 },
         { .reg = 0x00009888, .val = 0x61110155 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x19128000 },
         { .reg = 0x00009888, .val = 0x1B128000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100004 },
         { .reg = 0x00009888, .val = 0x51100004 },
         { .reg = 0x00009888, .val = 0x53100004 },
         { .reg = 0x00009888, .val = 0x55100004 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x000F0000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000180 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000600 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__sampler_1__avg_gpu_core_frequency__max,rkl__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__sampler_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__sampler_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__sampler_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__sampler_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__sampler_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__sampler_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__sampler_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__sampler_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__sampler_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__sampler_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 448, 92, percentage_max_float,rkl__sampler_1__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 449, 96, percentage_max_float,rkl__sampler_1__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 450, 100, percentage_max_float,rkl__sampler_1__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 451, 104, percentage_max_float,rkl__sampler_1__sampler01_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "8706c725-7753-427d-ae2d-ba25c1168f2a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x24110340 },
         { .reg = 0x00009888, .val = 0x2611001C },
         { .reg = 0x00009888, .val = 0x24310340 },
         { .reg = 0x00009888, .val = 0x2631001C },
         { .reg = 0x00009888, .val = 0x001100F3 },
         { .reg = 0x00009888, .val = 0x0E1100F2 },
         { .reg = 0x00009888, .val = 0x16110103 },
         { .reg = 0x00009888, .val = 0x06110107 },
         { .reg = 0x00009888, .val = 0x08110106 },
         { .reg = 0x00009888, .val = 0x0A110105 },
         { .reg = 0x00009888, .val = 0x0C110104 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x02110000 },
         { .reg = 0x00009888, .val = 0x04110000 },
         { .reg = 0x00009888, .val = 0x00128000 },
         { .reg = 0x00009888, .val = 0x0E128000 },
         { .reg = 0x00009888, .val = 0x16128000 },
         { .reg = 0x00009888, .val = 0x06128000 },
         { .reg = 0x00009888, .val = 0x08128000 },
         { .reg = 0x00009888, .val = 0x0A128000 },
         { .reg = 0x00009888, .val = 0x0C128000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x1C132300 },
         { .reg = 0x00009888, .val = 0x16138000 },
         { .reg = 0x00009888, .val = 0x18138000 },
         { .reg = 0x00009888, .val = 0x1A138000 },
         { .reg = 0x00009888, .val = 0x103100F3 },
         { .reg = 0x00009888, .val = 0x123100F2 },
         { .reg = 0x00009888, .val = 0x14310103 },
         { .reg = 0x00009888, .val = 0x1C310107 },
         { .reg = 0x00009888, .val = 0x1E310106 },
         { .reg = 0x00009888, .val = 0x02310105 },
         { .reg = 0x00009888, .val = 0x04310104 },
         { .reg = 0x00009888, .val = 0x08310000 },
         { .reg = 0x00009888, .val = 0x0A310000 },
         { .reg = 0x00009888, .val = 0x0E310000 },
         { .reg = 0x00009888, .val = 0x00310000 },
         { .reg = 0x00009888, .val = 0x10328000 },
         { .reg = 0x00009888, .val = 0x12328000 },
         { .reg = 0x00009888, .val = 0x14328000 },
         { .reg = 0x00009888, .val = 0x1C328000 },
         { .reg = 0x00009888, .val = 0x1E328000 },
         { .reg = 0x00009888, .val = 0x02328000 },
         { .reg = 0x00009888, .val = 0x04328000 },
         { .reg = 0x00009888, .val = 0x1C331C00 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x12338000 },
         { .reg = 0x00009888, .val = 0x14338000 },
         { .reg = 0x00009888, .val = 0x22050C70 },
         { .reg = 0x00009888, .val = 0x12058000 },
         { .reg = 0x00009888, .val = 0x14058000 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x100B8000 },
         { .reg = 0x00009888, .val = 0x120B8000 },
         { .reg = 0x00009888, .val = 0x140B8000 },
         { .reg = 0x00009888, .val = 0x160B4000 },
         { .reg = 0x00009888, .val = 0x1C0B8000 },
         { .reg = 0x00009888, .val = 0x1E0B8000 },
         { .reg = 0x00009888, .val = 0x020B8000 },
         { .reg = 0x00009888, .val = 0x040B8000 },
         { .reg = 0x00009888, .val = 0x060B4000 },
         { .reg = 0x00009888, .val = 0x080B4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x0C0B4000 },
         { .reg = 0x00009888, .val = 0x100C8000 },
         { .reg = 0x00009888, .val = 0x1E0C0023 },
         { .reg = 0x00009888, .val = 0x160C8000 },
         { .reg = 0x00009888, .val = 0x180C8000 },
         { .reg = 0x00009888, .val = 0x1A0C8000 },
         { .reg = 0x00009888, .val = 0x040D4000 },
         { .reg = 0x00009888, .val = 0x0A0DC000 },
         { .reg = 0x00009888, .val = 0x0E0D8000 },
         { .reg = 0x00009888, .val = 0x060D8000 },
         { .reg = 0x00009888, .val = 0x080DC000 },
         { .reg = 0x00009888, .val = 0x000E8000 },
         { .reg = 0x00009888, .val = 0x0E0E8000 },
         { .reg = 0x00009888, .val = 0x160E8000 },
         { .reg = 0x00009888, .val = 0x060E8000 },
         { .reg = 0x00009888, .val = 0x080E8000 },
         { .reg = 0x00009888, .val = 0x0A0E8000 },
         { .reg = 0x00009888, .val = 0x0C0E8000 },
         { .reg = 0x00009888, .val = 0x000F4000 },
         { .reg = 0x00009888, .val = 0x060FC000 },
         { .reg = 0x00009888, .val = 0x0A0F8000 },
         { .reg = 0x00009888, .val = 0x020F8000 },
         { .reg = 0x00009888, .val = 0x040FC000 },
         { .reg = 0x00009888, .val = 0x0C0AC000 },
         { .reg = 0x00009888, .val = 0x0E0A4000 },
         { .reg = 0x00009888, .val = 0x120AC000 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x060A4000 },
         { .reg = 0x00009888, .val = 0x16085015 },
         { .reg = 0x00009888, .val = 0x02084000 },
         { .reg = 0x00009888, .val = 0x04084000 },
         { .reg = 0x00009888, .val = 0x1409C180 },
         { .reg = 0x00009888, .val = 0x16090031 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101415 },
         { .reg = 0x00009888, .val = 0x4B112000 },
         { .reg = 0x00009888, .val = 0x5F115555 },
         { .reg = 0x00009888, .val = 0x61111415 },
         { .reg = 0x00009888, .val = 0x01128000 },
         { .reg = 0x00009888, .val = 0x0F128000 },
         { .reg = 0x00009888, .val = 0x11128000 },
         { .reg = 0x00009888, .val = 0x13128000 },
         { .reg = 0x00009888, .val = 0x15128000 },
         { .reg = 0x00009888, .val = 0x17128000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x07128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x53100000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000DC40, .val = 0x003F0000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000000 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000000 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFEF },
         { .reg = 0x0000DC10, .val = 0x00000002 },
         { .reg = 0x0000DC14, .val = 0x0000FFEF },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFDF },
         { .reg = 0x0000DC18, .val = 0x00000002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFDF },
         { .reg = 0x0000D960, .val = 0x00078000 },
         { .reg = 0x0000D964, .val = 0x00000FFF },
         { .reg = 0x0000DC20, .val = 0x00078000 },
         { .reg = 0x0000DC24, .val = 0x00000FFF },
         { .reg = 0x0000D968, .val = 0x00007800 },
         { .reg = 0x0000D96C, .val = 0x0000F0FF },
         { .reg = 0x0000DC28, .val = 0x00007800 },
         { .reg = 0x0000DC2C, .val = 0x0000F0FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__tdl_1__avg_gpu_core_frequency__max,rkl__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,rkl__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,rkl__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,rkl__tdl_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 452, 92, percentage_max_float,rkl__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 453, 96, percentage_max_float,rkl__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 454, 100, percentage_max_float,rkl__tdl_1__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 455, 104, percentage_max_float,rkl__tdl_1__ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 456, 108, percentage_max_float,rkl__tdl_1__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 457, 112, percentage_max_float,rkl__tdl_1__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 458, 116, percentage_max_float,rkl__tdl_1__thread_header00_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 459, 120, percentage_max_float,rkl__tdl_1__thread_header00_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 460, 124, percentage_max_float,rkl__tdl_1__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 461, 128, percentage_max_float,rkl__tdl_1__thread_header01_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 462, 132, percentage_max_float,rkl__tdl_1__thread_header01_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 463, 136, percentage_max_float,rkl__tdl_1__thread_header01_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 464, 140, percentage_max_float,rkl__tdl_1__thread_header00_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 465, 144, percentage_max_float,rkl__tdl_1__thread_header01_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "3eab195e-e4d8-482e-9981-811935722b21";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x040B4000 },
         { .reg = 0x00009888, .val = 0x080B4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x140C8000 },
         { .reg = 0x00009888, .val = 0x180C8000 },
         { .reg = 0x00009888, .val = 0x1A0C8000 },
         { .reg = 0x00009888, .val = 0x060D4000 },
         { .reg = 0x00009888, .val = 0x080DC000 },
         { .reg = 0x00009888, .val = 0x040E0043 },
         { .reg = 0x00009888, .val = 0x0A0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x080F00A3 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x020F4000 },
         { .reg = 0x00009888, .val = 0x040F8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x15102400 },
         { .reg = 0x00009888, .val = 0x230B0120 },
         { .reg = 0x00009888, .val = 0x15182400 },
         { .reg = 0x00009888, .val = 0x17100023 },
         { .reg = 0x00009888, .val = 0x11100000 },
         { .reg = 0x00009888, .val = 0x5D101000 },
         { .reg = 0x00009888, .val = 0x5B100544 },
         { .reg = 0x00009888, .val = 0x61112000 },
         { .reg = 0x00009888, .val = 0x5F110944 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x09128000 },
         { .reg = 0x00009888, .val = 0x0B128000 },
         { .reg = 0x00009888, .val = 0x1B0D0040 },
         { .reg = 0x00009888, .val = 0x0D0DC000 },
         { .reg = 0x00009888, .val = 0x1F0B00D3 },
         { .reg = 0x00009888, .val = 0x190B0000 },
         { .reg = 0x00009888, .val = 0x170B0000 },
         { .reg = 0x00009888, .val = 0x07174000 },
         { .reg = 0x00009888, .val = 0x071800A3 },
         { .reg = 0x00009888, .val = 0x11180000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x5710000A },
         { .reg = 0x00009888, .val = 0x49101000 },
         { .reg = 0x00009888, .val = 0x4B100206 },
         { .reg = 0x00009888, .val = 0x4D100800 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00024002 },
         { .reg = 0x0000D944, .val = 0x0000B7FF },
         { .reg = 0x0000DC00, .val = 0x00024002 },
         { .reg = 0x0000DC04, .val = 0x0000B7FF },
         { .reg = 0x0000D948, .val = 0x0007D000 },
         { .reg = 0x0000D94C, .val = 0x000005FF },
         { .reg = 0x0000DC08, .val = 0x0007D000 },
         { .reg = 0x0000DC0C, .val = 0x000005FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__gpu_busyness__avg_gpu_core_frequency__max,rkl__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,rkl__gpu_busyness__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,rkl__gpu_busyness__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,rkl__gpu_busyness__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,rkl__gpu_busyness__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,rkl__gpu_busyness__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,rkl__gpu_busyness__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,rkl__gpu_busyness__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,rkl__gpu_busyness__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,rkl__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 88, percentage_max_float,rkl__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 92, percentage_max_float,rkl__gpu_busyness__compute_busy__read);

      intel_perf_query_add_counter_float(query, 414, 96, percentage_max_float,rkl__gpu_busyness__posh_engine_busy__read);

      intel_perf_query_add_counter_float(query, 313, 100, percentage_max_float,rkl__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 312, 104, percentage_max_float,rkl__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 310, 108, percentage_max_float,rkl__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 467, 112, percentage_max_float,rkl__gpu_busyness__render_and_compute_busy__read);

      intel_perf_query_add_counter_float(query, 468, 116, percentage_max_float,rkl__gpu_busyness__any_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_eu_activity1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity1";
   query->symbol_name = "EuActivity1";
   query->guid = "100ae8ce-31c6-457f-97a2-dfd44812bce6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x1E0C0300 },
         { .reg = 0x00009888, .val = 0x120DC000 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x0E0FC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B101212 },
         { .reg = 0x00009888, .val = 0x4D100212 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00810710 },
         { .reg = 0x0000E558, .val = 0x00A10910 },
         { .reg = 0x0000E658, .val = 0x00850750 },
         { .reg = 0x0000E758, .val = 0x00A50950 },
         { .reg = 0x0000E45C, .val = 0x00802702 },
         { .reg = 0x0000E55C, .val = 0x00A02902 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__eu_activity1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__eu_activity1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__eu_activity1__avg_gpu_core_frequency__max,rkl__eu_activity1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__eu_activity1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__eu_activity1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__eu_activity1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__eu_activity1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__eu_activity1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__eu_activity1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__eu_activity1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,rkl__eu_activity1__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,rkl__eu_activity1__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,rkl__eu_activity1__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, rkl__eu_activity1__gti_read_throughput__max,rkl__eu_activity1__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, rkl__eu_activity1__gti_write_throughput__max,rkl__eu_activity1__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 469, 112, percentage_max_float,rkl__eu_activity1__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 470, 116, percentage_max_float,rkl__eu_activity1__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 153, 120, percentage_max_float,rkl__eu_activity1__eu_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_eu_activity2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity2";
   query->symbol_name = "EuActivity2";
   query->guid = "7e926c0a-471b-40b3-a641-75f3d73339ec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x1E0C0300 },
         { .reg = 0x00009888, .val = 0x120DC000 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x0E0FC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B101212 },
         { .reg = 0x00009888, .val = 0x4D100212 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00862762 },
         { .reg = 0x0000E558, .val = 0x00A62962 },
         { .reg = 0x0000E658, .val = 0x00860760 },
         { .reg = 0x0000E758, .val = 0x00A60960 },
         { .reg = 0x0000E45C, .val = 0x00861761 },
         { .reg = 0x0000E55C, .val = 0x00A61961 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__eu_activity2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__eu_activity2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__eu_activity2__avg_gpu_core_frequency__max,rkl__eu_activity2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__eu_activity2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__eu_activity2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__eu_activity2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__eu_activity2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__eu_activity2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__eu_activity2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__eu_activity2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,rkl__eu_activity2__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,rkl__eu_activity2__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,rkl__eu_activity2__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, rkl__eu_activity2__gti_read_throughput__max,rkl__eu_activity2__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, rkl__eu_activity2__gti_write_throughput__max,rkl__eu_activity2__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 471, 112, percentage_max_float,rkl__eu_activity2__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 472, 116, percentage_max_float,rkl__eu_activity2__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 473, 120, percentage_max_float,rkl__eu_activity2__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_eu_activity3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity3";
   query->symbol_name = "EuActivity3";
   query->guid = "aca9005f-fafe-4d02-a9de-b2584ff76f04";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x1E0C0300 },
         { .reg = 0x00009888, .val = 0x120DC000 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x0E0FC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B101212 },
         { .reg = 0x00009888, .val = 0x4D100212 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00811711 },
         { .reg = 0x0000E558, .val = 0x00A11911 },
         { .reg = 0x0000E658, .val = 0x00851751 },
         { .reg = 0x0000E758, .val = 0x00A51951 },
         { .reg = 0x0000E45C, .val = 0x00852752 },
         { .reg = 0x0000E55C, .val = 0x00A52952 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__eu_activity3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__eu_activity3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__eu_activity3__avg_gpu_core_frequency__max,rkl__eu_activity3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__eu_activity3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__eu_activity3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__eu_activity3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__eu_activity3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__eu_activity3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__eu_activity3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__eu_activity3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,rkl__eu_activity3__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,rkl__eu_activity3__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,rkl__eu_activity3__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, rkl__eu_activity3__gti_read_throughput__max,rkl__eu_activity3__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, rkl__eu_activity3__gti_write_throughput__max,rkl__eu_activity3__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 474, 112, percentage_max_float,rkl__eu_activity3__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 475, 116, percentage_max_float,rkl__eu_activity3__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 129, 120, percentage_max_float,rkl__eu_activity3__ps_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_eu_activity4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity4";
   query->symbol_name = "EuActivity4";
   query->guid = "ad96806d-7c0d-49f0-b844-c5010ade30af";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x1E0C0300 },
         { .reg = 0x00009888, .val = 0x120DC000 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x0E0FC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B101212 },
         { .reg = 0x00009888, .val = 0x4D100212 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00820720 },
         { .reg = 0x0000E558, .val = 0x00A20920 },
         { .reg = 0x0000E658, .val = 0x00830730 },
         { .reg = 0x0000E758, .val = 0x00A30930 },
         { .reg = 0x0000E45C, .val = 0x00812712 },
         { .reg = 0x0000E55C, .val = 0x00A12912 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__eu_activity4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__eu_activity4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__eu_activity4__avg_gpu_core_frequency__max,rkl__eu_activity4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__eu_activity4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__eu_activity4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__eu_activity4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__eu_activity4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__eu_activity4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__eu_activity4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__eu_activity4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,rkl__eu_activity4__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,rkl__eu_activity4__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,rkl__eu_activity4__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, rkl__eu_activity4__gti_read_throughput__max,rkl__eu_activity4__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, rkl__eu_activity4__gti_write_throughput__max,rkl__eu_activity4__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 476, 112, percentage_max_float,rkl__eu_activity4__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 477, 116, percentage_max_float,rkl__eu_activity4__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 126, 120, percentage_max_float,rkl__eu_activity4__vs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_eu_activity5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity5";
   query->symbol_name = "EuActivity5";
   query->guid = "1669e79f-976e-47ba-a553-0a716ebd3c71";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x1E0C0300 },
         { .reg = 0x00009888, .val = 0x120DC000 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x0E0FC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B101212 },
         { .reg = 0x00009888, .val = 0x4D100212 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00821721 },
         { .reg = 0x0000E558, .val = 0x00A21921 },
         { .reg = 0x0000E658, .val = 0x00831731 },
         { .reg = 0x0000E758, .val = 0x00A31931 },
         { .reg = 0x0000E45C, .val = 0x00822722 },
         { .reg = 0x0000E55C, .val = 0x00A22922 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__eu_activity5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__eu_activity5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__eu_activity5__avg_gpu_core_frequency__max,rkl__eu_activity5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__eu_activity5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__eu_activity5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__eu_activity5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__eu_activity5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__eu_activity5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__eu_activity5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__eu_activity5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,rkl__eu_activity5__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,rkl__eu_activity5__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,rkl__eu_activity5__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, rkl__eu_activity5__gti_read_throughput__max,rkl__eu_activity5__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, rkl__eu_activity5__gti_write_throughput__max,rkl__eu_activity5__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 478, 112, percentage_max_float,rkl__eu_activity5__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 479, 116, percentage_max_float,rkl__eu_activity5__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 480, 120, percentage_max_float,rkl__eu_activity5__hs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_eu_activity6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity6";
   query->symbol_name = "EuActivity6";
   query->guid = "d100e474-1e6c-4100-812b-71ec9cfe3523";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x1E0C0300 },
         { .reg = 0x00009888, .val = 0x120DC000 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x0E0FC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B101212 },
         { .reg = 0x00009888, .val = 0x4D100212 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00840740 },
         { .reg = 0x0000E558, .val = 0x00A40940 },
         { .reg = 0x0000E658, .val = 0x00841741 },
         { .reg = 0x0000E758, .val = 0x00A41941 },
         { .reg = 0x0000E45C, .val = 0x00842742 },
         { .reg = 0x0000E55C, .val = 0x00A42942 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__eu_activity6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__eu_activity6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__eu_activity6__avg_gpu_core_frequency__max,rkl__eu_activity6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__eu_activity6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__eu_activity6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__eu_activity6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__eu_activity6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__eu_activity6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__eu_activity6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__eu_activity6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,rkl__eu_activity6__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,rkl__eu_activity6__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,rkl__eu_activity6__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, rkl__eu_activity6__gti_read_throughput__max,rkl__eu_activity6__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, rkl__eu_activity6__gti_write_throughput__max,rkl__eu_activity6__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 481, 112, percentage_max_float,rkl__eu_activity6__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 482, 116, percentage_max_float,rkl__eu_activity6__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 483, 120, percentage_max_float,rkl__eu_activity6__gs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_eu_activity7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "EuActivity7";
   query->symbol_name = "EuActivity7";
   query->guid = "b22d38f6-a056-496a-8d7d-dede47051806";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x1E0C0300 },
         { .reg = 0x00009888, .val = 0x120DC000 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x0E0FC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B101212 },
         { .reg = 0x00009888, .val = 0x4D100212 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00803703 },
         { .reg = 0x0000E558, .val = 0x00A03903 },
         { .reg = 0x0000E658, .val = 0x00800700 },
         { .reg = 0x0000E758, .val = 0x00A00900 },
         { .reg = 0x0000E45C, .val = 0x00801701 },
         { .reg = 0x0000E55C, .val = 0x00A01901 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__eu_activity7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__eu_activity7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__eu_activity7__avg_gpu_core_frequency__max,rkl__eu_activity7__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__eu_activity7__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__eu_activity7__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__eu_activity7__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__eu_activity7__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__eu_activity7__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__eu_activity7__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__eu_activity7__cs_threads__read);

      intel_perf_query_add_counter_float(query, 484, 80, percentage_max_float,rkl__eu_activity7__fpu_active__read);

      intel_perf_query_add_counter_float(query, 485, 84, percentage_max_float,rkl__eu_activity7__em_active__read);

      intel_perf_query_add_counter_float(query, 486, 88, percentage_max_float,rkl__eu_activity7__eu_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 152, 92, rkl__eu_activity7__eu_avg_ipc_rate__max,rkl__eu_activity7__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 309, 96, percentage_max_float,rkl__eu_activity7__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 100, percentage_max_float,rkl__eu_activity7__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 104, percentage_max_float,rkl__eu_activity7__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 112, rkl__eu_activity7__gti_read_throughput__max,rkl__eu_activity7__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 120, rkl__eu_activity7__gti_write_throughput__max,rkl__eu_activity7__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_eu_activity8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 16);

   query->name = "EuActivity8";
   query->symbol_name = "EuActivity8";
   query->guid = "c68abf37-fe6e-45f6-9dcb-549b3fbef699";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E2400 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x1E0C0300 },
         { .reg = 0x00009888, .val = 0x120DC000 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x200E0000 },
         { .reg = 0x00009888, .val = 0x0E0FC000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x61111400 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B101212 },
         { .reg = 0x00009888, .val = 0x4D100212 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00832732 },
         { .reg = 0x0000E558, .val = 0x00A32932 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__eu_activity8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__eu_activity8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__eu_activity8__avg_gpu_core_frequency__max,rkl__eu_activity8__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,rkl__eu_activity8__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,rkl__eu_activity8__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,rkl__eu_activity8__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,rkl__eu_activity8__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,rkl__eu_activity8__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,rkl__eu_activity8__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,rkl__eu_activity8__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,rkl__eu_activity8__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,rkl__eu_activity8__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,rkl__eu_activity8__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, rkl__eu_activity8__gti_read_throughput__max,rkl__eu_activity8__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, rkl__eu_activity8__gti_write_throughput__max,rkl__eu_activity8__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 487, 112, percentage_max_float,rkl__eu_activity8__ds_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
rkl_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "74dbc739-d871-41b5-be7b-fb547ac5bec9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x1E0C0200 },
         { .reg = 0x00009888, .val = 0x120D8000 },
         { .reg = 0x00009888, .val = 0x1E0F0017 },
         { .reg = 0x00009888, .val = 0x100F0000 },
         { .reg = 0x00009888, .val = 0x0E0F0000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x49110000 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x1D1103A3 },
         { .reg = 0x00009888, .val = 0x01110000 },
         { .reg = 0x00009888, .val = 0x61111000 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100110 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000DC00, .val = 0x00000004 },
         { .reg = 0x0000DC04, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000DC08, .val = 0x00000003 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000DC10, .val = 0x00000007 },
         { .reg = 0x0000DC14, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00100002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000DC20, .val = 0x00100002 },
         { .reg = 0x0000DC24, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000DC28, .val = 0x00100082 },
         { .reg = 0x0000DC2C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000DC30, .val = 0x001000C2 },
         { .reg = 0x0000DC34, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
         { .reg = 0x0000DC38, .val = 0x00100001 },
         { .reg = 0x0000DC3C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,rkl__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,rkl__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, rkl__test_oa__avg_gpu_core_frequency__max,rkl__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,rkl__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,rkl__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,rkl__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,rkl__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 415, 56, NULL,rkl__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 416, 64, NULL,rkl__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 417, 72, NULL,rkl__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 418, 80, NULL,rkl__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 488, 88, NULL,rkl__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 489, 96, NULL,rkl__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_rkl(struct intel_perf_config *perf)
{
   rkl_register_render_basic_counter_query(perf);
   rkl_register_compute_basic_counter_query(perf);
   rkl_register_render_pipe_profile_counter_query(perf);
   rkl_register_hdc_and_sf_counter_query(perf);
   rkl_register_rasterizer_and_pixel_backend_counter_query(perf);
   rkl_register_l3_1_counter_query(perf);
   rkl_register_l3_2_counter_query(perf);
   rkl_register_l3_3_counter_query(perf);
   rkl_register_l3_4_counter_query(perf);
   rkl_register_l3_5_counter_query(perf);
   rkl_register_l3_6_counter_query(perf);
   rkl_register_sampler_1_counter_query(perf);
   rkl_register_tdl_1_counter_query(perf);
   rkl_register_gpu_busyness_counter_query(perf);
   rkl_register_eu_activity1_counter_query(perf);
   rkl_register_eu_activity2_counter_query(perf);
   rkl_register_eu_activity3_counter_query(perf);
   rkl_register_eu_activity4_counter_query(perf);
   rkl_register_eu_activity5_counter_query(perf);
   rkl_register_eu_activity6_counter_query(perf);
   rkl_register_eu_activity7_counter_query(perf);
   rkl_register_eu_activity8_counter_query(perf);
   rkl_register_test_oa_counter_query(perf);
}


static void
dg1_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 34);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "1caf6b6d-a1ef-40d3-9033-311e482b826e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14150001 },
         { .reg = 0x00009888, .val = 0x16150020 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0E124000 },
         { .reg = 0x00009888, .val = 0x10124000 },
         { .reg = 0x00009888, .val = 0x12124000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x1C130E00 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x06157000 },
         { .reg = 0x00009888, .val = 0x08157151 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x18150000 },
         { .reg = 0x00009888, .val = 0x1C150000 },
         { .reg = 0x00009888, .val = 0x00004000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x1C054000 },
         { .reg = 0x00009888, .val = 0x24050015 },
         { .reg = 0x00009888, .val = 0x10088000 },
         { .reg = 0x00009888, .val = 0x1C08000E },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D47 },
         { .reg = 0x00009888, .val = 0x09151536 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B1050BB },
         { .reg = 0x00009888, .val = 0x5D102C01 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x4B114000 },
         { .reg = 0x00009888, .val = 0x5F11A000 },
         { .reg = 0x00009888, .val = 0x61110002 },
         { .reg = 0x00009888, .val = 0x1F150137 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x0F168000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x1D350137 },
         { .reg = 0x00009888, .val = 0x03350147 },
         { .reg = 0x00009888, .val = 0x07350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x0F364000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55101610 },
         { .reg = 0x00009888, .val = 0x57100006 },
         { .reg = 0x00009888, .val = 0x49101616 },
         { .reg = 0x00009888, .val = 0x4B100616 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__render_basic__avg_gpu_core_frequency__max,dg1__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,dg1__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,dg1__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,dg1__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,dg1__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,dg1__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,dg1__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,dg1__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,dg1__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,dg1__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 84, percentage_max_float,dg1__render_basic__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 333, 88, percentage_max_float,dg1__render_basic__sampler00_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 435, 92, percentage_max_float,dg1__render_basic__sampler00_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 133, 96, percentage_max_float,dg1__render_basic__samplers_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 149, 100, percentage_max_float,dg1__render_basic__sampler_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 104, NULL,dg1__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 112, NULL,dg1__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 120, NULL,dg1__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 128, NULL,dg1__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 136, NULL,dg1__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 144, NULL,dg1__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 152, NULL,dg1__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 160, NULL,dg1__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 168, NULL,dg1__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 176, dg1__render_basic__slm_bytes_read__max,dg1__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 184, dg1__render_basic__slm_bytes_written__max,dg1__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 192, NULL,dg1__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 200, NULL,dg1__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 208, dg1__render_basic__l3_shader_throughput__max,dg1__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 216, NULL,dg1__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 224, dg1__render_basic__gti_read_throughput__max,dg1__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 232, dg1__render_basic__gti_write_throughput__max,dg1__render_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 30);

   query->name = "Compute Metrics Basic set";
   query->symbol_name = "ComputeBasic";
   query->guid = "e347a2bd-079d-4a77-b546-c3c114c55bae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__compute_basic__avg_gpu_core_frequency__max,dg1__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,dg1__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,dg1__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,dg1__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,dg1__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,dg1__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,dg1__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,dg1__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,dg1__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,dg1__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, dg1__compute_basic__slm_bytes_read__max,dg1__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, dg1__compute_basic__slm_bytes_written__max,dg1__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,dg1__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,dg1__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, dg1__compute_basic__l3_shader_throughput__max,dg1__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,dg1__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 216, dg1__compute_basic__gti_read_throughput__max,dg1__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 224, dg1__compute_basic__gti_write_throughput__max,dg1__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "3b27f553-aebc-45ec-aa2f-926d81a91fd9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00123E00 },
         { .reg = 0x00009888, .val = 0x10087C00 },
         { .reg = 0x00009888, .val = 0x060C40B3 },
         { .reg = 0x00009888, .val = 0x140C3C00 },
         { .reg = 0x00009888, .val = 0x1C0C0000 },
         { .reg = 0x00009888, .val = 0x120D0320 },
         { .reg = 0x00009888, .val = 0x040E3E00 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x280E0000 },
         { .reg = 0x00009888, .val = 0x2C0F001F },
         { .reg = 0x00009888, .val = 0x1E120002 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x1E130002 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x34005540 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x06004000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2A015500 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x06014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x2405FFDF },
         { .reg = 0x00009888, .val = 0x26050001 },
         { .reg = 0x00009888, .val = 0x2205FFF0 },
         { .reg = 0x00009888, .val = 0x08081000 },
         { .reg = 0x00009888, .val = 0x1C080200 },
         { .reg = 0x00009888, .val = 0x24065155 },
         { .reg = 0x00009888, .val = 0x26060015 },
         { .reg = 0x00009888, .val = 0x22065400 },
         { .reg = 0x00009888, .val = 0x1C0901F7 },
         { .reg = 0x00009888, .val = 0x14098000 },
         { .reg = 0x00009888, .val = 0x1A09F000 },
         { .reg = 0x00009888, .val = 0x0E0C0031 },
         { .reg = 0x00009888, .val = 0x180C0092 },
         { .reg = 0x00009888, .val = 0x1A0C00B1 },
         { .reg = 0x00009888, .val = 0x020C0093 },
         { .reg = 0x00009888, .val = 0x040C0033 },
         { .reg = 0x00009888, .val = 0x100C0000 },
         { .reg = 0x00009888, .val = 0x0C0C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x0A0D0022 },
         { .reg = 0x00009888, .val = 0x100D0000 },
         { .reg = 0x00009888, .val = 0x1E0DA5A8 },
         { .reg = 0x00009888, .val = 0x200D1A41 },
         { .reg = 0x00009888, .val = 0x100E0017 },
         { .reg = 0x00009888, .val = 0x160E0013 },
         { .reg = 0x00009888, .val = 0x1C0E0081 },
         { .reg = 0x00009888, .val = 0x080E0082 },
         { .reg = 0x00009888, .val = 0x0A0E0102 },
         { .reg = 0x00009888, .val = 0x140E0000 },
         { .reg = 0x00009888, .val = 0x0C0E0000 },
         { .reg = 0x00009888, .val = 0x0E0E0000 },
         { .reg = 0x00009888, .val = 0x120E0000 },
         { .reg = 0x00009888, .val = 0x0C0F0225 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x100B4000 },
         { .reg = 0x00009888, .val = 0x140B4000 },
         { .reg = 0x00009888, .val = 0x160B4000 },
         { .reg = 0x00009888, .val = 0x180B4000 },
         { .reg = 0x00009888, .val = 0x1A0B4000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x020B4000 },
         { .reg = 0x00009888, .val = 0x040B4000 },
         { .reg = 0x00009888, .val = 0x060B4000 },
         { .reg = 0x00009888, .val = 0x080B4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x0C0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x5F11AAAA },
         { .reg = 0x00009888, .val = 0x61112AAA },
         { .reg = 0x00009888, .val = 0x4D100002 },
         { .reg = 0x00009888, .val = 0x4F100202 },
         { .reg = 0x00009888, .val = 0x5110040A },
         { .reg = 0x00009888, .val = 0x53100202 },
         { .reg = 0x00009888, .val = 0x55100202 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100006 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100202 },
         { .reg = 0x00009888, .val = 0x4B100202 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__render_pipe_profile__avg_gpu_core_frequency__max,dg1__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__render_pipe_profile__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,dg1__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,dg1__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,dg1__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,dg1__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,dg1__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,dg1__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,dg1__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,dg1__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,dg1__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, dg1__render_pipe_profile__slm_bytes_read__max,dg1__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, dg1__render_pipe_profile__slm_bytes_written__max,dg1__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,dg1__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,dg1__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, dg1__render_pipe_profile__l3_shader_throughput__max,dg1__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,dg1__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 216, percentage_max_float,dg1__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 220, percentage_max_float,dg1__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 224, percentage_max_float,dg1__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 228, percentage_max_float,dg1__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 232, percentage_max_float,dg1__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 236, percentage_max_float,dg1__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 240, percentage_max_float,dg1__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 244, percentage_max_float,dg1__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 248, percentage_max_float,dg1__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 252, percentage_max_float,dg1__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 256, percentage_max_float,dg1__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 260, percentage_max_float,dg1__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 264, percentage_max_float,dg1__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 268, percentage_max_float,dg1__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 272, percentage_max_float,dg1__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Metric set HDCAndSF (DG1)";
   query->symbol_name = "HDCAndSF";
   query->guid = "1fa73aed-3861-4c19-8105-e55986c8a4e5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14112600 },
         { .reg = 0x00009888, .val = 0x14312600 },
         { .reg = 0x00009888, .val = 0x14512600 },
         { .reg = 0x00009888, .val = 0x14712600 },
         { .reg = 0x00009888, .val = 0x14912600 },
         { .reg = 0x00009888, .val = 0x14B12600 },
         { .reg = 0x00009888, .val = 0x120800A0 },
         { .reg = 0x00009888, .val = 0x120900A0 },
         { .reg = 0x00009888, .val = 0x120A00A0 },
         { .reg = 0x00009888, .val = 0x240B0019 },
         { .reg = 0x00009888, .val = 0x02110077 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x00110000 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x04310077 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x02310000 },
         { .reg = 0x00009888, .val = 0x04328000 },
         { .reg = 0x00009888, .val = 0x14338000 },
         { .reg = 0x00009888, .val = 0x06510077 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x02510000 },
         { .reg = 0x00009888, .val = 0x06528000 },
         { .reg = 0x00009888, .val = 0x16538000 },
         { .reg = 0x00009888, .val = 0x08710077 },
         { .reg = 0x00009888, .val = 0x10710000 },
         { .reg = 0x00009888, .val = 0x04710000 },
         { .reg = 0x00009888, .val = 0x08728000 },
         { .reg = 0x00009888, .val = 0x18738000 },
         { .reg = 0x00009888, .val = 0x0A910077 },
         { .reg = 0x00009888, .val = 0x10910000 },
         { .reg = 0x00009888, .val = 0x04910000 },
         { .reg = 0x00009888, .val = 0x0A928000 },
         { .reg = 0x00009888, .val = 0x1A938000 },
         { .reg = 0x00009888, .val = 0x0CB10077 },
         { .reg = 0x00009888, .val = 0x10B10000 },
         { .reg = 0x00009888, .val = 0x06B10000 },
         { .reg = 0x00009888, .val = 0x0CB28000 },
         { .reg = 0x00009888, .val = 0x1CB30100 },
         { .reg = 0x00009888, .val = 0x00004000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x34000540 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x06004000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2A011500 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x06014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x1C05C000 },
         { .reg = 0x00009888, .val = 0x240505FF },
         { .reg = 0x00009888, .val = 0x2205FF90 },
         { .reg = 0x00009888, .val = 0x0A082300 },
         { .reg = 0x00009888, .val = 0x0C080022 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x14088000 },
         { .reg = 0x00009888, .val = 0x1C064000 },
         { .reg = 0x00009888, .val = 0x24060156 },
         { .reg = 0x00009888, .val = 0x22064000 },
         { .reg = 0x00009888, .val = 0x08092300 },
         { .reg = 0x00009888, .val = 0x0A090022 },
         { .reg = 0x00009888, .val = 0x1C090007 },
         { .reg = 0x00009888, .val = 0x10098000 },
         { .reg = 0x00009888, .val = 0x1A09E000 },
         { .reg = 0x00009888, .val = 0x22078000 },
         { .reg = 0x00009888, .val = 0x060A2300 },
         { .reg = 0x00009888, .val = 0x080A0022 },
         { .reg = 0x00009888, .val = 0x100A0000 },
         { .reg = 0x00009888, .val = 0x180A0180 },
         { .reg = 0x00009888, .val = 0x1E0D5400 },
         { .reg = 0x00009888, .val = 0x200D0001 },
         { .reg = 0x00009888, .val = 0x0A0EC000 },
         { .reg = 0x00009888, .val = 0x0C0E4000 },
         { .reg = 0x00009888, .val = 0x080E8000 },
         { .reg = 0x00009888, .val = 0x000B00F7 },
         { .reg = 0x00009888, .val = 0x200B0000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x100B4000 },
         { .reg = 0x00009888, .val = 0x060B8000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x0C0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D100055 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D140007 },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B114000 },
         { .reg = 0x00009888, .val = 0x5F11AAAA },
         { .reg = 0x00009888, .val = 0x611100AA },
         { .reg = 0x00009888, .val = 0x47101310 },
         { .reg = 0x00009888, .val = 0x4D100002 },
         { .reg = 0x00009888, .val = 0x4F101808 },
         { .reg = 0x00009888, .val = 0x51101717 },
         { .reg = 0x00009888, .val = 0x53100717 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x49100311 },
         { .reg = 0x00009888, .val = 0x4B100A08 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x000F0000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000DC00, .val = 0x00000002 },
         { .reg = 0x0000DC04, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000030 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000DC08, .val = 0x00000030 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x000000C0 },
         { .reg = 0x0000D954, .val = 0x0000FFE7 },
         { .reg = 0x0000DC10, .val = 0x000000C0 },
         { .reg = 0x0000DC14, .val = 0x0000FFE7 },
         { .reg = 0x0000D958, .val = 0x00000300 },
         { .reg = 0x0000D95C, .val = 0x0000FF9F },
         { .reg = 0x0000DC18, .val = 0x00000300 },
         { .reg = 0x0000DC1C, .val = 0x0000FF9F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__hdc_and_sf__avg_gpu_core_frequency__max,dg1__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__hdc_and_sf__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,dg1__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,dg1__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,dg1__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,dg1__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,dg1__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,dg1__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,dg1__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,dg1__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,dg1__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, dg1__hdc_and_sf__slm_bytes_read__max,dg1__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, dg1__hdc_and_sf__slm_bytes_written__max,dg1__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,dg1__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,dg1__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, dg1__hdc_and_sf__l3_shader_throughput__max,dg1__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,dg1__hdc_and_sf__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 356, 216, percentage_max_float,dg1__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 357, 220, percentage_max_float,dg1__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 358, 224, percentage_max_float,dg1__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 359, 228, percentage_max_float,dg1__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 490, 232, percentage_max_float,dg1__hdc_and_sf__non_sampler_shader04_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 491, 236, percentage_max_float,dg1__hdc_and_sf__non_sampler_shader05_access_stalled_on_l3__read);
      }

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,dg1__hdc_and_sf__poly_data_ready__read);

      intel_perf_query_add_counter_float(query, 360, 244, percentage_max_float,dg1__hdc_and_sf__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 361, 248, percentage_max_float,dg1__hdc_and_sf__pixel_data01_ready__read);

      intel_perf_query_add_counter_float(query, 538, 252, percentage_max_float,dg1__hdc_and_sf__pixel_data02_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "2bb016ee-a9b7-477e-8d5d-f7fd179a8f16";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1E055000 },
         { .reg = 0x00009888, .val = 0x1A0500C0 },
         { .reg = 0x00009888, .val = 0x1E065000 },
         { .reg = 0x00009888, .val = 0x1A0600C0 },
         { .reg = 0x00009888, .val = 0x1E075000 },
         { .reg = 0x00009888, .val = 0x1A0700C0 },
         { .reg = 0x00009888, .val = 0x2A0B7300 },
         { .reg = 0x00009888, .val = 0x2C0B0000 },
         { .reg = 0x00009888, .val = 0x00004000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x34005500 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x2A015400 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x0C05C000 },
         { .reg = 0x00009888, .val = 0x00052700 },
         { .reg = 0x00009888, .val = 0x10050000 },
         { .reg = 0x00009888, .val = 0x1C05C000 },
         { .reg = 0x00009888, .val = 0x2405CF0F },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x220500C0 },
         { .reg = 0x00009888, .val = 0x0C0600D0 },
         { .reg = 0x00009888, .val = 0x0E062700 },
         { .reg = 0x00009888, .val = 0x10060000 },
         { .reg = 0x00009888, .val = 0x1C064000 },
         { .reg = 0x00009888, .val = 0x24064140 },
         { .reg = 0x00009888, .val = 0x26060010 },
         { .reg = 0x00009888, .val = 0x22061000 },
         { .reg = 0x00009888, .val = 0x10098000 },
         { .reg = 0x00009888, .val = 0x1C090366 },
         { .reg = 0x00009888, .val = 0x1A091000 },
         { .reg = 0x00009888, .val = 0x0A07C000 },
         { .reg = 0x00009888, .val = 0x0E070027 },
         { .reg = 0x00009888, .val = 0x10070000 },
         { .reg = 0x00009888, .val = 0x24070000 },
         { .reg = 0x00009888, .val = 0x1A0A0104 },
         { .reg = 0x00009888, .val = 0x200D1040 },
         { .reg = 0x00009888, .val = 0x0E0E8000 },
         { .reg = 0x00009888, .val = 0x120E4000 },
         { .reg = 0x00009888, .val = 0x000B0144 },
         { .reg = 0x00009888, .val = 0x0E0B0145 },
         { .reg = 0x00009888, .val = 0x100B0156 },
         { .reg = 0x00009888, .val = 0x040B014F },
         { .reg = 0x00009888, .val = 0x200B0000 },
         { .reg = 0x00009888, .val = 0x160B4000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x19151400 },
         { .reg = 0x00009888, .val = 0x21152800 },
         { .reg = 0x00009888, .val = 0x19351400 },
         { .reg = 0x00009888, .val = 0x21352800 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105FA5 },
         { .reg = 0x00009888, .val = 0x5D101550 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B146000 },
         { .reg = 0x00009888, .val = 0x1D14003E },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x4B114000 },
         { .reg = 0x00009888, .val = 0x5F11A00A },
         { .reg = 0x00009888, .val = 0x61112AA0 },
         { .reg = 0x00009888, .val = 0x07150016 },
         { .reg = 0x00009888, .val = 0x09150096 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03168000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x0B350016 },
         { .reg = 0x00009888, .val = 0x0D350096 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x07364000 },
         { .reg = 0x00009888, .val = 0x47101800 },
         { .reg = 0x00009888, .val = 0x4D100131 },
         { .reg = 0x00009888, .val = 0x4F100808 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x53101A00 },
         { .reg = 0x00009888, .val = 0x55100003 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x5710000A },
         { .reg = 0x00009888, .val = 0x49103803 },
         { .reg = 0x00009888, .val = 0x4B103131 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000DC00, .val = 0x00000038 },
         { .reg = 0x0000DC04, .val = 0x0000FFF8 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,dg1__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__rasterizer_and_pixel_backend__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,dg1__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,dg1__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,dg1__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,dg1__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,dg1__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,dg1__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,dg1__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,dg1__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,dg1__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, dg1__rasterizer_and_pixel_backend__slm_bytes_read__max,dg1__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, dg1__rasterizer_and_pixel_backend__slm_bytes_written__max,dg1__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,dg1__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,dg1__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, dg1__rasterizer_and_pixel_backend__l3_shader_throughput__max,dg1__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,dg1__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 266, 216, percentage_max_float,dg1__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 261, 220, percentage_max_float,dg1__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 362, 224, percentage_max_float,dg1__rasterizer_and_pixel_backend__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 363, 228, percentage_max_float,dg1__rasterizer_and_pixel_backend__ps_output01_available__read);

      intel_perf_query_add_counter_float(query, 492, 232, percentage_max_float,dg1__rasterizer_and_pixel_backend__ps_output02_available__read);

      intel_perf_query_add_counter_float(query, 364, 236, percentage_max_float,dg1__rasterizer_and_pixel_backend__pixel_values00_ready__read);

      intel_perf_query_add_counter_float(query, 365, 240, percentage_max_float,dg1__rasterizer_and_pixel_backend__pixel_values01_ready__read);

      intel_perf_query_add_counter_float(query, 493, 244, percentage_max_float,dg1__rasterizer_and_pixel_backend__pixel_values02_ready__read);

      intel_perf_query_add_counter_float(query, 436, 248, percentage_max_float,dg1__rasterizer_and_pixel_backend__gt_request_queue00_full__read);

      intel_perf_query_add_counter_float(query, 437, 252, percentage_max_float,dg1__rasterizer_and_pixel_backend__gt_request_queue01_full__read);

      intel_perf_query_add_counter_float(query, 438, 256, percentage_max_float,dg1__rasterizer_and_pixel_backend__gt_request_queue10_full__read);

      intel_perf_query_add_counter_float(query, 439, 260, percentage_max_float,dg1__rasterizer_and_pixel_backend__gt_request_queue11_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "L3_1";
   query->symbol_name = "L3_1";
   query->guid = "cdccda4b-c7c9-41a9-965f-fc2adf8cff0b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04022000 },
         { .reg = 0x00009888, .val = 0x06022800 },
         { .reg = 0x00009888, .val = 0x04002827 },
         { .reg = 0x00009888, .val = 0x0600202C },
         { .reg = 0x00009888, .val = 0x00020024 },
         { .reg = 0x00009888, .val = 0x0E020025 },
         { .reg = 0x00009888, .val = 0x10020026 },
         { .reg = 0x00009888, .val = 0x12020027 },
         { .reg = 0x00009888, .val = 0x1402002C },
         { .reg = 0x00009888, .val = 0x1602002D },
         { .reg = 0x00009888, .val = 0x1802002E },
         { .reg = 0x00009888, .val = 0x1A02002F },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x2C020000 },
         { .reg = 0x00009888, .val = 0x1C000024 },
         { .reg = 0x00009888, .val = 0x1E000025 },
         { .reg = 0x00009888, .val = 0x02000026 },
         { .reg = 0x00009888, .val = 0x0800002D },
         { .reg = 0x00009888, .val = 0x0A00002E },
         { .reg = 0x00009888, .val = 0x0C00002F },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009888, .val = 0x00004000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x34001540 },
         { .reg = 0x00009888, .val = 0x36000000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2A015500 },
         { .reg = 0x00009888, .val = 0x1C05C000 },
         { .reg = 0x00009888, .val = 0x24053FFF },
         { .reg = 0x00009888, .val = 0x1C064000 },
         { .reg = 0x00009888, .val = 0x24065540 },
         { .reg = 0x00009888, .val = 0x26060005 },
         { .reg = 0x00009888, .val = 0x10098000 },
         { .reg = 0x00009888, .val = 0x1C0900FE },
         { .reg = 0x00009888, .val = 0x1C074000 },
         { .reg = 0x00009888, .val = 0x24071555 },
         { .reg = 0x00009888, .val = 0x160A1000 },
         { .reg = 0x00009888, .val = 0x180A5400 },
         { .reg = 0x00009888, .val = 0x1A0A0055 },
         { .reg = 0x00009888, .val = 0x1E0D4001 },
         { .reg = 0x00009888, .val = 0x200D0555 },
         { .reg = 0x00009888, .val = 0x040E4000 },
         { .reg = 0x00009888, .val = 0x0A0E8000 },
         { .reg = 0x00009888, .val = 0x0C0EC000 },
         { .reg = 0x00009888, .val = 0x0E0EC000 },
         { .reg = 0x00009888, .val = 0x100EC000 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x100B4000 },
         { .reg = 0x00009888, .val = 0x120B4000 },
         { .reg = 0x00009888, .val = 0x140B4000 },
         { .reg = 0x00009888, .val = 0x160B4000 },
         { .reg = 0x00009888, .val = 0x180B4000 },
         { .reg = 0x00009888, .val = 0x1A0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B114000 },
         { .reg = 0x00009888, .val = 0x5F11AAAA },
         { .reg = 0x00009888, .val = 0x61112AAA },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x4D100919 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x53100000 },
         { .reg = 0x00009888, .val = 0x55101910 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100009 },
         { .reg = 0x00009888, .val = 0x49101919 },
         { .reg = 0x00009888, .val = 0x4B101919 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__l3_1__avg_gpu_core_frequency__max,dg1__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,dg1__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,dg1__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,dg1__l3_1__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,dg1__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,dg1__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,dg1__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,dg1__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,dg1__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,dg1__l3_1__cs_threads__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 440, 88, percentage_max_float,dg1__l3_1__l30_bank0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 441, 92, percentage_max_float,dg1__l3_1__l30_bank1_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 494, 96, percentage_max_float,dg1__l3_1__l30_bank4_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 495, 100, percentage_max_float,dg1__l3_1__l30_bank5_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "L3_2";
   query->symbol_name = "L3_2";
   query->guid = "3c44fb1b-f9b3-4d52-a507-e2b2a80ec8b7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04023027 },
         { .reg = 0x00009888, .val = 0x0602382C },
         { .reg = 0x00009888, .val = 0x04007000 },
         { .reg = 0x00009888, .val = 0x06007800 },
         { .reg = 0x00009888, .val = 0x1C020024 },
         { .reg = 0x00009888, .val = 0x1E020025 },
         { .reg = 0x00009888, .val = 0x02020026 },
         { .reg = 0x00009888, .val = 0x0802002D },
         { .reg = 0x00009888, .val = 0x0A02002E },
         { .reg = 0x00009888, .val = 0x0C02002F },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x2C020000 },
         { .reg = 0x00009888, .val = 0x00000024 },
         { .reg = 0x00009888, .val = 0x0E000025 },
         { .reg = 0x00009888, .val = 0x10000026 },
         { .reg = 0x00009888, .val = 0x12000027 },
         { .reg = 0x00009888, .val = 0x1400002C },
         { .reg = 0x00009888, .val = 0x1600002D },
         { .reg = 0x00009888, .val = 0x1800002E },
         { .reg = 0x00009888, .val = 0x1A00002F },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x06014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x2205FFF0 },
         { .reg = 0x00009888, .val = 0x26060050 },
         { .reg = 0x00009888, .val = 0x22065400 },
         { .reg = 0x00009888, .val = 0x24060015 },
         { .reg = 0x00009888, .val = 0x1C090301 },
         { .reg = 0x00009888, .val = 0x14098000 },
         { .reg = 0x00009888, .val = 0x1A09F000 },
         { .reg = 0x00009888, .val = 0x24074000 },
         { .reg = 0x00009888, .val = 0x26070001 },
         { .reg = 0x00009888, .val = 0x22075550 },
         { .reg = 0x00009888, .val = 0x1A0A0500 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x180A0155 },
         { .reg = 0x00009888, .val = 0x200D5000 },
         { .reg = 0x00009888, .val = 0x1E0D1554 },
         { .reg = 0x00009888, .val = 0x120EC000 },
         { .reg = 0x00009888, .val = 0x040E8000 },
         { .reg = 0x00009888, .val = 0x060EC000 },
         { .reg = 0x00009888, .val = 0x080EC000 },
         { .reg = 0x00009888, .val = 0x0A0E4000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009888, .val = 0x020B4000 },
         { .reg = 0x00009888, .val = 0x040B4000 },
         { .reg = 0x00009888, .val = 0x060B4000 },
         { .reg = 0x00009888, .val = 0x080B4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x0C0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B114000 },
         { .reg = 0x00009888, .val = 0x5F11AAAA },
         { .reg = 0x00009888, .val = 0x61112AAA },
         { .reg = 0x00009888, .val = 0x47100910 },
         { .reg = 0x00009888, .val = 0x4D101000 },
         { .reg = 0x00009888, .val = 0x4F101919 },
         { .reg = 0x00009888, .val = 0x51101919 },
         { .reg = 0x00009888, .val = 0x53101919 },
         { .reg = 0x00009888, .val = 0x55100009 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__l3_2__avg_gpu_core_frequency__max,dg1__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__l3_2__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 442, 92, percentage_max_float,dg1__l3_2__l30_bank2_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 443, 96, percentage_max_float,dg1__l3_2__l30_bank3_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 496, 100, percentage_max_float,dg1__l3_2__l30_bank6_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 497, 104, percentage_max_float,dg1__l3_2__l30_bank7_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_3";
   query->symbol_name = "L3_3";
   query->guid = "ec911098-71bf-4432-9153-6143e3cfbe06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04020200 },
         { .reg = 0x00009888, .val = 0x06020020 },
         { .reg = 0x00009888, .val = 0x04000200 },
         { .reg = 0x00009888, .val = 0x06004000 },
         { .reg = 0x00009888, .val = 0x08020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x0A000020 },
         { .reg = 0x00009888, .val = 0x0C000028 },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x06014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x22050F00 },
         { .reg = 0x00009888, .val = 0x22064000 },
         { .reg = 0x00009888, .val = 0x24060001 },
         { .reg = 0x00009888, .val = 0x1A096000 },
         { .reg = 0x00009888, .val = 0x22070500 },
         { .reg = 0x00009888, .val = 0x180A0014 },
         { .reg = 0x00009888, .val = 0x1E0D0140 },
         { .reg = 0x00009888, .val = 0x060E8000 },
         { .reg = 0x00009888, .val = 0x080E4000 },
         { .reg = 0x00009888, .val = 0x060B4000 },
         { .reg = 0x00009888, .val = 0x080B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x5F110AA0 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B101000 },
         { .reg = 0x00009888, .val = 0x4D100919 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__l3_3__avg_gpu_core_frequency__max,dg1__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__l3_3__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 444, 92, percentage_max_float,dg1__l3_3__l30_bank0_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 498, 96, percentage_max_float,dg1__l3_3__l30_bank4_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_l3_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_4";
   query->symbol_name = "L3_4";
   query->guid = "17d351db-7916-4eea-9817-29ca522daacd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04020A00 },
         { .reg = 0x00009888, .val = 0x06020800 },
         { .reg = 0x00009888, .val = 0x04000A00 },
         { .reg = 0x00009888, .val = 0x06000820 },
         { .reg = 0x00009888, .val = 0x0A020020 },
         { .reg = 0x00009888, .val = 0x0C020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x2205F000 },
         { .reg = 0x00009888, .val = 0x24060014 },
         { .reg = 0x00009888, .val = 0x1A098000 },
         { .reg = 0x00009888, .val = 0x1C090001 },
         { .reg = 0x00009888, .val = 0x22075000 },
         { .reg = 0x00009888, .val = 0x180A0140 },
         { .reg = 0x00009888, .val = 0x1E0D1400 },
         { .reg = 0x00009888, .val = 0x080E8000 },
         { .reg = 0x00009888, .val = 0x0A0E4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x0C0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x5F110AA0 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49101000 },
         { .reg = 0x00009888, .val = 0x4B100919 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__l3_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__l3_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__l3_4__avg_gpu_core_frequency__max,dg1__l3_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__l3_4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__l3_4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__l3_4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__l3_4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__l3_4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__l3_4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__l3_4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__l3_4__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__l3_4__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__l3_4__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 445, 92, percentage_max_float,dg1__l3_4__l30_bank1_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 499, 96, percentage_max_float,dg1__l3_4__l30_bank5_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_l3_5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_5";
   query->symbol_name = "L3_5";
   query->guid = "f2de5846-f330-4d26-ad41-824deb6b53f6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04021200 },
         { .reg = 0x00009888, .val = 0x06021000 },
         { .reg = 0x00009888, .val = 0x04001200 },
         { .reg = 0x00009888, .val = 0x06001020 },
         { .reg = 0x00009888, .val = 0x0A020020 },
         { .reg = 0x00009888, .val = 0x0C020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x2205F000 },
         { .reg = 0x00009888, .val = 0x24060014 },
         { .reg = 0x00009888, .val = 0x1A098000 },
         { .reg = 0x00009888, .val = 0x1C090001 },
         { .reg = 0x00009888, .val = 0x22075000 },
         { .reg = 0x00009888, .val = 0x180A0140 },
         { .reg = 0x00009888, .val = 0x1E0D1400 },
         { .reg = 0x00009888, .val = 0x080E8000 },
         { .reg = 0x00009888, .val = 0x0A0E4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x0C0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x5F110AA0 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49101000 },
         { .reg = 0x00009888, .val = 0x4B100919 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__l3_5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__l3_5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__l3_5__avg_gpu_core_frequency__max,dg1__l3_5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__l3_5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__l3_5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__l3_5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__l3_5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__l3_5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__l3_5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__l3_5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__l3_5__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__l3_5__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__l3_5__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 446, 92, percentage_max_float,dg1__l3_5__l30_bank2_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 500, 96, percentage_max_float,dg1__l3_5__l30_bank6_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_l3_6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_6";
   query->symbol_name = "L3_6";
   query->guid = "8f4ccb12-ee11-4741-93d4-d431b8ca58ef";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04021A00 },
         { .reg = 0x00009888, .val = 0x06021800 },
         { .reg = 0x00009888, .val = 0x04001A00 },
         { .reg = 0x00009888, .val = 0x06001820 },
         { .reg = 0x00009888, .val = 0x0A020020 },
         { .reg = 0x00009888, .val = 0x0C020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x3A000000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x2205F000 },
         { .reg = 0x00009888, .val = 0x24060014 },
         { .reg = 0x00009888, .val = 0x1A098000 },
         { .reg = 0x00009888, .val = 0x1C090001 },
         { .reg = 0x00009888, .val = 0x22075000 },
         { .reg = 0x00009888, .val = 0x180A0140 },
         { .reg = 0x00009888, .val = 0x1E0D1400 },
         { .reg = 0x00009888, .val = 0x080E8000 },
         { .reg = 0x00009888, .val = 0x0A0E4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x0C0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x5F110AA0 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49101000 },
         { .reg = 0x00009888, .val = 0x4B100919 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__l3_6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__l3_6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__l3_6__avg_gpu_core_frequency__max,dg1__l3_6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__l3_6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__l3_6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__l3_6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__l3_6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__l3_6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__l3_6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__l3_6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__l3_6__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__l3_6__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__l3_6__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 447, 92, percentage_max_float,dg1__l3_6__l30_bank3_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 501, 96, percentage_max_float,dg1__l3_6__l30_bank7_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Sampler_1";
   query->symbol_name = "Sampler_1";
   query->guid = "d336f948-7e5c-41a9-be57-e3b01b8c829a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C121600 },
         { .reg = 0x00009888, .val = 0x18141600 },
         { .reg = 0x00009888, .val = 0x1C325600 },
         { .reg = 0x00009888, .val = 0x18341600 },
         { .reg = 0x00009888, .val = 0x1C521600 },
         { .reg = 0x00009888, .val = 0x185416A6 },
         { .reg = 0x00009888, .val = 0x1C721600 },
         { .reg = 0x00009888, .val = 0x18741600 },
         { .reg = 0x00009888, .val = 0x1C921600 },
         { .reg = 0x00009888, .val = 0x18941600 },
         { .reg = 0x00009888, .val = 0x1CB21600 },
         { .reg = 0x00009888, .val = 0x18B41600 },
         { .reg = 0x00009888, .val = 0x04120086 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x02124000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x021400A6 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x00140000 },
         { .reg = 0x00009888, .val = 0x1A150020 },
         { .reg = 0x00009888, .val = 0x1E320086 },
         { .reg = 0x00009888, .val = 0x20320000 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x1C3400A6 },
         { .reg = 0x00009888, .val = 0x10340000 },
         { .reg = 0x00009888, .val = 0x0E340000 },
         { .reg = 0x00009888, .val = 0x1C358000 },
         { .reg = 0x00009888, .val = 0x1A520086 },
         { .reg = 0x00009888, .val = 0x20520000 },
         { .reg = 0x00009888, .val = 0x18524000 },
         { .reg = 0x00009888, .val = 0x1C53C000 },
         { .reg = 0x00009888, .val = 0x10540000 },
         { .reg = 0x00009888, .val = 0x0C540000 },
         { .reg = 0x00009888, .val = 0x1C550800 },
         { .reg = 0x00009888, .val = 0x16720086 },
         { .reg = 0x00009888, .val = 0x20720000 },
         { .reg = 0x00009888, .val = 0x14724000 },
         { .reg = 0x00009888, .val = 0x1C733000 },
         { .reg = 0x00009888, .val = 0x147400A6 },
         { .reg = 0x00009888, .val = 0x10740000 },
         { .reg = 0x00009888, .val = 0x0A740000 },
         { .reg = 0x00009888, .val = 0x1C750080 },
         { .reg = 0x00009888, .val = 0x12920086 },
         { .reg = 0x00009888, .val = 0x20920000 },
         { .reg = 0x00009888, .val = 0x10924000 },
         { .reg = 0x00009888, .val = 0x1C930C00 },
         { .reg = 0x00009888, .val = 0x109400A6 },
         { .reg = 0x00009888, .val = 0x08940000 },
         { .reg = 0x00009888, .val = 0x1C950008 },
         { .reg = 0x00009888, .val = 0x0EB20086 },
         { .reg = 0x00009888, .val = 0x20B20000 },
         { .reg = 0x00009888, .val = 0x00B24000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1CB30200 },
         { .reg = 0x00009888, .val = 0x00B400A6 },
         { .reg = 0x00009888, .val = 0x10B40000 },
         { .reg = 0x00009888, .val = 0x18B58000 },
         { .reg = 0x00009888, .val = 0x00004000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x34005540 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2A015500 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x1C05C000 },
         { .reg = 0x00009888, .val = 0x2405BFFF },
         { .reg = 0x00009888, .val = 0x26050002 },
         { .reg = 0x00009888, .val = 0x22050050 },
         { .reg = 0x00009888, .val = 0x14088000 },
         { .reg = 0x00009888, .val = 0x1A081000 },
         { .reg = 0x00009888, .val = 0x1C064000 },
         { .reg = 0x00009888, .val = 0x2406A540 },
         { .reg = 0x00009888, .val = 0x26060005 },
         { .reg = 0x00009888, .val = 0x10098000 },
         { .reg = 0x00009888, .val = 0x1C0900FE },
         { .reg = 0x00009888, .val = 0x1C078000 },
         { .reg = 0x00009888, .val = 0x24070002 },
         { .reg = 0x00009888, .val = 0x160A1000 },
         { .reg = 0x00009888, .val = 0x180AA400 },
         { .reg = 0x00009888, .val = 0x1E0D4001 },
         { .reg = 0x00009888, .val = 0x200D0005 },
         { .reg = 0x00009888, .val = 0x040E4000 },
         { .reg = 0x00009888, .val = 0x0A0E8000 },
         { .reg = 0x00009888, .val = 0x0C0EC000 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x100B4000 },
         { .reg = 0x00009888, .val = 0x120B4000 },
         { .reg = 0x00009888, .val = 0x180B8000 },
         { .reg = 0x00009888, .val = 0x1A0B8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105005 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x4B114000 },
         { .reg = 0x00009888, .val = 0x5F11A00A },
         { .reg = 0x00009888, .val = 0x61112AAA },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100204 },
         { .reg = 0x00009888, .val = 0x51101A06 },
         { .reg = 0x00009888, .val = 0x53101803 },
         { .reg = 0x00009888, .val = 0x55101311 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100007 },
         { .reg = 0x00009888, .val = 0x49100511 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000DC40, .val = 0x003F0000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000180 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000600 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000DC20, .val = 0x00001800 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000DC28, .val = 0x00006000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__sampler_1__avg_gpu_core_frequency__max,dg1__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__sampler_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__sampler_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__sampler_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__sampler_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__sampler_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__sampler_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__sampler_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__sampler_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__sampler_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__sampler_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 448, 92, percentage_max_float,dg1__sampler_1__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 449, 96, percentage_max_float,dg1__sampler_1__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 502, 100, percentage_max_float,dg1__sampler_1__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 503, 104, percentage_max_float,dg1__sampler_1__sampler03_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 504, 108, percentage_max_float,dg1__sampler_1__sampler04_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 505, 112, percentage_max_float,dg1__sampler_1__sampler05_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_sampler_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Sampler_2";
   query->symbol_name = "Sampler_2";
   query->guid = "c2929b2d-4ce9-4161-a1ac-fff0a75436b9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C123E00 },
         { .reg = 0x00009888, .val = 0x04143E00 },
         { .reg = 0x00009888, .val = 0x0C323E00 },
         { .reg = 0x00009888, .val = 0x04343E00 },
         { .reg = 0x00009888, .val = 0x0C523E00 },
         { .reg = 0x00009888, .val = 0x04543E00 },
         { .reg = 0x00009888, .val = 0x0C723E00 },
         { .reg = 0x00009888, .val = 0x04743E00 },
         { .reg = 0x00009888, .val = 0x0C923E00 },
         { .reg = 0x00009888, .val = 0x04943E00 },
         { .reg = 0x00009888, .val = 0x0CB23E00 },
         { .reg = 0x00009888, .val = 0x04B43E00 },
         { .reg = 0x00009888, .val = 0x04120033 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x02124000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x02140013 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x00140000 },
         { .reg = 0x00009888, .val = 0x1A150020 },
         { .reg = 0x00009888, .val = 0x1E320033 },
         { .reg = 0x00009888, .val = 0x20320000 },
         { .reg = 0x00009888, .val = 0x1C324000 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x1C340013 },
         { .reg = 0x00009888, .val = 0x10340000 },
         { .reg = 0x00009888, .val = 0x0E340000 },
         { .reg = 0x00009888, .val = 0x1C358000 },
         { .reg = 0x00009888, .val = 0x1A520033 },
         { .reg = 0x00009888, .val = 0x20520000 },
         { .reg = 0x00009888, .val = 0x18524000 },
         { .reg = 0x00009888, .val = 0x1C53C000 },
         { .reg = 0x00009888, .val = 0x18540013 },
         { .reg = 0x00009888, .val = 0x10540000 },
         { .reg = 0x00009888, .val = 0x0C540000 },
         { .reg = 0x00009888, .val = 0x1C550800 },
         { .reg = 0x00009888, .val = 0x16720033 },
         { .reg = 0x00009888, .val = 0x20720000 },
         { .reg = 0x00009888, .val = 0x14724000 },
         { .reg = 0x00009888, .val = 0x1C733000 },
         { .reg = 0x00009888, .val = 0x14740013 },
         { .reg = 0x00009888, .val = 0x10740000 },
         { .reg = 0x00009888, .val = 0x0A740000 },
         { .reg = 0x00009888, .val = 0x1C750080 },
         { .reg = 0x00009888, .val = 0x12920033 },
         { .reg = 0x00009888, .val = 0x20920000 },
         { .reg = 0x00009888, .val = 0x10924000 },
         { .reg = 0x00009888, .val = 0x1C930C00 },
         { .reg = 0x00009888, .val = 0x10940013 },
         { .reg = 0x00009888, .val = 0x08940000 },
         { .reg = 0x00009888, .val = 0x1C950008 },
         { .reg = 0x00009888, .val = 0x0EB20033 },
         { .reg = 0x00009888, .val = 0x20B20000 },
         { .reg = 0x00009888, .val = 0x00B24000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1CB30200 },
         { .reg = 0x00009888, .val = 0x00B40013 },
         { .reg = 0x00009888, .val = 0x10B40000 },
         { .reg = 0x00009888, .val = 0x18B58000 },
         { .reg = 0x00009888, .val = 0x00004000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x34005540 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2A015500 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x1C05C000 },
         { .reg = 0x00009888, .val = 0x2405BFFF },
         { .reg = 0x00009888, .val = 0x26050002 },
         { .reg = 0x00009888, .val = 0x22050050 },
         { .reg = 0x00009888, .val = 0x14088000 },
         { .reg = 0x00009888, .val = 0x1A081000 },
         { .reg = 0x00009888, .val = 0x1C064000 },
         { .reg = 0x00009888, .val = 0x2406A540 },
         { .reg = 0x00009888, .val = 0x26060005 },
         { .reg = 0x00009888, .val = 0x10098000 },
         { .reg = 0x00009888, .val = 0x1C0900FE },
         { .reg = 0x00009888, .val = 0x1C078000 },
         { .reg = 0x00009888, .val = 0x24070002 },
         { .reg = 0x00009888, .val = 0x160A1000 },
         { .reg = 0x00009888, .val = 0x180AA400 },
         { .reg = 0x00009888, .val = 0x1E0D4001 },
         { .reg = 0x00009888, .val = 0x200D0005 },
         { .reg = 0x00009888, .val = 0x040E4000 },
         { .reg = 0x00009888, .val = 0x0A0E8000 },
         { .reg = 0x00009888, .val = 0x0C0EC000 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x100B4000 },
         { .reg = 0x00009888, .val = 0x120B4000 },
         { .reg = 0x00009888, .val = 0x180B8000 },
         { .reg = 0x00009888, .val = 0x1A0B8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105005 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14E000 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x4B114000 },
         { .reg = 0x00009888, .val = 0x5F11A00A },
         { .reg = 0x00009888, .val = 0x61112AAA },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100204 },
         { .reg = 0x00009888, .val = 0x51101A06 },
         { .reg = 0x00009888, .val = 0x53101803 },
         { .reg = 0x00009888, .val = 0x55101311 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100007 },
         { .reg = 0x00009888, .val = 0x49100511 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000DC40, .val = 0x003F0000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000180 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000600 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000DC20, .val = 0x00001800 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000DC28, .val = 0x00006000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__sampler_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__sampler_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__sampler_2__avg_gpu_core_frequency__max,dg1__sampler_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__sampler_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__sampler_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__sampler_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__sampler_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__sampler_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__sampler_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__sampler_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__sampler_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__sampler_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__sampler_2__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 450, 92, percentage_max_float,dg1__sampler_2__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 451, 96, percentage_max_float,dg1__sampler_2__sampler01_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 506, 100, percentage_max_float,dg1__sampler_2__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 507, 104, percentage_max_float,dg1__sampler_2__sampler03_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 508, 108, percentage_max_float,dg1__sampler_2__sampler04_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 509, 112, percentage_max_float,dg1__sampler_2__sampler05_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "a98b240c-71b7-4e72-b167-8538a581e26d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2611001C },
         { .reg = 0x00009888, .val = 0x2631001C },
         { .reg = 0x00009888, .val = 0x2651001C },
         { .reg = 0x00009888, .val = 0x2671001C },
         { .reg = 0x00009888, .val = 0x2691001C },
         { .reg = 0x00009888, .val = 0x26B1001C },
         { .reg = 0x00009888, .val = 0x16110103 },
         { .reg = 0x00009888, .val = 0x1C110104 },
         { .reg = 0x00009888, .val = 0x1E110105 },
         { .reg = 0x00009888, .val = 0x02110106 },
         { .reg = 0x00009888, .val = 0x04110107 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x0A110000 },
         { .reg = 0x00009888, .val = 0x0E110000 },
         { .reg = 0x00009888, .val = 0x00110000 },
         { .reg = 0x00009888, .val = 0x16128000 },
         { .reg = 0x00009888, .val = 0x1C128000 },
         { .reg = 0x00009888, .val = 0x1E128000 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x1C132000 },
         { .reg = 0x00009888, .val = 0x1E130003 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x14310103 },
         { .reg = 0x00009888, .val = 0x06310104 },
         { .reg = 0x00009888, .val = 0x08310105 },
         { .reg = 0x00009888, .val = 0x0A310106 },
         { .reg = 0x00009888, .val = 0x0C310107 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x02310000 },
         { .reg = 0x00009888, .val = 0x04310000 },
         { .reg = 0x00009888, .val = 0x14328000 },
         { .reg = 0x00009888, .val = 0x06328000 },
         { .reg = 0x00009888, .val = 0x08328000 },
         { .reg = 0x00009888, .val = 0x0A328000 },
         { .reg = 0x00009888, .val = 0x0C328000 },
         { .reg = 0x00009888, .val = 0x1C331100 },
         { .reg = 0x00009888, .val = 0x16338000 },
         { .reg = 0x00009888, .val = 0x18338000 },
         { .reg = 0x00009888, .val = 0x1A338000 },
         { .reg = 0x00009888, .val = 0x12510103 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x08510000 },
         { .reg = 0x00009888, .val = 0x12528000 },
         { .reg = 0x00009888, .val = 0x1C530800 },
         { .reg = 0x00009888, .val = 0x10710103 },
         { .reg = 0x00009888, .val = 0x08710000 },
         { .reg = 0x00009888, .val = 0x10728000 },
         { .reg = 0x00009888, .val = 0x1C730400 },
         { .reg = 0x00009888, .val = 0x0E910103 },
         { .reg = 0x00009888, .val = 0x10910000 },
         { .reg = 0x00009888, .val = 0x06910000 },
         { .reg = 0x00009888, .val = 0x0E928000 },
         { .reg = 0x00009888, .val = 0x1C930200 },
         { .reg = 0x00009888, .val = 0x00B10103 },
         { .reg = 0x00009888, .val = 0x10B10000 },
         { .reg = 0x00009888, .val = 0x00B28000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x00004000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x34004140 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x06004000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2A010500 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x06014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x1C05C000 },
         { .reg = 0x00009888, .val = 0x240541BF },
         { .reg = 0x00009888, .val = 0x26050001 },
         { .reg = 0x00009888, .val = 0x2205AA50 },
         { .reg = 0x00009888, .val = 0x1C080320 },
         { .reg = 0x00009888, .val = 0x14088000 },
         { .reg = 0x00009888, .val = 0x1A081000 },
         { .reg = 0x00009888, .val = 0x1C064000 },
         { .reg = 0x00009888, .val = 0x24060640 },
         { .reg = 0x00009888, .val = 0x10098000 },
         { .reg = 0x00009888, .val = 0x1C09000E },
         { .reg = 0x00009888, .val = 0x1C078000 },
         { .reg = 0x00009888, .val = 0x160A1000 },
         { .reg = 0x00009888, .val = 0x180A0800 },
         { .reg = 0x00009888, .val = 0x1E0D4001 },
         { .reg = 0x00009888, .val = 0x040E4000 },
         { .reg = 0x00009888, .val = 0x0A0E8000 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x120B8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101415 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D140033 },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B114000 },
         { .reg = 0x00009888, .val = 0x5F11AAAA },
         { .reg = 0x00009888, .val = 0x6111282A },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x4D100313 },
         { .reg = 0x00009888, .val = 0x4F100A02 },
         { .reg = 0x00009888, .val = 0x51101318 },
         { .reg = 0x00009888, .val = 0x53100001 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55101110 },
         { .reg = 0x00009888, .val = 0x57100001 },
         { .reg = 0x00009888, .val = 0x49101111 },
         { .reg = 0x00009888, .val = 0x4B101313 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000DC00, .val = 0x00000002 },
         { .reg = 0x0000DC04, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000DC08, .val = 0x00000002 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000DC10, .val = 0x00000002 },
         { .reg = 0x0000DC14, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00000002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000DC20, .val = 0x00000002 },
         { .reg = 0x0000DC24, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000DC28, .val = 0x00000002 },
         { .reg = 0x0000DC2C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00007800 },
         { .reg = 0x0000D974, .val = 0x0000F0FF },
         { .reg = 0x0000DC30, .val = 0x00007800 },
         { .reg = 0x0000DC34, .val = 0x0000F0FF },
         { .reg = 0x0000D978, .val = 0x00078000 },
         { .reg = 0x0000D97C, .val = 0x00000FFF },
         { .reg = 0x0000DC38, .val = 0x00078000 },
         { .reg = 0x0000DC3C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__tdl_1__avg_gpu_core_frequency__max,dg1__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__tdl_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 452, 92, percentage_max_float,dg1__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 453, 96, percentage_max_float,dg1__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 510, 100, percentage_max_float,dg1__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 511, 104, percentage_max_float,dg1__tdl_1__non_ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 512, 108, percentage_max_float,dg1__tdl_1__non_ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 513, 112, percentage_max_float,dg1__tdl_1__non_ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 456, 116, percentage_max_float,dg1__tdl_1__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 457, 120, percentage_max_float,dg1__tdl_1__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 458, 124, percentage_max_float,dg1__tdl_1__thread_header00_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 459, 128, percentage_max_float,dg1__tdl_1__thread_header00_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 460, 132, percentage_max_float,dg1__tdl_1__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 461, 136, percentage_max_float,dg1__tdl_1__thread_header01_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 462, 140, percentage_max_float,dg1__tdl_1__thread_header01_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 463, 144, percentage_max_float,dg1__tdl_1__thread_header01_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 464, 148, percentage_max_float,dg1__tdl_1__thread_header00_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 465, 152, percentage_max_float,dg1__tdl_1__thread_header01_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 24);

   query->name = "TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "5e7aa748-e1a6-4282-b3ae-48dbfb06dcf8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x24110340 },
         { .reg = 0x00009888, .val = 0x24310340 },
         { .reg = 0x00009888, .val = 0x24510340 },
         { .reg = 0x00009888, .val = 0x24710340 },
         { .reg = 0x00009888, .val = 0x24910340 },
         { .reg = 0x00009888, .val = 0x24B10340 },
         { .reg = 0x00009888, .val = 0x26B1001C },
         { .reg = 0x00009888, .val = 0x021100F3 },
         { .reg = 0x00009888, .val = 0x041100F2 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x00110000 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x1C3100F3 },
         { .reg = 0x00009888, .val = 0x1E3100F2 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x0E310000 },
         { .reg = 0x00009888, .val = 0x1C328000 },
         { .reg = 0x00009888, .val = 0x1E328000 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x185100F3 },
         { .reg = 0x00009888, .val = 0x1A5100F2 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x0C510000 },
         { .reg = 0x00009888, .val = 0x18528000 },
         { .reg = 0x00009888, .val = 0x1A528000 },
         { .reg = 0x00009888, .val = 0x1C53C000 },
         { .reg = 0x00009888, .val = 0x147100F3 },
         { .reg = 0x00009888, .val = 0x167100F2 },
         { .reg = 0x00009888, .val = 0x10710000 },
         { .reg = 0x00009888, .val = 0x0A710000 },
         { .reg = 0x00009888, .val = 0x14728000 },
         { .reg = 0x00009888, .val = 0x16728000 },
         { .reg = 0x00009888, .val = 0x1C733000 },
         { .reg = 0x00009888, .val = 0x109100F3 },
         { .reg = 0x00009888, .val = 0x129100F2 },
         { .reg = 0x00009888, .val = 0x08910000 },
         { .reg = 0x00009888, .val = 0x10928000 },
         { .reg = 0x00009888, .val = 0x12928000 },
         { .reg = 0x00009888, .val = 0x1C930C00 },
         { .reg = 0x00009888, .val = 0x00B100F3 },
         { .reg = 0x00009888, .val = 0x0EB100F2 },
         { .reg = 0x00009888, .val = 0x06B10104 },
         { .reg = 0x00009888, .val = 0x08B10105 },
         { .reg = 0x00009888, .val = 0x0AB10106 },
         { .reg = 0x00009888, .val = 0x0CB10107 },
         { .reg = 0x00009888, .val = 0x10B10000 },
         { .reg = 0x00009888, .val = 0x02B10000 },
         { .reg = 0x00009888, .val = 0x04B10000 },
         { .reg = 0x00009888, .val = 0x00B28000 },
         { .reg = 0x00009888, .val = 0x0EB28000 },
         { .reg = 0x00009888, .val = 0x06B28000 },
         { .reg = 0x00009888, .val = 0x08B28000 },
         { .reg = 0x00009888, .val = 0x0AB28000 },
         { .reg = 0x00009888, .val = 0x0CB28000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1CB30300 },
         { .reg = 0x00009888, .val = 0x16B38000 },
         { .reg = 0x00009888, .val = 0x18B38000 },
         { .reg = 0x00009888, .val = 0x1AB38000 },
         { .reg = 0x00009888, .val = 0x00004000 },
         { .reg = 0x00009888, .val = 0x0E004000 },
         { .reg = 0x00009888, .val = 0x10004000 },
         { .reg = 0x00009888, .val = 0x12004000 },
         { .reg = 0x00009888, .val = 0x34005540 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x06004000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2A015500 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x06014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x1C05C000 },
         { .reg = 0x00009888, .val = 0x2405BFFF },
         { .reg = 0x00009888, .val = 0x26050002 },
         { .reg = 0x00009888, .val = 0x2205FF50 },
         { .reg = 0x00009888, .val = 0x14088000 },
         { .reg = 0x00009888, .val = 0x1A081000 },
         { .reg = 0x00009888, .val = 0x1C064000 },
         { .reg = 0x00009888, .val = 0x2406A555 },
         { .reg = 0x00009888, .val = 0x26060005 },
         { .reg = 0x00009888, .val = 0x22064000 },
         { .reg = 0x00009888, .val = 0x10098000 },
         { .reg = 0x00009888, .val = 0x1C0900FF },
         { .reg = 0x00009888, .val = 0x1A09E000 },
         { .reg = 0x00009888, .val = 0x1C078000 },
         { .reg = 0x00009888, .val = 0x24070002 },
         { .reg = 0x00009888, .val = 0x2207AA00 },
         { .reg = 0x00009888, .val = 0x160A1000 },
         { .reg = 0x00009888, .val = 0x180AA554 },
         { .reg = 0x00009888, .val = 0x1E0D5541 },
         { .reg = 0x00009888, .val = 0x200D0005 },
         { .reg = 0x00009888, .val = 0x040E4000 },
         { .reg = 0x00009888, .val = 0x0A0EC000 },
         { .reg = 0x00009888, .val = 0x0C0EC000 },
         { .reg = 0x00009888, .val = 0x060E8000 },
         { .reg = 0x00009888, .val = 0x080EC000 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x0E0B4000 },
         { .reg = 0x00009888, .val = 0x100B4000 },
         { .reg = 0x00009888, .val = 0x120B4000 },
         { .reg = 0x00009888, .val = 0x180B8000 },
         { .reg = 0x00009888, .val = 0x1A0B8000 },
         { .reg = 0x00009888, .val = 0x060B4000 },
         { .reg = 0x00009888, .val = 0x080B4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009888, .val = 0x0C0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x11148000 },
         { .reg = 0x00009888, .val = 0x1B14FC00 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x4B114000 },
         { .reg = 0x00009888, .val = 0x5F11AAAA },
         { .reg = 0x00009888, .val = 0x61112AAA },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100200 },
         { .reg = 0x00009888, .val = 0x51100A02 },
         { .reg = 0x00009888, .val = 0x5310080A },
         { .reg = 0x00009888, .val = 0x55101318 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100003 },
         { .reg = 0x00009888, .val = 0x49100111 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000000 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000000 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000000 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000000 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000DC20, .val = 0x00000000 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000DC28, .val = 0x00000000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00078000 },
         { .reg = 0x0000D974, .val = 0x00000FFF },
         { .reg = 0x0000DC30, .val = 0x00078000 },
         { .reg = 0x0000DC34, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__tdl_2__avg_gpu_core_frequency__max,dg1__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__tdl_2__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 454, 92, percentage_max_float,dg1__tdl_2__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 455, 96, percentage_max_float,dg1__tdl_2__ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 514, 100, percentage_max_float,dg1__tdl_2__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 515, 104, percentage_max_float,dg1__tdl_2__ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 516, 108, percentage_max_float,dg1__tdl_2__ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 517, 112, percentage_max_float,dg1__tdl_2__ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 518, 116, percentage_max_float,dg1__tdl_2__thread_header05_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 519, 120, percentage_max_float,dg1__tdl_2__thread_header05_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 520, 124, percentage_max_float,dg1__tdl_2__thread_header05_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 521, 128, percentage_max_float,dg1__tdl_2__thread_header05_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 522, 132, percentage_max_float,dg1__tdl_2__thread_header05_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_tdl_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 28);

   query->name = "TDL_3";
   query->symbol_name = "TDL_3";
   query->guid = "e12f8fc0-2eb9-4bf6-bf44-a13ceb42c9f7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2651001C },
         { .reg = 0x00009888, .val = 0x2671001C },
         { .reg = 0x00009888, .val = 0x2691001C },
         { .reg = 0x00009888, .val = 0x06510107 },
         { .reg = 0x00009888, .val = 0x08510106 },
         { .reg = 0x00009888, .val = 0x0A510105 },
         { .reg = 0x00009888, .val = 0x0C510104 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x02510000 },
         { .reg = 0x00009888, .val = 0x04510000 },
         { .reg = 0x00009888, .val = 0x06528000 },
         { .reg = 0x00009888, .val = 0x08528000 },
         { .reg = 0x00009888, .val = 0x0A528000 },
         { .reg = 0x00009888, .val = 0x0C528000 },
         { .reg = 0x00009888, .val = 0x16538000 },
         { .reg = 0x00009888, .val = 0x18538000 },
         { .reg = 0x00009888, .val = 0x1A538000 },
         { .reg = 0x00009888, .val = 0x1C530100 },
         { .reg = 0x00009888, .val = 0x1C710107 },
         { .reg = 0x00009888, .val = 0x1E710106 },
         { .reg = 0x00009888, .val = 0x02710105 },
         { .reg = 0x00009888, .val = 0x04710104 },
         { .reg = 0x00009888, .val = 0x10710000 },
         { .reg = 0x00009888, .val = 0x0E710000 },
         { .reg = 0x00009888, .val = 0x00710000 },
         { .reg = 0x00009888, .val = 0x1C728000 },
         { .reg = 0x00009888, .val = 0x1E728000 },
         { .reg = 0x00009888, .val = 0x02728000 },
         { .reg = 0x00009888, .val = 0x04728000 },
         { .reg = 0x00009888, .val = 0x1E730003 },
         { .reg = 0x00009888, .val = 0x12738000 },
         { .reg = 0x00009888, .val = 0x14738000 },
         { .reg = 0x00009888, .val = 0x14910107 },
         { .reg = 0x00009888, .val = 0x16910106 },
         { .reg = 0x00009888, .val = 0x18910105 },
         { .reg = 0x00009888, .val = 0x1A910104 },
         { .reg = 0x00009888, .val = 0x10910000 },
         { .reg = 0x00009888, .val = 0x0A910000 },
         { .reg = 0x00009888, .val = 0x0C910000 },
         { .reg = 0x00009888, .val = 0x14928000 },
         { .reg = 0x00009888, .val = 0x16928000 },
         { .reg = 0x00009888, .val = 0x18928000 },
         { .reg = 0x00009888, .val = 0x1A928000 },
         { .reg = 0x00009888, .val = 0x1C93F000 },
         { .reg = 0x00009888, .val = 0x34005540 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x02004000 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x06004000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x0C004000 },
         { .reg = 0x00009888, .val = 0x2A015500 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x06014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x2405FFC0 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x2205FFF0 },
         { .reg = 0x00009888, .val = 0x24065015 },
         { .reg = 0x00009888, .val = 0x260600A5 },
         { .reg = 0x00009888, .val = 0x22066800 },
         { .reg = 0x00009888, .val = 0x1C0903F1 },
         { .reg = 0x00009888, .val = 0x14098000 },
         { .reg = 0x00009888, .val = 0x1A09F000 },
         { .reg = 0x00009888, .val = 0x1A0A00AA },
         { .reg = 0x00009888, .val = 0x200D0550 },
         { .reg = 0x00009888, .val = 0x0E0EC000 },
         { .reg = 0x00009888, .val = 0x100EC000 },
         { .reg = 0x00009888, .val = 0x140B4000 },
         { .reg = 0x00009888, .val = 0x160B4000 },
         { .reg = 0x00009888, .val = 0x180B4000 },
         { .reg = 0x00009888, .val = 0x1A0B4000 },
         { .reg = 0x00009888, .val = 0x060B8000 },
         { .reg = 0x00009888, .val = 0x080B8000 },
         { .reg = 0x00009888, .val = 0x0A0B8000 },
         { .reg = 0x00009888, .val = 0x0C0B8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5D101554 },
         { .reg = 0x00009888, .val = 0x5B100555 },
         { .reg = 0x00009888, .val = 0x1D14003F },
         { .reg = 0x00009888, .val = 0x13148000 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x17148000 },
         { .reg = 0x00009888, .val = 0x1B141C00 },
         { .reg = 0x00009888, .val = 0x61112AA8 },
         { .reg = 0x00009888, .val = 0x5F110AAA },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x53100000 },
         { .reg = 0x00009888, .val = 0x55100800 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100008 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100808 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009888, .val = 0x4D100606 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00070000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000DC00, .val = 0x00078000 },
         { .reg = 0x0000DC04, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000DC08, .val = 0x00007800 },
         { .reg = 0x0000DC0C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000DC10, .val = 0x00000780 },
         { .reg = 0x0000DC14, .val = 0x0000FF0F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__tdl_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__tdl_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__tdl_3__avg_gpu_core_frequency__max,dg1__tdl_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__tdl_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__tdl_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__tdl_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__tdl_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__tdl_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__tdl_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__tdl_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,dg1__tdl_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,dg1__tdl_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,dg1__tdl_3__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 523, 92, percentage_max_float,dg1__tdl_3__thread_header02_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 524, 96, percentage_max_float,dg1__tdl_3__thread_header03_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 525, 100, percentage_max_float,dg1__tdl_3__thread_header04_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 526, 104, percentage_max_float,dg1__tdl_3__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 527, 108, percentage_max_float,dg1__tdl_3__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 528, 112, percentage_max_float,dg1__tdl_3__thread_header02_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 529, 116, percentage_max_float,dg1__tdl_3__thread_header02_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 530, 120, percentage_max_float,dg1__tdl_3__thread_header03_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 531, 124, percentage_max_float,dg1__tdl_3__thread_header03_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 532, 128, percentage_max_float,dg1__tdl_3__thread_header03_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 533, 132, percentage_max_float,dg1__tdl_3__thread_header03_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 534, 136, percentage_max_float,dg1__tdl_3__thread_header04_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 535, 140, percentage_max_float,dg1__tdl_3__thread_header04_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 536, 144, percentage_max_float,dg1__tdl_3__thread_header04_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 537, 148, percentage_max_float,dg1__tdl_3__thread_header04_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 22);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "81be185c-7ac7-4a17-85fc-4144ccba4a46";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0F2400 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x22100009 },
         { .reg = 0x00009888, .val = 0x04004000 },
         { .reg = 0x00009888, .val = 0x08004000 },
         { .reg = 0x00009888, .val = 0x0A004000 },
         { .reg = 0x00009888, .val = 0x04014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x22053CC0 },
         { .reg = 0x00009888, .val = 0x22061000 },
         { .reg = 0x00009888, .val = 0x24060005 },
         { .reg = 0x00009888, .val = 0x1A09D000 },
         { .reg = 0x00009888, .val = 0x020C4000 },
         { .reg = 0x00009888, .val = 0x040CC000 },
         { .reg = 0x00009888, .val = 0x1E0D0A20 },
         { .reg = 0x00009888, .val = 0x040F0043 },
         { .reg = 0x00009888, .val = 0x0A0F00B3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x080F8000 },
         { .reg = 0x00009888, .val = 0x081000A3 },
         { .reg = 0x00009888, .val = 0x00100000 },
         { .reg = 0x00009888, .val = 0x040B4000 },
         { .reg = 0x00009888, .val = 0x080B4000 },
         { .reg = 0x00009888, .val = 0x0A0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x15102400 },
         { .reg = 0x00009888, .val = 0x230B0120 },
         { .reg = 0x00009888, .val = 0x15182400 },
         { .reg = 0x00009888, .val = 0x232B0120 },
         { .reg = 0x00009888, .val = 0x17100023 },
         { .reg = 0x00009888, .val = 0x11100000 },
         { .reg = 0x00009888, .val = 0x5D101000 },
         { .reg = 0x00009888, .val = 0x5B100545 },
         { .reg = 0x00009888, .val = 0x15148000 },
         { .reg = 0x00009888, .val = 0x1B140C00 },
         { .reg = 0x00009888, .val = 0x61113000 },
         { .reg = 0x00009888, .val = 0x5F110E89 },
         { .reg = 0x00009888, .val = 0x05128000 },
         { .reg = 0x00009888, .val = 0x13138000 },
         { .reg = 0x00009888, .val = 0x1B0D0040 },
         { .reg = 0x00009888, .val = 0x1F0B00D3 },
         { .reg = 0x00009888, .val = 0x210B0000 },
         { .reg = 0x00009888, .val = 0x1B170002 },
         { .reg = 0x00009888, .val = 0x0D174000 },
         { .reg = 0x00009888, .val = 0x071800A3 },
         { .reg = 0x00009888, .val = 0x11180000 },
         { .reg = 0x00009888, .val = 0x032D4000 },
         { .reg = 0x00009888, .val = 0x032B00D3 },
         { .reg = 0x00009888, .val = 0x212B0000 },
         { .reg = 0x00009888, .val = 0x55101000 },
         { .reg = 0x00009888, .val = 0x57100007 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49103203 },
         { .reg = 0x00009888, .val = 0x4B100005 },
         { .reg = 0x00009888, .val = 0x4D100912 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00024002 },
         { .reg = 0x0000D944, .val = 0x0000B7FF },
         { .reg = 0x0000DC00, .val = 0x00024002 },
         { .reg = 0x0000DC04, .val = 0x0000B7FF },
         { .reg = 0x0000D948, .val = 0x0007F000 },
         { .reg = 0x0000D94C, .val = 0x000001FF },
         { .reg = 0x0000DC08, .val = 0x0007F000 },
         { .reg = 0x0000DC0C, .val = 0x000001FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__gpu_busyness__avg_gpu_core_frequency__max,dg1__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,dg1__gpu_busyness__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,dg1__gpu_busyness__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,dg1__gpu_busyness__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,dg1__gpu_busyness__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,dg1__gpu_busyness__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,dg1__gpu_busyness__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,dg1__gpu_busyness__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,dg1__gpu_busyness__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,dg1__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 88, percentage_max_float,dg1__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 92, percentage_max_float,dg1__gpu_busyness__compute_busy__read);

      intel_perf_query_add_counter_float(query, 414, 96, percentage_max_float,dg1__gpu_busyness__posh_engine_busy__read);

      intel_perf_query_add_counter_float(query, 313, 100, percentage_max_float,dg1__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 312, 104, percentage_max_float,dg1__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 310, 108, percentage_max_float,dg1__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 112, percentage_max_float,dg1__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 467, 116, percentage_max_float,dg1__gpu_busyness__render_and_compute_busy__read);

      intel_perf_query_add_counter_float(query, 468, 120, percentage_max_float,dg1__gpu_busyness__any_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_eu_activity1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity1";
   query->symbol_name = "EuActivity1";
   query->guid = "5354b8d9-12fd-44eb-8f7d-0a4dffae4409";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0F2400 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x26060050 },
         { .reg = 0x00009888, .val = 0x1C090300 },
         { .reg = 0x00009888, .val = 0x0E0CC000 },
         { .reg = 0x00009888, .val = 0x200DA000 },
         { .reg = 0x00009888, .val = 0x1C0F0043 },
         { .reg = 0x00009888, .val = 0x1E0F00B3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61112800 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101A1A },
         { .reg = 0x00009888, .val = 0x4B101A1A },
         { .reg = 0x00009888, .val = 0x4D100A1A },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00810710 },
         { .reg = 0x0000E558, .val = 0x00A10910 },
         { .reg = 0x0000E658, .val = 0x00850750 },
         { .reg = 0x0000E758, .val = 0x00A50950 },
         { .reg = 0x0000E45C, .val = 0x00802702 },
         { .reg = 0x0000E55C, .val = 0x00A02902 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__eu_activity1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__eu_activity1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__eu_activity1__avg_gpu_core_frequency__max,dg1__eu_activity1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__eu_activity1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__eu_activity1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__eu_activity1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__eu_activity1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__eu_activity1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__eu_activity1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__eu_activity1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,dg1__eu_activity1__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,dg1__eu_activity1__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,dg1__eu_activity1__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, dg1__eu_activity1__gti_read_throughput__max,dg1__eu_activity1__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, dg1__eu_activity1__gti_write_throughput__max,dg1__eu_activity1__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 469, 112, percentage_max_float,dg1__eu_activity1__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 470, 116, percentage_max_float,dg1__eu_activity1__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 153, 120, percentage_max_float,dg1__eu_activity1__eu_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_eu_activity2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity2";
   query->symbol_name = "EuActivity2";
   query->guid = "3225b6c6-805a-4e93-aaa5-5f09d87b31f9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0F2400 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x26060050 },
         { .reg = 0x00009888, .val = 0x1C090300 },
         { .reg = 0x00009888, .val = 0x0E0CC000 },
         { .reg = 0x00009888, .val = 0x200DA000 },
         { .reg = 0x00009888, .val = 0x1C0F0043 },
         { .reg = 0x00009888, .val = 0x1E0F00B3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61112800 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101A1A },
         { .reg = 0x00009888, .val = 0x4B101A1A },
         { .reg = 0x00009888, .val = 0x4D100A1A },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00862762 },
         { .reg = 0x0000E558, .val = 0x00A62962 },
         { .reg = 0x0000E658, .val = 0x00860760 },
         { .reg = 0x0000E758, .val = 0x00A60960 },
         { .reg = 0x0000E45C, .val = 0x00861761 },
         { .reg = 0x0000E55C, .val = 0x00A61961 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__eu_activity2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__eu_activity2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__eu_activity2__avg_gpu_core_frequency__max,dg1__eu_activity2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__eu_activity2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__eu_activity2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__eu_activity2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__eu_activity2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__eu_activity2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__eu_activity2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__eu_activity2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,dg1__eu_activity2__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,dg1__eu_activity2__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,dg1__eu_activity2__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, dg1__eu_activity2__gti_read_throughput__max,dg1__eu_activity2__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, dg1__eu_activity2__gti_write_throughput__max,dg1__eu_activity2__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 471, 112, percentage_max_float,dg1__eu_activity2__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 472, 116, percentage_max_float,dg1__eu_activity2__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 473, 120, percentage_max_float,dg1__eu_activity2__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_eu_activity3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity3";
   query->symbol_name = "EuActivity3";
   query->guid = "c423d483-13da-4bae-9b61-c13ec19ee450";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0F2400 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x26060050 },
         { .reg = 0x00009888, .val = 0x1C090300 },
         { .reg = 0x00009888, .val = 0x0E0CC000 },
         { .reg = 0x00009888, .val = 0x200DA000 },
         { .reg = 0x00009888, .val = 0x1C0F0043 },
         { .reg = 0x00009888, .val = 0x1E0F00B3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61112800 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101A1A },
         { .reg = 0x00009888, .val = 0x4B101A1A },
         { .reg = 0x00009888, .val = 0x4D100A1A },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00811711 },
         { .reg = 0x0000E558, .val = 0x00A11911 },
         { .reg = 0x0000E658, .val = 0x00851751 },
         { .reg = 0x0000E758, .val = 0x00A51951 },
         { .reg = 0x0000E45C, .val = 0x00852752 },
         { .reg = 0x0000E55C, .val = 0x00A52952 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__eu_activity3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__eu_activity3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__eu_activity3__avg_gpu_core_frequency__max,dg1__eu_activity3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__eu_activity3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__eu_activity3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__eu_activity3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__eu_activity3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__eu_activity3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__eu_activity3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__eu_activity3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,dg1__eu_activity3__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,dg1__eu_activity3__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,dg1__eu_activity3__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, dg1__eu_activity3__gti_read_throughput__max,dg1__eu_activity3__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, dg1__eu_activity3__gti_write_throughput__max,dg1__eu_activity3__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 474, 112, percentage_max_float,dg1__eu_activity3__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 475, 116, percentage_max_float,dg1__eu_activity3__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 129, 120, percentage_max_float,dg1__eu_activity3__ps_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_eu_activity4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity4";
   query->symbol_name = "EuActivity4";
   query->guid = "c7388ce3-9e3f-4804-a215-771791c4ea3c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0F2400 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x26060050 },
         { .reg = 0x00009888, .val = 0x1C090300 },
         { .reg = 0x00009888, .val = 0x0E0CC000 },
         { .reg = 0x00009888, .val = 0x200DA000 },
         { .reg = 0x00009888, .val = 0x1C0F0043 },
         { .reg = 0x00009888, .val = 0x1E0F00B3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61112800 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101A1A },
         { .reg = 0x00009888, .val = 0x4B101A1A },
         { .reg = 0x00009888, .val = 0x4D100A1A },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00820720 },
         { .reg = 0x0000E558, .val = 0x00A20920 },
         { .reg = 0x0000E658, .val = 0x00830730 },
         { .reg = 0x0000E758, .val = 0x00A30930 },
         { .reg = 0x0000E45C, .val = 0x00812712 },
         { .reg = 0x0000E55C, .val = 0x00A12912 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__eu_activity4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__eu_activity4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__eu_activity4__avg_gpu_core_frequency__max,dg1__eu_activity4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__eu_activity4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__eu_activity4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__eu_activity4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__eu_activity4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__eu_activity4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__eu_activity4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__eu_activity4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,dg1__eu_activity4__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,dg1__eu_activity4__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,dg1__eu_activity4__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, dg1__eu_activity4__gti_read_throughput__max,dg1__eu_activity4__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, dg1__eu_activity4__gti_write_throughput__max,dg1__eu_activity4__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 476, 112, percentage_max_float,dg1__eu_activity4__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 477, 116, percentage_max_float,dg1__eu_activity4__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 126, 120, percentage_max_float,dg1__eu_activity4__vs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_eu_activity5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity5";
   query->symbol_name = "EuActivity5";
   query->guid = "7ebc4a0a-5dc3-4de3-a8f8-2a6d1a95427f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0F2400 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x26060050 },
         { .reg = 0x00009888, .val = 0x1C090300 },
         { .reg = 0x00009888, .val = 0x0E0CC000 },
         { .reg = 0x00009888, .val = 0x200DA000 },
         { .reg = 0x00009888, .val = 0x1C0F0043 },
         { .reg = 0x00009888, .val = 0x1E0F00B3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61112800 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101A1A },
         { .reg = 0x00009888, .val = 0x4B101A1A },
         { .reg = 0x00009888, .val = 0x4D100A1A },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00821721 },
         { .reg = 0x0000E558, .val = 0x00A21921 },
         { .reg = 0x0000E658, .val = 0x00831731 },
         { .reg = 0x0000E758, .val = 0x00A31931 },
         { .reg = 0x0000E45C, .val = 0x00822722 },
         { .reg = 0x0000E55C, .val = 0x00A22922 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__eu_activity5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__eu_activity5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__eu_activity5__avg_gpu_core_frequency__max,dg1__eu_activity5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__eu_activity5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__eu_activity5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__eu_activity5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__eu_activity5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__eu_activity5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__eu_activity5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__eu_activity5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,dg1__eu_activity5__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,dg1__eu_activity5__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,dg1__eu_activity5__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, dg1__eu_activity5__gti_read_throughput__max,dg1__eu_activity5__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, dg1__eu_activity5__gti_write_throughput__max,dg1__eu_activity5__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 478, 112, percentage_max_float,dg1__eu_activity5__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 479, 116, percentage_max_float,dg1__eu_activity5__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 480, 120, percentage_max_float,dg1__eu_activity5__hs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_eu_activity6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity6";
   query->symbol_name = "EuActivity6";
   query->guid = "811a34c7-87f3-4d4d-b366-d4b5f5dc5be1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0F2400 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x26060050 },
         { .reg = 0x00009888, .val = 0x1C090300 },
         { .reg = 0x00009888, .val = 0x0E0CC000 },
         { .reg = 0x00009888, .val = 0x200DA000 },
         { .reg = 0x00009888, .val = 0x1C0F0043 },
         { .reg = 0x00009888, .val = 0x1E0F00B3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61112800 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101A1A },
         { .reg = 0x00009888, .val = 0x4B101A1A },
         { .reg = 0x00009888, .val = 0x4D100A1A },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00840740 },
         { .reg = 0x0000E558, .val = 0x00A40940 },
         { .reg = 0x0000E658, .val = 0x00841741 },
         { .reg = 0x0000E758, .val = 0x00A41941 },
         { .reg = 0x0000E45C, .val = 0x00842742 },
         { .reg = 0x0000E55C, .val = 0x00A42942 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__eu_activity6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__eu_activity6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__eu_activity6__avg_gpu_core_frequency__max,dg1__eu_activity6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__eu_activity6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__eu_activity6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__eu_activity6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__eu_activity6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__eu_activity6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__eu_activity6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__eu_activity6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,dg1__eu_activity6__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,dg1__eu_activity6__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,dg1__eu_activity6__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, dg1__eu_activity6__gti_read_throughput__max,dg1__eu_activity6__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, dg1__eu_activity6__gti_write_throughput__max,dg1__eu_activity6__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 481, 112, percentage_max_float,dg1__eu_activity6__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 482, 116, percentage_max_float,dg1__eu_activity6__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 483, 120, percentage_max_float,dg1__eu_activity6__gs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_eu_activity7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "EuActivity7";
   query->symbol_name = "EuActivity7";
   query->guid = "6ec13866-51c1-46c3-818b-c63cf38efcd5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0F2400 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x26060050 },
         { .reg = 0x00009888, .val = 0x1C090300 },
         { .reg = 0x00009888, .val = 0x0E0CC000 },
         { .reg = 0x00009888, .val = 0x200DA000 },
         { .reg = 0x00009888, .val = 0x1C0F0043 },
         { .reg = 0x00009888, .val = 0x1E0F00B3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61112800 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101A1A },
         { .reg = 0x00009888, .val = 0x4B101A1A },
         { .reg = 0x00009888, .val = 0x4D100A1A },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00803703 },
         { .reg = 0x0000E558, .val = 0x00A03903 },
         { .reg = 0x0000E658, .val = 0x00800700 },
         { .reg = 0x0000E758, .val = 0x00A00900 },
         { .reg = 0x0000E45C, .val = 0x00801701 },
         { .reg = 0x0000E55C, .val = 0x00A01901 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__eu_activity7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__eu_activity7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__eu_activity7__avg_gpu_core_frequency__max,dg1__eu_activity7__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__eu_activity7__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__eu_activity7__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__eu_activity7__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__eu_activity7__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__eu_activity7__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__eu_activity7__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__eu_activity7__cs_threads__read);

      intel_perf_query_add_counter_float(query, 484, 80, percentage_max_float,dg1__eu_activity7__fpu_active__read);

      intel_perf_query_add_counter_float(query, 485, 84, percentage_max_float,dg1__eu_activity7__em_active__read);

      intel_perf_query_add_counter_float(query, 486, 88, percentage_max_float,dg1__eu_activity7__eu_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 152, 92, dg1__eu_activity7__eu_avg_ipc_rate__max,dg1__eu_activity7__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 309, 96, percentage_max_float,dg1__eu_activity7__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 100, percentage_max_float,dg1__eu_activity7__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 104, percentage_max_float,dg1__eu_activity7__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 112, dg1__eu_activity7__gti_read_throughput__max,dg1__eu_activity7__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 120, dg1__eu_activity7__gti_write_throughput__max,dg1__eu_activity7__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_eu_activity8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 16);

   query->name = "EuActivity8";
   query->symbol_name = "EuActivity8";
   query->guid = "4bc9e67a-0ebd-4d65-86cd-2eb961ccac59";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0F2400 },
         { .reg = 0x00009888, .val = 0x220F0009 },
         { .reg = 0x00009888, .val = 0x34004000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x2C010005 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x26060050 },
         { .reg = 0x00009888, .val = 0x1C090300 },
         { .reg = 0x00009888, .val = 0x0E0CC000 },
         { .reg = 0x00009888, .val = 0x200DA000 },
         { .reg = 0x00009888, .val = 0x1C0F0043 },
         { .reg = 0x00009888, .val = 0x1E0F00B3 },
         { .reg = 0x00009888, .val = 0x200F0000 },
         { .reg = 0x00009888, .val = 0x1C0B4000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1D140030 },
         { .reg = 0x00009888, .val = 0x61112800 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101A1A },
         { .reg = 0x00009888, .val = 0x4B101A1A },
         { .reg = 0x00009888, .val = 0x4D100A1A },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00832732 },
         { .reg = 0x0000E558, .val = 0x00A32932 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__eu_activity8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__eu_activity8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__eu_activity8__avg_gpu_core_frequency__max,dg1__eu_activity8__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,dg1__eu_activity8__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,dg1__eu_activity8__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,dg1__eu_activity8__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,dg1__eu_activity8__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,dg1__eu_activity8__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,dg1__eu_activity8__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,dg1__eu_activity8__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,dg1__eu_activity8__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,dg1__eu_activity8__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,dg1__eu_activity8__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, dg1__eu_activity8__gti_read_throughput__max,dg1__eu_activity8__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, dg1__eu_activity8__gti_write_throughput__max,dg1__eu_activity8__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 487, 112, percentage_max_float,dg1__eu_activity8__ds_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
dg1_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "23f51139-6973-4b45-a211-778834ce2c9a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04100000 },
         { .reg = 0x00009888, .val = 0x36000001 },
         { .reg = 0x00009888, .val = 0x2C010004 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x26060040 },
         { .reg = 0x00009888, .val = 0x1C090200 },
         { .reg = 0x00009888, .val = 0x0E0C8000 },
         { .reg = 0x00009888, .val = 0x200D8000 },
         { .reg = 0x00009888, .val = 0x1E0F8000 },
         { .reg = 0x00009888, .val = 0x1E100017 },
         { .reg = 0x00009888, .val = 0x00100000 },
         { .reg = 0x00009888, .val = 0x1E0B4000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x49110000 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x1D140020 },
         { .reg = 0x00009888, .val = 0x1D1103A3 },
         { .reg = 0x00009888, .val = 0x01110000 },
         { .reg = 0x00009888, .val = 0x61112000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100230 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000DC00, .val = 0x00000004 },
         { .reg = 0x0000DC04, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000DC08, .val = 0x00000003 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000DC10, .val = 0x00000007 },
         { .reg = 0x0000DC14, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00100002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000DC20, .val = 0x00100002 },
         { .reg = 0x0000DC24, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000DC28, .val = 0x00100082 },
         { .reg = 0x0000DC2C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000DC30, .val = 0x001000C2 },
         { .reg = 0x0000DC34, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
         { .reg = 0x0000DC38, .val = 0x00100001 },
         { .reg = 0x0000DC3C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,dg1__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,dg1__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, dg1__test_oa__avg_gpu_core_frequency__max,dg1__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,dg1__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,dg1__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,dg1__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,dg1__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 415, 56, NULL,dg1__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 416, 64, NULL,dg1__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 417, 72, NULL,dg1__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 418, 80, NULL,dg1__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 488, 88, NULL,dg1__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 489, 96, NULL,dg1__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_dg1(struct intel_perf_config *perf)
{
   dg1_register_render_basic_counter_query(perf);
   dg1_register_compute_basic_counter_query(perf);
   dg1_register_render_pipe_profile_counter_query(perf);
   dg1_register_hdc_and_sf_counter_query(perf);
   dg1_register_rasterizer_and_pixel_backend_counter_query(perf);
   dg1_register_l3_1_counter_query(perf);
   dg1_register_l3_2_counter_query(perf);
   dg1_register_l3_3_counter_query(perf);
   dg1_register_l3_4_counter_query(perf);
   dg1_register_l3_5_counter_query(perf);
   dg1_register_l3_6_counter_query(perf);
   dg1_register_sampler_1_counter_query(perf);
   dg1_register_sampler_2_counter_query(perf);
   dg1_register_tdl_1_counter_query(perf);
   dg1_register_tdl_2_counter_query(perf);
   dg1_register_tdl_3_counter_query(perf);
   dg1_register_gpu_busyness_counter_query(perf);
   dg1_register_eu_activity1_counter_query(perf);
   dg1_register_eu_activity2_counter_query(perf);
   dg1_register_eu_activity3_counter_query(perf);
   dg1_register_eu_activity4_counter_query(perf);
   dg1_register_eu_activity5_counter_query(perf);
   dg1_register_eu_activity6_counter_query(perf);
   dg1_register_eu_activity7_counter_query(perf);
   dg1_register_eu_activity8_counter_query(perf);
   dg1_register_test_oa_counter_query(perf);
}


static void
adl_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 34);

   query->name = "Render Metrics Basic set";
   query->symbol_name = "RenderBasic";
   query->guid = "4b886bf3-61ff-4381-9994-ac9b91202fc7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14150001 },
         { .reg = 0x00009888, .val = 0x16150020 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0E124000 },
         { .reg = 0x00009888, .val = 0x10124000 },
         { .reg = 0x00009888, .val = 0x12124000 },
         { .reg = 0x00009888, .val = 0x10138000 },
         { .reg = 0x00009888, .val = 0x1C130E00 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x06157000 },
         { .reg = 0x00009888, .val = 0x08157151 },
         { .reg = 0x00009888, .val = 0x10150000 },
         { .reg = 0x00009888, .val = 0x18150000 },
         { .reg = 0x00009888, .val = 0x1C150000 },
         { .reg = 0x00009888, .val = 0x18004000 },
         { .reg = 0x00009888, .val = 0x36000490 },
         { .reg = 0x00009888, .val = 0x1C058000 },
         { .reg = 0x00009888, .val = 0x2405002A },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D47 },
         { .reg = 0x00009888, .val = 0x09151536 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B1050BB },
         { .reg = 0x00009888, .val = 0x5D102C01 },
         { .reg = 0x00009888, .val = 0x17144000 },
         { .reg = 0x00009888, .val = 0x1D1402A0 },
         { .reg = 0x00009888, .val = 0x01124000 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x1F150137 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x0F168000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x1D350137 },
         { .reg = 0x00009888, .val = 0x03350147 },
         { .reg = 0x00009888, .val = 0x07350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x0F364000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55101210 },
         { .reg = 0x00009888, .val = 0x57100002 },
         { .reg = 0x00009888, .val = 0x49101212 },
         { .reg = 0x00009888, .val = 0x4B100212 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__render_basic__avg_gpu_core_frequency__max,adl__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,adl__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,adl__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,adl__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,adl__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,adl__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,adl__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,adl__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 76, percentage_max_float,adl__render_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 80, percentage_max_float,adl__render_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 84, percentage_max_float,adl__render_basic__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 333, 88, percentage_max_float,adl__render_basic__sampler00_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 435, 92, percentage_max_float,adl__render_basic__sampler00_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 133, 96, percentage_max_float,adl__render_basic__samplers_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 149, 100, percentage_max_float,adl__render_basic__sampler_bottleneck__read);
      }

      intel_perf_query_add_counter_uint64(query, 139, 104, NULL,adl__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 112, NULL,adl__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 120, NULL,adl__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 128, NULL,adl__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 136, NULL,adl__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 144, NULL,adl__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 152, NULL,adl__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 160, NULL,adl__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 168, NULL,adl__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 176, adl__render_basic__slm_bytes_read__max,adl__render_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 184, adl__render_basic__slm_bytes_written__max,adl__render_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 192, NULL,adl__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 200, NULL,adl__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 208, adl__render_basic__l3_shader_throughput__max,adl__render_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 216, NULL,adl__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 224, adl__render_basic__gti_read_throughput__max,adl__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 232, adl__render_basic__gti_write_throughput__max,adl__render_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 30);

   query->name = "Compute Metrics Basic";
   query->symbol_name = "ComputeBasic";
   query->guid = "eb6a0ef8-4e8f-41fa-85ba-686835711f6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__compute_basic__avg_gpu_core_frequency__max,adl__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__compute_basic__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__compute_basic__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__compute_basic__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,adl__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,adl__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,adl__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,adl__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,adl__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,adl__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,adl__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,adl__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,adl__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, adl__compute_basic__slm_bytes_read__max,adl__compute_basic__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, adl__compute_basic__slm_bytes_written__max,adl__compute_basic__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,adl__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,adl__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, adl__compute_basic__l3_shader_throughput__max,adl__compute_basic__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,adl__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 216, adl__compute_basic__gti_read_throughput__max,adl__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 224, adl__compute_basic__gti_write_throughput__max,adl__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 43);

   query->name = "Render Metrics set for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "ee81cfab-667d-46c5-a2b7-17283b28c38d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00123E00 },
         { .reg = 0x00009888, .val = 0x060B00B3 },
         { .reg = 0x00009888, .val = 0x140B3C00 },
         { .reg = 0x00009888, .val = 0x1C0B0000 },
         { .reg = 0x00009888, .val = 0x120C8320 },
         { .reg = 0x00009888, .val = 0x040DBE00 },
         { .reg = 0x00009888, .val = 0x000D0000 },
         { .reg = 0x00009888, .val = 0x280D0000 },
         { .reg = 0x00009888, .val = 0x2C0E7C00 },
         { .reg = 0x00009888, .val = 0x10087C00 },
         { .reg = 0x00009888, .val = 0x1E120002 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x1E130002 },
         { .reg = 0x00009888, .val = 0x0E0B0031 },
         { .reg = 0x00009888, .val = 0x180B0092 },
         { .reg = 0x00009888, .val = 0x1A0B00B1 },
         { .reg = 0x00009888, .val = 0x020B0093 },
         { .reg = 0x00009888, .val = 0x040B0033 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x0A0C0022 },
         { .reg = 0x00009888, .val = 0x1E0C0030 },
         { .reg = 0x00009888, .val = 0x1C0C8000 },
         { .reg = 0x00009888, .val = 0x140C8000 },
         { .reg = 0x00009888, .val = 0x160C8000 },
         { .reg = 0x00009888, .val = 0x100DC017 },
         { .reg = 0x00009888, .val = 0x160D0013 },
         { .reg = 0x00009888, .val = 0x1C0D0081 },
         { .reg = 0x00009888, .val = 0x080D0082 },
         { .reg = 0x00009888, .val = 0x0A0D8102 },
         { .reg = 0x00009888, .val = 0x140D0000 },
         { .reg = 0x00009888, .val = 0x0C0D0000 },
         { .reg = 0x00009888, .val = 0x0E0D4000 },
         { .reg = 0x00009888, .val = 0x120D0000 },
         { .reg = 0x00009888, .val = 0x060DC000 },
         { .reg = 0x00009888, .val = 0x0C0EC1C5 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x0E0E8000 },
         { .reg = 0x00009888, .val = 0x100E4000 },
         { .reg = 0x00009888, .val = 0x120EC000 },
         { .reg = 0x00009888, .val = 0x140EC000 },
         { .reg = 0x00009888, .val = 0x160E4000 },
         { .reg = 0x00009888, .val = 0x080E8000 },
         { .reg = 0x00009888, .val = 0x0A0EC000 },
         { .reg = 0x00009888, .val = 0x1C0F5555 },
         { .reg = 0x00009888, .val = 0x1E0F0554 },
         { .reg = 0x00009888, .val = 0x0E104000 },
         { .reg = 0x00009888, .val = 0x10104000 },
         { .reg = 0x00009888, .val = 0x14104000 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x18104000 },
         { .reg = 0x00009888, .val = 0x1A104000 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x02104000 },
         { .reg = 0x00009888, .val = 0x04104000 },
         { .reg = 0x00009888, .val = 0x06104000 },
         { .reg = 0x00009888, .val = 0x08104000 },
         { .reg = 0x00009888, .val = 0x0A104000 },
         { .reg = 0x00009888, .val = 0x0C104000 },
         { .reg = 0x00009888, .val = 0x0E024000 },
         { .reg = 0x00009888, .val = 0x10024000 },
         { .reg = 0x00009888, .val = 0x2C024000 },
         { .reg = 0x00009888, .val = 0x2E020055 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x06024000 },
         { .reg = 0x00009888, .val = 0x08024000 },
         { .reg = 0x00009888, .val = 0x0A024000 },
         { .reg = 0x00009888, .val = 0x0C024000 },
         { .reg = 0x00009888, .val = 0x1A032000 },
         { .reg = 0x00009888, .val = 0x1C032000 },
         { .reg = 0x00009888, .val = 0x2A035500 },
         { .reg = 0x00009888, .val = 0x2C030001 },
         { .reg = 0x00009888, .val = 0x02034000 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08034000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x360036DB },
         { .reg = 0x00009888, .val = 0x380026DB },
         { .reg = 0x00009888, .val = 0x1A006000 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x1E006000 },
         { .reg = 0x00009888, .val = 0x34001B00 },
         { .reg = 0x00009888, .val = 0x26050002 },
         { .reg = 0x00009888, .val = 0x0E0A8000 },
         { .reg = 0x00009888, .val = 0x100A8000 },
         { .reg = 0x00009888, .val = 0x120A4000 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x020A8000 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009888, .val = 0x08081000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x1D14AAAA },
         { .reg = 0x00009888, .val = 0x1F14002A },
         { .reg = 0x00009888, .val = 0x1B14AA00 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x19124000 },
         { .reg = 0x00009888, .val = 0x1B124000 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x4D100604 },
         { .reg = 0x00009888, .val = 0x4F101400 },
         { .reg = 0x00009888, .val = 0x51100203 },
         { .reg = 0x00009888, .val = 0x53100004 },
         { .reg = 0x00009888, .val = 0x55101400 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100001 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100400 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__render_pipe_profile__avg_gpu_core_frequency__max,adl__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__render_pipe_profile__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__render_pipe_profile__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__render_pipe_profile__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__render_pipe_profile__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__render_pipe_profile__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__render_pipe_profile__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__render_pipe_profile__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__render_pipe_profile__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__render_pipe_profile__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,adl__render_pipe_profile__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,adl__render_pipe_profile__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,adl__render_pipe_profile__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,adl__render_pipe_profile__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,adl__render_pipe_profile__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,adl__render_pipe_profile__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,adl__render_pipe_profile__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,adl__render_pipe_profile__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,adl__render_pipe_profile__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, adl__render_pipe_profile__slm_bytes_read__max,adl__render_pipe_profile__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, adl__render_pipe_profile__slm_bytes_written__max,adl__render_pipe_profile__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,adl__render_pipe_profile__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,adl__render_pipe_profile__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, adl__render_pipe_profile__l3_shader_throughput__max,adl__render_pipe_profile__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,adl__render_pipe_profile__shader_barriers__read);

      intel_perf_query_add_counter_float(query, 157, 216, percentage_max_float,adl__render_pipe_profile__vf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 158, 220, percentage_max_float,adl__render_pipe_profile__vs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 159, 224, percentage_max_float,adl__render_pipe_profile__hs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 160, 228, percentage_max_float,adl__render_pipe_profile__ds_bottleneck__read);

      intel_perf_query_add_counter_float(query, 161, 232, percentage_max_float,adl__render_pipe_profile__gs_bottleneck__read);

      intel_perf_query_add_counter_float(query, 162, 236, percentage_max_float,adl__render_pipe_profile__so_bottleneck__read);

      intel_perf_query_add_counter_float(query, 163, 240, percentage_max_float,adl__render_pipe_profile__cl_bottleneck__read);

      intel_perf_query_add_counter_float(query, 164, 244, percentage_max_float,adl__render_pipe_profile__sf_bottleneck__read);

      intel_perf_query_add_counter_float(query, 165, 248, percentage_max_float,adl__render_pipe_profile__hi_depth_bottleneck__read);

      intel_perf_query_add_counter_float(query, 167, 252, percentage_max_float,adl__render_pipe_profile__bc_bottleneck__read);

      intel_perf_query_add_counter_float(query, 168, 256, percentage_max_float,adl__render_pipe_profile__hs_stall__read);

      intel_perf_query_add_counter_float(query, 169, 260, percentage_max_float,adl__render_pipe_profile__ds_stall__read);

      intel_perf_query_add_counter_float(query, 170, 264, percentage_max_float,adl__render_pipe_profile__so_stall__read);

      intel_perf_query_add_counter_float(query, 171, 268, percentage_max_float,adl__render_pipe_profile__cl_stall__read);

      intel_perf_query_add_counter_float(query, 172, 272, percentage_max_float,adl__render_pipe_profile__sf_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 35);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "73acd312-486b-4aa8-bcd1-232bfb29481b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14112400 },
         { .reg = 0x00009888, .val = 0x14312400 },
         { .reg = 0x00009888, .val = 0x14512474 },
         { .reg = 0x00009888, .val = 0x14712400 },
         { .reg = 0x00009888, .val = 0x14912400 },
         { .reg = 0x00009888, .val = 0x14B12400 },
         { .reg = 0x00009888, .val = 0x240A0019 },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x24070002 },
         { .reg = 0x00009888, .val = 0x10110074 },
         { .reg = 0x00009888, .val = 0x08110000 },
         { .reg = 0x00009888, .val = 0x10128000 },
         { .reg = 0x00009888, .val = 0x1C130400 },
         { .reg = 0x00009888, .val = 0x12310074 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x08310000 },
         { .reg = 0x00009888, .val = 0x12328000 },
         { .reg = 0x00009888, .val = 0x1C330800 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x0A510000 },
         { .reg = 0x00009888, .val = 0x14528000 },
         { .reg = 0x00009888, .val = 0x1C531000 },
         { .reg = 0x00009888, .val = 0x16710074 },
         { .reg = 0x00009888, .val = 0x10710000 },
         { .reg = 0x00009888, .val = 0x0A710000 },
         { .reg = 0x00009888, .val = 0x16728000 },
         { .reg = 0x00009888, .val = 0x1C732000 },
         { .reg = 0x00009888, .val = 0x0E910074 },
         { .reg = 0x00009888, .val = 0x10910000 },
         { .reg = 0x00009888, .val = 0x06910000 },
         { .reg = 0x00009888, .val = 0x0E928000 },
         { .reg = 0x00009888, .val = 0x1C930200 },
         { .reg = 0x00009888, .val = 0x00B10074 },
         { .reg = 0x00009888, .val = 0x10B10000 },
         { .reg = 0x00009888, .val = 0x00B28000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1E0F0020 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x2E020001 },
         { .reg = 0x00009888, .val = 0x2A030600 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x36003488 },
         { .reg = 0x00009888, .val = 0x3800001B },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x24050038 },
         { .reg = 0x00009888, .val = 0x24060080 },
         { .reg = 0x00009888, .val = 0x180A00F7 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105000 },
         { .reg = 0x00009888, .val = 0x5D100055 },
         { .reg = 0x00009888, .val = 0x17144000 },
         { .reg = 0x00009888, .val = 0x1D14AAA0 },
         { .reg = 0x00009888, .val = 0x01124000 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x19124000 },
         { .reg = 0x00009888, .val = 0x47100600 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100806 },
         { .reg = 0x00009888, .val = 0x51100408 },
         { .reg = 0x00009888, .val = 0x53100310 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000DC00, .val = 0x00000002 },
         { .reg = 0x0000DC04, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000DC08, .val = 0x00000002 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000DC10, .val = 0x00000002 },
         { .reg = 0x0000DC14, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00000002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000DC20, .val = 0x00000002 },
         { .reg = 0x0000DC24, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000DC28, .val = 0x00000002 },
         { .reg = 0x0000DC2C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000DC30, .val = 0x00000002 },
         { .reg = 0x0000DC34, .val = 0x0000FFBF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__hdc_and_sf__avg_gpu_core_frequency__max,adl__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__hdc_and_sf__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__hdc_and_sf__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__hdc_and_sf__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__hdc_and_sf__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__hdc_and_sf__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__hdc_and_sf__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__hdc_and_sf__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__hdc_and_sf__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__hdc_and_sf__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__hdc_and_sf__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,adl__hdc_and_sf__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,adl__hdc_and_sf__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,adl__hdc_and_sf__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,adl__hdc_and_sf__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,adl__hdc_and_sf__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,adl__hdc_and_sf__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,adl__hdc_and_sf__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,adl__hdc_and_sf__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,adl__hdc_and_sf__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, adl__hdc_and_sf__slm_bytes_read__max,adl__hdc_and_sf__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, adl__hdc_and_sf__slm_bytes_written__max,adl__hdc_and_sf__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,adl__hdc_and_sf__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,adl__hdc_and_sf__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, adl__hdc_and_sf__l3_shader_throughput__max,adl__hdc_and_sf__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,adl__hdc_and_sf__shader_barriers__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 356, 216, percentage_max_float,adl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 357, 220, percentage_max_float,adl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 358, 224, percentage_max_float,adl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 359, 228, percentage_max_float,adl__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 490, 232, percentage_max_float,adl__hdc_and_sf__non_sampler_shader04_access_stalled_on_l3__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 491, 236, percentage_max_float,adl__hdc_and_sf__non_sampler_shader05_access_stalled_on_l3__read);
      }

      intel_perf_query_add_counter_float(query, 237, 240, percentage_max_float,adl__hdc_and_sf__poly_data_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_rasterizer_and_pixel_backend_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 41);

   query->name = "Metric set RasterizerAndPixelBackend";
   query->symbol_name = "RasterizerAndPixelBackend";
   query->guid = "ef158e77-1bca-402c-b2d6-1654908fd977";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1E075000 },
         { .reg = 0x00009888, .val = 0x1A0700C0 },
         { .reg = 0x00009888, .val = 0x1E055000 },
         { .reg = 0x00009888, .val = 0x1A0500C0 },
         { .reg = 0x00009888, .val = 0x1E065000 },
         { .reg = 0x00009888, .val = 0x1A0600C0 },
         { .reg = 0x00009888, .val = 0x2A0A7300 },
         { .reg = 0x00009888, .val = 0x2C0A0000 },
         { .reg = 0x00009888, .val = 0x120800A0 },
         { .reg = 0x00009888, .val = 0x0A07C000 },
         { .reg = 0x00009888, .val = 0x0E070027 },
         { .reg = 0x00009888, .val = 0x10070000 },
         { .reg = 0x00009888, .val = 0x24070000 },
         { .reg = 0x00009888, .val = 0x2A032000 },
         { .reg = 0x00009888, .val = 0x2C030008 },
         { .reg = 0x00009888, .val = 0x18006000 },
         { .reg = 0x00009888, .val = 0x360036D8 },
         { .reg = 0x00009888, .val = 0x38003299 },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x2A010400 },
         { .reg = 0x00009888, .val = 0x2C010001 },
         { .reg = 0x00009888, .val = 0x0C05C000 },
         { .reg = 0x00009888, .val = 0x00052700 },
         { .reg = 0x00009888, .val = 0x10050000 },
         { .reg = 0x00009888, .val = 0x24050000 },
         { .reg = 0x00009888, .val = 0x22050000 },
         { .reg = 0x00009888, .val = 0x0C0600C0 },
         { .reg = 0x00009888, .val = 0x0E062700 },
         { .reg = 0x00009888, .val = 0x10060000 },
         { .reg = 0x00009888, .val = 0x24060000 },
         { .reg = 0x00009888, .val = 0x26060000 },
         { .reg = 0x00009888, .val = 0x000A0144 },
         { .reg = 0x00009888, .val = 0x0E0A0145 },
         { .reg = 0x00009888, .val = 0x100A0156 },
         { .reg = 0x00009888, .val = 0x040A014F },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x120A4000 },
         { .reg = 0x00009888, .val = 0x140A4000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009888, .val = 0x08081980 },
         { .reg = 0x00009888, .val = 0x0A080032 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x31152800 },
         { .reg = 0x00009888, .val = 0x331500A0 },
         { .reg = 0x00009888, .val = 0x31352800 },
         { .reg = 0x00009888, .val = 0x333500A0 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105FA5 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x17144000 },
         { .reg = 0x00009888, .val = 0x1D14AAA0 },
         { .reg = 0x00009888, .val = 0x1F14002A },
         { .reg = 0x00009888, .val = 0x1B140A00 },
         { .reg = 0x00009888, .val = 0x01124000 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x19124000 },
         { .reg = 0x00009888, .val = 0x1B124000 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x07150016 },
         { .reg = 0x00009888, .val = 0x09150096 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03168000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x0B350016 },
         { .reg = 0x00009888, .val = 0x0D350096 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x07364000 },
         { .reg = 0x00009888, .val = 0x47100400 },
         { .reg = 0x00009888, .val = 0x4D100010 },
         { .reg = 0x00009888, .val = 0x4F100404 },
         { .reg = 0x00009888, .val = 0x51100202 },
         { .reg = 0x00009888, .val = 0x53100002 },
         { .reg = 0x00009888, .val = 0x55100204 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x49101404 },
         { .reg = 0x00009888, .val = 0x4B101010 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000DC00, .val = 0x00000038 },
         { .reg = 0x0000DC04, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000DC08, .val = 0x000000C0 },
         { .reg = 0x0000DC0C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__rasterizer_and_pixel_backend__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__rasterizer_and_pixel_backend__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max,adl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__rasterizer_and_pixel_backend__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__rasterizer_and_pixel_backend__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__rasterizer_and_pixel_backend__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__rasterizer_and_pixel_backend__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__rasterizer_and_pixel_backend__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__rasterizer_and_pixel_backend__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__rasterizer_and_pixel_backend__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__rasterizer_and_pixel_backend__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__rasterizer_and_pixel_backend__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__rasterizer_and_pixel_backend__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 139, 96, NULL,adl__rasterizer_and_pixel_backend__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 104, NULL,adl__rasterizer_and_pixel_backend__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 112, NULL,adl__rasterizer_and_pixel_backend__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 120, NULL,adl__rasterizer_and_pixel_backend__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 128, NULL,adl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 136, NULL,adl__rasterizer_and_pixel_backend__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 144, NULL,adl__rasterizer_and_pixel_backend__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 152, NULL,adl__rasterizer_and_pixel_backend__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 160, NULL,adl__rasterizer_and_pixel_backend__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 75, 168, adl__rasterizer_and_pixel_backend__slm_bytes_read__max,adl__rasterizer_and_pixel_backend__slm_bytes_read__read);

      intel_perf_query_add_counter_uint64(query, 141, 176, adl__rasterizer_and_pixel_backend__slm_bytes_written__max,adl__rasterizer_and_pixel_backend__slm_bytes_written__read);

      intel_perf_query_add_counter_uint64(query, 142, 184, NULL,adl__rasterizer_and_pixel_backend__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 192, NULL,adl__rasterizer_and_pixel_backend__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 146, 200, adl__rasterizer_and_pixel_backend__l3_shader_throughput__max,adl__rasterizer_and_pixel_backend__l3_shader_throughput__read);

      intel_perf_query_add_counter_uint64(query, 147, 208, NULL,adl__rasterizer_and_pixel_backend__shader_barriers__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 266, 216, percentage_max_float,adl__rasterizer_and_pixel_backend__rasterizer0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 261, 220, percentage_max_float,adl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 360, 224, percentage_max_float,adl__rasterizer_and_pixel_backend__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 362, 228, percentage_max_float,adl__rasterizer_and_pixel_backend__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 363, 232, percentage_max_float,adl__rasterizer_and_pixel_backend__ps_output01_available__read);

      intel_perf_query_add_counter_float(query, 492, 236, percentage_max_float,adl__rasterizer_and_pixel_backend__ps_output02_available__read);

      intel_perf_query_add_counter_float(query, 364, 240, percentage_max_float,adl__rasterizer_and_pixel_backend__pixel_values00_ready__read);

      intel_perf_query_add_counter_float(query, 365, 244, percentage_max_float,adl__rasterizer_and_pixel_backend__pixel_values01_ready__read);

      intel_perf_query_add_counter_float(query, 493, 248, percentage_max_float,adl__rasterizer_and_pixel_backend__pixel_values02_ready__read);

      intel_perf_query_add_counter_float(query, 436, 252, percentage_max_float,adl__rasterizer_and_pixel_backend__gt_request_queue00_full__read);

      intel_perf_query_add_counter_float(query, 437, 256, percentage_max_float,adl__rasterizer_and_pixel_backend__gt_request_queue01_full__read);

      intel_perf_query_add_counter_float(query, 438, 260, percentage_max_float,adl__rasterizer_and_pixel_backend__gt_request_queue10_full__read);

      intel_perf_query_add_counter_float(query, 439, 264, percentage_max_float,adl__rasterizer_and_pixel_backend__gt_request_queue11_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "L3_1";
   query->symbol_name = "L3_1";
   query->guid = "b997e963-d322-4d97-b631-f875b2135fc9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04022000 },
         { .reg = 0x00009888, .val = 0x06022800 },
         { .reg = 0x00009888, .val = 0x04002827 },
         { .reg = 0x00009888, .val = 0x0600202C },
         { .reg = 0x00009888, .val = 0x00020024 },
         { .reg = 0x00009888, .val = 0x0E020025 },
         { .reg = 0x00009888, .val = 0x10020026 },
         { .reg = 0x00009888, .val = 0x12020027 },
         { .reg = 0x00009888, .val = 0x1402002C },
         { .reg = 0x00009888, .val = 0x1602002D },
         { .reg = 0x00009888, .val = 0x1802002E },
         { .reg = 0x00009888, .val = 0x1A02002F },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x2C020000 },
         { .reg = 0x00009888, .val = 0x00034000 },
         { .reg = 0x00009888, .val = 0x1A032000 },
         { .reg = 0x00009888, .val = 0x1C032000 },
         { .reg = 0x00009888, .val = 0x1E032000 },
         { .reg = 0x00009888, .val = 0x2A035500 },
         { .reg = 0x00009888, .val = 0x1C000024 },
         { .reg = 0x00009888, .val = 0x1E000025 },
         { .reg = 0x00009888, .val = 0x02000026 },
         { .reg = 0x00009888, .val = 0x0800002D },
         { .reg = 0x00009888, .val = 0x0A00002E },
         { .reg = 0x00009888, .val = 0x0C00002F },
         { .reg = 0x00009888, .val = 0x360036D8 },
         { .reg = 0x00009888, .val = 0x18006000 },
         { .reg = 0x00009888, .val = 0x380000DB },
         { .reg = 0x00009888, .val = 0x1A000000 },
         { .reg = 0x00009888, .val = 0x34000000 },
         { .reg = 0x00009888, .val = 0x000A8000 },
         { .reg = 0x00009888, .val = 0x0E0A8000 },
         { .reg = 0x00009888, .val = 0x100A8000 },
         { .reg = 0x00009888, .val = 0x120A8000 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x17144000 },
         { .reg = 0x00009888, .val = 0x1D14AAAA },
         { .reg = 0x00009888, .val = 0x1F14002A },
         { .reg = 0x00009888, .val = 0x1B14AA00 },
         { .reg = 0x00009888, .val = 0x01124000 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x19124000 },
         { .reg = 0x00009888, .val = 0x1B124000 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x4D100606 },
         { .reg = 0x00009888, .val = 0x4F100000 },
         { .reg = 0x00009888, .val = 0x51100000 },
         { .reg = 0x00009888, .val = 0x53100000 },
         { .reg = 0x00009888, .val = 0x55100600 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100006 },
         { .reg = 0x00009888, .val = 0x49100606 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__l3_1__avg_gpu_core_frequency__max,adl__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,adl__l3_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,adl__l3_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,adl__l3_1__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,adl__l3_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,adl__l3_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,adl__l3_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,adl__l3_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,adl__l3_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,adl__l3_1__cs_threads__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 440, 88, percentage_max_float,adl__l3_1__l30_bank0_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 441, 92, percentage_max_float,adl__l3_1__l30_bank1_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 494, 96, percentage_max_float,adl__l3_1__l30_bank4_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 495, 100, percentage_max_float,adl__l3_1__l30_bank5_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "L3_2";
   query->symbol_name = "L3_2";
   query->guid = "57c490ef-4993-465e-b1e0-774fbc104fdf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04023027 },
         { .reg = 0x00009888, .val = 0x0602382C },
         { .reg = 0x00009888, .val = 0x04003000 },
         { .reg = 0x00009888, .val = 0x06003800 },
         { .reg = 0x00009888, .val = 0x1C020024 },
         { .reg = 0x00009888, .val = 0x1E020025 },
         { .reg = 0x00009888, .val = 0x02020026 },
         { .reg = 0x00009888, .val = 0x0802002D },
         { .reg = 0x00009888, .val = 0x0A02002E },
         { .reg = 0x00009888, .val = 0x0C02002F },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x02034000 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08034000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x00000024 },
         { .reg = 0x00009888, .val = 0x0E000025 },
         { .reg = 0x00009888, .val = 0x10000026 },
         { .reg = 0x00009888, .val = 0x12000027 },
         { .reg = 0x00009888, .val = 0x1400002C },
         { .reg = 0x00009888, .val = 0x1600002D },
         { .reg = 0x00009888, .val = 0x1800002E },
         { .reg = 0x00009888, .val = 0x1A00602F },
         { .reg = 0x00009888, .val = 0x36000003 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x1E006000 },
         { .reg = 0x00009888, .val = 0x34001B00 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009888, .val = 0x020A8000 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x17144000 },
         { .reg = 0x00009888, .val = 0x1D14AAAA },
         { .reg = 0x00009888, .val = 0x1F14002A },
         { .reg = 0x00009888, .val = 0x1B14AA00 },
         { .reg = 0x00009888, .val = 0x01124000 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x19124000 },
         { .reg = 0x00009888, .val = 0x1B124000 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x47100600 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F100606 },
         { .reg = 0x00009888, .val = 0x51100606 },
         { .reg = 0x00009888, .val = 0x53100606 },
         { .reg = 0x00009888, .val = 0x55100006 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__l3_2__avg_gpu_core_frequency__max,adl__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__l3_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__l3_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__l3_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__l3_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__l3_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__l3_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__l3_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__l3_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__l3_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__l3_2__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 442, 92, percentage_max_float,adl__l3_2__l30_bank2_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 443, 96, percentage_max_float,adl__l3_2__l30_bank3_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 496, 100, percentage_max_float,adl__l3_2__l30_bank6_input_available__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 497, 104, percentage_max_float,adl__l3_2__l30_bank7_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_l3_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_3";
   query->symbol_name = "L3_3";
   query->guid = "50d02e16-414e-4b4c-adbd-71c584f857b5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04020200 },
         { .reg = 0x00009888, .val = 0x06020020 },
         { .reg = 0x00009888, .val = 0x04000200 },
         { .reg = 0x00009888, .val = 0x06000000 },
         { .reg = 0x00009888, .val = 0x08020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08034000 },
         { .reg = 0x00009888, .val = 0x0A000020 },
         { .reg = 0x00009888, .val = 0x0C000028 },
         { .reg = 0x00009888, .val = 0x36000000 },
         { .reg = 0x00009888, .val = 0x1E006000 },
         { .reg = 0x00009888, .val = 0x34000300 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x1B14A000 },
         { .reg = 0x00009888, .val = 0x1D14000A },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100000 },
         { .reg = 0x00009888, .val = 0x4D100606 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__l3_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__l3_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__l3_3__avg_gpu_core_frequency__max,adl__l3_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__l3_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__l3_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__l3_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__l3_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__l3_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__l3_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__l3_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__l3_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__l3_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__l3_3__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 444, 92, percentage_max_float,adl__l3_3__l30_bank0_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 498, 96, percentage_max_float,adl__l3_3__l30_bank4_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_l3_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_4";
   query->symbol_name = "L3_4";
   query->guid = "896dda0d-84b8-4d1d-b54b-c2e5ded94581";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04020A00 },
         { .reg = 0x00009888, .val = 0x06020800 },
         { .reg = 0x00009888, .val = 0x04000A00 },
         { .reg = 0x00009888, .val = 0x06000820 },
         { .reg = 0x00009888, .val = 0x0A020020 },
         { .reg = 0x00009888, .val = 0x0C020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x36000003 },
         { .reg = 0x00009888, .val = 0x1E000000 },
         { .reg = 0x00009888, .val = 0x34001800 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x1B14A000 },
         { .reg = 0x00009888, .val = 0x1D14000A },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__l3_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__l3_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__l3_4__avg_gpu_core_frequency__max,adl__l3_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__l3_4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__l3_4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__l3_4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__l3_4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__l3_4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__l3_4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__l3_4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__l3_4__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__l3_4__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__l3_4__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 445, 92, percentage_max_float,adl__l3_4__l30_bank1_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 499, 96, percentage_max_float,adl__l3_4__l30_bank5_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_l3_5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_5";
   query->symbol_name = "L3_5";
   query->guid = "f5e936f0-aacb-4aea-80a5-d434f21d427d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04021200 },
         { .reg = 0x00009888, .val = 0x06021000 },
         { .reg = 0x00009888, .val = 0x04001200 },
         { .reg = 0x00009888, .val = 0x06001020 },
         { .reg = 0x00009888, .val = 0x0A020020 },
         { .reg = 0x00009888, .val = 0x0C020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x36000003 },
         { .reg = 0x00009888, .val = 0x1E000000 },
         { .reg = 0x00009888, .val = 0x34001800 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x1B14A000 },
         { .reg = 0x00009888, .val = 0x1D14000A },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__l3_5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__l3_5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__l3_5__avg_gpu_core_frequency__max,adl__l3_5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__l3_5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__l3_5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__l3_5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__l3_5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__l3_5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__l3_5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__l3_5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__l3_5__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__l3_5__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__l3_5__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 446, 92, percentage_max_float,adl__l3_5__l30_bank2_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 500, 96, percentage_max_float,adl__l3_5__l30_bank6_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_l3_6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "L3_6";
   query->symbol_name = "L3_6";
   query->guid = "c9b51681-9e54-49b0-918d-4e588078d5cd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x04021A00 },
         { .reg = 0x00009888, .val = 0x06021800 },
         { .reg = 0x00009888, .val = 0x04001A00 },
         { .reg = 0x00009888, .val = 0x06001820 },
         { .reg = 0x00009888, .val = 0x0A020020 },
         { .reg = 0x00009888, .val = 0x0C020028 },
         { .reg = 0x00009888, .val = 0x2E020000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x18032000 },
         { .reg = 0x00009888, .val = 0x08000028 },
         { .reg = 0x00009888, .val = 0x36000003 },
         { .reg = 0x00009888, .val = 0x1E000000 },
         { .reg = 0x00009888, .val = 0x34001800 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5B100550 },
         { .reg = 0x00009888, .val = 0x1B14A000 },
         { .reg = 0x00009888, .val = 0x1D14000A },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__l3_6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__l3_6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__l3_6__avg_gpu_core_frequency__max,adl__l3_6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__l3_6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__l3_6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__l3_6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__l3_6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__l3_6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__l3_6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__l3_6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__l3_6__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__l3_6__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__l3_6__eu_thread_occupancy__read);

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 447, 92, percentage_max_float,adl__l3_6__l30_bank3_output_ready__read);
      }

      if (perf->sys_vars.slice_mask & 1) {
         intel_perf_query_add_counter_float(query, 501, 96, percentage_max_float,adl__l3_6__l30_bank7_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Sampler_1";
   query->symbol_name = "Sampler_1";
   query->guid = "c4a47a95-b80a-46d3-abf0-98a95a840407";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C121600 },
         { .reg = 0x00009888, .val = 0x18141600 },
         { .reg = 0x00009888, .val = 0x1C325600 },
         { .reg = 0x00009888, .val = 0x18341600 },
         { .reg = 0x00009888, .val = 0x1C521600 },
         { .reg = 0x00009888, .val = 0x185416A6 },
         { .reg = 0x00009888, .val = 0x1C721600 },
         { .reg = 0x00009888, .val = 0x18741600 },
         { .reg = 0x00009888, .val = 0x1C921600 },
         { .reg = 0x00009888, .val = 0x18941600 },
         { .reg = 0x00009888, .val = 0x1CB21600 },
         { .reg = 0x00009888, .val = 0x18B41600 },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x2407002B },
         { .reg = 0x00009888, .val = 0x04120086 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x02124000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x021400A6 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x00140000 },
         { .reg = 0x00009888, .val = 0x1A150020 },
         { .reg = 0x00009888, .val = 0x1E320086 },
         { .reg = 0x00009888, .val = 0x20320000 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x1C3400A6 },
         { .reg = 0x00009888, .val = 0x10340000 },
         { .reg = 0x00009888, .val = 0x0E340000 },
         { .reg = 0x00009888, .val = 0x1C358000 },
         { .reg = 0x00009888, .val = 0x1A520086 },
         { .reg = 0x00009888, .val = 0x20520000 },
         { .reg = 0x00009888, .val = 0x18524000 },
         { .reg = 0x00009888, .val = 0x1C53C000 },
         { .reg = 0x00009888, .val = 0x10540000 },
         { .reg = 0x00009888, .val = 0x0C540000 },
         { .reg = 0x00009888, .val = 0x1C550800 },
         { .reg = 0x00009888, .val = 0x16720086 },
         { .reg = 0x00009888, .val = 0x20720000 },
         { .reg = 0x00009888, .val = 0x14724000 },
         { .reg = 0x00009888, .val = 0x1C733000 },
         { .reg = 0x00009888, .val = 0x147400A6 },
         { .reg = 0x00009888, .val = 0x10740000 },
         { .reg = 0x00009888, .val = 0x0A740000 },
         { .reg = 0x00009888, .val = 0x1C750080 },
         { .reg = 0x00009888, .val = 0x12920086 },
         { .reg = 0x00009888, .val = 0x20920000 },
         { .reg = 0x00009888, .val = 0x10924000 },
         { .reg = 0x00009888, .val = 0x1C930C00 },
         { .reg = 0x00009888, .val = 0x109400A6 },
         { .reg = 0x00009888, .val = 0x08940000 },
         { .reg = 0x00009888, .val = 0x1C950008 },
         { .reg = 0x00009888, .val = 0x0EB20086 },
         { .reg = 0x00009888, .val = 0x20B20000 },
         { .reg = 0x00009888, .val = 0x00B24000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1CB30200 },
         { .reg = 0x00009888, .val = 0x00B400A6 },
         { .reg = 0x00009888, .val = 0x10B40000 },
         { .reg = 0x00009888, .val = 0x18B58000 },
         { .reg = 0x00009888, .val = 0x1E0F0028 },
         { .reg = 0x00009888, .val = 0x14104000 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x2C024000 },
         { .reg = 0x00009888, .val = 0x2E020001 },
         { .reg = 0x00009888, .val = 0x2A03A500 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x36003248 },
         { .reg = 0x00009888, .val = 0x380024DB },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x220500A0 },
         { .reg = 0x00009888, .val = 0x24062800 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105005 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x17144000 },
         { .reg = 0x00009888, .val = 0x1D14AAA0 },
         { .reg = 0x00009888, .val = 0x1F14002A },
         { .reg = 0x00009888, .val = 0x1B140A00 },
         { .reg = 0x00009888, .val = 0x01124000 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x19124000 },
         { .reg = 0x00009888, .val = 0x1B124000 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x47100600 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F10060A },
         { .reg = 0x00009888, .val = 0x5110000A },
         { .reg = 0x00009888, .val = 0x53100404 },
         { .reg = 0x00009888, .val = 0x55101808 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100001 },
         { .reg = 0x00009888, .val = 0x49100118 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000DC40, .val = 0x003F0000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000180 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000600 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000DC20, .val = 0x00001800 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000DC28, .val = 0x00006000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__sampler_1__avg_gpu_core_frequency__max,adl__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__sampler_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__sampler_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__sampler_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__sampler_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__sampler_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__sampler_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__sampler_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__sampler_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__sampler_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__sampler_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 448, 92, percentage_max_float,adl__sampler_1__sampler00_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 449, 96, percentage_max_float,adl__sampler_1__sampler01_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 502, 100, percentage_max_float,adl__sampler_1__sampler02_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 503, 104, percentage_max_float,adl__sampler_1__sampler03_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 504, 108, percentage_max_float,adl__sampler_1__sampler04_input_available__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 505, 112, percentage_max_float,adl__sampler_1__sampler05_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_sampler_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Sampler_2";
   query->symbol_name = "Sampler_2";
   query->guid = "2d7c9960-0ec0-4aa2-9bd0-e6d76f214bf7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C123E00 },
         { .reg = 0x00009888, .val = 0x04143E00 },
         { .reg = 0x00009888, .val = 0x0C323E00 },
         { .reg = 0x00009888, .val = 0x04343E00 },
         { .reg = 0x00009888, .val = 0x0C523E00 },
         { .reg = 0x00009888, .val = 0x04543E00 },
         { .reg = 0x00009888, .val = 0x0C723E00 },
         { .reg = 0x00009888, .val = 0x04743E00 },
         { .reg = 0x00009888, .val = 0x0C923E00 },
         { .reg = 0x00009888, .val = 0x04943E00 },
         { .reg = 0x00009888, .val = 0x0CB23E00 },
         { .reg = 0x00009888, .val = 0x04B43E00 },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x2407002B },
         { .reg = 0x00009888, .val = 0x04120033 },
         { .reg = 0x00009888, .val = 0x20120000 },
         { .reg = 0x00009888, .val = 0x02124000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x02140013 },
         { .reg = 0x00009888, .val = 0x10140000 },
         { .reg = 0x00009888, .val = 0x00140000 },
         { .reg = 0x00009888, .val = 0x1A150020 },
         { .reg = 0x00009888, .val = 0x1E320033 },
         { .reg = 0x00009888, .val = 0x20320000 },
         { .reg = 0x00009888, .val = 0x1C324000 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x1C340013 },
         { .reg = 0x00009888, .val = 0x10340000 },
         { .reg = 0x00009888, .val = 0x0E340000 },
         { .reg = 0x00009888, .val = 0x1C358000 },
         { .reg = 0x00009888, .val = 0x1A520033 },
         { .reg = 0x00009888, .val = 0x20520000 },
         { .reg = 0x00009888, .val = 0x18524000 },
         { .reg = 0x00009888, .val = 0x1C53C000 },
         { .reg = 0x00009888, .val = 0x18540013 },
         { .reg = 0x00009888, .val = 0x10540000 },
         { .reg = 0x00009888, .val = 0x0C540000 },
         { .reg = 0x00009888, .val = 0x1C550800 },
         { .reg = 0x00009888, .val = 0x16720033 },
         { .reg = 0x00009888, .val = 0x20720000 },
         { .reg = 0x00009888, .val = 0x14724000 },
         { .reg = 0x00009888, .val = 0x1C733000 },
         { .reg = 0x00009888, .val = 0x14740013 },
         { .reg = 0x00009888, .val = 0x10740000 },
         { .reg = 0x00009888, .val = 0x0A740000 },
         { .reg = 0x00009888, .val = 0x1C750080 },
         { .reg = 0x00009888, .val = 0x12920033 },
         { .reg = 0x00009888, .val = 0x20920000 },
         { .reg = 0x00009888, .val = 0x10924000 },
         { .reg = 0x00009888, .val = 0x1C930C00 },
         { .reg = 0x00009888, .val = 0x10940013 },
         { .reg = 0x00009888, .val = 0x08940000 },
         { .reg = 0x00009888, .val = 0x1C950008 },
         { .reg = 0x00009888, .val = 0x0EB20033 },
         { .reg = 0x00009888, .val = 0x20B20000 },
         { .reg = 0x00009888, .val = 0x00B24000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1CB30200 },
         { .reg = 0x00009888, .val = 0x00B40013 },
         { .reg = 0x00009888, .val = 0x10B40000 },
         { .reg = 0x00009888, .val = 0x18B58000 },
         { .reg = 0x00009888, .val = 0x1E0F0028 },
         { .reg = 0x00009888, .val = 0x14104000 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x2C024000 },
         { .reg = 0x00009888, .val = 0x2E020001 },
         { .reg = 0x00009888, .val = 0x2A03A500 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x36003248 },
         { .reg = 0x00009888, .val = 0x380024DB },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C004000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x220500A0 },
         { .reg = 0x00009888, .val = 0x24062800 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105005 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x17144000 },
         { .reg = 0x00009888, .val = 0x1D14AAA0 },
         { .reg = 0x00009888, .val = 0x1F14002A },
         { .reg = 0x00009888, .val = 0x1B140A00 },
         { .reg = 0x00009888, .val = 0x01124000 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x19124000 },
         { .reg = 0x00009888, .val = 0x1B124000 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x47100600 },
         { .reg = 0x00009888, .val = 0x4D100000 },
         { .reg = 0x00009888, .val = 0x4F10060A },
         { .reg = 0x00009888, .val = 0x5110000A },
         { .reg = 0x00009888, .val = 0x53100404 },
         { .reg = 0x00009888, .val = 0x55101808 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100001 },
         { .reg = 0x00009888, .val = 0x49100118 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000DC40, .val = 0x003F0000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000180 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000600 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000DC20, .val = 0x00001800 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000DC28, .val = 0x00006000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__sampler_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__sampler_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__sampler_2__avg_gpu_core_frequency__max,adl__sampler_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__sampler_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__sampler_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__sampler_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__sampler_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__sampler_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__sampler_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__sampler_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__sampler_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__sampler_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__sampler_2__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 450, 92, percentage_max_float,adl__sampler_2__sampler00_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 451, 96, percentage_max_float,adl__sampler_2__sampler01_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 506, 100, percentage_max_float,adl__sampler_2__sampler02_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 507, 104, percentage_max_float,adl__sampler_2__sampler03_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 508, 108, percentage_max_float,adl__sampler_2__sampler04_output_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 509, 112, percentage_max_float,adl__sampler_2__sampler05_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_tdl_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 29);

   query->name = "TDL_1";
   query->symbol_name = "TDL_1";
   query->guid = "85afcb2a-90a8-4b1a-adc3-61e322884520";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2611001C },
         { .reg = 0x00009888, .val = 0x2631001C },
         { .reg = 0x00009888, .val = 0x2651001C },
         { .reg = 0x00009888, .val = 0x2671001C },
         { .reg = 0x00009888, .val = 0x2691001C },
         { .reg = 0x00009888, .val = 0x26B1001C },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x24070002 },
         { .reg = 0x00009888, .val = 0x16110103 },
         { .reg = 0x00009888, .val = 0x1C110104 },
         { .reg = 0x00009888, .val = 0x1E110105 },
         { .reg = 0x00009888, .val = 0x02110106 },
         { .reg = 0x00009888, .val = 0x04110107 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x0A110000 },
         { .reg = 0x00009888, .val = 0x0E110000 },
         { .reg = 0x00009888, .val = 0x00110000 },
         { .reg = 0x00009888, .val = 0x16128000 },
         { .reg = 0x00009888, .val = 0x1C128000 },
         { .reg = 0x00009888, .val = 0x1E128000 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x1C132000 },
         { .reg = 0x00009888, .val = 0x1E130003 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x14310103 },
         { .reg = 0x00009888, .val = 0x06310104 },
         { .reg = 0x00009888, .val = 0x08310105 },
         { .reg = 0x00009888, .val = 0x0A310106 },
         { .reg = 0x00009888, .val = 0x0C310107 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x02310000 },
         { .reg = 0x00009888, .val = 0x04310000 },
         { .reg = 0x00009888, .val = 0x14328000 },
         { .reg = 0x00009888, .val = 0x06328000 },
         { .reg = 0x00009888, .val = 0x08328000 },
         { .reg = 0x00009888, .val = 0x0A328000 },
         { .reg = 0x00009888, .val = 0x0C328000 },
         { .reg = 0x00009888, .val = 0x1C331100 },
         { .reg = 0x00009888, .val = 0x16338000 },
         { .reg = 0x00009888, .val = 0x18338000 },
         { .reg = 0x00009888, .val = 0x1A338000 },
         { .reg = 0x00009888, .val = 0x12510103 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x08510000 },
         { .reg = 0x00009888, .val = 0x12528000 },
         { .reg = 0x00009888, .val = 0x1C530800 },
         { .reg = 0x00009888, .val = 0x10710103 },
         { .reg = 0x00009888, .val = 0x08710000 },
         { .reg = 0x00009888, .val = 0x10728000 },
         { .reg = 0x00009888, .val = 0x1C730400 },
         { .reg = 0x00009888, .val = 0x0E910103 },
         { .reg = 0x00009888, .val = 0x10910000 },
         { .reg = 0x00009888, .val = 0x06910000 },
         { .reg = 0x00009888, .val = 0x0E928000 },
         { .reg = 0x00009888, .val = 0x1C930200 },
         { .reg = 0x00009888, .val = 0x00B10103 },
         { .reg = 0x00009888, .val = 0x10B10000 },
         { .reg = 0x00009888, .val = 0x00B28000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1C0F8000 },
         { .reg = 0x00009888, .val = 0x10104000 },
         { .reg = 0x00009888, .val = 0x10024000 },
         { .reg = 0x00009888, .val = 0x1C032000 },
         { .reg = 0x00009888, .val = 0x1E034000 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x360026CA },
         { .reg = 0x00009888, .val = 0x38002402 },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C004000 },
         { .reg = 0x00009888, .val = 0x1E004000 },
         { .reg = 0x00009888, .val = 0x34001200 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x240582C0 },
         { .reg = 0x00009888, .val = 0x26050002 },
         { .reg = 0x00009888, .val = 0x2205FFA0 },
         { .reg = 0x00009888, .val = 0x24060020 },
         { .reg = 0x00009888, .val = 0x100A8000 },
         { .reg = 0x00009888, .val = 0x120A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101415 },
         { .reg = 0x00009888, .val = 0x17144000 },
         { .reg = 0x00009888, .val = 0x1D142AAA },
         { .reg = 0x00009888, .val = 0x1F140028 },
         { .reg = 0x00009888, .val = 0x1B14AA00 },
         { .reg = 0x00009888, .val = 0x01124000 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x47100600 },
         { .reg = 0x00009888, .val = 0x4D100808 },
         { .reg = 0x00009888, .val = 0x4F100006 },
         { .reg = 0x00009888, .val = 0x51100804 },
         { .reg = 0x00009888, .val = 0x53100008 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x55100800 },
         { .reg = 0x00009888, .val = 0x57100008 },
         { .reg = 0x00009888, .val = 0x49100808 },
         { .reg = 0x00009888, .val = 0x4B100808 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000DC00, .val = 0x00000002 },
         { .reg = 0x0000DC04, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000DC08, .val = 0x00000002 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000DC10, .val = 0x00000002 },
         { .reg = 0x0000DC14, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00000002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000DC20, .val = 0x00000002 },
         { .reg = 0x0000DC24, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000DC28, .val = 0x00000002 },
         { .reg = 0x0000DC2C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00007800 },
         { .reg = 0x0000D974, .val = 0x0000F0FF },
         { .reg = 0x0000DC30, .val = 0x00007800 },
         { .reg = 0x0000DC34, .val = 0x0000F0FF },
         { .reg = 0x0000D978, .val = 0x00078000 },
         { .reg = 0x0000D97C, .val = 0x00000FFF },
         { .reg = 0x0000DC38, .val = 0x00078000 },
         { .reg = 0x0000DC3C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__tdl_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__tdl_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__tdl_1__avg_gpu_core_frequency__max,adl__tdl_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__tdl_1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__tdl_1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__tdl_1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__tdl_1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__tdl_1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__tdl_1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__tdl_1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__tdl_1__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__tdl_1__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__tdl_1__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 452, 92, percentage_max_float,adl__tdl_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 453, 96, percentage_max_float,adl__tdl_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 510, 100, percentage_max_float,adl__tdl_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 511, 104, percentage_max_float,adl__tdl_1__non_ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 512, 108, percentage_max_float,adl__tdl_1__non_ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 513, 112, percentage_max_float,adl__tdl_1__non_ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 456, 116, percentage_max_float,adl__tdl_1__thread_header00_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 457, 120, percentage_max_float,adl__tdl_1__thread_header00_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 458, 124, percentage_max_float,adl__tdl_1__thread_header00_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 459, 128, percentage_max_float,adl__tdl_1__thread_header00_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 460, 132, percentage_max_float,adl__tdl_1__thread_header01_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 461, 136, percentage_max_float,adl__tdl_1__thread_header01_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 462, 140, percentage_max_float,adl__tdl_1__thread_header01_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 463, 144, percentage_max_float,adl__tdl_1__thread_header01_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 464, 148, percentage_max_float,adl__tdl_1__thread_header00_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 465, 152, percentage_max_float,adl__tdl_1__thread_header01_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_tdl_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 24);

   query->name = "TDL_2";
   query->symbol_name = "TDL_2";
   query->guid = "780e4dd7-8360-4294-9ff6-3bef25e0fe09";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x24110340 },
         { .reg = 0x00009888, .val = 0x24310340 },
         { .reg = 0x00009888, .val = 0x24510340 },
         { .reg = 0x00009888, .val = 0x24710340 },
         { .reg = 0x00009888, .val = 0x24910340 },
         { .reg = 0x00009888, .val = 0x24B10340 },
         { .reg = 0x00009888, .val = 0x26B1001C },
         { .reg = 0x00009888, .val = 0x1C07C000 },
         { .reg = 0x00009888, .val = 0x2407002B },
         { .reg = 0x00009888, .val = 0x2207FF00 },
         { .reg = 0x00009888, .val = 0x021100F3 },
         { .reg = 0x00009888, .val = 0x041100F2 },
         { .reg = 0x00009888, .val = 0x10110000 },
         { .reg = 0x00009888, .val = 0x00110000 },
         { .reg = 0x00009888, .val = 0x02128000 },
         { .reg = 0x00009888, .val = 0x04128000 },
         { .reg = 0x00009888, .val = 0x12138000 },
         { .reg = 0x00009888, .val = 0x14138000 },
         { .reg = 0x00009888, .val = 0x1C3100F3 },
         { .reg = 0x00009888, .val = 0x1E3100F2 },
         { .reg = 0x00009888, .val = 0x10310000 },
         { .reg = 0x00009888, .val = 0x0E310000 },
         { .reg = 0x00009888, .val = 0x1C328000 },
         { .reg = 0x00009888, .val = 0x1E328000 },
         { .reg = 0x00009888, .val = 0x1E330003 },
         { .reg = 0x00009888, .val = 0x185100F3 },
         { .reg = 0x00009888, .val = 0x1A5100F2 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x0C510000 },
         { .reg = 0x00009888, .val = 0x18528000 },
         { .reg = 0x00009888, .val = 0x1A528000 },
         { .reg = 0x00009888, .val = 0x1C53C000 },
         { .reg = 0x00009888, .val = 0x147100F3 },
         { .reg = 0x00009888, .val = 0x167100F2 },
         { .reg = 0x00009888, .val = 0x10710000 },
         { .reg = 0x00009888, .val = 0x0A710000 },
         { .reg = 0x00009888, .val = 0x14728000 },
         { .reg = 0x00009888, .val = 0x16728000 },
         { .reg = 0x00009888, .val = 0x1C733000 },
         { .reg = 0x00009888, .val = 0x109100F3 },
         { .reg = 0x00009888, .val = 0x129100F2 },
         { .reg = 0x00009888, .val = 0x08910000 },
         { .reg = 0x00009888, .val = 0x10928000 },
         { .reg = 0x00009888, .val = 0x12928000 },
         { .reg = 0x00009888, .val = 0x1C930C00 },
         { .reg = 0x00009888, .val = 0x00B100F3 },
         { .reg = 0x00009888, .val = 0x0EB100F2 },
         { .reg = 0x00009888, .val = 0x06B10104 },
         { .reg = 0x00009888, .val = 0x08B10105 },
         { .reg = 0x00009888, .val = 0x0AB10106 },
         { .reg = 0x00009888, .val = 0x0CB10107 },
         { .reg = 0x00009888, .val = 0x10B10000 },
         { .reg = 0x00009888, .val = 0x02B10000 },
         { .reg = 0x00009888, .val = 0x04B10000 },
         { .reg = 0x00009888, .val = 0x00B28000 },
         { .reg = 0x00009888, .val = 0x0EB28000 },
         { .reg = 0x00009888, .val = 0x06B28000 },
         { .reg = 0x00009888, .val = 0x08B28000 },
         { .reg = 0x00009888, .val = 0x0AB28000 },
         { .reg = 0x00009888, .val = 0x0CB28000 },
         { .reg = 0x00009888, .val = 0x10B38000 },
         { .reg = 0x00009888, .val = 0x1CB30300 },
         { .reg = 0x00009888, .val = 0x16B38000 },
         { .reg = 0x00009888, .val = 0x18B38000 },
         { .reg = 0x00009888, .val = 0x1AB38000 },
         { .reg = 0x00009888, .val = 0x1E0F0028 },
         { .reg = 0x00009888, .val = 0x14104000 },
         { .reg = 0x00009888, .val = 0x16104000 },
         { .reg = 0x00009888, .val = 0x2C024000 },
         { .reg = 0x00009888, .val = 0x2E020001 },
         { .reg = 0x00009888, .val = 0x2A03A500 },
         { .reg = 0x00009888, .val = 0x18002000 },
         { .reg = 0x00009888, .val = 0x36003249 },
         { .reg = 0x00009888, .val = 0x380024DB },
         { .reg = 0x00009888, .val = 0x1A004000 },
         { .reg = 0x00009888, .val = 0x1C004000 },
         { .reg = 0x00009888, .val = 0x1E002000 },
         { .reg = 0x00009888, .val = 0x34000900 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x1C012000 },
         { .reg = 0x00009888, .val = 0x1E012000 },
         { .reg = 0x00009888, .val = 0x06014000 },
         { .reg = 0x00009888, .val = 0x08014000 },
         { .reg = 0x00009888, .val = 0x0A014000 },
         { .reg = 0x00009888, .val = 0x18012000 },
         { .reg = 0x00009888, .val = 0x2405C000 },
         { .reg = 0x00009888, .val = 0x26050003 },
         { .reg = 0x00009888, .val = 0x220500A0 },
         { .reg = 0x00009888, .val = 0x24062800 },
         { .reg = 0x00009888, .val = 0x140A8000 },
         { .reg = 0x00009888, .val = 0x160A8000 },
         { .reg = 0x00009888, .val = 0x180A8000 },
         { .reg = 0x00009888, .val = 0x1A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x41104000 },
         { .reg = 0x00009888, .val = 0x5B105555 },
         { .reg = 0x00009888, .val = 0x5D101555 },
         { .reg = 0x00009888, .val = 0x17144000 },
         { .reg = 0x00009888, .val = 0x1D14AAAA },
         { .reg = 0x00009888, .val = 0x1F14002A },
         { .reg = 0x00009888, .val = 0x1B14AA00 },
         { .reg = 0x00009888, .val = 0x01124000 },
         { .reg = 0x00009888, .val = 0x0F124000 },
         { .reg = 0x00009888, .val = 0x11124000 },
         { .reg = 0x00009888, .val = 0x13124000 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x19124000 },
         { .reg = 0x00009888, .val = 0x1B124000 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x47100600 },
         { .reg = 0x00009888, .val = 0x4D100606 },
         { .reg = 0x00009888, .val = 0x4F100606 },
         { .reg = 0x00009888, .val = 0x51100006 },
         { .reg = 0x00009888, .val = 0x53100400 },
         { .reg = 0x00009888, .val = 0x55100804 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100008 },
         { .reg = 0x00009888, .val = 0x49100808 },
         { .reg = 0x00009888, .val = 0x4B100606 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000DC00, .val = 0x00000000 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC08, .val = 0x00000000 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000DC10, .val = 0x00000000 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000DC18, .val = 0x00000000 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000DC20, .val = 0x00000000 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000DC28, .val = 0x00000000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00078000 },
         { .reg = 0x0000D974, .val = 0x00000FFF },
         { .reg = 0x0000DC30, .val = 0x00078000 },
         { .reg = 0x0000DC34, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__tdl_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__tdl_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__tdl_2__avg_gpu_core_frequency__max,adl__tdl_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__tdl_2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__tdl_2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__tdl_2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__tdl_2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__tdl_2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__tdl_2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__tdl_2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__tdl_2__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__tdl_2__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__tdl_2__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 454, 92, percentage_max_float,adl__tdl_2__ps_thread00_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 2) {
         intel_perf_query_add_counter_float(query, 455, 96, percentage_max_float,adl__tdl_2__ps_thread01_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 514, 100, percentage_max_float,adl__tdl_2__ps_thread02_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 515, 104, percentage_max_float,adl__tdl_2__ps_thread03_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 516, 108, percentage_max_float,adl__tdl_2__ps_thread04_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 517, 112, percentage_max_float,adl__tdl_2__ps_thread05_ready_for_dispatch__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 518, 116, percentage_max_float,adl__tdl_2__thread_header05_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 519, 120, percentage_max_float,adl__tdl_2__thread_header05_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 520, 124, percentage_max_float,adl__tdl_2__thread_header05_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 521, 128, percentage_max_float,adl__tdl_2__thread_header05_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 32) {
         intel_perf_query_add_counter_float(query, 522, 132, percentage_max_float,adl__tdl_2__thread_header05_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_tdl_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 28);

   query->name = "TDL_3";
   query->symbol_name = "TDL_3";
   query->guid = "0348b595-94ef-445f-b4e5-11d0076b6307";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2651001C },
         { .reg = 0x00009888, .val = 0x2671001C },
         { .reg = 0x00009888, .val = 0x2691001C },
         { .reg = 0x00009888, .val = 0x24072A80 },
         { .reg = 0x00009888, .val = 0x06510107 },
         { .reg = 0x00009888, .val = 0x08510106 },
         { .reg = 0x00009888, .val = 0x0A510105 },
         { .reg = 0x00009888, .val = 0x0C510104 },
         { .reg = 0x00009888, .val = 0x10510000 },
         { .reg = 0x00009888, .val = 0x02510000 },
         { .reg = 0x00009888, .val = 0x04510000 },
         { .reg = 0x00009888, .val = 0x06528000 },
         { .reg = 0x00009888, .val = 0x08528000 },
         { .reg = 0x00009888, .val = 0x0A528000 },
         { .reg = 0x00009888, .val = 0x0C528000 },
         { .reg = 0x00009888, .val = 0x16538000 },
         { .reg = 0x00009888, .val = 0x18538000 },
         { .reg = 0x00009888, .val = 0x1A538000 },
         { .reg = 0x00009888, .val = 0x1C530100 },
         { .reg = 0x00009888, .val = 0x1C710107 },
         { .reg = 0x00009888, .val = 0x1E710106 },
         { .reg = 0x00009888, .val = 0x02710105 },
         { .reg = 0x00009888, .val = 0x04710104 },
         { .reg = 0x00009888, .val = 0x10710000 },
         { .reg = 0x00009888, .val = 0x0E710000 },
         { .reg = 0x00009888, .val = 0x00710000 },
         { .reg = 0x00009888, .val = 0x1C728000 },
         { .reg = 0x00009888, .val = 0x1E728000 },
         { .reg = 0x00009888, .val = 0x02728000 },
         { .reg = 0x00009888, .val = 0x04728000 },
         { .reg = 0x00009888, .val = 0x1E730003 },
         { .reg = 0x00009888, .val = 0x12738000 },
         { .reg = 0x00009888, .val = 0x14738000 },
         { .reg = 0x00009888, .val = 0x14910107 },
         { .reg = 0x00009888, .val = 0x16910106 },
         { .reg = 0x00009888, .val = 0x18910105 },
         { .reg = 0x00009888, .val = 0x1A910104 },
         { .reg = 0x00009888, .val = 0x10910000 },
         { .reg = 0x00009888, .val = 0x0A910000 },
         { .reg = 0x00009888, .val = 0x0C910000 },
         { .reg = 0x00009888, .val = 0x14928000 },
         { .reg = 0x00009888, .val = 0x16928000 },
         { .reg = 0x00009888, .val = 0x18928000 },
         { .reg = 0x00009888, .val = 0x1A928000 },
         { .reg = 0x00009888, .val = 0x1C93F000 },
         { .reg = 0x00009888, .val = 0x1E0F2800 },
         { .reg = 0x00009888, .val = 0x1C0F000A },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x02104000 },
         { .reg = 0x00009888, .val = 0x04104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x02034000 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x06038000 },
         { .reg = 0x00009888, .val = 0x08038000 },
         { .reg = 0x00009888, .val = 0x0A038000 },
         { .reg = 0x00009888, .val = 0x18034000 },
         { .reg = 0x00009888, .val = 0x36001003 },
         { .reg = 0x00009888, .val = 0x38003649 },
         { .reg = 0x00009888, .val = 0x1A006000 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x1E006000 },
         { .reg = 0x00009888, .val = 0x34001B00 },
         { .reg = 0x00009888, .val = 0x2A015500 },
         { .reg = 0x00009888, .val = 0x2206AA00 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009888, .val = 0x020A8000 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x060A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009888, .val = 0x0C0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x5D101554 },
         { .reg = 0x00009888, .val = 0x5B100555 },
         { .reg = 0x00009888, .val = 0x1D14A80A },
         { .reg = 0x00009888, .val = 0x1F14002A },
         { .reg = 0x00009888, .val = 0x1B14AA00 },
         { .reg = 0x00009888, .val = 0x15124000 },
         { .reg = 0x00009888, .val = 0x17124000 },
         { .reg = 0x00009888, .val = 0x19124000 },
         { .reg = 0x00009888, .val = 0x1B124000 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x03124000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x07124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D124000 },
         { .reg = 0x00009888, .val = 0x51100600 },
         { .reg = 0x00009888, .val = 0x53100606 },
         { .reg = 0x00009888, .val = 0x55100006 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49100000 },
         { .reg = 0x00009888, .val = 0x4B100404 },
         { .reg = 0x00009888, .val = 0x4D100404 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00070000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000DC00, .val = 0x00078000 },
         { .reg = 0x0000DC04, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000DC08, .val = 0x00007800 },
         { .reg = 0x0000DC0C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000DC10, .val = 0x00000780 },
         { .reg = 0x0000DC14, .val = 0x0000FF0F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__tdl_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__tdl_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__tdl_3__avg_gpu_core_frequency__max,adl__tdl_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__tdl_3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__tdl_3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__tdl_3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__tdl_3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__tdl_3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__tdl_3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__tdl_3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 10, 80, percentage_max_float,adl__tdl_3__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 84, percentage_max_float,adl__tdl_3__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 88, percentage_max_float,adl__tdl_3__eu_thread_occupancy__read);

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 523, 92, percentage_max_float,adl__tdl_3__thread_header02_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 524, 96, percentage_max_float,adl__tdl_3__thread_header03_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 525, 100, percentage_max_float,adl__tdl_3__thread_header04_ready__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 526, 104, percentage_max_float,adl__tdl_3__thread_header02_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 527, 108, percentage_max_float,adl__tdl_3__thread_header02_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 528, 112, percentage_max_float,adl__tdl_3__thread_header02_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 4) {
         intel_perf_query_add_counter_float(query, 529, 116, percentage_max_float,adl__tdl_3__thread_header02_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 530, 120, percentage_max_float,adl__tdl_3__thread_header03_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 531, 124, percentage_max_float,adl__tdl_3__thread_header03_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 532, 128, percentage_max_float,adl__tdl_3__thread_header03_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 8) {
         intel_perf_query_add_counter_float(query, 533, 132, percentage_max_float,adl__tdl_3__thread_header03_ready_port3__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 534, 136, percentage_max_float,adl__tdl_3__thread_header04_ready_port0__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 535, 140, percentage_max_float,adl__tdl_3__thread_header04_ready_port1__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 536, 144, percentage_max_float,adl__tdl_3__thread_header04_ready_port2__read);
      }

      if (perf->sys_vars.subslice_mask & 16) {
         intel_perf_query_add_counter_float(query, 537, 148, percentage_max_float,adl__tdl_3__thread_header04_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 22);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "67577936-ac11-46a1-b07d-44ea1318df5b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x0E101200 },
         { .reg = 0x00009888, .val = 0x040E0043 },
         { .reg = 0x00009888, .val = 0x0A0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x0C0E0000 },
         { .reg = 0x00009888, .val = 0x1C0F0104 },
         { .reg = 0x00009888, .val = 0x08100053 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x04104000 },
         { .reg = 0x00009888, .val = 0x0A104000 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08024000 },
         { .reg = 0x00009888, .val = 0x0A024000 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x08034000 },
         { .reg = 0x00009888, .val = 0x0A034000 },
         { .reg = 0x00009888, .val = 0x1C006000 },
         { .reg = 0x00009888, .val = 0x34001B00 },
         { .reg = 0x00009888, .val = 0x040A8000 },
         { .reg = 0x00009888, .val = 0x080A8000 },
         { .reg = 0x00009888, .val = 0x0A0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x15102400 },
         { .reg = 0x00009888, .val = 0x23010120 },
         { .reg = 0x00009888, .val = 0x15182400 },
         { .reg = 0x00009888, .val = 0x23210120 },
         { .reg = 0x00009888, .val = 0x17100023 },
         { .reg = 0x00009888, .val = 0x11100000 },
         { .reg = 0x00009888, .val = 0x5D101000 },
         { .reg = 0x00009888, .val = 0x5B100545 },
         { .reg = 0x00009888, .val = 0x1B148800 },
         { .reg = 0x00009888, .val = 0x1D140002 },
         { .reg = 0x00009888, .val = 0x61112000 },
         { .reg = 0x00009888, .val = 0x5F110401 },
         { .reg = 0x00009888, .val = 0x1F128000 },
         { .reg = 0x00009888, .val = 0x03128000 },
         { .reg = 0x00009888, .val = 0x05124000 },
         { .reg = 0x00009888, .val = 0x09124000 },
         { .reg = 0x00009888, .val = 0x0B124000 },
         { .reg = 0x00009888, .val = 0x0D128000 },
         { .reg = 0x00009888, .val = 0x01008000 },
         { .reg = 0x00009888, .val = 0x13028000 },
         { .reg = 0x00009888, .val = 0x030100D3 },
         { .reg = 0x00009888, .val = 0x21010000 },
         { .reg = 0x00009888, .val = 0x071800A3 },
         { .reg = 0x00009888, .val = 0x11180000 },
         { .reg = 0x00009888, .val = 0x21180400 },
         { .reg = 0x00009888, .val = 0x23180000 },
         { .reg = 0x00009888, .val = 0x0F208000 },
         { .reg = 0x00009888, .val = 0x21222000 },
         { .reg = 0x00009888, .val = 0x1F2100D3 },
         { .reg = 0x00009888, .val = 0x21210000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47100000 },
         { .reg = 0x00009888, .val = 0x49101007 },
         { .reg = 0x00009888, .val = 0x4B10040A },
         { .reg = 0x00009888, .val = 0x4D100210 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00030000 },
         { .reg = 0x0000D940, .val = 0x00024002 },
         { .reg = 0x0000D944, .val = 0x0000B7FF },
         { .reg = 0x0000DC00, .val = 0x00024002 },
         { .reg = 0x0000DC04, .val = 0x0000B7FF },
         { .reg = 0x0000D948, .val = 0x0007F000 },
         { .reg = 0x0000D94C, .val = 0x000001FF },
         { .reg = 0x0000DC08, .val = 0x0007F000 },
         { .reg = 0x0000DC0C, .val = 0x000001FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00804704 },
         { .reg = 0x0000E558, .val = 0x00A04904 },
         { .reg = 0x0000E658, .val = 0x00805705 },
         { .reg = 0x0000E758, .val = 0x00A05905 },
         { .reg = 0x0000E45C, .val = 0x00808708 },
         { .reg = 0x0000E55C, .val = 0x00A08908 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__gpu_busyness__avg_gpu_core_frequency__max,adl__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 10, 28, percentage_max_float,adl__gpu_busyness__eu_active__read);

      intel_perf_query_add_counter_float(query, 11, 32, percentage_max_float,adl__gpu_busyness__eu_stall__read);

      intel_perf_query_add_counter_float(query, 154, 36, percentage_max_float,adl__gpu_busyness__eu_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,adl__gpu_busyness__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,adl__gpu_busyness__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,adl__gpu_busyness__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,adl__gpu_busyness__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,adl__gpu_busyness__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,adl__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 88, percentage_max_float,adl__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 92, percentage_max_float,adl__gpu_busyness__compute_busy__read);

      intel_perf_query_add_counter_float(query, 414, 96, percentage_max_float,adl__gpu_busyness__posh_engine_busy__read);

      intel_perf_query_add_counter_float(query, 313, 100, percentage_max_float,adl__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 312, 104, percentage_max_float,adl__gpu_busyness__vebox_busy__read);

      intel_perf_query_add_counter_float(query, 310, 108, percentage_max_float,adl__gpu_busyness__vdbox0_busy__read);

      intel_perf_query_add_counter_float(query, 311, 112, percentage_max_float,adl__gpu_busyness__vdbox1_busy__read);

      intel_perf_query_add_counter_float(query, 467, 116, percentage_max_float,adl__gpu_busyness__render_and_compute_busy__read);

      intel_perf_query_add_counter_float(query, 468, 120, percentage_max_float,adl__gpu_busyness__any_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_eu_activity1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity1";
   query->symbol_name = "EuActivity1";
   query->guid = "b1c1cb56-f82f-444e-b408-aebbe4777f40";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1F140028 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101616 },
         { .reg = 0x00009888, .val = 0x4B101616 },
         { .reg = 0x00009888, .val = 0x4D100616 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00810710 },
         { .reg = 0x0000E558, .val = 0x00A10910 },
         { .reg = 0x0000E658, .val = 0x00850750 },
         { .reg = 0x0000E758, .val = 0x00A50950 },
         { .reg = 0x0000E45C, .val = 0x00802702 },
         { .reg = 0x0000E55C, .val = 0x00A02902 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__eu_activity1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__eu_activity1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__eu_activity1__avg_gpu_core_frequency__max,adl__eu_activity1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__eu_activity1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__eu_activity1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__eu_activity1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__eu_activity1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__eu_activity1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__eu_activity1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__eu_activity1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,adl__eu_activity1__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,adl__eu_activity1__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,adl__eu_activity1__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, adl__eu_activity1__gti_read_throughput__max,adl__eu_activity1__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, adl__eu_activity1__gti_write_throughput__max,adl__eu_activity1__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 469, 112, percentage_max_float,adl__eu_activity1__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 470, 116, percentage_max_float,adl__eu_activity1__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 153, 120, percentage_max_float,adl__eu_activity1__eu_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_eu_activity2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity2";
   query->symbol_name = "EuActivity2";
   query->guid = "b45c7714-75be-4639-83b8-258392695044";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1F140028 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101616 },
         { .reg = 0x00009888, .val = 0x4B101616 },
         { .reg = 0x00009888, .val = 0x4D100616 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00862762 },
         { .reg = 0x0000E558, .val = 0x00A62962 },
         { .reg = 0x0000E658, .val = 0x00860760 },
         { .reg = 0x0000E758, .val = 0x00A60960 },
         { .reg = 0x0000E45C, .val = 0x00861761 },
         { .reg = 0x0000E55C, .val = 0x00A61961 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__eu_activity2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__eu_activity2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__eu_activity2__avg_gpu_core_frequency__max,adl__eu_activity2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__eu_activity2__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__eu_activity2__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__eu_activity2__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__eu_activity2__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__eu_activity2__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__eu_activity2__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__eu_activity2__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,adl__eu_activity2__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,adl__eu_activity2__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,adl__eu_activity2__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, adl__eu_activity2__gti_read_throughput__max,adl__eu_activity2__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, adl__eu_activity2__gti_write_throughput__max,adl__eu_activity2__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 471, 112, percentage_max_float,adl__eu_activity2__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 472, 116, percentage_max_float,adl__eu_activity2__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 473, 120, percentage_max_float,adl__eu_activity2__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_eu_activity3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity3";
   query->symbol_name = "EuActivity3";
   query->guid = "e63fc92b-0c14-48b8-b832-52631f75b1c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1F140028 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101616 },
         { .reg = 0x00009888, .val = 0x4B101616 },
         { .reg = 0x00009888, .val = 0x4D100616 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00811711 },
         { .reg = 0x0000E558, .val = 0x00A11911 },
         { .reg = 0x0000E658, .val = 0x00851751 },
         { .reg = 0x0000E758, .val = 0x00A51951 },
         { .reg = 0x0000E45C, .val = 0x00852752 },
         { .reg = 0x0000E55C, .val = 0x00A52952 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__eu_activity3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__eu_activity3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__eu_activity3__avg_gpu_core_frequency__max,adl__eu_activity3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__eu_activity3__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__eu_activity3__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__eu_activity3__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__eu_activity3__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__eu_activity3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__eu_activity3__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__eu_activity3__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,adl__eu_activity3__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,adl__eu_activity3__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,adl__eu_activity3__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, adl__eu_activity3__gti_read_throughput__max,adl__eu_activity3__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, adl__eu_activity3__gti_write_throughput__max,adl__eu_activity3__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 474, 112, percentage_max_float,adl__eu_activity3__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 475, 116, percentage_max_float,adl__eu_activity3__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 129, 120, percentage_max_float,adl__eu_activity3__ps_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_eu_activity4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity4";
   query->symbol_name = "EuActivity4";
   query->guid = "a5bd7cc2-3b17-4287-bdb2-a6814998daa1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1F140028 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101616 },
         { .reg = 0x00009888, .val = 0x4B101616 },
         { .reg = 0x00009888, .val = 0x4D100616 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00820720 },
         { .reg = 0x0000E558, .val = 0x00A20920 },
         { .reg = 0x0000E658, .val = 0x00830730 },
         { .reg = 0x0000E758, .val = 0x00A30930 },
         { .reg = 0x0000E45C, .val = 0x00812712 },
         { .reg = 0x0000E55C, .val = 0x00A12912 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__eu_activity4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__eu_activity4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__eu_activity4__avg_gpu_core_frequency__max,adl__eu_activity4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__eu_activity4__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__eu_activity4__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__eu_activity4__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__eu_activity4__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__eu_activity4__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__eu_activity4__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__eu_activity4__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,adl__eu_activity4__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,adl__eu_activity4__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,adl__eu_activity4__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, adl__eu_activity4__gti_read_throughput__max,adl__eu_activity4__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, adl__eu_activity4__gti_write_throughput__max,adl__eu_activity4__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 476, 112, percentage_max_float,adl__eu_activity4__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 477, 116, percentage_max_float,adl__eu_activity4__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 126, 120, percentage_max_float,adl__eu_activity4__vs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_eu_activity5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity5";
   query->symbol_name = "EuActivity5";
   query->guid = "036c9033-142d-438f-a5ec-ea0ec62a6f43";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1F140028 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101616 },
         { .reg = 0x00009888, .val = 0x4B101616 },
         { .reg = 0x00009888, .val = 0x4D100616 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00821721 },
         { .reg = 0x0000E558, .val = 0x00A21921 },
         { .reg = 0x0000E658, .val = 0x00831731 },
         { .reg = 0x0000E758, .val = 0x00A31931 },
         { .reg = 0x0000E45C, .val = 0x00822722 },
         { .reg = 0x0000E55C, .val = 0x00A22922 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__eu_activity5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__eu_activity5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__eu_activity5__avg_gpu_core_frequency__max,adl__eu_activity5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__eu_activity5__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__eu_activity5__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__eu_activity5__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__eu_activity5__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__eu_activity5__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__eu_activity5__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__eu_activity5__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,adl__eu_activity5__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,adl__eu_activity5__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,adl__eu_activity5__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, adl__eu_activity5__gti_read_throughput__max,adl__eu_activity5__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, adl__eu_activity5__gti_write_throughput__max,adl__eu_activity5__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 478, 112, percentage_max_float,adl__eu_activity5__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 479, 116, percentage_max_float,adl__eu_activity5__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 480, 120, percentage_max_float,adl__eu_activity5__hs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_eu_activity6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "EuActivity6";
   query->symbol_name = "EuActivity6";
   query->guid = "fbba3669-b6db-4aa8-a993-b2e51998a8dd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1F140028 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101616 },
         { .reg = 0x00009888, .val = 0x4B101616 },
         { .reg = 0x00009888, .val = 0x4D100616 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00840740 },
         { .reg = 0x0000E558, .val = 0x00A40940 },
         { .reg = 0x0000E658, .val = 0x00841741 },
         { .reg = 0x0000E758, .val = 0x00A41941 },
         { .reg = 0x0000E45C, .val = 0x00842742 },
         { .reg = 0x0000E55C, .val = 0x00A42942 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__eu_activity6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__eu_activity6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__eu_activity6__avg_gpu_core_frequency__max,adl__eu_activity6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__eu_activity6__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__eu_activity6__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__eu_activity6__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__eu_activity6__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__eu_activity6__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__eu_activity6__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__eu_activity6__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,adl__eu_activity6__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,adl__eu_activity6__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,adl__eu_activity6__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, adl__eu_activity6__gti_read_throughput__max,adl__eu_activity6__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, adl__eu_activity6__gti_write_throughput__max,adl__eu_activity6__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 481, 112, percentage_max_float,adl__eu_activity6__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 482, 116, percentage_max_float,adl__eu_activity6__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 483, 120, percentage_max_float,adl__eu_activity6__gs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_eu_activity7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "EuActivity7";
   query->symbol_name = "EuActivity7";
   query->guid = "c3ea2a23-f1c7-4a19-9da2-b569226fb6de";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1F140028 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101616 },
         { .reg = 0x00009888, .val = 0x4B101616 },
         { .reg = 0x00009888, .val = 0x4D100616 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00803703 },
         { .reg = 0x0000E558, .val = 0x00A03903 },
         { .reg = 0x0000E658, .val = 0x00800700 },
         { .reg = 0x0000E758, .val = 0x00A00900 },
         { .reg = 0x0000E45C, .val = 0x00801701 },
         { .reg = 0x0000E55C, .val = 0x00A01901 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__eu_activity7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__eu_activity7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__eu_activity7__avg_gpu_core_frequency__max,adl__eu_activity7__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__eu_activity7__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__eu_activity7__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__eu_activity7__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__eu_activity7__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__eu_activity7__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__eu_activity7__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__eu_activity7__cs_threads__read);

      intel_perf_query_add_counter_float(query, 484, 80, percentage_max_float,adl__eu_activity7__fpu_active__read);

      intel_perf_query_add_counter_float(query, 485, 84, percentage_max_float,adl__eu_activity7__em_active__read);

      intel_perf_query_add_counter_float(query, 486, 88, percentage_max_float,adl__eu_activity7__eu_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 152, 92, adl__eu_activity7__eu_avg_ipc_rate__max,adl__eu_activity7__eu_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 309, 96, percentage_max_float,adl__eu_activity7__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 100, percentage_max_float,adl__eu_activity7__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 104, percentage_max_float,adl__eu_activity7__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 112, adl__eu_activity7__gti_read_throughput__max,adl__eu_activity7__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 120, adl__eu_activity7__gti_write_throughput__max,adl__eu_activity7__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_eu_activity8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 16);

   query->name = "EuActivity8";
   query->symbol_name = "EuActivity8";
   query->guid = "a5e2f79b-cecb-4eff-8f29-cda8e2a58749";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E1200 },
         { .reg = 0x00009888, .val = 0x220E0009 },
         { .reg = 0x00009888, .val = 0x1C0E0043 },
         { .reg = 0x00009888, .val = 0x1E0E00B3 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1400 },
         { .reg = 0x00009888, .val = 0x1C104000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020140 },
         { .reg = 0x00009888, .val = 0x2C030005 },
         { .reg = 0x00009888, .val = 0x38003600 },
         { .reg = 0x00009888, .val = 0x1C0A8000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x05151D37 },
         { .reg = 0x00009888, .val = 0x09151547 },
         { .reg = 0x00009888, .val = 0x05351C00 },
         { .reg = 0x00009888, .val = 0x09351400 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x5B100BBB },
         { .reg = 0x00009888, .val = 0x1F140028 },
         { .reg = 0x00009888, .val = 0x1D124000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x0D150136 },
         { .reg = 0x00009888, .val = 0x01150000 },
         { .reg = 0x00009888, .val = 0x03164000 },
         { .reg = 0x00009888, .val = 0x05164000 },
         { .reg = 0x00009888, .val = 0x07164000 },
         { .reg = 0x00009888, .val = 0x03350137 },
         { .reg = 0x00009888, .val = 0x07350147 },
         { .reg = 0x00009888, .val = 0x0B350136 },
         { .reg = 0x00009888, .val = 0x01350000 },
         { .reg = 0x00009888, .val = 0x01368000 },
         { .reg = 0x00009888, .val = 0x03368000 },
         { .reg = 0x00009888, .val = 0x05368000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100000 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x47101000 },
         { .reg = 0x00009888, .val = 0x49101616 },
         { .reg = 0x00009888, .val = 0x4B101616 },
         { .reg = 0x00009888, .val = 0x4D100616 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000DC40, .val = 0x00010000 },
         { .reg = 0x0000D940, .val = 0x00001802 },
         { .reg = 0x0000D944, .val = 0x0000FCFF },
         { .reg = 0x0000DC00, .val = 0x00001802 },
         { .reg = 0x0000DC04, .val = 0x0000FCFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00832732 },
         { .reg = 0x0000E558, .val = 0x00A32932 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__eu_activity8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__eu_activity8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__eu_activity8__avg_gpu_core_frequency__max,adl__eu_activity8__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,adl__eu_activity8__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,adl__eu_activity8__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,adl__eu_activity8__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,adl__eu_activity8__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,adl__eu_activity8__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,adl__eu_activity8__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,adl__eu_activity8__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 80, percentage_max_float,adl__eu_activity8__render_busy__read);

      intel_perf_query_add_counter_float(query, 466, 84, percentage_max_float,adl__eu_activity8__compute_busy__read);

      intel_perf_query_add_counter_float(query, 467, 88, percentage_max_float,adl__eu_activity8__render_and_compute_busy__read);

      intel_perf_query_add_counter_uint64(query, 57, 96, adl__eu_activity8__gti_read_throughput__max,adl__eu_activity8__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 104, adl__eu_activity8__gti_write_throughput__max,adl__eu_activity8__gti_write_throughput__read);

      intel_perf_query_add_counter_float(query, 487, 112, percentage_max_float,adl__eu_activity8__ds_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
adl_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "89173c19-fcfe-48da-ac26-fb64425f141b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009840, .val = 0x00000000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x280E0000 },
         { .reg = 0x00009888, .val = 0x1E0E0147 },
         { .reg = 0x00009888, .val = 0x180E0000 },
         { .reg = 0x00009888, .val = 0x160E0000 },
         { .reg = 0x00009888, .val = 0x1E0F1000 },
         { .reg = 0x00009888, .val = 0x1E104000 },
         { .reg = 0x00009888, .val = 0x2E020100 },
         { .reg = 0x00009888, .val = 0x2C030004 },
         { .reg = 0x00009888, .val = 0x38003000 },
         { .reg = 0x00009888, .val = 0x1E0A8000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x49110000 },
         { .reg = 0x00009888, .val = 0x5D101400 },
         { .reg = 0x00009888, .val = 0x1F140020 },
         { .reg = 0x00009888, .val = 0x1D1103B3 },
         { .reg = 0x00009888, .val = 0x01110000 },
         { .reg = 0x00009888, .val = 0x61110000 },
         { .reg = 0x00009888, .val = 0x1D128000 },
         { .reg = 0x00009888, .val = 0x1F124000 },
         { .reg = 0x00009888, .val = 0x17100000 },
         { .reg = 0x00009888, .val = 0x55100510 },
         { .reg = 0x00009888, .val = 0x57100000 },
         { .reg = 0x00009888, .val = 0x31100000 },
         { .reg = 0x00009884, .val = 0x00000003 },
         { .reg = 0x00009888, .val = 0x65100002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42000001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000DC00, .val = 0x00000004 },
         { .reg = 0x0000DC04, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000DC08, .val = 0x00000003 },
         { .reg = 0x0000DC0C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000DC10, .val = 0x00000007 },
         { .reg = 0x0000DC14, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000DC18, .val = 0x00100002 },
         { .reg = 0x0000DC1C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000DC20, .val = 0x00100002 },
         { .reg = 0x0000DC24, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000DC28, .val = 0x00100082 },
         { .reg = 0x0000DC2C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000DC30, .val = 0x001000C2 },
         { .reg = 0x0000DC34, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
         { .reg = 0x0000DC38, .val = 0x00100001 },
         { .reg = 0x0000DC3C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E65C, .val = 0xFFFFFFFF },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,adl__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,adl__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, adl__test_oa__avg_gpu_core_frequency__max,adl__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,adl__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,adl__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,adl__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,adl__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 415, 56, NULL,adl__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 416, 64, NULL,adl__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 417, 72, NULL,adl__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 418, 80, NULL,adl__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 488, 88, NULL,adl__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 489, 96, NULL,adl__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_adl(struct intel_perf_config *perf)
{
   adl_register_render_basic_counter_query(perf);
   adl_register_compute_basic_counter_query(perf);
   adl_register_render_pipe_profile_counter_query(perf);
   adl_register_hdc_and_sf_counter_query(perf);
   adl_register_rasterizer_and_pixel_backend_counter_query(perf);
   adl_register_l3_1_counter_query(perf);
   adl_register_l3_2_counter_query(perf);
   adl_register_l3_3_counter_query(perf);
   adl_register_l3_4_counter_query(perf);
   adl_register_l3_5_counter_query(perf);
   adl_register_l3_6_counter_query(perf);
   adl_register_sampler_1_counter_query(perf);
   adl_register_sampler_2_counter_query(perf);
   adl_register_tdl_1_counter_query(perf);
   adl_register_tdl_2_counter_query(perf);
   adl_register_tdl_3_counter_query(perf);
   adl_register_gpu_busyness_counter_query(perf);
   adl_register_eu_activity1_counter_query(perf);
   adl_register_eu_activity2_counter_query(perf);
   adl_register_eu_activity3_counter_query(perf);
   adl_register_eu_activity4_counter_query(perf);
   adl_register_eu_activity5_counter_query(perf);
   adl_register_eu_activity6_counter_query(perf);
   adl_register_eu_activity7_counter_query(perf);
   adl_register_eu_activity8_counter_query(perf);
   adl_register_test_oa_counter_query(perf);
}


static void
acmgt1_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 30);

   query->name = "Render Metrics Basic - aggregation approximation";
   query->symbol_name = "RenderBasic";
   query->guid = "f5b8f05e-c84c-4f1c-bb05-68fbea73879b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C840000 },
         { .reg = 0x00009888, .val = 0x1E842800 },
         { .reg = 0x00009888, .val = 0x02844000 },
         { .reg = 0x00009888, .val = 0x04840010 },
         { .reg = 0x00009888, .val = 0x10840800 },
         { .reg = 0x00009888, .val = 0x12840037 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x02860500 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009888, .val = 0x020A0500 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x02410006 },
         { .reg = 0x00009888, .val = 0x14410100 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610006 },
         { .reg = 0x00009888, .val = 0x16610004 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00043000 },
         { .reg = 0x00009888, .val = 0x02020A00 },
         { .reg = 0x00009888, .val = 0x0203F500 },
         { .reg = 0x00009888, .val = 0x0209E000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C60 },
         { .reg = 0x00009888, .val = 0x2403F000 },
         { .reg = 0x00009888, .val = 0x2803F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x02050500 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00003008 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__render_basic__avg_gpu_core_frequency__max,acmgt1__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 539, 24, NULL,acmgt1__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 540, 32, percentage_max_float,acmgt1__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 541, 36, percentage_max_float,acmgt1__render_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 40, percentage_max_float,acmgt1__render_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 543, 44, percentage_max_float,acmgt1__render_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 544, 48, percentage_max_float,acmgt1__render_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 545, 52, percentage_max_float,acmgt1__render_basic__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 546, 56, percentage_max_float,acmgt1__render_basic__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 547, 60, percentage_max_float,acmgt1__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 548, 64, percentage_max_float,acmgt1__render_basic__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 549, 68, percentage_max_float,acmgt1__render_basic__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 550, 72, percentage_max_float,acmgt1__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_uint64(query, 551, 80, NULL,acmgt1__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 552, 88, NULL,acmgt1__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 553, 96, NULL,acmgt1__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 554, 104, NULL,acmgt1__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 555, 112, acmgt1__render_basic__slm_reads__max,acmgt1__render_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 556, 120, acmgt1__render_basic__slm_writes__max,acmgt1__render_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 557, 128, NULL,acmgt1__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 558, 136, NULL,acmgt1__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 559, 144, NULL,acmgt1__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 560, 152, acmgt1__render_basic__gti_read_throughput__max,acmgt1__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 561, 160, acmgt1__render_basic__gti_write_throughput__max,acmgt1__render_basic__gti_write_throughput__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 562, 168, percentage_max_float,acmgt1__render_basic__sampler20_busy__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 563, 172, percentage_max_float,acmgt1__render_basic__samplers_busy__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 564, 176, percentage_max_float,acmgt1__render_basic__sampler20_bottleneck__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 565, 180, percentage_max_float,acmgt1__render_basic__sampler_bottleneck__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 25);

   query->name = "Compute Metrics Basic";
   query->symbol_name = "ComputeBasic";
   query->guid = "53ee6271-905c-4b2a-b449-9117ffd10a48";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x02410006 },
         { .reg = 0x00009888, .val = 0x16410004 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610006 },
         { .reg = 0x00009888, .val = 0x14610100 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0203F000 },
         { .reg = 0x00009888, .val = 0x0209B000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00003009 },
         { .reg = 0x0000E758, .val = 0x0000200A },
         { .reg = 0x0000E45C, .val = 0x00006008 },
         { .reg = 0x0000E55C, .val = 0x0000B007 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__compute_basic__avg_gpu_core_frequency__max,acmgt1__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 539, 32, NULL,acmgt1__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 541, 40, percentage_max_float,acmgt1__compute_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 44, percentage_max_float,acmgt1__compute_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 566, 48, percentage_max_float,acmgt1__compute_basic__fpu_active__read);

      intel_perf_query_add_counter_float(query, 567, 52, percentage_max_float,acmgt1__compute_basic__em_active__read);

      intel_perf_query_add_counter_float(query, 568, 56, percentage_max_float,acmgt1__compute_basic__xmx_active__read);

      intel_perf_query_add_counter_float(query, 544, 60, percentage_max_float,acmgt1__compute_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 569, 64, percentage_max_float,acmgt1__compute_basic__xve_fpu_xmx_active__read);

      intel_perf_query_add_counter_float(query, 570, 68, acmgt1__compute_basic__xve_avg_ipc_rate__max,acmgt1__compute_basic__xve_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 571, 72, percentage_max_float,acmgt1__compute_basic__send_active__read);

      intel_perf_query_add_counter_float(query, 543, 76, percentage_max_float,acmgt1__compute_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 572, 80, percentage_max_float,acmgt1__compute_basic__xve_fpu_flt16__read);

      intel_perf_query_add_counter_float(query, 573, 84, percentage_max_float,acmgt1__compute_basic__xve_fpu_flt32__read);

      intel_perf_query_add_counter_float(query, 574, 88, percentage_max_float,acmgt1__compute_basic__xve_fpu_flt64__read);

      intel_perf_query_add_counter_uint64(query, 555, 96, acmgt1__compute_basic__slm_reads__max,acmgt1__compute_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 556, 104, acmgt1__compute_basic__slm_writes__max,acmgt1__compute_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 557, 112, NULL,acmgt1__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 558, 120, NULL,acmgt1__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 559, 128, NULL,acmgt1__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 560, 136, acmgt1__compute_basic__gti_read_throughput__max,acmgt1__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 561, 144, acmgt1__compute_basic__gti_write_throughput__max,acmgt1__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_threads_and_rast1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadsAndRast1";
   query->symbol_name = "ThreadsAndRast1";
   query->guid = "952f5f55-449d-43db-87d7-6113e9c3b89a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x24817800 },
         { .reg = 0x00009888, .val = 0x28810000 },
         { .reg = 0x00009888, .val = 0x2A810001 },
         { .reg = 0x00009888, .val = 0x24A17800 },
         { .reg = 0x00009888, .val = 0x28A10000 },
         { .reg = 0x00009888, .val = 0x2AA10001 },
         { .reg = 0x00009888, .val = 0x24C17800 },
         { .reg = 0x00009888, .val = 0x28C10000 },
         { .reg = 0x00009888, .val = 0x2AC10001 },
         { .reg = 0x00009888, .val = 0x24E17800 },
         { .reg = 0x00009888, .val = 0x28E10000 },
         { .reg = 0x00009888, .val = 0x2AE10001 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A2800 },
         { .reg = 0x00009888, .val = 0x190A2800 },
         { .reg = 0x00009888, .val = 0x1E0A4003 },
         { .reg = 0x00009888, .val = 0x1F0A4003 },
         { .reg = 0x00009888, .val = 0x200A0060 },
         { .reg = 0x00009888, .val = 0x210A0060 },
         { .reg = 0x00009888, .val = 0x220A0028 },
         { .reg = 0x00009888, .val = 0x230A0028 },
         { .reg = 0x00009888, .val = 0x240A0023 },
         { .reg = 0x00009888, .val = 0x250A0023 },
         { .reg = 0x00009888, .val = 0x260A000A },
         { .reg = 0x00009888, .val = 0x270A000A },
         { .reg = 0x00009888, .val = 0x1A0A008C },
         { .reg = 0x00009888, .val = 0x1B0A008C },
         { .reg = 0x00009888, .val = 0x1C0A400A },
         { .reg = 0x00009888, .val = 0x1D0A400A },
         { .reg = 0x00009888, .val = 0x06813106 },
         { .reg = 0x00009888, .val = 0x0A810D00 },
         { .reg = 0x00009888, .val = 0x0E810D40 },
         { .reg = 0x00009888, .val = 0x12810980 },
         { .reg = 0x00009888, .val = 0x16810F80 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00838080 },
         { .reg = 0x00009888, .val = 0x02838080 },
         { .reg = 0x00009888, .val = 0x00848888 },
         { .reg = 0x00009888, .val = 0x00864040 },
         { .reg = 0x00009888, .val = 0x02864040 },
         { .reg = 0x00009888, .val = 0x00874040 },
         { .reg = 0x00009888, .val = 0x02874040 },
         { .reg = 0x00009888, .val = 0x06A13106 },
         { .reg = 0x00009888, .val = 0x0AA10034 },
         { .reg = 0x00009888, .val = 0x0EA10035 },
         { .reg = 0x00009888, .val = 0x12A10026 },
         { .reg = 0x00009888, .val = 0x16A1003E },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A32020 },
         { .reg = 0x00009888, .val = 0x02A32020 },
         { .reg = 0x00009888, .val = 0x00A44444 },
         { .reg = 0x00009888, .val = 0x00A61010 },
         { .reg = 0x00009888, .val = 0x02A61010 },
         { .reg = 0x00009888, .val = 0x00A71010 },
         { .reg = 0x00009888, .val = 0x02A71010 },
         { .reg = 0x00009888, .val = 0x06C13106 },
         { .reg = 0x00009888, .val = 0x08C10D00 },
         { .reg = 0x00009888, .val = 0x0CC10D40 },
         { .reg = 0x00009888, .val = 0x10C10980 },
         { .reg = 0x00009888, .val = 0x14C10F80 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30808 },
         { .reg = 0x00009888, .val = 0x02C30808 },
         { .reg = 0x00009888, .val = 0x00C42222 },
         { .reg = 0x00009888, .val = 0x00C60404 },
         { .reg = 0x00009888, .val = 0x02C60404 },
         { .reg = 0x00009888, .val = 0x00C70404 },
         { .reg = 0x00009888, .val = 0x02C70404 },
         { .reg = 0x00009888, .val = 0x06E13106 },
         { .reg = 0x00009888, .val = 0x08E10034 },
         { .reg = 0x00009888, .val = 0x0CE10035 },
         { .reg = 0x00009888, .val = 0x10E10026 },
         { .reg = 0x00009888, .val = 0x14E1003E },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30202 },
         { .reg = 0x00009888, .val = 0x02E30202 },
         { .reg = 0x00009888, .val = 0x00E41111 },
         { .reg = 0x00009888, .val = 0x00E60101 },
         { .reg = 0x00009888, .val = 0x02E60101 },
         { .reg = 0x00009888, .val = 0x00E70101 },
         { .reg = 0x00009888, .val = 0x02E70101 },
         { .reg = 0x00009888, .val = 0x00070909 },
         { .reg = 0x00009888, .val = 0x02070909 },
         { .reg = 0x00009888, .val = 0x0008B0B0 },
         { .reg = 0x00009888, .val = 0x0208B0B0 },
         { .reg = 0x00009888, .val = 0x00093333 },
         { .reg = 0x00009888, .val = 0x000A5A5A },
         { .reg = 0x00009888, .val = 0x020A5A5A },
         { .reg = 0x00009888, .val = 0x00014444 },
         { .reg = 0x00009888, .val = 0x000B1010 },
         { .reg = 0x00009888, .val = 0x020B1010 },
         { .reg = 0x00009888, .val = 0x00022222 },
         { .reg = 0x00009888, .val = 0x000C0404 },
         { .reg = 0x00009888, .val = 0x020C0404 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20102800 },
         { .reg = 0x00009888, .val = 0x26104000 },
         { .reg = 0x00009888, .val = 0x28100003 },
         { .reg = 0x00009888, .val = 0x2A100C0A },
         { .reg = 0x00009888, .val = 0x2C101401 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102803 },
         { .reg = 0x00009888, .val = 0x14101000 },
         { .reg = 0x00009888, .val = 0x24104600 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20102800 },
         { .reg = 0x00009888, .val = 0x26104000 },
         { .reg = 0x00009888, .val = 0x28100003 },
         { .reg = 0x00009888, .val = 0x2A100C0A },
         { .reg = 0x00009888, .val = 0x2C101401 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102803 },
         { .reg = 0x00009888, .val = 0x14101000 },
         { .reg = 0x00009888, .val = 0x24104600 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18082800 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080060 },
         { .reg = 0x00009888, .val = 0x0E081000 },
         { .reg = 0x00009888, .val = 0x20080C0A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12081000 },
         { .reg = 0x00009888, .val = 0x22080140 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06084000 },
         { .reg = 0x00009888, .val = 0x1A082803 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080060 },
         { .reg = 0x00009888, .val = 0x0A084000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x25817800 },
         { .reg = 0x00009888, .val = 0x29810000 },
         { .reg = 0x00009888, .val = 0x2B810001 },
         { .reg = 0x00009888, .val = 0x25A17800 },
         { .reg = 0x00009888, .val = 0x29A10000 },
         { .reg = 0x00009888, .val = 0x2BA10001 },
         { .reg = 0x00009888, .val = 0x25C17800 },
         { .reg = 0x00009888, .val = 0x29C10000 },
         { .reg = 0x00009888, .val = 0x2BC10001 },
         { .reg = 0x00009888, .val = 0x25E17800 },
         { .reg = 0x00009888, .val = 0x29E10000 },
         { .reg = 0x00009888, .val = 0x2BE10001 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A2800 },
         { .reg = 0x00009888, .val = 0x190A2800 },
         { .reg = 0x00009888, .val = 0x1E0A4003 },
         { .reg = 0x00009888, .val = 0x1F0A4003 },
         { .reg = 0x00009888, .val = 0x200A0060 },
         { .reg = 0x00009888, .val = 0x210A0060 },
         { .reg = 0x00009888, .val = 0x220A0028 },
         { .reg = 0x00009888, .val = 0x230A0028 },
         { .reg = 0x00009888, .val = 0x240A0023 },
         { .reg = 0x00009888, .val = 0x250A0023 },
         { .reg = 0x00009888, .val = 0x260A000A },
         { .reg = 0x00009888, .val = 0x270A000A },
         { .reg = 0x00009888, .val = 0x1A0A008C },
         { .reg = 0x00009888, .val = 0x1B0A008C },
         { .reg = 0x00009888, .val = 0x1C0A400A },
         { .reg = 0x00009888, .val = 0x1D0A400A },
         { .reg = 0x00009888, .val = 0x07813106 },
         { .reg = 0x00009888, .val = 0x0B810D00 },
         { .reg = 0x00009888, .val = 0x0F810D40 },
         { .reg = 0x00009888, .val = 0x13810980 },
         { .reg = 0x00009888, .val = 0x17810F80 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01838080 },
         { .reg = 0x00009888, .val = 0x03838080 },
         { .reg = 0x00009888, .val = 0x01848888 },
         { .reg = 0x00009888, .val = 0x01864040 },
         { .reg = 0x00009888, .val = 0x03864040 },
         { .reg = 0x00009888, .val = 0x01874040 },
         { .reg = 0x00009888, .val = 0x03874040 },
         { .reg = 0x00009888, .val = 0x07A13106 },
         { .reg = 0x00009888, .val = 0x0BA10034 },
         { .reg = 0x00009888, .val = 0x0FA10035 },
         { .reg = 0x00009888, .val = 0x13A10026 },
         { .reg = 0x00009888, .val = 0x17A1003E },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A32020 },
         { .reg = 0x00009888, .val = 0x03A32020 },
         { .reg = 0x00009888, .val = 0x01A44444 },
         { .reg = 0x00009888, .val = 0x01A61010 },
         { .reg = 0x00009888, .val = 0x03A61010 },
         { .reg = 0x00009888, .val = 0x01A71010 },
         { .reg = 0x00009888, .val = 0x03A71010 },
         { .reg = 0x00009888, .val = 0x07C13106 },
         { .reg = 0x00009888, .val = 0x09C10D00 },
         { .reg = 0x00009888, .val = 0x0DC10D40 },
         { .reg = 0x00009888, .val = 0x11C10980 },
         { .reg = 0x00009888, .val = 0x15C10F80 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C30808 },
         { .reg = 0x00009888, .val = 0x03C30808 },
         { .reg = 0x00009888, .val = 0x01C42222 },
         { .reg = 0x00009888, .val = 0x01C60404 },
         { .reg = 0x00009888, .val = 0x03C60404 },
         { .reg = 0x00009888, .val = 0x01C70404 },
         { .reg = 0x00009888, .val = 0x03C70404 },
         { .reg = 0x00009888, .val = 0x07E13106 },
         { .reg = 0x00009888, .val = 0x09E10034 },
         { .reg = 0x00009888, .val = 0x0DE10035 },
         { .reg = 0x00009888, .val = 0x11E10026 },
         { .reg = 0x00009888, .val = 0x15E1003E },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E30202 },
         { .reg = 0x00009888, .val = 0x03E30202 },
         { .reg = 0x00009888, .val = 0x01E41111 },
         { .reg = 0x00009888, .val = 0x01E60101 },
         { .reg = 0x00009888, .val = 0x03E60101 },
         { .reg = 0x00009888, .val = 0x01E70101 },
         { .reg = 0x00009888, .val = 0x03E70101 },
         { .reg = 0x00009888, .val = 0x01070909 },
         { .reg = 0x00009888, .val = 0x03070909 },
         { .reg = 0x00009888, .val = 0x0108B0B0 },
         { .reg = 0x00009888, .val = 0x0308B0B0 },
         { .reg = 0x00009888, .val = 0x01093333 },
         { .reg = 0x00009888, .val = 0x010A5A5A },
         { .reg = 0x00009888, .val = 0x030A5A5A },
         { .reg = 0x00009888, .val = 0x01014444 },
         { .reg = 0x00009888, .val = 0x010B1010 },
         { .reg = 0x00009888, .val = 0x030B1010 },
         { .reg = 0x00009888, .val = 0x01022222 },
         { .reg = 0x00009888, .val = 0x010C0404 },
         { .reg = 0x00009888, .val = 0x030C0404 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20102800 },
         { .reg = 0x00009888, .val = 0x26104000 },
         { .reg = 0x00009888, .val = 0x28100003 },
         { .reg = 0x00009888, .val = 0x2A100C0A },
         { .reg = 0x00009888, .val = 0x2C101401 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102803 },
         { .reg = 0x00009888, .val = 0x14101000 },
         { .reg = 0x00009888, .val = 0x24104600 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20102800 },
         { .reg = 0x00009888, .val = 0x26104000 },
         { .reg = 0x00009888, .val = 0x28100003 },
         { .reg = 0x00009888, .val = 0x2A100C0A },
         { .reg = 0x00009888, .val = 0x2C101401 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102803 },
         { .reg = 0x00009888, .val = 0x14101000 },
         { .reg = 0x00009888, .val = 0x24104600 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18082800 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080060 },
         { .reg = 0x00009888, .val = 0x0E081000 },
         { .reg = 0x00009888, .val = 0x20080C0A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12081000 },
         { .reg = 0x00009888, .val = 0x22080140 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06084000 },
         { .reg = 0x00009888, .val = 0x1A082803 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080060 },
         { .reg = 0x00009888, .val = 0x0A084000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__threads_and_rast1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__threads_and_rast1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__threads_and_rast1__avg_gpu_core_frequency__max,acmgt1__threads_and_rast1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 575, 24, NULL,acmgt1__threads_and_rast1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 576, 32, NULL,acmgt1__threads_and_rast1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 577, 40, NULL,acmgt1__threads_and_rast1__ds_threads__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_threads_and_rast2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ThreadsAndRast2";
   query->symbol_name = "ThreadsAndRast2";
   query->guid = "797ae4a3-6d36-4be1-9064-a9bc3263957f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x24817800 },
         { .reg = 0x00009888, .val = 0x2A810001 },
         { .reg = 0x00009888, .val = 0x24A17800 },
         { .reg = 0x00009888, .val = 0x2AA10001 },
         { .reg = 0x00009888, .val = 0x24C17800 },
         { .reg = 0x00009888, .val = 0x2AC10001 },
         { .reg = 0x00009888, .val = 0x24E17800 },
         { .reg = 0x00009888, .val = 0x2AE10001 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A054A },
         { .reg = 0x00009888, .val = 0x1F0A054A },
         { .reg = 0x00009888, .val = 0x200A0C60 },
         { .reg = 0x00009888, .val = 0x210A0C60 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A550A },
         { .reg = 0x00009888, .val = 0x250A550A },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x06810306 },
         { .reg = 0x00009888, .val = 0x08810D32 },
         { .reg = 0x00009888, .val = 0x10810922 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x00840303 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x06A10306 },
         { .reg = 0x00009888, .val = 0x0AA10D32 },
         { .reg = 0x00009888, .val = 0x12A10922 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x02A300A0 },
         { .reg = 0x00009888, .val = 0x00A40C0C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x02A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x02A70050 },
         { .reg = 0x00009888, .val = 0x06C10306 },
         { .reg = 0x00009888, .val = 0x0CC10D32 },
         { .reg = 0x00009888, .val = 0x14C10922 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x02C30A00 },
         { .reg = 0x00009888, .val = 0x00C43030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x02C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x02C70500 },
         { .reg = 0x00009888, .val = 0x06E10306 },
         { .reg = 0x00009888, .val = 0x0EE10D32 },
         { .reg = 0x00009888, .val = 0x16E10922 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x02E3A000 },
         { .reg = 0x00009888, .val = 0x00E4C0C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x02E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x02E75000 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x02075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x020800FA },
         { .reg = 0x00009888, .val = 0x0009F0F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010C0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020B0050 },
         { .reg = 0x00009888, .val = 0x00023030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x020C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12101000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610002A },
         { .reg = 0x00009888, .val = 0x28100063 },
         { .reg = 0x00009888, .val = 0x2A102800 },
         { .reg = 0x00009888, .val = 0x2C1040A8 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12101000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610002A },
         { .reg = 0x00009888, .val = 0x28100063 },
         { .reg = 0x00009888, .val = 0x2A102800 },
         { .reg = 0x00009888, .val = 0x2C1040A8 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C081000 },
         { .reg = 0x00009888, .val = 0x1E080C60 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20082800 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208040A },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x25817800 },
         { .reg = 0x00009888, .val = 0x2B810001 },
         { .reg = 0x00009888, .val = 0x25A17800 },
         { .reg = 0x00009888, .val = 0x2BA10001 },
         { .reg = 0x00009888, .val = 0x25C17800 },
         { .reg = 0x00009888, .val = 0x2BC10001 },
         { .reg = 0x00009888, .val = 0x25E17800 },
         { .reg = 0x00009888, .val = 0x2BE10001 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A054A },
         { .reg = 0x00009888, .val = 0x1F0A054A },
         { .reg = 0x00009888, .val = 0x200A0C60 },
         { .reg = 0x00009888, .val = 0x210A0C60 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A550A },
         { .reg = 0x00009888, .val = 0x250A550A },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x07810306 },
         { .reg = 0x00009888, .val = 0x09810D32 },
         { .reg = 0x00009888, .val = 0x11810922 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183000A },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840303 },
         { .reg = 0x00009888, .val = 0x01860005 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01870005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10306 },
         { .reg = 0x00009888, .val = 0x0BA10D32 },
         { .reg = 0x00009888, .val = 0x13A10922 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A300A0 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C0C },
         { .reg = 0x00009888, .val = 0x01A60050 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x01A70050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10306 },
         { .reg = 0x00009888, .val = 0x0DC10D32 },
         { .reg = 0x00009888, .val = 0x15C10922 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C30A00 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43030 },
         { .reg = 0x00009888, .val = 0x01C60500 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x01C70500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10306 },
         { .reg = 0x00009888, .val = 0x0FE10D32 },
         { .reg = 0x00009888, .val = 0x17E10922 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C0C0 },
         { .reg = 0x00009888, .val = 0x01E65000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x01E75000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x01075A00 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x010800FA },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F0F0 },
         { .reg = 0x00009888, .val = 0x010AAA55 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C0C },
         { .reg = 0x00009888, .val = 0x010B0050 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023030 },
         { .reg = 0x00009888, .val = 0x010C0500 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12101000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610002A },
         { .reg = 0x00009888, .val = 0x28100063 },
         { .reg = 0x00009888, .val = 0x2A102800 },
         { .reg = 0x00009888, .val = 0x2C1040A8 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12101000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610002A },
         { .reg = 0x00009888, .val = 0x28100063 },
         { .reg = 0x00009888, .val = 0x2A102800 },
         { .reg = 0x00009888, .val = 0x2C1040A8 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C081000 },
         { .reg = 0x00009888, .val = 0x1E080C60 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20082800 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208040A },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x000000FF },
         { .reg = 0x0000DC00, .val = 0x00000018 },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000060 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC10, .val = 0x00000180 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000DC18, .val = 0x00000600 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000DC20, .val = 0x00001800 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000DC28, .val = 0x00006000 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
         { .reg = 0x0000DC30, .val = 0x00018000 },
         { .reg = 0x0000DC34, .val = 0x0000CFFF },
         { .reg = 0x0000DC38, .val = 0x00060000 },
         { .reg = 0x0000DC3C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__threads_and_rast2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__threads_and_rast2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__threads_and_rast2__avg_gpu_core_frequency__max,acmgt1__threads_and_rast2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 578, 24, NULL,acmgt1__threads_and_rast2__ps_threads__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_threads_and_rast3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "ThreadsAndRast3";
   query->symbol_name = "ThreadsAndRast3";
   query->guid = "abb4b8fd-b9cd-4b11-a610-1c0707af14cf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810000 },
         { .reg = 0x00009888, .val = 0x28A10000 },
         { .reg = 0x00009888, .val = 0x28C10000 },
         { .reg = 0x00009888, .val = 0x28E10000 },
         { .reg = 0x00009888, .val = 0x1E0AFC03 },
         { .reg = 0x00009888, .val = 0x1F0AFC03 },
         { .reg = 0x00009888, .val = 0x200A0C63 },
         { .reg = 0x00009888, .val = 0x210A0C63 },
         { .reg = 0x00009888, .val = 0x220AC78F },
         { .reg = 0x00009888, .val = 0x230AC78F },
         { .reg = 0x00009888, .val = 0x240AF1E3 },
         { .reg = 0x00009888, .val = 0x250AF1E3 },
         { .reg = 0x00009888, .val = 0x260A0063 },
         { .reg = 0x00009888, .val = 0x270A0063 },
         { .reg = 0x00009888, .val = 0x1A0A078F },
         { .reg = 0x00009888, .val = 0x1B0A078F },
         { .reg = 0x00009888, .val = 0x1C0A400A },
         { .reg = 0x00009888, .val = 0x1D0A400A },
         { .reg = 0x00009888, .val = 0x160B4000 },
         { .reg = 0x00009888, .val = 0x180B0011 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x16810CC0 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x16A10033 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x14C10CC0 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x14E10033 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FFFC },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x000A5554 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FFE },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B1800 },
         { .reg = 0x00009888, .val = 0x080B0105 },
         { .reg = 0x00009888, .val = 0x0A0B038F },
         { .reg = 0x00009888, .val = 0x0C0B030D },
         { .reg = 0x00009888, .val = 0x0E0B028B },
         { .reg = 0x00009888, .val = 0x100B0209 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B1000 },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x2610F1E0 },
         { .reg = 0x00009888, .val = 0x2810FC63 },
         { .reg = 0x00009888, .val = 0x2A100C63 },
         { .reg = 0x00009888, .val = 0x2C10C78F },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x1210C000 },
         { .reg = 0x00009888, .val = 0x22102863 },
         { .reg = 0x00009888, .val = 0x14103000 },
         { .reg = 0x00009888, .val = 0x24104600 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x2610F1E0 },
         { .reg = 0x00009888, .val = 0x2810FC63 },
         { .reg = 0x00009888, .val = 0x2A100C63 },
         { .reg = 0x00009888, .val = 0x2C10C78F },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x1210C000 },
         { .reg = 0x00009888, .val = 0x22102863 },
         { .reg = 0x00009888, .val = 0x14103000 },
         { .reg = 0x00009888, .val = 0x24104600 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0C08F000 },
         { .reg = 0x00009888, .val = 0x1E080C63 },
         { .reg = 0x00009888, .val = 0x0E08F000 },
         { .reg = 0x00009888, .val = 0x20080C63 },
         { .reg = 0x00009888, .val = 0x1008F000 },
         { .reg = 0x00009888, .val = 0x1208F000 },
         { .reg = 0x00009888, .val = 0x22080C63 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x0608F000 },
         { .reg = 0x00009888, .val = 0x1A082863 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080060 },
         { .reg = 0x00009888, .val = 0x0A084000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x29810000 },
         { .reg = 0x00009888, .val = 0x29A10000 },
         { .reg = 0x00009888, .val = 0x29C10000 },
         { .reg = 0x00009888, .val = 0x29E10000 },
         { .reg = 0x00009888, .val = 0x1E0AFC03 },
         { .reg = 0x00009888, .val = 0x1F0AFC03 },
         { .reg = 0x00009888, .val = 0x200A0C63 },
         { .reg = 0x00009888, .val = 0x210A0C63 },
         { .reg = 0x00009888, .val = 0x220AC78F },
         { .reg = 0x00009888, .val = 0x230AC78F },
         { .reg = 0x00009888, .val = 0x240AF1E3 },
         { .reg = 0x00009888, .val = 0x250AF1E3 },
         { .reg = 0x00009888, .val = 0x260A0063 },
         { .reg = 0x00009888, .val = 0x270A0063 },
         { .reg = 0x00009888, .val = 0x1A0A078F },
         { .reg = 0x00009888, .val = 0x1B0A078F },
         { .reg = 0x00009888, .val = 0x1C0A400A },
         { .reg = 0x00009888, .val = 0x1D0A400A },
         { .reg = 0x00009888, .val = 0x170B4000 },
         { .reg = 0x00009888, .val = 0x190B0011 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x17810CC0 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03838000 },
         { .reg = 0x00009888, .val = 0x01848000 },
         { .reg = 0x00009888, .val = 0x03864000 },
         { .reg = 0x00009888, .val = 0x03874000 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x17A10033 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32000 },
         { .reg = 0x00009888, .val = 0x01A44000 },
         { .reg = 0x00009888, .val = 0x03A61000 },
         { .reg = 0x00009888, .val = 0x03A71000 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10CC0 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30800 },
         { .reg = 0x00009888, .val = 0x01C42000 },
         { .reg = 0x00009888, .val = 0x03C60400 },
         { .reg = 0x00009888, .val = 0x03C70400 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x15E10033 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30200 },
         { .reg = 0x00009888, .val = 0x01E41000 },
         { .reg = 0x00009888, .val = 0x03E60100 },
         { .reg = 0x00009888, .val = 0x03E70100 },
         { .reg = 0x00009888, .val = 0x03070900 },
         { .reg = 0x00009888, .val = 0x0108FFFC },
         { .reg = 0x00009888, .val = 0x0308B0FF },
         { .reg = 0x00009888, .val = 0x01093000 },
         { .reg = 0x00009888, .val = 0x010A5554 },
         { .reg = 0x00009888, .val = 0x030A5A55 },
         { .reg = 0x00009888, .val = 0x01014FFE },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B1800 },
         { .reg = 0x00009888, .val = 0x090B0105 },
         { .reg = 0x00009888, .val = 0x0B0B038F },
         { .reg = 0x00009888, .val = 0x0D0B030D },
         { .reg = 0x00009888, .val = 0x0F0B028B },
         { .reg = 0x00009888, .val = 0x110B0209 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B1000 },
         { .reg = 0x00009888, .val = 0x01022000 },
         { .reg = 0x00009888, .val = 0x030C0400 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x2610F1E0 },
         { .reg = 0x00009888, .val = 0x2810FC63 },
         { .reg = 0x00009888, .val = 0x2A100C63 },
         { .reg = 0x00009888, .val = 0x2C10C78F },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x1210C000 },
         { .reg = 0x00009888, .val = 0x22102863 },
         { .reg = 0x00009888, .val = 0x14103000 },
         { .reg = 0x00009888, .val = 0x24104600 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x2610F1E0 },
         { .reg = 0x00009888, .val = 0x2810FC63 },
         { .reg = 0x00009888, .val = 0x2A100C63 },
         { .reg = 0x00009888, .val = 0x2C10C78F },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x1210C000 },
         { .reg = 0x00009888, .val = 0x22102863 },
         { .reg = 0x00009888, .val = 0x14103000 },
         { .reg = 0x00009888, .val = 0x24104600 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0C08F000 },
         { .reg = 0x00009888, .val = 0x1E080C63 },
         { .reg = 0x00009888, .val = 0x0E08F000 },
         { .reg = 0x00009888, .val = 0x20080C63 },
         { .reg = 0x00009888, .val = 0x1008F000 },
         { .reg = 0x00009888, .val = 0x1208F000 },
         { .reg = 0x00009888, .val = 0x22080C63 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x0608F000 },
         { .reg = 0x00009888, .val = 0x1A082863 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080060 },
         { .reg = 0x00009888, .val = 0x0A084000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFFE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__threads_and_rast3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__threads_and_rast3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__threads_and_rast3__avg_gpu_core_frequency__max,acmgt1__threads_and_rast3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 579, 24, NULL,acmgt1__threads_and_rast3__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 580, 32, NULL,acmgt1__threads_and_rast3__hi_depth_test_fails__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_threads_and_rast4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ThreadsAndRast4";
   query->symbol_name = "ThreadsAndRast4";
   query->guid = "2da159d5-8ace-42bb-9d81-26f2b162d8d8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C10000C },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x22100060 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410000C },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C10000C },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x22100060 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410000C },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080003 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080060 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C03 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0180 },
         { .reg = 0x00009888, .val = 0x250A0180 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A0600 },
         { .reg = 0x00009888, .val = 0x1B0A0600 },
         { .reg = 0x00009888, .val = 0x1C0A0180 },
         { .reg = 0x00009888, .val = 0x1D0A0180 },
         { .reg = 0x00009888, .val = 0x1E0A0060 },
         { .reg = 0x00009888, .val = 0x1F0A0060 },
         { .reg = 0x00009888, .val = 0x100B5480 },
         { .reg = 0x00009888, .val = 0x100C5012 },
         { .reg = 0x00009888, .val = 0x00072000 },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x0008C000 },
         { .reg = 0x00009888, .val = 0x0208CCCC },
         { .reg = 0x00009888, .val = 0x00095540 },
         { .reg = 0x00009888, .val = 0x000A6000 },
         { .reg = 0x00009888, .val = 0x020A6666 },
         { .reg = 0x00009888, .val = 0x0001AA80 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x0C0B0500 },
         { .reg = 0x00009888, .val = 0x0E0B04C0 },
         { .reg = 0x00009888, .val = 0x120B0440 },
         { .reg = 0x00009888, .val = 0x140B0400 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009888, .val = 0x00025540 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x0C0C0014 },
         { .reg = 0x00009888, .val = 0x0E0C0013 },
         { .reg = 0x00009888, .val = 0x120C0011 },
         { .reg = 0x00009888, .val = 0x140C0010 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C10000C },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x22100060 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410000C },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C10000C },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x22100060 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410000C },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080003 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080060 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C03 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0180 },
         { .reg = 0x00009888, .val = 0x250A0180 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A0600 },
         { .reg = 0x00009888, .val = 0x1B0A0600 },
         { .reg = 0x00009888, .val = 0x1C0A0180 },
         { .reg = 0x00009888, .val = 0x1D0A0180 },
         { .reg = 0x00009888, .val = 0x1E0A0060 },
         { .reg = 0x00009888, .val = 0x1F0A0060 },
         { .reg = 0x00009888, .val = 0x110B5480 },
         { .reg = 0x00009888, .val = 0x110C5012 },
         { .reg = 0x00009888, .val = 0x01072000 },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x0108C000 },
         { .reg = 0x00009888, .val = 0x0308CCCC },
         { .reg = 0x00009888, .val = 0x01095540 },
         { .reg = 0x00009888, .val = 0x010A6000 },
         { .reg = 0x00009888, .val = 0x030A6666 },
         { .reg = 0x00009888, .val = 0x0101AA80 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x0D0B0500 },
         { .reg = 0x00009888, .val = 0x0F0B04C0 },
         { .reg = 0x00009888, .val = 0x130B0440 },
         { .reg = 0x00009888, .val = 0x150B0400 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01025540 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x0D0C0014 },
         { .reg = 0x00009888, .val = 0x0F0C0013 },
         { .reg = 0x00009888, .val = 0x130C0011 },
         { .reg = 0x00009888, .val = 0x150C0010 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFC0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__threads_and_rast4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__threads_and_rast4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__threads_and_rast4__avg_gpu_core_frequency__max,acmgt1__threads_and_rast4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 581, 24, NULL,acmgt1__threads_and_rast4__early_depth_test_fails__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "91273130-42fe-4c5e-ba34-6f9140b612c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00010000 },
         { .reg = 0x0000E558, .val = 0x00060050 },
         { .reg = 0x0000E658, .val = 0x00001090 },
         { .reg = 0x0000E758, .val = 0x00051011 },
         { .reg = 0x0000E45C, .val = 0x00091061 },
         { .reg = 0x0000E55C, .val = 0x00004008 },
         { .reg = 0x0000E65C, .val = 0x00000005 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__async_compute__avg_gpu_core_frequency__max,acmgt1__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 539, 32, NULL,acmgt1__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 566, 40, percentage_max_float,acmgt1__async_compute__fpu_active__read);

      intel_perf_query_add_counter_float(query, 545, 44, percentage_max_float,acmgt1__async_compute__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 548, 48, percentage_max_float,acmgt1__async_compute__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 582, 52, percentage_max_float,acmgt1__async_compute__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 583, 56, percentage_max_float,acmgt1__async_compute__async_cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 567, 60, percentage_max_float,acmgt1__async_compute__em_active__read);

      intel_perf_query_add_counter_float(query, 546, 64, percentage_max_float,acmgt1__async_compute__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 549, 68, percentage_max_float,acmgt1__async_compute__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 584, 72, percentage_max_float,acmgt1__async_compute__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 585, 76, percentage_max_float,acmgt1__async_compute__async_cs_em_active__read);

      intel_perf_query_add_counter_float(query, 543, 80, percentage_max_float,acmgt1__async_compute__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 541, 84, percentage_max_float,acmgt1__async_compute__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 88, percentage_max_float,acmgt1__async_compute__xve_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_xve_activity1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "XveActivity1";
   query->symbol_name = "XveActivity1";
   query->guid = "fd9d1ad4-13b3-4583-9f2c-998f627e370d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00030020 },
         { .reg = 0x0000E558, .val = 0x00021040 },
         { .reg = 0x0000E658, .val = 0x00041031 },
         { .reg = 0x0000E758, .val = 0x00032022 },
         { .reg = 0x0000E45C, .val = 0x00062042 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__xve_activity1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__xve_activity1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__xve_activity1__avg_gpu_core_frequency__max,acmgt1__xve_activity1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__xve_activity1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 539, 32, NULL,acmgt1__xve_activity1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 586, 40, percentage_max_float,acmgt1__xve_activity1__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 587, 44, percentage_max_float,acmgt1__xve_activity1__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 588, 48, percentage_max_float,acmgt1__xve_activity1__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 589, 52, percentage_max_float,acmgt1__xve_activity1__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 590, 56, percentage_max_float,acmgt1__xve_activity1__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 591, 60, percentage_max_float,acmgt1__xve_activity1__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 592, 64, percentage_max_float,acmgt1__xve_activity1__hs_send_active__read);

      intel_perf_query_add_counter_float(query, 593, 68, percentage_max_float,acmgt1__xve_activity1__ds_send_active__read);

      intel_perf_query_add_counter_float(query, 594, 72, percentage_max_float,acmgt1__xve_activity1__gs_send_active__read);

      intel_perf_query_add_counter_float(query, 595, 76, percentage_max_float,acmgt1__xve_activity1__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "4b785529-8efb-471e-93c5-481dae7b3b8b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x440A2400 },
         { .reg = 0x00009888, .val = 0x1A131200 },
         { .reg = 0x00009888, .val = 0x060A0022 },
         { .reg = 0x00009888, .val = 0x140A0014 },
         { .reg = 0x00009888, .val = 0x040A0000 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x00104000 },
         { .reg = 0x00009888, .val = 0x02100002 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x02130000 },
         { .reg = 0x00009888, .val = 0x0A130900 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x440A2400 },
         { .reg = 0x00009888, .val = 0x1A131200 },
         { .reg = 0x00009888, .val = 0x060A0022 },
         { .reg = 0x00009888, .val = 0x120A0014 },
         { .reg = 0x00009888, .val = 0x040A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x00102400 },
         { .reg = 0x00009888, .val = 0x00120400 },
         { .reg = 0x00009888, .val = 0x02130000 },
         { .reg = 0x00009888, .val = 0x08130900 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x18012400 },
         { .reg = 0x00009888, .val = 0x1A042400 },
         { .reg = 0x00009888, .val = 0x22042400 },
         { .reg = 0x00009888, .val = 0x2A042400 },
         { .reg = 0x00009888, .val = 0x34040009 },
         { .reg = 0x00009888, .val = 0x3E041200 },
         { .reg = 0x00009888, .val = 0x02010006 },
         { .reg = 0x00009888, .val = 0x10010004 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x020426E9 },
         { .reg = 0x00009888, .val = 0x040401B7 },
         { .reg = 0x00009888, .val = 0x06041000 },
         { .reg = 0x00009888, .val = 0x0804050C },
         { .reg = 0x00009888, .val = 0x0A04091C },
         { .reg = 0x00009888, .val = 0x1204051C },
         { .reg = 0x00009888, .val = 0x1404010C },
         { .reg = 0x00009888, .val = 0x16040024 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x0003FD55 },
         { .reg = 0x00009888, .val = 0x0203554B },
         { .reg = 0x00009888, .val = 0x00095400 },
         { .reg = 0x00009888, .val = 0x02090001 },
         { .reg = 0x00009888, .val = 0x00056800 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A0002 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A033000 },
         { .reg = 0x00009888, .val = 0x48030864 },
         { .reg = 0x00009888, .val = 0x4A030643 },
         { .reg = 0x00009888, .val = 0x4C031404 },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030043 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x44031080 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x46031084 },
         { .reg = 0x00009888, .val = 0x24033000 },
         { .reg = 0x00009888, .val = 0x28033000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000081 },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__gpu_busyness__avg_gpu_core_frequency__max,acmgt1__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 541, 28, percentage_max_float,acmgt1__gpu_busyness__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 32, percentage_max_float,acmgt1__gpu_busyness__xve_stall__read);

      intel_perf_query_add_counter_float(query, 543, 36, percentage_max_float,acmgt1__gpu_busyness__xve_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 539, 40, NULL,acmgt1__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 596, 48, percentage_max_float,acmgt1__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 597, 52, percentage_max_float,acmgt1__gpu_busyness__compute_engine0_busy__read);

      intel_perf_query_add_counter_float(query, 598, 56, percentage_max_float,acmgt1__gpu_busyness__compute_engine1_busy__read);

      intel_perf_query_add_counter_float(query, 599, 60, percentage_max_float,acmgt1__gpu_busyness__compute_engine2_busy__read);

      intel_perf_query_add_counter_float(query, 600, 64, percentage_max_float,acmgt1__gpu_busyness__compute_engine3_busy__read);

      intel_perf_query_add_counter_float(query, 601, 68, percentage_max_float,acmgt1__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 602, 72, percentage_max_float,acmgt1__gpu_busyness__vdbox00_busy__read);

      intel_perf_query_add_counter_float(query, 603, 76, percentage_max_float,acmgt1__gpu_busyness__vebox0_busy__read);

      intel_perf_query_add_counter_float(query, 604, 80, percentage_max_float,acmgt1__gpu_busyness__vdbox10_busy__read);

      intel_perf_query_add_counter_float(query, 605, 84, percentage_max_float,acmgt1__gpu_busyness__vebox1_busy__read);

      intel_perf_query_add_counter_float(query, 606, 88, percentage_max_float,acmgt1__gpu_busyness__any_compute_engine_busy__read);

      intel_perf_query_add_counter_float(query, 607, 92, percentage_max_float,acmgt1__gpu_busyness__render_and_any_compute_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_render_pipe_profile1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile1";
   query->guid = "8a0c5d31-e0cb-4d2c-8056-f3824c57ad9a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x168607C0 },
         { .reg = 0x00009888, .val = 0x1603001F },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x12040640 },
         { .reg = 0x00009888, .val = 0x08040021 },
         { .reg = 0x00009888, .val = 0x1C070000 },
         { .reg = 0x00009888, .val = 0x16090000 },
         { .reg = 0x00009888, .val = 0x1C0903C0 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x160B7C00 },
         { .reg = 0x00009888, .val = 0x04860000 },
         { .reg = 0x00009888, .val = 0x06860400 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x0A0301C0 },
         { .reg = 0x00009888, .val = 0x100300C0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x0C040080 },
         { .reg = 0x00009888, .val = 0x0E040022 },
         { .reg = 0x00009888, .val = 0x04074000 },
         { .reg = 0x00009888, .val = 0x0A070021 },
         { .reg = 0x00009888, .val = 0x0E0708C0 },
         { .reg = 0x00009888, .val = 0x00070800 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x00083032 },
         { .reg = 0x00009888, .val = 0x02083300 },
         { .reg = 0x00009888, .val = 0x02094003 },
         { .reg = 0x00009888, .val = 0x08090880 },
         { .reg = 0x00009888, .val = 0x0C090001 },
         { .reg = 0x00009888, .val = 0x0E090023 },
         { .reg = 0x00009888, .val = 0x12090003 },
         { .reg = 0x00009888, .val = 0x00090D28 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x140A0940 },
         { .reg = 0x00009888, .val = 0x000A9A91 },
         { .reg = 0x00009888, .val = 0x020A19AA },
         { .reg = 0x00009888, .val = 0x00015044 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x020B2200 },
         { .reg = 0x00009888, .val = 0x00020C20 },
         { .reg = 0x00009888, .val = 0x000C0800 },
         { .reg = 0x00009888, .val = 0x020C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFD },
         { .reg = 0x00009888, .val = 0x0002AAA2 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035551 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031C00 },
         { .reg = 0x00009888, .val = 0x48030C00 },
         { .reg = 0x00009888, .val = 0x4A030221 },
         { .reg = 0x00009888, .val = 0x4C030006 },
         { .reg = 0x00009888, .val = 0x4E030210 },
         { .reg = 0x00009888, .val = 0x50030426 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030061 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030400 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46032826 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__render_pipe_profile1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__render_pipe_profile1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__render_pipe_profile1__avg_gpu_core_frequency__max,acmgt1__render_pipe_profile1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__render_pipe_profile1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 608, 28, percentage_max_float,acmgt1__render_pipe_profile1__vf2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 609, 32, percentage_max_float,acmgt1__render_pipe_profile1__vs2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 610, 36, percentage_max_float,acmgt1__render_pipe_profile1__cl2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 611, 40, percentage_max_float,acmgt1__render_pipe_profile1__hs2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 612, 44, percentage_max_float,acmgt1__render_pipe_profile1__ds2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 613, 48, percentage_max_float,acmgt1__render_pipe_profile1__gs2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 614, 52, percentage_max_float,acmgt1__render_pipe_profile1__sf2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 615, 56, percentage_max_float,acmgt1__render_pipe_profile1__so2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 616, 60, percentage_max_float,acmgt1__render_pipe_profile1__cl2_stall__read);

      intel_perf_query_add_counter_float(query, 617, 64, percentage_max_float,acmgt1__render_pipe_profile1__hs2_stall__read);

      intel_perf_query_add_counter_float(query, 618, 68, percentage_max_float,acmgt1__render_pipe_profile1__ds2_stall__read);

      intel_perf_query_add_counter_float(query, 619, 72, percentage_max_float,acmgt1__render_pipe_profile1__sf2_stall__read);

      intel_perf_query_add_counter_float(query, 620, 76, percentage_max_float,acmgt1__render_pipe_profile1__so2_stall__read);

      intel_perf_query_add_counter_float(query, 621, 80, percentage_max_float,acmgt1__render_pipe_profile1__hi_depth20_bottleneck__read);

      intel_perf_query_add_counter_float(query, 622, 84, percentage_max_float,acmgt1__render_pipe_profile1__bc20_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_render_pipe_profile2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile2";
   query->guid = "0f40fba0-129a-4a19-87de-5fdbe111b915";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x178607C0 },
         { .reg = 0x00009888, .val = 0x1703001F },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x13040640 },
         { .reg = 0x00009888, .val = 0x09040021 },
         { .reg = 0x00009888, .val = 0x1D070000 },
         { .reg = 0x00009888, .val = 0x17090000 },
         { .reg = 0x00009888, .val = 0x1D0903C0 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x170B7C00 },
         { .reg = 0x00009888, .val = 0x05860000 },
         { .reg = 0x00009888, .val = 0x07860400 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x0003FFFD },
         { .reg = 0x00009888, .val = 0x0008FFF3 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5551 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x000BAAA2 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x0B0301C0 },
         { .reg = 0x00009888, .val = 0x110300C0 },
         { .reg = 0x00009888, .val = 0x13030C80 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01040000 },
         { .reg = 0x00009888, .val = 0x0D040080 },
         { .reg = 0x00009888, .val = 0x0F040022 },
         { .reg = 0x00009888, .val = 0x05074000 },
         { .reg = 0x00009888, .val = 0x0B070021 },
         { .reg = 0x00009888, .val = 0x0F0708C0 },
         { .reg = 0x00009888, .val = 0x01070800 },
         { .reg = 0x00009888, .val = 0x030700A0 },
         { .reg = 0x00009888, .val = 0x01083032 },
         { .reg = 0x00009888, .val = 0x03083300 },
         { .reg = 0x00009888, .val = 0x03094003 },
         { .reg = 0x00009888, .val = 0x09090880 },
         { .reg = 0x00009888, .val = 0x0D090001 },
         { .reg = 0x00009888, .val = 0x0F090023 },
         { .reg = 0x00009888, .val = 0x13090003 },
         { .reg = 0x00009888, .val = 0x01090D28 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x150A0940 },
         { .reg = 0x00009888, .val = 0x010A9A91 },
         { .reg = 0x00009888, .val = 0x030A19AA },
         { .reg = 0x00009888, .val = 0x01015044 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B2000 },
         { .reg = 0x00009888, .val = 0x030B2200 },
         { .reg = 0x00009888, .val = 0x01020C20 },
         { .reg = 0x00009888, .val = 0x010C0800 },
         { .reg = 0x00009888, .val = 0x030C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFD },
         { .reg = 0x00009888, .val = 0x0002AAA2 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035551 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031C00 },
         { .reg = 0x00009888, .val = 0x48030C00 },
         { .reg = 0x00009888, .val = 0x4A030221 },
         { .reg = 0x00009888, .val = 0x4C030006 },
         { .reg = 0x00009888, .val = 0x4E030210 },
         { .reg = 0x00009888, .val = 0x50030426 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030061 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030400 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46032826 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__render_pipe_profile2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__render_pipe_profile2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__render_pipe_profile2__avg_gpu_core_frequency__max,acmgt1__render_pipe_profile2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__render_pipe_profile2__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 623, 28, percentage_max_float,acmgt1__render_pipe_profile2__vf3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 624, 32, percentage_max_float,acmgt1__render_pipe_profile2__vs3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 625, 36, percentage_max_float,acmgt1__render_pipe_profile2__cl3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 626, 40, percentage_max_float,acmgt1__render_pipe_profile2__hs3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 627, 44, percentage_max_float,acmgt1__render_pipe_profile2__ds3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 628, 48, percentage_max_float,acmgt1__render_pipe_profile2__gs3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 629, 52, percentage_max_float,acmgt1__render_pipe_profile2__sf3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 630, 56, percentage_max_float,acmgt1__render_pipe_profile2__so3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 631, 60, percentage_max_float,acmgt1__render_pipe_profile2__cl3_stall__read);

      intel_perf_query_add_counter_float(query, 632, 64, percentage_max_float,acmgt1__render_pipe_profile2__hs3_stall__read);

      intel_perf_query_add_counter_float(query, 633, 68, percentage_max_float,acmgt1__render_pipe_profile2__ds3_stall__read);

      intel_perf_query_add_counter_float(query, 634, 72, percentage_max_float,acmgt1__render_pipe_profile2__sf3_stall__read);

      intel_perf_query_add_counter_float(query, 635, 76, percentage_max_float,acmgt1__render_pipe_profile2__so3_stall__read);

      intel_perf_query_add_counter_float(query, 636, 80, percentage_max_float,acmgt1__render_pipe_profile2__hi_depth30_bottleneck__read);

      intel_perf_query_add_counter_float(query, 637, 84, percentage_max_float,acmgt1__render_pipe_profile2__bc30_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_l3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "L3";
   query->symbol_name = "L3";
   query->guid = "24695fb7-a404-4cd6-9aad-d23738b6d499";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C03020A },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030801 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__l3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__l3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__l3__avg_gpu_core_frequency__max,acmgt1__l3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__l3__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 638, 28, percentage_max_float,acmgt1__l3__l31_bank0_input_available__read);

      intel_perf_query_add_counter_float(query, 639, 32, percentage_max_float,acmgt1__l3__l31_bank1_input_available__read);

      intel_perf_query_add_counter_float(query, 640, 36, percentage_max_float,acmgt1__l3__l31_bank2_input_available__read);

      intel_perf_query_add_counter_float(query, 641, 40, percentage_max_float,acmgt1__l3__l31_bank3_input_available__read);

      intel_perf_query_add_counter_float(query, 642, 44, percentage_max_float,acmgt1__l3__l31_bank4_input_available__read);

      intel_perf_query_add_counter_float(query, 643, 48, percentage_max_float,acmgt1__l3__l31_bank5_input_available__read);

      intel_perf_query_add_counter_float(query, 644, 52, percentage_max_float,acmgt1__l3__l31_bank6_input_available__read);

      intel_perf_query_add_counter_float(query, 645, 56, percentage_max_float,acmgt1__l3__l31_bank7_input_available__read);

      intel_perf_query_add_counter_float(query, 646, 60, percentage_max_float,acmgt1__l3__l31_bank0_output_ready__read);

      intel_perf_query_add_counter_float(query, 647, 64, percentage_max_float,acmgt1__l3__l31_bank1_output_ready__read);

      intel_perf_query_add_counter_float(query, 648, 68, percentage_max_float,acmgt1__l3__l31_bank2_output_ready__read);

      intel_perf_query_add_counter_float(query, 649, 72, percentage_max_float,acmgt1__l3__l31_bank3_output_ready__read);

      intel_perf_query_add_counter_float(query, 650, 76, percentage_max_float,acmgt1__l3__l31_bank4_output_ready__read);

      intel_perf_query_add_counter_float(query, 651, 80, percentage_max_float,acmgt1__l3__l31_bank5_output_ready__read);

      intel_perf_query_add_counter_float(query, 652, 84, percentage_max_float,acmgt1__l3__l31_bank6_output_ready__read);

      intel_perf_query_add_counter_float(query, 653, 88, percentage_max_float,acmgt1__l3__l31_bank7_output_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Sampler_Slice23";
   query->symbol_name = "Sampler";
   query->guid = "4486113b-a8a7-4f75-a1c2-7d307fa0e00e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x14832C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x14A32C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x14C32C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x14E32C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x15832C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x15A32C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x15C32C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x15E32C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x16820024 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x0A830580 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x14A20900 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x0AA30016 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x14C20024 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x08C30580 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x12E20900 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x08E30016 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x13820024 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x07830580 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x07A30016 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x11C20024 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x05C30580 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x0FE20900 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x05E30016 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030C00 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030E04 },
         { .reg = 0x00009888, .val = 0x4A031E61 },
         { .reg = 0x00009888, .val = 0x4C0302E0 },
         { .reg = 0x00009888, .val = 0x4E031E47 },
         { .reg = 0x00009888, .val = 0x50031403 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031C43 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x46032808 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__sampler__avg_gpu_core_frequency__max,acmgt1__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__sampler__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 654, 28, percentage_max_float,acmgt1__sampler__sampler20_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 655, 32, percentage_max_float,acmgt1__sampler__sampler21_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 656, 36, percentage_max_float,acmgt1__sampler__sampler22_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 657, 40, percentage_max_float,acmgt1__sampler__sampler23_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 658, 44, percentage_max_float,acmgt1__sampler__sampler30_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 659, 48, percentage_max_float,acmgt1__sampler__sampler31_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 660, 52, percentage_max_float,acmgt1__sampler__sampler32_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 661, 56, percentage_max_float,acmgt1__sampler__sampler33_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 662, 60, percentage_max_float,acmgt1__sampler__sampler20_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 663, 64, percentage_max_float,acmgt1__sampler__sampler21_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 664, 68, percentage_max_float,acmgt1__sampler__sampler22_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 665, 72, percentage_max_float,acmgt1__sampler__sampler23_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 666, 76, percentage_max_float,acmgt1__sampler__sampler30_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 667, 80, percentage_max_float,acmgt1__sampler__sampler31_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 668, 84, percentage_max_float,acmgt1__sampler__sampler32_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 669, 88, percentage_max_float,acmgt1__sampler__sampler33_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_hdc_and_sf1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set HDCAndSF1";
   query->symbol_name = "HDCAndSF1";
   query->guid = "75fc20f8-8694-47f2-b67b-cbb35f697a8e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8101E0 },
         { .reg = 0x00009888, .val = 0x1EA101E0 },
         { .reg = 0x00009888, .val = 0x1EC101E0 },
         { .reg = 0x00009888, .val = 0x1EE101E0 },
         { .reg = 0x00009888, .val = 0x1F8101E0 },
         { .reg = 0x00009888, .val = 0x1FA101E0 },
         { .reg = 0x00009888, .val = 0x1FC101E0 },
         { .reg = 0x00009888, .val = 0x1FE101E0 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x08810011 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x08A10440 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0AC10011 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0AE10440 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810011 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10440 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10011 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10440 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000400FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x48031060 },
         { .reg = 0x00009888, .val = 0x4A030277 },
         { .reg = 0x00009888, .val = 0x4C030602 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__hdc_and_sf1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__hdc_and_sf1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__hdc_and_sf1__avg_gpu_core_frequency__max,acmgt1__hdc_and_sf1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__hdc_and_sf1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 670, 28, percentage_max_float,acmgt1__hdc_and_sf1__non_sampler_shader20_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 671, 32, percentage_max_float,acmgt1__hdc_and_sf1__non_sampler_shader21_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 672, 36, percentage_max_float,acmgt1__hdc_and_sf1__non_sampler_shader22_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 673, 40, percentage_max_float,acmgt1__hdc_and_sf1__non_sampler_shader23_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 674, 44, percentage_max_float,acmgt1__hdc_and_sf1__non_sampler_shader30_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 675, 48, percentage_max_float,acmgt1__hdc_and_sf1__non_sampler_shader31_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 676, 52, percentage_max_float,acmgt1__hdc_and_sf1__non_sampler_shader32_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 677, 56, percentage_max_float,acmgt1__hdc_and_sf1__non_sampler_shader33_access_stalled_on_l3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_hdc_and_sf2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Metric set HDCAndSF2";
   query->symbol_name = "HDCAndSF2";
   query->guid = "d5e02a31-fc87-4cdc-8136-4b19e00b7e94";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12056400 },
         { .reg = 0x00009888, .val = 0x13056400 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x0205001C },
         { .reg = 0x00009888, .val = 0x00060001 },
         { .reg = 0x00009888, .val = 0x0008000D },
         { .reg = 0x00009888, .val = 0x000A0005 },
         { .reg = 0x00009888, .val = 0x00010002 },
         { .reg = 0x00009888, .val = 0x000B0008 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x03050700 },
         { .reg = 0x00009888, .val = 0x01060002 },
         { .reg = 0x00009888, .val = 0x01080004 },
         { .reg = 0x00009888, .val = 0x010A0004 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x0C417000 },
         { .reg = 0x00009888, .val = 0x0C617000 },
         { .reg = 0x00009888, .val = 0x02410010 },
         { .reg = 0x00009888, .val = 0x14410180 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610010 },
         { .reg = 0x00009888, .val = 0x16610006 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040003 },
         { .reg = 0x00009888, .val = 0x0002000A },
         { .reg = 0x00009888, .val = 0x00030005 },
         { .reg = 0x00009888, .val = 0x0203F000 },
         { .reg = 0x00009888, .val = 0x0209E000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x2403F000 },
         { .reg = 0x00009888, .val = 0x46036F60 },
         { .reg = 0x00009888, .val = 0x2803F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__hdc_and_sf2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__hdc_and_sf2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__hdc_and_sf2__avg_gpu_core_frequency__max,acmgt1__hdc_and_sf2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__hdc_and_sf2__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 678, 28, percentage_max_float,acmgt1__hdc_and_sf2__poly2_data_ready__read);

      intel_perf_query_add_counter_float(query, 679, 32, percentage_max_float,acmgt1__hdc_and_sf2__poly3_data_ready__read);

      intel_perf_query_add_counter_float(query, 680, 36, percentage_max_float,acmgt1__hdc_and_sf2__gt_request_queue20_full__read);

      intel_perf_query_add_counter_float(query, 681, 40, percentage_max_float,acmgt1__hdc_and_sf2__gt_request_queue30_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_rasterizer_and_pixel_backend1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set RasterizerAndPixelBackend1";
   query->symbol_name = "RasterizerAndPixelBackend1";
   query->guid = "08858210-0dc3-452b-afee-e5c7811c01cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A056000 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x0C0B7000 },
         { .reg = 0x00009888, .val = 0x0E0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C701F },
         { .reg = 0x00009888, .val = 0x0E0C6000 },
         { .reg = 0x00009888, .val = 0x1B057000 },
         { .reg = 0x00009888, .val = 0x00038000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x020535D2 },
         { .reg = 0x00009888, .val = 0x0405003E },
         { .reg = 0x00009888, .val = 0x00060007 },
         { .reg = 0x00009888, .val = 0x00072800 },
         { .reg = 0x00009888, .val = 0x000803D5 },
         { .reg = 0x00009888, .val = 0x0208C000 },
         { .reg = 0x00009888, .val = 0x00090060 },
         { .reg = 0x00009888, .val = 0x000A2955 },
         { .reg = 0x00009888, .val = 0x020A4000 },
         { .reg = 0x00009888, .val = 0x00018018 },
         { .reg = 0x00009888, .val = 0x040B0200 },
         { .reg = 0x00009888, .val = 0x080B0400 },
         { .reg = 0x00009888, .val = 0x0A0B001F },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B8000 },
         { .reg = 0x00009888, .val = 0x00020060 },
         { .reg = 0x00009888, .val = 0x040C0200 },
         { .reg = 0x00009888, .val = 0x0A0C0400 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x11050DC0 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01068000 },
         { .reg = 0x00009888, .val = 0x03084000 },
         { .reg = 0x00009888, .val = 0x030A4000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x0001807F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x0E030C40 },
         { .reg = 0x00009888, .val = 0x10030E00 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x02044880 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02054440 },
         { .reg = 0x00009888, .val = 0x10080031 },
         { .reg = 0x00009888, .val = 0x12080038 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02088880 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F87F },
         { .reg = 0x00009888, .val = 0x00022AAA },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00031555 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2A033000 },
         { .reg = 0x00009888, .val = 0x48031068 },
         { .reg = 0x00009888, .val = 0x4A030653 },
         { .reg = 0x00009888, .val = 0x4C030465 },
         { .reg = 0x00009888, .val = 0x4E030023 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x440340C0 },
         { .reg = 0x00009888, .val = 0x2003F000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030206 },
         { .reg = 0x00009888, .val = 0x2403F000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000D950, .val = 0x00000300 },
         { .reg = 0x0000D954, .val = 0x0000FF9F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__rasterizer_and_pixel_backend1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__rasterizer_and_pixel_backend1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max,acmgt1__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__rasterizer_and_pixel_backend1__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 682, 28, percentage_max_float,acmgt1__rasterizer_and_pixel_backend1__rasterizer2_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 683, 32, percentage_max_float,acmgt1__rasterizer_and_pixel_backend1__rasterizer3_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 684, 36, percentage_max_float,acmgt1__rasterizer_and_pixel_backend1__pixel_data20_ready__read);

      intel_perf_query_add_counter_float(query, 685, 40, percentage_max_float,acmgt1__rasterizer_and_pixel_backend1__pixel_data21_ready__read);

      intel_perf_query_add_counter_float(query, 686, 44, percentage_max_float,acmgt1__rasterizer_and_pixel_backend1__ps_output10_available__read);

      intel_perf_query_add_counter_float(query, 687, 48, percentage_max_float,acmgt1__rasterizer_and_pixel_backend1__ps_output11_available__read);

      intel_perf_query_add_counter_float(query, 688, 52, percentage_max_float,acmgt1__rasterizer_and_pixel_backend1__pixel_values10_ready__read);

      intel_perf_query_add_counter_float(query, 689, 56, percentage_max_float,acmgt1__rasterizer_and_pixel_backend1__pixel_values11_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_rasterizer_and_pixel_backend2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Metric set RasterizerAndPixelBackend2";
   query->symbol_name = "RasterizerAndPixelBackend2";
   query->guid = "30b71e0c-55eb-49ed-8863-ee7db68ff1b1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A057000 },
         { .reg = 0x00009888, .val = 0x1B056000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x0D0B7000 },
         { .reg = 0x00009888, .val = 0x0F0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C701F },
         { .reg = 0x00009888, .val = 0x0F0C6000 },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x10050DC0 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00068000 },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x02084000 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x020A4000 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x030535D2 },
         { .reg = 0x00009888, .val = 0x0505003E },
         { .reg = 0x00009888, .val = 0x01060007 },
         { .reg = 0x00009888, .val = 0x01072800 },
         { .reg = 0x00009888, .val = 0x010803D5 },
         { .reg = 0x00009888, .val = 0x01090060 },
         { .reg = 0x00009888, .val = 0x010A2955 },
         { .reg = 0x00009888, .val = 0x01010018 },
         { .reg = 0x00009888, .val = 0x050B0200 },
         { .reg = 0x00009888, .val = 0x090B0400 },
         { .reg = 0x00009888, .val = 0x0B0B001F },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x01020060 },
         { .reg = 0x00009888, .val = 0x050C0200 },
         { .reg = 0x00009888, .val = 0x0B0C0400 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004807F },
         { .reg = 0x00009888, .val = 0x00022AAA },
         { .reg = 0x00009888, .val = 0x02028000 },
         { .reg = 0x00009888, .val = 0x00031555 },
         { .reg = 0x00009888, .val = 0x02034000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030C06 },
         { .reg = 0x00009888, .val = 0x4A030030 },
         { .reg = 0x00009888, .val = 0x4C030003 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009888, .val = 0x46030C00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001807F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x02044000 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02054000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000D950, .val = 0x00000300 },
         { .reg = 0x0000D954, .val = 0x0000FF9F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__rasterizer_and_pixel_backend2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__rasterizer_and_pixel_backend2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max,acmgt1__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__rasterizer_and_pixel_backend2__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 690, 28, percentage_max_float,acmgt1__rasterizer_and_pixel_backend2__rasterizer3_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 691, 32, percentage_max_float,acmgt1__rasterizer_and_pixel_backend2__rasterizer2_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 692, 36, percentage_max_float,acmgt1__rasterizer_and_pixel_backend2__pixel_data30_ready__read);

      intel_perf_query_add_counter_float(query, 693, 40, percentage_max_float,acmgt1__rasterizer_and_pixel_backend2__pixel_data31_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_tdl1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL1";
   query->symbol_name = "TDL1";
   query->guid = "3620f0df-42c6-4904-b395-5497f5a2ea4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810030 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10C00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10030 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10C00 },
         { .reg = 0x00009888, .val = 0x14E10CF4 },
         { .reg = 0x00009888, .val = 0x16E10C72 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810030 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10C00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10030 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10C00 },
         { .reg = 0x00009888, .val = 0x11E10CF4 },
         { .reg = 0x00009888, .val = 0x13E10C72 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40F80 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70055 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x0009F00C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x48031060 },
         { .reg = 0x00009888, .val = 0x4A030277 },
         { .reg = 0x00009888, .val = 0x4C030602 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031D4A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46031CE7 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__tdl1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__tdl1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__tdl1__avg_gpu_core_frequency__max,acmgt1__tdl1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__tdl1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 694, 28, percentage_max_float,acmgt1__tdl1__non_ps_thread20_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 695, 32, percentage_max_float,acmgt1__tdl1__non_ps_thread21_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 696, 36, percentage_max_float,acmgt1__tdl1__non_ps_thread22_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 697, 40, percentage_max_float,acmgt1__tdl1__non_ps_thread23_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 698, 44, percentage_max_float,acmgt1__tdl1__non_ps_thread30_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 699, 48, percentage_max_float,acmgt1__tdl1__non_ps_thread31_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 700, 52, percentage_max_float,acmgt1__tdl1__non_ps_thread32_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 701, 56, percentage_max_float,acmgt1__tdl1__non_ps_thread33_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 702, 60, percentage_max_float,acmgt1__tdl1__thread_header23_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 703, 64, percentage_max_float,acmgt1__tdl1__thread_header23_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 704, 68, percentage_max_float,acmgt1__tdl1__thread_header23_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 705, 72, percentage_max_float,acmgt1__tdl1__thread_header23_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 706, 76, percentage_max_float,acmgt1__tdl1__thread_header33_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 707, 80, percentage_max_float,acmgt1__tdl1__thread_header33_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 708, 84, percentage_max_float,acmgt1__tdl1__thread_header33_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 709, 88, percentage_max_float,acmgt1__tdl1__thread_header33_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_tdl2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "TDL2";
   query->symbol_name = "TDL2";
   query->guid = "28357a3a-a53b-4da4-a5b7-395dbfa501f1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x480300EA },
         { .reg = 0x00009888, .val = 0x4A030607 },
         { .reg = 0x00009888, .val = 0x4C031068 },
         { .reg = 0x00009888, .val = 0x4E030E77 },
         { .reg = 0x00009888, .val = 0x50030427 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030021 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46032940 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__tdl2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__tdl2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__tdl2__avg_gpu_core_frequency__max,acmgt1__tdl2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__tdl2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 710, 28, percentage_max_float,acmgt1__tdl2__ps_thread20_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 711, 32, percentage_max_float,acmgt1__tdl2__ps_thread21_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 712, 36, percentage_max_float,acmgt1__tdl2__ps_thread22_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 713, 40, percentage_max_float,acmgt1__tdl2__ps_thread23_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 714, 44, percentage_max_float,acmgt1__tdl2__ps_thread30_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 715, 48, percentage_max_float,acmgt1__tdl2__ps_thread31_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 716, 52, percentage_max_float,acmgt1__tdl2__ps_thread32_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 717, 56, percentage_max_float,acmgt1__tdl2__ps_thread33_ready_for_dispatch__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_tdl3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL3";
   query->symbol_name = "TDL3";
   query->guid = "262cf8cb-824e-4f48-bac4-6be3d8dda6a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x14810CF4 },
         { .reg = 0x00009888, .val = 0x16810C72 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x02875500 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x10A10CF4 },
         { .reg = 0x00009888, .val = 0x12A10C72 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A70055 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0CC10CF4 },
         { .reg = 0x00009888, .val = 0x0EC10C72 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x08E10CB1 },
         { .reg = 0x00009888, .val = 0x0AE10D33 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__tdl3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__tdl3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__tdl3__avg_gpu_core_frequency__max,acmgt1__tdl3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__tdl3__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 718, 28, percentage_max_float,acmgt1__tdl3__thread_header20_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 719, 32, percentage_max_float,acmgt1__tdl3__thread_header20_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 720, 36, percentage_max_float,acmgt1__tdl3__thread_header20_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 721, 40, percentage_max_float,acmgt1__tdl3__thread_header20_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 722, 44, percentage_max_float,acmgt1__tdl3__thread_header20_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 723, 48, percentage_max_float,acmgt1__tdl3__thread_header21_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 724, 52, percentage_max_float,acmgt1__tdl3__thread_header21_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 725, 56, percentage_max_float,acmgt1__tdl3__thread_header21_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 726, 60, percentage_max_float,acmgt1__tdl3__thread_header21_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 727, 64, percentage_max_float,acmgt1__tdl3__thread_header21_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 728, 68, percentage_max_float,acmgt1__tdl3__thread_header22_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 729, 72, percentage_max_float,acmgt1__tdl3__thread_header22_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 730, 76, percentage_max_float,acmgt1__tdl3__thread_header22_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 731, 80, percentage_max_float,acmgt1__tdl3__thread_header22_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 732, 84, percentage_max_float,acmgt1__tdl3__thread_header22_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 733, 88, percentage_max_float,acmgt1__tdl3__thread_header23_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_tdl4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL4";
   query->symbol_name = "TDL4";
   query->guid = "1e629e21-abd2-418e-a184-753977bb529b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x15810CF4 },
         { .reg = 0x00009888, .val = 0x17810C72 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x03875500 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x11A10CF4 },
         { .reg = 0x00009888, .val = 0x13A10C72 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A70055 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0DC10CF4 },
         { .reg = 0x00009888, .val = 0x0FC10C72 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x09E10CB1 },
         { .reg = 0x00009888, .val = 0x0BE10D33 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__tdl4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__tdl4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__tdl4__avg_gpu_core_frequency__max,acmgt1__tdl4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt1__tdl4__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 734, 28, percentage_max_float,acmgt1__tdl4__thread_header30_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 735, 32, percentage_max_float,acmgt1__tdl4__thread_header30_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 736, 36, percentage_max_float,acmgt1__tdl4__thread_header30_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 737, 40, percentage_max_float,acmgt1__tdl4__thread_header30_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 738, 44, percentage_max_float,acmgt1__tdl4__thread_header30_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 739, 48, percentage_max_float,acmgt1__tdl4__thread_header31_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 740, 52, percentage_max_float,acmgt1__tdl4__thread_header31_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 741, 56, percentage_max_float,acmgt1__tdl4__thread_header31_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 742, 60, percentage_max_float,acmgt1__tdl4__thread_header31_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 743, 64, percentage_max_float,acmgt1__tdl4__thread_header31_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 744, 68, percentage_max_float,acmgt1__tdl4__thread_header32_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 745, 72, percentage_max_float,acmgt1__tdl4__thread_header32_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 746, 76, percentage_max_float,acmgt1__tdl4__thread_header32_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 747, 80, percentage_max_float,acmgt1__tdl4__thread_header32_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 748, 84, percentage_max_float,acmgt1__tdl4__thread_header32_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 749, 88, percentage_max_float,acmgt1__tdl4__thread_header33_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "57f210de-b537-464a-af7b-7dfe2f3780c1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x0803000C },
         { .reg = 0x00009888, .val = 0x10030FF3 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__test_oa__avg_gpu_core_frequency__max,acmgt1__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 750, 24, NULL,acmgt1__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 751, 32, NULL,acmgt1__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 752, 40, NULL,acmgt1__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 753, 48, NULL,acmgt1__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 754, 56, NULL,acmgt1__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 755, 64, NULL,acmgt1__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 756, 72, NULL,acmgt1__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 757, 80, NULL,acmgt1__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 758, 88, NULL,acmgt1__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 759, 96, NULL,acmgt1__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_compute_overview_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 26);

   query->name = "ComputeOverview";
   query->symbol_name = "ComputeOverview";
   query->guid = "37b5b93b-6acf-4726-9b57-1a65fab22bb2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0000 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B6000 },
         { .reg = 0x00009888, .val = 0x0B0B1005 },
         { .reg = 0x00009888, .val = 0x092B6005 },
         { .reg = 0x00009888, .val = 0x0B2B1000 },
         { .reg = 0x00009888, .val = 0x094B6000 },
         { .reg = 0x00009888, .val = 0x0B4B1000 },
         { .reg = 0x00009888, .val = 0x096B6000 },
         { .reg = 0x00009888, .val = 0x0B6B1000 },
         { .reg = 0x00009888, .val = 0x090C6000 },
         { .reg = 0x00009888, .val = 0x0B0C1140 },
         { .reg = 0x00009888, .val = 0x092C6140 },
         { .reg = 0x00009888, .val = 0x0B2C1000 },
         { .reg = 0x00009888, .val = 0x094C6000 },
         { .reg = 0x00009888, .val = 0x0B4C1000 },
         { .reg = 0x00009888, .val = 0x096C6000 },
         { .reg = 0x00009888, .val = 0x0B6C1000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x112B000D },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x0F4B000D },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x0D6B000D },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x130C0340 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x112C0340 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x0F4C0340 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x0D6C0340 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
         { .reg = 0x0000E658, .val = 0x00009001 },
         { .reg = 0x0000E758, .val = 0x02001002 },
         { .reg = 0x0000E45C, .val = 0x0000A003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__compute_overview__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__compute_overview__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__compute_overview__avg_gpu_core_frequency__max,acmgt1__compute_overview__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 760, 24, acmgt1__compute_overview__l3_byte_read__max,acmgt1__compute_overview__l3_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 761, 32, acmgt1__compute_overview__l3_byte_write__max,acmgt1__compute_overview__l3_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt1__compute_overview__gpu_memory_byte_read__max,acmgt1__compute_overview__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt1__compute_overview__gpu_memory_byte_write__max,acmgt1__compute_overview__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt1__compute_overview__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt1__compute_overview__xve_stall__read);

      intel_perf_query_add_counter_uint64(query, 766, 64, acmgt1__compute_overview__xve_busy__max,acmgt1__compute_overview__xve_busy__read);

      intel_perf_query_add_counter_float(query, 767, 72, percentage_max_float,acmgt1__compute_overview__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 768, 80, NULL,acmgt1__compute_overview__xve_compute_thread_count__read);

      intel_perf_query_add_counter_uint64(query, 769, 88, NULL,acmgt1__compute_overview__xve_atomic_access_count__read);

      intel_perf_query_add_counter_uint64(query, 770, 96, NULL,acmgt1__compute_overview__xve_barrier_message_count__read);

      intel_perf_query_add_counter_uint64(query, 771, 104, acmgt1__compute_overview__xve_inst_executed_alu0_all__max,acmgt1__compute_overview__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 772, 112, acmgt1__compute_overview__xve_inst_executed_alu1_all__max,acmgt1__compute_overview__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 773, 120, acmgt1__compute_overview__xve_inst_executed_xmx_all__max,acmgt1__compute_overview__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 774, 128, acmgt1__compute_overview__xve_inst_executed_send_all__max,acmgt1__compute_overview__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 775, 136, acmgt1__compute_overview__xve_inst_executed_control_all__max,acmgt1__compute_overview__xve_inst_executed_control_all__read);

      intel_perf_query_add_counter_float(query, 776, 144, percentage_max_float,acmgt1__compute_overview__xve_pipe_alu0_and_alu1_active__read);

      intel_perf_query_add_counter_float(query, 777, 148, percentage_max_float,acmgt1__compute_overview__xve_pipe_alu0_and_xmx_active__read);

      intel_perf_query_add_counter_float(query, 778, 152, percentage_max_float,acmgt1__compute_overview__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 779, 156, percentage_max_float,acmgt1__compute_overview__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 780, 160, percentage_max_float,acmgt1__compute_overview__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 781, 164, percentage_max_float,acmgt1__compute_overview__xve_inst_executed_control_all_utilization__read);

      intel_perf_query_add_counter_float(query, 782, 168, percentage_max_float,acmgt1__compute_overview__xve_inst_executed_xmx_all_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_l1_profile_reads__xe_core0_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1ProfileReads";
   query->symbol_name = "L1ProfileReads_XeCore0";
   query->guid = "a2fe4388-0540-4550-b57e-6948cd7ab47a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870253 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870004 },
         { .reg = 0x00009888, .val = 0x0E870140 },
         { .reg = 0x00009888, .val = 0x108700C4 },
         { .reg = 0x00009888, .val = 0x12870042 },
         { .reg = 0x00009888, .val = 0x148703C0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890387 },
         { .reg = 0x00009888, .val = 0x08890248 },
         { .reg = 0x00009888, .val = 0x0A8902CA },
         { .reg = 0x00009888, .val = 0x0C89034C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870253 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870004 },
         { .reg = 0x00009888, .val = 0x0F870140 },
         { .reg = 0x00009888, .val = 0x118700C4 },
         { .reg = 0x00009888, .val = 0x13870042 },
         { .reg = 0x00009888, .val = 0x158703C0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890387 },
         { .reg = 0x00009888, .val = 0x09890248 },
         { .reg = 0x00009888, .val = 0x0B8902CA },
         { .reg = 0x00009888, .val = 0x0D89034C },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FE7F },
         { .reg = 0x0000DC00, .val = 0x0000001A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000032 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF9 },
         { .reg = 0x0000DC10, .val = 0x00000052 },
         { .reg = 0x0000DC14, .val = 0x0000FFF5 },
         { .reg = 0x0000DC18, .val = 0x00000092 },
         { .reg = 0x0000DC1C, .val = 0x0000FFED },
         { .reg = 0x0000DC20, .val = 0x00000112 },
         { .reg = 0x0000DC24, .val = 0x0000FFDD },
         { .reg = 0x0000DC28, .val = 0x00000212 },
         { .reg = 0x0000DC2C, .val = 0x0000FFBD },
         { .reg = 0x0000DC30, .val = 0x00000412 },
         { .reg = 0x0000DC34, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__l1_profile_reads__xe_core0__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__l1_profile_reads__xe_core0__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__l1_profile_reads__xe_core0__avg_gpu_core_frequency__max,acmgt1__l1_profile_reads__xe_core0__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 783, 24, acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max,acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 784, 32, acmgt1__l1_profile_reads__xe_core0__slm_byte_read__max,acmgt1__l1_profile_reads__xe_core0__slm_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_read__max,acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_write__max,acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt1__l1_profile_reads__xe_core0__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt1__l1_profile_reads__xe_core0__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 64, percentage_max_float,acmgt1__l1_profile_reads__xe_core0__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt1__l1_profile_reads__xe_core0__xve_busy__max,acmgt1__l1_profile_reads__xe_core0__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_l1_profile_reads__xe_core3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1ProfileReads";
   query->symbol_name = "L1ProfileReads_XeCore3";
   query->guid = "16bc63c3-d365-4bee-baf7-bafbc1aa7c2d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E70253 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70004 },
         { .reg = 0x00009888, .val = 0x0EE70140 },
         { .reg = 0x00009888, .val = 0x10E700C4 },
         { .reg = 0x00009888, .val = 0x12E70042 },
         { .reg = 0x00009888, .val = 0x14E703C0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90387 },
         { .reg = 0x00009888, .val = 0x08E90248 },
         { .reg = 0x00009888, .val = 0x0AE902CA },
         { .reg = 0x00009888, .val = 0x0CE9034C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E70253 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70004 },
         { .reg = 0x00009888, .val = 0x0FE70140 },
         { .reg = 0x00009888, .val = 0x11E700C4 },
         { .reg = 0x00009888, .val = 0x13E70042 },
         { .reg = 0x00009888, .val = 0x15E703C0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90387 },
         { .reg = 0x00009888, .val = 0x09E90248 },
         { .reg = 0x00009888, .val = 0x0BE902CA },
         { .reg = 0x00009888, .val = 0x0DE9034C },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FE7F },
         { .reg = 0x0000DC00, .val = 0x0000001A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000032 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF9 },
         { .reg = 0x0000DC10, .val = 0x00000052 },
         { .reg = 0x0000DC14, .val = 0x0000FFF5 },
         { .reg = 0x0000DC18, .val = 0x00000092 },
         { .reg = 0x0000DC1C, .val = 0x0000FFED },
         { .reg = 0x0000DC20, .val = 0x00000112 },
         { .reg = 0x0000DC24, .val = 0x0000FFDD },
         { .reg = 0x0000DC28, .val = 0x00000212 },
         { .reg = 0x0000DC2C, .val = 0x0000FFBD },
         { .reg = 0x0000DC30, .val = 0x00000412 },
         { .reg = 0x0000DC34, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__l1_profile_reads__xe_core3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__l1_profile_reads__xe_core3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__l1_profile_reads__xe_core3__avg_gpu_core_frequency__max,acmgt1__l1_profile_reads__xe_core3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 783, 24, acmgt1__l1_profile_reads__xe_core3__load_store_cache_byte_read__max,acmgt1__l1_profile_reads__xe_core3__load_store_cache_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 784, 32, acmgt1__l1_profile_reads__xe_core3__slm_byte_read__max,acmgt1__l1_profile_reads__xe_core3__slm_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_read__max,acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_write__max,acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt1__l1_profile_reads__xe_core3__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt1__l1_profile_reads__xe_core3__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 64, percentage_max_float,acmgt1__l1_profile_reads__xe_core3__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt1__l1_profile_reads__xe_core3__xve_busy__max,acmgt1__l1_profile_reads__xe_core3__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_l1_profile_slm_bank_conflicts__xe_core0_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "L1ProfileSlmBankConflicts";
   query->symbol_name = "L1ProfileSlmBankConflicts_XeCore0";
   query->guid = "28da4c17-4629-4111-a575-787a85100db9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__max,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 785, 24, NULL,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__slm_bank_conflict_count__read);

      intel_perf_query_add_counter_uint64(query, 762, 32, acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__max,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 40, acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__max,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 48, percentage_max_float,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 52, percentage_max_float,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 56, percentage_max_float,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 64, acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__max,acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_l1_profile_slm_bank_conflicts__xe_core3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "L1ProfileSlmBankConflicts";
   query->symbol_name = "L1ProfileSlmBankConflicts_XeCore3";
   query->guid = "825f82b5-486a-4ca2-96fa-f358871984b0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__max,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 785, 24, NULL,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__slm_bank_conflict_count__read);

      intel_perf_query_add_counter_uint64(query, 762, 32, acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__max,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 40, acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__max,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 48, percentage_max_float,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 52, percentage_max_float,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 56, percentage_max_float,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 64, acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__max,acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_l1_profile_writes__xe_core0_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1ProfileWrites";
   query->symbol_name = "L1ProfileWrites_XeCore0";
   query->guid = "5d58094c-105e-4562-b53d-68185319c794";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870012 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x0E870180 },
         { .reg = 0x00009888, .val = 0x10870105 },
         { .reg = 0x00009888, .val = 0x12870083 },
         { .reg = 0x00009888, .val = 0x14870001 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890380 },
         { .reg = 0x00009888, .val = 0x08890081 },
         { .reg = 0x00009888, .val = 0x0A890103 },
         { .reg = 0x00009888, .val = 0x0C890185 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870012 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870000 },
         { .reg = 0x00009888, .val = 0x0F870180 },
         { .reg = 0x00009888, .val = 0x11870105 },
         { .reg = 0x00009888, .val = 0x13870083 },
         { .reg = 0x00009888, .val = 0x15870001 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890380 },
         { .reg = 0x00009888, .val = 0x09890081 },
         { .reg = 0x00009888, .val = 0x0B890103 },
         { .reg = 0x00009888, .val = 0x0D890185 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FE7F },
         { .reg = 0x0000DC00, .val = 0x0000001A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000032 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF9 },
         { .reg = 0x0000DC10, .val = 0x00000052 },
         { .reg = 0x0000DC14, .val = 0x0000FFF5 },
         { .reg = 0x0000DC18, .val = 0x00000092 },
         { .reg = 0x0000DC1C, .val = 0x0000FFED },
         { .reg = 0x0000DC20, .val = 0x00000112 },
         { .reg = 0x0000DC24, .val = 0x0000FFDD },
         { .reg = 0x0000DC28, .val = 0x00000212 },
         { .reg = 0x0000DC2C, .val = 0x0000FFBD },
         { .reg = 0x0000DC30, .val = 0x00000412 },
         { .reg = 0x0000DC34, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__l1_profile_writes__xe_core0__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__l1_profile_writes__xe_core0__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__l1_profile_writes__xe_core0__avg_gpu_core_frequency__max,acmgt1__l1_profile_writes__xe_core0__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 786, 24, acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max,acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 787, 32, acmgt1__l1_profile_writes__xe_core0__slm_byte_write__max,acmgt1__l1_profile_writes__xe_core0__slm_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_read__max,acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_write__max,acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt1__l1_profile_writes__xe_core0__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt1__l1_profile_writes__xe_core0__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 64, percentage_max_float,acmgt1__l1_profile_writes__xe_core0__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt1__l1_profile_writes__xe_core0__xve_busy__max,acmgt1__l1_profile_writes__xe_core0__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_l1_profile_writes__xe_core3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1ProfileWrites";
   query->symbol_name = "L1ProfileWrites_XeCore3";
   query->guid = "3ce21cd6-fe3e-468f-ae53-07dbf73c45f9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E70012 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x0EE70180 },
         { .reg = 0x00009888, .val = 0x10E70105 },
         { .reg = 0x00009888, .val = 0x12E70083 },
         { .reg = 0x00009888, .val = 0x14E70001 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90380 },
         { .reg = 0x00009888, .val = 0x08E90081 },
         { .reg = 0x00009888, .val = 0x0AE90103 },
         { .reg = 0x00009888, .val = 0x0CE90185 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E70012 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70000 },
         { .reg = 0x00009888, .val = 0x0FE70180 },
         { .reg = 0x00009888, .val = 0x11E70105 },
         { .reg = 0x00009888, .val = 0x13E70083 },
         { .reg = 0x00009888, .val = 0x15E70001 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90380 },
         { .reg = 0x00009888, .val = 0x09E90081 },
         { .reg = 0x00009888, .val = 0x0BE90103 },
         { .reg = 0x00009888, .val = 0x0DE90185 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FE7F },
         { .reg = 0x0000DC00, .val = 0x0000001A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000032 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF9 },
         { .reg = 0x0000DC10, .val = 0x00000052 },
         { .reg = 0x0000DC14, .val = 0x0000FFF5 },
         { .reg = 0x0000DC18, .val = 0x00000092 },
         { .reg = 0x0000DC1C, .val = 0x0000FFED },
         { .reg = 0x0000DC20, .val = 0x00000112 },
         { .reg = 0x0000DC24, .val = 0x0000FFDD },
         { .reg = 0x0000DC28, .val = 0x00000212 },
         { .reg = 0x0000DC2C, .val = 0x0000FFBD },
         { .reg = 0x0000DC30, .val = 0x00000412 },
         { .reg = 0x0000DC34, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__l1_profile_writes__xe_core3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__l1_profile_writes__xe_core3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__l1_profile_writes__xe_core3__avg_gpu_core_frequency__max,acmgt1__l1_profile_writes__xe_core3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 786, 24, acmgt1__l1_profile_writes__xe_core3__load_store_cache_byte_write__max,acmgt1__l1_profile_writes__xe_core3__load_store_cache_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 787, 32, acmgt1__l1_profile_writes__xe_core3__slm_byte_write__max,acmgt1__l1_profile_writes__xe_core3__slm_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_read__max,acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_write__max,acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt1__l1_profile_writes__xe_core3__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt1__l1_profile_writes__xe_core3__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 64, percentage_max_float,acmgt1__l1_profile_writes__xe_core3__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt1__l1_profile_writes__xe_core3__xve_busy__max,acmgt1__l1_profile_writes__xe_core3__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_dataport_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "DataportReads";
   query->symbol_name = "DataportReads";
   query->guid = "54d0193f-f8e0-4b81-99ba-e73a23fd9418";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C0800CA },
         { .reg = 0x00009888, .val = 0x0203F000 },
         { .reg = 0x00009888, .val = 0x08085800 },
         { .reg = 0x00009888, .val = 0x0A08001E },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02095000 },
         { .reg = 0x00009888, .val = 0x020A5000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B000 },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B695 },
         { .reg = 0x00009888, .val = 0x12E1A000 },
         { .reg = 0x00009888, .val = 0x14E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x10810617 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830A00 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x00840330 },
         { .reg = 0x00009888, .val = 0x00860500 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00870500 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x0EA106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A000 },
         { .reg = 0x00009888, .val = 0x02A300A0 },
         { .reg = 0x00009888, .val = 0x00A40CC0 },
         { .reg = 0x00009888, .val = 0x00A65000 },
         { .reg = 0x00009888, .val = 0x02A60050 },
         { .reg = 0x00009888, .val = 0x00A75000 },
         { .reg = 0x00009888, .val = 0x02A70050 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3000A },
         { .reg = 0x00009888, .val = 0x02C30A00 },
         { .reg = 0x00009888, .val = 0x00C43003 },
         { .reg = 0x00009888, .val = 0x00C60005 },
         { .reg = 0x00009888, .val = 0x02C60500 },
         { .reg = 0x00009888, .val = 0x00C70005 },
         { .reg = 0x00009888, .val = 0x02C70500 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x0AE10656 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E300A0 },
         { .reg = 0x00009888, .val = 0x02E3A000 },
         { .reg = 0x00009888, .val = 0x00E4C00C },
         { .reg = 0x00009888, .val = 0x00E60050 },
         { .reg = 0x00009888, .val = 0x02E65000 },
         { .reg = 0x00009888, .val = 0x00E70050 },
         { .reg = 0x00009888, .val = 0x02E75000 },
         { .reg = 0x00009888, .val = 0x0007005A },
         { .reg = 0x00009888, .val = 0x02075A00 },
         { .reg = 0x00009888, .val = 0x0008FA00 },
         { .reg = 0x00009888, .val = 0x020800FA },
         { .reg = 0x00009888, .val = 0x0009F00F },
         { .reg = 0x00009888, .val = 0x000A55AA },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010CC0 },
         { .reg = 0x00009888, .val = 0x000B5000 },
         { .reg = 0x00009888, .val = 0x020B0050 },
         { .reg = 0x00009888, .val = 0x00023003 },
         { .reg = 0x00009888, .val = 0x000C0005 },
         { .reg = 0x00009888, .val = 0x020C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B000 },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B695 },
         { .reg = 0x00009888, .val = 0x13E1A000 },
         { .reg = 0x00009888, .val = 0x15E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x11810617 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830A00 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840330 },
         { .reg = 0x00009888, .val = 0x01860500 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01870500 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x0FA106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40CC0 },
         { .reg = 0x00009888, .val = 0x01A65000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x01A75000 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3000A },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43003 },
         { .reg = 0x00009888, .val = 0x01C60005 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x01C70005 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x0BE10656 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E300A0 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C00C },
         { .reg = 0x00009888, .val = 0x01E60050 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x01E70050 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0107005A },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x0108FA00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F00F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010CC0 },
         { .reg = 0x00009888, .val = 0x010B5000 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023003 },
         { .reg = 0x00009888, .val = 0x010C0005 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000DC00, .val = 0x0000000A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000022 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC10, .val = 0x00000082 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000DC18, .val = 0x00000202 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000DC20, .val = 0x00000802 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000DC28, .val = 0x00002002 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
         { .reg = 0x0000DC30, .val = 0x00008002 },
         { .reg = 0x0000DC34, .val = 0x0000CFFF },
         { .reg = 0x0000DC38, .val = 0x00020002 },
         { .reg = 0x0000DC3C, .val = 0x00003FFF },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__dataport_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__dataport_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__dataport_reads__avg_gpu_core_frequency__max,acmgt1__dataport_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 788, 24, acmgt1__dataport_reads__dataport_byte_read__max,acmgt1__dataport_reads__dataport_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 789, 32, acmgt1__dataport_reads__host_to_gpumem_byte_read__max,acmgt1__dataport_reads__host_to_gpumem_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 790, 40, acmgt1__dataport_reads__host_to_gpumem_byte_write__max,acmgt1__dataport_reads__host_to_gpumem_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 48, acmgt1__dataport_reads__gpu_memory_byte_read__max,acmgt1__dataport_reads__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 56, acmgt1__dataport_reads__gpu_memory_byte_write__max,acmgt1__dataport_reads__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 64, percentage_max_float,acmgt1__dataport_reads__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 68, percentage_max_float,acmgt1__dataport_reads__xve_stall__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt1__dataport_reads__xve_busy__max,acmgt1__dataport_reads__xve_busy__read);

      intel_perf_query_add_counter_float(query, 767, 80, percentage_max_float,acmgt1__dataport_reads__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 768, 88, NULL,acmgt1__dataport_reads__xve_compute_thread_count__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_dataport_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "DataportWrites";
   query->symbol_name = "DataportWrites";
   query->guid = "17982512-46b0-4b58-9e8d-d59b5bf8b3f5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C080005 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00080292 },
         { .reg = 0x00009888, .val = 0x00090005 },
         { .reg = 0x00009888, .val = 0x000A0005 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x16030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0C810016 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830200 },
         { .reg = 0x00009888, .val = 0x00840010 },
         { .reg = 0x00009888, .val = 0x00860100 },
         { .reg = 0x00009888, .val = 0x00870100 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0CA10580 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30800 },
         { .reg = 0x00009888, .val = 0x00A40020 },
         { .reg = 0x00009888, .val = 0x00A60400 },
         { .reg = 0x00009888, .val = 0x00A70400 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0EC10016 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C32000 },
         { .reg = 0x00009888, .val = 0x00C40040 },
         { .reg = 0x00009888, .val = 0x00C61000 },
         { .reg = 0x00009888, .val = 0x00C71000 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0EE10580 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E38000 },
         { .reg = 0x00009888, .val = 0x00E40080 },
         { .reg = 0x00009888, .val = 0x00E64000 },
         { .reg = 0x00009888, .val = 0x00E74000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x06030000 },
         { .reg = 0x00009888, .val = 0x08030000 },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x0E030000 },
         { .reg = 0x00009888, .val = 0x10030000 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00076000 },
         { .reg = 0x00009888, .val = 0x00080EFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900C0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF2F },
         { .reg = 0x00009888, .val = 0x000B04AA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020040 },
         { .reg = 0x00009888, .val = 0x000C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x17030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810016 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10580 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10016 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10580 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030000 },
         { .reg = 0x00009888, .val = 0x07030000 },
         { .reg = 0x00009888, .val = 0x09030000 },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x0F030000 },
         { .reg = 0x00009888, .val = 0x11030000 },
         { .reg = 0x00009888, .val = 0x13030000 },
         { .reg = 0x00009888, .val = 0x15030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080EFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF2F },
         { .reg = 0x00009888, .val = 0x010B04AA },
         { .reg = 0x00009888, .val = 0x030BAAAA },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C3000 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x070C0000 },
         { .reg = 0x00009888, .val = 0x130C0380 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0180 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00065555 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0FF },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__dataport_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__dataport_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__dataport_writes__avg_gpu_core_frequency__max,acmgt1__dataport_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 791, 24, acmgt1__dataport_writes__dataport_byte_write__max,acmgt1__dataport_writes__dataport_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 792, 32, NULL,acmgt1__dataport_writes__sampler_l3_read__read);

      intel_perf_query_add_counter_uint64(query, 793, 40, acmgt1__dataport_writes__sysmem_byte_read__max,acmgt1__dataport_writes__sysmem_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 794, 48, acmgt1__dataport_writes__sysmem_byte_write__max,acmgt1__dataport_writes__sysmem_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 56, acmgt1__dataport_writes__gpu_memory_byte_read__max,acmgt1__dataport_writes__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 64, acmgt1__dataport_writes__gpu_memory_byte_write__max,acmgt1__dataport_writes__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 72, percentage_max_float,acmgt1__dataport_writes__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 76, percentage_max_float,acmgt1__dataport_writes__xve_stall__read);

      intel_perf_query_add_counter_uint64(query, 766, 80, acmgt1__dataport_writes__xve_busy__max,acmgt1__dataport_writes__xve_busy__read);

      intel_perf_query_add_counter_float(query, 767, 88, percentage_max_float,acmgt1__dataport_writes__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 768, 96, NULL,acmgt1__dataport_writes__xve_compute_thread_count__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 25);

   query->name = "Ext1";
   query->symbol_name = "Ext1";
   query->guid = "480895b0-8013-4be1-8bbf-fc3f1ad2e97f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C080005 },
         { .reg = 0x00009888, .val = 0x0003FFF0 },
         { .reg = 0x00009888, .val = 0x0203FFFF },
         { .reg = 0x00009888, .val = 0x04080292 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x00095EF0 },
         { .reg = 0x00009888, .val = 0x0209BBBA },
         { .reg = 0x00009888, .val = 0x000A5000 },
         { .reg = 0x00009888, .val = 0x48030400 },
         { .reg = 0x00009888, .val = 0x4A030020 },
         { .reg = 0x00009888, .val = 0x4C030402 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030020 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030842 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x1A410140 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x1A610140 },
         { .reg = 0x00009888, .val = 0x024100C8 },
         { .reg = 0x00009888, .val = 0x0A410180 },
         { .reg = 0x00009888, .val = 0x0E410380 },
         { .reg = 0x00009888, .val = 0x10410005 },
         { .reg = 0x00009888, .val = 0x1241000F },
         { .reg = 0x00009888, .val = 0x1441000D },
         { .reg = 0x00009888, .val = 0x1641000C },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610106 },
         { .reg = 0x00009888, .val = 0x08610180 },
         { .reg = 0x00009888, .val = 0x0A61000D },
         { .reg = 0x00009888, .val = 0x0C61000E },
         { .reg = 0x00009888, .val = 0x106101C0 },
         { .reg = 0x00009888, .val = 0x12610140 },
         { .reg = 0x00009888, .val = 0x14610100 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext1__avg_gpu_core_frequency__max,acmgt1__ext1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 795, 24, NULL,acmgt1__ext1__gpu_memory_byte_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 796, 32, NULL,acmgt1__ext1__gpu_memory_byte_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 797, 40, NULL,acmgt1__ext1__gpu_memory_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 798, 48, NULL,acmgt1__ext1__gpu_memory_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 799, 56, NULL,acmgt1__ext1__gpu_memory_write__read);

      intel_perf_query_add_counter_uint64(query, 800, 64, NULL,acmgt1__ext1__gpu_memory_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 801, 72, NULL,acmgt1__ext1__gpu_memory_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 802, 80, NULL,acmgt1__ext1__gpu_memory_read__read);

      intel_perf_query_add_counter_uint64(query, 803, 88, NULL,acmgt1__ext1__gpu_memory_byte_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 804, 96, NULL,acmgt1__ext1__gpu_memory_byte_read_sqidi1__read);

      intel_perf_query_add_counter_float(query, 805, 104, percentage_max_float,acmgt1__ext1__gpu_memory_active_sqidi0__read);

      intel_perf_query_add_counter_float(query, 806, 108, percentage_max_float,acmgt1__ext1__gpu_memory_active_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 762, 112, acmgt1__ext1__gpu_memory_byte_read__max,acmgt1__ext1__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 120, acmgt1__ext1__gpu_memory_byte_write__max,acmgt1__ext1__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 807, 128, NULL,acmgt1__ext1__sysmem_transaction_write__read);

      intel_perf_query_add_counter_uint64(query, 808, 136, NULL,acmgt1__ext1__sysmem_transaction_read__read);

      intel_perf_query_add_counter_float(query, 809, 144, NULL,acmgt1__ext1__gpu_memory_byte_read_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 810, 148, NULL,acmgt1__ext1__gpu_memory_byte_read_bw_sqidi1__read);

      intel_perf_query_add_counter_float(query, 811, 152, NULL,acmgt1__ext1__gpu_memory_byte_write_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 812, 156, NULL,acmgt1__ext1__gpu_memory_byte_write_bw_sqidi1__read);

      intel_perf_query_add_counter_float(query, 813, 160, NULL,acmgt1__ext1__gpu_memory_byte_read_bw__read);

      intel_perf_query_add_counter_float(query, 814, 164, NULL,acmgt1__ext1__gpu_memory_byte_write_bw__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext2";
   query->symbol_name = "Ext2";
   query->guid = "b899d843-d8ce-4803-8174-f2bf1107de00";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x16410340 },
         { .reg = 0x00009888, .val = 0x10420251 },
         { .reg = 0x00009888, .val = 0x16610342 },
         { .reg = 0x00009888, .val = 0x10620251 },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x14410080 },
         { .reg = 0x00009888, .val = 0x0041030C },
         { .reg = 0x00009888, .val = 0x02420207 },
         { .reg = 0x00009888, .val = 0x08420185 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x02610000 },
         { .reg = 0x00009888, .val = 0x006100F0 },
         { .reg = 0x00009888, .val = 0x04620185 },
         { .reg = 0x00009888, .val = 0x06620207 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0003FFF0 },
         { .reg = 0x00009888, .val = 0x0203F00F },
         { .reg = 0x00009888, .val = 0x0009FFA0 },
         { .reg = 0x00009888, .val = 0x0209E00A },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x46030420 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext2__avg_gpu_core_frequency__max,acmgt1__ext2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 815, 24, percentage_max_float,acmgt1__ext2__gpu_memory_request_queue_full_sqidi0__read);

      intel_perf_query_add_counter_float(query, 816, 28, percentage_max_float,acmgt1__ext2__gpu_memory_request_queue_full_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 817, 32, NULL,acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 818, 40, NULL,acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 819, 48, NULL,acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 820, 56, NULL,acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext3";
   query->symbol_name = "Ext3";
   query->guid = "59e0ed29-cd2d-43ee-bf49-e4637e8ef9ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C0800CA },
         { .reg = 0x00009888, .val = 0x0003F000 },
         { .reg = 0x00009888, .val = 0x0203FF00 },
         { .reg = 0x00009888, .val = 0x040803D6 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x00095000 },
         { .reg = 0x00009888, .val = 0x0209FA00 },
         { .reg = 0x00009888, .val = 0x000A5000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030400 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030421 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1042000C },
         { .reg = 0x00009888, .val = 0x1062000C },
         { .reg = 0x00009888, .val = 0x00413000 },
         { .reg = 0x00009888, .val = 0x0C420102 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x0061C000 },
         { .reg = 0x00009888, .val = 0x0E620102 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext3__avg_gpu_core_frequency__max,acmgt1__ext3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 821, 24, NULL,acmgt1__ext3__gpu_memory_32_b_transaction_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 822, 32, NULL,acmgt1__ext3__gpu_memory_64_b_transaction_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 823, 40, NULL,acmgt1__ext3__gpu_memory_32_b_transaction_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 824, 48, NULL,acmgt1__ext3__gpu_memory_64_b_transaction_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 825, 56, NULL,acmgt1__ext3__host_to_gpumem_transaction_read__read);

      intel_perf_query_add_counter_uint64(query, 826, 64, NULL,acmgt1__ext3__host_to_gpumem_transaction_write__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext4";
   query->symbol_name = "Ext4";
   query->guid = "475c650e-1045-45dc-a280-3365f7af8f8c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x0B0B6005 },
         { .reg = 0x00009888, .val = 0x092B1005 },
         { .reg = 0x00009888, .val = 0x0B2B6000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x0B4B6000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x0B6B6000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x0B0C6140 },
         { .reg = 0x00009888, .val = 0x092C1140 },
         { .reg = 0x00009888, .val = 0x0B2C6000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x0B4C6000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x0B6C6000 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x112B000D },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x0F4B000D },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x0D6B000D },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x130C0340 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x112C0340 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x0F4C0340 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x0D6C0340 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C03020A },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030801 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext4__avg_gpu_core_frequency__max,acmgt1__ext4__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 827, 24, NULL,acmgt1__ext4__l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 828, 32, NULL,acmgt1__ext4__l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 829, 40, NULL,acmgt1__ext4__l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 830, 48, NULL,acmgt1__ext4__l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 831, 56, NULL,acmgt1__ext4__l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 832, 64, NULL,acmgt1__ext4__l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 833, 72, NULL,acmgt1__ext4__l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 834, 80, NULL,acmgt1__ext4__l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 835, 88, NULL,acmgt1__ext4__l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 836, 96, NULL,acmgt1__ext4__l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 837, 104, NULL,acmgt1__ext4__l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 838, 112, NULL,acmgt1__ext4__l3_write_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 839, 120, NULL,acmgt1__ext4__l3_write_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 840, 128, NULL,acmgt1__ext4__l3_write_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 841, 136, NULL,acmgt1__ext4__l3_write_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 842, 144, NULL,acmgt1__ext4__l3_write_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext5";
   query->symbol_name = "Ext5";
   query->guid = "b7d7a874-19d8-48e6-bf54-f859a994b0a4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0003 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C00C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0003 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0003 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0003 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C00C0 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C00C0 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C00C0 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C03020A },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030801 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext5__avg_gpu_core_frequency__max,acmgt1__ext5__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 843, 24, NULL,acmgt1__ext5__dataport_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 844, 32, NULL,acmgt1__ext5__dataport_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 845, 40, NULL,acmgt1__ext5__dataport_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 846, 48, NULL,acmgt1__ext5__dataport_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 847, 56, NULL,acmgt1__ext5__dataport_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 848, 64, NULL,acmgt1__ext5__dataport_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 849, 72, NULL,acmgt1__ext5__dataport_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 850, 80, NULL,acmgt1__ext5__dataport_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 851, 88, NULL,acmgt1__ext5__dataport_l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 852, 96, NULL,acmgt1__ext5__dataport_l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 853, 104, NULL,acmgt1__ext5__dataport_l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 854, 112, NULL,acmgt1__ext5__dataport_l3_write_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 855, 120, NULL,acmgt1__ext5__dataport_l3_write_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 856, 128, NULL,acmgt1__ext5__dataport_l3_write_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 857, 136, NULL,acmgt1__ext5__dataport_l3_write_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 858, 144, NULL,acmgt1__ext5__dataport_l3_write_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext6";
   query->symbol_name = "Ext6";
   query->guid = "f1a94d28-672b-41a6-9ab9-e2040200d28a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2001 },
         { .reg = 0x00009888, .val = 0x114B2000 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2040 },
         { .reg = 0x00009888, .val = 0x114C2000 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0001 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0001 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0001 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0040 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0040 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0040 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x50030800 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext6__avg_gpu_core_frequency__max,acmgt1__ext6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 859, 24, NULL,acmgt1__ext6__l3_hit_l3_bank0__read);

      intel_perf_query_add_counter_uint64(query, 860, 32, NULL,acmgt1__ext6__l3_hit_l3_bank1__read);

      intel_perf_query_add_counter_uint64(query, 861, 40, NULL,acmgt1__ext6__l3_hit_l3_bank2__read);

      intel_perf_query_add_counter_uint64(query, 862, 48, NULL,acmgt1__ext6__l3_hit_l3_bank3__read);

      intel_perf_query_add_counter_uint64(query, 863, 56, NULL,acmgt1__ext6__l3_hit_l3_bank4__read);

      intel_perf_query_add_counter_uint64(query, 864, 64, NULL,acmgt1__ext6__l3_hit_l3_bank5__read);

      intel_perf_query_add_counter_uint64(query, 865, 72, NULL,acmgt1__ext6__l3_hit_l3_bank6__read);

      intel_perf_query_add_counter_uint64(query, 866, 80, NULL,acmgt1__ext6__l3_hit_l3_bank7__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext7";
   query->symbol_name = "Ext7";
   query->guid = "31d119ed-a150-4b52-9206-3f9832e275ea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x112B000E },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x112C0380 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0026 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x130B000E },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0026 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0026 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x0F4B000E },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0026 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x0D6B000E },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0026 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x130C0380 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0026 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0026 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x0F4C0380 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0026 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x0D6C0380 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C03020A },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030801 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext7__avg_gpu_core_frequency__max,acmgt1__ext7__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 867, 24, NULL,acmgt1__ext7__sampler_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 868, 32, NULL,acmgt1__ext7__sampler_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 869, 40, NULL,acmgt1__ext7__sampler_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 870, 48, NULL,acmgt1__ext7__sampler_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 871, 56, NULL,acmgt1__ext7__sampler_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 872, 64, NULL,acmgt1__ext7__sampler_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 873, 72, NULL,acmgt1__ext7__sampler_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 874, 80, NULL,acmgt1__ext7__sampler_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 875, 88, NULL,acmgt1__ext7__sampler_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 876, 96, NULL,acmgt1__ext7__sampler_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 877, 104, NULL,acmgt1__ext7__sampler_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 878, 112, NULL,acmgt1__ext7__sampler_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 879, 120, NULL,acmgt1__ext7__sampler_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 880, 128, NULL,acmgt1__ext7__sampler_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 881, 136, NULL,acmgt1__ext7__sampler_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 882, 144, NULL,acmgt1__ext7__sampler_l3_hit_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext8";
   query->symbol_name = "Ext8";
   query->guid = "4eb14f16-d2ac-46d3-b974-e413430fddec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x092B0002 },
         { .reg = 0x00009888, .val = 0x112B000F },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x092C0080 },
         { .reg = 0x00009888, .val = 0x112C03C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0026 },
         { .reg = 0x00009888, .val = 0x0B0B0002 },
         { .reg = 0x00009888, .val = 0x130B000F },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0026 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0026 },
         { .reg = 0x00009888, .val = 0x074B0002 },
         { .reg = 0x00009888, .val = 0x0F4B000F },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0026 },
         { .reg = 0x00009888, .val = 0x056B0002 },
         { .reg = 0x00009888, .val = 0x0D6B000F },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0026 },
         { .reg = 0x00009888, .val = 0x0B0C0080 },
         { .reg = 0x00009888, .val = 0x130C03C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0026 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0026 },
         { .reg = 0x00009888, .val = 0x074C0080 },
         { .reg = 0x00009888, .val = 0x0F4C03C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0026 },
         { .reg = 0x00009888, .val = 0x056C0080 },
         { .reg = 0x00009888, .val = 0x0D6C03C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C03020A },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030801 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext8__avg_gpu_core_frequency__max,acmgt1__ext8__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 883, 24, NULL,acmgt1__ext8__icache_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 884, 32, NULL,acmgt1__ext8__icache_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 885, 40, NULL,acmgt1__ext8__icache_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 886, 48, NULL,acmgt1__ext8__icache_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 887, 56, NULL,acmgt1__ext8__icache_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 888, 64, NULL,acmgt1__ext8__icache_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 889, 72, NULL,acmgt1__ext8__icache_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 890, 80, NULL,acmgt1__ext8__icache_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 891, 88, NULL,acmgt1__ext8__icache_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 892, 96, NULL,acmgt1__ext8__icache_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 893, 104, NULL,acmgt1__ext8__icache_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 894, 112, NULL,acmgt1__ext8__icache_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 895, 120, NULL,acmgt1__ext8__icache_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 896, 128, NULL,acmgt1__ext8__icache_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 897, 136, NULL,acmgt1__ext8__icache_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 898, 144, NULL,acmgt1__ext8__icache_l3_hit_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext9";
   query->symbol_name = "Ext9";
   query->guid = "b875dedd-f121-4f89-b02f-ff2c873e2543";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830D00 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30034 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30D00 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30034 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830D00 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30034 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30D00 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30034 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031C43 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x46032808 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext9__avg_gpu_core_frequency__max,acmgt1__ext9__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 899, 24, percentage_max_float,acmgt1__ext9__sampler_busy_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 900, 28, percentage_max_float,acmgt1__ext9__sampler_busy_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 901, 32, percentage_max_float,acmgt1__ext9__sampler_busy_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 902, 36, percentage_max_float,acmgt1__ext9__sampler_busy_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 903, 40, percentage_max_float,acmgt1__ext9__sampler_busy_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 904, 44, percentage_max_float,acmgt1__ext9__sampler_busy_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 905, 48, percentage_max_float,acmgt1__ext9__sampler_busy_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 906, 52, percentage_max_float,acmgt1__ext9__sampler_busy_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext10";
   query->symbol_name = "Ext10";
   query->guid = "691b6a0d-d3d7-4b5e-a70e-d8232722cddf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x0F4B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x0F4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C03020A },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030801 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext10__avg_gpu_core_frequency__max,acmgt1__ext10__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 907, 24, NULL,acmgt1__ext10__dataport_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 908, 32, NULL,acmgt1__ext10__dataport_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 909, 40, NULL,acmgt1__ext10__dataport_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 910, 48, NULL,acmgt1__ext10__dataport_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 911, 56, NULL,acmgt1__ext10__dataport_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 912, 64, NULL,acmgt1__ext10__dataport_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 913, 72, NULL,acmgt1__ext10__dataport_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 914, 80, NULL,acmgt1__ext10__dataport_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 915, 88, NULL,acmgt1__ext10__color_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 916, 96, NULL,acmgt1__ext10__color_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 917, 104, NULL,acmgt1__ext10__color_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 918, 112, NULL,acmgt1__ext10__color_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 919, 120, NULL,acmgt1__ext10__color_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 920, 128, NULL,acmgt1__ext10__color_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 921, 136, NULL,acmgt1__ext10__color_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 922, 144, NULL,acmgt1__ext10__color_l3_hit_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext11";
   query->symbol_name = "Ext11";
   query->guid = "3c626d93-4368-4115-a21d-8fd8cd10e8fa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x092B1004 },
         { .reg = 0x00009888, .val = 0x112B000D },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x092C1100 },
         { .reg = 0x00009888, .val = 0x112C0340 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0062 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0062 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0062 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x0F4B000D },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0062 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x0D6B000D },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0062 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x130C0340 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0062 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0062 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x0F4C0340 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0062 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x0D6C0340 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C03020A },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030801 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext11__avg_gpu_core_frequency__max,acmgt1__ext11__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 923, 24, NULL,acmgt1__ext11__z_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 924, 32, NULL,acmgt1__ext11__z_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 925, 40, NULL,acmgt1__ext11__z_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 926, 48, NULL,acmgt1__ext11__z_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 927, 56, NULL,acmgt1__ext11__z_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 928, 64, NULL,acmgt1__ext11__z_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 929, 72, NULL,acmgt1__ext11__z_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 930, 80, NULL,acmgt1__ext11__z_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 931, 88, NULL,acmgt1__ext11__l3_atomic_access_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 932, 96, NULL,acmgt1__ext11__l3_atomic_access_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 933, 104, NULL,acmgt1__ext11__l3_atomic_access_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 934, 112, NULL,acmgt1__ext11__l3_atomic_access_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 935, 120, NULL,acmgt1__ext11__l3_atomic_access_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 936, 128, NULL,acmgt1__ext11__l3_atomic_access_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 937, 136, NULL,acmgt1__ext11__l3_atomic_access_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 938, 144, NULL,acmgt1__ext11__l3_atomic_access_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext12";
   query->symbol_name = "Ext12";
   query->guid = "4678846c-99cd-4a3f-acb4-8f055f48da56";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C03020A },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030801 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext12__avg_gpu_core_frequency__max,acmgt1__ext12__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 939, 24, percentage_max_float,acmgt1__ext12__l3_input_available_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 940, 28, percentage_max_float,acmgt1__ext12__l3_input_available_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 941, 32, percentage_max_float,acmgt1__ext12__l3_input_available_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 942, 36, percentage_max_float,acmgt1__ext12__l3_input_available_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 943, 40, percentage_max_float,acmgt1__ext12__l3_input_available_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 944, 44, percentage_max_float,acmgt1__ext12__l3_input_available_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 945, 48, percentage_max_float,acmgt1__ext12__l3_input_available_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 946, 52, percentage_max_float,acmgt1__ext12__l3_input_available_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 947, 56, percentage_max_float,acmgt1__ext12__l3_output_ready_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 948, 60, percentage_max_float,acmgt1__ext12__l3_output_ready_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 949, 64, percentage_max_float,acmgt1__ext12__l3_output_ready_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 950, 68, percentage_max_float,acmgt1__ext12__l3_output_ready_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 951, 72, percentage_max_float,acmgt1__ext12__l3_output_ready_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 952, 76, percentage_max_float,acmgt1__ext12__l3_output_ready_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 953, 80, percentage_max_float,acmgt1__ext12__l3_output_ready_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 954, 84, percentage_max_float,acmgt1__ext12__l3_output_ready_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext13";
   query->symbol_name = "Ext13";
   query->guid = "04d1f1c5-17e5-4104-b5a1-d62337b681b9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B1000 },
         { .reg = 0x00009888, .val = 0x112B1000 },
         { .reg = 0x00009888, .val = 0x114B1000 },
         { .reg = 0x00009888, .val = 0x116B1000 },
         { .reg = 0x00009888, .val = 0x110C1000 },
         { .reg = 0x00009888, .val = 0x112C1000 },
         { .reg = 0x00009888, .val = 0x114C1000 },
         { .reg = 0x00009888, .val = 0x116C1183 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x070B0183 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0B2B0183 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0183 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0183 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x050C0183 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0183 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0D4C0183 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x020200F0 },
         { .reg = 0x00009888, .val = 0x02030A05 },
         { .reg = 0x00009888, .val = 0x0204FA5A },
         { .reg = 0x00009888, .val = 0x000500A0 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x00060A05 },
         { .reg = 0x00009888, .val = 0x00070033 },
         { .reg = 0x00009888, .val = 0x0008F5A5 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00090033 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030E01 },
         { .reg = 0x00009888, .val = 0x4A030070 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46031080 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext13__avg_gpu_core_frequency__max,acmgt1__ext13__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 955, 24, percentage_max_float,acmgt1__ext13__l3_superq_full_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 956, 28, percentage_max_float,acmgt1__ext13__l3_superq_full_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 957, 32, percentage_max_float,acmgt1__ext13__l3_superq_full_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 958, 36, percentage_max_float,acmgt1__ext13__l3_superq_full_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 959, 40, percentage_max_float,acmgt1__ext13__l3_superq_full_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 960, 44, percentage_max_float,acmgt1__ext13__l3_superq_full_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 961, 48, percentage_max_float,acmgt1__ext13__l3_superq_full_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 962, 52, percentage_max_float,acmgt1__ext13__l3_superq_full_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext14";
   query->symbol_name = "Ext14";
   query->guid = "9312e21f-5d97-4058-a2fc-c7497c18f0a1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x50030800 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032801 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x460304E1 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext14__avg_gpu_core_frequency__max,acmgt1__ext14__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 963, 24, percentage_max_float,acmgt1__ext14__l3_busy_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 964, 28, percentage_max_float,acmgt1__ext14__l3_busy_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 965, 32, percentage_max_float,acmgt1__ext14__l3_busy_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 966, 36, percentage_max_float,acmgt1__ext14__l3_busy_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 967, 40, percentage_max_float,acmgt1__ext14__l3_busy_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 968, 44, percentage_max_float,acmgt1__ext14__l3_busy_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 969, 48, percentage_max_float,acmgt1__ext14__l3_busy_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 970, 52, percentage_max_float,acmgt1__ext14__l3_busy_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext15";
   query->symbol_name = "Ext15";
   query->guid = "fd355e93-4edf-425c-99e6-8693a22ae3cd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1001 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x070B0080 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x0D2B0080 },
         { .reg = 0x00009888, .val = 0x0F2B0001 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x050C0042 },
         { .reg = 0x00009888, .val = 0x070C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x0B2C0042 },
         { .reg = 0x00009888, .val = 0x0D2C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x00050A80 },
         { .reg = 0x00009888, .val = 0x0006A015 },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x000701C7 },
         { .reg = 0x00009888, .val = 0x00085A95 },
         { .reg = 0x00009888, .val = 0x020800FD },
         { .reg = 0x00009888, .val = 0x000901C7 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030060 },
         { .reg = 0x00009888, .val = 0x4C030C06 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030090 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030129 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext15__avg_gpu_core_frequency__max,acmgt1__ext15__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 971, 24, percentage_max_float,acmgt1__ext15__l3_stall_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 972, 28, percentage_max_float,acmgt1__ext15__l3_stall_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 973, 32, percentage_max_float,acmgt1__ext15__l3_stall_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 974, 36, percentage_max_float,acmgt1__ext15__l3_stall_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext16";
   query->symbol_name = "Ext16";
   query->guid = "844efb3d-c453-4dd2-b556-7bac8e111b46";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x094B1001 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0080 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0080 },
         { .reg = 0x00009888, .val = 0x0F6B0001 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x054C0042 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0B6C0042 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x0003A015 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x0004A56A },
         { .reg = 0x00009888, .val = 0x020400FE },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030040 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext16__avg_gpu_core_frequency__max,acmgt1__ext16__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 975, 24, percentage_max_float,acmgt1__ext16__l3_stall_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 976, 28, percentage_max_float,acmgt1__ext16__l3_stall_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 977, 32, percentage_max_float,acmgt1__ext16__l3_stall_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 978, 36, percentage_max_float,acmgt1__ext16__l3_stall_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext17";
   query->symbol_name = "Ext17";
   query->guid = "fadda67d-1b94-40d1-be89-759f78641ab2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890002 },
         { .reg = 0x00009888, .val = 0x1E890800 },
         { .reg = 0x00009888, .val = 0x24890040 },
         { .reg = 0x00009888, .val = 0x2A890002 },
         { .reg = 0x00009888, .val = 0x1AA90002 },
         { .reg = 0x00009888, .val = 0x1EA90800 },
         { .reg = 0x00009888, .val = 0x24A90040 },
         { .reg = 0x00009888, .val = 0x2AA90002 },
         { .reg = 0x00009888, .val = 0x1AC90002 },
         { .reg = 0x00009888, .val = 0x1EC90800 },
         { .reg = 0x00009888, .val = 0x24C90040 },
         { .reg = 0x00009888, .val = 0x2AC90002 },
         { .reg = 0x00009888, .val = 0x1AE90002 },
         { .reg = 0x00009888, .val = 0x1EE90800 },
         { .reg = 0x00009888, .val = 0x24E90040 },
         { .reg = 0x00009888, .val = 0x2AE90002 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890975 },
         { .reg = 0x00009888, .val = 0x14890155 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90975 },
         { .reg = 0x00009888, .val = 0x10A90155 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90975 },
         { .reg = 0x00009888, .val = 0x0CC90155 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90975 },
         { .reg = 0x00009888, .val = 0x08E90155 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext17__avg_gpu_core_frequency__max,acmgt1__ext17__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 979, 24, percentage_max_float,acmgt1__ext17__load_store_cache_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 980, 28, percentage_max_float,acmgt1__ext17__load_store_cache_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 981, 32, percentage_max_float,acmgt1__ext17__load_store_cache_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 982, 36, percentage_max_float,acmgt1__ext17__load_store_cache_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext18";
   query->symbol_name = "Ext18";
   query->guid = "bdd021fa-a841-4f92-826f-c3ae681c68e6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890002 },
         { .reg = 0x00009888, .val = 0x1F890800 },
         { .reg = 0x00009888, .val = 0x25890040 },
         { .reg = 0x00009888, .val = 0x2B890002 },
         { .reg = 0x00009888, .val = 0x1BA90002 },
         { .reg = 0x00009888, .val = 0x1FA90800 },
         { .reg = 0x00009888, .val = 0x25A90040 },
         { .reg = 0x00009888, .val = 0x2BA90002 },
         { .reg = 0x00009888, .val = 0x1BC90002 },
         { .reg = 0x00009888, .val = 0x1FC90800 },
         { .reg = 0x00009888, .val = 0x25C90040 },
         { .reg = 0x00009888, .val = 0x2BC90002 },
         { .reg = 0x00009888, .val = 0x1BE90002 },
         { .reg = 0x00009888, .val = 0x1FE90800 },
         { .reg = 0x00009888, .val = 0x25E90040 },
         { .reg = 0x00009888, .val = 0x2BE90002 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890975 },
         { .reg = 0x00009888, .val = 0x15890155 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90975 },
         { .reg = 0x00009888, .val = 0x11A90155 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90975 },
         { .reg = 0x00009888, .val = 0x0DC90155 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90975 },
         { .reg = 0x00009888, .val = 0x09E90155 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext18__avg_gpu_core_frequency__max,acmgt1__ext18__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 983, 24, percentage_max_float,acmgt1__ext18__load_store_cache_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 984, 28, percentage_max_float,acmgt1__ext18__load_store_cache_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 985, 32, percentage_max_float,acmgt1__ext18__load_store_cache_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 986, 36, percentage_max_float,acmgt1__ext18__load_store_cache_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext19_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext19";
   query->symbol_name = "Ext19";
   query->guid = "1181d35b-bf9a-4640-82b8-e31e031ea8d3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890934 },
         { .reg = 0x00009888, .val = 0x14890114 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90934 },
         { .reg = 0x00009888, .val = 0x10A90114 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90934 },
         { .reg = 0x00009888, .val = 0x0CC90114 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90934 },
         { .reg = 0x00009888, .val = 0x08E90114 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext19__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext19__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext19__avg_gpu_core_frequency__max,acmgt1__ext19__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 987, 24, percentage_max_float,acmgt1__ext19__load_store_cache_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 988, 28, percentage_max_float,acmgt1__ext19__load_store_cache_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 989, 32, percentage_max_float,acmgt1__ext19__load_store_cache_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 990, 36, percentage_max_float,acmgt1__ext19__load_store_cache_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext20_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext20";
   query->symbol_name = "Ext20";
   query->guid = "aa39f75d-0a8a-43d1-9c51-bcd8c62cdfe6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890934 },
         { .reg = 0x00009888, .val = 0x15890114 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90934 },
         { .reg = 0x00009888, .val = 0x11A90114 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90934 },
         { .reg = 0x00009888, .val = 0x0DC90114 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90934 },
         { .reg = 0x00009888, .val = 0x09E90114 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext20__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext20__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext20__avg_gpu_core_frequency__max,acmgt1__ext20__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 991, 24, percentage_max_float,acmgt1__ext20__load_store_cache_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 992, 28, percentage_max_float,acmgt1__ext20__load_store_cache_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 993, 32, percentage_max_float,acmgt1__ext20__load_store_cache_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 994, 36, percentage_max_float,acmgt1__ext20__load_store_cache_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext21";
   query->symbol_name = "Ext21";
   query->guid = "ae58d1ad-8aed-4104-a8e2-443d7e800378";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803062A },
         { .reg = 0x00009888, .val = 0x4A030031 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030040 },
         { .reg = 0x00009888, .val = 0x50030604 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440308E7 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x460318C2 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext21__avg_gpu_core_frequency__max,acmgt1__ext21__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 995, 24, NULL,acmgt1__ext21__load_store_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 996, 32, NULL,acmgt1__ext21__load_store_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 997, 40, NULL,acmgt1__ext21__load_store_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 998, 48, NULL,acmgt1__ext21__load_store_cache_access_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext22";
   query->symbol_name = "Ext22";
   query->guid = "c27ebd95-f242-4f4b-969a-9850f1081c30";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803062A },
         { .reg = 0x00009888, .val = 0x4A030031 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030040 },
         { .reg = 0x00009888, .val = 0x50030604 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440308E7 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x460318C2 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext22__avg_gpu_core_frequency__max,acmgt1__ext22__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 999, 24, NULL,acmgt1__ext22__load_store_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1000, 32, NULL,acmgt1__ext22__load_store_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1001, 40, NULL,acmgt1__ext22__load_store_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1002, 48, NULL,acmgt1__ext22__load_store_cache_access_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext23";
   query->symbol_name = "Ext23";
   query->guid = "881a8616-b63f-4bb1-970a-73b40b762434";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x06870143 },
         { .reg = 0x00009888, .val = 0x08870553 },
         { .reg = 0x00009888, .val = 0x0087AA00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x06880143 },
         { .reg = 0x00009888, .val = 0x08880553 },
         { .reg = 0x00009888, .val = 0x008900F0 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70143 },
         { .reg = 0x00009888, .val = 0x10A70553 },
         { .reg = 0x00009888, .val = 0x02A7AA00 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0EA80143 },
         { .reg = 0x00009888, .val = 0x10A80553 },
         { .reg = 0x00009888, .val = 0x00A9F000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030C00 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030623 },
         { .reg = 0x00009888, .val = 0x4A030031 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003080A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030040 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext23__avg_gpu_core_frequency__max,acmgt1__ext23__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1003, 24, NULL,acmgt1__ext23__load_store_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1004, 32, NULL,acmgt1__ext23__load_store_cache_hit_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext24_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext24";
   query->symbol_name = "Ext24";
   query->guid = "9fe09ad3-d296-4d41-ab19-270431f7ab29";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x06C70143 },
         { .reg = 0x00009888, .val = 0x08C70553 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80143 },
         { .reg = 0x00009888, .val = 0x08C80553 },
         { .reg = 0x00009888, .val = 0x00C900F0 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70143 },
         { .reg = 0x00009888, .val = 0x10E70553 },
         { .reg = 0x00009888, .val = 0x02E7AA00 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0EE80143 },
         { .reg = 0x00009888, .val = 0x10E80553 },
         { .reg = 0x00009888, .val = 0x00E9F000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030804 },
         { .reg = 0x00009888, .val = 0x4A030040 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030620 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030031 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x44032863 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext24__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext24__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext24__avg_gpu_core_frequency__max,acmgt1__ext24__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1005, 24, NULL,acmgt1__ext24__load_store_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1006, 32, NULL,acmgt1__ext24__load_store_cache_hit_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext25_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext25";
   query->symbol_name = "Ext25";
   query->guid = "e2016425-8755-4ca0-bc93-354ba7a6ca7a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x07870143 },
         { .reg = 0x00009888, .val = 0x09870553 },
         { .reg = 0x00009888, .val = 0x0187AA00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x07880143 },
         { .reg = 0x00009888, .val = 0x09880553 },
         { .reg = 0x00009888, .val = 0x018900F0 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0FA70143 },
         { .reg = 0x00009888, .val = 0x11A70553 },
         { .reg = 0x00009888, .val = 0x03A7AA00 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0FA80143 },
         { .reg = 0x00009888, .val = 0x11A80553 },
         { .reg = 0x00009888, .val = 0x01A9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030C00 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030623 },
         { .reg = 0x00009888, .val = 0x4A030031 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003080A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030040 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext25__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext25__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext25__avg_gpu_core_frequency__max,acmgt1__ext25__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1007, 24, NULL,acmgt1__ext25__load_store_cache_hit_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1008, 32, NULL,acmgt1__ext25__load_store_cache_hit_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext26_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext26";
   query->symbol_name = "Ext26";
   query->guid = "9fc2d1f6-7504-41f2-9f4b-96ff3307f6cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x07C70143 },
         { .reg = 0x00009888, .val = 0x09C70553 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80143 },
         { .reg = 0x00009888, .val = 0x09C80553 },
         { .reg = 0x00009888, .val = 0x01C900F0 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x0FE70143 },
         { .reg = 0x00009888, .val = 0x11E70553 },
         { .reg = 0x00009888, .val = 0x03E7AA00 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0FE80143 },
         { .reg = 0x00009888, .val = 0x11E80553 },
         { .reg = 0x00009888, .val = 0x01E9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030804 },
         { .reg = 0x00009888, .val = 0x4A030040 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030620 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030031 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x44032863 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext26__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext26__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext26__avg_gpu_core_frequency__max,acmgt1__ext26__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1009, 24, NULL,acmgt1__ext26__load_store_cache_hit_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1010, 32, NULL,acmgt1__ext26__load_store_cache_hit_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext27_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext27";
   query->symbol_name = "Ext27";
   query->guid = "7bc1c162-2b4b-4cb8-b351-65be069d3f10";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890083 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90083 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90083 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90083 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890083 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90083 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90083 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803000A },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030221 },
         { .reg = 0x00009888, .val = 0x50030EE2 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030077 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46032940 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext27__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext27__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext27__avg_gpu_core_frequency__max,acmgt1__ext27__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1011, 24, NULL,acmgt1__ext27__load_store_cache_l3_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1012, 32, NULL,acmgt1__ext27__load_store_cache_l3_read_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1013, 40, NULL,acmgt1__ext27__load_store_cache_l3_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1014, 48, NULL,acmgt1__ext27__load_store_cache_l3_read_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1015, 56, NULL,acmgt1__ext27__load_store_cache_l3_read_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1016, 64, NULL,acmgt1__ext27__load_store_cache_l3_read_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1017, 72, NULL,acmgt1__ext27__load_store_cache_l3_read_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1018, 80, NULL,acmgt1__ext27__load_store_cache_l3_read_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext28";
   query->symbol_name = "Ext28";
   query->guid = "afdf809e-962c-4af5-8e08-cd55b455dee9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890105 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90105 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90105 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90105 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890105 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90105 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90105 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90105 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803000A },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030221 },
         { .reg = 0x00009888, .val = 0x50030EE2 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030077 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46032940 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext28__avg_gpu_core_frequency__max,acmgt1__ext28__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1019, 24, NULL,acmgt1__ext28__load_store_cache_l3_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1020, 32, NULL,acmgt1__ext28__load_store_cache_l3_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1021, 40, NULL,acmgt1__ext28__load_store_cache_l3_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1022, 48, NULL,acmgt1__ext28__load_store_cache_l3_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1023, 56, NULL,acmgt1__ext28__load_store_cache_l3_write_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1024, 64, NULL,acmgt1__ext28__load_store_cache_l3_write_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1025, 72, NULL,acmgt1__ext28__load_store_cache_l3_write_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1026, 80, NULL,acmgt1__ext28__load_store_cache_l3_write_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext29_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext29";
   query->symbol_name = "Ext29";
   query->guid = "4f22c4f0-68ce-46ad-91a7-272b517bfa2e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870005 },
         { .reg = 0x00009888, .val = 0x1A870005 },
         { .reg = 0x00009888, .val = 0x12880005 },
         { .reg = 0x00009888, .val = 0x16880005 },
         { .reg = 0x00009888, .val = 0x16A70005 },
         { .reg = 0x00009888, .val = 0x1AA70005 },
         { .reg = 0x00009888, .val = 0x12A80005 },
         { .reg = 0x00009888, .val = 0x16A80005 },
         { .reg = 0x00009888, .val = 0x16C70005 },
         { .reg = 0x00009888, .val = 0x1AC70005 },
         { .reg = 0x00009888, .val = 0x12C80005 },
         { .reg = 0x00009888, .val = 0x16C80005 },
         { .reg = 0x00009888, .val = 0x16E70005 },
         { .reg = 0x00009888, .val = 0x1AE70005 },
         { .reg = 0x00009888, .val = 0x12E80005 },
         { .reg = 0x00009888, .val = 0x16E80005 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803062A },
         { .reg = 0x00009888, .val = 0x4A030031 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030040 },
         { .reg = 0x00009888, .val = 0x50030604 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440308E7 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x460318C2 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext29__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext29__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext29__avg_gpu_core_frequency__max,acmgt1__ext29__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1027, 24, NULL,acmgt1__ext29__load_store_cache_partial_write_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1028, 32, NULL,acmgt1__ext29__load_store_cache_partial_write_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1029, 40, NULL,acmgt1__ext29__load_store_cache_partial_write_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1030, 48, NULL,acmgt1__ext29__load_store_cache_partial_write_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext30_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext30";
   query->symbol_name = "Ext30";
   query->guid = "376f6937-f69d-41b0-a1ae-402dee9d42cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870005 },
         { .reg = 0x00009888, .val = 0x1B870005 },
         { .reg = 0x00009888, .val = 0x13880005 },
         { .reg = 0x00009888, .val = 0x17880005 },
         { .reg = 0x00009888, .val = 0x17A70005 },
         { .reg = 0x00009888, .val = 0x1BA70005 },
         { .reg = 0x00009888, .val = 0x13A80005 },
         { .reg = 0x00009888, .val = 0x17A80005 },
         { .reg = 0x00009888, .val = 0x17C70005 },
         { .reg = 0x00009888, .val = 0x1BC70005 },
         { .reg = 0x00009888, .val = 0x13C80005 },
         { .reg = 0x00009888, .val = 0x17C80005 },
         { .reg = 0x00009888, .val = 0x17E70005 },
         { .reg = 0x00009888, .val = 0x1BE70005 },
         { .reg = 0x00009888, .val = 0x13E80005 },
         { .reg = 0x00009888, .val = 0x17E80005 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803062A },
         { .reg = 0x00009888, .val = 0x4A030031 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030040 },
         { .reg = 0x00009888, .val = 0x50030604 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440308E7 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x460318C2 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext30__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext30__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext30__avg_gpu_core_frequency__max,acmgt1__ext30__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1031, 24, NULL,acmgt1__ext30__load_store_cache_partial_write_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1032, 32, NULL,acmgt1__ext30__load_store_cache_partial_write_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1033, 40, NULL,acmgt1__ext30__load_store_cache_partial_write_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1034, 48, NULL,acmgt1__ext30__load_store_cache_partial_write_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext31";
   query->symbol_name = "Ext31";
   query->guid = "28e81769-8b4e-4a6f-a658-19901c71f724";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext31__avg_gpu_core_frequency__max,acmgt1__ext31__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1035, 24, NULL,acmgt1__ext31__xve_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1036, 32, NULL,acmgt1__ext31__xve_load_store_cache_read_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext32_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext32";
   query->symbol_name = "Ext32";
   query->guid = "0efcc5a6-bbc5-4af3-bf07-db3597f314ab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext32__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext32__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext32__avg_gpu_core_frequency__max,acmgt1__ext32__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1037, 24, NULL,acmgt1__ext32__xve_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1038, 32, NULL,acmgt1__ext32__xve_load_store_cache_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext33_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext33";
   query->symbol_name = "Ext33";
   query->guid = "038bcd96-55da-41c0-b9ad-6d71e943f1b9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext33__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext33__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext33__avg_gpu_core_frequency__max,acmgt1__ext33__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1039, 24, NULL,acmgt1__ext33__xve_load_store_cache_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1040, 32, NULL,acmgt1__ext33__xve_load_store_cache_read_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext34_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext34";
   query->symbol_name = "Ext34";
   query->guid = "48d0ac9b-3e47-43c9-9779-3e2cdf315635";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext34__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext34__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext34__avg_gpu_core_frequency__max,acmgt1__ext34__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1041, 24, NULL,acmgt1__ext34__xve_load_store_cache_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1042, 32, NULL,acmgt1__ext34__xve_load_store_cache_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext35";
   query->symbol_name = "Ext35";
   query->guid = "ebe68cc1-ddda-412d-b9de-4616c4421712";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext35__avg_gpu_core_frequency__max,acmgt1__ext35__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1043, 24, NULL,acmgt1__ext35__xve_load_store_cache_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1044, 32, NULL,acmgt1__ext35__xve_load_store_cache_write_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext36_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext36";
   query->symbol_name = "Ext36";
   query->guid = "b305a4ce-2466-4172-97f1-a09a874f377c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext36__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext36__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext36__avg_gpu_core_frequency__max,acmgt1__ext36__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1045, 24, NULL,acmgt1__ext36__xve_load_store_cache_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1046, 32, NULL,acmgt1__ext36__xve_load_store_cache_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext37_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext37";
   query->symbol_name = "Ext37";
   query->guid = "8184361a-7e98-4f4d-b047-42c767d4c863";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext37__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext37__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext37__avg_gpu_core_frequency__max,acmgt1__ext37__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1047, 24, NULL,acmgt1__ext37__xve_load_store_cache_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1048, 32, NULL,acmgt1__ext37__xve_load_store_cache_write_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext38_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext38";
   query->symbol_name = "Ext38";
   query->guid = "0298d65d-a984-4f19-b968-1e65f072189d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext38__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext38__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext38__avg_gpu_core_frequency__max,acmgt1__ext38__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1049, 24, NULL,acmgt1__ext38__xve_load_store_cache_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1050, 32, NULL,acmgt1__ext38__xve_load_store_cache_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext39";
   query->symbol_name = "Ext39";
   query->guid = "602b3d8e-9299-4615-9739-fe44dd9b7102";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext39__avg_gpu_core_frequency__max,acmgt1__ext39__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1051, 24, NULL,acmgt1__ext39__xve_load_store_cache_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1052, 32, NULL,acmgt1__ext39__xve_load_store_cache_fence_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext40_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext40";
   query->symbol_name = "Ext40";
   query->guid = "7595f984-7cd3-4b1c-8332-bacfd2b3a359";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext40__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext40__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext40__avg_gpu_core_frequency__max,acmgt1__ext40__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1053, 24, NULL,acmgt1__ext40__xve_load_store_cache_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1054, 32, NULL,acmgt1__ext40__xve_load_store_cache_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext41_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext41";
   query->symbol_name = "Ext41";
   query->guid = "61bf91ad-0dfa-421c-b503-0eed63b64ef5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext41__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext41__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext41__avg_gpu_core_frequency__max,acmgt1__ext41__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1055, 24, NULL,acmgt1__ext41__xve_load_store_cache_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1056, 32, NULL,acmgt1__ext41__xve_load_store_cache_fence_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext42_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext42";
   query->symbol_name = "Ext42";
   query->guid = "a2f3417e-fbe1-4c26-a20c-509c7205445f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext42__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext42__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext42__avg_gpu_core_frequency__max,acmgt1__ext42__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1057, 24, NULL,acmgt1__ext42__xve_load_store_cache_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1058, 32, NULL,acmgt1__ext42__xve_load_store_cache_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext43_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext43";
   query->symbol_name = "Ext43";
   query->guid = "343460a0-c54f-4fe5-b7ac-6d9870a56aaf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x12890A79 },
         { .reg = 0x00009888, .val = 0x14890259 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext43__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext43__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext43__avg_gpu_core_frequency__max,acmgt1__ext43__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1059, 24, NULL,acmgt1__ext43__xve_load_store_cache_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1060, 32, NULL,acmgt1__ext43__xve_load_store_cache_register_request_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext44_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext44";
   query->symbol_name = "Ext44";
   query->guid = "cfaeaf8e-4888-459f-8019-c3080595c528";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x12A90A79 },
         { .reg = 0x00009888, .val = 0x14A90259 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext44__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext44__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext44__avg_gpu_core_frequency__max,acmgt1__ext44__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1061, 24, NULL,acmgt1__ext44__xve_load_store_cache_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1062, 32, NULL,acmgt1__ext44__xve_load_store_cache_register_request_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext45";
   query->symbol_name = "Ext45";
   query->guid = "c50cb371-e940-4499-aa74-4e75bc131329";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x12C90A79 },
         { .reg = 0x00009888, .val = 0x14C90259 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext45__avg_gpu_core_frequency__max,acmgt1__ext45__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1063, 24, NULL,acmgt1__ext45__xve_load_store_cache_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1064, 32, NULL,acmgt1__ext45__xve_load_store_cache_register_request_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext46_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext46";
   query->symbol_name = "Ext46";
   query->guid = "b56a3837-111d-4ec1-8d3f-42e9e304d8f5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x12E90A79 },
         { .reg = 0x00009888, .val = 0x14E90259 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext46__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext46__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext46__avg_gpu_core_frequency__max,acmgt1__ext46__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1065, 24, NULL,acmgt1__ext46__xve_load_store_cache_atomic_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1066, 32, NULL,acmgt1__ext46__xve_load_store_cache_register_request_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext47_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext47";
   query->symbol_name = "Ext47";
   query->guid = "3725926f-9a84-4cc2-963c-2294f47c017c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x13890A79 },
         { .reg = 0x00009888, .val = 0x15890259 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext47__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext47__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext47__avg_gpu_core_frequency__max,acmgt1__ext47__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1067, 24, NULL,acmgt1__ext47__xve_load_store_cache_atomic_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1068, 32, NULL,acmgt1__ext47__xve_load_store_cache_register_request_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext48_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext48";
   query->symbol_name = "Ext48";
   query->guid = "357a3801-3f4e-4106-8f1e-c0bfe1c5f419";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x13A90A79 },
         { .reg = 0x00009888, .val = 0x15A90259 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext48__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext48__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext48__avg_gpu_core_frequency__max,acmgt1__ext48__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1069, 24, NULL,acmgt1__ext48__xve_load_store_cache_atomic_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1070, 32, NULL,acmgt1__ext48__xve_load_store_cache_register_request_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext49_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext49";
   query->symbol_name = "Ext49";
   query->guid = "8b324152-65d7-4b13-8fa9-cab57cd68471";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x13C90A79 },
         { .reg = 0x00009888, .val = 0x15C90259 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext49__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext49__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext49__avg_gpu_core_frequency__max,acmgt1__ext49__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1071, 24, NULL,acmgt1__ext49__xve_load_store_cache_atomic_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1072, 32, NULL,acmgt1__ext49__xve_load_store_cache_register_request_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext50_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext50";
   query->symbol_name = "Ext50";
   query->guid = "db09b08d-a300-4f2a-aeb0-b797e7073ef3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x13E90A79 },
         { .reg = 0x00009888, .val = 0x15E90259 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext50__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext50__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext50__avg_gpu_core_frequency__max,acmgt1__ext50__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1073, 24, NULL,acmgt1__ext50__xve_load_store_cache_atomic_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1074, 32, NULL,acmgt1__ext50__xve_load_store_cache_register_request_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext51_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext51";
   query->symbol_name = "Ext51";
   query->guid = "fc148084-3936-4dab-9b42-d7ba6ae1952d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext51__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext51__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext51__avg_gpu_core_frequency__max,acmgt1__ext51__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1075, 24, NULL,acmgt1__ext51__xve_load_store_cache_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1076, 32, NULL,acmgt1__ext51__xve_load_store_cache_register_response_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1077, 40, NULL,acmgt1__ext51__xve_load_store_cache_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1078, 48, NULL,acmgt1__ext51__xve_load_store_cache_register_response_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext52_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext52";
   query->symbol_name = "Ext52";
   query->guid = "f6a3c36f-9fd8-49c4-b25a-dbf26256bdc6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext52__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext52__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext52__avg_gpu_core_frequency__max,acmgt1__ext52__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1079, 24, NULL,acmgt1__ext52__xve_load_store_cache_register_response_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1080, 32, NULL,acmgt1__ext52__xve_load_store_cache_register_response_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1081, 40, NULL,acmgt1__ext52__xve_load_store_cache_register_response_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1082, 48, NULL,acmgt1__ext52__xve_load_store_cache_register_response_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext53_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext53";
   query->symbol_name = "Ext53";
   query->guid = "a9a91699-a2b3-4841-8641-4f09f04be7e1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext53__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext53__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext53__avg_gpu_core_frequency__max,acmgt1__ext53__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1083, 24, NULL,acmgt1__ext53__xve_slm_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1084, 32, NULL,acmgt1__ext53__xve_slm_read_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext54_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext54";
   query->symbol_name = "Ext54";
   query->guid = "c44659b1-937a-44bc-8819-9c1ae31d9bdd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext54__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext54__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext54__avg_gpu_core_frequency__max,acmgt1__ext54__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1085, 24, NULL,acmgt1__ext54__xve_slm_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1086, 32, NULL,acmgt1__ext54__xve_slm_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext55_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext55";
   query->symbol_name = "Ext55";
   query->guid = "5bfd7ae1-27ea-4211-beb2-64565a49dfbe";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext55__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext55__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext55__avg_gpu_core_frequency__max,acmgt1__ext55__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1087, 24, NULL,acmgt1__ext55__xve_slm_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1088, 32, NULL,acmgt1__ext55__xve_slm_read_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext56_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext56";
   query->symbol_name = "Ext56";
   query->guid = "7aefc824-149a-4f75-abed-f6430f8d4eee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext56__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext56__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext56__avg_gpu_core_frequency__max,acmgt1__ext56__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1089, 24, NULL,acmgt1__ext56__xve_slm_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1090, 32, NULL,acmgt1__ext56__xve_slm_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext57_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext57";
   query->symbol_name = "Ext57";
   query->guid = "0ccb67b5-7f31-4885-9973-d97e318a6f90";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext57__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext57__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext57__avg_gpu_core_frequency__max,acmgt1__ext57__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1091, 24, NULL,acmgt1__ext57__xve_slm_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1092, 32, NULL,acmgt1__ext57__xve_slm_write_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext58_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext58";
   query->symbol_name = "Ext58";
   query->guid = "af47d7b7-691b-4ec5-abfd-67ce50938fe4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext58__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext58__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext58__avg_gpu_core_frequency__max,acmgt1__ext58__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1093, 24, NULL,acmgt1__ext58__xve_slm_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1094, 32, NULL,acmgt1__ext58__xve_slm_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext59_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext59";
   query->symbol_name = "Ext59";
   query->guid = "0df81caa-d128-4f0e-9eff-69e0359fedf1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext59__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext59__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext59__avg_gpu_core_frequency__max,acmgt1__ext59__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1095, 24, NULL,acmgt1__ext59__xve_slm_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1096, 32, NULL,acmgt1__ext59__xve_slm_write_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext60_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext60";
   query->symbol_name = "Ext60";
   query->guid = "09e71710-e49d-4d9e-b7f8-0e597aabf25b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext60__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext60__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext60__avg_gpu_core_frequency__max,acmgt1__ext60__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1097, 24, NULL,acmgt1__ext60__xve_slm_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1098, 32, NULL,acmgt1__ext60__xve_slm_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext61_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext61";
   query->symbol_name = "Ext61";
   query->guid = "374c4608-89a8-46d3-92fa-d4848e4a7a95";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext61__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext61__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext61__avg_gpu_core_frequency__max,acmgt1__ext61__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1099, 24, NULL,acmgt1__ext61__xve_slm_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1100, 32, NULL,acmgt1__ext61__xve_slm_fence_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext62_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext62";
   query->symbol_name = "Ext62";
   query->guid = "1013ed95-4958-4cfe-8fbc-1482c07046cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext62__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext62__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext62__avg_gpu_core_frequency__max,acmgt1__ext62__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1101, 24, NULL,acmgt1__ext62__xve_slm_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1102, 32, NULL,acmgt1__ext62__xve_slm_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext63_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext63";
   query->symbol_name = "Ext63";
   query->guid = "7a3c4561-56d3-4b61-a619-ed8c1887e034";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext63__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext63__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext63__avg_gpu_core_frequency__max,acmgt1__ext63__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1103, 24, NULL,acmgt1__ext63__xve_slm_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1104, 32, NULL,acmgt1__ext63__xve_slm_fence_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext64_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext64";
   query->symbol_name = "Ext64";
   query->guid = "7d50a975-2d8d-48c2-ae61-86decd3aba1d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext64__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext64__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext64__avg_gpu_core_frequency__max,acmgt1__ext64__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1105, 24, NULL,acmgt1__ext64__xve_slm_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1106, 32, NULL,acmgt1__ext64__xve_slm_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext65_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext65";
   query->symbol_name = "Ext65";
   query->guid = "c036e0c0-c23a-45ec-8b24-7ab7577b18d1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x028300AA },
         { .reg = 0x00009888, .val = 0x00840FFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02860055 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x028700AA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext65__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext65__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext65__avg_gpu_core_frequency__max,acmgt1__ext65__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1107, 24, NULL,acmgt1__ext65__xve_slm_atomic_message_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext66_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext66";
   query->symbol_name = "Ext66";
   query->guid = "df8127a7-0efc-487e-a819-a20c2471e30b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40FFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext66__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext66__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext66__avg_gpu_core_frequency__max,acmgt1__ext66__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1108, 24, NULL,acmgt1__ext66__xve_slm_atomic_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext67_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext67";
   query->symbol_name = "Ext67";
   query->guid = "f9d2c7da-14c9-45a4-97f5-a0d58dd3a1aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40FFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C700AA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x020700AA },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext67__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext67__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext67__avg_gpu_core_frequency__max,acmgt1__ext67__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1109, 24, NULL,acmgt1__ext67__xve_slm_atomic_message_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext68_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext68";
   query->symbol_name = "Ext68";
   query->guid = "210f665b-abaa-4389-95e3-7cad6f71db8b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E300AA },
         { .reg = 0x00009888, .val = 0x00E40FFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E60055 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E700AA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070055 },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext68__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext68__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext68__avg_gpu_core_frequency__max,acmgt1__ext68__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1110, 24, NULL,acmgt1__ext68__xve_slm_atomic_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext69_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext69";
   query->symbol_name = "Ext69";
   query->guid = "26eeaeca-61f0-46ba-b6ad-effb4ea076ae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x038300AA },
         { .reg = 0x00009888, .val = 0x01840FFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x038700AA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x030800AA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext69__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext69__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext69__avg_gpu_core_frequency__max,acmgt1__ext69__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1111, 24, NULL,acmgt1__ext69__xve_slm_atomic_message_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext70_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext70";
   query->symbol_name = "Ext70";
   query->guid = "18a0a208-526a-4705-9b06-9145f03433ea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40FFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x030800FF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x01010FFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext70__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext70__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext70__avg_gpu_core_frequency__max,acmgt1__ext70__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1112, 24, NULL,acmgt1__ext70__xve_slm_atomic_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext71_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext71";
   query->symbol_name = "Ext71";
   query->guid = "0677d73a-a563-47ac-8b11-9c7c3371fc04";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40FFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C700AA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x030700AA },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01020FFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext71__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext71__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext71__avg_gpu_core_frequency__max,acmgt1__ext71__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1113, 24, NULL,acmgt1__ext71__xve_slm_atomic_message_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext72_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext72";
   query->symbol_name = "Ext72";
   query->guid = "0a10b421-f9ee-4147-81e2-b2ceeb74697f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40FFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E700AA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext72__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext72__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext72__avg_gpu_core_frequency__max,acmgt1__ext72__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1114, 24, NULL,acmgt1__ext72__xve_slm_atomic_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext73_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext73";
   query->symbol_name = "Ext73";
   query->guid = "4051668d-2020-4f10-a9e7-e840455b125b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1881039B },
         { .reg = 0x00009888, .val = 0x18A1039B },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A810207 },
         { .reg = 0x00009888, .val = 0x0C810081 },
         { .reg = 0x00009888, .val = 0x0E810103 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x10A10185 },
         { .reg = 0x00009888, .val = 0x12A10207 },
         { .reg = 0x00009888, .val = 0x14A10081 },
         { .reg = 0x00009888, .val = 0x16A10103 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext73__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext73__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext73__avg_gpu_core_frequency__max,acmgt1__ext73__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1115, 24, percentage_max_float,acmgt1__ext73__dataport_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1116, 28, percentage_max_float,acmgt1__ext73__dataport_input_available_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext74_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext74";
   query->symbol_name = "Ext74";
   query->guid = "0548ee0d-a4b2-42a7-86c6-4171ed191bec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18C1039B },
         { .reg = 0x00009888, .val = 0x18E1039B },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x08C10185 },
         { .reg = 0x00009888, .val = 0x0AC10207 },
         { .reg = 0x00009888, .val = 0x0CC10081 },
         { .reg = 0x00009888, .val = 0x0EC10103 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E10185 },
         { .reg = 0x00009888, .val = 0x12E10207 },
         { .reg = 0x00009888, .val = 0x14E10081 },
         { .reg = 0x00009888, .val = 0x16E10103 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext74__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext74__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext74__avg_gpu_core_frequency__max,acmgt1__ext74__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1117, 24, percentage_max_float,acmgt1__ext74__dataport_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1118, 28, percentage_max_float,acmgt1__ext74__dataport_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext75_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext75";
   query->symbol_name = "Ext75";
   query->guid = "4604dea5-4e86-4713-b82d-fce110cb82f8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1981039B },
         { .reg = 0x00009888, .val = 0x19A1039B },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B810207 },
         { .reg = 0x00009888, .val = 0x0D810081 },
         { .reg = 0x00009888, .val = 0x0F810103 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x11A10185 },
         { .reg = 0x00009888, .val = 0x13A10207 },
         { .reg = 0x00009888, .val = 0x15A10081 },
         { .reg = 0x00009888, .val = 0x17A10103 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext75__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext75__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext75__avg_gpu_core_frequency__max,acmgt1__ext75__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1119, 24, percentage_max_float,acmgt1__ext75__dataport_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1120, 28, percentage_max_float,acmgt1__ext75__dataport_input_available_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext76_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext76";
   query->symbol_name = "Ext76";
   query->guid = "d4171f1f-6e14-41e1-8b9d-0e28077aca25";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19C1039B },
         { .reg = 0x00009888, .val = 0x19E1039B },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x09C10185 },
         { .reg = 0x00009888, .val = 0x0BC10207 },
         { .reg = 0x00009888, .val = 0x0DC10081 },
         { .reg = 0x00009888, .val = 0x0FC10103 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x11E10185 },
         { .reg = 0x00009888, .val = 0x13E10207 },
         { .reg = 0x00009888, .val = 0x15E10081 },
         { .reg = 0x00009888, .val = 0x17E10103 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext76__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext76__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext76__avg_gpu_core_frequency__max,acmgt1__ext76__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1121, 24, percentage_max_float,acmgt1__ext76__dataport_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1122, 28, percentage_max_float,acmgt1__ext76__dataport_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext77_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext77";
   query->symbol_name = "Ext77";
   query->guid = "8e91f318-149b-4ffe-9b51-42dd9b2c80a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281C000 },
         { .reg = 0x00009888, .val = 0x12A1C000 },
         { .reg = 0x00009888, .val = 0x12C1C4D2 },
         { .reg = 0x00009888, .val = 0x12E1C000 },
         { .reg = 0x00009888, .val = 0x04810200 },
         { .reg = 0x00009888, .val = 0x08810450 },
         { .reg = 0x00009888, .val = 0x0A8104D2 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x04A10200 },
         { .reg = 0x00009888, .val = 0x0CA10450 },
         { .reg = 0x00009888, .val = 0x0EA104D2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x04C10200 },
         { .reg = 0x00009888, .val = 0x10C10450 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x02C70055 },
         { .reg = 0x00009888, .val = 0x04E10200 },
         { .reg = 0x00009888, .val = 0x14E10450 },
         { .reg = 0x00009888, .val = 0x16E104D2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext77__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext77__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext77__avg_gpu_core_frequency__max,acmgt1__ext77__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1123, 24, percentage_max_float,acmgt1__ext77__dataport_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1124, 28, percentage_max_float,acmgt1__ext77__dataport_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1125, 32, percentage_max_float,acmgt1__ext77__dataport_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1126, 36, percentage_max_float,acmgt1__ext77__dataport_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext78_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext78";
   query->symbol_name = "Ext78";
   query->guid = "bf68f6bc-fdcb-4dbe-a923-abaeb72e8af6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381C000 },
         { .reg = 0x00009888, .val = 0x13A1C000 },
         { .reg = 0x00009888, .val = 0x13C1C4D2 },
         { .reg = 0x00009888, .val = 0x13E1C000 },
         { .reg = 0x00009888, .val = 0x05810200 },
         { .reg = 0x00009888, .val = 0x09810450 },
         { .reg = 0x00009888, .val = 0x0B8104D2 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x05A10200 },
         { .reg = 0x00009888, .val = 0x0DA10450 },
         { .reg = 0x00009888, .val = 0x0FA104D2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x05C10200 },
         { .reg = 0x00009888, .val = 0x11C10450 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x03C70055 },
         { .reg = 0x00009888, .val = 0x05E10200 },
         { .reg = 0x00009888, .val = 0x15E10450 },
         { .reg = 0x00009888, .val = 0x17E104D2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x03E75500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext78__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext78__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext78__avg_gpu_core_frequency__max,acmgt1__ext78__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1127, 24, percentage_max_float,acmgt1__ext78__dataport_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1128, 28, percentage_max_float,acmgt1__ext78__dataport_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1129, 32, percentage_max_float,acmgt1__ext78__dataport_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1130, 36, percentage_max_float,acmgt1__ext78__dataport_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext79_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext79";
   query->symbol_name = "Ext79";
   query->guid = "76b52ef9-7a1b-4475-b3bc-3a035acd32e7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext79__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext79__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext79__avg_gpu_core_frequency__max,acmgt1__ext79__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1131, 24, NULL,acmgt1__ext79__dataport_byte_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1132, 32, NULL,acmgt1__ext79__dataport_byte_read_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext80_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext80";
   query->symbol_name = "Ext80";
   query->guid = "171d99e0-0ace-4af7-8702-19e9fbb04a46";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext80__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext80__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext80__avg_gpu_core_frequency__max,acmgt1__ext80__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1133, 24, NULL,acmgt1__ext80__dataport_byte_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1134, 32, NULL,acmgt1__ext80__dataport_byte_read_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext81_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext81";
   query->symbol_name = "Ext81";
   query->guid = "f399ee12-9656-47fe-8566-416a8e4e4c07";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext81__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext81__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext81__avg_gpu_core_frequency__max,acmgt1__ext81__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1135, 24, NULL,acmgt1__ext81__dataport_byte_read_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1136, 32, NULL,acmgt1__ext81__dataport_byte_read_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext82_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext82";
   query->symbol_name = "Ext82";
   query->guid = "766bbe37-ffda-41f0-92da-e31184140e43";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext82__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext82__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext82__avg_gpu_core_frequency__max,acmgt1__ext82__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1137, 24, NULL,acmgt1__ext82__dataport_byte_read_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1138, 32, NULL,acmgt1__ext82__dataport_byte_read_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext83_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext83";
   query->symbol_name = "Ext83";
   query->guid = "4d5d9009-c75e-4655-8374-503fd68ac0c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E816820 },
         { .reg = 0x00009888, .val = 0x1EA16820 },
         { .reg = 0x00009888, .val = 0x1EC16820 },
         { .reg = 0x00009888, .val = 0x1EE16820 },
         { .reg = 0x00009888, .val = 0x1F816820 },
         { .reg = 0x00009888, .val = 0x1FA16820 },
         { .reg = 0x00009888, .val = 0x1FC16820 },
         { .reg = 0x00009888, .val = 0x1FE16820 },
         { .reg = 0x00009888, .val = 0x04815400 },
         { .reg = 0x00009888, .val = 0x0E810440 },
         { .reg = 0x00009888, .val = 0x16810780 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A15400 },
         { .reg = 0x00009888, .val = 0x0EA10011 },
         { .reg = 0x00009888, .val = 0x16A1001E },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C15400 },
         { .reg = 0x00009888, .val = 0x0CC10440 },
         { .reg = 0x00009888, .val = 0x14C10780 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E15400 },
         { .reg = 0x00009888, .val = 0x0CE10011 },
         { .reg = 0x00009888, .val = 0x14E1001E },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05815400 },
         { .reg = 0x00009888, .val = 0x0B810440 },
         { .reg = 0x00009888, .val = 0x13810780 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A15400 },
         { .reg = 0x00009888, .val = 0x0BA10011 },
         { .reg = 0x00009888, .val = 0x13A1001E },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C15400 },
         { .reg = 0x00009888, .val = 0x09C10440 },
         { .reg = 0x00009888, .val = 0x11C10780 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E15400 },
         { .reg = 0x00009888, .val = 0x09E10011 },
         { .reg = 0x00009888, .val = 0x11E1001E },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030600 },
         { .reg = 0x00009888, .val = 0x4A030E21 },
         { .reg = 0x00009888, .val = 0x4C031067 },
         { .reg = 0x00009888, .val = 0x4E030E07 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031C43 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x46032808 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext83__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext83__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext83__avg_gpu_core_frequency__max,acmgt1__ext83__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1139, 24, NULL,acmgt1__ext83__dataport_byte_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1140, 32, NULL,acmgt1__ext83__dataport_byte_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1141, 40, NULL,acmgt1__ext83__dataport_byte_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1142, 48, NULL,acmgt1__ext83__dataport_byte_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1143, 56, NULL,acmgt1__ext83__dataport_byte_write_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1144, 64, NULL,acmgt1__ext83__dataport_byte_write_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1145, 72, NULL,acmgt1__ext83__dataport_byte_write_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1146, 80, NULL,acmgt1__ext83__dataport_byte_write_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1147, 88, NULL,acmgt1__ext83__dataport_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1148, 96, NULL,acmgt1__ext83__dataport_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1149, 104, NULL,acmgt1__ext83__dataport_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1150, 112, NULL,acmgt1__ext83__dataport_texture_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1151, 120, NULL,acmgt1__ext83__dataport_texture_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1152, 128, NULL,acmgt1__ext83__dataport_texture_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1153, 136, NULL,acmgt1__ext83__dataport_texture_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1154, 144, NULL,acmgt1__ext83__dataport_texture_cache_access_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext84_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext84";
   query->symbol_name = "Ext84";
   query->guid = "fd091d19-b48d-49d2-b99e-c5505624daa3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2081001F },
         { .reg = 0x00009888, .val = 0x20A1001F },
         { .reg = 0x00009888, .val = 0x20C1001F },
         { .reg = 0x00009888, .val = 0x20E1001F },
         { .reg = 0x00009888, .val = 0x2181001F },
         { .reg = 0x00009888, .val = 0x21A1001F },
         { .reg = 0x00009888, .val = 0x21C1001F },
         { .reg = 0x00009888, .val = 0x21E1001F },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x10810014 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02830002 },
         { .reg = 0x00009888, .val = 0x00840100 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x02870001 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x10A10500 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A30008 },
         { .reg = 0x00009888, .val = 0x00A40200 },
         { .reg = 0x00009888, .val = 0x02A60004 },
         { .reg = 0x00009888, .val = 0x02A70004 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x12C10014 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30020 },
         { .reg = 0x00009888, .val = 0x00C40400 },
         { .reg = 0x00009888, .val = 0x02C60010 },
         { .reg = 0x00009888, .val = 0x02C70010 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x12E10500 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30080 },
         { .reg = 0x00009888, .val = 0x00E40800 },
         { .reg = 0x00009888, .val = 0x02E60040 },
         { .reg = 0x00009888, .val = 0x02E70040 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x15810014 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830200 },
         { .reg = 0x00009888, .val = 0x01841000 },
         { .reg = 0x00009888, .val = 0x03860100 },
         { .reg = 0x00009888, .val = 0x03870100 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x15A10500 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30800 },
         { .reg = 0x00009888, .val = 0x01A42000 },
         { .reg = 0x00009888, .val = 0x03A60400 },
         { .reg = 0x00009888, .val = 0x03A70400 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x17C10014 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32000 },
         { .reg = 0x00009888, .val = 0x01C44000 },
         { .reg = 0x00009888, .val = 0x03C61000 },
         { .reg = 0x00009888, .val = 0x03C71000 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x17E10500 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E38000 },
         { .reg = 0x00009888, .val = 0x01E48000 },
         { .reg = 0x00009888, .val = 0x03E64000 },
         { .reg = 0x00009888, .val = 0x03E74000 },
         { .reg = 0x00009888, .val = 0x0003F000 },
         { .reg = 0x00009888, .val = 0x02070060 },
         { .reg = 0x00009888, .val = 0x0208FF0E },
         { .reg = 0x00009888, .val = 0x00090C00 },
         { .reg = 0x00009888, .val = 0x020A55A5 },
         { .reg = 0x00009888, .val = 0x0001F200 },
         { .reg = 0x00009888, .val = 0x020BAA04 },
         { .reg = 0x00009888, .val = 0x00020400 },
         { .reg = 0x00009888, .val = 0x020C0010 },
         { .reg = 0x00009888, .val = 0x03076000 },
         { .reg = 0x00009888, .val = 0x03080E00 },
         { .reg = 0x00009888, .val = 0x0109C000 },
         { .reg = 0x00009888, .val = 0x030AA500 },
         { .reg = 0x00009888, .val = 0x01012000 },
         { .reg = 0x00009888, .val = 0x030B0400 },
         { .reg = 0x00009888, .val = 0x01024000 },
         { .reg = 0x00009888, .val = 0x030C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x500314E0 },
         { .reg = 0x00009888, .val = 0x52030007 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x440308E8 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46032803 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext84__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext84__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext84__avg_gpu_core_frequency__max,acmgt1__ext84__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1155, 24, NULL,acmgt1__ext84__dataport_texture_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1156, 32, NULL,acmgt1__ext84__dataport_texture_cache_hit_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1157, 40, NULL,acmgt1__ext84__dataport_texture_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1158, 48, NULL,acmgt1__ext84__dataport_texture_cache_hit_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1159, 56, NULL,acmgt1__ext84__dataport_texture_cache_hit_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1160, 64, NULL,acmgt1__ext84__dataport_texture_cache_hit_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1161, 72, NULL,acmgt1__ext84__dataport_texture_cache_hit_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1162, 80, NULL,acmgt1__ext84__dataport_texture_cache_hit_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext85_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext85";
   query->symbol_name = "Ext85";
   query->guid = "d45a3f38-372d-4757-88cf-5589035652d5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x088101C5 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC101C5 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030030 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext85__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext85__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext85__avg_gpu_core_frequency__max,acmgt1__ext85__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1163, 24, NULL,acmgt1__ext85__xve_dataport_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1164, 32, NULL,acmgt1__ext85__xve_dataport_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1165, 40, NULL,acmgt1__ext85__xve_dataport_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1166, 48, NULL,acmgt1__ext85__xve_dataport_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext86_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext86";
   query->symbol_name = "Ext86";
   query->guid = "46f2e8eb-1a50-499e-9096-66f79932703e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x098101C5 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC101C5 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030030 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext86__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext86__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext86__avg_gpu_core_frequency__max,acmgt1__ext86__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1167, 24, NULL,acmgt1__ext86__xve_dataport_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1168, 32, NULL,acmgt1__ext86__xve_dataport_read_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1169, 40, NULL,acmgt1__ext86__xve_dataport_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1170, 48, NULL,acmgt1__ext86__xve_dataport_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext87_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext87";
   query->symbol_name = "Ext87";
   query->guid = "35a680fa-e0c7-4e60-9a42-4e5c67d90b4d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810206 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10180 },
         { .reg = 0x00009888, .val = 0x0CA102C8 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10206 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10180 },
         { .reg = 0x00009888, .val = 0x12E102C8 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030030 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext87__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext87__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext87__avg_gpu_core_frequency__max,acmgt1__ext87__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1171, 24, NULL,acmgt1__ext87__xve_dataport_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1172, 32, NULL,acmgt1__ext87__xve_dataport_write_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1173, 40, NULL,acmgt1__ext87__xve_dataport_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1174, 48, NULL,acmgt1__ext87__xve_dataport_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext88_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext88";
   query->symbol_name = "Ext88";
   query->guid = "e1d0a1c4-41c7-4d82-a6f0-42ea537e5664";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810206 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10180 },
         { .reg = 0x00009888, .val = 0x0DA102C8 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10206 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10180 },
         { .reg = 0x00009888, .val = 0x13E102C8 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030030 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext88__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext88__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext88__avg_gpu_core_frequency__max,acmgt1__ext88__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1175, 24, NULL,acmgt1__ext88__xve_dataport_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1176, 32, NULL,acmgt1__ext88__xve_dataport_write_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1177, 40, NULL,acmgt1__ext88__xve_dataport_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1178, 48, NULL,acmgt1__ext88__xve_dataport_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext91_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext91";
   query->symbol_name = "Ext91";
   query->guid = "c26ba023-58d3-4ec7-9282-f2638a292912";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C6 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10185 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C6 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030030 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext91__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext91__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext91__avg_gpu_core_frequency__max,acmgt1__ext91__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1179, 24, NULL,acmgt1__ext91__xve_dataport_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1180, 32, NULL,acmgt1__ext91__xve_dataport_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1181, 40, NULL,acmgt1__ext91__xve_dataport_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1182, 48, NULL,acmgt1__ext91__xve_dataport_atomic_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext92_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext92";
   query->symbol_name = "Ext92";
   query->guid = "7e5a8ef5-b434-4bf1-81f0-eeddaa072d37";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C6 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10185 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C6 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030030 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext92__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext92__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext92__avg_gpu_core_frequency__max,acmgt1__ext92__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1183, 24, NULL,acmgt1__ext92__xve_dataport_atomic_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1184, 32, NULL,acmgt1__ext92__xve_dataport_atomic_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1185, 40, NULL,acmgt1__ext92__xve_dataport_atomic_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1186, 48, NULL,acmgt1__ext92__xve_dataport_atomic_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext93_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext93";
   query->symbol_name = "Ext93";
   query->guid = "917a8688-0aa2-4b9a-a1a1-60dc016b17e6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext93__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext93__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext93__avg_gpu_core_frequency__max,acmgt1__ext93__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1187, 24, NULL,acmgt1__ext93__xve_dataport_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1188, 32, NULL,acmgt1__ext93__xve_dataport_register_response_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext94_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext94";
   query->symbol_name = "Ext94";
   query->guid = "dad96cfd-65c0-470c-a9d2-33d7881234c0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext94__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext94__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext94__avg_gpu_core_frequency__max,acmgt1__ext94__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1189, 24, NULL,acmgt1__ext94__xve_dataport_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1190, 28, NULL,acmgt1__ext94__xve_dataport_register_response_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext95_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext95";
   query->symbol_name = "Ext95";
   query->guid = "811672a2-3bd6-473e-bd4b-dae0a5786a00";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext95__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext95__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext95__avg_gpu_core_frequency__max,acmgt1__ext95__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1191, 24, NULL,acmgt1__ext95__xve_dataport_register_response_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1192, 28, NULL,acmgt1__ext95__xve_dataport_register_response_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext96_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext96";
   query->symbol_name = "Ext96";
   query->guid = "91ebb988-2cc5-4cb9-b071-3a9d76f42b55";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext96__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext96__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext96__avg_gpu_core_frequency__max,acmgt1__ext96__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1193, 24, NULL,acmgt1__ext96__xve_dataport_register_response_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1194, 28, NULL,acmgt1__ext96__xve_dataport_register_response_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext97_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext97";
   query->symbol_name = "Ext97";
   query->guid = "3e446a1f-d62b-4ea4-bbf3-845dc7f437e4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x188102FD },
         { .reg = 0x00009888, .val = 0x18A102FD },
         { .reg = 0x00009888, .val = 0x18C102FD },
         { .reg = 0x00009888, .val = 0x18E102FD },
         { .reg = 0x00009888, .val = 0x198102FD },
         { .reg = 0x00009888, .val = 0x19A102FD },
         { .reg = 0x00009888, .val = 0x19C102FD },
         { .reg = 0x00009888, .val = 0x19E102FD },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x168103C2 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x02875000 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x14A103C2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70500 },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x12C103C2 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C70050 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E103C2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x0F8103C2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x01875000 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x0DA103C2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70500 },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x0BC103C2 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C70050 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x09E103C2 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E70005 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803000A },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030221 },
         { .reg = 0x00009888, .val = 0x50030EE2 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030077 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46032940 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext97__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext97__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext97__avg_gpu_core_frequency__max,acmgt1__ext97__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1195, 24, NULL,acmgt1__ext97__xve_dataport_register_request_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1196, 32, NULL,acmgt1__ext97__xve_dataport_register_request_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1197, 40, NULL,acmgt1__ext97__xve_dataport_register_request_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1198, 48, NULL,acmgt1__ext97__xve_dataport_register_request_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1199, 56, NULL,acmgt1__ext97__xve_dataport_register_request_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1200, 64, NULL,acmgt1__ext97__xve_dataport_register_request_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1201, 72, NULL,acmgt1__ext97__xve_dataport_register_request_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1202, 80, NULL,acmgt1__ext97__xve_dataport_register_request_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext98_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext98";
   query->symbol_name = "Ext98";
   query->guid = "5ff858aa-50d0-44b9-bbf7-d07881ecdd9c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x14833000 },
         { .reg = 0x00009888, .val = 0x14A33000 },
         { .reg = 0x00009888, .val = 0x14C33000 },
         { .reg = 0x00009888, .val = 0x14E33000 },
         { .reg = 0x00009888, .val = 0x04830450 },
         { .reg = 0x00009888, .val = 0x068304D2 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x08A30450 },
         { .reg = 0x00009888, .val = 0x0AA304D2 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x0CC30450 },
         { .reg = 0x00009888, .val = 0x0EC304D2 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x10E30450 },
         { .reg = 0x00009888, .val = 0x12E304D2 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext98__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext98__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext98__avg_gpu_core_frequency__max,acmgt1__ext98__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1203, 24, percentage_max_float,acmgt1__ext98__sampler_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1204, 28, percentage_max_float,acmgt1__ext98__sampler_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1205, 32, percentage_max_float,acmgt1__ext98__sampler_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1206, 36, percentage_max_float,acmgt1__ext98__sampler_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext99_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext99";
   query->symbol_name = "Ext99";
   query->guid = "ba34845b-431b-41c8-9d51-5c8be2f0ac4c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x15833000 },
         { .reg = 0x00009888, .val = 0x15A33000 },
         { .reg = 0x00009888, .val = 0x15C33000 },
         { .reg = 0x00009888, .val = 0x15E33000 },
         { .reg = 0x00009888, .val = 0x05830450 },
         { .reg = 0x00009888, .val = 0x078304D2 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x09A30450 },
         { .reg = 0x00009888, .val = 0x0BA304D2 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x0DC30450 },
         { .reg = 0x00009888, .val = 0x0FC304D2 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x11E30450 },
         { .reg = 0x00009888, .val = 0x13E304D2 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext99__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext99__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext99__avg_gpu_core_frequency__max,acmgt1__ext99__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1207, 24, percentage_max_float,acmgt1__ext99__sampler_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1208, 28, percentage_max_float,acmgt1__ext99__sampler_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1209, 32, percentage_max_float,acmgt1__ext99__sampler_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1210, 36, percentage_max_float,acmgt1__ext99__sampler_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext100_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext100";
   query->symbol_name = "Ext100";
   query->guid = "978e5720-eb5a-46fc-aa24-7a34a853130b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E847400 },
         { .reg = 0x00009888, .val = 0x1EA47400 },
         { .reg = 0x00009888, .val = 0x1EC47400 },
         { .reg = 0x00009888, .val = 0x1EE47400 },
         { .reg = 0x00009888, .val = 0x1F847400 },
         { .reg = 0x00009888, .val = 0x1FA47400 },
         { .reg = 0x00009888, .val = 0x1FC47400 },
         { .reg = 0x00009888, .val = 0x1FE47400 },
         { .reg = 0x00009888, .val = 0x04846810 },
         { .reg = 0x00009888, .val = 0x06840035 },
         { .reg = 0x00009888, .val = 0x02840000 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A40010 },
         { .reg = 0x00009888, .val = 0x06A40D00 },
         { .reg = 0x00009888, .val = 0x08A40035 },
         { .reg = 0x00009888, .val = 0x02A40000 },
         { .reg = 0x00009888, .val = 0x00A40000 },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C40010 },
         { .reg = 0x00009888, .val = 0x08C40D00 },
         { .reg = 0x00009888, .val = 0x0AC40035 },
         { .reg = 0x00009888, .val = 0x02C40000 },
         { .reg = 0x00009888, .val = 0x00C40000 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E40010 },
         { .reg = 0x00009888, .val = 0x0AE40D00 },
         { .reg = 0x00009888, .val = 0x0CE40035 },
         { .reg = 0x00009888, .val = 0x02E40000 },
         { .reg = 0x00009888, .val = 0x00E40000 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05840010 },
         { .reg = 0x00009888, .val = 0x13840D00 },
         { .reg = 0x00009888, .val = 0x15840035 },
         { .reg = 0x00009888, .val = 0x03840000 },
         { .reg = 0x00009888, .val = 0x01840000 },
         { .reg = 0x00009888, .val = 0x03865000 },
         { .reg = 0x00009888, .val = 0x05A40010 },
         { .reg = 0x00009888, .val = 0x11A40D00 },
         { .reg = 0x00009888, .val = 0x13A40035 },
         { .reg = 0x00009888, .val = 0x03A40000 },
         { .reg = 0x00009888, .val = 0x01A40000 },
         { .reg = 0x00009888, .val = 0x03A60500 },
         { .reg = 0x00009888, .val = 0x05C40010 },
         { .reg = 0x00009888, .val = 0x0FC40D00 },
         { .reg = 0x00009888, .val = 0x11C40035 },
         { .reg = 0x00009888, .val = 0x03C40000 },
         { .reg = 0x00009888, .val = 0x01C40000 },
         { .reg = 0x00009888, .val = 0x03C60050 },
         { .reg = 0x00009888, .val = 0x05E40010 },
         { .reg = 0x00009888, .val = 0x0DE40D00 },
         { .reg = 0x00009888, .val = 0x0FE40035 },
         { .reg = 0x00009888, .val = 0x03E40000 },
         { .reg = 0x00009888, .val = 0x01E40000 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x030700A5 },
         { .reg = 0x00009888, .val = 0x0308AF00 },
         { .reg = 0x00009888, .val = 0x01090F00 },
         { .reg = 0x00009888, .val = 0x030A55AA },
         { .reg = 0x00009888, .val = 0x01013000 },
         { .reg = 0x00009888, .val = 0x030B0500 },
         { .reg = 0x00009888, .val = 0x01020C00 },
         { .reg = 0x00009888, .val = 0x030C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x480300EA },
         { .reg = 0x00009888, .val = 0x4A030607 },
         { .reg = 0x00009888, .val = 0x4C031068 },
         { .reg = 0x00009888, .val = 0x4E030E77 },
         { .reg = 0x00009888, .val = 0x50031407 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030843 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext100__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext100__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext100__avg_gpu_core_frequency__max,acmgt1__ext100__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1211, 24, percentage_max_float,acmgt1__ext100__sampler_memory_latency_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1212, 28, percentage_max_float,acmgt1__ext100__sampler_memory_latency_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1213, 32, percentage_max_float,acmgt1__ext100__sampler_memory_latency_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1214, 36, percentage_max_float,acmgt1__ext100__sampler_memory_latency_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1215, 40, percentage_max_float,acmgt1__ext100__sampler_memory_latency_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1216, 44, percentage_max_float,acmgt1__ext100__sampler_memory_latency_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1217, 48, percentage_max_float,acmgt1__ext100__sampler_memory_latency_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1218, 52, percentage_max_float,acmgt1__ext100__sampler_memory_latency_stall_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext101_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext101";
   query->symbol_name = "Ext101";
   query->guid = "9320b9d5-43c9-435d-b0ed-ec8a565d742d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810032 },
         { .reg = 0x00009888, .val = 0x10810034 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x02830002 },
         { .reg = 0x00009888, .val = 0x00840101 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x02870001 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x08A10C80 },
         { .reg = 0x00009888, .val = 0x10A10D00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x02A30008 },
         { .reg = 0x00009888, .val = 0x00A40202 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x02A70004 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0AC10032 },
         { .reg = 0x00009888, .val = 0x12C10034 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x02C30020 },
         { .reg = 0x00009888, .val = 0x00C40404 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x02C70010 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0AE10C80 },
         { .reg = 0x00009888, .val = 0x12E10D00 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E30080 },
         { .reg = 0x00009888, .val = 0x00E40808 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E70040 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x0D810032 },
         { .reg = 0x00009888, .val = 0x15810034 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x03830200 },
         { .reg = 0x00009888, .val = 0x01841010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x03870100 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x0DA10C80 },
         { .reg = 0x00009888, .val = 0x15A10D00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x03A30800 },
         { .reg = 0x00009888, .val = 0x01A42020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x03A70400 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x0FC10032 },
         { .reg = 0x00009888, .val = 0x17C10034 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x03C32000 },
         { .reg = 0x00009888, .val = 0x01C44040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x03C71000 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x0FE10C80 },
         { .reg = 0x00009888, .val = 0x17E10D00 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E38000 },
         { .reg = 0x00009888, .val = 0x01E48080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E74000 },
         { .reg = 0x00009888, .val = 0x0003F0F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208FF0E },
         { .reg = 0x00009888, .val = 0x00090C0C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A55A5 },
         { .reg = 0x00009888, .val = 0x0001F2F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020BAA04 },
         { .reg = 0x00009888, .val = 0x00020404 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x03080E00 },
         { .reg = 0x00009888, .val = 0x0109C0C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030AA500 },
         { .reg = 0x00009888, .val = 0x01012020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0400 },
         { .reg = 0x00009888, .val = 0x01024040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x48031060 },
         { .reg = 0x00009888, .val = 0x4A030277 },
         { .reg = 0x00009888, .val = 0x4C030602 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x500314EA },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030007 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x440308E8 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46032803 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext101__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext101__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext101__avg_gpu_core_frequency__max,acmgt1__ext101__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1219, 24, percentage_max_float,acmgt1__ext101__thread_dispatch_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1220, 28, percentage_max_float,acmgt1__ext101__thread_dispatch_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1221, 32, percentage_max_float,acmgt1__ext101__thread_dispatch_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1222, 36, percentage_max_float,acmgt1__ext101__thread_dispatch_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1223, 40, percentage_max_float,acmgt1__ext101__thread_dispatch_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1224, 44, percentage_max_float,acmgt1__ext101__thread_dispatch_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1225, 48, percentage_max_float,acmgt1__ext101__thread_dispatch_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1226, 52, percentage_max_float,acmgt1__ext101__thread_dispatch_stall_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1227, 56, percentage_max_float,acmgt1__ext101__thread_dispatch_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1228, 60, percentage_max_float,acmgt1__ext101__thread_dispatch_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1229, 64, percentage_max_float,acmgt1__ext101__thread_dispatch_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1230, 68, percentage_max_float,acmgt1__ext101__thread_dispatch_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1231, 72, percentage_max_float,acmgt1__ext101__thread_dispatch_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1232, 76, percentage_max_float,acmgt1__ext101__thread_dispatch_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1233, 80, percentage_max_float,acmgt1__ext101__thread_dispatch_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1234, 84, percentage_max_float,acmgt1__ext101__thread_dispatch_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext102_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext102";
   query->symbol_name = "Ext102";
   query->guid = "ff32c8bc-39ed-4dbe-9d88-2d2cdb973872";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830C80 },
         { .reg = 0x00009888, .val = 0x12830CC0 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x0AA30032 },
         { .reg = 0x00009888, .val = 0x12A30033 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x08C30C80 },
         { .reg = 0x00009888, .val = 0x10C30CC0 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x08E30032 },
         { .reg = 0x00009888, .val = 0x10E30033 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x07830C80 },
         { .reg = 0x00009888, .val = 0x0F830CC0 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x07A30032 },
         { .reg = 0x00009888, .val = 0x0FA30033 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C30C80 },
         { .reg = 0x00009888, .val = 0x0DC30CC0 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E30032 },
         { .reg = 0x00009888, .val = 0x0DE30033 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030600 },
         { .reg = 0x00009888, .val = 0x4A030E21 },
         { .reg = 0x00009888, .val = 0x4C031067 },
         { .reg = 0x00009888, .val = 0x4E030E07 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031C43 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x46032808 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext102__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext102__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext102__avg_gpu_core_frequency__max,acmgt1__ext102__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1235, 24, NULL,acmgt1__ext102__sampler_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1236, 32, NULL,acmgt1__ext102__sampler_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1237, 40, NULL,acmgt1__ext102__sampler_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1238, 48, NULL,acmgt1__ext102__sampler_texture_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1239, 56, NULL,acmgt1__ext102__sampler_texture_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1240, 64, NULL,acmgt1__ext102__sampler_texture_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1241, 72, NULL,acmgt1__ext102__sampler_texture_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1242, 80, NULL,acmgt1__ext102__sampler_texture_cache_access_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1243, 88, NULL,acmgt1__ext102__sampler_texture_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1244, 96, NULL,acmgt1__ext102__sampler_texture_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1245, 104, NULL,acmgt1__ext102__sampler_texture_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1246, 112, NULL,acmgt1__ext102__sampler_texture_cache_miss_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1247, 120, NULL,acmgt1__ext102__sampler_texture_cache_miss_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1248, 128, NULL,acmgt1__ext102__sampler_texture_cache_miss_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1249, 136, NULL,acmgt1__ext102__sampler_texture_cache_miss_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1250, 144, NULL,acmgt1__ext102__sampler_texture_cache_miss_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext103_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext103";
   query->symbol_name = "Ext103";
   query->guid = "73a834ac-afbe-4ca1-af18-af9aabc0280a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824800 },
         { .reg = 0x00009888, .val = 0x08820023 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00830005 },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20900 },
         { .reg = 0x00009888, .val = 0x0AA20023 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A30050 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x0AC20900 },
         { .reg = 0x00009888, .val = 0x0CC20023 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C30500 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0CE20900 },
         { .reg = 0x00009888, .val = 0x0EE20023 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x00E35000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0F820900 },
         { .reg = 0x00009888, .val = 0x11820023 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x03830005 },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x13A20023 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x03A30050 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x13C20900 },
         { .reg = 0x00009888, .val = 0x15C20023 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x03C30500 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x15E20900 },
         { .reg = 0x00009888, .val = 0x17E20023 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x03E35000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x480300EA },
         { .reg = 0x00009888, .val = 0x4A030607 },
         { .reg = 0x00009888, .val = 0x4C031068 },
         { .reg = 0x00009888, .val = 0x4E030E77 },
         { .reg = 0x00009888, .val = 0x50030427 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030021 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46032940 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext103__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext103__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext103__avg_gpu_core_frequency__max,acmgt1__ext103__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1251, 24, percentage_max_float,acmgt1__ext103__sampler_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1252, 28, percentage_max_float,acmgt1__ext103__sampler_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1253, 32, percentage_max_float,acmgt1__ext103__sampler_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1254, 36, percentage_max_float,acmgt1__ext103__sampler_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1255, 40, percentage_max_float,acmgt1__ext103__sampler_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1256, 44, percentage_max_float,acmgt1__ext103__sampler_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1257, 48, percentage_max_float,acmgt1__ext103__sampler_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1258, 52, percentage_max_float,acmgt1__ext103__sampler_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext104_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext104";
   query->symbol_name = "Ext104";
   query->guid = "eb13a257-4c07-469e-8bef-55da7dff1b41";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810C70 },
         { .reg = 0x00009888, .val = 0x0A810CF2 },
         { .reg = 0x00009888, .val = 0x0C810DB7 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830AAA },
         { .reg = 0x00009888, .val = 0x0084003F },
         { .reg = 0x00009888, .val = 0x00860555 },
         { .reg = 0x00009888, .val = 0x00870555 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0EC10CF2 },
         { .reg = 0x00009888, .val = 0x10C10D74 },
         { .reg = 0x00009888, .val = 0x12C10039 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C3002A },
         { .reg = 0x00009888, .val = 0x00C407C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60015 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70015 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x12E10C80 },
         { .reg = 0x00009888, .val = 0x14E10D33 },
         { .reg = 0x00009888, .val = 0x16E10E75 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AA80 },
         { .reg = 0x00009888, .val = 0x00E4F800 },
         { .reg = 0x00009888, .val = 0x02E65540 },
         { .reg = 0x00009888, .val = 0x02E75540 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x0207556A },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009888, .val = 0x0009FFC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000207C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0015 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030221 },
         { .reg = 0x00009888, .val = 0x4C030422 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032940 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x0005C002 },
         { .reg = 0x0000D95C, .val = 0x000007FF },
         { .reg = 0x0000D960, .val = 0x00002202 },
         { .reg = 0x0000D964, .val = 0x0000F83F },
         { .reg = 0x0000D968, .val = 0x00044002 },
         { .reg = 0x0000D96C, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext104__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext104__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext104__avg_gpu_core_frequency__max,acmgt1__ext104__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1259, 24, NULL,acmgt1__ext104__async_gpgpu_thread_exit_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1260, 32, NULL,acmgt1__ext104__task_thread_exit_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1261, 40, NULL,acmgt1__ext104__gpgpu_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1262, 48, NULL,acmgt1__ext104__gpgpu_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1263, 56, NULL,acmgt1__ext104__task_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1264, 64, NULL,acmgt1__ext104__task_threadgroup_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext105_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext105";
   query->symbol_name = "Ext105";
   query->guid = "0343e7a1-8f7d-44b8-a75c-73baef6cc22b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10C70 },
         { .reg = 0x00009888, .val = 0x0AA10CF2 },
         { .reg = 0x00009888, .val = 0x0CA10DB7 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30AAA },
         { .reg = 0x00009888, .val = 0x00A4003F },
         { .reg = 0x00009888, .val = 0x00A60555 },
         { .reg = 0x00009888, .val = 0x00A70555 },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0F810CF2 },
         { .reg = 0x00009888, .val = 0x11810D74 },
         { .reg = 0x00009888, .val = 0x13810039 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x0383002A },
         { .reg = 0x00009888, .val = 0x018407C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x03860015 },
         { .reg = 0x00009888, .val = 0x01875000 },
         { .reg = 0x00009888, .val = 0x03870015 },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x13A10C80 },
         { .reg = 0x00009888, .val = 0x15A10D33 },
         { .reg = 0x00009888, .val = 0x17A10E75 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AA80 },
         { .reg = 0x00009888, .val = 0x01A4F800 },
         { .reg = 0x00009888, .val = 0x03A65540 },
         { .reg = 0x00009888, .val = 0x03A75540 },
         { .reg = 0x00009888, .val = 0x0003FFC0 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BA555 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108A000 },
         { .reg = 0x00009888, .val = 0x0308FFEA },
         { .reg = 0x00009888, .val = 0x010A5000 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101F800 },
         { .reg = 0x00009888, .val = 0x030B5540 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2A033000 },
         { .reg = 0x00009888, .val = 0x48031068 },
         { .reg = 0x00009888, .val = 0x4A030683 },
         { .reg = 0x00009888, .val = 0x4C031068 },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x0005C002 },
         { .reg = 0x0000D95C, .val = 0x000007FF },
         { .reg = 0x0000D960, .val = 0x00002202 },
         { .reg = 0x0000D964, .val = 0x0000F83F },
         { .reg = 0x0000D968, .val = 0x00044002 },
         { .reg = 0x0000D96C, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext105__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext105__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext105__avg_gpu_core_frequency__max,acmgt1__ext105__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1265, 24, NULL,acmgt1__ext105__async_gpgpu_thread_exit_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1266, 32, NULL,acmgt1__ext105__task_thread_exit_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1267, 40, NULL,acmgt1__ext105__gpgpu_threadgroup_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1268, 48, NULL,acmgt1__ext105__gpgpu_threadgroup_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1269, 56, NULL,acmgt1__ext105__task_threadgroup_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1270, 64, NULL,acmgt1__ext105__task_threadgroup_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext106_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext106";
   query->symbol_name = "Ext106";
   query->guid = "048a2bcb-b786-4b51-b350-8908f50e69d7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x08C10C70 },
         { .reg = 0x00009888, .val = 0x0AC10CF2 },
         { .reg = 0x00009888, .val = 0x0CC10DB7 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30AAA },
         { .reg = 0x00009888, .val = 0x00C4003F },
         { .reg = 0x00009888, .val = 0x00C60555 },
         { .reg = 0x00009888, .val = 0x00C70555 },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0FC10CF2 },
         { .reg = 0x00009888, .val = 0x11C10D74 },
         { .reg = 0x00009888, .val = 0x13C10039 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C3002A },
         { .reg = 0x00009888, .val = 0x01C407C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60015 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70015 },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x13E10C80 },
         { .reg = 0x00009888, .val = 0x15E10D33 },
         { .reg = 0x00009888, .val = 0x17E10E75 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA80 },
         { .reg = 0x00009888, .val = 0x01E4F800 },
         { .reg = 0x00009888, .val = 0x03E65540 },
         { .reg = 0x00009888, .val = 0x03E75540 },
         { .reg = 0x00009888, .val = 0x0003FFC0 },
         { .reg = 0x00009888, .val = 0x00070AAA },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x0009003F },
         { .reg = 0x00009888, .val = 0x000A5AAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFC0 },
         { .reg = 0x00009888, .val = 0x000BA000 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0002003F },
         { .reg = 0x00009888, .val = 0x000C0555 },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x0307556A },
         { .reg = 0x00009888, .val = 0x0109FFC0 },
         { .reg = 0x00009888, .val = 0x010AA000 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010207C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0015 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2A033000 },
         { .reg = 0x00009888, .val = 0x48031068 },
         { .reg = 0x00009888, .val = 0x4A030683 },
         { .reg = 0x00009888, .val = 0x4C031068 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032940 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x0005C002 },
         { .reg = 0x0000D95C, .val = 0x000007FF },
         { .reg = 0x0000D960, .val = 0x00002202 },
         { .reg = 0x0000D964, .val = 0x0000F83F },
         { .reg = 0x0000D968, .val = 0x00044002 },
         { .reg = 0x0000D96C, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext106__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext106__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext106__avg_gpu_core_frequency__max,acmgt1__ext106__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1271, 24, NULL,acmgt1__ext106__async_gpgpu_thread_exit_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1272, 32, NULL,acmgt1__ext106__task_thread_exit_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1273, 40, NULL,acmgt1__ext106__gpgpu_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1274, 48, NULL,acmgt1__ext106__gpgpu_threadgroup_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1275, 56, NULL,acmgt1__ext106__task_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1276, 64, NULL,acmgt1__ext106__task_threadgroup_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext107_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext107";
   query->symbol_name = "Ext107";
   query->guid = "e393956e-78b0-4f7e-8482-cb13c1706ecd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0E810CF2 },
         { .reg = 0x00009888, .val = 0x10810D74 },
         { .reg = 0x00009888, .val = 0x12810039 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A000 },
         { .reg = 0x00009888, .val = 0x0283002A },
         { .reg = 0x00009888, .val = 0x008407C0 },
         { .reg = 0x00009888, .val = 0x00865000 },
         { .reg = 0x00009888, .val = 0x02860015 },
         { .reg = 0x00009888, .val = 0x00875000 },
         { .reg = 0x00009888, .val = 0x02870015 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x12A10C80 },
         { .reg = 0x00009888, .val = 0x14A10D33 },
         { .reg = 0x00009888, .val = 0x16A10E75 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AA80 },
         { .reg = 0x00009888, .val = 0x00A4F800 },
         { .reg = 0x00009888, .val = 0x02A65540 },
         { .reg = 0x00009888, .val = 0x02A75540 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10C70 },
         { .reg = 0x00009888, .val = 0x0AE10CF2 },
         { .reg = 0x00009888, .val = 0x0CE10DB7 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30AAA },
         { .reg = 0x00009888, .val = 0x00E4003F },
         { .reg = 0x00009888, .val = 0x00E60555 },
         { .reg = 0x00009888, .val = 0x00E70555 },
         { .reg = 0x00009888, .val = 0x00070555 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x0208FFEA },
         { .reg = 0x00009888, .val = 0x0009003F },
         { .reg = 0x00009888, .val = 0x000A5AAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001F800 },
         { .reg = 0x00009888, .val = 0x020B5540 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031C00 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030E07 },
         { .reg = 0x00009888, .val = 0x4A030070 },
         { .reg = 0x00009888, .val = 0x4C030E07 },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x0005C002 },
         { .reg = 0x0000D95C, .val = 0x000007FF },
         { .reg = 0x0000D960, .val = 0x00002202 },
         { .reg = 0x0000D964, .val = 0x0000F83F },
         { .reg = 0x0000D968, .val = 0x00044002 },
         { .reg = 0x0000D96C, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext107__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext107__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext107__avg_gpu_core_frequency__max,acmgt1__ext107__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1277, 24, NULL,acmgt1__ext107__async_gpgpu_thread_exit_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1278, 32, NULL,acmgt1__ext107__task_thread_exit_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1279, 40, NULL,acmgt1__ext107__gpgpu_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1280, 48, NULL,acmgt1__ext107__gpgpu_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1281, 56, NULL,acmgt1__ext107__task_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1282, 64, NULL,acmgt1__ext107__task_threadgroup_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext108_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext108";
   query->symbol_name = "Ext108";
   query->guid = "2ea41c1b-4751-446f-b178-9aa17cf85d72";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001D },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001D },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810C70 },
         { .reg = 0x00009888, .val = 0x0B810CF2 },
         { .reg = 0x00009888, .val = 0x0D810DB7 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830AAA },
         { .reg = 0x00009888, .val = 0x0184003F },
         { .reg = 0x00009888, .val = 0x01860555 },
         { .reg = 0x00009888, .val = 0x01870555 },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0FC10CF2 },
         { .reg = 0x00009888, .val = 0x11C10D74 },
         { .reg = 0x00009888, .val = 0x13C1003E },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C3002A },
         { .reg = 0x00009888, .val = 0x01C407C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60015 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70015 },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x13E10C80 },
         { .reg = 0x00009888, .val = 0x15E10D33 },
         { .reg = 0x00009888, .val = 0x17E10FB5 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA80 },
         { .reg = 0x00009888, .val = 0x01E4F800 },
         { .reg = 0x00009888, .val = 0x03E65540 },
         { .reg = 0x00009888, .val = 0x03E75540 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x0307556A },
         { .reg = 0x00009888, .val = 0x01080AAA },
         { .reg = 0x00009888, .val = 0x0109FFC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010207C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0015 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030221 },
         { .reg = 0x00009888, .val = 0x4C030422 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032940 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00003002 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00060002 },
         { .reg = 0x0000D95C, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext108__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext108__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext108__avg_gpu_core_frequency__max,acmgt1__ext108__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1283, 24, NULL,acmgt1__ext108__async_gpgpu_thread_exit_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1284, 32, NULL,acmgt1__ext108__task_thread_exit_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1285, 40, NULL,acmgt1__ext108__async_gpgpu_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1286, 48, NULL,acmgt1__ext108__async_gpgpu_threadgroup_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext109_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext109";
   query->symbol_name = "Ext109";
   query->guid = "32b61c78-b7d2-4162-8964-dbf47f187290";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001D },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001D },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0EA10CF2 },
         { .reg = 0x00009888, .val = 0x10A10D74 },
         { .reg = 0x00009888, .val = 0x12A1003E },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A000 },
         { .reg = 0x00009888, .val = 0x02A3002A },
         { .reg = 0x00009888, .val = 0x00A407C0 },
         { .reg = 0x00009888, .val = 0x00A65000 },
         { .reg = 0x00009888, .val = 0x02A60015 },
         { .reg = 0x00009888, .val = 0x00A75000 },
         { .reg = 0x00009888, .val = 0x02A70015 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x12C10C80 },
         { .reg = 0x00009888, .val = 0x14C10D33 },
         { .reg = 0x00009888, .val = 0x16C10FB5 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C3AA80 },
         { .reg = 0x00009888, .val = 0x00C4F800 },
         { .reg = 0x00009888, .val = 0x02C65540 },
         { .reg = 0x00009888, .val = 0x02C75540 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x09A10C70 },
         { .reg = 0x00009888, .val = 0x0BA10CF2 },
         { .reg = 0x00009888, .val = 0x0DA10DB7 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30AAA },
         { .reg = 0x00009888, .val = 0x01A4003F },
         { .reg = 0x00009888, .val = 0x01A60555 },
         { .reg = 0x00009888, .val = 0x01A70555 },
         { .reg = 0x00009888, .val = 0x0003003F },
         { .reg = 0x00009888, .val = 0x0207AA80 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208003F },
         { .reg = 0x00009888, .val = 0x0009F800 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAA95 },
         { .reg = 0x00009888, .val = 0x000107FF },
         { .reg = 0x00009888, .val = 0x000B5AAA },
         { .reg = 0x00009888, .val = 0x020B0015 },
         { .reg = 0x00009888, .val = 0x0002F800 },
         { .reg = 0x00009888, .val = 0x020C5540 },
         { .reg = 0x00009888, .val = 0x01080FFF },
         { .reg = 0x00009888, .val = 0x010A0555 },
         { .reg = 0x00009888, .val = 0x0101003F },
         { .reg = 0x00009888, .val = 0x010B0555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030683 },
         { .reg = 0x00009888, .val = 0x50031068 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030083 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x440314A8 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x460314A5 },
         { .reg = 0x00009888, .val = 0x24033000 },
         { .reg = 0x00009888, .val = 0x28033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00003002 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00060002 },
         { .reg = 0x0000D95C, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext109__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext109__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext109__avg_gpu_core_frequency__max,acmgt1__ext109__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1287, 24, NULL,acmgt1__ext109__async_gpgpu_thread_exit_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1288, 32, NULL,acmgt1__ext109__task_thread_exit_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1289, 40, NULL,acmgt1__ext109__async_gpgpu_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1290, 48, NULL,acmgt1__ext109__async_gpgpu_threadgroup_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext110_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext110";
   query->symbol_name = "Ext110";
   query->guid = "536ed3af-e1e6-4f5a-be8b-3eabfa9487fa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001D },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001D },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0EE10CF2 },
         { .reg = 0x00009888, .val = 0x10E10D74 },
         { .reg = 0x00009888, .val = 0x12E1003E },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x02E3002A },
         { .reg = 0x00009888, .val = 0x00E407C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x02E60015 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x02E70015 },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x13810C80 },
         { .reg = 0x00009888, .val = 0x15810D33 },
         { .reg = 0x00009888, .val = 0x17810FB5 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AA80 },
         { .reg = 0x00009888, .val = 0x0184F800 },
         { .reg = 0x00009888, .val = 0x03865540 },
         { .reg = 0x00009888, .val = 0x03875540 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10C70 },
         { .reg = 0x00009888, .val = 0x0BC10CF2 },
         { .reg = 0x00009888, .val = 0x0DC10DB7 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30AAA },
         { .reg = 0x00009888, .val = 0x01C4003F },
         { .reg = 0x00009888, .val = 0x01C60555 },
         { .reg = 0x00009888, .val = 0x01C70555 },
         { .reg = 0x00009888, .val = 0x0003F83F },
         { .reg = 0x00009888, .val = 0x00075000 },
         { .reg = 0x00009888, .val = 0x02070015 },
         { .reg = 0x00009888, .val = 0x00080FFF },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000907C0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A556A },
         { .reg = 0x00009888, .val = 0x0001F83F },
         { .reg = 0x00009888, .val = 0x000B0AAA },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01070AAA },
         { .reg = 0x00009888, .val = 0x0308AA80 },
         { .reg = 0x00009888, .val = 0x0109003F },
         { .reg = 0x00009888, .val = 0x010A0AAA },
         { .reg = 0x00009888, .val = 0x030A5540 },
         { .reg = 0x00009888, .val = 0x0102003F },
         { .reg = 0x00009888, .val = 0x010C0555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030E77 },
         { .reg = 0x00009888, .val = 0x50030EE7 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030077 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x44030847 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00003002 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00060002 },
         { .reg = 0x0000D95C, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext110__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext110__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext110__avg_gpu_core_frequency__max,acmgt1__ext110__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1291, 24, NULL,acmgt1__ext110__async_gpgpu_thread_exit_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1292, 32, NULL,acmgt1__ext110__task_thread_exit_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1293, 40, NULL,acmgt1__ext110__async_gpgpu_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1294, 48, NULL,acmgt1__ext110__async_gpgpu_threadgroup_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext111_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext111";
   query->symbol_name = "Ext111";
   query->guid = "11eedd05-3490-4a57-8ea7-56e1d2dd066a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001D },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001D },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x12810C80 },
         { .reg = 0x00009888, .val = 0x14810D33 },
         { .reg = 0x00009888, .val = 0x16810FB5 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AA80 },
         { .reg = 0x00009888, .val = 0x0084F800 },
         { .reg = 0x00009888, .val = 0x02865540 },
         { .reg = 0x00009888, .val = 0x02875540 },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0FA10CF2 },
         { .reg = 0x00009888, .val = 0x11A10D74 },
         { .reg = 0x00009888, .val = 0x13A1003E },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A000 },
         { .reg = 0x00009888, .val = 0x03A3002A },
         { .reg = 0x00009888, .val = 0x01A407C0 },
         { .reg = 0x00009888, .val = 0x01A65000 },
         { .reg = 0x00009888, .val = 0x03A60015 },
         { .reg = 0x00009888, .val = 0x01A75000 },
         { .reg = 0x00009888, .val = 0x03A70015 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10C70 },
         { .reg = 0x00009888, .val = 0x0BE10CF2 },
         { .reg = 0x00009888, .val = 0x0DE10DB7 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30AAA },
         { .reg = 0x00009888, .val = 0x01E4003F },
         { .reg = 0x00009888, .val = 0x01E60555 },
         { .reg = 0x00009888, .val = 0x01E70555 },
         { .reg = 0x00009888, .val = 0x000307FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AABF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x000107FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B002A },
         { .reg = 0x00009888, .val = 0x01070555 },
         { .reg = 0x00009888, .val = 0x0108F000 },
         { .reg = 0x00009888, .val = 0x0308003F },
         { .reg = 0x00009888, .val = 0x0109003F },
         { .reg = 0x00009888, .val = 0x010A5AAA },
         { .reg = 0x00009888, .val = 0x030A0015 },
         { .reg = 0x00009888, .val = 0x010107C0 },
         { .reg = 0x00009888, .val = 0x010B5000 },
         { .reg = 0x00009888, .val = 0x030B0015 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42031C00 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030E07 },
         { .reg = 0x00009888, .val = 0x4A030070 },
         { .reg = 0x00009888, .val = 0x4C030E07 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031CE0 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46031CE7 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00003002 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00060002 },
         { .reg = 0x0000D95C, .val = 0x000007FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext111__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext111__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext111__avg_gpu_core_frequency__max,acmgt1__ext111__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1295, 24, NULL,acmgt1__ext111__async_gpgpu_thread_exit_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1296, 32, NULL,acmgt1__ext111__task_thread_exit_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1297, 40, NULL,acmgt1__ext111__async_gpgpu_threadgroup_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1298, 48, NULL,acmgt1__ext111__async_gpgpu_threadgroup_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext112_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext112";
   query->symbol_name = "Ext112";
   query->guid = "2324dd37-ac7e-4a5e-8d0c-f7b94fd36961";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C817400 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2CA17400 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2CC17400 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2CE17400 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2D817400 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x2DA17400 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x2DC17400 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x2DE17400 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0E810DC0 },
         { .reg = 0x00009888, .val = 0x16810E00 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0EA10037 },
         { .reg = 0x00009888, .val = 0x16A10038 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10DC0 },
         { .reg = 0x00009888, .val = 0x14C10E00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10037 },
         { .reg = 0x00009888, .val = 0x14E10038 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0B810DC0 },
         { .reg = 0x00009888, .val = 0x13810E00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0BA10037 },
         { .reg = 0x00009888, .val = 0x13A10038 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x09C10DC0 },
         { .reg = 0x00009888, .val = 0x11C10E00 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x09E10037 },
         { .reg = 0x00009888, .val = 0x11E10038 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030600 },
         { .reg = 0x00009888, .val = 0x4A030E21 },
         { .reg = 0x00009888, .val = 0x4C031067 },
         { .reg = 0x00009888, .val = 0x4E030E07 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031C43 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x46032808 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext112__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext112__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext112__avg_gpu_core_frequency__max,acmgt1__ext112__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1299, 24, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1300, 28, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1301, 32, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1302, 36, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1303, 40, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1304, 44, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1305, 48, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1306, 52, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1307, 56, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1308, 60, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1309, 64, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1310, 68, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1311, 72, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1312, 76, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1313, 80, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1314, 84, percentage_max_float,acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext113_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext113";
   query->symbol_name = "Ext113";
   query->guid = "03551880-b834-45f0-8b71-e61f548e5d83";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x480300EA },
         { .reg = 0x00009888, .val = 0x4A030607 },
         { .reg = 0x00009888, .val = 0x4C031068 },
         { .reg = 0x00009888, .val = 0x4E030E77 },
         { .reg = 0x00009888, .val = 0x50030427 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030021 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46032940 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext113__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext113__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext113__avg_gpu_core_frequency__max,acmgt1__ext113__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1315, 24, percentage_max_float,acmgt1__ext113__thread_dispatch_ps_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1316, 28, percentage_max_float,acmgt1__ext113__thread_dispatch_ps_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1317, 32, percentage_max_float,acmgt1__ext113__thread_dispatch_ps_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1318, 36, percentage_max_float,acmgt1__ext113__thread_dispatch_ps_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1319, 40, percentage_max_float,acmgt1__ext113__thread_dispatch_ps_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1320, 44, percentage_max_float,acmgt1__ext113__thread_dispatch_ps_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1321, 48, percentage_max_float,acmgt1__ext113__thread_dispatch_ps_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1322, 52, percentage_max_float,acmgt1__ext113__thread_dispatch_ps_active_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext114_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext114";
   query->symbol_name = "Ext114";
   query->guid = "8d368e2f-7c30-4a9e-a20f-b098105300b7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2A810002 },
         { .reg = 0x00009888, .val = 0x2AA10002 },
         { .reg = 0x00009888, .val = 0x2AC10002 },
         { .reg = 0x00009888, .val = 0x2AE10002 },
         { .reg = 0x00009888, .val = 0x2B810002 },
         { .reg = 0x00009888, .val = 0x2BA10002 },
         { .reg = 0x00009888, .val = 0x2BC10002 },
         { .reg = 0x00009888, .val = 0x2BE10002 },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810034 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10D00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10034 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10D00 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810034 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10D00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10034 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10D00 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000400FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x48031060 },
         { .reg = 0x00009888, .val = 0x4A030277 },
         { .reg = 0x00009888, .val = 0x4C030602 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext114__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext114__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext114__avg_gpu_core_frequency__max,acmgt1__ext114__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1323, 24, percentage_max_float,acmgt1__ext114__thread_dispatch_queue0_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1324, 28, percentage_max_float,acmgt1__ext114__thread_dispatch_queue0_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1325, 32, percentage_max_float,acmgt1__ext114__thread_dispatch_queue0_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1326, 36, percentage_max_float,acmgt1__ext114__thread_dispatch_queue0_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1327, 40, percentage_max_float,acmgt1__ext114__thread_dispatch_queue0_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1328, 44, percentage_max_float,acmgt1__ext114__thread_dispatch_queue0_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1329, 48, percentage_max_float,acmgt1__ext114__thread_dispatch_queue0_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1330, 52, percentage_max_float,acmgt1__ext114__thread_dispatch_queue0_active_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext115_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext115";
   query->symbol_name = "Ext115";
   query->guid = "cb96d66c-bfc4-4de8-a3dc-5d67c5acda38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2A810004 },
         { .reg = 0x00009888, .val = 0x2AA10004 },
         { .reg = 0x00009888, .val = 0x2AC10004 },
         { .reg = 0x00009888, .val = 0x2AE10004 },
         { .reg = 0x00009888, .val = 0x2B810004 },
         { .reg = 0x00009888, .val = 0x2BA10004 },
         { .reg = 0x00009888, .val = 0x2BC10004 },
         { .reg = 0x00009888, .val = 0x2BE10004 },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810035 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10D40 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10035 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10D40 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810035 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10D40 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10035 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10D40 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000400FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x48031060 },
         { .reg = 0x00009888, .val = 0x4A030277 },
         { .reg = 0x00009888, .val = 0x4C030602 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext115__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext115__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext115__avg_gpu_core_frequency__max,acmgt1__ext115__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1331, 24, percentage_max_float,acmgt1__ext115__thread_dispatch_queue1_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1332, 28, percentage_max_float,acmgt1__ext115__thread_dispatch_queue1_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1333, 32, percentage_max_float,acmgt1__ext115__thread_dispatch_queue1_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1334, 36, percentage_max_float,acmgt1__ext115__thread_dispatch_queue1_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1335, 40, percentage_max_float,acmgt1__ext115__thread_dispatch_queue1_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1336, 44, percentage_max_float,acmgt1__ext115__thread_dispatch_queue1_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1337, 48, percentage_max_float,acmgt1__ext115__thread_dispatch_queue1_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1338, 52, percentage_max_float,acmgt1__ext115__thread_dispatch_queue1_active_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext116_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext116";
   query->symbol_name = "Ext116";
   query->guid = "2355cc8b-c596-479d-ab76-16c2d3644b5b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810DB7 },
         { .reg = 0x00009888, .val = 0x0A810CF5 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0CA10DB7 },
         { .reg = 0x00009888, .val = 0x0EA10CF5 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x10C10DB7 },
         { .reg = 0x00009888, .val = 0x12C10CF5 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x02C70055 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x14E10DB7 },
         { .reg = 0x00009888, .val = 0x16E10CF5 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000401 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00004001 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00040001 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext116__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext116__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext116__avg_gpu_core_frequency__max,acmgt1__ext116__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1339, 24, percentage_max_float,acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1340, 28, percentage_max_float,acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1341, 32, percentage_max_float,acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1342, 36, percentage_max_float,acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext117_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext117";
   query->symbol_name = "Ext117";
   query->guid = "006584d5-ebb1-4d21-a8ab-cfa66e75dae4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810DB7 },
         { .reg = 0x00009888, .val = 0x0B810CF5 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0DA10DB7 },
         { .reg = 0x00009888, .val = 0x0FA10CF5 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10DB7 },
         { .reg = 0x00009888, .val = 0x13C10CF5 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x03C70055 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x15E10DB7 },
         { .reg = 0x00009888, .val = 0x17E10CF5 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x03E75500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000401 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00004001 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00040001 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext117__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext117__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext117__avg_gpu_core_frequency__max,acmgt1__ext117__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1343, 24, percentage_max_float,acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1344, 28, percentage_max_float,acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1345, 32, percentage_max_float,acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1346, 36, percentage_max_float,acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext118_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext118";
   query->symbol_name = "Ext118";
   query->guid = "9ae38060-8785-44ec-a758-4082b94af42d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x14060700 },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x02060010 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x06060081 },
         { .reg = 0x00009888, .val = 0x080603C3 },
         { .reg = 0x00009888, .val = 0x0A06034E },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x00081555 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x16080BC0 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x0E080C40 },
         { .reg = 0x00009888, .val = 0x100809B8 },
         { .reg = 0x00009888, .val = 0x12080BD0 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F87F },
         { .reg = 0x00009888, .val = 0x00022AAA },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00031555 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x440314A0 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x460314A5 },
         { .reg = 0x00009888, .val = 0x24033000 },
         { .reg = 0x00009888, .val = 0x28033000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext118__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext118__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext118__avg_gpu_core_frequency__max,acmgt1__ext118__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1347, 24, percentage_max_float,acmgt1__ext118__amfs_stall_all_input_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1348, 28, percentage_max_float,acmgt1__ext118__amfs_stall_any_input_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1349, 32, NULL,acmgt1__ext118__amfs_cache_hit_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1350, 40, NULL,acmgt1__ext118__amfs_cache_miss_slice0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1351, 48, NULL,acmgt1__ext118__render_cache_hit_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1352, 56, NULL,acmgt1__ext118__render_cache_read_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1353, 64, NULL,acmgt1__ext118__render_cache_write_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1354, 72, percentage_max_float,acmgt1__ext118__render_cache_input_available_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1355, 76, percentage_max_float,acmgt1__ext118__render_cache_output_ready_l3_node0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext119_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext119";
   query->symbol_name = "Ext119";
   query->guid = "8ef448b2-776c-4d73-8a44-eabfb2fcc888";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x15060700 },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x03060010 },
         { .reg = 0x00009888, .val = 0x05060000 },
         { .reg = 0x00009888, .val = 0x07060081 },
         { .reg = 0x00009888, .val = 0x090603C3 },
         { .reg = 0x00009888, .val = 0x0B06034E },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01081555 },
         { .reg = 0x00009888, .val = 0x010A1555 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x16037840 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x0E030C40 },
         { .reg = 0x00009888, .val = 0x10030438 },
         { .reg = 0x00009888, .val = 0x12030BA7 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x0204AA80 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F87F },
         { .reg = 0x00009888, .val = 0x00022AAA },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00031555 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x44030C60 },
         { .reg = 0x00009888, .val = 0x2003F000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x2403F000 },
         { .reg = 0x00009888, .val = 0x2803F000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext119__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext119__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext119__avg_gpu_core_frequency__max,acmgt1__ext119__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1356, 24, percentage_max_float,acmgt1__ext119__amfs_stall_all_input_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1357, 28, percentage_max_float,acmgt1__ext119__amfs_stall_any_input_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1358, 32, NULL,acmgt1__ext119__amfs_cache_hit_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1359, 40, NULL,acmgt1__ext119__amfs_cache_miss_slice1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1360, 48, NULL,acmgt1__ext119__render_cache_hit_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1361, 56, NULL,acmgt1__ext119__render_cache_read_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1362, 64, NULL,acmgt1__ext119__render_cache_write_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1363, 72, percentage_max_float,acmgt1__ext119__render_cache_input_available_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1364, 76, percentage_max_float,acmgt1__ext119__render_cache_output_ready_l3_node1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext120_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext120";
   query->symbol_name = "Ext120";
   query->guid = "3b5b473c-259e-4eb7-8643-a88b53aa2e1c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x20860011 },
         { .reg = 0x00009888, .val = 0x20A60011 },
         { .reg = 0x00009888, .val = 0x20C60011 },
         { .reg = 0x00009888, .val = 0x20E60011 },
         { .reg = 0x00009888, .val = 0x04860180 },
         { .reg = 0x00009888, .val = 0x06862800 },
         { .reg = 0x00009888, .val = 0x08860595 },
         { .reg = 0x00009888, .val = 0x0A860017 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x04A60180 },
         { .reg = 0x00009888, .val = 0x0AA60500 },
         { .reg = 0x00009888, .val = 0x0CA60595 },
         { .reg = 0x00009888, .val = 0x0EA60017 },
         { .reg = 0x00009888, .val = 0x00A60000 },
         { .reg = 0x00009888, .val = 0x04C60180 },
         { .reg = 0x00009888, .val = 0x0EC60500 },
         { .reg = 0x00009888, .val = 0x10C60595 },
         { .reg = 0x00009888, .val = 0x12C60017 },
         { .reg = 0x00009888, .val = 0x02C60000 },
         { .reg = 0x00009888, .val = 0x04E60180 },
         { .reg = 0x00009888, .val = 0x12E60500 },
         { .reg = 0x00009888, .val = 0x14E60595 },
         { .reg = 0x00009888, .val = 0x16E60017 },
         { .reg = 0x00009888, .val = 0x02E60000 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext120__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext120__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext120__avg_gpu_core_frequency__max,acmgt1__ext120__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1365, 24, percentage_max_float,acmgt1__ext120__pixel_post_process_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1366, 28, percentage_max_float,acmgt1__ext120__pixel_post_process_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1367, 32, percentage_max_float,acmgt1__ext120__pixel_post_process_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1368, 36, percentage_max_float,acmgt1__ext120__pixel_post_process_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext121_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext121";
   query->symbol_name = "Ext121";
   query->guid = "f2045966-fcf0-479b-aef4-0358574f67ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x21860011 },
         { .reg = 0x00009888, .val = 0x21A60011 },
         { .reg = 0x00009888, .val = 0x21C60011 },
         { .reg = 0x00009888, .val = 0x21E60011 },
         { .reg = 0x00009888, .val = 0x05860180 },
         { .reg = 0x00009888, .val = 0x07862800 },
         { .reg = 0x00009888, .val = 0x09860595 },
         { .reg = 0x00009888, .val = 0x0B860017 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x05A60180 },
         { .reg = 0x00009888, .val = 0x0BA60500 },
         { .reg = 0x00009888, .val = 0x0DA60595 },
         { .reg = 0x00009888, .val = 0x0FA60017 },
         { .reg = 0x00009888, .val = 0x01A60000 },
         { .reg = 0x00009888, .val = 0x05C60180 },
         { .reg = 0x00009888, .val = 0x0FC60500 },
         { .reg = 0x00009888, .val = 0x11C60595 },
         { .reg = 0x00009888, .val = 0x13C60017 },
         { .reg = 0x00009888, .val = 0x03C60000 },
         { .reg = 0x00009888, .val = 0x05E60180 },
         { .reg = 0x00009888, .val = 0x13E60500 },
         { .reg = 0x00009888, .val = 0x15E60595 },
         { .reg = 0x00009888, .val = 0x17E60017 },
         { .reg = 0x00009888, .val = 0x03E60000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext121__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext121__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext121__avg_gpu_core_frequency__max,acmgt1__ext121__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1369, 24, percentage_max_float,acmgt1__ext121__pixel_post_process_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1370, 28, percentage_max_float,acmgt1__ext121__pixel_post_process_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1371, 32, percentage_max_float,acmgt1__ext121__pixel_post_process_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1372, 36, percentage_max_float,acmgt1__ext121__pixel_post_process_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext122_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Ext122";
   query->symbol_name = "Ext122";
   query->guid = "e175d8c3-7672-4e57-83a0-87caf56a5440";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x16010003 },
         { .reg = 0x00009888, .val = 0x12011000 },
         { .reg = 0x00009888, .val = 0x16020003 },
         { .reg = 0x00009888, .val = 0x12021C00 },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x17010003 },
         { .reg = 0x00009888, .val = 0x13011030 },
         { .reg = 0x00009888, .val = 0x17020003 },
         { .reg = 0x00009888, .val = 0x13021000 },
         { .reg = 0x00009888, .val = 0x0003330C },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x04060E00 },
         { .reg = 0x00009888, .val = 0x06060006 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x02072020 },
         { .reg = 0x00009888, .val = 0x000800F5 },
         { .reg = 0x00009888, .val = 0x0208CFCF },
         { .reg = 0x00009888, .val = 0x00094400 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A6565 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x10010017 },
         { .reg = 0x00009888, .val = 0x14010030 },
         { .reg = 0x00009888, .val = 0x0001330C },
         { .reg = 0x00009888, .val = 0x000B00A0 },
         { .reg = 0x00009888, .val = 0x020B0A0A },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x0E0205C0 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x070601C0 },
         { .reg = 0x00009888, .val = 0x09060006 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03070202 },
         { .reg = 0x00009888, .val = 0x01080050 },
         { .reg = 0x00009888, .val = 0x03080C0C },
         { .reg = 0x00009888, .val = 0x01091100 },
         { .reg = 0x00009888, .val = 0x010A0050 },
         { .reg = 0x00009888, .val = 0x030A0606 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x05010000 },
         { .reg = 0x00009888, .val = 0x0F010017 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x05020000 },
         { .reg = 0x00009888, .val = 0x0D0205C0 },
         { .reg = 0x00009888, .val = 0x11020C00 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FF0F },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00030055 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x48030801 },
         { .reg = 0x00009888, .val = 0x4A030040 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x44030008 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030103 },
         { .reg = 0x00009888, .val = 0x24033000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext122__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext122__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext122__avg_gpu_core_frequency__max,acmgt1__ext122__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1373, 24, NULL,acmgt1__ext122__amfs_4_x4_shading_request_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1374, 32, NULL,acmgt1__ext122__amfs_4_x4_shading_request_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1375, 40, percentage_max_float,acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1376, 44, percentage_max_float,acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1377, 48, percentage_max_float,acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1378, 52, percentage_max_float,acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1379, 56, percentage_max_float,acmgt1__ext122__pixel_post_process_output_ready_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1380, 60, percentage_max_float,acmgt1__ext122__pixel_post_process_output_ready_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1381, 64, percentage_max_float,acmgt1__ext122__pixel_post_process_output_ready_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1382, 68, percentage_max_float,acmgt1__ext122__pixel_post_process_output_ready_cpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext123_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext123";
   query->symbol_name = "Ext123";
   query->guid = "7f7218b1-462c-4f08-8032-86e426dbc83d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1606018A },
         { .reg = 0x00009888, .val = 0x18010320 },
         { .reg = 0x00009888, .val = 0x18020320 },
         { .reg = 0x00009888, .val = 0x1706018A },
         { .reg = 0x00009888, .val = 0x19010320 },
         { .reg = 0x00009888, .val = 0x19020320 },
         { .reg = 0x00009888, .val = 0x000342F0 },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x0C060000 },
         { .reg = 0x00009888, .val = 0x1406000F },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x0008FF0F },
         { .reg = 0x00009888, .val = 0x0208700D },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5005 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x04011100 },
         { .reg = 0x00009888, .val = 0x06010021 },
         { .reg = 0x00009888, .val = 0x000142F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B2008 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x06020880 },
         { .reg = 0x00009888, .val = 0x08020021 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x0F060000 },
         { .reg = 0x00009888, .val = 0x130603C0 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x01080F00 },
         { .reg = 0x00009888, .val = 0x03081004 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A1004 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x09010880 },
         { .reg = 0x00009888, .val = 0x0B010021 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x0B020880 },
         { .reg = 0x00009888, .val = 0x0D020021 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004C3FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A00A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035005 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x48031060 },
         { .reg = 0x00009888, .val = 0x4A030083 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x500302E0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030040 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x46030480 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001C3FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A00A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00040802 },
         { .reg = 0x0000D964, .val = 0x00007EFF },
         { .reg = 0x0000D968, .val = 0x00021002 },
         { .reg = 0x0000D96C, .val = 0x0000BDFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext123__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext123__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext123__avg_gpu_core_frequency__max,acmgt1__ext123__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1383, 24, percentage_max_float,acmgt1__ext123__ps_output_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1384, 28, percentage_max_float,acmgt1__ext123__ps_output_available_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1385, 32, percentage_max_float,acmgt1__ext123__ps_output_available_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1386, 36, percentage_max_float,acmgt1__ext123__ps_output_available_cpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1387, 40, NULL,acmgt1__ext123__amfs_l3_access_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1388, 48, NULL,acmgt1__ext123__amfs_l3_access_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1389, 56, NULL,acmgt1__ext123__amfs_l3_atomic_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1390, 64, NULL,acmgt1__ext123__amfs_l3_atomic_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext124_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Ext124";
   query->symbol_name = "Ext124";
   query->guid = "bd7a8af3-2d23-4c95-9cb1-429840dfc38f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x1C073C00 },
         { .reg = 0x00009888, .val = 0x14090440 },
         { .reg = 0x00009888, .val = 0x16090013 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x180A001F },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x1D073C00 },
         { .reg = 0x00009888, .val = 0x15090440 },
         { .reg = 0x00009888, .val = 0x17090013 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x190A001F },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x10030031 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x000354E2 },
         { .reg = 0x00009888, .val = 0x06070000 },
         { .reg = 0x00009888, .val = 0x14070034 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x0008FC0C },
         { .reg = 0x00009888, .val = 0x020833F0 },
         { .reg = 0x00009888, .val = 0x02090010 },
         { .reg = 0x00009888, .val = 0x06090140 },
         { .reg = 0x00009888, .val = 0x0809034A },
         { .reg = 0x00009888, .val = 0x00092000 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x060A0027 },
         { .reg = 0x00009888, .val = 0x140A0D80 },
         { .reg = 0x00009888, .val = 0x000A56A4 },
         { .reg = 0x00009888, .val = 0x020A1950 },
         { .reg = 0x00009888, .val = 0x00015CE2 },
         { .reg = 0x00009888, .val = 0x000BA808 },
         { .reg = 0x00009888, .val = 0x020B22A0 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x0F030C40 },
         { .reg = 0x00009888, .val = 0x03030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x07070000 },
         { .reg = 0x00009888, .val = 0x13070D00 },
         { .reg = 0x00009888, .val = 0x05070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x03080030 },
         { .reg = 0x00009888, .val = 0x03090010 },
         { .reg = 0x00009888, .val = 0x0B090285 },
         { .reg = 0x00009888, .val = 0x0D09000D },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x070A09C0 },
         { .reg = 0x00009888, .val = 0x150A0036 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A0210 },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0020 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FCFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA0 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035550 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x42031800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x480305E9 },
         { .reg = 0x00009888, .val = 0x4A031E2F },
         { .reg = 0x00009888, .val = 0x4C030A22 },
         { .reg = 0x00009888, .val = 0x4E030251 },
         { .reg = 0x00009888, .val = 0x50030005 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030500 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46031929 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x2803F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x00000022 },
         { .reg = 0x0000D95C, .val = 0x0000FFEB },
         { .reg = 0x0000D960, .val = 0x00000302 },
         { .reg = 0x0000D964, .val = 0x0000FF9F },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FF5F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext124__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext124__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext124__avg_gpu_core_frequency__max,acmgt1__ext124__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1391, 24, percentage_max_float,acmgt1__ext124__vertex_fetch_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1392, 28, percentage_max_float,acmgt1__ext124__vertex_fetch_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1393, 32, percentage_max_float,acmgt1__ext124__vertex_fetch_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1394, 36, percentage_max_float,acmgt1__ext124__vertex_fetch_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1395, 40, NULL,acmgt1__ext124__clipper_input_vertex_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1396, 48, NULL,acmgt1__ext124__clipper_input_vertex_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1397, 56, NULL,acmgt1__ext124__streamout_output_vertex_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1398, 64, NULL,acmgt1__ext124__streamout_output_vertex_count_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1399, 72, percentage_max_float,acmgt1__ext124__vs_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1400, 76, percentage_max_float,acmgt1__ext124__vs_output_ready_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext125_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext125";
   query->symbol_name = "Ext125";
   query->guid = "2e16a8a7-613a-4df1-91bf-eec73d281822";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18091800 },
         { .reg = 0x00009888, .val = 0x16090340 },
         { .reg = 0x00009888, .val = 0x1C0903E0 },
         { .reg = 0x00009888, .val = 0x19091800 },
         { .reg = 0x00009888, .val = 0x17090340 },
         { .reg = 0x00009888, .val = 0x1D0903E0 },
         { .reg = 0x00009888, .val = 0x00034012 },
         { .reg = 0x00009888, .val = 0x0008030C },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009888, .val = 0x02094043 },
         { .reg = 0x00009888, .val = 0x04092400 },
         { .reg = 0x00009888, .val = 0x0A090025 },
         { .reg = 0x00009888, .val = 0x14090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0906 },
         { .reg = 0x00009888, .val = 0x020A9000 },
         { .reg = 0x00009888, .val = 0x00014012 },
         { .reg = 0x00009888, .val = 0x000B0208 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x03094043 },
         { .reg = 0x00009888, .val = 0x07090012 },
         { .reg = 0x00009888, .val = 0x09090940 },
         { .reg = 0x00009888, .val = 0x13090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0208 },
         { .reg = 0x00009888, .val = 0x030A2000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004C033 },
         { .reg = 0x00009888, .val = 0x00020A0A },
         { .reg = 0x00009888, .val = 0x0202A000 },
         { .reg = 0x00009888, .val = 0x00030505 },
         { .reg = 0x00009888, .val = 0x02035000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C031060 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x46032000 },
         { .reg = 0x00009888, .val = 0x28033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001C033 },
         { .reg = 0x00009888, .val = 0x00020505 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00040505 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00050505 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x00080A0A },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext125__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext125__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext125__avg_gpu_core_frequency__max,acmgt1__ext125__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1401, 24, percentage_max_float,acmgt1__ext125__clipper_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1402, 28, percentage_max_float,acmgt1__ext125__clipper_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1403, 32, percentage_max_float,acmgt1__ext125__clipper_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1404, 36, percentage_max_float,acmgt1__ext125__clipper_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1405, 40, NULL,acmgt1__ext125__clipper_primitive_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1406, 48, NULL,acmgt1__ext125__clipper_primitive_output_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext126_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Ext126";
   query->symbol_name = "Ext126";
   query->guid = "7cddf3f3-4ed8-484d-b8c7-82a4857ad030";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12057C00 },
         { .reg = 0x00009888, .val = 0x1A057C00 },
         { .reg = 0x00009888, .val = 0x1C050013 },
         { .reg = 0x00009888, .val = 0x14090000 },
         { .reg = 0x00009888, .val = 0x1C097FC0 },
         { .reg = 0x00009888, .val = 0x1E09000A },
         { .reg = 0x00009888, .val = 0x13057C00 },
         { .reg = 0x00009888, .val = 0x1B057C00 },
         { .reg = 0x00009888, .val = 0x1D050013 },
         { .reg = 0x00009888, .val = 0x15090000 },
         { .reg = 0x00009888, .val = 0x1D097FC0 },
         { .reg = 0x00009888, .val = 0x1F09000A },
         { .reg = 0x00009888, .val = 0x00035332 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x08050F31 },
         { .reg = 0x00009888, .val = 0x0E050080 },
         { .reg = 0x00009888, .val = 0x000620C0 },
         { .reg = 0x00009888, .val = 0x00085F0C },
         { .reg = 0x00009888, .val = 0x0208370F },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x04096805 },
         { .reg = 0x00009888, .val = 0x0E090940 },
         { .reg = 0x00009888, .val = 0x1009002A },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A5506 },
         { .reg = 0x00009888, .val = 0x020A95A5 },
         { .reg = 0x00009888, .val = 0x00015332 },
         { .reg = 0x00009888, .val = 0x000B0A08 },
         { .reg = 0x00009888, .val = 0x020B220A },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x03050001 },
         { .reg = 0x00009888, .val = 0x07050F31 },
         { .reg = 0x00009888, .val = 0x0F050002 },
         { .reg = 0x00009888, .val = 0x01061030 },
         { .reg = 0x00009888, .val = 0x01080500 },
         { .reg = 0x00009888, .val = 0x03080100 },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x05090005 },
         { .reg = 0x00009888, .val = 0x07090034 },
         { .reg = 0x00009888, .val = 0x0D090940 },
         { .reg = 0x00009888, .val = 0x0F09002A },
         { .reg = 0x00009888, .val = 0x13090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0508 },
         { .reg = 0x00009888, .val = 0x030A210A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFF3 },
         { .reg = 0x00009888, .val = 0x0002AA0A },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035505 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42031400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030008 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030683 },
         { .reg = 0x00009888, .val = 0x50031008 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030080 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x440300A5 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x46031508 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFF3 },
         { .reg = 0x00009888, .val = 0x00025505 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045505 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055505 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AA0A },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext126__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext126__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext126__avg_gpu_core_frequency__max,acmgt1__ext126__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1407, 24, NULL,acmgt1__ext126__clipper_transaction_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1408, 32, NULL,acmgt1__ext126__clipper_transaction_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1409, 40, NULL,acmgt1__ext126__stripsfan_object_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1410, 48, NULL,acmgt1__ext126__stripsfan_object_count_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1411, 56, NULL,acmgt1__ext126__stripsfan_objects_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1412, 64, NULL,acmgt1__ext126__stripsfan_objects_cull_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1413, 72, percentage_max_float,acmgt1__ext126__stripsfan_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1414, 76, percentage_max_float,acmgt1__ext126__stripsfan_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1415, 80, NULL,acmgt1__ext126__rasterizer_transaction_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1416, 88, NULL,acmgt1__ext126__rasterizer_transaction_output_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext127_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext127";
   query->symbol_name = "Ext127";
   query->guid = "cc78dbe3-bf19-4e4f-8957-c75488d8a47b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A057800 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x18090000 },
         { .reg = 0x00009888, .val = 0x160929C0 },
         { .reg = 0x00009888, .val = 0x1B057800 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x19090000 },
         { .reg = 0x00009888, .val = 0x170929C0 },
         { .reg = 0x00009888, .val = 0x00034F8C },
         { .reg = 0x00009888, .val = 0x00058000 },
         { .reg = 0x00009888, .val = 0x020530C8 },
         { .reg = 0x00009888, .val = 0x10050F00 },
         { .reg = 0x00009888, .val = 0x00068003 },
         { .reg = 0x00009888, .val = 0x0008C0F5 },
         { .reg = 0x00009888, .val = 0x020870FF },
         { .reg = 0x00009888, .val = 0x02090063 },
         { .reg = 0x00009888, .val = 0x08090180 },
         { .reg = 0x00009888, .val = 0x0A0902CC },
         { .reg = 0x00009888, .val = 0x10090480 },
         { .reg = 0x00009888, .val = 0x12090013 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A6A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F8C },
         { .reg = 0x00009888, .val = 0x000B80A0 },
         { .reg = 0x00009888, .val = 0x020B20AA },
         { .reg = 0x00009888, .val = 0x01058000 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x05050C32 },
         { .reg = 0x00009888, .val = 0x1105003C },
         { .reg = 0x00009888, .val = 0x0106400C },
         { .reg = 0x00009888, .val = 0x01080050 },
         { .reg = 0x00009888, .val = 0x03081000 },
         { .reg = 0x00009888, .val = 0x03090063 },
         { .reg = 0x00009888, .val = 0x0D090306 },
         { .reg = 0x00009888, .val = 0x0F09048B },
         { .reg = 0x00009888, .val = 0x11090013 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A8050 },
         { .reg = 0x00009888, .val = 0x030A10AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2A033000 },
         { .reg = 0x00009888, .val = 0x48030008 },
         { .reg = 0x00009888, .val = 0x4A030E00 },
         { .reg = 0x00009888, .val = 0x4C030AE5 },
         { .reg = 0x00009888, .val = 0x4E030057 },
         { .reg = 0x00009888, .val = 0x50031008 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030080 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031508 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46032005 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000282 },
         { .reg = 0x0000D95C, .val = 0x0000FFAF },
         { .reg = 0x0000D960, .val = 0x00000C02 },
         { .reg = 0x0000D964, .val = 0x0000FE7F },
         { .reg = 0x0000D968, .val = 0x00001402 },
         { .reg = 0x0000D96C, .val = 0x0000FD7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext127__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext127__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext127__avg_gpu_core_frequency__max,acmgt1__ext127__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1417, 24, percentage_max_float,acmgt1__ext127__rasterizer_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1418, 28, percentage_max_float,acmgt1__ext127__rasterizer_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1419, 32, percentage_max_float,acmgt1__ext127__rasterizer_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1420, 36, percentage_max_float,acmgt1__ext127__rasterizer_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1421, 40, NULL,acmgt1__ext127__clipper_primitive_far_near_clip_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1422, 48, NULL,acmgt1__ext127__clipper_primitive_far_near_clip_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1423, 56, NULL,acmgt1__ext127__clipper_primitive_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1424, 64, NULL,acmgt1__ext127__clipper_primitive_cull_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext128_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext128";
   query->symbol_name = "Ext128";
   query->guid = "9722a829-b7e5-4716-b62e-ff6cb930232b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x180703C0 },
         { .reg = 0x00009888, .val = 0x1A070180 },
         { .reg = 0x00009888, .val = 0x18080F00 },
         { .reg = 0x00009888, .val = 0x1A080180 },
         { .reg = 0x00009888, .val = 0x04072100 },
         { .reg = 0x00009888, .val = 0x08070840 },
         { .reg = 0x00009888, .val = 0x0A070020 },
         { .reg = 0x00009888, .val = 0x0E0704D4 },
         { .reg = 0x00009888, .val = 0x10070012 },
         { .reg = 0x00009888, .val = 0x14070597 },
         { .reg = 0x00009888, .val = 0x16070015 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0608C310 },
         { .reg = 0x00009888, .val = 0x0A0808E4 },
         { .reg = 0x00009888, .val = 0x0C080022 },
         { .reg = 0x00009888, .val = 0x100809A7 },
         { .reg = 0x00009888, .val = 0x12080025 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0009E38C },
         { .reg = 0x00009888, .val = 0x000A95A5 },
         { .reg = 0x00009888, .val = 0x020AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030C00 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030003 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext128__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext128__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext128__avg_gpu_core_frequency__max,acmgt1__ext128__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1425, 24, NULL,acmgt1__ext128__urb_read_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1426, 32, NULL,acmgt1__ext128__urb_write_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1427, 40, NULL,acmgt1__ext128__urb_cross_slice_read_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext129_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext129";
   query->symbol_name = "Ext129";
   query->guid = "4d7bb9a8-4b02-435a-b2be-16a2314c421d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x190703C0 },
         { .reg = 0x00009888, .val = 0x1B070180 },
         { .reg = 0x00009888, .val = 0x19080F00 },
         { .reg = 0x00009888, .val = 0x1B080180 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x05072100 },
         { .reg = 0x00009888, .val = 0x09070840 },
         { .reg = 0x00009888, .val = 0x0B070020 },
         { .reg = 0x00009888, .val = 0x0F0704D4 },
         { .reg = 0x00009888, .val = 0x11070012 },
         { .reg = 0x00009888, .val = 0x15070597 },
         { .reg = 0x00009888, .val = 0x17070015 },
         { .reg = 0x00009888, .val = 0x01070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x05080000 },
         { .reg = 0x00009888, .val = 0x0708C310 },
         { .reg = 0x00009888, .val = 0x0B0808E4 },
         { .reg = 0x00009888, .val = 0x0D080022 },
         { .reg = 0x00009888, .val = 0x110809A7 },
         { .reg = 0x00009888, .val = 0x13080025 },
         { .reg = 0x00009888, .val = 0x09080000 },
         { .reg = 0x00009888, .val = 0x01080000 },
         { .reg = 0x00009888, .val = 0x03080000 },
         { .reg = 0x00009888, .val = 0x0109E38C },
         { .reg = 0x00009888, .val = 0x010A95A5 },
         { .reg = 0x00009888, .val = 0x030AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030C00 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030003 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext129__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext129__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext129__avg_gpu_core_frequency__max,acmgt1__ext129__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1428, 24, NULL,acmgt1__ext129__urb_read_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1429, 32, NULL,acmgt1__ext129__urb_write_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1430, 40, NULL,acmgt1__ext129__urb_cross_slice_read_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext130_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext130";
   query->symbol_name = "Ext130";
   query->guid = "307951f8-0159-4d0c-bc8f-04fee7247e0a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x100B5500 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x060B0150 },
         { .reg = 0x00009888, .val = 0x120B0493 },
         { .reg = 0x00009888, .val = 0x140B0411 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F801 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext130__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext130__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext130__avg_gpu_core_frequency__max,acmgt1__ext130__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1431, 24, NULL,acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1432, 32, NULL,acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext131_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext131";
   query->symbol_name = "Ext131";
   query->guid = "aa04f1fa-826e-4b25-a7a6-4fbb4a7d0dd2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x100C5500 },
         { .reg = 0x00009888, .val = 0x00070002 },
         { .reg = 0x00009888, .val = 0x0207AA80 },
         { .reg = 0x00009888, .val = 0x0009F801 },
         { .reg = 0x00009888, .val = 0x000A0002 },
         { .reg = 0x00009888, .val = 0x020AAA80 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x060C0150 },
         { .reg = 0x00009888, .val = 0x120C0493 },
         { .reg = 0x00009888, .val = 0x140C0411 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F801 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext131__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext131__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext131__avg_gpu_core_frequency__max,acmgt1__ext131__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1433, 24, NULL,acmgt1__ext131__early_depth_stencil_test_fail_np_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1434, 32, NULL,acmgt1__ext131__early_depth_stencil_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext132_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext132";
   query->symbol_name = "Ext132";
   query->guid = "9121bb2c-a28d-4796-a60b-52905e317576";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x110B5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01080003 },
         { .reg = 0x00009888, .val = 0x0308FFC0 },
         { .reg = 0x00009888, .val = 0x010A0001 },
         { .reg = 0x00009888, .val = 0x030A5540 },
         { .reg = 0x00009888, .val = 0x0101F801 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x070B0150 },
         { .reg = 0x00009888, .val = 0x130B0493 },
         { .reg = 0x00009888, .val = 0x150B0411 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F801 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext132__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext132__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext132__avg_gpu_core_frequency__max,acmgt1__ext132__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1435, 24, NULL,acmgt1__ext132__early_depth_stencil_test_fail_np_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1436, 32, NULL,acmgt1__ext132__early_depth_stencil_test_fail_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext133_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext133";
   query->symbol_name = "Ext133";
   query->guid = "14a8d00b-a361-4bc5-94fe-4664b837cc56";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x110C5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0307AA80 },
         { .reg = 0x00009888, .val = 0x0109F801 },
         { .reg = 0x00009888, .val = 0x010A0002 },
         { .reg = 0x00009888, .val = 0x030AAA80 },
         { .reg = 0x00009888, .val = 0x0102F801 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x070C0150 },
         { .reg = 0x00009888, .val = 0x130C0493 },
         { .reg = 0x00009888, .val = 0x150C0411 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F801 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext133__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext133__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext133__avg_gpu_core_frequency__max,acmgt1__ext133__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1437, 24, NULL,acmgt1__ext133__early_depth_stencil_test_fail_np_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1438, 32, NULL,acmgt1__ext133__early_depth_stencil_test_fail_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext134_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext134";
   query->symbol_name = "Ext134";
   query->guid = "74fda750-6436-4a97-897b-8eff0a63de70";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203008F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030100 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030008 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext134__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext134__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext134__avg_gpu_core_frequency__max,acmgt1__ext134__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1439, 24, NULL,acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext135_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext135";
   query->symbol_name = "Ext135";
   query->guid = "1712c473-6635-49af-a6da-43c724c96dcd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x520300BF },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030160 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x4603000B },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext135__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext135__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext135__avg_gpu_core_frequency__max,acmgt1__ext135__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1440, 24, NULL,acmgt1__ext135__hiz_depth_test_ambig_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext136_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext136";
   query->symbol_name = "Ext136";
   query->guid = "5c1a57d6-2dff-48ca-98bf-02c71a22057a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203006F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440300C0 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030006 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext136__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext136__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext136__avg_gpu_core_frequency__max,acmgt1__ext136__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1441, 24, NULL,acmgt1__ext136__hiz_depth_test_ambig_np_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext137_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext137";
   query->symbol_name = "Ext137";
   query->guid = "6ede1a62-069a-4b3d-8b17-000005541bfd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203009F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030120 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030009 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext137__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext137__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext137__avg_gpu_core_frequency__max,acmgt1__ext137__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1442, 24, NULL,acmgt1__ext137__hiz_depth_test_ambig_np_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext138_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext138";
   query->symbol_name = "Ext138";
   query->guid = "4a31afda-7a08-4d3d-91fd-138bae3eb836";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203008F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030100 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030008 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext138__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext138__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext138__avg_gpu_core_frequency__max,acmgt1__ext138__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1443, 24, NULL,acmgt1__ext138__hiz_depth_test_ambig_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext139_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext139";
   query->symbol_name = "Ext139";
   query->guid = "c800871b-2505-40f3-99e2-6c0ccb9102f2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x520300BF },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030160 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x4603000B },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext139__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext139__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext139__avg_gpu_core_frequency__max,acmgt1__ext139__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1444, 24, NULL,acmgt1__ext139__hiz_depth_test_ambig_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext140_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext140";
   query->symbol_name = "Ext140";
   query->guid = "067cbc21-6b6c-48c6-b47c-922a27b60b30";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203006F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440300C0 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030006 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext140__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext140__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext140__avg_gpu_core_frequency__max,acmgt1__ext140__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1445, 24, NULL,acmgt1__ext140__hiz_depth_test_ambig_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext141_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext141";
   query->symbol_name = "Ext141";
   query->guid = "e8ee8621-7110-4d70-9651-846fd4fa3c3c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203009F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030120 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030009 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext141__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext141__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext141__avg_gpu_core_frequency__max,acmgt1__ext141__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1446, 24, NULL,acmgt1__ext141__hiz_depth_test_ambig_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext142_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext142";
   query->symbol_name = "Ext142";
   query->guid = "87a9d5f2-2029-48b9-bbd3-78867e022166";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203008F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030100 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030008 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext142__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext142__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext142__avg_gpu_core_frequency__max,acmgt1__ext142__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1447, 24, NULL,acmgt1__ext142__hiz_depth_test_fail_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext143_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext143";
   query->symbol_name = "Ext143";
   query->guid = "bffa2382-3aff-471a-92af-5dd571c7868f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x520300BF },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030160 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x4603000B },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext143__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext143__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext143__avg_gpu_core_frequency__max,acmgt1__ext143__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1448, 24, NULL,acmgt1__ext143__hiz_depth_test_fail_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext144_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext144";
   query->symbol_name = "Ext144";
   query->guid = "951f3ee4-6a3c-470c-b403-c01ee6a7e97d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203006F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440300C0 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030006 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext144__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext144__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext144__avg_gpu_core_frequency__max,acmgt1__ext144__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1449, 24, NULL,acmgt1__ext144__hiz_depth_test_fail_np_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext145_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext145";
   query->symbol_name = "Ext145";
   query->guid = "4d34c592-973b-4e75-a451-cf4ad90f79e1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203009F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030120 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030009 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext145__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext145__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext145__avg_gpu_core_frequency__max,acmgt1__ext145__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1450, 24, NULL,acmgt1__ext145__hiz_depth_test_fail_np_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext146_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext146";
   query->symbol_name = "Ext146";
   query->guid = "4a881a06-44b8-4199-a609-e0e4e22631c4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203008F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030100 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030008 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext146__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext146__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext146__avg_gpu_core_frequency__max,acmgt1__ext146__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1451, 24, NULL,acmgt1__ext146__hiz_depth_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext147_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext147";
   query->symbol_name = "Ext147";
   query->guid = "20b339b5-abb6-48fc-8a09-bb4cafacbb72";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x520300BF },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030160 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x4603000B },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext147__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext147__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext147__avg_gpu_core_frequency__max,acmgt1__ext147__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1452, 24, NULL,acmgt1__ext147__hiz_depth_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext148_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext148";
   query->symbol_name = "Ext148";
   query->guid = "8b62b22b-a467-4638-a113-81a5c59d64e8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203006F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440300C0 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030006 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext148__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext148__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext148__avg_gpu_core_frequency__max,acmgt1__ext148__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1453, 24, NULL,acmgt1__ext148__hiz_depth_test_fail_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext149_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext149";
   query->symbol_name = "Ext149";
   query->guid = "a563237d-76f3-45bc-82d7-c4a441c9230c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203009F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030120 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030009 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext149__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext149__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext149__avg_gpu_core_frequency__max,acmgt1__ext149__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1454, 24, NULL,acmgt1__ext149__hiz_depth_test_fail_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext150_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext150";
   query->symbol_name = "Ext150";
   query->guid = "dee6b408-d907-4eae-a961-7262816be56c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203008F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030100 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030008 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B6000 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B0008 },
         { .reg = 0x00009888, .val = 0x120B0009 },
         { .reg = 0x00009888, .val = 0x140B000A },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext150__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext150__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext150__avg_gpu_core_frequency__max,acmgt1__ext150__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1455, 24, NULL,acmgt1__ext150__hiz_depth_test_pass_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext151_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext151";
   query->symbol_name = "Ext151";
   query->guid = "c2bf9d7d-0998-483b-bede-7ced3f8cf423";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x520300BF },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030160 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x4603000B },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C6000 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C0008 },
         { .reg = 0x00009888, .val = 0x120C0009 },
         { .reg = 0x00009888, .val = 0x140C000A },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext151__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext151__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext151__avg_gpu_core_frequency__max,acmgt1__ext151__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1456, 24, NULL,acmgt1__ext151__hiz_depth_test_pass_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext152_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext152";
   query->symbol_name = "Ext152";
   query->guid = "06c6ecdb-9b66-400b-83ca-484309fba532";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203006F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440300C0 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030006 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B6000 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B0008 },
         { .reg = 0x00009888, .val = 0x130B0009 },
         { .reg = 0x00009888, .val = 0x150B000A },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext152__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext152__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext152__avg_gpu_core_frequency__max,acmgt1__ext152__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1457, 24, NULL,acmgt1__ext152__hiz_depth_test_pass_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext153_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext153";
   query->symbol_name = "Ext153";
   query->guid = "af12ca37-4f11-4c7a-b6b3-695210972c92";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203009F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030120 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030009 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C6000 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C0008 },
         { .reg = 0x00009888, .val = 0x130C0009 },
         { .reg = 0x00009888, .val = 0x150C000A },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext153__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext153__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext153__avg_gpu_core_frequency__max,acmgt1__ext153__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1458, 24, NULL,acmgt1__ext153__hiz_depth_test_pass_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext154_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext154";
   query->symbol_name = "Ext154";
   query->guid = "f72930f8-79c3-49f3-9fa3-07a05070d1fd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B2C00 },
         { .reg = 0x00009888, .val = 0x0C0B6580 },
         { .reg = 0x00009888, .val = 0x100B6740 },
         { .reg = 0x00009888, .val = 0x160C2C00 },
         { .reg = 0x00009888, .val = 0x0C0C6016 },
         { .reg = 0x00009888, .val = 0x100C601D },
         { .reg = 0x00009888, .val = 0x170B2C00 },
         { .reg = 0x00009888, .val = 0x0D0B6000 },
         { .reg = 0x00009888, .val = 0x110B6000 },
         { .reg = 0x00009888, .val = 0x170C2C00 },
         { .reg = 0x00009888, .val = 0x0D0C6000 },
         { .reg = 0x00009888, .val = 0x110C6000 },
         { .reg = 0x00009888, .val = 0x00033330 },
         { .reg = 0x00009888, .val = 0x00072000 },
         { .reg = 0x00009888, .val = 0x02072020 },
         { .reg = 0x00009888, .val = 0x0008CF00 },
         { .reg = 0x00009888, .val = 0x0208CFCF },
         { .reg = 0x00009888, .val = 0x00094440 },
         { .reg = 0x00009888, .val = 0x000A6500 },
         { .reg = 0x00009888, .val = 0x020A6565 },
         { .reg = 0x00009888, .val = 0x0001BBB0 },
         { .reg = 0x00009888, .val = 0x040B0404 },
         { .reg = 0x00009888, .val = 0x140B0080 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0A00 },
         { .reg = 0x00009888, .val = 0x020B0A0A },
         { .reg = 0x00009888, .val = 0x00024440 },
         { .reg = 0x00009888, .val = 0x040C0404 },
         { .reg = 0x00009888, .val = 0x140C0002 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x01070200 },
         { .reg = 0x00009888, .val = 0x03070202 },
         { .reg = 0x00009888, .val = 0x01080C00 },
         { .reg = 0x00009888, .val = 0x03080C0C },
         { .reg = 0x00009888, .val = 0x01091110 },
         { .reg = 0x00009888, .val = 0x010A0600 },
         { .reg = 0x00009888, .val = 0x030A0606 },
         { .reg = 0x00009888, .val = 0x01012220 },
         { .reg = 0x00009888, .val = 0x050B0404 },
         { .reg = 0x00009888, .val = 0x0B0B0580 },
         { .reg = 0x00009888, .val = 0x0F0B0740 },
         { .reg = 0x00009888, .val = 0x130B0080 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01021110 },
         { .reg = 0x00009888, .val = 0x050C0404 },
         { .reg = 0x00009888, .val = 0x0B0C0016 },
         { .reg = 0x00009888, .val = 0x0F0C001D },
         { .reg = 0x00009888, .val = 0x130C0002 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFF0 },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035500 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030600 },
         { .reg = 0x00009888, .val = 0x4E030E83 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x44030008 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030103 },
         { .reg = 0x00009888, .val = 0x24033000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext154__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext154__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext154__avg_gpu_core_frequency__max,acmgt1__ext154__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1459, 24, percentage_max_float,acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1460, 28, percentage_max_float,acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1461, 32, percentage_max_float,acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1462, 36, percentage_max_float,acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1463, 40, percentage_max_float,acmgt1__ext154__iz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1464, 44, percentage_max_float,acmgt1__ext154__iz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1465, 48, percentage_max_float,acmgt1__ext154__iz_subspan_latency_fifofull_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1466, 52, percentage_max_float,acmgt1__ext154__iz_subspan_latency_fifofull_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1467, 56, percentage_max_float,acmgt1__ext154__iz_output_ready_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1468, 60, percentage_max_float,acmgt1__ext154__iz_output_ready_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1469, 64, percentage_max_float,acmgt1__ext154__iz_output_ready_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1470, 68, percentage_max_float,acmgt1__ext154__iz_output_ready_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext155_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext155";
   query->symbol_name = "Ext155";
   query->guid = "ac5346ae-2be4-47d1-8300-6e25c445297d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x16040400 },
         { .reg = 0x00009888, .val = 0x1E040200 },
         { .reg = 0x00009888, .val = 0x26040200 },
         { .reg = 0x00009888, .val = 0x2E040200 },
         { .reg = 0x00009888, .val = 0x3A040010 },
         { .reg = 0x00009888, .val = 0x020401C0 },
         { .reg = 0x00009888, .val = 0x0404008E },
         { .reg = 0x00009888, .val = 0x06040000 },
         { .reg = 0x00009888, .val = 0x08040081 },
         { .reg = 0x00009888, .val = 0x0A040248 },
         { .reg = 0x00009888, .val = 0x0C04040A },
         { .reg = 0x00009888, .val = 0x0E040491 },
         { .reg = 0x00009888, .val = 0x10040658 },
         { .reg = 0x00009888, .val = 0x1204081A },
         { .reg = 0x00009888, .val = 0x140408A1 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext155__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext155__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext155__avg_gpu_core_frequency__max,acmgt1__ext155__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 1471, 24, percentage_max_float,acmgt1__ext155__command_parser_compute_engine_busy_ccs0__read);

      intel_perf_query_add_counter_float(query, 1472, 28, percentage_max_float,acmgt1__ext155__command_parser_compute_engine_busy_ccs1__read);

      intel_perf_query_add_counter_float(query, 1473, 32, percentage_max_float,acmgt1__ext155__command_parser_compute_engine_busy_ccs2__read);

      intel_perf_query_add_counter_float(query, 1474, 36, percentage_max_float,acmgt1__ext155__command_parser_compute_engine_busy_ccs3__read);

      intel_perf_query_add_counter_float(query, 1475, 40, percentage_max_float,acmgt1__ext155__command_parser_render_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext156_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext156";
   query->symbol_name = "Ext156";
   query->guid = "f8f7091d-7f71-42cf-84de-8ad23fe45432";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1E04001F },
         { .reg = 0x00009888, .val = 0x2604001F },
         { .reg = 0x00009888, .val = 0x2E04001F },
         { .reg = 0x00009888, .val = 0x360403E0 },
         { .reg = 0x00009888, .val = 0x4204001F },
         { .reg = 0x00009888, .val = 0x02046DBB },
         { .reg = 0x00009888, .val = 0x0404022D },
         { .reg = 0x00009888, .val = 0x06048C00 },
         { .reg = 0x00009888, .val = 0x08040022 },
         { .reg = 0x00009888, .val = 0x10040900 },
         { .reg = 0x00009888, .val = 0x12040420 },
         { .reg = 0x00009888, .val = 0x14040018 },
         { .reg = 0x00009888, .val = 0x16040008 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x00030005 },
         { .reg = 0x00009888, .val = 0x02035550 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext156__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext156__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext156__avg_gpu_core_frequency__max,acmgt1__ext156__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1476, 24, NULL,acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs0__read);

      intel_perf_query_add_counter_uint64(query, 1477, 32, NULL,acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs1__read);

      intel_perf_query_add_counter_uint64(query, 1478, 40, NULL,acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs2__read);

      intel_perf_query_add_counter_uint64(query, 1479, 48, NULL,acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs3__read);

      intel_perf_query_add_counter_uint64(query, 1480, 56, NULL,acmgt1__ext156__command_parser_render_engine_dispatch_kernel_count__read);

      intel_perf_query_add_counter_uint64(query, 1481, 64, NULL,acmgt1__ext156__command_parser_render_engine_draw_count__read);

      intel_perf_query_add_counter_uint64(query, 1482, 72, NULL,acmgt1__ext156__command_parser_flush_count__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext157_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext157";
   query->symbol_name = "Ext157";
   query->guid = "ac6eecdc-0074-4a94-9269-48b5e3833439";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x440A0010 },
         { .reg = 0x00009888, .val = 0x18134000 },
         { .reg = 0x00009888, .val = 0x060A001E },
         { .reg = 0x00009888, .val = 0x0E0A0400 },
         { .reg = 0x00009888, .val = 0x100A0491 },
         { .reg = 0x00009888, .val = 0x040A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x00100A80 },
         { .reg = 0x00009888, .val = 0x02100054 },
         { .reg = 0x00009888, .val = 0x02120054 },
         { .reg = 0x00009888, .val = 0x00130600 },
         { .reg = 0x00009888, .val = 0x0C130400 },
         { .reg = 0x00009888, .val = 0x0E130491 },
         { .reg = 0x00009888, .val = 0x02130000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x440A0010 },
         { .reg = 0x00009888, .val = 0x18134000 },
         { .reg = 0x00009888, .val = 0x060A001E },
         { .reg = 0x00009888, .val = 0x120A0450 },
         { .reg = 0x00009888, .val = 0x140A0012 },
         { .reg = 0x00009888, .val = 0x040A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x0010A000 },
         { .reg = 0x00009888, .val = 0x02101502 },
         { .reg = 0x00009888, .val = 0x02121500 },
         { .reg = 0x00009888, .val = 0x00130600 },
         { .reg = 0x00009888, .val = 0x10130450 },
         { .reg = 0x00009888, .val = 0x12130012 },
         { .reg = 0x00009888, .val = 0x02130000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x18010010 },
         { .reg = 0x00009888, .val = 0x02010002 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x08010081 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x0003FFEA },
         { .reg = 0x00009888, .val = 0x02033FFF },
         { .reg = 0x00009888, .val = 0x00095540 },
         { .reg = 0x00009888, .val = 0x02091555 },
         { .reg = 0x00009888, .val = 0x0005A540 },
         { .reg = 0x00009888, .val = 0x02052A56 },
         { .reg = 0x00009888, .val = 0x000AAA80 },
         { .reg = 0x00009888, .val = 0x020A2AAA },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A033000 },
         { .reg = 0x00009888, .val = 0x48030864 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603014A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext157__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext157__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext157__avg_gpu_core_frequency__max,acmgt1__ext157__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 1483, 24, percentage_max_float,acmgt1__ext157__command_parser_copy_engine_busy__read);

      intel_perf_query_add_counter_float(query, 1484, 28, percentage_max_float,acmgt1__ext157__command_parser_video_engine_busy_vdbox0__read);

      intel_perf_query_add_counter_float(query, 1485, 32, percentage_max_float,acmgt1__ext157__command_parser_video_engine_busy_vdbox1__read);

      intel_perf_query_add_counter_float(query, 1486, 36, percentage_max_float,acmgt1__ext157__command_parser_video_enhancement_engine_busy_vebox0__read);

      intel_perf_query_add_counter_float(query, 1487, 40, percentage_max_float,acmgt1__ext157__command_parser_video_enhancement_engine_busy_vebox1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext158_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext158";
   query->symbol_name = "Ext158";
   query->guid = "4c27f089-06ab-4c33-b084-fc7cc9cc78ea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x168503E0 },
         { .reg = 0x00009888, .val = 0x16A503E0 },
         { .reg = 0x00009888, .val = 0x16C503E0 },
         { .reg = 0x00009888, .val = 0x16E503E0 },
         { .reg = 0x00009888, .val = 0x178503E0 },
         { .reg = 0x00009888, .val = 0x17A503E0 },
         { .reg = 0x00009888, .val = 0x17C503E0 },
         { .reg = 0x00009888, .val = 0x17E503E0 },
         { .reg = 0x00009888, .val = 0x02850004 },
         { .reg = 0x00009888, .val = 0x128501C6 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0286A000 },
         { .reg = 0x00009888, .val = 0x02A50004 },
         { .reg = 0x00009888, .val = 0x10A501C6 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A60A00 },
         { .reg = 0x00009888, .val = 0x02C50004 },
         { .reg = 0x00009888, .val = 0x0EC501C6 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600A0 },
         { .reg = 0x00009888, .val = 0x02E50004 },
         { .reg = 0x00009888, .val = 0x0CE501C6 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6000A },
         { .reg = 0x00009888, .val = 0x03850004 },
         { .reg = 0x00009888, .val = 0x0B8501C6 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186A000 },
         { .reg = 0x00009888, .val = 0x03A50004 },
         { .reg = 0x00009888, .val = 0x09A501C6 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A60A00 },
         { .reg = 0x00009888, .val = 0x03C50004 },
         { .reg = 0x00009888, .val = 0x07C501C6 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C600A0 },
         { .reg = 0x00009888, .val = 0x03E50004 },
         { .reg = 0x00009888, .val = 0x05E51C60 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6000A },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803000A },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030221 },
         { .reg = 0x00009888, .val = 0x50030EE2 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030077 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46032940 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext158__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext158__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext158__avg_gpu_core_frequency__max,acmgt1__ext158__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1488, 24, NULL,acmgt1__ext158__rt_input_message_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1489, 32, NULL,acmgt1__ext158__rt_input_message_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1490, 40, NULL,acmgt1__ext158__rt_input_message_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1491, 48, NULL,acmgt1__ext158__rt_input_message_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1492, 56, NULL,acmgt1__ext158__rt_input_message_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1493, 64, NULL,acmgt1__ext158__rt_input_message_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1494, 72, NULL,acmgt1__ext158__rt_input_message_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1495, 80, NULL,acmgt1__ext158__rt_input_message_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1496, 88, NULL,acmgt1__ext158__rt_traversal_input_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1497, 96, NULL,acmgt1__ext158__rt_traversal_input_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1498, 104, NULL,acmgt1__ext158__rt_traversal_input_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1499, 112, NULL,acmgt1__ext158__rt_traversal_input_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1500, 120, NULL,acmgt1__ext158__rt_traversal_input_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1501, 128, NULL,acmgt1__ext158__rt_traversal_input_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1502, 136, NULL,acmgt1__ext158__rt_traversal_input_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1503, 144, NULL,acmgt1__ext158__rt_traversal_input_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext159_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext159";
   query->symbol_name = "Ext159";
   query->guid = "1918a5b9-f991-4451-afff-565a739dbfb9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D77E },
         { .reg = 0x00009888, .val = 0x06850F7F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D77 },
         { .reg = 0x00009888, .val = 0x0AA50F7F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D77 },
         { .reg = 0x00009888, .val = 0x0EC50F7F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D77 },
         { .reg = 0x00009888, .val = 0x12E50F7F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext159__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext159__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext159__avg_gpu_core_frequency__max,acmgt1__ext159__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1504, 24, NULL,acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1505, 32, NULL,acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1506, 40, NULL,acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1507, 48, NULL,acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext160_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext160";
   query->symbol_name = "Ext160";
   query->guid = "6cf8ce0d-617c-4ed8-962c-6b750c0cf012";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D77E },
         { .reg = 0x00009888, .val = 0x07850F7F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D77 },
         { .reg = 0x00009888, .val = 0x0BA50F7F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D77 },
         { .reg = 0x00009888, .val = 0x0FC50F7F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D77 },
         { .reg = 0x00009888, .val = 0x13E50F7F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext160__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext160__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext160__avg_gpu_core_frequency__max,acmgt1__ext160__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1508, 24, NULL,acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1509, 32, NULL,acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1510, 40, NULL,acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1511, 48, NULL,acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext161_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext161";
   query->symbol_name = "Ext161";
   query->guid = "453d205a-8bd1-4ebe-b617-1168cbfda3ca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485DB7E },
         { .reg = 0x00009888, .val = 0x06850FBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50DB7 },
         { .reg = 0x00009888, .val = 0x0AA50FBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50DB7 },
         { .reg = 0x00009888, .val = 0x0EC50FBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50DB7 },
         { .reg = 0x00009888, .val = 0x12E50FBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext161__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext161__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext161__avg_gpu_core_frequency__max,acmgt1__ext161__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1512, 24, NULL,acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1513, 32, NULL,acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1514, 40, NULL,acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1515, 48, NULL,acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext162_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext162";
   query->symbol_name = "Ext162";
   query->guid = "9d94eefc-0c25-4725-a6af-3eb468cae42d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585DB7E },
         { .reg = 0x00009888, .val = 0x07850FBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50DB7 },
         { .reg = 0x00009888, .val = 0x0BA50FBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50DB7 },
         { .reg = 0x00009888, .val = 0x0FC50FBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50DB7 },
         { .reg = 0x00009888, .val = 0x13E50FBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext162__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext162__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext162__avg_gpu_core_frequency__max,acmgt1__ext162__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1516, 24, NULL,acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1517, 32, NULL,acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1518, 40, NULL,acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1519, 48, NULL,acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext163_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext163";
   query->symbol_name = "Ext163";
   query->guid = "fbba6a19-98df-4a94-9a42-2660674d8e25";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D37E },
         { .reg = 0x00009888, .val = 0x06850F3F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D37 },
         { .reg = 0x00009888, .val = 0x0AA50F3F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D37 },
         { .reg = 0x00009888, .val = 0x0EC50F3F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D37 },
         { .reg = 0x00009888, .val = 0x12E50F3F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext163__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext163__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext163__avg_gpu_core_frequency__max,acmgt1__ext163__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1520, 24, NULL,acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1521, 32, NULL,acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1522, 40, NULL,acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1523, 48, NULL,acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext164_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext164";
   query->symbol_name = "Ext164";
   query->guid = "ec971ed3-3fb2-4d4c-bf27-08eeb418dc68";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D37E },
         { .reg = 0x00009888, .val = 0x07850F3F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D37 },
         { .reg = 0x00009888, .val = 0x0BA50F3F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D37 },
         { .reg = 0x00009888, .val = 0x0FC50F3F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D37 },
         { .reg = 0x00009888, .val = 0x13E50F3F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext164__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext164__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext164__avg_gpu_core_frequency__max,acmgt1__ext164__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1524, 24, NULL,acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1525, 32, NULL,acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1526, 40, NULL,acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1527, 48, NULL,acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext165_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext165";
   query->symbol_name = "Ext165";
   query->guid = "a1d6b535-1d00-4951-bdcc-8586b9ba7c0a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CF7E },
         { .reg = 0x00009888, .val = 0x06850EFF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CF7 },
         { .reg = 0x00009888, .val = 0x0AA50EFF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CF7 },
         { .reg = 0x00009888, .val = 0x0EC50EFF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CF7 },
         { .reg = 0x00009888, .val = 0x12E50EFF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext165__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext165__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext165__avg_gpu_core_frequency__max,acmgt1__ext165__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1528, 24, NULL,acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1529, 32, NULL,acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1530, 40, NULL,acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1531, 48, NULL,acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext166_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext166";
   query->symbol_name = "Ext166";
   query->guid = "5f78bfe9-b17b-4df2-b1de-54e7c84d93ab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CF7E },
         { .reg = 0x00009888, .val = 0x07850EFF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CF7 },
         { .reg = 0x00009888, .val = 0x0BA50EFF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CF7 },
         { .reg = 0x00009888, .val = 0x0FC50EFF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CF7 },
         { .reg = 0x00009888, .val = 0x13E50EFF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext166__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext166__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext166__avg_gpu_core_frequency__max,acmgt1__ext166__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1532, 24, NULL,acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1533, 32, NULL,acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1534, 40, NULL,acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1535, 48, NULL,acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext167_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext167";
   query->symbol_name = "Ext167";
   query->guid = "c76128ab-fe65-4ccc-94ea-f351ccbd5f16";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CB7E },
         { .reg = 0x00009888, .val = 0x06850EBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CB7 },
         { .reg = 0x00009888, .val = 0x0AA50EBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CB7 },
         { .reg = 0x00009888, .val = 0x0EC50EBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CB7 },
         { .reg = 0x00009888, .val = 0x12E50EBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext167__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext167__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext167__avg_gpu_core_frequency__max,acmgt1__ext167__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1536, 24, NULL,acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1537, 32, NULL,acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1538, 40, NULL,acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1539, 48, NULL,acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext168_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext168";
   query->symbol_name = "Ext168";
   query->guid = "fac0445a-ae46-412e-bf26-0b4dddd64485";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CB7E },
         { .reg = 0x00009888, .val = 0x07850EBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CB7 },
         { .reg = 0x00009888, .val = 0x0BA50EBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CB7 },
         { .reg = 0x00009888, .val = 0x0FC50EBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CB7 },
         { .reg = 0x00009888, .val = 0x13E50EBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext168__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext168__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext168__avg_gpu_core_frequency__max,acmgt1__ext168__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1540, 24, NULL,acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1541, 32, NULL,acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1542, 40, NULL,acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1543, 48, NULL,acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext169_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext169";
   query->symbol_name = "Ext169";
   query->guid = "386322a7-4cf5-4bf9-bbd9-35a6477a4479";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8545E0 },
         { .reg = 0x00009888, .val = 0x1EA545E0 },
         { .reg = 0x00009888, .val = 0x1EC545E0 },
         { .reg = 0x00009888, .val = 0x1EE545E0 },
         { .reg = 0x00009888, .val = 0x0485C70E },
         { .reg = 0x00009888, .val = 0x06850E78 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50C70 },
         { .reg = 0x00009888, .val = 0x0AA50E78 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50C70 },
         { .reg = 0x00009888, .val = 0x0EC50E78 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50C70 },
         { .reg = 0x00009888, .val = 0x12E50E78 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext169__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext169__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext169__avg_gpu_core_frequency__max,acmgt1__ext169__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1544, 24, NULL,acmgt1__ext169__rt_traversal_output_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1545, 32, NULL,acmgt1__ext169__rt_traversal_output_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1546, 40, NULL,acmgt1__ext169__rt_traversal_output_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1547, 48, NULL,acmgt1__ext169__rt_traversal_output_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext170_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext170";
   query->symbol_name = "Ext170";
   query->guid = "b175ecb9-b8cd-4f9c-97d4-73bf5cf12fa7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8545E0 },
         { .reg = 0x00009888, .val = 0x1FA545E0 },
         { .reg = 0x00009888, .val = 0x1FC545E0 },
         { .reg = 0x00009888, .val = 0x1FE545E0 },
         { .reg = 0x00009888, .val = 0x0585C70E },
         { .reg = 0x00009888, .val = 0x07850E78 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50C70 },
         { .reg = 0x00009888, .val = 0x0BA50E78 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50C70 },
         { .reg = 0x00009888, .val = 0x0FC50E78 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50C70 },
         { .reg = 0x00009888, .val = 0x13E50E78 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext170__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext170__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext170__avg_gpu_core_frequency__max,acmgt1__ext170__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1548, 24, NULL,acmgt1__ext170__rt_traversal_output_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1549, 32, NULL,acmgt1__ext170__rt_traversal_output_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1550, 40, NULL,acmgt1__ext170__rt_traversal_output_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1551, 48, NULL,acmgt1__ext170__rt_traversal_output_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext171_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext171";
   query->symbol_name = "Ext171";
   query->guid = "f2b8f05e-1936-47b6-b1ac-99a441971cea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x07850500 },
         { .reg = 0x00009888, .val = 0x07A50014 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x02850100 },
         { .reg = 0x00009888, .val = 0x0A850500 },
         { .reg = 0x00009888, .val = 0x128505C0 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00868000 },
         { .reg = 0x00009888, .val = 0x02868000 },
         { .reg = 0x00009888, .val = 0x02A50100 },
         { .reg = 0x00009888, .val = 0x0AA50014 },
         { .reg = 0x00009888, .val = 0x12A50017 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A62000 },
         { .reg = 0x00009888, .val = 0x02A62000 },
         { .reg = 0x00009888, .val = 0x02C50100 },
         { .reg = 0x00009888, .val = 0x08C50500 },
         { .reg = 0x00009888, .val = 0x10C505C0 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C60800 },
         { .reg = 0x00009888, .val = 0x02C60800 },
         { .reg = 0x00009888, .val = 0x02E50100 },
         { .reg = 0x00009888, .val = 0x08E50014 },
         { .reg = 0x00009888, .val = 0x10E50017 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E60200 },
         { .reg = 0x00009888, .val = 0x02E60200 },
         { .reg = 0x00009888, .val = 0x03850100 },
         { .reg = 0x00009888, .val = 0x0F8505C0 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x01860080 },
         { .reg = 0x00009888, .val = 0x03860080 },
         { .reg = 0x00009888, .val = 0x03A50100 },
         { .reg = 0x00009888, .val = 0x0FA50017 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A60020 },
         { .reg = 0x00009888, .val = 0x03A60020 },
         { .reg = 0x00009888, .val = 0x03C50100 },
         { .reg = 0x00009888, .val = 0x05C55000 },
         { .reg = 0x00009888, .val = 0x0DC505C0 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C60008 },
         { .reg = 0x00009888, .val = 0x03C60008 },
         { .reg = 0x00009888, .val = 0x03E50100 },
         { .reg = 0x00009888, .val = 0x05E50140 },
         { .reg = 0x00009888, .val = 0x0DE50017 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E60002 },
         { .reg = 0x00009888, .val = 0x03E60002 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030600 },
         { .reg = 0x00009888, .val = 0x4A030E21 },
         { .reg = 0x00009888, .val = 0x4C031067 },
         { .reg = 0x00009888, .val = 0x4E030E07 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031C43 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x46032808 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext171__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext171__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext171__avg_gpu_core_frequency__max,acmgt1__ext171__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1552, 24, NULL,acmgt1__ext171__rt_quad_test_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1553, 32, NULL,acmgt1__ext171__rt_quad_test_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1554, 40, NULL,acmgt1__ext171__rt_quad_test_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1555, 48, NULL,acmgt1__ext171__rt_quad_test_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1556, 56, NULL,acmgt1__ext171__rt_quad_test_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1557, 64, NULL,acmgt1__ext171__rt_quad_test_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1558, 72, NULL,acmgt1__ext171__rt_quad_test_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1559, 80, NULL,acmgt1__ext171__rt_quad_test_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1560, 88, NULL,acmgt1__ext171__rt_transform_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1561, 96, NULL,acmgt1__ext171__rt_transform_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1562, 104, NULL,acmgt1__ext171__rt_transform_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1563, 112, NULL,acmgt1__ext171__rt_transform_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1564, 120, NULL,acmgt1__ext171__rt_transform_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1565, 128, NULL,acmgt1__ext171__rt_transform_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1566, 136, NULL,acmgt1__ext171__rt_transform_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1567, 144, NULL,acmgt1__ext171__rt_transform_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext172_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext172";
   query->symbol_name = "Ext172";
   query->guid = "72ae9945-8887-4c8b-acd6-559e4b92203e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x168503C0 },
         { .reg = 0x00009888, .val = 0x06852000 },
         { .reg = 0x00009888, .val = 0x16A503C0 },
         { .reg = 0x00009888, .val = 0x06A52000 },
         { .reg = 0x00009888, .val = 0x16C503C0 },
         { .reg = 0x00009888, .val = 0x06C52000 },
         { .reg = 0x00009888, .val = 0x16E503C0 },
         { .reg = 0x00009888, .val = 0x06E52000 },
         { .reg = 0x00009888, .val = 0x178503C0 },
         { .reg = 0x00009888, .val = 0x07852400 },
         { .reg = 0x00009888, .val = 0x17A503C0 },
         { .reg = 0x00009888, .val = 0x07A52010 },
         { .reg = 0x00009888, .val = 0x17C503C0 },
         { .reg = 0x00009888, .val = 0x07C52000 },
         { .reg = 0x00009888, .val = 0x17E503C0 },
         { .reg = 0x00009888, .val = 0x07E52000 },
         { .reg = 0x00009888, .val = 0x02850104 },
         { .reg = 0x00009888, .val = 0x0A850400 },
         { .reg = 0x00009888, .val = 0x12850140 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00868000 },
         { .reg = 0x00009888, .val = 0x02868000 },
         { .reg = 0x00009888, .val = 0x02A50104 },
         { .reg = 0x00009888, .val = 0x0AA50010 },
         { .reg = 0x00009888, .val = 0x12A50005 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A62000 },
         { .reg = 0x00009888, .val = 0x02A62000 },
         { .reg = 0x00009888, .val = 0x02C50104 },
         { .reg = 0x00009888, .val = 0x08C50400 },
         { .reg = 0x00009888, .val = 0x10C50140 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C60800 },
         { .reg = 0x00009888, .val = 0x02C60800 },
         { .reg = 0x00009888, .val = 0x02E50104 },
         { .reg = 0x00009888, .val = 0x08E50010 },
         { .reg = 0x00009888, .val = 0x10E50005 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E60200 },
         { .reg = 0x00009888, .val = 0x02E60200 },
         { .reg = 0x00009888, .val = 0x03850104 },
         { .reg = 0x00009888, .val = 0x0F850140 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x01860080 },
         { .reg = 0x00009888, .val = 0x03860080 },
         { .reg = 0x00009888, .val = 0x03A50104 },
         { .reg = 0x00009888, .val = 0x0FA50005 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A60020 },
         { .reg = 0x00009888, .val = 0x03A60020 },
         { .reg = 0x00009888, .val = 0x03C50104 },
         { .reg = 0x00009888, .val = 0x05C54000 },
         { .reg = 0x00009888, .val = 0x0DC50140 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C60008 },
         { .reg = 0x00009888, .val = 0x03C60008 },
         { .reg = 0x00009888, .val = 0x03E50104 },
         { .reg = 0x00009888, .val = 0x05E50100 },
         { .reg = 0x00009888, .val = 0x0DE50005 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E60002 },
         { .reg = 0x00009888, .val = 0x03E60002 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030600 },
         { .reg = 0x00009888, .val = 0x4A030E21 },
         { .reg = 0x00009888, .val = 0x4C031067 },
         { .reg = 0x00009888, .val = 0x4E030E07 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44031C43 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22033000 },
         { .reg = 0x00009888, .val = 0x46032808 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext172__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext172__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext172__avg_gpu_core_frequency__max,acmgt1__ext172__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1568, 24, percentage_max_float,acmgt1__ext172__rt_message_stall_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1569, 28, percentage_max_float,acmgt1__ext172__rt_message_stall_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1570, 32, percentage_max_float,acmgt1__ext172__rt_message_stall_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1571, 36, percentage_max_float,acmgt1__ext172__rt_message_stall_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1572, 40, percentage_max_float,acmgt1__ext172__rt_message_stall_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1573, 44, percentage_max_float,acmgt1__ext172__rt_message_stall_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1574, 48, percentage_max_float,acmgt1__ext172__rt_message_stall_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1575, 52, percentage_max_float,acmgt1__ext172__rt_message_stall_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1576, 56, NULL,acmgt1__ext172__rt_request_collision_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1577, 64, NULL,acmgt1__ext172__rt_request_collision_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1578, 72, NULL,acmgt1__ext172__rt_request_collision_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1579, 80, NULL,acmgt1__ext172__rt_request_collision_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1580, 88, NULL,acmgt1__ext172__rt_request_collision_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1581, 96, NULL,acmgt1__ext172__rt_request_collision_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1582, 104, NULL,acmgt1__ext172__rt_request_collision_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1583, 112, NULL,acmgt1__ext172__rt_request_collision_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext173_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext173";
   query->symbol_name = "Ext173";
   query->guid = "1861b4c1-3950-4855-a8db-6e0b90fc44aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0A900236 },
         { .reg = 0x00009888, .val = 0x0C90016A },
         { .reg = 0x00009888, .val = 0x009042B2 },
         { .reg = 0x00009888, .val = 0x02904E9C },
         { .reg = 0x00009888, .val = 0x04900717 },
         { .reg = 0x00009888, .val = 0x069000E6 },
         { .reg = 0x00009888, .val = 0x08900840 },
         { .reg = 0x00009888, .val = 0x00815555 },
         { .reg = 0x00009888, .val = 0x02815415 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283A82A },
         { .reg = 0x00009888, .val = 0x0084E7FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865415 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x02875415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004E7FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035415 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext173__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext173__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext173__avg_gpu_core_frequency__max,acmgt1__ext173__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1584, 24, percentage_max_float,acmgt1__ext173__xve_stall_aluwr_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1585, 28, percentage_max_float,acmgt1__ext173__xve_stall_barrier_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1586, 32, percentage_max_float,acmgt1__ext173__xve_stall_instfetch_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1587, 36, percentage_max_float,acmgt1__ext173__xve_stall_other_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1588, 40, percentage_max_float,acmgt1__ext173__xve_stall_sbid_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1589, 44, percentage_max_float,acmgt1__ext173__xve_stall_sendwr_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1590, 48, percentage_max_float,acmgt1__ext173__xve_shared_function_access_hold_xecore0_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext174_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext174";
   query->symbol_name = "Ext174";
   query->guid = "b29accb6-ff91-45d5-953b-2ca3c0983f66";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AB00236 },
         { .reg = 0x00009888, .val = 0x0CB0016A },
         { .reg = 0x00009888, .val = 0x00B042B2 },
         { .reg = 0x00009888, .val = 0x02B04E9C },
         { .reg = 0x00009888, .val = 0x04B00717 },
         { .reg = 0x00009888, .val = 0x06B000E6 },
         { .reg = 0x00009888, .val = 0x08B00840 },
         { .reg = 0x00009888, .val = 0x00A15555 },
         { .reg = 0x00009888, .val = 0x02A15415 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3A82A },
         { .reg = 0x00009888, .val = 0x00A4E7FF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65415 },
         { .reg = 0x00009888, .val = 0x00A75555 },
         { .reg = 0x00009888, .val = 0x02A75415 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004E7FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035415 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext174__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext174__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext174__avg_gpu_core_frequency__max,acmgt1__ext174__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1591, 24, percentage_max_float,acmgt1__ext174__xve_stall_aluwr_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1592, 28, percentage_max_float,acmgt1__ext174__xve_stall_barrier_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1593, 32, percentage_max_float,acmgt1__ext174__xve_stall_instfetch_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1594, 36, percentage_max_float,acmgt1__ext174__xve_stall_other_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1595, 40, percentage_max_float,acmgt1__ext174__xve_stall_sbid_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1596, 44, percentage_max_float,acmgt1__ext174__xve_stall_sendwr_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1597, 48, percentage_max_float,acmgt1__ext174__xve_shared_function_access_hold_xecore1_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext175_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext175";
   query->symbol_name = "Ext175";
   query->guid = "218c081a-6fe6-4a26-afb6-ca6bd1bf78eb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AD00236 },
         { .reg = 0x00009888, .val = 0x0CD0016A },
         { .reg = 0x00009888, .val = 0x00D042B2 },
         { .reg = 0x00009888, .val = 0x02D04E9C },
         { .reg = 0x00009888, .val = 0x04D00717 },
         { .reg = 0x00009888, .val = 0x06D000E6 },
         { .reg = 0x00009888, .val = 0x08D00840 },
         { .reg = 0x00009888, .val = 0x00C15555 },
         { .reg = 0x00009888, .val = 0x02C15415 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3A82A },
         { .reg = 0x00009888, .val = 0x00C4E7FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65415 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x02C75415 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207A82A },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009888, .val = 0x0002E7FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004E7FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035415 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext175__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext175__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext175__avg_gpu_core_frequency__max,acmgt1__ext175__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1598, 24, percentage_max_float,acmgt1__ext175__xve_stall_aluwr_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1599, 28, percentage_max_float,acmgt1__ext175__xve_stall_barrier_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1600, 32, percentage_max_float,acmgt1__ext175__xve_stall_instfetch_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1601, 36, percentage_max_float,acmgt1__ext175__xve_stall_other_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1602, 40, percentage_max_float,acmgt1__ext175__xve_stall_sbid_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1603, 44, percentage_max_float,acmgt1__ext175__xve_stall_sendwr_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1604, 48, percentage_max_float,acmgt1__ext175__xve_shared_function_access_hold_xecore2_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext176_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext176";
   query->symbol_name = "Ext176";
   query->guid = "f7d99e5e-4cb7-47da-835f-ec31a8838dc5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AF00236 },
         { .reg = 0x00009888, .val = 0x0CF0016A },
         { .reg = 0x00009888, .val = 0x00F042B2 },
         { .reg = 0x00009888, .val = 0x02F04E9C },
         { .reg = 0x00009888, .val = 0x04F00717 },
         { .reg = 0x00009888, .val = 0x06F000E6 },
         { .reg = 0x00009888, .val = 0x08F00840 },
         { .reg = 0x00009888, .val = 0x00E15555 },
         { .reg = 0x00009888, .val = 0x02E15415 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3A82A },
         { .reg = 0x00009888, .val = 0x00E4E7FF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65415 },
         { .reg = 0x00009888, .val = 0x00E75555 },
         { .reg = 0x00009888, .val = 0x02E75415 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075415 },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004E7FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035415 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext176__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext176__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext176__avg_gpu_core_frequency__max,acmgt1__ext176__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1605, 24, percentage_max_float,acmgt1__ext176__xve_stall_aluwr_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1606, 28, percentage_max_float,acmgt1__ext176__xve_stall_barrier_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1607, 32, percentage_max_float,acmgt1__ext176__xve_stall_instfetch_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1608, 36, percentage_max_float,acmgt1__ext176__xve_stall_other_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1609, 40, percentage_max_float,acmgt1__ext176__xve_stall_sbid_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1610, 44, percentage_max_float,acmgt1__ext176__xve_stall_sendwr_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1611, 48, percentage_max_float,acmgt1__ext176__xve_shared_function_access_hold_xecore3_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext177_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext177";
   query->symbol_name = "Ext177";
   query->guid = "da0fd1f5-25bd-44d7-aced-87d78f3f0a7d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0B900236 },
         { .reg = 0x00009888, .val = 0x0D90016A },
         { .reg = 0x00009888, .val = 0x019042B2 },
         { .reg = 0x00009888, .val = 0x03904E9C },
         { .reg = 0x00009888, .val = 0x05900717 },
         { .reg = 0x00009888, .val = 0x079000E6 },
         { .reg = 0x00009888, .val = 0x09900840 },
         { .reg = 0x00009888, .val = 0x01815555 },
         { .reg = 0x00009888, .val = 0x03815415 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383A82A },
         { .reg = 0x00009888, .val = 0x0184E7FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865415 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x03875415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308A82A },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004E7FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035415 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext177__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext177__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext177__avg_gpu_core_frequency__max,acmgt1__ext177__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1612, 24, percentage_max_float,acmgt1__ext177__xve_stall_aluwr_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1613, 28, percentage_max_float,acmgt1__ext177__xve_stall_barrier_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1614, 32, percentage_max_float,acmgt1__ext177__xve_stall_instfetch_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1615, 36, percentage_max_float,acmgt1__ext177__xve_stall_other_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1616, 40, percentage_max_float,acmgt1__ext177__xve_stall_sbid_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1617, 44, percentage_max_float,acmgt1__ext177__xve_stall_sendwr_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1618, 48, percentage_max_float,acmgt1__ext177__xve_shared_function_access_hold_xecore4_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext178_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext178";
   query->symbol_name = "Ext178";
   query->guid = "e1495a70-d6ea-4867-aa48-4135567bf19b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BB00236 },
         { .reg = 0x00009888, .val = 0x0DB0016A },
         { .reg = 0x00009888, .val = 0x01B042B2 },
         { .reg = 0x00009888, .val = 0x03B04E9C },
         { .reg = 0x00009888, .val = 0x05B00717 },
         { .reg = 0x00009888, .val = 0x07B000E6 },
         { .reg = 0x00009888, .val = 0x09B00840 },
         { .reg = 0x00009888, .val = 0x01A15555 },
         { .reg = 0x00009888, .val = 0x03A15415 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3A82A },
         { .reg = 0x00009888, .val = 0x01A4E7FF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65415 },
         { .reg = 0x00009888, .val = 0x01A75555 },
         { .reg = 0x00009888, .val = 0x03A75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FC3F },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009888, .val = 0x0101E7FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004E7FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035415 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext178__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext178__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext178__avg_gpu_core_frequency__max,acmgt1__ext178__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1619, 24, percentage_max_float,acmgt1__ext178__xve_stall_aluwr_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1620, 28, percentage_max_float,acmgt1__ext178__xve_stall_barrier_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1621, 32, percentage_max_float,acmgt1__ext178__xve_stall_instfetch_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1622, 36, percentage_max_float,acmgt1__ext178__xve_stall_other_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1623, 40, percentage_max_float,acmgt1__ext178__xve_stall_sbid_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1624, 44, percentage_max_float,acmgt1__ext178__xve_stall_sendwr_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1625, 48, percentage_max_float,acmgt1__ext178__xve_shared_function_access_hold_xecore5_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext179_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext179";
   query->symbol_name = "Ext179";
   query->guid = "d2b946b8-ddbc-47bb-b02d-f89652163b6a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BD00236 },
         { .reg = 0x00009888, .val = 0x0DD0016A },
         { .reg = 0x00009888, .val = 0x01D042B2 },
         { .reg = 0x00009888, .val = 0x03D04E9C },
         { .reg = 0x00009888, .val = 0x05D00717 },
         { .reg = 0x00009888, .val = 0x07D000E6 },
         { .reg = 0x00009888, .val = 0x09D00840 },
         { .reg = 0x00009888, .val = 0x01C15555 },
         { .reg = 0x00009888, .val = 0x03C15415 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3A82A },
         { .reg = 0x00009888, .val = 0x01C4E7FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65415 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x03C75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307A82A },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009888, .val = 0x0102E7FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004E7FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035415 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext179__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext179__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext179__avg_gpu_core_frequency__max,acmgt1__ext179__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1626, 24, percentage_max_float,acmgt1__ext179__xve_stall_aluwr_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1627, 28, percentage_max_float,acmgt1__ext179__xve_stall_barrier_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1628, 32, percentage_max_float,acmgt1__ext179__xve_stall_instfetch_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1629, 36, percentage_max_float,acmgt1__ext179__xve_stall_other_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1630, 40, percentage_max_float,acmgt1__ext179__xve_stall_sbid_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1631, 44, percentage_max_float,acmgt1__ext179__xve_stall_sendwr_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1632, 48, percentage_max_float,acmgt1__ext179__xve_shared_function_access_hold_xecore6_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext180_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext180";
   query->symbol_name = "Ext180";
   query->guid = "44915f22-aaca-4871-b8ca-7a83aa83d605";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BF00236 },
         { .reg = 0x00009888, .val = 0x0DF0016A },
         { .reg = 0x00009888, .val = 0x01F042B2 },
         { .reg = 0x00009888, .val = 0x03F04E9C },
         { .reg = 0x00009888, .val = 0x05F00717 },
         { .reg = 0x00009888, .val = 0x07F000E6 },
         { .reg = 0x00009888, .val = 0x09F00840 },
         { .reg = 0x00009888, .val = 0x01E15555 },
         { .reg = 0x00009888, .val = 0x03E15415 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3A82A },
         { .reg = 0x00009888, .val = 0x01E4E7FF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65415 },
         { .reg = 0x00009888, .val = 0x01E75555 },
         { .reg = 0x00009888, .val = 0x03E75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075415 },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004E7FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035415 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext180__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext180__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext180__avg_gpu_core_frequency__max,acmgt1__ext180__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1633, 24, percentage_max_float,acmgt1__ext180__xve_stall_aluwr_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1634, 28, percentage_max_float,acmgt1__ext180__xve_stall_barrier_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1635, 32, percentage_max_float,acmgt1__ext180__xve_stall_instfetch_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1636, 36, percentage_max_float,acmgt1__ext180__xve_stall_other_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1637, 40, percentage_max_float,acmgt1__ext180__xve_stall_sbid_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1638, 44, percentage_max_float,acmgt1__ext180__xve_stall_sendwr_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1639, 48, percentage_max_float,acmgt1__ext180__xve_shared_function_access_hold_xecore7_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext181_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext181";
   query->symbol_name = "Ext181";
   query->guid = "fe0eda19-22d8-410e-b61d-24bce297d8ae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0A906F40 },
         { .reg = 0x00009888, .val = 0x0C900006 },
         { .reg = 0x00009888, .val = 0x0AB06F40 },
         { .reg = 0x00009888, .val = 0x0CB00006 },
         { .reg = 0x00009888, .val = 0x0AD06F40 },
         { .reg = 0x00009888, .val = 0x0CD00006 },
         { .reg = 0x00009888, .val = 0x00904EB4 },
         { .reg = 0x00009888, .val = 0x02900166 },
         { .reg = 0x00009888, .val = 0x00810155 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x02B05000 },
         { .reg = 0x00009888, .val = 0x04B01A75 },
         { .reg = 0x00009888, .val = 0x06B0000B },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A15400 },
         { .reg = 0x00009888, .val = 0x02A10005 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x06D05680 },
         { .reg = 0x00009888, .val = 0x08D02CD3 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x02C11550 },
         { .reg = 0x00009888, .val = 0x02C32AA0 },
         { .reg = 0x00009888, .val = 0x00C47C00 },
         { .reg = 0x00009888, .val = 0x02C61550 },
         { .reg = 0x00009888, .val = 0x02C71550 },
         { .reg = 0x00009888, .val = 0x02072AA0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x00097C00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A2AA5 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020B0005 },
         { .reg = 0x00009888, .val = 0x00027C00 },
         { .reg = 0x00009888, .val = 0x020C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00047FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030221 },
         { .reg = 0x00009888, .val = 0x4C030602 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030603 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext181__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext181__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext181__avg_gpu_core_frequency__max,acmgt1__ext181__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1640, 24, NULL,acmgt1__ext181__xve_inst_issued_all_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1641, 32, NULL,acmgt1__ext181__xve_inst_issued_all_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1642, 40, NULL,acmgt1__ext181__xve_inst_issued_all_xecore2_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext182_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext182";
   query->symbol_name = "Ext182";
   query->guid = "aef5adcb-e3ef-4839-aea5-a6bbb9bb5faa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AF06F40 },
         { .reg = 0x00009888, .val = 0x0CF00006 },
         { .reg = 0x00009888, .val = 0x0B906F40 },
         { .reg = 0x00009888, .val = 0x0D900006 },
         { .reg = 0x00009888, .val = 0x0BB06F40 },
         { .reg = 0x00009888, .val = 0x0DB00006 },
         { .reg = 0x00009888, .val = 0x00F04EB4 },
         { .reg = 0x00009888, .val = 0x02F00166 },
         { .reg = 0x00009888, .val = 0x00E10155 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x03905000 },
         { .reg = 0x00009888, .val = 0x05901A75 },
         { .reg = 0x00009888, .val = 0x0790000B },
         { .reg = 0x00009888, .val = 0x01900000 },
         { .reg = 0x00009888, .val = 0x01815400 },
         { .reg = 0x00009888, .val = 0x03810005 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07B05680 },
         { .reg = 0x00009888, .val = 0x09B02CD3 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x03A11550 },
         { .reg = 0x00009888, .val = 0x03A32AA0 },
         { .reg = 0x00009888, .val = 0x01A47C00 },
         { .reg = 0x00009888, .val = 0x03A61550 },
         { .reg = 0x00009888, .val = 0x03A71550 },
         { .reg = 0x00009888, .val = 0x00037FE0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x03083FFA },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A1555 },
         { .reg = 0x00009888, .val = 0x01017C00 },
         { .reg = 0x00009888, .val = 0x030B1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00047FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x480308E4 },
         { .reg = 0x00009888, .val = 0x4A030E47 },
         { .reg = 0x00009888, .val = 0x4C031404 },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext182__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext182__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext182__avg_gpu_core_frequency__max,acmgt1__ext182__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1643, 24, NULL,acmgt1__ext182__xve_inst_issued_all_xecore3_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1644, 32, NULL,acmgt1__ext182__xve_inst_issued_all_xecore4_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1645, 40, NULL,acmgt1__ext182__xve_inst_issued_all_xecore5_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext183_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext183";
   query->symbol_name = "Ext183";
   query->guid = "1cf7ed05-8260-4abe-b00c-7f3ae3441d4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BD06F40 },
         { .reg = 0x00009888, .val = 0x0DD00006 },
         { .reg = 0x00009888, .val = 0x0BF06F40 },
         { .reg = 0x00009888, .val = 0x0DF00006 },
         { .reg = 0x00009888, .val = 0x01D04EB4 },
         { .reg = 0x00009888, .val = 0x03D00166 },
         { .reg = 0x00009888, .val = 0x01C10155 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x03F05000 },
         { .reg = 0x00009888, .val = 0x05F01A75 },
         { .reg = 0x00009888, .val = 0x07F0000B },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x01E15400 },
         { .reg = 0x00009888, .val = 0x03E10005 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x010756AA },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x180301E9 },
         { .reg = 0x00009888, .val = 0x180801E9 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x0E030E30 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x020400A5 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x10080E30 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00043FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02020AAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C031400 },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x44034908 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x2003F000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030012 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00002002 },
         { .reg = 0x0000D954, .val = 0x0000F3FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x0000CFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext183__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext183__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext183__avg_gpu_core_frequency__max,acmgt1__ext183__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1646, 24, NULL,acmgt1__ext183__xve_inst_issued_all_xecore6_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1647, 32, NULL,acmgt1__ext183__xve_inst_issued_all_xecore7_xve0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1648, 40, NULL,acmgt1__ext183__render_cache_alloc_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1649, 48, NULL,acmgt1__ext183__render_cache_alloc_l3_node1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext184_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext184";
   query->symbol_name = "Ext184";
   query->guid = "39badcb4-5410-4218-b272-1e5edc606b5c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18894740 },
         { .reg = 0x00009888, .val = 0x1E89023A },
         { .reg = 0x00009888, .val = 0x22896800 },
         { .reg = 0x00009888, .val = 0x24890011 },
         { .reg = 0x00009888, .val = 0x28894740 },
         { .reg = 0x00009888, .val = 0x18A94740 },
         { .reg = 0x00009888, .val = 0x1EA9023A },
         { .reg = 0x00009888, .val = 0x22A96800 },
         { .reg = 0x00009888, .val = 0x24A90011 },
         { .reg = 0x00009888, .val = 0x28A94740 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x068903C1 },
         { .reg = 0x00009888, .val = 0x088907D1 },
         { .reg = 0x00009888, .val = 0x0A890BE1 },
         { .reg = 0x00009888, .val = 0x0C890FF1 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x0EA903C1 },
         { .reg = 0x00009888, .val = 0x10A907D1 },
         { .reg = 0x00009888, .val = 0x12A90BE1 },
         { .reg = 0x00009888, .val = 0x14A90FF1 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext184__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext184__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext184__avg_gpu_core_frequency__max,acmgt1__ext184__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1650, 24, NULL,acmgt1__ext184__rt_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1651, 32, NULL,acmgt1__ext184__rt_load_store_cache_read_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext185_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext185";
   query->symbol_name = "Ext185";
   query->guid = "e1e40930-36f2-480c-b15d-cf2fb07f18e1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18C94740 },
         { .reg = 0x00009888, .val = 0x1EC9023A },
         { .reg = 0x00009888, .val = 0x22C96800 },
         { .reg = 0x00009888, .val = 0x24C90011 },
         { .reg = 0x00009888, .val = 0x28C94740 },
         { .reg = 0x00009888, .val = 0x18E94740 },
         { .reg = 0x00009888, .val = 0x1EE9023A },
         { .reg = 0x00009888, .val = 0x22E96800 },
         { .reg = 0x00009888, .val = 0x24E90011 },
         { .reg = 0x00009888, .val = 0x28E94740 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C903C1 },
         { .reg = 0x00009888, .val = 0x08C907D1 },
         { .reg = 0x00009888, .val = 0x0AC90BE1 },
         { .reg = 0x00009888, .val = 0x0CC90FF1 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x0EE903C1 },
         { .reg = 0x00009888, .val = 0x10E907D1 },
         { .reg = 0x00009888, .val = 0x12E90BE1 },
         { .reg = 0x00009888, .val = 0x14E90FF1 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext185__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext185__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext185__avg_gpu_core_frequency__max,acmgt1__ext185__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1652, 24, NULL,acmgt1__ext185__rt_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1653, 32, NULL,acmgt1__ext185__rt_load_store_cache_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext186_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext186";
   query->symbol_name = "Ext186";
   query->guid = "4edf8144-d144-4110-b34c-0f6133409bae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19894740 },
         { .reg = 0x00009888, .val = 0x1F89023A },
         { .reg = 0x00009888, .val = 0x23896800 },
         { .reg = 0x00009888, .val = 0x25890011 },
         { .reg = 0x00009888, .val = 0x29894740 },
         { .reg = 0x00009888, .val = 0x19A94740 },
         { .reg = 0x00009888, .val = 0x1FA9023A },
         { .reg = 0x00009888, .val = 0x23A96800 },
         { .reg = 0x00009888, .val = 0x25A90011 },
         { .reg = 0x00009888, .val = 0x29A94740 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x078903C1 },
         { .reg = 0x00009888, .val = 0x098907D1 },
         { .reg = 0x00009888, .val = 0x0B890BE1 },
         { .reg = 0x00009888, .val = 0x0D890FF1 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x0FA903C1 },
         { .reg = 0x00009888, .val = 0x11A907D1 },
         { .reg = 0x00009888, .val = 0x13A90BE1 },
         { .reg = 0x00009888, .val = 0x15A90FF1 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext186__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext186__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext186__avg_gpu_core_frequency__max,acmgt1__ext186__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1654, 24, NULL,acmgt1__ext186__rt_load_store_cache_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1655, 32, NULL,acmgt1__ext186__rt_load_store_cache_read_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext187_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext187";
   query->symbol_name = "Ext187";
   query->guid = "a035c742-180e-4bf0-8009-5668cb08981f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19C94740 },
         { .reg = 0x00009888, .val = 0x1FC9023A },
         { .reg = 0x00009888, .val = 0x23C96800 },
         { .reg = 0x00009888, .val = 0x25C90011 },
         { .reg = 0x00009888, .val = 0x29C94740 },
         { .reg = 0x00009888, .val = 0x19E94740 },
         { .reg = 0x00009888, .val = 0x1FE9023A },
         { .reg = 0x00009888, .val = 0x23E96800 },
         { .reg = 0x00009888, .val = 0x25E90011 },
         { .reg = 0x00009888, .val = 0x29E94740 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C903C1 },
         { .reg = 0x00009888, .val = 0x09C907D1 },
         { .reg = 0x00009888, .val = 0x0BC90BE1 },
         { .reg = 0x00009888, .val = 0x0DC90FF1 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x0FE903C1 },
         { .reg = 0x00009888, .val = 0x11E907D1 },
         { .reg = 0x00009888, .val = 0x13E90BE1 },
         { .reg = 0x00009888, .val = 0x15E90FF1 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext187__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext187__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext187__avg_gpu_core_frequency__max,acmgt1__ext187__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1656, 24, NULL,acmgt1__ext187__rt_load_store_cache_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1657, 32, NULL,acmgt1__ext187__rt_load_store_cache_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext188_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext188";
   query->symbol_name = "Ext188";
   query->guid = "1236f8d6-fa44-40eb-addc-8e4695b02ab3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18894740 },
         { .reg = 0x00009888, .val = 0x1E89023A },
         { .reg = 0x00009888, .val = 0x22896800 },
         { .reg = 0x00009888, .val = 0x24890011 },
         { .reg = 0x00009888, .val = 0x28894740 },
         { .reg = 0x00009888, .val = 0x18A94740 },
         { .reg = 0x00009888, .val = 0x1EA9023A },
         { .reg = 0x00009888, .val = 0x22A96800 },
         { .reg = 0x00009888, .val = 0x24A90011 },
         { .reg = 0x00009888, .val = 0x28A94740 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x068903C1 },
         { .reg = 0x00009888, .val = 0x088907D1 },
         { .reg = 0x00009888, .val = 0x0A890BE1 },
         { .reg = 0x00009888, .val = 0x0C890FF1 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x0EA903C1 },
         { .reg = 0x00009888, .val = 0x10A907D1 },
         { .reg = 0x00009888, .val = 0x12A90BE1 },
         { .reg = 0x00009888, .val = 0x14A90FF1 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext188__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext188__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext188__avg_gpu_core_frequency__max,acmgt1__ext188__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1658, 24, NULL,acmgt1__ext188__rt_load_store_cache_write_from_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1659, 32, NULL,acmgt1__ext188__rt_load_store_cache_write_from_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext189_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext189";
   query->symbol_name = "Ext189";
   query->guid = "d37f51e7-16dd-4616-88a0-cfc54b90a43f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18C94740 },
         { .reg = 0x00009888, .val = 0x1EC9023A },
         { .reg = 0x00009888, .val = 0x22C96800 },
         { .reg = 0x00009888, .val = 0x24C90011 },
         { .reg = 0x00009888, .val = 0x28C94740 },
         { .reg = 0x00009888, .val = 0x18E94740 },
         { .reg = 0x00009888, .val = 0x1EE9023A },
         { .reg = 0x00009888, .val = 0x22E96800 },
         { .reg = 0x00009888, .val = 0x24E90011 },
         { .reg = 0x00009888, .val = 0x28E94740 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C903C1 },
         { .reg = 0x00009888, .val = 0x08C907D1 },
         { .reg = 0x00009888, .val = 0x0AC90BE1 },
         { .reg = 0x00009888, .val = 0x0CC90FF1 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x0EE903C1 },
         { .reg = 0x00009888, .val = 0x10E907D1 },
         { .reg = 0x00009888, .val = 0x12E90BE1 },
         { .reg = 0x00009888, .val = 0x14E90FF1 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext189__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext189__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext189__avg_gpu_core_frequency__max,acmgt1__ext189__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1660, 24, NULL,acmgt1__ext189__rt_load_store_cache_write_from_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1661, 32, NULL,acmgt1__ext189__rt_load_store_cache_write_from_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext190_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext190";
   query->symbol_name = "Ext190";
   query->guid = "c9ac09ca-af08-4072-8e8b-dbc81cd95ada";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19894740 },
         { .reg = 0x00009888, .val = 0x1F89023A },
         { .reg = 0x00009888, .val = 0x23896800 },
         { .reg = 0x00009888, .val = 0x25890011 },
         { .reg = 0x00009888, .val = 0x29894740 },
         { .reg = 0x00009888, .val = 0x19A94740 },
         { .reg = 0x00009888, .val = 0x1FA9023A },
         { .reg = 0x00009888, .val = 0x23A96800 },
         { .reg = 0x00009888, .val = 0x25A90011 },
         { .reg = 0x00009888, .val = 0x29A94740 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x078903C1 },
         { .reg = 0x00009888, .val = 0x098907D1 },
         { .reg = 0x00009888, .val = 0x0B890BE1 },
         { .reg = 0x00009888, .val = 0x0D890FF1 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x0FA903C1 },
         { .reg = 0x00009888, .val = 0x11A907D1 },
         { .reg = 0x00009888, .val = 0x13A90BE1 },
         { .reg = 0x00009888, .val = 0x15A90FF1 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003000A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext190__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext190__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext190__avg_gpu_core_frequency__max,acmgt1__ext190__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1662, 24, NULL,acmgt1__ext190__rt_load_store_cache_write_from_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1663, 32, NULL,acmgt1__ext190__rt_load_store_cache_write_from_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext191_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext191";
   query->symbol_name = "Ext191";
   query->guid = "9e1699e6-cea6-46de-bb89-050415f0a8a2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19C94740 },
         { .reg = 0x00009888, .val = 0x1FC9023A },
         { .reg = 0x00009888, .val = 0x23C96800 },
         { .reg = 0x00009888, .val = 0x25C90011 },
         { .reg = 0x00009888, .val = 0x29C94740 },
         { .reg = 0x00009888, .val = 0x19E94740 },
         { .reg = 0x00009888, .val = 0x1FE9023A },
         { .reg = 0x00009888, .val = 0x23E96800 },
         { .reg = 0x00009888, .val = 0x25E90011 },
         { .reg = 0x00009888, .val = 0x29E94740 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C903C1 },
         { .reg = 0x00009888, .val = 0x09C907D1 },
         { .reg = 0x00009888, .val = 0x0BC90BE1 },
         { .reg = 0x00009888, .val = 0x0DC90FF1 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x0FE903C1 },
         { .reg = 0x00009888, .val = 0x11E907D1 },
         { .reg = 0x00009888, .val = 0x13E90BE1 },
         { .reg = 0x00009888, .val = 0x15E90FF1 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50031400 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext191__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext191__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext191__avg_gpu_core_frequency__max,acmgt1__ext191__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1664, 24, NULL,acmgt1__ext191__rt_load_store_cache_write_from_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1665, 32, NULL,acmgt1__ext191__rt_load_store_cache_write_from_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext192_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext192";
   query->symbol_name = "Ext192";
   query->guid = "e671dd75-968d-49e4-9c03-5269d95de66e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x168502A0 },
         { .reg = 0x00009888, .val = 0x16A502A0 },
         { .reg = 0x00009888, .val = 0x16C502A0 },
         { .reg = 0x00009888, .val = 0x16E502A0 },
         { .reg = 0x00009888, .val = 0x178502A0 },
         { .reg = 0x00009888, .val = 0x17A502A0 },
         { .reg = 0x00009888, .val = 0x17C502A0 },
         { .reg = 0x00009888, .val = 0x17E502A0 },
         { .reg = 0x00009888, .val = 0x02850004 },
         { .reg = 0x00009888, .val = 0x128500C2 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0286A000 },
         { .reg = 0x00009888, .val = 0x02A50004 },
         { .reg = 0x00009888, .val = 0x10A500C2 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A60A00 },
         { .reg = 0x00009888, .val = 0x02C50004 },
         { .reg = 0x00009888, .val = 0x0EC500C2 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600A0 },
         { .reg = 0x00009888, .val = 0x02E50004 },
         { .reg = 0x00009888, .val = 0x0CE500C2 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6000A },
         { .reg = 0x00009888, .val = 0x03850004 },
         { .reg = 0x00009888, .val = 0x0B8500C2 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186A000 },
         { .reg = 0x00009888, .val = 0x03A50004 },
         { .reg = 0x00009888, .val = 0x09A500C2 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A60A00 },
         { .reg = 0x00009888, .val = 0x03C50004 },
         { .reg = 0x00009888, .val = 0x07C500C2 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C600A0 },
         { .reg = 0x00009888, .val = 0x03E50004 },
         { .reg = 0x00009888, .val = 0x05E50C20 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6000A },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803000A },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030221 },
         { .reg = 0x00009888, .val = 0x50030EE2 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030077 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46032940 },
         { .reg = 0x00009888, .val = 0x24037000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001805 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006005 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018005 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060005 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext192__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext192__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext192__avg_gpu_core_frequency__max,acmgt1__ext192__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1666, 24, percentage_max_float,acmgt1__ext192__rt_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1667, 28, percentage_max_float,acmgt1__ext192__rt_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1668, 32, percentage_max_float,acmgt1__ext192__rt_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1669, 36, percentage_max_float,acmgt1__ext192__rt_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1670, 40, percentage_max_float,acmgt1__ext192__rt_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1671, 44, percentage_max_float,acmgt1__ext192__rt_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1672, 48, percentage_max_float,acmgt1__ext192__rt_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1673, 52, percentage_max_float,acmgt1__ext192__rt_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext193_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext193";
   query->symbol_name = "Ext193";
   query->guid = "9a53799a-f746-4d6d-a723-57af53243454";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x20860011 },
         { .reg = 0x00009888, .val = 0x20A60011 },
         { .reg = 0x00009888, .val = 0x20C60011 },
         { .reg = 0x00009888, .val = 0x20E60011 },
         { .reg = 0x00009888, .val = 0x04860180 },
         { .reg = 0x00009888, .val = 0x06862800 },
         { .reg = 0x00009888, .val = 0x08860595 },
         { .reg = 0x00009888, .val = 0x0A860017 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x04A60180 },
         { .reg = 0x00009888, .val = 0x0AA60500 },
         { .reg = 0x00009888, .val = 0x0CA60595 },
         { .reg = 0x00009888, .val = 0x0EA60017 },
         { .reg = 0x00009888, .val = 0x00A60000 },
         { .reg = 0x00009888, .val = 0x04C60180 },
         { .reg = 0x00009888, .val = 0x0EC60500 },
         { .reg = 0x00009888, .val = 0x10C60595 },
         { .reg = 0x00009888, .val = 0x12C60017 },
         { .reg = 0x00009888, .val = 0x02C60000 },
         { .reg = 0x00009888, .val = 0x04E60180 },
         { .reg = 0x00009888, .val = 0x12E60500 },
         { .reg = 0x00009888, .val = 0x14E60595 },
         { .reg = 0x00009888, .val = 0x16E60017 },
         { .reg = 0x00009888, .val = 0x02E60000 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030422 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030003 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603294A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext193__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext193__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext193__avg_gpu_core_frequency__max,acmgt1__ext193__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1674, 24, percentage_max_float,acmgt1__ext193__pixel_post_process_input_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1675, 28, percentage_max_float,acmgt1__ext193__pixel_post_process_input_available_cpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext194_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext194";
   query->symbol_name = "Ext194";
   query->guid = "3b4157d9-9905-48c5-a9fa-3f53f94b9b5d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x21860011 },
         { .reg = 0x00009888, .val = 0x21A60011 },
         { .reg = 0x00009888, .val = 0x21C60011 },
         { .reg = 0x00009888, .val = 0x21E60011 },
         { .reg = 0x00009888, .val = 0x05860180 },
         { .reg = 0x00009888, .val = 0x0F860500 },
         { .reg = 0x00009888, .val = 0x11860595 },
         { .reg = 0x00009888, .val = 0x13860017 },
         { .reg = 0x00009888, .val = 0x03860000 },
         { .reg = 0x00009888, .val = 0x05A60180 },
         { .reg = 0x00009888, .val = 0x13A60500 },
         { .reg = 0x00009888, .val = 0x15A60595 },
         { .reg = 0x00009888, .val = 0x17A60017 },
         { .reg = 0x00009888, .val = 0x03A60000 },
         { .reg = 0x00009888, .val = 0x05C60180 },
         { .reg = 0x00009888, .val = 0x07C62800 },
         { .reg = 0x00009888, .val = 0x09C60595 },
         { .reg = 0x00009888, .val = 0x0BC60017 },
         { .reg = 0x00009888, .val = 0x01C60000 },
         { .reg = 0x00009888, .val = 0x05E60180 },
         { .reg = 0x00009888, .val = 0x0BE60500 },
         { .reg = 0x00009888, .val = 0x0DE60595 },
         { .reg = 0x00009888, .val = 0x0FE60017 },
         { .reg = 0x00009888, .val = 0x01E60000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x010755AA },
         { .reg = 0x00009888, .val = 0x0308FFAA },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101F000 },
         { .reg = 0x00009888, .val = 0x030B5500 },
         { .reg = 0x00009888, .val = 0x0102000F },
         { .reg = 0x00009888, .val = 0x010C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C03140A },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003042A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030021 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x44030C42 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext194__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext194__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext194__avg_gpu_core_frequency__max,acmgt1__ext194__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1676, 24, percentage_max_float,acmgt1__ext194__pixel_post_process_input_available_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1677, 28, percentage_max_float,acmgt1__ext194__pixel_post_process_input_available_cpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext195_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext195";
   query->symbol_name = "Ext195";
   query->guid = "b7468d66-8862-4deb-aeb7-d2cefa81ea0e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0A902960 },
         { .reg = 0x00009888, .val = 0x0AB02960 },
         { .reg = 0x00009888, .val = 0x0AD02960 },
         { .reg = 0x00009888, .val = 0x0AF02960 },
         { .reg = 0x00009888, .val = 0x069039E0 },
         { .reg = 0x00009888, .val = 0x00900000 },
         { .reg = 0x00009888, .val = 0x02810054 },
         { .reg = 0x00009888, .val = 0x028300A8 },
         { .reg = 0x00009888, .val = 0x00840E00 },
         { .reg = 0x00009888, .val = 0x02860054 },
         { .reg = 0x00009888, .val = 0x02870054 },
         { .reg = 0x00009888, .val = 0x04B039E0 },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A15000 },
         { .reg = 0x00009888, .val = 0x02A10001 },
         { .reg = 0x00009888, .val = 0x00A3A000 },
         { .reg = 0x00009888, .val = 0x02A30002 },
         { .reg = 0x00009888, .val = 0x00A401C0 },
         { .reg = 0x00009888, .val = 0x00A65000 },
         { .reg = 0x00009888, .val = 0x02A60001 },
         { .reg = 0x00009888, .val = 0x00A75000 },
         { .reg = 0x00009888, .val = 0x02A70001 },
         { .reg = 0x00009888, .val = 0x02D039E0 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x00C10540 },
         { .reg = 0x00009888, .val = 0x00C30A80 },
         { .reg = 0x00009888, .val = 0x00C40038 },
         { .reg = 0x00009888, .val = 0x00C60540 },
         { .reg = 0x00009888, .val = 0x00C70540 },
         { .reg = 0x00009888, .val = 0x00F039E0 },
         { .reg = 0x00009888, .val = 0x00E10015 },
         { .reg = 0x00009888, .val = 0x00E3002A },
         { .reg = 0x00009888, .val = 0x00E40007 },
         { .reg = 0x00009888, .val = 0x00E60015 },
         { .reg = 0x00009888, .val = 0x00E70015 },
         { .reg = 0x00009888, .val = 0x00070A95 },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x020800AB },
         { .reg = 0x00009888, .val = 0x0009003F },
         { .reg = 0x00009888, .val = 0x000A5AAA },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x000101C0 },
         { .reg = 0x00009888, .val = 0x000B5000 },
         { .reg = 0x00009888, .val = 0x020B0001 },
         { .reg = 0x00009888, .val = 0x00020038 },
         { .reg = 0x00009888, .val = 0x000C0540 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030603 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030021 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FE3F },
         { .reg = 0x0000D968, .val = 0x00004002 },
         { .reg = 0x0000D96C, .val = 0x0000F1FF },
         { .reg = 0x0000D970, .val = 0x00000022 },
         { .reg = 0x0000D974, .val = 0x0000FFF8 },
         { .reg = 0x0000D978, .val = 0x00000102 },
         { .reg = 0x0000D97C, .val = 0x0000FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext195__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext195__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext195__avg_gpu_core_frequency__max,acmgt1__ext195__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1678, 24, percentage_max_float,acmgt1__ext195__xve_multiple_pipe_active_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1679, 28, percentage_max_float,acmgt1__ext195__xve_multiple_pipe_active_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1680, 32, percentage_max_float,acmgt1__ext195__xve_multiple_pipe_active_xecore2_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1681, 36, percentage_max_float,acmgt1__ext195__xve_multiple_pipe_active_xecore3_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext196_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext196";
   query->symbol_name = "Ext196";
   query->guid = "a09b78bb-b10e-4250-84c5-336f839c4e0c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0B902960 },
         { .reg = 0x00009888, .val = 0x0BB02960 },
         { .reg = 0x00009888, .val = 0x0BD02960 },
         { .reg = 0x00009888, .val = 0x0BF02960 },
         { .reg = 0x00009888, .val = 0x079039E0 },
         { .reg = 0x00009888, .val = 0x01900000 },
         { .reg = 0x00009888, .val = 0x03810054 },
         { .reg = 0x00009888, .val = 0x038300A8 },
         { .reg = 0x00009888, .val = 0x01840E00 },
         { .reg = 0x00009888, .val = 0x03860054 },
         { .reg = 0x00009888, .val = 0x03870054 },
         { .reg = 0x00009888, .val = 0x05B039E0 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x01A15000 },
         { .reg = 0x00009888, .val = 0x03A10001 },
         { .reg = 0x00009888, .val = 0x01A3A000 },
         { .reg = 0x00009888, .val = 0x03A30002 },
         { .reg = 0x00009888, .val = 0x01A401C0 },
         { .reg = 0x00009888, .val = 0x01A65000 },
         { .reg = 0x00009888, .val = 0x03A60001 },
         { .reg = 0x00009888, .val = 0x01A75000 },
         { .reg = 0x00009888, .val = 0x03A70001 },
         { .reg = 0x00009888, .val = 0x03D039E0 },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x01C10540 },
         { .reg = 0x00009888, .val = 0x01C30A80 },
         { .reg = 0x00009888, .val = 0x01C40038 },
         { .reg = 0x00009888, .val = 0x01C60540 },
         { .reg = 0x00009888, .val = 0x01C70540 },
         { .reg = 0x00009888, .val = 0x01F039E0 },
         { .reg = 0x00009888, .val = 0x01E10015 },
         { .reg = 0x00009888, .val = 0x01E3002A },
         { .reg = 0x00009888, .val = 0x01E40007 },
         { .reg = 0x00009888, .val = 0x01E60015 },
         { .reg = 0x00009888, .val = 0x01E70015 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01070A95 },
         { .reg = 0x00009888, .val = 0x0108F000 },
         { .reg = 0x00009888, .val = 0x030800AB },
         { .reg = 0x00009888, .val = 0x0109003F },
         { .reg = 0x00009888, .val = 0x010A5AAA },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x010101C0 },
         { .reg = 0x00009888, .val = 0x010B5000 },
         { .reg = 0x00009888, .val = 0x030B0001 },
         { .reg = 0x00009888, .val = 0x01020038 },
         { .reg = 0x00009888, .val = 0x010C0540 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030030 },
         { .reg = 0x00009888, .val = 0x50030603 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030021 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext196__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext196__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext196__avg_gpu_core_frequency__max,acmgt1__ext196__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1682, 24, percentage_max_float,acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1683, 28, percentage_max_float,acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1684, 32, percentage_max_float,acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1685, 36, percentage_max_float,acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext197_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext197";
   query->symbol_name = "Ext197";
   query->guid = "8b7e5a75-7734-4d48-bdd7-0adf976b8a89";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C813C00 },
         { .reg = 0x00009888, .val = 0x2CA13C00 },
         { .reg = 0x00009888, .val = 0x2CC13C00 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x0C810DC0 },
         { .reg = 0x00009888, .val = 0x0E810C70 },
         { .reg = 0x00009888, .val = 0x10810CF2 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A800 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x008403E0 },
         { .reg = 0x00009888, .val = 0x00865400 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00875400 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10C37 },
         { .reg = 0x00009888, .val = 0x0AA10CB1 },
         { .reg = 0x00009888, .val = 0x0CA10033 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C37 },
         { .reg = 0x00009888, .val = 0x14C10CB1 },
         { .reg = 0x00009888, .val = 0x16C10033 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA0 },
         { .reg = 0x00009888, .val = 0x00C47C00 },
         { .reg = 0x00009888, .val = 0x02C61550 },
         { .reg = 0x00009888, .val = 0x02C71550 },
         { .reg = 0x00009888, .val = 0x02072AA0 },
         { .reg = 0x00009888, .val = 0x0008ABFF },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009888, .val = 0x00097C00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A2AA5 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B0155 },
         { .reg = 0x00009888, .val = 0x00027C00 },
         { .reg = 0x00009888, .val = 0x020C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00047FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030C00 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030603 },
         { .reg = 0x00009888, .val = 0x4A030030 },
         { .reg = 0x00009888, .val = 0x4C030423 },
         { .reg = 0x00009888, .val = 0x4E030221 },
         { .reg = 0x00009888, .val = 0x50030422 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030021 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext197__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext197__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext197__avg_gpu_core_frequency__max,acmgt1__ext197__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1686, 24, NULL,acmgt1__ext197__gpgpu_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1687, 32, NULL,acmgt1__ext197__gpgpu_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1688, 40, NULL,acmgt1__ext197__gpgpu_dispatch_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext198_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext198";
   query->symbol_name = "Ext198";
   query->guid = "8157717a-d7e3-465e-a6b9-a5a5d4902b49";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE13C00 },
         { .reg = 0x00009888, .val = 0x2D813C00 },
         { .reg = 0x00009888, .val = 0x2DA13C00 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10C37 },
         { .reg = 0x00009888, .val = 0x0AE10CB1 },
         { .reg = 0x00009888, .val = 0x0CE10033 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C37 },
         { .reg = 0x00009888, .val = 0x15810CB1 },
         { .reg = 0x00009888, .val = 0x17810033 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03832AA0 },
         { .reg = 0x00009888, .val = 0x01847C00 },
         { .reg = 0x00009888, .val = 0x03861550 },
         { .reg = 0x00009888, .val = 0x03871550 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0DA10DC0 },
         { .reg = 0x00009888, .val = 0x0FA10C70 },
         { .reg = 0x00009888, .val = 0x11A10CF2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x00037FE0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0108FC00 },
         { .reg = 0x00009888, .val = 0x03082AAF },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A1555 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00047FFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42031000 },
         { .reg = 0x00009888, .val = 0x2A037000 },
         { .reg = 0x00009888, .val = 0x480308E4 },
         { .reg = 0x00009888, .val = 0x4A030E47 },
         { .reg = 0x00009888, .val = 0x4C030004 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x4403294A },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x4603014A },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext198__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext198__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext198__avg_gpu_core_frequency__max,acmgt1__ext198__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1689, 24, NULL,acmgt1__ext198__gpgpu_dispatch_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1690, 32, NULL,acmgt1__ext198__gpgpu_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1691, 40, NULL,acmgt1__ext198__gpgpu_dispatch_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext199_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext199";
   query->symbol_name = "Ext199";
   query->guid = "fc122f7d-c66a-458b-a06c-cee29569262d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DC13C00 },
         { .reg = 0x00009888, .val = 0x2DE13C00 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10C37 },
         { .reg = 0x00009888, .val = 0x0BC10CB1 },
         { .reg = 0x00009888, .val = 0x0DC10033 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x0DE10DC0 },
         { .reg = 0x00009888, .val = 0x0FE10C70 },
         { .reg = 0x00009888, .val = 0x11E10CF2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x010756AA },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000403FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202000A },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030005 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C031400 },
         { .reg = 0x00009888, .val = 0x4E0300A0 },
         { .reg = 0x00009888, .val = 0x5003140A },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x520300A0 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext199__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext199__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext199__avg_gpu_core_frequency__max,acmgt1__ext199__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1692, 24, NULL,acmgt1__ext199__gpgpu_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1693, 32, NULL,acmgt1__ext199__gpgpu_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext200_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext200";
   query->symbol_name = "Ext200";
   query->guid = "80da4065-1cc6-4e17-8594-731e1acc01ef";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1687000F },
         { .reg = 0x00009888, .val = 0x1A87000F },
         { .reg = 0x00009888, .val = 0x1288000F },
         { .reg = 0x00009888, .val = 0x1688000F },
         { .reg = 0x00009888, .val = 0x16A7000F },
         { .reg = 0x00009888, .val = 0x1AA7000F },
         { .reg = 0x00009888, .val = 0x12A8000F },
         { .reg = 0x00009888, .val = 0x16A8000F },
         { .reg = 0x00009888, .val = 0x16C7000F },
         { .reg = 0x00009888, .val = 0x1AC7000F },
         { .reg = 0x00009888, .val = 0x12C8000F },
         { .reg = 0x00009888, .val = 0x16C8000F },
         { .reg = 0x00009888, .val = 0x16E7000F },
         { .reg = 0x00009888, .val = 0x1AE7000F },
         { .reg = 0x00009888, .val = 0x12E8000F },
         { .reg = 0x00009888, .val = 0x16E8000F },
         { .reg = 0x00009888, .val = 0x0083AA00 },
         { .reg = 0x00009888, .val = 0x008400F0 },
         { .reg = 0x00009888, .val = 0x00865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x0C8701D7 },
         { .reg = 0x00009888, .val = 0x00870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x068801D7 },
         { .reg = 0x00009888, .val = 0x00890030 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x02C3AA00 },
         { .reg = 0x00009888, .val = 0x00C4F000 },
         { .reg = 0x00009888, .val = 0x02C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x14C701D7 },
         { .reg = 0x00009888, .val = 0x02C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x0EC801D7 },
         { .reg = 0x00009888, .val = 0x00C93000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x00070055 },
         { .reg = 0x00009888, .val = 0x0207AA00 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x0009F00F },
         { .reg = 0x00009888, .val = 0x000A55AA },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x020C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803062A },
         { .reg = 0x00009888, .val = 0x4A030231 },
         { .reg = 0x00009888, .val = 0x4C030422 },
         { .reg = 0x00009888, .val = 0x4E030261 },
         { .reg = 0x00009888, .val = 0x50030606 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440300E7 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46031080 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext200__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext200__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext200__avg_gpu_core_frequency__max,acmgt1__ext200__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1694, 24, NULL,acmgt1__ext200__slm_access_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1695, 32, NULL,acmgt1__ext200__slm_access_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1696, 40, NULL,acmgt1__ext200__slm_access_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1697, 48, NULL,acmgt1__ext200__slm_access_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext201_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext201";
   query->symbol_name = "Ext201";
   query->guid = "5c664618-1692-4ded-b6bb-a9e17f37250d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1787000F },
         { .reg = 0x00009888, .val = 0x1B87000F },
         { .reg = 0x00009888, .val = 0x1388000F },
         { .reg = 0x00009888, .val = 0x1788000F },
         { .reg = 0x00009888, .val = 0x17A7000F },
         { .reg = 0x00009888, .val = 0x1BA7000F },
         { .reg = 0x00009888, .val = 0x13A8000F },
         { .reg = 0x00009888, .val = 0x17A8000F },
         { .reg = 0x00009888, .val = 0x17C7000F },
         { .reg = 0x00009888, .val = 0x1BC7000F },
         { .reg = 0x00009888, .val = 0x13C8000F },
         { .reg = 0x00009888, .val = 0x17C8000F },
         { .reg = 0x00009888, .val = 0x17E7000F },
         { .reg = 0x00009888, .val = 0x1BE7000F },
         { .reg = 0x00009888, .val = 0x13E8000F },
         { .reg = 0x00009888, .val = 0x17E8000F },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x098701D7 },
         { .reg = 0x00009888, .val = 0x0187000A },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x038801D7 },
         { .reg = 0x00009888, .val = 0x01890003 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0DA701D7 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x07A801D7 },
         { .reg = 0x00009888, .val = 0x01A90030 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x11C701D7 },
         { .reg = 0x00009888, .val = 0x03C7000A },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x0BC801D7 },
         { .reg = 0x00009888, .val = 0x01C90300 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x15E701D7 },
         { .reg = 0x00009888, .val = 0x03E70A00 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0FE801D7 },
         { .reg = 0x00009888, .val = 0x01E93000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030C22 },
         { .reg = 0x00009888, .val = 0x4A030061 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030007 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032884 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C6A },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext201__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext201__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext201__avg_gpu_core_frequency__max,acmgt1__ext201__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1698, 24, NULL,acmgt1__ext201__slm_access_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1699, 32, NULL,acmgt1__ext201__slm_access_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1700, 40, NULL,acmgt1__ext201__slm_access_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1701, 48, NULL,acmgt1__ext201__slm_access_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext202_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext202";
   query->symbol_name = "Ext202";
   query->guid = "671c0d10-0f02-490f-acf6-2d2a88c0bc62";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x1A41000F },
         { .reg = 0x00009888, .val = 0x024100E6 },
         { .reg = 0x00009888, .val = 0x06411C00 },
         { .reg = 0x00009888, .val = 0x08410248 },
         { .reg = 0x00009888, .val = 0x0A4102CA },
         { .reg = 0x00009888, .val = 0x0C41034C },
         { .reg = 0x00009888, .val = 0x0E4103CE },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x02030003 },
         { .reg = 0x00009888, .val = 0x0009AAAA },
         { .reg = 0x00009888, .val = 0x02090002 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext202__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext202__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext202__avg_gpu_core_frequency__max,acmgt1__ext202__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1702, 24, NULL,acmgt1__ext202__gpu_memory_l3_write_sqidi0__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext203_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext203";
   query->symbol_name = "Ext203";
   query->guid = "d1c46c3e-fd18-4ca4-905b-64b95a6f10e8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x1A61000F },
         { .reg = 0x00009888, .val = 0x026100E6 },
         { .reg = 0x00009888, .val = 0x06611C00 },
         { .reg = 0x00009888, .val = 0x08610248 },
         { .reg = 0x00009888, .val = 0x0A6102CA },
         { .reg = 0x00009888, .val = 0x0C61034C },
         { .reg = 0x00009888, .val = 0x0E6103CE },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x02030003 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x02090003 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext203__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext203__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext203__avg_gpu_core_frequency__max,acmgt1__ext203__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1703, 24, NULL,acmgt1__ext203__gpu_memory_l3_write_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext204_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext204";
   query->symbol_name = "Ext204";
   query->guid = "4e426fcb-9591-42a4-9b9a-7207d548bc0b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04858240 },
         { .reg = 0x00009888, .val = 0x06850B28 },
         { .reg = 0x00009888, .val = 0x088508A6 },
         { .reg = 0x00009888, .val = 0x0A850BAA },
         { .reg = 0x00009888, .val = 0x10850BEB },
         { .reg = 0x00009888, .val = 0x128509E3 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext204__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext204__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext204__avg_gpu_core_frequency__max,acmgt1__ext204__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1704, 24, NULL,acmgt1__ext204__rt_instance_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1705, 32, NULL,acmgt1__ext204__rt_internal_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1706, 40, NULL,acmgt1__ext204__rt_traversal_step_ray_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext205_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext205";
   query->symbol_name = "Ext205";
   query->guid = "12aa9868-f7c6-4c8d-80fe-cc1605608ef1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A58240 },
         { .reg = 0x00009888, .val = 0x06A50B28 },
         { .reg = 0x00009888, .val = 0x08A508A6 },
         { .reg = 0x00009888, .val = 0x0AA50BAA },
         { .reg = 0x00009888, .val = 0x10A50BEB },
         { .reg = 0x00009888, .val = 0x12A509E3 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AA00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext205__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext205__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext205__avg_gpu_core_frequency__max,acmgt1__ext205__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1707, 24, NULL,acmgt1__ext205__rt_instance_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1708, 32, NULL,acmgt1__ext205__rt_internal_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1709, 40, NULL,acmgt1__ext205__rt_traversal_step_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext206_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext206";
   query->symbol_name = "Ext206";
   query->guid = "7a64382c-70d1-41c4-a1e9-28a8bcb4785a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C58240 },
         { .reg = 0x00009888, .val = 0x06C50B28 },
         { .reg = 0x00009888, .val = 0x08C508A6 },
         { .reg = 0x00009888, .val = 0x0AC50BAA },
         { .reg = 0x00009888, .val = 0x10C50BEB },
         { .reg = 0x00009888, .val = 0x12C509E3 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AA00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AA00 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext206__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext206__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext206__avg_gpu_core_frequency__max,acmgt1__ext206__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1710, 24, NULL,acmgt1__ext206__rt_instance_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1711, 32, NULL,acmgt1__ext206__rt_internal_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1712, 40, NULL,acmgt1__ext206__rt_traversal_step_ray_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext207_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext207";
   query->symbol_name = "Ext207";
   query->guid = "2fa63ea7-c2d9-40fc-b9d5-74cf4a7a3761";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E58240 },
         { .reg = 0x00009888, .val = 0x06E50B28 },
         { .reg = 0x00009888, .val = 0x08E508A6 },
         { .reg = 0x00009888, .val = 0x0AE50BAA },
         { .reg = 0x00009888, .val = 0x10E50BEB },
         { .reg = 0x00009888, .val = 0x12E509E3 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext207__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext207__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext207__avg_gpu_core_frequency__max,acmgt1__ext207__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1713, 24, NULL,acmgt1__ext207__rt_instance_node_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1714, 32, NULL,acmgt1__ext207__rt_internal_node_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1715, 40, NULL,acmgt1__ext207__rt_traversal_step_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext208_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext208";
   query->symbol_name = "Ext208";
   query->guid = "c26befd3-0199-4b5a-9768-963eded47ddc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05858240 },
         { .reg = 0x00009888, .val = 0x07850B28 },
         { .reg = 0x00009888, .val = 0x098508A6 },
         { .reg = 0x00009888, .val = 0x0B850BAA },
         { .reg = 0x00009888, .val = 0x11850BEB },
         { .reg = 0x00009888, .val = 0x138509E3 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AA00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext208__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext208__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext208__avg_gpu_core_frequency__max,acmgt1__ext208__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1716, 24, NULL,acmgt1__ext208__rt_instance_node_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1717, 32, NULL,acmgt1__ext208__rt_internal_node_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1718, 40, NULL,acmgt1__ext208__rt_traversal_step_ray_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext209_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext209";
   query->symbol_name = "Ext209";
   query->guid = "6ac62a5e-3593-4f68-90c1-452cbc83af7b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A58240 },
         { .reg = 0x00009888, .val = 0x07A50B28 },
         { .reg = 0x00009888, .val = 0x09A508A6 },
         { .reg = 0x00009888, .val = 0x0BA50BAA },
         { .reg = 0x00009888, .val = 0x11A50BEB },
         { .reg = 0x00009888, .val = 0x13A509E3 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009888, .val = 0x0101F0FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext209__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext209__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext209__avg_gpu_core_frequency__max,acmgt1__ext209__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1719, 24, NULL,acmgt1__ext209__rt_instance_node_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1720, 32, NULL,acmgt1__ext209__rt_internal_node_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1721, 40, NULL,acmgt1__ext209__rt_traversal_step_ray_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext210_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext210";
   query->symbol_name = "Ext210";
   query->guid = "869238af-0548-47ba-9703-fb4d12825f89";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C58240 },
         { .reg = 0x00009888, .val = 0x07C50B28 },
         { .reg = 0x00009888, .val = 0x09C508A6 },
         { .reg = 0x00009888, .val = 0x0BC50BAA },
         { .reg = 0x00009888, .val = 0x11C50BEB },
         { .reg = 0x00009888, .val = 0x13C509E3 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AA00 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009888, .val = 0x0102F0FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext210__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext210__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext210__avg_gpu_core_frequency__max,acmgt1__ext210__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1722, 24, NULL,acmgt1__ext210__rt_instance_node_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1723, 32, NULL,acmgt1__ext210__rt_internal_node_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1724, 40, NULL,acmgt1__ext210__rt_traversal_step_ray_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext211_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext211";
   query->symbol_name = "Ext211";
   query->guid = "1986e401-2a47-4ced-be1e-1412f795388f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E58240 },
         { .reg = 0x00009888, .val = 0x07E50B28 },
         { .reg = 0x00009888, .val = 0x09E508A6 },
         { .reg = 0x00009888, .val = 0x0BE50BAA },
         { .reg = 0x00009888, .val = 0x11E50BEB },
         { .reg = 0x00009888, .val = 0x13E509E3 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075500 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext211__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext211__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext211__avg_gpu_core_frequency__max,acmgt1__ext211__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1725, 24, NULL,acmgt1__ext211__rt_instance_node_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1726, 32, NULL,acmgt1__ext211__rt_internal_node_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1727, 40, NULL,acmgt1__ext211__rt_traversal_step_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext212_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext212";
   query->symbol_name = "Ext212";
   query->guid = "61f0e78f-0095-4595-993c-0d2a7b474f05";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04859A70 },
         { .reg = 0x00009888, .val = 0x06850925 },
         { .reg = 0x00009888, .val = 0x088508A3 },
         { .reg = 0x00009888, .val = 0x0A850821 },
         { .reg = 0x00009888, .val = 0x0C850BAF },
         { .reg = 0x00009888, .val = 0x0E850B2D },
         { .reg = 0x00009888, .val = 0x10850AAB },
         { .reg = 0x00009888, .val = 0x12850A29 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AAAA },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext212__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext212__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext212__avg_gpu_core_frequency__max,acmgt1__ext212__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1728, 24, NULL,acmgt1__ext212__rt_quad_leaf_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1729, 32, NULL,acmgt1__ext212__rt_procedural_node_ray_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext213_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext213";
   query->symbol_name = "Ext213";
   query->guid = "aac878c4-c131-4e46-a022-673b0c0f6adf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A59A70 },
         { .reg = 0x00009888, .val = 0x06A50925 },
         { .reg = 0x00009888, .val = 0x08A508A3 },
         { .reg = 0x00009888, .val = 0x0AA50821 },
         { .reg = 0x00009888, .val = 0x0CA50BAF },
         { .reg = 0x00009888, .val = 0x0EA50B2D },
         { .reg = 0x00009888, .val = 0x10A50AAB },
         { .reg = 0x00009888, .val = 0x12A50A29 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AAAA },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext213__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext213__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext213__avg_gpu_core_frequency__max,acmgt1__ext213__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1730, 24, NULL,acmgt1__ext213__rt_quad_leaf_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1731, 32, NULL,acmgt1__ext213__rt_procedural_node_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext214_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext214";
   query->symbol_name = "Ext214";
   query->guid = "02fc686b-6061-4224-957b-0c80f4fb5973";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C59A70 },
         { .reg = 0x00009888, .val = 0x06C50925 },
         { .reg = 0x00009888, .val = 0x08C508A3 },
         { .reg = 0x00009888, .val = 0x0AC50821 },
         { .reg = 0x00009888, .val = 0x0CC50BAF },
         { .reg = 0x00009888, .val = 0x0EC50B2D },
         { .reg = 0x00009888, .val = 0x10C50AAB },
         { .reg = 0x00009888, .val = 0x12C50A29 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AAAA },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext214__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext214__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext214__avg_gpu_core_frequency__max,acmgt1__ext214__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1732, 24, NULL,acmgt1__ext214__rt_quad_leaf_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1733, 32, NULL,acmgt1__ext214__rt_procedural_node_ray_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext215_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext215";
   query->symbol_name = "Ext215";
   query->guid = "6965f87c-43a9-437b-9bfb-78e30f504806";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E59A70 },
         { .reg = 0x00009888, .val = 0x06E50925 },
         { .reg = 0x00009888, .val = 0x08E508A3 },
         { .reg = 0x00009888, .val = 0x0AE50821 },
         { .reg = 0x00009888, .val = 0x0CE50BAF },
         { .reg = 0x00009888, .val = 0x0EE50B2D },
         { .reg = 0x00009888, .val = 0x10E50AAB },
         { .reg = 0x00009888, .val = 0x12E50A29 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AAAA },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext215__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext215__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext215__avg_gpu_core_frequency__max,acmgt1__ext215__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1734, 24, NULL,acmgt1__ext215__rt_quad_leaf_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1735, 32, NULL,acmgt1__ext215__rt_procedural_node_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext216_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext216";
   query->symbol_name = "Ext216";
   query->guid = "834f9ddb-0ef2-47a8-bcf3-871cf2b5634e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05859A70 },
         { .reg = 0x00009888, .val = 0x07850925 },
         { .reg = 0x00009888, .val = 0x098508A3 },
         { .reg = 0x00009888, .val = 0x0B850821 },
         { .reg = 0x00009888, .val = 0x0D850BAF },
         { .reg = 0x00009888, .val = 0x0F850B2D },
         { .reg = 0x00009888, .val = 0x11850AAB },
         { .reg = 0x00009888, .val = 0x13850A29 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext216__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext216__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext216__avg_gpu_core_frequency__max,acmgt1__ext216__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1736, 24, NULL,acmgt1__ext216__rt_quad_leaf_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1737, 32, NULL,acmgt1__ext216__rt_procedural_node_ray_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext217_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext217";
   query->symbol_name = "Ext217";
   query->guid = "dd1c62fd-8d41-4f1d-a980-95eba5b62d3d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A59A70 },
         { .reg = 0x00009888, .val = 0x07A50925 },
         { .reg = 0x00009888, .val = 0x09A508A3 },
         { .reg = 0x00009888, .val = 0x0BA50821 },
         { .reg = 0x00009888, .val = 0x0DA50BAF },
         { .reg = 0x00009888, .val = 0x0FA50B2D },
         { .reg = 0x00009888, .val = 0x11A50AAB },
         { .reg = 0x00009888, .val = 0x13A50A29 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext217__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext217__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext217__avg_gpu_core_frequency__max,acmgt1__ext217__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1738, 24, NULL,acmgt1__ext217__rt_quad_leaf_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1739, 32, NULL,acmgt1__ext217__rt_procedural_node_ray_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext218_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext218";
   query->symbol_name = "Ext218";
   query->guid = "1a1e9195-858b-47aa-8f1c-c66eea6efbb9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C59A70 },
         { .reg = 0x00009888, .val = 0x07C50925 },
         { .reg = 0x00009888, .val = 0x09C508A3 },
         { .reg = 0x00009888, .val = 0x0BC50821 },
         { .reg = 0x00009888, .val = 0x0DC50BAF },
         { .reg = 0x00009888, .val = 0x0FC50B2D },
         { .reg = 0x00009888, .val = 0x11C50AAB },
         { .reg = 0x00009888, .val = 0x13C50A29 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext218__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext218__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext218__avg_gpu_core_frequency__max,acmgt1__ext218__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1740, 24, NULL,acmgt1__ext218__rt_quad_leaf_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1741, 32, NULL,acmgt1__ext218__rt_procedural_node_ray_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext219_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext219";
   query->symbol_name = "Ext219";
   query->guid = "a75e98da-d723-42d0-8cd2-c4dc704e6aa1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E59A70 },
         { .reg = 0x00009888, .val = 0x07E50925 },
         { .reg = 0x00009888, .val = 0x09E508A3 },
         { .reg = 0x00009888, .val = 0x0BE50821 },
         { .reg = 0x00009888, .val = 0x0DE50BAF },
         { .reg = 0x00009888, .val = 0x0FE50B2D },
         { .reg = 0x00009888, .val = 0x11E50AAB },
         { .reg = 0x00009888, .val = 0x13E50A29 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext219__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext219__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext219__avg_gpu_core_frequency__max,acmgt1__ext219__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1742, 24, NULL,acmgt1__ext219__rt_quad_leaf_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1743, 32, NULL,acmgt1__ext219__rt_procedural_node_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext220_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext220";
   query->symbol_name = "Ext220";
   query->guid = "440ba901-38f7-495d-986b-486534274741";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x14850000 },
         { .reg = 0x00009888, .val = 0x14A50000 },
         { .reg = 0x00009888, .val = 0x14C50000 },
         { .reg = 0x00009888, .val = 0x14E50000 },
         { .reg = 0x00009888, .val = 0x02850002 },
         { .reg = 0x00009888, .val = 0x10850083 },
         { .reg = 0x00009888, .val = 0x12850001 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x02A50002 },
         { .reg = 0x00009888, .val = 0x0CA50083 },
         { .reg = 0x00009888, .val = 0x0EA50001 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A600AA },
         { .reg = 0x00009888, .val = 0x02C50002 },
         { .reg = 0x00009888, .val = 0x08C50083 },
         { .reg = 0x00009888, .val = 0x0AC50001 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AA00 },
         { .reg = 0x00009888, .val = 0x02E50002 },
         { .reg = 0x00009888, .val = 0x04E50830 },
         { .reg = 0x00009888, .val = 0x06E50001 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E600AA },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext220__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext220__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext220__avg_gpu_core_frequency__max,acmgt1__ext220__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1744, 24, NULL,acmgt1__ext220__rt_bvh_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1745, 32, NULL,acmgt1__ext220__rt_bvh_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1746, 40, NULL,acmgt1__ext220__rt_bvh_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1747, 48, NULL,acmgt1__ext220__rt_bvh_cache_miss_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext221_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext221";
   query->symbol_name = "Ext221";
   query->guid = "6d047d05-95ca-46b4-aac3-a7b055b8fd15";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x15850000 },
         { .reg = 0x00009888, .val = 0x15A50000 },
         { .reg = 0x00009888, .val = 0x15C50000 },
         { .reg = 0x00009888, .val = 0x15E50000 },
         { .reg = 0x00009888, .val = 0x03850002 },
         { .reg = 0x00009888, .val = 0x11850083 },
         { .reg = 0x00009888, .val = 0x13850001 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x03A50002 },
         { .reg = 0x00009888, .val = 0x0DA50083 },
         { .reg = 0x00009888, .val = 0x0FA50001 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600AA },
         { .reg = 0x00009888, .val = 0x03C50002 },
         { .reg = 0x00009888, .val = 0x09C50083 },
         { .reg = 0x00009888, .val = 0x0BC50001 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AA00 },
         { .reg = 0x00009888, .val = 0x03E50002 },
         { .reg = 0x00009888, .val = 0x05E50830 },
         { .reg = 0x00009888, .val = 0x07E50001 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E600AA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x4803140A },
         { .reg = 0x00009888, .val = 0x4A0300A0 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030600 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030863 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22031000 },
         { .reg = 0x00009888, .val = 0x46030842 },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext221__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext221__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext221__avg_gpu_core_frequency__max,acmgt1__ext221__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1748, 24, NULL,acmgt1__ext221__rt_bvh_cache_miss_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1749, 32, NULL,acmgt1__ext221__rt_bvh_cache_miss_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1750, 40, NULL,acmgt1__ext221__rt_bvh_cache_miss_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1751, 48, NULL,acmgt1__ext221__rt_bvh_cache_miss_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext222_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext222";
   query->symbol_name = "Ext222";
   query->guid = "a338ef12-c1bf-45f8-8c0b-084fa99376c8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x08870010 },
         { .reg = 0x00009888, .val = 0x0087000A },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x02880010 },
         { .reg = 0x00009888, .val = 0x00890003 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0CA70010 },
         { .reg = 0x00009888, .val = 0x00A70A00 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x06A80010 },
         { .reg = 0x00009888, .val = 0x00A90030 },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x10C70010 },
         { .reg = 0x00009888, .val = 0x02C7000A },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x0AC80010 },
         { .reg = 0x00009888, .val = 0x00C90300 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x14E70010 },
         { .reg = 0x00009888, .val = 0x02E70A00 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0EE80010 },
         { .reg = 0x00009888, .val = 0x00E93000 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030C22 },
         { .reg = 0x00009888, .val = 0x4A030061 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030007 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032884 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C6A },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext222__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext222__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext222__avg_gpu_core_frequency__max,acmgt1__ext222__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1752, 24, NULL,acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1753, 32, NULL,acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1754, 40, NULL,acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1755, 48, NULL,acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext223_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext223";
   query->symbol_name = "Ext223";
   query->guid = "2684ee0f-2950-4445-939a-549f07d3370a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x09870010 },
         { .reg = 0x00009888, .val = 0x0187000A },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x03880010 },
         { .reg = 0x00009888, .val = 0x01890003 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0DA70010 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x07A80010 },
         { .reg = 0x00009888, .val = 0x01A90030 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x11C70010 },
         { .reg = 0x00009888, .val = 0x03C7000A },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x0BC80010 },
         { .reg = 0x00009888, .val = 0x01C90300 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x15E70010 },
         { .reg = 0x00009888, .val = 0x03E70A00 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0FE80010 },
         { .reg = 0x00009888, .val = 0x01E93000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x42030800 },
         { .reg = 0x00009888, .val = 0x2A031000 },
         { .reg = 0x00009888, .val = 0x48030C22 },
         { .reg = 0x00009888, .val = 0x4A030061 },
         { .reg = 0x00009888, .val = 0x4C030603 },
         { .reg = 0x00009888, .val = 0x4E030070 },
         { .reg = 0x00009888, .val = 0x50030007 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032884 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C6A },
         { .reg = 0x00009888, .val = 0x24031000 },
         { .reg = 0x00009888, .val = 0x28031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext223__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext223__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext223__avg_gpu_core_frequency__max,acmgt1__ext223__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1756, 24, NULL,acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1757, 32, NULL,acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1758, 40, NULL,acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1759, 48, NULL,acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext224_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext224";
   query->symbol_name = "Ext224";
   query->guid = "e1de83dc-4fb2-4e1a-852d-9c5e49bf45db";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x12030012 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02042000 },
         { .reg = 0x00009888, .val = 0x02051000 },
         { .reg = 0x00009888, .val = 0x12080480 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004C000 },
         { .reg = 0x00009888, .val = 0x0202A000 },
         { .reg = 0x00009888, .val = 0x02035000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x46032800 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext224__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext224__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext224__avg_gpu_core_frequency__max,acmgt1__ext224__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1760, 24, percentage_max_float,acmgt1__ext224__color_pipe_cache_latency2_stall_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1761, 28, percentage_max_float,acmgt1__ext224__color_pipe_cache_latency2_stall_l3_node1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext225_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext225";
   query->symbol_name = "Ext225";
   query->guid = "81beafd2-8d1e-46bc-96c0-7f914522a760";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203005F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440300A0 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030005 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext225__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext225__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext225__avg_gpu_core_frequency__max,acmgt1__ext225__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1762, 24, NULL,acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext226_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext226";
   query->symbol_name = "Ext226";
   query->guid = "e299ef7e-7be1-4554-a5c7-e64d36be98e6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203003F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext226__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext226__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext226__avg_gpu_core_frequency__max,acmgt1__ext226__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1763, 24, NULL,acmgt1__ext226__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext227_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext227";
   query->symbol_name = "Ext227";
   query->guid = "e9d1019b-205c-4d1e-a2a7-fd7708a6ad91";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203005F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x440300A0 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030005 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext227__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext227__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext227__avg_gpu_core_frequency__max,acmgt1__ext227__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1764, 24, NULL,acmgt1__ext227__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext228_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext228";
   query->symbol_name = "Ext228";
   query->guid = "ccf8706c-40ea-40a6-ab4c-47e5b32a1485";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x3C036020 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x06034000 },
         { .reg = 0x00009888, .val = 0x08030005 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x14030EC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031111 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x5203003F },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x2203F000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext228__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext228__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext228__avg_gpu_core_frequency__max,acmgt1__ext228__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1765, 24, NULL,acmgt1__ext228__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext229_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext229";
   query->symbol_name = "Ext229";
   query->guid = "2ebb4747-7eb7-4a65-96f8-6a57131a5e82";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext229__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext229__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext229__avg_gpu_core_frequency__max,acmgt1__ext229__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1766, 24, NULL,acmgt1__ext229__slm_bank_conflict_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext230_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext230";
   query->symbol_name = "Ext230";
   query->guid = "baaa8d7e-40b7-4abd-991a-d71265437230";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18A914C0 },
         { .reg = 0x00009888, .val = 0x1EA900A6 },
         { .reg = 0x00009888, .val = 0x22A91800 },
         { .reg = 0x00009888, .val = 0x24A90005 },
         { .reg = 0x00009888, .val = 0x28A914C0 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A90C31 },
         { .reg = 0x00009888, .val = 0x08A90FBF },
         { .reg = 0x00009888, .val = 0x0AA90821 },
         { .reg = 0x00009888, .val = 0x0CA90BAF },
         { .reg = 0x00009888, .val = 0x0EA90411 },
         { .reg = 0x00009888, .val = 0x10A9079F },
         { .reg = 0x00009888, .val = 0x12A90001 },
         { .reg = 0x00009888, .val = 0x14A9038F },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext230__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext230__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext230__avg_gpu_core_frequency__max,acmgt1__ext230__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1767, 24, NULL,acmgt1__ext230__slm_bank_conflict_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext231_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext231";
   query->symbol_name = "Ext231";
   query->guid = "a57ee736-e6ab-4e8b-a719-3a63d7d20f34";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18C914C0 },
         { .reg = 0x00009888, .val = 0x1EC900A6 },
         { .reg = 0x00009888, .val = 0x22C91800 },
         { .reg = 0x00009888, .val = 0x24C90005 },
         { .reg = 0x00009888, .val = 0x28C914C0 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C90C31 },
         { .reg = 0x00009888, .val = 0x08C90FBF },
         { .reg = 0x00009888, .val = 0x0AC90821 },
         { .reg = 0x00009888, .val = 0x0CC90BAF },
         { .reg = 0x00009888, .val = 0x0EC90411 },
         { .reg = 0x00009888, .val = 0x10C9079F },
         { .reg = 0x00009888, .val = 0x12C90001 },
         { .reg = 0x00009888, .val = 0x14C9038F },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext231__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext231__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext231__avg_gpu_core_frequency__max,acmgt1__ext231__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1768, 24, NULL,acmgt1__ext231__slm_bank_conflict_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext232_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext232";
   query->symbol_name = "Ext232";
   query->guid = "c33082a0-ae0d-4679-adbc-9566c75ffe6a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext232__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext232__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext232__avg_gpu_core_frequency__max,acmgt1__ext232__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1769, 24, NULL,acmgt1__ext232__slm_bank_conflict_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext233_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext233";
   query->symbol_name = "Ext233";
   query->guid = "3381cf54-6e4f-48b1-81c9-d5cfd542d316";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext233__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext233__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext233__avg_gpu_core_frequency__max,acmgt1__ext233__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1770, 24, NULL,acmgt1__ext233__slm_bank_conflict_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext234_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext234";
   query->symbol_name = "Ext234";
   query->guid = "b7f1e445-7aaa-4fe3-a7f1-53fe57e1a7c8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19A914C0 },
         { .reg = 0x00009888, .val = 0x1FA900A6 },
         { .reg = 0x00009888, .val = 0x23A91800 },
         { .reg = 0x00009888, .val = 0x25A90005 },
         { .reg = 0x00009888, .val = 0x29A914C0 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A90C31 },
         { .reg = 0x00009888, .val = 0x09A90FBF },
         { .reg = 0x00009888, .val = 0x0BA90821 },
         { .reg = 0x00009888, .val = 0x0DA90BAF },
         { .reg = 0x00009888, .val = 0x0FA90411 },
         { .reg = 0x00009888, .val = 0x11A9079F },
         { .reg = 0x00009888, .val = 0x13A90001 },
         { .reg = 0x00009888, .val = 0x15A9038F },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext234__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext234__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext234__avg_gpu_core_frequency__max,acmgt1__ext234__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1771, 24, NULL,acmgt1__ext234__slm_bank_conflict_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext235_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext235";
   query->symbol_name = "Ext235";
   query->guid = "7e29d0d3-2ec5-4716-90d4-917c7b3cbdca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19C914C0 },
         { .reg = 0x00009888, .val = 0x1FC900A6 },
         { .reg = 0x00009888, .val = 0x23C91800 },
         { .reg = 0x00009888, .val = 0x25C90005 },
         { .reg = 0x00009888, .val = 0x29C914C0 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C90C31 },
         { .reg = 0x00009888, .val = 0x09C90FBF },
         { .reg = 0x00009888, .val = 0x0BC90821 },
         { .reg = 0x00009888, .val = 0x0DC90BAF },
         { .reg = 0x00009888, .val = 0x0FC90411 },
         { .reg = 0x00009888, .val = 0x11C9079F },
         { .reg = 0x00009888, .val = 0x13C90001 },
         { .reg = 0x00009888, .val = 0x15C9038F },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext235__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext235__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext235__avg_gpu_core_frequency__max,acmgt1__ext235__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1772, 24, NULL,acmgt1__ext235__slm_bank_conflict_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext236_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext236";
   query->symbol_name = "Ext236";
   query->guid = "ae42189a-f2a1-4494-84b0-f2d506decbc1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext236__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext236__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext236__avg_gpu_core_frequency__max,acmgt1__ext236__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1773, 24, NULL,acmgt1__ext236__slm_bank_conflict_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext237_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext237";
   query->symbol_name = "Ext237";
   query->guid = "6f65878e-1b6b-4a3b-8107-837073903643";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2000 },
         { .reg = 0x00009888, .val = 0x114B2080 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2000 },
         { .reg = 0x00009888, .val = 0x114C2002 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0D0B0080 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0F2B0080 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0080 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0D0C0002 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x0F2C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x136C0002 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020C00 },
         { .reg = 0x00009888, .val = 0x02032100 },
         { .reg = 0x00009888, .val = 0x0204E600 },
         { .reg = 0x00009888, .val = 0x02055508 },
         { .reg = 0x00009888, .val = 0x02060021 },
         { .reg = 0x00009888, .val = 0x00070500 },
         { .reg = 0x00009888, .val = 0x0208AAD9 },
         { .reg = 0x00009888, .val = 0x00090500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x50030200 },
         { .reg = 0x00009888, .val = 0x52030070 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030141 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46031001 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext237__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext237__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext237__avg_gpu_core_frequency__max,acmgt1__ext237__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1774, 24, NULL,acmgt1__ext237__l3_miss_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1775, 32, NULL,acmgt1__ext237__l3_miss_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1776, 40, NULL,acmgt1__ext237__l3_miss_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1777, 48, NULL,acmgt1__ext237__l3_miss_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1778, 56, NULL,acmgt1__ext237__l3_miss_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1779, 64, NULL,acmgt1__ext237__l3_miss_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1780, 72, NULL,acmgt1__ext237__l3_miss_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1781, 80, NULL,acmgt1__ext237__l3_miss_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext238_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Ext238";
   query->symbol_name = "Ext238";
   query->guid = "a1c8b5b0-7b8c-4dbc-a4dd-eb29f8055ab0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x20810011 },
         { .reg = 0x00009888, .val = 0x20A10011 },
         { .reg = 0x00009888, .val = 0x20C10011 },
         { .reg = 0x00009888, .val = 0x20E10011 },
         { .reg = 0x00009888, .val = 0x21810011 },
         { .reg = 0x00009888, .val = 0x21A10011 },
         { .reg = 0x00009888, .val = 0x21C10011 },
         { .reg = 0x00009888, .val = 0x21E10011 },
         { .reg = 0x00009888, .val = 0x1606014C },
         { .reg = 0x00009888, .val = 0x1706014C },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x10810016 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02830002 },
         { .reg = 0x00009888, .val = 0x00840100 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x02870001 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x10A10580 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A30008 },
         { .reg = 0x00009888, .val = 0x00A40200 },
         { .reg = 0x00009888, .val = 0x02A60004 },
         { .reg = 0x00009888, .val = 0x02A70004 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x12C10016 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30020 },
         { .reg = 0x00009888, .val = 0x00C40400 },
         { .reg = 0x00009888, .val = 0x02C60010 },
         { .reg = 0x00009888, .val = 0x02C70010 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x12E10580 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30080 },
         { .reg = 0x00009888, .val = 0x00E40800 },
         { .reg = 0x00009888, .val = 0x02E60040 },
         { .reg = 0x00009888, .val = 0x02E70040 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x15810016 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830200 },
         { .reg = 0x00009888, .val = 0x01841000 },
         { .reg = 0x00009888, .val = 0x03860100 },
         { .reg = 0x00009888, .val = 0x03870100 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x15A10580 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30800 },
         { .reg = 0x00009888, .val = 0x01A42000 },
         { .reg = 0x00009888, .val = 0x03A60400 },
         { .reg = 0x00009888, .val = 0x03A70400 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x17C10016 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32000 },
         { .reg = 0x00009888, .val = 0x01C44000 },
         { .reg = 0x00009888, .val = 0x03C61000 },
         { .reg = 0x00009888, .val = 0x03C71000 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x17E10580 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E38000 },
         { .reg = 0x00009888, .val = 0x01E48000 },
         { .reg = 0x00009888, .val = 0x03E64000 },
         { .reg = 0x00009888, .val = 0x03E74000 },
         { .reg = 0x00009888, .val = 0x0003F00C },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x04060E00 },
         { .reg = 0x00009888, .val = 0x06060008 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x02070060 },
         { .reg = 0x00009888, .val = 0x000800F5 },
         { .reg = 0x00009888, .val = 0x0208FF0E },
         { .reg = 0x00009888, .val = 0x00090C00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A55A5 },
         { .reg = 0x00009888, .val = 0x0001F20C },
         { .reg = 0x00009888, .val = 0x000B00A0 },
         { .reg = 0x00009888, .val = 0x020BAA04 },
         { .reg = 0x00009888, .val = 0x00020400 },
         { .reg = 0x00009888, .val = 0x020C0010 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x070601C0 },
         { .reg = 0x00009888, .val = 0x09060008 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03076000 },
         { .reg = 0x00009888, .val = 0x01080050 },
         { .reg = 0x00009888, .val = 0x03080E00 },
         { .reg = 0x00009888, .val = 0x0109C000 },
         { .reg = 0x00009888, .val = 0x010A0050 },
         { .reg = 0x00009888, .val = 0x030AA500 },
         { .reg = 0x00009888, .val = 0x01012000 },
         { .reg = 0x00009888, .val = 0x030B0400 },
         { .reg = 0x00009888, .val = 0x01024000 },
         { .reg = 0x00009888, .val = 0x030C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FF0F },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00030055 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x42035400 },
         { .reg = 0x00009888, .val = 0x2A03F000 },
         { .reg = 0x00009888, .val = 0x480304F5 },
         { .reg = 0x00009888, .val = 0x4A030027 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x500314E0 },
         { .reg = 0x00009888, .val = 0x52030007 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x440308E8 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46032803 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext238__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext238__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext238__avg_gpu_core_frequency__max,acmgt1__ext238__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1782, 24, NULL,acmgt1__ext238__amfs_l3_write_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1783, 32, NULL,acmgt1__ext238__amfs_l3_write_slice1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1784, 40, NULL,acmgt1__ext238__xve_dataport_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1785, 48, NULL,acmgt1__ext238__xve_dataport_fence_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1786, 56, NULL,acmgt1__ext238__xve_dataport_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1787, 64, NULL,acmgt1__ext238__xve_dataport_fence_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1788, 72, NULL,acmgt1__ext238__xve_dataport_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1789, 80, NULL,acmgt1__ext238__xve_dataport_fence_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1790, 88, NULL,acmgt1__ext238__xve_dataport_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1791, 96, NULL,acmgt1__ext238__xve_dataport_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext239_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext239";
   query->symbol_name = "Ext239";
   query->guid = "cc574967-0ba6-4c22-801f-881b3974395a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1A412540 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x1A61000F },
         { .reg = 0x00009888, .val = 0x02410128 },
         { .reg = 0x00009888, .val = 0x06411400 },
         { .reg = 0x00009888, .val = 0x08410288 },
         { .reg = 0x00009888, .val = 0x0A41030B },
         { .reg = 0x00009888, .val = 0x0C41038D },
         { .reg = 0x00009888, .val = 0x0E41000F },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x026100E6 },
         { .reg = 0x00009888, .val = 0x0E610180 },
         { .reg = 0x00009888, .val = 0x10610288 },
         { .reg = 0x00009888, .val = 0x1261030B },
         { .reg = 0x00009888, .val = 0x1461038D },
         { .reg = 0x00009888, .val = 0x1661000F },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0203FFFF },
         { .reg = 0x00009888, .val = 0x0009AAAA },
         { .reg = 0x00009888, .val = 0x0209FFFF },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext239__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext239__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext239__avg_gpu_core_frequency__max,acmgt1__ext239__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1792, 24, NULL,acmgt1__ext239__gpu_memory_l3_read_sqidi0__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext240_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext240";
   query->symbol_name = "Ext240";
   query->guid = "d96495d3-d734-4b58-bf54-ece1a4a1ab09";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x1A41000F },
         { .reg = 0x00009888, .val = 0x1A612540 },
         { .reg = 0x00009888, .val = 0x024100E6 },
         { .reg = 0x00009888, .val = 0x0E410180 },
         { .reg = 0x00009888, .val = 0x10410288 },
         { .reg = 0x00009888, .val = 0x1241030B },
         { .reg = 0x00009888, .val = 0x1441038D },
         { .reg = 0x00009888, .val = 0x1641000F },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610128 },
         { .reg = 0x00009888, .val = 0x06611400 },
         { .reg = 0x00009888, .val = 0x08610288 },
         { .reg = 0x00009888, .val = 0x0A61030B },
         { .reg = 0x00009888, .val = 0x0C61038D },
         { .reg = 0x00009888, .val = 0x0E61000F },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0203FFFF },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x0209AAAA },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext240__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext240__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext240__avg_gpu_core_frequency__max,acmgt1__ext240__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1793, 24, NULL,acmgt1__ext240__gpu_memory_l3_read_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext500_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext500";
   query->symbol_name = "Ext500";
   query->guid = "1c157760-179c-40d1-aa3c-b419f609ea79";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1882000C },
         { .reg = 0x00009888, .val = 0x18A2000C },
         { .reg = 0x00009888, .val = 0x18C2000C },
         { .reg = 0x00009888, .val = 0x18E2000C },
         { .reg = 0x00009888, .val = 0x1982000C },
         { .reg = 0x00009888, .val = 0x19A2000C },
         { .reg = 0x00009888, .val = 0x19C2000C },
         { .reg = 0x00009888, .val = 0x19E2000C },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x0A820006 },
         { .reg = 0x00009888, .val = 0x12820140 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830040 },
         { .reg = 0x00009888, .val = 0x02830100 },
         { .reg = 0x00009888, .val = 0x00841008 },
         { .reg = 0x00009888, .val = 0x00860040 },
         { .reg = 0x00009888, .val = 0x02860100 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20180 },
         { .reg = 0x00009888, .val = 0x14A20005 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30010 },
         { .reg = 0x00009888, .val = 0x02A30400 },
         { .reg = 0x00009888, .val = 0x00A42004 },
         { .reg = 0x00009888, .val = 0x00A60010 },
         { .reg = 0x00009888, .val = 0x02A60400 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20006 },
         { .reg = 0x00009888, .val = 0x14C20140 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30004 },
         { .reg = 0x00009888, .val = 0x02C31000 },
         { .reg = 0x00009888, .val = 0x00C44002 },
         { .reg = 0x00009888, .val = 0x00C60004 },
         { .reg = 0x00009888, .val = 0x02C61000 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x06E20C00 },
         { .reg = 0x00009888, .val = 0x16E20005 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30001 },
         { .reg = 0x00009888, .val = 0x02E34000 },
         { .reg = 0x00009888, .val = 0x00E48001 },
         { .reg = 0x00009888, .val = 0x00E60001 },
         { .reg = 0x00009888, .val = 0x02E64000 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0F820146 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01834000 },
         { .reg = 0x00009888, .val = 0x03830001 },
         { .reg = 0x00009888, .val = 0x01840180 },
         { .reg = 0x00009888, .val = 0x01864000 },
         { .reg = 0x00009888, .val = 0x03860001 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20180 },
         { .reg = 0x00009888, .val = 0x11A20005 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A31000 },
         { .reg = 0x00009888, .val = 0x03A30004 },
         { .reg = 0x00009888, .val = 0x01A40240 },
         { .reg = 0x00009888, .val = 0x01A61000 },
         { .reg = 0x00009888, .val = 0x03A60004 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20006 },
         { .reg = 0x00009888, .val = 0x11C20140 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C30400 },
         { .reg = 0x00009888, .val = 0x03C30010 },
         { .reg = 0x00009888, .val = 0x01C40420 },
         { .reg = 0x00009888, .val = 0x01C60400 },
         { .reg = 0x00009888, .val = 0x03C60010 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0BE20180 },
         { .reg = 0x00009888, .val = 0x13E20005 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E30100 },
         { .reg = 0x00009888, .val = 0x03E30040 },
         { .reg = 0x00009888, .val = 0x01E40810 },
         { .reg = 0x00009888, .val = 0x01E60100 },
         { .reg = 0x00009888, .val = 0x03E60040 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070009 },
         { .reg = 0x00009888, .val = 0x02076000 },
         { .reg = 0x00009888, .val = 0x0008FFB0 },
         { .reg = 0x00009888, .val = 0x02080EFF },
         { .reg = 0x00009888, .val = 0x0009C003 },
         { .reg = 0x00009888, .val = 0x000A555A },
         { .reg = 0x00009888, .val = 0x020AA555 },
         { .reg = 0x00009888, .val = 0x00012FF4 },
         { .reg = 0x00009888, .val = 0x000BAA10 },
         { .reg = 0x00009888, .val = 0x020B04AA },
         { .reg = 0x00009888, .val = 0x00024002 },
         { .reg = 0x00009888, .val = 0x000C0004 },
         { .reg = 0x00009888, .val = 0x020C1000 },
         { .reg = 0x00009888, .val = 0x01070900 },
         { .reg = 0x00009888, .val = 0x03070060 },
         { .reg = 0x00009888, .val = 0x0108B000 },
         { .reg = 0x00009888, .val = 0x0308000E },
         { .reg = 0x00009888, .val = 0x01090C30 },
         { .reg = 0x00009888, .val = 0x010A5A00 },
         { .reg = 0x00009888, .val = 0x030A00A5 },
         { .reg = 0x00009888, .val = 0x01010240 },
         { .reg = 0x00009888, .val = 0x010B1000 },
         { .reg = 0x00009888, .val = 0x030B0004 },
         { .reg = 0x00009888, .val = 0x01020420 },
         { .reg = 0x00009888, .val = 0x010C0400 },
         { .reg = 0x00009888, .val = 0x030C0010 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x42031C00 },
         { .reg = 0x00009888, .val = 0x2A033000 },
         { .reg = 0x00009888, .val = 0x480300E8 },
         { .reg = 0x00009888, .val = 0x4A0300A7 },
         { .reg = 0x00009888, .val = 0x4C03000A },
         { .reg = 0x00009888, .val = 0x4E030230 },
         { .reg = 0x00009888, .val = 0x50030422 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44032940 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x22037000 },
         { .reg = 0x00009888, .val = 0x46031D00 },
         { .reg = 0x00009888, .val = 0x24033000 },
         { .reg = 0x00009888, .val = 0x28037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext500__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext500__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext500__avg_gpu_core_frequency__max,acmgt1__ext500__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1794, 24, NULL,acmgt1__ext500__icache_hit_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1795, 32, NULL,acmgt1__ext500__icache_miss_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1796, 40, NULL,acmgt1__ext500__icache_hit_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1797, 48, NULL,acmgt1__ext500__icache_miss_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1798, 56, NULL,acmgt1__ext500__icache_hit_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1799, 64, NULL,acmgt1__ext500__icache_miss_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1800, 72, NULL,acmgt1__ext500__icache_hit_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1801, 80, NULL,acmgt1__ext500__icache_miss_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1802, 88, NULL,acmgt1__ext500__icache_hit_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1803, 96, NULL,acmgt1__ext500__icache_miss_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1804, 104, NULL,acmgt1__ext500__icache_hit_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1805, 112, NULL,acmgt1__ext500__icache_miss_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1806, 120, NULL,acmgt1__ext500__icache_hit_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1807, 128, NULL,acmgt1__ext500__icache_miss_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1808, 136, NULL,acmgt1__ext500__icache_hit_bank0_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1809, 144, NULL,acmgt1__ext500__icache_miss_bank0_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext501_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext501";
   query->symbol_name = "Ext501";
   query->guid = "06451560-fa04-4f38-b502-e0a096965a64";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18820011 },
         { .reg = 0x00009888, .val = 0x18A20011 },
         { .reg = 0x00009888, .val = 0x18C20011 },
         { .reg = 0x00009888, .val = 0x18E20011 },
         { .reg = 0x00009888, .val = 0x19820011 },
         { .reg = 0x00009888, .val = 0x19A20011 },
         { .reg = 0x00009888, .val = 0x19C20011 },
         { .reg = 0x00009888, .val = 0x19E20011 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x0E820146 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00834000 },
         { .reg = 0x00009888, .val = 0x02830001 },
         { .reg = 0x00009888, .val = 0x00840180 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x0CA20180 },
         { .reg = 0x00009888, .val = 0x10A20005 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A31000 },
         { .reg = 0x00009888, .val = 0x02A30004 },
         { .reg = 0x00009888, .val = 0x00A40240 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A60004 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x0CC20006 },
         { .reg = 0x00009888, .val = 0x10C20140 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30400 },
         { .reg = 0x00009888, .val = 0x02C30010 },
         { .reg = 0x00009888, .val = 0x00C40420 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60010 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20180 },
         { .reg = 0x00009888, .val = 0x12E20005 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30100 },
         { .reg = 0x00009888, .val = 0x02E30040 },
         { .reg = 0x00009888, .val = 0x00E40810 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60040 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820006 },
         { .reg = 0x00009888, .val = 0x13820140 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830040 },
         { .reg = 0x00009888, .val = 0x03830100 },
         { .reg = 0x00009888, .val = 0x01841008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860100 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x09A20180 },
         { .reg = 0x00009888, .val = 0x15A20005 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30010 },
         { .reg = 0x00009888, .val = 0x03A30400 },
         { .reg = 0x00009888, .val = 0x01A42004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60400 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x09C20006 },
         { .reg = 0x00009888, .val = 0x15C20140 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C30004 },
         { .reg = 0x00009888, .val = 0x03C31000 },
         { .reg = 0x00009888, .val = 0x01C44002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C61000 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x07E20C00 },
         { .reg = 0x00009888, .val = 0x17E20005 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E30001 },
         { .reg = 0x00009888, .val = 0x03E34000 },
         { .reg = 0x00009888, .val = 0x01E48001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E64000 },
         { .reg = 0x00009888, .val = 0x0003F00F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070060 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208FF0E },
         { .reg = 0x00009888, .val = 0x00090C30 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A55A5 },
         { .reg = 0x00009888, .val = 0x0001F24F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020BAA04 },
         { .reg = 0x00009888, .val = 0x00020420 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0010 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03076000 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x03080E00 },
         { .reg = 0x00009888, .val = 0x0109C003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030AA500 },
         { .reg = 0x00009888, .val = 0x01012004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0400 },
         { .reg = 0x00009888, .val = 0x01024002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030600 },
         { .reg = 0x00009888, .val = 0x4A030E21 },
         { .reg = 0x00009888, .val = 0x4C031067 },
         { .reg = 0x00009888, .val = 0x4E030E07 },
         { .reg = 0x00009888, .val = 0x500314EA },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030007 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x440308E8 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46032803 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext501__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext501__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext501__avg_gpu_core_frequency__max,acmgt1__ext501__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1810, 24, NULL,acmgt1__ext501__icache_hit_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1811, 32, NULL,acmgt1__ext501__icache_miss_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1812, 40, NULL,acmgt1__ext501__icache_hit_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1813, 48, NULL,acmgt1__ext501__icache_miss_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1814, 56, NULL,acmgt1__ext501__icache_hit_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1815, 64, NULL,acmgt1__ext501__icache_miss_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1816, 72, NULL,acmgt1__ext501__icache_hit_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1817, 80, NULL,acmgt1__ext501__icache_miss_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1818, 88, NULL,acmgt1__ext501__icache_hit_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1819, 96, NULL,acmgt1__ext501__icache_miss_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1820, 104, NULL,acmgt1__ext501__icache_hit_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1821, 112, NULL,acmgt1__ext501__icache_miss_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1822, 120, NULL,acmgt1__ext501__icache_hit_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1823, 128, NULL,acmgt1__ext501__icache_miss_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1824, 136, NULL,acmgt1__ext501__icache_hit_bank1_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1825, 144, NULL,acmgt1__ext501__icache_miss_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext502_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext502";
   query->symbol_name = "Ext502";
   query->guid = "9d21c47c-92e0-4454-b3f1-484f27763e83";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18820016 },
         { .reg = 0x00009888, .val = 0x18A20016 },
         { .reg = 0x00009888, .val = 0x18C20016 },
         { .reg = 0x00009888, .val = 0x18E20016 },
         { .reg = 0x00009888, .val = 0x19820016 },
         { .reg = 0x00009888, .val = 0x19A20016 },
         { .reg = 0x00009888, .val = 0x19C20016 },
         { .reg = 0x00009888, .val = 0x19E20016 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x0E820146 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00834000 },
         { .reg = 0x00009888, .val = 0x02830001 },
         { .reg = 0x00009888, .val = 0x00840180 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x0CA20180 },
         { .reg = 0x00009888, .val = 0x10A20005 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A31000 },
         { .reg = 0x00009888, .val = 0x02A30004 },
         { .reg = 0x00009888, .val = 0x00A40240 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A60004 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x0CC20006 },
         { .reg = 0x00009888, .val = 0x10C20140 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30400 },
         { .reg = 0x00009888, .val = 0x02C30010 },
         { .reg = 0x00009888, .val = 0x00C40420 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60010 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20180 },
         { .reg = 0x00009888, .val = 0x12E20005 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30100 },
         { .reg = 0x00009888, .val = 0x02E30040 },
         { .reg = 0x00009888, .val = 0x00E40810 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60040 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820006 },
         { .reg = 0x00009888, .val = 0x13820140 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830040 },
         { .reg = 0x00009888, .val = 0x03830100 },
         { .reg = 0x00009888, .val = 0x01841008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860100 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x09A20180 },
         { .reg = 0x00009888, .val = 0x15A20005 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30010 },
         { .reg = 0x00009888, .val = 0x03A30400 },
         { .reg = 0x00009888, .val = 0x01A42004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60400 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x09C20006 },
         { .reg = 0x00009888, .val = 0x15C20140 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C30004 },
         { .reg = 0x00009888, .val = 0x03C31000 },
         { .reg = 0x00009888, .val = 0x01C44002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C61000 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x07E20C00 },
         { .reg = 0x00009888, .val = 0x17E20005 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E30001 },
         { .reg = 0x00009888, .val = 0x03E34000 },
         { .reg = 0x00009888, .val = 0x01E48001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E64000 },
         { .reg = 0x00009888, .val = 0x0003F00F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070060 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208FF0E },
         { .reg = 0x00009888, .val = 0x00090C30 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A55A5 },
         { .reg = 0x00009888, .val = 0x0001F24F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020BAA04 },
         { .reg = 0x00009888, .val = 0x00020420 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0010 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03076000 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x03080E00 },
         { .reg = 0x00009888, .val = 0x0109C003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030AA500 },
         { .reg = 0x00009888, .val = 0x01012004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0400 },
         { .reg = 0x00009888, .val = 0x01024002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030600 },
         { .reg = 0x00009888, .val = 0x4A030E21 },
         { .reg = 0x00009888, .val = 0x4C031067 },
         { .reg = 0x00009888, .val = 0x4E030E07 },
         { .reg = 0x00009888, .val = 0x500314EA },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030007 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x440308E8 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46032803 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext502__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext502__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext502__avg_gpu_core_frequency__max,acmgt1__ext502__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1826, 24, NULL,acmgt1__ext502__icache_hit_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1827, 32, NULL,acmgt1__ext502__icache_miss_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1828, 40, NULL,acmgt1__ext502__icache_hit_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1829, 48, NULL,acmgt1__ext502__icache_miss_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1830, 56, NULL,acmgt1__ext502__icache_hit_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1831, 64, NULL,acmgt1__ext502__icache_miss_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1832, 72, NULL,acmgt1__ext502__icache_hit_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1833, 80, NULL,acmgt1__ext502__icache_miss_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1834, 88, NULL,acmgt1__ext502__icache_hit_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1835, 96, NULL,acmgt1__ext502__icache_miss_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1836, 104, NULL,acmgt1__ext502__icache_hit_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1837, 112, NULL,acmgt1__ext502__icache_miss_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1838, 120, NULL,acmgt1__ext502__icache_hit_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1839, 128, NULL,acmgt1__ext502__icache_miss_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1840, 136, NULL,acmgt1__ext502__icache_hit_bank2_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1841, 144, NULL,acmgt1__ext502__icache_miss_bank2_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext503_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext503";
   query->symbol_name = "Ext503";
   query->guid = "3cbb77d0-15f3-4bd0-8db1-5644266d78fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1882001B },
         { .reg = 0x00009888, .val = 0x18A2001B },
         { .reg = 0x00009888, .val = 0x18C2001B },
         { .reg = 0x00009888, .val = 0x18E2001B },
         { .reg = 0x00009888, .val = 0x1982001B },
         { .reg = 0x00009888, .val = 0x19A2001B },
         { .reg = 0x00009888, .val = 0x19C2001B },
         { .reg = 0x00009888, .val = 0x19E2001B },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x0E820146 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00834000 },
         { .reg = 0x00009888, .val = 0x02830001 },
         { .reg = 0x00009888, .val = 0x00840180 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x0CA20180 },
         { .reg = 0x00009888, .val = 0x10A20005 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A31000 },
         { .reg = 0x00009888, .val = 0x02A30004 },
         { .reg = 0x00009888, .val = 0x00A40240 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A60004 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x0CC20006 },
         { .reg = 0x00009888, .val = 0x10C20140 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30400 },
         { .reg = 0x00009888, .val = 0x02C30010 },
         { .reg = 0x00009888, .val = 0x00C40420 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60010 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20180 },
         { .reg = 0x00009888, .val = 0x12E20005 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30100 },
         { .reg = 0x00009888, .val = 0x02E30040 },
         { .reg = 0x00009888, .val = 0x00E40810 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60040 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820006 },
         { .reg = 0x00009888, .val = 0x13820140 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830040 },
         { .reg = 0x00009888, .val = 0x03830100 },
         { .reg = 0x00009888, .val = 0x01841008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860100 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x09A20180 },
         { .reg = 0x00009888, .val = 0x15A20005 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30010 },
         { .reg = 0x00009888, .val = 0x03A30400 },
         { .reg = 0x00009888, .val = 0x01A42004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60400 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x09C20006 },
         { .reg = 0x00009888, .val = 0x15C20140 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C30004 },
         { .reg = 0x00009888, .val = 0x03C31000 },
         { .reg = 0x00009888, .val = 0x01C44002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C61000 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x07E20C00 },
         { .reg = 0x00009888, .val = 0x17E20005 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E30001 },
         { .reg = 0x00009888, .val = 0x03E34000 },
         { .reg = 0x00009888, .val = 0x01E48001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E64000 },
         { .reg = 0x00009888, .val = 0x0003F00F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070060 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208FF0E },
         { .reg = 0x00009888, .val = 0x00090C30 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A55A5 },
         { .reg = 0x00009888, .val = 0x0001F24F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020BAA04 },
         { .reg = 0x00009888, .val = 0x00020420 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0010 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03076000 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x03080E00 },
         { .reg = 0x00009888, .val = 0x0109C003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030AA500 },
         { .reg = 0x00009888, .val = 0x01012004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0400 },
         { .reg = 0x00009888, .val = 0x01024002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42032800 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030600 },
         { .reg = 0x00009888, .val = 0x4A030E21 },
         { .reg = 0x00009888, .val = 0x4C031067 },
         { .reg = 0x00009888, .val = 0x4E030E07 },
         { .reg = 0x00009888, .val = 0x500314EA },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030007 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x440308E8 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46032803 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext503__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext503__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext503__avg_gpu_core_frequency__max,acmgt1__ext503__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1842, 24, NULL,acmgt1__ext503__icache_hit_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1843, 32, NULL,acmgt1__ext503__icache_miss_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1844, 40, NULL,acmgt1__ext503__icache_hit_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1845, 48, NULL,acmgt1__ext503__icache_miss_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1846, 56, NULL,acmgt1__ext503__icache_hit_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1847, 64, NULL,acmgt1__ext503__icache_miss_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1848, 72, NULL,acmgt1__ext503__icache_hit_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1849, 80, NULL,acmgt1__ext503__icache_miss_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1850, 88, NULL,acmgt1__ext503__icache_hit_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1851, 96, NULL,acmgt1__ext503__icache_miss_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1852, 104, NULL,acmgt1__ext503__icache_hit_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1853, 112, NULL,acmgt1__ext503__icache_miss_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1854, 120, NULL,acmgt1__ext503__icache_hit_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1855, 128, NULL,acmgt1__ext503__icache_miss_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1856, 136, NULL,acmgt1__ext503__icache_hit_bank3_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1857, 144, NULL,acmgt1__ext503__icache_miss_bank3_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext508_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext508";
   query->symbol_name = "Ext508";
   query->guid = "e81aaa56-a54b-491f-9803-ed19d2762e13";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870253 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870004 },
         { .reg = 0x00009888, .val = 0x0E870140 },
         { .reg = 0x00009888, .val = 0x108700C4 },
         { .reg = 0x00009888, .val = 0x12870042 },
         { .reg = 0x00009888, .val = 0x148703C0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890387 },
         { .reg = 0x00009888, .val = 0x08890248 },
         { .reg = 0x00009888, .val = 0x0A8902CA },
         { .reg = 0x00009888, .val = 0x0C89034C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext508__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext508__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext508__avg_gpu_core_frequency__max,acmgt1__ext508__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1858, 24, NULL,acmgt1__ext508__slm_byte_read_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1859, 32, NULL,acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext509_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext509";
   query->symbol_name = "Ext509";
   query->guid = "3c10260c-cb15-4474-ab84-c226d54f2974";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A70253 },
         { .reg = 0x00009888, .val = 0x18A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A70004 },
         { .reg = 0x00009888, .val = 0x0EA70140 },
         { .reg = 0x00009888, .val = 0x10A700C4 },
         { .reg = 0x00009888, .val = 0x12A70042 },
         { .reg = 0x00009888, .val = 0x14A703C0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A90054 },
         { .reg = 0x00009888, .val = 0x06A90387 },
         { .reg = 0x00009888, .val = 0x08A90248 },
         { .reg = 0x00009888, .val = 0x0AA902CA },
         { .reg = 0x00009888, .val = 0x0CA9034C },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext509__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext509__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext509__avg_gpu_core_frequency__max,acmgt1__ext509__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1860, 24, NULL,acmgt1__ext509__slm_byte_read_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1861, 32, NULL,acmgt1__ext509__load_store_cache_byte_read_bank0_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext510_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext510";
   query->symbol_name = "Ext510";
   query->guid = "95455b22-bda5-4f6e-86ae-0e500f0b419e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C70253 },
         { .reg = 0x00009888, .val = 0x18C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C70004 },
         { .reg = 0x00009888, .val = 0x0EC70140 },
         { .reg = 0x00009888, .val = 0x10C700C4 },
         { .reg = 0x00009888, .val = 0x12C70042 },
         { .reg = 0x00009888, .val = 0x14C703C0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C90054 },
         { .reg = 0x00009888, .val = 0x06C90387 },
         { .reg = 0x00009888, .val = 0x08C90248 },
         { .reg = 0x00009888, .val = 0x0AC902CA },
         { .reg = 0x00009888, .val = 0x0CC9034C },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext510__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext510__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext510__avg_gpu_core_frequency__max,acmgt1__ext510__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1862, 24, NULL,acmgt1__ext510__slm_byte_read_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1863, 32, NULL,acmgt1__ext510__load_store_cache_byte_read_bank0_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext511_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext511";
   query->symbol_name = "Ext511";
   query->guid = "95137f7b-f35e-4bef-9949-3c6681813bb9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E70253 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70004 },
         { .reg = 0x00009888, .val = 0x0EE70140 },
         { .reg = 0x00009888, .val = 0x10E700C4 },
         { .reg = 0x00009888, .val = 0x12E70042 },
         { .reg = 0x00009888, .val = 0x14E703C0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90387 },
         { .reg = 0x00009888, .val = 0x08E90248 },
         { .reg = 0x00009888, .val = 0x0AE902CA },
         { .reg = 0x00009888, .val = 0x0CE9034C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext511__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext511__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext511__avg_gpu_core_frequency__max,acmgt1__ext511__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1864, 24, NULL,acmgt1__ext511__slm_byte_read_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1865, 32, NULL,acmgt1__ext511__load_store_cache_byte_read_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext512_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext512";
   query->symbol_name = "Ext512";
   query->guid = "3effc828-e8ca-4aab-a1a6-c478a41d55a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870253 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870004 },
         { .reg = 0x00009888, .val = 0x0F870140 },
         { .reg = 0x00009888, .val = 0x118700C4 },
         { .reg = 0x00009888, .val = 0x13870042 },
         { .reg = 0x00009888, .val = 0x158703C0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890387 },
         { .reg = 0x00009888, .val = 0x09890248 },
         { .reg = 0x00009888, .val = 0x0B8902CA },
         { .reg = 0x00009888, .val = 0x0D89034C },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext512__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext512__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext512__avg_gpu_core_frequency__max,acmgt1__ext512__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1866, 24, NULL,acmgt1__ext512__slm_byte_read_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1867, 32, NULL,acmgt1__ext512__load_store_cache_byte_read_bank0_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext513_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext513";
   query->symbol_name = "Ext513";
   query->guid = "42d607af-0d8c-4d80-8443-73f5952060bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17A70253 },
         { .reg = 0x00009888, .val = 0x19A91060 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAA8 },
         { .reg = 0x00009888, .val = 0x01A4FEFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65554 },
         { .reg = 0x00009888, .val = 0x05A70004 },
         { .reg = 0x00009888, .val = 0x0FA70140 },
         { .reg = 0x00009888, .val = 0x11A700C4 },
         { .reg = 0x00009888, .val = 0x13A70042 },
         { .reg = 0x00009888, .val = 0x15A703C0 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A70000 },
         { .reg = 0x00009888, .val = 0x03A90054 },
         { .reg = 0x00009888, .val = 0x07A90387 },
         { .reg = 0x00009888, .val = 0x09A90248 },
         { .reg = 0x00009888, .val = 0x0BA902CA },
         { .reg = 0x00009888, .val = 0x0DA9034C },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFC },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009888, .val = 0x0101FEFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext513__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext513__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext513__avg_gpu_core_frequency__max,acmgt1__ext513__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1868, 24, NULL,acmgt1__ext513__slm_byte_read_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1869, 32, NULL,acmgt1__ext513__load_store_cache_byte_read_bank0_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext514_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext514";
   query->symbol_name = "Ext514";
   query->guid = "bc6702b9-80d9-463e-9699-334c9543e076";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17C70253 },
         { .reg = 0x00009888, .val = 0x19C91060 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAA8 },
         { .reg = 0x00009888, .val = 0x01C4FEFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65554 },
         { .reg = 0x00009888, .val = 0x05C70004 },
         { .reg = 0x00009888, .val = 0x0FC70140 },
         { .reg = 0x00009888, .val = 0x11C700C4 },
         { .reg = 0x00009888, .val = 0x13C70042 },
         { .reg = 0x00009888, .val = 0x15C703C0 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C70000 },
         { .reg = 0x00009888, .val = 0x03C90054 },
         { .reg = 0x00009888, .val = 0x07C90387 },
         { .reg = 0x00009888, .val = 0x09C90248 },
         { .reg = 0x00009888, .val = 0x0BC902CA },
         { .reg = 0x00009888, .val = 0x0DC9034C },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA8 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009888, .val = 0x0102FEFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext514__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext514__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext514__avg_gpu_core_frequency__max,acmgt1__ext514__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1870, 24, NULL,acmgt1__ext514__slm_byte_read_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1871, 32, NULL,acmgt1__ext514__load_store_cache_byte_read_bank0_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext515_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext515";
   query->symbol_name = "Ext515";
   query->guid = "5a8af975-8ceb-4111-b13a-3584b5485afb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E70253 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70004 },
         { .reg = 0x00009888, .val = 0x0FE70140 },
         { .reg = 0x00009888, .val = 0x11E700C4 },
         { .reg = 0x00009888, .val = 0x13E70042 },
         { .reg = 0x00009888, .val = 0x15E703C0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90387 },
         { .reg = 0x00009888, .val = 0x09E90248 },
         { .reg = 0x00009888, .val = 0x0BE902CA },
         { .reg = 0x00009888, .val = 0x0DE9034C },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext515__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext515__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext515__avg_gpu_core_frequency__max,acmgt1__ext515__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1872, 24, NULL,acmgt1__ext515__slm_byte_read_bank0_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1873, 32, NULL,acmgt1__ext515__load_store_cache_byte_read_bank0_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext516_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext516";
   query->symbol_name = "Ext516";
   query->guid = "a0bd2654-8654-4aec-b9c3-609b7cfc7c29";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A870253 },
         { .reg = 0x00009888, .val = 0x1E890083 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x048700E0 },
         { .reg = 0x00009888, .val = 0x0E870540 },
         { .reg = 0x00009888, .val = 0x108704D4 },
         { .reg = 0x00009888, .val = 0x12870452 },
         { .reg = 0x00009888, .val = 0x148707D0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02893200 },
         { .reg = 0x00009888, .val = 0x06890797 },
         { .reg = 0x00009888, .val = 0x08890658 },
         { .reg = 0x00009888, .val = 0x0A8906DA },
         { .reg = 0x00009888, .val = 0x0C89075C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext516__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext516__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext516__avg_gpu_core_frequency__max,acmgt1__ext516__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1874, 24, NULL,acmgt1__ext516__slm_byte_read_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1875, 32, NULL,acmgt1__ext516__load_store_cache_byte_read_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext517_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext517";
   query->symbol_name = "Ext517";
   query->guid = "56c67cc8-4bbb-44bc-8552-1d095f1800bc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA70253 },
         { .reg = 0x00009888, .val = 0x1EA90083 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A700E0 },
         { .reg = 0x00009888, .val = 0x0EA70540 },
         { .reg = 0x00009888, .val = 0x10A704D4 },
         { .reg = 0x00009888, .val = 0x12A70452 },
         { .reg = 0x00009888, .val = 0x14A707D0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A93200 },
         { .reg = 0x00009888, .val = 0x06A90797 },
         { .reg = 0x00009888, .val = 0x08A90658 },
         { .reg = 0x00009888, .val = 0x0AA906DA },
         { .reg = 0x00009888, .val = 0x0CA9075C },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext517__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext517__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext517__avg_gpu_core_frequency__max,acmgt1__ext517__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1876, 24, NULL,acmgt1__ext517__slm_byte_read_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1877, 32, NULL,acmgt1__ext517__load_store_cache_byte_read_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext518_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext518";
   query->symbol_name = "Ext518";
   query->guid = "f4f45c2b-4810-43db-a47d-cb854884f724";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC70253 },
         { .reg = 0x00009888, .val = 0x1EC90083 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C700E0 },
         { .reg = 0x00009888, .val = 0x0EC70540 },
         { .reg = 0x00009888, .val = 0x10C704D4 },
         { .reg = 0x00009888, .val = 0x12C70452 },
         { .reg = 0x00009888, .val = 0x14C707D0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C93200 },
         { .reg = 0x00009888, .val = 0x06C90797 },
         { .reg = 0x00009888, .val = 0x08C90658 },
         { .reg = 0x00009888, .val = 0x0AC906DA },
         { .reg = 0x00009888, .val = 0x0CC9075C },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext518__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext518__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext518__avg_gpu_core_frequency__max,acmgt1__ext518__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1878, 24, NULL,acmgt1__ext518__slm_byte_read_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1879, 32, NULL,acmgt1__ext518__load_store_cache_byte_read_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext519_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext519";
   query->symbol_name = "Ext519";
   query->guid = "58283b64-3a38-4985-b19c-db349947311a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE70253 },
         { .reg = 0x00009888, .val = 0x1EE90083 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E700E0 },
         { .reg = 0x00009888, .val = 0x0EE70540 },
         { .reg = 0x00009888, .val = 0x10E704D4 },
         { .reg = 0x00009888, .val = 0x12E70452 },
         { .reg = 0x00009888, .val = 0x14E707D0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E93200 },
         { .reg = 0x00009888, .val = 0x06E90797 },
         { .reg = 0x00009888, .val = 0x08E90658 },
         { .reg = 0x00009888, .val = 0x0AE906DA },
         { .reg = 0x00009888, .val = 0x0CE9075C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext519__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext519__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext519__avg_gpu_core_frequency__max,acmgt1__ext519__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1880, 24, NULL,acmgt1__ext519__slm_byte_read_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1881, 32, NULL,acmgt1__ext519__load_store_cache_byte_read_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext520_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext520";
   query->symbol_name = "Ext520";
   query->guid = "144cc1f2-ff34-4ce7-8bb9-7cb6cee76403";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B870253 },
         { .reg = 0x00009888, .val = 0x1F890083 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x058700E0 },
         { .reg = 0x00009888, .val = 0x0F870540 },
         { .reg = 0x00009888, .val = 0x118704D4 },
         { .reg = 0x00009888, .val = 0x13870452 },
         { .reg = 0x00009888, .val = 0x158707D0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03893200 },
         { .reg = 0x00009888, .val = 0x07890797 },
         { .reg = 0x00009888, .val = 0x09890658 },
         { .reg = 0x00009888, .val = 0x0B8906DA },
         { .reg = 0x00009888, .val = 0x0D89075C },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext520__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext520__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext520__avg_gpu_core_frequency__max,acmgt1__ext520__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1882, 24, NULL,acmgt1__ext520__slm_byte_read_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1883, 32, NULL,acmgt1__ext520__load_store_cache_byte_read_bank1_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext521_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext521";
   query->symbol_name = "Ext521";
   query->guid = "9b5b6101-2131-4069-ace5-bcb3300991cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA70253 },
         { .reg = 0x00009888, .val = 0x1FA90083 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAA8 },
         { .reg = 0x00009888, .val = 0x01A4FEFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65554 },
         { .reg = 0x00009888, .val = 0x05A700E0 },
         { .reg = 0x00009888, .val = 0x0FA70540 },
         { .reg = 0x00009888, .val = 0x11A704D4 },
         { .reg = 0x00009888, .val = 0x13A70452 },
         { .reg = 0x00009888, .val = 0x15A707D0 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A70000 },
         { .reg = 0x00009888, .val = 0x03A93200 },
         { .reg = 0x00009888, .val = 0x07A90797 },
         { .reg = 0x00009888, .val = 0x09A90658 },
         { .reg = 0x00009888, .val = 0x0BA906DA },
         { .reg = 0x00009888, .val = 0x0DA9075C },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFC },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009888, .val = 0x0101FEFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext521__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext521__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext521__avg_gpu_core_frequency__max,acmgt1__ext521__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1884, 24, NULL,acmgt1__ext521__slm_byte_read_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1885, 32, NULL,acmgt1__ext521__load_store_cache_byte_read_bank1_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext522_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext522";
   query->symbol_name = "Ext522";
   query->guid = "b3cfc81d-5297-483d-8e45-b77e4935fbe9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC70253 },
         { .reg = 0x00009888, .val = 0x1FC90083 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAA8 },
         { .reg = 0x00009888, .val = 0x01C4FEFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65554 },
         { .reg = 0x00009888, .val = 0x05C700E0 },
         { .reg = 0x00009888, .val = 0x0FC70540 },
         { .reg = 0x00009888, .val = 0x11C704D4 },
         { .reg = 0x00009888, .val = 0x13C70452 },
         { .reg = 0x00009888, .val = 0x15C707D0 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C70000 },
         { .reg = 0x00009888, .val = 0x03C93200 },
         { .reg = 0x00009888, .val = 0x07C90797 },
         { .reg = 0x00009888, .val = 0x09C90658 },
         { .reg = 0x00009888, .val = 0x0BC906DA },
         { .reg = 0x00009888, .val = 0x0DC9075C },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA8 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009888, .val = 0x0102FEFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext522__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext522__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext522__avg_gpu_core_frequency__max,acmgt1__ext522__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1886, 24, NULL,acmgt1__ext522__slm_byte_read_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1887, 32, NULL,acmgt1__ext522__load_store_cache_byte_read_bank1_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext523_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext523";
   query->symbol_name = "Ext523";
   query->guid = "1975278e-2c3f-49a3-891a-fc2ed8f22eec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE70253 },
         { .reg = 0x00009888, .val = 0x1FE90083 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E700E0 },
         { .reg = 0x00009888, .val = 0x0FE70540 },
         { .reg = 0x00009888, .val = 0x11E704D4 },
         { .reg = 0x00009888, .val = 0x13E70452 },
         { .reg = 0x00009888, .val = 0x15E707D0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E93200 },
         { .reg = 0x00009888, .val = 0x07E90797 },
         { .reg = 0x00009888, .val = 0x09E90658 },
         { .reg = 0x00009888, .val = 0x0BE906DA },
         { .reg = 0x00009888, .val = 0x0DE9075C },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext523__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext523__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext523__avg_gpu_core_frequency__max,acmgt1__ext523__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1888, 24, NULL,acmgt1__ext523__slm_byte_read_bank1_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1889, 32, NULL,acmgt1__ext523__load_store_cache_byte_read_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext524_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext524";
   query->symbol_name = "Ext524";
   query->guid = "06d3fa26-617a-4443-a552-17937fc2bc83";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12880253 },
         { .reg = 0x00009888, .val = 0x22890C00 },
         { .reg = 0x00009888, .val = 0x24890004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x00880004 },
         { .reg = 0x00009888, .val = 0x0A880140 },
         { .reg = 0x00009888, .val = 0x0C8800C4 },
         { .reg = 0x00009888, .val = 0x0E880042 },
         { .reg = 0x00009888, .val = 0x108803C0 },
         { .reg = 0x00009888, .val = 0x04890008 },
         { .reg = 0x00009888, .val = 0x06890BA7 },
         { .reg = 0x00009888, .val = 0x08890A68 },
         { .reg = 0x00009888, .val = 0x0A890AEA },
         { .reg = 0x00009888, .val = 0x0C890B6C },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext524__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext524__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext524__avg_gpu_core_frequency__max,acmgt1__ext524__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1890, 24, NULL,acmgt1__ext524__slm_byte_read_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1891, 32, NULL,acmgt1__ext524__load_store_cache_byte_read_bank2_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext525_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext525";
   query->symbol_name = "Ext525";
   query->guid = "5115960e-f55c-4854-bac4-b771c4185270";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12A80253 },
         { .reg = 0x00009888, .val = 0x22A90C00 },
         { .reg = 0x00009888, .val = 0x24A90004 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A80004 },
         { .reg = 0x00009888, .val = 0x0AA80140 },
         { .reg = 0x00009888, .val = 0x0CA800C4 },
         { .reg = 0x00009888, .val = 0x0EA80042 },
         { .reg = 0x00009888, .val = 0x10A803C0 },
         { .reg = 0x00009888, .val = 0x04A90008 },
         { .reg = 0x00009888, .val = 0x06A90BA7 },
         { .reg = 0x00009888, .val = 0x08A90A68 },
         { .reg = 0x00009888, .val = 0x0AA90AEA },
         { .reg = 0x00009888, .val = 0x0CA90B6C },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext525__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext525__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext525__avg_gpu_core_frequency__max,acmgt1__ext525__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1892, 24, NULL,acmgt1__ext525__slm_byte_read_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1893, 32, NULL,acmgt1__ext525__load_store_cache_byte_read_bank2_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext526_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext526";
   query->symbol_name = "Ext526";
   query->guid = "4dc30759-6119-4bf0-85b7-4a7cd5e79956";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C80253 },
         { .reg = 0x00009888, .val = 0x22C90C00 },
         { .reg = 0x00009888, .val = 0x24C90004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C80004 },
         { .reg = 0x00009888, .val = 0x0AC80140 },
         { .reg = 0x00009888, .val = 0x0CC800C4 },
         { .reg = 0x00009888, .val = 0x0EC80042 },
         { .reg = 0x00009888, .val = 0x10C803C0 },
         { .reg = 0x00009888, .val = 0x04C90008 },
         { .reg = 0x00009888, .val = 0x06C90BA7 },
         { .reg = 0x00009888, .val = 0x08C90A68 },
         { .reg = 0x00009888, .val = 0x0AC90AEA },
         { .reg = 0x00009888, .val = 0x0CC90B6C },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext526__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext526__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext526__avg_gpu_core_frequency__max,acmgt1__ext526__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1894, 24, NULL,acmgt1__ext526__slm_byte_read_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1895, 32, NULL,acmgt1__ext526__load_store_cache_byte_read_bank2_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext527_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext527";
   query->symbol_name = "Ext527";
   query->guid = "2060bec5-9739-4970-ab77-09dd7c107044";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12E80253 },
         { .reg = 0x00009888, .val = 0x22E90C00 },
         { .reg = 0x00009888, .val = 0x24E90004 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E80004 },
         { .reg = 0x00009888, .val = 0x0AE80140 },
         { .reg = 0x00009888, .val = 0x0CE800C4 },
         { .reg = 0x00009888, .val = 0x0EE80042 },
         { .reg = 0x00009888, .val = 0x10E803C0 },
         { .reg = 0x00009888, .val = 0x04E90008 },
         { .reg = 0x00009888, .val = 0x06E90BA7 },
         { .reg = 0x00009888, .val = 0x08E90A68 },
         { .reg = 0x00009888, .val = 0x0AE90AEA },
         { .reg = 0x00009888, .val = 0x0CE90B6C },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext527__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext527__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext527__avg_gpu_core_frequency__max,acmgt1__ext527__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1896, 24, NULL,acmgt1__ext527__slm_byte_read_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1897, 32, NULL,acmgt1__ext527__load_store_cache_byte_read_bank2_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext528_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext528";
   query->symbol_name = "Ext528";
   query->guid = "91384c6e-5087-43d6-a32f-699690ca8917";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13880253 },
         { .reg = 0x00009888, .val = 0x23890C00 },
         { .reg = 0x00009888, .val = 0x25890004 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAA8 },
         { .reg = 0x00009888, .val = 0x01880004 },
         { .reg = 0x00009888, .val = 0x0B880140 },
         { .reg = 0x00009888, .val = 0x0D8800C4 },
         { .reg = 0x00009888, .val = 0x0F880042 },
         { .reg = 0x00009888, .val = 0x118803C0 },
         { .reg = 0x00009888, .val = 0x05890008 },
         { .reg = 0x00009888, .val = 0x07890BA7 },
         { .reg = 0x00009888, .val = 0x09890A68 },
         { .reg = 0x00009888, .val = 0x0B890AEA },
         { .reg = 0x00009888, .val = 0x0D890B6C },
         { .reg = 0x00009888, .val = 0x0189FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext528__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext528__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext528__avg_gpu_core_frequency__max,acmgt1__ext528__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1898, 24, NULL,acmgt1__ext528__slm_byte_read_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1899, 32, NULL,acmgt1__ext528__load_store_cache_byte_read_bank2_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext529_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext529";
   query->symbol_name = "Ext529";
   query->guid = "cb4f7554-9a12-4f83-a7c6-0ff8911f9e73";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13A80253 },
         { .reg = 0x00009888, .val = 0x23A90C00 },
         { .reg = 0x00009888, .val = 0x25A90004 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAA8 },
         { .reg = 0x00009888, .val = 0x01A4FEFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65554 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAA8 },
         { .reg = 0x00009888, .val = 0x01A80004 },
         { .reg = 0x00009888, .val = 0x0BA80140 },
         { .reg = 0x00009888, .val = 0x0DA800C4 },
         { .reg = 0x00009888, .val = 0x0FA80042 },
         { .reg = 0x00009888, .val = 0x11A803C0 },
         { .reg = 0x00009888, .val = 0x05A90008 },
         { .reg = 0x00009888, .val = 0x07A90BA7 },
         { .reg = 0x00009888, .val = 0x09A90A68 },
         { .reg = 0x00009888, .val = 0x0BA90AEA },
         { .reg = 0x00009888, .val = 0x0DA90B6C },
         { .reg = 0x00009888, .val = 0x01A9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFC },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009888, .val = 0x0101FEFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext529__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext529__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext529__avg_gpu_core_frequency__max,acmgt1__ext529__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1900, 24, NULL,acmgt1__ext529__slm_byte_read_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1901, 32, NULL,acmgt1__ext529__load_store_cache_byte_read_bank2_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext530_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext530";
   query->symbol_name = "Ext530";
   query->guid = "80502c88-9c1e-4804-8d54-53b3d784a540";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13C80253 },
         { .reg = 0x00009888, .val = 0x23C90C00 },
         { .reg = 0x00009888, .val = 0x25C90004 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAA8 },
         { .reg = 0x00009888, .val = 0x01C4FEFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65554 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAA8 },
         { .reg = 0x00009888, .val = 0x01C80004 },
         { .reg = 0x00009888, .val = 0x0BC80140 },
         { .reg = 0x00009888, .val = 0x0DC800C4 },
         { .reg = 0x00009888, .val = 0x0FC80042 },
         { .reg = 0x00009888, .val = 0x11C803C0 },
         { .reg = 0x00009888, .val = 0x05C90008 },
         { .reg = 0x00009888, .val = 0x07C90BA7 },
         { .reg = 0x00009888, .val = 0x09C90A68 },
         { .reg = 0x00009888, .val = 0x0BC90AEA },
         { .reg = 0x00009888, .val = 0x0DC90B6C },
         { .reg = 0x00009888, .val = 0x01C9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA8 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009888, .val = 0x0102FEFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext530__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext530__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext530__avg_gpu_core_frequency__max,acmgt1__ext530__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1902, 24, NULL,acmgt1__ext530__slm_byte_read_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1903, 32, NULL,acmgt1__ext530__load_store_cache_byte_read_bank2_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext531_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext531";
   query->symbol_name = "Ext531";
   query->guid = "eccbb94d-f7ed-4d45-89bb-d17a0e28e97d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13E80253 },
         { .reg = 0x00009888, .val = 0x23E90C00 },
         { .reg = 0x00009888, .val = 0x25E90004 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAA8 },
         { .reg = 0x00009888, .val = 0x01E80004 },
         { .reg = 0x00009888, .val = 0x0BE80140 },
         { .reg = 0x00009888, .val = 0x0DE800C4 },
         { .reg = 0x00009888, .val = 0x0FE80042 },
         { .reg = 0x00009888, .val = 0x11E803C0 },
         { .reg = 0x00009888, .val = 0x05E90008 },
         { .reg = 0x00009888, .val = 0x07E90BA7 },
         { .reg = 0x00009888, .val = 0x09E90A68 },
         { .reg = 0x00009888, .val = 0x0BE90AEA },
         { .reg = 0x00009888, .val = 0x0DE90B6C },
         { .reg = 0x00009888, .val = 0x01E9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext531__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext531__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext531__avg_gpu_core_frequency__max,acmgt1__ext531__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1904, 24, NULL,acmgt1__ext531__slm_byte_read_bank2_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1905, 32, NULL,acmgt1__ext531__load_store_cache_byte_read_bank2_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext532_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext532";
   query->symbol_name = "Ext532";
   query->guid = "09cb4790-899a-456f-9c12-f0b5ae36bf39";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16880253 },
         { .reg = 0x00009888, .val = 0x28891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x008800E0 },
         { .reg = 0x00009888, .val = 0x0A880540 },
         { .reg = 0x00009888, .val = 0x0C8804D4 },
         { .reg = 0x00009888, .val = 0x0E880452 },
         { .reg = 0x00009888, .val = 0x108807D0 },
         { .reg = 0x00009888, .val = 0x04890200 },
         { .reg = 0x00009888, .val = 0x06890FB7 },
         { .reg = 0x00009888, .val = 0x08890E78 },
         { .reg = 0x00009888, .val = 0x0A890EFA },
         { .reg = 0x00009888, .val = 0x0C890F7C },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext532__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext532__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext532__avg_gpu_core_frequency__max,acmgt1__ext532__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1906, 24, NULL,acmgt1__ext532__slm_byte_read_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1907, 32, NULL,acmgt1__ext532__load_store_cache_byte_read_bank3_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext533_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext533";
   query->symbol_name = "Ext533";
   query->guid = "e257595b-2e38-4da5-b375-bc494b4d0ee8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A80253 },
         { .reg = 0x00009888, .val = 0x28A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A800E0 },
         { .reg = 0x00009888, .val = 0x0AA80540 },
         { .reg = 0x00009888, .val = 0x0CA804D4 },
         { .reg = 0x00009888, .val = 0x0EA80452 },
         { .reg = 0x00009888, .val = 0x10A807D0 },
         { .reg = 0x00009888, .val = 0x04A90200 },
         { .reg = 0x00009888, .val = 0x06A90FB7 },
         { .reg = 0x00009888, .val = 0x08A90E78 },
         { .reg = 0x00009888, .val = 0x0AA90EFA },
         { .reg = 0x00009888, .val = 0x0CA90F7C },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext533__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext533__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext533__avg_gpu_core_frequency__max,acmgt1__ext533__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1908, 24, NULL,acmgt1__ext533__slm_byte_read_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1909, 32, NULL,acmgt1__ext533__load_store_cache_byte_read_bank3_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext534_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext534";
   query->symbol_name = "Ext534";
   query->guid = "f2477c56-db39-43cf-bd4c-42782dd02e27";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C80253 },
         { .reg = 0x00009888, .val = 0x28C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C800E0 },
         { .reg = 0x00009888, .val = 0x0AC80540 },
         { .reg = 0x00009888, .val = 0x0CC804D4 },
         { .reg = 0x00009888, .val = 0x0EC80452 },
         { .reg = 0x00009888, .val = 0x10C807D0 },
         { .reg = 0x00009888, .val = 0x04C90200 },
         { .reg = 0x00009888, .val = 0x06C90FB7 },
         { .reg = 0x00009888, .val = 0x08C90E78 },
         { .reg = 0x00009888, .val = 0x0AC90EFA },
         { .reg = 0x00009888, .val = 0x0CC90F7C },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext534__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext534__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext534__avg_gpu_core_frequency__max,acmgt1__ext534__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1910, 24, NULL,acmgt1__ext534__slm_byte_read_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1911, 32, NULL,acmgt1__ext534__load_store_cache_byte_read_bank3_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext535_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext535";
   query->symbol_name = "Ext535";
   query->guid = "b6417928-9c95-4df7-88a2-e6b8de52abec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E80253 },
         { .reg = 0x00009888, .val = 0x28E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E800E0 },
         { .reg = 0x00009888, .val = 0x0AE80540 },
         { .reg = 0x00009888, .val = 0x0CE804D4 },
         { .reg = 0x00009888, .val = 0x0EE80452 },
         { .reg = 0x00009888, .val = 0x10E807D0 },
         { .reg = 0x00009888, .val = 0x04E90200 },
         { .reg = 0x00009888, .val = 0x06E90FB7 },
         { .reg = 0x00009888, .val = 0x08E90E78 },
         { .reg = 0x00009888, .val = 0x0AE90EFA },
         { .reg = 0x00009888, .val = 0x0CE90F7C },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext535__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext535__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext535__avg_gpu_core_frequency__max,acmgt1__ext535__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1912, 24, NULL,acmgt1__ext535__slm_byte_read_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1913, 32, NULL,acmgt1__ext535__load_store_cache_byte_read_bank3_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext536_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext536";
   query->symbol_name = "Ext536";
   query->guid = "ac88f2a7-2f38-4e61-a6d5-9da2d50edd38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17880253 },
         { .reg = 0x00009888, .val = 0x29891060 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAA8 },
         { .reg = 0x00009888, .val = 0x018800E0 },
         { .reg = 0x00009888, .val = 0x0B880540 },
         { .reg = 0x00009888, .val = 0x0D8804D4 },
         { .reg = 0x00009888, .val = 0x0F880452 },
         { .reg = 0x00009888, .val = 0x118807D0 },
         { .reg = 0x00009888, .val = 0x05890200 },
         { .reg = 0x00009888, .val = 0x07890FB7 },
         { .reg = 0x00009888, .val = 0x09890E78 },
         { .reg = 0x00009888, .val = 0x0B890EFA },
         { .reg = 0x00009888, .val = 0x0D890F7C },
         { .reg = 0x00009888, .val = 0x0189FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext536__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext536__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext536__avg_gpu_core_frequency__max,acmgt1__ext536__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1914, 24, NULL,acmgt1__ext536__slm_byte_read_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1915, 32, NULL,acmgt1__ext536__load_store_cache_byte_read_bank3_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext537_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext537";
   query->symbol_name = "Ext537";
   query->guid = "87640cd9-04b0-4b76-a016-308ab7975f8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17A80253 },
         { .reg = 0x00009888, .val = 0x29A91060 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAA8 },
         { .reg = 0x00009888, .val = 0x01A4FEFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65554 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAA8 },
         { .reg = 0x00009888, .val = 0x01A800E0 },
         { .reg = 0x00009888, .val = 0x0BA80540 },
         { .reg = 0x00009888, .val = 0x0DA804D4 },
         { .reg = 0x00009888, .val = 0x0FA80452 },
         { .reg = 0x00009888, .val = 0x11A807D0 },
         { .reg = 0x00009888, .val = 0x05A90200 },
         { .reg = 0x00009888, .val = 0x07A90FB7 },
         { .reg = 0x00009888, .val = 0x09A90E78 },
         { .reg = 0x00009888, .val = 0x0BA90EFA },
         { .reg = 0x00009888, .val = 0x0DA90F7C },
         { .reg = 0x00009888, .val = 0x01A9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFC },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009888, .val = 0x0101FEFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext537__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext537__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext537__avg_gpu_core_frequency__max,acmgt1__ext537__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1916, 24, NULL,acmgt1__ext537__slm_byte_read_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1917, 32, NULL,acmgt1__ext537__load_store_cache_byte_read_bank3_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext538_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext538";
   query->symbol_name = "Ext538";
   query->guid = "2a2f8a81-b046-4a67-92c3-2ded36755f76";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17C80253 },
         { .reg = 0x00009888, .val = 0x29C91060 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAA8 },
         { .reg = 0x00009888, .val = 0x01C4FEFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65554 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAA8 },
         { .reg = 0x00009888, .val = 0x01C800E0 },
         { .reg = 0x00009888, .val = 0x0BC80540 },
         { .reg = 0x00009888, .val = 0x0DC804D4 },
         { .reg = 0x00009888, .val = 0x0FC80452 },
         { .reg = 0x00009888, .val = 0x11C807D0 },
         { .reg = 0x00009888, .val = 0x05C90200 },
         { .reg = 0x00009888, .val = 0x07C90FB7 },
         { .reg = 0x00009888, .val = 0x09C90E78 },
         { .reg = 0x00009888, .val = 0x0BC90EFA },
         { .reg = 0x00009888, .val = 0x0DC90F7C },
         { .reg = 0x00009888, .val = 0x01C9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA8 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009888, .val = 0x0102FEFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext538__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext538__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext538__avg_gpu_core_frequency__max,acmgt1__ext538__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1918, 24, NULL,acmgt1__ext538__slm_byte_read_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1919, 32, NULL,acmgt1__ext538__load_store_cache_byte_read_bank3_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext539_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext539";
   query->symbol_name = "Ext539";
   query->guid = "89f03450-0e5f-4370-b7cf-cea4e627d4e8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E80253 },
         { .reg = 0x00009888, .val = 0x29E91060 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAA8 },
         { .reg = 0x00009888, .val = 0x01E800E0 },
         { .reg = 0x00009888, .val = 0x0BE80540 },
         { .reg = 0x00009888, .val = 0x0DE804D4 },
         { .reg = 0x00009888, .val = 0x0FE80452 },
         { .reg = 0x00009888, .val = 0x11E807D0 },
         { .reg = 0x00009888, .val = 0x05E90200 },
         { .reg = 0x00009888, .val = 0x07E90FB7 },
         { .reg = 0x00009888, .val = 0x09E90E78 },
         { .reg = 0x00009888, .val = 0x0BE90EFA },
         { .reg = 0x00009888, .val = 0x0DE90F7C },
         { .reg = 0x00009888, .val = 0x01E9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext539__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext539__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext539__avg_gpu_core_frequency__max,acmgt1__ext539__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1920, 24, NULL,acmgt1__ext539__slm_byte_read_bank3_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1921, 32, NULL,acmgt1__ext539__load_store_cache_byte_read_bank3_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext540_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext540";
   query->symbol_name = "Ext540";
   query->guid = "85c7638d-976e-47e5-8f52-2079a0ea147f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870012 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x0E870180 },
         { .reg = 0x00009888, .val = 0x10870105 },
         { .reg = 0x00009888, .val = 0x12870083 },
         { .reg = 0x00009888, .val = 0x14870001 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890380 },
         { .reg = 0x00009888, .val = 0x08890081 },
         { .reg = 0x00009888, .val = 0x0A890103 },
         { .reg = 0x00009888, .val = 0x0C890185 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext540__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext540__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext540__avg_gpu_core_frequency__max,acmgt1__ext540__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1922, 24, NULL,acmgt1__ext540__slm_byte_write_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1923, 32, NULL,acmgt1__ext540__load_store_cache_byte_write_bank0_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext541_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext541";
   query->symbol_name = "Ext541";
   query->guid = "69645853-2e7f-4a77-83fc-fa03f43b5d35";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A70012 },
         { .reg = 0x00009888, .val = 0x18A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x0EA70180 },
         { .reg = 0x00009888, .val = 0x10A70105 },
         { .reg = 0x00009888, .val = 0x12A70083 },
         { .reg = 0x00009888, .val = 0x14A70001 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A90054 },
         { .reg = 0x00009888, .val = 0x06A90380 },
         { .reg = 0x00009888, .val = 0x08A90081 },
         { .reg = 0x00009888, .val = 0x0AA90103 },
         { .reg = 0x00009888, .val = 0x0CA90185 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext541__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext541__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext541__avg_gpu_core_frequency__max,acmgt1__ext541__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1924, 24, NULL,acmgt1__ext541__slm_byte_write_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1925, 32, NULL,acmgt1__ext541__load_store_cache_byte_write_bank0_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext542_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext542";
   query->symbol_name = "Ext542";
   query->guid = "657218aa-a73a-4127-b081-07ece46ff786";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C70012 },
         { .reg = 0x00009888, .val = 0x18C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x0EC70180 },
         { .reg = 0x00009888, .val = 0x10C70105 },
         { .reg = 0x00009888, .val = 0x12C70083 },
         { .reg = 0x00009888, .val = 0x14C70001 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C90054 },
         { .reg = 0x00009888, .val = 0x06C90380 },
         { .reg = 0x00009888, .val = 0x08C90081 },
         { .reg = 0x00009888, .val = 0x0AC90103 },
         { .reg = 0x00009888, .val = 0x0CC90185 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext542__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext542__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext542__avg_gpu_core_frequency__max,acmgt1__ext542__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1926, 24, NULL,acmgt1__ext542__slm_byte_write_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1927, 32, NULL,acmgt1__ext542__load_store_cache_byte_write_bank0_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext543_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext543";
   query->symbol_name = "Ext543";
   query->guid = "1a51853a-37a2-4020-8ccb-650604ea4f64";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E70012 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x0EE70180 },
         { .reg = 0x00009888, .val = 0x10E70105 },
         { .reg = 0x00009888, .val = 0x12E70083 },
         { .reg = 0x00009888, .val = 0x14E70001 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90380 },
         { .reg = 0x00009888, .val = 0x08E90081 },
         { .reg = 0x00009888, .val = 0x0AE90103 },
         { .reg = 0x00009888, .val = 0x0CE90185 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext543__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext543__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext543__avg_gpu_core_frequency__max,acmgt1__ext543__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1928, 24, NULL,acmgt1__ext543__slm_byte_write_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1929, 32, NULL,acmgt1__ext543__load_store_cache_byte_write_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext544_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext544";
   query->symbol_name = "Ext544";
   query->guid = "9aa2e068-b13a-44b2-be93-a4cf68924cdd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870012 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870000 },
         { .reg = 0x00009888, .val = 0x0F870180 },
         { .reg = 0x00009888, .val = 0x11870105 },
         { .reg = 0x00009888, .val = 0x13870083 },
         { .reg = 0x00009888, .val = 0x15870001 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890380 },
         { .reg = 0x00009888, .val = 0x09890081 },
         { .reg = 0x00009888, .val = 0x0B890103 },
         { .reg = 0x00009888, .val = 0x0D890185 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext544__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext544__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext544__avg_gpu_core_frequency__max,acmgt1__ext544__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1930, 24, NULL,acmgt1__ext544__slm_byte_write_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1931, 32, NULL,acmgt1__ext544__load_store_cache_byte_write_bank0_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext545_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext545";
   query->symbol_name = "Ext545";
   query->guid = "5e8c65a2-97ac-4dea-af1b-27b9f12dafe6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17A70012 },
         { .reg = 0x00009888, .val = 0x19A91060 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAA8 },
         { .reg = 0x00009888, .val = 0x01A4FEFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65554 },
         { .reg = 0x00009888, .val = 0x05A70000 },
         { .reg = 0x00009888, .val = 0x0FA70180 },
         { .reg = 0x00009888, .val = 0x11A70105 },
         { .reg = 0x00009888, .val = 0x13A70083 },
         { .reg = 0x00009888, .val = 0x15A70001 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A70000 },
         { .reg = 0x00009888, .val = 0x03A90054 },
         { .reg = 0x00009888, .val = 0x07A90380 },
         { .reg = 0x00009888, .val = 0x09A90081 },
         { .reg = 0x00009888, .val = 0x0BA90103 },
         { .reg = 0x00009888, .val = 0x0DA90185 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFC },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009888, .val = 0x0101FEFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext545__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext545__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext545__avg_gpu_core_frequency__max,acmgt1__ext545__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1932, 24, NULL,acmgt1__ext545__slm_byte_write_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1933, 32, NULL,acmgt1__ext545__load_store_cache_byte_write_bank0_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext546_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext546";
   query->symbol_name = "Ext546";
   query->guid = "192ec14b-c329-4e81-bd2d-02f7cae24579";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17C70012 },
         { .reg = 0x00009888, .val = 0x19C91060 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAA8 },
         { .reg = 0x00009888, .val = 0x01C4FEFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65554 },
         { .reg = 0x00009888, .val = 0x05C70000 },
         { .reg = 0x00009888, .val = 0x0FC70180 },
         { .reg = 0x00009888, .val = 0x11C70105 },
         { .reg = 0x00009888, .val = 0x13C70083 },
         { .reg = 0x00009888, .val = 0x15C70001 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C70000 },
         { .reg = 0x00009888, .val = 0x03C90054 },
         { .reg = 0x00009888, .val = 0x07C90380 },
         { .reg = 0x00009888, .val = 0x09C90081 },
         { .reg = 0x00009888, .val = 0x0BC90103 },
         { .reg = 0x00009888, .val = 0x0DC90185 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA8 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009888, .val = 0x0102FEFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext546__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext546__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext546__avg_gpu_core_frequency__max,acmgt1__ext546__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1934, 24, NULL,acmgt1__ext546__slm_byte_write_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1935, 32, NULL,acmgt1__ext546__load_store_cache_byte_write_bank0_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext547_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext547";
   query->symbol_name = "Ext547";
   query->guid = "2e5ac978-b4e4-4693-8f88-d90d0353dd77";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E70012 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70000 },
         { .reg = 0x00009888, .val = 0x0FE70180 },
         { .reg = 0x00009888, .val = 0x11E70105 },
         { .reg = 0x00009888, .val = 0x13E70083 },
         { .reg = 0x00009888, .val = 0x15E70001 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90380 },
         { .reg = 0x00009888, .val = 0x09E90081 },
         { .reg = 0x00009888, .val = 0x0BE90103 },
         { .reg = 0x00009888, .val = 0x0DE90185 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext547__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext547__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext547__avg_gpu_core_frequency__max,acmgt1__ext547__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1936, 24, NULL,acmgt1__ext547__slm_byte_write_bank0_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1937, 32, NULL,acmgt1__ext547__load_store_cache_byte_write_bank0_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext548_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext548";
   query->symbol_name = "Ext548";
   query->guid = "7c95ba0f-cd85-4eb2-ab43-987f84214820";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A870012 },
         { .reg = 0x00009888, .val = 0x1E890083 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x0E870580 },
         { .reg = 0x00009888, .val = 0x10870515 },
         { .reg = 0x00009888, .val = 0x12870493 },
         { .reg = 0x00009888, .val = 0x14870411 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02893200 },
         { .reg = 0x00009888, .val = 0x06890790 },
         { .reg = 0x00009888, .val = 0x08890491 },
         { .reg = 0x00009888, .val = 0x0A890513 },
         { .reg = 0x00009888, .val = 0x0C890595 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext548__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext548__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext548__avg_gpu_core_frequency__max,acmgt1__ext548__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1938, 24, NULL,acmgt1__ext548__slm_byte_write_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1939, 32, NULL,acmgt1__ext548__load_store_cache_byte_write_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext549_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext549";
   query->symbol_name = "Ext549";
   query->guid = "8fa03693-d2d5-42eb-a382-e2cf05bf8197";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA70012 },
         { .reg = 0x00009888, .val = 0x1EA90083 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70580 },
         { .reg = 0x00009888, .val = 0x10A70515 },
         { .reg = 0x00009888, .val = 0x12A70493 },
         { .reg = 0x00009888, .val = 0x14A70411 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A93200 },
         { .reg = 0x00009888, .val = 0x06A90790 },
         { .reg = 0x00009888, .val = 0x08A90491 },
         { .reg = 0x00009888, .val = 0x0AA90513 },
         { .reg = 0x00009888, .val = 0x0CA90595 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext549__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext549__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext549__avg_gpu_core_frequency__max,acmgt1__ext549__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1940, 24, NULL,acmgt1__ext549__slm_byte_write_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1941, 32, NULL,acmgt1__ext549__load_store_cache_byte_write_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext550_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext550";
   query->symbol_name = "Ext550";
   query->guid = "3714122b-03ee-499b-bc5f-31ed5400924e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC70012 },
         { .reg = 0x00009888, .val = 0x1EC90083 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0EC70580 },
         { .reg = 0x00009888, .val = 0x10C70515 },
         { .reg = 0x00009888, .val = 0x12C70493 },
         { .reg = 0x00009888, .val = 0x14C70411 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C93200 },
         { .reg = 0x00009888, .val = 0x06C90790 },
         { .reg = 0x00009888, .val = 0x08C90491 },
         { .reg = 0x00009888, .val = 0x0AC90513 },
         { .reg = 0x00009888, .val = 0x0CC90595 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext550__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext550__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext550__avg_gpu_core_frequency__max,acmgt1__ext550__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1942, 24, NULL,acmgt1__ext550__slm_byte_write_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1943, 32, NULL,acmgt1__ext550__load_store_cache_byte_write_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext551_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext551";
   query->symbol_name = "Ext551";
   query->guid = "31ed9c46-b219-4bcc-8c20-22586fb077f8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE70012 },
         { .reg = 0x00009888, .val = 0x1EE90083 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70580 },
         { .reg = 0x00009888, .val = 0x10E70515 },
         { .reg = 0x00009888, .val = 0x12E70493 },
         { .reg = 0x00009888, .val = 0x14E70411 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E93200 },
         { .reg = 0x00009888, .val = 0x06E90790 },
         { .reg = 0x00009888, .val = 0x08E90491 },
         { .reg = 0x00009888, .val = 0x0AE90513 },
         { .reg = 0x00009888, .val = 0x0CE90595 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext551__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext551__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext551__avg_gpu_core_frequency__max,acmgt1__ext551__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1944, 24, NULL,acmgt1__ext551__slm_byte_write_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1945, 32, NULL,acmgt1__ext551__load_store_cache_byte_write_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext552_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext552";
   query->symbol_name = "Ext552";
   query->guid = "f639c566-949f-4484-8c12-5127fb771b4c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B870012 },
         { .reg = 0x00009888, .val = 0x1F890083 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x0F870580 },
         { .reg = 0x00009888, .val = 0x11870515 },
         { .reg = 0x00009888, .val = 0x13870493 },
         { .reg = 0x00009888, .val = 0x15870411 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03893200 },
         { .reg = 0x00009888, .val = 0x07890790 },
         { .reg = 0x00009888, .val = 0x09890491 },
         { .reg = 0x00009888, .val = 0x0B890513 },
         { .reg = 0x00009888, .val = 0x0D890595 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext552__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext552__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext552__avg_gpu_core_frequency__max,acmgt1__ext552__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1946, 24, NULL,acmgt1__ext552__slm_byte_write_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1947, 32, NULL,acmgt1__ext552__load_store_cache_byte_write_bank1_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext553_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext553";
   query->symbol_name = "Ext553";
   query->guid = "40b20c9d-0935-4000-91d7-f312a515bb4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA70012 },
         { .reg = 0x00009888, .val = 0x1FA90083 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAA8 },
         { .reg = 0x00009888, .val = 0x01A4FEFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65554 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0FA70580 },
         { .reg = 0x00009888, .val = 0x11A70515 },
         { .reg = 0x00009888, .val = 0x13A70493 },
         { .reg = 0x00009888, .val = 0x15A70411 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A70000 },
         { .reg = 0x00009888, .val = 0x03A93200 },
         { .reg = 0x00009888, .val = 0x07A90790 },
         { .reg = 0x00009888, .val = 0x09A90491 },
         { .reg = 0x00009888, .val = 0x0BA90513 },
         { .reg = 0x00009888, .val = 0x0DA90595 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFC },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009888, .val = 0x0101FEFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext553__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext553__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext553__avg_gpu_core_frequency__max,acmgt1__ext553__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1948, 24, NULL,acmgt1__ext553__slm_byte_write_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1949, 32, NULL,acmgt1__ext553__load_store_cache_byte_write_bank1_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext554_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext554";
   query->symbol_name = "Ext554";
   query->guid = "bcff8729-44e4-4efa-8436-f1775fcb204a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC70012 },
         { .reg = 0x00009888, .val = 0x1FC90083 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAA8 },
         { .reg = 0x00009888, .val = 0x01C4FEFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65554 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0FC70580 },
         { .reg = 0x00009888, .val = 0x11C70515 },
         { .reg = 0x00009888, .val = 0x13C70493 },
         { .reg = 0x00009888, .val = 0x15C70411 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C70000 },
         { .reg = 0x00009888, .val = 0x03C93200 },
         { .reg = 0x00009888, .val = 0x07C90790 },
         { .reg = 0x00009888, .val = 0x09C90491 },
         { .reg = 0x00009888, .val = 0x0BC90513 },
         { .reg = 0x00009888, .val = 0x0DC90595 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA8 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009888, .val = 0x0102FEFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext554__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext554__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext554__avg_gpu_core_frequency__max,acmgt1__ext554__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1950, 24, NULL,acmgt1__ext554__slm_byte_write_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1951, 32, NULL,acmgt1__ext554__load_store_cache_byte_write_bank1_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext555_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext555";
   query->symbol_name = "Ext555";
   query->guid = "6bf30c0e-a169-4ba3-8527-047d4f691aa3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE70012 },
         { .reg = 0x00009888, .val = 0x1FE90083 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x0FE70580 },
         { .reg = 0x00009888, .val = 0x11E70515 },
         { .reg = 0x00009888, .val = 0x13E70493 },
         { .reg = 0x00009888, .val = 0x15E70411 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E93200 },
         { .reg = 0x00009888, .val = 0x07E90790 },
         { .reg = 0x00009888, .val = 0x09E90491 },
         { .reg = 0x00009888, .val = 0x0BE90513 },
         { .reg = 0x00009888, .val = 0x0DE90595 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x4C030000 },
         { .reg = 0x00009888, .val = 0x4E030000 },
         { .reg = 0x00009888, .val = 0x50030000 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030030 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030C63 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030C63 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext555__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext555__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext555__avg_gpu_core_frequency__max,acmgt1__ext555__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1952, 24, NULL,acmgt1__ext555__slm_byte_write_bank1_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1953, 32, NULL,acmgt1__ext555__load_store_cache_byte_write_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext556_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext556";
   query->symbol_name = "Ext556";
   query->guid = "bc1cda24-8e1b-4000-9443-1135be1b976e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12880012 },
         { .reg = 0x00009888, .val = 0x22890C00 },
         { .reg = 0x00009888, .val = 0x24890004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x0A880180 },
         { .reg = 0x00009888, .val = 0x0C880105 },
         { .reg = 0x00009888, .val = 0x0E880083 },
         { .reg = 0x00009888, .val = 0x10880001 },
         { .reg = 0x00009888, .val = 0x04890008 },
         { .reg = 0x00009888, .val = 0x06890BA0 },
         { .reg = 0x00009888, .val = 0x088908A1 },
         { .reg = 0x00009888, .val = 0x0A890923 },
         { .reg = 0x00009888, .val = 0x0C8909A5 },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext556__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext556__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext556__avg_gpu_core_frequency__max,acmgt1__ext556__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1954, 24, NULL,acmgt1__ext556__slm_byte_write_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1955, 32, NULL,acmgt1__ext556__load_store_cache_byte_write_bank2_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext557_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext557";
   query->symbol_name = "Ext557";
   query->guid = "c8a172f8-4a06-4931-b877-bc8aa687a9b8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12A80012 },
         { .reg = 0x00009888, .val = 0x22A90C00 },
         { .reg = 0x00009888, .val = 0x24A90004 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x0AA80180 },
         { .reg = 0x00009888, .val = 0x0CA80105 },
         { .reg = 0x00009888, .val = 0x0EA80083 },
         { .reg = 0x00009888, .val = 0x10A80001 },
         { .reg = 0x00009888, .val = 0x04A90008 },
         { .reg = 0x00009888, .val = 0x06A90BA0 },
         { .reg = 0x00009888, .val = 0x08A908A1 },
         { .reg = 0x00009888, .val = 0x0AA90923 },
         { .reg = 0x00009888, .val = 0x0CA909A5 },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext557__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext557__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext557__avg_gpu_core_frequency__max,acmgt1__ext557__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1956, 24, NULL,acmgt1__ext557__slm_byte_write_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1957, 32, NULL,acmgt1__ext557__load_store_cache_byte_write_bank2_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext558_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext558";
   query->symbol_name = "Ext558";
   query->guid = "a5a9b5ed-c78c-4e3d-a808-22f1debd6b43";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C80012 },
         { .reg = 0x00009888, .val = 0x22C90C00 },
         { .reg = 0x00009888, .val = 0x24C90004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x0AC80180 },
         { .reg = 0x00009888, .val = 0x0CC80105 },
         { .reg = 0x00009888, .val = 0x0EC80083 },
         { .reg = 0x00009888, .val = 0x10C80001 },
         { .reg = 0x00009888, .val = 0x04C90008 },
         { .reg = 0x00009888, .val = 0x06C90BA0 },
         { .reg = 0x00009888, .val = 0x08C908A1 },
         { .reg = 0x00009888, .val = 0x0AC90923 },
         { .reg = 0x00009888, .val = 0x0CC909A5 },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext558__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext558__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext558__avg_gpu_core_frequency__max,acmgt1__ext558__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1958, 24, NULL,acmgt1__ext558__slm_byte_write_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1959, 32, NULL,acmgt1__ext558__load_store_cache_byte_write_bank2_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext559_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext559";
   query->symbol_name = "Ext559";
   query->guid = "93bba39f-4d65-434b-9251-37f2badf256e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12E80012 },
         { .reg = 0x00009888, .val = 0x22E90C00 },
         { .reg = 0x00009888, .val = 0x24E90004 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x0AE80180 },
         { .reg = 0x00009888, .val = 0x0CE80105 },
         { .reg = 0x00009888, .val = 0x0EE80083 },
         { .reg = 0x00009888, .val = 0x10E80001 },
         { .reg = 0x00009888, .val = 0x04E90008 },
         { .reg = 0x00009888, .val = 0x06E90BA0 },
         { .reg = 0x00009888, .val = 0x08E908A1 },
         { .reg = 0x00009888, .val = 0x0AE90923 },
         { .reg = 0x00009888, .val = 0x0CE909A5 },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext559__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext559__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext559__avg_gpu_core_frequency__max,acmgt1__ext559__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1960, 24, NULL,acmgt1__ext559__slm_byte_write_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1961, 32, NULL,acmgt1__ext559__load_store_cache_byte_write_bank2_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext560_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext560";
   query->symbol_name = "Ext560";
   query->guid = "a16d5961-ab03-4193-87d9-394ad9c2da80";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13880012 },
         { .reg = 0x00009888, .val = 0x23890C00 },
         { .reg = 0x00009888, .val = 0x25890004 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAA8 },
         { .reg = 0x00009888, .val = 0x01880000 },
         { .reg = 0x00009888, .val = 0x0B880180 },
         { .reg = 0x00009888, .val = 0x0D880105 },
         { .reg = 0x00009888, .val = 0x0F880083 },
         { .reg = 0x00009888, .val = 0x11880001 },
         { .reg = 0x00009888, .val = 0x05890008 },
         { .reg = 0x00009888, .val = 0x07890BA0 },
         { .reg = 0x00009888, .val = 0x098908A1 },
         { .reg = 0x00009888, .val = 0x0B890923 },
         { .reg = 0x00009888, .val = 0x0D8909A5 },
         { .reg = 0x00009888, .val = 0x0189FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext560__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext560__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext560__avg_gpu_core_frequency__max,acmgt1__ext560__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1962, 24, NULL,acmgt1__ext560__slm_byte_write_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1963, 32, NULL,acmgt1__ext560__load_store_cache_byte_write_bank2_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext561_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext561";
   query->symbol_name = "Ext561";
   query->guid = "8dfd3f4a-0686-48bb-94cf-76a3bc5386ec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13A80012 },
         { .reg = 0x00009888, .val = 0x23A90C00 },
         { .reg = 0x00009888, .val = 0x25A90004 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAA8 },
         { .reg = 0x00009888, .val = 0x01A4FEFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65554 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAA8 },
         { .reg = 0x00009888, .val = 0x01A80000 },
         { .reg = 0x00009888, .val = 0x0BA80180 },
         { .reg = 0x00009888, .val = 0x0DA80105 },
         { .reg = 0x00009888, .val = 0x0FA80083 },
         { .reg = 0x00009888, .val = 0x11A80001 },
         { .reg = 0x00009888, .val = 0x05A90008 },
         { .reg = 0x00009888, .val = 0x07A90BA0 },
         { .reg = 0x00009888, .val = 0x09A908A1 },
         { .reg = 0x00009888, .val = 0x0BA90923 },
         { .reg = 0x00009888, .val = 0x0DA909A5 },
         { .reg = 0x00009888, .val = 0x01A9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFC },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009888, .val = 0x0101FEFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext561__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext561__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext561__avg_gpu_core_frequency__max,acmgt1__ext561__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1964, 24, NULL,acmgt1__ext561__slm_byte_write_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1965, 32, NULL,acmgt1__ext561__load_store_cache_byte_write_bank2_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext562_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext562";
   query->symbol_name = "Ext562";
   query->guid = "f41e3a7c-de83-46af-8be2-b26c605d1317";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13C80012 },
         { .reg = 0x00009888, .val = 0x23C90C00 },
         { .reg = 0x00009888, .val = 0x25C90004 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAA8 },
         { .reg = 0x00009888, .val = 0x01C4FEFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65554 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAA8 },
         { .reg = 0x00009888, .val = 0x01C80000 },
         { .reg = 0x00009888, .val = 0x0BC80180 },
         { .reg = 0x00009888, .val = 0x0DC80105 },
         { .reg = 0x00009888, .val = 0x0FC80083 },
         { .reg = 0x00009888, .val = 0x11C80001 },
         { .reg = 0x00009888, .val = 0x05C90008 },
         { .reg = 0x00009888, .val = 0x07C90BA0 },
         { .reg = 0x00009888, .val = 0x09C908A1 },
         { .reg = 0x00009888, .val = 0x0BC90923 },
         { .reg = 0x00009888, .val = 0x0DC909A5 },
         { .reg = 0x00009888, .val = 0x01C9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA8 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009888, .val = 0x0102FEFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext562__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext562__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext562__avg_gpu_core_frequency__max,acmgt1__ext562__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1966, 24, NULL,acmgt1__ext562__slm_byte_write_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1967, 32, NULL,acmgt1__ext562__load_store_cache_byte_write_bank2_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext563_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext563";
   query->symbol_name = "Ext563";
   query->guid = "c599736d-1b09-4ae6-9e82-c98d17c3582a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13E80012 },
         { .reg = 0x00009888, .val = 0x23E90C00 },
         { .reg = 0x00009888, .val = 0x25E90004 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAA8 },
         { .reg = 0x00009888, .val = 0x01E80000 },
         { .reg = 0x00009888, .val = 0x0BE80180 },
         { .reg = 0x00009888, .val = 0x0DE80105 },
         { .reg = 0x00009888, .val = 0x0FE80083 },
         { .reg = 0x00009888, .val = 0x11E80001 },
         { .reg = 0x00009888, .val = 0x05E90008 },
         { .reg = 0x00009888, .val = 0x07E90BA0 },
         { .reg = 0x00009888, .val = 0x09E908A1 },
         { .reg = 0x00009888, .val = 0x0BE90923 },
         { .reg = 0x00009888, .val = 0x0DE909A5 },
         { .reg = 0x00009888, .val = 0x01E9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext563__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext563__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext563__avg_gpu_core_frequency__max,acmgt1__ext563__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1968, 24, NULL,acmgt1__ext563__slm_byte_write_bank2_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1969, 32, NULL,acmgt1__ext563__load_store_cache_byte_write_bank2_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext564_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext564";
   query->symbol_name = "Ext564";
   query->guid = "0f9c5fb0-e5bc-4119-a11f-d32d0304bca8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16880012 },
         { .reg = 0x00009888, .val = 0x28891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0A880580 },
         { .reg = 0x00009888, .val = 0x0C880515 },
         { .reg = 0x00009888, .val = 0x0E880493 },
         { .reg = 0x00009888, .val = 0x10880411 },
         { .reg = 0x00009888, .val = 0x04890200 },
         { .reg = 0x00009888, .val = 0x06890FB0 },
         { .reg = 0x00009888, .val = 0x08890CB1 },
         { .reg = 0x00009888, .val = 0x0A890D33 },
         { .reg = 0x00009888, .val = 0x0C890DB5 },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext564__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext564__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext564__avg_gpu_core_frequency__max,acmgt1__ext564__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1970, 24, NULL,acmgt1__ext564__slm_byte_write_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1971, 32, NULL,acmgt1__ext564__load_store_cache_byte_write_bank3_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext565_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext565";
   query->symbol_name = "Ext565";
   query->guid = "def2b365-d8d1-4e4b-b832-39afd5e214d9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A80012 },
         { .reg = 0x00009888, .val = 0x28A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80580 },
         { .reg = 0x00009888, .val = 0x0CA80515 },
         { .reg = 0x00009888, .val = 0x0EA80493 },
         { .reg = 0x00009888, .val = 0x10A80411 },
         { .reg = 0x00009888, .val = 0x04A90200 },
         { .reg = 0x00009888, .val = 0x06A90FB0 },
         { .reg = 0x00009888, .val = 0x08A90CB1 },
         { .reg = 0x00009888, .val = 0x0AA90D33 },
         { .reg = 0x00009888, .val = 0x0CA90DB5 },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext565__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext565__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext565__avg_gpu_core_frequency__max,acmgt1__ext565__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1972, 24, NULL,acmgt1__ext565__slm_byte_write_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1973, 32, NULL,acmgt1__ext565__load_store_cache_byte_write_bank3_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext566_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext566";
   query->symbol_name = "Ext566";
   query->guid = "a53e91c2-03b4-488a-ab7e-293f4466e00f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C80012 },
         { .reg = 0x00009888, .val = 0x28C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x0AC80580 },
         { .reg = 0x00009888, .val = 0x0CC80515 },
         { .reg = 0x00009888, .val = 0x0EC80493 },
         { .reg = 0x00009888, .val = 0x10C80411 },
         { .reg = 0x00009888, .val = 0x04C90200 },
         { .reg = 0x00009888, .val = 0x06C90FB0 },
         { .reg = 0x00009888, .val = 0x08C90CB1 },
         { .reg = 0x00009888, .val = 0x0AC90D33 },
         { .reg = 0x00009888, .val = 0x0CC90DB5 },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext566__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext566__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext566__avg_gpu_core_frequency__max,acmgt1__ext566__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1974, 24, NULL,acmgt1__ext566__slm_byte_write_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1975, 32, NULL,acmgt1__ext566__load_store_cache_byte_write_bank3_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext567_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext567";
   query->symbol_name = "Ext567";
   query->guid = "0cdefa4f-f4ac-4072-a021-be48ed5b0ee7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E80012 },
         { .reg = 0x00009888, .val = 0x28E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0AE80580 },
         { .reg = 0x00009888, .val = 0x0CE80515 },
         { .reg = 0x00009888, .val = 0x0EE80493 },
         { .reg = 0x00009888, .val = 0x10E80411 },
         { .reg = 0x00009888, .val = 0x04E90200 },
         { .reg = 0x00009888, .val = 0x06E90FB0 },
         { .reg = 0x00009888, .val = 0x08E90CB1 },
         { .reg = 0x00009888, .val = 0x0AE90D33 },
         { .reg = 0x00009888, .val = 0x0CE90DB5 },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext567__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext567__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext567__avg_gpu_core_frequency__max,acmgt1__ext567__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1976, 24, NULL,acmgt1__ext567__slm_byte_write_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1977, 32, NULL,acmgt1__ext567__load_store_cache_byte_write_bank3_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext568_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext568";
   query->symbol_name = "Ext568";
   query->guid = "7404a462-f9c0-4fb6-9ec9-b03bbd5e4572";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17880012 },
         { .reg = 0x00009888, .val = 0x29891060 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAA8 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0B880580 },
         { .reg = 0x00009888, .val = 0x0D880515 },
         { .reg = 0x00009888, .val = 0x0F880493 },
         { .reg = 0x00009888, .val = 0x11880411 },
         { .reg = 0x00009888, .val = 0x05890200 },
         { .reg = 0x00009888, .val = 0x07890FB0 },
         { .reg = 0x00009888, .val = 0x09890CB1 },
         { .reg = 0x00009888, .val = 0x0B890D33 },
         { .reg = 0x00009888, .val = 0x0D890DB5 },
         { .reg = 0x00009888, .val = 0x0189FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext568__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext568__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext568__avg_gpu_core_frequency__max,acmgt1__ext568__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1978, 24, NULL,acmgt1__ext568__slm_byte_write_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1979, 32, NULL,acmgt1__ext568__load_store_cache_byte_write_bank3_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext569_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext569";
   query->symbol_name = "Ext569";
   query->guid = "b3515130-788c-4d36-b20d-e8ca02e11cf1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17A80012 },
         { .reg = 0x00009888, .val = 0x29A91060 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAA8 },
         { .reg = 0x00009888, .val = 0x01A4FEFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65554 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAA8 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80580 },
         { .reg = 0x00009888, .val = 0x0DA80515 },
         { .reg = 0x00009888, .val = 0x0FA80493 },
         { .reg = 0x00009888, .val = 0x11A80411 },
         { .reg = 0x00009888, .val = 0x05A90200 },
         { .reg = 0x00009888, .val = 0x07A90FB0 },
         { .reg = 0x00009888, .val = 0x09A90CB1 },
         { .reg = 0x00009888, .val = 0x0BA90D33 },
         { .reg = 0x00009888, .val = 0x0DA90DB5 },
         { .reg = 0x00009888, .val = 0x01A9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFC },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009888, .val = 0x0101FEFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext569__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext569__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext569__avg_gpu_core_frequency__max,acmgt1__ext569__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1980, 24, NULL,acmgt1__ext569__slm_byte_write_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1981, 32, NULL,acmgt1__ext569__load_store_cache_byte_write_bank3_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext570_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext570";
   query->symbol_name = "Ext570";
   query->guid = "73e5a9f9-ca88-4467-b407-737e7c7080fe";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17C80012 },
         { .reg = 0x00009888, .val = 0x29C91060 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAA8 },
         { .reg = 0x00009888, .val = 0x01C4FEFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65554 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAA8 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x0BC80580 },
         { .reg = 0x00009888, .val = 0x0DC80515 },
         { .reg = 0x00009888, .val = 0x0FC80493 },
         { .reg = 0x00009888, .val = 0x11C80411 },
         { .reg = 0x00009888, .val = 0x05C90200 },
         { .reg = 0x00009888, .val = 0x07C90FB0 },
         { .reg = 0x00009888, .val = 0x09C90CB1 },
         { .reg = 0x00009888, .val = 0x0BC90D33 },
         { .reg = 0x00009888, .val = 0x0DC90DB5 },
         { .reg = 0x00009888, .val = 0x01C9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA8 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009888, .val = 0x0102FEFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext570__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext570__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext570__avg_gpu_core_frequency__max,acmgt1__ext570__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1982, 24, NULL,acmgt1__ext570__slm_byte_write_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1983, 32, NULL,acmgt1__ext570__load_store_cache_byte_write_bank3_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext571_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext571";
   query->symbol_name = "Ext571";
   query->guid = "ae2fa4f6-2afb-4ac9-866e-bfd943f91a54";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E80012 },
         { .reg = 0x00009888, .val = 0x29E91060 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAA8 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0BE80580 },
         { .reg = 0x00009888, .val = 0x0DE80515 },
         { .reg = 0x00009888, .val = 0x0FE80493 },
         { .reg = 0x00009888, .val = 0x11E80411 },
         { .reg = 0x00009888, .val = 0x05E90200 },
         { .reg = 0x00009888, .val = 0x07E90FB0 },
         { .reg = 0x00009888, .val = 0x09E90CB1 },
         { .reg = 0x00009888, .val = 0x0BE90D33 },
         { .reg = 0x00009888, .val = 0x0DE90DB5 },
         { .reg = 0x00009888, .val = 0x01E9FE00 },
         { .reg = 0x00009888, .val = 0x0003FEFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA8 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0004FEFF },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2A030000 },
         { .reg = 0x00009888, .val = 0x48030201 },
         { .reg = 0x00009888, .val = 0x4A030010 },
         { .reg = 0x00009888, .val = 0x4C030201 },
         { .reg = 0x00009888, .val = 0x4E030010 },
         { .reg = 0x00009888, .val = 0x50030001 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x52030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x24030000 },
         { .reg = 0x00009888, .val = 0x28030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x64030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext571__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext571__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext571__avg_gpu_core_frequency__max,acmgt1__ext571__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1984, 24, NULL,acmgt1__ext571__slm_byte_write_bank3_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1985, 32, NULL,acmgt1__ext571__load_store_cache_byte_write_bank3_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext1000_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1000";
   query->symbol_name = "Ext1000";
   query->guid = "cea714fc-17a9-4dae-b3e8-8be0f3149918";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00002009 },
         { .reg = 0x0000E758, .val = 0x01008001 },
         { .reg = 0x0000E45C, .val = 0x0000300A },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext1000__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext1000__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext1000__avg_gpu_core_frequency__max,acmgt1__ext1000__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 764, 24, percentage_max_float,acmgt1__ext1000__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 28, percentage_max_float,acmgt1__ext1000__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 32, percentage_max_float,acmgt1__ext1000__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 771, 40, acmgt1__ext1000__xve_inst_executed_alu0_all__max,acmgt1__ext1000__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 772, 48, acmgt1__ext1000__xve_inst_executed_alu1_all__max,acmgt1__ext1000__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 773, 56, acmgt1__ext1000__xve_inst_executed_xmx_all__max,acmgt1__ext1000__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 774, 64, acmgt1__ext1000__xve_inst_executed_send_all__max,acmgt1__ext1000__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 775, 72, acmgt1__ext1000__xve_inst_executed_control_all__max,acmgt1__ext1000__xve_inst_executed_control_all__read);

      intel_perf_query_add_counter_float(query, 776, 80, percentage_max_float,acmgt1__ext1000__xve_pipe_alu0_and_alu1_active__read);

      intel_perf_query_add_counter_float(query, 777, 84, percentage_max_float,acmgt1__ext1000__xve_pipe_alu0_and_xmx_active__read);

      intel_perf_query_add_counter_float(query, 778, 88, percentage_max_float,acmgt1__ext1000__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 779, 92, percentage_max_float,acmgt1__ext1000__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 782, 96, percentage_max_float,acmgt1__ext1000__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 780, 100, percentage_max_float,acmgt1__ext1000__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 781, 104, percentage_max_float,acmgt1__ext1000__xve_inst_executed_control_all_utilization__read);

      intel_perf_query_add_counter_uint64(query, 1986, 112, acmgt1__ext1000__xve_active_cycles__max,acmgt1__ext1000__xve_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 1987, 120, acmgt1__ext1000__xve_stall_cycles__max,acmgt1__ext1000__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 1988, 128, acmgt1__ext1000__xve_threads_occupancy_cycles_all__max,acmgt1__ext1000__xve_threads_occupancy_cycles_all__read);

      intel_perf_query_add_counter_uint64(query, 1989, 136, acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max,acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 1990, 144, acmgt1__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max,acmgt1__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext1001_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Ext1001";
   query->symbol_name = "Ext1001";
   query->guid = "3ec074a8-e3cb-4090-86c0-0d1426ac9a63";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00020010 },
         { .reg = 0x0000E558, .val = 0x00050030 },
         { .reg = 0x0000E658, .val = 0x00090060 },
         { .reg = 0x0000E758, .val = 0x00031011 },
         { .reg = 0x0000E45C, .val = 0x00051021 },
         { .reg = 0x0000E55C, .val = 0x00091061 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext1001__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext1001__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext1001__avg_gpu_core_frequency__max,acmgt1__ext1001__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1991, 24, acmgt1__ext1001__xve_inst_executed_alu0_vs__max,acmgt1__ext1001__xve_inst_executed_alu0_vs__read);

      intel_perf_query_add_counter_uint64(query, 1992, 32, acmgt1__ext1001__xve_inst_executed_alu0_hs__max,acmgt1__ext1001__xve_inst_executed_alu0_hs__read);

      intel_perf_query_add_counter_uint64(query, 1993, 40, acmgt1__ext1001__xve_inst_executed_alu0_ds__max,acmgt1__ext1001__xve_inst_executed_alu0_ds__read);

      intel_perf_query_add_counter_uint64(query, 1994, 48, acmgt1__ext1001__xve_inst_executed_alu0_ps__max,acmgt1__ext1001__xve_inst_executed_alu0_ps__read);

      intel_perf_query_add_counter_uint64(query, 1995, 56, acmgt1__ext1001__xve_inst_executed_alu0_cs__max,acmgt1__ext1001__xve_inst_executed_alu0_cs__read);

      intel_perf_query_add_counter_uint64(query, 1996, 64, acmgt1__ext1001__xve_inst_executed_alu0_async_cs__max,acmgt1__ext1001__xve_inst_executed_alu0_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 1997, 72, acmgt1__ext1001__xve_inst_executed_alu1_vs__max,acmgt1__ext1001__xve_inst_executed_alu1_vs__read);

      intel_perf_query_add_counter_uint64(query, 1998, 80, acmgt1__ext1001__xve_inst_executed_alu1_hs__max,acmgt1__ext1001__xve_inst_executed_alu1_hs__read);

      intel_perf_query_add_counter_uint64(query, 1999, 88, acmgt1__ext1001__xve_inst_executed_alu1_ds__max,acmgt1__ext1001__xve_inst_executed_alu1_ds__read);

      intel_perf_query_add_counter_uint64(query, 2000, 96, acmgt1__ext1001__xve_inst_executed_alu1_ps__max,acmgt1__ext1001__xve_inst_executed_alu1_ps__read);

      intel_perf_query_add_counter_uint64(query, 2001, 104, acmgt1__ext1001__xve_inst_executed_alu1_cs__max,acmgt1__ext1001__xve_inst_executed_alu1_cs__read);

      intel_perf_query_add_counter_uint64(query, 2002, 112, acmgt1__ext1001__xve_inst_executed_alu1_async_cs__max,acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read);

      intel_perf_query_add_counter_float(query, 2003, 120, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu0_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 2004, 124, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu0_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 2005, 128, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu0_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 2006, 132, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu0_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 2007, 136, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu0_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2008, 140, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu0_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2009, 144, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu1_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 2010, 148, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu1_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 2011, 152, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu1_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 2012, 156, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu1_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 2013, 160, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu1_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2014, 164, percentage_max_float,acmgt1__ext1001__xve_inst_executed_alu1_async_cs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext1002_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "Ext1002";
   query->symbol_name = "Ext1002";
   query->guid = "17275fa7-be46-48a6-a654-6931ecbfed77";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x000C10C0 },
         { .reg = 0x0000E558, .val = 0x000D00C2 },
         { .reg = 0x0000E658, .val = 0x000D20D1 },
         { .reg = 0x0000E758, .val = 0x000E10E0 },
         { .reg = 0x0000E45C, .val = 0x000000E2 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext1002__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext1002__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext1002__avg_gpu_core_frequency__max,acmgt1__ext1002__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 2015, 24, percentage_max_float,acmgt1__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 2016, 28, percentage_max_float,acmgt1__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 2017, 32, percentage_max_float,acmgt1__ext1002__xve_inst_executed_send_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 2018, 36, percentage_max_float,acmgt1__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 2019, 40, percentage_max_float,acmgt1__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 2020, 44, percentage_max_float,acmgt1__ext1002__xve_inst_executed_send_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 2021, 48, percentage_max_float,acmgt1__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2022, 52, percentage_max_float,acmgt1__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2023, 56, percentage_max_float,acmgt1__ext1002__xve_inst_executed_send_rt_ms_utilization__read);

      intel_perf_query_add_counter_uint64(query, 2024, 64, acmgt1__ext1002__xve_inst_executed_alu0_rt_ahs__max,acmgt1__ext1002__xve_inst_executed_alu0_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 2025, 72, acmgt1__ext1002__xve_inst_executed_alu1_rt_ahs__max,acmgt1__ext1002__xve_inst_executed_alu1_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 2026, 80, acmgt1__ext1002__xve_inst_executed_send_rt_ahs__max,acmgt1__ext1002__xve_inst_executed_send_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 2027, 88, acmgt1__ext1002__xve_inst_executed_alu0_rt_chs__max,acmgt1__ext1002__xve_inst_executed_alu0_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 2028, 96, acmgt1__ext1002__xve_inst_executed_alu1_rt_chs__max,acmgt1__ext1002__xve_inst_executed_alu1_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 2029, 104, acmgt1__ext1002__xve_inst_executed_send_rt_chs__max,acmgt1__ext1002__xve_inst_executed_send_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 2030, 112, acmgt1__ext1002__xve_inst_executed_alu0_rt_ms__max,acmgt1__ext1002__xve_inst_executed_alu0_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 2031, 120, acmgt1__ext1002__xve_inst_executed_alu1_rt_ms__max,acmgt1__ext1002__xve_inst_executed_alu1_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 2032, 128, acmgt1__ext1002__xve_inst_executed_send_rt_ms__max,acmgt1__ext1002__xve_inst_executed_send_rt_ms__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext1004_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1004";
   query->symbol_name = "Ext1004";
   query->guid = "a56f028c-27c7-4e9b-bc19-04bbf67444b0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00015005 },
         { .reg = 0x0000E558, .val = 0x000550A5 },
         { .reg = 0x0000E658, .val = 0x000250B5 },
         { .reg = 0x0000E758, .val = 0x00065035 },
         { .reg = 0x0000E45C, .val = 0x00000095 },
         { .reg = 0x0000E55C, .val = 0x000C5000 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext1004__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext1004__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext1004__avg_gpu_core_frequency__max,acmgt1__ext1004__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 765, 24, percentage_max_float,acmgt1__ext1004__xve_stall__read);

      intel_perf_query_add_counter_float(query, 2033, 28, percentage_max_float,acmgt1__ext1004__xve_stall_async_cs__read);

      intel_perf_query_add_counter_float(query, 2034, 32, percentage_max_float,acmgt1__ext1004__xve_stall_cs__read);

      intel_perf_query_add_counter_float(query, 2035, 36, percentage_max_float,acmgt1__ext1004__xve_stall_ds__read);

      intel_perf_query_add_counter_float(query, 2036, 40, percentage_max_float,acmgt1__ext1004__xve_stall_hs__read);

      intel_perf_query_add_counter_float(query, 2037, 44, percentage_max_float,acmgt1__ext1004__xve_stall_ms__read);

      intel_perf_query_add_counter_float(query, 2038, 48, percentage_max_float,acmgt1__ext1004__xve_stall_ps__read);

      intel_perf_query_add_counter_float(query, 2039, 52, percentage_max_float,acmgt1__ext1004__xve_stall_ts__read);

      intel_perf_query_add_counter_float(query, 2040, 56, percentage_max_float,acmgt1__ext1004__xve_stall_vs__read);

      intel_perf_query_add_counter_float(query, 2041, 60, percentage_max_float,acmgt1__ext1004__xve_stall_rt__read);

      intel_perf_query_add_counter_uint64(query, 1987, 64, acmgt1__ext1004__xve_stall_cycles__max,acmgt1__ext1004__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 2042, 72, acmgt1__ext1004__xve_stall_cycles_async_cs__max,acmgt1__ext1004__xve_stall_cycles_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 2043, 80, acmgt1__ext1004__xve_stall_cycles_cs__max,acmgt1__ext1004__xve_stall_cycles_cs__read);

      intel_perf_query_add_counter_uint64(query, 2044, 88, acmgt1__ext1004__xve_stall_cycles_ds__max,acmgt1__ext1004__xve_stall_cycles_ds__read);

      intel_perf_query_add_counter_uint64(query, 2045, 96, acmgt1__ext1004__xve_stall_cycles_hs__max,acmgt1__ext1004__xve_stall_cycles_hs__read);

      intel_perf_query_add_counter_uint64(query, 2046, 104, acmgt1__ext1004__xve_stall_cycles_ms__max,acmgt1__ext1004__xve_stall_cycles_ms__read);

      intel_perf_query_add_counter_uint64(query, 2047, 112, acmgt1__ext1004__xve_stall_cycles_ps__max,acmgt1__ext1004__xve_stall_cycles_ps__read);

      intel_perf_query_add_counter_uint64(query, 2048, 120, acmgt1__ext1004__xve_stall_cycles_ts__max,acmgt1__ext1004__xve_stall_cycles_ts__read);

      intel_perf_query_add_counter_uint64(query, 2049, 128, acmgt1__ext1004__xve_stall_cycles_vs__max,acmgt1__ext1004__xve_stall_cycles_vs__read);

      intel_perf_query_add_counter_uint64(query, 2050, 136, acmgt1__ext1004__xve_stall_cycles_rt__max,acmgt1__ext1004__xve_stall_cycles_rt__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext1005_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Ext1005";
   query->symbol_name = "Ext1005";
   query->guid = "f43c884f-817d-4037-bc96-7bed64906683";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x0000700B },
         { .reg = 0x0000E558, .val = 0x02000006 },
         { .reg = 0x0000E658, .val = 0x0000C00D },
         { .reg = 0x0000E758, .val = 0x0200200F },
         { .reg = 0x0000E45C, .val = 0x0000000E },
         { .reg = 0x0000E55C, .val = 0x00009001 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext1005__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext1005__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext1005__avg_gpu_core_frequency__max,acmgt1__ext1005__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 771, 24, acmgt1__ext1005__xve_inst_executed_alu0_all__max,acmgt1__ext1005__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 2051, 32, acmgt1__ext1005__xve_inst_executed_fp16__max,acmgt1__ext1005__xve_inst_executed_fp16__read);

      intel_perf_query_add_counter_uint64(query, 2052, 40, acmgt1__ext1005__xve_inst_executed_fp32__max,acmgt1__ext1005__xve_inst_executed_fp32__read);

      intel_perf_query_add_counter_uint64(query, 2053, 48, acmgt1__ext1005__xve_inst_executed_fp64__max,acmgt1__ext1005__xve_inst_executed_fp64__read);

      intel_perf_query_add_counter_uint64(query, 772, 56, acmgt1__ext1005__xve_inst_executed_alu1_all__max,acmgt1__ext1005__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 2054, 64, acmgt1__ext1005__xve_inst_executed_int16__max,acmgt1__ext1005__xve_inst_executed_int16__read);

      intel_perf_query_add_counter_uint64(query, 2055, 72, acmgt1__ext1005__xve_inst_executed_int32__max,acmgt1__ext1005__xve_inst_executed_int32__read);

      intel_perf_query_add_counter_uint64(query, 2056, 80, acmgt1__ext1005__xve_inst_executed_math__max,acmgt1__ext1005__xve_inst_executed_math__read);

      intel_perf_query_add_counter_uint64(query, 773, 88, acmgt1__ext1005__xve_inst_executed_xmx_all__max,acmgt1__ext1005__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 2057, 96, acmgt1__ext1005__xve_inst_executed_xmx_bf16__max,acmgt1__ext1005__xve_inst_executed_xmx_bf16__read);

      intel_perf_query_add_counter_uint64(query, 2058, 104, acmgt1__ext1005__xve_inst_executed_xmx_fp16__max,acmgt1__ext1005__xve_inst_executed_xmx_fp16__read);

      intel_perf_query_add_counter_uint64(query, 2059, 112, acmgt1__ext1005__xve_inst_executed_xmx_int8__max,acmgt1__ext1005__xve_inst_executed_xmx_int8__read);

      intel_perf_query_add_counter_float(query, 778, 120, percentage_max_float,acmgt1__ext1005__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2060, 124, percentage_max_float,acmgt1__ext1005__xve_inst_executed_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 2061, 128, percentage_max_float,acmgt1__ext1005__xve_inst_executed_fp32_utilization__read);

      intel_perf_query_add_counter_float(query, 2062, 132, percentage_max_float,acmgt1__ext1005__xve_inst_executed_fp64_utilization__read);

      intel_perf_query_add_counter_float(query, 779, 136, percentage_max_float,acmgt1__ext1005__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2063, 140, percentage_max_float,acmgt1__ext1005__xve_inst_executed_int16_utilization__read);

      intel_perf_query_add_counter_float(query, 2064, 144, percentage_max_float,acmgt1__ext1005__xve_inst_executed_int32_utilization__read);

      intel_perf_query_add_counter_float(query, 2065, 148, percentage_max_float,acmgt1__ext1005__xve_inst_executed_math_utilization__read);

      intel_perf_query_add_counter_float(query, 782, 152, percentage_max_float,acmgt1__ext1005__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2066, 156, percentage_max_float,acmgt1__ext1005__xve_inst_executed_xmx_bf16_utilization__read);

      intel_perf_query_add_counter_float(query, 2067, 160, percentage_max_float,acmgt1__ext1005__xve_inst_executed_xmx_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 2068, 164, percentage_max_float,acmgt1__ext1005__xve_inst_executed_xmx_int8_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext1006_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1006";
   query->symbol_name = "Ext1006";
   query->guid = "6a6e8e1d-6148-4316-95f9-2a8b5236520f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x000A2012 },
         { .reg = 0x0000E558, .val = 0x000B2052 },
         { .reg = 0x0000E658, .val = 0x00042022 },
         { .reg = 0x0000E758, .val = 0x00062032 },
         { .reg = 0x0000E45C, .val = 0x00002092 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext1006__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext1006__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext1006__avg_gpu_core_frequency__max,acmgt1__ext1006__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 774, 24, acmgt1__ext1006__xve_inst_executed_send_all__max,acmgt1__ext1006__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 2069, 32, acmgt1__ext1006__xve_inst_executed_send_async_cs__max,acmgt1__ext1006__xve_inst_executed_send_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 2070, 40, acmgt1__ext1006__xve_inst_executed_send_cs__max,acmgt1__ext1006__xve_inst_executed_send_cs__read);

      intel_perf_query_add_counter_uint64(query, 2071, 48, acmgt1__ext1006__xve_inst_executed_send_ds__max,acmgt1__ext1006__xve_inst_executed_send_ds__read);

      intel_perf_query_add_counter_uint64(query, 2072, 56, acmgt1__ext1006__xve_inst_executed_send_gs__max,acmgt1__ext1006__xve_inst_executed_send_gs__read);

      intel_perf_query_add_counter_uint64(query, 2073, 64, acmgt1__ext1006__xve_inst_executed_send_hs__max,acmgt1__ext1006__xve_inst_executed_send_hs__read);

      intel_perf_query_add_counter_uint64(query, 2074, 72, acmgt1__ext1006__xve_inst_executed_send_ms__max,acmgt1__ext1006__xve_inst_executed_send_ms__read);

      intel_perf_query_add_counter_uint64(query, 2075, 80, acmgt1__ext1006__xve_inst_executed_send_ps__max,acmgt1__ext1006__xve_inst_executed_send_ps__read);

      intel_perf_query_add_counter_uint64(query, 2076, 88, acmgt1__ext1006__xve_inst_executed_send_ts__max,acmgt1__ext1006__xve_inst_executed_send_ts__read);

      intel_perf_query_add_counter_uint64(query, 2077, 96, acmgt1__ext1006__xve_inst_executed_send_vs__max,acmgt1__ext1006__xve_inst_executed_send_vs__read);

      intel_perf_query_add_counter_float(query, 780, 104, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2078, 108, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2079, 112, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2080, 116, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 2081, 120, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 2082, 124, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 2083, 128, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2084, 132, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 2085, 136, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 2086, 140, percentage_max_float,acmgt1__ext1006__xve_inst_executed_send_vs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext1007_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "Ext1007";
   query->symbol_name = "Ext1007";
   query->guid = "b6b53888-0a0b-4fc6-b77e-c604875495a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00045000 },
         { .reg = 0x0000E558, .val = 0x00040041 },
         { .reg = 0x0000E658, .val = 0x000B10A1 },
         { .reg = 0x0000E758, .val = 0x000B00A0 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext1007__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext1007__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext1007__avg_gpu_core_frequency__max,acmgt1__ext1007__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 2087, 24, percentage_max_float,acmgt1__ext1007__xve_stall_gs__read);

      intel_perf_query_add_counter_uint64(query, 2088, 32, acmgt1__ext1007__xve_inst_executed_alu0_gs__max,acmgt1__ext1007__xve_inst_executed_alu0_gs__read);

      intel_perf_query_add_counter_uint64(query, 2089, 40, acmgt1__ext1007__xve_inst_executed_alu1_gs__max,acmgt1__ext1007__xve_inst_executed_alu1_gs__read);

      intel_perf_query_add_counter_uint64(query, 2090, 48, acmgt1__ext1007__xve_stall_cycles_gs__max,acmgt1__ext1007__xve_stall_cycles_gs__read);

      intel_perf_query_add_counter_uint64(query, 2091, 56, acmgt1__ext1007__xve_inst_executed_alu0_ms__max,acmgt1__ext1007__xve_inst_executed_alu0_ms__read);

      intel_perf_query_add_counter_uint64(query, 2092, 64, acmgt1__ext1007__xve_inst_executed_alu0_ts__max,acmgt1__ext1007__xve_inst_executed_alu0_ts__read);

      intel_perf_query_add_counter_uint64(query, 2093, 72, acmgt1__ext1007__xve_inst_executed_alu1_ms__max,acmgt1__ext1007__xve_inst_executed_alu1_ms__read);

      intel_perf_query_add_counter_uint64(query, 2094, 80, acmgt1__ext1007__xve_inst_executed_alu1_ts__max,acmgt1__ext1007__xve_inst_executed_alu1_ts__read);

      intel_perf_query_add_counter_float(query, 2095, 88, percentage_max_float,acmgt1__ext1007__xve_inst_executed_alu0_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 2096, 92, percentage_max_float,acmgt1__ext1007__xve_inst_executed_alu1_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 2097, 96, percentage_max_float,acmgt1__ext1007__xve_inst_executed_alu0_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2098, 100, percentage_max_float,acmgt1__ext1007__xve_inst_executed_alu0_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 2099, 104, percentage_max_float,acmgt1__ext1007__xve_inst_executed_alu1_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2100, 108, percentage_max_float,acmgt1__ext1007__xve_inst_executed_alu1_ts_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt1_register_ext1010_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext1010";
   query->symbol_name = "Ext1010";
   query->guid = "6e06382a-3c98-464a-9811-cdfb956e4e8e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt1__ext1010__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt1__ext1010__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt1__ext1010__avg_gpu_core_frequency__max,acmgt1__ext1010__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2101, 24, NULL,acmgt1__ext1010__sampler_2_x2_read__read);

      intel_perf_query_add_counter_uint64(query, 2102, 32, NULL,acmgt1__ext1010__pixel_write__read);

      intel_perf_query_add_counter_uint64(query, 2103, 40, NULL,acmgt1__ext1010__pixel_blend__read);

      intel_perf_query_add_counter_uint64(query, 2104, 48, NULL,acmgt1__ext1010__rasterizer_sample_output__read);

      intel_perf_query_add_counter_uint64(query, 2105, 56, NULL,acmgt1__ext1010__postps_depth_stencil_alpha_test_fail__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_acmgt1(struct intel_perf_config *perf)
{
   acmgt1_register_render_basic_counter_query(perf);
   acmgt1_register_compute_basic_counter_query(perf);
   acmgt1_register_threads_and_rast1_counter_query(perf);
   acmgt1_register_threads_and_rast2_counter_query(perf);
   acmgt1_register_threads_and_rast3_counter_query(perf);
   acmgt1_register_threads_and_rast4_counter_query(perf);
   acmgt1_register_async_compute_counter_query(perf);
   acmgt1_register_xve_activity1_counter_query(perf);
   acmgt1_register_gpu_busyness_counter_query(perf);
   acmgt1_register_render_pipe_profile1_counter_query(perf);
   acmgt1_register_render_pipe_profile2_counter_query(perf);
   acmgt1_register_l3_counter_query(perf);
   acmgt1_register_sampler_counter_query(perf);
   acmgt1_register_hdc_and_sf1_counter_query(perf);
   acmgt1_register_hdc_and_sf2_counter_query(perf);
   acmgt1_register_rasterizer_and_pixel_backend1_counter_query(perf);
   acmgt1_register_rasterizer_and_pixel_backend2_counter_query(perf);
   acmgt1_register_tdl1_counter_query(perf);
   acmgt1_register_tdl2_counter_query(perf);
   acmgt1_register_tdl3_counter_query(perf);
   acmgt1_register_tdl4_counter_query(perf);
   acmgt1_register_test_oa_counter_query(perf);
   acmgt1_register_compute_overview_counter_query(perf);
   acmgt1_register_l1_profile_reads__xe_core0_counter_query(perf);
   acmgt1_register_l1_profile_reads__xe_core3_counter_query(perf);
   acmgt1_register_l1_profile_slm_bank_conflicts__xe_core0_counter_query(perf);
   acmgt1_register_l1_profile_slm_bank_conflicts__xe_core3_counter_query(perf);
   acmgt1_register_l1_profile_writes__xe_core0_counter_query(perf);
   acmgt1_register_l1_profile_writes__xe_core3_counter_query(perf);
   acmgt1_register_dataport_reads_counter_query(perf);
   acmgt1_register_dataport_writes_counter_query(perf);
   acmgt1_register_ext1_counter_query(perf);
   acmgt1_register_ext2_counter_query(perf);
   acmgt1_register_ext3_counter_query(perf);
   acmgt1_register_ext4_counter_query(perf);
   acmgt1_register_ext5_counter_query(perf);
   acmgt1_register_ext6_counter_query(perf);
   acmgt1_register_ext7_counter_query(perf);
   acmgt1_register_ext8_counter_query(perf);
   acmgt1_register_ext9_counter_query(perf);
   acmgt1_register_ext10_counter_query(perf);
   acmgt1_register_ext11_counter_query(perf);
   acmgt1_register_ext12_counter_query(perf);
   acmgt1_register_ext13_counter_query(perf);
   acmgt1_register_ext14_counter_query(perf);
   acmgt1_register_ext15_counter_query(perf);
   acmgt1_register_ext16_counter_query(perf);
   acmgt1_register_ext17_counter_query(perf);
   acmgt1_register_ext18_counter_query(perf);
   acmgt1_register_ext19_counter_query(perf);
   acmgt1_register_ext20_counter_query(perf);
   acmgt1_register_ext21_counter_query(perf);
   acmgt1_register_ext22_counter_query(perf);
   acmgt1_register_ext23_counter_query(perf);
   acmgt1_register_ext24_counter_query(perf);
   acmgt1_register_ext25_counter_query(perf);
   acmgt1_register_ext26_counter_query(perf);
   acmgt1_register_ext27_counter_query(perf);
   acmgt1_register_ext28_counter_query(perf);
   acmgt1_register_ext29_counter_query(perf);
   acmgt1_register_ext30_counter_query(perf);
   acmgt1_register_ext31_counter_query(perf);
   acmgt1_register_ext32_counter_query(perf);
   acmgt1_register_ext33_counter_query(perf);
   acmgt1_register_ext34_counter_query(perf);
   acmgt1_register_ext35_counter_query(perf);
   acmgt1_register_ext36_counter_query(perf);
   acmgt1_register_ext37_counter_query(perf);
   acmgt1_register_ext38_counter_query(perf);
   acmgt1_register_ext39_counter_query(perf);
   acmgt1_register_ext40_counter_query(perf);
   acmgt1_register_ext41_counter_query(perf);
   acmgt1_register_ext42_counter_query(perf);
   acmgt1_register_ext43_counter_query(perf);
   acmgt1_register_ext44_counter_query(perf);
   acmgt1_register_ext45_counter_query(perf);
   acmgt1_register_ext46_counter_query(perf);
   acmgt1_register_ext47_counter_query(perf);
   acmgt1_register_ext48_counter_query(perf);
   acmgt1_register_ext49_counter_query(perf);
   acmgt1_register_ext50_counter_query(perf);
   acmgt1_register_ext51_counter_query(perf);
   acmgt1_register_ext52_counter_query(perf);
   acmgt1_register_ext53_counter_query(perf);
   acmgt1_register_ext54_counter_query(perf);
   acmgt1_register_ext55_counter_query(perf);
   acmgt1_register_ext56_counter_query(perf);
   acmgt1_register_ext57_counter_query(perf);
   acmgt1_register_ext58_counter_query(perf);
   acmgt1_register_ext59_counter_query(perf);
   acmgt1_register_ext60_counter_query(perf);
   acmgt1_register_ext61_counter_query(perf);
   acmgt1_register_ext62_counter_query(perf);
   acmgt1_register_ext63_counter_query(perf);
   acmgt1_register_ext64_counter_query(perf);
   acmgt1_register_ext65_counter_query(perf);
   acmgt1_register_ext66_counter_query(perf);
   acmgt1_register_ext67_counter_query(perf);
   acmgt1_register_ext68_counter_query(perf);
   acmgt1_register_ext69_counter_query(perf);
   acmgt1_register_ext70_counter_query(perf);
   acmgt1_register_ext71_counter_query(perf);
   acmgt1_register_ext72_counter_query(perf);
   acmgt1_register_ext73_counter_query(perf);
   acmgt1_register_ext74_counter_query(perf);
   acmgt1_register_ext75_counter_query(perf);
   acmgt1_register_ext76_counter_query(perf);
   acmgt1_register_ext77_counter_query(perf);
   acmgt1_register_ext78_counter_query(perf);
   acmgt1_register_ext79_counter_query(perf);
   acmgt1_register_ext80_counter_query(perf);
   acmgt1_register_ext81_counter_query(perf);
   acmgt1_register_ext82_counter_query(perf);
   acmgt1_register_ext83_counter_query(perf);
   acmgt1_register_ext84_counter_query(perf);
   acmgt1_register_ext85_counter_query(perf);
   acmgt1_register_ext86_counter_query(perf);
   acmgt1_register_ext87_counter_query(perf);
   acmgt1_register_ext88_counter_query(perf);
   acmgt1_register_ext91_counter_query(perf);
   acmgt1_register_ext92_counter_query(perf);
   acmgt1_register_ext93_counter_query(perf);
   acmgt1_register_ext94_counter_query(perf);
   acmgt1_register_ext95_counter_query(perf);
   acmgt1_register_ext96_counter_query(perf);
   acmgt1_register_ext97_counter_query(perf);
   acmgt1_register_ext98_counter_query(perf);
   acmgt1_register_ext99_counter_query(perf);
   acmgt1_register_ext100_counter_query(perf);
   acmgt1_register_ext101_counter_query(perf);
   acmgt1_register_ext102_counter_query(perf);
   acmgt1_register_ext103_counter_query(perf);
   acmgt1_register_ext104_counter_query(perf);
   acmgt1_register_ext105_counter_query(perf);
   acmgt1_register_ext106_counter_query(perf);
   acmgt1_register_ext107_counter_query(perf);
   acmgt1_register_ext108_counter_query(perf);
   acmgt1_register_ext109_counter_query(perf);
   acmgt1_register_ext110_counter_query(perf);
   acmgt1_register_ext111_counter_query(perf);
   acmgt1_register_ext112_counter_query(perf);
   acmgt1_register_ext113_counter_query(perf);
   acmgt1_register_ext114_counter_query(perf);
   acmgt1_register_ext115_counter_query(perf);
   acmgt1_register_ext116_counter_query(perf);
   acmgt1_register_ext117_counter_query(perf);
   acmgt1_register_ext118_counter_query(perf);
   acmgt1_register_ext119_counter_query(perf);
   acmgt1_register_ext120_counter_query(perf);
   acmgt1_register_ext121_counter_query(perf);
   acmgt1_register_ext122_counter_query(perf);
   acmgt1_register_ext123_counter_query(perf);
   acmgt1_register_ext124_counter_query(perf);
   acmgt1_register_ext125_counter_query(perf);
   acmgt1_register_ext126_counter_query(perf);
   acmgt1_register_ext127_counter_query(perf);
   acmgt1_register_ext128_counter_query(perf);
   acmgt1_register_ext129_counter_query(perf);
   acmgt1_register_ext130_counter_query(perf);
   acmgt1_register_ext131_counter_query(perf);
   acmgt1_register_ext132_counter_query(perf);
   acmgt1_register_ext133_counter_query(perf);
   acmgt1_register_ext134_counter_query(perf);
   acmgt1_register_ext135_counter_query(perf);
   acmgt1_register_ext136_counter_query(perf);
   acmgt1_register_ext137_counter_query(perf);
   acmgt1_register_ext138_counter_query(perf);
   acmgt1_register_ext139_counter_query(perf);
   acmgt1_register_ext140_counter_query(perf);
   acmgt1_register_ext141_counter_query(perf);
   acmgt1_register_ext142_counter_query(perf);
   acmgt1_register_ext143_counter_query(perf);
   acmgt1_register_ext144_counter_query(perf);
   acmgt1_register_ext145_counter_query(perf);
   acmgt1_register_ext146_counter_query(perf);
   acmgt1_register_ext147_counter_query(perf);
   acmgt1_register_ext148_counter_query(perf);
   acmgt1_register_ext149_counter_query(perf);
   acmgt1_register_ext150_counter_query(perf);
   acmgt1_register_ext151_counter_query(perf);
   acmgt1_register_ext152_counter_query(perf);
   acmgt1_register_ext153_counter_query(perf);
   acmgt1_register_ext154_counter_query(perf);
   acmgt1_register_ext155_counter_query(perf);
   acmgt1_register_ext156_counter_query(perf);
   acmgt1_register_ext157_counter_query(perf);
   acmgt1_register_ext158_counter_query(perf);
   acmgt1_register_ext159_counter_query(perf);
   acmgt1_register_ext160_counter_query(perf);
   acmgt1_register_ext161_counter_query(perf);
   acmgt1_register_ext162_counter_query(perf);
   acmgt1_register_ext163_counter_query(perf);
   acmgt1_register_ext164_counter_query(perf);
   acmgt1_register_ext165_counter_query(perf);
   acmgt1_register_ext166_counter_query(perf);
   acmgt1_register_ext167_counter_query(perf);
   acmgt1_register_ext168_counter_query(perf);
   acmgt1_register_ext169_counter_query(perf);
   acmgt1_register_ext170_counter_query(perf);
   acmgt1_register_ext171_counter_query(perf);
   acmgt1_register_ext172_counter_query(perf);
   acmgt1_register_ext173_counter_query(perf);
   acmgt1_register_ext174_counter_query(perf);
   acmgt1_register_ext175_counter_query(perf);
   acmgt1_register_ext176_counter_query(perf);
   acmgt1_register_ext177_counter_query(perf);
   acmgt1_register_ext178_counter_query(perf);
   acmgt1_register_ext179_counter_query(perf);
   acmgt1_register_ext180_counter_query(perf);
   acmgt1_register_ext181_counter_query(perf);
   acmgt1_register_ext182_counter_query(perf);
   acmgt1_register_ext183_counter_query(perf);
   acmgt1_register_ext184_counter_query(perf);
   acmgt1_register_ext185_counter_query(perf);
   acmgt1_register_ext186_counter_query(perf);
   acmgt1_register_ext187_counter_query(perf);
   acmgt1_register_ext188_counter_query(perf);
   acmgt1_register_ext189_counter_query(perf);
   acmgt1_register_ext190_counter_query(perf);
   acmgt1_register_ext191_counter_query(perf);
   acmgt1_register_ext192_counter_query(perf);
   acmgt1_register_ext193_counter_query(perf);
   acmgt1_register_ext194_counter_query(perf);
   acmgt1_register_ext195_counter_query(perf);
   acmgt1_register_ext196_counter_query(perf);
   acmgt1_register_ext197_counter_query(perf);
   acmgt1_register_ext198_counter_query(perf);
   acmgt1_register_ext199_counter_query(perf);
   acmgt1_register_ext200_counter_query(perf);
   acmgt1_register_ext201_counter_query(perf);
   acmgt1_register_ext202_counter_query(perf);
   acmgt1_register_ext203_counter_query(perf);
   acmgt1_register_ext204_counter_query(perf);
   acmgt1_register_ext205_counter_query(perf);
   acmgt1_register_ext206_counter_query(perf);
   acmgt1_register_ext207_counter_query(perf);
   acmgt1_register_ext208_counter_query(perf);
   acmgt1_register_ext209_counter_query(perf);
   acmgt1_register_ext210_counter_query(perf);
   acmgt1_register_ext211_counter_query(perf);
   acmgt1_register_ext212_counter_query(perf);
   acmgt1_register_ext213_counter_query(perf);
   acmgt1_register_ext214_counter_query(perf);
   acmgt1_register_ext215_counter_query(perf);
   acmgt1_register_ext216_counter_query(perf);
   acmgt1_register_ext217_counter_query(perf);
   acmgt1_register_ext218_counter_query(perf);
   acmgt1_register_ext219_counter_query(perf);
   acmgt1_register_ext220_counter_query(perf);
   acmgt1_register_ext221_counter_query(perf);
   acmgt1_register_ext222_counter_query(perf);
   acmgt1_register_ext223_counter_query(perf);
   acmgt1_register_ext224_counter_query(perf);
   acmgt1_register_ext225_counter_query(perf);
   acmgt1_register_ext226_counter_query(perf);
   acmgt1_register_ext227_counter_query(perf);
   acmgt1_register_ext228_counter_query(perf);
   acmgt1_register_ext229_counter_query(perf);
   acmgt1_register_ext230_counter_query(perf);
   acmgt1_register_ext231_counter_query(perf);
   acmgt1_register_ext232_counter_query(perf);
   acmgt1_register_ext233_counter_query(perf);
   acmgt1_register_ext234_counter_query(perf);
   acmgt1_register_ext235_counter_query(perf);
   acmgt1_register_ext236_counter_query(perf);
   acmgt1_register_ext237_counter_query(perf);
   acmgt1_register_ext238_counter_query(perf);
   acmgt1_register_ext239_counter_query(perf);
   acmgt1_register_ext240_counter_query(perf);
   acmgt1_register_ext500_counter_query(perf);
   acmgt1_register_ext501_counter_query(perf);
   acmgt1_register_ext502_counter_query(perf);
   acmgt1_register_ext503_counter_query(perf);
   acmgt1_register_ext508_counter_query(perf);
   acmgt1_register_ext509_counter_query(perf);
   acmgt1_register_ext510_counter_query(perf);
   acmgt1_register_ext511_counter_query(perf);
   acmgt1_register_ext512_counter_query(perf);
   acmgt1_register_ext513_counter_query(perf);
   acmgt1_register_ext514_counter_query(perf);
   acmgt1_register_ext515_counter_query(perf);
   acmgt1_register_ext516_counter_query(perf);
   acmgt1_register_ext517_counter_query(perf);
   acmgt1_register_ext518_counter_query(perf);
   acmgt1_register_ext519_counter_query(perf);
   acmgt1_register_ext520_counter_query(perf);
   acmgt1_register_ext521_counter_query(perf);
   acmgt1_register_ext522_counter_query(perf);
   acmgt1_register_ext523_counter_query(perf);
   acmgt1_register_ext524_counter_query(perf);
   acmgt1_register_ext525_counter_query(perf);
   acmgt1_register_ext526_counter_query(perf);
   acmgt1_register_ext527_counter_query(perf);
   acmgt1_register_ext528_counter_query(perf);
   acmgt1_register_ext529_counter_query(perf);
   acmgt1_register_ext530_counter_query(perf);
   acmgt1_register_ext531_counter_query(perf);
   acmgt1_register_ext532_counter_query(perf);
   acmgt1_register_ext533_counter_query(perf);
   acmgt1_register_ext534_counter_query(perf);
   acmgt1_register_ext535_counter_query(perf);
   acmgt1_register_ext536_counter_query(perf);
   acmgt1_register_ext537_counter_query(perf);
   acmgt1_register_ext538_counter_query(perf);
   acmgt1_register_ext539_counter_query(perf);
   acmgt1_register_ext540_counter_query(perf);
   acmgt1_register_ext541_counter_query(perf);
   acmgt1_register_ext542_counter_query(perf);
   acmgt1_register_ext543_counter_query(perf);
   acmgt1_register_ext544_counter_query(perf);
   acmgt1_register_ext545_counter_query(perf);
   acmgt1_register_ext546_counter_query(perf);
   acmgt1_register_ext547_counter_query(perf);
   acmgt1_register_ext548_counter_query(perf);
   acmgt1_register_ext549_counter_query(perf);
   acmgt1_register_ext550_counter_query(perf);
   acmgt1_register_ext551_counter_query(perf);
   acmgt1_register_ext552_counter_query(perf);
   acmgt1_register_ext553_counter_query(perf);
   acmgt1_register_ext554_counter_query(perf);
   acmgt1_register_ext555_counter_query(perf);
   acmgt1_register_ext556_counter_query(perf);
   acmgt1_register_ext557_counter_query(perf);
   acmgt1_register_ext558_counter_query(perf);
   acmgt1_register_ext559_counter_query(perf);
   acmgt1_register_ext560_counter_query(perf);
   acmgt1_register_ext561_counter_query(perf);
   acmgt1_register_ext562_counter_query(perf);
   acmgt1_register_ext563_counter_query(perf);
   acmgt1_register_ext564_counter_query(perf);
   acmgt1_register_ext565_counter_query(perf);
   acmgt1_register_ext566_counter_query(perf);
   acmgt1_register_ext567_counter_query(perf);
   acmgt1_register_ext568_counter_query(perf);
   acmgt1_register_ext569_counter_query(perf);
   acmgt1_register_ext570_counter_query(perf);
   acmgt1_register_ext571_counter_query(perf);
   acmgt1_register_ext1000_counter_query(perf);
   acmgt1_register_ext1001_counter_query(perf);
   acmgt1_register_ext1002_counter_query(perf);
   acmgt1_register_ext1004_counter_query(perf);
   acmgt1_register_ext1005_counter_query(perf);
   acmgt1_register_ext1006_counter_query(perf);
   acmgt1_register_ext1007_counter_query(perf);
   acmgt1_register_ext1010_counter_query(perf);
}


static void
acmgt2_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Render Metrics Basic - aggregation approximation";
   query->symbol_name = "RenderBasic";
   query->guid = "0692a728-614d-4d12-8c03-7b3ffe961ef8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C840000 },
         { .reg = 0x00009888, .val = 0x1E842800 },
         { .reg = 0x00009888, .val = 0x02844000 },
         { .reg = 0x00009888, .val = 0x04840010 },
         { .reg = 0x00009888, .val = 0x12840800 },
         { .reg = 0x00009888, .val = 0x14840037 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009888, .val = 0x020A5000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009888, .val = 0x04032000 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001C000 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00003008 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__render_basic__avg_gpu_core_frequency__max,acmgt2__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2106, 24, NULL,acmgt2__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2107, 32, NULL,acmgt2__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2108, 40, NULL,acmgt2__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 2109, 48, NULL,acmgt2__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2110, 56, NULL,acmgt2__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 539, 64, NULL,acmgt2__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 540, 72, percentage_max_float,acmgt2__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 541, 76, percentage_max_float,acmgt2__render_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 80, percentage_max_float,acmgt2__render_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 543, 84, percentage_max_float,acmgt2__render_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 544, 88, percentage_max_float,acmgt2__render_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 545, 92, percentage_max_float,acmgt2__render_basic__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 546, 96, percentage_max_float,acmgt2__render_basic__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 547, 100, percentage_max_float,acmgt2__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 548, 104, percentage_max_float,acmgt2__render_basic__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 549, 108, percentage_max_float,acmgt2__render_basic__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 550, 112, percentage_max_float,acmgt2__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_uint64(query, 2111, 120, NULL,acmgt2__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 580, 128, NULL,acmgt2__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 2112, 136, NULL,acmgt2__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 2113, 144, NULL,acmgt2__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 2114, 152, NULL,acmgt2__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 551, 160, NULL,acmgt2__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 552, 168, NULL,acmgt2__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 553, 176, NULL,acmgt2__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 554, 184, NULL,acmgt2__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 555, 192, acmgt2__render_basic__slm_reads__max,acmgt2__render_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 556, 200, acmgt2__render_basic__slm_writes__max,acmgt2__render_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 557, 208, NULL,acmgt2__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 558, 216, NULL,acmgt2__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 559, 224, NULL,acmgt2__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 560, 232, acmgt2__render_basic__gti_read_throughput__max,acmgt2__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 561, 240, acmgt2__render_basic__gti_write_throughput__max,acmgt2__render_basic__gti_write_throughput__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 562, 248, percentage_max_float,acmgt2__render_basic__sampler20_busy__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 563, 252, percentage_max_float,acmgt2__render_basic__samplers_busy__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 564, 256, percentage_max_float,acmgt2__render_basic__sampler20_bottleneck__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 565, 260, percentage_max_float,acmgt2__render_basic__sampler_bottleneck__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Compute Metrics Basic";
   query->symbol_name = "ComputeBasic";
   query->guid = "ccde9a29-a5c5-4a9e-b7f5-ec1092387e2a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00003009 },
         { .reg = 0x0000E758, .val = 0x0000200A },
         { .reg = 0x0000E45C, .val = 0x00006008 },
         { .reg = 0x0000E55C, .val = 0x0000B007 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__compute_basic__avg_gpu_core_frequency__max,acmgt2__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 539, 32, NULL,acmgt2__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 541, 40, percentage_max_float,acmgt2__compute_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 44, percentage_max_float,acmgt2__compute_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 566, 48, percentage_max_float,acmgt2__compute_basic__fpu_active__read);

      intel_perf_query_add_counter_float(query, 567, 52, percentage_max_float,acmgt2__compute_basic__em_active__read);

      intel_perf_query_add_counter_float(query, 568, 56, percentage_max_float,acmgt2__compute_basic__xmx_active__read);

      intel_perf_query_add_counter_float(query, 544, 60, percentage_max_float,acmgt2__compute_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 569, 64, percentage_max_float,acmgt2__compute_basic__xve_fpu_xmx_active__read);

      intel_perf_query_add_counter_float(query, 570, 68, acmgt2__compute_basic__xve_avg_ipc_rate__max,acmgt2__compute_basic__xve_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 571, 72, percentage_max_float,acmgt2__compute_basic__send_active__read);

      intel_perf_query_add_counter_float(query, 543, 76, percentage_max_float,acmgt2__compute_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 572, 80, percentage_max_float,acmgt2__compute_basic__xve_fpu_flt16__read);

      intel_perf_query_add_counter_float(query, 573, 84, percentage_max_float,acmgt2__compute_basic__xve_fpu_flt32__read);

      intel_perf_query_add_counter_float(query, 574, 88, percentage_max_float,acmgt2__compute_basic__xve_fpu_flt64__read);

      intel_perf_query_add_counter_uint64(query, 553, 96, NULL,acmgt2__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 554, 104, NULL,acmgt2__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 555, 112, acmgt2__compute_basic__slm_reads__max,acmgt2__compute_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 556, 120, acmgt2__compute_basic__slm_writes__max,acmgt2__compute_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 557, 128, NULL,acmgt2__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 558, 136, NULL,acmgt2__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 559, 144, NULL,acmgt2__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 560, 152, acmgt2__compute_basic__gti_read_throughput__max,acmgt2__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 561, 160, acmgt2__compute_basic__gti_write_throughput__max,acmgt2__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "e529d23d-d766-4391-84e2-68d43fd1f9b0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00010000 },
         { .reg = 0x0000E558, .val = 0x00060050 },
         { .reg = 0x0000E658, .val = 0x00001090 },
         { .reg = 0x0000E758, .val = 0x00051011 },
         { .reg = 0x0000E45C, .val = 0x00091061 },
         { .reg = 0x0000E55C, .val = 0x00004008 },
         { .reg = 0x0000E65C, .val = 0x00000005 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__async_compute__avg_gpu_core_frequency__max,acmgt2__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 2106, 32, NULL,acmgt2__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2107, 40, NULL,acmgt2__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2108, 48, NULL,acmgt2__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 2109, 56, NULL,acmgt2__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2110, 64, NULL,acmgt2__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 539, 72, NULL,acmgt2__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 566, 80, percentage_max_float,acmgt2__async_compute__fpu_active__read);

      intel_perf_query_add_counter_float(query, 545, 84, percentage_max_float,acmgt2__async_compute__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 548, 88, percentage_max_float,acmgt2__async_compute__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 582, 92, percentage_max_float,acmgt2__async_compute__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 583, 96, percentage_max_float,acmgt2__async_compute__async_cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 567, 100, percentage_max_float,acmgt2__async_compute__em_active__read);

      intel_perf_query_add_counter_float(query, 546, 104, percentage_max_float,acmgt2__async_compute__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 549, 108, percentage_max_float,acmgt2__async_compute__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 584, 112, percentage_max_float,acmgt2__async_compute__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 585, 116, percentage_max_float,acmgt2__async_compute__async_cs_em_active__read);

      intel_perf_query_add_counter_float(query, 543, 120, percentage_max_float,acmgt2__async_compute__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 541, 124, percentage_max_float,acmgt2__async_compute__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 128, percentage_max_float,acmgt2__async_compute__xve_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_xve_activity1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "XveActivity1";
   query->symbol_name = "XveActivity1";
   query->guid = "0785f0af-8ae2-470c-bc7b-dd81154d4d24";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00030020 },
         { .reg = 0x0000E558, .val = 0x00021040 },
         { .reg = 0x0000E658, .val = 0x00041031 },
         { .reg = 0x0000E758, .val = 0x00032022 },
         { .reg = 0x0000E45C, .val = 0x00062042 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__xve_activity1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__xve_activity1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__xve_activity1__avg_gpu_core_frequency__max,acmgt2__xve_activity1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__xve_activity1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 2106, 32, NULL,acmgt2__xve_activity1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2107, 40, NULL,acmgt2__xve_activity1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2108, 48, NULL,acmgt2__xve_activity1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 2109, 56, NULL,acmgt2__xve_activity1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2110, 64, NULL,acmgt2__xve_activity1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 539, 72, NULL,acmgt2__xve_activity1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 586, 80, percentage_max_float,acmgt2__xve_activity1__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 587, 84, percentage_max_float,acmgt2__xve_activity1__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 588, 88, percentage_max_float,acmgt2__xve_activity1__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 589, 92, percentage_max_float,acmgt2__xve_activity1__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 590, 96, percentage_max_float,acmgt2__xve_activity1__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 591, 100, percentage_max_float,acmgt2__xve_activity1__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 592, 104, percentage_max_float,acmgt2__xve_activity1__hs_send_active__read);

      intel_perf_query_add_counter_float(query, 593, 108, percentage_max_float,acmgt2__xve_activity1__ds_send_active__read);

      intel_perf_query_add_counter_float(query, 594, 112, percentage_max_float,acmgt2__xve_activity1__gs_send_active__read);

      intel_perf_query_add_counter_float(query, 595, 116, percentage_max_float,acmgt2__xve_activity1__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "1a01365e-7c8d-4816-b69a-edb89731dcf9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x420A2400 },
         { .reg = 0x00009888, .val = 0x1A131200 },
         { .reg = 0x00009888, .val = 0x040A0022 },
         { .reg = 0x00009888, .val = 0x120A0014 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x00104000 },
         { .reg = 0x00009888, .val = 0x02100002 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x00134000 },
         { .reg = 0x00009888, .val = 0x0A130024 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x420A2400 },
         { .reg = 0x00009888, .val = 0x1A131200 },
         { .reg = 0x00009888, .val = 0x040A0022 },
         { .reg = 0x00009888, .val = 0x100A0014 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x00102400 },
         { .reg = 0x00009888, .val = 0x00120400 },
         { .reg = 0x00009888, .val = 0x00134000 },
         { .reg = 0x00009888, .val = 0x08130024 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1A012400 },
         { .reg = 0x00009888, .val = 0x1C042400 },
         { .reg = 0x00009888, .val = 0x24042400 },
         { .reg = 0x00009888, .val = 0x2C042400 },
         { .reg = 0x00009888, .val = 0x36040009 },
         { .reg = 0x00009888, .val = 0x40041200 },
         { .reg = 0x00009888, .val = 0x04010006 },
         { .reg = 0x00009888, .val = 0x12010004 },
         { .reg = 0x00009888, .val = 0x00010155 },
         { .reg = 0x00009888, .val = 0x02014500 },
         { .reg = 0x00009888, .val = 0x040426E9 },
         { .reg = 0x00009888, .val = 0x060401F7 },
         { .reg = 0x00009888, .val = 0x08041000 },
         { .reg = 0x00009888, .val = 0x0A04050C },
         { .reg = 0x00009888, .val = 0x0C04091C },
         { .reg = 0x00009888, .val = 0x14040500 },
         { .reg = 0x00009888, .val = 0x1604000C },
         { .reg = 0x00009888, .val = 0x18040024 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x02040000 },
         { .reg = 0x00009888, .val = 0x00080155 },
         { .reg = 0x00009888, .val = 0x02084504 },
         { .reg = 0x00009888, .val = 0x00056800 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032924 },
         { .reg = 0x00009888, .val = 0x04030480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x3603294A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x3803146A },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030003 },
         { .reg = 0x00009888, .val = 0x3E030E20 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x3403014A },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000081 },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__gpu_busyness__avg_gpu_core_frequency__max,acmgt2__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 541, 28, percentage_max_float,acmgt2__gpu_busyness__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 32, percentage_max_float,acmgt2__gpu_busyness__xve_stall__read);

      intel_perf_query_add_counter_float(query, 543, 36, percentage_max_float,acmgt2__gpu_busyness__xve_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 2106, 40, NULL,acmgt2__gpu_busyness__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2107, 48, NULL,acmgt2__gpu_busyness__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2108, 56, NULL,acmgt2__gpu_busyness__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 2109, 64, NULL,acmgt2__gpu_busyness__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2110, 72, NULL,acmgt2__gpu_busyness__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 539, 80, NULL,acmgt2__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 596, 88, percentage_max_float,acmgt2__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 598, 92, percentage_max_float,acmgt2__gpu_busyness__compute_engine1_busy__read);

      intel_perf_query_add_counter_float(query, 599, 96, percentage_max_float,acmgt2__gpu_busyness__compute_engine2_busy__read);

      intel_perf_query_add_counter_float(query, 601, 100, percentage_max_float,acmgt2__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 602, 104, percentage_max_float,acmgt2__gpu_busyness__vdbox00_busy__read);

      intel_perf_query_add_counter_float(query, 603, 108, percentage_max_float,acmgt2__gpu_busyness__vebox0_busy__read);

      intel_perf_query_add_counter_float(query, 604, 112, percentage_max_float,acmgt2__gpu_busyness__vdbox10_busy__read);

      intel_perf_query_add_counter_float(query, 605, 116, percentage_max_float,acmgt2__gpu_busyness__vebox1_busy__read);

      intel_perf_query_add_counter_float(query, 606, 120, percentage_max_float,acmgt2__gpu_busyness__any_compute_engine_busy__read);

      intel_perf_query_add_counter_float(query, 607, 124, percentage_max_float,acmgt2__gpu_busyness__render_and_any_compute_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_render_pipe_profile1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile1";
   query->guid = "9ca2b4be-4bd5-4873-9d59-9d6a5d9f8c29";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x168607C0 },
         { .reg = 0x00009888, .val = 0x1603001F },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x12040640 },
         { .reg = 0x00009888, .val = 0x08040021 },
         { .reg = 0x00009888, .val = 0x1C070000 },
         { .reg = 0x00009888, .val = 0x16090000 },
         { .reg = 0x00009888, .val = 0x1C0903C0 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x160B7C00 },
         { .reg = 0x00009888, .val = 0x04860000 },
         { .reg = 0x00009888, .val = 0x06860400 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x0A0301C0 },
         { .reg = 0x00009888, .val = 0x100300C0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x0C040080 },
         { .reg = 0x00009888, .val = 0x0E040022 },
         { .reg = 0x00009888, .val = 0x04074000 },
         { .reg = 0x00009888, .val = 0x0A070021 },
         { .reg = 0x00009888, .val = 0x0E0708C0 },
         { .reg = 0x00009888, .val = 0x00070800 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x00083032 },
         { .reg = 0x00009888, .val = 0x02083300 },
         { .reg = 0x00009888, .val = 0x02094003 },
         { .reg = 0x00009888, .val = 0x08090880 },
         { .reg = 0x00009888, .val = 0x0C090001 },
         { .reg = 0x00009888, .val = 0x0E090023 },
         { .reg = 0x00009888, .val = 0x12090003 },
         { .reg = 0x00009888, .val = 0x00090D28 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x140A0940 },
         { .reg = 0x00009888, .val = 0x000A9A91 },
         { .reg = 0x00009888, .val = 0x020A19AA },
         { .reg = 0x00009888, .val = 0x00015044 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x020B2200 },
         { .reg = 0x00009888, .val = 0x00020C20 },
         { .reg = 0x00009888, .val = 0x000C0800 },
         { .reg = 0x00009888, .val = 0x020C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032482 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030007 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x3603180A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030C22 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030C21 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030006 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340304C1 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__render_pipe_profile1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__render_pipe_profile1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__render_pipe_profile1__avg_gpu_core_frequency__max,acmgt2__render_pipe_profile1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__render_pipe_profile1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 608, 28, percentage_max_float,acmgt2__render_pipe_profile1__vf2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 609, 32, percentage_max_float,acmgt2__render_pipe_profile1__vs2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 610, 36, percentage_max_float,acmgt2__render_pipe_profile1__cl2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 611, 40, percentage_max_float,acmgt2__render_pipe_profile1__hs2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 612, 44, percentage_max_float,acmgt2__render_pipe_profile1__ds2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 613, 48, percentage_max_float,acmgt2__render_pipe_profile1__gs2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 614, 52, percentage_max_float,acmgt2__render_pipe_profile1__sf2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 615, 56, percentage_max_float,acmgt2__render_pipe_profile1__so2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 616, 60, percentage_max_float,acmgt2__render_pipe_profile1__cl2_stall__read);

      intel_perf_query_add_counter_float(query, 617, 64, percentage_max_float,acmgt2__render_pipe_profile1__hs2_stall__read);

      intel_perf_query_add_counter_float(query, 618, 68, percentage_max_float,acmgt2__render_pipe_profile1__ds2_stall__read);

      intel_perf_query_add_counter_float(query, 619, 72, percentage_max_float,acmgt2__render_pipe_profile1__sf2_stall__read);

      intel_perf_query_add_counter_float(query, 620, 76, percentage_max_float,acmgt2__render_pipe_profile1__so2_stall__read);

      intel_perf_query_add_counter_float(query, 621, 80, percentage_max_float,acmgt2__render_pipe_profile1__hi_depth20_bottleneck__read);

      intel_perf_query_add_counter_float(query, 622, 84, percentage_max_float,acmgt2__render_pipe_profile1__bc20_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_render_pipe_profile2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile2";
   query->guid = "901cbc75-aa84-496c-a07d-c5db62b8dadb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x178607C0 },
         { .reg = 0x00009888, .val = 0x1703001F },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x13040640 },
         { .reg = 0x00009888, .val = 0x09040021 },
         { .reg = 0x00009888, .val = 0x1D070000 },
         { .reg = 0x00009888, .val = 0x17090000 },
         { .reg = 0x00009888, .val = 0x1D0903C0 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x170B7C00 },
         { .reg = 0x00009888, .val = 0x05860000 },
         { .reg = 0x00009888, .val = 0x07860400 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x0003FFFD },
         { .reg = 0x00009888, .val = 0x0008FFF3 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5551 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x000BAAA2 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x0B0301C0 },
         { .reg = 0x00009888, .val = 0x110300C0 },
         { .reg = 0x00009888, .val = 0x13030C80 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01040000 },
         { .reg = 0x00009888, .val = 0x0D040080 },
         { .reg = 0x00009888, .val = 0x0F040022 },
         { .reg = 0x00009888, .val = 0x05074000 },
         { .reg = 0x00009888, .val = 0x0B070021 },
         { .reg = 0x00009888, .val = 0x0F0708C0 },
         { .reg = 0x00009888, .val = 0x01070800 },
         { .reg = 0x00009888, .val = 0x030700A0 },
         { .reg = 0x00009888, .val = 0x01083032 },
         { .reg = 0x00009888, .val = 0x03083300 },
         { .reg = 0x00009888, .val = 0x03094003 },
         { .reg = 0x00009888, .val = 0x09090880 },
         { .reg = 0x00009888, .val = 0x0D090001 },
         { .reg = 0x00009888, .val = 0x0F090023 },
         { .reg = 0x00009888, .val = 0x13090003 },
         { .reg = 0x00009888, .val = 0x01090D28 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x150A0940 },
         { .reg = 0x00009888, .val = 0x010A9A91 },
         { .reg = 0x00009888, .val = 0x030A19AA },
         { .reg = 0x00009888, .val = 0x01015044 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B2000 },
         { .reg = 0x00009888, .val = 0x030B2200 },
         { .reg = 0x00009888, .val = 0x01020C20 },
         { .reg = 0x00009888, .val = 0x010C0800 },
         { .reg = 0x00009888, .val = 0x030C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032482 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030007 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x3603180A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030C22 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030C21 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030006 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340304C1 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__render_pipe_profile2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__render_pipe_profile2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__render_pipe_profile2__avg_gpu_core_frequency__max,acmgt2__render_pipe_profile2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__render_pipe_profile2__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 623, 28, percentage_max_float,acmgt2__render_pipe_profile2__vf3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 624, 32, percentage_max_float,acmgt2__render_pipe_profile2__vs3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 625, 36, percentage_max_float,acmgt2__render_pipe_profile2__cl3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 626, 40, percentage_max_float,acmgt2__render_pipe_profile2__hs3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 627, 44, percentage_max_float,acmgt2__render_pipe_profile2__ds3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 628, 48, percentage_max_float,acmgt2__render_pipe_profile2__gs3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 629, 52, percentage_max_float,acmgt2__render_pipe_profile2__sf3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 630, 56, percentage_max_float,acmgt2__render_pipe_profile2__so3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 631, 60, percentage_max_float,acmgt2__render_pipe_profile2__cl3_stall__read);

      intel_perf_query_add_counter_float(query, 632, 64, percentage_max_float,acmgt2__render_pipe_profile2__hs3_stall__read);

      intel_perf_query_add_counter_float(query, 633, 68, percentage_max_float,acmgt2__render_pipe_profile2__ds3_stall__read);

      intel_perf_query_add_counter_float(query, 634, 72, percentage_max_float,acmgt2__render_pipe_profile2__sf3_stall__read);

      intel_perf_query_add_counter_float(query, 635, 76, percentage_max_float,acmgt2__render_pipe_profile2__so3_stall__read);

      intel_perf_query_add_counter_float(query, 636, 80, percentage_max_float,acmgt2__render_pipe_profile2__hi_depth30_bottleneck__read);

      intel_perf_query_add_counter_float(query, 637, 84, percentage_max_float,acmgt2__render_pipe_profile2__bc30_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_render_pipe_profile3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile3";
   query->guid = "9afedc01-2ddf-46af-a5da-8310c1afed17";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x168607C0 },
         { .reg = 0x00009888, .val = 0x1603001F },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x12040640 },
         { .reg = 0x00009888, .val = 0x08040021 },
         { .reg = 0x00009888, .val = 0x1C070000 },
         { .reg = 0x00009888, .val = 0x16090000 },
         { .reg = 0x00009888, .val = 0x1C0903C0 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x160B7C00 },
         { .reg = 0x00009888, .val = 0x04860000 },
         { .reg = 0x00009888, .val = 0x08860002 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x0A0301C0 },
         { .reg = 0x00009888, .val = 0x100300C0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x0C040080 },
         { .reg = 0x00009888, .val = 0x0E040022 },
         { .reg = 0x00009888, .val = 0x04074000 },
         { .reg = 0x00009888, .val = 0x0A070021 },
         { .reg = 0x00009888, .val = 0x0E0708C0 },
         { .reg = 0x00009888, .val = 0x00070800 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x00083038 },
         { .reg = 0x00009888, .val = 0x02083300 },
         { .reg = 0x00009888, .val = 0x02094003 },
         { .reg = 0x00009888, .val = 0x08090880 },
         { .reg = 0x00009888, .val = 0x0C090001 },
         { .reg = 0x00009888, .val = 0x0E090023 },
         { .reg = 0x00009888, .val = 0x12090003 },
         { .reg = 0x00009888, .val = 0x00090D28 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x140A0940 },
         { .reg = 0x00009888, .val = 0x000A9A94 },
         { .reg = 0x00009888, .val = 0x020A19AA },
         { .reg = 0x00009888, .val = 0x00015044 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x020B2200 },
         { .reg = 0x00009888, .val = 0x00020C20 },
         { .reg = 0x00009888, .val = 0x000C0800 },
         { .reg = 0x00009888, .val = 0x020C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031248 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x360318EA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030C22 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030C21 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030006 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340304C1 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFE },
         { .reg = 0x00009888, .val = 0x00025554 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045554 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055554 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA8 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__render_pipe_profile3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__render_pipe_profile3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__render_pipe_profile3__avg_gpu_core_frequency__max,acmgt2__render_pipe_profile3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__render_pipe_profile3__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 2115, 28, percentage_max_float,acmgt2__render_pipe_profile3__vf4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2116, 32, percentage_max_float,acmgt2__render_pipe_profile3__vs4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2117, 36, percentage_max_float,acmgt2__render_pipe_profile3__cl4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2118, 40, percentage_max_float,acmgt2__render_pipe_profile3__hs4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2119, 44, percentage_max_float,acmgt2__render_pipe_profile3__ds4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2120, 48, percentage_max_float,acmgt2__render_pipe_profile3__gs4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2121, 52, percentage_max_float,acmgt2__render_pipe_profile3__sf4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2122, 56, percentage_max_float,acmgt2__render_pipe_profile3__so4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2123, 60, percentage_max_float,acmgt2__render_pipe_profile3__cl4_stall__read);

      intel_perf_query_add_counter_float(query, 2124, 64, percentage_max_float,acmgt2__render_pipe_profile3__hs4_stall__read);

      intel_perf_query_add_counter_float(query, 2125, 68, percentage_max_float,acmgt2__render_pipe_profile3__ds4_stall__read);

      intel_perf_query_add_counter_float(query, 2126, 72, percentage_max_float,acmgt2__render_pipe_profile3__sf4_stall__read);

      intel_perf_query_add_counter_float(query, 2127, 76, percentage_max_float,acmgt2__render_pipe_profile3__so4_stall__read);

      intel_perf_query_add_counter_float(query, 2128, 80, percentage_max_float,acmgt2__render_pipe_profile3__hi_depth40_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2129, 84, percentage_max_float,acmgt2__render_pipe_profile3__bc40_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_render_pipe_profile4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile4";
   query->guid = "89469a84-856d-4433-8962-773c68ce818b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x178607C0 },
         { .reg = 0x00009888, .val = 0x1703001F },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x13040640 },
         { .reg = 0x00009888, .val = 0x09040021 },
         { .reg = 0x00009888, .val = 0x1D070000 },
         { .reg = 0x00009888, .val = 0x17090000 },
         { .reg = 0x00009888, .val = 0x1D0903C0 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x170B7C00 },
         { .reg = 0x00009888, .val = 0x05860000 },
         { .reg = 0x00009888, .val = 0x07860400 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x0003FFFD },
         { .reg = 0x00009888, .val = 0x0008FFF3 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5551 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x000BAAA2 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x0B0301C0 },
         { .reg = 0x00009888, .val = 0x110300C0 },
         { .reg = 0x00009888, .val = 0x13030C80 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01040000 },
         { .reg = 0x00009888, .val = 0x0D040080 },
         { .reg = 0x00009888, .val = 0x0F040022 },
         { .reg = 0x00009888, .val = 0x05074000 },
         { .reg = 0x00009888, .val = 0x0B070021 },
         { .reg = 0x00009888, .val = 0x0F0708C0 },
         { .reg = 0x00009888, .val = 0x01070800 },
         { .reg = 0x00009888, .val = 0x030700A0 },
         { .reg = 0x00009888, .val = 0x01083032 },
         { .reg = 0x00009888, .val = 0x03083300 },
         { .reg = 0x00009888, .val = 0x03094003 },
         { .reg = 0x00009888, .val = 0x09090880 },
         { .reg = 0x00009888, .val = 0x0D090001 },
         { .reg = 0x00009888, .val = 0x0F090023 },
         { .reg = 0x00009888, .val = 0x13090003 },
         { .reg = 0x00009888, .val = 0x01090D28 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x150A0940 },
         { .reg = 0x00009888, .val = 0x010A9A91 },
         { .reg = 0x00009888, .val = 0x030A19AA },
         { .reg = 0x00009888, .val = 0x01015044 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B2000 },
         { .reg = 0x00009888, .val = 0x030B2200 },
         { .reg = 0x00009888, .val = 0x01020C20 },
         { .reg = 0x00009888, .val = 0x010C0800 },
         { .reg = 0x00009888, .val = 0x030C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFF3 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031241 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030007 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x3603180A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030C22 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030C21 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030006 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340304C1 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__render_pipe_profile4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__render_pipe_profile4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__render_pipe_profile4__avg_gpu_core_frequency__max,acmgt2__render_pipe_profile4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__render_pipe_profile4__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 2130, 28, percentage_max_float,acmgt2__render_pipe_profile4__vf5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2131, 32, percentage_max_float,acmgt2__render_pipe_profile4__vs5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2132, 36, percentage_max_float,acmgt2__render_pipe_profile4__cl5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2133, 40, percentage_max_float,acmgt2__render_pipe_profile4__hs5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2134, 44, percentage_max_float,acmgt2__render_pipe_profile4__ds5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2135, 48, percentage_max_float,acmgt2__render_pipe_profile4__gs5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2136, 52, percentage_max_float,acmgt2__render_pipe_profile4__sf5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2137, 56, percentage_max_float,acmgt2__render_pipe_profile4__so5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2138, 60, percentage_max_float,acmgt2__render_pipe_profile4__cl5_stall__read);

      intel_perf_query_add_counter_float(query, 2139, 64, percentage_max_float,acmgt2__render_pipe_profile4__hs5_stall__read);

      intel_perf_query_add_counter_float(query, 2140, 68, percentage_max_float,acmgt2__render_pipe_profile4__ds5_stall__read);

      intel_perf_query_add_counter_float(query, 2141, 72, percentage_max_float,acmgt2__render_pipe_profile4__sf5_stall__read);

      intel_perf_query_add_counter_float(query, 2142, 76, percentage_max_float,acmgt2__render_pipe_profile4__so5_stall__read);

      intel_perf_query_add_counter_float(query, 2143, 80, percentage_max_float,acmgt2__render_pipe_profile4__hi_depth50_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2144, 84, percentage_max_float,acmgt2__render_pipe_profile4__bc50_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "L3_1";
   query->symbol_name = "L3_1";
   query->guid = "2128b792-e30e-49ec-a64b-8a636364f728";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_1__avg_gpu_core_frequency__max,acmgt2__l3_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__l3_1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 638, 28, percentage_max_float,acmgt2__l3_1__l31_bank0_input_available__read);

      intel_perf_query_add_counter_float(query, 639, 32, percentage_max_float,acmgt2__l3_1__l31_bank1_input_available__read);

      intel_perf_query_add_counter_float(query, 640, 36, percentage_max_float,acmgt2__l3_1__l31_bank2_input_available__read);

      intel_perf_query_add_counter_float(query, 641, 40, percentage_max_float,acmgt2__l3_1__l31_bank3_input_available__read);

      intel_perf_query_add_counter_float(query, 642, 44, percentage_max_float,acmgt2__l3_1__l31_bank4_input_available__read);

      intel_perf_query_add_counter_float(query, 643, 48, percentage_max_float,acmgt2__l3_1__l31_bank5_input_available__read);

      intel_perf_query_add_counter_float(query, 644, 52, percentage_max_float,acmgt2__l3_1__l31_bank6_input_available__read);

      intel_perf_query_add_counter_float(query, 645, 56, percentage_max_float,acmgt2__l3_1__l31_bank7_input_available__read);

      intel_perf_query_add_counter_float(query, 646, 60, percentage_max_float,acmgt2__l3_1__l31_bank0_output_ready__read);

      intel_perf_query_add_counter_float(query, 647, 64, percentage_max_float,acmgt2__l3_1__l31_bank1_output_ready__read);

      intel_perf_query_add_counter_float(query, 648, 68, percentage_max_float,acmgt2__l3_1__l31_bank2_output_ready__read);

      intel_perf_query_add_counter_float(query, 649, 72, percentage_max_float,acmgt2__l3_1__l31_bank3_output_ready__read);

      intel_perf_query_add_counter_float(query, 650, 76, percentage_max_float,acmgt2__l3_1__l31_bank4_output_ready__read);

      intel_perf_query_add_counter_float(query, 651, 80, percentage_max_float,acmgt2__l3_1__l31_bank5_output_ready__read);

      intel_perf_query_add_counter_float(query, 652, 84, percentage_max_float,acmgt2__l3_1__l31_bank6_output_ready__read);

      intel_perf_query_add_counter_float(query, 653, 88, percentage_max_float,acmgt2__l3_1__l31_bank7_output_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3_2";
   query->symbol_name = "L3_2";
   query->guid = "a70724fd-5214-4325-b32c-61b37f409efa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_2__avg_gpu_core_frequency__max,acmgt2__l3_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 2145, 24, percentage_max_float,acmgt2__l3_2__l32_bank0_input_available__read);

      intel_perf_query_add_counter_float(query, 2146, 28, percentage_max_float,acmgt2__l3_2__l32_bank1_input_available__read);

      intel_perf_query_add_counter_float(query, 2147, 32, percentage_max_float,acmgt2__l3_2__l32_bank2_input_available__read);

      intel_perf_query_add_counter_float(query, 2148, 36, percentage_max_float,acmgt2__l3_2__l32_bank3_input_available__read);

      intel_perf_query_add_counter_float(query, 2149, 40, percentage_max_float,acmgt2__l3_2__l32_bank4_input_available__read);

      intel_perf_query_add_counter_float(query, 2150, 44, percentage_max_float,acmgt2__l3_2__l32_bank5_input_available__read);

      intel_perf_query_add_counter_float(query, 2151, 48, percentage_max_float,acmgt2__l3_2__l32_bank6_input_available__read);

      intel_perf_query_add_counter_float(query, 2152, 52, percentage_max_float,acmgt2__l3_2__l32_bank7_input_available__read);

      intel_perf_query_add_counter_float(query, 2153, 56, percentage_max_float,acmgt2__l3_2__l32_bank0_output_ready__read);

      intel_perf_query_add_counter_float(query, 2154, 60, percentage_max_float,acmgt2__l3_2__l32_bank1_output_ready__read);

      intel_perf_query_add_counter_float(query, 2155, 64, percentage_max_float,acmgt2__l3_2__l32_bank2_output_ready__read);

      intel_perf_query_add_counter_float(query, 2156, 68, percentage_max_float,acmgt2__l3_2__l32_bank3_output_ready__read);

      intel_perf_query_add_counter_float(query, 2157, 72, percentage_max_float,acmgt2__l3_2__l32_bank4_output_ready__read);

      intel_perf_query_add_counter_float(query, 2158, 76, percentage_max_float,acmgt2__l3_2__l32_bank5_output_ready__read);

      intel_perf_query_add_counter_float(query, 2159, 80, percentage_max_float,acmgt2__l3_2__l32_bank6_output_ready__read);

      intel_perf_query_add_counter_float(query, 2160, 84, percentage_max_float,acmgt2__l3_2__l32_bank7_output_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Sampler_1";
   query->symbol_name = "Sampler_1";
   query->guid = "167e0c1d-8ef2-44d3-b4fa-407b9a23eb5a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x14832C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x14A32C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x14C32C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x14E32C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x15832C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x15A32C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x15C32C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x15E32C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x16820024 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x0A830580 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x14A20900 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x0AA30016 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x14C20024 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x08C30580 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x12E20900 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x08E30016 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x13820024 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x07830580 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x07A30016 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x11C20024 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x05C30580 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x0FE20900 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x05E30016 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030863 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36031C8A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x380301E6 },
         { .reg = 0x00009888, .val = 0x3A030E17 },
         { .reg = 0x00009888, .val = 0x3C0307E4 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler_1__avg_gpu_core_frequency__max,acmgt2__sampler_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__sampler_1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 654, 28, percentage_max_float,acmgt2__sampler_1__sampler20_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 655, 32, percentage_max_float,acmgt2__sampler_1__sampler21_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 656, 36, percentage_max_float,acmgt2__sampler_1__sampler22_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 657, 40, percentage_max_float,acmgt2__sampler_1__sampler23_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 658, 44, percentage_max_float,acmgt2__sampler_1__sampler30_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 659, 48, percentage_max_float,acmgt2__sampler_1__sampler31_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 660, 52, percentage_max_float,acmgt2__sampler_1__sampler32_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 661, 56, percentage_max_float,acmgt2__sampler_1__sampler33_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 662, 60, percentage_max_float,acmgt2__sampler_1__sampler20_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 663, 64, percentage_max_float,acmgt2__sampler_1__sampler21_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 664, 68, percentage_max_float,acmgt2__sampler_1__sampler22_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 665, 72, percentage_max_float,acmgt2__sampler_1__sampler23_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 666, 76, percentage_max_float,acmgt2__sampler_1__sampler30_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 667, 80, percentage_max_float,acmgt2__sampler_1__sampler31_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 668, 84, percentage_max_float,acmgt2__sampler_1__sampler32_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 669, 88, percentage_max_float,acmgt2__sampler_1__sampler33_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Sampler_2";
   query->symbol_name = "Sampler_2";
   query->guid = "879e3747-17f6-40b8-9a7a-2c6752ff6d6c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x14832C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x14A32C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x14C32C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x14E32C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x15832C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x15A32C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x15C32C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x15E32C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x16820024 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x0A830580 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x14A20900 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x0AA30016 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x14C20024 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x08C30580 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x12E20900 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x08E30016 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x13820024 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x07830580 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x07A30016 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x11C20024 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x05C30580 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x0FE20900 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x05E30016 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030863 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36031C8A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x380301E6 },
         { .reg = 0x00009888, .val = 0x3A030E17 },
         { .reg = 0x00009888, .val = 0x3C0307E4 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler_2__avg_gpu_core_frequency__max,acmgt2__sampler_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__sampler_2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2161, 28, percentage_max_float,acmgt2__sampler_2__sampler40_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2162, 32, percentage_max_float,acmgt2__sampler_2__sampler41_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2163, 36, percentage_max_float,acmgt2__sampler_2__sampler42_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2164, 40, percentage_max_float,acmgt2__sampler_2__sampler43_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2165, 44, percentage_max_float,acmgt2__sampler_2__sampler50_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2166, 48, percentage_max_float,acmgt2__sampler_2__sampler51_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2167, 52, percentage_max_float,acmgt2__sampler_2__sampler52_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2168, 56, percentage_max_float,acmgt2__sampler_2__sampler53_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2169, 60, percentage_max_float,acmgt2__sampler_2__sampler40_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2170, 64, percentage_max_float,acmgt2__sampler_2__sampler41_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2171, 68, percentage_max_float,acmgt2__sampler_2__sampler42_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2172, 72, percentage_max_float,acmgt2__sampler_2__sampler43_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2173, 76, percentage_max_float,acmgt2__sampler_2__sampler50_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2174, 80, percentage_max_float,acmgt2__sampler_2__sampler51_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2175, 84, percentage_max_float,acmgt2__sampler_2__sampler52_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2176, 88, percentage_max_float,acmgt2__sampler_2__sampler53_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_hdc_and_sf1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set HDCAndSF1";
   query->symbol_name = "HDCAndSF1";
   query->guid = "55aebe75-d0e0-4d07-aa50-4b1e672341a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8101E0 },
         { .reg = 0x00009888, .val = 0x1EA101E0 },
         { .reg = 0x00009888, .val = 0x1EC101E0 },
         { .reg = 0x00009888, .val = 0x1EE101E0 },
         { .reg = 0x00009888, .val = 0x1F8101E0 },
         { .reg = 0x00009888, .val = 0x1FA101E0 },
         { .reg = 0x00009888, .val = 0x1FC101E0 },
         { .reg = 0x00009888, .val = 0x1FE101E0 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x08810011 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x08A10440 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0AC10011 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0AE10440 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810011 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10440 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10011 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10440 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x36032000 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__hdc_and_sf1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__hdc_and_sf1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__hdc_and_sf1__avg_gpu_core_frequency__max,acmgt2__hdc_and_sf1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__hdc_and_sf1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 670, 28, percentage_max_float,acmgt2__hdc_and_sf1__non_sampler_shader20_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 671, 32, percentage_max_float,acmgt2__hdc_and_sf1__non_sampler_shader21_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 672, 36, percentage_max_float,acmgt2__hdc_and_sf1__non_sampler_shader22_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 673, 40, percentage_max_float,acmgt2__hdc_and_sf1__non_sampler_shader23_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 674, 44, percentage_max_float,acmgt2__hdc_and_sf1__non_sampler_shader30_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 675, 48, percentage_max_float,acmgt2__hdc_and_sf1__non_sampler_shader31_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 676, 52, percentage_max_float,acmgt2__hdc_and_sf1__non_sampler_shader32_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 677, 56, percentage_max_float,acmgt2__hdc_and_sf1__non_sampler_shader33_access_stalled_on_l3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_hdc_and_sf2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set HDCAndSF2";
   query->symbol_name = "HDCAndSF2";
   query->guid = "d9c30016-f7b6-4c66-81e1-cb75b68a2222";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12056400 },
         { .reg = 0x00009888, .val = 0x13056400 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x0205001C },
         { .reg = 0x00009888, .val = 0x00060001 },
         { .reg = 0x00009888, .val = 0x0008000D },
         { .reg = 0x00009888, .val = 0x000A0005 },
         { .reg = 0x00009888, .val = 0x00010002 },
         { .reg = 0x00009888, .val = 0x000B0008 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x03050700 },
         { .reg = 0x00009888, .val = 0x01060002 },
         { .reg = 0x00009888, .val = 0x01080004 },
         { .reg = 0x00009888, .val = 0x010A0004 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12056400 },
         { .reg = 0x00009888, .val = 0x13056400 },
         { .reg = 0x00009888, .val = 0x00030008 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x04050007 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00060004 },
         { .reg = 0x00009888, .val = 0x000800D0 },
         { .reg = 0x00009888, .val = 0x000A0050 },
         { .reg = 0x00009888, .val = 0x00010008 },
         { .reg = 0x00009888, .val = 0x000B0080 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x050501C0 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01060008 },
         { .reg = 0x00009888, .val = 0x01080040 },
         { .reg = 0x00009888, .val = 0x010A0040 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x0C417000 },
         { .reg = 0x00009888, .val = 0x0C617000 },
         { .reg = 0x00009888, .val = 0x0C817000 },
         { .reg = 0x00009888, .val = 0x0CA17000 },
         { .reg = 0x00009888, .val = 0x02410010 },
         { .reg = 0x00009888, .val = 0x14410180 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610010 },
         { .reg = 0x00009888, .val = 0x16610006 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810010 },
         { .reg = 0x00009888, .val = 0x14810006 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10010 },
         { .reg = 0x00009888, .val = 0x12A10180 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02015000 },
         { .reg = 0x00009888, .val = 0x0204E000 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009888, .val = 0x02085000 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x00030252 },
         { .reg = 0x00009888, .val = 0x04032240 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x02090B00 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030009 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032033 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x34034E73 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000C },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__hdc_and_sf2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__hdc_and_sf2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__hdc_and_sf2__avg_gpu_core_frequency__max,acmgt2__hdc_and_sf2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__hdc_and_sf2__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 678, 28, percentage_max_float,acmgt2__hdc_and_sf2__poly2_data_ready__read);

      intel_perf_query_add_counter_float(query, 679, 32, percentage_max_float,acmgt2__hdc_and_sf2__poly3_data_ready__read);

      intel_perf_query_add_counter_float(query, 2177, 36, percentage_max_float,acmgt2__hdc_and_sf2__poly4_data_ready__read);

      intel_perf_query_add_counter_float(query, 2178, 40, percentage_max_float,acmgt2__hdc_and_sf2__poly5_data_ready__read);

      intel_perf_query_add_counter_float(query, 680, 44, percentage_max_float,acmgt2__hdc_and_sf2__gt_request_queue20_full__read);

      intel_perf_query_add_counter_float(query, 681, 48, percentage_max_float,acmgt2__hdc_and_sf2__gt_request_queue30_full__read);

      intel_perf_query_add_counter_float(query, 2179, 52, percentage_max_float,acmgt2__hdc_and_sf2__gt_request_queue40_full__read);

      intel_perf_query_add_counter_float(query, 2180, 56, percentage_max_float,acmgt2__hdc_and_sf2__gt_request_queue50_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_hdc_and_sf3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "HDCAndSF3";
   query->symbol_name = "HDCAndSF3";
   query->guid = "6357cd3a-3553-4a60-8c86-7c59347c3916";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8101E0 },
         { .reg = 0x00009888, .val = 0x1EA101E0 },
         { .reg = 0x00009888, .val = 0x1EC101E0 },
         { .reg = 0x00009888, .val = 0x1EE101E0 },
         { .reg = 0x00009888, .val = 0x1F8101E0 },
         { .reg = 0x00009888, .val = 0x1FA101E0 },
         { .reg = 0x00009888, .val = 0x1FC101E0 },
         { .reg = 0x00009888, .val = 0x1FE101E0 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0E810440 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0EA10011 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0CC10440 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0CE10011 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0B810440 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0BA10011 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x09C10440 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x09E10011 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030EE2 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C0314E0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__hdc_and_sf3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__hdc_and_sf3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__hdc_and_sf3__avg_gpu_core_frequency__max,acmgt2__hdc_and_sf3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__hdc_and_sf3__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2181, 28, percentage_max_float,acmgt2__hdc_and_sf3__non_sampler_shader40_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2182, 32, percentage_max_float,acmgt2__hdc_and_sf3__non_sampler_shader41_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2183, 36, percentage_max_float,acmgt2__hdc_and_sf3__non_sampler_shader42_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2184, 40, percentage_max_float,acmgt2__hdc_and_sf3__non_sampler_shader43_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2185, 44, percentage_max_float,acmgt2__hdc_and_sf3__non_sampler_shader50_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2186, 48, percentage_max_float,acmgt2__hdc_and_sf3__non_sampler_shader51_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2187, 52, percentage_max_float,acmgt2__hdc_and_sf3__non_sampler_shader52_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2188, 56, percentage_max_float,acmgt2__hdc_and_sf3__non_sampler_shader53_access_stalled_on_l3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_rasterizer_and_pixel_backend1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set RasterizerAndPixelBackend1";
   query->symbol_name = "RasterizerAndPixelBackend1";
   query->guid = "031a7f13-0f25-4794-958d-38cea3050a32";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A056000 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x0C0B7000 },
         { .reg = 0x00009888, .val = 0x0E0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C7000 },
         { .reg = 0x00009888, .val = 0x0E0C6000 },
         { .reg = 0x00009888, .val = 0x1B057000 },
         { .reg = 0x00009888, .val = 0x0D0B7000 },
         { .reg = 0x00009888, .val = 0x0F0B67D0 },
         { .reg = 0x00009888, .val = 0x0D0C77D0 },
         { .reg = 0x00009888, .val = 0x0F0C6000 },
         { .reg = 0x00009888, .val = 0x000383C0 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x020535D2 },
         { .reg = 0x00009888, .val = 0x0405003E },
         { .reg = 0x00009888, .val = 0x00060007 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x0008F015 },
         { .reg = 0x00009888, .val = 0x0208CF0F },
         { .reg = 0x00009888, .val = 0x00090C00 },
         { .reg = 0x00009888, .val = 0x000A5015 },
         { .reg = 0x00009888, .val = 0x020A45A5 },
         { .reg = 0x00009888, .val = 0x0001B3C0 },
         { .reg = 0x00009888, .val = 0x040B0200 },
         { .reg = 0x00009888, .val = 0x120B07D0 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000BA000 },
         { .reg = 0x00009888, .val = 0x020B800A },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x040C0200 },
         { .reg = 0x00009888, .val = 0x100C07D0 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x11050DC0 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01068000 },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x0308400F },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA000 },
         { .reg = 0x00009888, .val = 0x030A4005 },
         { .reg = 0x00009888, .val = 0x01010300 },
         { .reg = 0x00009888, .val = 0x050B0200 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x010200C0 },
         { .reg = 0x00009888, .val = 0x050C0200 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A056000 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x1B057000 },
         { .reg = 0x00009888, .val = 0x00034000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050002 },
         { .reg = 0x00009888, .val = 0x04050D00 },
         { .reg = 0x00009888, .val = 0x06050FB5 },
         { .reg = 0x00009888, .val = 0x00060038 },
         { .reg = 0x00009888, .val = 0x00080540 },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009888, .val = 0x000A0540 },
         { .reg = 0x00009888, .val = 0x020A1000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x11050037 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01064000 },
         { .reg = 0x00009888, .val = 0x03081000 },
         { .reg = 0x00009888, .val = 0x030A1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A02A },
         { .reg = 0x00009888, .val = 0x02088AAA },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x00031292 },
         { .reg = 0x00009888, .val = 0x02032491 },
         { .reg = 0x00009888, .val = 0x04031492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32032103 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x36030C66 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x380304E2 },
         { .reg = 0x00009888, .val = 0x3A030027 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34031400 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001BFC7 },
         { .reg = 0x00009888, .val = 0x00025015 },
         { .reg = 0x00009888, .val = 0x02024555 },
         { .reg = 0x00009888, .val = 0x00045015 },
         { .reg = 0x00009888, .val = 0x02044555 },
         { .reg = 0x00009888, .val = 0x00055015 },
         { .reg = 0x00009888, .val = 0x02054555 },
         { .reg = 0x00009888, .val = 0x0008A02A },
         { .reg = 0x00009888, .val = 0x02088AAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00014038 },
         { .reg = 0x00009888, .val = 0x00020540 },
         { .reg = 0x00009888, .val = 0x02021000 },
         { .reg = 0x00009888, .val = 0x00040540 },
         { .reg = 0x00009888, .val = 0x02041000 },
         { .reg = 0x00009888, .val = 0x00050540 },
         { .reg = 0x00009888, .val = 0x02051000 },
         { .reg = 0x00009888, .val = 0x00080A80 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000600 },
         { .reg = 0x0000D954, .val = 0x0000FF3F },
         { .reg = 0x0000D958, .val = 0x00001800 },
         { .reg = 0x0000D95C, .val = 0x0000FCFF },
         { .reg = 0x0000D960, .val = 0x00006000 },
         { .reg = 0x0000D964, .val = 0x0000F3FF },
         { .reg = 0x0000D968, .val = 0x00018000 },
         { .reg = 0x0000D96C, .val = 0x0000CFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__rasterizer_and_pixel_backend1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__rasterizer_and_pixel_backend1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max,acmgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__rasterizer_and_pixel_backend1__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 682, 28, percentage_max_float,acmgt2__rasterizer_and_pixel_backend1__rasterizer2_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 683, 32, percentage_max_float,acmgt2__rasterizer_and_pixel_backend1__rasterizer3_output_ready__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2189, 36, percentage_max_float,acmgt2__rasterizer_and_pixel_backend1__rasterizer4_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2190, 40, percentage_max_float,acmgt2__rasterizer_and_pixel_backend1__rasterizer5_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 684, 44, percentage_max_float,acmgt2__rasterizer_and_pixel_backend1__pixel_data20_ready__read);

      intel_perf_query_add_counter_float(query, 685, 48, percentage_max_float,acmgt2__rasterizer_and_pixel_backend1__pixel_data21_ready__read);

      intel_perf_query_add_counter_float(query, 692, 52, percentage_max_float,acmgt2__rasterizer_and_pixel_backend1__pixel_data30_ready__read);

      intel_perf_query_add_counter_float(query, 693, 56, percentage_max_float,acmgt2__rasterizer_and_pixel_backend1__pixel_data31_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_rasterizer_and_pixel_backend2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set RasterizerAndPixelBackend2";
   query->symbol_name = "RasterizerAndPixelBackend2";
   query->guid = "2032fb37-ebc9-4eb6-8916-4550474edd5d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A057000 },
         { .reg = 0x00009888, .val = 0x1B056000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x00030007 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x10050DC0 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00068000 },
         { .reg = 0x00009888, .val = 0x0008003F },
         { .reg = 0x00009888, .val = 0x02084000 },
         { .reg = 0x00009888, .val = 0x000A0015 },
         { .reg = 0x00009888, .val = 0x020A4000 },
         { .reg = 0x00009888, .val = 0x00010007 },
         { .reg = 0x00009888, .val = 0x000B002A },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x030535D2 },
         { .reg = 0x00009888, .val = 0x0505003E },
         { .reg = 0x00009888, .val = 0x01060007 },
         { .reg = 0x00009888, .val = 0x01080015 },
         { .reg = 0x00009888, .val = 0x010A0015 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A057000 },
         { .reg = 0x00009888, .val = 0x0C0B7000 },
         { .reg = 0x00009888, .val = 0x0E0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C7000 },
         { .reg = 0x00009888, .val = 0x0E0C6000 },
         { .reg = 0x00009888, .val = 0x1B056000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x0D0B7000 },
         { .reg = 0x00009888, .val = 0x0F0B67D0 },
         { .reg = 0x00009888, .val = 0x0D0C77D0 },
         { .reg = 0x00009888, .val = 0x0F0C6000 },
         { .reg = 0x00009888, .val = 0x000303F8 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x10050037 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00064000 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x0008FFC0 },
         { .reg = 0x00009888, .val = 0x02081F0F },
         { .reg = 0x00009888, .val = 0x00090C00 },
         { .reg = 0x00009888, .val = 0x000A5540 },
         { .reg = 0x00009888, .val = 0x020A15A5 },
         { .reg = 0x00009888, .val = 0x000133F8 },
         { .reg = 0x00009888, .val = 0x040B0200 },
         { .reg = 0x00009888, .val = 0x120B07D0 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000BAA80 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x040C0200 },
         { .reg = 0x00009888, .val = 0x100C07D0 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03050002 },
         { .reg = 0x00009888, .val = 0x05050D00 },
         { .reg = 0x00009888, .val = 0x07050FB5 },
         { .reg = 0x00009888, .val = 0x01060038 },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x01080540 },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA540 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009888, .val = 0x01010300 },
         { .reg = 0x00009888, .val = 0x050B0200 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x010200C0 },
         { .reg = 0x00009888, .val = 0x050C0200 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008002A },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009888, .val = 0x0002FFC0 },
         { .reg = 0x00009888, .val = 0x02023FFF },
         { .reg = 0x00009888, .val = 0x00031292 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032107 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36031CE4 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030C06 },
         { .reg = 0x00009888, .val = 0x3A030060 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030C00 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00018007 },
         { .reg = 0x00009888, .val = 0x00020015 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x00040015 },
         { .reg = 0x00009888, .val = 0x02044000 },
         { .reg = 0x00009888, .val = 0x00050015 },
         { .reg = 0x00009888, .val = 0x02054000 },
         { .reg = 0x00009888, .val = 0x0008002A },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FF8 },
         { .reg = 0x00009888, .val = 0x00025540 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045540 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055540 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA80 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000600 },
         { .reg = 0x0000D954, .val = 0x0000FF3F },
         { .reg = 0x0000D958, .val = 0x00001800 },
         { .reg = 0x0000D95C, .val = 0x0000FCFF },
         { .reg = 0x0000D960, .val = 0x00006000 },
         { .reg = 0x0000D964, .val = 0x0000F3FF },
         { .reg = 0x0000D968, .val = 0x00018000 },
         { .reg = 0x0000D96C, .val = 0x0000CFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__rasterizer_and_pixel_backend2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__rasterizer_and_pixel_backend2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max,acmgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__rasterizer_and_pixel_backend2__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 691, 28, percentage_max_float,acmgt2__rasterizer_and_pixel_backend2__rasterizer2_output_ready__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 690, 32, percentage_max_float,acmgt2__rasterizer_and_pixel_backend2__rasterizer3_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2191, 36, percentage_max_float,acmgt2__rasterizer_and_pixel_backend2__rasterizer4_output_ready__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2192, 40, percentage_max_float,acmgt2__rasterizer_and_pixel_backend2__rasterizer5_input_available__read);
      }

      intel_perf_query_add_counter_float(query, 2193, 44, percentage_max_float,acmgt2__rasterizer_and_pixel_backend2__pixel_data40_ready__read);

      intel_perf_query_add_counter_float(query, 2194, 48, percentage_max_float,acmgt2__rasterizer_and_pixel_backend2__pixel_data41_ready__read);

      intel_perf_query_add_counter_float(query, 2195, 52, percentage_max_float,acmgt2__rasterizer_and_pixel_backend2__pixel_data50_ready__read);

      intel_perf_query_add_counter_float(query, 2196, 56, percentage_max_float,acmgt2__rasterizer_and_pixel_backend2__pixel_data51_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_rasterizer_and_pixel_backend3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RasterizerAndPixelBackend3";
   query->symbol_name = "RasterizerAndPixelBackend3";
   query->guid = "51bc5454-ff6e-4033-b8b0-c9734975b3d4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x180300C9 },
         { .reg = 0x00009888, .val = 0x180800C9 },
         { .reg = 0x00009888, .val = 0x0E030E70 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x020400A0 },
         { .reg = 0x00009888, .val = 0x02050050 },
         { .reg = 0x00009888, .val = 0x0C080E70 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x020800A0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x180300C9 },
         { .reg = 0x00009888, .val = 0x180800C9 },
         { .reg = 0x00009888, .val = 0x12030E70 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x0204A000 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x10080E70 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02032400 },
         { .reg = 0x00009888, .val = 0x04031252 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x3E030201 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x32030420 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403014A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__rasterizer_and_pixel_backend3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__rasterizer_and_pixel_backend3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__max,acmgt2__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 686, 24, percentage_max_float,acmgt2__rasterizer_and_pixel_backend3__ps_output10_available__read);

      intel_perf_query_add_counter_float(query, 688, 28, percentage_max_float,acmgt2__rasterizer_and_pixel_backend3__pixel_values10_ready__read);

      intel_perf_query_add_counter_float(query, 687, 32, percentage_max_float,acmgt2__rasterizer_and_pixel_backend3__ps_output11_available__read);

      intel_perf_query_add_counter_float(query, 689, 36, percentage_max_float,acmgt2__rasterizer_and_pixel_backend3__pixel_values11_ready__read);

      intel_perf_query_add_counter_float(query, 2197, 40, percentage_max_float,acmgt2__rasterizer_and_pixel_backend3__ps_output20_available__read);

      intel_perf_query_add_counter_float(query, 2198, 44, percentage_max_float,acmgt2__rasterizer_and_pixel_backend3__pixel_values20_ready__read);

      intel_perf_query_add_counter_float(query, 2199, 48, percentage_max_float,acmgt2__rasterizer_and_pixel_backend3__ps_output21_available__read);

      intel_perf_query_add_counter_float(query, 2200, 52, percentage_max_float,acmgt2__rasterizer_and_pixel_backend3__pixel_values21_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_tdl1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL1";
   query->symbol_name = "TDL1";
   query->guid = "5b08d0b8-c976-4d7b-b770-8f538bee394a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810030 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10C00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10030 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10C00 },
         { .reg = 0x00009888, .val = 0x14E10CF4 },
         { .reg = 0x00009888, .val = 0x16E10C72 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810030 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10C00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10030 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10C00 },
         { .reg = 0x00009888, .val = 0x11E10CF4 },
         { .reg = 0x00009888, .val = 0x13E10C72 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40F80 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70055 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x0009F00C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203294A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x36032007 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34031CE7 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__tdl1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__tdl1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__tdl1__avg_gpu_core_frequency__max,acmgt2__tdl1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__tdl1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 694, 28, percentage_max_float,acmgt2__tdl1__non_ps_thread20_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 695, 32, percentage_max_float,acmgt2__tdl1__non_ps_thread21_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 696, 36, percentage_max_float,acmgt2__tdl1__non_ps_thread22_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 697, 40, percentage_max_float,acmgt2__tdl1__non_ps_thread23_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 698, 44, percentage_max_float,acmgt2__tdl1__non_ps_thread30_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 699, 48, percentage_max_float,acmgt2__tdl1__non_ps_thread31_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 700, 52, percentage_max_float,acmgt2__tdl1__non_ps_thread32_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 701, 56, percentage_max_float,acmgt2__tdl1__non_ps_thread33_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 702, 60, percentage_max_float,acmgt2__tdl1__thread_header23_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 703, 64, percentage_max_float,acmgt2__tdl1__thread_header23_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 704, 68, percentage_max_float,acmgt2__tdl1__thread_header23_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 705, 72, percentage_max_float,acmgt2__tdl1__thread_header23_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 706, 76, percentage_max_float,acmgt2__tdl1__thread_header33_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 707, 80, percentage_max_float,acmgt2__tdl1__thread_header33_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 708, 84, percentage_max_float,acmgt2__tdl1__thread_header33_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 709, 88, percentage_max_float,acmgt2__tdl1__thread_header33_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_tdl2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "TDL2";
   query->symbol_name = "TDL2";
   query->guid = "27ee6bcc-1378-4046-8922-124ea2115039";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__tdl2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__tdl2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__tdl2__avg_gpu_core_frequency__max,acmgt2__tdl2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__tdl2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 710, 28, percentage_max_float,acmgt2__tdl2__ps_thread20_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 711, 32, percentage_max_float,acmgt2__tdl2__ps_thread21_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 712, 36, percentage_max_float,acmgt2__tdl2__ps_thread22_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 713, 40, percentage_max_float,acmgt2__tdl2__ps_thread23_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 714, 44, percentage_max_float,acmgt2__tdl2__ps_thread30_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 715, 48, percentage_max_float,acmgt2__tdl2__ps_thread31_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 716, 52, percentage_max_float,acmgt2__tdl2__ps_thread32_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 717, 56, percentage_max_float,acmgt2__tdl2__ps_thread33_ready_for_dispatch__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_tdl3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL3";
   query->symbol_name = "TDL3";
   query->guid = "dd909127-caff-408f-994f-e0f64a672918";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x14810CF4 },
         { .reg = 0x00009888, .val = 0x16810C72 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x02875500 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x10A10CF4 },
         { .reg = 0x00009888, .val = 0x12A10C72 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A70055 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0CC10CF4 },
         { .reg = 0x00009888, .val = 0x0EC10C72 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x08E10CB1 },
         { .reg = 0x00009888, .val = 0x0AE10D33 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__tdl3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__tdl3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__tdl3__avg_gpu_core_frequency__max,acmgt2__tdl3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__tdl3__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 718, 28, percentage_max_float,acmgt2__tdl3__thread_header20_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 719, 32, percentage_max_float,acmgt2__tdl3__thread_header20_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 720, 36, percentage_max_float,acmgt2__tdl3__thread_header20_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 721, 40, percentage_max_float,acmgt2__tdl3__thread_header20_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 722, 44, percentage_max_float,acmgt2__tdl3__thread_header20_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 723, 48, percentage_max_float,acmgt2__tdl3__thread_header21_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 724, 52, percentage_max_float,acmgt2__tdl3__thread_header21_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 725, 56, percentage_max_float,acmgt2__tdl3__thread_header21_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 726, 60, percentage_max_float,acmgt2__tdl3__thread_header21_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 727, 64, percentage_max_float,acmgt2__tdl3__thread_header21_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 728, 68, percentage_max_float,acmgt2__tdl3__thread_header22_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 729, 72, percentage_max_float,acmgt2__tdl3__thread_header22_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 730, 76, percentage_max_float,acmgt2__tdl3__thread_header22_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 731, 80, percentage_max_float,acmgt2__tdl3__thread_header22_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 732, 84, percentage_max_float,acmgt2__tdl3__thread_header22_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 733, 88, percentage_max_float,acmgt2__tdl3__thread_header23_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_tdl4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL4";
   query->symbol_name = "TDL4";
   query->guid = "64fae233-cafe-4594-ab7b-fcbf5b442933";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x15810CF4 },
         { .reg = 0x00009888, .val = 0x17810C72 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x03875500 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x11A10CF4 },
         { .reg = 0x00009888, .val = 0x13A10C72 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A70055 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0DC10CF4 },
         { .reg = 0x00009888, .val = 0x0FC10C72 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x09E10CB1 },
         { .reg = 0x00009888, .val = 0x0BE10D33 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__tdl4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__tdl4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__tdl4__avg_gpu_core_frequency__max,acmgt2__tdl4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__tdl4__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 734, 28, percentage_max_float,acmgt2__tdl4__thread_header30_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 735, 32, percentage_max_float,acmgt2__tdl4__thread_header30_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 736, 36, percentage_max_float,acmgt2__tdl4__thread_header30_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 737, 40, percentage_max_float,acmgt2__tdl4__thread_header30_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 738, 44, percentage_max_float,acmgt2__tdl4__thread_header30_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 739, 48, percentage_max_float,acmgt2__tdl4__thread_header31_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 740, 52, percentage_max_float,acmgt2__tdl4__thread_header31_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 741, 56, percentage_max_float,acmgt2__tdl4__thread_header31_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 742, 60, percentage_max_float,acmgt2__tdl4__thread_header31_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 743, 64, percentage_max_float,acmgt2__tdl4__thread_header31_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 744, 68, percentage_max_float,acmgt2__tdl4__thread_header32_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 745, 72, percentage_max_float,acmgt2__tdl4__thread_header32_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 746, 76, percentage_max_float,acmgt2__tdl4__thread_header32_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 747, 80, percentage_max_float,acmgt2__tdl4__thread_header32_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 748, 84, percentage_max_float,acmgt2__tdl4__thread_header32_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 749, 88, percentage_max_float,acmgt2__tdl4__thread_header33_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_tdl5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL5";
   query->symbol_name = "TDL5";
   query->guid = "063f5cea-f9ba-4c93-b7e8-22dc5c05060e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810030 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10C00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10030 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10C00 },
         { .reg = 0x00009888, .val = 0x14E10CF4 },
         { .reg = 0x00009888, .val = 0x16E10C72 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810030 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10C00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10030 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10C00 },
         { .reg = 0x00009888, .val = 0x11E10CF4 },
         { .reg = 0x00009888, .val = 0x13E10C72 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40F80 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70055 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x0009F00C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203294A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x36032007 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34031CE7 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__tdl5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__tdl5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__tdl5__avg_gpu_core_frequency__max,acmgt2__tdl5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__tdl5__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2201, 28, percentage_max_float,acmgt2__tdl5__non_ps_thread40_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2202, 32, percentage_max_float,acmgt2__tdl5__non_ps_thread41_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2203, 36, percentage_max_float,acmgt2__tdl5__non_ps_thread42_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2204, 40, percentage_max_float,acmgt2__tdl5__non_ps_thread43_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2205, 44, percentage_max_float,acmgt2__tdl5__non_ps_thread50_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2206, 48, percentage_max_float,acmgt2__tdl5__non_ps_thread51_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2207, 52, percentage_max_float,acmgt2__tdl5__non_ps_thread52_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2208, 56, percentage_max_float,acmgt2__tdl5__non_ps_thread53_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2209, 60, percentage_max_float,acmgt2__tdl5__thread_header43_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2210, 64, percentage_max_float,acmgt2__tdl5__thread_header43_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2211, 68, percentage_max_float,acmgt2__tdl5__thread_header43_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2212, 72, percentage_max_float,acmgt2__tdl5__thread_header43_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2213, 76, percentage_max_float,acmgt2__tdl5__thread_header53_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2214, 80, percentage_max_float,acmgt2__tdl5__thread_header53_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2215, 84, percentage_max_float,acmgt2__tdl5__thread_header53_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2216, 88, percentage_max_float,acmgt2__tdl5__thread_header53_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_tdl6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "TDL6";
   query->symbol_name = "TDL6";
   query->guid = "4cba20e7-78ea-4aaf-bd5d-42b8647cf778";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__tdl6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__tdl6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__tdl6__avg_gpu_core_frequency__max,acmgt2__tdl6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__tdl6__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2217, 28, percentage_max_float,acmgt2__tdl6__ps_thread40_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2218, 32, percentage_max_float,acmgt2__tdl6__ps_thread41_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2219, 36, percentage_max_float,acmgt2__tdl6__ps_thread42_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2220, 40, percentage_max_float,acmgt2__tdl6__ps_thread43_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2221, 44, percentage_max_float,acmgt2__tdl6__ps_thread50_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2222, 48, percentage_max_float,acmgt2__tdl6__ps_thread51_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2223, 52, percentage_max_float,acmgt2__tdl6__ps_thread52_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2224, 56, percentage_max_float,acmgt2__tdl6__ps_thread53_ready_for_dispatch__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_tdl7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL7";
   query->symbol_name = "TDL7";
   query->guid = "f76dee3e-b215-4780-9c83-7a1dfb1a6e63";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x14810CF4 },
         { .reg = 0x00009888, .val = 0x16810C72 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x02875500 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x10A10CF4 },
         { .reg = 0x00009888, .val = 0x12A10C72 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A70055 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0CC10CF4 },
         { .reg = 0x00009888, .val = 0x0EC10C72 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x08E10CB1 },
         { .reg = 0x00009888, .val = 0x0AE10D33 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__tdl7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__tdl7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__tdl7__avg_gpu_core_frequency__max,acmgt2__tdl7__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__tdl7__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2225, 28, percentage_max_float,acmgt2__tdl7__thread_header40_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2226, 32, percentage_max_float,acmgt2__tdl7__thread_header40_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2227, 36, percentage_max_float,acmgt2__tdl7__thread_header40_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2228, 40, percentage_max_float,acmgt2__tdl7__thread_header40_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2229, 44, percentage_max_float,acmgt2__tdl7__thread_header40_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2230, 48, percentage_max_float,acmgt2__tdl7__thread_header41_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2231, 52, percentage_max_float,acmgt2__tdl7__thread_header41_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2232, 56, percentage_max_float,acmgt2__tdl7__thread_header41_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2233, 60, percentage_max_float,acmgt2__tdl7__thread_header41_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2234, 64, percentage_max_float,acmgt2__tdl7__thread_header41_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2235, 68, percentage_max_float,acmgt2__tdl7__thread_header42_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2236, 72, percentage_max_float,acmgt2__tdl7__thread_header42_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2237, 76, percentage_max_float,acmgt2__tdl7__thread_header42_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2238, 80, percentage_max_float,acmgt2__tdl7__thread_header42_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2239, 84, percentage_max_float,acmgt2__tdl7__thread_header42_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2240, 88, percentage_max_float,acmgt2__tdl7__thread_header43_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_tdl8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL8";
   query->symbol_name = "TDL8";
   query->guid = "70a8e39e-5244-43ea-b922-bd7024baf879";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x15810CF4 },
         { .reg = 0x00009888, .val = 0x17810C72 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x03875500 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x11A10CF4 },
         { .reg = 0x00009888, .val = 0x13A10C72 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A70055 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0DC10CF4 },
         { .reg = 0x00009888, .val = 0x0FC10C72 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x09E10CB1 },
         { .reg = 0x00009888, .val = 0x0BE10D33 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__tdl8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__tdl8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__tdl8__avg_gpu_core_frequency__max,acmgt2__tdl8__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt2__tdl8__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2241, 28, percentage_max_float,acmgt2__tdl8__thread_header50_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2242, 32, percentage_max_float,acmgt2__tdl8__thread_header50_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2243, 36, percentage_max_float,acmgt2__tdl8__thread_header50_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2244, 40, percentage_max_float,acmgt2__tdl8__thread_header50_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2245, 44, percentage_max_float,acmgt2__tdl8__thread_header50_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2246, 48, percentage_max_float,acmgt2__tdl8__thread_header51_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2247, 52, percentage_max_float,acmgt2__tdl8__thread_header51_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2248, 56, percentage_max_float,acmgt2__tdl8__thread_header51_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2249, 60, percentage_max_float,acmgt2__tdl8__thread_header51_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2250, 64, percentage_max_float,acmgt2__tdl8__thread_header51_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2251, 68, percentage_max_float,acmgt2__tdl8__thread_header52_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2252, 72, percentage_max_float,acmgt2__tdl8__thread_header52_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2253, 76, percentage_max_float,acmgt2__tdl8__thread_header52_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2254, 80, percentage_max_float,acmgt2__tdl8__thread_header52_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2255, 84, percentage_max_float,acmgt2__tdl8__thread_header52_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2256, 88, percentage_max_float,acmgt2__tdl8__thread_header53_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "cfac9130-4f6a-4a2a-aafc-9e88751ce983";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x34080000 },
         { .reg = 0x00009888, .val = 0x06088000 },
         { .reg = 0x00009888, .val = 0x10080FF3 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x02032400 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__test_oa__avg_gpu_core_frequency__max,acmgt2__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 750, 24, NULL,acmgt2__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 751, 32, NULL,acmgt2__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 752, 40, NULL,acmgt2__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 753, 48, NULL,acmgt2__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 754, 56, NULL,acmgt2__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 755, 64, NULL,acmgt2__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 756, 72, NULL,acmgt2__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 757, 80, NULL,acmgt2__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 758, 88, NULL,acmgt2__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 759, 96, NULL,acmgt2__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_amfs1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "AMFS1";
   query->symbol_name = "AMFS1";
   query->guid = "7bb51d65-bc5c-4e23-904c-e7ad932d162e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x14060700 },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x04060E00 },
         { .reg = 0x00009888, .val = 0x06060146 },
         { .reg = 0x00009888, .val = 0x08060248 },
         { .reg = 0x00009888, .val = 0x0A0602CA },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x00081555 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030012 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000002A },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x0000000A },
         { .reg = 0x0000D94C, .val = 0x0000FFF8 },
         { .reg = 0x0000D950, .val = 0x0000000A },
         { .reg = 0x0000D954, .val = 0x0000FFFC },
         { .reg = 0x0000D958, .val = 0x00100180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x000000C2 },
         { .reg = 0x0000D964, .val = 0x0000FFE7 },
         { .reg = 0x0000D968, .val = 0x00000302 },
         { .reg = 0x0000D96C, .val = 0x0000FF9F },
         { .reg = 0x0000D970, .val = 0x000003C2 },
         { .reg = 0x0000D974, .val = 0x0000FF87 },
         { .reg = 0x0000D978, .val = 0x000000C2 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__amfs1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__amfs1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__amfs1__avg_gpu_core_frequency__max,acmgt2__amfs1__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1349, 24, NULL,acmgt2__amfs1__amfs_cache_hit_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1350, 32, NULL,acmgt2__amfs1__amfs_cache_miss_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1373, 40, NULL,acmgt2__amfs1__amfs_4_x4_shading_request_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1348, 48, percentage_max_float,acmgt2__amfs1__amfs_stall_any_input_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1347, 52, percentage_max_float,acmgt2__amfs1__amfs_stall_all_input_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_amfs2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "AMFS2";
   query->symbol_name = "AMFS2";
   query->guid = "b4899455-a030-400a-a66b-ea270f7722fd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x15060700 },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x05060E00 },
         { .reg = 0x00009888, .val = 0x07060146 },
         { .reg = 0x00009888, .val = 0x09060248 },
         { .reg = 0x00009888, .val = 0x0B0602CA },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01081555 },
         { .reg = 0x00009888, .val = 0x010A1555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030012 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000002A },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x0000000A },
         { .reg = 0x0000D94C, .val = 0x0000FFF8 },
         { .reg = 0x0000D950, .val = 0x0000000A },
         { .reg = 0x0000D954, .val = 0x0000FFFC },
         { .reg = 0x0000D958, .val = 0x00100180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x000000C2 },
         { .reg = 0x0000D964, .val = 0x0000FFE7 },
         { .reg = 0x0000D968, .val = 0x00000302 },
         { .reg = 0x0000D96C, .val = 0x0000FF9F },
         { .reg = 0x0000D970, .val = 0x000003C2 },
         { .reg = 0x0000D974, .val = 0x0000FF87 },
         { .reg = 0x0000D978, .val = 0x000000C2 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__amfs2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__amfs2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__amfs2__avg_gpu_core_frequency__max,acmgt2__amfs2__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1358, 24, NULL,acmgt2__amfs2__amfs_cache_hit_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1359, 32, NULL,acmgt2__amfs2__amfs_cache_miss_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1374, 40, NULL,acmgt2__amfs2__amfs_4_x4_shading_request_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1357, 48, percentage_max_float,acmgt2__amfs2__amfs_stall_any_input_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1356, 52, percentage_max_float,acmgt2__amfs2__amfs_stall_all_input_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_amfs3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "AMFS3";
   query->symbol_name = "AMFS3";
   query->guid = "cb47ffdf-f1a9-45f2-8ee6-21e0fb8111dd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x14060700 },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x04060E00 },
         { .reg = 0x00009888, .val = 0x06060146 },
         { .reg = 0x00009888, .val = 0x08060248 },
         { .reg = 0x00009888, .val = 0x0A0602CA },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x00081555 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00023FFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030009 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000002A },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x0000000A },
         { .reg = 0x0000D94C, .val = 0x0000FFF8 },
         { .reg = 0x0000D950, .val = 0x0000000A },
         { .reg = 0x0000D954, .val = 0x0000FFFC },
         { .reg = 0x0000D958, .val = 0x00100180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x000000C2 },
         { .reg = 0x0000D964, .val = 0x0000FFE7 },
         { .reg = 0x0000D968, .val = 0x00000302 },
         { .reg = 0x0000D96C, .val = 0x0000FF9F },
         { .reg = 0x0000D970, .val = 0x000003C2 },
         { .reg = 0x0000D974, .val = 0x0000FF87 },
         { .reg = 0x0000D978, .val = 0x000000C2 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__amfs3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__amfs3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__amfs3__avg_gpu_core_frequency__max,acmgt2__amfs3__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2257, 24, NULL,acmgt2__amfs3__amfs_cache_hit_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2258, 32, NULL,acmgt2__amfs3__amfs_cache_miss_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2259, 40, NULL,acmgt2__amfs3__amfs_4_x4_shading_request_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2260, 48, percentage_max_float,acmgt2__amfs3__amfs_stall_any_input_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2261, 52, percentage_max_float,acmgt2__amfs3__amfs_stall_all_input_slice2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_amfs4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "AMFS4";
   query->symbol_name = "AMFS4";
   query->guid = "2e296498-77db-42ad-8f34-9cda1ff4dcd8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x15060700 },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x05060E00 },
         { .reg = 0x00009888, .val = 0x07060146 },
         { .reg = 0x00009888, .val = 0x09060248 },
         { .reg = 0x00009888, .val = 0x0B0602CA },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01081555 },
         { .reg = 0x00009888, .val = 0x010A1555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00023FFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030009 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000002A },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x0000000A },
         { .reg = 0x0000D94C, .val = 0x0000FFF8 },
         { .reg = 0x0000D950, .val = 0x0000000A },
         { .reg = 0x0000D954, .val = 0x0000FFFC },
         { .reg = 0x0000D958, .val = 0x00100180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x000000C2 },
         { .reg = 0x0000D964, .val = 0x0000FFE7 },
         { .reg = 0x0000D968, .val = 0x00000302 },
         { .reg = 0x0000D96C, .val = 0x0000FF9F },
         { .reg = 0x0000D970, .val = 0x000003C2 },
         { .reg = 0x0000D974, .val = 0x0000FF87 },
         { .reg = 0x0000D978, .val = 0x000000C2 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__amfs4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__amfs4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__amfs4__avg_gpu_core_frequency__max,acmgt2__amfs4__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2262, 24, NULL,acmgt2__amfs4__amfs_cache_hit_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2263, 32, NULL,acmgt2__amfs4__amfs_cache_miss_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2264, 40, NULL,acmgt2__amfs4__amfs_4_x4_shading_request_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2265, 48, percentage_max_float,acmgt2__amfs4__amfs_stall_any_input_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2266, 52, percentage_max_float,acmgt2__amfs4__amfs_stall_all_input_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_amfs5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "AMFS5";
   query->symbol_name = "AMFS5";
   query->guid = "ef47f98a-fb5f-426d-922e-8ae13cedb198";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1606018A },
         { .reg = 0x00009888, .val = 0x1706018A },
         { .reg = 0x00009888, .val = 0x00034002 },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x1406000F },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0008000D },
         { .reg = 0x00009888, .val = 0x02087000 },
         { .reg = 0x00009888, .val = 0x000A0005 },
         { .reg = 0x00009888, .val = 0x020A5000 },
         { .reg = 0x00009888, .val = 0x00014002 },
         { .reg = 0x00009888, .val = 0x000B0008 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x07060000 },
         { .reg = 0x00009888, .val = 0x130603C0 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01080004 },
         { .reg = 0x00009888, .val = 0x03081000 },
         { .reg = 0x00009888, .val = 0x010A0004 },
         { .reg = 0x00009888, .val = 0x030A1000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1606018A },
         { .reg = 0x00009888, .val = 0x1706018A },
         { .reg = 0x00009888, .val = 0x00031008 },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x06060000 },
         { .reg = 0x00009888, .val = 0x1206000F },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x000800D0 },
         { .reg = 0x00009888, .val = 0x02080700 },
         { .reg = 0x00009888, .val = 0x000A0050 },
         { .reg = 0x00009888, .val = 0x020A0500 },
         { .reg = 0x00009888, .val = 0x00011008 },
         { .reg = 0x00009888, .val = 0x000B0080 },
         { .reg = 0x00009888, .val = 0x020B0200 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x09060000 },
         { .reg = 0x00009888, .val = 0x110603C0 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01080040 },
         { .reg = 0x00009888, .val = 0x03080100 },
         { .reg = 0x00009888, .val = 0x010A0040 },
         { .reg = 0x00009888, .val = 0x030A0100 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x00030252 },
         { .reg = 0x00009888, .val = 0x04032240 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030009 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032029 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030500 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001C003 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001300C },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x02050500 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00010022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00008042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x0004000A },
         { .reg = 0x0000D964, .val = 0x00007FFE },
         { .reg = 0x0000D968, .val = 0x00020012 },
         { .reg = 0x0000D96C, .val = 0x0000BFFD },
         { .reg = 0x0000D970, .val = 0x00010022 },
         { .reg = 0x0000D974, .val = 0x0000DFFB },
         { .reg = 0x0000D978, .val = 0x00008042 },
         { .reg = 0x0000D97C, .val = 0x0000EFF7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__amfs5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__amfs5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__amfs5__avg_gpu_core_frequency__max,acmgt2__amfs5__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1389, 24, NULL,acmgt2__amfs5__amfs_l3_atomic_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1390, 32, NULL,acmgt2__amfs5__amfs_l3_atomic_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2267, 40, NULL,acmgt2__amfs5__amfs_l3_atomic_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2268, 48, NULL,acmgt2__amfs5__amfs_l3_atomic_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1387, 56, NULL,acmgt2__amfs5__amfs_l3_access_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1388, 64, NULL,acmgt2__amfs5__amfs_l3_access_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2269, 72, NULL,acmgt2__amfs5__amfs_l3_access_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2270, 80, NULL,acmgt2__amfs5__amfs_l3_access_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1782, 88, NULL,acmgt2__amfs5__amfs_l3_write_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1783, 96, NULL,acmgt2__amfs5__amfs_l3_write_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2271, 104, NULL,acmgt2__amfs5__amfs_l3_write_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2272, 112, NULL,acmgt2__amfs5__amfs_l3_write_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "ColorPipe1";
   query->symbol_name = "ColorPipe1";
   query->guid = "ec2c2ae9-a41e-4ff4-99f1-118959c94bfb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x16037840 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x16087840 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x06030031 },
         { .reg = 0x00009888, .val = 0x08030E00 },
         { .reg = 0x00009888, .val = 0x0C030010 },
         { .reg = 0x00009888, .val = 0x0E0309C0 },
         { .reg = 0x00009888, .val = 0x1203002E },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00040820 },
         { .reg = 0x00009888, .val = 0x02042082 },
         { .reg = 0x00009888, .val = 0x00050410 },
         { .reg = 0x00009888, .val = 0x02051041 },
         { .reg = 0x00009888, .val = 0x06080C40 },
         { .reg = 0x00009888, .val = 0x0A080038 },
         { .reg = 0x00009888, .val = 0x0C080400 },
         { .reg = 0x00009888, .val = 0x10080027 },
         { .reg = 0x00009888, .val = 0x12080B80 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00080820 },
         { .reg = 0x00009888, .val = 0x02082082 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x16087840 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x04080C40 },
         { .reg = 0x00009888, .val = 0x08080038 },
         { .reg = 0x00009888, .val = 0x0A080400 },
         { .reg = 0x00009888, .val = 0x0E080027 },
         { .reg = 0x00009888, .val = 0x10080B80 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000828A0 },
         { .reg = 0x00009888, .val = 0x0208A28A },
         { .reg = 0x00009888, .val = 0x0002C30C },
         { .reg = 0x00009888, .val = 0x02020C30 },
         { .reg = 0x00009888, .val = 0x00031488 },
         { .reg = 0x00009888, .val = 0x02032452 },
         { .reg = 0x00009888, .val = 0x04032291 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603012A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803120A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C03120A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x32030120 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403012A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe1__avg_gpu_core_frequency__max,acmgt2__color_pipe1__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1351, 24, NULL,acmgt2__color_pipe1__render_cache_hit_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1360, 32, NULL,acmgt2__color_pipe1__render_cache_hit_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2273, 40, NULL,acmgt2__color_pipe1__render_cache_hit_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1352, 48, NULL,acmgt2__color_pipe1__render_cache_read_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1361, 56, NULL,acmgt2__color_pipe1__render_cache_read_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2274, 64, NULL,acmgt2__color_pipe1__render_cache_read_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1353, 72, NULL,acmgt2__color_pipe1__render_cache_write_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1362, 80, NULL,acmgt2__color_pipe1__render_cache_write_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2275, 88, NULL,acmgt2__color_pipe1__render_cache_write_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1354, 96, percentage_max_float,acmgt2__color_pipe1__render_cache_input_available_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1363, 100, percentage_max_float,acmgt2__color_pipe1__render_cache_input_available_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2276, 104, percentage_max_float,acmgt2__color_pipe1__render_cache_input_available_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1355, 108, percentage_max_float,acmgt2__color_pipe1__render_cache_output_ready_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1364, 112, percentage_max_float,acmgt2__color_pipe1__render_cache_output_ready_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2277, 116, percentage_max_float,acmgt2__color_pipe1__render_cache_output_ready_l3_node2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "ColorPipe2";
   query->symbol_name = "ColorPipe2";
   query->guid = "d7862a6d-902e-4d1f-9f39-e0f94aa4346e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x16037840 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x0E030C40 },
         { .reg = 0x00009888, .val = 0x10030438 },
         { .reg = 0x00009888, .val = 0x12030BA7 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x0204AA80 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0202FFC0 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe2__avg_gpu_core_frequency__max,acmgt2__color_pipe2__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2278, 24, NULL,acmgt2__color_pipe2__render_cache_hit_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2279, 32, NULL,acmgt2__color_pipe2__render_cache_read_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2280, 40, NULL,acmgt2__color_pipe2__render_cache_write_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2281, 48, percentage_max_float,acmgt2__color_pipe2__render_cache_input_available_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2282, 52, percentage_max_float,acmgt2__color_pipe2__render_cache_output_ready_l3_node3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "ColorPipe3";
   query->symbol_name = "ColorPipe3";
   query->guid = "f00094e7-2baa-4bb9-807b-d77bb1c72eba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12011000 },
         { .reg = 0x00009888, .val = 0x18010320 },
         { .reg = 0x00009888, .val = 0x12021C00 },
         { .reg = 0x00009888, .val = 0x18020320 },
         { .reg = 0x00009888, .val = 0x13011030 },
         { .reg = 0x00009888, .val = 0x13021000 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x0008000F },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x0009400C },
         { .reg = 0x00009888, .val = 0x000A00A5 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x04011100 },
         { .reg = 0x00009888, .val = 0x06010021 },
         { .reg = 0x00009888, .val = 0x14010030 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x06020880 },
         { .reg = 0x00009888, .val = 0x08020021 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x05010000 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x05020000 },
         { .reg = 0x00009888, .val = 0x11020C00 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x0001F00F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x0A030012 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00042055 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00051055 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0A080480 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x000820AA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12011000 },
         { .reg = 0x00009888, .val = 0x12021000 },
         { .reg = 0x00009888, .val = 0x13011000 },
         { .reg = 0x00009888, .val = 0x13021000 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x02070020 },
         { .reg = 0x00009888, .val = 0x020800CF },
         { .reg = 0x00009888, .val = 0x00090400 },
         { .reg = 0x00009888, .val = 0x020A0065 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x10010030 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00010300 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x0E020C00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x0308000C },
         { .reg = 0x00009888, .val = 0x01090100 },
         { .reg = 0x00009888, .val = 0x030A0006 },
         { .reg = 0x00009888, .val = 0x05010000 },
         { .reg = 0x00009888, .val = 0x0F010030 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x05020000 },
         { .reg = 0x00009888, .val = 0x0D020C00 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x08030012 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040200 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00050100 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x08080480 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00080200 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A0AA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031291 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030101 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x36032421 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38030FE9 },
         { .reg = 0x00009888, .val = 0x3A031F1F },
         { .reg = 0x00009888, .val = 0x3C0325E8 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032481 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe3__avg_gpu_core_frequency__max,acmgt2__color_pipe3__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1375, 24, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1376, 28, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1377, 32, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1378, 36, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2283, 40, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2284, 44, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2285, 48, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2286, 52, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency1_stall_cpipe7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1760, 56, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 1761, 60, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2287, 64, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2288, 68, percentage_max_float,acmgt2__color_pipe3__color_pipe_cache_latency2_stall_l3_node3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1383, 72, percentage_max_float,acmgt2__color_pipe3__ps_output_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1384, 76, percentage_max_float,acmgt2__color_pipe3__ps_output_available_cpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "ColorPipe4";
   query->symbol_name = "ColorPipe4";
   query->guid = "341991a5-3457-4201-a48e-d368a979f01d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x20860011 },
         { .reg = 0x00009888, .val = 0x20A60011 },
         { .reg = 0x00009888, .val = 0x20C60011 },
         { .reg = 0x00009888, .val = 0x20E60011 },
         { .reg = 0x00009888, .val = 0x04860180 },
         { .reg = 0x00009888, .val = 0x06862800 },
         { .reg = 0x00009888, .val = 0x08860595 },
         { .reg = 0x00009888, .val = 0x0A860017 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x04A60180 },
         { .reg = 0x00009888, .val = 0x0AA60500 },
         { .reg = 0x00009888, .val = 0x0CA60595 },
         { .reg = 0x00009888, .val = 0x0EA60017 },
         { .reg = 0x00009888, .val = 0x00A60000 },
         { .reg = 0x00009888, .val = 0x04C60180 },
         { .reg = 0x00009888, .val = 0x0EC60500 },
         { .reg = 0x00009888, .val = 0x10C60595 },
         { .reg = 0x00009888, .val = 0x12C60017 },
         { .reg = 0x00009888, .val = 0x02C60000 },
         { .reg = 0x00009888, .val = 0x04E60180 },
         { .reg = 0x00009888, .val = 0x12E60500 },
         { .reg = 0x00009888, .val = 0x14E60595 },
         { .reg = 0x00009888, .val = 0x16E60017 },
         { .reg = 0x00009888, .val = 0x02E60000 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe4__avg_gpu_core_frequency__max,acmgt2__color_pipe4__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1674, 24, percentage_max_float,acmgt2__color_pipe4__pixel_post_process_input_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1675, 28, percentage_max_float,acmgt2__color_pipe4__pixel_post_process_input_available_cpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "ColorPipe5";
   query->symbol_name = "ColorPipe5";
   query->guid = "34664510-6687-48d0-adc5-b7a60069de8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x21860011 },
         { .reg = 0x00009888, .val = 0x21A60011 },
         { .reg = 0x00009888, .val = 0x21C60011 },
         { .reg = 0x00009888, .val = 0x21E60011 },
         { .reg = 0x00009888, .val = 0x05860180 },
         { .reg = 0x00009888, .val = 0x07862800 },
         { .reg = 0x00009888, .val = 0x09860595 },
         { .reg = 0x00009888, .val = 0x0B860017 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x05A60180 },
         { .reg = 0x00009888, .val = 0x0BA60500 },
         { .reg = 0x00009888, .val = 0x0DA60595 },
         { .reg = 0x00009888, .val = 0x0FA60017 },
         { .reg = 0x00009888, .val = 0x01A60000 },
         { .reg = 0x00009888, .val = 0x05C60180 },
         { .reg = 0x00009888, .val = 0x0FC60500 },
         { .reg = 0x00009888, .val = 0x11C60595 },
         { .reg = 0x00009888, .val = 0x13C60017 },
         { .reg = 0x00009888, .val = 0x03C60000 },
         { .reg = 0x00009888, .val = 0x05E60180 },
         { .reg = 0x00009888, .val = 0x13E60500 },
         { .reg = 0x00009888, .val = 0x15E60595 },
         { .reg = 0x00009888, .val = 0x17E60017 },
         { .reg = 0x00009888, .val = 0x03E60000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe5__avg_gpu_core_frequency__max,acmgt2__color_pipe5__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1676, 24, percentage_max_float,acmgt2__color_pipe5__pixel_post_process_input_available_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1677, 28, percentage_max_float,acmgt2__color_pipe5__pixel_post_process_input_available_cpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "ColorPipe6";
   query->symbol_name = "ColorPipe6";
   query->guid = "1c9a3218-c1ee-402f-b483-6263a0757515";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x20860011 },
         { .reg = 0x00009888, .val = 0x20A60011 },
         { .reg = 0x00009888, .val = 0x20C60011 },
         { .reg = 0x00009888, .val = 0x20E60011 },
         { .reg = 0x00009888, .val = 0x04860180 },
         { .reg = 0x00009888, .val = 0x06862800 },
         { .reg = 0x00009888, .val = 0x08860595 },
         { .reg = 0x00009888, .val = 0x0A860017 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x04A60180 },
         { .reg = 0x00009888, .val = 0x0AA60500 },
         { .reg = 0x00009888, .val = 0x0CA60595 },
         { .reg = 0x00009888, .val = 0x0EA60017 },
         { .reg = 0x00009888, .val = 0x00A60000 },
         { .reg = 0x00009888, .val = 0x04C60180 },
         { .reg = 0x00009888, .val = 0x0EC60500 },
         { .reg = 0x00009888, .val = 0x10C60595 },
         { .reg = 0x00009888, .val = 0x12C60017 },
         { .reg = 0x00009888, .val = 0x02C60000 },
         { .reg = 0x00009888, .val = 0x04E60180 },
         { .reg = 0x00009888, .val = 0x12E60500 },
         { .reg = 0x00009888, .val = 0x14E60595 },
         { .reg = 0x00009888, .val = 0x16E60017 },
         { .reg = 0x00009888, .val = 0x02E60000 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe6__avg_gpu_core_frequency__max,acmgt2__color_pipe6__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2289, 24, percentage_max_float,acmgt2__color_pipe6__pixel_post_process_input_available_cpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2290, 28, percentage_max_float,acmgt2__color_pipe6__pixel_post_process_input_available_cpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "ColorPipe7";
   query->symbol_name = "ColorPipe7";
   query->guid = "d85dc73b-5121-44c8-87b2-df05b1eecdf3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x21860011 },
         { .reg = 0x00009888, .val = 0x21A60011 },
         { .reg = 0x00009888, .val = 0x21C60011 },
         { .reg = 0x00009888, .val = 0x21E60011 },
         { .reg = 0x00009888, .val = 0x05860180 },
         { .reg = 0x00009888, .val = 0x07862800 },
         { .reg = 0x00009888, .val = 0x09860595 },
         { .reg = 0x00009888, .val = 0x0B860017 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x05A60180 },
         { .reg = 0x00009888, .val = 0x0BA60500 },
         { .reg = 0x00009888, .val = 0x0DA60595 },
         { .reg = 0x00009888, .val = 0x0FA60017 },
         { .reg = 0x00009888, .val = 0x01A60000 },
         { .reg = 0x00009888, .val = 0x05C60180 },
         { .reg = 0x00009888, .val = 0x0FC60500 },
         { .reg = 0x00009888, .val = 0x11C60595 },
         { .reg = 0x00009888, .val = 0x13C60017 },
         { .reg = 0x00009888, .val = 0x03C60000 },
         { .reg = 0x00009888, .val = 0x05E60180 },
         { .reg = 0x00009888, .val = 0x13E60500 },
         { .reg = 0x00009888, .val = 0x15E60595 },
         { .reg = 0x00009888, .val = 0x17E60017 },
         { .reg = 0x00009888, .val = 0x03E60000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe7__avg_gpu_core_frequency__max,acmgt2__color_pipe7__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2291, 24, percentage_max_float,acmgt2__color_pipe7__pixel_post_process_input_available_cpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2292, 28, percentage_max_float,acmgt2__color_pipe7__pixel_post_process_input_available_cpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "ColorPipe8";
   query->symbol_name = "ColorPipe8";
   query->guid = "4695a23b-b2b0-48f5-8bf1-743255be3e2e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16010003 },
         { .reg = 0x00009888, .val = 0x16020003 },
         { .reg = 0x00009888, .val = 0x17010003 },
         { .reg = 0x00009888, .val = 0x19010320 },
         { .reg = 0x00009888, .val = 0x17020003 },
         { .reg = 0x00009888, .val = 0x19020320 },
         { .reg = 0x00009888, .val = 0x0003300F },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x00094000 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x14010017 },
         { .reg = 0x00009888, .val = 0x0001300F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x120205C0 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x010700A0 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x0108000F },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x0109100C },
         { .reg = 0x00009888, .val = 0x010A00A5 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x05011100 },
         { .reg = 0x00009888, .val = 0x07010021 },
         { .reg = 0x00009888, .val = 0x13010017 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x07020880 },
         { .reg = 0x00009888, .val = 0x09020021 },
         { .reg = 0x00009888, .val = 0x110205C0 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18010320 },
         { .reg = 0x00009888, .val = 0x18020320 },
         { .reg = 0x00009888, .val = 0x19010320 },
         { .reg = 0x00009888, .val = 0x19020320 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x00080F00 },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000900C0 },
         { .reg = 0x00009888, .val = 0x000AA500 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x08010880 },
         { .reg = 0x00009888, .val = 0x0A010021 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x0A020880 },
         { .reg = 0x00009888, .val = 0x0C020021 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x030700A0 },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x01090C00 },
         { .reg = 0x00009888, .val = 0x030A00A5 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x0D010880 },
         { .reg = 0x00009888, .val = 0x0F010021 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x0F020880 },
         { .reg = 0x00009888, .val = 0x11020021 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030004 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030481 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x380300E1 },
         { .reg = 0x00009888, .val = 0x3A030607 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032481 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F00F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe8__avg_gpu_core_frequency__max,acmgt2__color_pipe8__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1385, 24, percentage_max_float,acmgt2__color_pipe8__ps_output_available_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1386, 28, percentage_max_float,acmgt2__color_pipe8__ps_output_available_cpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2293, 32, percentage_max_float,acmgt2__color_pipe8__ps_output_available_cpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2294, 36, percentage_max_float,acmgt2__color_pipe8__ps_output_available_cpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2295, 40, percentage_max_float,acmgt2__color_pipe8__ps_output_available_cpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2296, 44, percentage_max_float,acmgt2__color_pipe8__ps_output_available_cpipe7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1379, 48, percentage_max_float,acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1380, 52, percentage_max_float,acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1381, 56, percentage_max_float,acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1382, 60, percentage_max_float,acmgt2__color_pipe8__pixel_post_process_output_ready_cpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "ColorPipe9";
   query->symbol_name = "ColorPipe9";
   query->guid = "73b4fa16-fd16-4c45-bb66-a733308a8b57";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x180301E9 },
         { .reg = 0x00009888, .val = 0x180801E9 },
         { .reg = 0x00009888, .val = 0x06030E30 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x000400A0 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x04080E30 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16010003 },
         { .reg = 0x00009888, .val = 0x16020003 },
         { .reg = 0x00009888, .val = 0x17010003 },
         { .reg = 0x00009888, .val = 0x17020003 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x00094000 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x14010017 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x120205C0 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x13010017 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x110205C0 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x180301E9 },
         { .reg = 0x00009888, .val = 0x180801E9 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x0A030E30 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x0004A000 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x08080E30 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x1203F000 },
         { .reg = 0x00009888, .val = 0x32030012 },
         { .reg = 0x00009888, .val = 0x2003F000 },
         { .reg = 0x00009888, .val = 0x36032240 },
         { .reg = 0x00009888, .val = 0x2603F000 },
         { .reg = 0x00009888, .val = 0x2C03F000 },
         { .reg = 0x00009888, .val = 0x380323E8 },
         { .reg = 0x00009888, .val = 0x3A031F1F },
         { .reg = 0x00009888, .val = 0x3C030FE7 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032060 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe9__avg_gpu_core_frequency__max,acmgt2__color_pipe9__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2297, 24, percentage_max_float,acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2298, 28, percentage_max_float,acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2299, 32, percentage_max_float,acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2300, 36, percentage_max_float,acmgt2__color_pipe9__pixel_post_process_output_ready_cpipe7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1648, 40, NULL,acmgt2__color_pipe9__render_cache_alloc_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1649, 48, NULL,acmgt2__color_pipe9__render_cache_alloc_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2301, 56, NULL,acmgt2__color_pipe9__render_cache_alloc_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2302, 64, NULL,acmgt2__color_pipe9__render_cache_alloc_l3_node3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ColorPipe10";
   query->symbol_name = "ColorPipe10";
   query->guid = "41a973fd-a067-4760-be3a-ccac78e0eadb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030E00 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030120 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe10__avg_gpu_core_frequency__max,acmgt2__color_pipe10__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1762, 24, NULL,acmgt2__color_pipe10__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ColorPipe11";
   query->symbol_name = "ColorPipe11";
   query->guid = "a42ec42b-53d5-40b2-8950-9aabe714601a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x4003001C },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030380 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe11__avg_gpu_core_frequency__max,acmgt2__color_pipe11__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1763, 24, NULL,acmgt2__color_pipe11__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ColorPipe12";
   query->symbol_name = "ColorPipe12";
   query->guid = "4682628b-6cc3-4b22-b818-ca5347cd7bf3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030E00 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030140 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe12__avg_gpu_core_frequency__max,acmgt2__color_pipe12__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2303, 24, NULL,acmgt2__color_pipe12__pixel_2x2_lit_post_rasterizer_early_depth_slice2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ColorPipe13";
   query->symbol_name = "ColorPipe13";
   query->guid = "76fcf17c-a3ad-474c-a2fb-58a1517c28f4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32037400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x4003001D },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340303A0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe13__avg_gpu_core_frequency__max,acmgt2__color_pipe13__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2304, 24, NULL,acmgt2__color_pipe13__pixel_2x2_lit_post_rasterizer_early_depth_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ColorPipe14";
   query->symbol_name = "ColorPipe14";
   query->guid = "6708cf0b-dd77-4fb7-aad1-909ffea99aea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030E00 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030120 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe14__avg_gpu_core_frequency__max,acmgt2__color_pipe14__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1764, 24, NULL,acmgt2__color_pipe14__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ColorPipe15";
   query->symbol_name = "ColorPipe15";
   query->guid = "cb36baf7-85bd-4ce3-a0d7-4d296c5932a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x4003001C },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030380 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe15__avg_gpu_core_frequency__max,acmgt2__color_pipe15__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1765, 24, NULL,acmgt2__color_pipe15__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ColorPipe16";
   query->symbol_name = "ColorPipe16";
   query->guid = "f1e33629-b9d8-4033-a791-2afb70f5bf8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030E00 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030140 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe16__avg_gpu_core_frequency__max,acmgt2__color_pipe16__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2305, 24, NULL,acmgt2__color_pipe16__pixel_2x2_lit_post_rasterizer_late_depth_slice2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_color_pipe17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ColorPipe17";
   query->symbol_name = "ColorPipe17";
   query->guid = "fb67c9e2-4acb-4775-b715-ffc4b743d9e8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32037400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x4003001D },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340303A0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__color_pipe17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__color_pipe17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__color_pipe17__avg_gpu_core_frequency__max,acmgt2__color_pipe17__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2306, 24, NULL,acmgt2__color_pipe17__pixel_2x2_lit_post_rasterizer_late_depth_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport1";
   query->symbol_name = "Dataport1";
   query->guid = "e0466349-b62f-474c-88f9-3a9b62a3274a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x20810011 },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x20A10011 },
         { .reg = 0x00009888, .val = 0x04810676 },
         { .reg = 0x00009888, .val = 0x088101C5 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x0E810206 },
         { .reg = 0x00009888, .val = 0x1081000B },
         { .reg = 0x00009888, .val = 0x16810580 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A02A },
         { .reg = 0x00009888, .val = 0x02838002 },
         { .reg = 0x00009888, .val = 0x008481C7 },
         { .reg = 0x00009888, .val = 0x00865015 },
         { .reg = 0x00009888, .val = 0x02864001 },
         { .reg = 0x00009888, .val = 0x00875015 },
         { .reg = 0x00009888, .val = 0x02874001 },
         { .reg = 0x00009888, .val = 0x04A10676 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C7 },
         { .reg = 0x00009888, .val = 0x10A10180 },
         { .reg = 0x00009888, .val = 0x12A102C8 },
         { .reg = 0x00009888, .val = 0x16A10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x02A320A8 },
         { .reg = 0x00009888, .val = 0x00A44E38 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x02A61054 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x02A71054 },
         { .reg = 0x00009888, .val = 0x0008AFEA },
         { .reg = 0x00009888, .val = 0x0208B0FE },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5055 },
         { .reg = 0x00009888, .val = 0x00014E38 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x020B1054 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032012 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603294A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000801 },
         { .reg = 0x0000D964, .val = 0x0000FEBE },
         { .reg = 0x0000D968, .val = 0x00004001 },
         { .reg = 0x0000D96C, .val = 0x0000F5F7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport1__avg_gpu_core_frequency__max,acmgt2__dataport1__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1163, 24, NULL,acmgt2__dataport1__xve_dataport_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1164, 32, NULL,acmgt2__dataport1__xve_dataport_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1171, 40, NULL,acmgt2__dataport1__xve_dataport_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1172, 48, NULL,acmgt2__dataport1__xve_dataport_write_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1179, 56, NULL,acmgt2__dataport1__xve_dataport_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1180, 64, NULL,acmgt2__dataport1__xve_dataport_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1784, 72, NULL,acmgt2__dataport1__xve_dataport_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1785, 80, NULL,acmgt2__dataport1__xve_dataport_fence_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport2";
   query->symbol_name = "Dataport2";
   query->guid = "28e63e4a-ae68-4913-9f28-ae9269aadf2b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x20C10011 },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x20E10011 },
         { .reg = 0x00009888, .val = 0x04C10676 },
         { .reg = 0x00009888, .val = 0x08C101C5 },
         { .reg = 0x00009888, .val = 0x0AC1000B },
         { .reg = 0x00009888, .val = 0x0EC10206 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x16C10580 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A02A },
         { .reg = 0x00009888, .val = 0x02C38002 },
         { .reg = 0x00009888, .val = 0x00C481C7 },
         { .reg = 0x00009888, .val = 0x00C65015 },
         { .reg = 0x00009888, .val = 0x02C64001 },
         { .reg = 0x00009888, .val = 0x00C75015 },
         { .reg = 0x00009888, .val = 0x02C74001 },
         { .reg = 0x00009888, .val = 0x04E10676 },
         { .reg = 0x00009888, .val = 0x0AE10140 },
         { .reg = 0x00009888, .val = 0x0CE102C7 },
         { .reg = 0x00009888, .val = 0x10E10180 },
         { .reg = 0x00009888, .val = 0x12E102C8 },
         { .reg = 0x00009888, .val = 0x16E10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30A80 },
         { .reg = 0x00009888, .val = 0x02E320A8 },
         { .reg = 0x00009888, .val = 0x00E44E38 },
         { .reg = 0x00009888, .val = 0x00E60540 },
         { .reg = 0x00009888, .val = 0x02E61054 },
         { .reg = 0x00009888, .val = 0x00E70540 },
         { .reg = 0x00009888, .val = 0x02E71054 },
         { .reg = 0x00009888, .val = 0x0007A56A },
         { .reg = 0x00009888, .val = 0x02079056 },
         { .reg = 0x00009888, .val = 0x0009CFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA0AA },
         { .reg = 0x00009888, .val = 0x000281C7 },
         { .reg = 0x00009888, .val = 0x000C5015 },
         { .reg = 0x00009888, .val = 0x020C4001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032012 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000801 },
         { .reg = 0x0000D964, .val = 0x0000FEBE },
         { .reg = 0x0000D968, .val = 0x00004001 },
         { .reg = 0x0000D96C, .val = 0x0000F5F7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport2__avg_gpu_core_frequency__max,acmgt2__dataport2__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1165, 24, NULL,acmgt2__dataport2__xve_dataport_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1166, 32, NULL,acmgt2__dataport2__xve_dataport_read_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1173, 40, NULL,acmgt2__dataport2__xve_dataport_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1174, 48, NULL,acmgt2__dataport2__xve_dataport_write_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1181, 56, NULL,acmgt2__dataport2__xve_dataport_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1182, 64, NULL,acmgt2__dataport2__xve_dataport_atomic_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1786, 72, NULL,acmgt2__dataport2__xve_dataport_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1787, 80, NULL,acmgt2__dataport2__xve_dataport_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport3";
   query->symbol_name = "Dataport3";
   query->guid = "f9dd355a-29ce-4f78-9ea4-e2f0f799876d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x21810011 },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x21A10011 },
         { .reg = 0x00009888, .val = 0x05810676 },
         { .reg = 0x00009888, .val = 0x098101C5 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x0F810206 },
         { .reg = 0x00009888, .val = 0x1181000B },
         { .reg = 0x00009888, .val = 0x17810580 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A02A },
         { .reg = 0x00009888, .val = 0x03838002 },
         { .reg = 0x00009888, .val = 0x018481C7 },
         { .reg = 0x00009888, .val = 0x01865015 },
         { .reg = 0x00009888, .val = 0x03864001 },
         { .reg = 0x00009888, .val = 0x01875015 },
         { .reg = 0x00009888, .val = 0x03874001 },
         { .reg = 0x00009888, .val = 0x05A10676 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C7 },
         { .reg = 0x00009888, .val = 0x11A10180 },
         { .reg = 0x00009888, .val = 0x13A102C8 },
         { .reg = 0x00009888, .val = 0x17A10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x03A320A8 },
         { .reg = 0x00009888, .val = 0x01A44E38 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x03A61054 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x03A71054 },
         { .reg = 0x00009888, .val = 0x0003CFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208F0FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5055 },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA0AA },
         { .reg = 0x00009888, .val = 0x0108AFEA },
         { .reg = 0x00009888, .val = 0x0308B0FE },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5055 },
         { .reg = 0x00009888, .val = 0x01014E38 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x030B1054 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032012 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603294A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000801 },
         { .reg = 0x0000D964, .val = 0x0000FEBE },
         { .reg = 0x0000D968, .val = 0x00004001 },
         { .reg = 0x0000D96C, .val = 0x0000F5F7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport3__avg_gpu_core_frequency__max,acmgt2__dataport3__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1167, 24, NULL,acmgt2__dataport3__xve_dataport_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1168, 32, NULL,acmgt2__dataport3__xve_dataport_read_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1175, 40, NULL,acmgt2__dataport3__xve_dataport_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1176, 48, NULL,acmgt2__dataport3__xve_dataport_write_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1183, 56, NULL,acmgt2__dataport3__xve_dataport_atomic_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1184, 64, NULL,acmgt2__dataport3__xve_dataport_atomic_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1788, 72, NULL,acmgt2__dataport3__xve_dataport_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1789, 80, NULL,acmgt2__dataport3__xve_dataport_fence_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport4";
   query->symbol_name = "Dataport4";
   query->guid = "d79af0bc-b6e9-4057-8eb8-f61fad6efe55";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x21C10011 },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x21E10011 },
         { .reg = 0x00009888, .val = 0x05C10676 },
         { .reg = 0x00009888, .val = 0x09C101C5 },
         { .reg = 0x00009888, .val = 0x0BC1000B },
         { .reg = 0x00009888, .val = 0x0FC10206 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x17C10580 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A02A },
         { .reg = 0x00009888, .val = 0x03C38002 },
         { .reg = 0x00009888, .val = 0x01C481C7 },
         { .reg = 0x00009888, .val = 0x01C65015 },
         { .reg = 0x00009888, .val = 0x03C64001 },
         { .reg = 0x00009888, .val = 0x01C75015 },
         { .reg = 0x00009888, .val = 0x03C74001 },
         { .reg = 0x00009888, .val = 0x05E10676 },
         { .reg = 0x00009888, .val = 0x0BE10140 },
         { .reg = 0x00009888, .val = 0x0DE102C7 },
         { .reg = 0x00009888, .val = 0x11E10180 },
         { .reg = 0x00009888, .val = 0x13E102C8 },
         { .reg = 0x00009888, .val = 0x17E10016 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E30A80 },
         { .reg = 0x00009888, .val = 0x03E320A8 },
         { .reg = 0x00009888, .val = 0x01E44E38 },
         { .reg = 0x00009888, .val = 0x01E60540 },
         { .reg = 0x00009888, .val = 0x03E61054 },
         { .reg = 0x00009888, .val = 0x01E70540 },
         { .reg = 0x00009888, .val = 0x03E71054 },
         { .reg = 0x00009888, .val = 0x0003CFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208F0FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5055 },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA0AA },
         { .reg = 0x00009888, .val = 0x0107A56A },
         { .reg = 0x00009888, .val = 0x03079056 },
         { .reg = 0x00009888, .val = 0x0109CFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA0AA },
         { .reg = 0x00009888, .val = 0x010281C7 },
         { .reg = 0x00009888, .val = 0x010C5015 },
         { .reg = 0x00009888, .val = 0x030C4001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032012 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000801 },
         { .reg = 0x0000D964, .val = 0x0000FEBE },
         { .reg = 0x0000D968, .val = 0x00004001 },
         { .reg = 0x0000D96C, .val = 0x0000F5F7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport4__avg_gpu_core_frequency__max,acmgt2__dataport4__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1169, 24, NULL,acmgt2__dataport4__xve_dataport_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1170, 32, NULL,acmgt2__dataport4__xve_dataport_read_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1177, 40, NULL,acmgt2__dataport4__xve_dataport_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1178, 48, NULL,acmgt2__dataport4__xve_dataport_write_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1185, 56, NULL,acmgt2__dataport4__xve_dataport_atomic_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1186, 64, NULL,acmgt2__dataport4__xve_dataport_atomic_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1790, 72, NULL,acmgt2__dataport4__xve_dataport_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1791, 80, NULL,acmgt2__dataport4__xve_dataport_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport5";
   query->symbol_name = "Dataport5";
   query->guid = "8890d6d6-bac2-4830-9abb-e38e1da08e0b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x20810011 },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x20A10011 },
         { .reg = 0x00009888, .val = 0x04810676 },
         { .reg = 0x00009888, .val = 0x088101C5 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x0E810206 },
         { .reg = 0x00009888, .val = 0x1081000B },
         { .reg = 0x00009888, .val = 0x16810580 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A02A },
         { .reg = 0x00009888, .val = 0x02838002 },
         { .reg = 0x00009888, .val = 0x008481C7 },
         { .reg = 0x00009888, .val = 0x00865015 },
         { .reg = 0x00009888, .val = 0x02864001 },
         { .reg = 0x00009888, .val = 0x00875015 },
         { .reg = 0x00009888, .val = 0x02874001 },
         { .reg = 0x00009888, .val = 0x04A10676 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C7 },
         { .reg = 0x00009888, .val = 0x10A10180 },
         { .reg = 0x00009888, .val = 0x12A102C8 },
         { .reg = 0x00009888, .val = 0x16A10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x02A320A8 },
         { .reg = 0x00009888, .val = 0x00A44E38 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x02A61054 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x02A71054 },
         { .reg = 0x00009888, .val = 0x0008AFEA },
         { .reg = 0x00009888, .val = 0x0208B0FE },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5055 },
         { .reg = 0x00009888, .val = 0x00014E38 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x020B1054 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202F0FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031009 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603294A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000801 },
         { .reg = 0x0000D964, .val = 0x0000FEBE },
         { .reg = 0x0000D968, .val = 0x00004001 },
         { .reg = 0x0000D96C, .val = 0x0000F5F7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport5__avg_gpu_core_frequency__max,acmgt2__dataport5__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2307, 24, NULL,acmgt2__dataport5__xve_dataport_read_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2308, 32, NULL,acmgt2__dataport5__xve_dataport_read_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2309, 40, NULL,acmgt2__dataport5__xve_dataport_write_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2310, 48, NULL,acmgt2__dataport5__xve_dataport_write_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2311, 56, NULL,acmgt2__dataport5__xve_dataport_atomic_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2312, 64, NULL,acmgt2__dataport5__xve_dataport_atomic_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2313, 72, NULL,acmgt2__dataport5__xve_dataport_fence_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2314, 80, NULL,acmgt2__dataport5__xve_dataport_fence_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport6";
   query->symbol_name = "Dataport6";
   query->guid = "c181f521-7c29-4ac6-a44e-d398043d1c41";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x20C10011 },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x20E10011 },
         { .reg = 0x00009888, .val = 0x04C10676 },
         { .reg = 0x00009888, .val = 0x08C101C5 },
         { .reg = 0x00009888, .val = 0x0AC1000B },
         { .reg = 0x00009888, .val = 0x0EC10206 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x16C10580 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A02A },
         { .reg = 0x00009888, .val = 0x02C38002 },
         { .reg = 0x00009888, .val = 0x00C481C7 },
         { .reg = 0x00009888, .val = 0x00C65015 },
         { .reg = 0x00009888, .val = 0x02C64001 },
         { .reg = 0x00009888, .val = 0x00C75015 },
         { .reg = 0x00009888, .val = 0x02C74001 },
         { .reg = 0x00009888, .val = 0x04E10676 },
         { .reg = 0x00009888, .val = 0x0AE10140 },
         { .reg = 0x00009888, .val = 0x0CE102C7 },
         { .reg = 0x00009888, .val = 0x10E10180 },
         { .reg = 0x00009888, .val = 0x12E102C8 },
         { .reg = 0x00009888, .val = 0x16E10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30A80 },
         { .reg = 0x00009888, .val = 0x02E320A8 },
         { .reg = 0x00009888, .val = 0x00E44E38 },
         { .reg = 0x00009888, .val = 0x00E60540 },
         { .reg = 0x00009888, .val = 0x02E61054 },
         { .reg = 0x00009888, .val = 0x00E70540 },
         { .reg = 0x00009888, .val = 0x02E71054 },
         { .reg = 0x00009888, .val = 0x0007A56A },
         { .reg = 0x00009888, .val = 0x02079056 },
         { .reg = 0x00009888, .val = 0x0009CFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA0AA },
         { .reg = 0x00009888, .val = 0x000281C7 },
         { .reg = 0x00009888, .val = 0x000C5015 },
         { .reg = 0x00009888, .val = 0x020C4001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202F0FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031009 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000801 },
         { .reg = 0x0000D964, .val = 0x0000FEBE },
         { .reg = 0x0000D968, .val = 0x00004001 },
         { .reg = 0x0000D96C, .val = 0x0000F5F7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport6__avg_gpu_core_frequency__max,acmgt2__dataport6__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2315, 24, NULL,acmgt2__dataport6__xve_dataport_read_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2316, 32, NULL,acmgt2__dataport6__xve_dataport_read_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2317, 40, NULL,acmgt2__dataport6__xve_dataport_write_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2318, 48, NULL,acmgt2__dataport6__xve_dataport_write_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2319, 56, NULL,acmgt2__dataport6__xve_dataport_atomic_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2320, 64, NULL,acmgt2__dataport6__xve_dataport_atomic_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2321, 72, NULL,acmgt2__dataport6__xve_dataport_fence_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2322, 80, NULL,acmgt2__dataport6__xve_dataport_fence_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport7";
   query->symbol_name = "Dataport7";
   query->guid = "b83732c6-e9b4-4449-90df-3d3518bcc6a2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x21810011 },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x21A10011 },
         { .reg = 0x00009888, .val = 0x05810676 },
         { .reg = 0x00009888, .val = 0x098101C5 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x0F810206 },
         { .reg = 0x00009888, .val = 0x1181000B },
         { .reg = 0x00009888, .val = 0x17810580 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A02A },
         { .reg = 0x00009888, .val = 0x03838002 },
         { .reg = 0x00009888, .val = 0x018481C7 },
         { .reg = 0x00009888, .val = 0x01865015 },
         { .reg = 0x00009888, .val = 0x03864001 },
         { .reg = 0x00009888, .val = 0x01875015 },
         { .reg = 0x00009888, .val = 0x03874001 },
         { .reg = 0x00009888, .val = 0x05A10676 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C7 },
         { .reg = 0x00009888, .val = 0x11A10180 },
         { .reg = 0x00009888, .val = 0x13A102C8 },
         { .reg = 0x00009888, .val = 0x17A10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x03A320A8 },
         { .reg = 0x00009888, .val = 0x01A44E38 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x03A61054 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x03A71054 },
         { .reg = 0x00009888, .val = 0x0003CFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208F0FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5055 },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA0AA },
         { .reg = 0x00009888, .val = 0x0108AFEA },
         { .reg = 0x00009888, .val = 0x0308B0FE },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5055 },
         { .reg = 0x00009888, .val = 0x01014E38 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x030B1054 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202F0FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031009 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603294A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000801 },
         { .reg = 0x0000D964, .val = 0x0000FEBE },
         { .reg = 0x0000D968, .val = 0x00004001 },
         { .reg = 0x0000D96C, .val = 0x0000F5F7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport7__avg_gpu_core_frequency__max,acmgt2__dataport7__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2323, 24, NULL,acmgt2__dataport7__xve_dataport_read_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2324, 32, NULL,acmgt2__dataport7__xve_dataport_read_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2325, 40, NULL,acmgt2__dataport7__xve_dataport_write_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2326, 48, NULL,acmgt2__dataport7__xve_dataport_write_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2327, 56, NULL,acmgt2__dataport7__xve_dataport_atomic_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2328, 64, NULL,acmgt2__dataport7__xve_dataport_atomic_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2329, 72, NULL,acmgt2__dataport7__xve_dataport_fence_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2330, 80, NULL,acmgt2__dataport7__xve_dataport_fence_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport8";
   query->symbol_name = "Dataport8";
   query->guid = "a82addb0-e73f-43a4-9b0a-89df6b2ad267";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x21C10011 },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x21E10011 },
         { .reg = 0x00009888, .val = 0x05C10676 },
         { .reg = 0x00009888, .val = 0x09C101C5 },
         { .reg = 0x00009888, .val = 0x0BC1000B },
         { .reg = 0x00009888, .val = 0x0FC10206 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x17C10580 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A02A },
         { .reg = 0x00009888, .val = 0x03C38002 },
         { .reg = 0x00009888, .val = 0x01C481C7 },
         { .reg = 0x00009888, .val = 0x01C65015 },
         { .reg = 0x00009888, .val = 0x03C64001 },
         { .reg = 0x00009888, .val = 0x01C75015 },
         { .reg = 0x00009888, .val = 0x03C74001 },
         { .reg = 0x00009888, .val = 0x05E10676 },
         { .reg = 0x00009888, .val = 0x0BE10140 },
         { .reg = 0x00009888, .val = 0x0DE102C7 },
         { .reg = 0x00009888, .val = 0x11E10180 },
         { .reg = 0x00009888, .val = 0x13E102C8 },
         { .reg = 0x00009888, .val = 0x17E10016 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E30A80 },
         { .reg = 0x00009888, .val = 0x03E320A8 },
         { .reg = 0x00009888, .val = 0x01E44E38 },
         { .reg = 0x00009888, .val = 0x01E60540 },
         { .reg = 0x00009888, .val = 0x03E61054 },
         { .reg = 0x00009888, .val = 0x01E70540 },
         { .reg = 0x00009888, .val = 0x03E71054 },
         { .reg = 0x00009888, .val = 0x0003CFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208F0FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5055 },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA0AA },
         { .reg = 0x00009888, .val = 0x0107A56A },
         { .reg = 0x00009888, .val = 0x03079056 },
         { .reg = 0x00009888, .val = 0x0109CFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA0AA },
         { .reg = 0x00009888, .val = 0x010281C7 },
         { .reg = 0x00009888, .val = 0x010C5015 },
         { .reg = 0x00009888, .val = 0x030C4001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202F0FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031009 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001CFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000801 },
         { .reg = 0x0000D964, .val = 0x0000FEBE },
         { .reg = 0x0000D968, .val = 0x00004001 },
         { .reg = 0x0000D96C, .val = 0x0000F5F7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport8__avg_gpu_core_frequency__max,acmgt2__dataport8__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2331, 24, NULL,acmgt2__dataport8__xve_dataport_read_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2332, 32, NULL,acmgt2__dataport8__xve_dataport_read_message_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2333, 40, NULL,acmgt2__dataport8__xve_dataport_write_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2334, 48, NULL,acmgt2__dataport8__xve_dataport_write_message_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2335, 56, NULL,acmgt2__dataport8__xve_dataport_atomic_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2336, 64, NULL,acmgt2__dataport8__xve_dataport_atomic_message_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2337, 72, NULL,acmgt2__dataport8__xve_dataport_fence_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2338, 80, NULL,acmgt2__dataport8__xve_dataport_fence_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport9";
   query->symbol_name = "Dataport9";
   query->guid = "91d91417-69c7-458d-bb48-d1c83871d61a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1881039B },
         { .reg = 0x00009888, .val = 0x18A1039B },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A810207 },
         { .reg = 0x00009888, .val = 0x0C810081 },
         { .reg = 0x00009888, .val = 0x0E810103 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x10A10185 },
         { .reg = 0x00009888, .val = 0x12A10207 },
         { .reg = 0x00009888, .val = 0x14A10081 },
         { .reg = 0x00009888, .val = 0x16A10103 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport9__avg_gpu_core_frequency__max,acmgt2__dataport9__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1115, 24, percentage_max_float,acmgt2__dataport9__dataport_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1116, 28, percentage_max_float,acmgt2__dataport9__dataport_input_available_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport10";
   query->symbol_name = "Dataport10";
   query->guid = "7bb38598-cd33-4e49-957c-cbe7ab599120";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18C1039B },
         { .reg = 0x00009888, .val = 0x18E1039B },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x08C10185 },
         { .reg = 0x00009888, .val = 0x0AC10207 },
         { .reg = 0x00009888, .val = 0x0CC10081 },
         { .reg = 0x00009888, .val = 0x0EC10103 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E10185 },
         { .reg = 0x00009888, .val = 0x12E10207 },
         { .reg = 0x00009888, .val = 0x14E10081 },
         { .reg = 0x00009888, .val = 0x16E10103 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport10__avg_gpu_core_frequency__max,acmgt2__dataport10__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1117, 24, percentage_max_float,acmgt2__dataport10__dataport_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1118, 28, percentage_max_float,acmgt2__dataport10__dataport_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport11";
   query->symbol_name = "Dataport11";
   query->guid = "8108a31f-3d5d-46f3-8cd0-6c9b2c3e0038";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1981039B },
         { .reg = 0x00009888, .val = 0x19A1039B },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B810207 },
         { .reg = 0x00009888, .val = 0x0D810081 },
         { .reg = 0x00009888, .val = 0x0F810103 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x11A10185 },
         { .reg = 0x00009888, .val = 0x13A10207 },
         { .reg = 0x00009888, .val = 0x15A10081 },
         { .reg = 0x00009888, .val = 0x17A10103 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport11__avg_gpu_core_frequency__max,acmgt2__dataport11__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1119, 24, percentage_max_float,acmgt2__dataport11__dataport_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1120, 28, percentage_max_float,acmgt2__dataport11__dataport_input_available_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport12";
   query->symbol_name = "Dataport12";
   query->guid = "c7acfa27-136c-4527-8e81-517c6a2aa724";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19C1039B },
         { .reg = 0x00009888, .val = 0x19E1039B },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x09C10185 },
         { .reg = 0x00009888, .val = 0x0BC10207 },
         { .reg = 0x00009888, .val = 0x0DC10081 },
         { .reg = 0x00009888, .val = 0x0FC10103 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x11E10185 },
         { .reg = 0x00009888, .val = 0x13E10207 },
         { .reg = 0x00009888, .val = 0x15E10081 },
         { .reg = 0x00009888, .val = 0x17E10103 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport12__avg_gpu_core_frequency__max,acmgt2__dataport12__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1121, 24, percentage_max_float,acmgt2__dataport12__dataport_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1122, 28, percentage_max_float,acmgt2__dataport12__dataport_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport13";
   query->symbol_name = "Dataport13";
   query->guid = "10c1bda5-f032-4e6e-8597-741046aa81c4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1881039B },
         { .reg = 0x00009888, .val = 0x18A1039B },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A810207 },
         { .reg = 0x00009888, .val = 0x0C810081 },
         { .reg = 0x00009888, .val = 0x0E810103 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x10A10185 },
         { .reg = 0x00009888, .val = 0x12A10207 },
         { .reg = 0x00009888, .val = 0x14A10081 },
         { .reg = 0x00009888, .val = 0x16A10103 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport13__avg_gpu_core_frequency__max,acmgt2__dataport13__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2339, 24, percentage_max_float,acmgt2__dataport13__dataport_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2340, 28, percentage_max_float,acmgt2__dataport13__dataport_input_available_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport14";
   query->symbol_name = "Dataport14";
   query->guid = "9e026386-432e-42ce-8bb8-c833127dbbe7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18C1039B },
         { .reg = 0x00009888, .val = 0x18E1039B },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x08C10185 },
         { .reg = 0x00009888, .val = 0x0AC10207 },
         { .reg = 0x00009888, .val = 0x0CC10081 },
         { .reg = 0x00009888, .val = 0x0EC10103 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E10185 },
         { .reg = 0x00009888, .val = 0x12E10207 },
         { .reg = 0x00009888, .val = 0x14E10081 },
         { .reg = 0x00009888, .val = 0x16E10103 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport14__avg_gpu_core_frequency__max,acmgt2__dataport14__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2341, 24, percentage_max_float,acmgt2__dataport14__dataport_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2342, 28, percentage_max_float,acmgt2__dataport14__dataport_input_available_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport15";
   query->symbol_name = "Dataport15";
   query->guid = "51c4a645-0ffe-4dc2-bc5c-30075c771f71";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1981039B },
         { .reg = 0x00009888, .val = 0x19A1039B },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B810207 },
         { .reg = 0x00009888, .val = 0x0D810081 },
         { .reg = 0x00009888, .val = 0x0F810103 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x11A10185 },
         { .reg = 0x00009888, .val = 0x13A10207 },
         { .reg = 0x00009888, .val = 0x15A10081 },
         { .reg = 0x00009888, .val = 0x17A10103 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport15__avg_gpu_core_frequency__max,acmgt2__dataport15__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2343, 24, percentage_max_float,acmgt2__dataport15__dataport_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2344, 28, percentage_max_float,acmgt2__dataport15__dataport_input_available_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport16";
   query->symbol_name = "Dataport16";
   query->guid = "4699e9f0-8029-44dc-9f86-23ee43b2592e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19C1039B },
         { .reg = 0x00009888, .val = 0x19E1039B },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x09C10185 },
         { .reg = 0x00009888, .val = 0x0BC10207 },
         { .reg = 0x00009888, .val = 0x0DC10081 },
         { .reg = 0x00009888, .val = 0x0FC10103 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x11E10185 },
         { .reg = 0x00009888, .val = 0x13E10207 },
         { .reg = 0x00009888, .val = 0x15E10081 },
         { .reg = 0x00009888, .val = 0x17E10103 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport16__avg_gpu_core_frequency__max,acmgt2__dataport16__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2345, 24, percentage_max_float,acmgt2__dataport16__dataport_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2346, 28, percentage_max_float,acmgt2__dataport16__dataport_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Dataport17";
   query->symbol_name = "Dataport17";
   query->guid = "eae3432b-6340-4d86-bae1-3d6da5d6f9c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281C000 },
         { .reg = 0x00009888, .val = 0x12A1C000 },
         { .reg = 0x00009888, .val = 0x12C1C4D2 },
         { .reg = 0x00009888, .val = 0x12E1C000 },
         { .reg = 0x00009888, .val = 0x04810200 },
         { .reg = 0x00009888, .val = 0x08810450 },
         { .reg = 0x00009888, .val = 0x0A8104D2 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x04A10200 },
         { .reg = 0x00009888, .val = 0x0CA10450 },
         { .reg = 0x00009888, .val = 0x0EA104D2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x04C10200 },
         { .reg = 0x00009888, .val = 0x10C10450 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x02C70055 },
         { .reg = 0x00009888, .val = 0x04E10200 },
         { .reg = 0x00009888, .val = 0x14E10450 },
         { .reg = 0x00009888, .val = 0x16E104D2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport17__avg_gpu_core_frequency__max,acmgt2__dataport17__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1123, 24, percentage_max_float,acmgt2__dataport17__dataport_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1124, 28, percentage_max_float,acmgt2__dataport17__dataport_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1125, 32, percentage_max_float,acmgt2__dataport17__dataport_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1126, 36, percentage_max_float,acmgt2__dataport17__dataport_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Dataport18";
   query->symbol_name = "Dataport18";
   query->guid = "fc5c5c04-55ea-4094-92fc-1d40f7f132b0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381C000 },
         { .reg = 0x00009888, .val = 0x13A1C000 },
         { .reg = 0x00009888, .val = 0x13C1C4D2 },
         { .reg = 0x00009888, .val = 0x13E1C000 },
         { .reg = 0x00009888, .val = 0x05810200 },
         { .reg = 0x00009888, .val = 0x09810450 },
         { .reg = 0x00009888, .val = 0x0B8104D2 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x05A10200 },
         { .reg = 0x00009888, .val = 0x0DA10450 },
         { .reg = 0x00009888, .val = 0x0FA104D2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x05C10200 },
         { .reg = 0x00009888, .val = 0x11C10450 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x03C70055 },
         { .reg = 0x00009888, .val = 0x05E10200 },
         { .reg = 0x00009888, .val = 0x15E10450 },
         { .reg = 0x00009888, .val = 0x17E104D2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x03E75500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport18__avg_gpu_core_frequency__max,acmgt2__dataport18__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1127, 24, percentage_max_float,acmgt2__dataport18__dataport_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1128, 28, percentage_max_float,acmgt2__dataport18__dataport_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1129, 32, percentage_max_float,acmgt2__dataport18__dataport_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1130, 36, percentage_max_float,acmgt2__dataport18__dataport_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport19_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Dataport19";
   query->symbol_name = "Dataport19";
   query->guid = "66cc68bd-b460-42ec-b815-2531dc145a33";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1281C000 },
         { .reg = 0x00009888, .val = 0x12A1C000 },
         { .reg = 0x00009888, .val = 0x12C1C4D2 },
         { .reg = 0x00009888, .val = 0x12E1C000 },
         { .reg = 0x00009888, .val = 0x04810200 },
         { .reg = 0x00009888, .val = 0x08810450 },
         { .reg = 0x00009888, .val = 0x0A8104D2 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x04A10200 },
         { .reg = 0x00009888, .val = 0x0CA10450 },
         { .reg = 0x00009888, .val = 0x0EA104D2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x04C10200 },
         { .reg = 0x00009888, .val = 0x10C10450 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x02C70055 },
         { .reg = 0x00009888, .val = 0x04E10200 },
         { .reg = 0x00009888, .val = 0x14E10450 },
         { .reg = 0x00009888, .val = 0x16E104D2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport19__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport19__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport19__avg_gpu_core_frequency__max,acmgt2__dataport19__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2347, 24, percentage_max_float,acmgt2__dataport19__dataport_output_ready_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2348, 28, percentage_max_float,acmgt2__dataport19__dataport_output_ready_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2349, 32, percentage_max_float,acmgt2__dataport19__dataport_output_ready_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2350, 36, percentage_max_float,acmgt2__dataport19__dataport_output_ready_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport20_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Dataport20";
   query->symbol_name = "Dataport20";
   query->guid = "c3f17ea7-bdba-4ce6-971e-9920ae779870";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1381C000 },
         { .reg = 0x00009888, .val = 0x13A1C000 },
         { .reg = 0x00009888, .val = 0x13C1C4D2 },
         { .reg = 0x00009888, .val = 0x13E1C000 },
         { .reg = 0x00009888, .val = 0x05810200 },
         { .reg = 0x00009888, .val = 0x09810450 },
         { .reg = 0x00009888, .val = 0x0B8104D2 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x05A10200 },
         { .reg = 0x00009888, .val = 0x0DA10450 },
         { .reg = 0x00009888, .val = 0x0FA104D2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x05C10200 },
         { .reg = 0x00009888, .val = 0x11C10450 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x03C70055 },
         { .reg = 0x00009888, .val = 0x05E10200 },
         { .reg = 0x00009888, .val = 0x15E10450 },
         { .reg = 0x00009888, .val = 0x17E104D2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x03E75500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport20__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport20__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport20__avg_gpu_core_frequency__max,acmgt2__dataport20__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2351, 24, percentage_max_float,acmgt2__dataport20__dataport_output_ready_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2352, 28, percentage_max_float,acmgt2__dataport20__dataport_output_ready_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2353, 32, percentage_max_float,acmgt2__dataport20__dataport_output_ready_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2354, 36, percentage_max_float,acmgt2__dataport20__dataport_output_ready_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport21";
   query->symbol_name = "Dataport21";
   query->guid = "fe3d6064-fb8d-4c1c-8375-65c1b2d23287";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport21__avg_gpu_core_frequency__max,acmgt2__dataport21__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1131, 24, NULL,acmgt2__dataport21__dataport_byte_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1132, 32, NULL,acmgt2__dataport21__dataport_byte_read_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport22";
   query->symbol_name = "Dataport22";
   query->guid = "ca29a63a-9e93-4631-befe-cb0985365d3b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport22__avg_gpu_core_frequency__max,acmgt2__dataport22__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1133, 24, NULL,acmgt2__dataport22__dataport_byte_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1134, 32, NULL,acmgt2__dataport22__dataport_byte_read_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport23";
   query->symbol_name = "Dataport23";
   query->guid = "f194891f-8915-4c9d-978e-4ef91c44d5d1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport23__avg_gpu_core_frequency__max,acmgt2__dataport23__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1135, 24, NULL,acmgt2__dataport23__dataport_byte_read_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1136, 32, NULL,acmgt2__dataport23__dataport_byte_read_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport24_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport24";
   query->symbol_name = "Dataport24";
   query->guid = "62bac6fb-20ca-4fbf-b821-cd80ecdcb57b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport24__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport24__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport24__avg_gpu_core_frequency__max,acmgt2__dataport24__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1137, 24, NULL,acmgt2__dataport24__dataport_byte_read_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1138, 32, NULL,acmgt2__dataport24__dataport_byte_read_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport25_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport25";
   query->symbol_name = "Dataport25";
   query->guid = "7a2a2ce5-0e00-429b-9d96-ce5c030378e2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport25__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport25__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport25__avg_gpu_core_frequency__max,acmgt2__dataport25__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2355, 24, NULL,acmgt2__dataport25__dataport_byte_read_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2356, 32, NULL,acmgt2__dataport25__dataport_byte_read_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport26_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport26";
   query->symbol_name = "Dataport26";
   query->guid = "d6169119-c923-4d10-b16e-6439fa5e150d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport26__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport26__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport26__avg_gpu_core_frequency__max,acmgt2__dataport26__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2357, 24, NULL,acmgt2__dataport26__dataport_byte_read_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2358, 32, NULL,acmgt2__dataport26__dataport_byte_read_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport27_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport27";
   query->symbol_name = "Dataport27";
   query->guid = "703a8fb1-96b2-4c89-ad1b-f721efa0fade";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport27__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport27__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport27__avg_gpu_core_frequency__max,acmgt2__dataport27__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2359, 24, NULL,acmgt2__dataport27__dataport_byte_read_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2360, 32, NULL,acmgt2__dataport27__dataport_byte_read_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport28";
   query->symbol_name = "Dataport28";
   query->guid = "7d3ea8fa-f0e2-4436-bfed-2cfd5d42e3fa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport28__avg_gpu_core_frequency__max,acmgt2__dataport28__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2361, 24, NULL,acmgt2__dataport28__dataport_byte_read_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2362, 32, NULL,acmgt2__dataport28__dataport_byte_read_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport29_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Dataport29";
   query->symbol_name = "Dataport29";
   query->guid = "f42d9eaa-4a36-4b10-a96e-6794cbbdc43a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x16810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x16A10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x14C10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x14E10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x13810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x13A10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x11C10580 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x11E10016 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0E810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0EA10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0CC10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0CE10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0B810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0BA10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x09C10580 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x09E10016 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C8A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030EE2 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C0314E0 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030528 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport29__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport29__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport29__avg_gpu_core_frequency__max,acmgt2__dataport29__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1139, 24, NULL,acmgt2__dataport29__dataport_byte_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1140, 32, NULL,acmgt2__dataport29__dataport_byte_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1141, 40, NULL,acmgt2__dataport29__dataport_byte_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1142, 48, NULL,acmgt2__dataport29__dataport_byte_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1143, 56, NULL,acmgt2__dataport29__dataport_byte_write_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1144, 64, NULL,acmgt2__dataport29__dataport_byte_write_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1145, 72, NULL,acmgt2__dataport29__dataport_byte_write_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1146, 80, NULL,acmgt2__dataport29__dataport_byte_write_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2363, 88, NULL,acmgt2__dataport29__dataport_byte_write_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2364, 96, NULL,acmgt2__dataport29__dataport_byte_write_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2365, 104, NULL,acmgt2__dataport29__dataport_byte_write_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2366, 112, NULL,acmgt2__dataport29__dataport_byte_write_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2367, 120, NULL,acmgt2__dataport29__dataport_byte_write_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2368, 128, NULL,acmgt2__dataport29__dataport_byte_write_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2369, 136, NULL,acmgt2__dataport29__dataport_byte_write_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2370, 144, NULL,acmgt2__dataport29__dataport_byte_write_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport30_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport30";
   query->symbol_name = "Dataport30";
   query->guid = "6805565e-e6aa-41a8-b486-4f1ca91c11c9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x188102FD },
         { .reg = 0x00009888, .val = 0x18A102FD },
         { .reg = 0x00009888, .val = 0x18C102FD },
         { .reg = 0x00009888, .val = 0x18E102FD },
         { .reg = 0x00009888, .val = 0x198102FD },
         { .reg = 0x00009888, .val = 0x19A102FD },
         { .reg = 0x00009888, .val = 0x19C102FD },
         { .reg = 0x00009888, .val = 0x19E102FD },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x168103C2 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x02875000 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x14A103C2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70500 },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x12C103C2 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C70050 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E103C2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x0F8103C2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x01875000 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x0DA103C2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70500 },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x0BC103C2 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C70050 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x09E103C2 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E70005 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203210A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030230 },
         { .reg = 0x00009888, .val = 0x3C030422 },
         { .reg = 0x00009888, .val = 0x3E030E77 },
         { .reg = 0x00009888, .val = 0x40030007 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport30__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport30__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport30__avg_gpu_core_frequency__max,acmgt2__dataport30__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1195, 24, NULL,acmgt2__dataport30__xve_dataport_register_request_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1196, 32, NULL,acmgt2__dataport30__xve_dataport_register_request_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1197, 40, NULL,acmgt2__dataport30__xve_dataport_register_request_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1198, 48, NULL,acmgt2__dataport30__xve_dataport_register_request_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1199, 56, NULL,acmgt2__dataport30__xve_dataport_register_request_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1200, 64, NULL,acmgt2__dataport30__xve_dataport_register_request_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1201, 72, NULL,acmgt2__dataport30__xve_dataport_register_request_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1202, 80, NULL,acmgt2__dataport30__xve_dataport_register_request_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Dataport31";
   query->symbol_name = "Dataport31";
   query->guid = "c4d2235c-1d4b-44b7-b746-a11016520ffd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x188102FD },
         { .reg = 0x00009888, .val = 0x18A102FD },
         { .reg = 0x00009888, .val = 0x18C102FD },
         { .reg = 0x00009888, .val = 0x18E102FD },
         { .reg = 0x00009888, .val = 0x198102FD },
         { .reg = 0x00009888, .val = 0x19A102FD },
         { .reg = 0x00009888, .val = 0x19C102FD },
         { .reg = 0x00009888, .val = 0x19E102FD },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x168103C2 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x02875000 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x14A103C2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70500 },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x12C103C2 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C70050 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E103C2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x0F8103C2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x01875000 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x0DA103C2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70500 },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x0BC103C2 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C70050 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x09E103C2 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E70005 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203210A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030230 },
         { .reg = 0x00009888, .val = 0x3C030422 },
         { .reg = 0x00009888, .val = 0x3E030E77 },
         { .reg = 0x00009888, .val = 0x40030007 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport31__avg_gpu_core_frequency__max,acmgt2__dataport31__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2371, 24, NULL,acmgt2__dataport31__xve_dataport_register_request_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2372, 32, NULL,acmgt2__dataport31__xve_dataport_register_request_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2373, 40, NULL,acmgt2__dataport31__xve_dataport_register_request_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2374, 48, NULL,acmgt2__dataport31__xve_dataport_register_request_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2375, 56, NULL,acmgt2__dataport31__xve_dataport_register_request_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2376, 64, NULL,acmgt2__dataport31__xve_dataport_register_request_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2377, 72, NULL,acmgt2__dataport31__xve_dataport_register_request_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2378, 80, NULL,acmgt2__dataport31__xve_dataport_register_request_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport32_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport32";
   query->symbol_name = "Dataport32";
   query->guid = "1f7d4994-5397-410c-98ed-5e1bc3d44ceb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport32__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport32__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport32__avg_gpu_core_frequency__max,acmgt2__dataport32__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1187, 24, NULL,acmgt2__dataport32__xve_dataport_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1188, 32, NULL,acmgt2__dataport32__xve_dataport_register_response_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport33_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport33";
   query->symbol_name = "Dataport33";
   query->guid = "42d54580-601f-4dcb-9c91-c5bd37782f65";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport33__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport33__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport33__avg_gpu_core_frequency__max,acmgt2__dataport33__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1189, 24, NULL,acmgt2__dataport33__xve_dataport_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1190, 28, NULL,acmgt2__dataport33__xve_dataport_register_response_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport34_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport34";
   query->symbol_name = "Dataport34";
   query->guid = "0ce98a1c-8516-4412-b1ce-b0eeaca989df";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport34__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport34__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport34__avg_gpu_core_frequency__max,acmgt2__dataport34__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1191, 24, NULL,acmgt2__dataport34__xve_dataport_register_response_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1192, 28, NULL,acmgt2__dataport34__xve_dataport_register_response_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport35";
   query->symbol_name = "Dataport35";
   query->guid = "857f49c7-71b4-4fa0-86f0-55f817676cff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport35__avg_gpu_core_frequency__max,acmgt2__dataport35__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1193, 24, NULL,acmgt2__dataport35__xve_dataport_register_response_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1194, 28, NULL,acmgt2__dataport35__xve_dataport_register_response_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport36_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport36";
   query->symbol_name = "Dataport36";
   query->guid = "dde58e8e-e867-4144-9782-4464798e7c63";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport36__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport36__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport36__avg_gpu_core_frequency__max,acmgt2__dataport36__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2379, 24, NULL,acmgt2__dataport36__xve_dataport_register_response_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2380, 28, NULL,acmgt2__dataport36__xve_dataport_register_response_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport37_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport37";
   query->symbol_name = "Dataport37";
   query->guid = "fd0e95c3-0a28-4911-80d7-dad9716739c3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport37__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport37__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport37__avg_gpu_core_frequency__max,acmgt2__dataport37__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2381, 24, NULL,acmgt2__dataport37__xve_dataport_register_response_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2382, 28, NULL,acmgt2__dataport37__xve_dataport_register_response_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport38_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport38";
   query->symbol_name = "Dataport38";
   query->guid = "ac3fa7ef-1963-4643-917f-9f9b6161ee62";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport38__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport38__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport38__avg_gpu_core_frequency__max,acmgt2__dataport38__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2383, 24, NULL,acmgt2__dataport38__xve_dataport_register_response_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2384, 28, NULL,acmgt2__dataport38__xve_dataport_register_response_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Dataport39";
   query->symbol_name = "Dataport39";
   query->guid = "ca4e1039-7322-4606-b3cc-7f33dcb93301";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport39__avg_gpu_core_frequency__max,acmgt2__dataport39__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2385, 24, NULL,acmgt2__dataport39__xve_dataport_register_response_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2386, 28, NULL,acmgt2__dataport39__xve_dataport_register_response_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport40_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Dataport40";
   query->symbol_name = "Dataport40";
   query->guid = "3712af1f-03c7-48e3-b2a5-6d9ac64b3122";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E810020 },
         { .reg = 0x00009888, .val = 0x1EA10020 },
         { .reg = 0x00009888, .val = 0x1EC10020 },
         { .reg = 0x00009888, .val = 0x1EE10020 },
         { .reg = 0x00009888, .val = 0x1F810020 },
         { .reg = 0x00009888, .val = 0x1FA10020 },
         { .reg = 0x00009888, .val = 0x1FC10020 },
         { .reg = 0x00009888, .val = 0x1FE10020 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x16810440 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x16A10011 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x14C10440 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x14E10011 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x13810440 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x13A10011 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x11C10440 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x11E10011 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E810020 },
         { .reg = 0x00009888, .val = 0x1EA10020 },
         { .reg = 0x00009888, .val = 0x1EC10020 },
         { .reg = 0x00009888, .val = 0x1EE10020 },
         { .reg = 0x00009888, .val = 0x1F810020 },
         { .reg = 0x00009888, .val = 0x1FA10020 },
         { .reg = 0x00009888, .val = 0x1FC10020 },
         { .reg = 0x00009888, .val = 0x1FE10020 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0E810440 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0EA10011 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0CC10440 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0CE10011 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0B810440 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0BA10011 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x09C10440 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x09E10011 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C8A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030EE2 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C0314E0 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030528 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport40__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport40__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport40__avg_gpu_core_frequency__max,acmgt2__dataport40__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1147, 24, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1148, 32, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1149, 40, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1150, 48, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1151, 56, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1152, 64, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1153, 72, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1154, 80, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2387, 88, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2388, 96, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2389, 104, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2390, 112, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2391, 120, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2392, 128, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2393, 136, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2394, 144, NULL,acmgt2__dataport40__dataport_texture_cache_access_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_dataport41_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Dataport41";
   query->symbol_name = "Dataport41";
   query->guid = "3df5cfc4-865d-4314-a53a-379d76aac638";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2081001F },
         { .reg = 0x00009888, .val = 0x20A1001F },
         { .reg = 0x00009888, .val = 0x20C1001F },
         { .reg = 0x00009888, .val = 0x20E1001F },
         { .reg = 0x00009888, .val = 0x2181001F },
         { .reg = 0x00009888, .val = 0x21A1001F },
         { .reg = 0x00009888, .val = 0x21C1001F },
         { .reg = 0x00009888, .val = 0x21E1001F },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x16810500 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x16A10014 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x14C10500 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x14E10014 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x13810500 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x13A10014 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x11C10500 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x11E10014 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2081001F },
         { .reg = 0x00009888, .val = 0x20A1001F },
         { .reg = 0x00009888, .val = 0x20C1001F },
         { .reg = 0x00009888, .val = 0x20E1001F },
         { .reg = 0x00009888, .val = 0x2181001F },
         { .reg = 0x00009888, .val = 0x21A1001F },
         { .reg = 0x00009888, .val = 0x21C1001F },
         { .reg = 0x00009888, .val = 0x21E1001F },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x0E810500 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x0EA10014 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x0CC10500 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x0CE10014 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x0B810500 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x0BA10014 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x09C10500 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x09E10014 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C8A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030EE2 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C0314E0 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030528 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__dataport41__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__dataport41__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__dataport41__avg_gpu_core_frequency__max,acmgt2__dataport41__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1155, 24, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1156, 32, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1157, 40, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1158, 48, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1159, 56, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1160, 64, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1161, 72, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1162, 80, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2395, 88, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2396, 96, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2397, 104, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2398, 112, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2399, 120, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2400, 128, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2401, 136, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2402, 144, NULL,acmgt2__dataport41__dataport_texture_cache_hit_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "DepthPipe1";
   query->symbol_name = "DepthPipe1";
   query->guid = "33168209-e5ab-4330-856c-0d4a1b95dce3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x100B5500 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x060B0150 },
         { .reg = 0x00009888, .val = 0x120B0493 },
         { .reg = 0x00009888, .val = 0x140B0411 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe1__avg_gpu_core_frequency__max,acmgt2__depth_pipe1__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1431, 24, NULL,acmgt2__depth_pipe1__early_depth_stencil_test_fail_np_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1432, 32, NULL,acmgt2__depth_pipe1__early_depth_stencil_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "DepthPipe2";
   query->symbol_name = "DepthPipe2";
   query->guid = "ada82722-0eaf-4903-96f0-3c8ed2227c7f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x100C5500 },
         { .reg = 0x00009888, .val = 0x00070002 },
         { .reg = 0x00009888, .val = 0x0207AA80 },
         { .reg = 0x00009888, .val = 0x0009F801 },
         { .reg = 0x00009888, .val = 0x000A0002 },
         { .reg = 0x00009888, .val = 0x020AAA80 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x060C0150 },
         { .reg = 0x00009888, .val = 0x120C0493 },
         { .reg = 0x00009888, .val = 0x140C0411 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe2__avg_gpu_core_frequency__max,acmgt2__depth_pipe2__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1433, 24, NULL,acmgt2__depth_pipe2__early_depth_stencil_test_fail_np_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1434, 32, NULL,acmgt2__depth_pipe2__early_depth_stencil_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "DepthPipe3";
   query->symbol_name = "DepthPipe3";
   query->guid = "359bdac8-5929-4e54-a5e5-526b28a487ab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x110B5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01080003 },
         { .reg = 0x00009888, .val = 0x0308FFC0 },
         { .reg = 0x00009888, .val = 0x010A0001 },
         { .reg = 0x00009888, .val = 0x030A5540 },
         { .reg = 0x00009888, .val = 0x0101F801 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x070B0150 },
         { .reg = 0x00009888, .val = 0x130B0493 },
         { .reg = 0x00009888, .val = 0x150B0411 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe3__avg_gpu_core_frequency__max,acmgt2__depth_pipe3__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1435, 24, NULL,acmgt2__depth_pipe3__early_depth_stencil_test_fail_np_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1436, 32, NULL,acmgt2__depth_pipe3__early_depth_stencil_test_fail_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "DepthPipe4";
   query->symbol_name = "DepthPipe4";
   query->guid = "1b8e5aa0-be13-4c87-9ad0-f0d4f7d7f2a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x110C5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0307AA80 },
         { .reg = 0x00009888, .val = 0x0109F801 },
         { .reg = 0x00009888, .val = 0x010A0002 },
         { .reg = 0x00009888, .val = 0x030AAA80 },
         { .reg = 0x00009888, .val = 0x0102F801 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x070C0150 },
         { .reg = 0x00009888, .val = 0x130C0493 },
         { .reg = 0x00009888, .val = 0x150C0411 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe4__avg_gpu_core_frequency__max,acmgt2__depth_pipe4__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1437, 24, NULL,acmgt2__depth_pipe4__early_depth_stencil_test_fail_np_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1438, 32, NULL,acmgt2__depth_pipe4__early_depth_stencil_test_fail_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "DepthPipe5";
   query->symbol_name = "DepthPipe5";
   query->guid = "b192f113-23af-494e-82e7-b9a81810c75d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x100B5500 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x060B0150 },
         { .reg = 0x00009888, .val = 0x120B0493 },
         { .reg = 0x00009888, .val = 0x140B0411 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020003 },
         { .reg = 0x00009888, .val = 0x0202FFC0 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe5__avg_gpu_core_frequency__max,acmgt2__depth_pipe5__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2403, 24, NULL,acmgt2__depth_pipe5__early_depth_stencil_test_fail_np_zpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2404, 32, NULL,acmgt2__depth_pipe5__early_depth_stencil_test_fail_p_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "DepthPipe6";
   query->symbol_name = "DepthPipe6";
   query->guid = "f617db06-51cc-447d-989c-0811dc7c7b38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x100C5500 },
         { .reg = 0x00009888, .val = 0x00070002 },
         { .reg = 0x00009888, .val = 0x0207AA80 },
         { .reg = 0x00009888, .val = 0x0009F801 },
         { .reg = 0x00009888, .val = 0x000A0002 },
         { .reg = 0x00009888, .val = 0x020AAA80 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x060C0150 },
         { .reg = 0x00009888, .val = 0x120C0493 },
         { .reg = 0x00009888, .val = 0x140C0411 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020003 },
         { .reg = 0x00009888, .val = 0x0202FFC0 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe6__avg_gpu_core_frequency__max,acmgt2__depth_pipe6__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2405, 24, NULL,acmgt2__depth_pipe6__early_depth_stencil_test_fail_np_zpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2406, 32, NULL,acmgt2__depth_pipe6__early_depth_stencil_test_fail_p_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "DepthPipe7";
   query->symbol_name = "DepthPipe7";
   query->guid = "bd2422a2-0a56-476d-a52d-b4aa15a5d842";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x110B5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01080003 },
         { .reg = 0x00009888, .val = 0x0308FFC0 },
         { .reg = 0x00009888, .val = 0x010A0001 },
         { .reg = 0x00009888, .val = 0x030A5540 },
         { .reg = 0x00009888, .val = 0x0101F801 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x070B0150 },
         { .reg = 0x00009888, .val = 0x130B0493 },
         { .reg = 0x00009888, .val = 0x150B0411 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020003 },
         { .reg = 0x00009888, .val = 0x0202FFC0 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe7__avg_gpu_core_frequency__max,acmgt2__depth_pipe7__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2407, 24, NULL,acmgt2__depth_pipe7__early_depth_stencil_test_fail_np_zpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2408, 32, NULL,acmgt2__depth_pipe7__early_depth_stencil_test_fail_p_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "DepthPipe8";
   query->symbol_name = "DepthPipe8";
   query->guid = "7856d434-02e6-4a06-b585-e45e7616f1d5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x110C5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0307AA80 },
         { .reg = 0x00009888, .val = 0x0109F801 },
         { .reg = 0x00009888, .val = 0x010A0002 },
         { .reg = 0x00009888, .val = 0x030AAA80 },
         { .reg = 0x00009888, .val = 0x0102F801 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x070C0150 },
         { .reg = 0x00009888, .val = 0x130C0493 },
         { .reg = 0x00009888, .val = 0x150C0411 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020003 },
         { .reg = 0x00009888, .val = 0x0202FFC0 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe8__avg_gpu_core_frequency__max,acmgt2__depth_pipe8__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2409, 24, NULL,acmgt2__depth_pipe8__early_depth_stencil_test_fail_np_zpipe7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2410, 32, NULL,acmgt2__depth_pipe8__early_depth_stencil_test_fail_p_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe9";
   query->symbol_name = "DepthPipe9";
   query->guid = "60b56817-8e14-488e-917d-29bffd9fefbb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030020 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe9__avg_gpu_core_frequency__max,acmgt2__depth_pipe9__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1439, 24, NULL,acmgt2__depth_pipe9__hiz_depth_test_ambig_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe10";
   query->symbol_name = "DepthPipe10";
   query->guid = "8dff928f-699b-4f34-a297-cf46c9519662";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030080 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe10__avg_gpu_core_frequency__max,acmgt2__depth_pipe10__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1440, 24, NULL,acmgt2__depth_pipe10__hiz_depth_test_ambig_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe11";
   query->symbol_name = "DepthPipe11";
   query->guid = "fa8e2ae9-3507-4eed-9a02-b18c396a21b1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32037C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x4003001F },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340303E0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe11__avg_gpu_core_frequency__max,acmgt2__depth_pipe11__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1441, 24, NULL,acmgt2__depth_pipe11__hiz_depth_test_ambig_np_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe12";
   query->symbol_name = "DepthPipe12";
   query->guid = "4736a783-c2f3-4f67-931f-eca0fdddf57f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe12__avg_gpu_core_frequency__max,acmgt2__depth_pipe12__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1442, 24, NULL,acmgt2__depth_pipe12__hiz_depth_test_ambig_np_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe13";
   query->symbol_name = "DepthPipe13";
   query->guid = "a305b93f-dba5-4318-89ba-051192cbe1be";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe13__avg_gpu_core_frequency__max,acmgt2__depth_pipe13__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2411, 24, NULL,acmgt2__depth_pipe13__hiz_depth_test_ambig_np_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe14";
   query->symbol_name = "DepthPipe14";
   query->guid = "dcfc3d88-b9bd-424b-b3ca-854f2e2d4863";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030005 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340300A0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe14__avg_gpu_core_frequency__max,acmgt2__depth_pipe14__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2412, 24, NULL,acmgt2__depth_pipe14__hiz_depth_test_ambig_np_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe15";
   query->symbol_name = "DepthPipe15";
   query->guid = "d706dc1e-e6c8-4fe0-b6ed-ea99cdc41673";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe15__avg_gpu_core_frequency__max,acmgt2__depth_pipe15__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2413, 24, NULL,acmgt2__depth_pipe15__hiz_depth_test_ambig_np_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe16";
   query->symbol_name = "DepthPipe16";
   query->guid = "de4874a3-6881-43a8-9243-6af156af44e5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030060 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe16__avg_gpu_core_frequency__max,acmgt2__depth_pipe16__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2414, 24, NULL,acmgt2__depth_pipe16__hiz_depth_test_ambig_np_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe17";
   query->symbol_name = "DepthPipe17";
   query->guid = "c3d18c22-f267-4f8a-8b4e-b26abd1d1660";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030020 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe17__avg_gpu_core_frequency__max,acmgt2__depth_pipe17__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1443, 24, NULL,acmgt2__depth_pipe17__hiz_depth_test_ambig_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe18";
   query->symbol_name = "DepthPipe18";
   query->guid = "0fa14813-96d3-424b-8935-b70b4e24ea85";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030080 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe18__avg_gpu_core_frequency__max,acmgt2__depth_pipe18__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1444, 24, NULL,acmgt2__depth_pipe18__hiz_depth_test_ambig_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe19_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe19";
   query->symbol_name = "DepthPipe19";
   query->guid = "4e741dfb-12e7-4a31-8bed-1d587c0cafc5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32037C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x4003001F },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340303E0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe19__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe19__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe19__avg_gpu_core_frequency__max,acmgt2__depth_pipe19__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1445, 24, NULL,acmgt2__depth_pipe19__hiz_depth_test_ambig_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe20_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe20";
   query->symbol_name = "DepthPipe20";
   query->guid = "66117e26-8834-4f72-b8f3-162bafb24232";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe20__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe20__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe20__avg_gpu_core_frequency__max,acmgt2__depth_pipe20__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1446, 24, NULL,acmgt2__depth_pipe20__hiz_depth_test_ambig_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe21";
   query->symbol_name = "DepthPipe21";
   query->guid = "4b9e649c-1392-4856-abe6-9e67bb06ac5e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe21__avg_gpu_core_frequency__max,acmgt2__depth_pipe21__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2415, 24, NULL,acmgt2__depth_pipe21__hiz_depth_test_ambig_p_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe22";
   query->symbol_name = "DepthPipe22";
   query->guid = "ced7882f-f88d-431c-9dad-8f3016a64777";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030005 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340300A0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe22__avg_gpu_core_frequency__max,acmgt2__depth_pipe22__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2416, 24, NULL,acmgt2__depth_pipe22__hiz_depth_test_ambig_p_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe23";
   query->symbol_name = "DepthPipe23";
   query->guid = "17ba725c-bcfb-444c-8725-fe9bc1a99c5b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe23__avg_gpu_core_frequency__max,acmgt2__depth_pipe23__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2417, 24, NULL,acmgt2__depth_pipe23__hiz_depth_test_ambig_p_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe24_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe24";
   query->symbol_name = "DepthPipe24";
   query->guid = "efdfcd4f-8bc6-4251-b956-dfd351f8632e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030060 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe24__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe24__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe24__avg_gpu_core_frequency__max,acmgt2__depth_pipe24__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2418, 24, NULL,acmgt2__depth_pipe24__hiz_depth_test_ambig_p_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe25_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe25";
   query->symbol_name = "DepthPipe25";
   query->guid = "bad6c158-57f6-471f-a9e3-cad9e779d211";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030020 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe25__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe25__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe25__avg_gpu_core_frequency__max,acmgt2__depth_pipe25__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1447, 24, NULL,acmgt2__depth_pipe25__hiz_depth_test_fail_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe26_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe26";
   query->symbol_name = "DepthPipe26";
   query->guid = "4a7b11ce-2d9e-4905-99c4-ededa640b342";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030080 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe26__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe26__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe26__avg_gpu_core_frequency__max,acmgt2__depth_pipe26__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1448, 24, NULL,acmgt2__depth_pipe26__hiz_depth_test_fail_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe27_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe27";
   query->symbol_name = "DepthPipe27";
   query->guid = "8c0a8f9b-3e97-4b6d-adb1-fbecb395ec00";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32037C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x4003001F },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340303E0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe27__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe27__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe27__avg_gpu_core_frequency__max,acmgt2__depth_pipe27__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1449, 24, NULL,acmgt2__depth_pipe27__hiz_depth_test_fail_np_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe28";
   query->symbol_name = "DepthPipe28";
   query->guid = "b7471c18-89e6-4e6d-826c-5f0ca0791154";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe28__avg_gpu_core_frequency__max,acmgt2__depth_pipe28__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1450, 24, NULL,acmgt2__depth_pipe28__hiz_depth_test_fail_np_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe29_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe29";
   query->symbol_name = "DepthPipe29";
   query->guid = "36d7c5ca-28e3-41c8-8e2b-f67beba4b23f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe29__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe29__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe29__avg_gpu_core_frequency__max,acmgt2__depth_pipe29__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2419, 24, NULL,acmgt2__depth_pipe29__hiz_depth_test_fail_np_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe30_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe30";
   query->symbol_name = "DepthPipe30";
   query->guid = "1bfbb150-1614-49a3-973b-7972bf7c9a91";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030005 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340300A0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe30__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe30__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe30__avg_gpu_core_frequency__max,acmgt2__depth_pipe30__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2420, 24, NULL,acmgt2__depth_pipe30__hiz_depth_test_fail_np_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe31";
   query->symbol_name = "DepthPipe31";
   query->guid = "80d75f6a-6c5b-46c9-a3a7-1911e2cba86e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe31__avg_gpu_core_frequency__max,acmgt2__depth_pipe31__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2421, 24, NULL,acmgt2__depth_pipe31__hiz_depth_test_fail_np_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe32_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe32";
   query->symbol_name = "DepthPipe32";
   query->guid = "3368bfa2-0680-4282-aaf1-9ec1a1713b82";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030060 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe32__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe32__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe32__avg_gpu_core_frequency__max,acmgt2__depth_pipe32__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2422, 24, NULL,acmgt2__depth_pipe32__hiz_depth_test_fail_np_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe33_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe33";
   query->symbol_name = "DepthPipe33";
   query->guid = "101b4d80-895b-4957-9f24-18456078793a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030020 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe33__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe33__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe33__avg_gpu_core_frequency__max,acmgt2__depth_pipe33__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1451, 24, NULL,acmgt2__depth_pipe33__hiz_depth_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe34_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe34";
   query->symbol_name = "DepthPipe34";
   query->guid = "342e501a-0038-412c-9e8a-a9ed02b7b9ef";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030080 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe34__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe34__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe34__avg_gpu_core_frequency__max,acmgt2__depth_pipe34__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1452, 24, NULL,acmgt2__depth_pipe34__hiz_depth_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe35";
   query->symbol_name = "DepthPipe35";
   query->guid = "5c4a1a1c-3df5-43af-adb0-9cd78dd944f8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32037C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x4003001F },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340303E0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe35__avg_gpu_core_frequency__max,acmgt2__depth_pipe35__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1453, 24, NULL,acmgt2__depth_pipe35__hiz_depth_test_fail_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe36_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe36";
   query->symbol_name = "DepthPipe36";
   query->guid = "f19a51db-ff00-40c0-a13f-1c404e80652e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe36__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe36__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe36__avg_gpu_core_frequency__max,acmgt2__depth_pipe36__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1454, 24, NULL,acmgt2__depth_pipe36__hiz_depth_test_fail_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe37_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe37";
   query->symbol_name = "DepthPipe37";
   query->guid = "6f269feb-2743-4953-a8b4-7e4b000901bc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe37__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe37__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe37__avg_gpu_core_frequency__max,acmgt2__depth_pipe37__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2423, 24, NULL,acmgt2__depth_pipe37__hiz_depth_test_fail_p_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe38_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe38";
   query->symbol_name = "DepthPipe38";
   query->guid = "7b9d22cb-7c4e-4885-be22-833c310e7fd4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030005 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340300A0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe38__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe38__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe38__avg_gpu_core_frequency__max,acmgt2__depth_pipe38__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2424, 24, NULL,acmgt2__depth_pipe38__hiz_depth_test_fail_p_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe39";
   query->symbol_name = "DepthPipe39";
   query->guid = "482c20b4-68c5-4656-8de2-039b2ca8a0f9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe39__avg_gpu_core_frequency__max,acmgt2__depth_pipe39__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2425, 24, NULL,acmgt2__depth_pipe39__hiz_depth_test_fail_p_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe40_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe40";
   query->symbol_name = "DepthPipe40";
   query->guid = "743ffcbc-c6d5-4b28-b58c-1d23d1ea8fff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030060 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe40__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe40__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe40__avg_gpu_core_frequency__max,acmgt2__depth_pipe40__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2426, 24, NULL,acmgt2__depth_pipe40__hiz_depth_test_fail_p_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe41_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe41";
   query->symbol_name = "DepthPipe41";
   query->guid = "f809a7a3-2248-480c-b851-1b23f3d6e7f2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030020 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B6000 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B0008 },
         { .reg = 0x00009888, .val = 0x120B0009 },
         { .reg = 0x00009888, .val = 0x140B000A },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe41__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe41__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe41__avg_gpu_core_frequency__max,acmgt2__depth_pipe41__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1455, 24, NULL,acmgt2__depth_pipe41__hiz_depth_test_pass_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe42_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe42";
   query->symbol_name = "DepthPipe42";
   query->guid = "effaccd8-6f1c-4a50-b39b-3a0f75eebf66";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030080 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C6000 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C0008 },
         { .reg = 0x00009888, .val = 0x120C0009 },
         { .reg = 0x00009888, .val = 0x140C000A },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe42__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe42__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe42__avg_gpu_core_frequency__max,acmgt2__depth_pipe42__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1456, 24, NULL,acmgt2__depth_pipe42__hiz_depth_test_pass_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe43_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe43";
   query->symbol_name = "DepthPipe43";
   query->guid = "39b392ed-3513-4c3f-9b22-bde5a9ee725c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32037C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x4003001F },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340303E0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B6000 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B0008 },
         { .reg = 0x00009888, .val = 0x130B0009 },
         { .reg = 0x00009888, .val = 0x150B000A },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe43__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe43__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe43__avg_gpu_core_frequency__max,acmgt2__depth_pipe43__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1457, 24, NULL,acmgt2__depth_pipe43__hiz_depth_test_pass_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe44_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe44";
   query->symbol_name = "DepthPipe44";
   query->guid = "adb868c4-97f3-420f-b766-073244232afb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C6000 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C0008 },
         { .reg = 0x00009888, .val = 0x130C0009 },
         { .reg = 0x00009888, .val = 0x150C000A },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe44__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe44__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe44__avg_gpu_core_frequency__max,acmgt2__depth_pipe44__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1458, 24, NULL,acmgt2__depth_pipe44__hiz_depth_test_pass_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe45";
   query->symbol_name = "DepthPipe45";
   query->guid = "71825303-a777-4079-85e0-69ee3f3caad3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030800 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030040 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B6000 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B0008 },
         { .reg = 0x00009888, .val = 0x120B0009 },
         { .reg = 0x00009888, .val = 0x140B000A },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe45__avg_gpu_core_frequency__max,acmgt2__depth_pipe45__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2427, 24, NULL,acmgt2__depth_pipe45__hiz_depth_test_pass_p_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe46_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe46";
   query->symbol_name = "DepthPipe46";
   query->guid = "2e086ff4-e74f-45bd-82d7-599a27a9aaba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031400 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030005 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x340300A0 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C6000 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C0008 },
         { .reg = 0x00009888, .val = 0x120C0009 },
         { .reg = 0x00009888, .val = 0x140C000A },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe46__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe46__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe46__avg_gpu_core_frequency__max,acmgt2__depth_pipe46__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2428, 24, NULL,acmgt2__depth_pipe46__hiz_depth_test_pass_p_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe47_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe47";
   query->symbol_name = "DepthPipe47";
   query->guid = "b0b33553-4e1c-445d-8e40-c03873ef1d5e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B6000 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B0008 },
         { .reg = 0x00009888, .val = 0x130B0009 },
         { .reg = 0x00009888, .val = 0x150B000A },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe47__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe47__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe47__avg_gpu_core_frequency__max,acmgt2__depth_pipe47__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2429, 24, NULL,acmgt2__depth_pipe47__hiz_depth_test_pass_p_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe48_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "DepthPipe48";
   query->symbol_name = "DepthPipe48";
   query->guid = "154e627a-ce2c-4d36-a441-dae9e8317fba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023333 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C00 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E031E00 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030060 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C6000 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C0008 },
         { .reg = 0x00009888, .val = 0x130C0009 },
         { .reg = 0x00009888, .val = 0x150C000A },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe48__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe48__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe48__avg_gpu_core_frequency__max,acmgt2__depth_pipe48__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2430, 24, NULL,acmgt2__depth_pipe48__hiz_depth_test_pass_p_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe49_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "DepthPipe49";
   query->symbol_name = "DepthPipe49";
   query->guid = "8d79b860-44be-4e17-bd33-eb95a7d6ad47";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B2C00 },
         { .reg = 0x00009888, .val = 0x100B6000 },
         { .reg = 0x00009888, .val = 0x160C2C00 },
         { .reg = 0x00009888, .val = 0x100C6000 },
         { .reg = 0x00009888, .val = 0x170B2C00 },
         { .reg = 0x00009888, .val = 0x110B6000 },
         { .reg = 0x00009888, .val = 0x170C2C00 },
         { .reg = 0x00009888, .val = 0x110C6000 },
         { .reg = 0x00009888, .val = 0x00033030 },
         { .reg = 0x00009888, .val = 0x00072000 },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x0008CF00 },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x00094040 },
         { .reg = 0x00009888, .val = 0x000A6500 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x0001B0B0 },
         { .reg = 0x00009888, .val = 0x040B0084 },
         { .reg = 0x00009888, .val = 0x0C0B0540 },
         { .reg = 0x00009888, .val = 0x140B0080 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0A00 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x00024040 },
         { .reg = 0x00009888, .val = 0x040C0084 },
         { .reg = 0x00009888, .val = 0x0C0C0015 },
         { .reg = 0x00009888, .val = 0x140C0002 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x01070200 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x01080C00 },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x01091010 },
         { .reg = 0x00009888, .val = 0x010A0600 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x01012020 },
         { .reg = 0x00009888, .val = 0x050B0084 },
         { .reg = 0x00009888, .val = 0x0B0B0540 },
         { .reg = 0x00009888, .val = 0x130B0080 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01021010 },
         { .reg = 0x00009888, .val = 0x050C0084 },
         { .reg = 0x00009888, .val = 0x0B0C0015 },
         { .reg = 0x00009888, .val = 0x130C0002 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B2C00 },
         { .reg = 0x00009888, .val = 0x100B6080 },
         { .reg = 0x00009888, .val = 0x160C2C00 },
         { .reg = 0x00009888, .val = 0x100C6002 },
         { .reg = 0x00009888, .val = 0x170B2C00 },
         { .reg = 0x00009888, .val = 0x110B6000 },
         { .reg = 0x00009888, .val = 0x170C2C00 },
         { .reg = 0x00009888, .val = 0x110C6000 },
         { .reg = 0x00009888, .val = 0x00030303 },
         { .reg = 0x00009888, .val = 0x00070020 },
         { .reg = 0x00009888, .val = 0x02070020 },
         { .reg = 0x00009888, .val = 0x000800CF },
         { .reg = 0x00009888, .val = 0x020800CF },
         { .reg = 0x00009888, .val = 0x00090404 },
         { .reg = 0x00009888, .val = 0x000A0065 },
         { .reg = 0x00009888, .val = 0x020A0065 },
         { .reg = 0x00009888, .val = 0x00010B0B },
         { .reg = 0x00009888, .val = 0x040B0084 },
         { .reg = 0x00009888, .val = 0x080B0540 },
         { .reg = 0x00009888, .val = 0x000B000A },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x00020404 },
         { .reg = 0x00009888, .val = 0x040C0084 },
         { .reg = 0x00009888, .val = 0x080C0015 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x0108000C },
         { .reg = 0x00009888, .val = 0x0308000C },
         { .reg = 0x00009888, .val = 0x01090101 },
         { .reg = 0x00009888, .val = 0x010A0006 },
         { .reg = 0x00009888, .val = 0x030A0006 },
         { .reg = 0x00009888, .val = 0x01010202 },
         { .reg = 0x00009888, .val = 0x050B0084 },
         { .reg = 0x00009888, .val = 0x070B5400 },
         { .reg = 0x00009888, .val = 0x0F0B0080 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01020101 },
         { .reg = 0x00009888, .val = 0x050C0084 },
         { .reg = 0x00009888, .val = 0x070C0150 },
         { .reg = 0x00009888, .val = 0x0F0C0002 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030100 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032061 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030200 },
         { .reg = 0x00009888, .val = 0x3A030640 },
         { .reg = 0x00009888, .val = 0x3C0302E9 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032481 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010F0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe49__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe49__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe49__avg_gpu_core_frequency__max,acmgt2__depth_pipe49__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1459, 24, percentage_max_float,acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1460, 28, percentage_max_float,acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1461, 32, percentage_max_float,acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1462, 36, percentage_max_float,acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2431, 40, percentage_max_float,acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2432, 44, percentage_max_float,acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2433, 48, percentage_max_float,acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2434, 52, percentage_max_float,acmgt2__depth_pipe49__hiz_subspan_latency_fifofull_zpipe7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1463, 56, percentage_max_float,acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1464, 60, percentage_max_float,acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1465, 64, percentage_max_float,acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1466, 68, percentage_max_float,acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2435, 72, percentage_max_float,acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2436, 76, percentage_max_float,acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2437, 80, percentage_max_float,acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2438, 84, percentage_max_float,acmgt2__depth_pipe49__iz_subspan_latency_fifofull_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_depth_pipe50_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "DepthPipe50";
   query->symbol_name = "DepthPipe50";
   query->guid = "980f1b68-a258-493e-aad2-8b40a0923a67";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0C0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C6000 },
         { .reg = 0x00009888, .val = 0x0D0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C6000 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x00094000 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x0001B000 },
         { .reg = 0x00009888, .val = 0x040B0000 },
         { .reg = 0x00009888, .val = 0x140B0580 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x040C0000 },
         { .reg = 0x00009888, .val = 0x140C0016 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x01012000 },
         { .reg = 0x00009888, .val = 0x050B0000 },
         { .reg = 0x00009888, .val = 0x130B0580 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01021000 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x130C0016 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0C0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C6000 },
         { .reg = 0x00009888, .val = 0x0D0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C6000 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x02070020 },
         { .reg = 0x00009888, .val = 0x020800CF },
         { .reg = 0x00009888, .val = 0x00090400 },
         { .reg = 0x00009888, .val = 0x020A0065 },
         { .reg = 0x00009888, .val = 0x00010B00 },
         { .reg = 0x00009888, .val = 0x040B0000 },
         { .reg = 0x00009888, .val = 0x100B0580 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x00020400 },
         { .reg = 0x00009888, .val = 0x040C0000 },
         { .reg = 0x00009888, .val = 0x100C0016 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x0308000C },
         { .reg = 0x00009888, .val = 0x01090100 },
         { .reg = 0x00009888, .val = 0x030A0006 },
         { .reg = 0x00009888, .val = 0x01010200 },
         { .reg = 0x00009888, .val = 0x050B0000 },
         { .reg = 0x00009888, .val = 0x0F0B0580 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01020100 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x0F0C0016 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x02031200 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x32030100 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032481 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x36030001 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__depth_pipe50__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__depth_pipe50__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__depth_pipe50__avg_gpu_core_frequency__max,acmgt2__depth_pipe50__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1467, 24, percentage_max_float,acmgt2__depth_pipe50__iz_output_ready_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1468, 28, percentage_max_float,acmgt2__depth_pipe50__iz_output_ready_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1469, 32, percentage_max_float,acmgt2__depth_pipe50__iz_output_ready_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1470, 36, percentage_max_float,acmgt2__depth_pipe50__iz_output_ready_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2439, 40, percentage_max_float,acmgt2__depth_pipe50__iz_output_ready_zpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2440, 44, percentage_max_float,acmgt2__depth_pipe50__iz_output_ready_zpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2441, 48, percentage_max_float,acmgt2__depth_pipe50__iz_output_ready_zpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2442, 52, percentage_max_float,acmgt2__depth_pipe50__iz_output_ready_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_front_end1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "FrontEnd1";
   query->symbol_name = "FrontEnd1";
   query->guid = "502ad763-3720-4e28-93c2-6d9e4383c8b2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x420A7C00 },
         { .reg = 0x00009888, .val = 0x1A133E00 },
         { .reg = 0x00009888, .val = 0x040A0022 },
         { .reg = 0x00009888, .val = 0x140A0540 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x02100084 },
         { .reg = 0x00009888, .val = 0x02120004 },
         { .reg = 0x00009888, .val = 0x00134000 },
         { .reg = 0x00009888, .val = 0x0C130025 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x420A7C00 },
         { .reg = 0x00009888, .val = 0x1A133E00 },
         { .reg = 0x00009888, .val = 0x040A0022 },
         { .reg = 0x00009888, .val = 0x140A0015 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x02100021 },
         { .reg = 0x00009888, .val = 0x02120001 },
         { .reg = 0x00009888, .val = 0x00134000 },
         { .reg = 0x00009888, .val = 0x0A130940 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1A017C00 },
         { .reg = 0x00009888, .val = 0x2804001F },
         { .reg = 0x00009888, .val = 0x24047C00 },
         { .reg = 0x00009888, .val = 0x3004001F },
         { .reg = 0x00009888, .val = 0x2C047C00 },
         { .reg = 0x00009888, .val = 0x4404001F },
         { .reg = 0x00009888, .val = 0x40043E00 },
         { .reg = 0x00009888, .val = 0x04010006 },
         { .reg = 0x00009888, .val = 0x14010140 },
         { .reg = 0x00009888, .val = 0x00015505 },
         { .reg = 0x00009888, .val = 0x02015400 },
         { .reg = 0x00009888, .val = 0x040436FB },
         { .reg = 0x00009888, .val = 0x06043E69 },
         { .reg = 0x00009888, .val = 0x08048C00 },
         { .reg = 0x00009888, .val = 0x0A040022 },
         { .reg = 0x00009888, .val = 0x0C040900 },
         { .reg = 0x00009888, .val = 0x0E040420 },
         { .reg = 0x00009888, .val = 0x10040000 },
         { .reg = 0x00009888, .val = 0x1604076D },
         { .reg = 0x00009888, .val = 0x1804000D },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x02040000 },
         { .reg = 0x00009888, .val = 0x00085505 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009888, .val = 0x02050066 },
         { .reg = 0x00009888, .val = 0x00032012 },
         { .reg = 0x00009888, .val = 0x02034892 },
         { .reg = 0x00009888, .val = 0x040324A4 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x38031460 },
         { .reg = 0x00009888, .val = 0x3A0306A3 },
         { .reg = 0x00009888, .val = 0x3C03146A },
         { .reg = 0x00009888, .val = 0x3E030010 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34032942 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__front_end1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__front_end1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__front_end1__avg_gpu_core_frequency__max,acmgt2__front_end1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 1471, 24, percentage_max_float,acmgt2__front_end1__command_parser_compute_engine_busy_ccs0__read);

      intel_perf_query_add_counter_float(query, 1472, 28, percentage_max_float,acmgt2__front_end1__command_parser_compute_engine_busy_ccs1__read);

      intel_perf_query_add_counter_float(query, 2443, 32, percentage_max_float,acmgt2__front_end1__command_parser_compute_engine_busy__read);

      intel_perf_query_add_counter_float(query, 1475, 36, percentage_max_float,acmgt2__front_end1__command_parser_render_engine_busy__read);

      intel_perf_query_add_counter_float(query, 1483, 40, percentage_max_float,acmgt2__front_end1__command_parser_copy_engine_busy__read);

      intel_perf_query_add_counter_float(query, 1484, 44, percentage_max_float,acmgt2__front_end1__command_parser_video_engine_busy_vdbox0__read);

      intel_perf_query_add_counter_float(query, 1485, 48, percentage_max_float,acmgt2__front_end1__command_parser_video_engine_busy_vdbox1__read);

      intel_perf_query_add_counter_float(query, 1486, 52, percentage_max_float,acmgt2__front_end1__command_parser_video_enhancement_engine_busy_vebox0__read);

      intel_perf_query_add_counter_float(query, 1487, 56, percentage_max_float,acmgt2__front_end1__command_parser_video_enhancement_engine_busy_vebox1__read);

      intel_perf_query_add_counter_float(query, 2444, 60, percentage_max_float,acmgt2__front_end1__command_parser_video_engine_busy__read);

      intel_perf_query_add_counter_float(query, 2445, 64, percentage_max_float,acmgt2__front_end1__command_parser_video_enhancement_engine_busy__read);

      intel_perf_query_add_counter_uint64(query, 1476, 72, NULL,acmgt2__front_end1__command_parser_compute_engine_dispatch_kernel_count_ccs0__read);

      intel_perf_query_add_counter_uint64(query, 1477, 80, NULL,acmgt2__front_end1__command_parser_compute_engine_dispatch_kernel_count_ccs1__read);

      intel_perf_query_add_counter_uint64(query, 2446, 88, NULL,acmgt2__front_end1__command_parser_compute_engine_dispatch_kernel_count__read);

      intel_perf_query_add_counter_uint64(query, 1480, 96, NULL,acmgt2__front_end1__command_parser_render_engine_dispatch_kernel_count__read);

      intel_perf_query_add_counter_uint64(query, 1482, 104, NULL,acmgt2__front_end1__command_parser_flush_count__read);

      intel_perf_query_add_counter_uint64(query, 1481, 112, NULL,acmgt2__front_end1__command_parser_render_engine_draw_count__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_geometry1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Geometry1";
   query->symbol_name = "Geometry1";
   query->guid = "f655036b-8302-4327-880e-014cffa29448";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C073C00 },
         { .reg = 0x00009888, .val = 0x14090440 },
         { .reg = 0x00009888, .val = 0x16090013 },
         { .reg = 0x00009888, .val = 0x1D073C00 },
         { .reg = 0x00009888, .val = 0x15090440 },
         { .reg = 0x00009888, .val = 0x17090013 },
         { .reg = 0x00009888, .val = 0x00034038 },
         { .reg = 0x00009888, .val = 0x06070000 },
         { .reg = 0x00009888, .val = 0x16070034 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009888, .val = 0x02090010 },
         { .reg = 0x00009888, .val = 0x04090A00 },
         { .reg = 0x00009888, .val = 0x0609034A },
         { .reg = 0x00009888, .val = 0x00098000 },
         { .reg = 0x00009888, .val = 0x000A056A },
         { .reg = 0x00009888, .val = 0x020A9000 },
         { .reg = 0x00009888, .val = 0x00014038 },
         { .reg = 0x00009888, .val = 0x000B0A80 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x07070000 },
         { .reg = 0x00009888, .val = 0x15070D00 },
         { .reg = 0x00009888, .val = 0x05070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x03090010 },
         { .reg = 0x00009888, .val = 0x09090285 },
         { .reg = 0x00009888, .val = 0x0B09000D },
         { .reg = 0x00009888, .val = 0x01094000 },
         { .reg = 0x00009888, .val = 0x010A0A80 },
         { .reg = 0x00009888, .val = 0x030A2000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1C073C00 },
         { .reg = 0x00009888, .val = 0x14090440 },
         { .reg = 0x00009888, .val = 0x16090013 },
         { .reg = 0x00009888, .val = 0x1D073C00 },
         { .reg = 0x00009888, .val = 0x15090440 },
         { .reg = 0x00009888, .val = 0x17090013 },
         { .reg = 0x00009888, .val = 0x00031E00 },
         { .reg = 0x00009888, .val = 0x06070000 },
         { .reg = 0x00009888, .val = 0x14070034 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x020803FC },
         { .reg = 0x00009888, .val = 0x02090010 },
         { .reg = 0x00009888, .val = 0x0A090140 },
         { .reg = 0x00009888, .val = 0x0C09034A },
         { .reg = 0x00009888, .val = 0x00092000 },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020A0956 },
         { .reg = 0x00009888, .val = 0x00011E00 },
         { .reg = 0x00009888, .val = 0x020B02A8 },
         { .reg = 0x00009888, .val = 0x07070000 },
         { .reg = 0x00009888, .val = 0x13070D00 },
         { .reg = 0x00009888, .val = 0x05070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x03090010 },
         { .reg = 0x00009888, .val = 0x0F090285 },
         { .reg = 0x00009888, .val = 0x1109000D },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A02A8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x02020FFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x0203124A },
         { .reg = 0x00009888, .val = 0x04032249 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32031082 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x36030849 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030A05 },
         { .reg = 0x00009888, .val = 0x3A030E50 },
         { .reg = 0x00009888, .val = 0x3C0302E1 },
         { .reg = 0x00009888, .val = 0x3E030017 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030500 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001C03F },
         { .reg = 0x00009888, .val = 0x00020555 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00050555 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00013FC0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02020555 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040555 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02050555 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x02080AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x0000000A },
         { .reg = 0x0000D94C, .val = 0x0000FFFA },
         { .reg = 0x0000D950, .val = 0x000000C2 },
         { .reg = 0x0000D954, .val = 0x0000FFE7 },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000FFD7 },
         { .reg = 0x0000D960, .val = 0x00000602 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FEBF },
         { .reg = 0x0000D970, .val = 0x00003002 },
         { .reg = 0x0000D974, .val = 0x0000F9FF },
         { .reg = 0x0000D978, .val = 0x00001002 },
         { .reg = 0x0000D97C, .val = 0x0000F5FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1395, 0, NULL,acmgt2__geometry1__clipper_input_vertex_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1396, 8, NULL,acmgt2__geometry1__clipper_input_vertex_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2447, 16, NULL,acmgt2__geometry1__clipper_input_vertex_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2448, 24, NULL,acmgt2__geometry1__clipper_input_vertex_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1397, 32, NULL,acmgt2__geometry1__streamout_output_vertex_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1398, 40, NULL,acmgt2__geometry1__streamout_output_vertex_count_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2449, 48, NULL,acmgt2__geometry1__streamout_output_vertex_count_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2450, 56, NULL,acmgt2__geometry1__streamout_output_vertex_count_slice3__read);
      }

      intel_perf_query_add_counter_uint64(query, 1, 64, NULL,acmgt2__geometry1__gpu_core_clocks__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_geometry2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "Geometry2";
   query->symbol_name = "Geometry2";
   query->guid = "80abe21d-174e-4d5f-a64f-34eea53e8c59";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18091800 },
         { .reg = 0x00009888, .val = 0x16090340 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x180A001F },
         { .reg = 0x00009888, .val = 0x19091800 },
         { .reg = 0x00009888, .val = 0x17090340 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x190A001F },
         { .reg = 0x00009888, .val = 0x00034422 },
         { .reg = 0x00009888, .val = 0x00080C0C },
         { .reg = 0x00009888, .val = 0x02083030 },
         { .reg = 0x00009888, .val = 0x02090043 },
         { .reg = 0x00009888, .val = 0x08090480 },
         { .reg = 0x00009888, .val = 0x10090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x060A0027 },
         { .reg = 0x00009888, .val = 0x140A0D80 },
         { .reg = 0x00009888, .val = 0x000A0604 },
         { .reg = 0x00009888, .val = 0x020A1090 },
         { .reg = 0x00009888, .val = 0x00014422 },
         { .reg = 0x00009888, .val = 0x000B0808 },
         { .reg = 0x00009888, .val = 0x020B2020 },
         { .reg = 0x00009888, .val = 0x03090043 },
         { .reg = 0x00009888, .val = 0x0B090012 },
         { .reg = 0x00009888, .val = 0x0F090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x070A09C0 },
         { .reg = 0x00009888, .val = 0x150A0036 },
         { .reg = 0x00009888, .val = 0x010A0800 },
         { .reg = 0x00009888, .val = 0x030A0020 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18091800 },
         { .reg = 0x00009888, .val = 0x16090340 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x180A001F },
         { .reg = 0x00009888, .val = 0x19091800 },
         { .reg = 0x00009888, .val = 0x17090340 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x190A001F },
         { .reg = 0x00009888, .val = 0x00031188 },
         { .reg = 0x00009888, .val = 0x0008C0C0 },
         { .reg = 0x00009888, .val = 0x02080303 },
         { .reg = 0x00009888, .val = 0x02090043 },
         { .reg = 0x00009888, .val = 0x0A090480 },
         { .reg = 0x00009888, .val = 0x0E090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x080A0027 },
         { .reg = 0x00009888, .val = 0x120A0D80 },
         { .reg = 0x00009888, .val = 0x000A6040 },
         { .reg = 0x00009888, .val = 0x020A0109 },
         { .reg = 0x00009888, .val = 0x00011188 },
         { .reg = 0x00009888, .val = 0x000B8080 },
         { .reg = 0x00009888, .val = 0x020B0202 },
         { .reg = 0x00009888, .val = 0x03090043 },
         { .reg = 0x00009888, .val = 0x0D090012 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x090A09C0 },
         { .reg = 0x00009888, .val = 0x130A0036 },
         { .reg = 0x00009888, .val = 0x010A8000 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080A0A },
         { .reg = 0x00009888, .val = 0x0208A0A0 },
         { .reg = 0x00009888, .val = 0x0002F0F0 },
         { .reg = 0x00009888, .val = 0x02020F0F },
         { .reg = 0x00009888, .val = 0x00032252 },
         { .reg = 0x00009888, .val = 0x0203124A },
         { .reg = 0x00009888, .val = 0x04032252 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32032422 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x360304A2 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031264 },
         { .reg = 0x00009888, .val = 0x3A030610 },
         { .reg = 0x00009888, .val = 0x3C030008 },
         { .reg = 0x00009888, .val = 0x3E030600 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031424 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001CC33 },
         { .reg = 0x00009888, .val = 0x00020505 },
         { .reg = 0x00009888, .val = 0x02025050 },
         { .reg = 0x00009888, .val = 0x00040505 },
         { .reg = 0x00009888, .val = 0x02045050 },
         { .reg = 0x00009888, .val = 0x00050505 },
         { .reg = 0x00009888, .val = 0x02055050 },
         { .reg = 0x00009888, .val = 0x00080A0A },
         { .reg = 0x00009888, .val = 0x0208A0A0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000133CC },
         { .reg = 0x00009888, .val = 0x00025050 },
         { .reg = 0x00009888, .val = 0x02020505 },
         { .reg = 0x00009888, .val = 0x00045050 },
         { .reg = 0x00009888, .val = 0x02040505 },
         { .reg = 0x00009888, .val = 0x00055050 },
         { .reg = 0x00009888, .val = 0x02050505 },
         { .reg = 0x00009888, .val = 0x0008A0A0 },
         { .reg = 0x00009888, .val = 0x02080A0A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 1, 0, NULL,acmgt2__geometry2__gpu_core_clocks__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1391, 8, percentage_max_float,acmgt2__geometry2__vertex_fetch_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1392, 12, percentage_max_float,acmgt2__geometry2__vertex_fetch_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2451, 16, percentage_max_float,acmgt2__geometry2__vertex_fetch_input_available_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2452, 20, percentage_max_float,acmgt2__geometry2__vertex_fetch_input_available_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1393, 24, percentage_max_float,acmgt2__geometry2__vertex_fetch_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1394, 28, percentage_max_float,acmgt2__geometry2__vertex_fetch_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2453, 32, percentage_max_float,acmgt2__geometry2__vertex_fetch_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2454, 36, percentage_max_float,acmgt2__geometry2__vertex_fetch_output_ready_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1401, 40, percentage_max_float,acmgt2__geometry2__clipper_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1402, 44, percentage_max_float,acmgt2__geometry2__clipper_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2455, 48, percentage_max_float,acmgt2__geometry2__clipper_input_available_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2456, 52, percentage_max_float,acmgt2__geometry2__clipper_input_available_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1403, 56, percentage_max_float,acmgt2__geometry2__clipper_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1404, 60, percentage_max_float,acmgt2__geometry2__clipper_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2457, 64, percentage_max_float,acmgt2__geometry2__clipper_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2458, 68, percentage_max_float,acmgt2__geometry2__clipper_output_ready_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_geometry3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Geometry3";
   query->symbol_name = "Geometry3";
   query->guid = "f736c728-c16c-4125-97c3-b7e2f7d25ecc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x18090000 },
         { .reg = 0x00009888, .val = 0x1E09000A },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x19090000 },
         { .reg = 0x00009888, .val = 0x1F09000A },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x14030031 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00034302 },
         { .reg = 0x00009888, .val = 0x0008000C },
         { .reg = 0x00009888, .val = 0x0208F00F },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x04096800 },
         { .reg = 0x00009888, .val = 0x0E090480 },
         { .reg = 0x00009888, .val = 0x10090013 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0006 },
         { .reg = 0x00009888, .val = 0x020A50A5 },
         { .reg = 0x00009888, .val = 0x0001C302 },
         { .reg = 0x00009888, .val = 0x000B0008 },
         { .reg = 0x00009888, .val = 0x020BA00A },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x13030C40 },
         { .reg = 0x00009888, .val = 0x03030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x03083000 },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x05090000 },
         { .reg = 0x00009888, .val = 0x07090034 },
         { .reg = 0x00009888, .val = 0x0D090480 },
         { .reg = 0x00009888, .val = 0x0F090013 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0008 },
         { .reg = 0x00009888, .val = 0x030A100A },
         { .reg = 0x00009888, .val = 0x01014000 },
         { .reg = 0x00009888, .val = 0x030B2000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x18090000 },
         { .reg = 0x00009888, .val = 0x1E09000A },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x19090000 },
         { .reg = 0x00009888, .val = 0x1F09000A },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x12030031 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00031038 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x04090000 },
         { .reg = 0x00009888, .val = 0x06090D00 },
         { .reg = 0x00009888, .val = 0x0A090480 },
         { .reg = 0x00009888, .val = 0x0C090013 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000AA560 },
         { .reg = 0x00009888, .val = 0x020A0500 },
         { .reg = 0x00009888, .val = 0x00013038 },
         { .reg = 0x00009888, .val = 0x000B0A80 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x11030C40 },
         { .reg = 0x00009888, .val = 0x03030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x03080300 },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x05090000 },
         { .reg = 0x00009888, .val = 0x090904B4 },
         { .reg = 0x00009888, .val = 0x0B090013 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0A80 },
         { .reg = 0x00009888, .val = 0x030A0100 },
         { .reg = 0x00009888, .val = 0x01011000 },
         { .reg = 0x00009888, .val = 0x030B0200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x00031252 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032252 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x1203F000 },
         { .reg = 0x00009888, .val = 0x32030C63 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x360308C9 },
         { .reg = 0x00009888, .val = 0x2603F000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030A25 },
         { .reg = 0x00009888, .val = 0x3A031E51 },
         { .reg = 0x00009888, .val = 0x3C0305E2 },
         { .reg = 0x00009888, .val = 0x3E030261 },
         { .reg = 0x00009888, .val = 0x40030006 },
         { .reg = 0x00009888, .val = 0x1403F000 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030500 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001CF03 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x02025055 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x02055055 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009888, .val = 0x0208A0AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000130FC },
         { .reg = 0x00009888, .val = 0x00025550 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x00055550 },
         { .reg = 0x00009888, .val = 0x02050500 },
         { .reg = 0x00009888, .val = 0x0008AAA0 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 1, 0, NULL,acmgt2__geometry3__gpu_core_clocks__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1413, 8, percentage_max_float,acmgt2__geometry3__stripsfan_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1414, 12, percentage_max_float,acmgt2__geometry3__stripsfan_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2459, 16, percentage_max_float,acmgt2__geometry3__stripsfan_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2460, 20, percentage_max_float,acmgt2__geometry3__stripsfan_output_ready_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1399, 24, percentage_max_float,acmgt2__geometry3__vs_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1400, 28, percentage_max_float,acmgt2__geometry3__vs_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2461, 32, percentage_max_float,acmgt2__geometry3__vs_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2462, 36, percentage_max_float,acmgt2__geometry3__vs_output_ready_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1423, 40, NULL,acmgt2__geometry3__clipper_primitive_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1424, 48, NULL,acmgt2__geometry3__clipper_primitive_cull_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2463, 56, NULL,acmgt2__geometry3__clipper_primitive_cull_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2464, 64, NULL,acmgt2__geometry3__clipper_primitive_cull_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_geometry4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Geometry4";
   query->symbol_name = "Geometry4";
   query->guid = "81996036-5d85-4ca6-83f8-a5bce6428d80";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160929C0 },
         { .reg = 0x00009888, .val = 0x1C0903E0 },
         { .reg = 0x00009888, .val = 0x170929C0 },
         { .reg = 0x00009888, .val = 0x1D0903E0 },
         { .reg = 0x00009888, .val = 0x00034038 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009888, .val = 0x02094023 },
         { .reg = 0x00009888, .val = 0x04090C00 },
         { .reg = 0x00009888, .val = 0x060902CC },
         { .reg = 0x00009888, .val = 0x14090025 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A056A },
         { .reg = 0x00009888, .val = 0x020A9000 },
         { .reg = 0x00009888, .val = 0x00014038 },
         { .reg = 0x00009888, .val = 0x000B0A80 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x03094023 },
         { .reg = 0x00009888, .val = 0x09090306 },
         { .reg = 0x00009888, .val = 0x0B09000B },
         { .reg = 0x00009888, .val = 0x13090940 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0A80 },
         { .reg = 0x00009888, .val = 0x030A2000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160929C0 },
         { .reg = 0x00009888, .val = 0x1C0903E0 },
         { .reg = 0x00009888, .val = 0x170929C0 },
         { .reg = 0x00009888, .val = 0x1D0903E0 },
         { .reg = 0x00009888, .val = 0x00031E00 },
         { .reg = 0x00009888, .val = 0x020803FC },
         { .reg = 0x00009888, .val = 0x02094023 },
         { .reg = 0x00009888, .val = 0x0A090180 },
         { .reg = 0x00009888, .val = 0x0C0902CC },
         { .reg = 0x00009888, .val = 0x12090025 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020A0956 },
         { .reg = 0x00009888, .val = 0x00011E00 },
         { .reg = 0x00009888, .val = 0x020B02A8 },
         { .reg = 0x00009888, .val = 0x03094023 },
         { .reg = 0x00009888, .val = 0x0F090306 },
         { .reg = 0x00009888, .val = 0x1109094B },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x030A02A8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x02020FFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x0203124A },
         { .reg = 0x00009888, .val = 0x04032249 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030009 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032529 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030610 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030083 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030500 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001C03F },
         { .reg = 0x00009888, .val = 0x00020555 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00050555 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00013FC0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02020555 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040555 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02050555 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x02080AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x0000002A },
         { .reg = 0x0000D94C, .val = 0x0000FFFA },
         { .reg = 0x0000D950, .val = 0x000000C2 },
         { .reg = 0x0000D954, .val = 0x0000FFE7 },
         { .reg = 0x0000D958, .val = 0x00000142 },
         { .reg = 0x0000D95C, .val = 0x0000FFD7 },
         { .reg = 0x0000D960, .val = 0x00000602 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00000A02 },
         { .reg = 0x0000D96C, .val = 0x0000FEBF },
         { .reg = 0x0000D970, .val = 0x00003002 },
         { .reg = 0x0000D974, .val = 0x0000F9FF },
         { .reg = 0x0000D978, .val = 0x00005002 },
         { .reg = 0x0000D97C, .val = 0x0000F5FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1421, 0, NULL,acmgt2__geometry4__clipper_primitive_far_near_clip_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1422, 8, NULL,acmgt2__geometry4__clipper_primitive_far_near_clip_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2465, 16, NULL,acmgt2__geometry4__clipper_primitive_far_near_clip_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2466, 24, NULL,acmgt2__geometry4__clipper_primitive_far_near_clip_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1405, 32, NULL,acmgt2__geometry4__clipper_primitive_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1406, 40, NULL,acmgt2__geometry4__clipper_primitive_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2467, 48, NULL,acmgt2__geometry4__clipper_primitive_output_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2468, 56, NULL,acmgt2__geometry4__clipper_primitive_output_slice3__read);
      }

      intel_perf_query_add_counter_uint64(query, 1, 64, NULL,acmgt2__geometry4__gpu_core_clocks__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_geometry5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Geometry5";
   query->symbol_name = "Geometry5";
   query->guid = "09075af6-ccdd-49bf-8581-92a84840bbb5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12057C00 },
         { .reg = 0x00009888, .val = 0x1409002A },
         { .reg = 0x00009888, .val = 0x1C097FC0 },
         { .reg = 0x00009888, .val = 0x13057C00 },
         { .reg = 0x00009888, .val = 0x15090000 },
         { .reg = 0x00009888, .val = 0x1D097FC0 },
         { .reg = 0x00009888, .val = 0x00033044 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x08050080 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00060080 },
         { .reg = 0x00009888, .val = 0x00087030 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x04090005 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x12090940 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A5090 },
         { .reg = 0x00009888, .val = 0x020AA500 },
         { .reg = 0x00009888, .val = 0x00013044 },
         { .reg = 0x00009888, .val = 0x000B2020 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x09050002 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01060040 },
         { .reg = 0x00009888, .val = 0x01081000 },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x05090005 },
         { .reg = 0x00009888, .val = 0x07090000 },
         { .reg = 0x00009888, .val = 0x11090940 },
         { .reg = 0x00009888, .val = 0x1309002A },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A1020 },
         { .reg = 0x00009888, .val = 0x030A0A00 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12057C00 },
         { .reg = 0x00009888, .val = 0x14090000 },
         { .reg = 0x00009888, .val = 0x1C097FC0 },
         { .reg = 0x00009888, .val = 0x13057C00 },
         { .reg = 0x00009888, .val = 0x15090000 },
         { .reg = 0x00009888, .val = 0x1D097FC0 },
         { .reg = 0x00009888, .val = 0x00030311 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x06050080 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00060020 },
         { .reg = 0x00009888, .val = 0x00080703 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x04090005 },
         { .reg = 0x00009888, .val = 0x06090000 },
         { .reg = 0x00009888, .val = 0x0E090940 },
         { .reg = 0x00009888, .val = 0x1009002A },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0509 },
         { .reg = 0x00009888, .val = 0x020A00A5 },
         { .reg = 0x00009888, .val = 0x00010311 },
         { .reg = 0x00009888, .val = 0x000B0202 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x07050002 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01060010 },
         { .reg = 0x00009888, .val = 0x01080100 },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x05090005 },
         { .reg = 0x00009888, .val = 0x0D090940 },
         { .reg = 0x00009888, .val = 0x0F09002A },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0102 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A0A0 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00020F0F },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00031489 },
         { .reg = 0x00009888, .val = 0x02031291 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x320314A8 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x360324A6 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030006 },
         { .reg = 0x00009888, .val = 0x3A030083 },
         { .reg = 0x00009888, .val = 0x3C031261 },
         { .reg = 0x00009888, .val = 0x3E030080 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031929 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0CC },
         { .reg = 0x00009888, .val = 0x00025050 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045050 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055050 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008A0A0 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010F33 },
         { .reg = 0x00009888, .val = 0x00020505 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00040505 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00050505 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x00080A0A },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1411, 0, NULL,acmgt2__geometry5__stripsfan_objects_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1412, 8, NULL,acmgt2__geometry5__stripsfan_objects_cull_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2469, 16, NULL,acmgt2__geometry5__stripsfan_objects_cull_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2470, 24, NULL,acmgt2__geometry5__stripsfan_objects_cull_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1409, 32, NULL,acmgt2__geometry5__stripsfan_object_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1410, 40, NULL,acmgt2__geometry5__stripsfan_object_count_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2471, 48, NULL,acmgt2__geometry5__stripsfan_object_count_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2472, 56, NULL,acmgt2__geometry5__stripsfan_object_count_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1407, 64, NULL,acmgt2__geometry5__clipper_transaction_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1408, 72, NULL,acmgt2__geometry5__clipper_transaction_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2473, 80, NULL,acmgt2__geometry5__clipper_transaction_output_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2474, 88, NULL,acmgt2__geometry5__clipper_transaction_output_slice3__read);
      }

      intel_perf_query_add_counter_uint64(query, 1, 96, NULL,acmgt2__geometry5__gpu_core_clocks__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache1";
   query->symbol_name = "L1Cache1";
   query->guid = "09aaf18b-f85d-443d-9644-9cc847782212";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890002 },
         { .reg = 0x00009888, .val = 0x1E890800 },
         { .reg = 0x00009888, .val = 0x24890040 },
         { .reg = 0x00009888, .val = 0x2A890002 },
         { .reg = 0x00009888, .val = 0x1AA90002 },
         { .reg = 0x00009888, .val = 0x1EA90800 },
         { .reg = 0x00009888, .val = 0x24A90040 },
         { .reg = 0x00009888, .val = 0x2AA90002 },
         { .reg = 0x00009888, .val = 0x1AC90002 },
         { .reg = 0x00009888, .val = 0x1EC90800 },
         { .reg = 0x00009888, .val = 0x24C90040 },
         { .reg = 0x00009888, .val = 0x2AC90002 },
         { .reg = 0x00009888, .val = 0x1AE90002 },
         { .reg = 0x00009888, .val = 0x1EE90800 },
         { .reg = 0x00009888, .val = 0x24E90040 },
         { .reg = 0x00009888, .val = 0x2AE90002 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890975 },
         { .reg = 0x00009888, .val = 0x14890155 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90975 },
         { .reg = 0x00009888, .val = 0x10A90155 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90975 },
         { .reg = 0x00009888, .val = 0x0CC90155 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90975 },
         { .reg = 0x00009888, .val = 0x08E90155 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache1__avg_gpu_core_frequency__max,acmgt2__l1_cache1__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 979, 24, percentage_max_float,acmgt2__l1_cache1__load_store_cache_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 980, 28, percentage_max_float,acmgt2__l1_cache1__load_store_cache_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 981, 32, percentage_max_float,acmgt2__l1_cache1__load_store_cache_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 982, 36, percentage_max_float,acmgt2__l1_cache1__load_store_cache_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache2";
   query->symbol_name = "L1Cache2";
   query->guid = "66096c29-519c-4063-9d03-e04e50d8d478";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890002 },
         { .reg = 0x00009888, .val = 0x1F890800 },
         { .reg = 0x00009888, .val = 0x25890040 },
         { .reg = 0x00009888, .val = 0x2B890002 },
         { .reg = 0x00009888, .val = 0x1BA90002 },
         { .reg = 0x00009888, .val = 0x1FA90800 },
         { .reg = 0x00009888, .val = 0x25A90040 },
         { .reg = 0x00009888, .val = 0x2BA90002 },
         { .reg = 0x00009888, .val = 0x1BC90002 },
         { .reg = 0x00009888, .val = 0x1FC90800 },
         { .reg = 0x00009888, .val = 0x25C90040 },
         { .reg = 0x00009888, .val = 0x2BC90002 },
         { .reg = 0x00009888, .val = 0x1BE90002 },
         { .reg = 0x00009888, .val = 0x1FE90800 },
         { .reg = 0x00009888, .val = 0x25E90040 },
         { .reg = 0x00009888, .val = 0x2BE90002 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890975 },
         { .reg = 0x00009888, .val = 0x15890155 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90975 },
         { .reg = 0x00009888, .val = 0x11A90155 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90975 },
         { .reg = 0x00009888, .val = 0x0DC90155 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90975 },
         { .reg = 0x00009888, .val = 0x09E90155 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache2__avg_gpu_core_frequency__max,acmgt2__l1_cache2__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 983, 24, percentage_max_float,acmgt2__l1_cache2__load_store_cache_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 984, 28, percentage_max_float,acmgt2__l1_cache2__load_store_cache_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 985, 32, percentage_max_float,acmgt2__l1_cache2__load_store_cache_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 986, 36, percentage_max_float,acmgt2__l1_cache2__load_store_cache_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache3";
   query->symbol_name = "L1Cache3";
   query->guid = "2237bc33-3e20-446a-8d7d-7ac651314287";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890002 },
         { .reg = 0x00009888, .val = 0x1E890800 },
         { .reg = 0x00009888, .val = 0x24890040 },
         { .reg = 0x00009888, .val = 0x2A890002 },
         { .reg = 0x00009888, .val = 0x1AA90002 },
         { .reg = 0x00009888, .val = 0x1EA90800 },
         { .reg = 0x00009888, .val = 0x24A90040 },
         { .reg = 0x00009888, .val = 0x2AA90002 },
         { .reg = 0x00009888, .val = 0x1AC90002 },
         { .reg = 0x00009888, .val = 0x1EC90800 },
         { .reg = 0x00009888, .val = 0x24C90040 },
         { .reg = 0x00009888, .val = 0x2AC90002 },
         { .reg = 0x00009888, .val = 0x1AE90002 },
         { .reg = 0x00009888, .val = 0x1EE90800 },
         { .reg = 0x00009888, .val = 0x24E90040 },
         { .reg = 0x00009888, .val = 0x2AE90002 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890975 },
         { .reg = 0x00009888, .val = 0x14890155 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90975 },
         { .reg = 0x00009888, .val = 0x10A90155 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90975 },
         { .reg = 0x00009888, .val = 0x0CC90155 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90975 },
         { .reg = 0x00009888, .val = 0x08E90155 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache3__avg_gpu_core_frequency__max,acmgt2__l1_cache3__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2475, 24, percentage_max_float,acmgt2__l1_cache3__load_store_cache_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2476, 28, percentage_max_float,acmgt2__l1_cache3__load_store_cache_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2477, 32, percentage_max_float,acmgt2__l1_cache3__load_store_cache_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2478, 36, percentage_max_float,acmgt2__l1_cache3__load_store_cache_input_available_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache4";
   query->symbol_name = "L1Cache4";
   query->guid = "c4e31e05-c514-4e2e-9686-f4225de24213";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890002 },
         { .reg = 0x00009888, .val = 0x1F890800 },
         { .reg = 0x00009888, .val = 0x25890040 },
         { .reg = 0x00009888, .val = 0x2B890002 },
         { .reg = 0x00009888, .val = 0x1BA90002 },
         { .reg = 0x00009888, .val = 0x1FA90800 },
         { .reg = 0x00009888, .val = 0x25A90040 },
         { .reg = 0x00009888, .val = 0x2BA90002 },
         { .reg = 0x00009888, .val = 0x1BC90002 },
         { .reg = 0x00009888, .val = 0x1FC90800 },
         { .reg = 0x00009888, .val = 0x25C90040 },
         { .reg = 0x00009888, .val = 0x2BC90002 },
         { .reg = 0x00009888, .val = 0x1BE90002 },
         { .reg = 0x00009888, .val = 0x1FE90800 },
         { .reg = 0x00009888, .val = 0x25E90040 },
         { .reg = 0x00009888, .val = 0x2BE90002 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890975 },
         { .reg = 0x00009888, .val = 0x15890155 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90975 },
         { .reg = 0x00009888, .val = 0x11A90155 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90975 },
         { .reg = 0x00009888, .val = 0x0DC90155 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90975 },
         { .reg = 0x00009888, .val = 0x09E90155 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache4__avg_gpu_core_frequency__max,acmgt2__l1_cache4__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2479, 24, percentage_max_float,acmgt2__l1_cache4__load_store_cache_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2480, 28, percentage_max_float,acmgt2__l1_cache4__load_store_cache_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2481, 32, percentage_max_float,acmgt2__l1_cache4__load_store_cache_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2482, 36, percentage_max_float,acmgt2__l1_cache4__load_store_cache_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache5";
   query->symbol_name = "L1Cache5";
   query->guid = "1c608270-6be1-4381-bd2a-e7e5e6ec0c84";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890934 },
         { .reg = 0x00009888, .val = 0x14890114 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90934 },
         { .reg = 0x00009888, .val = 0x10A90114 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90934 },
         { .reg = 0x00009888, .val = 0x0CC90114 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90934 },
         { .reg = 0x00009888, .val = 0x08E90114 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache5__avg_gpu_core_frequency__max,acmgt2__l1_cache5__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 987, 24, percentage_max_float,acmgt2__l1_cache5__load_store_cache_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 988, 28, percentage_max_float,acmgt2__l1_cache5__load_store_cache_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 989, 32, percentage_max_float,acmgt2__l1_cache5__load_store_cache_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 990, 36, percentage_max_float,acmgt2__l1_cache5__load_store_cache_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache6";
   query->symbol_name = "L1Cache6";
   query->guid = "8ea12c1c-6dfc-4539-b7cc-4c0ed0a0e172";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890934 },
         { .reg = 0x00009888, .val = 0x15890114 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90934 },
         { .reg = 0x00009888, .val = 0x11A90114 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90934 },
         { .reg = 0x00009888, .val = 0x0DC90114 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90934 },
         { .reg = 0x00009888, .val = 0x09E90114 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache6__avg_gpu_core_frequency__max,acmgt2__l1_cache6__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 991, 24, percentage_max_float,acmgt2__l1_cache6__load_store_cache_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 992, 28, percentage_max_float,acmgt2__l1_cache6__load_store_cache_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 993, 32, percentage_max_float,acmgt2__l1_cache6__load_store_cache_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 994, 36, percentage_max_float,acmgt2__l1_cache6__load_store_cache_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache7";
   query->symbol_name = "L1Cache7";
   query->guid = "563cb980-9a7e-469f-8fa7-75fbbda1b6a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890934 },
         { .reg = 0x00009888, .val = 0x14890114 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90934 },
         { .reg = 0x00009888, .val = 0x10A90114 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90934 },
         { .reg = 0x00009888, .val = 0x0CC90114 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90934 },
         { .reg = 0x00009888, .val = 0x08E90114 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache7__avg_gpu_core_frequency__max,acmgt2__l1_cache7__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2483, 24, percentage_max_float,acmgt2__l1_cache7__load_store_cache_output_ready_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2484, 28, percentage_max_float,acmgt2__l1_cache7__load_store_cache_output_ready_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2485, 32, percentage_max_float,acmgt2__l1_cache7__load_store_cache_output_ready_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2486, 36, percentage_max_float,acmgt2__l1_cache7__load_store_cache_output_ready_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache8";
   query->symbol_name = "L1Cache8";
   query->guid = "203752ae-e3b3-4895-85cd-9cef09669196";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890934 },
         { .reg = 0x00009888, .val = 0x15890114 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90934 },
         { .reg = 0x00009888, .val = 0x11A90114 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90934 },
         { .reg = 0x00009888, .val = 0x0DC90114 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90934 },
         { .reg = 0x00009888, .val = 0x09E90114 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache8__avg_gpu_core_frequency__max,acmgt2__l1_cache8__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2487, 24, percentage_max_float,acmgt2__l1_cache8__load_store_cache_output_ready_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2488, 28, percentage_max_float,acmgt2__l1_cache8__load_store_cache_output_ready_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2489, 32, percentage_max_float,acmgt2__l1_cache8__load_store_cache_output_ready_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2490, 36, percentage_max_float,acmgt2__l1_cache8__load_store_cache_output_ready_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1Cache9";
   query->symbol_name = "L1Cache9";
   query->guid = "94ae89ad-096f-42c3-a666-b3bb904605e9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890083 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90083 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90083 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90083 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890083 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90083 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90083 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203210A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030230 },
         { .reg = 0x00009888, .val = 0x3C030422 },
         { .reg = 0x00009888, .val = 0x3E030E77 },
         { .reg = 0x00009888, .val = 0x40030007 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache9__avg_gpu_core_frequency__max,acmgt2__l1_cache9__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1011, 24, NULL,acmgt2__l1_cache9__load_store_cache_l3_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1012, 32, NULL,acmgt2__l1_cache9__load_store_cache_l3_read_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1013, 40, NULL,acmgt2__l1_cache9__load_store_cache_l3_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1014, 48, NULL,acmgt2__l1_cache9__load_store_cache_l3_read_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1015, 56, NULL,acmgt2__l1_cache9__load_store_cache_l3_read_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1016, 64, NULL,acmgt2__l1_cache9__load_store_cache_l3_read_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1017, 72, NULL,acmgt2__l1_cache9__load_store_cache_l3_read_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1018, 80, NULL,acmgt2__l1_cache9__load_store_cache_l3_read_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1Cache10";
   query->symbol_name = "L1Cache10";
   query->guid = "97f2d572-60c2-422d-b9eb-f0edb2f9e788";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890083 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90083 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90083 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90083 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890083 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90083 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90083 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203210A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030230 },
         { .reg = 0x00009888, .val = 0x3C030422 },
         { .reg = 0x00009888, .val = 0x3E030E77 },
         { .reg = 0x00009888, .val = 0x40030007 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache10__avg_gpu_core_frequency__max,acmgt2__l1_cache10__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2491, 24, NULL,acmgt2__l1_cache10__load_store_cache_l3_read_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2492, 32, NULL,acmgt2__l1_cache10__load_store_cache_l3_read_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2493, 40, NULL,acmgt2__l1_cache10__load_store_cache_l3_read_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2494, 48, NULL,acmgt2__l1_cache10__load_store_cache_l3_read_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2495, 56, NULL,acmgt2__l1_cache10__load_store_cache_l3_read_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2496, 64, NULL,acmgt2__l1_cache10__load_store_cache_l3_read_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2497, 72, NULL,acmgt2__l1_cache10__load_store_cache_l3_read_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2498, 80, NULL,acmgt2__l1_cache10__load_store_cache_l3_read_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1Cache11";
   query->symbol_name = "L1Cache11";
   query->guid = "df474009-ed7f-4a1b-84a5-473b35804e42";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890105 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90105 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90105 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90105 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890105 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90105 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90105 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90105 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203210A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030230 },
         { .reg = 0x00009888, .val = 0x3C030422 },
         { .reg = 0x00009888, .val = 0x3E030E77 },
         { .reg = 0x00009888, .val = 0x40030007 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache11__avg_gpu_core_frequency__max,acmgt2__l1_cache11__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1019, 24, NULL,acmgt2__l1_cache11__load_store_cache_l3_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1020, 32, NULL,acmgt2__l1_cache11__load_store_cache_l3_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1021, 40, NULL,acmgt2__l1_cache11__load_store_cache_l3_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1022, 48, NULL,acmgt2__l1_cache11__load_store_cache_l3_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1023, 56, NULL,acmgt2__l1_cache11__load_store_cache_l3_write_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1024, 64, NULL,acmgt2__l1_cache11__load_store_cache_l3_write_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1025, 72, NULL,acmgt2__l1_cache11__load_store_cache_l3_write_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1026, 80, NULL,acmgt2__l1_cache11__load_store_cache_l3_write_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1Cache12";
   query->symbol_name = "L1Cache12";
   query->guid = "7c3b945e-3b30-4ef2-8544-34b535ca90b8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890105 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90105 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90105 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90105 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890105 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90105 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90105 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90105 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203210A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030230 },
         { .reg = 0x00009888, .val = 0x3C030422 },
         { .reg = 0x00009888, .val = 0x3E030E77 },
         { .reg = 0x00009888, .val = 0x40030007 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache12__avg_gpu_core_frequency__max,acmgt2__l1_cache12__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2499, 24, NULL,acmgt2__l1_cache12__load_store_cache_l3_write_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2500, 32, NULL,acmgt2__l1_cache12__load_store_cache_l3_write_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2501, 40, NULL,acmgt2__l1_cache12__load_store_cache_l3_write_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2502, 48, NULL,acmgt2__l1_cache12__load_store_cache_l3_write_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2503, 56, NULL,acmgt2__l1_cache12__load_store_cache_l3_write_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2504, 64, NULL,acmgt2__l1_cache12__load_store_cache_l3_write_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2505, 72, NULL,acmgt2__l1_cache12__load_store_cache_l3_write_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2506, 80, NULL,acmgt2__l1_cache12__load_store_cache_l3_write_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache13";
   query->symbol_name = "L1Cache13";
   query->guid = "a55bc2da-2c6f-4774-a20e-bd79371902db";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache13__avg_gpu_core_frequency__max,acmgt2__l1_cache13__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 995, 24, NULL,acmgt2__l1_cache13__load_store_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 996, 32, NULL,acmgt2__l1_cache13__load_store_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 997, 40, NULL,acmgt2__l1_cache13__load_store_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 998, 48, NULL,acmgt2__l1_cache13__load_store_cache_access_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache14";
   query->symbol_name = "L1Cache14";
   query->guid = "0e4e660e-96bf-4b86-90cb-64ec0532fd03";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache14__avg_gpu_core_frequency__max,acmgt2__l1_cache14__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 999, 24, NULL,acmgt2__l1_cache14__load_store_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1000, 32, NULL,acmgt2__l1_cache14__load_store_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1001, 40, NULL,acmgt2__l1_cache14__load_store_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1002, 48, NULL,acmgt2__l1_cache14__load_store_cache_access_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache15";
   query->symbol_name = "L1Cache15";
   query->guid = "8bb39f7a-53b5-403d-94fb-f1f7350d2ce0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache15__avg_gpu_core_frequency__max,acmgt2__l1_cache15__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2507, 24, NULL,acmgt2__l1_cache15__load_store_cache_access_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2508, 32, NULL,acmgt2__l1_cache15__load_store_cache_access_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2509, 40, NULL,acmgt2__l1_cache15__load_store_cache_access_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2510, 48, NULL,acmgt2__l1_cache15__load_store_cache_access_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache16";
   query->symbol_name = "L1Cache16";
   query->guid = "f4b433d4-2af0-45c2-b61c-7e9a4db553cc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache16__avg_gpu_core_frequency__max,acmgt2__l1_cache16__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2511, 24, NULL,acmgt2__l1_cache16__load_store_cache_access_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2512, 32, NULL,acmgt2__l1_cache16__load_store_cache_access_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2513, 40, NULL,acmgt2__l1_cache16__load_store_cache_access_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2514, 48, NULL,acmgt2__l1_cache16__load_store_cache_access_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache17";
   query->symbol_name = "L1Cache17";
   query->guid = "bde419e8-3eb1-4525-9317-f74900301c1d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870005 },
         { .reg = 0x00009888, .val = 0x1A870005 },
         { .reg = 0x00009888, .val = 0x12880005 },
         { .reg = 0x00009888, .val = 0x16880005 },
         { .reg = 0x00009888, .val = 0x16A70005 },
         { .reg = 0x00009888, .val = 0x1AA70005 },
         { .reg = 0x00009888, .val = 0x12A80005 },
         { .reg = 0x00009888, .val = 0x16A80005 },
         { .reg = 0x00009888, .val = 0x16C70005 },
         { .reg = 0x00009888, .val = 0x1AC70005 },
         { .reg = 0x00009888, .val = 0x12C80005 },
         { .reg = 0x00009888, .val = 0x16C80005 },
         { .reg = 0x00009888, .val = 0x16E70005 },
         { .reg = 0x00009888, .val = 0x1AE70005 },
         { .reg = 0x00009888, .val = 0x12E80005 },
         { .reg = 0x00009888, .val = 0x16E80005 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache17__avg_gpu_core_frequency__max,acmgt2__l1_cache17__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1027, 24, NULL,acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1028, 32, NULL,acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1029, 40, NULL,acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1030, 48, NULL,acmgt2__l1_cache17__load_store_cache_partial_write_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache18";
   query->symbol_name = "L1Cache18";
   query->guid = "7a8bccbc-6900-470c-8204-2dc21423e247";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870005 },
         { .reg = 0x00009888, .val = 0x1B870005 },
         { .reg = 0x00009888, .val = 0x13880005 },
         { .reg = 0x00009888, .val = 0x17880005 },
         { .reg = 0x00009888, .val = 0x17A70005 },
         { .reg = 0x00009888, .val = 0x1BA70005 },
         { .reg = 0x00009888, .val = 0x13A80005 },
         { .reg = 0x00009888, .val = 0x17A80005 },
         { .reg = 0x00009888, .val = 0x17C70005 },
         { .reg = 0x00009888, .val = 0x1BC70005 },
         { .reg = 0x00009888, .val = 0x13C80005 },
         { .reg = 0x00009888, .val = 0x17C80005 },
         { .reg = 0x00009888, .val = 0x17E70005 },
         { .reg = 0x00009888, .val = 0x1BE70005 },
         { .reg = 0x00009888, .val = 0x13E80005 },
         { .reg = 0x00009888, .val = 0x17E80005 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache18__avg_gpu_core_frequency__max,acmgt2__l1_cache18__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1031, 24, NULL,acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1032, 32, NULL,acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1033, 40, NULL,acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1034, 48, NULL,acmgt2__l1_cache18__load_store_cache_partial_write_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache19_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache19";
   query->symbol_name = "L1Cache19";
   query->guid = "2d1b823a-ee3a-43b4-b46f-379ab7920aef";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870005 },
         { .reg = 0x00009888, .val = 0x1A870005 },
         { .reg = 0x00009888, .val = 0x12880005 },
         { .reg = 0x00009888, .val = 0x16880005 },
         { .reg = 0x00009888, .val = 0x16A70005 },
         { .reg = 0x00009888, .val = 0x1AA70005 },
         { .reg = 0x00009888, .val = 0x12A80005 },
         { .reg = 0x00009888, .val = 0x16A80005 },
         { .reg = 0x00009888, .val = 0x16C70005 },
         { .reg = 0x00009888, .val = 0x1AC70005 },
         { .reg = 0x00009888, .val = 0x12C80005 },
         { .reg = 0x00009888, .val = 0x16C80005 },
         { .reg = 0x00009888, .val = 0x16E70005 },
         { .reg = 0x00009888, .val = 0x1AE70005 },
         { .reg = 0x00009888, .val = 0x12E80005 },
         { .reg = 0x00009888, .val = 0x16E80005 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache19__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache19__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache19__avg_gpu_core_frequency__max,acmgt2__l1_cache19__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2515, 24, NULL,acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2516, 32, NULL,acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2517, 40, NULL,acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2518, 48, NULL,acmgt2__l1_cache19__load_store_cache_partial_write_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache20_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache20";
   query->symbol_name = "L1Cache20";
   query->guid = "3b20c2df-ccd7-4c6c-a211-5724fa8bda6d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870005 },
         { .reg = 0x00009888, .val = 0x1B870005 },
         { .reg = 0x00009888, .val = 0x13880005 },
         { .reg = 0x00009888, .val = 0x17880005 },
         { .reg = 0x00009888, .val = 0x17A70005 },
         { .reg = 0x00009888, .val = 0x1BA70005 },
         { .reg = 0x00009888, .val = 0x13A80005 },
         { .reg = 0x00009888, .val = 0x17A80005 },
         { .reg = 0x00009888, .val = 0x17C70005 },
         { .reg = 0x00009888, .val = 0x1BC70005 },
         { .reg = 0x00009888, .val = 0x13C80005 },
         { .reg = 0x00009888, .val = 0x17C80005 },
         { .reg = 0x00009888, .val = 0x17E70005 },
         { .reg = 0x00009888, .val = 0x1BE70005 },
         { .reg = 0x00009888, .val = 0x13E80005 },
         { .reg = 0x00009888, .val = 0x17E80005 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache20__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache20__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache20__avg_gpu_core_frequency__max,acmgt2__l1_cache20__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2519, 24, NULL,acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2520, 32, NULL,acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2521, 40, NULL,acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2522, 48, NULL,acmgt2__l1_cache20__load_store_cache_partial_write_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache21";
   query->symbol_name = "L1Cache21";
   query->guid = "186189aa-0aaf-4c63-9977-d5dfd5eb5084";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x06870143 },
         { .reg = 0x00009888, .val = 0x08870553 },
         { .reg = 0x00009888, .val = 0x0087AA00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x06880143 },
         { .reg = 0x00009888, .val = 0x08880553 },
         { .reg = 0x00009888, .val = 0x008900F0 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70143 },
         { .reg = 0x00009888, .val = 0x10A70553 },
         { .reg = 0x00009888, .val = 0x02A7AA00 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0EA80143 },
         { .reg = 0x00009888, .val = 0x10A80553 },
         { .reg = 0x00009888, .val = 0x00A9F000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32031083 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030C60 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38031403 },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache21__avg_gpu_core_frequency__max,acmgt2__l1_cache21__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1003, 24, NULL,acmgt2__l1_cache21__load_store_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1004, 32, NULL,acmgt2__l1_cache21__load_store_cache_hit_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache22";
   query->symbol_name = "L1Cache22";
   query->guid = "13dee569-144e-4bb0-b2da-e902336c2f08";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x06C70143 },
         { .reg = 0x00009888, .val = 0x08C70553 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80143 },
         { .reg = 0x00009888, .val = 0x08C80553 },
         { .reg = 0x00009888, .val = 0x00C900F0 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70143 },
         { .reg = 0x00009888, .val = 0x10E70553 },
         { .reg = 0x00009888, .val = 0x02E7AA00 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0EE80143 },
         { .reg = 0x00009888, .val = 0x10E80553 },
         { .reg = 0x00009888, .val = 0x00E9F000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C64 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603108A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030004 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030231 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache22__avg_gpu_core_frequency__max,acmgt2__l1_cache22__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1005, 24, NULL,acmgt2__l1_cache22__load_store_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1006, 32, NULL,acmgt2__l1_cache22__load_store_cache_hit_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache23";
   query->symbol_name = "L1Cache23";
   query->guid = "4b450172-544b-4249-87a4-96acdde97d6c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x07870143 },
         { .reg = 0x00009888, .val = 0x09870553 },
         { .reg = 0x00009888, .val = 0x0187AA00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x07880143 },
         { .reg = 0x00009888, .val = 0x09880553 },
         { .reg = 0x00009888, .val = 0x018900F0 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0FA70143 },
         { .reg = 0x00009888, .val = 0x11A70553 },
         { .reg = 0x00009888, .val = 0x03A7AA00 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0FA80143 },
         { .reg = 0x00009888, .val = 0x11A80553 },
         { .reg = 0x00009888, .val = 0x01A9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32031083 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030C60 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38031403 },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache23__avg_gpu_core_frequency__max,acmgt2__l1_cache23__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1007, 24, NULL,acmgt2__l1_cache23__load_store_cache_hit_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1008, 32, NULL,acmgt2__l1_cache23__load_store_cache_hit_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache24_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache24";
   query->symbol_name = "L1Cache24";
   query->guid = "2bf27543-d6b4-4cb7-b53a-3b83fe6c102e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x07C70143 },
         { .reg = 0x00009888, .val = 0x09C70553 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80143 },
         { .reg = 0x00009888, .val = 0x09C80553 },
         { .reg = 0x00009888, .val = 0x01C900F0 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x0FE70143 },
         { .reg = 0x00009888, .val = 0x11E70553 },
         { .reg = 0x00009888, .val = 0x03E7AA00 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0FE80143 },
         { .reg = 0x00009888, .val = 0x11E80553 },
         { .reg = 0x00009888, .val = 0x01E9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C64 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603108A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030004 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030231 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache24__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache24__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache24__avg_gpu_core_frequency__max,acmgt2__l1_cache24__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1009, 24, NULL,acmgt2__l1_cache24__load_store_cache_hit_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1010, 32, NULL,acmgt2__l1_cache24__load_store_cache_hit_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache25_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache25";
   query->symbol_name = "L1Cache25";
   query->guid = "e1066219-5e33-4b74-b056-94b3a62a7900";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x06870143 },
         { .reg = 0x00009888, .val = 0x08870553 },
         { .reg = 0x00009888, .val = 0x0087AA00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x06880143 },
         { .reg = 0x00009888, .val = 0x08880553 },
         { .reg = 0x00009888, .val = 0x008900F0 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70143 },
         { .reg = 0x00009888, .val = 0x10A70553 },
         { .reg = 0x00009888, .val = 0x02A7AA00 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0EA80143 },
         { .reg = 0x00009888, .val = 0x10A80553 },
         { .reg = 0x00009888, .val = 0x00A9F000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32031083 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030C60 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38031403 },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache25__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache25__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache25__avg_gpu_core_frequency__max,acmgt2__l1_cache25__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2523, 24, NULL,acmgt2__l1_cache25__load_store_cache_hit_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2524, 32, NULL,acmgt2__l1_cache25__load_store_cache_hit_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache26_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache26";
   query->symbol_name = "L1Cache26";
   query->guid = "30ee8347-968a-4ec0-985a-234c0d5ee72e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x06C70143 },
         { .reg = 0x00009888, .val = 0x08C70553 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80143 },
         { .reg = 0x00009888, .val = 0x08C80553 },
         { .reg = 0x00009888, .val = 0x00C900F0 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70143 },
         { .reg = 0x00009888, .val = 0x10E70553 },
         { .reg = 0x00009888, .val = 0x02E7AA00 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0EE80143 },
         { .reg = 0x00009888, .val = 0x10E80553 },
         { .reg = 0x00009888, .val = 0x00E9F000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C64 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603108A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030004 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030231 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache26__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache26__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache26__avg_gpu_core_frequency__max,acmgt2__l1_cache26__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2525, 24, NULL,acmgt2__l1_cache26__load_store_cache_hit_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2526, 32, NULL,acmgt2__l1_cache26__load_store_cache_hit_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache27_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache27";
   query->symbol_name = "L1Cache27";
   query->guid = "d38715b6-5d8d-44ad-82b4-83d6a143d61c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x07870143 },
         { .reg = 0x00009888, .val = 0x09870553 },
         { .reg = 0x00009888, .val = 0x0187AA00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x07880143 },
         { .reg = 0x00009888, .val = 0x09880553 },
         { .reg = 0x00009888, .val = 0x018900F0 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0FA70143 },
         { .reg = 0x00009888, .val = 0x11A70553 },
         { .reg = 0x00009888, .val = 0x03A7AA00 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0FA80143 },
         { .reg = 0x00009888, .val = 0x11A80553 },
         { .reg = 0x00009888, .val = 0x01A9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32031083 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030C60 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38031403 },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache27__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache27__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache27__avg_gpu_core_frequency__max,acmgt2__l1_cache27__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2527, 24, NULL,acmgt2__l1_cache27__load_store_cache_hit_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2528, 32, NULL,acmgt2__l1_cache27__load_store_cache_hit_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache28";
   query->symbol_name = "L1Cache28";
   query->guid = "1f851454-2f9c-44da-b403-82493b4e41ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x07C70143 },
         { .reg = 0x00009888, .val = 0x09C70553 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80143 },
         { .reg = 0x00009888, .val = 0x09C80553 },
         { .reg = 0x00009888, .val = 0x01C900F0 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x0FE70143 },
         { .reg = 0x00009888, .val = 0x11E70553 },
         { .reg = 0x00009888, .val = 0x03E7AA00 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0FE80143 },
         { .reg = 0x00009888, .val = 0x11E80553 },
         { .reg = 0x00009888, .val = 0x01E9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C64 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603108A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030004 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030231 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache28__avg_gpu_core_frequency__max,acmgt2__l1_cache28__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2529, 24, NULL,acmgt2__l1_cache28__load_store_cache_hit_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2530, 32, NULL,acmgt2__l1_cache28__load_store_cache_hit_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache29_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache29";
   query->symbol_name = "L1Cache29";
   query->guid = "32f03e2e-890a-4db8-9d12-cd2a9b46456c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache29__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache29__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache29__avg_gpu_core_frequency__max,acmgt2__l1_cache29__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1766, 24, NULL,acmgt2__l1_cache29__slm_bank_conflict_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache30_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache30";
   query->symbol_name = "L1Cache30";
   query->guid = "f124e69c-983e-4d57-bd6a-26af2dd386ba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18A914C0 },
         { .reg = 0x00009888, .val = 0x1EA900A6 },
         { .reg = 0x00009888, .val = 0x22A91800 },
         { .reg = 0x00009888, .val = 0x24A90005 },
         { .reg = 0x00009888, .val = 0x28A914C0 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A90C31 },
         { .reg = 0x00009888, .val = 0x08A90FBF },
         { .reg = 0x00009888, .val = 0x0AA90821 },
         { .reg = 0x00009888, .val = 0x0CA90BAF },
         { .reg = 0x00009888, .val = 0x0EA90411 },
         { .reg = 0x00009888, .val = 0x10A9079F },
         { .reg = 0x00009888, .val = 0x12A90001 },
         { .reg = 0x00009888, .val = 0x14A9038F },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache30__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache30__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache30__avg_gpu_core_frequency__max,acmgt2__l1_cache30__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1767, 24, NULL,acmgt2__l1_cache30__slm_bank_conflict_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache31";
   query->symbol_name = "L1Cache31";
   query->guid = "77bfa913-7775-4d45-8c3f-4510520c7b15";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18C914C0 },
         { .reg = 0x00009888, .val = 0x1EC900A6 },
         { .reg = 0x00009888, .val = 0x22C91800 },
         { .reg = 0x00009888, .val = 0x24C90005 },
         { .reg = 0x00009888, .val = 0x28C914C0 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C90C31 },
         { .reg = 0x00009888, .val = 0x08C90FBF },
         { .reg = 0x00009888, .val = 0x0AC90821 },
         { .reg = 0x00009888, .val = 0x0CC90BAF },
         { .reg = 0x00009888, .val = 0x0EC90411 },
         { .reg = 0x00009888, .val = 0x10C9079F },
         { .reg = 0x00009888, .val = 0x12C90001 },
         { .reg = 0x00009888, .val = 0x14C9038F },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache31__avg_gpu_core_frequency__max,acmgt2__l1_cache31__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1768, 24, NULL,acmgt2__l1_cache31__slm_bank_conflict_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache32_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache32";
   query->symbol_name = "L1Cache32";
   query->guid = "9ed928dc-d0e2-455c-a2ef-b5cac335bab9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache32__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache32__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache32__avg_gpu_core_frequency__max,acmgt2__l1_cache32__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1769, 24, NULL,acmgt2__l1_cache32__slm_bank_conflict_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache33_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache33";
   query->symbol_name = "L1Cache33";
   query->guid = "6ac07bf2-e77c-4a85-97d8-08d9f86b3f77";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache33__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache33__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache33__avg_gpu_core_frequency__max,acmgt2__l1_cache33__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1770, 24, NULL,acmgt2__l1_cache33__slm_bank_conflict_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache34_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache34";
   query->symbol_name = "L1Cache34";
   query->guid = "d8fde355-eb9a-4490-b61f-31fb98ba4f70";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19A914C0 },
         { .reg = 0x00009888, .val = 0x1FA900A6 },
         { .reg = 0x00009888, .val = 0x23A91800 },
         { .reg = 0x00009888, .val = 0x25A90005 },
         { .reg = 0x00009888, .val = 0x29A914C0 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A90C31 },
         { .reg = 0x00009888, .val = 0x09A90FBF },
         { .reg = 0x00009888, .val = 0x0BA90821 },
         { .reg = 0x00009888, .val = 0x0DA90BAF },
         { .reg = 0x00009888, .val = 0x0FA90411 },
         { .reg = 0x00009888, .val = 0x11A9079F },
         { .reg = 0x00009888, .val = 0x13A90001 },
         { .reg = 0x00009888, .val = 0x15A9038F },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache34__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache34__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache34__avg_gpu_core_frequency__max,acmgt2__l1_cache34__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1771, 24, NULL,acmgt2__l1_cache34__slm_bank_conflict_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache35";
   query->symbol_name = "L1Cache35";
   query->guid = "c045a7e6-dd83-419c-abff-643ccb4ff70f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19C914C0 },
         { .reg = 0x00009888, .val = 0x1FC900A6 },
         { .reg = 0x00009888, .val = 0x23C91800 },
         { .reg = 0x00009888, .val = 0x25C90005 },
         { .reg = 0x00009888, .val = 0x29C914C0 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C90C31 },
         { .reg = 0x00009888, .val = 0x09C90FBF },
         { .reg = 0x00009888, .val = 0x0BC90821 },
         { .reg = 0x00009888, .val = 0x0DC90BAF },
         { .reg = 0x00009888, .val = 0x0FC90411 },
         { .reg = 0x00009888, .val = 0x11C9079F },
         { .reg = 0x00009888, .val = 0x13C90001 },
         { .reg = 0x00009888, .val = 0x15C9038F },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache35__avg_gpu_core_frequency__max,acmgt2__l1_cache35__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1772, 24, NULL,acmgt2__l1_cache35__slm_bank_conflict_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache36_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache36";
   query->symbol_name = "L1Cache36";
   query->guid = "5c6b81b0-056f-451e-b3be-dea10b2c1ecb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache36__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache36__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache36__avg_gpu_core_frequency__max,acmgt2__l1_cache36__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1773, 24, NULL,acmgt2__l1_cache36__slm_bank_conflict_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache37_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache37";
   query->symbol_name = "L1Cache37";
   query->guid = "2558f9cd-1565-498c-a539-430377a55a93";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache37__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache37__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache37__avg_gpu_core_frequency__max,acmgt2__l1_cache37__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2531, 24, NULL,acmgt2__l1_cache37__slm_bank_conflict_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache38_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache38";
   query->symbol_name = "L1Cache38";
   query->guid = "a4a5c1e1-beeb-42ec-ba01-6af0c5eeee90";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18A914C0 },
         { .reg = 0x00009888, .val = 0x1EA900A6 },
         { .reg = 0x00009888, .val = 0x22A91800 },
         { .reg = 0x00009888, .val = 0x24A90005 },
         { .reg = 0x00009888, .val = 0x28A914C0 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A90C31 },
         { .reg = 0x00009888, .val = 0x08A90FBF },
         { .reg = 0x00009888, .val = 0x0AA90821 },
         { .reg = 0x00009888, .val = 0x0CA90BAF },
         { .reg = 0x00009888, .val = 0x0EA90411 },
         { .reg = 0x00009888, .val = 0x10A9079F },
         { .reg = 0x00009888, .val = 0x12A90001 },
         { .reg = 0x00009888, .val = 0x14A9038F },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache38__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache38__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache38__avg_gpu_core_frequency__max,acmgt2__l1_cache38__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2532, 24, NULL,acmgt2__l1_cache38__slm_bank_conflict_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache39";
   query->symbol_name = "L1Cache39";
   query->guid = "7d80234b-4dae-4def-aa0b-2b1fe3ff0a13";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18C914C0 },
         { .reg = 0x00009888, .val = 0x1EC900A6 },
         { .reg = 0x00009888, .val = 0x22C91800 },
         { .reg = 0x00009888, .val = 0x24C90005 },
         { .reg = 0x00009888, .val = 0x28C914C0 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C90C31 },
         { .reg = 0x00009888, .val = 0x08C90FBF },
         { .reg = 0x00009888, .val = 0x0AC90821 },
         { .reg = 0x00009888, .val = 0x0CC90BAF },
         { .reg = 0x00009888, .val = 0x0EC90411 },
         { .reg = 0x00009888, .val = 0x10C9079F },
         { .reg = 0x00009888, .val = 0x12C90001 },
         { .reg = 0x00009888, .val = 0x14C9038F },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache39__avg_gpu_core_frequency__max,acmgt2__l1_cache39__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2533, 24, NULL,acmgt2__l1_cache39__slm_bank_conflict_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache40_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache40";
   query->symbol_name = "L1Cache40";
   query->guid = "ba5d47a0-a35b-4ee2-9cdd-8272cfc149d9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache40__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache40__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache40__avg_gpu_core_frequency__max,acmgt2__l1_cache40__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2534, 24, NULL,acmgt2__l1_cache40__slm_bank_conflict_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache41_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache41";
   query->symbol_name = "L1Cache41";
   query->guid = "692e3adb-d471-44a3-a3ad-0b0fedf05630";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache41__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache41__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache41__avg_gpu_core_frequency__max,acmgt2__l1_cache41__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2535, 24, NULL,acmgt2__l1_cache41__slm_bank_conflict_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache42_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache42";
   query->symbol_name = "L1Cache42";
   query->guid = "c1c40fc7-8db1-401b-8dc9-42c3b51361a4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19A914C0 },
         { .reg = 0x00009888, .val = 0x1FA900A6 },
         { .reg = 0x00009888, .val = 0x23A91800 },
         { .reg = 0x00009888, .val = 0x25A90005 },
         { .reg = 0x00009888, .val = 0x29A914C0 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A90C31 },
         { .reg = 0x00009888, .val = 0x09A90FBF },
         { .reg = 0x00009888, .val = 0x0BA90821 },
         { .reg = 0x00009888, .val = 0x0DA90BAF },
         { .reg = 0x00009888, .val = 0x0FA90411 },
         { .reg = 0x00009888, .val = 0x11A9079F },
         { .reg = 0x00009888, .val = 0x13A90001 },
         { .reg = 0x00009888, .val = 0x15A9038F },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache42__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache42__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache42__avg_gpu_core_frequency__max,acmgt2__l1_cache42__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2536, 24, NULL,acmgt2__l1_cache42__slm_bank_conflict_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache43_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache43";
   query->symbol_name = "L1Cache43";
   query->guid = "e75bf1f9-071f-4c21-8f55-e9ee154638ba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19C914C0 },
         { .reg = 0x00009888, .val = 0x1FC900A6 },
         { .reg = 0x00009888, .val = 0x23C91800 },
         { .reg = 0x00009888, .val = 0x25C90005 },
         { .reg = 0x00009888, .val = 0x29C914C0 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C90C31 },
         { .reg = 0x00009888, .val = 0x09C90FBF },
         { .reg = 0x00009888, .val = 0x0BC90821 },
         { .reg = 0x00009888, .val = 0x0DC90BAF },
         { .reg = 0x00009888, .val = 0x0FC90411 },
         { .reg = 0x00009888, .val = 0x11C9079F },
         { .reg = 0x00009888, .val = 0x13C90001 },
         { .reg = 0x00009888, .val = 0x15C9038F },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache43__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache43__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache43__avg_gpu_core_frequency__max,acmgt2__l1_cache43__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2537, 24, NULL,acmgt2__l1_cache43__slm_bank_conflict_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache44_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "L1Cache44";
   query->symbol_name = "L1Cache44";
   query->guid = "975595a3-2d15-44aa-b32f-0204e42485f4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache44__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache44__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache44__avg_gpu_core_frequency__max,acmgt2__l1_cache44__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2538, 24, NULL,acmgt2__l1_cache44__slm_bank_conflict_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache45";
   query->symbol_name = "L1Cache45";
   query->guid = "9c1f54c9-3b59-479a-97e9-179a40b4b949";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1687000F },
         { .reg = 0x00009888, .val = 0x1A87000F },
         { .reg = 0x00009888, .val = 0x1288000F },
         { .reg = 0x00009888, .val = 0x1688000F },
         { .reg = 0x00009888, .val = 0x16A7000F },
         { .reg = 0x00009888, .val = 0x1AA7000F },
         { .reg = 0x00009888, .val = 0x12A8000F },
         { .reg = 0x00009888, .val = 0x16A8000F },
         { .reg = 0x00009888, .val = 0x16C7000F },
         { .reg = 0x00009888, .val = 0x1AC7000F },
         { .reg = 0x00009888, .val = 0x12C8000F },
         { .reg = 0x00009888, .val = 0x16C8000F },
         { .reg = 0x00009888, .val = 0x16E7000F },
         { .reg = 0x00009888, .val = 0x1AE7000F },
         { .reg = 0x00009888, .val = 0x12E8000F },
         { .reg = 0x00009888, .val = 0x16E8000F },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache45__avg_gpu_core_frequency__max,acmgt2__l1_cache45__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1696, 24, NULL,acmgt2__l1_cache45__slm_access_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1695, 32, NULL,acmgt2__l1_cache45__slm_access_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1694, 40, NULL,acmgt2__l1_cache45__slm_access_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1697, 48, NULL,acmgt2__l1_cache45__slm_access_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache46_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache46";
   query->symbol_name = "L1Cache46";
   query->guid = "eebc8739-0987-4f55-b70f-6cdee1a4ec02";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1787000F },
         { .reg = 0x00009888, .val = 0x1B87000F },
         { .reg = 0x00009888, .val = 0x1388000F },
         { .reg = 0x00009888, .val = 0x1788000F },
         { .reg = 0x00009888, .val = 0x17A7000F },
         { .reg = 0x00009888, .val = 0x1BA7000F },
         { .reg = 0x00009888, .val = 0x13A8000F },
         { .reg = 0x00009888, .val = 0x17A8000F },
         { .reg = 0x00009888, .val = 0x17C7000F },
         { .reg = 0x00009888, .val = 0x1BC7000F },
         { .reg = 0x00009888, .val = 0x13C8000F },
         { .reg = 0x00009888, .val = 0x17C8000F },
         { .reg = 0x00009888, .val = 0x17E7000F },
         { .reg = 0x00009888, .val = 0x1BE7000F },
         { .reg = 0x00009888, .val = 0x13E8000F },
         { .reg = 0x00009888, .val = 0x17E8000F },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache46__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache46__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache46__avg_gpu_core_frequency__max,acmgt2__l1_cache46__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1698, 24, NULL,acmgt2__l1_cache46__slm_access_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1699, 32, NULL,acmgt2__l1_cache46__slm_access_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1700, 40, NULL,acmgt2__l1_cache46__slm_access_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1701, 48, NULL,acmgt2__l1_cache46__slm_access_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache47_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache47";
   query->symbol_name = "L1Cache47";
   query->guid = "e01f5549-332a-4e23-b915-828860d438cc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1687000F },
         { .reg = 0x00009888, .val = 0x1A87000F },
         { .reg = 0x00009888, .val = 0x1288000F },
         { .reg = 0x00009888, .val = 0x1688000F },
         { .reg = 0x00009888, .val = 0x16A7000F },
         { .reg = 0x00009888, .val = 0x1AA7000F },
         { .reg = 0x00009888, .val = 0x12A8000F },
         { .reg = 0x00009888, .val = 0x16A8000F },
         { .reg = 0x00009888, .val = 0x16C7000F },
         { .reg = 0x00009888, .val = 0x1AC7000F },
         { .reg = 0x00009888, .val = 0x12C8000F },
         { .reg = 0x00009888, .val = 0x16C8000F },
         { .reg = 0x00009888, .val = 0x16E7000F },
         { .reg = 0x00009888, .val = 0x1AE7000F },
         { .reg = 0x00009888, .val = 0x12E8000F },
         { .reg = 0x00009888, .val = 0x16E8000F },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache47__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache47__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache47__avg_gpu_core_frequency__max,acmgt2__l1_cache47__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2539, 24, NULL,acmgt2__l1_cache47__slm_access_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2540, 32, NULL,acmgt2__l1_cache47__slm_access_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2541, 40, NULL,acmgt2__l1_cache47__slm_access_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2542, 48, NULL,acmgt2__l1_cache47__slm_access_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache48_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache48";
   query->symbol_name = "L1Cache48";
   query->guid = "389c0253-dbfb-47b3-878e-3eb1b9b6e74f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1787000F },
         { .reg = 0x00009888, .val = 0x1B87000F },
         { .reg = 0x00009888, .val = 0x1388000F },
         { .reg = 0x00009888, .val = 0x1788000F },
         { .reg = 0x00009888, .val = 0x17A7000F },
         { .reg = 0x00009888, .val = 0x1BA7000F },
         { .reg = 0x00009888, .val = 0x13A8000F },
         { .reg = 0x00009888, .val = 0x17A8000F },
         { .reg = 0x00009888, .val = 0x17C7000F },
         { .reg = 0x00009888, .val = 0x1BC7000F },
         { .reg = 0x00009888, .val = 0x13C8000F },
         { .reg = 0x00009888, .val = 0x17C8000F },
         { .reg = 0x00009888, .val = 0x17E7000F },
         { .reg = 0x00009888, .val = 0x1BE7000F },
         { .reg = 0x00009888, .val = 0x13E8000F },
         { .reg = 0x00009888, .val = 0x17E8000F },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache48__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache48__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache48__avg_gpu_core_frequency__max,acmgt2__l1_cache48__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2543, 24, NULL,acmgt2__l1_cache48__slm_access_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2544, 32, NULL,acmgt2__l1_cache48__slm_access_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2545, 40, NULL,acmgt2__l1_cache48__slm_access_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2546, 48, NULL,acmgt2__l1_cache48__slm_access_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache49_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache49";
   query->symbol_name = "L1Cache49";
   query->guid = "23488fdc-0420-4cee-b15a-000f3fe0c61c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache49__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache49__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache49__avg_gpu_core_frequency__max,acmgt2__l1_cache49__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1083, 24, NULL,acmgt2__l1_cache49__xve_slm_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1084, 32, NULL,acmgt2__l1_cache49__xve_slm_read_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache50_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache50";
   query->symbol_name = "L1Cache50";
   query->guid = "229bdc13-d602-4e78-a325-c082919dc47a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache50__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache50__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache50__avg_gpu_core_frequency__max,acmgt2__l1_cache50__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1085, 24, NULL,acmgt2__l1_cache50__xve_slm_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1086, 32, NULL,acmgt2__l1_cache50__xve_slm_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache51_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache51";
   query->symbol_name = "L1Cache51";
   query->guid = "35c25f46-14d7-46fa-927f-35507e61a2fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache51__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache51__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache51__avg_gpu_core_frequency__max,acmgt2__l1_cache51__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1087, 24, NULL,acmgt2__l1_cache51__xve_slm_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1088, 32, NULL,acmgt2__l1_cache51__xve_slm_read_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache52_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache52";
   query->symbol_name = "L1Cache52";
   query->guid = "94284c36-9664-4d60-b4d9-15179f266d23";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache52__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache52__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache52__avg_gpu_core_frequency__max,acmgt2__l1_cache52__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1089, 24, NULL,acmgt2__l1_cache52__xve_slm_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1090, 32, NULL,acmgt2__l1_cache52__xve_slm_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache53_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache53";
   query->symbol_name = "L1Cache53";
   query->guid = "a2b93539-7c7e-4ea4-85df-2fa675381a1b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache53__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache53__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache53__avg_gpu_core_frequency__max,acmgt2__l1_cache53__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2547, 24, NULL,acmgt2__l1_cache53__xve_slm_read_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2548, 32, NULL,acmgt2__l1_cache53__xve_slm_read_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache54_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache54";
   query->symbol_name = "L1Cache54";
   query->guid = "8efc5126-1bb6-47cd-bd3c-b1bfa6a99dc1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache54__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache54__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache54__avg_gpu_core_frequency__max,acmgt2__l1_cache54__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2549, 24, NULL,acmgt2__l1_cache54__xve_slm_read_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2550, 32, NULL,acmgt2__l1_cache54__xve_slm_read_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache55_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache55";
   query->symbol_name = "L1Cache55";
   query->guid = "4a628907-5db2-437c-b04e-8c14dede3794";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache55__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache55__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache55__avg_gpu_core_frequency__max,acmgt2__l1_cache55__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2551, 24, NULL,acmgt2__l1_cache55__xve_slm_read_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2552, 32, NULL,acmgt2__l1_cache55__xve_slm_read_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache56_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache56";
   query->symbol_name = "L1Cache56";
   query->guid = "e017d352-78fe-4f3e-bda9-814fb14f495e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache56__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache56__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache56__avg_gpu_core_frequency__max,acmgt2__l1_cache56__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2553, 24, NULL,acmgt2__l1_cache56__xve_slm_read_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2554, 32, NULL,acmgt2__l1_cache56__xve_slm_read_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache57_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache57";
   query->symbol_name = "L1Cache57";
   query->guid = "c89b207d-e5c1-480a-8b15-5403d0e45fb9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache57__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache57__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache57__avg_gpu_core_frequency__max,acmgt2__l1_cache57__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1091, 24, NULL,acmgt2__l1_cache57__xve_slm_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1092, 32, NULL,acmgt2__l1_cache57__xve_slm_write_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache58_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache58";
   query->symbol_name = "L1Cache58";
   query->guid = "dd46fc9a-6a2c-44c7-94f3-069b58c95aca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache58__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache58__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache58__avg_gpu_core_frequency__max,acmgt2__l1_cache58__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1093, 24, NULL,acmgt2__l1_cache58__xve_slm_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1094, 32, NULL,acmgt2__l1_cache58__xve_slm_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache59_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache59";
   query->symbol_name = "L1Cache59";
   query->guid = "4669435c-6f14-4557-b983-3f5186807fd6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache59__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache59__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache59__avg_gpu_core_frequency__max,acmgt2__l1_cache59__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1095, 24, NULL,acmgt2__l1_cache59__xve_slm_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1096, 32, NULL,acmgt2__l1_cache59__xve_slm_write_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache60_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache60";
   query->symbol_name = "L1Cache60";
   query->guid = "6f37e5b7-c8fd-4f28-a95d-919848fe4a95";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache60__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache60__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache60__avg_gpu_core_frequency__max,acmgt2__l1_cache60__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1097, 24, NULL,acmgt2__l1_cache60__xve_slm_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1098, 32, NULL,acmgt2__l1_cache60__xve_slm_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache61_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache61";
   query->symbol_name = "L1Cache61";
   query->guid = "0cd1c331-f998-467e-ae36-ea334c3ba2a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache61__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache61__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache61__avg_gpu_core_frequency__max,acmgt2__l1_cache61__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2555, 24, NULL,acmgt2__l1_cache61__xve_slm_write_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2556, 32, NULL,acmgt2__l1_cache61__xve_slm_write_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache62_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache62";
   query->symbol_name = "L1Cache62";
   query->guid = "09153d17-1912-4ce4-b41a-709df4aba848";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache62__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache62__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache62__avg_gpu_core_frequency__max,acmgt2__l1_cache62__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2557, 24, NULL,acmgt2__l1_cache62__xve_slm_write_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2558, 32, NULL,acmgt2__l1_cache62__xve_slm_write_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache63_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache63";
   query->symbol_name = "L1Cache63";
   query->guid = "ea0e19bb-8a13-4e51-92ca-1cb3db78fb10";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache63__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache63__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache63__avg_gpu_core_frequency__max,acmgt2__l1_cache63__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2559, 24, NULL,acmgt2__l1_cache63__xve_slm_write_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2560, 32, NULL,acmgt2__l1_cache63__xve_slm_write_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache64_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache64";
   query->symbol_name = "L1Cache64";
   query->guid = "d7eb30f5-28aa-455b-b8a5-221db2ccfe62";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache64__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache64__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache64__avg_gpu_core_frequency__max,acmgt2__l1_cache64__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2561, 24, NULL,acmgt2__l1_cache64__xve_slm_write_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2562, 32, NULL,acmgt2__l1_cache64__xve_slm_write_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache65_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache65";
   query->symbol_name = "L1Cache65";
   query->guid = "ae51ef65-a808-4248-8c26-8fcda92bb018";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x128905C7 },
         { .reg = 0x00009888, .val = 0x14890DE7 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache65__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache65__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache65__avg_gpu_core_frequency__max,acmgt2__l1_cache65__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1107, 24, NULL,acmgt2__l1_cache65__xve_slm_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1099, 32, NULL,acmgt2__l1_cache65__xve_slm_fence_message_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache66_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache66";
   query->symbol_name = "L1Cache66";
   query->guid = "e6e2b49c-615f-4af1-a7b1-349f6b906c90";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x12A905C7 },
         { .reg = 0x00009888, .val = 0x14A90DE7 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache66__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache66__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache66__avg_gpu_core_frequency__max,acmgt2__l1_cache66__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1108, 24, NULL,acmgt2__l1_cache66__xve_slm_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1100, 32, NULL,acmgt2__l1_cache66__xve_slm_fence_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache67_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache67";
   query->symbol_name = "L1Cache67";
   query->guid = "691098de-d8d8-40f3-906f-b20df78f5b52";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x12C905C7 },
         { .reg = 0x00009888, .val = 0x14C90DE7 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache67__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache67__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache67__avg_gpu_core_frequency__max,acmgt2__l1_cache67__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1109, 24, NULL,acmgt2__l1_cache67__xve_slm_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1101, 32, NULL,acmgt2__l1_cache67__xve_slm_fence_message_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache68_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache68";
   query->symbol_name = "L1Cache68";
   query->guid = "bdcc17c1-0c82-4277-8c4a-6c878af1f374";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x12E905C7 },
         { .reg = 0x00009888, .val = 0x14E90DE7 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache68__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache68__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache68__avg_gpu_core_frequency__max,acmgt2__l1_cache68__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1110, 24, NULL,acmgt2__l1_cache68__xve_slm_atomic_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1102, 32, NULL,acmgt2__l1_cache68__xve_slm_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache69_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache69";
   query->symbol_name = "L1Cache69";
   query->guid = "e2417f86-ea22-4512-b4b6-1918c6721e47";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x138905C7 },
         { .reg = 0x00009888, .val = 0x15890DE7 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache69__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache69__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache69__avg_gpu_core_frequency__max,acmgt2__l1_cache69__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1111, 24, NULL,acmgt2__l1_cache69__xve_slm_atomic_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1103, 32, NULL,acmgt2__l1_cache69__xve_slm_fence_message_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache70_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache70";
   query->symbol_name = "L1Cache70";
   query->guid = "0b7a01c5-5622-43cd-90c1-963d8ebc4d30";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x13A905C7 },
         { .reg = 0x00009888, .val = 0x15A90DE7 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache70__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache70__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache70__avg_gpu_core_frequency__max,acmgt2__l1_cache70__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1112, 24, NULL,acmgt2__l1_cache70__xve_slm_atomic_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1104, 32, NULL,acmgt2__l1_cache70__xve_slm_fence_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache71_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache71";
   query->symbol_name = "L1Cache71";
   query->guid = "e0da306c-65eb-4032-b327-f95f4eba3020";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x13C905C7 },
         { .reg = 0x00009888, .val = 0x15C90DE7 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache71__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache71__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache71__avg_gpu_core_frequency__max,acmgt2__l1_cache71__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1113, 24, NULL,acmgt2__l1_cache71__xve_slm_atomic_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1105, 32, NULL,acmgt2__l1_cache71__xve_slm_fence_message_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache72_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache72";
   query->symbol_name = "L1Cache72";
   query->guid = "10f602b1-6401-49df-b617-8fb07c188fa2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x13E905C7 },
         { .reg = 0x00009888, .val = 0x15E90DE7 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache72__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache72__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache72__avg_gpu_core_frequency__max,acmgt2__l1_cache72__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1114, 24, NULL,acmgt2__l1_cache72__xve_slm_atomic_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1106, 32, NULL,acmgt2__l1_cache72__xve_slm_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache73_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache73";
   query->symbol_name = "L1Cache73";
   query->guid = "8bcaab96-b9ff-4445-9b12-77c6645d4889";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x128905C7 },
         { .reg = 0x00009888, .val = 0x14890DE7 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache73__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache73__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache73__avg_gpu_core_frequency__max,acmgt2__l1_cache73__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2563, 24, NULL,acmgt2__l1_cache73__xve_slm_atomic_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2564, 32, NULL,acmgt2__l1_cache73__xve_slm_fence_message_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache74_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache74";
   query->symbol_name = "L1Cache74";
   query->guid = "fb2f0a27-1305-4d18-9940-d644f2fd2607";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x12A905C7 },
         { .reg = 0x00009888, .val = 0x14A90DE7 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache74__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache74__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache74__avg_gpu_core_frequency__max,acmgt2__l1_cache74__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2565, 24, NULL,acmgt2__l1_cache74__xve_slm_atomic_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2566, 32, NULL,acmgt2__l1_cache74__xve_slm_fence_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache75_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache75";
   query->symbol_name = "L1Cache75";
   query->guid = "e79fe17b-cecf-4808-98f8-dbf002286e99";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x12C905C7 },
         { .reg = 0x00009888, .val = 0x14C90DE7 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache75__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache75__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache75__avg_gpu_core_frequency__max,acmgt2__l1_cache75__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2567, 24, NULL,acmgt2__l1_cache75__xve_slm_atomic_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2568, 32, NULL,acmgt2__l1_cache75__xve_slm_fence_message_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache76_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache76";
   query->symbol_name = "L1Cache76";
   query->guid = "b25a8d2b-6410-4f91-af8d-364c2f31263a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x12E905C7 },
         { .reg = 0x00009888, .val = 0x14E90DE7 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache76__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache76__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache76__avg_gpu_core_frequency__max,acmgt2__l1_cache76__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2569, 24, NULL,acmgt2__l1_cache76__xve_slm_atomic_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2570, 32, NULL,acmgt2__l1_cache76__xve_slm_fence_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache77_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache77";
   query->symbol_name = "L1Cache77";
   query->guid = "45ec41ff-4a28-4282-973b-8fcbe65cf00d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x138905C7 },
         { .reg = 0x00009888, .val = 0x15890DE7 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache77__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache77__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache77__avg_gpu_core_frequency__max,acmgt2__l1_cache77__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2571, 24, NULL,acmgt2__l1_cache77__xve_slm_atomic_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2572, 32, NULL,acmgt2__l1_cache77__xve_slm_fence_message_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache78_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache78";
   query->symbol_name = "L1Cache78";
   query->guid = "f2ea74eb-3520-4e62-a9e9-6907afd1a5e6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x13A905C7 },
         { .reg = 0x00009888, .val = 0x15A90DE7 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache78__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache78__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache78__avg_gpu_core_frequency__max,acmgt2__l1_cache78__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2573, 24, NULL,acmgt2__l1_cache78__xve_slm_atomic_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2574, 32, NULL,acmgt2__l1_cache78__xve_slm_fence_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache79_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache79";
   query->symbol_name = "L1Cache79";
   query->guid = "90e0b182-84d1-4bc7-aa0b-448bb0a7a850";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x13C905C7 },
         { .reg = 0x00009888, .val = 0x15C90DE7 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache79__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache79__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache79__avg_gpu_core_frequency__max,acmgt2__l1_cache79__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2575, 24, NULL,acmgt2__l1_cache79__xve_slm_atomic_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2576, 32, NULL,acmgt2__l1_cache79__xve_slm_fence_message_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache80_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache80";
   query->symbol_name = "L1Cache80";
   query->guid = "8f0b735d-f269-4545-8a11-a31b3ebed779";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x13E905C7 },
         { .reg = 0x00009888, .val = 0x15E90DE7 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008022 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010102 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020802 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00044002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache80__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache80__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache80__avg_gpu_core_frequency__max,acmgt2__l1_cache80__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2577, 24, NULL,acmgt2__l1_cache80__xve_slm_atomic_message_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2578, 32, NULL,acmgt2__l1_cache80__xve_slm_fence_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache81_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache81";
   query->symbol_name = "L1Cache81";
   query->guid = "6e136a5b-e7fa-4349-be46-e83455caec62";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache81__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache81__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache81__avg_gpu_core_frequency__max,acmgt2__l1_cache81__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1060, 24, NULL,acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1062, 32, NULL,acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1064, 40, NULL,acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1066, 48, NULL,acmgt2__l1_cache81__xve_load_store_cache_register_request_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache82_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache82";
   query->symbol_name = "L1Cache82";
   query->guid = "c59e0c0d-d038-4b0a-b643-bccfd3963f4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache82__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache82__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache82__avg_gpu_core_frequency__max,acmgt2__l1_cache82__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1068, 24, NULL,acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1070, 32, NULL,acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1072, 40, NULL,acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1074, 48, NULL,acmgt2__l1_cache82__xve_load_store_cache_register_request_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache83_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache83";
   query->symbol_name = "L1Cache83";
   query->guid = "5180e659-772f-4531-a2cb-f38a86841e22";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache83__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache83__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache83__avg_gpu_core_frequency__max,acmgt2__l1_cache83__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2579, 24, NULL,acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2580, 32, NULL,acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2581, 40, NULL,acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2582, 48, NULL,acmgt2__l1_cache83__xve_load_store_cache_register_request_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache84_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache84";
   query->symbol_name = "L1Cache84";
   query->guid = "53e81609-e3d2-4679-b348-6f6473dd0fe2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache84__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache84__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache84__avg_gpu_core_frequency__max,acmgt2__l1_cache84__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2583, 24, NULL,acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2584, 32, NULL,acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2585, 40, NULL,acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2586, 48, NULL,acmgt2__l1_cache84__xve_load_store_cache_register_request_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache85_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache85";
   query->symbol_name = "L1Cache85";
   query->guid = "16e8cd96-5a5d-4528-999b-90629facef72";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache85__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache85__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache85__avg_gpu_core_frequency__max,acmgt2__l1_cache85__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1075, 24, NULL,acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1076, 32, NULL,acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1077, 40, NULL,acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1078, 48, NULL,acmgt2__l1_cache85__xve_load_store_cache_register_response_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache86_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache86";
   query->symbol_name = "L1Cache86";
   query->guid = "d4e55aa0-754b-4fab-9134-ba7168529642";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache86__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache86__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache86__avg_gpu_core_frequency__max,acmgt2__l1_cache86__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1079, 24, NULL,acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1080, 32, NULL,acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1081, 40, NULL,acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1082, 48, NULL,acmgt2__l1_cache86__xve_load_store_cache_register_response_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache87_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache87";
   query->symbol_name = "L1Cache87";
   query->guid = "e80e1404-d74b-4e84-b8b2-317fe06a2900";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache87__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache87__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache87__avg_gpu_core_frequency__max,acmgt2__l1_cache87__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2587, 24, NULL,acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2588, 32, NULL,acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2589, 40, NULL,acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2590, 48, NULL,acmgt2__l1_cache87__xve_load_store_cache_register_response_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache88_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache88";
   query->symbol_name = "L1Cache88";
   query->guid = "b096a99f-7544-4891-9336-6a1a8f341b31";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache88__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache88__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache88__avg_gpu_core_frequency__max,acmgt2__l1_cache88__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2591, 24, NULL,acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2592, 32, NULL,acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2593, 40, NULL,acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2594, 48, NULL,acmgt2__l1_cache88__xve_load_store_cache_register_response_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache89_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache89";
   query->symbol_name = "L1Cache89";
   query->guid = "8164944d-16b7-4415-9c9d-c9155b54d313";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache89__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache89__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache89__avg_gpu_core_frequency__max,acmgt2__l1_cache89__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1035, 24, NULL,acmgt2__l1_cache89__xve_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1036, 32, NULL,acmgt2__l1_cache89__xve_load_store_cache_read_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache90_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache90";
   query->symbol_name = "L1Cache90";
   query->guid = "f04cb35e-ad18-487c-a3a7-4c3df903df4e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache90__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache90__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache90__avg_gpu_core_frequency__max,acmgt2__l1_cache90__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1037, 24, NULL,acmgt2__l1_cache90__xve_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1038, 32, NULL,acmgt2__l1_cache90__xve_load_store_cache_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache91_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache91";
   query->symbol_name = "L1Cache91";
   query->guid = "7476a997-fd23-4e09-9e41-be5ad6998370";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache91__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache91__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache91__avg_gpu_core_frequency__max,acmgt2__l1_cache91__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1039, 24, NULL,acmgt2__l1_cache91__xve_load_store_cache_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1040, 32, NULL,acmgt2__l1_cache91__xve_load_store_cache_read_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache92_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache92";
   query->symbol_name = "L1Cache92";
   query->guid = "c39f76fb-108f-4470-adb7-92f0830b4b85";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache92__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache92__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache92__avg_gpu_core_frequency__max,acmgt2__l1_cache92__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1041, 24, NULL,acmgt2__l1_cache92__xve_load_store_cache_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1042, 32, NULL,acmgt2__l1_cache92__xve_load_store_cache_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache93_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache93";
   query->symbol_name = "L1Cache93";
   query->guid = "3a32053e-1919-4630-a163-dcacf9c6d003";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache93__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache93__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache93__avg_gpu_core_frequency__max,acmgt2__l1_cache93__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2595, 24, NULL,acmgt2__l1_cache93__xve_load_store_cache_read_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2596, 32, NULL,acmgt2__l1_cache93__xve_load_store_cache_read_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache94_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache94";
   query->symbol_name = "L1Cache94";
   query->guid = "340e5f66-a0d2-4365-9a67-76f5fea0b623";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache94__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache94__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache94__avg_gpu_core_frequency__max,acmgt2__l1_cache94__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2597, 24, NULL,acmgt2__l1_cache94__xve_load_store_cache_read_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2598, 32, NULL,acmgt2__l1_cache94__xve_load_store_cache_read_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache95_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache95";
   query->symbol_name = "L1Cache95";
   query->guid = "14d53071-a58c-4e71-b4e4-160815efdc7c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache95__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache95__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache95__avg_gpu_core_frequency__max,acmgt2__l1_cache95__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2599, 24, NULL,acmgt2__l1_cache95__xve_load_store_cache_read_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2600, 32, NULL,acmgt2__l1_cache95__xve_load_store_cache_read_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache96_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache96";
   query->symbol_name = "L1Cache96";
   query->guid = "b390699e-0883-423a-a7c3-064e0520ebed";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache96__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache96__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache96__avg_gpu_core_frequency__max,acmgt2__l1_cache96__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2601, 24, NULL,acmgt2__l1_cache96__xve_load_store_cache_read_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2602, 32, NULL,acmgt2__l1_cache96__xve_load_store_cache_read_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache97_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache97";
   query->symbol_name = "L1Cache97";
   query->guid = "74f12f6d-05be-4a80-9870-2a2c487f7bd9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache97__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache97__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache97__avg_gpu_core_frequency__max,acmgt2__l1_cache97__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1043, 24, NULL,acmgt2__l1_cache97__xve_load_store_cache_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1044, 32, NULL,acmgt2__l1_cache97__xve_load_store_cache_write_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache98_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache98";
   query->symbol_name = "L1Cache98";
   query->guid = "f587f7f5-b5fd-4183-a59c-3ca769fe8148";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache98__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache98__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache98__avg_gpu_core_frequency__max,acmgt2__l1_cache98__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1045, 24, NULL,acmgt2__l1_cache98__xve_load_store_cache_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1046, 32, NULL,acmgt2__l1_cache98__xve_load_store_cache_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache99_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache99";
   query->symbol_name = "L1Cache99";
   query->guid = "08848093-c9f7-4554-a447-278c4da9f9ea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache99__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache99__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache99__avg_gpu_core_frequency__max,acmgt2__l1_cache99__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1047, 24, NULL,acmgt2__l1_cache99__xve_load_store_cache_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1048, 32, NULL,acmgt2__l1_cache99__xve_load_store_cache_write_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache100_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache100";
   query->symbol_name = "L1Cache100";
   query->guid = "8fd337d7-938c-4a64-b5b9-37df6074e4c0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache100__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache100__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache100__avg_gpu_core_frequency__max,acmgt2__l1_cache100__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1049, 24, NULL,acmgt2__l1_cache100__xve_load_store_cache_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1050, 32, NULL,acmgt2__l1_cache100__xve_load_store_cache_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache101_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache101";
   query->symbol_name = "L1Cache101";
   query->guid = "e47ea265-e42a-4a04-81b2-30814815b3aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache101__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache101__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache101__avg_gpu_core_frequency__max,acmgt2__l1_cache101__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2603, 24, NULL,acmgt2__l1_cache101__xve_load_store_cache_write_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2604, 32, NULL,acmgt2__l1_cache101__xve_load_store_cache_write_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache102_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache102";
   query->symbol_name = "L1Cache102";
   query->guid = "ff5717d6-fae7-4288-885c-3850588e4b2e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache102__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache102__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache102__avg_gpu_core_frequency__max,acmgt2__l1_cache102__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2605, 24, NULL,acmgt2__l1_cache102__xve_load_store_cache_write_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2606, 32, NULL,acmgt2__l1_cache102__xve_load_store_cache_write_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache103_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache103";
   query->symbol_name = "L1Cache103";
   query->guid = "9fad96f4-5977-4cf8-a2e4-bd72b277075f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x3203000A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803140A },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache103__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache103__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache103__avg_gpu_core_frequency__max,acmgt2__l1_cache103__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2607, 24, NULL,acmgt2__l1_cache103__xve_load_store_cache_write_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2608, 32, NULL,acmgt2__l1_cache103__xve_load_store_cache_write_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache104_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache104";
   query->symbol_name = "L1Cache104";
   query->guid = "997c44e5-85b3-47f7-9845-6c42c554caae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032940 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x3603000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache104__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache104__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache104__avg_gpu_core_frequency__max,acmgt2__l1_cache104__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2609, 24, NULL,acmgt2__l1_cache104__xve_load_store_cache_write_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2610, 32, NULL,acmgt2__l1_cache104__xve_load_store_cache_write_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache105_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache105";
   query->symbol_name = "L1Cache105";
   query->guid = "7c51d383-b682-4f1d-831d-b689c8be3fdd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x128905C7 },
         { .reg = 0x00009888, .val = 0x14890DE7 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache105__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache105__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache105__avg_gpu_core_frequency__max,acmgt2__l1_cache105__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1059, 24, NULL,acmgt2__l1_cache105__xve_load_store_cache_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1051, 32, NULL,acmgt2__l1_cache105__xve_load_store_cache_fence_message_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache106_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache106";
   query->symbol_name = "L1Cache106";
   query->guid = "04638c41-779d-4d79-a3bc-69b642342b99";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x12A905C7 },
         { .reg = 0x00009888, .val = 0x14A90DE7 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache106__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache106__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache106__avg_gpu_core_frequency__max,acmgt2__l1_cache106__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1061, 24, NULL,acmgt2__l1_cache106__xve_load_store_cache_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1052, 32, NULL,acmgt2__l1_cache106__xve_load_store_cache_fence_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache107_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache107";
   query->symbol_name = "L1Cache107";
   query->guid = "86bb1e10-f542-4f9c-b0f3-8a1fc1caf5aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x12C905C7 },
         { .reg = 0x00009888, .val = 0x14C90DE7 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache107__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache107__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache107__avg_gpu_core_frequency__max,acmgt2__l1_cache107__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1063, 24, NULL,acmgt2__l1_cache107__xve_load_store_cache_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1053, 32, NULL,acmgt2__l1_cache107__xve_load_store_cache_fence_message_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache108_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache108";
   query->symbol_name = "L1Cache108";
   query->guid = "dab065f1-c8a2-4e03-823e-ad9591fdcf29";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x12E905C7 },
         { .reg = 0x00009888, .val = 0x14E90DE7 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache108__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache108__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache108__avg_gpu_core_frequency__max,acmgt2__l1_cache108__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1065, 24, NULL,acmgt2__l1_cache108__xve_load_store_cache_atomic_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1054, 32, NULL,acmgt2__l1_cache108__xve_load_store_cache_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache109_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache109";
   query->symbol_name = "L1Cache109";
   query->guid = "cefea11c-d38d-4ddb-8ce1-f24d75799a7e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x138905C7 },
         { .reg = 0x00009888, .val = 0x15890DE7 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache109__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache109__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache109__avg_gpu_core_frequency__max,acmgt2__l1_cache109__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1067, 24, NULL,acmgt2__l1_cache109__xve_load_store_cache_atomic_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1055, 32, NULL,acmgt2__l1_cache109__xve_load_store_cache_fence_message_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache110_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache110";
   query->symbol_name = "L1Cache110";
   query->guid = "1178f323-ea3e-41c3-905c-2a8442f3b4f6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x13A905C7 },
         { .reg = 0x00009888, .val = 0x15A90DE7 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache110__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache110__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache110__avg_gpu_core_frequency__max,acmgt2__l1_cache110__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1069, 24, NULL,acmgt2__l1_cache110__xve_load_store_cache_atomic_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1056, 32, NULL,acmgt2__l1_cache110__xve_load_store_cache_fence_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache111_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache111";
   query->symbol_name = "L1Cache111";
   query->guid = "26bca320-d4e2-460a-9896-a5fb2a279ccf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x13C905C7 },
         { .reg = 0x00009888, .val = 0x15C90DE7 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache111__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache111__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache111__avg_gpu_core_frequency__max,acmgt2__l1_cache111__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1071, 24, NULL,acmgt2__l1_cache111__xve_load_store_cache_atomic_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1057, 32, NULL,acmgt2__l1_cache111__xve_load_store_cache_fence_message_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache112_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache112";
   query->symbol_name = "L1Cache112";
   query->guid = "3f8fbb78-69b9-4e93-afcb-2a0f380c2013";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x13E905C7 },
         { .reg = 0x00009888, .val = 0x15E90DE7 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache112__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache112__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache112__avg_gpu_core_frequency__max,acmgt2__l1_cache112__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1073, 24, NULL,acmgt2__l1_cache112__xve_load_store_cache_atomic_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1058, 32, NULL,acmgt2__l1_cache112__xve_load_store_cache_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache113_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache113";
   query->symbol_name = "L1Cache113";
   query->guid = "da9b2768-977e-4de8-bbd1-036260d79f93";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x128905C7 },
         { .reg = 0x00009888, .val = 0x14890DE7 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache113__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache113__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache113__avg_gpu_core_frequency__max,acmgt2__l1_cache113__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2611, 24, NULL,acmgt2__l1_cache113__xve_load_store_cache_atomic_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2612, 32, NULL,acmgt2__l1_cache113__xve_load_store_cache_fence_message_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache114_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache114";
   query->symbol_name = "L1Cache114";
   query->guid = "0eb1375c-25b4-47ff-b124-ba4eba95871a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x12A905C7 },
         { .reg = 0x00009888, .val = 0x14A90DE7 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache114__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache114__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache114__avg_gpu_core_frequency__max,acmgt2__l1_cache114__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2613, 24, NULL,acmgt2__l1_cache114__xve_load_store_cache_atomic_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2614, 32, NULL,acmgt2__l1_cache114__xve_load_store_cache_fence_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache115_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache115";
   query->symbol_name = "L1Cache115";
   query->guid = "58be8181-92a3-4cec-ad46-30ea575830ad";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x12C905C7 },
         { .reg = 0x00009888, .val = 0x14C90DE7 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache115__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache115__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache115__avg_gpu_core_frequency__max,acmgt2__l1_cache115__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2615, 24, NULL,acmgt2__l1_cache115__xve_load_store_cache_atomic_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2616, 32, NULL,acmgt2__l1_cache115__xve_load_store_cache_fence_message_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache116_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache116";
   query->symbol_name = "L1Cache116";
   query->guid = "1a3918a7-1fc2-430f-82f2-9114e69586fb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x12E905C7 },
         { .reg = 0x00009888, .val = 0x14E90DE7 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache116__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache116__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache116__avg_gpu_core_frequency__max,acmgt2__l1_cache116__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2617, 24, NULL,acmgt2__l1_cache116__xve_load_store_cache_atomic_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2618, 32, NULL,acmgt2__l1_cache116__xve_load_store_cache_fence_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache117_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache117";
   query->symbol_name = "L1Cache117";
   query->guid = "5206a8c9-3c75-485b-8e78-e3057cda1bb2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x138905C7 },
         { .reg = 0x00009888, .val = 0x15890DE7 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache117__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache117__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache117__avg_gpu_core_frequency__max,acmgt2__l1_cache117__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2619, 24, NULL,acmgt2__l1_cache117__xve_load_store_cache_atomic_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2620, 32, NULL,acmgt2__l1_cache117__xve_load_store_cache_fence_message_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache118_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache118";
   query->symbol_name = "L1Cache118";
   query->guid = "fe39d1bc-b405-4a4d-99a5-3079c0cb6a71";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x13A905C7 },
         { .reg = 0x00009888, .val = 0x15A90DE7 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache118__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache118__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache118__avg_gpu_core_frequency__max,acmgt2__l1_cache118__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2621, 24, NULL,acmgt2__l1_cache118__xve_load_store_cache_atomic_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2622, 32, NULL,acmgt2__l1_cache118__xve_load_store_cache_fence_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache119_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache119";
   query->symbol_name = "L1Cache119";
   query->guid = "7580647f-8c47-4796-a7f6-8f6011aaabe8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x13C905C7 },
         { .reg = 0x00009888, .val = 0x15C90DE7 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache119__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache119__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache119__avg_gpu_core_frequency__max,acmgt2__l1_cache119__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2623, 24, NULL,acmgt2__l1_cache119__xve_load_store_cache_atomic_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2624, 32, NULL,acmgt2__l1_cache119__xve_load_store_cache_fence_message_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache120_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache120";
   query->symbol_name = "L1Cache120";
   query->guid = "b7ae9004-efa6-4851-951c-e901b3228664";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x13E905C7 },
         { .reg = 0x00009888, .val = 0x15E90DE7 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00008002 },
         { .reg = 0x0000D964, .val = 0x0000EFFB },
         { .reg = 0x0000D968, .val = 0x00010002 },
         { .reg = 0x0000D96C, .val = 0x0000DFDF },
         { .reg = 0x0000D970, .val = 0x00020002 },
         { .reg = 0x0000D974, .val = 0x0000BEFF },
         { .reg = 0x0000D978, .val = 0x00040002 },
         { .reg = 0x0000D97C, .val = 0x000077FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache120__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache120__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache120__avg_gpu_core_frequency__max,acmgt2__l1_cache120__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2625, 24, NULL,acmgt2__l1_cache120__xve_load_store_cache_atomic_message_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2626, 32, NULL,acmgt2__l1_cache120__xve_load_store_cache_fence_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache121_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache121";
   query->symbol_name = "L1Cache121";
   query->guid = "77902327-49d2-4174-ba8c-94a796e54c72";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870253 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870004 },
         { .reg = 0x00009888, .val = 0x0E870140 },
         { .reg = 0x00009888, .val = 0x108700C4 },
         { .reg = 0x00009888, .val = 0x12870042 },
         { .reg = 0x00009888, .val = 0x148703C0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890387 },
         { .reg = 0x00009888, .val = 0x08890248 },
         { .reg = 0x00009888, .val = 0x0A8902CA },
         { .reg = 0x00009888, .val = 0x0C89034C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache121__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache121__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache121__avg_gpu_core_frequency__max,acmgt2__l1_cache121__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1859, 24, NULL,acmgt2__l1_cache121__load_store_cache_byte_read_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1858, 32, NULL,acmgt2__l1_cache121__slm_byte_read_bank0_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache122_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache122";
   query->symbol_name = "L1Cache122";
   query->guid = "f4c597eb-8ac7-4138-8775-759d14e2cd40";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A70253 },
         { .reg = 0x00009888, .val = 0x18A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A70004 },
         { .reg = 0x00009888, .val = 0x0EA70140 },
         { .reg = 0x00009888, .val = 0x10A700C4 },
         { .reg = 0x00009888, .val = 0x12A70042 },
         { .reg = 0x00009888, .val = 0x14A703C0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A90054 },
         { .reg = 0x00009888, .val = 0x06A90387 },
         { .reg = 0x00009888, .val = 0x08A90248 },
         { .reg = 0x00009888, .val = 0x0AA902CA },
         { .reg = 0x00009888, .val = 0x0CA9034C },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache122__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache122__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache122__avg_gpu_core_frequency__max,acmgt2__l1_cache122__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1861, 24, NULL,acmgt2__l1_cache122__load_store_cache_byte_read_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1860, 32, NULL,acmgt2__l1_cache122__slm_byte_read_bank0_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache123_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache123";
   query->symbol_name = "L1Cache123";
   query->guid = "e9ee5eb7-90aa-4798-a586-79764c58a6ac";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C70253 },
         { .reg = 0x00009888, .val = 0x18C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C70004 },
         { .reg = 0x00009888, .val = 0x0EC70140 },
         { .reg = 0x00009888, .val = 0x10C700C4 },
         { .reg = 0x00009888, .val = 0x12C70042 },
         { .reg = 0x00009888, .val = 0x14C703C0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C90054 },
         { .reg = 0x00009888, .val = 0x06C90387 },
         { .reg = 0x00009888, .val = 0x08C90248 },
         { .reg = 0x00009888, .val = 0x0AC902CA },
         { .reg = 0x00009888, .val = 0x0CC9034C },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache123__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache123__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache123__avg_gpu_core_frequency__max,acmgt2__l1_cache123__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1863, 24, NULL,acmgt2__l1_cache123__load_store_cache_byte_read_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1862, 32, NULL,acmgt2__l1_cache123__slm_byte_read_bank0_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache124_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache124";
   query->symbol_name = "L1Cache124";
   query->guid = "a5438972-875a-4301-9b15-f4d16d9d106e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E70253 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70004 },
         { .reg = 0x00009888, .val = 0x0EE70140 },
         { .reg = 0x00009888, .val = 0x10E700C4 },
         { .reg = 0x00009888, .val = 0x12E70042 },
         { .reg = 0x00009888, .val = 0x14E703C0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90387 },
         { .reg = 0x00009888, .val = 0x08E90248 },
         { .reg = 0x00009888, .val = 0x0AE902CA },
         { .reg = 0x00009888, .val = 0x0CE9034C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache124__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache124__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache124__avg_gpu_core_frequency__max,acmgt2__l1_cache124__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1865, 24, NULL,acmgt2__l1_cache124__load_store_cache_byte_read_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1864, 32, NULL,acmgt2__l1_cache124__slm_byte_read_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache125_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache125";
   query->symbol_name = "L1Cache125";
   query->guid = "9d7b58e1-a5fa-47fb-a446-1e03556fa59a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A870253 },
         { .reg = 0x00009888, .val = 0x1E890083 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x048700E0 },
         { .reg = 0x00009888, .val = 0x0E870540 },
         { .reg = 0x00009888, .val = 0x108704D4 },
         { .reg = 0x00009888, .val = 0x12870452 },
         { .reg = 0x00009888, .val = 0x148707D0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02893200 },
         { .reg = 0x00009888, .val = 0x06890797 },
         { .reg = 0x00009888, .val = 0x08890658 },
         { .reg = 0x00009888, .val = 0x0A8906DA },
         { .reg = 0x00009888, .val = 0x0C89075C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache125__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache125__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache125__avg_gpu_core_frequency__max,acmgt2__l1_cache125__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1875, 24, NULL,acmgt2__l1_cache125__load_store_cache_byte_read_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1874, 32, NULL,acmgt2__l1_cache125__slm_byte_read_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache126_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache126";
   query->symbol_name = "L1Cache126";
   query->guid = "7ce674af-6177-4d79-8bd4-dff2ef2fab24";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA70253 },
         { .reg = 0x00009888, .val = 0x1EA90083 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A700E0 },
         { .reg = 0x00009888, .val = 0x0EA70540 },
         { .reg = 0x00009888, .val = 0x10A704D4 },
         { .reg = 0x00009888, .val = 0x12A70452 },
         { .reg = 0x00009888, .val = 0x14A707D0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A93200 },
         { .reg = 0x00009888, .val = 0x06A90797 },
         { .reg = 0x00009888, .val = 0x08A90658 },
         { .reg = 0x00009888, .val = 0x0AA906DA },
         { .reg = 0x00009888, .val = 0x0CA9075C },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache126__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache126__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache126__avg_gpu_core_frequency__max,acmgt2__l1_cache126__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1877, 24, NULL,acmgt2__l1_cache126__load_store_cache_byte_read_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1876, 32, NULL,acmgt2__l1_cache126__slm_byte_read_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache127_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache127";
   query->symbol_name = "L1Cache127";
   query->guid = "6dedd9cf-b928-4862-80b5-32a0a17cc238";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC70253 },
         { .reg = 0x00009888, .val = 0x1EC90083 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C700E0 },
         { .reg = 0x00009888, .val = 0x0EC70540 },
         { .reg = 0x00009888, .val = 0x10C704D4 },
         { .reg = 0x00009888, .val = 0x12C70452 },
         { .reg = 0x00009888, .val = 0x14C707D0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C93200 },
         { .reg = 0x00009888, .val = 0x06C90797 },
         { .reg = 0x00009888, .val = 0x08C90658 },
         { .reg = 0x00009888, .val = 0x0AC906DA },
         { .reg = 0x00009888, .val = 0x0CC9075C },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache127__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache127__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache127__avg_gpu_core_frequency__max,acmgt2__l1_cache127__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1879, 24, NULL,acmgt2__l1_cache127__load_store_cache_byte_read_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1878, 32, NULL,acmgt2__l1_cache127__slm_byte_read_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache128_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache128";
   query->symbol_name = "L1Cache128";
   query->guid = "f9352d6f-8b0f-4df0-9e79-1bd75ed6c2b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE70253 },
         { .reg = 0x00009888, .val = 0x1EE90083 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E700E0 },
         { .reg = 0x00009888, .val = 0x0EE70540 },
         { .reg = 0x00009888, .val = 0x10E704D4 },
         { .reg = 0x00009888, .val = 0x12E70452 },
         { .reg = 0x00009888, .val = 0x14E707D0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E93200 },
         { .reg = 0x00009888, .val = 0x06E90797 },
         { .reg = 0x00009888, .val = 0x08E90658 },
         { .reg = 0x00009888, .val = 0x0AE906DA },
         { .reg = 0x00009888, .val = 0x0CE9075C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache128__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache128__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache128__avg_gpu_core_frequency__max,acmgt2__l1_cache128__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1881, 24, NULL,acmgt2__l1_cache128__load_store_cache_byte_read_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1880, 32, NULL,acmgt2__l1_cache128__slm_byte_read_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache129_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache129";
   query->symbol_name = "L1Cache129";
   query->guid = "6c5a3c61-b4cb-48d7-970f-13740c6fd02e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12880253 },
         { .reg = 0x00009888, .val = 0x22890C00 },
         { .reg = 0x00009888, .val = 0x24890004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x00880004 },
         { .reg = 0x00009888, .val = 0x0A880140 },
         { .reg = 0x00009888, .val = 0x0C8800C4 },
         { .reg = 0x00009888, .val = 0x0E880042 },
         { .reg = 0x00009888, .val = 0x108803C0 },
         { .reg = 0x00009888, .val = 0x04890008 },
         { .reg = 0x00009888, .val = 0x06890BA7 },
         { .reg = 0x00009888, .val = 0x08890A68 },
         { .reg = 0x00009888, .val = 0x0A890AEA },
         { .reg = 0x00009888, .val = 0x0C890B6C },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache129__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache129__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache129__avg_gpu_core_frequency__max,acmgt2__l1_cache129__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1891, 24, NULL,acmgt2__l1_cache129__load_store_cache_byte_read_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1890, 32, NULL,acmgt2__l1_cache129__slm_byte_read_bank2_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache130_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache130";
   query->symbol_name = "L1Cache130";
   query->guid = "a0ee28df-2030-4045-b858-d7153e151801";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12A80253 },
         { .reg = 0x00009888, .val = 0x22A90C00 },
         { .reg = 0x00009888, .val = 0x24A90004 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A80004 },
         { .reg = 0x00009888, .val = 0x0AA80140 },
         { .reg = 0x00009888, .val = 0x0CA800C4 },
         { .reg = 0x00009888, .val = 0x0EA80042 },
         { .reg = 0x00009888, .val = 0x10A803C0 },
         { .reg = 0x00009888, .val = 0x04A90008 },
         { .reg = 0x00009888, .val = 0x06A90BA7 },
         { .reg = 0x00009888, .val = 0x08A90A68 },
         { .reg = 0x00009888, .val = 0x0AA90AEA },
         { .reg = 0x00009888, .val = 0x0CA90B6C },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache130__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache130__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache130__avg_gpu_core_frequency__max,acmgt2__l1_cache130__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1893, 24, NULL,acmgt2__l1_cache130__load_store_cache_byte_read_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1892, 32, NULL,acmgt2__l1_cache130__slm_byte_read_bank2_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache131_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache131";
   query->symbol_name = "L1Cache131";
   query->guid = "6a5e1ad7-35fe-4877-a057-c029fdcbd1eb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C80253 },
         { .reg = 0x00009888, .val = 0x22C90C00 },
         { .reg = 0x00009888, .val = 0x24C90004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C80004 },
         { .reg = 0x00009888, .val = 0x0AC80140 },
         { .reg = 0x00009888, .val = 0x0CC800C4 },
         { .reg = 0x00009888, .val = 0x0EC80042 },
         { .reg = 0x00009888, .val = 0x10C803C0 },
         { .reg = 0x00009888, .val = 0x04C90008 },
         { .reg = 0x00009888, .val = 0x06C90BA7 },
         { .reg = 0x00009888, .val = 0x08C90A68 },
         { .reg = 0x00009888, .val = 0x0AC90AEA },
         { .reg = 0x00009888, .val = 0x0CC90B6C },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache131__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache131__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache131__avg_gpu_core_frequency__max,acmgt2__l1_cache131__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1895, 24, NULL,acmgt2__l1_cache131__load_store_cache_byte_read_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1894, 32, NULL,acmgt2__l1_cache131__slm_byte_read_bank2_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache132_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache132";
   query->symbol_name = "L1Cache132";
   query->guid = "8c4700c6-ea20-4b8e-a74a-f42f46f9bac4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12E80253 },
         { .reg = 0x00009888, .val = 0x22E90C00 },
         { .reg = 0x00009888, .val = 0x24E90004 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E80004 },
         { .reg = 0x00009888, .val = 0x0AE80140 },
         { .reg = 0x00009888, .val = 0x0CE800C4 },
         { .reg = 0x00009888, .val = 0x0EE80042 },
         { .reg = 0x00009888, .val = 0x10E803C0 },
         { .reg = 0x00009888, .val = 0x04E90008 },
         { .reg = 0x00009888, .val = 0x06E90BA7 },
         { .reg = 0x00009888, .val = 0x08E90A68 },
         { .reg = 0x00009888, .val = 0x0AE90AEA },
         { .reg = 0x00009888, .val = 0x0CE90B6C },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache132__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache132__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache132__avg_gpu_core_frequency__max,acmgt2__l1_cache132__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1897, 24, NULL,acmgt2__l1_cache132__load_store_cache_byte_read_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1896, 32, NULL,acmgt2__l1_cache132__slm_byte_read_bank2_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache133_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache133";
   query->symbol_name = "L1Cache133";
   query->guid = "e1fd9e53-181f-4a61-95a1-3612f36fdeef";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16880253 },
         { .reg = 0x00009888, .val = 0x28891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x008800E0 },
         { .reg = 0x00009888, .val = 0x0A880540 },
         { .reg = 0x00009888, .val = 0x0C8804D4 },
         { .reg = 0x00009888, .val = 0x0E880452 },
         { .reg = 0x00009888, .val = 0x108807D0 },
         { .reg = 0x00009888, .val = 0x04890200 },
         { .reg = 0x00009888, .val = 0x06890FB7 },
         { .reg = 0x00009888, .val = 0x08890E78 },
         { .reg = 0x00009888, .val = 0x0A890EFA },
         { .reg = 0x00009888, .val = 0x0C890F7C },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache133__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache133__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache133__avg_gpu_core_frequency__max,acmgt2__l1_cache133__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1907, 24, NULL,acmgt2__l1_cache133__load_store_cache_byte_read_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1906, 32, NULL,acmgt2__l1_cache133__slm_byte_read_bank3_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache134_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache134";
   query->symbol_name = "L1Cache134";
   query->guid = "0f1d1caf-29f5-4ae3-8b3b-8a645752df97";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A80253 },
         { .reg = 0x00009888, .val = 0x28A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A800E0 },
         { .reg = 0x00009888, .val = 0x0AA80540 },
         { .reg = 0x00009888, .val = 0x0CA804D4 },
         { .reg = 0x00009888, .val = 0x0EA80452 },
         { .reg = 0x00009888, .val = 0x10A807D0 },
         { .reg = 0x00009888, .val = 0x04A90200 },
         { .reg = 0x00009888, .val = 0x06A90FB7 },
         { .reg = 0x00009888, .val = 0x08A90E78 },
         { .reg = 0x00009888, .val = 0x0AA90EFA },
         { .reg = 0x00009888, .val = 0x0CA90F7C },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache134__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache134__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache134__avg_gpu_core_frequency__max,acmgt2__l1_cache134__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1909, 24, NULL,acmgt2__l1_cache134__load_store_cache_byte_read_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1908, 32, NULL,acmgt2__l1_cache134__slm_byte_read_bank3_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache135_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache135";
   query->symbol_name = "L1Cache135";
   query->guid = "6eed11fb-4013-479b-94d3-9c4e084e82f1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C80253 },
         { .reg = 0x00009888, .val = 0x28C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C800E0 },
         { .reg = 0x00009888, .val = 0x0AC80540 },
         { .reg = 0x00009888, .val = 0x0CC804D4 },
         { .reg = 0x00009888, .val = 0x0EC80452 },
         { .reg = 0x00009888, .val = 0x10C807D0 },
         { .reg = 0x00009888, .val = 0x04C90200 },
         { .reg = 0x00009888, .val = 0x06C90FB7 },
         { .reg = 0x00009888, .val = 0x08C90E78 },
         { .reg = 0x00009888, .val = 0x0AC90EFA },
         { .reg = 0x00009888, .val = 0x0CC90F7C },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache135__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache135__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache135__avg_gpu_core_frequency__max,acmgt2__l1_cache135__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1911, 24, NULL,acmgt2__l1_cache135__load_store_cache_byte_read_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1910, 32, NULL,acmgt2__l1_cache135__slm_byte_read_bank3_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache136_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache136";
   query->symbol_name = "L1Cache136";
   query->guid = "d08bf17e-d459-43d6-83fe-ba8ee4829cdc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E80253 },
         { .reg = 0x00009888, .val = 0x28E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E800E0 },
         { .reg = 0x00009888, .val = 0x0AE80540 },
         { .reg = 0x00009888, .val = 0x0CE804D4 },
         { .reg = 0x00009888, .val = 0x0EE80452 },
         { .reg = 0x00009888, .val = 0x10E807D0 },
         { .reg = 0x00009888, .val = 0x04E90200 },
         { .reg = 0x00009888, .val = 0x06E90FB7 },
         { .reg = 0x00009888, .val = 0x08E90E78 },
         { .reg = 0x00009888, .val = 0x0AE90EFA },
         { .reg = 0x00009888, .val = 0x0CE90F7C },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache136__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache136__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache136__avg_gpu_core_frequency__max,acmgt2__l1_cache136__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1913, 24, NULL,acmgt2__l1_cache136__load_store_cache_byte_read_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1912, 32, NULL,acmgt2__l1_cache136__slm_byte_read_bank3_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache137_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache137";
   query->symbol_name = "L1Cache137";
   query->guid = "b3d01145-903d-49f7-9ed7-45ed893af630";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870012 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x0E870180 },
         { .reg = 0x00009888, .val = 0x10870105 },
         { .reg = 0x00009888, .val = 0x12870083 },
         { .reg = 0x00009888, .val = 0x14870001 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890380 },
         { .reg = 0x00009888, .val = 0x08890081 },
         { .reg = 0x00009888, .val = 0x0A890103 },
         { .reg = 0x00009888, .val = 0x0C890185 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache137__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache137__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache137__avg_gpu_core_frequency__max,acmgt2__l1_cache137__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1923, 24, NULL,acmgt2__l1_cache137__load_store_cache_byte_write_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1922, 32, NULL,acmgt2__l1_cache137__slm_byte_write_bank0_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache138_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache138";
   query->symbol_name = "L1Cache138";
   query->guid = "5abc1aeb-9795-4d41-8872-7d9c6bb83f46";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A70012 },
         { .reg = 0x00009888, .val = 0x18A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x0EA70180 },
         { .reg = 0x00009888, .val = 0x10A70105 },
         { .reg = 0x00009888, .val = 0x12A70083 },
         { .reg = 0x00009888, .val = 0x14A70001 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A90054 },
         { .reg = 0x00009888, .val = 0x06A90380 },
         { .reg = 0x00009888, .val = 0x08A90081 },
         { .reg = 0x00009888, .val = 0x0AA90103 },
         { .reg = 0x00009888, .val = 0x0CA90185 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache138__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache138__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache138__avg_gpu_core_frequency__max,acmgt2__l1_cache138__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1925, 24, NULL,acmgt2__l1_cache138__load_store_cache_byte_write_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1924, 32, NULL,acmgt2__l1_cache138__slm_byte_write_bank0_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache139_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache139";
   query->symbol_name = "L1Cache139";
   query->guid = "231f49f8-1312-4cf8-86a5-ecdeb9070b44";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C70012 },
         { .reg = 0x00009888, .val = 0x18C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x0EC70180 },
         { .reg = 0x00009888, .val = 0x10C70105 },
         { .reg = 0x00009888, .val = 0x12C70083 },
         { .reg = 0x00009888, .val = 0x14C70001 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C90054 },
         { .reg = 0x00009888, .val = 0x06C90380 },
         { .reg = 0x00009888, .val = 0x08C90081 },
         { .reg = 0x00009888, .val = 0x0AC90103 },
         { .reg = 0x00009888, .val = 0x0CC90185 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache139__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache139__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache139__avg_gpu_core_frequency__max,acmgt2__l1_cache139__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1927, 24, NULL,acmgt2__l1_cache139__load_store_cache_byte_write_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1926, 32, NULL,acmgt2__l1_cache139__slm_byte_write_bank0_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache140_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache140";
   query->symbol_name = "L1Cache140";
   query->guid = "231e99e6-e1ad-47b3-ba45-2ac2846202b6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E70012 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x0EE70180 },
         { .reg = 0x00009888, .val = 0x10E70105 },
         { .reg = 0x00009888, .val = 0x12E70083 },
         { .reg = 0x00009888, .val = 0x14E70001 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90380 },
         { .reg = 0x00009888, .val = 0x08E90081 },
         { .reg = 0x00009888, .val = 0x0AE90103 },
         { .reg = 0x00009888, .val = 0x0CE90185 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache140__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache140__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache140__avg_gpu_core_frequency__max,acmgt2__l1_cache140__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1929, 24, NULL,acmgt2__l1_cache140__load_store_cache_byte_write_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1928, 32, NULL,acmgt2__l1_cache140__slm_byte_write_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache141_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache141";
   query->symbol_name = "L1Cache141";
   query->guid = "34ccdeff-29d0-4a12-8d2a-45d6ac39a2bf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A870012 },
         { .reg = 0x00009888, .val = 0x1E890083 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x0E870580 },
         { .reg = 0x00009888, .val = 0x10870515 },
         { .reg = 0x00009888, .val = 0x12870493 },
         { .reg = 0x00009888, .val = 0x14870411 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02893200 },
         { .reg = 0x00009888, .val = 0x06890790 },
         { .reg = 0x00009888, .val = 0x08890491 },
         { .reg = 0x00009888, .val = 0x0A890513 },
         { .reg = 0x00009888, .val = 0x0C890595 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache141__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache141__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache141__avg_gpu_core_frequency__max,acmgt2__l1_cache141__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1939, 24, NULL,acmgt2__l1_cache141__load_store_cache_byte_write_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1938, 32, NULL,acmgt2__l1_cache141__slm_byte_write_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache142_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache142";
   query->symbol_name = "L1Cache142";
   query->guid = "2e9e5b1f-3974-405c-a8a1-aeed17baca42";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA70012 },
         { .reg = 0x00009888, .val = 0x1EA90083 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70580 },
         { .reg = 0x00009888, .val = 0x10A70515 },
         { .reg = 0x00009888, .val = 0x12A70493 },
         { .reg = 0x00009888, .val = 0x14A70411 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A93200 },
         { .reg = 0x00009888, .val = 0x06A90790 },
         { .reg = 0x00009888, .val = 0x08A90491 },
         { .reg = 0x00009888, .val = 0x0AA90513 },
         { .reg = 0x00009888, .val = 0x0CA90595 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache142__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache142__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache142__avg_gpu_core_frequency__max,acmgt2__l1_cache142__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1941, 24, NULL,acmgt2__l1_cache142__load_store_cache_byte_write_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1940, 32, NULL,acmgt2__l1_cache142__slm_byte_write_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache143_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache143";
   query->symbol_name = "L1Cache143";
   query->guid = "7d8da90c-fd7c-482c-afed-007f8323285c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC70012 },
         { .reg = 0x00009888, .val = 0x1EC90083 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0EC70580 },
         { .reg = 0x00009888, .val = 0x10C70515 },
         { .reg = 0x00009888, .val = 0x12C70493 },
         { .reg = 0x00009888, .val = 0x14C70411 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C93200 },
         { .reg = 0x00009888, .val = 0x06C90790 },
         { .reg = 0x00009888, .val = 0x08C90491 },
         { .reg = 0x00009888, .val = 0x0AC90513 },
         { .reg = 0x00009888, .val = 0x0CC90595 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache143__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache143__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache143__avg_gpu_core_frequency__max,acmgt2__l1_cache143__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1943, 24, NULL,acmgt2__l1_cache143__load_store_cache_byte_write_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1942, 32, NULL,acmgt2__l1_cache143__slm_byte_write_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache144_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache144";
   query->symbol_name = "L1Cache144";
   query->guid = "ab19e5f0-333d-4787-a32d-83f2396b1dd9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE70012 },
         { .reg = 0x00009888, .val = 0x1EE90083 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70580 },
         { .reg = 0x00009888, .val = 0x10E70515 },
         { .reg = 0x00009888, .val = 0x12E70493 },
         { .reg = 0x00009888, .val = 0x14E70411 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E93200 },
         { .reg = 0x00009888, .val = 0x06E90790 },
         { .reg = 0x00009888, .val = 0x08E90491 },
         { .reg = 0x00009888, .val = 0x0AE90513 },
         { .reg = 0x00009888, .val = 0x0CE90595 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C60 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030003 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030C63 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache144__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache144__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache144__avg_gpu_core_frequency__max,acmgt2__l1_cache144__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1945, 24, NULL,acmgt2__l1_cache144__load_store_cache_byte_write_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1944, 32, NULL,acmgt2__l1_cache144__slm_byte_write_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache145_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache145";
   query->symbol_name = "L1Cache145";
   query->guid = "49fb217b-1f94-480f-9f7f-80350a8b3f05";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12880012 },
         { .reg = 0x00009888, .val = 0x22890C00 },
         { .reg = 0x00009888, .val = 0x24890004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x0A880180 },
         { .reg = 0x00009888, .val = 0x0C880105 },
         { .reg = 0x00009888, .val = 0x0E880083 },
         { .reg = 0x00009888, .val = 0x10880001 },
         { .reg = 0x00009888, .val = 0x04890008 },
         { .reg = 0x00009888, .val = 0x06890BA0 },
         { .reg = 0x00009888, .val = 0x088908A1 },
         { .reg = 0x00009888, .val = 0x0A890923 },
         { .reg = 0x00009888, .val = 0x0C8909A5 },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache145__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache145__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache145__avg_gpu_core_frequency__max,acmgt2__l1_cache145__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1955, 24, NULL,acmgt2__l1_cache145__load_store_cache_byte_write_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1954, 32, NULL,acmgt2__l1_cache145__slm_byte_write_bank2_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache146_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache146";
   query->symbol_name = "L1Cache146";
   query->guid = "448d0663-b147-4471-8bd3-41a75af71caa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12A80012 },
         { .reg = 0x00009888, .val = 0x22A90C00 },
         { .reg = 0x00009888, .val = 0x24A90004 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x0AA80180 },
         { .reg = 0x00009888, .val = 0x0CA80105 },
         { .reg = 0x00009888, .val = 0x0EA80083 },
         { .reg = 0x00009888, .val = 0x10A80001 },
         { .reg = 0x00009888, .val = 0x04A90008 },
         { .reg = 0x00009888, .val = 0x06A90BA0 },
         { .reg = 0x00009888, .val = 0x08A908A1 },
         { .reg = 0x00009888, .val = 0x0AA90923 },
         { .reg = 0x00009888, .val = 0x0CA909A5 },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache146__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache146__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache146__avg_gpu_core_frequency__max,acmgt2__l1_cache146__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1957, 24, NULL,acmgt2__l1_cache146__load_store_cache_byte_write_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1956, 32, NULL,acmgt2__l1_cache146__slm_byte_write_bank2_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache147_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache147";
   query->symbol_name = "L1Cache147";
   query->guid = "b1dda4b7-b8aa-4db5-8e88-d09b47f092c0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C80012 },
         { .reg = 0x00009888, .val = 0x22C90C00 },
         { .reg = 0x00009888, .val = 0x24C90004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x0AC80180 },
         { .reg = 0x00009888, .val = 0x0CC80105 },
         { .reg = 0x00009888, .val = 0x0EC80083 },
         { .reg = 0x00009888, .val = 0x10C80001 },
         { .reg = 0x00009888, .val = 0x04C90008 },
         { .reg = 0x00009888, .val = 0x06C90BA0 },
         { .reg = 0x00009888, .val = 0x08C908A1 },
         { .reg = 0x00009888, .val = 0x0AC90923 },
         { .reg = 0x00009888, .val = 0x0CC909A5 },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache147__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache147__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache147__avg_gpu_core_frequency__max,acmgt2__l1_cache147__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1959, 24, NULL,acmgt2__l1_cache147__load_store_cache_byte_write_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1958, 32, NULL,acmgt2__l1_cache147__slm_byte_write_bank2_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache148_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache148";
   query->symbol_name = "L1Cache148";
   query->guid = "c2eb3ac8-1dd9-4a95-9723-f4bb3e1f9040";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12E80012 },
         { .reg = 0x00009888, .val = 0x22E90C00 },
         { .reg = 0x00009888, .val = 0x24E90004 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x0AE80180 },
         { .reg = 0x00009888, .val = 0x0CE80105 },
         { .reg = 0x00009888, .val = 0x0EE80083 },
         { .reg = 0x00009888, .val = 0x10E80001 },
         { .reg = 0x00009888, .val = 0x04E90008 },
         { .reg = 0x00009888, .val = 0x06E90BA0 },
         { .reg = 0x00009888, .val = 0x08E908A1 },
         { .reg = 0x00009888, .val = 0x0AE90923 },
         { .reg = 0x00009888, .val = 0x0CE909A5 },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache148__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache148__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache148__avg_gpu_core_frequency__max,acmgt2__l1_cache148__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1961, 24, NULL,acmgt2__l1_cache148__load_store_cache_byte_write_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1960, 32, NULL,acmgt2__l1_cache148__slm_byte_write_bank2_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache149_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache149";
   query->symbol_name = "L1Cache149";
   query->guid = "1fc4fe4d-473a-42c1-a9d4-c68a23c1bc02";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16880012 },
         { .reg = 0x00009888, .val = 0x28891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0A880580 },
         { .reg = 0x00009888, .val = 0x0C880515 },
         { .reg = 0x00009888, .val = 0x0E880493 },
         { .reg = 0x00009888, .val = 0x10880411 },
         { .reg = 0x00009888, .val = 0x04890200 },
         { .reg = 0x00009888, .val = 0x06890FB0 },
         { .reg = 0x00009888, .val = 0x08890CB1 },
         { .reg = 0x00009888, .val = 0x0A890D33 },
         { .reg = 0x00009888, .val = 0x0C890DB5 },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache149__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache149__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache149__avg_gpu_core_frequency__max,acmgt2__l1_cache149__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1971, 24, NULL,acmgt2__l1_cache149__load_store_cache_byte_write_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1970, 32, NULL,acmgt2__l1_cache149__slm_byte_write_bank3_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache150_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache150";
   query->symbol_name = "L1Cache150";
   query->guid = "cb3742b7-e01b-4759-a5cf-a473ffdc1bae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A80012 },
         { .reg = 0x00009888, .val = 0x28A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80580 },
         { .reg = 0x00009888, .val = 0x0CA80515 },
         { .reg = 0x00009888, .val = 0x0EA80493 },
         { .reg = 0x00009888, .val = 0x10A80411 },
         { .reg = 0x00009888, .val = 0x04A90200 },
         { .reg = 0x00009888, .val = 0x06A90FB0 },
         { .reg = 0x00009888, .val = 0x08A90CB1 },
         { .reg = 0x00009888, .val = 0x0AA90D33 },
         { .reg = 0x00009888, .val = 0x0CA90DB5 },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache150__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache150__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache150__avg_gpu_core_frequency__max,acmgt2__l1_cache150__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1973, 24, NULL,acmgt2__l1_cache150__load_store_cache_byte_write_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1972, 32, NULL,acmgt2__l1_cache150__slm_byte_write_bank3_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache151_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache151";
   query->symbol_name = "L1Cache151";
   query->guid = "e116bb6e-4a74-4d70-91ef-30162e83fa72";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C80012 },
         { .reg = 0x00009888, .val = 0x28C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x0AC80580 },
         { .reg = 0x00009888, .val = 0x0CC80515 },
         { .reg = 0x00009888, .val = 0x0EC80493 },
         { .reg = 0x00009888, .val = 0x10C80411 },
         { .reg = 0x00009888, .val = 0x04C90200 },
         { .reg = 0x00009888, .val = 0x06C90FB0 },
         { .reg = 0x00009888, .val = 0x08C90CB1 },
         { .reg = 0x00009888, .val = 0x0AC90D33 },
         { .reg = 0x00009888, .val = 0x0CC90DB5 },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache151__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache151__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache151__avg_gpu_core_frequency__max,acmgt2__l1_cache151__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1975, 24, NULL,acmgt2__l1_cache151__load_store_cache_byte_write_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1974, 32, NULL,acmgt2__l1_cache151__slm_byte_write_bank3_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache152_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "L1Cache152";
   query->symbol_name = "L1Cache152";
   query->guid = "d2731321-319c-4e1e-8cc2-70832ed45e85";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E80012 },
         { .reg = 0x00009888, .val = 0x28E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0AE80580 },
         { .reg = 0x00009888, .val = 0x0CE80515 },
         { .reg = 0x00009888, .val = 0x0EE80493 },
         { .reg = 0x00009888, .val = 0x10E80411 },
         { .reg = 0x00009888, .val = 0x04E90200 },
         { .reg = 0x00009888, .val = 0x06E90FB0 },
         { .reg = 0x00009888, .val = 0x08E90CB1 },
         { .reg = 0x00009888, .val = 0x0AE90D33 },
         { .reg = 0x00009888, .val = 0x0CE90DB5 },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache152__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache152__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache152__avg_gpu_core_frequency__max,acmgt2__l1_cache152__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1977, 24, NULL,acmgt2__l1_cache152__load_store_cache_byte_write_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1976, 32, NULL,acmgt2__l1_cache152__slm_byte_write_bank3_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache153_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache153";
   query->symbol_name = "L1Cache153";
   query->guid = "9b3e9938-36a7-45fa-a855-a1664cca7e7b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache153__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache153__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache153__avg_gpu_core_frequency__max,acmgt2__l1_cache153__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1752, 24, NULL,acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1753, 32, NULL,acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1754, 40, NULL,acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1755, 48, NULL,acmgt2__l1_cache153__load_store_cache_number_of_bank_access_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache154_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache154";
   query->symbol_name = "L1Cache154";
   query->guid = "6588bbbc-22b5-4387-8263-2de455505fe5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache154__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache154__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache154__avg_gpu_core_frequency__max,acmgt2__l1_cache154__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1756, 24, NULL,acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1757, 32, NULL,acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1758, 40, NULL,acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1759, 48, NULL,acmgt2__l1_cache154__load_store_cache_number_of_bank_access_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache155_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache155";
   query->symbol_name = "L1Cache155";
   query->guid = "916d2db4-8950-4577-b17a-91bae4439648";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache155__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache155__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache155__avg_gpu_core_frequency__max,acmgt2__l1_cache155__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2627, 24, NULL,acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2628, 32, NULL,acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2629, 40, NULL,acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2630, 48, NULL,acmgt2__l1_cache155__load_store_cache_number_of_bank_access_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l1_cache156_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "L1Cache156";
   query->symbol_name = "L1Cache156";
   query->guid = "60481905-7439-44f1-81b6-ef356e002f74";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031CEA },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030D46 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030003 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030804 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34031842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l1_cache156__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l1_cache156__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l1_cache156__avg_gpu_core_frequency__max,acmgt2__l1_cache156__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2631, 24, NULL,acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2632, 32, NULL,acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2633, 40, NULL,acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2634, 48, NULL,acmgt2__l1_cache156__load_store_cache_number_of_bank_access_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache1";
   query->symbol_name = "L3Cache1";
   query->guid = "e735a53a-442a-43e6-b5be-d1c89c017bf2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache1__avg_gpu_core_frequency__max,acmgt2__l3_cache1__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 939, 24, percentage_max_float,acmgt2__l3_cache1__l3_input_available_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 940, 28, percentage_max_float,acmgt2__l3_cache1__l3_input_available_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 941, 32, percentage_max_float,acmgt2__l3_cache1__l3_input_available_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 942, 36, percentage_max_float,acmgt2__l3_cache1__l3_input_available_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 943, 40, percentage_max_float,acmgt2__l3_cache1__l3_input_available_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 944, 44, percentage_max_float,acmgt2__l3_cache1__l3_input_available_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 945, 48, percentage_max_float,acmgt2__l3_cache1__l3_input_available_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 946, 52, percentage_max_float,acmgt2__l3_cache1__l3_input_available_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 947, 56, percentage_max_float,acmgt2__l3_cache1__l3_output_ready_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 948, 60, percentage_max_float,acmgt2__l3_cache1__l3_output_ready_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 949, 64, percentage_max_float,acmgt2__l3_cache1__l3_output_ready_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 950, 68, percentage_max_float,acmgt2__l3_cache1__l3_output_ready_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 951, 72, percentage_max_float,acmgt2__l3_cache1__l3_output_ready_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 952, 76, percentage_max_float,acmgt2__l3_cache1__l3_output_ready_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 953, 80, percentage_max_float,acmgt2__l3_cache1__l3_output_ready_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 954, 84, percentage_max_float,acmgt2__l3_cache1__l3_output_ready_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache2";
   query->symbol_name = "L3Cache2";
   query->guid = "fd307172-3c1e-432f-8347-014d0a93e2be";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache2__avg_gpu_core_frequency__max,acmgt2__l3_cache2__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2635, 24, percentage_max_float,acmgt2__l3_cache2__l3_input_available_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2636, 28, percentage_max_float,acmgt2__l3_cache2__l3_input_available_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2637, 32, percentage_max_float,acmgt2__l3_cache2__l3_input_available_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2638, 36, percentage_max_float,acmgt2__l3_cache2__l3_input_available_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2639, 40, percentage_max_float,acmgt2__l3_cache2__l3_input_available_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2640, 44, percentage_max_float,acmgt2__l3_cache2__l3_input_available_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2641, 48, percentage_max_float,acmgt2__l3_cache2__l3_input_available_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2642, 52, percentage_max_float,acmgt2__l3_cache2__l3_input_available_l3_bank15__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2643, 56, percentage_max_float,acmgt2__l3_cache2__l3_output_ready_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2644, 60, percentage_max_float,acmgt2__l3_cache2__l3_output_ready_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2645, 64, percentage_max_float,acmgt2__l3_cache2__l3_output_ready_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2646, 68, percentage_max_float,acmgt2__l3_cache2__l3_output_ready_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2647, 72, percentage_max_float,acmgt2__l3_cache2__l3_output_ready_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2648, 76, percentage_max_float,acmgt2__l3_cache2__l3_output_ready_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2649, 80, percentage_max_float,acmgt2__l3_cache2__l3_output_ready_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2650, 84, percentage_max_float,acmgt2__l3_cache2__l3_output_ready_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache3";
   query->symbol_name = "L3Cache3";
   query->guid = "44447e1a-90df-452e-b701-e38c034a4eca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x0B0B6005 },
         { .reg = 0x00009888, .val = 0x092B1005 },
         { .reg = 0x00009888, .val = 0x0B2B6000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x0B4B6000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x0B6B6000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x0B0C6140 },
         { .reg = 0x00009888, .val = 0x092C1140 },
         { .reg = 0x00009888, .val = 0x0B2C6000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x0B4C6000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x0B6C6000 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x112B000D },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x0F4B000D },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x0D6B000D },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x130C0340 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x112C0340 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x0F4C0340 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x0D6C0340 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache3__avg_gpu_core_frequency__max,acmgt2__l3_cache3__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 827, 24, NULL,acmgt2__l3_cache3__l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 828, 32, NULL,acmgt2__l3_cache3__l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 829, 40, NULL,acmgt2__l3_cache3__l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 830, 48, NULL,acmgt2__l3_cache3__l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 831, 56, NULL,acmgt2__l3_cache3__l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 832, 64, NULL,acmgt2__l3_cache3__l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 833, 72, NULL,acmgt2__l3_cache3__l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 834, 80, NULL,acmgt2__l3_cache3__l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 835, 88, NULL,acmgt2__l3_cache3__l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 836, 96, NULL,acmgt2__l3_cache3__l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 837, 104, NULL,acmgt2__l3_cache3__l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 838, 112, NULL,acmgt2__l3_cache3__l3_write_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 839, 120, NULL,acmgt2__l3_cache3__l3_write_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 840, 128, NULL,acmgt2__l3_cache3__l3_write_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 841, 136, NULL,acmgt2__l3_cache3__l3_write_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 842, 144, NULL,acmgt2__l3_cache3__l3_write_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache4";
   query->symbol_name = "L3Cache4";
   query->guid = "e37c49ce-822e-43c5-9875-6945c962305e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x0B0B6005 },
         { .reg = 0x00009888, .val = 0x092B1005 },
         { .reg = 0x00009888, .val = 0x0B2B6000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x0B4B6000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x0B6B6000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x0B0C6140 },
         { .reg = 0x00009888, .val = 0x092C1140 },
         { .reg = 0x00009888, .val = 0x0B2C6000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x0B4C6000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x0B6C6000 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x112B000D },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x0F4B000D },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x0D6B000D },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x130C0340 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x112C0340 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x0F4C0340 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x0D6C0340 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache4__avg_gpu_core_frequency__max,acmgt2__l3_cache4__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2651, 24, NULL,acmgt2__l3_cache4__l3_read_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2652, 32, NULL,acmgt2__l3_cache4__l3_read_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2653, 40, NULL,acmgt2__l3_cache4__l3_read_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2654, 48, NULL,acmgt2__l3_cache4__l3_read_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2655, 56, NULL,acmgt2__l3_cache4__l3_read_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2656, 64, NULL,acmgt2__l3_cache4__l3_read_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2657, 72, NULL,acmgt2__l3_cache4__l3_read_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2658, 80, NULL,acmgt2__l3_cache4__l3_read_l3_bank15__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2659, 88, NULL,acmgt2__l3_cache4__l3_write_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2660, 96, NULL,acmgt2__l3_cache4__l3_write_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2661, 104, NULL,acmgt2__l3_cache4__l3_write_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2662, 112, NULL,acmgt2__l3_cache4__l3_write_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2663, 120, NULL,acmgt2__l3_cache4__l3_write_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2664, 128, NULL,acmgt2__l3_cache4__l3_write_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2665, 136, NULL,acmgt2__l3_cache4__l3_write_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2666, 144, NULL,acmgt2__l3_cache4__l3_write_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache5";
   query->symbol_name = "L3Cache5";
   query->guid = "45bb2f55-4b48-4d0d-882a-abfbac133ca4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2001 },
         { .reg = 0x00009888, .val = 0x114B2000 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2040 },
         { .reg = 0x00009888, .val = 0x114C2000 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0002 },
         { .reg = 0x00009888, .val = 0x130B0001 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0001 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0001 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0080 },
         { .reg = 0x00009888, .val = 0x130C0040 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0080 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0080 },
         { .reg = 0x00009888, .val = 0x0F4C0040 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0080 },
         { .reg = 0x00009888, .val = 0x0D6C0040 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache5__avg_gpu_core_frequency__max,acmgt2__l3_cache5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 859, 24, NULL,acmgt2__l3_cache5__l3_hit_l3_bank0__read);

      intel_perf_query_add_counter_uint64(query, 860, 32, NULL,acmgt2__l3_cache5__l3_hit_l3_bank1__read);

      intel_perf_query_add_counter_uint64(query, 861, 40, NULL,acmgt2__l3_cache5__l3_hit_l3_bank2__read);

      intel_perf_query_add_counter_uint64(query, 862, 48, NULL,acmgt2__l3_cache5__l3_hit_l3_bank3__read);

      intel_perf_query_add_counter_uint64(query, 863, 56, NULL,acmgt2__l3_cache5__l3_hit_l3_bank4__read);

      intel_perf_query_add_counter_uint64(query, 864, 64, NULL,acmgt2__l3_cache5__l3_hit_l3_bank5__read);

      intel_perf_query_add_counter_uint64(query, 865, 72, NULL,acmgt2__l3_cache5__l3_hit_l3_bank6__read);

      intel_perf_query_add_counter_uint64(query, 866, 80, NULL,acmgt2__l3_cache5__l3_hit_l3_bank7__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1774, 88, NULL,acmgt2__l3_cache5__l3_miss_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1775, 96, NULL,acmgt2__l3_cache5__l3_miss_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1776, 104, NULL,acmgt2__l3_cache5__l3_miss_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1777, 112, NULL,acmgt2__l3_cache5__l3_miss_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1778, 120, NULL,acmgt2__l3_cache5__l3_miss_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1779, 128, NULL,acmgt2__l3_cache5__l3_miss_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1780, 136, NULL,acmgt2__l3_cache5__l3_miss_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1781, 144, NULL,acmgt2__l3_cache5__l3_miss_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache6";
   query->symbol_name = "L3Cache6";
   query->guid = "215b0c4c-5977-4f01-a4de-3c8f654e3573";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2001 },
         { .reg = 0x00009888, .val = 0x114B2000 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2040 },
         { .reg = 0x00009888, .val = 0x114C2000 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0002 },
         { .reg = 0x00009888, .val = 0x130B0001 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0001 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0001 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0080 },
         { .reg = 0x00009888, .val = 0x130C0040 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0080 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0080 },
         { .reg = 0x00009888, .val = 0x0F4C0040 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0080 },
         { .reg = 0x00009888, .val = 0x0D6C0040 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache6__avg_gpu_core_frequency__max,acmgt2__l3_cache6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2667, 24, NULL,acmgt2__l3_cache6__l3_hit_l3_bank8__read);

      intel_perf_query_add_counter_uint64(query, 2668, 32, NULL,acmgt2__l3_cache6__l3_hit_l3_bank9__read);

      intel_perf_query_add_counter_uint64(query, 2669, 40, NULL,acmgt2__l3_cache6__l3_hit_l3_bank10__read);

      intel_perf_query_add_counter_uint64(query, 2670, 48, NULL,acmgt2__l3_cache6__l3_hit_l3_bank11__read);

      intel_perf_query_add_counter_uint64(query, 2671, 56, NULL,acmgt2__l3_cache6__l3_hit_l3_bank12__read);

      intel_perf_query_add_counter_uint64(query, 2672, 64, NULL,acmgt2__l3_cache6__l3_hit_l3_bank13__read);

      intel_perf_query_add_counter_uint64(query, 2673, 72, NULL,acmgt2__l3_cache6__l3_hit_l3_bank14__read);

      intel_perf_query_add_counter_uint64(query, 2674, 80, NULL,acmgt2__l3_cache6__l3_hit_l3_bank15__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2675, 88, NULL,acmgt2__l3_cache6__l3_miss_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2676, 96, NULL,acmgt2__l3_cache6__l3_miss_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2677, 104, NULL,acmgt2__l3_cache6__l3_miss_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2678, 112, NULL,acmgt2__l3_cache6__l3_miss_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2679, 120, NULL,acmgt2__l3_cache6__l3_miss_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2680, 128, NULL,acmgt2__l3_cache6__l3_miss_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2681, 136, NULL,acmgt2__l3_cache6__l3_miss_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2682, 144, NULL,acmgt2__l3_cache6__l3_miss_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache7";
   query->symbol_name = "L3Cache7";
   query->guid = "47f3839a-9fcb-4bc5-85ed-7096d712cda6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0003 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C00C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0003 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0003 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0003 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C00C0 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C00C0 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C00C0 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache7__avg_gpu_core_frequency__max,acmgt2__l3_cache7__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 843, 24, NULL,acmgt2__l3_cache7__dataport_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 844, 32, NULL,acmgt2__l3_cache7__dataport_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 845, 40, NULL,acmgt2__l3_cache7__dataport_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 846, 48, NULL,acmgt2__l3_cache7__dataport_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 847, 56, NULL,acmgt2__l3_cache7__dataport_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 848, 64, NULL,acmgt2__l3_cache7__dataport_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 849, 72, NULL,acmgt2__l3_cache7__dataport_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 850, 80, NULL,acmgt2__l3_cache7__dataport_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 851, 88, NULL,acmgt2__l3_cache7__dataport_l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 852, 96, NULL,acmgt2__l3_cache7__dataport_l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 853, 104, NULL,acmgt2__l3_cache7__dataport_l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 854, 112, NULL,acmgt2__l3_cache7__dataport_l3_write_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 855, 120, NULL,acmgt2__l3_cache7__dataport_l3_write_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 856, 128, NULL,acmgt2__l3_cache7__dataport_l3_write_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 857, 136, NULL,acmgt2__l3_cache7__dataport_l3_write_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 858, 144, NULL,acmgt2__l3_cache7__dataport_l3_write_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache8";
   query->symbol_name = "L3Cache8";
   query->guid = "84f32171-9963-413e-8f14-163a3e258342";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0003 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C00C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0003 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0003 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0003 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C00C0 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C00C0 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C00C0 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache8__avg_gpu_core_frequency__max,acmgt2__l3_cache8__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2683, 24, NULL,acmgt2__l3_cache8__dataport_l3_read_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2684, 32, NULL,acmgt2__l3_cache8__dataport_l3_read_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2685, 40, NULL,acmgt2__l3_cache8__dataport_l3_read_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2686, 48, NULL,acmgt2__l3_cache8__dataport_l3_read_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2687, 56, NULL,acmgt2__l3_cache8__dataport_l3_read_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2688, 64, NULL,acmgt2__l3_cache8__dataport_l3_read_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2689, 72, NULL,acmgt2__l3_cache8__dataport_l3_read_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2690, 80, NULL,acmgt2__l3_cache8__dataport_l3_read_l3_bank15__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2691, 88, NULL,acmgt2__l3_cache8__dataport_l3_write_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2692, 96, NULL,acmgt2__l3_cache8__dataport_l3_write_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2693, 104, NULL,acmgt2__l3_cache8__dataport_l3_write_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2694, 112, NULL,acmgt2__l3_cache8__dataport_l3_write_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2695, 120, NULL,acmgt2__l3_cache8__dataport_l3_write_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2696, 128, NULL,acmgt2__l3_cache8__dataport_l3_write_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2697, 136, NULL,acmgt2__l3_cache8__dataport_l3_write_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2698, 144, NULL,acmgt2__l3_cache8__dataport_l3_write_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache9";
   query->symbol_name = "L3Cache9";
   query->guid = "9e9237e0-0d36-4e0d-8413-1109670a1f0f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x092B0002 },
         { .reg = 0x00009888, .val = 0x112B000F },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x092C0080 },
         { .reg = 0x00009888, .val = 0x112C03C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0026 },
         { .reg = 0x00009888, .val = 0x0B0B0002 },
         { .reg = 0x00009888, .val = 0x130B000F },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0026 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0026 },
         { .reg = 0x00009888, .val = 0x074B0002 },
         { .reg = 0x00009888, .val = 0x0F4B000F },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0026 },
         { .reg = 0x00009888, .val = 0x056B0002 },
         { .reg = 0x00009888, .val = 0x0D6B000F },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0026 },
         { .reg = 0x00009888, .val = 0x0B0C0080 },
         { .reg = 0x00009888, .val = 0x130C03C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0026 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0026 },
         { .reg = 0x00009888, .val = 0x074C0080 },
         { .reg = 0x00009888, .val = 0x0F4C03C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0026 },
         { .reg = 0x00009888, .val = 0x056C0080 },
         { .reg = 0x00009888, .val = 0x0D6C03C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache9__avg_gpu_core_frequency__max,acmgt2__l3_cache9__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 883, 24, NULL,acmgt2__l3_cache9__icache_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 884, 32, NULL,acmgt2__l3_cache9__icache_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 885, 40, NULL,acmgt2__l3_cache9__icache_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 886, 48, NULL,acmgt2__l3_cache9__icache_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 887, 56, NULL,acmgt2__l3_cache9__icache_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 888, 64, NULL,acmgt2__l3_cache9__icache_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 889, 72, NULL,acmgt2__l3_cache9__icache_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 890, 80, NULL,acmgt2__l3_cache9__icache_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 891, 88, NULL,acmgt2__l3_cache9__icache_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 892, 96, NULL,acmgt2__l3_cache9__icache_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 893, 104, NULL,acmgt2__l3_cache9__icache_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 894, 112, NULL,acmgt2__l3_cache9__icache_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 895, 120, NULL,acmgt2__l3_cache9__icache_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 896, 128, NULL,acmgt2__l3_cache9__icache_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 897, 136, NULL,acmgt2__l3_cache9__icache_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 898, 144, NULL,acmgt2__l3_cache9__icache_l3_hit_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache10";
   query->symbol_name = "L3Cache10";
   query->guid = "156b77b5-f696-42be-ad63-13a8372d5d51";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x092B0002 },
         { .reg = 0x00009888, .val = 0x112B000F },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x092C0080 },
         { .reg = 0x00009888, .val = 0x112C03C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0026 },
         { .reg = 0x00009888, .val = 0x0B0B0002 },
         { .reg = 0x00009888, .val = 0x130B000F },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0026 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0026 },
         { .reg = 0x00009888, .val = 0x074B0002 },
         { .reg = 0x00009888, .val = 0x0F4B000F },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0026 },
         { .reg = 0x00009888, .val = 0x056B0002 },
         { .reg = 0x00009888, .val = 0x0D6B000F },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0026 },
         { .reg = 0x00009888, .val = 0x0B0C0080 },
         { .reg = 0x00009888, .val = 0x130C03C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0026 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0026 },
         { .reg = 0x00009888, .val = 0x074C0080 },
         { .reg = 0x00009888, .val = 0x0F4C03C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0026 },
         { .reg = 0x00009888, .val = 0x056C0080 },
         { .reg = 0x00009888, .val = 0x0D6C03C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache10__avg_gpu_core_frequency__max,acmgt2__l3_cache10__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2699, 24, NULL,acmgt2__l3_cache10__icache_l3_read_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2700, 32, NULL,acmgt2__l3_cache10__icache_l3_read_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2701, 40, NULL,acmgt2__l3_cache10__icache_l3_read_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2702, 48, NULL,acmgt2__l3_cache10__icache_l3_read_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2703, 56, NULL,acmgt2__l3_cache10__icache_l3_read_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2704, 64, NULL,acmgt2__l3_cache10__icache_l3_read_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2705, 72, NULL,acmgt2__l3_cache10__icache_l3_read_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2706, 80, NULL,acmgt2__l3_cache10__icache_l3_read_l3_bank15__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2707, 88, NULL,acmgt2__l3_cache10__icache_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2708, 96, NULL,acmgt2__l3_cache10__icache_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2709, 104, NULL,acmgt2__l3_cache10__icache_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2710, 112, NULL,acmgt2__l3_cache10__icache_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2711, 120, NULL,acmgt2__l3_cache10__icache_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2712, 128, NULL,acmgt2__l3_cache10__icache_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2713, 136, NULL,acmgt2__l3_cache10__icache_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2714, 144, NULL,acmgt2__l3_cache10__icache_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L3Cache11";
   query->symbol_name = "L3Cache11";
   query->guid = "fd98f311-2512-48f3-b0fe-464f34238811";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1001 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x0B2B0000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x0B2C0042 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x070B0080 },
         { .reg = 0x00009888, .val = 0x130B0008 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x0D2B0080 },
         { .reg = 0x00009888, .val = 0x0F2B0001 },
         { .reg = 0x00009888, .val = 0x112B0008 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x050C0042 },
         { .reg = 0x00009888, .val = 0x070C0000 },
         { .reg = 0x00009888, .val = 0x130C0200 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x0D2C0000 },
         { .reg = 0x00009888, .val = 0x112C0200 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x00050A80 },
         { .reg = 0x00009888, .val = 0x02052000 },
         { .reg = 0x00009888, .val = 0x0006A015 },
         { .reg = 0x00009888, .val = 0x02064802 },
         { .reg = 0x00009888, .val = 0x0007A1C7 },
         { .reg = 0x00009888, .val = 0x00085A95 },
         { .reg = 0x00009888, .val = 0x020867FD },
         { .reg = 0x00009888, .val = 0x0009A1C7 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032520 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030C06 },
         { .reg = 0x00009888, .val = 0x3A030060 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031809 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache11__avg_gpu_core_frequency__max,acmgt2__l3_cache11__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 963, 24, percentage_max_float,acmgt2__l3_cache11__l3_busy_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 964, 28, percentage_max_float,acmgt2__l3_cache11__l3_busy_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 965, 32, percentage_max_float,acmgt2__l3_cache11__l3_busy_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 966, 36, percentage_max_float,acmgt2__l3_cache11__l3_busy_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 971, 40, percentage_max_float,acmgt2__l3_cache11__l3_stall_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 972, 44, percentage_max_float,acmgt2__l3_cache11__l3_stall_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 973, 48, percentage_max_float,acmgt2__l3_cache11__l3_stall_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 974, 52, percentage_max_float,acmgt2__l3_cache11__l3_stall_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L3Cache12";
   query->symbol_name = "L3Cache12";
   query->guid = "efee1ff5-333a-49f5-8093-7b7a6196cfce";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x094B1001 },
         { .reg = 0x00009888, .val = 0x0B4B0000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x0B6B0000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x0B4C0000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x0B6C0042 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0080 },
         { .reg = 0x00009888, .val = 0x134B0008 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x0D6B0080 },
         { .reg = 0x00009888, .val = 0x0F6B0001 },
         { .reg = 0x00009888, .val = 0x116B0008 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x054C0042 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x134C0200 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x116C0200 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x0003A015 },
         { .reg = 0x00009888, .val = 0x02034802 },
         { .reg = 0x00009888, .val = 0x0004A56A },
         { .reg = 0x00009888, .val = 0x02049BFE },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031080 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030404 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache12__avg_gpu_core_frequency__max,acmgt2__l3_cache12__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 967, 24, percentage_max_float,acmgt2__l3_cache12__l3_busy_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 968, 28, percentage_max_float,acmgt2__l3_cache12__l3_busy_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 969, 32, percentage_max_float,acmgt2__l3_cache12__l3_busy_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 970, 36, percentage_max_float,acmgt2__l3_cache12__l3_busy_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 975, 40, percentage_max_float,acmgt2__l3_cache12__l3_stall_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 976, 44, percentage_max_float,acmgt2__l3_cache12__l3_stall_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 977, 48, percentage_max_float,acmgt2__l3_cache12__l3_stall_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 978, 52, percentage_max_float,acmgt2__l3_cache12__l3_stall_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L3Cache13";
   query->symbol_name = "L3Cache13";
   query->guid = "a979c83d-ccd1-4aea-8a3f-966aa9e5a4aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1001 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x0B2B0000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x0B2C0042 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x070B0080 },
         { .reg = 0x00009888, .val = 0x130B0008 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x0D2B0080 },
         { .reg = 0x00009888, .val = 0x0F2B0001 },
         { .reg = 0x00009888, .val = 0x112B0008 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x050C0042 },
         { .reg = 0x00009888, .val = 0x070C0000 },
         { .reg = 0x00009888, .val = 0x130C0200 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x0D2C0000 },
         { .reg = 0x00009888, .val = 0x112C0200 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x00050A80 },
         { .reg = 0x00009888, .val = 0x02052000 },
         { .reg = 0x00009888, .val = 0x0006A015 },
         { .reg = 0x00009888, .val = 0x02064802 },
         { .reg = 0x00009888, .val = 0x0007A1C7 },
         { .reg = 0x00009888, .val = 0x00085A95 },
         { .reg = 0x00009888, .val = 0x020867FD },
         { .reg = 0x00009888, .val = 0x0009A1C7 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032520 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030C06 },
         { .reg = 0x00009888, .val = 0x3A030060 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031809 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache13__avg_gpu_core_frequency__max,acmgt2__l3_cache13__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2715, 24, percentage_max_float,acmgt2__l3_cache13__l3_busy_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2716, 28, percentage_max_float,acmgt2__l3_cache13__l3_busy_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2717, 32, percentage_max_float,acmgt2__l3_cache13__l3_busy_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2718, 36, percentage_max_float,acmgt2__l3_cache13__l3_busy_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2719, 40, percentage_max_float,acmgt2__l3_cache13__l3_stall_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2720, 44, percentage_max_float,acmgt2__l3_cache13__l3_stall_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2721, 48, percentage_max_float,acmgt2__l3_cache13__l3_stall_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2722, 52, percentage_max_float,acmgt2__l3_cache13__l3_stall_l3_bank11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L3Cache14";
   query->symbol_name = "L3Cache14";
   query->guid = "6c0c13ac-31ac-4875-a5bd-a2a0ee46dd29";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x094B1001 },
         { .reg = 0x00009888, .val = 0x0B4B0000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x0B6B0000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x0B4C0000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x0B6C0042 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0080 },
         { .reg = 0x00009888, .val = 0x134B0008 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x0D6B0080 },
         { .reg = 0x00009888, .val = 0x0F6B0001 },
         { .reg = 0x00009888, .val = 0x116B0008 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x054C0042 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x134C0200 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x116C0200 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x0003A015 },
         { .reg = 0x00009888, .val = 0x02034802 },
         { .reg = 0x00009888, .val = 0x0004A56A },
         { .reg = 0x00009888, .val = 0x02049BFE },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32031080 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030404 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache14__avg_gpu_core_frequency__max,acmgt2__l3_cache14__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2723, 24, percentage_max_float,acmgt2__l3_cache14__l3_busy_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2724, 28, percentage_max_float,acmgt2__l3_cache14__l3_busy_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2725, 32, percentage_max_float,acmgt2__l3_cache14__l3_busy_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2726, 36, percentage_max_float,acmgt2__l3_cache14__l3_busy_l3_bank15__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2727, 40, percentage_max_float,acmgt2__l3_cache14__l3_stall_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2728, 44, percentage_max_float,acmgt2__l3_cache14__l3_stall_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2729, 48, percentage_max_float,acmgt2__l3_cache14__l3_stall_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2730, 52, percentage_max_float,acmgt2__l3_cache14__l3_stall_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache15";
   query->symbol_name = "L3Cache15";
   query->guid = "7c562d8e-e5ab-44c4-8d2d-76026e6d9ac1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x112B000E },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x112C0380 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0026 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x130B000E },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0026 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0026 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x0F4B000E },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0026 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x0D6B000E },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0026 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x130C0380 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0026 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0026 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x0F4C0380 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0026 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x0D6C0380 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache15__avg_gpu_core_frequency__max,acmgt2__l3_cache15__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 867, 24, NULL,acmgt2__l3_cache15__sampler_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 868, 32, NULL,acmgt2__l3_cache15__sampler_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 869, 40, NULL,acmgt2__l3_cache15__sampler_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 870, 48, NULL,acmgt2__l3_cache15__sampler_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 871, 56, NULL,acmgt2__l3_cache15__sampler_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 872, 64, NULL,acmgt2__l3_cache15__sampler_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 873, 72, NULL,acmgt2__l3_cache15__sampler_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 874, 80, NULL,acmgt2__l3_cache15__sampler_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 875, 88, NULL,acmgt2__l3_cache15__sampler_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 876, 96, NULL,acmgt2__l3_cache15__sampler_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 877, 104, NULL,acmgt2__l3_cache15__sampler_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 878, 112, NULL,acmgt2__l3_cache15__sampler_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 879, 120, NULL,acmgt2__l3_cache15__sampler_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 880, 128, NULL,acmgt2__l3_cache15__sampler_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 881, 136, NULL,acmgt2__l3_cache15__sampler_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 882, 144, NULL,acmgt2__l3_cache15__sampler_l3_hit_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache16";
   query->symbol_name = "L3Cache16";
   query->guid = "7eb61dda-7e60-40ed-aaae-603533cf941f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x112B000E },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x112C0380 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0026 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x130B000E },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0026 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0026 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x0F4B000E },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0026 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x0D6B000E },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0026 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x130C0380 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0026 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0026 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x0F4C0380 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0026 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x0D6C0380 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030024 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030401 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030040 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031C2A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache16__avg_gpu_core_frequency__max,acmgt2__l3_cache16__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2731, 24, NULL,acmgt2__l3_cache16__sampler_l3_read_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2732, 32, NULL,acmgt2__l3_cache16__sampler_l3_read_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2733, 40, NULL,acmgt2__l3_cache16__sampler_l3_read_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2734, 48, NULL,acmgt2__l3_cache16__sampler_l3_read_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2735, 56, NULL,acmgt2__l3_cache16__sampler_l3_read_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2736, 64, NULL,acmgt2__l3_cache16__sampler_l3_read_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2737, 72, NULL,acmgt2__l3_cache16__sampler_l3_read_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2738, 80, NULL,acmgt2__l3_cache16__sampler_l3_read_l3_bank15__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2739, 88, NULL,acmgt2__l3_cache16__sampler_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2740, 96, NULL,acmgt2__l3_cache16__sampler_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2741, 104, NULL,acmgt2__l3_cache16__sampler_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2742, 112, NULL,acmgt2__l3_cache16__sampler_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2743, 120, NULL,acmgt2__l3_cache16__sampler_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2744, 128, NULL,acmgt2__l3_cache16__sampler_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2745, 136, NULL,acmgt2__l3_cache16__sampler_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2746, 144, NULL,acmgt2__l3_cache16__sampler_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L3Cache17";
   query->symbol_name = "L3Cache17";
   query->guid = "07329ee0-625a-45bf-851c-a8d7b8694afb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B1000 },
         { .reg = 0x00009888, .val = 0x112B1000 },
         { .reg = 0x00009888, .val = 0x114B1000 },
         { .reg = 0x00009888, .val = 0x116B1000 },
         { .reg = 0x00009888, .val = 0x110C1000 },
         { .reg = 0x00009888, .val = 0x112C1000 },
         { .reg = 0x00009888, .val = 0x114C1000 },
         { .reg = 0x00009888, .val = 0x116C1183 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x070B0183 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0B2B0183 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0183 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0183 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x050C0183 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0183 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0D4C0183 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x020200F0 },
         { .reg = 0x00009888, .val = 0x02030A05 },
         { .reg = 0x00009888, .val = 0x0204FA5A },
         { .reg = 0x00009888, .val = 0x000500A0 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x00060A05 },
         { .reg = 0x00009888, .val = 0x00070033 },
         { .reg = 0x00009888, .val = 0x0008F5A5 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00090033 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030421 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36031C24 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030207 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache17__avg_gpu_core_frequency__max,acmgt2__l3_cache17__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 955, 24, percentage_max_float,acmgt2__l3_cache17__l3_superq_full_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 956, 28, percentage_max_float,acmgt2__l3_cache17__l3_superq_full_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 957, 32, percentage_max_float,acmgt2__l3_cache17__l3_superq_full_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 958, 36, percentage_max_float,acmgt2__l3_cache17__l3_superq_full_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 959, 40, percentage_max_float,acmgt2__l3_cache17__l3_superq_full_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 960, 44, percentage_max_float,acmgt2__l3_cache17__l3_superq_full_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 961, 48, percentage_max_float,acmgt2__l3_cache17__l3_superq_full_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 962, 52, percentage_max_float,acmgt2__l3_cache17__l3_superq_full_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L3Cache18";
   query->symbol_name = "L3Cache18";
   query->guid = "ee38be83-7e26-4c3d-83ce-4882411fba2a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B1000 },
         { .reg = 0x00009888, .val = 0x112B1000 },
         { .reg = 0x00009888, .val = 0x114B1000 },
         { .reg = 0x00009888, .val = 0x116B1000 },
         { .reg = 0x00009888, .val = 0x110C1000 },
         { .reg = 0x00009888, .val = 0x112C1000 },
         { .reg = 0x00009888, .val = 0x114C1000 },
         { .reg = 0x00009888, .val = 0x116C1183 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x070B0183 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0B2B0183 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0183 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0183 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x050C0183 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0183 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0D4C0183 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x020200F0 },
         { .reg = 0x00009888, .val = 0x02030A05 },
         { .reg = 0x00009888, .val = 0x0204FA5A },
         { .reg = 0x00009888, .val = 0x000500A0 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x00060A05 },
         { .reg = 0x00009888, .val = 0x00070033 },
         { .reg = 0x00009888, .val = 0x0008F5A5 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00090033 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030421 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36031C24 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030207 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache18__avg_gpu_core_frequency__max,acmgt2__l3_cache18__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2747, 24, percentage_max_float,acmgt2__l3_cache18__l3_superq_full_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2748, 28, percentage_max_float,acmgt2__l3_cache18__l3_superq_full_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2749, 32, percentage_max_float,acmgt2__l3_cache18__l3_superq_full_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2750, 36, percentage_max_float,acmgt2__l3_cache18__l3_superq_full_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2751, 40, percentage_max_float,acmgt2__l3_cache18__l3_superq_full_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2752, 44, percentage_max_float,acmgt2__l3_cache18__l3_superq_full_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2753, 48, percentage_max_float,acmgt2__l3_cache18__l3_superq_full_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 2754, 52, percentage_max_float,acmgt2__l3_cache18__l3_superq_full_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache19_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache19";
   query->symbol_name = "L3Cache19";
   query->guid = "9c3213fc-98df-4619-b6ed-3dbfe01b76e7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030444 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030402 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030050 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34032040 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache19__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache19__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache19__avg_gpu_core_frequency__max,acmgt2__l3_cache19__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 915, 24, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 916, 32, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 917, 40, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 918, 48, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 919, 56, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 920, 64, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 921, 72, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 922, 80, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2755, 88, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2756, 96, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2757, 104, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2758, 112, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2759, 120, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2760, 128, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2761, 136, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2762, 144, NULL,acmgt2__l3_cache19__color_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache20_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache20";
   query->symbol_name = "L3Cache20";
   query->guid = "eeee50d3-45ec-4978-a359-c577c3c7ccdb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0005 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0140 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0005 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0140 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030444 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030402 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030050 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34032040 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache20__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache20__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache20__avg_gpu_core_frequency__max,acmgt2__l3_cache20__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 923, 24, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 924, 32, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 925, 40, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 926, 48, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 927, 56, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 928, 64, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 929, 72, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 930, 80, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2763, 88, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2764, 96, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2765, 104, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2766, 112, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2767, 120, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2768, 128, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2769, 136, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2770, 144, NULL,acmgt2__l3_cache20__z_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache21";
   query->symbol_name = "L3Cache21";
   query->guid = "955bae70-17de-4328-ac24-3f8f2c8e1f78";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030444 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030402 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030050 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34032040 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache21__avg_gpu_core_frequency__max,acmgt2__l3_cache21__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 907, 24, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 908, 32, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 909, 40, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 910, 48, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 911, 56, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 912, 64, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 913, 72, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 914, 80, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2771, 88, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2772, 96, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2773, 104, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2774, 112, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2775, 120, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2776, 128, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2777, 136, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2778, 144, NULL,acmgt2__l3_cache21__dataport_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_l3_cache22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "L3Cache22";
   query->symbol_name = "L3Cache22";
   query->guid = "a3076e23-85b3-4aae-bfa3-de0b0806fa54";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1004 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1100 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030444 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030402 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031400 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030207 },
         { .reg = 0x00009888, .val = 0x3E030050 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34032040 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__l3_cache22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__l3_cache22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__l3_cache22__avg_gpu_core_frequency__max,acmgt2__l3_cache22__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 931, 24, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 932, 32, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 933, 40, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 934, 48, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 935, 56, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 936, 64, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 937, 72, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 938, 80, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2779, 88, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2780, 96, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2781, 104, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2782, 112, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2783, 120, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2784, 128, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2785, 136, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2786, 144, NULL,acmgt2__l3_cache22__l3_atomic_access_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Memory1";
   query->symbol_name = "Memory1";
   query->guid = "6b77c667-0ea4-4d77-9a2a-ae996fc127bc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x02410006 },
         { .reg = 0x00009888, .val = 0x12410004 },
         { .reg = 0x00009888, .val = 0x16410005 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610006 },
         { .reg = 0x00009888, .val = 0x10610100 },
         { .reg = 0x00009888, .val = 0x14610140 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810006 },
         { .reg = 0x00009888, .val = 0x10810004 },
         { .reg = 0x00009888, .val = 0x14810005 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10006 },
         { .reg = 0x00009888, .val = 0x0EA10100 },
         { .reg = 0x00009888, .val = 0x12A10140 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02015050 },
         { .reg = 0x00009888, .val = 0x0204B0B0 },
         { .reg = 0x00009888, .val = 0x02085050 },
         { .reg = 0x00009888, .val = 0x02020505 },
         { .reg = 0x00009888, .val = 0x02031200 },
         { .reg = 0x00009888, .val = 0x04032252 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x02090B0B },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory1__avg_gpu_core_frequency__max,acmgt2__memory1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 803, 24, NULL,acmgt2__memory1__gpu_memory_byte_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 804, 32, NULL,acmgt2__memory1__gpu_memory_byte_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2787, 40, NULL,acmgt2__memory1__gpu_memory_byte_read_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2788, 48, NULL,acmgt2__memory1__gpu_memory_byte_read_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 795, 56, NULL,acmgt2__memory1__gpu_memory_byte_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 796, 64, NULL,acmgt2__memory1__gpu_memory_byte_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2789, 72, NULL,acmgt2__memory1__gpu_memory_byte_write_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2790, 80, NULL,acmgt2__memory1__gpu_memory_byte_write_sqidi3__read);

      intel_perf_query_add_counter_float(query, 809, 88, NULL,acmgt2__memory1__gpu_memory_byte_read_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 810, 92, NULL,acmgt2__memory1__gpu_memory_byte_read_bw_sqidi1__read);

      intel_perf_query_add_counter_float(query, 2791, 96, NULL,acmgt2__memory1__gpu_memory_byte_read_bw_sqidi2__read);

      intel_perf_query_add_counter_float(query, 2792, 100, NULL,acmgt2__memory1__gpu_memory_byte_read_bw_sqidi3__read);

      intel_perf_query_add_counter_float(query, 811, 104, NULL,acmgt2__memory1__gpu_memory_byte_write_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 812, 108, NULL,acmgt2__memory1__gpu_memory_byte_write_bw_sqidi1__read);

      intel_perf_query_add_counter_float(query, 2793, 112, NULL,acmgt2__memory1__gpu_memory_byte_write_bw_sqidi2__read);

      intel_perf_query_add_counter_float(query, 2794, 116, NULL,acmgt2__memory1__gpu_memory_byte_write_bw_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 762, 120, acmgt2__memory1__gpu_memory_byte_read__max,acmgt2__memory1__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 128, acmgt2__memory1__gpu_memory_byte_write__max,acmgt2__memory1__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 813, 136, NULL,acmgt2__memory1__gpu_memory_byte_read_bw__read);

      intel_perf_query_add_counter_float(query, 814, 140, NULL,acmgt2__memory1__gpu_memory_byte_write_bw__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Memory2";
   query->symbol_name = "Memory2";
   query->guid = "d96f021b-8a19-44df-8f52-68ed64096056";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x1A410140 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x1A610140 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x1A810140 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x1AA10140 },
         { .reg = 0x00009888, .val = 0x02410106 },
         { .reg = 0x00009888, .val = 0x14410180 },
         { .reg = 0x00009888, .val = 0x1641000D },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610106 },
         { .reg = 0x00009888, .val = 0x12610180 },
         { .reg = 0x00009888, .val = 0x1461000D },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810106 },
         { .reg = 0x00009888, .val = 0x10810180 },
         { .reg = 0x00009888, .val = 0x1281000D },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10106 },
         { .reg = 0x00009888, .val = 0x0EA10180 },
         { .reg = 0x00009888, .val = 0x10A1000D },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02015500 },
         { .reg = 0x00009888, .val = 0x0204AF00 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02031200 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x020900AF },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory2__avg_gpu_core_frequency__max,acmgt2__memory2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 800, 24, NULL,acmgt2__memory2__gpu_memory_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 801, 32, NULL,acmgt2__memory2__gpu_memory_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2795, 40, NULL,acmgt2__memory2__gpu_memory_read_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2796, 48, NULL,acmgt2__memory2__gpu_memory_read_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 802, 56, NULL,acmgt2__memory2__gpu_memory_read__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Memory3";
   query->symbol_name = "Memory3";
   query->guid = "1aefcfd0-08ce-4632-b634-2009d3303341";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x100900AC },
         { .reg = 0x00009888, .val = 0x02015000 },
         { .reg = 0x00009888, .val = 0x0204B000 },
         { .reg = 0x00009888, .val = 0x02085000 },
         { .reg = 0x00009888, .val = 0x02020550 },
         { .reg = 0x00009888, .val = 0x04032249 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x0A097AC0 },
         { .reg = 0x00009888, .val = 0x04090000 },
         { .reg = 0x00009888, .val = 0x02090B00 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x32031080 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x02410006 },
         { .reg = 0x00009888, .val = 0x16410007 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610006 },
         { .reg = 0x00009888, .val = 0x146101C0 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810006 },
         { .reg = 0x00009888, .val = 0x14810007 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10006 },
         { .reg = 0x00009888, .val = 0x12A101C0 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory3__avg_gpu_core_frequency__max,acmgt2__memory3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 797, 24, NULL,acmgt2__memory3__gpu_memory_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 798, 32, NULL,acmgt2__memory3__gpu_memory_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2797, 40, NULL,acmgt2__memory3__gpu_memory_write_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2798, 48, NULL,acmgt2__memory3__gpu_memory_write_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 799, 56, NULL,acmgt2__memory3__gpu_memory_write__read);

      intel_perf_query_add_counter_uint64(query, 825, 64, NULL,acmgt2__memory3__host_to_gpumem_transaction_read__read);

      intel_perf_query_add_counter_uint64(query, 826, 72, NULL,acmgt2__memory3__host_to_gpumem_transaction_write__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Memory4";
   query->symbol_name = "Memory4";
   query->guid = "d49bf819-990d-4638-a1f2-57943ad58d8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x10420251 },
         { .reg = 0x00009888, .val = 0x10620251 },
         { .reg = 0x00009888, .val = 0x10820251 },
         { .reg = 0x00009888, .val = 0x10A20251 },
         { .reg = 0x00009888, .val = 0x0041C0C0 },
         { .reg = 0x00009888, .val = 0x06420207 },
         { .reg = 0x00009888, .val = 0x0E420185 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00613030 },
         { .reg = 0x00009888, .val = 0x04620207 },
         { .reg = 0x00009888, .val = 0x0C620185 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00810C0C },
         { .reg = 0x00009888, .val = 0x02820207 },
         { .reg = 0x00009888, .val = 0x0A820185 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00A10303 },
         { .reg = 0x00009888, .val = 0x00A20207 },
         { .reg = 0x00009888, .val = 0x08A20185 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00015500 },
         { .reg = 0x00009888, .val = 0x02015500 },
         { .reg = 0x00009888, .val = 0x0004AF00 },
         { .reg = 0x00009888, .val = 0x0204AF00 },
         { .reg = 0x00009888, .val = 0x00085500 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x000900AF },
         { .reg = 0x00009888, .val = 0x020900AF },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory4__avg_gpu_core_frequency__max,acmgt2__memory4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 817, 24, NULL,acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 819, 32, NULL,acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2799, 40, NULL,acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2800, 48, NULL,acmgt2__memory4__gpu_memory_32_b_transaction_read_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 818, 56, NULL,acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 820, 64, NULL,acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2801, 72, NULL,acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2802, 80, NULL,acmgt2__memory4__gpu_memory_64_b_transaction_read_sqidi3__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Memory5";
   query->symbol_name = "Memory5";
   query->guid = "bd8af739-2f08-4384-823b-ea5fe198fee9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1042000C },
         { .reg = 0x00009888, .val = 0x1062000C },
         { .reg = 0x00009888, .val = 0x1082000C },
         { .reg = 0x00009888, .val = 0x10A2000C },
         { .reg = 0x00009888, .val = 0x00418800 },
         { .reg = 0x00009888, .val = 0x0A420100 },
         { .reg = 0x00009888, .val = 0x0E420080 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00614400 },
         { .reg = 0x00009888, .val = 0x0A620004 },
         { .reg = 0x00009888, .val = 0x0E620002 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00812200 },
         { .reg = 0x00009888, .val = 0x08820100 },
         { .reg = 0x00009888, .val = 0x0C820080 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00A11100 },
         { .reg = 0x00009888, .val = 0x08A20004 },
         { .reg = 0x00009888, .val = 0x0CA20002 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02015050 },
         { .reg = 0x00009888, .val = 0x0204B0B0 },
         { .reg = 0x00009888, .val = 0x02085050 },
         { .reg = 0x00009888, .val = 0x02020505 },
         { .reg = 0x00009888, .val = 0x02031200 },
         { .reg = 0x00009888, .val = 0x04032252 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x02090B0B },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory5__avg_gpu_core_frequency__max,acmgt2__memory5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 821, 24, NULL,acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 823, 32, NULL,acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2803, 40, NULL,acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2804, 48, NULL,acmgt2__memory5__gpu_memory_32_b_transaction_write_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 822, 56, NULL,acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 824, 64, NULL,acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2805, 72, NULL,acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2806, 80, NULL,acmgt2__memory5__gpu_memory_64_b_transaction_write_sqidi3__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Memory6";
   query->symbol_name = "Memory6";
   query->guid = "b43a5fd8-3d74-46c4-9261-62c25070e559";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1641034E },
         { .reg = 0x00009888, .val = 0x1A410140 },
         { .reg = 0x00009888, .val = 0x16610340 },
         { .reg = 0x00009888, .val = 0x1A610140 },
         { .reg = 0x00009888, .val = 0x16810340 },
         { .reg = 0x00009888, .val = 0x1A810140 },
         { .reg = 0x00009888, .val = 0x16A10340 },
         { .reg = 0x00009888, .val = 0x1AA10140 },
         { .reg = 0x00009888, .val = 0x02410100 },
         { .reg = 0x00009888, .val = 0x12410002 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610100 },
         { .reg = 0x00009888, .val = 0x10610080 },
         { .reg = 0x00009888, .val = 0x14610380 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810100 },
         { .reg = 0x00009888, .val = 0x10810002 },
         { .reg = 0x00009888, .val = 0x1481000E },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10100 },
         { .reg = 0x00009888, .val = 0x0EA10080 },
         { .reg = 0x00009888, .val = 0x12A10380 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02015050 },
         { .reg = 0x00009888, .val = 0x0204B0B0 },
         { .reg = 0x00009888, .val = 0x02085050 },
         { .reg = 0x00009888, .val = 0x02020505 },
         { .reg = 0x00009888, .val = 0x02031200 },
         { .reg = 0x00009888, .val = 0x04032252 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x02090B0B },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory6__avg_gpu_core_frequency__max,acmgt2__memory6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 805, 24, percentage_max_float,acmgt2__memory6__gpu_memory_active_sqidi0__read);

      intel_perf_query_add_counter_float(query, 806, 28, percentage_max_float,acmgt2__memory6__gpu_memory_active_sqidi1__read);

      intel_perf_query_add_counter_float(query, 2807, 32, percentage_max_float,acmgt2__memory6__gpu_memory_active_sqidi2__read);

      intel_perf_query_add_counter_float(query, 2808, 36, percentage_max_float,acmgt2__memory6__gpu_memory_active_sqidi3__read);

      intel_perf_query_add_counter_float(query, 815, 40, percentage_max_float,acmgt2__memory6__gpu_memory_request_queue_full_sqidi0__read);

      intel_perf_query_add_counter_float(query, 816, 44, percentage_max_float,acmgt2__memory6__gpu_memory_request_queue_full_sqidi1__read);

      intel_perf_query_add_counter_float(query, 2809, 48, percentage_max_float,acmgt2__memory6__gpu_memory_request_queue_full_sqidi2__read);

      intel_perf_query_add_counter_float(query, 2810, 52, percentage_max_float,acmgt2__memory6__gpu_memory_request_queue_full_sqidi3__read);

      intel_perf_query_add_counter_float(query, 2811, 56, percentage_max_float,acmgt2__memory6__gpu_memory_active__read);

      intel_perf_query_add_counter_float(query, 2812, 60, percentage_max_float,acmgt2__memory6__gpu_memory_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Memory7";
   query->symbol_name = "Memory7";
   query->guid = "51e468d7-f95f-4b2a-bfeb-01986463e901";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x10090005 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010001 },
         { .reg = 0x00009888, .val = 0x0004AAAA },
         { .reg = 0x00009888, .val = 0x02040002 },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02080001 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030492 },
         { .reg = 0x00009888, .val = 0x04031000 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x0C095000 },
         { .reg = 0x00009888, .val = 0x0E090012 },
         { .reg = 0x00009888, .val = 0x04090000 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030004 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x34031000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x1A41000F },
         { .reg = 0x00009888, .val = 0x024100E6 },
         { .reg = 0x00009888, .val = 0x06411C00 },
         { .reg = 0x00009888, .val = 0x08410248 },
         { .reg = 0x00009888, .val = 0x0A4102CA },
         { .reg = 0x00009888, .val = 0x0C41034C },
         { .reg = 0x00009888, .val = 0x0E4103CE },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory7__avg_gpu_core_frequency__max,acmgt2__memory7__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1702, 24, NULL,acmgt2__memory7__gpu_memory_l3_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 808, 32, NULL,acmgt2__memory7__sysmem_transaction_read__read);

      intel_perf_query_add_counter_uint64(query, 807, 40, NULL,acmgt2__memory7__sysmem_transaction_write__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Memory8";
   query->symbol_name = "Memory8";
   query->guid = "08667e1d-ae1b-4370-bc59-2347bb0d7f8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x1A61000F },
         { .reg = 0x00009888, .val = 0x026100E6 },
         { .reg = 0x00009888, .val = 0x06611C00 },
         { .reg = 0x00009888, .val = 0x08610248 },
         { .reg = 0x00009888, .val = 0x0A6102CA },
         { .reg = 0x00009888, .val = 0x0C61034C },
         { .reg = 0x00009888, .val = 0x0E6103CE },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010001 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x02040003 },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02080001 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory8__avg_gpu_core_frequency__max,acmgt2__memory8__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1703, 24, NULL,acmgt2__memory8__gpu_memory_l3_write_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Memory9";
   query->symbol_name = "Memory9";
   query->guid = "b2462b2f-f73f-42d6-9b5e-46cae062d1c1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x1A81000F },
         { .reg = 0x00009888, .val = 0x028100E6 },
         { .reg = 0x00009888, .val = 0x06811C00 },
         { .reg = 0x00009888, .val = 0x08810248 },
         { .reg = 0x00009888, .val = 0x0A8102CA },
         { .reg = 0x00009888, .val = 0x0C81034C },
         { .reg = 0x00009888, .val = 0x0E8103CE },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030249 },
         { .reg = 0x00009888, .val = 0x0009AAAA },
         { .reg = 0x00009888, .val = 0x02090002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory9__avg_gpu_core_frequency__max,acmgt2__memory9__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2813, 24, NULL,acmgt2__memory9__gpu_memory_l3_write_sqidi2__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Memory10";
   query->symbol_name = "Memory10";
   query->guid = "15694e7b-c38d-4a65-a355-df93411ed0df";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x1AA1000F },
         { .reg = 0x00009888, .val = 0x02A100E6 },
         { .reg = 0x00009888, .val = 0x06A11C00 },
         { .reg = 0x00009888, .val = 0x08A10248 },
         { .reg = 0x00009888, .val = 0x0AA102CA },
         { .reg = 0x00009888, .val = 0x0CA1034C },
         { .reg = 0x00009888, .val = 0x0EA103CE },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030249 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x02090003 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory10__avg_gpu_core_frequency__max,acmgt2__memory10__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2814, 24, NULL,acmgt2__memory10__gpu_memory_l3_write_sqidi3__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Memory11";
   query->symbol_name = "Memory11";
   query->guid = "84667f81-6441-46d7-844d-e13078a16811";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1A412540 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x1A61000F },
         { .reg = 0x00009888, .val = 0x02410128 },
         { .reg = 0x00009888, .val = 0x06411400 },
         { .reg = 0x00009888, .val = 0x08410288 },
         { .reg = 0x00009888, .val = 0x0A41030B },
         { .reg = 0x00009888, .val = 0x0C41038D },
         { .reg = 0x00009888, .val = 0x0E41000F },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x026100E6 },
         { .reg = 0x00009888, .val = 0x0E610180 },
         { .reg = 0x00009888, .val = 0x10610288 },
         { .reg = 0x00009888, .val = 0x1261030B },
         { .reg = 0x00009888, .val = 0x1461038D },
         { .reg = 0x00009888, .val = 0x1661000F },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0004AAAA },
         { .reg = 0x00009888, .val = 0x0204FFFF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02085555 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory11__avg_gpu_core_frequency__max,acmgt2__memory11__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1792, 24, NULL,acmgt2__memory11__gpu_memory_l3_read_sqidi0__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Memory12";
   query->symbol_name = "Memory12";
   query->guid = "3ec5f9fe-1567-456a-bb0c-f3b026813bd7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x1A41000F },
         { .reg = 0x00009888, .val = 0x1A612540 },
         { .reg = 0x00009888, .val = 0x024100E6 },
         { .reg = 0x00009888, .val = 0x0E410180 },
         { .reg = 0x00009888, .val = 0x10410288 },
         { .reg = 0x00009888, .val = 0x1241030B },
         { .reg = 0x00009888, .val = 0x1441038D },
         { .reg = 0x00009888, .val = 0x1641000F },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610128 },
         { .reg = 0x00009888, .val = 0x06611400 },
         { .reg = 0x00009888, .val = 0x08610288 },
         { .reg = 0x00009888, .val = 0x0A61030B },
         { .reg = 0x00009888, .val = 0x0C61038D },
         { .reg = 0x00009888, .val = 0x0E61000F },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x0204AAAA },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02085555 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory12__avg_gpu_core_frequency__max,acmgt2__memory12__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1793, 24, NULL,acmgt2__memory12__gpu_memory_l3_read_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Memory13";
   query->symbol_name = "Memory13";
   query->guid = "3ab47029-8b0b-4049-ac68-1ff07d0e7a6e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1A812540 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x1AA1000F },
         { .reg = 0x00009888, .val = 0x02810128 },
         { .reg = 0x00009888, .val = 0x06811400 },
         { .reg = 0x00009888, .val = 0x08810288 },
         { .reg = 0x00009888, .val = 0x0A81030B },
         { .reg = 0x00009888, .val = 0x0C81038D },
         { .reg = 0x00009888, .val = 0x0E81000F },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A100E6 },
         { .reg = 0x00009888, .val = 0x0EA10180 },
         { .reg = 0x00009888, .val = 0x10A10288 },
         { .reg = 0x00009888, .val = 0x12A1030B },
         { .reg = 0x00009888, .val = 0x14A1038D },
         { .reg = 0x00009888, .val = 0x16A1000F },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x0009AAAA },
         { .reg = 0x00009888, .val = 0x0209FFFF },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory13__avg_gpu_core_frequency__max,acmgt2__memory13__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2815, 24, NULL,acmgt2__memory13__gpu_memory_l3_read_sqidi2__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_memory14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Memory14";
   query->symbol_name = "Memory14";
   query->guid = "8748eaa5-422c-4597-b4a1-519ccb6f4e95";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x1A81000F },
         { .reg = 0x00009888, .val = 0x1AA12540 },
         { .reg = 0x00009888, .val = 0x028100E6 },
         { .reg = 0x00009888, .val = 0x0E810180 },
         { .reg = 0x00009888, .val = 0x10810288 },
         { .reg = 0x00009888, .val = 0x1281030B },
         { .reg = 0x00009888, .val = 0x1481038D },
         { .reg = 0x00009888, .val = 0x1681000F },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10128 },
         { .reg = 0x00009888, .val = 0x06A11400 },
         { .reg = 0x00009888, .val = 0x08A10288 },
         { .reg = 0x00009888, .val = 0x0AA1030B },
         { .reg = 0x00009888, .val = 0x0CA1038D },
         { .reg = 0x00009888, .val = 0x0EA1000F },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x0209AAAA },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__memory14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__memory14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__memory14__avg_gpu_core_frequency__max,acmgt2__memory14__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2816, 24, NULL,acmgt2__memory14__gpu_memory_l3_read_sqidi3__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_rasterizer1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Rasterizer1";
   query->symbol_name = "Rasterizer1";
   query->guid = "5050cadd-fc05-4183-b3dc-99f9ff5a0075";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A057800 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x1B057800 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x0003400C },
         { .reg = 0x00009888, .val = 0x00058000 },
         { .reg = 0x00009888, .val = 0x020530C8 },
         { .reg = 0x00009888, .val = 0x10050F00 },
         { .reg = 0x00009888, .val = 0x00068003 },
         { .reg = 0x00009888, .val = 0x000800F5 },
         { .reg = 0x00009888, .val = 0x02087000 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A5000 },
         { .reg = 0x00009888, .val = 0x0001400C },
         { .reg = 0x00009888, .val = 0x000B00A0 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x01058000 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x05050C32 },
         { .reg = 0x00009888, .val = 0x1105003C },
         { .reg = 0x00009888, .val = 0x0106400C },
         { .reg = 0x00009888, .val = 0x01080050 },
         { .reg = 0x00009888, .val = 0x03081000 },
         { .reg = 0x00009888, .val = 0x010A0050 },
         { .reg = 0x00009888, .val = 0x030A1000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A057800 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x1B057800 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x000310C0 },
         { .reg = 0x00009888, .val = 0x00058000 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x06050C32 },
         { .reg = 0x00009888, .val = 0x0E050F00 },
         { .reg = 0x00009888, .val = 0x00062030 },
         { .reg = 0x00009888, .val = 0x0008F500 },
         { .reg = 0x00009888, .val = 0x02080700 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0500 },
         { .reg = 0x00009888, .val = 0x000110C0 },
         { .reg = 0x00009888, .val = 0x000BA000 },
         { .reg = 0x00009888, .val = 0x020B0200 },
         { .reg = 0x00009888, .val = 0x01058000 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x09050C32 },
         { .reg = 0x00009888, .val = 0x0F05003C },
         { .reg = 0x00009888, .val = 0x010610C0 },
         { .reg = 0x00009888, .val = 0x01085000 },
         { .reg = 0x00009888, .val = 0x03080100 },
         { .reg = 0x00009888, .val = 0x010A5000 },
         { .reg = 0x00009888, .val = 0x030A0100 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04032240 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030009 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36030529 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38031061 },
         { .reg = 0x00009888, .val = 0x3A030083 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030500 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001C00F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000130F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__rasterizer1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__rasterizer1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__rasterizer1__avg_gpu_core_frequency__max,acmgt2__rasterizer1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2104, 24, NULL,acmgt2__rasterizer1__rasterizer_sample_output__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1417, 32, percentage_max_float,acmgt2__rasterizer1__rasterizer_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1418, 36, percentage_max_float,acmgt2__rasterizer1__rasterizer_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2817, 40, percentage_max_float,acmgt2__rasterizer1__rasterizer_input_available_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2818, 44, percentage_max_float,acmgt2__rasterizer1__rasterizer_input_available_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 1419, 48, percentage_max_float,acmgt2__rasterizer1__rasterizer_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 1420, 52, percentage_max_float,acmgt2__rasterizer1__rasterizer_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2819, 56, percentage_max_float,acmgt2__rasterizer1__rasterizer_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2820, 60, percentage_max_float,acmgt2__rasterizer1__rasterizer_output_ready_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_rasterizer2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Rasterizer2";
   query->symbol_name = "Rasterizer2";
   query->guid = "57ce566e-b572-4434-981c-558a16bd62d3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A057C00 },
         { .reg = 0x00009888, .val = 0x1C050013 },
         { .reg = 0x00009888, .val = 0x1B057C00 },
         { .reg = 0x00009888, .val = 0x1D050013 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x10050F31 },
         { .reg = 0x00009888, .val = 0x0006C000 },
         { .reg = 0x00009888, .val = 0x02085F00 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03050001 },
         { .reg = 0x00009888, .val = 0x0F050F31 },
         { .reg = 0x00009888, .val = 0x01063000 },
         { .reg = 0x00009888, .val = 0x03080500 },
         { .reg = 0x00009888, .val = 0x030A0500 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A057C00 },
         { .reg = 0x00009888, .val = 0x1C050013 },
         { .reg = 0x00009888, .val = 0x1B057C00 },
         { .reg = 0x00009888, .val = 0x1D050013 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0C050F31 },
         { .reg = 0x00009888, .val = 0x00060C00 },
         { .reg = 0x00009888, .val = 0x0208005F },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010300 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03050001 },
         { .reg = 0x00009888, .val = 0x0B050F31 },
         { .reg = 0x00009888, .val = 0x01060300 },
         { .reg = 0x00009888, .val = 0x03080005 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x02031200 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x32032100 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032421 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x36030009 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__rasterizer2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__rasterizer2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__rasterizer2__avg_gpu_core_frequency__max,acmgt2__rasterizer2__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1415, 24, NULL,acmgt2__rasterizer2__rasterizer_transaction_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1416, 32, NULL,acmgt2__rasterizer2__rasterizer_transaction_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 2821, 40, NULL,acmgt2__rasterizer2__rasterizer_transaction_output_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 2822, 48, NULL,acmgt2__rasterizer2__rasterizer_transaction_output_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing1";
   query->symbol_name = "RayTracing1";
   query->guid = "2db46c14-6718-46e3-a9a4-b2ba4aa10a3a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16857FC0 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x08851000 },
         { .reg = 0x00009888, .val = 0x18894740 },
         { .reg = 0x00009888, .val = 0x1E89023A },
         { .reg = 0x00009888, .val = 0x22896800 },
         { .reg = 0x00009888, .val = 0x24890011 },
         { .reg = 0x00009888, .val = 0x28894740 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x02850B2C },
         { .reg = 0x00009888, .val = 0x0E850154 },
         { .reg = 0x00009888, .val = 0x108505D8 },
         { .reg = 0x00009888, .val = 0x128503CE },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0286AAA0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x068903C1 },
         { .reg = 0x00009888, .val = 0x088907D1 },
         { .reg = 0x00009888, .val = 0x0A890BE1 },
         { .reg = 0x00009888, .val = 0x0C890FF1 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing1__avg_gpu_core_frequency__max,acmgt2__ray_tracing1__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1650, 24, NULL,acmgt2__ray_tracing1__rt_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1658, 32, NULL,acmgt2__ray_tracing1__rt_load_store_cache_write_from_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1496, 40, NULL,acmgt2__ray_tracing1__rt_traversal_input_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1552, 48, NULL,acmgt2__ray_tracing1__rt_quad_test_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1576, 56, NULL,acmgt2__ray_tracing1__rt_request_collision_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1488, 64, NULL,acmgt2__ray_tracing1__rt_input_message_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1568, 72, percentage_max_float,acmgt2__ray_tracing1__rt_message_stall_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1560, 80, NULL,acmgt2__ray_tracing1__rt_transform_ray_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing2";
   query->symbol_name = "RayTracing2";
   query->guid = "97513a9f-a2b6-4766-a2c7-530ae3271f9d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A57FC0 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x08A51000 },
         { .reg = 0x00009888, .val = 0x18A94740 },
         { .reg = 0x00009888, .val = 0x1EA9023A },
         { .reg = 0x00009888, .val = 0x22A96800 },
         { .reg = 0x00009888, .val = 0x24A90011 },
         { .reg = 0x00009888, .val = 0x28A94740 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x00A400FF },
         { .reg = 0x00009888, .val = 0x02A50B2C },
         { .reg = 0x00009888, .val = 0x0EA50154 },
         { .reg = 0x00009888, .val = 0x10A505D8 },
         { .reg = 0x00009888, .val = 0x12A503CE },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A6AAA0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A903C1 },
         { .reg = 0x00009888, .val = 0x08A907D1 },
         { .reg = 0x00009888, .val = 0x0AA90BE1 },
         { .reg = 0x00009888, .val = 0x0CA90FF1 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing2__avg_gpu_core_frequency__max,acmgt2__ray_tracing2__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1651, 24, NULL,acmgt2__ray_tracing2__rt_load_store_cache_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1659, 32, NULL,acmgt2__ray_tracing2__rt_load_store_cache_write_from_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1497, 40, NULL,acmgt2__ray_tracing2__rt_traversal_input_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1553, 48, NULL,acmgt2__ray_tracing2__rt_quad_test_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1577, 56, NULL,acmgt2__ray_tracing2__rt_request_collision_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1489, 64, NULL,acmgt2__ray_tracing2__rt_input_message_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1569, 72, percentage_max_float,acmgt2__ray_tracing2__rt_message_stall_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1561, 80, NULL,acmgt2__ray_tracing2__rt_transform_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing3";
   query->symbol_name = "RayTracing3";
   query->guid = "9ed83fc5-a773-479f-9cf4-146f2aca4e48";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C57FC0 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x08C51000 },
         { .reg = 0x00009888, .val = 0x18C94740 },
         { .reg = 0x00009888, .val = 0x1EC9023A },
         { .reg = 0x00009888, .val = 0x22C96800 },
         { .reg = 0x00009888, .val = 0x24C90011 },
         { .reg = 0x00009888, .val = 0x28C94740 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x02C50B2C },
         { .reg = 0x00009888, .val = 0x0EC50154 },
         { .reg = 0x00009888, .val = 0x10C505D8 },
         { .reg = 0x00009888, .val = 0x12C503CE },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C6AAA0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C903C1 },
         { .reg = 0x00009888, .val = 0x08C907D1 },
         { .reg = 0x00009888, .val = 0x0AC90BE1 },
         { .reg = 0x00009888, .val = 0x0CC90FF1 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FCFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing3__avg_gpu_core_frequency__max,acmgt2__ray_tracing3__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1652, 24, NULL,acmgt2__ray_tracing3__rt_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1660, 32, NULL,acmgt2__ray_tracing3__rt_load_store_cache_write_from_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1498, 40, NULL,acmgt2__ray_tracing3__rt_traversal_input_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1554, 48, NULL,acmgt2__ray_tracing3__rt_quad_test_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1578, 56, NULL,acmgt2__ray_tracing3__rt_request_collision_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1490, 64, NULL,acmgt2__ray_tracing3__rt_input_message_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1570, 72, percentage_max_float,acmgt2__ray_tracing3__rt_message_stall_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1562, 80, NULL,acmgt2__ray_tracing3__rt_transform_ray_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing4";
   query->symbol_name = "RayTracing4";
   query->guid = "5564a1fd-d09e-46bd-8f4d-50a38ca7eb32";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E57FC0 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x08E51000 },
         { .reg = 0x00009888, .val = 0x18E94740 },
         { .reg = 0x00009888, .val = 0x1EE9023A },
         { .reg = 0x00009888, .val = 0x22E96800 },
         { .reg = 0x00009888, .val = 0x24E90011 },
         { .reg = 0x00009888, .val = 0x28E94740 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x00E400FF },
         { .reg = 0x00009888, .val = 0x02E50B2C },
         { .reg = 0x00009888, .val = 0x0EE50154 },
         { .reg = 0x00009888, .val = 0x10E505D8 },
         { .reg = 0x00009888, .val = 0x12E503CE },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E6AAA0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E903C1 },
         { .reg = 0x00009888, .val = 0x08E907D1 },
         { .reg = 0x00009888, .val = 0x0AE90BE1 },
         { .reg = 0x00009888, .val = 0x0CE90FF1 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing4__avg_gpu_core_frequency__max,acmgt2__ray_tracing4__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1653, 24, NULL,acmgt2__ray_tracing4__rt_load_store_cache_read_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1661, 32, NULL,acmgt2__ray_tracing4__rt_load_store_cache_write_from_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1499, 40, NULL,acmgt2__ray_tracing4__rt_traversal_input_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1555, 48, NULL,acmgt2__ray_tracing4__rt_quad_test_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1579, 56, NULL,acmgt2__ray_tracing4__rt_request_collision_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1491, 64, NULL,acmgt2__ray_tracing4__rt_input_message_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1571, 72, percentage_max_float,acmgt2__ray_tracing4__rt_message_stall_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1563, 80, NULL,acmgt2__ray_tracing4__rt_transform_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing5";
   query->symbol_name = "RayTracing5";
   query->guid = "d345e009-3b67-4991-89f8-7d57749f8455";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17857FC0 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x09851000 },
         { .reg = 0x00009888, .val = 0x19894740 },
         { .reg = 0x00009888, .val = 0x1F89023A },
         { .reg = 0x00009888, .val = 0x23896800 },
         { .reg = 0x00009888, .val = 0x25890011 },
         { .reg = 0x00009888, .val = 0x29894740 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x03850B2C },
         { .reg = 0x00009888, .val = 0x0F850154 },
         { .reg = 0x00009888, .val = 0x118505D8 },
         { .reg = 0x00009888, .val = 0x138503CE },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0386AAA0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x078903C1 },
         { .reg = 0x00009888, .val = 0x098907D1 },
         { .reg = 0x00009888, .val = 0x0B890BE1 },
         { .reg = 0x00009888, .val = 0x0D890FF1 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing5__avg_gpu_core_frequency__max,acmgt2__ray_tracing5__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1654, 24, NULL,acmgt2__ray_tracing5__rt_load_store_cache_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1662, 32, NULL,acmgt2__ray_tracing5__rt_load_store_cache_write_from_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1500, 40, NULL,acmgt2__ray_tracing5__rt_traversal_input_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1556, 48, NULL,acmgt2__ray_tracing5__rt_quad_test_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1580, 56, NULL,acmgt2__ray_tracing5__rt_request_collision_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1492, 64, NULL,acmgt2__ray_tracing5__rt_input_message_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1572, 72, percentage_max_float,acmgt2__ray_tracing5__rt_message_stall_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1564, 80, NULL,acmgt2__ray_tracing5__rt_transform_ray_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing6";
   query->symbol_name = "RayTracing6";
   query->guid = "08c76b7d-54fd-4dd2-8d7b-e84a91850b26";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17A57FC0 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x09A51000 },
         { .reg = 0x00009888, .val = 0x19A94740 },
         { .reg = 0x00009888, .val = 0x1FA9023A },
         { .reg = 0x00009888, .val = 0x23A96800 },
         { .reg = 0x00009888, .val = 0x25A90011 },
         { .reg = 0x00009888, .val = 0x29A94740 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x01A400FF },
         { .reg = 0x00009888, .val = 0x03A50B2C },
         { .reg = 0x00009888, .val = 0x0FA50154 },
         { .reg = 0x00009888, .val = 0x11A505D8 },
         { .reg = 0x00009888, .val = 0x13A503CE },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A6AAA0 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A903C1 },
         { .reg = 0x00009888, .val = 0x09A907D1 },
         { .reg = 0x00009888, .val = 0x0BA90BE1 },
         { .reg = 0x00009888, .val = 0x0DA90FF1 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FCFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing6__avg_gpu_core_frequency__max,acmgt2__ray_tracing6__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1655, 24, NULL,acmgt2__ray_tracing6__rt_load_store_cache_read_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1663, 32, NULL,acmgt2__ray_tracing6__rt_load_store_cache_write_from_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1501, 40, NULL,acmgt2__ray_tracing6__rt_traversal_input_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1557, 48, NULL,acmgt2__ray_tracing6__rt_quad_test_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1581, 56, NULL,acmgt2__ray_tracing6__rt_request_collision_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1493, 64, NULL,acmgt2__ray_tracing6__rt_input_message_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1573, 72, percentage_max_float,acmgt2__ray_tracing6__rt_message_stall_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1565, 80, NULL,acmgt2__ray_tracing6__rt_transform_ray_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing7";
   query->symbol_name = "RayTracing7";
   query->guid = "db089729-1516-43ef-b2ab-c2170bbefa69";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17C57FC0 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x09C51000 },
         { .reg = 0x00009888, .val = 0x19C94740 },
         { .reg = 0x00009888, .val = 0x1FC9023A },
         { .reg = 0x00009888, .val = 0x23C96800 },
         { .reg = 0x00009888, .val = 0x25C90011 },
         { .reg = 0x00009888, .val = 0x29C94740 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x03C50B2C },
         { .reg = 0x00009888, .val = 0x0FC50154 },
         { .reg = 0x00009888, .val = 0x11C505D8 },
         { .reg = 0x00009888, .val = 0x13C503CE },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C6AAA0 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C903C1 },
         { .reg = 0x00009888, .val = 0x09C907D1 },
         { .reg = 0x00009888, .val = 0x0BC90BE1 },
         { .reg = 0x00009888, .val = 0x0DC90FF1 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FCFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing7__avg_gpu_core_frequency__max,acmgt2__ray_tracing7__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1656, 24, NULL,acmgt2__ray_tracing7__rt_load_store_cache_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1664, 32, NULL,acmgt2__ray_tracing7__rt_load_store_cache_write_from_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1502, 40, NULL,acmgt2__ray_tracing7__rt_traversal_input_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1558, 48, NULL,acmgt2__ray_tracing7__rt_quad_test_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1582, 56, NULL,acmgt2__ray_tracing7__rt_request_collision_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1494, 64, NULL,acmgt2__ray_tracing7__rt_input_message_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1574, 72, percentage_max_float,acmgt2__ray_tracing7__rt_message_stall_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1566, 80, NULL,acmgt2__ray_tracing7__rt_transform_ray_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing8";
   query->symbol_name = "RayTracing8";
   query->guid = "080a531d-76e8-44b4-b17e-6c3557d01be7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E57FC0 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x09E51000 },
         { .reg = 0x00009888, .val = 0x19E94740 },
         { .reg = 0x00009888, .val = 0x1FE9023A },
         { .reg = 0x00009888, .val = 0x23E96800 },
         { .reg = 0x00009888, .val = 0x25E90011 },
         { .reg = 0x00009888, .val = 0x29E94740 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x01E400FF },
         { .reg = 0x00009888, .val = 0x03E50B2C },
         { .reg = 0x00009888, .val = 0x0FE50154 },
         { .reg = 0x00009888, .val = 0x11E505D8 },
         { .reg = 0x00009888, .val = 0x13E503CE },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E6AAA0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E903C1 },
         { .reg = 0x00009888, .val = 0x09E907D1 },
         { .reg = 0x00009888, .val = 0x0BE90BE1 },
         { .reg = 0x00009888, .val = 0x0DE90FF1 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing8__avg_gpu_core_frequency__max,acmgt2__ray_tracing8__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1657, 24, NULL,acmgt2__ray_tracing8__rt_load_store_cache_read_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1665, 32, NULL,acmgt2__ray_tracing8__rt_load_store_cache_write_from_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1503, 40, NULL,acmgt2__ray_tracing8__rt_traversal_input_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1559, 48, NULL,acmgt2__ray_tracing8__rt_quad_test_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1583, 56, NULL,acmgt2__ray_tracing8__rt_request_collision_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1495, 64, NULL,acmgt2__ray_tracing8__rt_input_message_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1575, 72, percentage_max_float,acmgt2__ray_tracing8__rt_message_stall_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1567, 80, NULL,acmgt2__ray_tracing8__rt_transform_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing9";
   query->symbol_name = "RayTracing9";
   query->guid = "8edc7efe-7966-49b1-b318-49de98d12bc7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16857FC0 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x08851000 },
         { .reg = 0x00009888, .val = 0x18894740 },
         { .reg = 0x00009888, .val = 0x1E89023A },
         { .reg = 0x00009888, .val = 0x22896800 },
         { .reg = 0x00009888, .val = 0x24890011 },
         { .reg = 0x00009888, .val = 0x28894740 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x02850B2C },
         { .reg = 0x00009888, .val = 0x0E850154 },
         { .reg = 0x00009888, .val = 0x108505D8 },
         { .reg = 0x00009888, .val = 0x128503CE },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0286AAA0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x068903C1 },
         { .reg = 0x00009888, .val = 0x088907D1 },
         { .reg = 0x00009888, .val = 0x0A890BE1 },
         { .reg = 0x00009888, .val = 0x0C890FF1 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing9__avg_gpu_core_frequency__max,acmgt2__ray_tracing9__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2823, 24, NULL,acmgt2__ray_tracing9__rt_load_store_cache_read_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2824, 32, NULL,acmgt2__ray_tracing9__rt_load_store_cache_write_from_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2825, 40, NULL,acmgt2__ray_tracing9__rt_traversal_input_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2826, 48, NULL,acmgt2__ray_tracing9__rt_quad_test_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2827, 56, NULL,acmgt2__ray_tracing9__rt_request_collision_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2828, 64, NULL,acmgt2__ray_tracing9__rt_input_message_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2829, 72, percentage_max_float,acmgt2__ray_tracing9__rt_message_stall_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2830, 80, NULL,acmgt2__ray_tracing9__rt_transform_ray_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing10";
   query->symbol_name = "RayTracing10";
   query->guid = "98044ed5-0502-4b10-b288-db406e6c7345";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16A57FC0 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x08A51000 },
         { .reg = 0x00009888, .val = 0x18A94740 },
         { .reg = 0x00009888, .val = 0x1EA9023A },
         { .reg = 0x00009888, .val = 0x22A96800 },
         { .reg = 0x00009888, .val = 0x24A90011 },
         { .reg = 0x00009888, .val = 0x28A94740 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x00A400FF },
         { .reg = 0x00009888, .val = 0x02A50B2C },
         { .reg = 0x00009888, .val = 0x0EA50154 },
         { .reg = 0x00009888, .val = 0x10A505D8 },
         { .reg = 0x00009888, .val = 0x12A503CE },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A6AAA0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A903C1 },
         { .reg = 0x00009888, .val = 0x08A907D1 },
         { .reg = 0x00009888, .val = 0x0AA90BE1 },
         { .reg = 0x00009888, .val = 0x0CA90FF1 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing10__avg_gpu_core_frequency__max,acmgt2__ray_tracing10__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2831, 24, NULL,acmgt2__ray_tracing10__rt_load_store_cache_read_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2832, 32, NULL,acmgt2__ray_tracing10__rt_load_store_cache_write_from_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2833, 40, NULL,acmgt2__ray_tracing10__rt_traversal_input_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2834, 48, NULL,acmgt2__ray_tracing10__rt_quad_test_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2835, 56, NULL,acmgt2__ray_tracing10__rt_request_collision_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2836, 64, NULL,acmgt2__ray_tracing10__rt_input_message_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2837, 72, percentage_max_float,acmgt2__ray_tracing10__rt_message_stall_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2838, 80, NULL,acmgt2__ray_tracing10__rt_transform_ray_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing11";
   query->symbol_name = "RayTracing11";
   query->guid = "f15f0972-5362-4c24-a379-7d4da15a9cdb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16C57FC0 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x08C51000 },
         { .reg = 0x00009888, .val = 0x18C94740 },
         { .reg = 0x00009888, .val = 0x1EC9023A },
         { .reg = 0x00009888, .val = 0x22C96800 },
         { .reg = 0x00009888, .val = 0x24C90011 },
         { .reg = 0x00009888, .val = 0x28C94740 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x02C50B2C },
         { .reg = 0x00009888, .val = 0x0EC50154 },
         { .reg = 0x00009888, .val = 0x10C505D8 },
         { .reg = 0x00009888, .val = 0x12C503CE },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C6AAA0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C903C1 },
         { .reg = 0x00009888, .val = 0x08C907D1 },
         { .reg = 0x00009888, .val = 0x0AC90BE1 },
         { .reg = 0x00009888, .val = 0x0CC90FF1 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FCFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing11__avg_gpu_core_frequency__max,acmgt2__ray_tracing11__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2839, 24, NULL,acmgt2__ray_tracing11__rt_load_store_cache_read_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2840, 32, NULL,acmgt2__ray_tracing11__rt_load_store_cache_write_from_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2841, 40, NULL,acmgt2__ray_tracing11__rt_traversal_input_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2842, 48, NULL,acmgt2__ray_tracing11__rt_quad_test_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2843, 56, NULL,acmgt2__ray_tracing11__rt_request_collision_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2844, 64, NULL,acmgt2__ray_tracing11__rt_input_message_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2845, 72, percentage_max_float,acmgt2__ray_tracing11__rt_message_stall_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2846, 80, NULL,acmgt2__ray_tracing11__rt_transform_ray_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing12";
   query->symbol_name = "RayTracing12";
   query->guid = "f9ceae49-ee15-4483-8033-5bcbc66c962e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16E57FC0 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x08E51000 },
         { .reg = 0x00009888, .val = 0x18E94740 },
         { .reg = 0x00009888, .val = 0x1EE9023A },
         { .reg = 0x00009888, .val = 0x22E96800 },
         { .reg = 0x00009888, .val = 0x24E90011 },
         { .reg = 0x00009888, .val = 0x28E94740 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x00E400FF },
         { .reg = 0x00009888, .val = 0x02E50B2C },
         { .reg = 0x00009888, .val = 0x0EE50154 },
         { .reg = 0x00009888, .val = 0x10E505D8 },
         { .reg = 0x00009888, .val = 0x12E503CE },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E6AAA0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E903C1 },
         { .reg = 0x00009888, .val = 0x08E907D1 },
         { .reg = 0x00009888, .val = 0x0AE90BE1 },
         { .reg = 0x00009888, .val = 0x0CE90FF1 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing12__avg_gpu_core_frequency__max,acmgt2__ray_tracing12__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2847, 24, NULL,acmgt2__ray_tracing12__rt_load_store_cache_read_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2848, 32, NULL,acmgt2__ray_tracing12__rt_load_store_cache_write_from_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2849, 40, NULL,acmgt2__ray_tracing12__rt_traversal_input_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2850, 48, NULL,acmgt2__ray_tracing12__rt_quad_test_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2851, 56, NULL,acmgt2__ray_tracing12__rt_request_collision_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2852, 64, NULL,acmgt2__ray_tracing12__rt_input_message_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2853, 72, percentage_max_float,acmgt2__ray_tracing12__rt_message_stall_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2854, 80, NULL,acmgt2__ray_tracing12__rt_transform_ray_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing13";
   query->symbol_name = "RayTracing13";
   query->guid = "61aa5615-f570-4915-a9af-6c9ab3b52719";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17857FC0 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x09851000 },
         { .reg = 0x00009888, .val = 0x19894740 },
         { .reg = 0x00009888, .val = 0x1F89023A },
         { .reg = 0x00009888, .val = 0x23896800 },
         { .reg = 0x00009888, .val = 0x25890011 },
         { .reg = 0x00009888, .val = 0x29894740 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x03850B2C },
         { .reg = 0x00009888, .val = 0x0F850154 },
         { .reg = 0x00009888, .val = 0x118505D8 },
         { .reg = 0x00009888, .val = 0x138503CE },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0386AAA0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x078903C1 },
         { .reg = 0x00009888, .val = 0x098907D1 },
         { .reg = 0x00009888, .val = 0x0B890BE1 },
         { .reg = 0x00009888, .val = 0x0D890FF1 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing13__avg_gpu_core_frequency__max,acmgt2__ray_tracing13__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2855, 24, NULL,acmgt2__ray_tracing13__rt_load_store_cache_read_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2856, 32, NULL,acmgt2__ray_tracing13__rt_load_store_cache_write_from_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2857, 40, NULL,acmgt2__ray_tracing13__rt_traversal_input_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2858, 48, NULL,acmgt2__ray_tracing13__rt_quad_test_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2859, 56, NULL,acmgt2__ray_tracing13__rt_request_collision_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2860, 64, NULL,acmgt2__ray_tracing13__rt_input_message_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2861, 72, percentage_max_float,acmgt2__ray_tracing13__rt_message_stall_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2862, 80, NULL,acmgt2__ray_tracing13__rt_transform_ray_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing14";
   query->symbol_name = "RayTracing14";
   query->guid = "638c0798-61d0-4943-b160-87b8095d87a3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17A57FC0 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x09A51000 },
         { .reg = 0x00009888, .val = 0x19A94740 },
         { .reg = 0x00009888, .val = 0x1FA9023A },
         { .reg = 0x00009888, .val = 0x23A96800 },
         { .reg = 0x00009888, .val = 0x25A90011 },
         { .reg = 0x00009888, .val = 0x29A94740 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x01A400FF },
         { .reg = 0x00009888, .val = 0x03A50B2C },
         { .reg = 0x00009888, .val = 0x0FA50154 },
         { .reg = 0x00009888, .val = 0x11A505D8 },
         { .reg = 0x00009888, .val = 0x13A503CE },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A6AAA0 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A903C1 },
         { .reg = 0x00009888, .val = 0x09A907D1 },
         { .reg = 0x00009888, .val = 0x0BA90BE1 },
         { .reg = 0x00009888, .val = 0x0DA90FF1 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FCFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing14__avg_gpu_core_frequency__max,acmgt2__ray_tracing14__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2863, 24, NULL,acmgt2__ray_tracing14__rt_load_store_cache_read_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2864, 32, NULL,acmgt2__ray_tracing14__rt_load_store_cache_write_from_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2865, 40, NULL,acmgt2__ray_tracing14__rt_traversal_input_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2866, 48, NULL,acmgt2__ray_tracing14__rt_quad_test_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2867, 56, NULL,acmgt2__ray_tracing14__rt_request_collision_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2868, 64, NULL,acmgt2__ray_tracing14__rt_input_message_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2869, 72, percentage_max_float,acmgt2__ray_tracing14__rt_message_stall_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2870, 80, NULL,acmgt2__ray_tracing14__rt_transform_ray_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing15";
   query->symbol_name = "RayTracing15";
   query->guid = "20c09ffa-66e3-45a8-8429-acdfb972e75b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17C57FC0 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x09C51000 },
         { .reg = 0x00009888, .val = 0x19C94740 },
         { .reg = 0x00009888, .val = 0x1FC9023A },
         { .reg = 0x00009888, .val = 0x23C96800 },
         { .reg = 0x00009888, .val = 0x25C90011 },
         { .reg = 0x00009888, .val = 0x29C94740 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x03C50B2C },
         { .reg = 0x00009888, .val = 0x0FC50154 },
         { .reg = 0x00009888, .val = 0x11C505D8 },
         { .reg = 0x00009888, .val = 0x13C503CE },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C6AAA0 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C903C1 },
         { .reg = 0x00009888, .val = 0x09C907D1 },
         { .reg = 0x00009888, .val = 0x0BC90BE1 },
         { .reg = 0x00009888, .val = 0x0DC90FF1 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FCFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing15__avg_gpu_core_frequency__max,acmgt2__ray_tracing15__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2871, 24, NULL,acmgt2__ray_tracing15__rt_load_store_cache_read_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2872, 32, NULL,acmgt2__ray_tracing15__rt_load_store_cache_write_from_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2873, 40, NULL,acmgt2__ray_tracing15__rt_traversal_input_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2874, 48, NULL,acmgt2__ray_tracing15__rt_quad_test_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2875, 56, NULL,acmgt2__ray_tracing15__rt_request_collision_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2876, 64, NULL,acmgt2__ray_tracing15__rt_input_message_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2877, 72, percentage_max_float,acmgt2__ray_tracing15__rt_message_stall_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2878, 80, NULL,acmgt2__ray_tracing15__rt_transform_ray_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing16";
   query->symbol_name = "RayTracing16";
   query->guid = "ea6550e2-b1cd-43d9-9f45-79146292d692";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17E57FC0 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x09E51000 },
         { .reg = 0x00009888, .val = 0x19E94740 },
         { .reg = 0x00009888, .val = 0x1FE9023A },
         { .reg = 0x00009888, .val = 0x23E96800 },
         { .reg = 0x00009888, .val = 0x25E90011 },
         { .reg = 0x00009888, .val = 0x29E94740 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x01E400FF },
         { .reg = 0x00009888, .val = 0x03E50B2C },
         { .reg = 0x00009888, .val = 0x0FE50154 },
         { .reg = 0x00009888, .val = 0x11E505D8 },
         { .reg = 0x00009888, .val = 0x13E503CE },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E6AAA0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E903C1 },
         { .reg = 0x00009888, .val = 0x09E907D1 },
         { .reg = 0x00009888, .val = 0x0BE90BE1 },
         { .reg = 0x00009888, .val = 0x0DE90FF1 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing16__avg_gpu_core_frequency__max,acmgt2__ray_tracing16__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2879, 24, NULL,acmgt2__ray_tracing16__rt_load_store_cache_read_message_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2880, 32, NULL,acmgt2__ray_tracing16__rt_load_store_cache_write_from_message_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2881, 40, NULL,acmgt2__ray_tracing16__rt_traversal_input_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2882, 48, NULL,acmgt2__ray_tracing16__rt_quad_test_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2883, 56, NULL,acmgt2__ray_tracing16__rt_request_collision_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2884, 64, NULL,acmgt2__ray_tracing16__rt_input_message_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2885, 72, percentage_max_float,acmgt2__ray_tracing16__rt_message_stall_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2886, 80, NULL,acmgt2__ray_tracing16__rt_transform_ray_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing17";
   query->symbol_name = "RayTracing17";
   query->guid = "d10100fb-ac64-42a1-a418-b03e112ba033";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04858240 },
         { .reg = 0x00009888, .val = 0x06850B28 },
         { .reg = 0x00009888, .val = 0x088508A6 },
         { .reg = 0x00009888, .val = 0x0A850BAA },
         { .reg = 0x00009888, .val = 0x10850BEB },
         { .reg = 0x00009888, .val = 0x128509E3 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing17__avg_gpu_core_frequency__max,acmgt2__ray_tracing17__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1704, 24, NULL,acmgt2__ray_tracing17__rt_instance_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1705, 32, NULL,acmgt2__ray_tracing17__rt_internal_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1706, 40, NULL,acmgt2__ray_tracing17__rt_traversal_step_ray_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing18";
   query->symbol_name = "RayTracing18";
   query->guid = "f140f11f-5b0e-434d-ae88-cf1acd37ab49";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A58240 },
         { .reg = 0x00009888, .val = 0x06A50B28 },
         { .reg = 0x00009888, .val = 0x08A508A6 },
         { .reg = 0x00009888, .val = 0x0AA50BAA },
         { .reg = 0x00009888, .val = 0x10A50BEB },
         { .reg = 0x00009888, .val = 0x12A509E3 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AA00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing18__avg_gpu_core_frequency__max,acmgt2__ray_tracing18__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1707, 24, NULL,acmgt2__ray_tracing18__rt_instance_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1708, 32, NULL,acmgt2__ray_tracing18__rt_internal_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1709, 40, NULL,acmgt2__ray_tracing18__rt_traversal_step_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing19_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing19";
   query->symbol_name = "RayTracing19";
   query->guid = "011f9af3-43c4-45ac-b584-defd44cd442c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C58240 },
         { .reg = 0x00009888, .val = 0x06C50B28 },
         { .reg = 0x00009888, .val = 0x08C508A6 },
         { .reg = 0x00009888, .val = 0x0AC50BAA },
         { .reg = 0x00009888, .val = 0x10C50BEB },
         { .reg = 0x00009888, .val = 0x12C509E3 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AA00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AA00 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing19__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing19__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing19__avg_gpu_core_frequency__max,acmgt2__ray_tracing19__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1710, 24, NULL,acmgt2__ray_tracing19__rt_instance_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1711, 32, NULL,acmgt2__ray_tracing19__rt_internal_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1712, 40, NULL,acmgt2__ray_tracing19__rt_traversal_step_ray_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing20_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing20";
   query->symbol_name = "RayTracing20";
   query->guid = "fd6ea82c-5618-4a96-b4eb-b7d63f72432f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E58240 },
         { .reg = 0x00009888, .val = 0x06E50B28 },
         { .reg = 0x00009888, .val = 0x08E508A6 },
         { .reg = 0x00009888, .val = 0x0AE50BAA },
         { .reg = 0x00009888, .val = 0x10E50BEB },
         { .reg = 0x00009888, .val = 0x12E509E3 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing20__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing20__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing20__avg_gpu_core_frequency__max,acmgt2__ray_tracing20__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1713, 24, NULL,acmgt2__ray_tracing20__rt_instance_node_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1714, 32, NULL,acmgt2__ray_tracing20__rt_internal_node_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1715, 40, NULL,acmgt2__ray_tracing20__rt_traversal_step_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing21";
   query->symbol_name = "RayTracing21";
   query->guid = "cc205019-d6e9-4570-83f7-596dee6615a2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05858240 },
         { .reg = 0x00009888, .val = 0x07850B28 },
         { .reg = 0x00009888, .val = 0x098508A6 },
         { .reg = 0x00009888, .val = 0x0B850BAA },
         { .reg = 0x00009888, .val = 0x11850BEB },
         { .reg = 0x00009888, .val = 0x138509E3 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AA00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing21__avg_gpu_core_frequency__max,acmgt2__ray_tracing21__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1716, 24, NULL,acmgt2__ray_tracing21__rt_instance_node_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1717, 32, NULL,acmgt2__ray_tracing21__rt_internal_node_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1718, 40, NULL,acmgt2__ray_tracing21__rt_traversal_step_ray_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing22";
   query->symbol_name = "RayTracing22";
   query->guid = "14a7e762-a069-46e6-8c2e-6555813c3047";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A58240 },
         { .reg = 0x00009888, .val = 0x07A50B28 },
         { .reg = 0x00009888, .val = 0x09A508A6 },
         { .reg = 0x00009888, .val = 0x0BA50BAA },
         { .reg = 0x00009888, .val = 0x11A50BEB },
         { .reg = 0x00009888, .val = 0x13A509E3 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009888, .val = 0x0101F0FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing22__avg_gpu_core_frequency__max,acmgt2__ray_tracing22__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1719, 24, NULL,acmgt2__ray_tracing22__rt_instance_node_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1720, 32, NULL,acmgt2__ray_tracing22__rt_internal_node_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1721, 40, NULL,acmgt2__ray_tracing22__rt_traversal_step_ray_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing23";
   query->symbol_name = "RayTracing23";
   query->guid = "ce74158a-e893-45a0-acd8-32ff5ac3e64c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C58240 },
         { .reg = 0x00009888, .val = 0x07C50B28 },
         { .reg = 0x00009888, .val = 0x09C508A6 },
         { .reg = 0x00009888, .val = 0x0BC50BAA },
         { .reg = 0x00009888, .val = 0x11C50BEB },
         { .reg = 0x00009888, .val = 0x13C509E3 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AA00 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009888, .val = 0x0102F0FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing23__avg_gpu_core_frequency__max,acmgt2__ray_tracing23__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1722, 24, NULL,acmgt2__ray_tracing23__rt_instance_node_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1723, 32, NULL,acmgt2__ray_tracing23__rt_internal_node_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1724, 40, NULL,acmgt2__ray_tracing23__rt_traversal_step_ray_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing24_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing24";
   query->symbol_name = "RayTracing24";
   query->guid = "cdbdfbe1-d554-4ec9-9eb0-8a03b5ab8e01";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E58240 },
         { .reg = 0x00009888, .val = 0x07E50B28 },
         { .reg = 0x00009888, .val = 0x09E508A6 },
         { .reg = 0x00009888, .val = 0x0BE50BAA },
         { .reg = 0x00009888, .val = 0x11E50BEB },
         { .reg = 0x00009888, .val = 0x13E509E3 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075500 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing24__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing24__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing24__avg_gpu_core_frequency__max,acmgt2__ray_tracing24__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1725, 24, NULL,acmgt2__ray_tracing24__rt_instance_node_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1726, 32, NULL,acmgt2__ray_tracing24__rt_internal_node_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1727, 40, NULL,acmgt2__ray_tracing24__rt_traversal_step_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing25_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing25";
   query->symbol_name = "RayTracing25";
   query->guid = "ff175695-a7d9-4623-9bf2-69b0bd950f3d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04858240 },
         { .reg = 0x00009888, .val = 0x06850B28 },
         { .reg = 0x00009888, .val = 0x088508A6 },
         { .reg = 0x00009888, .val = 0x0A850BAA },
         { .reg = 0x00009888, .val = 0x10850BEB },
         { .reg = 0x00009888, .val = 0x128509E3 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing25__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing25__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing25__avg_gpu_core_frequency__max,acmgt2__ray_tracing25__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2887, 24, NULL,acmgt2__ray_tracing25__rt_instance_node_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2888, 32, NULL,acmgt2__ray_tracing25__rt_internal_node_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2889, 40, NULL,acmgt2__ray_tracing25__rt_traversal_step_ray_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing26_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing26";
   query->symbol_name = "RayTracing26";
   query->guid = "b091df5b-4f20-4c91-a3d5-d2b376810ec2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A58240 },
         { .reg = 0x00009888, .val = 0x06A50B28 },
         { .reg = 0x00009888, .val = 0x08A508A6 },
         { .reg = 0x00009888, .val = 0x0AA50BAA },
         { .reg = 0x00009888, .val = 0x10A50BEB },
         { .reg = 0x00009888, .val = 0x12A509E3 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AA00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing26__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing26__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing26__avg_gpu_core_frequency__max,acmgt2__ray_tracing26__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2890, 24, NULL,acmgt2__ray_tracing26__rt_instance_node_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2891, 32, NULL,acmgt2__ray_tracing26__rt_internal_node_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2892, 40, NULL,acmgt2__ray_tracing26__rt_traversal_step_ray_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing27_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing27";
   query->symbol_name = "RayTracing27";
   query->guid = "54634c6d-3ef3-4cd8-b80d-9642867ff9de";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C58240 },
         { .reg = 0x00009888, .val = 0x06C50B28 },
         { .reg = 0x00009888, .val = 0x08C508A6 },
         { .reg = 0x00009888, .val = 0x0AC50BAA },
         { .reg = 0x00009888, .val = 0x10C50BEB },
         { .reg = 0x00009888, .val = 0x12C509E3 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AA00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AA00 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing27__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing27__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing27__avg_gpu_core_frequency__max,acmgt2__ray_tracing27__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2893, 24, NULL,acmgt2__ray_tracing27__rt_instance_node_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2894, 32, NULL,acmgt2__ray_tracing27__rt_internal_node_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2895, 40, NULL,acmgt2__ray_tracing27__rt_traversal_step_ray_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing28";
   query->symbol_name = "RayTracing28";
   query->guid = "284d68a1-6924-4746-8ac1-8e94a116be75";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E58240 },
         { .reg = 0x00009888, .val = 0x06E50B28 },
         { .reg = 0x00009888, .val = 0x08E508A6 },
         { .reg = 0x00009888, .val = 0x0AE50BAA },
         { .reg = 0x00009888, .val = 0x10E50BEB },
         { .reg = 0x00009888, .val = 0x12E509E3 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing28__avg_gpu_core_frequency__max,acmgt2__ray_tracing28__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2896, 24, NULL,acmgt2__ray_tracing28__rt_instance_node_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2897, 32, NULL,acmgt2__ray_tracing28__rt_internal_node_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2898, 40, NULL,acmgt2__ray_tracing28__rt_traversal_step_ray_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing29_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing29";
   query->symbol_name = "RayTracing29";
   query->guid = "8129227a-30cf-40cc-85ea-95614a31975a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05858240 },
         { .reg = 0x00009888, .val = 0x07850B28 },
         { .reg = 0x00009888, .val = 0x098508A6 },
         { .reg = 0x00009888, .val = 0x0B850BAA },
         { .reg = 0x00009888, .val = 0x11850BEB },
         { .reg = 0x00009888, .val = 0x138509E3 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AA00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing29__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing29__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing29__avg_gpu_core_frequency__max,acmgt2__ray_tracing29__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2899, 24, NULL,acmgt2__ray_tracing29__rt_instance_node_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2900, 32, NULL,acmgt2__ray_tracing29__rt_internal_node_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2901, 40, NULL,acmgt2__ray_tracing29__rt_traversal_step_ray_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing30_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing30";
   query->symbol_name = "RayTracing30";
   query->guid = "4de4fb3e-bd28-4e5a-8fd8-01ca378184ce";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A58240 },
         { .reg = 0x00009888, .val = 0x07A50B28 },
         { .reg = 0x00009888, .val = 0x09A508A6 },
         { .reg = 0x00009888, .val = 0x0BA50BAA },
         { .reg = 0x00009888, .val = 0x11A50BEB },
         { .reg = 0x00009888, .val = 0x13A509E3 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009888, .val = 0x0101F0FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing30__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing30__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing30__avg_gpu_core_frequency__max,acmgt2__ray_tracing30__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2902, 24, NULL,acmgt2__ray_tracing30__rt_instance_node_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2903, 32, NULL,acmgt2__ray_tracing30__rt_internal_node_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2904, 40, NULL,acmgt2__ray_tracing30__rt_traversal_step_ray_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing31";
   query->symbol_name = "RayTracing31";
   query->guid = "5acdb2be-3918-4eed-9bc5-f272bc175a3f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C58240 },
         { .reg = 0x00009888, .val = 0x07C50B28 },
         { .reg = 0x00009888, .val = 0x09C508A6 },
         { .reg = 0x00009888, .val = 0x0BC50BAA },
         { .reg = 0x00009888, .val = 0x11C50BEB },
         { .reg = 0x00009888, .val = 0x13C509E3 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AA00 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009888, .val = 0x0102F0FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing31__avg_gpu_core_frequency__max,acmgt2__ray_tracing31__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2905, 24, NULL,acmgt2__ray_tracing31__rt_instance_node_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2906, 32, NULL,acmgt2__ray_tracing31__rt_internal_node_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2907, 40, NULL,acmgt2__ray_tracing31__rt_traversal_step_ray_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing32_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "RayTracing32";
   query->symbol_name = "RayTracing32";
   query->guid = "10125720-3004-4838-8a03-24fff2d9fb06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E58240 },
         { .reg = 0x00009888, .val = 0x07E50B28 },
         { .reg = 0x00009888, .val = 0x09E508A6 },
         { .reg = 0x00009888, .val = 0x0BE50BAA },
         { .reg = 0x00009888, .val = 0x11E50BEB },
         { .reg = 0x00009888, .val = 0x13E509E3 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075500 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing32__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing32__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing32__avg_gpu_core_frequency__max,acmgt2__ray_tracing32__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2908, 24, NULL,acmgt2__ray_tracing32__rt_instance_node_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2909, 32, NULL,acmgt2__ray_tracing32__rt_internal_node_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2910, 40, NULL,acmgt2__ray_tracing32__rt_traversal_step_ray_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing33_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing33";
   query->symbol_name = "RayTracing33";
   query->guid = "b1e299f2-35c3-4954-8cce-4fd1dd2491db";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04859A70 },
         { .reg = 0x00009888, .val = 0x06850925 },
         { .reg = 0x00009888, .val = 0x088508A3 },
         { .reg = 0x00009888, .val = 0x0A850821 },
         { .reg = 0x00009888, .val = 0x0C850BAF },
         { .reg = 0x00009888, .val = 0x0E850B2D },
         { .reg = 0x00009888, .val = 0x10850AAB },
         { .reg = 0x00009888, .val = 0x12850A29 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AAAA },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing33__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing33__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing33__avg_gpu_core_frequency__max,acmgt2__ray_tracing33__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1728, 24, NULL,acmgt2__ray_tracing33__rt_quad_leaf_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1729, 32, NULL,acmgt2__ray_tracing33__rt_procedural_node_ray_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing34_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing34";
   query->symbol_name = "RayTracing34";
   query->guid = "bf47e090-9786-47b2-bf6d-746b7970001e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A59A70 },
         { .reg = 0x00009888, .val = 0x06A50925 },
         { .reg = 0x00009888, .val = 0x08A508A3 },
         { .reg = 0x00009888, .val = 0x0AA50821 },
         { .reg = 0x00009888, .val = 0x0CA50BAF },
         { .reg = 0x00009888, .val = 0x0EA50B2D },
         { .reg = 0x00009888, .val = 0x10A50AAB },
         { .reg = 0x00009888, .val = 0x12A50A29 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AAAA },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing34__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing34__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing34__avg_gpu_core_frequency__max,acmgt2__ray_tracing34__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1730, 24, NULL,acmgt2__ray_tracing34__rt_quad_leaf_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1731, 32, NULL,acmgt2__ray_tracing34__rt_procedural_node_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing35";
   query->symbol_name = "RayTracing35";
   query->guid = "df706146-44af-46d0-9ce4-0af556b009e3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C59A70 },
         { .reg = 0x00009888, .val = 0x06C50925 },
         { .reg = 0x00009888, .val = 0x08C508A3 },
         { .reg = 0x00009888, .val = 0x0AC50821 },
         { .reg = 0x00009888, .val = 0x0CC50BAF },
         { .reg = 0x00009888, .val = 0x0EC50B2D },
         { .reg = 0x00009888, .val = 0x10C50AAB },
         { .reg = 0x00009888, .val = 0x12C50A29 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AAAA },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing35__avg_gpu_core_frequency__max,acmgt2__ray_tracing35__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1732, 24, NULL,acmgt2__ray_tracing35__rt_quad_leaf_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1733, 32, NULL,acmgt2__ray_tracing35__rt_procedural_node_ray_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing36_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing36";
   query->symbol_name = "RayTracing36";
   query->guid = "d1e152cd-ef8e-48c0-b63c-421e17083a0a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E59A70 },
         { .reg = 0x00009888, .val = 0x06E50925 },
         { .reg = 0x00009888, .val = 0x08E508A3 },
         { .reg = 0x00009888, .val = 0x0AE50821 },
         { .reg = 0x00009888, .val = 0x0CE50BAF },
         { .reg = 0x00009888, .val = 0x0EE50B2D },
         { .reg = 0x00009888, .val = 0x10E50AAB },
         { .reg = 0x00009888, .val = 0x12E50A29 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AAAA },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing36__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing36__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing36__avg_gpu_core_frequency__max,acmgt2__ray_tracing36__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1734, 24, NULL,acmgt2__ray_tracing36__rt_quad_leaf_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1735, 32, NULL,acmgt2__ray_tracing36__rt_procedural_node_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing37_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing37";
   query->symbol_name = "RayTracing37";
   query->guid = "e5cdc5f8-81f8-442c-a0c2-b94621efc7be";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05859A70 },
         { .reg = 0x00009888, .val = 0x07850925 },
         { .reg = 0x00009888, .val = 0x098508A3 },
         { .reg = 0x00009888, .val = 0x0B850821 },
         { .reg = 0x00009888, .val = 0x0D850BAF },
         { .reg = 0x00009888, .val = 0x0F850B2D },
         { .reg = 0x00009888, .val = 0x11850AAB },
         { .reg = 0x00009888, .val = 0x13850A29 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing37__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing37__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing37__avg_gpu_core_frequency__max,acmgt2__ray_tracing37__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1736, 24, NULL,acmgt2__ray_tracing37__rt_quad_leaf_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1737, 32, NULL,acmgt2__ray_tracing37__rt_procedural_node_ray_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing38_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing38";
   query->symbol_name = "RayTracing38";
   query->guid = "6604e545-3a89-4f6e-a697-65b1f5bcb306";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A59A70 },
         { .reg = 0x00009888, .val = 0x07A50925 },
         { .reg = 0x00009888, .val = 0x09A508A3 },
         { .reg = 0x00009888, .val = 0x0BA50821 },
         { .reg = 0x00009888, .val = 0x0DA50BAF },
         { .reg = 0x00009888, .val = 0x0FA50B2D },
         { .reg = 0x00009888, .val = 0x11A50AAB },
         { .reg = 0x00009888, .val = 0x13A50A29 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing38__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing38__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing38__avg_gpu_core_frequency__max,acmgt2__ray_tracing38__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1738, 24, NULL,acmgt2__ray_tracing38__rt_quad_leaf_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1739, 32, NULL,acmgt2__ray_tracing38__rt_procedural_node_ray_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing39";
   query->symbol_name = "RayTracing39";
   query->guid = "3b7d7a01-6242-4544-b68b-54eb4b2f59d7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C59A70 },
         { .reg = 0x00009888, .val = 0x07C50925 },
         { .reg = 0x00009888, .val = 0x09C508A3 },
         { .reg = 0x00009888, .val = 0x0BC50821 },
         { .reg = 0x00009888, .val = 0x0DC50BAF },
         { .reg = 0x00009888, .val = 0x0FC50B2D },
         { .reg = 0x00009888, .val = 0x11C50AAB },
         { .reg = 0x00009888, .val = 0x13C50A29 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing39__avg_gpu_core_frequency__max,acmgt2__ray_tracing39__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1740, 24, NULL,acmgt2__ray_tracing39__rt_quad_leaf_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1741, 32, NULL,acmgt2__ray_tracing39__rt_procedural_node_ray_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing40_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing40";
   query->symbol_name = "RayTracing40";
   query->guid = "d7617e5d-23ae-482f-95fe-ae8615cf9172";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E59A70 },
         { .reg = 0x00009888, .val = 0x07E50925 },
         { .reg = 0x00009888, .val = 0x09E508A3 },
         { .reg = 0x00009888, .val = 0x0BE50821 },
         { .reg = 0x00009888, .val = 0x0DE50BAF },
         { .reg = 0x00009888, .val = 0x0FE50B2D },
         { .reg = 0x00009888, .val = 0x11E50AAB },
         { .reg = 0x00009888, .val = 0x13E50A29 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing40__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing40__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing40__avg_gpu_core_frequency__max,acmgt2__ray_tracing40__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1742, 24, NULL,acmgt2__ray_tracing40__rt_quad_leaf_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1743, 32, NULL,acmgt2__ray_tracing40__rt_procedural_node_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing41_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing41";
   query->symbol_name = "RayTracing41";
   query->guid = "f8410bd7-acba-4fd2-a2f4-9bec43057129";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04859A70 },
         { .reg = 0x00009888, .val = 0x06850925 },
         { .reg = 0x00009888, .val = 0x088508A3 },
         { .reg = 0x00009888, .val = 0x0A850821 },
         { .reg = 0x00009888, .val = 0x0C850BAF },
         { .reg = 0x00009888, .val = 0x0E850B2D },
         { .reg = 0x00009888, .val = 0x10850AAB },
         { .reg = 0x00009888, .val = 0x12850A29 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AAAA },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing41__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing41__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing41__avg_gpu_core_frequency__max,acmgt2__ray_tracing41__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2911, 24, NULL,acmgt2__ray_tracing41__rt_quad_leaf_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2912, 32, NULL,acmgt2__ray_tracing41__rt_procedural_node_ray_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing42_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing42";
   query->symbol_name = "RayTracing42";
   query->guid = "c7cf55e8-7633-424a-a524-78c46698b5b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A59A70 },
         { .reg = 0x00009888, .val = 0x06A50925 },
         { .reg = 0x00009888, .val = 0x08A508A3 },
         { .reg = 0x00009888, .val = 0x0AA50821 },
         { .reg = 0x00009888, .val = 0x0CA50BAF },
         { .reg = 0x00009888, .val = 0x0EA50B2D },
         { .reg = 0x00009888, .val = 0x10A50AAB },
         { .reg = 0x00009888, .val = 0x12A50A29 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AAAA },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing42__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing42__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing42__avg_gpu_core_frequency__max,acmgt2__ray_tracing42__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2913, 24, NULL,acmgt2__ray_tracing42__rt_quad_leaf_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2914, 32, NULL,acmgt2__ray_tracing42__rt_procedural_node_ray_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing43_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing43";
   query->symbol_name = "RayTracing43";
   query->guid = "5f5c6ff1-c38b-4b0a-bba9-187d65965cbd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C59A70 },
         { .reg = 0x00009888, .val = 0x06C50925 },
         { .reg = 0x00009888, .val = 0x08C508A3 },
         { .reg = 0x00009888, .val = 0x0AC50821 },
         { .reg = 0x00009888, .val = 0x0CC50BAF },
         { .reg = 0x00009888, .val = 0x0EC50B2D },
         { .reg = 0x00009888, .val = 0x10C50AAB },
         { .reg = 0x00009888, .val = 0x12C50A29 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AAAA },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing43__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing43__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing43__avg_gpu_core_frequency__max,acmgt2__ray_tracing43__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2915, 24, NULL,acmgt2__ray_tracing43__rt_quad_leaf_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2916, 32, NULL,acmgt2__ray_tracing43__rt_procedural_node_ray_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing44_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing44";
   query->symbol_name = "RayTracing44";
   query->guid = "eeb417cc-d7ff-4713-92c8-dac7f5cf865d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E59A70 },
         { .reg = 0x00009888, .val = 0x06E50925 },
         { .reg = 0x00009888, .val = 0x08E508A3 },
         { .reg = 0x00009888, .val = 0x0AE50821 },
         { .reg = 0x00009888, .val = 0x0CE50BAF },
         { .reg = 0x00009888, .val = 0x0EE50B2D },
         { .reg = 0x00009888, .val = 0x10E50AAB },
         { .reg = 0x00009888, .val = 0x12E50A29 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AAAA },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing44__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing44__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing44__avg_gpu_core_frequency__max,acmgt2__ray_tracing44__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2917, 24, NULL,acmgt2__ray_tracing44__rt_quad_leaf_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2918, 32, NULL,acmgt2__ray_tracing44__rt_procedural_node_ray_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing45";
   query->symbol_name = "RayTracing45";
   query->guid = "e7b14d21-de4f-46e5-9be9-619f8d0cac25";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05859A70 },
         { .reg = 0x00009888, .val = 0x07850925 },
         { .reg = 0x00009888, .val = 0x098508A3 },
         { .reg = 0x00009888, .val = 0x0B850821 },
         { .reg = 0x00009888, .val = 0x0D850BAF },
         { .reg = 0x00009888, .val = 0x0F850B2D },
         { .reg = 0x00009888, .val = 0x11850AAB },
         { .reg = 0x00009888, .val = 0x13850A29 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing45__avg_gpu_core_frequency__max,acmgt2__ray_tracing45__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2919, 24, NULL,acmgt2__ray_tracing45__rt_quad_leaf_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2920, 32, NULL,acmgt2__ray_tracing45__rt_procedural_node_ray_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing46_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing46";
   query->symbol_name = "RayTracing46";
   query->guid = "243b4356-4036-42c6-bec9-40c9f2c15bb0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A59A70 },
         { .reg = 0x00009888, .val = 0x07A50925 },
         { .reg = 0x00009888, .val = 0x09A508A3 },
         { .reg = 0x00009888, .val = 0x0BA50821 },
         { .reg = 0x00009888, .val = 0x0DA50BAF },
         { .reg = 0x00009888, .val = 0x0FA50B2D },
         { .reg = 0x00009888, .val = 0x11A50AAB },
         { .reg = 0x00009888, .val = 0x13A50A29 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing46__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing46__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing46__avg_gpu_core_frequency__max,acmgt2__ray_tracing46__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2921, 24, NULL,acmgt2__ray_tracing46__rt_quad_leaf_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2922, 32, NULL,acmgt2__ray_tracing46__rt_procedural_node_ray_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing47_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing47";
   query->symbol_name = "RayTracing47";
   query->guid = "c1961a4a-56fa-4693-88f8-24c7c58f37fb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C59A70 },
         { .reg = 0x00009888, .val = 0x07C50925 },
         { .reg = 0x00009888, .val = 0x09C508A3 },
         { .reg = 0x00009888, .val = 0x0BC50821 },
         { .reg = 0x00009888, .val = 0x0DC50BAF },
         { .reg = 0x00009888, .val = 0x0FC50B2D },
         { .reg = 0x00009888, .val = 0x11C50AAB },
         { .reg = 0x00009888, .val = 0x13C50A29 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing47__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing47__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing47__avg_gpu_core_frequency__max,acmgt2__ray_tracing47__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2923, 24, NULL,acmgt2__ray_tracing47__rt_quad_leaf_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2924, 32, NULL,acmgt2__ray_tracing47__rt_procedural_node_ray_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing48_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "RayTracing48";
   query->symbol_name = "RayTracing48";
   query->guid = "0c4634e5-207a-4f8d-afd0-b7ee705e9a1c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E59A70 },
         { .reg = 0x00009888, .val = 0x07E50925 },
         { .reg = 0x00009888, .val = 0x09E508A3 },
         { .reg = 0x00009888, .val = 0x0BE50821 },
         { .reg = 0x00009888, .val = 0x0DE50BAF },
         { .reg = 0x00009888, .val = 0x0FE50B2D },
         { .reg = 0x00009888, .val = 0x11E50AAB },
         { .reg = 0x00009888, .val = 0x13E50A29 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing48__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing48__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing48__avg_gpu_core_frequency__max,acmgt2__ray_tracing48__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2925, 24, NULL,acmgt2__ray_tracing48__rt_quad_leaf_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2926, 32, NULL,acmgt2__ray_tracing48__rt_procedural_node_ray_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing49_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing49";
   query->symbol_name = "RayTracing49";
   query->guid = "3983a842-c461-43e4-86be-43f74d1fc1fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8545E0 },
         { .reg = 0x00009888, .val = 0x1EA545E0 },
         { .reg = 0x00009888, .val = 0x1EC545E0 },
         { .reg = 0x00009888, .val = 0x1EE545E0 },
         { .reg = 0x00009888, .val = 0x0485C70E },
         { .reg = 0x00009888, .val = 0x06850E78 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50C70 },
         { .reg = 0x00009888, .val = 0x0AA50E78 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50C70 },
         { .reg = 0x00009888, .val = 0x0EC50E78 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50C70 },
         { .reg = 0x00009888, .val = 0x12E50E78 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing49__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing49__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing49__avg_gpu_core_frequency__max,acmgt2__ray_tracing49__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1544, 24, NULL,acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1545, 32, NULL,acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1546, 40, NULL,acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1547, 48, NULL,acmgt2__ray_tracing49__rt_traversal_output_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing50_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing50";
   query->symbol_name = "RayTracing50";
   query->guid = "8da1e755-69e8-4c30-9d55-317dbd8c843b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8545E0 },
         { .reg = 0x00009888, .val = 0x1FA545E0 },
         { .reg = 0x00009888, .val = 0x1FC545E0 },
         { .reg = 0x00009888, .val = 0x1FE545E0 },
         { .reg = 0x00009888, .val = 0x0585C70E },
         { .reg = 0x00009888, .val = 0x07850E78 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50C70 },
         { .reg = 0x00009888, .val = 0x0BA50E78 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50C70 },
         { .reg = 0x00009888, .val = 0x0FC50E78 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50C70 },
         { .reg = 0x00009888, .val = 0x13E50E78 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing50__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing50__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing50__avg_gpu_core_frequency__max,acmgt2__ray_tracing50__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1548, 24, NULL,acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1549, 32, NULL,acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1550, 40, NULL,acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1551, 48, NULL,acmgt2__ray_tracing50__rt_traversal_output_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing51_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing51";
   query->symbol_name = "RayTracing51";
   query->guid = "95175ccf-d7f5-47cd-aa92-3598fc431169";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8545E0 },
         { .reg = 0x00009888, .val = 0x1EA545E0 },
         { .reg = 0x00009888, .val = 0x1EC545E0 },
         { .reg = 0x00009888, .val = 0x1EE545E0 },
         { .reg = 0x00009888, .val = 0x0485C70E },
         { .reg = 0x00009888, .val = 0x06850E78 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50C70 },
         { .reg = 0x00009888, .val = 0x0AA50E78 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50C70 },
         { .reg = 0x00009888, .val = 0x0EC50E78 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50C70 },
         { .reg = 0x00009888, .val = 0x12E50E78 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing51__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing51__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing51__avg_gpu_core_frequency__max,acmgt2__ray_tracing51__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2927, 24, NULL,acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2928, 32, NULL,acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2929, 40, NULL,acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2930, 48, NULL,acmgt2__ray_tracing51__rt_traversal_output_ray_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing52_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing52";
   query->symbol_name = "RayTracing52";
   query->guid = "d2d43104-87a6-4fe2-9979-5469dd33f9fd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8545E0 },
         { .reg = 0x00009888, .val = 0x1FA545E0 },
         { .reg = 0x00009888, .val = 0x1FC545E0 },
         { .reg = 0x00009888, .val = 0x1FE545E0 },
         { .reg = 0x00009888, .val = 0x0585C70E },
         { .reg = 0x00009888, .val = 0x07850E78 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50C70 },
         { .reg = 0x00009888, .val = 0x0BA50E78 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50C70 },
         { .reg = 0x00009888, .val = 0x0FC50E78 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50C70 },
         { .reg = 0x00009888, .val = 0x13E50E78 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing52__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing52__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing52__avg_gpu_core_frequency__max,acmgt2__ray_tracing52__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2931, 24, NULL,acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2932, 32, NULL,acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2933, 40, NULL,acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2934, 48, NULL,acmgt2__ray_tracing52__rt_traversal_output_ray_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing53_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing53";
   query->symbol_name = "RayTracing53";
   query->guid = "a51b5ede-d663-45a2-8ce1-f19dc664a936";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D37E },
         { .reg = 0x00009888, .val = 0x06850F3F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D37 },
         { .reg = 0x00009888, .val = 0x0AA50F3F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D37 },
         { .reg = 0x00009888, .val = 0x0EC50F3F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D37 },
         { .reg = 0x00009888, .val = 0x12E50F3F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing53__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing53__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing53__avg_gpu_core_frequency__max,acmgt2__ray_tracing53__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1520, 24, NULL,acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1521, 32, NULL,acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1522, 40, NULL,acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1523, 48, NULL,acmgt2__ray_tracing53__rt_any_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing54_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing54";
   query->symbol_name = "RayTracing54";
   query->guid = "25676609-7d64-47ca-b92c-9128a9907f65";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D37E },
         { .reg = 0x00009888, .val = 0x07850F3F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D37 },
         { .reg = 0x00009888, .val = 0x0BA50F3F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D37 },
         { .reg = 0x00009888, .val = 0x0FC50F3F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D37 },
         { .reg = 0x00009888, .val = 0x13E50F3F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing54__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing54__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing54__avg_gpu_core_frequency__max,acmgt2__ray_tracing54__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1524, 24, NULL,acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1525, 32, NULL,acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1526, 40, NULL,acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1527, 48, NULL,acmgt2__ray_tracing54__rt_any_hit_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing55_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing55";
   query->symbol_name = "RayTracing55";
   query->guid = "1edc6759-9642-442c-9aa6-850ca7715097";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D37E },
         { .reg = 0x00009888, .val = 0x06850F3F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D37 },
         { .reg = 0x00009888, .val = 0x0AA50F3F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D37 },
         { .reg = 0x00009888, .val = 0x0EC50F3F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D37 },
         { .reg = 0x00009888, .val = 0x12E50F3F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing55__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing55__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing55__avg_gpu_core_frequency__max,acmgt2__ray_tracing55__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2935, 24, NULL,acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2936, 32, NULL,acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2937, 40, NULL,acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2938, 48, NULL,acmgt2__ray_tracing55__rt_any_hit_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing56_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing56";
   query->symbol_name = "RayTracing56";
   query->guid = "ecf6d5e1-928c-49dc-868b-89893073c183";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D37E },
         { .reg = 0x00009888, .val = 0x07850F3F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D37 },
         { .reg = 0x00009888, .val = 0x0BA50F3F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D37 },
         { .reg = 0x00009888, .val = 0x0FC50F3F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D37 },
         { .reg = 0x00009888, .val = 0x13E50F3F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing56__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing56__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing56__avg_gpu_core_frequency__max,acmgt2__ray_tracing56__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2939, 24, NULL,acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2940, 32, NULL,acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2941, 40, NULL,acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2942, 48, NULL,acmgt2__ray_tracing56__rt_any_hit_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing57_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing57";
   query->symbol_name = "RayTracing57";
   query->guid = "f8998902-7ceb-46ca-a62b-881dca4ff1f6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CB7E },
         { .reg = 0x00009888, .val = 0x06850EBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CB7 },
         { .reg = 0x00009888, .val = 0x0AA50EBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CB7 },
         { .reg = 0x00009888, .val = 0x0EC50EBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CB7 },
         { .reg = 0x00009888, .val = 0x12E50EBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing57__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing57__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing57__avg_gpu_core_frequency__max,acmgt2__ray_tracing57__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1536, 24, NULL,acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1537, 32, NULL,acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1538, 40, NULL,acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1539, 48, NULL,acmgt2__ray_tracing57__rt_callable_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing58_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing58";
   query->symbol_name = "RayTracing58";
   query->guid = "b7b90bb9-b0b5-428d-a175-d9c89ecd35d1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CB7E },
         { .reg = 0x00009888, .val = 0x07850EBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CB7 },
         { .reg = 0x00009888, .val = 0x0BA50EBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CB7 },
         { .reg = 0x00009888, .val = 0x0FC50EBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CB7 },
         { .reg = 0x00009888, .val = 0x13E50EBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing58__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing58__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing58__avg_gpu_core_frequency__max,acmgt2__ray_tracing58__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1540, 24, NULL,acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1541, 32, NULL,acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1542, 40, NULL,acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1543, 48, NULL,acmgt2__ray_tracing58__rt_callable_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing59_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing59";
   query->symbol_name = "RayTracing59";
   query->guid = "f7cd6361-0226-4e03-8856-cf375bd1264d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CB7E },
         { .reg = 0x00009888, .val = 0x06850EBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CB7 },
         { .reg = 0x00009888, .val = 0x0AA50EBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CB7 },
         { .reg = 0x00009888, .val = 0x0EC50EBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CB7 },
         { .reg = 0x00009888, .val = 0x12E50EBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing59__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing59__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing59__avg_gpu_core_frequency__max,acmgt2__ray_tracing59__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2943, 24, NULL,acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2944, 32, NULL,acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2945, 40, NULL,acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2946, 48, NULL,acmgt2__ray_tracing59__rt_callable_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing60_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing60";
   query->symbol_name = "RayTracing60";
   query->guid = "945822ee-5469-4db5-b86e-c5f5255ac9fe";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CB7E },
         { .reg = 0x00009888, .val = 0x07850EBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CB7 },
         { .reg = 0x00009888, .val = 0x0BA50EBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CB7 },
         { .reg = 0x00009888, .val = 0x0FC50EBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CB7 },
         { .reg = 0x00009888, .val = 0x13E50EBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing60__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing60__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing60__avg_gpu_core_frequency__max,acmgt2__ray_tracing60__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2947, 24, NULL,acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2948, 32, NULL,acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2949, 40, NULL,acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2950, 48, NULL,acmgt2__ray_tracing60__rt_callable_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing61_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing61";
   query->symbol_name = "RayTracing61";
   query->guid = "8cd0af0d-1298-4414-aa94-5e13b6083af2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D77E },
         { .reg = 0x00009888, .val = 0x06850F7F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D77 },
         { .reg = 0x00009888, .val = 0x0AA50F7F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D77 },
         { .reg = 0x00009888, .val = 0x0EC50F7F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D77 },
         { .reg = 0x00009888, .val = 0x12E50F7F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing61__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing61__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing61__avg_gpu_core_frequency__max,acmgt2__ray_tracing61__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1504, 24, NULL,acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1505, 32, NULL,acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1506, 40, NULL,acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1507, 48, NULL,acmgt2__ray_tracing61__rt_closest_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing62_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing62";
   query->symbol_name = "RayTracing62";
   query->guid = "bb7ccc48-ff70-4ec5-a35d-9b77ca79034a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D77E },
         { .reg = 0x00009888, .val = 0x07850F7F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D77 },
         { .reg = 0x00009888, .val = 0x0BA50F7F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D77 },
         { .reg = 0x00009888, .val = 0x0FC50F7F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D77 },
         { .reg = 0x00009888, .val = 0x13E50F7F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing62__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing62__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing62__avg_gpu_core_frequency__max,acmgt2__ray_tracing62__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1508, 24, NULL,acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1509, 32, NULL,acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1510, 40, NULL,acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1511, 48, NULL,acmgt2__ray_tracing62__rt_closest_hit_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing63_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing63";
   query->symbol_name = "RayTracing63";
   query->guid = "f4c111b5-6f5f-4109-9887-0968ddb7901e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D77E },
         { .reg = 0x00009888, .val = 0x06850F7F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D77 },
         { .reg = 0x00009888, .val = 0x0AA50F7F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D77 },
         { .reg = 0x00009888, .val = 0x0EC50F7F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D77 },
         { .reg = 0x00009888, .val = 0x12E50F7F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing63__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing63__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing63__avg_gpu_core_frequency__max,acmgt2__ray_tracing63__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2951, 24, NULL,acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2952, 32, NULL,acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2953, 40, NULL,acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2954, 48, NULL,acmgt2__ray_tracing63__rt_closest_hit_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing64_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing64";
   query->symbol_name = "RayTracing64";
   query->guid = "dd2c9174-67a1-4114-a71e-921548e9a033";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D77E },
         { .reg = 0x00009888, .val = 0x07850F7F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D77 },
         { .reg = 0x00009888, .val = 0x0BA50F7F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D77 },
         { .reg = 0x00009888, .val = 0x0FC50F7F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D77 },
         { .reg = 0x00009888, .val = 0x13E50F7F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing64__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing64__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing64__avg_gpu_core_frequency__max,acmgt2__ray_tracing64__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2955, 24, NULL,acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2956, 32, NULL,acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2957, 40, NULL,acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2958, 48, NULL,acmgt2__ray_tracing64__rt_closest_hit_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing65_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing65";
   query->symbol_name = "RayTracing65";
   query->guid = "1a5ef45d-9d6c-4cde-804f-bdd054d2527a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CF7E },
         { .reg = 0x00009888, .val = 0x06850EFF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CF7 },
         { .reg = 0x00009888, .val = 0x0AA50EFF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CF7 },
         { .reg = 0x00009888, .val = 0x0EC50EFF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CF7 },
         { .reg = 0x00009888, .val = 0x12E50EFF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing65__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing65__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing65__avg_gpu_core_frequency__max,acmgt2__ray_tracing65__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1528, 24, NULL,acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1529, 32, NULL,acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1530, 40, NULL,acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1531, 48, NULL,acmgt2__ray_tracing65__rt_intersection_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing66_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing66";
   query->symbol_name = "RayTracing66";
   query->guid = "fa54a0b0-a5d0-4423-97c3-37cc477cbcca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CF7E },
         { .reg = 0x00009888, .val = 0x07850EFF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CF7 },
         { .reg = 0x00009888, .val = 0x0BA50EFF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CF7 },
         { .reg = 0x00009888, .val = 0x0FC50EFF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CF7 },
         { .reg = 0x00009888, .val = 0x13E50EFF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing66__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing66__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing66__avg_gpu_core_frequency__max,acmgt2__ray_tracing66__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1532, 24, NULL,acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1533, 32, NULL,acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1534, 40, NULL,acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1535, 48, NULL,acmgt2__ray_tracing66__rt_intersection_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing67_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing67";
   query->symbol_name = "RayTracing67";
   query->guid = "1efaa5e7-98d8-4752-8111-3b293d46b884";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CF7E },
         { .reg = 0x00009888, .val = 0x06850EFF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CF7 },
         { .reg = 0x00009888, .val = 0x0AA50EFF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CF7 },
         { .reg = 0x00009888, .val = 0x0EC50EFF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CF7 },
         { .reg = 0x00009888, .val = 0x12E50EFF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing67__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing67__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing67__avg_gpu_core_frequency__max,acmgt2__ray_tracing67__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2959, 24, NULL,acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2960, 32, NULL,acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2961, 40, NULL,acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2962, 48, NULL,acmgt2__ray_tracing67__rt_intersection_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing68_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing68";
   query->symbol_name = "RayTracing68";
   query->guid = "046afd23-c347-4139-9768-ced28fb81d81";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CF7E },
         { .reg = 0x00009888, .val = 0x07850EFF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CF7 },
         { .reg = 0x00009888, .val = 0x0BA50EFF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CF7 },
         { .reg = 0x00009888, .val = 0x0FC50EFF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CF7 },
         { .reg = 0x00009888, .val = 0x13E50EFF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing68__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing68__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing68__avg_gpu_core_frequency__max,acmgt2__ray_tracing68__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2963, 24, NULL,acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2964, 32, NULL,acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2965, 40, NULL,acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2966, 48, NULL,acmgt2__ray_tracing68__rt_intersection_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing69_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing69";
   query->symbol_name = "RayTracing69";
   query->guid = "7b00995c-f689-4a8a-862d-6391ffa9ceee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485DB7E },
         { .reg = 0x00009888, .val = 0x06850FBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50DB7 },
         { .reg = 0x00009888, .val = 0x0AA50FBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50DB7 },
         { .reg = 0x00009888, .val = 0x0EC50FBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50DB7 },
         { .reg = 0x00009888, .val = 0x12E50FBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing69__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing69__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing69__avg_gpu_core_frequency__max,acmgt2__ray_tracing69__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1512, 24, NULL,acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1513, 32, NULL,acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1514, 40, NULL,acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1515, 48, NULL,acmgt2__ray_tracing69__rt_miss_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing70_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing70";
   query->symbol_name = "RayTracing70";
   query->guid = "981e8cee-e786-42de-9ca0-2ffbf6eb4ed1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585DB7E },
         { .reg = 0x00009888, .val = 0x07850FBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50DB7 },
         { .reg = 0x00009888, .val = 0x0BA50FBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50DB7 },
         { .reg = 0x00009888, .val = 0x0FC50FBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50DB7 },
         { .reg = 0x00009888, .val = 0x13E50FBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing70__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing70__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing70__avg_gpu_core_frequency__max,acmgt2__ray_tracing70__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1516, 24, NULL,acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1517, 32, NULL,acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1518, 40, NULL,acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1519, 48, NULL,acmgt2__ray_tracing70__rt_miss_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing71_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing71";
   query->symbol_name = "RayTracing71";
   query->guid = "b02dcfab-bb8d-4327-ae9f-677412a38645";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485DB7E },
         { .reg = 0x00009888, .val = 0x06850FBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50DB7 },
         { .reg = 0x00009888, .val = 0x0AA50FBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50DB7 },
         { .reg = 0x00009888, .val = 0x0EC50FBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50DB7 },
         { .reg = 0x00009888, .val = 0x12E50FBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing71__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing71__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing71__avg_gpu_core_frequency__max,acmgt2__ray_tracing71__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2967, 24, NULL,acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2968, 32, NULL,acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2969, 40, NULL,acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2970, 48, NULL,acmgt2__ray_tracing71__rt_miss_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing72_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing72";
   query->symbol_name = "RayTracing72";
   query->guid = "87ae14d2-1266-4939-a094-0b69e0b7f171";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585DB7E },
         { .reg = 0x00009888, .val = 0x07850FBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50DB7 },
         { .reg = 0x00009888, .val = 0x0BA50FBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50DB7 },
         { .reg = 0x00009888, .val = 0x0FC50FBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50DB7 },
         { .reg = 0x00009888, .val = 0x13E50FBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing72__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing72__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing72__avg_gpu_core_frequency__max,acmgt2__ray_tracing72__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2971, 24, NULL,acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2972, 32, NULL,acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2973, 40, NULL,acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2974, 48, NULL,acmgt2__ray_tracing72__rt_miss_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing73_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing73";
   query->symbol_name = "RayTracing73";
   query->guid = "e561fce8-e7a3-44f6-950d-96e2c7e621e3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x14850000 },
         { .reg = 0x00009888, .val = 0x14A50000 },
         { .reg = 0x00009888, .val = 0x14C50000 },
         { .reg = 0x00009888, .val = 0x14E50000 },
         { .reg = 0x00009888, .val = 0x02850002 },
         { .reg = 0x00009888, .val = 0x10850083 },
         { .reg = 0x00009888, .val = 0x12850001 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x02A50002 },
         { .reg = 0x00009888, .val = 0x0CA50083 },
         { .reg = 0x00009888, .val = 0x0EA50001 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A600AA },
         { .reg = 0x00009888, .val = 0x02C50002 },
         { .reg = 0x00009888, .val = 0x08C50083 },
         { .reg = 0x00009888, .val = 0x0AC50001 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AA00 },
         { .reg = 0x00009888, .val = 0x02E50002 },
         { .reg = 0x00009888, .val = 0x04E50830 },
         { .reg = 0x00009888, .val = 0x06E50001 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E600AA },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing73__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing73__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing73__avg_gpu_core_frequency__max,acmgt2__ray_tracing73__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1744, 24, NULL,acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1745, 32, NULL,acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1746, 40, NULL,acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1747, 48, NULL,acmgt2__ray_tracing73__rt_bvh_cache_miss_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing74_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing74";
   query->symbol_name = "RayTracing74";
   query->guid = "f396f14f-c1f5-4f46-839a-ac7f00810d4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x15850000 },
         { .reg = 0x00009888, .val = 0x15A50000 },
         { .reg = 0x00009888, .val = 0x15C50000 },
         { .reg = 0x00009888, .val = 0x15E50000 },
         { .reg = 0x00009888, .val = 0x03850002 },
         { .reg = 0x00009888, .val = 0x11850083 },
         { .reg = 0x00009888, .val = 0x13850001 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x03A50002 },
         { .reg = 0x00009888, .val = 0x0DA50083 },
         { .reg = 0x00009888, .val = 0x0FA50001 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600AA },
         { .reg = 0x00009888, .val = 0x03C50002 },
         { .reg = 0x00009888, .val = 0x09C50083 },
         { .reg = 0x00009888, .val = 0x0BC50001 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AA00 },
         { .reg = 0x00009888, .val = 0x03E50002 },
         { .reg = 0x00009888, .val = 0x05E50830 },
         { .reg = 0x00009888, .val = 0x07E50001 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E600AA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing74__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing74__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing74__avg_gpu_core_frequency__max,acmgt2__ray_tracing74__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1748, 24, NULL,acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1749, 32, NULL,acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1750, 40, NULL,acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1751, 48, NULL,acmgt2__ray_tracing74__rt_bvh_cache_miss_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing75_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing75";
   query->symbol_name = "RayTracing75";
   query->guid = "028f9e23-485e-4124-b061-6448a3a5b676";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x14850000 },
         { .reg = 0x00009888, .val = 0x14A50000 },
         { .reg = 0x00009888, .val = 0x14C50000 },
         { .reg = 0x00009888, .val = 0x14E50000 },
         { .reg = 0x00009888, .val = 0x02850002 },
         { .reg = 0x00009888, .val = 0x10850083 },
         { .reg = 0x00009888, .val = 0x12850001 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x02A50002 },
         { .reg = 0x00009888, .val = 0x0CA50083 },
         { .reg = 0x00009888, .val = 0x0EA50001 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A600AA },
         { .reg = 0x00009888, .val = 0x02C50002 },
         { .reg = 0x00009888, .val = 0x08C50083 },
         { .reg = 0x00009888, .val = 0x0AC50001 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AA00 },
         { .reg = 0x00009888, .val = 0x02E50002 },
         { .reg = 0x00009888, .val = 0x04E50830 },
         { .reg = 0x00009888, .val = 0x06E50001 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E600AA },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing75__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing75__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing75__avg_gpu_core_frequency__max,acmgt2__ray_tracing75__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 2975, 24, NULL,acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 2976, 32, NULL,acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 2977, 40, NULL,acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 2978, 48, NULL,acmgt2__ray_tracing75__rt_bvh_cache_miss_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing76_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "RayTracing76";
   query->symbol_name = "RayTracing76";
   query->guid = "57b2791d-0a96-42a3-8e1b-5692658c4f87";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x15850000 },
         { .reg = 0x00009888, .val = 0x15A50000 },
         { .reg = 0x00009888, .val = 0x15C50000 },
         { .reg = 0x00009888, .val = 0x15E50000 },
         { .reg = 0x00009888, .val = 0x03850002 },
         { .reg = 0x00009888, .val = 0x11850083 },
         { .reg = 0x00009888, .val = 0x13850001 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x03A50002 },
         { .reg = 0x00009888, .val = 0x0DA50083 },
         { .reg = 0x00009888, .val = 0x0FA50001 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600AA },
         { .reg = 0x00009888, .val = 0x03C50002 },
         { .reg = 0x00009888, .val = 0x09C50083 },
         { .reg = 0x00009888, .val = 0x0BC50001 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AA00 },
         { .reg = 0x00009888, .val = 0x03E50002 },
         { .reg = 0x00009888, .val = 0x05E50830 },
         { .reg = 0x00009888, .val = 0x07E50001 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E600AA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36032942 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x3803000A },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x34030842 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing76__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing76__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing76__avg_gpu_core_frequency__max,acmgt2__ray_tracing76__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 2979, 24, NULL,acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 2980, 32, NULL,acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 2981, 40, NULL,acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 2982, 48, NULL,acmgt2__ray_tracing76__rt_bvh_cache_miss_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing77_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing77";
   query->symbol_name = "RayTracing77";
   query->guid = "a2ff8f41-89ef-4e9a-a7f0-31412cff350d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x168502A0 },
         { .reg = 0x00009888, .val = 0x16A502A0 },
         { .reg = 0x00009888, .val = 0x16C502A0 },
         { .reg = 0x00009888, .val = 0x16E502A0 },
         { .reg = 0x00009888, .val = 0x178502A0 },
         { .reg = 0x00009888, .val = 0x17A502A0 },
         { .reg = 0x00009888, .val = 0x17C502A0 },
         { .reg = 0x00009888, .val = 0x17E502A0 },
         { .reg = 0x00009888, .val = 0x02850004 },
         { .reg = 0x00009888, .val = 0x04850C20 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086000A },
         { .reg = 0x00009888, .val = 0x02A50004 },
         { .reg = 0x00009888, .val = 0x06A500C2 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A600A0 },
         { .reg = 0x00009888, .val = 0x02C50004 },
         { .reg = 0x00009888, .val = 0x08C500C2 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C60A00 },
         { .reg = 0x00009888, .val = 0x02E50004 },
         { .reg = 0x00009888, .val = 0x0AE500C2 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6A000 },
         { .reg = 0x00009888, .val = 0x03850004 },
         { .reg = 0x00009888, .val = 0x0D8500C2 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386000A },
         { .reg = 0x00009888, .val = 0x03A50004 },
         { .reg = 0x00009888, .val = 0x0FA500C2 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600A0 },
         { .reg = 0x00009888, .val = 0x03C50004 },
         { .reg = 0x00009888, .val = 0x11C500C2 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C60A00 },
         { .reg = 0x00009888, .val = 0x03E50004 },
         { .reg = 0x00009888, .val = 0x13E500C2 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6A000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001805 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006005 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018005 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060005 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing77__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing77__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing77__avg_gpu_core_frequency__max,acmgt2__ray_tracing77__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1666, 24, percentage_max_float,acmgt2__ray_tracing77__rt_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1667, 28, percentage_max_float,acmgt2__ray_tracing77__rt_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1668, 32, percentage_max_float,acmgt2__ray_tracing77__rt_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1669, 36, percentage_max_float,acmgt2__ray_tracing77__rt_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1670, 40, percentage_max_float,acmgt2__ray_tracing77__rt_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1671, 44, percentage_max_float,acmgt2__ray_tracing77__rt_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1672, 48, percentage_max_float,acmgt2__ray_tracing77__rt_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1673, 52, percentage_max_float,acmgt2__ray_tracing77__rt_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_ray_tracing78_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "RayTracing78";
   query->symbol_name = "RayTracing78";
   query->guid = "c9ed79c3-88ef-415b-8d59-a4da69888f66";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x168502A0 },
         { .reg = 0x00009888, .val = 0x16A502A0 },
         { .reg = 0x00009888, .val = 0x16C502A0 },
         { .reg = 0x00009888, .val = 0x16E502A0 },
         { .reg = 0x00009888, .val = 0x178502A0 },
         { .reg = 0x00009888, .val = 0x17A502A0 },
         { .reg = 0x00009888, .val = 0x17C502A0 },
         { .reg = 0x00009888, .val = 0x17E502A0 },
         { .reg = 0x00009888, .val = 0x02850004 },
         { .reg = 0x00009888, .val = 0x04850C20 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086000A },
         { .reg = 0x00009888, .val = 0x02A50004 },
         { .reg = 0x00009888, .val = 0x06A500C2 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A600A0 },
         { .reg = 0x00009888, .val = 0x02C50004 },
         { .reg = 0x00009888, .val = 0x08C500C2 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C60A00 },
         { .reg = 0x00009888, .val = 0x02E50004 },
         { .reg = 0x00009888, .val = 0x0AE500C2 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6A000 },
         { .reg = 0x00009888, .val = 0x03850004 },
         { .reg = 0x00009888, .val = 0x0D8500C2 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386000A },
         { .reg = 0x00009888, .val = 0x03A50004 },
         { .reg = 0x00009888, .val = 0x0FA500C2 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600A0 },
         { .reg = 0x00009888, .val = 0x03C50004 },
         { .reg = 0x00009888, .val = 0x11C500C2 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C60A00 },
         { .reg = 0x00009888, .val = 0x03E50004 },
         { .reg = 0x00009888, .val = 0x13E500C2 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6A000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001805 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006005 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018005 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060005 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__ray_tracing78__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__ray_tracing78__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__ray_tracing78__avg_gpu_core_frequency__max,acmgt2__ray_tracing78__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2983, 24, percentage_max_float,acmgt2__ray_tracing78__rt_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2984, 28, percentage_max_float,acmgt2__ray_tracing78__rt_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2985, 32, percentage_max_float,acmgt2__ray_tracing78__rt_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2986, 36, percentage_max_float,acmgt2__ray_tracing78__rt_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2987, 40, percentage_max_float,acmgt2__ray_tracing78__rt_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2988, 44, percentage_max_float,acmgt2__ray_tracing78__rt_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2989, 48, percentage_max_float,acmgt2__ray_tracing78__rt_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2990, 52, percentage_max_float,acmgt2__ray_tracing78__rt_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Sampler1";
   query->symbol_name = "Sampler1";
   query->guid = "97b017f6-f65c-4a0c-8078-7a1cb65157f0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x14833000 },
         { .reg = 0x00009888, .val = 0x14A33000 },
         { .reg = 0x00009888, .val = 0x14C33000 },
         { .reg = 0x00009888, .val = 0x14E33000 },
         { .reg = 0x00009888, .val = 0x04830450 },
         { .reg = 0x00009888, .val = 0x068304D2 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x08A30450 },
         { .reg = 0x00009888, .val = 0x0AA304D2 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x0CC30450 },
         { .reg = 0x00009888, .val = 0x0EC304D2 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x10E30450 },
         { .reg = 0x00009888, .val = 0x12E304D2 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler1__avg_gpu_core_frequency__max,acmgt2__sampler1__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1203, 24, percentage_max_float,acmgt2__sampler1__sampler_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1204, 28, percentage_max_float,acmgt2__sampler1__sampler_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1205, 32, percentage_max_float,acmgt2__sampler1__sampler_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1206, 36, percentage_max_float,acmgt2__sampler1__sampler_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Sampler2";
   query->symbol_name = "Sampler2";
   query->guid = "62f6959a-fdae-4cdf-b50e-e818f96d3fa5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x15833000 },
         { .reg = 0x00009888, .val = 0x15A33000 },
         { .reg = 0x00009888, .val = 0x15C33000 },
         { .reg = 0x00009888, .val = 0x15E33000 },
         { .reg = 0x00009888, .val = 0x05830450 },
         { .reg = 0x00009888, .val = 0x078304D2 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x09A30450 },
         { .reg = 0x00009888, .val = 0x0BA304D2 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x0DC30450 },
         { .reg = 0x00009888, .val = 0x0FC304D2 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x11E30450 },
         { .reg = 0x00009888, .val = 0x13E304D2 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler2__avg_gpu_core_frequency__max,acmgt2__sampler2__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1207, 24, percentage_max_float,acmgt2__sampler2__sampler_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1208, 28, percentage_max_float,acmgt2__sampler2__sampler_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1209, 32, percentage_max_float,acmgt2__sampler2__sampler_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1210, 36, percentage_max_float,acmgt2__sampler2__sampler_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Sampler3";
   query->symbol_name = "Sampler3";
   query->guid = "ec2a8d38-54ef-4090-99de-4e2cc5a1892f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x14833000 },
         { .reg = 0x00009888, .val = 0x14A33000 },
         { .reg = 0x00009888, .val = 0x14C33000 },
         { .reg = 0x00009888, .val = 0x14E33000 },
         { .reg = 0x00009888, .val = 0x04830450 },
         { .reg = 0x00009888, .val = 0x068304D2 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x08A30450 },
         { .reg = 0x00009888, .val = 0x0AA304D2 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x0CC30450 },
         { .reg = 0x00009888, .val = 0x0EC304D2 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x10E30450 },
         { .reg = 0x00009888, .val = 0x12E304D2 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler3__avg_gpu_core_frequency__max,acmgt2__sampler3__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2991, 24, percentage_max_float,acmgt2__sampler3__sampler_output_ready_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2992, 28, percentage_max_float,acmgt2__sampler3__sampler_output_ready_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2993, 32, percentage_max_float,acmgt2__sampler3__sampler_output_ready_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2994, 36, percentage_max_float,acmgt2__sampler3__sampler_output_ready_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Sampler4";
   query->symbol_name = "Sampler4";
   query->guid = "2a10d977-d656-464c-91a0-303aff97e4af";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x15833000 },
         { .reg = 0x00009888, .val = 0x15A33000 },
         { .reg = 0x00009888, .val = 0x15C33000 },
         { .reg = 0x00009888, .val = 0x15E33000 },
         { .reg = 0x00009888, .val = 0x05830450 },
         { .reg = 0x00009888, .val = 0x078304D2 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x09A30450 },
         { .reg = 0x00009888, .val = 0x0BA304D2 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x0DC30450 },
         { .reg = 0x00009888, .val = 0x0FC304D2 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x11E30450 },
         { .reg = 0x00009888, .val = 0x13E304D2 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x3603084A },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030602 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler4__avg_gpu_core_frequency__max,acmgt2__sampler4__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2995, 24, percentage_max_float,acmgt2__sampler4__sampler_output_ready_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2996, 28, percentage_max_float,acmgt2__sampler4__sampler_output_ready_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2997, 32, percentage_max_float,acmgt2__sampler4__sampler_output_ready_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2998, 36, percentage_max_float,acmgt2__sampler4__sampler_output_ready_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Sampler5";
   query->symbol_name = "Sampler5";
   query->guid = "51dcfdcf-ea8c-4963-ab0b-72013e72e433";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830D00 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30034 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30D00 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30034 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830D00 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30034 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30D00 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30034 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830D00 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x0AA30034 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x08C30D00 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x08E30034 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x07830D00 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x07A30034 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x05C30D00 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x05E30034 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C8A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030EE2 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C0314E0 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030528 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler5__avg_gpu_core_frequency__max,acmgt2__sampler5__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 899, 24, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 900, 28, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 901, 32, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 902, 36, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 903, 40, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 904, 44, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 905, 48, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 906, 52, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2999, 56, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3000, 60, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3001, 64, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3002, 68, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3003, 72, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3004, 76, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3005, 80, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3006, 84, percentage_max_float,acmgt2__sampler5__sampler_busy_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Sampler6";
   query->symbol_name = "Sampler6";
   query->guid = "8203850e-45ae-4f59-81be-45f721f5406a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E847400 },
         { .reg = 0x00009888, .val = 0x1EA47400 },
         { .reg = 0x00009888, .val = 0x1EC47400 },
         { .reg = 0x00009888, .val = 0x1EE47400 },
         { .reg = 0x00009888, .val = 0x1F847400 },
         { .reg = 0x00009888, .val = 0x1FA47400 },
         { .reg = 0x00009888, .val = 0x1FC47400 },
         { .reg = 0x00009888, .val = 0x1FE47400 },
         { .reg = 0x00009888, .val = 0x04846810 },
         { .reg = 0x00009888, .val = 0x06840035 },
         { .reg = 0x00009888, .val = 0x02840000 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A40010 },
         { .reg = 0x00009888, .val = 0x06A40D00 },
         { .reg = 0x00009888, .val = 0x08A40035 },
         { .reg = 0x00009888, .val = 0x02A40000 },
         { .reg = 0x00009888, .val = 0x00A40000 },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C40010 },
         { .reg = 0x00009888, .val = 0x08C40D00 },
         { .reg = 0x00009888, .val = 0x0AC40035 },
         { .reg = 0x00009888, .val = 0x02C40000 },
         { .reg = 0x00009888, .val = 0x00C40000 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E40010 },
         { .reg = 0x00009888, .val = 0x0AE40D00 },
         { .reg = 0x00009888, .val = 0x0CE40035 },
         { .reg = 0x00009888, .val = 0x02E40000 },
         { .reg = 0x00009888, .val = 0x00E40000 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05840010 },
         { .reg = 0x00009888, .val = 0x0D840D00 },
         { .reg = 0x00009888, .val = 0x0F840035 },
         { .reg = 0x00009888, .val = 0x03840000 },
         { .reg = 0x00009888, .val = 0x01840000 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A40010 },
         { .reg = 0x00009888, .val = 0x0FA40D00 },
         { .reg = 0x00009888, .val = 0x11A40035 },
         { .reg = 0x00009888, .val = 0x03A40000 },
         { .reg = 0x00009888, .val = 0x01A40000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C40010 },
         { .reg = 0x00009888, .val = 0x11C40D00 },
         { .reg = 0x00009888, .val = 0x13C40035 },
         { .reg = 0x00009888, .val = 0x03C40000 },
         { .reg = 0x00009888, .val = 0x01C40000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E40010 },
         { .reg = 0x00009888, .val = 0x13E40D00 },
         { .reg = 0x00009888, .val = 0x15E40035 },
         { .reg = 0x00009888, .val = 0x03E40000 },
         { .reg = 0x00009888, .val = 0x01E40000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler6__avg_gpu_core_frequency__max,acmgt2__sampler6__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1211, 24, percentage_max_float,acmgt2__sampler6__sampler_memory_latency_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1212, 28, percentage_max_float,acmgt2__sampler6__sampler_memory_latency_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1213, 32, percentage_max_float,acmgt2__sampler6__sampler_memory_latency_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1214, 36, percentage_max_float,acmgt2__sampler6__sampler_memory_latency_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1215, 40, percentage_max_float,acmgt2__sampler6__sampler_memory_latency_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1216, 44, percentage_max_float,acmgt2__sampler6__sampler_memory_latency_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1217, 48, percentage_max_float,acmgt2__sampler6__sampler_memory_latency_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1218, 52, percentage_max_float,acmgt2__sampler6__sampler_memory_latency_stall_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Sampler7";
   query->symbol_name = "Sampler7";
   query->guid = "3e6e7ddd-572c-4628-94a2-b8a8385fc7b0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E847400 },
         { .reg = 0x00009888, .val = 0x1EA47400 },
         { .reg = 0x00009888, .val = 0x1EC47400 },
         { .reg = 0x00009888, .val = 0x1EE47400 },
         { .reg = 0x00009888, .val = 0x1F847400 },
         { .reg = 0x00009888, .val = 0x1FA47400 },
         { .reg = 0x00009888, .val = 0x1FC47400 },
         { .reg = 0x00009888, .val = 0x1FE47400 },
         { .reg = 0x00009888, .val = 0x04846810 },
         { .reg = 0x00009888, .val = 0x06840035 },
         { .reg = 0x00009888, .val = 0x02840000 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A40010 },
         { .reg = 0x00009888, .val = 0x06A40D00 },
         { .reg = 0x00009888, .val = 0x08A40035 },
         { .reg = 0x00009888, .val = 0x02A40000 },
         { .reg = 0x00009888, .val = 0x00A40000 },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C40010 },
         { .reg = 0x00009888, .val = 0x08C40D00 },
         { .reg = 0x00009888, .val = 0x0AC40035 },
         { .reg = 0x00009888, .val = 0x02C40000 },
         { .reg = 0x00009888, .val = 0x00C40000 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E40010 },
         { .reg = 0x00009888, .val = 0x0AE40D00 },
         { .reg = 0x00009888, .val = 0x0CE40035 },
         { .reg = 0x00009888, .val = 0x02E40000 },
         { .reg = 0x00009888, .val = 0x00E40000 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05840010 },
         { .reg = 0x00009888, .val = 0x0D840D00 },
         { .reg = 0x00009888, .val = 0x0F840035 },
         { .reg = 0x00009888, .val = 0x03840000 },
         { .reg = 0x00009888, .val = 0x01840000 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A40010 },
         { .reg = 0x00009888, .val = 0x0FA40D00 },
         { .reg = 0x00009888, .val = 0x11A40035 },
         { .reg = 0x00009888, .val = 0x03A40000 },
         { .reg = 0x00009888, .val = 0x01A40000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C40010 },
         { .reg = 0x00009888, .val = 0x11C40D00 },
         { .reg = 0x00009888, .val = 0x13C40035 },
         { .reg = 0x00009888, .val = 0x03C40000 },
         { .reg = 0x00009888, .val = 0x01C40000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E40010 },
         { .reg = 0x00009888, .val = 0x13E40D00 },
         { .reg = 0x00009888, .val = 0x15E40035 },
         { .reg = 0x00009888, .val = 0x03E40000 },
         { .reg = 0x00009888, .val = 0x01E40000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler7__avg_gpu_core_frequency__max,acmgt2__sampler7__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3007, 24, percentage_max_float,acmgt2__sampler7__sampler_memory_latency_stall_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3008, 28, percentage_max_float,acmgt2__sampler7__sampler_memory_latency_stall_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3009, 32, percentage_max_float,acmgt2__sampler7__sampler_memory_latency_stall_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3010, 36, percentage_max_float,acmgt2__sampler7__sampler_memory_latency_stall_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3011, 40, percentage_max_float,acmgt2__sampler7__sampler_memory_latency_stall_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3012, 44, percentage_max_float,acmgt2__sampler7__sampler_memory_latency_stall_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3013, 48, percentage_max_float,acmgt2__sampler7__sampler_memory_latency_stall_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3014, 52, percentage_max_float,acmgt2__sampler7__sampler_memory_latency_stall_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Sampler8";
   query->symbol_name = "Sampler8";
   query->guid = "5683991d-228c-41e5-812b-98bc82e244b2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824800 },
         { .reg = 0x00009888, .val = 0x08820023 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00830005 },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20900 },
         { .reg = 0x00009888, .val = 0x0AA20023 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A30050 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x0AC20900 },
         { .reg = 0x00009888, .val = 0x0CC20023 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C30500 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0CE20900 },
         { .reg = 0x00009888, .val = 0x0EE20023 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x00E35000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0F820900 },
         { .reg = 0x00009888, .val = 0x11820023 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x03830005 },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x13A20023 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x03A30050 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x13C20900 },
         { .reg = 0x00009888, .val = 0x15C20023 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x03C30500 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x15E20900 },
         { .reg = 0x00009888, .val = 0x17E20023 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x03E35000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler8__avg_gpu_core_frequency__max,acmgt2__sampler8__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1251, 24, percentage_max_float,acmgt2__sampler8__sampler_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1252, 28, percentage_max_float,acmgt2__sampler8__sampler_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1253, 32, percentage_max_float,acmgt2__sampler8__sampler_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1254, 36, percentage_max_float,acmgt2__sampler8__sampler_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1255, 40, percentage_max_float,acmgt2__sampler8__sampler_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1256, 44, percentage_max_float,acmgt2__sampler8__sampler_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1257, 48, percentage_max_float,acmgt2__sampler8__sampler_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1258, 52, percentage_max_float,acmgt2__sampler8__sampler_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Sampler9";
   query->symbol_name = "Sampler9";
   query->guid = "2c897818-565a-4753-a1f6-8f81529b2447";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824800 },
         { .reg = 0x00009888, .val = 0x08820023 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00830005 },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20900 },
         { .reg = 0x00009888, .val = 0x0AA20023 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A30050 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x0AC20900 },
         { .reg = 0x00009888, .val = 0x0CC20023 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C30500 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0CE20900 },
         { .reg = 0x00009888, .val = 0x0EE20023 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x00E35000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0F820900 },
         { .reg = 0x00009888, .val = 0x11820023 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x03830005 },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x13A20023 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x03A30050 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x13C20900 },
         { .reg = 0x00009888, .val = 0x15C20023 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x03C30500 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x15E20900 },
         { .reg = 0x00009888, .val = 0x17E20023 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x03E35000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler9__avg_gpu_core_frequency__max,acmgt2__sampler9__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3015, 24, percentage_max_float,acmgt2__sampler9__sampler_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3016, 28, percentage_max_float,acmgt2__sampler9__sampler_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3017, 32, percentage_max_float,acmgt2__sampler9__sampler_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3018, 36, percentage_max_float,acmgt2__sampler9__sampler_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3019, 40, percentage_max_float,acmgt2__sampler9__sampler_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3020, 44, percentage_max_float,acmgt2__sampler9__sampler_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3021, 48, percentage_max_float,acmgt2__sampler9__sampler_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3022, 52, percentage_max_float,acmgt2__sampler9__sampler_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Sampler10";
   query->symbol_name = "Sampler10";
   query->guid = "f74b6a50-22da-4c0e-b621-c0627525e511";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830CC0 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30033 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30CC0 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30033 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830CC0 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30033 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30CC0 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30033 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830CC0 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x0AA30033 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x08C30CC0 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x08E30033 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x07830CC0 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x07A30033 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x05C30CC0 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x05E30033 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C8A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030EE2 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C0314E0 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030528 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler10__avg_gpu_core_frequency__max,acmgt2__sampler10__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1235, 24, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1236, 32, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1237, 40, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1238, 48, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1239, 56, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1240, 64, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1241, 72, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1242, 80, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3023, 88, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3024, 96, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3025, 104, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3026, 112, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3027, 120, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3028, 128, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3029, 136, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3030, 144, NULL,acmgt2__sampler10__sampler_texture_cache_access_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_sampler11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Sampler11";
   query->symbol_name = "Sampler11";
   query->guid = "6edeb7d7-a21c-4d06-bd66-dd804480f1f1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830C80 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30032 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30C80 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30032 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830C80 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30032 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30C80 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30032 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830C80 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x0AA30032 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x08C30C80 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x08E30032 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x07830C80 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x07A30032 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x05C30C80 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x05E30032 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C8A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030EE2 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C0314E0 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030528 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__sampler11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__sampler11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__sampler11__avg_gpu_core_frequency__max,acmgt2__sampler11__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1243, 24, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1244, 32, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1245, 40, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1246, 48, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1247, 56, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1248, 64, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1249, 72, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1250, 80, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3031, 88, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3032, 96, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3033, 104, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3034, 112, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3035, 120, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3036, 128, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3037, 136, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3038, 144, NULL,acmgt2__sampler11__sampler_texture_cache_miss_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher1";
   query->symbol_name = "ThreadDispatcher1";
   query->guid = "7d691d4b-febf-415b-8d1b-1d623e936c19";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001D },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x08810CF2 },
         { .reg = 0x00009888, .val = 0x0A810D74 },
         { .reg = 0x00009888, .val = 0x0C810039 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810C80 },
         { .reg = 0x00009888, .val = 0x0F810D33 },
         { .reg = 0x00009888, .val = 0x11810FB5 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x0308000A },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x12810C70 },
         { .reg = 0x00009888, .val = 0x14810CF2 },
         { .reg = 0x00009888, .val = 0x16810DB7 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AAA0 },
         { .reg = 0x00009888, .val = 0x0084FC00 },
         { .reg = 0x00009888, .val = 0x02865550 },
         { .reg = 0x00009888, .val = 0x02875550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32031CE8 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032107 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031068 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34031CE7 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher1__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher1__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1279, 24, NULL,acmgt2__thread_dispatcher1__gpgpu_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1294, 32, NULL,acmgt2__thread_dispatcher1__async_gpgpu_threadgroup_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3039, 40, NULL,acmgt2__thread_dispatcher1__async_gpgpu_thread_exit_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher2";
   query->symbol_name = "ThreadDispatcher2";
   query->guid = "04737515-c210-40b6-90b0-2ad6ce51ff72";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001D },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x08A10CF2 },
         { .reg = 0x00009888, .val = 0x0AA10D74 },
         { .reg = 0x00009888, .val = 0x0CA10039 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10C80 },
         { .reg = 0x00009888, .val = 0x0FA10D33 },
         { .reg = 0x00009888, .val = 0x11A10FB5 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BA955 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108FC00 },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x12A10C70 },
         { .reg = 0x00009888, .val = 0x14A10CF2 },
         { .reg = 0x00009888, .val = 0x16A10DB7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAA0 },
         { .reg = 0x00009888, .val = 0x00A4FC00 },
         { .reg = 0x00009888, .val = 0x02A65550 },
         { .reg = 0x00009888, .val = 0x02A75550 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32031CE8 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032107 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031068 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34031CE7 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher2__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher2__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1280, 24, NULL,acmgt2__thread_dispatcher2__gpgpu_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1297, 32, NULL,acmgt2__thread_dispatcher2__async_gpgpu_threadgroup_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3040, 40, NULL,acmgt2__thread_dispatcher2__async_gpgpu_thread_exit_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher3";
   query->symbol_name = "ThreadDispatcher3";
   query->guid = "6215b3ed-0c9a-4171-b8bc-035be8e8b140";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001D },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x08C10CF2 },
         { .reg = 0x00009888, .val = 0x0AC10D74 },
         { .reg = 0x00009888, .val = 0x0CC10039 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C302AA },
         { .reg = 0x00009888, .val = 0x00C4001F },
         { .reg = 0x00009888, .val = 0x00C60155 },
         { .reg = 0x00009888, .val = 0x00C70155 },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10C80 },
         { .reg = 0x00009888, .val = 0x0FC10D33 },
         { .reg = 0x00009888, .val = 0x11C10FB5 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A800 },
         { .reg = 0x00009888, .val = 0x03C3000A },
         { .reg = 0x00009888, .val = 0x01C403E0 },
         { .reg = 0x00009888, .val = 0x01C65400 },
         { .reg = 0x00009888, .val = 0x03C60005 },
         { .reg = 0x00009888, .val = 0x01C75400 },
         { .reg = 0x00009888, .val = 0x03C70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x000702AA },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x000C0155 },
         { .reg = 0x00009888, .val = 0x0107A800 },
         { .reg = 0x00009888, .val = 0x0307000A },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x010203E0 },
         { .reg = 0x00009888, .val = 0x010C5400 },
         { .reg = 0x00009888, .val = 0x030C0005 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C70 },
         { .reg = 0x00009888, .val = 0x14C10CF2 },
         { .reg = 0x00009888, .val = 0x16C10DB7 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C3AAA0 },
         { .reg = 0x00009888, .val = 0x00C4FC00 },
         { .reg = 0x00009888, .val = 0x02C65550 },
         { .reg = 0x00009888, .val = 0x02C75550 },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32031CE8 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032107 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031068 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34031CE7 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher3__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher3__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1261, 24, NULL,acmgt2__thread_dispatcher3__gpgpu_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1285, 32, NULL,acmgt2__thread_dispatcher3__async_gpgpu_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3041, 40, NULL,acmgt2__thread_dispatcher3__async_gpgpu_thread_exit_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher4";
   query->symbol_name = "ThreadDispatcher4";
   query->guid = "cf7b0026-fbed-4f29-ab6a-0f6acbea337b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001D },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x08E10CF2 },
         { .reg = 0x00009888, .val = 0x0AE10D74 },
         { .reg = 0x00009888, .val = 0x0CE10039 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10C80 },
         { .reg = 0x00009888, .val = 0x0FE10D33 },
         { .reg = 0x00009888, .val = 0x11E10FB5 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01075400 },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x12E10C70 },
         { .reg = 0x00009888, .val = 0x14E10CF2 },
         { .reg = 0x00009888, .val = 0x16E10DB7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAA0 },
         { .reg = 0x00009888, .val = 0x00E4FC00 },
         { .reg = 0x00009888, .val = 0x02E65550 },
         { .reg = 0x00009888, .val = 0x02E75550 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009888, .val = 0x0202FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32031CE8 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032107 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031068 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34031CE7 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher4__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher4__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1262, 24, NULL,acmgt2__thread_dispatcher4__gpgpu_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1286, 32, NULL,acmgt2__thread_dispatcher4__async_gpgpu_threadgroup_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3042, 40, NULL,acmgt2__thread_dispatcher4__async_gpgpu_thread_exit_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher5";
   query->symbol_name = "ThreadDispatcher5";
   query->guid = "9fcfbc28-caaf-44ea-84a5-f1c5c2341b2a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x09810CF2 },
         { .reg = 0x00009888, .val = 0x0B810D74 },
         { .reg = 0x00009888, .val = 0x0D810039 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010802AA },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001D },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810C80 },
         { .reg = 0x00009888, .val = 0x0E810D33 },
         { .reg = 0x00009888, .val = 0x10810FB5 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A800 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x008403E0 },
         { .reg = 0x00009888, .val = 0x00865400 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00875400 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C70 },
         { .reg = 0x00009888, .val = 0x15810CF2 },
         { .reg = 0x00009888, .val = 0x17810DB7 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AAA0 },
         { .reg = 0x00009888, .val = 0x0184FC00 },
         { .reg = 0x00009888, .val = 0x03865550 },
         { .reg = 0x00009888, .val = 0x03875550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030683 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher5__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher5__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1267, 24, NULL,acmgt2__thread_dispatcher5__gpgpu_threadgroup_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3043, 32, NULL,acmgt2__thread_dispatcher5__async_gpgpu_threadgroup_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3044, 40, NULL,acmgt2__thread_dispatcher5__async_gpgpu_thread_exit_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher6";
   query->symbol_name = "ThreadDispatcher6";
   query->guid = "c0af81b4-8172-4e9c-8da2-5051e5817de6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x09A10CF2 },
         { .reg = 0x00009888, .val = 0x0BA10D74 },
         { .reg = 0x00009888, .val = 0x0DA10039 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A302AA },
         { .reg = 0x00009888, .val = 0x01A4001F },
         { .reg = 0x00009888, .val = 0x01A60155 },
         { .reg = 0x00009888, .val = 0x01A70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010803FF },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009888, .val = 0x0101001F },
         { .reg = 0x00009888, .val = 0x010B0155 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001D },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10C80 },
         { .reg = 0x00009888, .val = 0x0EA10D33 },
         { .reg = 0x00009888, .val = 0x10A10FB5 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10C70 },
         { .reg = 0x00009888, .val = 0x15A10CF2 },
         { .reg = 0x00009888, .val = 0x17A10DB7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAA0 },
         { .reg = 0x00009888, .val = 0x01A4FC00 },
         { .reg = 0x00009888, .val = 0x03A65550 },
         { .reg = 0x00009888, .val = 0x03A75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020BAAA5 },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FC00 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030683 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher6__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher6__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1268, 24, NULL,acmgt2__thread_dispatcher6__gpgpu_threadgroup_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3045, 32, NULL,acmgt2__thread_dispatcher6__async_gpgpu_threadgroup_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3046, 40, NULL,acmgt2__thread_dispatcher6__async_gpgpu_thread_exit_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher7";
   query->symbol_name = "ThreadDispatcher7";
   query->guid = "74538036-2ddc-486d-914c-ffe5d3ce6cfb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x09C10CF2 },
         { .reg = 0x00009888, .val = 0x0BC10D74 },
         { .reg = 0x00009888, .val = 0x0DC10039 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010702AA },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001D },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10C80 },
         { .reg = 0x00009888, .val = 0x0EC10D33 },
         { .reg = 0x00009888, .val = 0x10C10FB5 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x13C10C70 },
         { .reg = 0x00009888, .val = 0x15C10CF2 },
         { .reg = 0x00009888, .val = 0x17C10DB7 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C3AAA0 },
         { .reg = 0x00009888, .val = 0x01C4FC00 },
         { .reg = 0x00009888, .val = 0x03C65550 },
         { .reg = 0x00009888, .val = 0x03C75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207000A },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FC00 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030683 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher7__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher7__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1273, 24, NULL,acmgt2__thread_dispatcher7__gpgpu_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3047, 32, NULL,acmgt2__thread_dispatcher7__async_gpgpu_threadgroup_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3048, 40, NULL,acmgt2__thread_dispatcher7__async_gpgpu_thread_exit_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher8";
   query->symbol_name = "ThreadDispatcher8";
   query->guid = "558bd2fd-a7f4-41e5-9ef6-1d529263bcd2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x09E10CF2 },
         { .reg = 0x00009888, .val = 0x0BE10D74 },
         { .reg = 0x00009888, .val = 0x0DE10039 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001D },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10C80 },
         { .reg = 0x00009888, .val = 0x0EE10D33 },
         { .reg = 0x00009888, .val = 0x10E10FB5 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3A800 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E403E0 },
         { .reg = 0x00009888, .val = 0x00E65400 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x00E75400 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x13E10C70 },
         { .reg = 0x00009888, .val = 0x15E10CF2 },
         { .reg = 0x00009888, .val = 0x17E10DB7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAA0 },
         { .reg = 0x00009888, .val = 0x01E4FC00 },
         { .reg = 0x00009888, .val = 0x03E65550 },
         { .reg = 0x00009888, .val = 0x03E75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x00075400 },
         { .reg = 0x00009888, .val = 0x02070005 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030001 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030201 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030683 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher8__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher8__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1274, 24, NULL,acmgt2__thread_dispatcher8__gpgpu_threadgroup_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3049, 32, NULL,acmgt2__thread_dispatcher8__async_gpgpu_threadgroup_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3050, 40, NULL,acmgt2__thread_dispatcher8__async_gpgpu_thread_exit_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher9";
   query->symbol_name = "ThreadDispatcher9";
   query->guid = "ac68b4c3-f63a-4dd8-855e-d3fd781a8bde";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x12810C70 },
         { .reg = 0x00009888, .val = 0x14810CF2 },
         { .reg = 0x00009888, .val = 0x16810DB7 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AAA0 },
         { .reg = 0x00009888, .val = 0x0084FC00 },
         { .reg = 0x00009888, .val = 0x02865550 },
         { .reg = 0x00009888, .val = 0x02875550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001D },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x08810CF2 },
         { .reg = 0x00009888, .val = 0x0A810D74 },
         { .reg = 0x00009888, .val = 0x0C810039 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810C80 },
         { .reg = 0x00009888, .val = 0x0F810D33 },
         { .reg = 0x00009888, .val = 0x11810FB5 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x0308000A },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32032528 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032109 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031068 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher9__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher9__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3051, 24, NULL,acmgt2__thread_dispatcher9__gpgpu_threadgroup_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3052, 32, NULL,acmgt2__thread_dispatcher9__async_gpgpu_threadgroup_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1259, 40, NULL,acmgt2__thread_dispatcher9__async_gpgpu_thread_exit_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher10";
   query->symbol_name = "ThreadDispatcher10";
   query->guid = "b969747f-2450-4725-899f-5d0701930ea7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x12A10C70 },
         { .reg = 0x00009888, .val = 0x14A10CF2 },
         { .reg = 0x00009888, .val = 0x16A10DB7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAA0 },
         { .reg = 0x00009888, .val = 0x00A4FC00 },
         { .reg = 0x00009888, .val = 0x02A65550 },
         { .reg = 0x00009888, .val = 0x02A75550 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001D },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x08A10CF2 },
         { .reg = 0x00009888, .val = 0x0AA10D74 },
         { .reg = 0x00009888, .val = 0x0CA10039 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10C80 },
         { .reg = 0x00009888, .val = 0x0FA10D33 },
         { .reg = 0x00009888, .val = 0x11A10FB5 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BA955 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108FC00 },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32032528 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032109 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031068 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher10__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher10__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3053, 24, NULL,acmgt2__thread_dispatcher10__gpgpu_threadgroup_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3054, 32, NULL,acmgt2__thread_dispatcher10__async_gpgpu_threadgroup_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1265, 40, NULL,acmgt2__thread_dispatcher10__async_gpgpu_thread_exit_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher11";
   query->symbol_name = "ThreadDispatcher11";
   query->guid = "b2e80bd3-d852-4c07-86e0-520c90236acf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C70 },
         { .reg = 0x00009888, .val = 0x14C10CF2 },
         { .reg = 0x00009888, .val = 0x16C10DB7 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C3AAA0 },
         { .reg = 0x00009888, .val = 0x00C4FC00 },
         { .reg = 0x00009888, .val = 0x02C65550 },
         { .reg = 0x00009888, .val = 0x02C75550 },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001D },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x08C10CF2 },
         { .reg = 0x00009888, .val = 0x0AC10D74 },
         { .reg = 0x00009888, .val = 0x0CC10039 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C302AA },
         { .reg = 0x00009888, .val = 0x00C4001F },
         { .reg = 0x00009888, .val = 0x00C60155 },
         { .reg = 0x00009888, .val = 0x00C70155 },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10C80 },
         { .reg = 0x00009888, .val = 0x0FC10D33 },
         { .reg = 0x00009888, .val = 0x11C10FB5 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A800 },
         { .reg = 0x00009888, .val = 0x03C3000A },
         { .reg = 0x00009888, .val = 0x01C403E0 },
         { .reg = 0x00009888, .val = 0x01C65400 },
         { .reg = 0x00009888, .val = 0x03C60005 },
         { .reg = 0x00009888, .val = 0x01C75400 },
         { .reg = 0x00009888, .val = 0x03C70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x000702AA },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x000C0155 },
         { .reg = 0x00009888, .val = 0x0107A800 },
         { .reg = 0x00009888, .val = 0x0307000A },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x010203E0 },
         { .reg = 0x00009888, .val = 0x010C5400 },
         { .reg = 0x00009888, .val = 0x030C0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32032528 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032109 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031068 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher11__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher11__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3055, 24, NULL,acmgt2__thread_dispatcher11__gpgpu_threadgroup_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3056, 32, NULL,acmgt2__thread_dispatcher11__async_gpgpu_threadgroup_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1271, 40, NULL,acmgt2__thread_dispatcher11__async_gpgpu_thread_exit_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher12";
   query->symbol_name = "ThreadDispatcher12";
   query->guid = "5622d707-7646-48bc-90e0-af17a55ab1c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x12E10C70 },
         { .reg = 0x00009888, .val = 0x14E10CF2 },
         { .reg = 0x00009888, .val = 0x16E10DB7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAA0 },
         { .reg = 0x00009888, .val = 0x00E4FC00 },
         { .reg = 0x00009888, .val = 0x02E65550 },
         { .reg = 0x00009888, .val = 0x02E75550 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001D },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x08E10CF2 },
         { .reg = 0x00009888, .val = 0x0AE10D74 },
         { .reg = 0x00009888, .val = 0x0CE10039 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10C80 },
         { .reg = 0x00009888, .val = 0x0FE10D33 },
         { .reg = 0x00009888, .val = 0x11E10FB5 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01075400 },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32032528 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032109 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031068 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher12__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher12__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3057, 24, NULL,acmgt2__thread_dispatcher12__gpgpu_threadgroup_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3058, 32, NULL,acmgt2__thread_dispatcher12__async_gpgpu_threadgroup_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1277, 40, NULL,acmgt2__thread_dispatcher12__async_gpgpu_thread_exit_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher13";
   query->symbol_name = "ThreadDispatcher13";
   query->guid = "6149c8e0-84f6-4643-ac19-0f5b5a8fa830";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001D },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810C80 },
         { .reg = 0x00009888, .val = 0x0E810D33 },
         { .reg = 0x00009888, .val = 0x10810FB5 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A800 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x008403E0 },
         { .reg = 0x00009888, .val = 0x00865400 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00875400 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C70 },
         { .reg = 0x00009888, .val = 0x15810CF2 },
         { .reg = 0x00009888, .val = 0x17810DB7 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AAA0 },
         { .reg = 0x00009888, .val = 0x0184FC00 },
         { .reg = 0x00009888, .val = 0x03865550 },
         { .reg = 0x00009888, .val = 0x03875550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x09810CF2 },
         { .reg = 0x00009888, .val = 0x0B810D74 },
         { .reg = 0x00009888, .val = 0x0D810039 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010802AA },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000203FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030420 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030693 },
         { .reg = 0x00009888, .val = 0x3C031269 },
         { .reg = 0x00009888, .val = 0x3E030693 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030421 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher13__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher13__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3059, 24, NULL,acmgt2__thread_dispatcher13__gpgpu_threadgroup_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1298, 32, NULL,acmgt2__thread_dispatcher13__async_gpgpu_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1283, 40, NULL,acmgt2__thread_dispatcher13__async_gpgpu_thread_exit_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher14";
   query->symbol_name = "ThreadDispatcher14";
   query->guid = "3ad2842e-a192-4cb9-aca4-c3dfa9238070";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001D },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10C80 },
         { .reg = 0x00009888, .val = 0x0EA10D33 },
         { .reg = 0x00009888, .val = 0x10A10FB5 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10C70 },
         { .reg = 0x00009888, .val = 0x15A10CF2 },
         { .reg = 0x00009888, .val = 0x17A10DB7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAA0 },
         { .reg = 0x00009888, .val = 0x01A4FC00 },
         { .reg = 0x00009888, .val = 0x03A65550 },
         { .reg = 0x00009888, .val = 0x03A75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020BAAA5 },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FC00 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x09A10CF2 },
         { .reg = 0x00009888, .val = 0x0BA10D74 },
         { .reg = 0x00009888, .val = 0x0DA10039 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A302AA },
         { .reg = 0x00009888, .val = 0x01A4001F },
         { .reg = 0x00009888, .val = 0x01A60155 },
         { .reg = 0x00009888, .val = 0x01A70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010803FF },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009888, .val = 0x0101001F },
         { .reg = 0x00009888, .val = 0x010B0155 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000203FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030420 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030693 },
         { .reg = 0x00009888, .val = 0x3C031269 },
         { .reg = 0x00009888, .val = 0x3E030693 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030421 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher14__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher14__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3060, 24, NULL,acmgt2__thread_dispatcher14__gpgpu_threadgroup_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1289, 32, NULL,acmgt2__thread_dispatcher14__async_gpgpu_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1287, 40, NULL,acmgt2__thread_dispatcher14__async_gpgpu_thread_exit_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher15";
   query->symbol_name = "ThreadDispatcher15";
   query->guid = "a8b90aef-99fa-443f-8e74-06489d14a031";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001D },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10C80 },
         { .reg = 0x00009888, .val = 0x0EC10D33 },
         { .reg = 0x00009888, .val = 0x10C10FB5 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x13C10C70 },
         { .reg = 0x00009888, .val = 0x15C10CF2 },
         { .reg = 0x00009888, .val = 0x17C10DB7 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C3AAA0 },
         { .reg = 0x00009888, .val = 0x01C4FC00 },
         { .reg = 0x00009888, .val = 0x03C65550 },
         { .reg = 0x00009888, .val = 0x03C75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207000A },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FC00 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x09C10CF2 },
         { .reg = 0x00009888, .val = 0x0BC10D74 },
         { .reg = 0x00009888, .val = 0x0DC10039 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010702AA },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000203FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030420 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030693 },
         { .reg = 0x00009888, .val = 0x3C031269 },
         { .reg = 0x00009888, .val = 0x3E030693 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030421 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher15__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher15__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3061, 24, NULL,acmgt2__thread_dispatcher15__gpgpu_threadgroup_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1290, 32, NULL,acmgt2__thread_dispatcher15__async_gpgpu_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1291, 40, NULL,acmgt2__thread_dispatcher15__async_gpgpu_thread_exit_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher16";
   query->symbol_name = "ThreadDispatcher16";
   query->guid = "3c5182e0-c1f6-4e9a-b5a6-752052f23389";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001D },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10C80 },
         { .reg = 0x00009888, .val = 0x0EE10D33 },
         { .reg = 0x00009888, .val = 0x10E10FB5 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3A800 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E403E0 },
         { .reg = 0x00009888, .val = 0x00E65400 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x00E75400 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x13E10C70 },
         { .reg = 0x00009888, .val = 0x15E10CF2 },
         { .reg = 0x00009888, .val = 0x17E10DB7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAA0 },
         { .reg = 0x00009888, .val = 0x01E4FC00 },
         { .reg = 0x00009888, .val = 0x03E65550 },
         { .reg = 0x00009888, .val = 0x03E75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x00075400 },
         { .reg = 0x00009888, .val = 0x02070005 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x09E10CF2 },
         { .reg = 0x00009888, .val = 0x0BE10D74 },
         { .reg = 0x00009888, .val = 0x0DE10039 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000203FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030420 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030693 },
         { .reg = 0x00009888, .val = 0x3C031269 },
         { .reg = 0x00009888, .val = 0x3E030693 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030421 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher16__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher16__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3062, 24, NULL,acmgt2__thread_dispatcher16__gpgpu_threadgroup_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1293, 32, NULL,acmgt2__thread_dispatcher16__async_gpgpu_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1295, 40, NULL,acmgt2__thread_dispatcher16__async_gpgpu_thread_exit_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher17";
   query->symbol_name = "ThreadDispatcher17";
   query->guid = "72a4eaf8-b31d-4749-85e9-d6670ecfda25";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810CF2 },
         { .reg = 0x00009888, .val = 0x0E810D74 },
         { .reg = 0x00009888, .val = 0x10810039 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083AA00 },
         { .reg = 0x00009888, .val = 0x02830002 },
         { .reg = 0x00009888, .val = 0x008401F0 },
         { .reg = 0x00009888, .val = 0x00865500 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x00875500 },
         { .reg = 0x00009888, .val = 0x02870001 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x13810CB1 },
         { .reg = 0x00009888, .val = 0x15810DF3 },
         { .reg = 0x00009888, .val = 0x17810036 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03832AA8 },
         { .reg = 0x00009888, .val = 0x01847E00 },
         { .reg = 0x00009888, .val = 0x03861554 },
         { .reg = 0x00009888, .val = 0x03871554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03082AA8 },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810DB7 },
         { .reg = 0x00009888, .val = 0x0A810CF5 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030007 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36031CE0 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031067 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030083 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher17__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher17__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1281, 24, NULL,acmgt2__thread_dispatcher17__task_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1284, 32, NULL,acmgt2__thread_dispatcher17__task_thread_exit_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3063, 40, percentage_max_float,acmgt2__thread_dispatcher17__threadgroup_dispatch_resource_stall_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher18";
   query->symbol_name = "ThreadDispatcher18";
   query->guid = "2b0b4fde-719b-49de-a309-aeb1f96e2f6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10CF2 },
         { .reg = 0x00009888, .val = 0x0EA10D74 },
         { .reg = 0x00009888, .val = 0x10A10039 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x02A30002 },
         { .reg = 0x00009888, .val = 0x00A401F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x02A60001 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x02A70001 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x11A10C00 },
         { .reg = 0x00009888, .val = 0x13A10CB1 },
         { .reg = 0x00009888, .val = 0x15A10DF3 },
         { .reg = 0x00009888, .val = 0x17A10036 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32AA8 },
         { .reg = 0x00009888, .val = 0x01A47E00 },
         { .reg = 0x00009888, .val = 0x03A61554 },
         { .reg = 0x00009888, .val = 0x03A71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x020B2AA9 },
         { .reg = 0x00009888, .val = 0x03083FFC },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009888, .val = 0x01017E00 },
         { .reg = 0x00009888, .val = 0x030B1554 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10DB7 },
         { .reg = 0x00009888, .val = 0x0AA10CF5 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300AA },
         { .reg = 0x00009888, .val = 0x00A4000F },
         { .reg = 0x00009888, .val = 0x00A60055 },
         { .reg = 0x00009888, .val = 0x00A70055 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030007 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36031CE0 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031067 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030083 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher18__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher18__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1282, 24, NULL,acmgt2__thread_dispatcher18__task_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1288, 32, NULL,acmgt2__thread_dispatcher18__task_thread_exit_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3064, 40, percentage_max_float,acmgt2__thread_dispatcher18__threadgroup_dispatch_resource_stall_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher19_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher19";
   query->symbol_name = "ThreadDispatcher19";
   query->guid = "d25f6c66-eb80-49f5-ba95-74e5bbeffba8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10CF2 },
         { .reg = 0x00009888, .val = 0x0EC10D74 },
         { .reg = 0x00009888, .val = 0x10C10039 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10C00 },
         { .reg = 0x00009888, .val = 0x13C10CB1 },
         { .reg = 0x00009888, .val = 0x15C10DF3 },
         { .reg = 0x00009888, .val = 0x17C10036 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32AA8 },
         { .reg = 0x00009888, .val = 0x01C47E00 },
         { .reg = 0x00009888, .val = 0x03C61554 },
         { .reg = 0x00009888, .val = 0x03C71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0007AA00 },
         { .reg = 0x00009888, .val = 0x02070002 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x000201F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009888, .val = 0x03072AA8 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009888, .val = 0x01027E00 },
         { .reg = 0x00009888, .val = 0x030C1554 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x08C10DB7 },
         { .reg = 0x00009888, .val = 0x0AC10CF5 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C300AA },
         { .reg = 0x00009888, .val = 0x00C4000F },
         { .reg = 0x00009888, .val = 0x00C60055 },
         { .reg = 0x00009888, .val = 0x00C70055 },
         { .reg = 0x00009888, .val = 0x000700AA },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009888, .val = 0x0002000F },
         { .reg = 0x00009888, .val = 0x000C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030007 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36031CE0 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031067 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030083 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher19__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher19__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher19__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher19__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1263, 24, NULL,acmgt2__thread_dispatcher19__task_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1292, 32, NULL,acmgt2__thread_dispatcher19__task_thread_exit_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3065, 40, percentage_max_float,acmgt2__thread_dispatcher19__threadgroup_dispatch_resource_stall_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher20_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher20";
   query->symbol_name = "ThreadDispatcher20";
   query->guid = "9decfc7a-90a5-4e0c-8f20-be21a3e00e2b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10CF2 },
         { .reg = 0x00009888, .val = 0x0EE10D74 },
         { .reg = 0x00009888, .val = 0x10E10039 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3AA00 },
         { .reg = 0x00009888, .val = 0x02E30002 },
         { .reg = 0x00009888, .val = 0x00E401F0 },
         { .reg = 0x00009888, .val = 0x00E65500 },
         { .reg = 0x00009888, .val = 0x02E60001 },
         { .reg = 0x00009888, .val = 0x00E75500 },
         { .reg = 0x00009888, .val = 0x02E70001 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10C00 },
         { .reg = 0x00009888, .val = 0x13E10CB1 },
         { .reg = 0x00009888, .val = 0x15E10DF3 },
         { .reg = 0x00009888, .val = 0x17E10036 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E32AA8 },
         { .reg = 0x00009888, .val = 0x01E47E00 },
         { .reg = 0x00009888, .val = 0x03E61554 },
         { .reg = 0x00009888, .val = 0x03E71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x00075500 },
         { .reg = 0x00009888, .val = 0x02070001 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03071554 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10DB7 },
         { .reg = 0x00009888, .val = 0x0AE10CF5 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x00070055 },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030007 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36031CE0 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031067 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030083 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher20__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher20__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher20__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher20__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1264, 24, NULL,acmgt2__thread_dispatcher20__task_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1296, 32, NULL,acmgt2__thread_dispatcher20__task_thread_exit_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3066, 40, percentage_max_float,acmgt2__thread_dispatcher20__threadgroup_dispatch_resource_stall_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher21";
   query->symbol_name = "ThreadDispatcher21";
   query->guid = "f2099f1b-7280-4175-b2a9-a373b7039027";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810CF2 },
         { .reg = 0x00009888, .val = 0x0F810D74 },
         { .reg = 0x00009888, .val = 0x11810039 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183AA00 },
         { .reg = 0x00009888, .val = 0x03830002 },
         { .reg = 0x00009888, .val = 0x018401F0 },
         { .reg = 0x00009888, .val = 0x01865500 },
         { .reg = 0x00009888, .val = 0x03860001 },
         { .reg = 0x00009888, .val = 0x01875500 },
         { .reg = 0x00009888, .val = 0x03870001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108AA00 },
         { .reg = 0x00009888, .val = 0x03080002 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x10810C00 },
         { .reg = 0x00009888, .val = 0x12810CB1 },
         { .reg = 0x00009888, .val = 0x14810DF3 },
         { .reg = 0x00009888, .val = 0x16810036 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02832AA8 },
         { .reg = 0x00009888, .val = 0x00847E00 },
         { .reg = 0x00009888, .val = 0x02861554 },
         { .reg = 0x00009888, .val = 0x02871554 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810DB7 },
         { .reg = 0x00009888, .val = 0x0B810CF5 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x010800AA },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x02023FFC },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032100 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030200 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030610 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032108 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher21__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher21__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1269, 24, NULL,acmgt2__thread_dispatcher21__task_threadgroup_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3067, 32, NULL,acmgt2__thread_dispatcher21__task_thread_exit_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3068, 40, percentage_max_float,acmgt2__thread_dispatcher21__threadgroup_dispatch_resource_stall_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher22";
   query->symbol_name = "ThreadDispatcher22";
   query->guid = "1be88735-2a46-4564-84f3-0c832cd05571";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10CF2 },
         { .reg = 0x00009888, .val = 0x0FA10D74 },
         { .reg = 0x00009888, .val = 0x11A10039 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x03A30002 },
         { .reg = 0x00009888, .val = 0x01A401F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x03A60001 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x03A70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108FF00 },
         { .reg = 0x00009888, .val = 0x03080003 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009888, .val = 0x010101F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x030B0001 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x10A10C00 },
         { .reg = 0x00009888, .val = 0x12A10CB1 },
         { .reg = 0x00009888, .val = 0x14A10DF3 },
         { .reg = 0x00009888, .val = 0x16A10036 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32AA8 },
         { .reg = 0x00009888, .val = 0x00A47E00 },
         { .reg = 0x00009888, .val = 0x02A61554 },
         { .reg = 0x00009888, .val = 0x02A71554 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x09A10DB7 },
         { .reg = 0x00009888, .val = 0x0BA10CF5 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A300AA },
         { .reg = 0x00009888, .val = 0x01A4000F },
         { .reg = 0x00009888, .val = 0x01A60055 },
         { .reg = 0x00009888, .val = 0x01A70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x020B1554 },
         { .reg = 0x00009888, .val = 0x010800FF },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009888, .val = 0x0101000F },
         { .reg = 0x00009888, .val = 0x010B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x02023FFC },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032100 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030200 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030610 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032108 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher22__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher22__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1270, 24, NULL,acmgt2__thread_dispatcher22__task_threadgroup_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3069, 32, NULL,acmgt2__thread_dispatcher22__task_thread_exit_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3070, 40, percentage_max_float,acmgt2__thread_dispatcher22__threadgroup_dispatch_resource_stall_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher23";
   query->symbol_name = "ThreadDispatcher23";
   query->guid = "71d12693-64c0-4da1-8f5e-fdaf00bcf83e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10CF2 },
         { .reg = 0x00009888, .val = 0x0FC10D74 },
         { .reg = 0x00009888, .val = 0x11C10039 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0107AA00 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009888, .val = 0x010201F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x10C10C00 },
         { .reg = 0x00009888, .val = 0x12C10CB1 },
         { .reg = 0x00009888, .val = 0x14C10DF3 },
         { .reg = 0x00009888, .val = 0x16C10036 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA8 },
         { .reg = 0x00009888, .val = 0x00C47E00 },
         { .reg = 0x00009888, .val = 0x02C61554 },
         { .reg = 0x00009888, .val = 0x02C71554 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10DB7 },
         { .reg = 0x00009888, .val = 0x0BC10CF5 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300AA },
         { .reg = 0x00009888, .val = 0x01C4000F },
         { .reg = 0x00009888, .val = 0x01C60055 },
         { .reg = 0x00009888, .val = 0x01C70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02072AA8 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x00027E00 },
         { .reg = 0x00009888, .val = 0x020C1554 },
         { .reg = 0x00009888, .val = 0x010700AA },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009888, .val = 0x0102000F },
         { .reg = 0x00009888, .val = 0x010C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x02023FFC },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032100 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030200 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030610 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032108 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher23__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher23__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1275, 24, NULL,acmgt2__thread_dispatcher23__task_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3071, 32, NULL,acmgt2__thread_dispatcher23__task_thread_exit_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3072, 40, percentage_max_float,acmgt2__thread_dispatcher23__threadgroup_dispatch_resource_stall_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher24_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher24";
   query->symbol_name = "ThreadDispatcher24";
   query->guid = "6ad141b6-faae-40da-bdf4-02247ec1121c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10CF2 },
         { .reg = 0x00009888, .val = 0x0FE10D74 },
         { .reg = 0x00009888, .val = 0x11E10039 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3AA00 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E401F0 },
         { .reg = 0x00009888, .val = 0x01E65500 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E75500 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x01075500 },
         { .reg = 0x00009888, .val = 0x03070001 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x10E10C00 },
         { .reg = 0x00009888, .val = 0x12E10CB1 },
         { .reg = 0x00009888, .val = 0x14E10DF3 },
         { .reg = 0x00009888, .val = 0x16E10036 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E32AA8 },
         { .reg = 0x00009888, .val = 0x00E47E00 },
         { .reg = 0x00009888, .val = 0x02E61554 },
         { .reg = 0x00009888, .val = 0x02E71554 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10DB7 },
         { .reg = 0x00009888, .val = 0x0BE10CF5 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02071554 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x01070055 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x02023FFC },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032100 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030200 },
         { .reg = 0x00009888, .val = 0x3A030010 },
         { .reg = 0x00009888, .val = 0x3C030201 },
         { .reg = 0x00009888, .val = 0x3E030610 },
         { .reg = 0x00009888, .val = 0x40030008 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032108 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher24__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher24__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher24__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher24__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1276, 24, NULL,acmgt2__thread_dispatcher24__task_threadgroup_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3073, 32, NULL,acmgt2__thread_dispatcher24__task_thread_exit_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3074, 40, percentage_max_float,acmgt2__thread_dispatcher24__threadgroup_dispatch_resource_stall_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher25_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher25";
   query->symbol_name = "ThreadDispatcher25";
   query->guid = "74433d30-ffa1-410d-8c87-7cee0acfe4ea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810DB7 },
         { .reg = 0x00009888, .val = 0x0A810CF5 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810CF2 },
         { .reg = 0x00009888, .val = 0x0E810D74 },
         { .reg = 0x00009888, .val = 0x10810039 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083AA00 },
         { .reg = 0x00009888, .val = 0x02830002 },
         { .reg = 0x00009888, .val = 0x008401F0 },
         { .reg = 0x00009888, .val = 0x00865500 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x00875500 },
         { .reg = 0x00009888, .val = 0x02870001 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x13810CB1 },
         { .reg = 0x00009888, .val = 0x15810DF3 },
         { .reg = 0x00009888, .val = 0x17810036 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03832AA8 },
         { .reg = 0x00009888, .val = 0x01847E00 },
         { .reg = 0x00009888, .val = 0x03861554 },
         { .reg = 0x00009888, .val = 0x03871554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03082AA8 },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02023FFF },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030009 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032520 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031069 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030083 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher25__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher25__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher25__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher25__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3075, 24, NULL,acmgt2__thread_dispatcher25__task_threadgroup_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3076, 32, NULL,acmgt2__thread_dispatcher25__task_thread_exit_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1339, 40, percentage_max_float,acmgt2__thread_dispatcher25__threadgroup_dispatch_resource_stall_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher26_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher26";
   query->symbol_name = "ThreadDispatcher26";
   query->guid = "5ba834b3-4603-4c43-94da-6e1bacf9500a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10DB7 },
         { .reg = 0x00009888, .val = 0x0AA10CF5 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300AA },
         { .reg = 0x00009888, .val = 0x00A4000F },
         { .reg = 0x00009888, .val = 0x00A60055 },
         { .reg = 0x00009888, .val = 0x00A70055 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B0055 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10CF2 },
         { .reg = 0x00009888, .val = 0x0EA10D74 },
         { .reg = 0x00009888, .val = 0x10A10039 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x02A30002 },
         { .reg = 0x00009888, .val = 0x00A401F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x02A60001 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x02A70001 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x11A10C00 },
         { .reg = 0x00009888, .val = 0x13A10CB1 },
         { .reg = 0x00009888, .val = 0x15A10DF3 },
         { .reg = 0x00009888, .val = 0x17A10036 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32AA8 },
         { .reg = 0x00009888, .val = 0x01A47E00 },
         { .reg = 0x00009888, .val = 0x03A61554 },
         { .reg = 0x00009888, .val = 0x03A71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x020B2AA9 },
         { .reg = 0x00009888, .val = 0x03083FFC },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009888, .val = 0x01017E00 },
         { .reg = 0x00009888, .val = 0x030B1554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02023FFF },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030009 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032520 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031069 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030083 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher26__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher26__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher26__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher26__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3077, 24, NULL,acmgt2__thread_dispatcher26__task_threadgroup_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3078, 32, NULL,acmgt2__thread_dispatcher26__task_thread_exit_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1340, 40, percentage_max_float,acmgt2__thread_dispatcher26__threadgroup_dispatch_resource_stall_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher27_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher27";
   query->symbol_name = "ThreadDispatcher27";
   query->guid = "dcfd59c3-e7b0-402e-a656-ca2a2f2d95dd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x08C10DB7 },
         { .reg = 0x00009888, .val = 0x0AC10CF5 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C300AA },
         { .reg = 0x00009888, .val = 0x00C4000F },
         { .reg = 0x00009888, .val = 0x00C60055 },
         { .reg = 0x00009888, .val = 0x00C70055 },
         { .reg = 0x00009888, .val = 0x000700AA },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009888, .val = 0x0002000F },
         { .reg = 0x00009888, .val = 0x000C0055 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10CF2 },
         { .reg = 0x00009888, .val = 0x0EC10D74 },
         { .reg = 0x00009888, .val = 0x10C10039 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10C00 },
         { .reg = 0x00009888, .val = 0x13C10CB1 },
         { .reg = 0x00009888, .val = 0x15C10DF3 },
         { .reg = 0x00009888, .val = 0x17C10036 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32AA8 },
         { .reg = 0x00009888, .val = 0x01C47E00 },
         { .reg = 0x00009888, .val = 0x03C61554 },
         { .reg = 0x00009888, .val = 0x03C71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0007AA00 },
         { .reg = 0x00009888, .val = 0x02070002 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x000201F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009888, .val = 0x03072AA8 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009888, .val = 0x01027E00 },
         { .reg = 0x00009888, .val = 0x030C1554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02023FFF },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030009 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032520 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031069 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030083 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher27__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher27__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher27__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher27__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3079, 24, NULL,acmgt2__thread_dispatcher27__task_threadgroup_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3080, 32, NULL,acmgt2__thread_dispatcher27__task_thread_exit_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1341, 40, percentage_max_float,acmgt2__thread_dispatcher27__threadgroup_dispatch_resource_stall_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher28";
   query->symbol_name = "ThreadDispatcher28";
   query->guid = "f4a8f90b-7b27-40e1-9015-6b2b3c60920a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10DB7 },
         { .reg = 0x00009888, .val = 0x0AE10CF5 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x00070055 },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10CF2 },
         { .reg = 0x00009888, .val = 0x0EE10D74 },
         { .reg = 0x00009888, .val = 0x10E10039 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3AA00 },
         { .reg = 0x00009888, .val = 0x02E30002 },
         { .reg = 0x00009888, .val = 0x00E401F0 },
         { .reg = 0x00009888, .val = 0x00E65500 },
         { .reg = 0x00009888, .val = 0x02E60001 },
         { .reg = 0x00009888, .val = 0x00E75500 },
         { .reg = 0x00009888, .val = 0x02E70001 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10C00 },
         { .reg = 0x00009888, .val = 0x13E10CB1 },
         { .reg = 0x00009888, .val = 0x15E10DF3 },
         { .reg = 0x00009888, .val = 0x17E10036 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E32AA8 },
         { .reg = 0x00009888, .val = 0x01E47E00 },
         { .reg = 0x00009888, .val = 0x03E61554 },
         { .reg = 0x00009888, .val = 0x03E71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x00075500 },
         { .reg = 0x00009888, .val = 0x02070001 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03071554 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02023FFF },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12033000 },
         { .reg = 0x00009888, .val = 0x32030009 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x36032520 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x38031069 },
         { .reg = 0x00009888, .val = 0x3A030683 },
         { .reg = 0x00009888, .val = 0x3C031068 },
         { .reg = 0x00009888, .val = 0x3E030083 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher28__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher28__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3081, 24, NULL,acmgt2__thread_dispatcher28__task_threadgroup_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3082, 32, NULL,acmgt2__thread_dispatcher28__task_thread_exit_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1342, 40, percentage_max_float,acmgt2__thread_dispatcher28__threadgroup_dispatch_resource_stall_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher29_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher29";
   query->symbol_name = "ThreadDispatcher29";
   query->guid = "e3476c20-6530-4dfe-bbcd-f98065ce0702";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x10810C00 },
         { .reg = 0x00009888, .val = 0x12810CB1 },
         { .reg = 0x00009888, .val = 0x14810DF3 },
         { .reg = 0x00009888, .val = 0x16810036 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02832AA8 },
         { .reg = 0x00009888, .val = 0x00847E00 },
         { .reg = 0x00009888, .val = 0x02861554 },
         { .reg = 0x00009888, .val = 0x02871554 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810DB7 },
         { .reg = 0x00009888, .val = 0x0B810CF5 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x010800AA },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810CF2 },
         { .reg = 0x00009888, .val = 0x0F810D74 },
         { .reg = 0x00009888, .val = 0x11810039 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183AA00 },
         { .reg = 0x00009888, .val = 0x03830002 },
         { .reg = 0x00009888, .val = 0x018401F0 },
         { .reg = 0x00009888, .val = 0x01865500 },
         { .reg = 0x00009888, .val = 0x03860001 },
         { .reg = 0x00009888, .val = 0x01875500 },
         { .reg = 0x00009888, .val = 0x03870001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108AA00 },
         { .reg = 0x00009888, .val = 0x03080002 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02020003 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032521 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030001 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030600 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher29__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher29__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher29__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher29__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3083, 24, NULL,acmgt2__thread_dispatcher29__task_threadgroup_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1260, 32, NULL,acmgt2__thread_dispatcher29__task_thread_exit_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1343, 40, percentage_max_float,acmgt2__thread_dispatcher29__threadgroup_dispatch_resource_stall_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher30_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher30";
   query->symbol_name = "ThreadDispatcher30";
   query->guid = "235cf07d-fa5f-48bf-8906-f089284a77c0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x10A10C00 },
         { .reg = 0x00009888, .val = 0x12A10CB1 },
         { .reg = 0x00009888, .val = 0x14A10DF3 },
         { .reg = 0x00009888, .val = 0x16A10036 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32AA8 },
         { .reg = 0x00009888, .val = 0x00A47E00 },
         { .reg = 0x00009888, .val = 0x02A61554 },
         { .reg = 0x00009888, .val = 0x02A71554 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x09A10DB7 },
         { .reg = 0x00009888, .val = 0x0BA10CF5 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A300AA },
         { .reg = 0x00009888, .val = 0x01A4000F },
         { .reg = 0x00009888, .val = 0x01A60055 },
         { .reg = 0x00009888, .val = 0x01A70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x020B1554 },
         { .reg = 0x00009888, .val = 0x010800FF },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009888, .val = 0x0101000F },
         { .reg = 0x00009888, .val = 0x010B0055 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10CF2 },
         { .reg = 0x00009888, .val = 0x0FA10D74 },
         { .reg = 0x00009888, .val = 0x11A10039 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x03A30002 },
         { .reg = 0x00009888, .val = 0x01A401F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x03A60001 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x03A70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108FF00 },
         { .reg = 0x00009888, .val = 0x03080003 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009888, .val = 0x010101F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x030B0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02020003 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032521 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030001 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030600 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher30__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher30__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher30__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher30__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3084, 24, NULL,acmgt2__thread_dispatcher30__task_threadgroup_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1266, 32, NULL,acmgt2__thread_dispatcher30__task_thread_exit_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1344, 40, percentage_max_float,acmgt2__thread_dispatcher30__threadgroup_dispatch_resource_stall_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher31";
   query->symbol_name = "ThreadDispatcher31";
   query->guid = "60f202e0-3078-4cee-bb6c-7b579827b501";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x10C10C00 },
         { .reg = 0x00009888, .val = 0x12C10CB1 },
         { .reg = 0x00009888, .val = 0x14C10DF3 },
         { .reg = 0x00009888, .val = 0x16C10036 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA8 },
         { .reg = 0x00009888, .val = 0x00C47E00 },
         { .reg = 0x00009888, .val = 0x02C61554 },
         { .reg = 0x00009888, .val = 0x02C71554 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10DB7 },
         { .reg = 0x00009888, .val = 0x0BC10CF5 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300AA },
         { .reg = 0x00009888, .val = 0x01C4000F },
         { .reg = 0x00009888, .val = 0x01C60055 },
         { .reg = 0x00009888, .val = 0x01C70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02072AA8 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x00027E00 },
         { .reg = 0x00009888, .val = 0x020C1554 },
         { .reg = 0x00009888, .val = 0x010700AA },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009888, .val = 0x0102000F },
         { .reg = 0x00009888, .val = 0x010C0055 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10CF2 },
         { .reg = 0x00009888, .val = 0x0FC10D74 },
         { .reg = 0x00009888, .val = 0x11C10039 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0107AA00 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009888, .val = 0x010201F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02020003 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032521 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030001 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030600 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher31__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher31__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3085, 24, NULL,acmgt2__thread_dispatcher31__task_threadgroup_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1272, 32, NULL,acmgt2__thread_dispatcher31__task_thread_exit_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1345, 40, percentage_max_float,acmgt2__thread_dispatcher31__threadgroup_dispatch_resource_stall_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher32_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher32";
   query->symbol_name = "ThreadDispatcher32";
   query->guid = "68400a0d-dffd-4787-a1f3-7385e2f2f39a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x10E10C00 },
         { .reg = 0x00009888, .val = 0x12E10CB1 },
         { .reg = 0x00009888, .val = 0x14E10DF3 },
         { .reg = 0x00009888, .val = 0x16E10036 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E32AA8 },
         { .reg = 0x00009888, .val = 0x00E47E00 },
         { .reg = 0x00009888, .val = 0x02E61554 },
         { .reg = 0x00009888, .val = 0x02E71554 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10DB7 },
         { .reg = 0x00009888, .val = 0x0BE10CF5 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02071554 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x01070055 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10CF2 },
         { .reg = 0x00009888, .val = 0x0FE10D74 },
         { .reg = 0x00009888, .val = 0x11E10039 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3AA00 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E401F0 },
         { .reg = 0x00009888, .val = 0x01E65500 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E75500 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x01075500 },
         { .reg = 0x00009888, .val = 0x03070001 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02020003 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032521 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030001 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030600 },
         { .reg = 0x00009888, .val = 0x40030009 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher32__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher32__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher32__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher32__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3086, 24, NULL,acmgt2__thread_dispatcher32__task_threadgroup_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1278, 32, NULL,acmgt2__thread_dispatcher32__task_thread_exit_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1346, 40, percentage_max_float,acmgt2__thread_dispatcher32__threadgroup_dispatch_resource_stall_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher33_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "ThreadDispatcher33";
   query->symbol_name = "ThreadDispatcher33";
   query->guid = "c0fb4de2-f14e-4576-b7b4-b564a6d1eccf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x16810C00 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x16A10030 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x14C10C00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x14E10030 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10030 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10C00 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10030 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x0E810C00 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0EA10030 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x0CC10C00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x0CE10030 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x0B810C00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0BA10030 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10C00 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10030 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C8A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030EE2 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C0314E0 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030528 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher33__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher33__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher33__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher33__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1299, 24, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1300, 28, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1301, 32, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1302, 36, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1303, 40, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1304, 44, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1305, 48, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1306, 52, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3087, 56, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3088, 60, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3089, 64, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3090, 68, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3091, 72, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3092, 76, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3093, 80, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3094, 84, percentage_max_float,acmgt2__thread_dispatcher33__threadgroup_dispatch_queue0_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher34_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "ThreadDispatcher34";
   query->symbol_name = "ThreadDispatcher34";
   query->guid = "ebaac92d-ede4-44be-b0d8-d3a292f1c696";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C817400 },
         { .reg = 0x00009888, .val = 0x2CA17400 },
         { .reg = 0x00009888, .val = 0x2CC17400 },
         { .reg = 0x00009888, .val = 0x2CE17400 },
         { .reg = 0x00009888, .val = 0x2D817400 },
         { .reg = 0x00009888, .val = 0x2DA17400 },
         { .reg = 0x00009888, .val = 0x2DC17400 },
         { .reg = 0x00009888, .val = 0x2DE17400 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x16810DC0 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x16A10037 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x14C10DC0 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x14E10037 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810DC0 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10037 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10DC0 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10037 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C817400 },
         { .reg = 0x00009888, .val = 0x2CA17400 },
         { .reg = 0x00009888, .val = 0x2CC17400 },
         { .reg = 0x00009888, .val = 0x2CE17400 },
         { .reg = 0x00009888, .val = 0x2D817400 },
         { .reg = 0x00009888, .val = 0x2DA17400 },
         { .reg = 0x00009888, .val = 0x2DC17400 },
         { .reg = 0x00009888, .val = 0x2DE17400 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x0E810DC0 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0EA10037 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x0CC10DC0 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x0CE10037 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x0B810DC0 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0BA10037 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10DC0 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10037 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C8A },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030EE2 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C0314E0 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x40030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030528 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher34__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher34__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher34__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher34__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1307, 24, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1308, 28, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1309, 32, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1310, 36, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1311, 40, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1312, 44, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1313, 48, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1314, 52, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3095, 56, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3096, 60, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3097, 64, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3098, 68, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3099, 72, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3100, 76, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3101, 80, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3102, 84, percentage_max_float,acmgt2__thread_dispatcher34__threadgroup_dispatch_queue1_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "ThreadDispatcher35";
   query->symbol_name = "ThreadDispatcher35";
   query->guid = "310c4352-616a-4995-a8ca-dc1b0b4083e2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x2A810002 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x2AA10002 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x2AC10002 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x2AE10002 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x2B810002 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x2BA10002 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x2BC10002 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x2BE10002 },
         { .reg = 0x00009888, .val = 0x06811300 },
         { .reg = 0x00009888, .val = 0x08810034 },
         { .reg = 0x00009888, .val = 0x16810F00 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A11300 },
         { .reg = 0x00009888, .val = 0x08A10D00 },
         { .reg = 0x00009888, .val = 0x16A1003C },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C11300 },
         { .reg = 0x00009888, .val = 0x0AC10034 },
         { .reg = 0x00009888, .val = 0x14C10F00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E11300 },
         { .reg = 0x00009888, .val = 0x0AE10D00 },
         { .reg = 0x00009888, .val = 0x14E1003C },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07811300 },
         { .reg = 0x00009888, .val = 0x0D810034 },
         { .reg = 0x00009888, .val = 0x13810F00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A11300 },
         { .reg = 0x00009888, .val = 0x0DA10D00 },
         { .reg = 0x00009888, .val = 0x13A1003C },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C11300 },
         { .reg = 0x00009888, .val = 0x0FC10034 },
         { .reg = 0x00009888, .val = 0x11C10F00 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E11300 },
         { .reg = 0x00009888, .val = 0x0FE10D00 },
         { .reg = 0x00009888, .val = 0x11E1003C },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher35__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher35__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1323, 24, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1324, 28, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1325, 32, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1326, 36, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1327, 40, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1328, 44, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1329, 48, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1330, 52, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_queue0_active_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1219, 56, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1220, 60, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1221, 64, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1222, 68, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1223, 72, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1224, 76, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1225, 80, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1226, 84, percentage_max_float,acmgt2__thread_dispatcher35__thread_dispatch_stall_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher36_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "ThreadDispatcher36";
   query->symbol_name = "ThreadDispatcher36";
   query->guid = "70244132-9e7c-42e1-ad19-14b16fd415ac";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x2A810002 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x2AA10002 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x2AC10002 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x2AE10002 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x2B810002 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x2BA10002 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x2BC10002 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x2BE10002 },
         { .reg = 0x00009888, .val = 0x06811300 },
         { .reg = 0x00009888, .val = 0x08810034 },
         { .reg = 0x00009888, .val = 0x16810F00 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A11300 },
         { .reg = 0x00009888, .val = 0x08A10D00 },
         { .reg = 0x00009888, .val = 0x16A1003C },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C11300 },
         { .reg = 0x00009888, .val = 0x0AC10034 },
         { .reg = 0x00009888, .val = 0x14C10F00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E11300 },
         { .reg = 0x00009888, .val = 0x0AE10D00 },
         { .reg = 0x00009888, .val = 0x14E1003C },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07811300 },
         { .reg = 0x00009888, .val = 0x0D810034 },
         { .reg = 0x00009888, .val = 0x13810F00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A11300 },
         { .reg = 0x00009888, .val = 0x0DA10D00 },
         { .reg = 0x00009888, .val = 0x13A1003C },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C11300 },
         { .reg = 0x00009888, .val = 0x0FC10034 },
         { .reg = 0x00009888, .val = 0x11C10F00 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E11300 },
         { .reg = 0x00009888, .val = 0x0FE10D00 },
         { .reg = 0x00009888, .val = 0x11E1003C },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher36__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher36__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher36__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher36__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3103, 24, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3104, 28, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3105, 32, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3106, 36, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3107, 40, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3108, 44, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3109, 48, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3110, 52, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_queue0_active_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3111, 56, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3112, 60, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3113, 64, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3114, 68, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3115, 72, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3116, 76, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3117, 80, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3118, 84, percentage_max_float,acmgt2__thread_dispatcher36__thread_dispatch_stall_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher37_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "ThreadDispatcher37";
   query->symbol_name = "ThreadDispatcher37";
   query->guid = "c7d9ebf5-268e-4377-852d-0dd8eb89151f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x2A810004 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x2AA10004 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x2AC10004 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x2AE10004 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x2B810004 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x2BA10004 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x2BC10004 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x2BE10004 },
         { .reg = 0x00009888, .val = 0x06811300 },
         { .reg = 0x00009888, .val = 0x08810035 },
         { .reg = 0x00009888, .val = 0x16810E80 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A11300 },
         { .reg = 0x00009888, .val = 0x08A10D40 },
         { .reg = 0x00009888, .val = 0x16A1003A },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C11300 },
         { .reg = 0x00009888, .val = 0x0AC10035 },
         { .reg = 0x00009888, .val = 0x14C10E80 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E11300 },
         { .reg = 0x00009888, .val = 0x0AE10D40 },
         { .reg = 0x00009888, .val = 0x14E1003A },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07811300 },
         { .reg = 0x00009888, .val = 0x0D810035 },
         { .reg = 0x00009888, .val = 0x13810E80 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A11300 },
         { .reg = 0x00009888, .val = 0x0DA10D40 },
         { .reg = 0x00009888, .val = 0x13A1003A },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C11300 },
         { .reg = 0x00009888, .val = 0x0FC10035 },
         { .reg = 0x00009888, .val = 0x11C10E80 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E11300 },
         { .reg = 0x00009888, .val = 0x0FE10D40 },
         { .reg = 0x00009888, .val = 0x11E1003A },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher37__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher37__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher37__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher37__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1331, 24, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1332, 28, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1333, 32, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1334, 36, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1335, 40, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1336, 44, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1337, 48, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1338, 52, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_queue1_active_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1227, 56, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1228, 60, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1229, 64, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1230, 68, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1231, 72, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1232, 76, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1233, 80, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1234, 84, percentage_max_float,acmgt2__thread_dispatcher37__thread_dispatch_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher38_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "ThreadDispatcher38";
   query->symbol_name = "ThreadDispatcher38";
   query->guid = "b7b02568-d2ce-40b8-bcbb-4ecc07ff731e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x2A810004 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x2AA10004 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x2AC10004 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x2AE10004 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x2B810004 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x2BA10004 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x2BC10004 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x2BE10004 },
         { .reg = 0x00009888, .val = 0x06811300 },
         { .reg = 0x00009888, .val = 0x08810035 },
         { .reg = 0x00009888, .val = 0x16810E80 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A11300 },
         { .reg = 0x00009888, .val = 0x08A10D40 },
         { .reg = 0x00009888, .val = 0x16A1003A },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C11300 },
         { .reg = 0x00009888, .val = 0x0AC10035 },
         { .reg = 0x00009888, .val = 0x14C10E80 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E11300 },
         { .reg = 0x00009888, .val = 0x0AE10D40 },
         { .reg = 0x00009888, .val = 0x14E1003A },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07811300 },
         { .reg = 0x00009888, .val = 0x0D810035 },
         { .reg = 0x00009888, .val = 0x13810E80 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A11300 },
         { .reg = 0x00009888, .val = 0x0DA10D40 },
         { .reg = 0x00009888, .val = 0x13A1003A },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C11300 },
         { .reg = 0x00009888, .val = 0x0FC10035 },
         { .reg = 0x00009888, .val = 0x11C10E80 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E11300 },
         { .reg = 0x00009888, .val = 0x0FE10D40 },
         { .reg = 0x00009888, .val = 0x11E1003A },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher38__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher38__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher38__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher38__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3119, 24, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3120, 28, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3121, 32, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3122, 36, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3123, 40, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3124, 44, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3125, 48, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3126, 52, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_queue1_active_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3127, 56, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3128, 60, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3129, 64, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3130, 68, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3131, 72, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3132, 76, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3133, 80, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3134, 84, percentage_max_float,acmgt2__thread_dispatcher38__thread_dispatch_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "ThreadDispatcher39";
   query->symbol_name = "ThreadDispatcher39";
   query->guid = "af83fc4d-719e-460b-8cac-d315583f63a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher39__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher39__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1315, 24, percentage_max_float,acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1316, 28, percentage_max_float,acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1317, 32, percentage_max_float,acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1318, 36, percentage_max_float,acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1319, 40, percentage_max_float,acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1320, 44, percentage_max_float,acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1321, 48, percentage_max_float,acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1322, 52, percentage_max_float,acmgt2__thread_dispatcher39__thread_dispatch_ps_active_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher40_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "ThreadDispatcher40";
   query->symbol_name = "ThreadDispatcher40";
   query->guid = "3d539f37-55b5-4473-9b4c-2f7d704c0d3b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030C6A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603014A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38031060 },
         { .reg = 0x00009888, .val = 0x3A030E83 },
         { .reg = 0x00009888, .val = 0x3C030EE7 },
         { .reg = 0x00009888, .val = 0x3E030221 },
         { .reg = 0x00009888, .val = 0x40030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34032800 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher40__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher40__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher40__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher40__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3135, 24, percentage_max_float,acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3136, 28, percentage_max_float,acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3137, 32, percentage_max_float,acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3138, 36, percentage_max_float,acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3139, 40, percentage_max_float,acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3140, 44, percentage_max_float,acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3141, 48, percentage_max_float,acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3142, 52, percentage_max_float,acmgt2__thread_dispatcher40__thread_dispatch_ps_active_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher41_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher41";
   query->symbol_name = "ThreadDispatcher41";
   query->guid = "c6251684-6ce6-462f-807c-657b84a2234f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C813C00 },
         { .reg = 0x00009888, .val = 0x2CA13C00 },
         { .reg = 0x00009888, .val = 0x2CC13C00 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810C37 },
         { .reg = 0x00009888, .val = 0x0A810CB1 },
         { .reg = 0x00009888, .val = 0x0C810033 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0CA10DC0 },
         { .reg = 0x00009888, .val = 0x0EA10C70 },
         { .reg = 0x00009888, .val = 0x10A10CF2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C37 },
         { .reg = 0x00009888, .val = 0x14C10CB1 },
         { .reg = 0x00009888, .val = 0x16C10033 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA0 },
         { .reg = 0x00009888, .val = 0x00C47C00 },
         { .reg = 0x00009888, .val = 0x02C61550 },
         { .reg = 0x00009888, .val = 0x02C71550 },
         { .reg = 0x00009888, .val = 0x02072AA0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x00097C00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A2AA5 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020B0005 },
         { .reg = 0x00009888, .val = 0x00027C00 },
         { .reg = 0x00009888, .val = 0x020C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030840 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030422 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher41__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher41__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher41__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher41__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1686, 24, NULL,acmgt2__thread_dispatcher41__gpgpu_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1687, 32, NULL,acmgt2__thread_dispatcher41__gpgpu_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1688, 40, NULL,acmgt2__thread_dispatcher41__gpgpu_dispatch_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher42_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher42";
   query->symbol_name = "ThreadDispatcher42";
   query->guid = "55cbe93c-e003-445a-95ca-478e9b8b9b51";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE13C00 },
         { .reg = 0x00009888, .val = 0x2D813C00 },
         { .reg = 0x00009888, .val = 0x2DA13C00 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10C37 },
         { .reg = 0x00009888, .val = 0x0AE10CB1 },
         { .reg = 0x00009888, .val = 0x0CE10033 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x0D810DC0 },
         { .reg = 0x00009888, .val = 0x0F810C70 },
         { .reg = 0x00009888, .val = 0x11810CF2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10C37 },
         { .reg = 0x00009888, .val = 0x15A10CB1 },
         { .reg = 0x00009888, .val = 0x17A10033 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32AA0 },
         { .reg = 0x00009888, .val = 0x01A47C00 },
         { .reg = 0x00009888, .val = 0x03A61550 },
         { .reg = 0x00009888, .val = 0x03A71550 },
         { .reg = 0x00009888, .val = 0x00037FE0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x03083FFA },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A1555 },
         { .reg = 0x00009888, .val = 0x01017C00 },
         { .reg = 0x00009888, .val = 0x030B1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030004 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x36031080 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x380308E4 },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher42__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher42__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher42__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher42__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1689, 24, NULL,acmgt2__thread_dispatcher42__gpgpu_dispatch_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1690, 32, NULL,acmgt2__thread_dispatcher42__gpgpu_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1691, 40, NULL,acmgt2__thread_dispatcher42__gpgpu_dispatch_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher43_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher43";
   query->symbol_name = "ThreadDispatcher43";
   query->guid = "9c9204e8-e9e6-4b93-975e-2fc874b22d9c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DC13C00 },
         { .reg = 0x00009888, .val = 0x2DE13C00 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10C37 },
         { .reg = 0x00009888, .val = 0x0BC10CB1 },
         { .reg = 0x00009888, .val = 0x0DC10033 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x0DE10DC0 },
         { .reg = 0x00009888, .val = 0x0FE10C70 },
         { .reg = 0x00009888, .val = 0x11E10CF2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x010756AA },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C813C00 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x12810C37 },
         { .reg = 0x00009888, .val = 0x14810CB1 },
         { .reg = 0x00009888, .val = 0x16810033 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02832AA0 },
         { .reg = 0x00009888, .val = 0x00847C00 },
         { .reg = 0x00009888, .val = 0x02861550 },
         { .reg = 0x00009888, .val = 0x02871550 },
         { .reg = 0x00009888, .val = 0x02082AA0 },
         { .reg = 0x00009888, .val = 0x020A1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009888, .val = 0x02023FF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032520 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017C00 },
         { .reg = 0x00009888, .val = 0x02021550 },
         { .reg = 0x00009888, .val = 0x02041550 },
         { .reg = 0x00009888, .val = 0x02051550 },
         { .reg = 0x00009888, .val = 0x02082AA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher43__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher43__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher43__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher43__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1692, 24, NULL,acmgt2__thread_dispatcher43__gpgpu_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1693, 32, NULL,acmgt2__thread_dispatcher43__gpgpu_dispatch_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3143, 40, NULL,acmgt2__thread_dispatcher43__gpgpu_dispatch_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher44_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher44";
   query->symbol_name = "ThreadDispatcher44";
   query->guid = "ea77a8e8-375a-46a7-a4cb-b0a40f3ff83a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA13C00 },
         { .reg = 0x00009888, .val = 0x2CC13C00 },
         { .reg = 0x00009888, .val = 0x2CE13C00 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10C37 },
         { .reg = 0x00009888, .val = 0x0AA10CB1 },
         { .reg = 0x00009888, .val = 0x0CA10033 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x0CC10DC0 },
         { .reg = 0x00009888, .val = 0x0EC10C70 },
         { .reg = 0x00009888, .val = 0x10C10CF2 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x12E10C37 },
         { .reg = 0x00009888, .val = 0x14E10CB1 },
         { .reg = 0x00009888, .val = 0x16E10033 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E32AA0 },
         { .reg = 0x00009888, .val = 0x00E47C00 },
         { .reg = 0x00009888, .val = 0x02E61550 },
         { .reg = 0x00009888, .val = 0x02E71550 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207155A },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00097FE0 },
         { .reg = 0x00009888, .val = 0x000AA955 },
         { .reg = 0x00009888, .val = 0x020A2AAA },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B0155 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023FFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032943 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030603 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher44__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher44__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher44__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher44__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3144, 24, NULL,acmgt2__thread_dispatcher44__gpgpu_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3145, 32, NULL,acmgt2__thread_dispatcher44__gpgpu_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3146, 40, NULL,acmgt2__thread_dispatcher44__gpgpu_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "ThreadDispatcher45";
   query->symbol_name = "ThreadDispatcher45";
   query->guid = "22202c50-f46b-4a14-aab6-15d079655616";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2D813C00 },
         { .reg = 0x00009888, .val = 0x2DA13C00 },
         { .reg = 0x00009888, .val = 0x2DC13C00 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810C37 },
         { .reg = 0x00009888, .val = 0x0B810CB1 },
         { .reg = 0x00009888, .val = 0x0D810033 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0DA10DC0 },
         { .reg = 0x00009888, .val = 0x0FA10C70 },
         { .reg = 0x00009888, .val = 0x11A10CF2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x13C10C37 },
         { .reg = 0x00009888, .val = 0x15C10CB1 },
         { .reg = 0x00009888, .val = 0x17C10033 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32AA0 },
         { .reg = 0x00009888, .val = 0x01C47C00 },
         { .reg = 0x00009888, .val = 0x03C61550 },
         { .reg = 0x00009888, .val = 0x03C71550 },
         { .reg = 0x00009888, .val = 0x00037FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x03072AA0 },
         { .reg = 0x00009888, .val = 0x0108FEAA },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x01097C00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A2AA5 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009888, .val = 0x01027C00 },
         { .reg = 0x00009888, .val = 0x030C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023FFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030840 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030422 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher45__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher45__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3147, 24, NULL,acmgt2__thread_dispatcher45__gpgpu_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3148, 32, NULL,acmgt2__thread_dispatcher45__gpgpu_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3149, 40, NULL,acmgt2__thread_dispatcher45__gpgpu_dispatch_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_thread_dispatcher46_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "ThreadDispatcher46";
   query->symbol_name = "ThreadDispatcher46";
   query->guid = "4d77eb41-a74f-4e76-a0ac-66a63d2ad7c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DE13C00 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10C37 },
         { .reg = 0x00009888, .val = 0x0BE10CB1 },
         { .reg = 0x00009888, .val = 0x0DE10033 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000203FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__thread_dispatcher46__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__thread_dispatcher46__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__thread_dispatcher46__avg_gpu_core_frequency__max,acmgt2__thread_dispatcher46__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3150, 24, NULL,acmgt2__thread_dispatcher46__gpgpu_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_urb1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "URB1";
   query->symbol_name = "URB1";
   query->guid = "f02fbce6-28cf-42d5-a07d-6a5c07e3baf6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x180703C0 },
         { .reg = 0x00009888, .val = 0x1A070180 },
         { .reg = 0x00009888, .val = 0x18080F00 },
         { .reg = 0x00009888, .val = 0x1A080180 },
         { .reg = 0x00009888, .val = 0x04072100 },
         { .reg = 0x00009888, .val = 0x08070840 },
         { .reg = 0x00009888, .val = 0x0A070020 },
         { .reg = 0x00009888, .val = 0x0E0704D4 },
         { .reg = 0x00009888, .val = 0x10070012 },
         { .reg = 0x00009888, .val = 0x14070597 },
         { .reg = 0x00009888, .val = 0x16070015 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0608C310 },
         { .reg = 0x00009888, .val = 0x0A0808E4 },
         { .reg = 0x00009888, .val = 0x0C080022 },
         { .reg = 0x00009888, .val = 0x100809A7 },
         { .reg = 0x00009888, .val = 0x12080025 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0009E38C },
         { .reg = 0x00009888, .val = 0x000A95A5 },
         { .reg = 0x00009888, .val = 0x020AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C63 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030060 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030003 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030003 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__urb1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__urb1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__urb1__avg_gpu_core_frequency__max,acmgt2__urb1__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1425, 24, NULL,acmgt2__urb1__urb_read_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1426, 32, NULL,acmgt2__urb1__urb_write_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 1427, 40, NULL,acmgt2__urb1__urb_cross_slice_read_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_urb2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "URB2";
   query->symbol_name = "URB2";
   query->guid = "1f749c36-964c-40d3-ac0f-3b8e24d4149b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x190703C0 },
         { .reg = 0x00009888, .val = 0x1B070180 },
         { .reg = 0x00009888, .val = 0x19080F00 },
         { .reg = 0x00009888, .val = 0x1B080180 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x05072100 },
         { .reg = 0x00009888, .val = 0x09070840 },
         { .reg = 0x00009888, .val = 0x0B070020 },
         { .reg = 0x00009888, .val = 0x0F0704D4 },
         { .reg = 0x00009888, .val = 0x11070012 },
         { .reg = 0x00009888, .val = 0x15070597 },
         { .reg = 0x00009888, .val = 0x17070015 },
         { .reg = 0x00009888, .val = 0x01070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x05080000 },
         { .reg = 0x00009888, .val = 0x0708C310 },
         { .reg = 0x00009888, .val = 0x0B0808E4 },
         { .reg = 0x00009888, .val = 0x0D080022 },
         { .reg = 0x00009888, .val = 0x110809A7 },
         { .reg = 0x00009888, .val = 0x13080025 },
         { .reg = 0x00009888, .val = 0x09080000 },
         { .reg = 0x00009888, .val = 0x01080000 },
         { .reg = 0x00009888, .val = 0x03080000 },
         { .reg = 0x00009888, .val = 0x0109E38C },
         { .reg = 0x00009888, .val = 0x010A95A5 },
         { .reg = 0x00009888, .val = 0x030AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C63 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030060 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030003 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030003 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__urb2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__urb2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__urb2__avg_gpu_core_frequency__max,acmgt2__urb2__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1428, 24, NULL,acmgt2__urb2__urb_read_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1429, 32, NULL,acmgt2__urb2__urb_write_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 1430, 40, NULL,acmgt2__urb2__urb_cross_slice_read_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_urb3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "URB3";
   query->symbol_name = "URB3";
   query->guid = "b7679a40-d48d-4994-8342-6277a37840ce";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x180703C0 },
         { .reg = 0x00009888, .val = 0x1A070180 },
         { .reg = 0x00009888, .val = 0x18080F00 },
         { .reg = 0x00009888, .val = 0x1A080180 },
         { .reg = 0x00009888, .val = 0x04072100 },
         { .reg = 0x00009888, .val = 0x08070840 },
         { .reg = 0x00009888, .val = 0x0A070020 },
         { .reg = 0x00009888, .val = 0x0E0704D4 },
         { .reg = 0x00009888, .val = 0x10070012 },
         { .reg = 0x00009888, .val = 0x14070597 },
         { .reg = 0x00009888, .val = 0x16070015 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0608C310 },
         { .reg = 0x00009888, .val = 0x0A0808E4 },
         { .reg = 0x00009888, .val = 0x0C080022 },
         { .reg = 0x00009888, .val = 0x100809A7 },
         { .reg = 0x00009888, .val = 0x12080025 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0009E38C },
         { .reg = 0x00009888, .val = 0x000A95A5 },
         { .reg = 0x00009888, .val = 0x020AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C63 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030060 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030003 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030003 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__urb3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__urb3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__urb3__avg_gpu_core_frequency__max,acmgt2__urb3__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 3151, 24, NULL,acmgt2__urb3__urb_read_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 3152, 32, NULL,acmgt2__urb3__urb_write_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 3153, 40, NULL,acmgt2__urb3__urb_cross_slice_read_slice2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_urb4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "URB4";
   query->symbol_name = "URB4";
   query->guid = "23924e32-c593-4b9f-905b-908c380fb0b9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x190703C0 },
         { .reg = 0x00009888, .val = 0x1B070180 },
         { .reg = 0x00009888, .val = 0x19080F00 },
         { .reg = 0x00009888, .val = 0x1B080180 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x05072100 },
         { .reg = 0x00009888, .val = 0x09070840 },
         { .reg = 0x00009888, .val = 0x0B070020 },
         { .reg = 0x00009888, .val = 0x0F0704D4 },
         { .reg = 0x00009888, .val = 0x11070012 },
         { .reg = 0x00009888, .val = 0x15070597 },
         { .reg = 0x00009888, .val = 0x17070015 },
         { .reg = 0x00009888, .val = 0x01070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x05080000 },
         { .reg = 0x00009888, .val = 0x0708C310 },
         { .reg = 0x00009888, .val = 0x0B0808E4 },
         { .reg = 0x00009888, .val = 0x0D080022 },
         { .reg = 0x00009888, .val = 0x110809A7 },
         { .reg = 0x00009888, .val = 0x13080025 },
         { .reg = 0x00009888, .val = 0x09080000 },
         { .reg = 0x00009888, .val = 0x01080000 },
         { .reg = 0x00009888, .val = 0x03080000 },
         { .reg = 0x00009888, .val = 0x0109E38C },
         { .reg = 0x00009888, .val = 0x010A95A5 },
         { .reg = 0x00009888, .val = 0x030AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030C63 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030060 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030600 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030003 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030003 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__urb4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__urb4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__urb4__avg_gpu_core_frequency__max,acmgt2__urb4__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 3154, 24, NULL,acmgt2__urb4__urb_read_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 3155, 32, NULL,acmgt2__urb4__urb_write_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 3156, 40, NULL,acmgt2__urb4__urb_cross_slice_read_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine1";
   query->symbol_name = "VectorEngine1";
   query->guid = "30376d17-f01b-44cb-b41e-43a606fe4e0d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0A900236 },
         { .reg = 0x00009888, .val = 0x0C90016A },
         { .reg = 0x00009888, .val = 0x009042B2 },
         { .reg = 0x00009888, .val = 0x02904E9C },
         { .reg = 0x00009888, .val = 0x04900717 },
         { .reg = 0x00009888, .val = 0x069000E6 },
         { .reg = 0x00009888, .val = 0x08900840 },
         { .reg = 0x00009888, .val = 0x00815555 },
         { .reg = 0x00009888, .val = 0x02815415 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283A82A },
         { .reg = 0x00009888, .val = 0x0084E7FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865415 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x02875415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine1__avg_gpu_core_frequency__max,acmgt2__vector_engine1__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1584, 24, percentage_max_float,acmgt2__vector_engine1__xve_stall_aluwr_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1585, 28, percentage_max_float,acmgt2__vector_engine1__xve_stall_barrier_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1586, 32, percentage_max_float,acmgt2__vector_engine1__xve_stall_instfetch_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1587, 36, percentage_max_float,acmgt2__vector_engine1__xve_stall_other_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1588, 40, percentage_max_float,acmgt2__vector_engine1__xve_stall_sbid_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1589, 44, percentage_max_float,acmgt2__vector_engine1__xve_stall_sendwr_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1590, 48, percentage_max_float,acmgt2__vector_engine1__xve_shared_function_access_hold_xecore0_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine2";
   query->symbol_name = "VectorEngine2";
   query->guid = "cbc51aeb-65c2-4bb6-8fb5-40a47800bf28";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AB00236 },
         { .reg = 0x00009888, .val = 0x0CB0016A },
         { .reg = 0x00009888, .val = 0x00B042B2 },
         { .reg = 0x00009888, .val = 0x02B04E9C },
         { .reg = 0x00009888, .val = 0x04B00717 },
         { .reg = 0x00009888, .val = 0x06B000E6 },
         { .reg = 0x00009888, .val = 0x08B00840 },
         { .reg = 0x00009888, .val = 0x00A15555 },
         { .reg = 0x00009888, .val = 0x02A15415 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3A82A },
         { .reg = 0x00009888, .val = 0x00A4E7FF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65415 },
         { .reg = 0x00009888, .val = 0x00A75555 },
         { .reg = 0x00009888, .val = 0x02A75415 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine2__avg_gpu_core_frequency__max,acmgt2__vector_engine2__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1591, 24, percentage_max_float,acmgt2__vector_engine2__xve_stall_aluwr_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1592, 28, percentage_max_float,acmgt2__vector_engine2__xve_stall_barrier_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1593, 32, percentage_max_float,acmgt2__vector_engine2__xve_stall_instfetch_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1594, 36, percentage_max_float,acmgt2__vector_engine2__xve_stall_other_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1595, 40, percentage_max_float,acmgt2__vector_engine2__xve_stall_sbid_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1596, 44, percentage_max_float,acmgt2__vector_engine2__xve_stall_sendwr_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1597, 48, percentage_max_float,acmgt2__vector_engine2__xve_shared_function_access_hold_xecore1_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine3";
   query->symbol_name = "VectorEngine3";
   query->guid = "48620eda-41d2-4684-b4da-0140d1cdc8ba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AD00236 },
         { .reg = 0x00009888, .val = 0x0CD0016A },
         { .reg = 0x00009888, .val = 0x00D042B2 },
         { .reg = 0x00009888, .val = 0x02D04E9C },
         { .reg = 0x00009888, .val = 0x04D00717 },
         { .reg = 0x00009888, .val = 0x06D000E6 },
         { .reg = 0x00009888, .val = 0x08D00840 },
         { .reg = 0x00009888, .val = 0x00C15555 },
         { .reg = 0x00009888, .val = 0x02C15415 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3A82A },
         { .reg = 0x00009888, .val = 0x00C4E7FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65415 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x02C75415 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207A82A },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009888, .val = 0x0002E7FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine3__avg_gpu_core_frequency__max,acmgt2__vector_engine3__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1598, 24, percentage_max_float,acmgt2__vector_engine3__xve_stall_aluwr_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1599, 28, percentage_max_float,acmgt2__vector_engine3__xve_stall_barrier_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1600, 32, percentage_max_float,acmgt2__vector_engine3__xve_stall_instfetch_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1601, 36, percentage_max_float,acmgt2__vector_engine3__xve_stall_other_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1602, 40, percentage_max_float,acmgt2__vector_engine3__xve_stall_sbid_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1603, 44, percentage_max_float,acmgt2__vector_engine3__xve_stall_sendwr_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1604, 48, percentage_max_float,acmgt2__vector_engine3__xve_shared_function_access_hold_xecore2_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine4";
   query->symbol_name = "VectorEngine4";
   query->guid = "4f2d3240-5242-48d7-8f25-1064a7044c01";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AF00236 },
         { .reg = 0x00009888, .val = 0x0CF0016A },
         { .reg = 0x00009888, .val = 0x00F042B2 },
         { .reg = 0x00009888, .val = 0x02F04E9C },
         { .reg = 0x00009888, .val = 0x04F00717 },
         { .reg = 0x00009888, .val = 0x06F000E6 },
         { .reg = 0x00009888, .val = 0x08F00840 },
         { .reg = 0x00009888, .val = 0x00E15555 },
         { .reg = 0x00009888, .val = 0x02E15415 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3A82A },
         { .reg = 0x00009888, .val = 0x00E4E7FF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65415 },
         { .reg = 0x00009888, .val = 0x00E75555 },
         { .reg = 0x00009888, .val = 0x02E75415 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075415 },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine4__avg_gpu_core_frequency__max,acmgt2__vector_engine4__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1605, 24, percentage_max_float,acmgt2__vector_engine4__xve_stall_aluwr_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1606, 28, percentage_max_float,acmgt2__vector_engine4__xve_stall_barrier_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1607, 32, percentage_max_float,acmgt2__vector_engine4__xve_stall_instfetch_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1608, 36, percentage_max_float,acmgt2__vector_engine4__xve_stall_other_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1609, 40, percentage_max_float,acmgt2__vector_engine4__xve_stall_sbid_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1610, 44, percentage_max_float,acmgt2__vector_engine4__xve_stall_sendwr_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1611, 48, percentage_max_float,acmgt2__vector_engine4__xve_shared_function_access_hold_xecore3_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine5";
   query->symbol_name = "VectorEngine5";
   query->guid = "510e005b-5631-437d-b898-17d89b9df71d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0B900236 },
         { .reg = 0x00009888, .val = 0x0D90016A },
         { .reg = 0x00009888, .val = 0x019042B2 },
         { .reg = 0x00009888, .val = 0x03904E9C },
         { .reg = 0x00009888, .val = 0x05900717 },
         { .reg = 0x00009888, .val = 0x079000E6 },
         { .reg = 0x00009888, .val = 0x09900840 },
         { .reg = 0x00009888, .val = 0x01815555 },
         { .reg = 0x00009888, .val = 0x03815415 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383A82A },
         { .reg = 0x00009888, .val = 0x0184E7FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865415 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x03875415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308A82A },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine5__avg_gpu_core_frequency__max,acmgt2__vector_engine5__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1612, 24, percentage_max_float,acmgt2__vector_engine5__xve_stall_aluwr_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1613, 28, percentage_max_float,acmgt2__vector_engine5__xve_stall_barrier_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1614, 32, percentage_max_float,acmgt2__vector_engine5__xve_stall_instfetch_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1615, 36, percentage_max_float,acmgt2__vector_engine5__xve_stall_other_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1616, 40, percentage_max_float,acmgt2__vector_engine5__xve_stall_sbid_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1617, 44, percentage_max_float,acmgt2__vector_engine5__xve_stall_sendwr_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1618, 48, percentage_max_float,acmgt2__vector_engine5__xve_shared_function_access_hold_xecore4_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine6";
   query->symbol_name = "VectorEngine6";
   query->guid = "c063d6a9-6cb2-449f-8799-322c31d6eb0d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BB00236 },
         { .reg = 0x00009888, .val = 0x0DB0016A },
         { .reg = 0x00009888, .val = 0x01B042B2 },
         { .reg = 0x00009888, .val = 0x03B04E9C },
         { .reg = 0x00009888, .val = 0x05B00717 },
         { .reg = 0x00009888, .val = 0x07B000E6 },
         { .reg = 0x00009888, .val = 0x09B00840 },
         { .reg = 0x00009888, .val = 0x01A15555 },
         { .reg = 0x00009888, .val = 0x03A15415 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3A82A },
         { .reg = 0x00009888, .val = 0x01A4E7FF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65415 },
         { .reg = 0x00009888, .val = 0x01A75555 },
         { .reg = 0x00009888, .val = 0x03A75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FC3F },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009888, .val = 0x0101E7FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine6__avg_gpu_core_frequency__max,acmgt2__vector_engine6__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1619, 24, percentage_max_float,acmgt2__vector_engine6__xve_stall_aluwr_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1620, 28, percentage_max_float,acmgt2__vector_engine6__xve_stall_barrier_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1621, 32, percentage_max_float,acmgt2__vector_engine6__xve_stall_instfetch_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1622, 36, percentage_max_float,acmgt2__vector_engine6__xve_stall_other_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1623, 40, percentage_max_float,acmgt2__vector_engine6__xve_stall_sbid_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1624, 44, percentage_max_float,acmgt2__vector_engine6__xve_stall_sendwr_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1625, 48, percentage_max_float,acmgt2__vector_engine6__xve_shared_function_access_hold_xecore5_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine7";
   query->symbol_name = "VectorEngine7";
   query->guid = "fbfb8b12-d3b3-469d-ae93-c026b05b2107";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BD00236 },
         { .reg = 0x00009888, .val = 0x0DD0016A },
         { .reg = 0x00009888, .val = 0x01D042B2 },
         { .reg = 0x00009888, .val = 0x03D04E9C },
         { .reg = 0x00009888, .val = 0x05D00717 },
         { .reg = 0x00009888, .val = 0x07D000E6 },
         { .reg = 0x00009888, .val = 0x09D00840 },
         { .reg = 0x00009888, .val = 0x01C15555 },
         { .reg = 0x00009888, .val = 0x03C15415 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3A82A },
         { .reg = 0x00009888, .val = 0x01C4E7FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65415 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x03C75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307A82A },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009888, .val = 0x0102E7FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine7__avg_gpu_core_frequency__max,acmgt2__vector_engine7__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1626, 24, percentage_max_float,acmgt2__vector_engine7__xve_stall_aluwr_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1627, 28, percentage_max_float,acmgt2__vector_engine7__xve_stall_barrier_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1628, 32, percentage_max_float,acmgt2__vector_engine7__xve_stall_instfetch_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1629, 36, percentage_max_float,acmgt2__vector_engine7__xve_stall_other_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1630, 40, percentage_max_float,acmgt2__vector_engine7__xve_stall_sbid_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1631, 44, percentage_max_float,acmgt2__vector_engine7__xve_stall_sendwr_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1632, 48, percentage_max_float,acmgt2__vector_engine7__xve_shared_function_access_hold_xecore6_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine8";
   query->symbol_name = "VectorEngine8";
   query->guid = "2705f48c-206f-43e8-bde7-110fbfb0facd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BF00236 },
         { .reg = 0x00009888, .val = 0x0DF0016A },
         { .reg = 0x00009888, .val = 0x01F042B2 },
         { .reg = 0x00009888, .val = 0x03F04E9C },
         { .reg = 0x00009888, .val = 0x05F00717 },
         { .reg = 0x00009888, .val = 0x07F000E6 },
         { .reg = 0x00009888, .val = 0x09F00840 },
         { .reg = 0x00009888, .val = 0x01E15555 },
         { .reg = 0x00009888, .val = 0x03E15415 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3A82A },
         { .reg = 0x00009888, .val = 0x01E4E7FF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65415 },
         { .reg = 0x00009888, .val = 0x01E75555 },
         { .reg = 0x00009888, .val = 0x03E75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075415 },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine8__avg_gpu_core_frequency__max,acmgt2__vector_engine8__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1633, 24, percentage_max_float,acmgt2__vector_engine8__xve_stall_aluwr_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1634, 28, percentage_max_float,acmgt2__vector_engine8__xve_stall_barrier_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1635, 32, percentage_max_float,acmgt2__vector_engine8__xve_stall_instfetch_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1636, 36, percentage_max_float,acmgt2__vector_engine8__xve_stall_other_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1637, 40, percentage_max_float,acmgt2__vector_engine8__xve_stall_sbid_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1638, 44, percentage_max_float,acmgt2__vector_engine8__xve_stall_sendwr_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1639, 48, percentage_max_float,acmgt2__vector_engine8__xve_shared_function_access_hold_xecore7_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine9";
   query->symbol_name = "VectorEngine9";
   query->guid = "85cb3e85-43ab-4e7f-8962-ff5e203b079f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0A900236 },
         { .reg = 0x00009888, .val = 0x0C90016A },
         { .reg = 0x00009888, .val = 0x009042B2 },
         { .reg = 0x00009888, .val = 0x02904E9C },
         { .reg = 0x00009888, .val = 0x04900717 },
         { .reg = 0x00009888, .val = 0x069000E6 },
         { .reg = 0x00009888, .val = 0x08900840 },
         { .reg = 0x00009888, .val = 0x00815555 },
         { .reg = 0x00009888, .val = 0x02815415 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283A82A },
         { .reg = 0x00009888, .val = 0x0084E7FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865415 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x02875415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FC3F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine9__avg_gpu_core_frequency__max,acmgt2__vector_engine9__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3157, 24, percentage_max_float,acmgt2__vector_engine9__xve_stall_aluwr_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3158, 28, percentage_max_float,acmgt2__vector_engine9__xve_stall_barrier_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3159, 32, percentage_max_float,acmgt2__vector_engine9__xve_stall_instfetch_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3160, 36, percentage_max_float,acmgt2__vector_engine9__xve_stall_other_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3161, 40, percentage_max_float,acmgt2__vector_engine9__xve_stall_sbid_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3162, 44, percentage_max_float,acmgt2__vector_engine9__xve_stall_sendwr_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3163, 48, percentage_max_float,acmgt2__vector_engine9__xve_shared_function_access_hold_xecore8_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine10";
   query->symbol_name = "VectorEngine10";
   query->guid = "b2c23ce7-cfd8-45c8-bde6-b5d7c248b5b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0AB00236 },
         { .reg = 0x00009888, .val = 0x0CB0016A },
         { .reg = 0x00009888, .val = 0x00B042B2 },
         { .reg = 0x00009888, .val = 0x02B04E9C },
         { .reg = 0x00009888, .val = 0x04B00717 },
         { .reg = 0x00009888, .val = 0x06B000E6 },
         { .reg = 0x00009888, .val = 0x08B00840 },
         { .reg = 0x00009888, .val = 0x00A15555 },
         { .reg = 0x00009888, .val = 0x02A15415 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3A82A },
         { .reg = 0x00009888, .val = 0x00A4E7FF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65415 },
         { .reg = 0x00009888, .val = 0x00A75555 },
         { .reg = 0x00009888, .val = 0x02A75415 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FC3F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine10__avg_gpu_core_frequency__max,acmgt2__vector_engine10__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3164, 24, percentage_max_float,acmgt2__vector_engine10__xve_stall_aluwr_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3165, 28, percentage_max_float,acmgt2__vector_engine10__xve_stall_barrier_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3166, 32, percentage_max_float,acmgt2__vector_engine10__xve_stall_instfetch_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3167, 36, percentage_max_float,acmgt2__vector_engine10__xve_stall_other_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3168, 40, percentage_max_float,acmgt2__vector_engine10__xve_stall_sbid_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3169, 44, percentage_max_float,acmgt2__vector_engine10__xve_stall_sendwr_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3170, 48, percentage_max_float,acmgt2__vector_engine10__xve_shared_function_access_hold_xecore9_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine11";
   query->symbol_name = "VectorEngine11";
   query->guid = "567eef44-e37e-48d9-8f4d-fe2634110051";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0AD00236 },
         { .reg = 0x00009888, .val = 0x0CD0016A },
         { .reg = 0x00009888, .val = 0x00D042B2 },
         { .reg = 0x00009888, .val = 0x02D04E9C },
         { .reg = 0x00009888, .val = 0x04D00717 },
         { .reg = 0x00009888, .val = 0x06D000E6 },
         { .reg = 0x00009888, .val = 0x08D00840 },
         { .reg = 0x00009888, .val = 0x00C15555 },
         { .reg = 0x00009888, .val = 0x02C15415 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3A82A },
         { .reg = 0x00009888, .val = 0x00C4E7FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65415 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x02C75415 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207A82A },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009888, .val = 0x0002E7FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FC3F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine11__avg_gpu_core_frequency__max,acmgt2__vector_engine11__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3171, 24, percentage_max_float,acmgt2__vector_engine11__xve_stall_aluwr_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3172, 28, percentage_max_float,acmgt2__vector_engine11__xve_stall_barrier_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3173, 32, percentage_max_float,acmgt2__vector_engine11__xve_stall_instfetch_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3174, 36, percentage_max_float,acmgt2__vector_engine11__xve_stall_other_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3175, 40, percentage_max_float,acmgt2__vector_engine11__xve_stall_sbid_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3176, 44, percentage_max_float,acmgt2__vector_engine11__xve_stall_sendwr_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3177, 48, percentage_max_float,acmgt2__vector_engine11__xve_shared_function_access_hold_xecore10_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine12";
   query->symbol_name = "VectorEngine12";
   query->guid = "d68e64a7-2ddb-4c33-a5d0-a0ff9de398f9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0AF00236 },
         { .reg = 0x00009888, .val = 0x0CF0016A },
         { .reg = 0x00009888, .val = 0x00F042B2 },
         { .reg = 0x00009888, .val = 0x02F04E9C },
         { .reg = 0x00009888, .val = 0x04F00717 },
         { .reg = 0x00009888, .val = 0x06F000E6 },
         { .reg = 0x00009888, .val = 0x08F00840 },
         { .reg = 0x00009888, .val = 0x00E15555 },
         { .reg = 0x00009888, .val = 0x02E15415 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3A82A },
         { .reg = 0x00009888, .val = 0x00E4E7FF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65415 },
         { .reg = 0x00009888, .val = 0x00E75555 },
         { .reg = 0x00009888, .val = 0x02E75415 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075415 },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FC3F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine12__avg_gpu_core_frequency__max,acmgt2__vector_engine12__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3178, 24, percentage_max_float,acmgt2__vector_engine12__xve_stall_aluwr_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3179, 28, percentage_max_float,acmgt2__vector_engine12__xve_stall_barrier_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3180, 32, percentage_max_float,acmgt2__vector_engine12__xve_stall_instfetch_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3181, 36, percentage_max_float,acmgt2__vector_engine12__xve_stall_other_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3182, 40, percentage_max_float,acmgt2__vector_engine12__xve_stall_sbid_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3183, 44, percentage_max_float,acmgt2__vector_engine12__xve_stall_sendwr_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3184, 48, percentage_max_float,acmgt2__vector_engine12__xve_shared_function_access_hold_xecore11_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine13";
   query->symbol_name = "VectorEngine13";
   query->guid = "5123cfe9-f7b0-41ee-a2f2-6e5801ac55f6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0B900236 },
         { .reg = 0x00009888, .val = 0x0D90016A },
         { .reg = 0x00009888, .val = 0x019042B2 },
         { .reg = 0x00009888, .val = 0x03904E9C },
         { .reg = 0x00009888, .val = 0x05900717 },
         { .reg = 0x00009888, .val = 0x079000E6 },
         { .reg = 0x00009888, .val = 0x09900840 },
         { .reg = 0x00009888, .val = 0x01815555 },
         { .reg = 0x00009888, .val = 0x03815415 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383A82A },
         { .reg = 0x00009888, .val = 0x0184E7FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865415 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x03875415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308A82A },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FC3F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine13__avg_gpu_core_frequency__max,acmgt2__vector_engine13__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3185, 24, percentage_max_float,acmgt2__vector_engine13__xve_stall_aluwr_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3186, 28, percentage_max_float,acmgt2__vector_engine13__xve_stall_barrier_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3187, 32, percentage_max_float,acmgt2__vector_engine13__xve_stall_instfetch_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3188, 36, percentage_max_float,acmgt2__vector_engine13__xve_stall_other_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3189, 40, percentage_max_float,acmgt2__vector_engine13__xve_stall_sbid_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3190, 44, percentage_max_float,acmgt2__vector_engine13__xve_stall_sendwr_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3191, 48, percentage_max_float,acmgt2__vector_engine13__xve_shared_function_access_hold_xecore12_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine14";
   query->symbol_name = "VectorEngine14";
   query->guid = "f7b22238-61e9-4c17-a211-90f5feb9dd31";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0BB00236 },
         { .reg = 0x00009888, .val = 0x0DB0016A },
         { .reg = 0x00009888, .val = 0x01B042B2 },
         { .reg = 0x00009888, .val = 0x03B04E9C },
         { .reg = 0x00009888, .val = 0x05B00717 },
         { .reg = 0x00009888, .val = 0x07B000E6 },
         { .reg = 0x00009888, .val = 0x09B00840 },
         { .reg = 0x00009888, .val = 0x01A15555 },
         { .reg = 0x00009888, .val = 0x03A15415 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3A82A },
         { .reg = 0x00009888, .val = 0x01A4E7FF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65415 },
         { .reg = 0x00009888, .val = 0x01A75555 },
         { .reg = 0x00009888, .val = 0x03A75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FC3F },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009888, .val = 0x0101E7FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FC3F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine14__avg_gpu_core_frequency__max,acmgt2__vector_engine14__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3192, 24, percentage_max_float,acmgt2__vector_engine14__xve_stall_aluwr_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3193, 28, percentage_max_float,acmgt2__vector_engine14__xve_stall_barrier_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3194, 32, percentage_max_float,acmgt2__vector_engine14__xve_stall_instfetch_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3195, 36, percentage_max_float,acmgt2__vector_engine14__xve_stall_other_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3196, 40, percentage_max_float,acmgt2__vector_engine14__xve_stall_sbid_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3197, 44, percentage_max_float,acmgt2__vector_engine14__xve_stall_sendwr_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3198, 48, percentage_max_float,acmgt2__vector_engine14__xve_shared_function_access_hold_xecore13_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine15";
   query->symbol_name = "VectorEngine15";
   query->guid = "27f15518-fd8e-48ac-8fa8-f844a09a9cf3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0BD00236 },
         { .reg = 0x00009888, .val = 0x0DD0016A },
         { .reg = 0x00009888, .val = 0x01D042B2 },
         { .reg = 0x00009888, .val = 0x03D04E9C },
         { .reg = 0x00009888, .val = 0x05D00717 },
         { .reg = 0x00009888, .val = 0x07D000E6 },
         { .reg = 0x00009888, .val = 0x09D00840 },
         { .reg = 0x00009888, .val = 0x01C15555 },
         { .reg = 0x00009888, .val = 0x03C15415 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3A82A },
         { .reg = 0x00009888, .val = 0x01C4E7FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65415 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x03C75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307A82A },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009888, .val = 0x0102E7FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FC3F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine15__avg_gpu_core_frequency__max,acmgt2__vector_engine15__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3199, 24, percentage_max_float,acmgt2__vector_engine15__xve_stall_aluwr_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3200, 28, percentage_max_float,acmgt2__vector_engine15__xve_stall_barrier_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3201, 32, percentage_max_float,acmgt2__vector_engine15__xve_stall_instfetch_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3202, 36, percentage_max_float,acmgt2__vector_engine15__xve_stall_other_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3203, 40, percentage_max_float,acmgt2__vector_engine15__xve_stall_sbid_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3204, 44, percentage_max_float,acmgt2__vector_engine15__xve_stall_sendwr_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3205, 48, percentage_max_float,acmgt2__vector_engine15__xve_shared_function_access_hold_xecore14_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "VectorEngine16";
   query->symbol_name = "VectorEngine16";
   query->guid = "75bcab1e-545a-41a4-8437-70d37569f798";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0BF00236 },
         { .reg = 0x00009888, .val = 0x0DF0016A },
         { .reg = 0x00009888, .val = 0x01F042B2 },
         { .reg = 0x00009888, .val = 0x03F04E9C },
         { .reg = 0x00009888, .val = 0x05F00717 },
         { .reg = 0x00009888, .val = 0x07F000E6 },
         { .reg = 0x00009888, .val = 0x09F00840 },
         { .reg = 0x00009888, .val = 0x01E15555 },
         { .reg = 0x00009888, .val = 0x03E15415 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3A82A },
         { .reg = 0x00009888, .val = 0x01E4E7FF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65415 },
         { .reg = 0x00009888, .val = 0x01E75555 },
         { .reg = 0x00009888, .val = 0x03E75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075415 },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FC3F },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine16__avg_gpu_core_frequency__max,acmgt2__vector_engine16__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3206, 24, percentage_max_float,acmgt2__vector_engine16__xve_stall_aluwr_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3207, 28, percentage_max_float,acmgt2__vector_engine16__xve_stall_barrier_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3208, 32, percentage_max_float,acmgt2__vector_engine16__xve_stall_instfetch_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3209, 36, percentage_max_float,acmgt2__vector_engine16__xve_stall_other_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3210, 40, percentage_max_float,acmgt2__vector_engine16__xve_stall_sbid_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3211, 44, percentage_max_float,acmgt2__vector_engine16__xve_stall_sendwr_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3212, 48, percentage_max_float,acmgt2__vector_engine16__xve_shared_function_access_hold_xecore15_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "VectorEngine17";
   query->symbol_name = "VectorEngine17";
   query->guid = "5f1c4a7a-d5ab-45ad-a4fc-1e64a66839db";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1882000C },
         { .reg = 0x00009888, .val = 0x18A2000C },
         { .reg = 0x00009888, .val = 0x18C2000C },
         { .reg = 0x00009888, .val = 0x18E2000C },
         { .reg = 0x00009888, .val = 0x1982000C },
         { .reg = 0x00009888, .val = 0x19A2000C },
         { .reg = 0x00009888, .val = 0x19C2000C },
         { .reg = 0x00009888, .val = 0x19E2000C },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine17__avg_gpu_core_frequency__max,acmgt2__vector_engine17__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1794, 24, NULL,acmgt2__vector_engine17__icache_hit_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1796, 32, NULL,acmgt2__vector_engine17__icache_hit_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1798, 40, NULL,acmgt2__vector_engine17__icache_hit_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1800, 48, NULL,acmgt2__vector_engine17__icache_hit_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1802, 56, NULL,acmgt2__vector_engine17__icache_hit_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1804, 64, NULL,acmgt2__vector_engine17__icache_hit_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1806, 72, NULL,acmgt2__vector_engine17__icache_hit_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1808, 80, NULL,acmgt2__vector_engine17__icache_hit_bank0_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1795, 88, NULL,acmgt2__vector_engine17__icache_miss_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1797, 96, NULL,acmgt2__vector_engine17__icache_miss_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1799, 104, NULL,acmgt2__vector_engine17__icache_miss_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1801, 112, NULL,acmgt2__vector_engine17__icache_miss_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1803, 120, NULL,acmgt2__vector_engine17__icache_miss_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1805, 128, NULL,acmgt2__vector_engine17__icache_miss_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1807, 136, NULL,acmgt2__vector_engine17__icache_miss_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1809, 144, NULL,acmgt2__vector_engine17__icache_miss_bank0_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "VectorEngine18";
   query->symbol_name = "VectorEngine18";
   query->guid = "c3522b36-01a6-4b3d-b95f-414dbc013ba6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1882000C },
         { .reg = 0x00009888, .val = 0x18A2000C },
         { .reg = 0x00009888, .val = 0x18C2000C },
         { .reg = 0x00009888, .val = 0x18E2000C },
         { .reg = 0x00009888, .val = 0x1982000C },
         { .reg = 0x00009888, .val = 0x19A2000C },
         { .reg = 0x00009888, .val = 0x19C2000C },
         { .reg = 0x00009888, .val = 0x19E2000C },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine18__avg_gpu_core_frequency__max,acmgt2__vector_engine18__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3213, 24, NULL,acmgt2__vector_engine18__icache_hit_bank0_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3214, 32, NULL,acmgt2__vector_engine18__icache_hit_bank0_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3215, 40, NULL,acmgt2__vector_engine18__icache_hit_bank0_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3216, 48, NULL,acmgt2__vector_engine18__icache_hit_bank0_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3217, 56, NULL,acmgt2__vector_engine18__icache_hit_bank0_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3218, 64, NULL,acmgt2__vector_engine18__icache_hit_bank0_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3219, 72, NULL,acmgt2__vector_engine18__icache_hit_bank0_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3220, 80, NULL,acmgt2__vector_engine18__icache_hit_bank0_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3221, 88, NULL,acmgt2__vector_engine18__icache_miss_bank0_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3222, 96, NULL,acmgt2__vector_engine18__icache_miss_bank0_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3223, 104, NULL,acmgt2__vector_engine18__icache_miss_bank0_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3224, 112, NULL,acmgt2__vector_engine18__icache_miss_bank0_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3225, 120, NULL,acmgt2__vector_engine18__icache_miss_bank0_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3226, 128, NULL,acmgt2__vector_engine18__icache_miss_bank0_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3227, 136, NULL,acmgt2__vector_engine18__icache_miss_bank0_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3228, 144, NULL,acmgt2__vector_engine18__icache_miss_bank0_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine19_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "VectorEngine19";
   query->symbol_name = "VectorEngine19";
   query->guid = "3e973327-7b3f-4168-afd9-b244050e9ce7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18820011 },
         { .reg = 0x00009888, .val = 0x18A20011 },
         { .reg = 0x00009888, .val = 0x18C20011 },
         { .reg = 0x00009888, .val = 0x18E20011 },
         { .reg = 0x00009888, .val = 0x19820011 },
         { .reg = 0x00009888, .val = 0x19A20011 },
         { .reg = 0x00009888, .val = 0x19C20011 },
         { .reg = 0x00009888, .val = 0x19E20011 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine19__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine19__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine19__avg_gpu_core_frequency__max,acmgt2__vector_engine19__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1810, 24, NULL,acmgt2__vector_engine19__icache_hit_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1812, 32, NULL,acmgt2__vector_engine19__icache_hit_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1814, 40, NULL,acmgt2__vector_engine19__icache_hit_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1816, 48, NULL,acmgt2__vector_engine19__icache_hit_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1818, 56, NULL,acmgt2__vector_engine19__icache_hit_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1820, 64, NULL,acmgt2__vector_engine19__icache_hit_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1822, 72, NULL,acmgt2__vector_engine19__icache_hit_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1824, 80, NULL,acmgt2__vector_engine19__icache_hit_bank1_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1811, 88, NULL,acmgt2__vector_engine19__icache_miss_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1813, 96, NULL,acmgt2__vector_engine19__icache_miss_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1815, 104, NULL,acmgt2__vector_engine19__icache_miss_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1817, 112, NULL,acmgt2__vector_engine19__icache_miss_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1819, 120, NULL,acmgt2__vector_engine19__icache_miss_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1821, 128, NULL,acmgt2__vector_engine19__icache_miss_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1823, 136, NULL,acmgt2__vector_engine19__icache_miss_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1825, 144, NULL,acmgt2__vector_engine19__icache_miss_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine20_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "VectorEngine20";
   query->symbol_name = "VectorEngine20";
   query->guid = "71d2d15b-f26c-4978-908a-f60275fa3562";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18820011 },
         { .reg = 0x00009888, .val = 0x18A20011 },
         { .reg = 0x00009888, .val = 0x18C20011 },
         { .reg = 0x00009888, .val = 0x18E20011 },
         { .reg = 0x00009888, .val = 0x19820011 },
         { .reg = 0x00009888, .val = 0x19A20011 },
         { .reg = 0x00009888, .val = 0x19C20011 },
         { .reg = 0x00009888, .val = 0x19E20011 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine20__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine20__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine20__avg_gpu_core_frequency__max,acmgt2__vector_engine20__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3229, 24, NULL,acmgt2__vector_engine20__icache_hit_bank1_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3230, 32, NULL,acmgt2__vector_engine20__icache_hit_bank1_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3231, 40, NULL,acmgt2__vector_engine20__icache_hit_bank1_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3232, 48, NULL,acmgt2__vector_engine20__icache_hit_bank1_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3233, 56, NULL,acmgt2__vector_engine20__icache_hit_bank1_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3234, 64, NULL,acmgt2__vector_engine20__icache_hit_bank1_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3235, 72, NULL,acmgt2__vector_engine20__icache_hit_bank1_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3236, 80, NULL,acmgt2__vector_engine20__icache_hit_bank1_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3237, 88, NULL,acmgt2__vector_engine20__icache_miss_bank1_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3238, 96, NULL,acmgt2__vector_engine20__icache_miss_bank1_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3239, 104, NULL,acmgt2__vector_engine20__icache_miss_bank1_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3240, 112, NULL,acmgt2__vector_engine20__icache_miss_bank1_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3241, 120, NULL,acmgt2__vector_engine20__icache_miss_bank1_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3242, 128, NULL,acmgt2__vector_engine20__icache_miss_bank1_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3243, 136, NULL,acmgt2__vector_engine20__icache_miss_bank1_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3244, 144, NULL,acmgt2__vector_engine20__icache_miss_bank1_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "VectorEngine21";
   query->symbol_name = "VectorEngine21";
   query->guid = "83cf4cf3-b666-44df-8702-7fc3e907164a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18820016 },
         { .reg = 0x00009888, .val = 0x18A20016 },
         { .reg = 0x00009888, .val = 0x18C20016 },
         { .reg = 0x00009888, .val = 0x18E20016 },
         { .reg = 0x00009888, .val = 0x19820016 },
         { .reg = 0x00009888, .val = 0x19A20016 },
         { .reg = 0x00009888, .val = 0x19C20016 },
         { .reg = 0x00009888, .val = 0x19E20016 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine21__avg_gpu_core_frequency__max,acmgt2__vector_engine21__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1826, 24, NULL,acmgt2__vector_engine21__icache_hit_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1828, 32, NULL,acmgt2__vector_engine21__icache_hit_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1830, 40, NULL,acmgt2__vector_engine21__icache_hit_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1832, 48, NULL,acmgt2__vector_engine21__icache_hit_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1834, 56, NULL,acmgt2__vector_engine21__icache_hit_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1836, 64, NULL,acmgt2__vector_engine21__icache_hit_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1838, 72, NULL,acmgt2__vector_engine21__icache_hit_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1840, 80, NULL,acmgt2__vector_engine21__icache_hit_bank2_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1827, 88, NULL,acmgt2__vector_engine21__icache_miss_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1829, 96, NULL,acmgt2__vector_engine21__icache_miss_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1831, 104, NULL,acmgt2__vector_engine21__icache_miss_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1833, 112, NULL,acmgt2__vector_engine21__icache_miss_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1835, 120, NULL,acmgt2__vector_engine21__icache_miss_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1837, 128, NULL,acmgt2__vector_engine21__icache_miss_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1839, 136, NULL,acmgt2__vector_engine21__icache_miss_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1841, 144, NULL,acmgt2__vector_engine21__icache_miss_bank2_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "VectorEngine22";
   query->symbol_name = "VectorEngine22";
   query->guid = "c6b408ba-0479-40cb-8326-0fb1d709a261";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18820016 },
         { .reg = 0x00009888, .val = 0x18A20016 },
         { .reg = 0x00009888, .val = 0x18C20016 },
         { .reg = 0x00009888, .val = 0x18E20016 },
         { .reg = 0x00009888, .val = 0x19820016 },
         { .reg = 0x00009888, .val = 0x19A20016 },
         { .reg = 0x00009888, .val = 0x19C20016 },
         { .reg = 0x00009888, .val = 0x19E20016 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine22__avg_gpu_core_frequency__max,acmgt2__vector_engine22__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3245, 24, NULL,acmgt2__vector_engine22__icache_hit_bank2_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3246, 32, NULL,acmgt2__vector_engine22__icache_hit_bank2_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3247, 40, NULL,acmgt2__vector_engine22__icache_hit_bank2_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3248, 48, NULL,acmgt2__vector_engine22__icache_hit_bank2_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3249, 56, NULL,acmgt2__vector_engine22__icache_hit_bank2_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3250, 64, NULL,acmgt2__vector_engine22__icache_hit_bank2_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3251, 72, NULL,acmgt2__vector_engine22__icache_hit_bank2_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3252, 80, NULL,acmgt2__vector_engine22__icache_hit_bank2_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3253, 88, NULL,acmgt2__vector_engine22__icache_miss_bank2_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3254, 96, NULL,acmgt2__vector_engine22__icache_miss_bank2_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3255, 104, NULL,acmgt2__vector_engine22__icache_miss_bank2_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3256, 112, NULL,acmgt2__vector_engine22__icache_miss_bank2_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3257, 120, NULL,acmgt2__vector_engine22__icache_miss_bank2_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3258, 128, NULL,acmgt2__vector_engine22__icache_miss_bank2_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3259, 136, NULL,acmgt2__vector_engine22__icache_miss_bank2_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3260, 144, NULL,acmgt2__vector_engine22__icache_miss_bank2_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "VectorEngine23";
   query->symbol_name = "VectorEngine23";
   query->guid = "1f43061b-db78-405a-9246-6df8ff0592f4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1882001B },
         { .reg = 0x00009888, .val = 0x18A2001B },
         { .reg = 0x00009888, .val = 0x18C2001B },
         { .reg = 0x00009888, .val = 0x18E2001B },
         { .reg = 0x00009888, .val = 0x1982001B },
         { .reg = 0x00009888, .val = 0x19A2001B },
         { .reg = 0x00009888, .val = 0x19C2001B },
         { .reg = 0x00009888, .val = 0x19E2001B },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine23__avg_gpu_core_frequency__max,acmgt2__vector_engine23__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1842, 24, NULL,acmgt2__vector_engine23__icache_hit_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1844, 32, NULL,acmgt2__vector_engine23__icache_hit_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1846, 40, NULL,acmgt2__vector_engine23__icache_hit_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1848, 48, NULL,acmgt2__vector_engine23__icache_hit_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1850, 56, NULL,acmgt2__vector_engine23__icache_hit_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1852, 64, NULL,acmgt2__vector_engine23__icache_hit_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1854, 72, NULL,acmgt2__vector_engine23__icache_hit_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1856, 80, NULL,acmgt2__vector_engine23__icache_hit_bank3_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1843, 88, NULL,acmgt2__vector_engine23__icache_miss_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1845, 96, NULL,acmgt2__vector_engine23__icache_miss_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1847, 104, NULL,acmgt2__vector_engine23__icache_miss_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1849, 112, NULL,acmgt2__vector_engine23__icache_miss_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1851, 120, NULL,acmgt2__vector_engine23__icache_miss_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1853, 128, NULL,acmgt2__vector_engine23__icache_miss_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1855, 136, NULL,acmgt2__vector_engine23__icache_miss_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1857, 144, NULL,acmgt2__vector_engine23__icache_miss_bank3_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine24_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "VectorEngine24";
   query->symbol_name = "VectorEngine24";
   query->guid = "7aa880f9-6185-4b35-9d71-45cd71099d1c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1882001B },
         { .reg = 0x00009888, .val = 0x18A2001B },
         { .reg = 0x00009888, .val = 0x18C2001B },
         { .reg = 0x00009888, .val = 0x18E2001B },
         { .reg = 0x00009888, .val = 0x1982001B },
         { .reg = 0x00009888, .val = 0x19A2001B },
         { .reg = 0x00009888, .val = 0x19C2001B },
         { .reg = 0x00009888, .val = 0x19E2001B },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x3203086A },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x3603200A },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x38030427 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C031400 },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34030107 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine24__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine24__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine24__avg_gpu_core_frequency__max,acmgt2__vector_engine24__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3261, 24, NULL,acmgt2__vector_engine24__icache_hit_bank3_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3262, 32, NULL,acmgt2__vector_engine24__icache_hit_bank3_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3263, 40, NULL,acmgt2__vector_engine24__icache_hit_bank3_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3264, 48, NULL,acmgt2__vector_engine24__icache_hit_bank3_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3265, 56, NULL,acmgt2__vector_engine24__icache_hit_bank3_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3266, 64, NULL,acmgt2__vector_engine24__icache_hit_bank3_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3267, 72, NULL,acmgt2__vector_engine24__icache_hit_bank3_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3268, 80, NULL,acmgt2__vector_engine24__icache_hit_bank3_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3269, 88, NULL,acmgt2__vector_engine24__icache_miss_bank3_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3270, 96, NULL,acmgt2__vector_engine24__icache_miss_bank3_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3271, 104, NULL,acmgt2__vector_engine24__icache_miss_bank3_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3272, 112, NULL,acmgt2__vector_engine24__icache_miss_bank3_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3273, 120, NULL,acmgt2__vector_engine24__icache_miss_bank3_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3274, 128, NULL,acmgt2__vector_engine24__icache_miss_bank3_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3275, 136, NULL,acmgt2__vector_engine24__icache_miss_bank3_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3276, 144, NULL,acmgt2__vector_engine24__icache_miss_bank3_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine25_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "VectorEngine25";
   query->symbol_name = "VectorEngine25";
   query->guid = "35c22c75-f1bd-4740-854b-b7248e45bb84";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0A902960 },
         { .reg = 0x00009888, .val = 0x0AB02960 },
         { .reg = 0x00009888, .val = 0x0AD02960 },
         { .reg = 0x00009888, .val = 0x0AF02960 },
         { .reg = 0x00009888, .val = 0x009039E0 },
         { .reg = 0x00009888, .val = 0x00810015 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x02B039E0 },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A10540 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04D039E0 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x00C15000 },
         { .reg = 0x00009888, .val = 0x02C10001 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x06F039E0 },
         { .reg = 0x00009888, .val = 0x00F00000 },
         { .reg = 0x00009888, .val = 0x02E10054 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32032942 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030840 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030603 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine25__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine25__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine25__avg_gpu_core_frequency__max,acmgt2__vector_engine25__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 1678, 24, percentage_max_float,acmgt2__vector_engine25__xve_multiple_pipe_active_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 1679, 28, percentage_max_float,acmgt2__vector_engine25__xve_multiple_pipe_active_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 1680, 32, percentage_max_float,acmgt2__vector_engine25__xve_multiple_pipe_active_xecore2_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 1681, 36, percentage_max_float,acmgt2__vector_engine25__xve_multiple_pipe_active_xecore3_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine26_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "VectorEngine26";
   query->symbol_name = "VectorEngine26";
   query->guid = "208fe223-385c-4961-b2e7-cb44f3612b79";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0B902960 },
         { .reg = 0x00009888, .val = 0x0BB02960 },
         { .reg = 0x00009888, .val = 0x0BD02960 },
         { .reg = 0x00009888, .val = 0x0BF02960 },
         { .reg = 0x00009888, .val = 0x019039E0 },
         { .reg = 0x00009888, .val = 0x01810015 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x03B039E0 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x01A10540 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05D039E0 },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x01C15000 },
         { .reg = 0x00009888, .val = 0x03C10001 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x07F039E0 },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x03E10054 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32032942 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030840 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030603 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine26__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine26__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine26__avg_gpu_core_frequency__max,acmgt2__vector_engine26__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 1682, 24, percentage_max_float,acmgt2__vector_engine26__xve_multiple_pipe_active_xecore4_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 1683, 28, percentage_max_float,acmgt2__vector_engine26__xve_multiple_pipe_active_xecore5_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 1684, 32, percentage_max_float,acmgt2__vector_engine26__xve_multiple_pipe_active_xecore6_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 1685, 36, percentage_max_float,acmgt2__vector_engine26__xve_multiple_pipe_active_xecore7_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine27_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "VectorEngine27";
   query->symbol_name = "VectorEngine27";
   query->guid = "b72101b8-7ef1-4bd1-ac6f-5e9ac5d098d6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0A902960 },
         { .reg = 0x00009888, .val = 0x0AB02960 },
         { .reg = 0x00009888, .val = 0x0AD02960 },
         { .reg = 0x00009888, .val = 0x0AF02960 },
         { .reg = 0x00009888, .val = 0x009039E0 },
         { .reg = 0x00009888, .val = 0x00810015 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x02B039E0 },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A10540 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04D039E0 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x00C15000 },
         { .reg = 0x00009888, .val = 0x02C10001 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x06F039E0 },
         { .reg = 0x00009888, .val = 0x00F00000 },
         { .reg = 0x00009888, .val = 0x02E10054 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32032942 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030840 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030603 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine27__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine27__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine27__avg_gpu_core_frequency__max,acmgt2__vector_engine27__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 3277, 24, percentage_max_float,acmgt2__vector_engine27__xve_multiple_pipe_active_xecore8_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 3278, 28, percentage_max_float,acmgt2__vector_engine27__xve_multiple_pipe_active_xecore9_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 3279, 32, percentage_max_float,acmgt2__vector_engine27__xve_multiple_pipe_active_xecore10_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 3280, 36, percentage_max_float,acmgt2__vector_engine27__xve_multiple_pipe_active_xecore11_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "VectorEngine28";
   query->symbol_name = "VectorEngine28";
   query->guid = "fdd412a9-274d-46ab-a27f-f3e107321d24";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0B902960 },
         { .reg = 0x00009888, .val = 0x0BB02960 },
         { .reg = 0x00009888, .val = 0x0BD02960 },
         { .reg = 0x00009888, .val = 0x0BF02960 },
         { .reg = 0x00009888, .val = 0x019039E0 },
         { .reg = 0x00009888, .val = 0x01810015 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x03B039E0 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x01A10540 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05D039E0 },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x01C15000 },
         { .reg = 0x00009888, .val = 0x03C10001 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x07F039E0 },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x03E10054 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32032942 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030840 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030603 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine28__avg_gpu_core_frequency__max,acmgt2__vector_engine28__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 3281, 24, percentage_max_float,acmgt2__vector_engine28__xve_multiple_pipe_active_xecore12_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 3282, 28, percentage_max_float,acmgt2__vector_engine28__xve_multiple_pipe_active_xecore13_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 3283, 32, percentage_max_float,acmgt2__vector_engine28__xve_multiple_pipe_active_xecore14_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 3284, 36, percentage_max_float,acmgt2__vector_engine28__xve_multiple_pipe_active_xecore15_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine29_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "VectorEngine29";
   query->symbol_name = "VectorEngine29";
   query->guid = "233317d4-03cf-4497-bb57-f9690bc057f4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0A906F40 },
         { .reg = 0x00009888, .val = 0x0C900006 },
         { .reg = 0x00009888, .val = 0x0AB06F40 },
         { .reg = 0x00009888, .val = 0x0CB00006 },
         { .reg = 0x00009888, .val = 0x0AD06F40 },
         { .reg = 0x00009888, .val = 0x0CD00006 },
         { .reg = 0x00009888, .val = 0x00904EB4 },
         { .reg = 0x00009888, .val = 0x02900166 },
         { .reg = 0x00009888, .val = 0x00810155 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x02B05000 },
         { .reg = 0x00009888, .val = 0x04B01A75 },
         { .reg = 0x00009888, .val = 0x06B0000B },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A15400 },
         { .reg = 0x00009888, .val = 0x02A10005 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x06D05680 },
         { .reg = 0x00009888, .val = 0x08D02CD3 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x02C11550 },
         { .reg = 0x00009888, .val = 0x02C32AA0 },
         { .reg = 0x00009888, .val = 0x00C47C00 },
         { .reg = 0x00009888, .val = 0x02C61550 },
         { .reg = 0x00009888, .val = 0x02C71550 },
         { .reg = 0x00009888, .val = 0x02072AA0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x00097C00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A2AA5 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020B0005 },
         { .reg = 0x00009888, .val = 0x00027C00 },
         { .reg = 0x00009888, .val = 0x020C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030840 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030422 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine29__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine29__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine29__avg_gpu_core_frequency__max,acmgt2__vector_engine29__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 1640, 24, NULL,acmgt2__vector_engine29__xve_inst_issued_all_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 1641, 32, NULL,acmgt2__vector_engine29__xve_inst_issued_all_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 1642, 40, NULL,acmgt2__vector_engine29__xve_inst_issued_all_xecore2_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine30_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "VectorEngine30";
   query->symbol_name = "VectorEngine30";
   query->guid = "c11f8f0b-35fc-45de-b8d9-06664fa2b65c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AF06F40 },
         { .reg = 0x00009888, .val = 0x0CF00006 },
         { .reg = 0x00009888, .val = 0x0B906F40 },
         { .reg = 0x00009888, .val = 0x0D900006 },
         { .reg = 0x00009888, .val = 0x0BB06F40 },
         { .reg = 0x00009888, .val = 0x0DB00006 },
         { .reg = 0x00009888, .val = 0x00F04EB4 },
         { .reg = 0x00009888, .val = 0x02F00166 },
         { .reg = 0x00009888, .val = 0x00E10155 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x03905000 },
         { .reg = 0x00009888, .val = 0x05901A75 },
         { .reg = 0x00009888, .val = 0x0790000B },
         { .reg = 0x00009888, .val = 0x01900000 },
         { .reg = 0x00009888, .val = 0x01815400 },
         { .reg = 0x00009888, .val = 0x03810005 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07B05680 },
         { .reg = 0x00009888, .val = 0x09B02CD3 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x03A11550 },
         { .reg = 0x00009888, .val = 0x03A32AA0 },
         { .reg = 0x00009888, .val = 0x01A47C00 },
         { .reg = 0x00009888, .val = 0x03A61550 },
         { .reg = 0x00009888, .val = 0x03A71550 },
         { .reg = 0x00009888, .val = 0x00037FE0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x03083FFA },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A1555 },
         { .reg = 0x00009888, .val = 0x01017C00 },
         { .reg = 0x00009888, .val = 0x030B1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x12037000 },
         { .reg = 0x00009888, .val = 0x32030004 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009888, .val = 0x36031080 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x380308E4 },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine30__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine30__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine30__avg_gpu_core_frequency__max,acmgt2__vector_engine30__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 1643, 24, NULL,acmgt2__vector_engine30__xve_inst_issued_all_xecore3_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 1644, 32, NULL,acmgt2__vector_engine30__xve_inst_issued_all_xecore4_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 1645, 40, NULL,acmgt2__vector_engine30__xve_inst_issued_all_xecore5_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "VectorEngine31";
   query->symbol_name = "VectorEngine31";
   query->guid = "413fc3f3-9886-46d6-ab81-8cd6537f20e3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BD06F40 },
         { .reg = 0x00009888, .val = 0x0DD00006 },
         { .reg = 0x00009888, .val = 0x0BF06F40 },
         { .reg = 0x00009888, .val = 0x0DF00006 },
         { .reg = 0x00009888, .val = 0x01D04EB4 },
         { .reg = 0x00009888, .val = 0x03D00166 },
         { .reg = 0x00009888, .val = 0x01C10155 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x03F05000 },
         { .reg = 0x00009888, .val = 0x05F01A75 },
         { .reg = 0x00009888, .val = 0x07F0000B },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x01E15400 },
         { .reg = 0x00009888, .val = 0x03E10005 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x010756AA },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0A906F40 },
         { .reg = 0x00009888, .val = 0x0C900006 },
         { .reg = 0x00009888, .val = 0x06905680 },
         { .reg = 0x00009888, .val = 0x08902CD3 },
         { .reg = 0x00009888, .val = 0x00900000 },
         { .reg = 0x00009888, .val = 0x02811550 },
         { .reg = 0x00009888, .val = 0x02832AA0 },
         { .reg = 0x00009888, .val = 0x00847C00 },
         { .reg = 0x00009888, .val = 0x02861550 },
         { .reg = 0x00009888, .val = 0x02871550 },
         { .reg = 0x00009888, .val = 0x02082AA0 },
         { .reg = 0x00009888, .val = 0x020A1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009888, .val = 0x02023FF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032520 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x3A0300A0 },
         { .reg = 0x00009888, .val = 0x3C03140A },
         { .reg = 0x00009888, .val = 0x3E0300A0 },
         { .reg = 0x00009888, .val = 0x4003000A },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x34032529 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017C00 },
         { .reg = 0x00009888, .val = 0x02021550 },
         { .reg = 0x00009888, .val = 0x02041550 },
         { .reg = 0x00009888, .val = 0x02051550 },
         { .reg = 0x00009888, .val = 0x02082AA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine31__avg_gpu_core_frequency__max,acmgt2__vector_engine31__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 1646, 24, NULL,acmgt2__vector_engine31__xve_inst_issued_all_xecore6_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 1647, 32, NULL,acmgt2__vector_engine31__xve_inst_issued_all_xecore7_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3285, 40, NULL,acmgt2__vector_engine31__xve_inst_issued_all_xecore8_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine32_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "VectorEngine32";
   query->symbol_name = "VectorEngine32";
   query->guid = "fc0b9614-6c1b-4e90-976c-41dab7ef47aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0AB06F40 },
         { .reg = 0x00009888, .val = 0x0CB00006 },
         { .reg = 0x00009888, .val = 0x0AD06F40 },
         { .reg = 0x00009888, .val = 0x0CD00006 },
         { .reg = 0x00009888, .val = 0x0AF06F40 },
         { .reg = 0x00009888, .val = 0x0CF00006 },
         { .reg = 0x00009888, .val = 0x00B04EB4 },
         { .reg = 0x00009888, .val = 0x02B00166 },
         { .reg = 0x00009888, .val = 0x00A10155 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x02D05000 },
         { .reg = 0x00009888, .val = 0x04D01A75 },
         { .reg = 0x00009888, .val = 0x06D0000B },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x00C15400 },
         { .reg = 0x00009888, .val = 0x02C10005 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x06F05680 },
         { .reg = 0x00009888, .val = 0x08F02CD3 },
         { .reg = 0x00009888, .val = 0x00F00000 },
         { .reg = 0x00009888, .val = 0x02E11550 },
         { .reg = 0x00009888, .val = 0x02E32AA0 },
         { .reg = 0x00009888, .val = 0x00E47C00 },
         { .reg = 0x00009888, .val = 0x02E61550 },
         { .reg = 0x00009888, .val = 0x02E71550 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207155A },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00097FE0 },
         { .reg = 0x00009888, .val = 0x000AA955 },
         { .reg = 0x00009888, .val = 0x020A2AAA },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B0155 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023FFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32032943 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030603 },
         { .reg = 0x00009888, .val = 0x3A030000 },
         { .reg = 0x00009888, .val = 0x3C030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x3403294A },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine32__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine32__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine32__avg_gpu_core_frequency__max,acmgt2__vector_engine32__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3286, 24, NULL,acmgt2__vector_engine32__xve_inst_issued_all_xecore9_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3287, 32, NULL,acmgt2__vector_engine32__xve_inst_issued_all_xecore10_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3288, 40, NULL,acmgt2__vector_engine32__xve_inst_issued_all_xecore11_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine33_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "VectorEngine33";
   query->symbol_name = "VectorEngine33";
   query->guid = "fc0d31b8-0d2d-4674-943a-3b2929dd7053";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0B906F40 },
         { .reg = 0x00009888, .val = 0x0D900006 },
         { .reg = 0x00009888, .val = 0x0BB06F40 },
         { .reg = 0x00009888, .val = 0x0DB00006 },
         { .reg = 0x00009888, .val = 0x0BD06F40 },
         { .reg = 0x00009888, .val = 0x0DD00006 },
         { .reg = 0x00009888, .val = 0x01904EB4 },
         { .reg = 0x00009888, .val = 0x03900166 },
         { .reg = 0x00009888, .val = 0x01810155 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x03B05000 },
         { .reg = 0x00009888, .val = 0x05B01A75 },
         { .reg = 0x00009888, .val = 0x07B0000B },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x01A15400 },
         { .reg = 0x00009888, .val = 0x03A10005 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x07D05680 },
         { .reg = 0x00009888, .val = 0x09D02CD3 },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x03C11550 },
         { .reg = 0x00009888, .val = 0x03C32AA0 },
         { .reg = 0x00009888, .val = 0x01C47C00 },
         { .reg = 0x00009888, .val = 0x03C61550 },
         { .reg = 0x00009888, .val = 0x03C71550 },
         { .reg = 0x00009888, .val = 0x00037FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x03072AA0 },
         { .reg = 0x00009888, .val = 0x0108FEAA },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x01097C00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A2AA5 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009888, .val = 0x01027C00 },
         { .reg = 0x00009888, .val = 0x030C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x02023FFF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x12031000 },
         { .reg = 0x00009888, .val = 0x32030002 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009888, .val = 0x36030840 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x38030422 },
         { .reg = 0x00009888, .val = 0x3A030030 },
         { .reg = 0x00009888, .val = 0x3C030603 },
         { .reg = 0x00009888, .val = 0x3E030030 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x34030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine33__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine33__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine33__avg_gpu_core_frequency__max,acmgt2__vector_engine33__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3289, 24, NULL,acmgt2__vector_engine33__xve_inst_issued_all_xecore12_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3290, 32, NULL,acmgt2__vector_engine33__xve_inst_issued_all_xecore13_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3291, 40, NULL,acmgt2__vector_engine33__xve_inst_issued_all_xecore14_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine34_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "VectorEngine34";
   query->symbol_name = "VectorEngine34";
   query->guid = "0b91a434-3d1a-44b4-aeb8-c0fe350f4ef0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0BF06F40 },
         { .reg = 0x00009888, .val = 0x0DF00006 },
         { .reg = 0x00009888, .val = 0x01F04EB4 },
         { .reg = 0x00009888, .val = 0x03F00166 },
         { .reg = 0x00009888, .val = 0x01E10155 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000203FF },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x36030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x52030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine34__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine34__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine34__avg_gpu_core_frequency__max,acmgt2__vector_engine34__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3292, 24, NULL,acmgt2__vector_engine34__xve_inst_issued_all_xecore15_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "VectorEngine35";
   query->symbol_name = "VectorEngine35";
   query->guid = "bf1e00b6-18c0-409e-8d2c-8105be297da4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
         { .reg = 0x0000E658, .val = 0x00009001 },
         { .reg = 0x0000E758, .val = 0x02001002 },
         { .reg = 0x0000E45C, .val = 0x0000A003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine35__avg_gpu_core_frequency__max,acmgt2__vector_engine35__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 764, 24, percentage_max_float,acmgt2__vector_engine35__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 28, percentage_max_float,acmgt2__vector_engine35__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 32, percentage_max_float,acmgt2__vector_engine35__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 771, 40, acmgt2__vector_engine35__xve_inst_executed_alu0_all__max,acmgt2__vector_engine35__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 772, 48, acmgt2__vector_engine35__xve_inst_executed_alu1_all__max,acmgt2__vector_engine35__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 773, 56, acmgt2__vector_engine35__xve_inst_executed_xmx_all__max,acmgt2__vector_engine35__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 774, 64, acmgt2__vector_engine35__xve_inst_executed_send_all__max,acmgt2__vector_engine35__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 775, 72, acmgt2__vector_engine35__xve_inst_executed_control_all__max,acmgt2__vector_engine35__xve_inst_executed_control_all__read);

      intel_perf_query_add_counter_float(query, 776, 80, percentage_max_float,acmgt2__vector_engine35__xve_pipe_alu0_and_alu1_active__read);

      intel_perf_query_add_counter_float(query, 777, 84, percentage_max_float,acmgt2__vector_engine35__xve_pipe_alu0_and_xmx_active__read);

      intel_perf_query_add_counter_float(query, 778, 88, percentage_max_float,acmgt2__vector_engine35__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 779, 92, percentage_max_float,acmgt2__vector_engine35__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 782, 96, percentage_max_float,acmgt2__vector_engine35__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 780, 100, percentage_max_float,acmgt2__vector_engine35__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 781, 104, percentage_max_float,acmgt2__vector_engine35__xve_inst_executed_control_all_utilization__read);

      intel_perf_query_add_counter_uint64(query, 1986, 112, acmgt2__vector_engine35__xve_active_cycles__max,acmgt2__vector_engine35__xve_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 1987, 120, acmgt2__vector_engine35__xve_stall_cycles__max,acmgt2__vector_engine35__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 1988, 128, acmgt2__vector_engine35__xve_threads_occupancy_cycles_all__max,acmgt2__vector_engine35__xve_threads_occupancy_cycles_all__read);

      intel_perf_query_add_counter_uint64(query, 1989, 136, acmgt2__vector_engine35__xve_pipe_alu0_and_alu1_active_cycles__max,acmgt2__vector_engine35__xve_pipe_alu0_and_alu1_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 1990, 144, acmgt2__vector_engine35__xve_pipe_alu0_and_xmx_active_cycles__max,acmgt2__vector_engine35__xve_pipe_alu0_and_xmx_active_cycles__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine36_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "VectorEngine36";
   query->symbol_name = "VectorEngine36";
   query->guid = "bbb25709-1345-473f-8233-6df9075eacda";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00020010 },
         { .reg = 0x0000E558, .val = 0x00050030 },
         { .reg = 0x0000E658, .val = 0x00090060 },
         { .reg = 0x0000E758, .val = 0x00021011 },
         { .reg = 0x0000E45C, .val = 0x00051031 },
         { .reg = 0x0000E55C, .val = 0x00091061 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine36__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine36__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine36__avg_gpu_core_frequency__max,acmgt2__vector_engine36__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1991, 24, acmgt2__vector_engine36__xve_inst_executed_alu0_vs__max,acmgt2__vector_engine36__xve_inst_executed_alu0_vs__read);

      intel_perf_query_add_counter_uint64(query, 1992, 32, acmgt2__vector_engine36__xve_inst_executed_alu0_hs__max,acmgt2__vector_engine36__xve_inst_executed_alu0_hs__read);

      intel_perf_query_add_counter_uint64(query, 1993, 40, acmgt2__vector_engine36__xve_inst_executed_alu0_ds__max,acmgt2__vector_engine36__xve_inst_executed_alu0_ds__read);

      intel_perf_query_add_counter_uint64(query, 1994, 48, acmgt2__vector_engine36__xve_inst_executed_alu0_ps__max,acmgt2__vector_engine36__xve_inst_executed_alu0_ps__read);

      intel_perf_query_add_counter_uint64(query, 1995, 56, acmgt2__vector_engine36__xve_inst_executed_alu0_cs__max,acmgt2__vector_engine36__xve_inst_executed_alu0_cs__read);

      intel_perf_query_add_counter_uint64(query, 1996, 64, acmgt2__vector_engine36__xve_inst_executed_alu0_async_cs__max,acmgt2__vector_engine36__xve_inst_executed_alu0_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 1997, 72, acmgt2__vector_engine36__xve_inst_executed_alu1_vs__max,acmgt2__vector_engine36__xve_inst_executed_alu1_vs__read);

      intel_perf_query_add_counter_uint64(query, 1998, 80, acmgt2__vector_engine36__xve_inst_executed_alu1_hs__max,acmgt2__vector_engine36__xve_inst_executed_alu1_hs__read);

      intel_perf_query_add_counter_uint64(query, 1999, 88, acmgt2__vector_engine36__xve_inst_executed_alu1_ds__max,acmgt2__vector_engine36__xve_inst_executed_alu1_ds__read);

      intel_perf_query_add_counter_uint64(query, 2000, 96, acmgt2__vector_engine36__xve_inst_executed_alu1_ps__max,acmgt2__vector_engine36__xve_inst_executed_alu1_ps__read);

      intel_perf_query_add_counter_uint64(query, 2001, 104, acmgt2__vector_engine36__xve_inst_executed_alu1_cs__max,acmgt2__vector_engine36__xve_inst_executed_alu1_cs__read);

      intel_perf_query_add_counter_uint64(query, 2002, 112, acmgt2__vector_engine36__xve_inst_executed_alu1_async_cs__max,acmgt2__vector_engine36__xve_inst_executed_alu1_async_cs__read);

      intel_perf_query_add_counter_float(query, 2003, 120, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu0_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 2004, 124, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu0_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 2005, 128, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu0_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 2006, 132, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu0_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 2007, 136, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu0_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2008, 140, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu0_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2009, 144, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu1_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 2010, 148, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu1_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 2011, 152, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu1_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 2012, 156, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu1_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 2013, 160, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu1_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2014, 164, percentage_max_float,acmgt2__vector_engine36__xve_inst_executed_alu1_async_cs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine37_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "VectorEngine37";
   query->symbol_name = "VectorEngine37";
   query->guid = "fc1c6f5b-60ad-48c8-b0b7-ed9328548c7a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x000C10C0 },
         { .reg = 0x0000E558, .val = 0x000D00C2 },
         { .reg = 0x0000E658, .val = 0x000D20D1 },
         { .reg = 0x0000E758, .val = 0x000E10E0 },
         { .reg = 0x0000E45C, .val = 0x000000E2 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine37__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine37__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine37__avg_gpu_core_frequency__max,acmgt2__vector_engine37__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 2015, 24, percentage_max_float,acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 2016, 28, percentage_max_float,acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 2017, 32, percentage_max_float,acmgt2__vector_engine37__xve_inst_executed_send_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 2018, 36, percentage_max_float,acmgt2__vector_engine37__xve_inst_executed_alu0_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 2019, 40, percentage_max_float,acmgt2__vector_engine37__xve_inst_executed_alu1_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 2020, 44, percentage_max_float,acmgt2__vector_engine37__xve_inst_executed_send_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 2021, 48, percentage_max_float,acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2022, 52, percentage_max_float,acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2023, 56, percentage_max_float,acmgt2__vector_engine37__xve_inst_executed_send_rt_ms_utilization__read);

      intel_perf_query_add_counter_uint64(query, 2024, 64, acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ahs__max,acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 2025, 72, acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ahs__max,acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 2026, 80, acmgt2__vector_engine37__xve_inst_executed_send_rt_ahs__max,acmgt2__vector_engine37__xve_inst_executed_send_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 2027, 88, acmgt2__vector_engine37__xve_inst_executed_alu0_rt_chs__max,acmgt2__vector_engine37__xve_inst_executed_alu0_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 2028, 96, acmgt2__vector_engine37__xve_inst_executed_alu1_rt_chs__max,acmgt2__vector_engine37__xve_inst_executed_alu1_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 2029, 104, acmgt2__vector_engine37__xve_inst_executed_send_rt_chs__max,acmgt2__vector_engine37__xve_inst_executed_send_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 2030, 112, acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ms__max,acmgt2__vector_engine37__xve_inst_executed_alu0_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 2031, 120, acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ms__max,acmgt2__vector_engine37__xve_inst_executed_alu1_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 2032, 128, acmgt2__vector_engine37__xve_inst_executed_send_rt_ms__max,acmgt2__vector_engine37__xve_inst_executed_send_rt_ms__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine38_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "VectorEngine38";
   query->symbol_name = "VectorEngine38";
   query->guid = "39a71cf8-2d00-49f4-b8fb-38da2b23da30";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00095005 },
         { .reg = 0x0000E558, .val = 0x00035065 },
         { .reg = 0x0000E658, .val = 0x000B5025 },
         { .reg = 0x0000E758, .val = 0x000A5055 },
         { .reg = 0x0000E45C, .val = 0x000C5015 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine38__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine38__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine38__avg_gpu_core_frequency__max,acmgt2__vector_engine38__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 765, 24, percentage_max_float,acmgt2__vector_engine38__xve_stall__read);

      intel_perf_query_add_counter_float(query, 2033, 28, percentage_max_float,acmgt2__vector_engine38__xve_stall_async_cs__read);

      intel_perf_query_add_counter_float(query, 2034, 32, percentage_max_float,acmgt2__vector_engine38__xve_stall_cs__read);

      intel_perf_query_add_counter_float(query, 2035, 36, percentage_max_float,acmgt2__vector_engine38__xve_stall_ds__read);

      intel_perf_query_add_counter_float(query, 2036, 40, percentage_max_float,acmgt2__vector_engine38__xve_stall_hs__read);

      intel_perf_query_add_counter_float(query, 2037, 44, percentage_max_float,acmgt2__vector_engine38__xve_stall_ms__read);

      intel_perf_query_add_counter_float(query, 2038, 48, percentage_max_float,acmgt2__vector_engine38__xve_stall_ps__read);

      intel_perf_query_add_counter_float(query, 2039, 52, percentage_max_float,acmgt2__vector_engine38__xve_stall_ts__read);

      intel_perf_query_add_counter_float(query, 2040, 56, percentage_max_float,acmgt2__vector_engine38__xve_stall_vs__read);

      intel_perf_query_add_counter_float(query, 2041, 60, percentage_max_float,acmgt2__vector_engine38__xve_stall_rt__read);

      intel_perf_query_add_counter_uint64(query, 1987, 64, acmgt2__vector_engine38__xve_stall_cycles__max,acmgt2__vector_engine38__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 2042, 72, acmgt2__vector_engine38__xve_stall_cycles_async_cs__max,acmgt2__vector_engine38__xve_stall_cycles_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 2043, 80, acmgt2__vector_engine38__xve_stall_cycles_cs__max,acmgt2__vector_engine38__xve_stall_cycles_cs__read);

      intel_perf_query_add_counter_uint64(query, 2044, 88, acmgt2__vector_engine38__xve_stall_cycles_ds__max,acmgt2__vector_engine38__xve_stall_cycles_ds__read);

      intel_perf_query_add_counter_uint64(query, 2045, 96, acmgt2__vector_engine38__xve_stall_cycles_hs__max,acmgt2__vector_engine38__xve_stall_cycles_hs__read);

      intel_perf_query_add_counter_uint64(query, 2046, 104, acmgt2__vector_engine38__xve_stall_cycles_ms__max,acmgt2__vector_engine38__xve_stall_cycles_ms__read);

      intel_perf_query_add_counter_uint64(query, 2047, 112, acmgt2__vector_engine38__xve_stall_cycles_ps__max,acmgt2__vector_engine38__xve_stall_cycles_ps__read);

      intel_perf_query_add_counter_uint64(query, 2048, 120, acmgt2__vector_engine38__xve_stall_cycles_ts__max,acmgt2__vector_engine38__xve_stall_cycles_ts__read);

      intel_perf_query_add_counter_uint64(query, 2049, 128, acmgt2__vector_engine38__xve_stall_cycles_vs__max,acmgt2__vector_engine38__xve_stall_cycles_vs__read);

      intel_perf_query_add_counter_uint64(query, 2050, 136, acmgt2__vector_engine38__xve_stall_cycles_rt__max,acmgt2__vector_engine38__xve_stall_cycles_rt__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "VectorEngine39";
   query->symbol_name = "VectorEngine39";
   query->guid = "d538856d-b249-46ab-b850-9058093d45d6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00006000 },
         { .reg = 0x0000E558, .val = 0x0000B007 },
         { .reg = 0x0000E658, .val = 0x0000C001 },
         { .reg = 0x0000E758, .val = 0x0200000D },
         { .reg = 0x0000E45C, .val = 0x0000E009 },
         { .reg = 0x0000E55C, .val = 0x0100F002 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine39__avg_gpu_core_frequency__max,acmgt2__vector_engine39__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 771, 24, acmgt2__vector_engine39__xve_inst_executed_alu0_all__max,acmgt2__vector_engine39__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 2051, 32, acmgt2__vector_engine39__xve_inst_executed_fp16__max,acmgt2__vector_engine39__xve_inst_executed_fp16__read);

      intel_perf_query_add_counter_uint64(query, 2052, 40, acmgt2__vector_engine39__xve_inst_executed_fp32__max,acmgt2__vector_engine39__xve_inst_executed_fp32__read);

      intel_perf_query_add_counter_uint64(query, 2053, 48, acmgt2__vector_engine39__xve_inst_executed_fp64__max,acmgt2__vector_engine39__xve_inst_executed_fp64__read);

      intel_perf_query_add_counter_uint64(query, 772, 56, acmgt2__vector_engine39__xve_inst_executed_alu1_all__max,acmgt2__vector_engine39__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 2054, 64, acmgt2__vector_engine39__xve_inst_executed_int16__max,acmgt2__vector_engine39__xve_inst_executed_int16__read);

      intel_perf_query_add_counter_uint64(query, 2055, 72, acmgt2__vector_engine39__xve_inst_executed_int32__max,acmgt2__vector_engine39__xve_inst_executed_int32__read);

      intel_perf_query_add_counter_uint64(query, 2056, 80, acmgt2__vector_engine39__xve_inst_executed_math__max,acmgt2__vector_engine39__xve_inst_executed_math__read);

      intel_perf_query_add_counter_uint64(query, 773, 88, acmgt2__vector_engine39__xve_inst_executed_xmx_all__max,acmgt2__vector_engine39__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 2057, 96, acmgt2__vector_engine39__xve_inst_executed_xmx_bf16__max,acmgt2__vector_engine39__xve_inst_executed_xmx_bf16__read);

      intel_perf_query_add_counter_uint64(query, 2058, 104, acmgt2__vector_engine39__xve_inst_executed_xmx_fp16__max,acmgt2__vector_engine39__xve_inst_executed_xmx_fp16__read);

      intel_perf_query_add_counter_uint64(query, 2059, 112, acmgt2__vector_engine39__xve_inst_executed_xmx_int8__max,acmgt2__vector_engine39__xve_inst_executed_xmx_int8__read);

      intel_perf_query_add_counter_float(query, 778, 120, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2060, 124, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 2061, 128, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_fp32_utilization__read);

      intel_perf_query_add_counter_float(query, 2062, 132, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_fp64_utilization__read);

      intel_perf_query_add_counter_float(query, 779, 136, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2063, 140, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_int16_utilization__read);

      intel_perf_query_add_counter_float(query, 2064, 144, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_int32_utilization__read);

      intel_perf_query_add_counter_float(query, 2065, 148, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_math_utilization__read);

      intel_perf_query_add_counter_float(query, 782, 152, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2066, 156, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_xmx_bf16_utilization__read);

      intel_perf_query_add_counter_float(query, 2067, 160, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_xmx_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 2068, 164, percentage_max_float,acmgt2__vector_engine39__xve_inst_executed_xmx_int8_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine40_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "VectorEngine40";
   query->symbol_name = "VectorEngine40";
   query->guid = "7392b735-c76c-4e4d-b936-8ec5fc8877e6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00092002 },
         { .reg = 0x0000E558, .val = 0x00032062 },
         { .reg = 0x0000E658, .val = 0x00022042 },
         { .reg = 0x0000E758, .val = 0x000520B2 },
         { .reg = 0x0000E45C, .val = 0x000120A2 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine40__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine40__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine40__avg_gpu_core_frequency__max,acmgt2__vector_engine40__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 774, 24, acmgt2__vector_engine40__xve_inst_executed_send_all__max,acmgt2__vector_engine40__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 2069, 32, acmgt2__vector_engine40__xve_inst_executed_send_async_cs__max,acmgt2__vector_engine40__xve_inst_executed_send_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 2070, 40, acmgt2__vector_engine40__xve_inst_executed_send_cs__max,acmgt2__vector_engine40__xve_inst_executed_send_cs__read);

      intel_perf_query_add_counter_uint64(query, 2071, 48, acmgt2__vector_engine40__xve_inst_executed_send_ds__max,acmgt2__vector_engine40__xve_inst_executed_send_ds__read);

      intel_perf_query_add_counter_uint64(query, 2072, 56, acmgt2__vector_engine40__xve_inst_executed_send_gs__max,acmgt2__vector_engine40__xve_inst_executed_send_gs__read);

      intel_perf_query_add_counter_uint64(query, 2073, 64, acmgt2__vector_engine40__xve_inst_executed_send_hs__max,acmgt2__vector_engine40__xve_inst_executed_send_hs__read);

      intel_perf_query_add_counter_uint64(query, 2074, 72, acmgt2__vector_engine40__xve_inst_executed_send_ms__max,acmgt2__vector_engine40__xve_inst_executed_send_ms__read);

      intel_perf_query_add_counter_uint64(query, 2075, 80, acmgt2__vector_engine40__xve_inst_executed_send_ps__max,acmgt2__vector_engine40__xve_inst_executed_send_ps__read);

      intel_perf_query_add_counter_uint64(query, 2076, 88, acmgt2__vector_engine40__xve_inst_executed_send_ts__max,acmgt2__vector_engine40__xve_inst_executed_send_ts__read);

      intel_perf_query_add_counter_uint64(query, 2077, 96, acmgt2__vector_engine40__xve_inst_executed_send_vs__max,acmgt2__vector_engine40__xve_inst_executed_send_vs__read);

      intel_perf_query_add_counter_float(query, 780, 104, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2078, 108, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2079, 112, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2080, 116, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 2081, 120, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 2082, 124, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 2083, 128, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2084, 132, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 2085, 136, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 2086, 140, percentage_max_float,acmgt2__vector_engine40__xve_inst_executed_send_vs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt2_register_vector_engine41_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "VectorEngine41";
   query->symbol_name = "VectorEngine41";
   query->guid = "02d21db0-db5d-4eae-9ffa-8fa1603ec8f2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00040045 },
         { .reg = 0x0000E558, .val = 0x000B0041 },
         { .reg = 0x0000E658, .val = 0x000B10A0 },
         { .reg = 0x0000E758, .val = 0x000000A1 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt2__vector_engine41__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt2__vector_engine41__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt2__vector_engine41__avg_gpu_core_frequency__max,acmgt2__vector_engine41__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 2087, 24, percentage_max_float,acmgt2__vector_engine41__xve_stall_gs__read);

      intel_perf_query_add_counter_uint64(query, 2088, 32, acmgt2__vector_engine41__xve_inst_executed_alu0_gs__max,acmgt2__vector_engine41__xve_inst_executed_alu0_gs__read);

      intel_perf_query_add_counter_uint64(query, 2089, 40, acmgt2__vector_engine41__xve_inst_executed_alu1_gs__max,acmgt2__vector_engine41__xve_inst_executed_alu1_gs__read);

      intel_perf_query_add_counter_uint64(query, 2090, 48, acmgt2__vector_engine41__xve_stall_cycles_gs__max,acmgt2__vector_engine41__xve_stall_cycles_gs__read);

      intel_perf_query_add_counter_uint64(query, 2091, 56, acmgt2__vector_engine41__xve_inst_executed_alu0_ms__max,acmgt2__vector_engine41__xve_inst_executed_alu0_ms__read);

      intel_perf_query_add_counter_uint64(query, 2092, 64, acmgt2__vector_engine41__xve_inst_executed_alu0_ts__max,acmgt2__vector_engine41__xve_inst_executed_alu0_ts__read);

      intel_perf_query_add_counter_uint64(query, 2093, 72, acmgt2__vector_engine41__xve_inst_executed_alu1_ms__max,acmgt2__vector_engine41__xve_inst_executed_alu1_ms__read);

      intel_perf_query_add_counter_uint64(query, 2094, 80, acmgt2__vector_engine41__xve_inst_executed_alu1_ts__max,acmgt2__vector_engine41__xve_inst_executed_alu1_ts__read);

      intel_perf_query_add_counter_float(query, 2095, 88, percentage_max_float,acmgt2__vector_engine41__xve_inst_executed_alu0_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 2096, 92, percentage_max_float,acmgt2__vector_engine41__xve_inst_executed_alu1_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 2097, 96, percentage_max_float,acmgt2__vector_engine41__xve_inst_executed_alu0_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2098, 100, percentage_max_float,acmgt2__vector_engine41__xve_inst_executed_alu0_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 2099, 104, percentage_max_float,acmgt2__vector_engine41__xve_inst_executed_alu1_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2100, 108, percentage_max_float,acmgt2__vector_engine41__xve_inst_executed_alu1_ts_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_acmgt2(struct intel_perf_config *perf)
{
   acmgt2_register_render_basic_counter_query(perf);
   acmgt2_register_compute_basic_counter_query(perf);
   acmgt2_register_async_compute_counter_query(perf);
   acmgt2_register_xve_activity1_counter_query(perf);
   acmgt2_register_gpu_busyness_counter_query(perf);
   acmgt2_register_render_pipe_profile1_counter_query(perf);
   acmgt2_register_render_pipe_profile2_counter_query(perf);
   acmgt2_register_render_pipe_profile3_counter_query(perf);
   acmgt2_register_render_pipe_profile4_counter_query(perf);
   acmgt2_register_l3_1_counter_query(perf);
   acmgt2_register_l3_2_counter_query(perf);
   acmgt2_register_sampler_1_counter_query(perf);
   acmgt2_register_sampler_2_counter_query(perf);
   acmgt2_register_hdc_and_sf1_counter_query(perf);
   acmgt2_register_hdc_and_sf2_counter_query(perf);
   acmgt2_register_hdc_and_sf3_counter_query(perf);
   acmgt2_register_rasterizer_and_pixel_backend1_counter_query(perf);
   acmgt2_register_rasterizer_and_pixel_backend2_counter_query(perf);
   acmgt2_register_rasterizer_and_pixel_backend3_counter_query(perf);
   acmgt2_register_tdl1_counter_query(perf);
   acmgt2_register_tdl2_counter_query(perf);
   acmgt2_register_tdl3_counter_query(perf);
   acmgt2_register_tdl4_counter_query(perf);
   acmgt2_register_tdl5_counter_query(perf);
   acmgt2_register_tdl6_counter_query(perf);
   acmgt2_register_tdl7_counter_query(perf);
   acmgt2_register_tdl8_counter_query(perf);
   acmgt2_register_test_oa_counter_query(perf);
   acmgt2_register_amfs1_counter_query(perf);
   acmgt2_register_amfs2_counter_query(perf);
   acmgt2_register_amfs3_counter_query(perf);
   acmgt2_register_amfs4_counter_query(perf);
   acmgt2_register_amfs5_counter_query(perf);
   acmgt2_register_color_pipe1_counter_query(perf);
   acmgt2_register_color_pipe2_counter_query(perf);
   acmgt2_register_color_pipe3_counter_query(perf);
   acmgt2_register_color_pipe4_counter_query(perf);
   acmgt2_register_color_pipe5_counter_query(perf);
   acmgt2_register_color_pipe6_counter_query(perf);
   acmgt2_register_color_pipe7_counter_query(perf);
   acmgt2_register_color_pipe8_counter_query(perf);
   acmgt2_register_color_pipe9_counter_query(perf);
   acmgt2_register_color_pipe10_counter_query(perf);
   acmgt2_register_color_pipe11_counter_query(perf);
   acmgt2_register_color_pipe12_counter_query(perf);
   acmgt2_register_color_pipe13_counter_query(perf);
   acmgt2_register_color_pipe14_counter_query(perf);
   acmgt2_register_color_pipe15_counter_query(perf);
   acmgt2_register_color_pipe16_counter_query(perf);
   acmgt2_register_color_pipe17_counter_query(perf);
   acmgt2_register_dataport1_counter_query(perf);
   acmgt2_register_dataport2_counter_query(perf);
   acmgt2_register_dataport3_counter_query(perf);
   acmgt2_register_dataport4_counter_query(perf);
   acmgt2_register_dataport5_counter_query(perf);
   acmgt2_register_dataport6_counter_query(perf);
   acmgt2_register_dataport7_counter_query(perf);
   acmgt2_register_dataport8_counter_query(perf);
   acmgt2_register_dataport9_counter_query(perf);
   acmgt2_register_dataport10_counter_query(perf);
   acmgt2_register_dataport11_counter_query(perf);
   acmgt2_register_dataport12_counter_query(perf);
   acmgt2_register_dataport13_counter_query(perf);
   acmgt2_register_dataport14_counter_query(perf);
   acmgt2_register_dataport15_counter_query(perf);
   acmgt2_register_dataport16_counter_query(perf);
   acmgt2_register_dataport17_counter_query(perf);
   acmgt2_register_dataport18_counter_query(perf);
   acmgt2_register_dataport19_counter_query(perf);
   acmgt2_register_dataport20_counter_query(perf);
   acmgt2_register_dataport21_counter_query(perf);
   acmgt2_register_dataport22_counter_query(perf);
   acmgt2_register_dataport23_counter_query(perf);
   acmgt2_register_dataport24_counter_query(perf);
   acmgt2_register_dataport25_counter_query(perf);
   acmgt2_register_dataport26_counter_query(perf);
   acmgt2_register_dataport27_counter_query(perf);
   acmgt2_register_dataport28_counter_query(perf);
   acmgt2_register_dataport29_counter_query(perf);
   acmgt2_register_dataport30_counter_query(perf);
   acmgt2_register_dataport31_counter_query(perf);
   acmgt2_register_dataport32_counter_query(perf);
   acmgt2_register_dataport33_counter_query(perf);
   acmgt2_register_dataport34_counter_query(perf);
   acmgt2_register_dataport35_counter_query(perf);
   acmgt2_register_dataport36_counter_query(perf);
   acmgt2_register_dataport37_counter_query(perf);
   acmgt2_register_dataport38_counter_query(perf);
   acmgt2_register_dataport39_counter_query(perf);
   acmgt2_register_dataport40_counter_query(perf);
   acmgt2_register_dataport41_counter_query(perf);
   acmgt2_register_depth_pipe1_counter_query(perf);
   acmgt2_register_depth_pipe2_counter_query(perf);
   acmgt2_register_depth_pipe3_counter_query(perf);
   acmgt2_register_depth_pipe4_counter_query(perf);
   acmgt2_register_depth_pipe5_counter_query(perf);
   acmgt2_register_depth_pipe6_counter_query(perf);
   acmgt2_register_depth_pipe7_counter_query(perf);
   acmgt2_register_depth_pipe8_counter_query(perf);
   acmgt2_register_depth_pipe9_counter_query(perf);
   acmgt2_register_depth_pipe10_counter_query(perf);
   acmgt2_register_depth_pipe11_counter_query(perf);
   acmgt2_register_depth_pipe12_counter_query(perf);
   acmgt2_register_depth_pipe13_counter_query(perf);
   acmgt2_register_depth_pipe14_counter_query(perf);
   acmgt2_register_depth_pipe15_counter_query(perf);
   acmgt2_register_depth_pipe16_counter_query(perf);
   acmgt2_register_depth_pipe17_counter_query(perf);
   acmgt2_register_depth_pipe18_counter_query(perf);
   acmgt2_register_depth_pipe19_counter_query(perf);
   acmgt2_register_depth_pipe20_counter_query(perf);
   acmgt2_register_depth_pipe21_counter_query(perf);
   acmgt2_register_depth_pipe22_counter_query(perf);
   acmgt2_register_depth_pipe23_counter_query(perf);
   acmgt2_register_depth_pipe24_counter_query(perf);
   acmgt2_register_depth_pipe25_counter_query(perf);
   acmgt2_register_depth_pipe26_counter_query(perf);
   acmgt2_register_depth_pipe27_counter_query(perf);
   acmgt2_register_depth_pipe28_counter_query(perf);
   acmgt2_register_depth_pipe29_counter_query(perf);
   acmgt2_register_depth_pipe30_counter_query(perf);
   acmgt2_register_depth_pipe31_counter_query(perf);
   acmgt2_register_depth_pipe32_counter_query(perf);
   acmgt2_register_depth_pipe33_counter_query(perf);
   acmgt2_register_depth_pipe34_counter_query(perf);
   acmgt2_register_depth_pipe35_counter_query(perf);
   acmgt2_register_depth_pipe36_counter_query(perf);
   acmgt2_register_depth_pipe37_counter_query(perf);
   acmgt2_register_depth_pipe38_counter_query(perf);
   acmgt2_register_depth_pipe39_counter_query(perf);
   acmgt2_register_depth_pipe40_counter_query(perf);
   acmgt2_register_depth_pipe41_counter_query(perf);
   acmgt2_register_depth_pipe42_counter_query(perf);
   acmgt2_register_depth_pipe43_counter_query(perf);
   acmgt2_register_depth_pipe44_counter_query(perf);
   acmgt2_register_depth_pipe45_counter_query(perf);
   acmgt2_register_depth_pipe46_counter_query(perf);
   acmgt2_register_depth_pipe47_counter_query(perf);
   acmgt2_register_depth_pipe48_counter_query(perf);
   acmgt2_register_depth_pipe49_counter_query(perf);
   acmgt2_register_depth_pipe50_counter_query(perf);
   acmgt2_register_front_end1_counter_query(perf);
   acmgt2_register_geometry1_counter_query(perf);
   acmgt2_register_geometry2_counter_query(perf);
   acmgt2_register_geometry3_counter_query(perf);
   acmgt2_register_geometry4_counter_query(perf);
   acmgt2_register_geometry5_counter_query(perf);
   acmgt2_register_l1_cache1_counter_query(perf);
   acmgt2_register_l1_cache2_counter_query(perf);
   acmgt2_register_l1_cache3_counter_query(perf);
   acmgt2_register_l1_cache4_counter_query(perf);
   acmgt2_register_l1_cache5_counter_query(perf);
   acmgt2_register_l1_cache6_counter_query(perf);
   acmgt2_register_l1_cache7_counter_query(perf);
   acmgt2_register_l1_cache8_counter_query(perf);
   acmgt2_register_l1_cache9_counter_query(perf);
   acmgt2_register_l1_cache10_counter_query(perf);
   acmgt2_register_l1_cache11_counter_query(perf);
   acmgt2_register_l1_cache12_counter_query(perf);
   acmgt2_register_l1_cache13_counter_query(perf);
   acmgt2_register_l1_cache14_counter_query(perf);
   acmgt2_register_l1_cache15_counter_query(perf);
   acmgt2_register_l1_cache16_counter_query(perf);
   acmgt2_register_l1_cache17_counter_query(perf);
   acmgt2_register_l1_cache18_counter_query(perf);
   acmgt2_register_l1_cache19_counter_query(perf);
   acmgt2_register_l1_cache20_counter_query(perf);
   acmgt2_register_l1_cache21_counter_query(perf);
   acmgt2_register_l1_cache22_counter_query(perf);
   acmgt2_register_l1_cache23_counter_query(perf);
   acmgt2_register_l1_cache24_counter_query(perf);
   acmgt2_register_l1_cache25_counter_query(perf);
   acmgt2_register_l1_cache26_counter_query(perf);
   acmgt2_register_l1_cache27_counter_query(perf);
   acmgt2_register_l1_cache28_counter_query(perf);
   acmgt2_register_l1_cache29_counter_query(perf);
   acmgt2_register_l1_cache30_counter_query(perf);
   acmgt2_register_l1_cache31_counter_query(perf);
   acmgt2_register_l1_cache32_counter_query(perf);
   acmgt2_register_l1_cache33_counter_query(perf);
   acmgt2_register_l1_cache34_counter_query(perf);
   acmgt2_register_l1_cache35_counter_query(perf);
   acmgt2_register_l1_cache36_counter_query(perf);
   acmgt2_register_l1_cache37_counter_query(perf);
   acmgt2_register_l1_cache38_counter_query(perf);
   acmgt2_register_l1_cache39_counter_query(perf);
   acmgt2_register_l1_cache40_counter_query(perf);
   acmgt2_register_l1_cache41_counter_query(perf);
   acmgt2_register_l1_cache42_counter_query(perf);
   acmgt2_register_l1_cache43_counter_query(perf);
   acmgt2_register_l1_cache44_counter_query(perf);
   acmgt2_register_l1_cache45_counter_query(perf);
   acmgt2_register_l1_cache46_counter_query(perf);
   acmgt2_register_l1_cache47_counter_query(perf);
   acmgt2_register_l1_cache48_counter_query(perf);
   acmgt2_register_l1_cache49_counter_query(perf);
   acmgt2_register_l1_cache50_counter_query(perf);
   acmgt2_register_l1_cache51_counter_query(perf);
   acmgt2_register_l1_cache52_counter_query(perf);
   acmgt2_register_l1_cache53_counter_query(perf);
   acmgt2_register_l1_cache54_counter_query(perf);
   acmgt2_register_l1_cache55_counter_query(perf);
   acmgt2_register_l1_cache56_counter_query(perf);
   acmgt2_register_l1_cache57_counter_query(perf);
   acmgt2_register_l1_cache58_counter_query(perf);
   acmgt2_register_l1_cache59_counter_query(perf);
   acmgt2_register_l1_cache60_counter_query(perf);
   acmgt2_register_l1_cache61_counter_query(perf);
   acmgt2_register_l1_cache62_counter_query(perf);
   acmgt2_register_l1_cache63_counter_query(perf);
   acmgt2_register_l1_cache64_counter_query(perf);
   acmgt2_register_l1_cache65_counter_query(perf);
   acmgt2_register_l1_cache66_counter_query(perf);
   acmgt2_register_l1_cache67_counter_query(perf);
   acmgt2_register_l1_cache68_counter_query(perf);
   acmgt2_register_l1_cache69_counter_query(perf);
   acmgt2_register_l1_cache70_counter_query(perf);
   acmgt2_register_l1_cache71_counter_query(perf);
   acmgt2_register_l1_cache72_counter_query(perf);
   acmgt2_register_l1_cache73_counter_query(perf);
   acmgt2_register_l1_cache74_counter_query(perf);
   acmgt2_register_l1_cache75_counter_query(perf);
   acmgt2_register_l1_cache76_counter_query(perf);
   acmgt2_register_l1_cache77_counter_query(perf);
   acmgt2_register_l1_cache78_counter_query(perf);
   acmgt2_register_l1_cache79_counter_query(perf);
   acmgt2_register_l1_cache80_counter_query(perf);
   acmgt2_register_l1_cache81_counter_query(perf);
   acmgt2_register_l1_cache82_counter_query(perf);
   acmgt2_register_l1_cache83_counter_query(perf);
   acmgt2_register_l1_cache84_counter_query(perf);
   acmgt2_register_l1_cache85_counter_query(perf);
   acmgt2_register_l1_cache86_counter_query(perf);
   acmgt2_register_l1_cache87_counter_query(perf);
   acmgt2_register_l1_cache88_counter_query(perf);
   acmgt2_register_l1_cache89_counter_query(perf);
   acmgt2_register_l1_cache90_counter_query(perf);
   acmgt2_register_l1_cache91_counter_query(perf);
   acmgt2_register_l1_cache92_counter_query(perf);
   acmgt2_register_l1_cache93_counter_query(perf);
   acmgt2_register_l1_cache94_counter_query(perf);
   acmgt2_register_l1_cache95_counter_query(perf);
   acmgt2_register_l1_cache96_counter_query(perf);
   acmgt2_register_l1_cache97_counter_query(perf);
   acmgt2_register_l1_cache98_counter_query(perf);
   acmgt2_register_l1_cache99_counter_query(perf);
   acmgt2_register_l1_cache100_counter_query(perf);
   acmgt2_register_l1_cache101_counter_query(perf);
   acmgt2_register_l1_cache102_counter_query(perf);
   acmgt2_register_l1_cache103_counter_query(perf);
   acmgt2_register_l1_cache104_counter_query(perf);
   acmgt2_register_l1_cache105_counter_query(perf);
   acmgt2_register_l1_cache106_counter_query(perf);
   acmgt2_register_l1_cache107_counter_query(perf);
   acmgt2_register_l1_cache108_counter_query(perf);
   acmgt2_register_l1_cache109_counter_query(perf);
   acmgt2_register_l1_cache110_counter_query(perf);
   acmgt2_register_l1_cache111_counter_query(perf);
   acmgt2_register_l1_cache112_counter_query(perf);
   acmgt2_register_l1_cache113_counter_query(perf);
   acmgt2_register_l1_cache114_counter_query(perf);
   acmgt2_register_l1_cache115_counter_query(perf);
   acmgt2_register_l1_cache116_counter_query(perf);
   acmgt2_register_l1_cache117_counter_query(perf);
   acmgt2_register_l1_cache118_counter_query(perf);
   acmgt2_register_l1_cache119_counter_query(perf);
   acmgt2_register_l1_cache120_counter_query(perf);
   acmgt2_register_l1_cache121_counter_query(perf);
   acmgt2_register_l1_cache122_counter_query(perf);
   acmgt2_register_l1_cache123_counter_query(perf);
   acmgt2_register_l1_cache124_counter_query(perf);
   acmgt2_register_l1_cache125_counter_query(perf);
   acmgt2_register_l1_cache126_counter_query(perf);
   acmgt2_register_l1_cache127_counter_query(perf);
   acmgt2_register_l1_cache128_counter_query(perf);
   acmgt2_register_l1_cache129_counter_query(perf);
   acmgt2_register_l1_cache130_counter_query(perf);
   acmgt2_register_l1_cache131_counter_query(perf);
   acmgt2_register_l1_cache132_counter_query(perf);
   acmgt2_register_l1_cache133_counter_query(perf);
   acmgt2_register_l1_cache134_counter_query(perf);
   acmgt2_register_l1_cache135_counter_query(perf);
   acmgt2_register_l1_cache136_counter_query(perf);
   acmgt2_register_l1_cache137_counter_query(perf);
   acmgt2_register_l1_cache138_counter_query(perf);
   acmgt2_register_l1_cache139_counter_query(perf);
   acmgt2_register_l1_cache140_counter_query(perf);
   acmgt2_register_l1_cache141_counter_query(perf);
   acmgt2_register_l1_cache142_counter_query(perf);
   acmgt2_register_l1_cache143_counter_query(perf);
   acmgt2_register_l1_cache144_counter_query(perf);
   acmgt2_register_l1_cache145_counter_query(perf);
   acmgt2_register_l1_cache146_counter_query(perf);
   acmgt2_register_l1_cache147_counter_query(perf);
   acmgt2_register_l1_cache148_counter_query(perf);
   acmgt2_register_l1_cache149_counter_query(perf);
   acmgt2_register_l1_cache150_counter_query(perf);
   acmgt2_register_l1_cache151_counter_query(perf);
   acmgt2_register_l1_cache152_counter_query(perf);
   acmgt2_register_l1_cache153_counter_query(perf);
   acmgt2_register_l1_cache154_counter_query(perf);
   acmgt2_register_l1_cache155_counter_query(perf);
   acmgt2_register_l1_cache156_counter_query(perf);
   acmgt2_register_l3_cache1_counter_query(perf);
   acmgt2_register_l3_cache2_counter_query(perf);
   acmgt2_register_l3_cache3_counter_query(perf);
   acmgt2_register_l3_cache4_counter_query(perf);
   acmgt2_register_l3_cache5_counter_query(perf);
   acmgt2_register_l3_cache6_counter_query(perf);
   acmgt2_register_l3_cache7_counter_query(perf);
   acmgt2_register_l3_cache8_counter_query(perf);
   acmgt2_register_l3_cache9_counter_query(perf);
   acmgt2_register_l3_cache10_counter_query(perf);
   acmgt2_register_l3_cache11_counter_query(perf);
   acmgt2_register_l3_cache12_counter_query(perf);
   acmgt2_register_l3_cache13_counter_query(perf);
   acmgt2_register_l3_cache14_counter_query(perf);
   acmgt2_register_l3_cache15_counter_query(perf);
   acmgt2_register_l3_cache16_counter_query(perf);
   acmgt2_register_l3_cache17_counter_query(perf);
   acmgt2_register_l3_cache18_counter_query(perf);
   acmgt2_register_l3_cache19_counter_query(perf);
   acmgt2_register_l3_cache20_counter_query(perf);
   acmgt2_register_l3_cache21_counter_query(perf);
   acmgt2_register_l3_cache22_counter_query(perf);
   acmgt2_register_memory1_counter_query(perf);
   acmgt2_register_memory2_counter_query(perf);
   acmgt2_register_memory3_counter_query(perf);
   acmgt2_register_memory4_counter_query(perf);
   acmgt2_register_memory5_counter_query(perf);
   acmgt2_register_memory6_counter_query(perf);
   acmgt2_register_memory7_counter_query(perf);
   acmgt2_register_memory8_counter_query(perf);
   acmgt2_register_memory9_counter_query(perf);
   acmgt2_register_memory10_counter_query(perf);
   acmgt2_register_memory11_counter_query(perf);
   acmgt2_register_memory12_counter_query(perf);
   acmgt2_register_memory13_counter_query(perf);
   acmgt2_register_memory14_counter_query(perf);
   acmgt2_register_rasterizer1_counter_query(perf);
   acmgt2_register_rasterizer2_counter_query(perf);
   acmgt2_register_ray_tracing1_counter_query(perf);
   acmgt2_register_ray_tracing2_counter_query(perf);
   acmgt2_register_ray_tracing3_counter_query(perf);
   acmgt2_register_ray_tracing4_counter_query(perf);
   acmgt2_register_ray_tracing5_counter_query(perf);
   acmgt2_register_ray_tracing6_counter_query(perf);
   acmgt2_register_ray_tracing7_counter_query(perf);
   acmgt2_register_ray_tracing8_counter_query(perf);
   acmgt2_register_ray_tracing9_counter_query(perf);
   acmgt2_register_ray_tracing10_counter_query(perf);
   acmgt2_register_ray_tracing11_counter_query(perf);
   acmgt2_register_ray_tracing12_counter_query(perf);
   acmgt2_register_ray_tracing13_counter_query(perf);
   acmgt2_register_ray_tracing14_counter_query(perf);
   acmgt2_register_ray_tracing15_counter_query(perf);
   acmgt2_register_ray_tracing16_counter_query(perf);
   acmgt2_register_ray_tracing17_counter_query(perf);
   acmgt2_register_ray_tracing18_counter_query(perf);
   acmgt2_register_ray_tracing19_counter_query(perf);
   acmgt2_register_ray_tracing20_counter_query(perf);
   acmgt2_register_ray_tracing21_counter_query(perf);
   acmgt2_register_ray_tracing22_counter_query(perf);
   acmgt2_register_ray_tracing23_counter_query(perf);
   acmgt2_register_ray_tracing24_counter_query(perf);
   acmgt2_register_ray_tracing25_counter_query(perf);
   acmgt2_register_ray_tracing26_counter_query(perf);
   acmgt2_register_ray_tracing27_counter_query(perf);
   acmgt2_register_ray_tracing28_counter_query(perf);
   acmgt2_register_ray_tracing29_counter_query(perf);
   acmgt2_register_ray_tracing30_counter_query(perf);
   acmgt2_register_ray_tracing31_counter_query(perf);
   acmgt2_register_ray_tracing32_counter_query(perf);
   acmgt2_register_ray_tracing33_counter_query(perf);
   acmgt2_register_ray_tracing34_counter_query(perf);
   acmgt2_register_ray_tracing35_counter_query(perf);
   acmgt2_register_ray_tracing36_counter_query(perf);
   acmgt2_register_ray_tracing37_counter_query(perf);
   acmgt2_register_ray_tracing38_counter_query(perf);
   acmgt2_register_ray_tracing39_counter_query(perf);
   acmgt2_register_ray_tracing40_counter_query(perf);
   acmgt2_register_ray_tracing41_counter_query(perf);
   acmgt2_register_ray_tracing42_counter_query(perf);
   acmgt2_register_ray_tracing43_counter_query(perf);
   acmgt2_register_ray_tracing44_counter_query(perf);
   acmgt2_register_ray_tracing45_counter_query(perf);
   acmgt2_register_ray_tracing46_counter_query(perf);
   acmgt2_register_ray_tracing47_counter_query(perf);
   acmgt2_register_ray_tracing48_counter_query(perf);
   acmgt2_register_ray_tracing49_counter_query(perf);
   acmgt2_register_ray_tracing50_counter_query(perf);
   acmgt2_register_ray_tracing51_counter_query(perf);
   acmgt2_register_ray_tracing52_counter_query(perf);
   acmgt2_register_ray_tracing53_counter_query(perf);
   acmgt2_register_ray_tracing54_counter_query(perf);
   acmgt2_register_ray_tracing55_counter_query(perf);
   acmgt2_register_ray_tracing56_counter_query(perf);
   acmgt2_register_ray_tracing57_counter_query(perf);
   acmgt2_register_ray_tracing58_counter_query(perf);
   acmgt2_register_ray_tracing59_counter_query(perf);
   acmgt2_register_ray_tracing60_counter_query(perf);
   acmgt2_register_ray_tracing61_counter_query(perf);
   acmgt2_register_ray_tracing62_counter_query(perf);
   acmgt2_register_ray_tracing63_counter_query(perf);
   acmgt2_register_ray_tracing64_counter_query(perf);
   acmgt2_register_ray_tracing65_counter_query(perf);
   acmgt2_register_ray_tracing66_counter_query(perf);
   acmgt2_register_ray_tracing67_counter_query(perf);
   acmgt2_register_ray_tracing68_counter_query(perf);
   acmgt2_register_ray_tracing69_counter_query(perf);
   acmgt2_register_ray_tracing70_counter_query(perf);
   acmgt2_register_ray_tracing71_counter_query(perf);
   acmgt2_register_ray_tracing72_counter_query(perf);
   acmgt2_register_ray_tracing73_counter_query(perf);
   acmgt2_register_ray_tracing74_counter_query(perf);
   acmgt2_register_ray_tracing75_counter_query(perf);
   acmgt2_register_ray_tracing76_counter_query(perf);
   acmgt2_register_ray_tracing77_counter_query(perf);
   acmgt2_register_ray_tracing78_counter_query(perf);
   acmgt2_register_sampler1_counter_query(perf);
   acmgt2_register_sampler2_counter_query(perf);
   acmgt2_register_sampler3_counter_query(perf);
   acmgt2_register_sampler4_counter_query(perf);
   acmgt2_register_sampler5_counter_query(perf);
   acmgt2_register_sampler6_counter_query(perf);
   acmgt2_register_sampler7_counter_query(perf);
   acmgt2_register_sampler8_counter_query(perf);
   acmgt2_register_sampler9_counter_query(perf);
   acmgt2_register_sampler10_counter_query(perf);
   acmgt2_register_sampler11_counter_query(perf);
   acmgt2_register_thread_dispatcher1_counter_query(perf);
   acmgt2_register_thread_dispatcher2_counter_query(perf);
   acmgt2_register_thread_dispatcher3_counter_query(perf);
   acmgt2_register_thread_dispatcher4_counter_query(perf);
   acmgt2_register_thread_dispatcher5_counter_query(perf);
   acmgt2_register_thread_dispatcher6_counter_query(perf);
   acmgt2_register_thread_dispatcher7_counter_query(perf);
   acmgt2_register_thread_dispatcher8_counter_query(perf);
   acmgt2_register_thread_dispatcher9_counter_query(perf);
   acmgt2_register_thread_dispatcher10_counter_query(perf);
   acmgt2_register_thread_dispatcher11_counter_query(perf);
   acmgt2_register_thread_dispatcher12_counter_query(perf);
   acmgt2_register_thread_dispatcher13_counter_query(perf);
   acmgt2_register_thread_dispatcher14_counter_query(perf);
   acmgt2_register_thread_dispatcher15_counter_query(perf);
   acmgt2_register_thread_dispatcher16_counter_query(perf);
   acmgt2_register_thread_dispatcher17_counter_query(perf);
   acmgt2_register_thread_dispatcher18_counter_query(perf);
   acmgt2_register_thread_dispatcher19_counter_query(perf);
   acmgt2_register_thread_dispatcher20_counter_query(perf);
   acmgt2_register_thread_dispatcher21_counter_query(perf);
   acmgt2_register_thread_dispatcher22_counter_query(perf);
   acmgt2_register_thread_dispatcher23_counter_query(perf);
   acmgt2_register_thread_dispatcher24_counter_query(perf);
   acmgt2_register_thread_dispatcher25_counter_query(perf);
   acmgt2_register_thread_dispatcher26_counter_query(perf);
   acmgt2_register_thread_dispatcher27_counter_query(perf);
   acmgt2_register_thread_dispatcher28_counter_query(perf);
   acmgt2_register_thread_dispatcher29_counter_query(perf);
   acmgt2_register_thread_dispatcher30_counter_query(perf);
   acmgt2_register_thread_dispatcher31_counter_query(perf);
   acmgt2_register_thread_dispatcher32_counter_query(perf);
   acmgt2_register_thread_dispatcher33_counter_query(perf);
   acmgt2_register_thread_dispatcher34_counter_query(perf);
   acmgt2_register_thread_dispatcher35_counter_query(perf);
   acmgt2_register_thread_dispatcher36_counter_query(perf);
   acmgt2_register_thread_dispatcher37_counter_query(perf);
   acmgt2_register_thread_dispatcher38_counter_query(perf);
   acmgt2_register_thread_dispatcher39_counter_query(perf);
   acmgt2_register_thread_dispatcher40_counter_query(perf);
   acmgt2_register_thread_dispatcher41_counter_query(perf);
   acmgt2_register_thread_dispatcher42_counter_query(perf);
   acmgt2_register_thread_dispatcher43_counter_query(perf);
   acmgt2_register_thread_dispatcher44_counter_query(perf);
   acmgt2_register_thread_dispatcher45_counter_query(perf);
   acmgt2_register_thread_dispatcher46_counter_query(perf);
   acmgt2_register_urb1_counter_query(perf);
   acmgt2_register_urb2_counter_query(perf);
   acmgt2_register_urb3_counter_query(perf);
   acmgt2_register_urb4_counter_query(perf);
   acmgt2_register_vector_engine1_counter_query(perf);
   acmgt2_register_vector_engine2_counter_query(perf);
   acmgt2_register_vector_engine3_counter_query(perf);
   acmgt2_register_vector_engine4_counter_query(perf);
   acmgt2_register_vector_engine5_counter_query(perf);
   acmgt2_register_vector_engine6_counter_query(perf);
   acmgt2_register_vector_engine7_counter_query(perf);
   acmgt2_register_vector_engine8_counter_query(perf);
   acmgt2_register_vector_engine9_counter_query(perf);
   acmgt2_register_vector_engine10_counter_query(perf);
   acmgt2_register_vector_engine11_counter_query(perf);
   acmgt2_register_vector_engine12_counter_query(perf);
   acmgt2_register_vector_engine13_counter_query(perf);
   acmgt2_register_vector_engine14_counter_query(perf);
   acmgt2_register_vector_engine15_counter_query(perf);
   acmgt2_register_vector_engine16_counter_query(perf);
   acmgt2_register_vector_engine17_counter_query(perf);
   acmgt2_register_vector_engine18_counter_query(perf);
   acmgt2_register_vector_engine19_counter_query(perf);
   acmgt2_register_vector_engine20_counter_query(perf);
   acmgt2_register_vector_engine21_counter_query(perf);
   acmgt2_register_vector_engine22_counter_query(perf);
   acmgt2_register_vector_engine23_counter_query(perf);
   acmgt2_register_vector_engine24_counter_query(perf);
   acmgt2_register_vector_engine25_counter_query(perf);
   acmgt2_register_vector_engine26_counter_query(perf);
   acmgt2_register_vector_engine27_counter_query(perf);
   acmgt2_register_vector_engine28_counter_query(perf);
   acmgt2_register_vector_engine29_counter_query(perf);
   acmgt2_register_vector_engine30_counter_query(perf);
   acmgt2_register_vector_engine31_counter_query(perf);
   acmgt2_register_vector_engine32_counter_query(perf);
   acmgt2_register_vector_engine33_counter_query(perf);
   acmgt2_register_vector_engine34_counter_query(perf);
   acmgt2_register_vector_engine35_counter_query(perf);
   acmgt2_register_vector_engine36_counter_query(perf);
   acmgt2_register_vector_engine37_counter_query(perf);
   acmgt2_register_vector_engine38_counter_query(perf);
   acmgt2_register_vector_engine39_counter_query(perf);
   acmgt2_register_vector_engine40_counter_query(perf);
   acmgt2_register_vector_engine41_counter_query(perf);
}


static void
acmgt3_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 40);

   query->name = "Render Metrics Basic";
   query->symbol_name = "RenderBasic";
   query->guid = "47b237c5-ed48-465b-b869-0d7ef59a6982";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C840000 },
         { .reg = 0x00009888, .val = 0x1E842800 },
         { .reg = 0x00009888, .val = 0x02844000 },
         { .reg = 0x00009888, .val = 0x04840010 },
         { .reg = 0x00009888, .val = 0x0A840800 },
         { .reg = 0x00009888, .val = 0x0C840037 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x00865000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x000A5000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x02030090 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000100C0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00003008 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__render_basic__avg_gpu_core_frequency__max,acmgt3__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2106, 24, NULL,acmgt3__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2107, 32, NULL,acmgt3__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2108, 40, NULL,acmgt3__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 2109, 48, NULL,acmgt3__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2110, 56, NULL,acmgt3__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 539, 64, NULL,acmgt3__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 540, 72, percentage_max_float,acmgt3__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 541, 76, percentage_max_float,acmgt3__render_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 80, percentage_max_float,acmgt3__render_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 543, 84, percentage_max_float,acmgt3__render_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 544, 88, percentage_max_float,acmgt3__render_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 545, 92, percentage_max_float,acmgt3__render_basic__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 546, 96, percentage_max_float,acmgt3__render_basic__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 547, 100, percentage_max_float,acmgt3__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 548, 104, percentage_max_float,acmgt3__render_basic__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 549, 108, percentage_max_float,acmgt3__render_basic__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 550, 112, percentage_max_float,acmgt3__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_uint64(query, 2111, 120, NULL,acmgt3__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 580, 128, NULL,acmgt3__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 2112, 136, NULL,acmgt3__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 2113, 144, NULL,acmgt3__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 2114, 152, NULL,acmgt3__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 551, 160, NULL,acmgt3__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 552, 168, NULL,acmgt3__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 553, 176, NULL,acmgt3__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 554, 184, NULL,acmgt3__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 555, 192, acmgt3__render_basic__slm_reads__max,acmgt3__render_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 556, 200, acmgt3__render_basic__slm_writes__max,acmgt3__render_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 557, 208, NULL,acmgt3__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 558, 216, NULL,acmgt3__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 559, 224, NULL,acmgt3__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 560, 232, acmgt3__render_basic__gti_read_throughput__max,acmgt3__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 561, 240, acmgt3__render_basic__gti_write_throughput__max,acmgt3__render_basic__gti_write_throughput__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3293, 248, percentage_max_float,acmgt3__render_basic__sampler00_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 563, 252, percentage_max_float,acmgt3__render_basic__samplers_busy__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3294, 256, percentage_max_float,acmgt3__render_basic__sampler00_bottleneck__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 565, 260, percentage_max_float,acmgt3__render_basic__sampler_bottleneck__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Compute Metrics Basic";
   query->symbol_name = "ComputeBasic";
   query->guid = "1643fb69-a674-4438-8b44-840e988877bd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00003009 },
         { .reg = 0x0000E758, .val = 0x0000200A },
         { .reg = 0x0000E45C, .val = 0x00006008 },
         { .reg = 0x0000E55C, .val = 0x0000B007 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__compute_basic__avg_gpu_core_frequency__max,acmgt3__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 539, 32, NULL,acmgt3__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 541, 40, percentage_max_float,acmgt3__compute_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 44, percentage_max_float,acmgt3__compute_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 566, 48, percentage_max_float,acmgt3__compute_basic__fpu_active__read);

      intel_perf_query_add_counter_float(query, 567, 52, percentage_max_float,acmgt3__compute_basic__em_active__read);

      intel_perf_query_add_counter_float(query, 568, 56, percentage_max_float,acmgt3__compute_basic__xmx_active__read);

      intel_perf_query_add_counter_float(query, 544, 60, percentage_max_float,acmgt3__compute_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 569, 64, percentage_max_float,acmgt3__compute_basic__xve_fpu_xmx_active__read);

      intel_perf_query_add_counter_float(query, 570, 68, acmgt3__compute_basic__xve_avg_ipc_rate__max,acmgt3__compute_basic__xve_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 571, 72, percentage_max_float,acmgt3__compute_basic__send_active__read);

      intel_perf_query_add_counter_float(query, 543, 76, percentage_max_float,acmgt3__compute_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 572, 80, percentage_max_float,acmgt3__compute_basic__xve_fpu_flt16__read);

      intel_perf_query_add_counter_float(query, 573, 84, percentage_max_float,acmgt3__compute_basic__xve_fpu_flt32__read);

      intel_perf_query_add_counter_float(query, 574, 88, percentage_max_float,acmgt3__compute_basic__xve_fpu_flt64__read);

      intel_perf_query_add_counter_uint64(query, 553, 96, NULL,acmgt3__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 554, 104, NULL,acmgt3__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 555, 112, acmgt3__compute_basic__slm_reads__max,acmgt3__compute_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 556, 120, acmgt3__compute_basic__slm_writes__max,acmgt3__compute_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 557, 128, NULL,acmgt3__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 558, 136, NULL,acmgt3__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 559, 144, NULL,acmgt3__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 560, 152, acmgt3__compute_basic__gti_read_throughput__max,acmgt3__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 561, 160, acmgt3__compute_basic__gti_write_throughput__max,acmgt3__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "a4b6cfe0-e514-49d2-857c-38f3487ea62a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00010000 },
         { .reg = 0x0000E558, .val = 0x00060050 },
         { .reg = 0x0000E658, .val = 0x00001090 },
         { .reg = 0x0000E758, .val = 0x00051011 },
         { .reg = 0x0000E45C, .val = 0x00091061 },
         { .reg = 0x0000E55C, .val = 0x00004008 },
         { .reg = 0x0000E65C, .val = 0x00000005 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__async_compute__avg_gpu_core_frequency__max,acmgt3__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 2106, 32, NULL,acmgt3__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2107, 40, NULL,acmgt3__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2108, 48, NULL,acmgt3__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 2109, 56, NULL,acmgt3__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2110, 64, NULL,acmgt3__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 539, 72, NULL,acmgt3__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 566, 80, percentage_max_float,acmgt3__async_compute__fpu_active__read);

      intel_perf_query_add_counter_float(query, 545, 84, percentage_max_float,acmgt3__async_compute__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 548, 88, percentage_max_float,acmgt3__async_compute__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 582, 92, percentage_max_float,acmgt3__async_compute__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 583, 96, percentage_max_float,acmgt3__async_compute__async_cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 567, 100, percentage_max_float,acmgt3__async_compute__em_active__read);

      intel_perf_query_add_counter_float(query, 546, 104, percentage_max_float,acmgt3__async_compute__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 549, 108, percentage_max_float,acmgt3__async_compute__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 584, 112, percentage_max_float,acmgt3__async_compute__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 585, 116, percentage_max_float,acmgt3__async_compute__async_cs_em_active__read);

      intel_perf_query_add_counter_float(query, 543, 120, percentage_max_float,acmgt3__async_compute__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 541, 124, percentage_max_float,acmgt3__async_compute__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 128, percentage_max_float,acmgt3__async_compute__xve_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_xve_activity1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "XveActivity1";
   query->symbol_name = "XveActivity1";
   query->guid = "026653d5-37d2-4970-bffd-b1c64dc03dec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00030020 },
         { .reg = 0x0000E558, .val = 0x00021040 },
         { .reg = 0x0000E658, .val = 0x00041031 },
         { .reg = 0x0000E758, .val = 0x00032022 },
         { .reg = 0x0000E45C, .val = 0x00062042 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__xve_activity1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__xve_activity1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__xve_activity1__avg_gpu_core_frequency__max,acmgt3__xve_activity1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__xve_activity1__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 2106, 32, NULL,acmgt3__xve_activity1__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2107, 40, NULL,acmgt3__xve_activity1__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2108, 48, NULL,acmgt3__xve_activity1__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 2109, 56, NULL,acmgt3__xve_activity1__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2110, 64, NULL,acmgt3__xve_activity1__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 539, 72, NULL,acmgt3__xve_activity1__cs_threads__read);

      intel_perf_query_add_counter_float(query, 586, 80, percentage_max_float,acmgt3__xve_activity1__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 587, 84, percentage_max_float,acmgt3__xve_activity1__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 588, 88, percentage_max_float,acmgt3__xve_activity1__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 589, 92, percentage_max_float,acmgt3__xve_activity1__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 590, 96, percentage_max_float,acmgt3__xve_activity1__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 591, 100, percentage_max_float,acmgt3__xve_activity1__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 592, 104, percentage_max_float,acmgt3__xve_activity1__hs_send_active__read);

      intel_perf_query_add_counter_float(query, 593, 108, percentage_max_float,acmgt3__xve_activity1__ds_send_active__read);

      intel_perf_query_add_counter_float(query, 594, 112, percentage_max_float,acmgt3__xve_activity1__gs_send_active__read);

      intel_perf_query_add_counter_float(query, 595, 116, percentage_max_float,acmgt3__xve_activity1__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 25);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "a20872dc-9d91-4ec5-966b-3ae75cb581b7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x420A2400 },
         { .reg = 0x00009888, .val = 0x1A131200 },
         { .reg = 0x00009888, .val = 0x040A0022 },
         { .reg = 0x00009888, .val = 0x120A0014 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x00104000 },
         { .reg = 0x00009888, .val = 0x02100002 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x00134000 },
         { .reg = 0x00009888, .val = 0x0A130024 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x420A2400 },
         { .reg = 0x00009888, .val = 0x1A131200 },
         { .reg = 0x00009888, .val = 0x040A0022 },
         { .reg = 0x00009888, .val = 0x100A0014 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x00102400 },
         { .reg = 0x00009888, .val = 0x00120400 },
         { .reg = 0x00009888, .val = 0x00134000 },
         { .reg = 0x00009888, .val = 0x08130024 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x18012400 },
         { .reg = 0x00009888, .val = 0x18042400 },
         { .reg = 0x00009888, .val = 0x20042400 },
         { .reg = 0x00009888, .val = 0x28042400 },
         { .reg = 0x00009888, .val = 0x32040009 },
         { .reg = 0x00009888, .val = 0x3C041200 },
         { .reg = 0x00009888, .val = 0x02010006 },
         { .reg = 0x00009888, .val = 0x10010004 },
         { .reg = 0x00009888, .val = 0x0001F81F },
         { .reg = 0x00009888, .val = 0x000426E9 },
         { .reg = 0x00009888, .val = 0x020401F7 },
         { .reg = 0x00009888, .val = 0x04041000 },
         { .reg = 0x00009888, .val = 0x0604050C },
         { .reg = 0x00009888, .val = 0x0804091C },
         { .reg = 0x00009888, .val = 0x1004051C },
         { .reg = 0x00009888, .val = 0x1204010C },
         { .reg = 0x00009888, .val = 0x14040024 },
         { .reg = 0x00009888, .val = 0x00080155 },
         { .reg = 0x00009888, .val = 0x02085544 },
         { .reg = 0x00009888, .val = 0x00056800 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032B6D },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E031004 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42031084 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030400 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030C62 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40031084 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000081 },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__gpu_busyness__avg_gpu_core_frequency__max,acmgt3__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 541, 28, percentage_max_float,acmgt3__gpu_busyness__xve_active__read);

      intel_perf_query_add_counter_float(query, 542, 32, percentage_max_float,acmgt3__gpu_busyness__xve_stall__read);

      intel_perf_query_add_counter_float(query, 543, 36, percentage_max_float,acmgt3__gpu_busyness__xve_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 2106, 40, NULL,acmgt3__gpu_busyness__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2107, 48, NULL,acmgt3__gpu_busyness__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2108, 56, NULL,acmgt3__gpu_busyness__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 2109, 64, NULL,acmgt3__gpu_busyness__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 2110, 72, NULL,acmgt3__gpu_busyness__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 539, 80, NULL,acmgt3__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 596, 88, percentage_max_float,acmgt3__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 597, 92, percentage_max_float,acmgt3__gpu_busyness__compute_engine0_busy__read);

      intel_perf_query_add_counter_float(query, 598, 96, percentage_max_float,acmgt3__gpu_busyness__compute_engine1_busy__read);

      intel_perf_query_add_counter_float(query, 599, 100, percentage_max_float,acmgt3__gpu_busyness__compute_engine2_busy__read);

      intel_perf_query_add_counter_float(query, 600, 104, percentage_max_float,acmgt3__gpu_busyness__compute_engine3_busy__read);

      intel_perf_query_add_counter_float(query, 601, 108, percentage_max_float,acmgt3__gpu_busyness__blitter_busy__read);

      intel_perf_query_add_counter_float(query, 602, 112, percentage_max_float,acmgt3__gpu_busyness__vdbox00_busy__read);

      intel_perf_query_add_counter_float(query, 603, 116, percentage_max_float,acmgt3__gpu_busyness__vebox0_busy__read);

      intel_perf_query_add_counter_float(query, 604, 120, percentage_max_float,acmgt3__gpu_busyness__vdbox10_busy__read);

      intel_perf_query_add_counter_float(query, 605, 124, percentage_max_float,acmgt3__gpu_busyness__vebox1_busy__read);

      intel_perf_query_add_counter_float(query, 606, 128, percentage_max_float,acmgt3__gpu_busyness__any_compute_engine_busy__read);

      intel_perf_query_add_counter_float(query, 607, 132, percentage_max_float,acmgt3__gpu_busyness__render_and_any_compute_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "7389b9c9-de73-468d-83a8-b27776215e6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x34080000 },
         { .reg = 0x00009888, .val = 0x06088000 },
         { .reg = 0x00009888, .val = 0x10080FF3 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x02032400 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__test_oa__avg_gpu_core_frequency__max,acmgt3__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 750, 24, NULL,acmgt3__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 751, 32, NULL,acmgt3__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 752, 40, NULL,acmgt3__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 753, 48, NULL,acmgt3__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 754, 56, NULL,acmgt3__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 755, 64, NULL,acmgt3__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 756, 72, NULL,acmgt3__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 757, 80, NULL,acmgt3__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 758, 88, NULL,acmgt3__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 759, 96, NULL,acmgt3__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_hdc_and_sf__slice01_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set HDCAndSF for Slice01";
   query->symbol_name = "HDCAndSF_Slice01";
   query->guid = "ba8ef361-332f-42f2-9c66-f8531db5e511";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E8101E0 },
         { .reg = 0x00009888, .val = 0x1EA101E0 },
         { .reg = 0x00009888, .val = 0x1EC101E0 },
         { .reg = 0x00009888, .val = 0x1EE101E0 },
         { .reg = 0x00009888, .val = 0x1F8101E0 },
         { .reg = 0x00009888, .val = 0x1FA101E0 },
         { .reg = 0x00009888, .val = 0x1FC101E0 },
         { .reg = 0x00009888, .val = 0x1FE101E0 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x08810011 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x08A10440 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0AC10011 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0AE10440 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810011 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10440 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10011 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10440 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__hdc_and_sf__slice01__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__hdc_and_sf__slice01__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__hdc_and_sf__slice01__avg_gpu_core_frequency__max,acmgt3__hdc_and_sf__slice01__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__hdc_and_sf__slice01__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3295, 28, percentage_max_float,acmgt3__hdc_and_sf__slice01__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3296, 32, percentage_max_float,acmgt3__hdc_and_sf__slice01__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3297, 36, percentage_max_float,acmgt3__hdc_and_sf__slice01__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3298, 40, percentage_max_float,acmgt3__hdc_and_sf__slice01__non_sampler_shader03_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3299, 44, percentage_max_float,acmgt3__hdc_and_sf__slice01__non_sampler_shader10_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3300, 48, percentage_max_float,acmgt3__hdc_and_sf__slice01__non_sampler_shader11_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3301, 52, percentage_max_float,acmgt3__hdc_and_sf__slice01__non_sampler_shader12_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3302, 56, percentage_max_float,acmgt3__hdc_and_sf__slice01__non_sampler_shader13_access_stalled_on_l3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_hdc_and_sf__slice23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set HDCAndSF for Slice23";
   query->symbol_name = "HDCAndSF_Slice23";
   query->guid = "a950a603-f683-4f26-a83d-a7ebbe218afb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8101E0 },
         { .reg = 0x00009888, .val = 0x1EA101E0 },
         { .reg = 0x00009888, .val = 0x1EC101E0 },
         { .reg = 0x00009888, .val = 0x1EE101E0 },
         { .reg = 0x00009888, .val = 0x1F8101E0 },
         { .reg = 0x00009888, .val = 0x1FA101E0 },
         { .reg = 0x00009888, .val = 0x1FC101E0 },
         { .reg = 0x00009888, .val = 0x1FE101E0 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x08810011 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x08A10440 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0AC10011 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0AE10440 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810011 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10440 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10011 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10440 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__hdc_and_sf__slice23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__hdc_and_sf__slice23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__hdc_and_sf__slice23__avg_gpu_core_frequency__max,acmgt3__hdc_and_sf__slice23__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__hdc_and_sf__slice23__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 670, 28, percentage_max_float,acmgt3__hdc_and_sf__slice23__non_sampler_shader20_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 671, 32, percentage_max_float,acmgt3__hdc_and_sf__slice23__non_sampler_shader21_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 672, 36, percentage_max_float,acmgt3__hdc_and_sf__slice23__non_sampler_shader22_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 673, 40, percentage_max_float,acmgt3__hdc_and_sf__slice23__non_sampler_shader23_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 674, 44, percentage_max_float,acmgt3__hdc_and_sf__slice23__non_sampler_shader30_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 675, 48, percentage_max_float,acmgt3__hdc_and_sf__slice23__non_sampler_shader31_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 676, 52, percentage_max_float,acmgt3__hdc_and_sf__slice23__non_sampler_shader32_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 677, 56, percentage_max_float,acmgt3__hdc_and_sf__slice23__non_sampler_shader33_access_stalled_on_l3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_hdc_and_sf__slice45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set HDCAndSF for Slice45";
   query->symbol_name = "HDCAndSF_Slice45";
   query->guid = "60f4dc32-a7b6-4301-8d34-be04b1c94e38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8101E0 },
         { .reg = 0x00009888, .val = 0x1EA101E0 },
         { .reg = 0x00009888, .val = 0x1EC101E0 },
         { .reg = 0x00009888, .val = 0x1EE101E0 },
         { .reg = 0x00009888, .val = 0x1F8101E0 },
         { .reg = 0x00009888, .val = 0x1FA101E0 },
         { .reg = 0x00009888, .val = 0x1FC101E0 },
         { .reg = 0x00009888, .val = 0x1FE101E0 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x08810011 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x08A10440 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0AC10011 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0AE10440 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810011 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10440 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10011 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10440 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__hdc_and_sf__slice45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__hdc_and_sf__slice45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__hdc_and_sf__slice45__avg_gpu_core_frequency__max,acmgt3__hdc_and_sf__slice45__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__hdc_and_sf__slice45__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2181, 28, percentage_max_float,acmgt3__hdc_and_sf__slice45__non_sampler_shader40_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2182, 32, percentage_max_float,acmgt3__hdc_and_sf__slice45__non_sampler_shader41_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2183, 36, percentage_max_float,acmgt3__hdc_and_sf__slice45__non_sampler_shader42_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2184, 40, percentage_max_float,acmgt3__hdc_and_sf__slice45__non_sampler_shader43_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2185, 44, percentage_max_float,acmgt3__hdc_and_sf__slice45__non_sampler_shader50_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2186, 48, percentage_max_float,acmgt3__hdc_and_sf__slice45__non_sampler_shader51_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2187, 52, percentage_max_float,acmgt3__hdc_and_sf__slice45__non_sampler_shader52_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2188, 56, percentage_max_float,acmgt3__hdc_and_sf__slice45__non_sampler_shader53_access_stalled_on_l3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_hdc_and_sf__slice67_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set HDCAndSF for Slice67";
   query->symbol_name = "HDCAndSF_Slice67";
   query->guid = "7666a6f3-801d-4082-ab47-f534b4dad494";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E8101E0 },
         { .reg = 0x00009888, .val = 0x1EA101E0 },
         { .reg = 0x00009888, .val = 0x1EC101E0 },
         { .reg = 0x00009888, .val = 0x1EE101E0 },
         { .reg = 0x00009888, .val = 0x1F8101E0 },
         { .reg = 0x00009888, .val = 0x1FA101E0 },
         { .reg = 0x00009888, .val = 0x1FC101E0 },
         { .reg = 0x00009888, .val = 0x1FE101E0 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x08810011 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x08A10440 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0AC10011 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0AE10440 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810011 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10440 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10011 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10440 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__hdc_and_sf__slice67__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__hdc_and_sf__slice67__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__hdc_and_sf__slice67__avg_gpu_core_frequency__max,acmgt3__hdc_and_sf__slice67__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__hdc_and_sf__slice67__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3303, 28, percentage_max_float,acmgt3__hdc_and_sf__slice67__non_sampler_shader60_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3304, 32, percentage_max_float,acmgt3__hdc_and_sf__slice67__non_sampler_shader61_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3305, 36, percentage_max_float,acmgt3__hdc_and_sf__slice67__non_sampler_shader62_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3306, 40, percentage_max_float,acmgt3__hdc_and_sf__slice67__non_sampler_shader63_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3307, 44, percentage_max_float,acmgt3__hdc_and_sf__slice67__non_sampler_shader70_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3308, 48, percentage_max_float,acmgt3__hdc_and_sf__slice67__non_sampler_shader71_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3309, 52, percentage_max_float,acmgt3__hdc_and_sf__slice67__non_sampler_shader72_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3310, 56, percentage_max_float,acmgt3__hdc_and_sf__slice67__non_sampler_shader73_access_stalled_on_l3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_hdc_and_sf1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Metric set HDCAndSF1";
   query->symbol_name = "HDCAndSF1";
   query->guid = "5357c0dc-c0cb-4ee0-bb6e-2d0882d357a6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12056400 },
         { .reg = 0x00009888, .val = 0x13056400 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x0205001C },
         { .reg = 0x00009888, .val = 0x00060001 },
         { .reg = 0x00009888, .val = 0x0008000D },
         { .reg = 0x00009888, .val = 0x000A0005 },
         { .reg = 0x00009888, .val = 0x00010002 },
         { .reg = 0x00009888, .val = 0x000B0008 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x03050700 },
         { .reg = 0x00009888, .val = 0x01060002 },
         { .reg = 0x00009888, .val = 0x01080004 },
         { .reg = 0x00009888, .val = 0x010A0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12056400 },
         { .reg = 0x00009888, .val = 0x13056400 },
         { .reg = 0x00009888, .val = 0x00030008 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x04050007 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00060004 },
         { .reg = 0x00009888, .val = 0x000800D0 },
         { .reg = 0x00009888, .val = 0x000A0050 },
         { .reg = 0x00009888, .val = 0x00010008 },
         { .reg = 0x00009888, .val = 0x000B0080 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x050501C0 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01060008 },
         { .reg = 0x00009888, .val = 0x01080040 },
         { .reg = 0x00009888, .val = 0x010A0040 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12056400 },
         { .reg = 0x00009888, .val = 0x13056400 },
         { .reg = 0x00009888, .val = 0x00030020 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x06050007 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00060010 },
         { .reg = 0x00009888, .val = 0x00080D00 },
         { .reg = 0x00009888, .val = 0x000A0500 },
         { .reg = 0x00009888, .val = 0x00010020 },
         { .reg = 0x00009888, .val = 0x000B0800 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x070501C0 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01060020 },
         { .reg = 0x00009888, .val = 0x01080400 },
         { .reg = 0x00009888, .val = 0x010A0400 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x12056400 },
         { .reg = 0x00009888, .val = 0x13056400 },
         { .reg = 0x00009888, .val = 0x00030080 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x08050007 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00060040 },
         { .reg = 0x00009888, .val = 0x0008D000 },
         { .reg = 0x00009888, .val = 0x000A5000 },
         { .reg = 0x00009888, .val = 0x00010080 },
         { .reg = 0x00009888, .val = 0x000B8000 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x090501C0 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01060080 },
         { .reg = 0x00009888, .val = 0x01084000 },
         { .reg = 0x00009888, .val = 0x010A4000 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x0C017000 },
         { .reg = 0x00009888, .val = 0x0C217000 },
         { .reg = 0x00009888, .val = 0x0C417000 },
         { .reg = 0x00009888, .val = 0x0C617000 },
         { .reg = 0x00009888, .val = 0x0C817000 },
         { .reg = 0x00009888, .val = 0x0CA17000 },
         { .reg = 0x00009888, .val = 0x0CC17000 },
         { .reg = 0x00009888, .val = 0x0CE17000 },
         { .reg = 0x00009888, .val = 0x02010010 },
         { .reg = 0x00009888, .val = 0x16010006 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02210010 },
         { .reg = 0x00009888, .val = 0x14210180 },
         { .reg = 0x00009888, .val = 0x00210000 },
         { .reg = 0x00009888, .val = 0x02410010 },
         { .reg = 0x00009888, .val = 0x14410006 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610010 },
         { .reg = 0x00009888, .val = 0x12610180 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810010 },
         { .reg = 0x00009888, .val = 0x12810006 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10010 },
         { .reg = 0x00009888, .val = 0x10A10180 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02C10010 },
         { .reg = 0x00009888, .val = 0x10C10006 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02E10010 },
         { .reg = 0x00009888, .val = 0x0EE10180 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0002A500 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02034849 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x02093800 },
         { .reg = 0x00009888, .val = 0x0409000A },
         { .reg = 0x00009888, .val = 0x020A1200 },
         { .reg = 0x00009888, .val = 0x040A2489 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x040B2700 },
         { .reg = 0x00009888, .val = 0x060B0001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E0314C9 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032424 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030101 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031060 },
         { .reg = 0x00009888, .val = 0x48031E00 },
         { .reg = 0x00009888, .val = 0x4A030DE6 },
         { .reg = 0x00009888, .val = 0x1603F000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x40031084 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x2003F000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000C },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010030 },
         { .reg = 0x00009888, .val = 0x00020500 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x00050500 },
         { .reg = 0x00009888, .val = 0x00080A00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100C0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__hdc_and_sf1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__hdc_and_sf1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__hdc_and_sf1__avg_gpu_core_frequency__max,acmgt3__hdc_and_sf1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__hdc_and_sf1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 3311, 28, percentage_max_float,acmgt3__hdc_and_sf1__poly0_data_ready__read);

      intel_perf_query_add_counter_float(query, 3312, 32, percentage_max_float,acmgt3__hdc_and_sf1__poly1_data_ready__read);

      intel_perf_query_add_counter_float(query, 678, 36, percentage_max_float,acmgt3__hdc_and_sf1__poly2_data_ready__read);

      intel_perf_query_add_counter_float(query, 679, 40, percentage_max_float,acmgt3__hdc_and_sf1__poly3_data_ready__read);

      intel_perf_query_add_counter_float(query, 2177, 44, percentage_max_float,acmgt3__hdc_and_sf1__poly4_data_ready__read);

      intel_perf_query_add_counter_float(query, 2178, 48, percentage_max_float,acmgt3__hdc_and_sf1__poly5_data_ready__read);

      intel_perf_query_add_counter_float(query, 3313, 52, percentage_max_float,acmgt3__hdc_and_sf1__poly6_data_ready__read);

      intel_perf_query_add_counter_float(query, 3314, 56, percentage_max_float,acmgt3__hdc_and_sf1__poly7_data_ready__read);

      intel_perf_query_add_counter_float(query, 3315, 60, percentage_max_float,acmgt3__hdc_and_sf1__gt_request_queue00_full__read);

      intel_perf_query_add_counter_float(query, 3316, 64, percentage_max_float,acmgt3__hdc_and_sf1__gt_request_queue10_full__read);

      intel_perf_query_add_counter_float(query, 680, 68, percentage_max_float,acmgt3__hdc_and_sf1__gt_request_queue20_full__read);

      intel_perf_query_add_counter_float(query, 681, 72, percentage_max_float,acmgt3__hdc_and_sf1__gt_request_queue30_full__read);

      intel_perf_query_add_counter_float(query, 2179, 76, percentage_max_float,acmgt3__hdc_and_sf1__gt_request_queue40_full__read);

      intel_perf_query_add_counter_float(query, 2180, 80, percentage_max_float,acmgt3__hdc_and_sf1__gt_request_queue50_full__read);

      intel_perf_query_add_counter_float(query, 3317, 84, percentage_max_float,acmgt3__hdc_and_sf1__gt_request_queue60_full__read);

      intel_perf_query_add_counter_float(query, 3318, 88, percentage_max_float,acmgt3__hdc_and_sf1__gt_request_queue70_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l3__slice01_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "L3_Slice01";
   query->symbol_name = "L3_Slice01";
   query->guid = "b0c45d01-03a9-46c2-a04f-2c6a7a5d73d7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l3__slice01__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l3__slice01__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l3__slice01__avg_gpu_core_frequency__max,acmgt3__l3__slice01__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__l3__slice01__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 3319, 28, percentage_max_float,acmgt3__l3__slice01__l30_bank0_input_available__read);

      intel_perf_query_add_counter_float(query, 3320, 32, percentage_max_float,acmgt3__l3__slice01__l30_bank1_input_available__read);

      intel_perf_query_add_counter_float(query, 3321, 36, percentage_max_float,acmgt3__l3__slice01__l30_bank2_input_available__read);

      intel_perf_query_add_counter_float(query, 3322, 40, percentage_max_float,acmgt3__l3__slice01__l30_bank3_input_available__read);

      intel_perf_query_add_counter_float(query, 3323, 44, percentage_max_float,acmgt3__l3__slice01__l30_bank4_input_available__read);

      intel_perf_query_add_counter_float(query, 3324, 48, percentage_max_float,acmgt3__l3__slice01__l30_bank5_input_available__read);

      intel_perf_query_add_counter_float(query, 3325, 52, percentage_max_float,acmgt3__l3__slice01__l30_bank6_input_available__read);

      intel_perf_query_add_counter_float(query, 3326, 56, percentage_max_float,acmgt3__l3__slice01__l30_bank7_input_available__read);

      intel_perf_query_add_counter_float(query, 3327, 60, percentage_max_float,acmgt3__l3__slice01__l30_bank0_output_ready__read);

      intel_perf_query_add_counter_float(query, 3328, 64, percentage_max_float,acmgt3__l3__slice01__l30_bank1_output_ready__read);

      intel_perf_query_add_counter_float(query, 3329, 68, percentage_max_float,acmgt3__l3__slice01__l30_bank2_output_ready__read);

      intel_perf_query_add_counter_float(query, 3330, 72, percentage_max_float,acmgt3__l3__slice01__l30_bank3_output_ready__read);

      intel_perf_query_add_counter_float(query, 3331, 76, percentage_max_float,acmgt3__l3__slice01__l30_bank4_output_ready__read);

      intel_perf_query_add_counter_float(query, 3332, 80, percentage_max_float,acmgt3__l3__slice01__l30_bank5_output_ready__read);

      intel_perf_query_add_counter_float(query, 3333, 84, percentage_max_float,acmgt3__l3__slice01__l30_bank6_output_ready__read);

      intel_perf_query_add_counter_float(query, 3334, 88, percentage_max_float,acmgt3__l3__slice01__l30_bank7_output_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l3__slice23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "L3_Slice23";
   query->symbol_name = "L3_Slice23";
   query->guid = "0c42d17c-81b7-4058-9864-65db72b70e27";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l3__slice23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l3__slice23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l3__slice23__avg_gpu_core_frequency__max,acmgt3__l3__slice23__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__l3__slice23__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 638, 28, percentage_max_float,acmgt3__l3__slice23__l31_bank0_input_available__read);

      intel_perf_query_add_counter_float(query, 639, 32, percentage_max_float,acmgt3__l3__slice23__l31_bank1_input_available__read);

      intel_perf_query_add_counter_float(query, 640, 36, percentage_max_float,acmgt3__l3__slice23__l31_bank2_input_available__read);

      intel_perf_query_add_counter_float(query, 641, 40, percentage_max_float,acmgt3__l3__slice23__l31_bank3_input_available__read);

      intel_perf_query_add_counter_float(query, 642, 44, percentage_max_float,acmgt3__l3__slice23__l31_bank4_input_available__read);

      intel_perf_query_add_counter_float(query, 643, 48, percentage_max_float,acmgt3__l3__slice23__l31_bank5_input_available__read);

      intel_perf_query_add_counter_float(query, 644, 52, percentage_max_float,acmgt3__l3__slice23__l31_bank6_input_available__read);

      intel_perf_query_add_counter_float(query, 645, 56, percentage_max_float,acmgt3__l3__slice23__l31_bank7_input_available__read);

      intel_perf_query_add_counter_float(query, 646, 60, percentage_max_float,acmgt3__l3__slice23__l31_bank0_output_ready__read);

      intel_perf_query_add_counter_float(query, 647, 64, percentage_max_float,acmgt3__l3__slice23__l31_bank1_output_ready__read);

      intel_perf_query_add_counter_float(query, 648, 68, percentage_max_float,acmgt3__l3__slice23__l31_bank2_output_ready__read);

      intel_perf_query_add_counter_float(query, 649, 72, percentage_max_float,acmgt3__l3__slice23__l31_bank3_output_ready__read);

      intel_perf_query_add_counter_float(query, 650, 76, percentage_max_float,acmgt3__l3__slice23__l31_bank4_output_ready__read);

      intel_perf_query_add_counter_float(query, 651, 80, percentage_max_float,acmgt3__l3__slice23__l31_bank5_output_ready__read);

      intel_perf_query_add_counter_float(query, 652, 84, percentage_max_float,acmgt3__l3__slice23__l31_bank6_output_ready__read);

      intel_perf_query_add_counter_float(query, 653, 88, percentage_max_float,acmgt3__l3__slice23__l31_bank7_output_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l3__slice45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "L3_Slice45";
   query->symbol_name = "L3_Slice45";
   query->guid = "59ce881a-3c51-45e0-96b4-3b565220f3a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l3__slice45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l3__slice45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l3__slice45__avg_gpu_core_frequency__max,acmgt3__l3__slice45__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__l3__slice45__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 2145, 28, percentage_max_float,acmgt3__l3__slice45__l32_bank0_input_available__read);

      intel_perf_query_add_counter_float(query, 2146, 32, percentage_max_float,acmgt3__l3__slice45__l32_bank1_input_available__read);

      intel_perf_query_add_counter_float(query, 2147, 36, percentage_max_float,acmgt3__l3__slice45__l32_bank2_input_available__read);

      intel_perf_query_add_counter_float(query, 2148, 40, percentage_max_float,acmgt3__l3__slice45__l32_bank3_input_available__read);

      intel_perf_query_add_counter_float(query, 2149, 44, percentage_max_float,acmgt3__l3__slice45__l32_bank4_input_available__read);

      intel_perf_query_add_counter_float(query, 2150, 48, percentage_max_float,acmgt3__l3__slice45__l32_bank5_input_available__read);

      intel_perf_query_add_counter_float(query, 2151, 52, percentage_max_float,acmgt3__l3__slice45__l32_bank6_input_available__read);

      intel_perf_query_add_counter_float(query, 2152, 56, percentage_max_float,acmgt3__l3__slice45__l32_bank7_input_available__read);

      intel_perf_query_add_counter_float(query, 2153, 60, percentage_max_float,acmgt3__l3__slice45__l32_bank0_output_ready__read);

      intel_perf_query_add_counter_float(query, 2154, 64, percentage_max_float,acmgt3__l3__slice45__l32_bank1_output_ready__read);

      intel_perf_query_add_counter_float(query, 2155, 68, percentage_max_float,acmgt3__l3__slice45__l32_bank2_output_ready__read);

      intel_perf_query_add_counter_float(query, 2156, 72, percentage_max_float,acmgt3__l3__slice45__l32_bank3_output_ready__read);

      intel_perf_query_add_counter_float(query, 2157, 76, percentage_max_float,acmgt3__l3__slice45__l32_bank4_output_ready__read);

      intel_perf_query_add_counter_float(query, 2158, 80, percentage_max_float,acmgt3__l3__slice45__l32_bank5_output_ready__read);

      intel_perf_query_add_counter_float(query, 2159, 84, percentage_max_float,acmgt3__l3__slice45__l32_bank6_output_ready__read);

      intel_perf_query_add_counter_float(query, 2160, 88, percentage_max_float,acmgt3__l3__slice45__l32_bank7_output_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l3__slice67_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "L3_Slice67";
   query->symbol_name = "L3_Slice67";
   query->guid = "36b86585-1933-4c0f-9fd0-6dfe61480d8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l3__slice67__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l3__slice67__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l3__slice67__avg_gpu_core_frequency__max,acmgt3__l3__slice67__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__l3__slice67__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 3335, 28, percentage_max_float,acmgt3__l3__slice67__l33_bank0_input_available__read);

      intel_perf_query_add_counter_float(query, 3336, 32, percentage_max_float,acmgt3__l3__slice67__l33_bank1_input_available__read);

      intel_perf_query_add_counter_float(query, 3337, 36, percentage_max_float,acmgt3__l3__slice67__l33_bank2_input_available__read);

      intel_perf_query_add_counter_float(query, 3338, 40, percentage_max_float,acmgt3__l3__slice67__l33_bank3_input_available__read);

      intel_perf_query_add_counter_float(query, 3339, 44, percentage_max_float,acmgt3__l3__slice67__l33_bank4_input_available__read);

      intel_perf_query_add_counter_float(query, 3340, 48, percentage_max_float,acmgt3__l3__slice67__l33_bank5_input_available__read);

      intel_perf_query_add_counter_float(query, 3341, 52, percentage_max_float,acmgt3__l3__slice67__l33_bank6_input_available__read);

      intel_perf_query_add_counter_float(query, 3342, 56, percentage_max_float,acmgt3__l3__slice67__l33_bank7_input_available__read);

      intel_perf_query_add_counter_float(query, 3343, 60, percentage_max_float,acmgt3__l3__slice67__l33_bank0_output_ready__read);

      intel_perf_query_add_counter_float(query, 3344, 64, percentage_max_float,acmgt3__l3__slice67__l33_bank1_output_ready__read);

      intel_perf_query_add_counter_float(query, 3345, 68, percentage_max_float,acmgt3__l3__slice67__l33_bank2_output_ready__read);

      intel_perf_query_add_counter_float(query, 3346, 72, percentage_max_float,acmgt3__l3__slice67__l33_bank3_output_ready__read);

      intel_perf_query_add_counter_float(query, 3347, 76, percentage_max_float,acmgt3__l3__slice67__l33_bank4_output_ready__read);

      intel_perf_query_add_counter_float(query, 3348, 80, percentage_max_float,acmgt3__l3__slice67__l33_bank5_output_ready__read);

      intel_perf_query_add_counter_float(query, 3349, 84, percentage_max_float,acmgt3__l3__slice67__l33_bank6_output_ready__read);

      intel_perf_query_add_counter_float(query, 3350, 88, percentage_max_float,acmgt3__l3__slice67__l33_bank7_output_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_rasterizer_and_pixel_backend1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set RasterizerAndPixelBackend1";
   query->symbol_name = "RasterizerAndPixelBackend1";
   query->guid = "99a4388a-a104-4bbb-b8b2-7b827644a16b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A056000 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x0C0B7000 },
         { .reg = 0x00009888, .val = 0x0E0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C701F },
         { .reg = 0x00009888, .val = 0x0E0C6000 },
         { .reg = 0x00009888, .val = 0x1B057000 },
         { .reg = 0x00009888, .val = 0x00038000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x020535D2 },
         { .reg = 0x00009888, .val = 0x0405003E },
         { .reg = 0x00009888, .val = 0x00060007 },
         { .reg = 0x00009888, .val = 0x00072800 },
         { .reg = 0x00009888, .val = 0x000803D5 },
         { .reg = 0x00009888, .val = 0x0208C000 },
         { .reg = 0x00009888, .val = 0x00090060 },
         { .reg = 0x00009888, .val = 0x000A2955 },
         { .reg = 0x00009888, .val = 0x020A4000 },
         { .reg = 0x00009888, .val = 0x00018018 },
         { .reg = 0x00009888, .val = 0x040B0200 },
         { .reg = 0x00009888, .val = 0x080B0400 },
         { .reg = 0x00009888, .val = 0x0A0B001F },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B8000 },
         { .reg = 0x00009888, .val = 0x00020060 },
         { .reg = 0x00009888, .val = 0x040C0200 },
         { .reg = 0x00009888, .val = 0x0A0C0400 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x11050DC0 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01068000 },
         { .reg = 0x00009888, .val = 0x03084000 },
         { .reg = 0x00009888, .val = 0x030A4000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A056000 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x0C0B7000 },
         { .reg = 0x00009888, .val = 0x0E0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C7000 },
         { .reg = 0x00009888, .val = 0x0E0C6000 },
         { .reg = 0x00009888, .val = 0x1B057000 },
         { .reg = 0x00009888, .val = 0x00034000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050002 },
         { .reg = 0x00009888, .val = 0x08050D00 },
         { .reg = 0x00009888, .val = 0x0A050FB5 },
         { .reg = 0x00009888, .val = 0x00060380 },
         { .reg = 0x00009888, .val = 0x02070A00 },
         { .reg = 0x00009888, .val = 0x00084000 },
         { .reg = 0x00009888, .val = 0x020830F5 },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x000A4000 },
         { .reg = 0x00009888, .val = 0x020A1A55 },
         { .reg = 0x00009888, .val = 0x00014C00 },
         { .reg = 0x00009888, .val = 0x040B0200 },
         { .reg = 0x00009888, .val = 0x100B07D0 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x00023000 },
         { .reg = 0x00009888, .val = 0x040C0200 },
         { .reg = 0x00009888, .val = 0x120C07D0 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x11050037 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01064000 },
         { .reg = 0x00009888, .val = 0x03081000 },
         { .reg = 0x00009888, .val = 0x030A1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008EAAA },
         { .reg = 0x00009888, .val = 0x0208BFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E0314A8 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030CA5 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030462 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40030042 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001807F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x02044000 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02054000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017F80 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00044000 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00054000 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000D950, .val = 0x00000300 },
         { .reg = 0x0000D954, .val = 0x0000FF9F },
         { .reg = 0x0000D958, .val = 0x00001C00 },
         { .reg = 0x0000D95C, .val = 0x0000FC7F },
         { .reg = 0x0000D960, .val = 0x00006000 },
         { .reg = 0x0000D964, .val = 0x0000F3FF },
         { .reg = 0x0000D968, .val = 0x00018000 },
         { .reg = 0x0000D96C, .val = 0x0000CFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__rasterizer_and_pixel_backend1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__rasterizer_and_pixel_backend1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max,acmgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__rasterizer_and_pixel_backend1__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 3351, 28, percentage_max_float,acmgt3__rasterizer_and_pixel_backend1__rasterizer0_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 3352, 32, percentage_max_float,acmgt3__rasterizer_and_pixel_backend1__rasterizer1_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 3353, 36, percentage_max_float,acmgt3__rasterizer_and_pixel_backend1__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 3354, 40, percentage_max_float,acmgt3__rasterizer_and_pixel_backend1__pixel_data01_ready__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 682, 44, percentage_max_float,acmgt3__rasterizer_and_pixel_backend1__rasterizer2_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 683, 48, percentage_max_float,acmgt3__rasterizer_and_pixel_backend1__rasterizer3_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 684, 52, percentage_max_float,acmgt3__rasterizer_and_pixel_backend1__pixel_data20_ready__read);

      intel_perf_query_add_counter_float(query, 685, 56, percentage_max_float,acmgt3__rasterizer_and_pixel_backend1__pixel_data21_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_rasterizer_and_pixel_backend2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set RasterizerAndPixelBackend2";
   query->symbol_name = "RasterizerAndPixelBackend2";
   query->guid = "c5db2948-d89c-468c-b52e-f2323a099c92";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A057000 },
         { .reg = 0x00009888, .val = 0x1B056000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x0D0B701F },
         { .reg = 0x00009888, .val = 0x0F0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C7000 },
         { .reg = 0x00009888, .val = 0x0F0C6000 },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x10050DC0 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00068000 },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x02084000 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x020A4000 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x030535D2 },
         { .reg = 0x00009888, .val = 0x0505003E },
         { .reg = 0x00009888, .val = 0x01060007 },
         { .reg = 0x00009888, .val = 0x01070280 },
         { .reg = 0x00009888, .val = 0x01083C15 },
         { .reg = 0x00009888, .val = 0x01090018 },
         { .reg = 0x00009888, .val = 0x010A1695 },
         { .reg = 0x00009888, .val = 0x01010060 },
         { .reg = 0x00009888, .val = 0x050B0200 },
         { .reg = 0x00009888, .val = 0x0B0B0400 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x01020018 },
         { .reg = 0x00009888, .val = 0x050C0200 },
         { .reg = 0x00009888, .val = 0x090C0400 },
         { .reg = 0x00009888, .val = 0x0B0C001F },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A057000 },
         { .reg = 0x00009888, .val = 0x1B056000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x0D0B7000 },
         { .reg = 0x00009888, .val = 0x0F0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C7000 },
         { .reg = 0x00009888, .val = 0x0F0C6000 },
         { .reg = 0x00009888, .val = 0x00033F80 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x10050037 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00064000 },
         { .reg = 0x00009888, .val = 0x0008C000 },
         { .reg = 0x00009888, .val = 0x02081FFF },
         { .reg = 0x00009888, .val = 0x000A4000 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00013F80 },
         { .reg = 0x00009888, .val = 0x000B8000 },
         { .reg = 0x00009888, .val = 0x020B0AAA },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03050002 },
         { .reg = 0x00009888, .val = 0x09050D00 },
         { .reg = 0x00009888, .val = 0x0B050FB5 },
         { .reg = 0x00009888, .val = 0x01060380 },
         { .reg = 0x00009888, .val = 0x03070A00 },
         { .reg = 0x00009888, .val = 0x01084000 },
         { .reg = 0x00009888, .val = 0x030800F5 },
         { .reg = 0x00009888, .val = 0x01093000 },
         { .reg = 0x00009888, .val = 0x010A4000 },
         { .reg = 0x00009888, .val = 0x030A0A55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x050B0200 },
         { .reg = 0x00009888, .val = 0x110B07D0 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x050C0200 },
         { .reg = 0x00009888, .val = 0x130C07D0 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008EAAA },
         { .reg = 0x00009888, .val = 0x0208BFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C66 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x420318C3 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030060 },
         { .reg = 0x00009888, .val = 0x4A030C06 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C00 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001807F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x02044000 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02054000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017F80 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00044000 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00054000 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000D950, .val = 0x00000300 },
         { .reg = 0x0000D954, .val = 0x0000FF9F },
         { .reg = 0x0000D958, .val = 0x00001C00 },
         { .reg = 0x0000D95C, .val = 0x0000FC7F },
         { .reg = 0x0000D960, .val = 0x00006000 },
         { .reg = 0x0000D964, .val = 0x0000F3FF },
         { .reg = 0x0000D968, .val = 0x00018000 },
         { .reg = 0x0000D96C, .val = 0x0000CFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__rasterizer_and_pixel_backend2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__rasterizer_and_pixel_backend2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max,acmgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__rasterizer_and_pixel_backend2__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 3355, 28, percentage_max_float,acmgt3__rasterizer_and_pixel_backend2__rasterizer1_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 3356, 32, percentage_max_float,acmgt3__rasterizer_and_pixel_backend2__rasterizer0_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 3357, 36, percentage_max_float,acmgt3__rasterizer_and_pixel_backend2__pixel_data10_ready__read);

      intel_perf_query_add_counter_float(query, 3358, 40, percentage_max_float,acmgt3__rasterizer_and_pixel_backend2__pixel_data11_ready__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 690, 44, percentage_max_float,acmgt3__rasterizer_and_pixel_backend2__rasterizer3_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 691, 48, percentage_max_float,acmgt3__rasterizer_and_pixel_backend2__rasterizer2_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 692, 52, percentage_max_float,acmgt3__rasterizer_and_pixel_backend2__pixel_data30_ready__read);

      intel_perf_query_add_counter_float(query, 693, 56, percentage_max_float,acmgt3__rasterizer_and_pixel_backend2__pixel_data31_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_rasterizer_and_pixel_backend3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set RasterizerAndPixelBackend3";
   query->symbol_name = "RasterizerAndPixelBackend3";
   query->guid = "d8d668a7-3468-4ff2-84ab-f285b2468295";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A056000 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x0C0B7000 },
         { .reg = 0x00009888, .val = 0x0E0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C701F },
         { .reg = 0x00009888, .val = 0x0E0C6000 },
         { .reg = 0x00009888, .val = 0x1B057000 },
         { .reg = 0x00009888, .val = 0x00038000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x020535D2 },
         { .reg = 0x00009888, .val = 0x0405003E },
         { .reg = 0x00009888, .val = 0x00060007 },
         { .reg = 0x00009888, .val = 0x00072800 },
         { .reg = 0x00009888, .val = 0x000803D5 },
         { .reg = 0x00009888, .val = 0x0208C000 },
         { .reg = 0x00009888, .val = 0x00090060 },
         { .reg = 0x00009888, .val = 0x000A2955 },
         { .reg = 0x00009888, .val = 0x020A4000 },
         { .reg = 0x00009888, .val = 0x00018018 },
         { .reg = 0x00009888, .val = 0x040B0200 },
         { .reg = 0x00009888, .val = 0x080B0400 },
         { .reg = 0x00009888, .val = 0x0A0B001F },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B8000 },
         { .reg = 0x00009888, .val = 0x00020060 },
         { .reg = 0x00009888, .val = 0x040C0200 },
         { .reg = 0x00009888, .val = 0x0A0C0400 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x11050DC0 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01068000 },
         { .reg = 0x00009888, .val = 0x03084000 },
         { .reg = 0x00009888, .val = 0x030A4000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A056000 },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x0C0B7000 },
         { .reg = 0x00009888, .val = 0x0E0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C7000 },
         { .reg = 0x00009888, .val = 0x0E0C6000 },
         { .reg = 0x00009888, .val = 0x1B057000 },
         { .reg = 0x00009888, .val = 0x00034000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050002 },
         { .reg = 0x00009888, .val = 0x08050D00 },
         { .reg = 0x00009888, .val = 0x0A050FB5 },
         { .reg = 0x00009888, .val = 0x00060380 },
         { .reg = 0x00009888, .val = 0x02070A00 },
         { .reg = 0x00009888, .val = 0x00084000 },
         { .reg = 0x00009888, .val = 0x020830F5 },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x000A4000 },
         { .reg = 0x00009888, .val = 0x020A1A55 },
         { .reg = 0x00009888, .val = 0x00014C00 },
         { .reg = 0x00009888, .val = 0x040B0200 },
         { .reg = 0x00009888, .val = 0x100B07D0 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x00023000 },
         { .reg = 0x00009888, .val = 0x040C0200 },
         { .reg = 0x00009888, .val = 0x120C07D0 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x11050037 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01064000 },
         { .reg = 0x00009888, .val = 0x03081000 },
         { .reg = 0x00009888, .val = 0x030A1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00029555 },
         { .reg = 0x00009888, .val = 0x02026AAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E0314A8 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030CA5 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030462 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40030042 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001807F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x02044000 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02054000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017F80 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00044000 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00054000 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000D950, .val = 0x00000300 },
         { .reg = 0x0000D954, .val = 0x0000FF9F },
         { .reg = 0x0000D958, .val = 0x00001C00 },
         { .reg = 0x0000D95C, .val = 0x0000FC7F },
         { .reg = 0x0000D960, .val = 0x00006000 },
         { .reg = 0x0000D964, .val = 0x0000F3FF },
         { .reg = 0x0000D968, .val = 0x00018000 },
         { .reg = 0x0000D96C, .val = 0x0000CFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__rasterizer_and_pixel_backend3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__rasterizer_and_pixel_backend3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__max,acmgt3__rasterizer_and_pixel_backend3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__rasterizer_and_pixel_backend3__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2189, 28, percentage_max_float,acmgt3__rasterizer_and_pixel_backend3__rasterizer4_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2190, 32, percentage_max_float,acmgt3__rasterizer_and_pixel_backend3__rasterizer5_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 2193, 36, percentage_max_float,acmgt3__rasterizer_and_pixel_backend3__pixel_data40_ready__read);

      intel_perf_query_add_counter_float(query, 2194, 40, percentage_max_float,acmgt3__rasterizer_and_pixel_backend3__pixel_data41_ready__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 3359, 44, percentage_max_float,acmgt3__rasterizer_and_pixel_backend3__rasterizer6_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 3360, 48, percentage_max_float,acmgt3__rasterizer_and_pixel_backend3__rasterizer7_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 3361, 52, percentage_max_float,acmgt3__rasterizer_and_pixel_backend3__pixel_data60_ready__read);

      intel_perf_query_add_counter_float(query, 3362, 56, percentage_max_float,acmgt3__rasterizer_and_pixel_backend3__pixel_data61_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_rasterizer_and_pixel_backend4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Metric set RasterizerAndPixelBackend4";
   query->symbol_name = "RasterizerAndPixelBackend4";
   query->guid = "0c4bf00d-3ee4-4804-9f61-5b78f9810d6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A057000 },
         { .reg = 0x00009888, .val = 0x1B056000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x0D0B701F },
         { .reg = 0x00009888, .val = 0x0F0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C7000 },
         { .reg = 0x00009888, .val = 0x0F0C6000 },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x10050DC0 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00068000 },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x02084000 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x020A4000 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x030535D2 },
         { .reg = 0x00009888, .val = 0x0505003E },
         { .reg = 0x00009888, .val = 0x01060007 },
         { .reg = 0x00009888, .val = 0x01070280 },
         { .reg = 0x00009888, .val = 0x01083C15 },
         { .reg = 0x00009888, .val = 0x01090018 },
         { .reg = 0x00009888, .val = 0x010A1695 },
         { .reg = 0x00009888, .val = 0x01010060 },
         { .reg = 0x00009888, .val = 0x050B0200 },
         { .reg = 0x00009888, .val = 0x0B0B0400 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x01020018 },
         { .reg = 0x00009888, .val = 0x050C0200 },
         { .reg = 0x00009888, .val = 0x090C0400 },
         { .reg = 0x00009888, .val = 0x0B0C001F },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A057000 },
         { .reg = 0x00009888, .val = 0x1B056000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x0D0B7000 },
         { .reg = 0x00009888, .val = 0x0F0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C7000 },
         { .reg = 0x00009888, .val = 0x0F0C6000 },
         { .reg = 0x00009888, .val = 0x00033F80 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x10050037 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00064000 },
         { .reg = 0x00009888, .val = 0x0008C000 },
         { .reg = 0x00009888, .val = 0x02081FFF },
         { .reg = 0x00009888, .val = 0x000A4000 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00013F80 },
         { .reg = 0x00009888, .val = 0x000B8000 },
         { .reg = 0x00009888, .val = 0x020B0AAA },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03050002 },
         { .reg = 0x00009888, .val = 0x09050D00 },
         { .reg = 0x00009888, .val = 0x0B050FB5 },
         { .reg = 0x00009888, .val = 0x01060380 },
         { .reg = 0x00009888, .val = 0x03070A00 },
         { .reg = 0x00009888, .val = 0x01084000 },
         { .reg = 0x00009888, .val = 0x030800F5 },
         { .reg = 0x00009888, .val = 0x01093000 },
         { .reg = 0x00009888, .val = 0x010A4000 },
         { .reg = 0x00009888, .val = 0x030A0A55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x050B0200 },
         { .reg = 0x00009888, .val = 0x110B07D0 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x050C0200 },
         { .reg = 0x00009888, .val = 0x130C07D0 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00029555 },
         { .reg = 0x00009888, .val = 0x02026AAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C66 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x420318C3 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030060 },
         { .reg = 0x00009888, .val = 0x4A030C06 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C00 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001807F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x02044000 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02054000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017F80 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00044000 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00054000 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000D950, .val = 0x00000300 },
         { .reg = 0x0000D954, .val = 0x0000FF9F },
         { .reg = 0x0000D958, .val = 0x00001C00 },
         { .reg = 0x0000D95C, .val = 0x0000FC7F },
         { .reg = 0x0000D960, .val = 0x00006000 },
         { .reg = 0x0000D964, .val = 0x0000F3FF },
         { .reg = 0x0000D968, .val = 0x00018000 },
         { .reg = 0x0000D96C, .val = 0x0000CFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__rasterizer_and_pixel_backend4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__rasterizer_and_pixel_backend4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__rasterizer_and_pixel_backend4__avg_gpu_core_frequency__max,acmgt3__rasterizer_and_pixel_backend4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__rasterizer_and_pixel_backend4__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 2192, 28, percentage_max_float,acmgt3__rasterizer_and_pixel_backend4__rasterizer5_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 2191, 32, percentage_max_float,acmgt3__rasterizer_and_pixel_backend4__rasterizer4_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 2195, 36, percentage_max_float,acmgt3__rasterizer_and_pixel_backend4__pixel_data50_ready__read);

      intel_perf_query_add_counter_float(query, 2196, 40, percentage_max_float,acmgt3__rasterizer_and_pixel_backend4__pixel_data51_ready__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 3363, 44, percentage_max_float,acmgt3__rasterizer_and_pixel_backend4__rasterizer7_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 3364, 48, percentage_max_float,acmgt3__rasterizer_and_pixel_backend4__rasterizer6_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 3365, 52, percentage_max_float,acmgt3__rasterizer_and_pixel_backend4__pixel_data70_ready__read);

      intel_perf_query_add_counter_float(query, 3366, 56, percentage_max_float,acmgt3__rasterizer_and_pixel_backend4__pixel_data71_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_rasterizer_and_pixel_backend5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "RasterizerAndPixelBackend5";
   query->symbol_name = "RasterizerAndPixelBackend5";
   query->guid = "0eef4659-956d-4a4e-840c-dca20176165a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x04030C40 },
         { .reg = 0x00009888, .val = 0x0C030038 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00040008 },
         { .reg = 0x00009888, .val = 0x02040002 },
         { .reg = 0x00009888, .val = 0x00050004 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x04080031 },
         { .reg = 0x00009888, .val = 0x12080E00 },
         { .reg = 0x00009888, .val = 0x00080008 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x06030C40 },
         { .reg = 0x00009888, .val = 0x0E030038 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00040080 },
         { .reg = 0x00009888, .val = 0x02040020 },
         { .reg = 0x00009888, .val = 0x00050040 },
         { .reg = 0x00009888, .val = 0x02050010 },
         { .reg = 0x00009888, .val = 0x06080031 },
         { .reg = 0x00009888, .val = 0x0C080E00 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00080080 },
         { .reg = 0x00009888, .val = 0x02080020 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x08030C40 },
         { .reg = 0x00009888, .val = 0x10030038 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00040800 },
         { .reg = 0x00009888, .val = 0x02040200 },
         { .reg = 0x00009888, .val = 0x00050400 },
         { .reg = 0x00009888, .val = 0x02050100 },
         { .reg = 0x00009888, .val = 0x08080031 },
         { .reg = 0x00009888, .val = 0x0E080E00 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00080800 },
         { .reg = 0x00009888, .val = 0x02080200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x0A030C40 },
         { .reg = 0x00009888, .val = 0x12030038 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00048000 },
         { .reg = 0x00009888, .val = 0x02042000 },
         { .reg = 0x00009888, .val = 0x00054000 },
         { .reg = 0x00009888, .val = 0x02051000 },
         { .reg = 0x00009888, .val = 0x0A080031 },
         { .reg = 0x00009888, .val = 0x10080E00 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00088000 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208803E },
         { .reg = 0x00009888, .val = 0x0002A500 },
         { .reg = 0x00009888, .val = 0x02022940 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x0403124A },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032820 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030020 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030141 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031400 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030021 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030140 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__rasterizer_and_pixel_backend5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__rasterizer_and_pixel_backend5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__rasterizer_and_pixel_backend5__avg_gpu_core_frequency__max,acmgt3__rasterizer_and_pixel_backend5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 3367, 28, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 3368, 32, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__ps_output01_available__read);

      intel_perf_query_add_counter_float(query, 686, 36, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__ps_output10_available__read);

      intel_perf_query_add_counter_float(query, 687, 40, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__ps_output11_available__read);

      intel_perf_query_add_counter_float(query, 2197, 44, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__ps_output20_available__read);

      intel_perf_query_add_counter_float(query, 2199, 48, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__ps_output21_available__read);

      intel_perf_query_add_counter_float(query, 3369, 52, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__ps_output30_available__read);

      intel_perf_query_add_counter_float(query, 3370, 56, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__ps_output31_available__read);

      intel_perf_query_add_counter_float(query, 3371, 60, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__pixel_values00_ready__read);

      intel_perf_query_add_counter_float(query, 3372, 64, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__pixel_values01_ready__read);

      intel_perf_query_add_counter_float(query, 688, 68, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__pixel_values10_ready__read);

      intel_perf_query_add_counter_float(query, 689, 72, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__pixel_values11_ready__read);

      intel_perf_query_add_counter_float(query, 2198, 76, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__pixel_values20_ready__read);

      intel_perf_query_add_counter_float(query, 2200, 80, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__pixel_values21_ready__read);

      intel_perf_query_add_counter_float(query, 3373, 84, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__pixel_values30_ready__read);

      intel_perf_query_add_counter_float(query, 3374, 88, percentage_max_float,acmgt3__rasterizer_and_pixel_backend5__pixel_values31_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_render_pipe_profile__slice0_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile_Slice0";
   query->guid = "ac9c3eb4-c49e-4297-8126-3d0a78a056f8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x168607C0 },
         { .reg = 0x00009888, .val = 0x1603001F },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x12040640 },
         { .reg = 0x00009888, .val = 0x08040021 },
         { .reg = 0x00009888, .val = 0x1C070000 },
         { .reg = 0x00009888, .val = 0x16090000 },
         { .reg = 0x00009888, .val = 0x1C0903C0 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x160B7C00 },
         { .reg = 0x00009888, .val = 0x04860000 },
         { .reg = 0x00009888, .val = 0x06860400 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x0A0301C0 },
         { .reg = 0x00009888, .val = 0x100300C0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x0C040080 },
         { .reg = 0x00009888, .val = 0x0E040022 },
         { .reg = 0x00009888, .val = 0x04074000 },
         { .reg = 0x00009888, .val = 0x0A070021 },
         { .reg = 0x00009888, .val = 0x0E0708C0 },
         { .reg = 0x00009888, .val = 0x00070800 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x00083032 },
         { .reg = 0x00009888, .val = 0x02083300 },
         { .reg = 0x00009888, .val = 0x02094003 },
         { .reg = 0x00009888, .val = 0x08090880 },
         { .reg = 0x00009888, .val = 0x0C090001 },
         { .reg = 0x00009888, .val = 0x0E090023 },
         { .reg = 0x00009888, .val = 0x12090003 },
         { .reg = 0x00009888, .val = 0x00090D28 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x140A0940 },
         { .reg = 0x00009888, .val = 0x000A9A91 },
         { .reg = 0x00009888, .val = 0x020A19AA },
         { .reg = 0x00009888, .val = 0x00015044 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x020B2200 },
         { .reg = 0x00009888, .val = 0x00020C20 },
         { .reg = 0x00009888, .val = 0x000C0800 },
         { .reg = 0x00009888, .val = 0x020C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032482 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x4203180A },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x440300C2 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030200 },
         { .reg = 0x00009888, .val = 0x48030261 },
         { .reg = 0x00009888, .val = 0x4A030C22 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400304C1 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__render_pipe_profile__slice0__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__render_pipe_profile__slice0__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__render_pipe_profile__slice0__avg_gpu_core_frequency__max,acmgt3__render_pipe_profile__slice0__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__render_pipe_profile__slice0__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 3375, 28, percentage_max_float,acmgt3__render_pipe_profile__slice0__vf0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3376, 32, percentage_max_float,acmgt3__render_pipe_profile__slice0__vs0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3377, 36, percentage_max_float,acmgt3__render_pipe_profile__slice0__cl0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3378, 40, percentage_max_float,acmgt3__render_pipe_profile__slice0__hs0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3379, 44, percentage_max_float,acmgt3__render_pipe_profile__slice0__ds0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3380, 48, percentage_max_float,acmgt3__render_pipe_profile__slice0__gs0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3381, 52, percentage_max_float,acmgt3__render_pipe_profile__slice0__sf0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3382, 56, percentage_max_float,acmgt3__render_pipe_profile__slice0__so0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3383, 60, percentage_max_float,acmgt3__render_pipe_profile__slice0__cl0_stall__read);

      intel_perf_query_add_counter_float(query, 3384, 64, percentage_max_float,acmgt3__render_pipe_profile__slice0__hs0_stall__read);

      intel_perf_query_add_counter_float(query, 3385, 68, percentage_max_float,acmgt3__render_pipe_profile__slice0__ds0_stall__read);

      intel_perf_query_add_counter_float(query, 3386, 72, percentage_max_float,acmgt3__render_pipe_profile__slice0__sf0_stall__read);

      intel_perf_query_add_counter_float(query, 3387, 76, percentage_max_float,acmgt3__render_pipe_profile__slice0__so0_stall__read);

      intel_perf_query_add_counter_float(query, 3388, 80, percentage_max_float,acmgt3__render_pipe_profile__slice0__hi_depth00_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3389, 84, percentage_max_float,acmgt3__render_pipe_profile__slice0__bc00_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_render_pipe_profile__slice1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile_Slice1";
   query->guid = "53434b4e-ae6b-457a-b337-c9ebefa86aeb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x178607C0 },
         { .reg = 0x00009888, .val = 0x1703001F },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x13040640 },
         { .reg = 0x00009888, .val = 0x09040021 },
         { .reg = 0x00009888, .val = 0x1D070000 },
         { .reg = 0x00009888, .val = 0x17090000 },
         { .reg = 0x00009888, .val = 0x1D0903C0 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x170B7C00 },
         { .reg = 0x00009888, .val = 0x05860000 },
         { .reg = 0x00009888, .val = 0x07860400 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x0003FFFD },
         { .reg = 0x00009888, .val = 0x0008FFF3 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5551 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x000BAAA2 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x0B0301C0 },
         { .reg = 0x00009888, .val = 0x110300C0 },
         { .reg = 0x00009888, .val = 0x13030C80 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01040000 },
         { .reg = 0x00009888, .val = 0x0D040080 },
         { .reg = 0x00009888, .val = 0x0F040022 },
         { .reg = 0x00009888, .val = 0x05074000 },
         { .reg = 0x00009888, .val = 0x0B070021 },
         { .reg = 0x00009888, .val = 0x0F0708C0 },
         { .reg = 0x00009888, .val = 0x01070800 },
         { .reg = 0x00009888, .val = 0x030700A0 },
         { .reg = 0x00009888, .val = 0x01083032 },
         { .reg = 0x00009888, .val = 0x03083300 },
         { .reg = 0x00009888, .val = 0x03094003 },
         { .reg = 0x00009888, .val = 0x09090880 },
         { .reg = 0x00009888, .val = 0x0D090001 },
         { .reg = 0x00009888, .val = 0x0F090023 },
         { .reg = 0x00009888, .val = 0x13090003 },
         { .reg = 0x00009888, .val = 0x01090D28 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x150A0940 },
         { .reg = 0x00009888, .val = 0x010A9A91 },
         { .reg = 0x00009888, .val = 0x030A19AA },
         { .reg = 0x00009888, .val = 0x01015044 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B2000 },
         { .reg = 0x00009888, .val = 0x030B2200 },
         { .reg = 0x00009888, .val = 0x01020C20 },
         { .reg = 0x00009888, .val = 0x010C0800 },
         { .reg = 0x00009888, .val = 0x030C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032482 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x4203180A },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x440300C2 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030200 },
         { .reg = 0x00009888, .val = 0x48030261 },
         { .reg = 0x00009888, .val = 0x4A030C22 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400304C1 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__render_pipe_profile__slice1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__render_pipe_profile__slice1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__render_pipe_profile__slice1__avg_gpu_core_frequency__max,acmgt3__render_pipe_profile__slice1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__render_pipe_profile__slice1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 3390, 28, percentage_max_float,acmgt3__render_pipe_profile__slice1__vf1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3391, 32, percentage_max_float,acmgt3__render_pipe_profile__slice1__vs1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3392, 36, percentage_max_float,acmgt3__render_pipe_profile__slice1__cl1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3393, 40, percentage_max_float,acmgt3__render_pipe_profile__slice1__hs1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3394, 44, percentage_max_float,acmgt3__render_pipe_profile__slice1__ds1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3395, 48, percentage_max_float,acmgt3__render_pipe_profile__slice1__gs1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3396, 52, percentage_max_float,acmgt3__render_pipe_profile__slice1__sf1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3397, 56, percentage_max_float,acmgt3__render_pipe_profile__slice1__so1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3398, 60, percentage_max_float,acmgt3__render_pipe_profile__slice1__cl1_stall__read);

      intel_perf_query_add_counter_float(query, 3399, 64, percentage_max_float,acmgt3__render_pipe_profile__slice1__hs1_stall__read);

      intel_perf_query_add_counter_float(query, 3400, 68, percentage_max_float,acmgt3__render_pipe_profile__slice1__ds1_stall__read);

      intel_perf_query_add_counter_float(query, 3401, 72, percentage_max_float,acmgt3__render_pipe_profile__slice1__sf1_stall__read);

      intel_perf_query_add_counter_float(query, 3402, 76, percentage_max_float,acmgt3__render_pipe_profile__slice1__so1_stall__read);

      intel_perf_query_add_counter_float(query, 3403, 80, percentage_max_float,acmgt3__render_pipe_profile__slice1__hi_depth10_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3404, 84, percentage_max_float,acmgt3__render_pipe_profile__slice1__bc10_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_render_pipe_profile__slice2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile_Slice2";
   query->guid = "3921cb4b-32f1-4595-b51b-531651d6d89d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x168607C0 },
         { .reg = 0x00009888, .val = 0x1603001F },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x12040640 },
         { .reg = 0x00009888, .val = 0x08040021 },
         { .reg = 0x00009888, .val = 0x1C070000 },
         { .reg = 0x00009888, .val = 0x16090000 },
         { .reg = 0x00009888, .val = 0x1C0903C0 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x160B7C00 },
         { .reg = 0x00009888, .val = 0x04860000 },
         { .reg = 0x00009888, .val = 0x06860400 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x0A0301C0 },
         { .reg = 0x00009888, .val = 0x100300C0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x0C040080 },
         { .reg = 0x00009888, .val = 0x0E040022 },
         { .reg = 0x00009888, .val = 0x04074000 },
         { .reg = 0x00009888, .val = 0x0A070021 },
         { .reg = 0x00009888, .val = 0x0E0708C0 },
         { .reg = 0x00009888, .val = 0x00070800 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x00083032 },
         { .reg = 0x00009888, .val = 0x02083300 },
         { .reg = 0x00009888, .val = 0x02094003 },
         { .reg = 0x00009888, .val = 0x08090880 },
         { .reg = 0x00009888, .val = 0x0C090001 },
         { .reg = 0x00009888, .val = 0x0E090023 },
         { .reg = 0x00009888, .val = 0x12090003 },
         { .reg = 0x00009888, .val = 0x00090D28 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x140A0940 },
         { .reg = 0x00009888, .val = 0x000A9A91 },
         { .reg = 0x00009888, .val = 0x020A19AA },
         { .reg = 0x00009888, .val = 0x00015044 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x020B2200 },
         { .reg = 0x00009888, .val = 0x00020C20 },
         { .reg = 0x00009888, .val = 0x000C0800 },
         { .reg = 0x00009888, .val = 0x020C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFF3 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032482 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x4203180A },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x440300C2 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030200 },
         { .reg = 0x00009888, .val = 0x48030261 },
         { .reg = 0x00009888, .val = 0x4A030C22 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400304C1 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__render_pipe_profile__slice2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__render_pipe_profile__slice2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__render_pipe_profile__slice2__avg_gpu_core_frequency__max,acmgt3__render_pipe_profile__slice2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__render_pipe_profile__slice2__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 608, 28, percentage_max_float,acmgt3__render_pipe_profile__slice2__vf2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 609, 32, percentage_max_float,acmgt3__render_pipe_profile__slice2__vs2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 610, 36, percentage_max_float,acmgt3__render_pipe_profile__slice2__cl2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 611, 40, percentage_max_float,acmgt3__render_pipe_profile__slice2__hs2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 612, 44, percentage_max_float,acmgt3__render_pipe_profile__slice2__ds2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 613, 48, percentage_max_float,acmgt3__render_pipe_profile__slice2__gs2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 614, 52, percentage_max_float,acmgt3__render_pipe_profile__slice2__sf2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 615, 56, percentage_max_float,acmgt3__render_pipe_profile__slice2__so2_bottleneck__read);

      intel_perf_query_add_counter_float(query, 616, 60, percentage_max_float,acmgt3__render_pipe_profile__slice2__cl2_stall__read);

      intel_perf_query_add_counter_float(query, 617, 64, percentage_max_float,acmgt3__render_pipe_profile__slice2__hs2_stall__read);

      intel_perf_query_add_counter_float(query, 618, 68, percentage_max_float,acmgt3__render_pipe_profile__slice2__ds2_stall__read);

      intel_perf_query_add_counter_float(query, 619, 72, percentage_max_float,acmgt3__render_pipe_profile__slice2__sf2_stall__read);

      intel_perf_query_add_counter_float(query, 620, 76, percentage_max_float,acmgt3__render_pipe_profile__slice2__so2_stall__read);

      intel_perf_query_add_counter_float(query, 621, 80, percentage_max_float,acmgt3__render_pipe_profile__slice2__hi_depth20_bottleneck__read);

      intel_perf_query_add_counter_float(query, 622, 84, percentage_max_float,acmgt3__render_pipe_profile__slice2__bc20_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_render_pipe_profile__slice3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile_Slice3";
   query->guid = "47924a4a-4cbb-4c9a-a186-efd3af8acf6a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x178607C0 },
         { .reg = 0x00009888, .val = 0x1703001F },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x13040640 },
         { .reg = 0x00009888, .val = 0x09040021 },
         { .reg = 0x00009888, .val = 0x1D070000 },
         { .reg = 0x00009888, .val = 0x17090000 },
         { .reg = 0x00009888, .val = 0x1D0903C0 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x170B7C00 },
         { .reg = 0x00009888, .val = 0x05860000 },
         { .reg = 0x00009888, .val = 0x07860400 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x0003FFFD },
         { .reg = 0x00009888, .val = 0x0008FFF3 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5551 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x000BAAA2 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x0B0301C0 },
         { .reg = 0x00009888, .val = 0x110300C0 },
         { .reg = 0x00009888, .val = 0x13030C80 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01040000 },
         { .reg = 0x00009888, .val = 0x0D040080 },
         { .reg = 0x00009888, .val = 0x0F040022 },
         { .reg = 0x00009888, .val = 0x05074000 },
         { .reg = 0x00009888, .val = 0x0B070021 },
         { .reg = 0x00009888, .val = 0x0F0708C0 },
         { .reg = 0x00009888, .val = 0x01070800 },
         { .reg = 0x00009888, .val = 0x030700A0 },
         { .reg = 0x00009888, .val = 0x01083032 },
         { .reg = 0x00009888, .val = 0x03083300 },
         { .reg = 0x00009888, .val = 0x03094003 },
         { .reg = 0x00009888, .val = 0x09090880 },
         { .reg = 0x00009888, .val = 0x0D090001 },
         { .reg = 0x00009888, .val = 0x0F090023 },
         { .reg = 0x00009888, .val = 0x13090003 },
         { .reg = 0x00009888, .val = 0x01090D28 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x150A0940 },
         { .reg = 0x00009888, .val = 0x010A9A91 },
         { .reg = 0x00009888, .val = 0x030A19AA },
         { .reg = 0x00009888, .val = 0x01015044 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B2000 },
         { .reg = 0x00009888, .val = 0x030B2200 },
         { .reg = 0x00009888, .val = 0x01020C20 },
         { .reg = 0x00009888, .val = 0x010C0800 },
         { .reg = 0x00009888, .val = 0x030C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFF3 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032482 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x4203180A },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x440300C2 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030200 },
         { .reg = 0x00009888, .val = 0x48030261 },
         { .reg = 0x00009888, .val = 0x4A030C22 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400304C1 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__render_pipe_profile__slice3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__render_pipe_profile__slice3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__render_pipe_profile__slice3__avg_gpu_core_frequency__max,acmgt3__render_pipe_profile__slice3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__render_pipe_profile__slice3__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 623, 28, percentage_max_float,acmgt3__render_pipe_profile__slice3__vf3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 624, 32, percentage_max_float,acmgt3__render_pipe_profile__slice3__vs3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 625, 36, percentage_max_float,acmgt3__render_pipe_profile__slice3__cl3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 626, 40, percentage_max_float,acmgt3__render_pipe_profile__slice3__hs3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 627, 44, percentage_max_float,acmgt3__render_pipe_profile__slice3__ds3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 628, 48, percentage_max_float,acmgt3__render_pipe_profile__slice3__gs3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 629, 52, percentage_max_float,acmgt3__render_pipe_profile__slice3__sf3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 630, 56, percentage_max_float,acmgt3__render_pipe_profile__slice3__so3_bottleneck__read);

      intel_perf_query_add_counter_float(query, 631, 60, percentage_max_float,acmgt3__render_pipe_profile__slice3__cl3_stall__read);

      intel_perf_query_add_counter_float(query, 632, 64, percentage_max_float,acmgt3__render_pipe_profile__slice3__hs3_stall__read);

      intel_perf_query_add_counter_float(query, 633, 68, percentage_max_float,acmgt3__render_pipe_profile__slice3__ds3_stall__read);

      intel_perf_query_add_counter_float(query, 634, 72, percentage_max_float,acmgt3__render_pipe_profile__slice3__sf3_stall__read);

      intel_perf_query_add_counter_float(query, 635, 76, percentage_max_float,acmgt3__render_pipe_profile__slice3__so3_stall__read);

      intel_perf_query_add_counter_float(query, 636, 80, percentage_max_float,acmgt3__render_pipe_profile__slice3__hi_depth30_bottleneck__read);

      intel_perf_query_add_counter_float(query, 637, 84, percentage_max_float,acmgt3__render_pipe_profile__slice3__bc30_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_render_pipe_profile__slice4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile_Slice4";
   query->guid = "ee1b4183-c89c-4bad-a11d-b91b60769895";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x168607C0 },
         { .reg = 0x00009888, .val = 0x1603001F },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x12040640 },
         { .reg = 0x00009888, .val = 0x08040021 },
         { .reg = 0x00009888, .val = 0x1C070000 },
         { .reg = 0x00009888, .val = 0x16090000 },
         { .reg = 0x00009888, .val = 0x1C0903C0 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x160B7C00 },
         { .reg = 0x00009888, .val = 0x04860000 },
         { .reg = 0x00009888, .val = 0x06860400 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x0A0301C0 },
         { .reg = 0x00009888, .val = 0x100300C0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x0C040080 },
         { .reg = 0x00009888, .val = 0x0E040022 },
         { .reg = 0x00009888, .val = 0x04074000 },
         { .reg = 0x00009888, .val = 0x0A070021 },
         { .reg = 0x00009888, .val = 0x0E0708C0 },
         { .reg = 0x00009888, .val = 0x00070800 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x00083032 },
         { .reg = 0x00009888, .val = 0x02083300 },
         { .reg = 0x00009888, .val = 0x02094003 },
         { .reg = 0x00009888, .val = 0x08090880 },
         { .reg = 0x00009888, .val = 0x0C090001 },
         { .reg = 0x00009888, .val = 0x0E090023 },
         { .reg = 0x00009888, .val = 0x12090003 },
         { .reg = 0x00009888, .val = 0x00090D28 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x140A0940 },
         { .reg = 0x00009888, .val = 0x000A9A91 },
         { .reg = 0x00009888, .val = 0x020A19AA },
         { .reg = 0x00009888, .val = 0x00015044 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x020B2200 },
         { .reg = 0x00009888, .val = 0x00020C20 },
         { .reg = 0x00009888, .val = 0x000C0800 },
         { .reg = 0x00009888, .val = 0x020C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031241 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x4203180A },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x440300C2 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030200 },
         { .reg = 0x00009888, .val = 0x48030261 },
         { .reg = 0x00009888, .val = 0x4A030C22 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400304C1 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__render_pipe_profile__slice4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__render_pipe_profile__slice4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__render_pipe_profile__slice4__avg_gpu_core_frequency__max,acmgt3__render_pipe_profile__slice4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__render_pipe_profile__slice4__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 2115, 28, percentage_max_float,acmgt3__render_pipe_profile__slice4__vf4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2116, 32, percentage_max_float,acmgt3__render_pipe_profile__slice4__vs4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2117, 36, percentage_max_float,acmgt3__render_pipe_profile__slice4__cl4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2118, 40, percentage_max_float,acmgt3__render_pipe_profile__slice4__hs4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2119, 44, percentage_max_float,acmgt3__render_pipe_profile__slice4__ds4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2120, 48, percentage_max_float,acmgt3__render_pipe_profile__slice4__gs4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2121, 52, percentage_max_float,acmgt3__render_pipe_profile__slice4__sf4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2122, 56, percentage_max_float,acmgt3__render_pipe_profile__slice4__so4_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2123, 60, percentage_max_float,acmgt3__render_pipe_profile__slice4__cl4_stall__read);

      intel_perf_query_add_counter_float(query, 2124, 64, percentage_max_float,acmgt3__render_pipe_profile__slice4__hs4_stall__read);

      intel_perf_query_add_counter_float(query, 2125, 68, percentage_max_float,acmgt3__render_pipe_profile__slice4__ds4_stall__read);

      intel_perf_query_add_counter_float(query, 2126, 72, percentage_max_float,acmgt3__render_pipe_profile__slice4__sf4_stall__read);

      intel_perf_query_add_counter_float(query, 2127, 76, percentage_max_float,acmgt3__render_pipe_profile__slice4__so4_stall__read);

      intel_perf_query_add_counter_float(query, 2128, 80, percentage_max_float,acmgt3__render_pipe_profile__slice4__hi_depth40_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2129, 84, percentage_max_float,acmgt3__render_pipe_profile__slice4__bc40_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_render_pipe_profile__slice5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile_Slice5";
   query->guid = "a1534029-affd-453e-b8d9-2931505c5288";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x178607C0 },
         { .reg = 0x00009888, .val = 0x1703001F },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x13040640 },
         { .reg = 0x00009888, .val = 0x09040021 },
         { .reg = 0x00009888, .val = 0x1D070000 },
         { .reg = 0x00009888, .val = 0x17090000 },
         { .reg = 0x00009888, .val = 0x1D0903C0 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x170B7C00 },
         { .reg = 0x00009888, .val = 0x05860000 },
         { .reg = 0x00009888, .val = 0x07860400 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x0003FFFD },
         { .reg = 0x00009888, .val = 0x0008FFF3 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5551 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x000BAAA2 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x0B0301C0 },
         { .reg = 0x00009888, .val = 0x110300C0 },
         { .reg = 0x00009888, .val = 0x13030C80 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01040000 },
         { .reg = 0x00009888, .val = 0x0D040080 },
         { .reg = 0x00009888, .val = 0x0F040022 },
         { .reg = 0x00009888, .val = 0x05074000 },
         { .reg = 0x00009888, .val = 0x0B070021 },
         { .reg = 0x00009888, .val = 0x0F0708C0 },
         { .reg = 0x00009888, .val = 0x01070800 },
         { .reg = 0x00009888, .val = 0x030700A0 },
         { .reg = 0x00009888, .val = 0x01083032 },
         { .reg = 0x00009888, .val = 0x03083300 },
         { .reg = 0x00009888, .val = 0x03094003 },
         { .reg = 0x00009888, .val = 0x09090880 },
         { .reg = 0x00009888, .val = 0x0D090001 },
         { .reg = 0x00009888, .val = 0x0F090023 },
         { .reg = 0x00009888, .val = 0x13090003 },
         { .reg = 0x00009888, .val = 0x01090D28 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x150A0940 },
         { .reg = 0x00009888, .val = 0x010A9A91 },
         { .reg = 0x00009888, .val = 0x030A19AA },
         { .reg = 0x00009888, .val = 0x01015044 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B2000 },
         { .reg = 0x00009888, .val = 0x030B2200 },
         { .reg = 0x00009888, .val = 0x01020C20 },
         { .reg = 0x00009888, .val = 0x010C0800 },
         { .reg = 0x00009888, .val = 0x030C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031241 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x4203180A },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x440300C2 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030200 },
         { .reg = 0x00009888, .val = 0x48030261 },
         { .reg = 0x00009888, .val = 0x4A030C22 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400304C1 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__render_pipe_profile__slice5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__render_pipe_profile__slice5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__render_pipe_profile__slice5__avg_gpu_core_frequency__max,acmgt3__render_pipe_profile__slice5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__render_pipe_profile__slice5__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 2130, 28, percentage_max_float,acmgt3__render_pipe_profile__slice5__vf5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2131, 32, percentage_max_float,acmgt3__render_pipe_profile__slice5__vs5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2132, 36, percentage_max_float,acmgt3__render_pipe_profile__slice5__cl5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2133, 40, percentage_max_float,acmgt3__render_pipe_profile__slice5__hs5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2134, 44, percentage_max_float,acmgt3__render_pipe_profile__slice5__ds5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2135, 48, percentage_max_float,acmgt3__render_pipe_profile__slice5__gs5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2136, 52, percentage_max_float,acmgt3__render_pipe_profile__slice5__sf5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2137, 56, percentage_max_float,acmgt3__render_pipe_profile__slice5__so5_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2138, 60, percentage_max_float,acmgt3__render_pipe_profile__slice5__cl5_stall__read);

      intel_perf_query_add_counter_float(query, 2139, 64, percentage_max_float,acmgt3__render_pipe_profile__slice5__hs5_stall__read);

      intel_perf_query_add_counter_float(query, 2140, 68, percentage_max_float,acmgt3__render_pipe_profile__slice5__ds5_stall__read);

      intel_perf_query_add_counter_float(query, 2141, 72, percentage_max_float,acmgt3__render_pipe_profile__slice5__sf5_stall__read);

      intel_perf_query_add_counter_float(query, 2142, 76, percentage_max_float,acmgt3__render_pipe_profile__slice5__so5_stall__read);

      intel_perf_query_add_counter_float(query, 2143, 80, percentage_max_float,acmgt3__render_pipe_profile__slice5__hi_depth50_bottleneck__read);

      intel_perf_query_add_counter_float(query, 2144, 84, percentage_max_float,acmgt3__render_pipe_profile__slice5__bc50_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_render_pipe_profile__slice6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile_Slice6";
   query->guid = "26a82035-dadd-4227-a1b4-f7808081f10c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x168607C0 },
         { .reg = 0x00009888, .val = 0x1603001F },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x12040640 },
         { .reg = 0x00009888, .val = 0x08040021 },
         { .reg = 0x00009888, .val = 0x1C070000 },
         { .reg = 0x00009888, .val = 0x16090000 },
         { .reg = 0x00009888, .val = 0x1C0903C0 },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x160B7C00 },
         { .reg = 0x00009888, .val = 0x04860000 },
         { .reg = 0x00009888, .val = 0x06860400 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x0A0301C0 },
         { .reg = 0x00009888, .val = 0x100300C0 },
         { .reg = 0x00009888, .val = 0x12030C80 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040000 },
         { .reg = 0x00009888, .val = 0x0C040080 },
         { .reg = 0x00009888, .val = 0x0E040022 },
         { .reg = 0x00009888, .val = 0x04074000 },
         { .reg = 0x00009888, .val = 0x0A070021 },
         { .reg = 0x00009888, .val = 0x0E0708C0 },
         { .reg = 0x00009888, .val = 0x00070800 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x00083032 },
         { .reg = 0x00009888, .val = 0x02083300 },
         { .reg = 0x00009888, .val = 0x02094003 },
         { .reg = 0x00009888, .val = 0x08090880 },
         { .reg = 0x00009888, .val = 0x0C090001 },
         { .reg = 0x00009888, .val = 0x0E090023 },
         { .reg = 0x00009888, .val = 0x12090003 },
         { .reg = 0x00009888, .val = 0x00090D28 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x140A0940 },
         { .reg = 0x00009888, .val = 0x000A9A91 },
         { .reg = 0x00009888, .val = 0x020A19AA },
         { .reg = 0x00009888, .val = 0x00015044 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x020B2200 },
         { .reg = 0x00009888, .val = 0x00020C20 },
         { .reg = 0x00009888, .val = 0x000C0800 },
         { .reg = 0x00009888, .val = 0x020C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAA2 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031241 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x4203180A },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x440300C2 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030200 },
         { .reg = 0x00009888, .val = 0x48030261 },
         { .reg = 0x00009888, .val = 0x4A030C22 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400304C1 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__render_pipe_profile__slice6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__render_pipe_profile__slice6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__render_pipe_profile__slice6__avg_gpu_core_frequency__max,acmgt3__render_pipe_profile__slice6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__render_pipe_profile__slice6__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 3405, 28, percentage_max_float,acmgt3__render_pipe_profile__slice6__vf6_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3406, 32, percentage_max_float,acmgt3__render_pipe_profile__slice6__vs6_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3407, 36, percentage_max_float,acmgt3__render_pipe_profile__slice6__cl6_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3408, 40, percentage_max_float,acmgt3__render_pipe_profile__slice6__hs6_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3409, 44, percentage_max_float,acmgt3__render_pipe_profile__slice6__ds6_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3410, 48, percentage_max_float,acmgt3__render_pipe_profile__slice6__gs6_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3411, 52, percentage_max_float,acmgt3__render_pipe_profile__slice6__sf6_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3412, 56, percentage_max_float,acmgt3__render_pipe_profile__slice6__so6_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3413, 60, percentage_max_float,acmgt3__render_pipe_profile__slice6__cl6_stall__read);

      intel_perf_query_add_counter_float(query, 3414, 64, percentage_max_float,acmgt3__render_pipe_profile__slice6__hs6_stall__read);

      intel_perf_query_add_counter_float(query, 3415, 68, percentage_max_float,acmgt3__render_pipe_profile__slice6__ds6_stall__read);

      intel_perf_query_add_counter_float(query, 3416, 72, percentage_max_float,acmgt3__render_pipe_profile__slice6__sf6_stall__read);

      intel_perf_query_add_counter_float(query, 3417, 76, percentage_max_float,acmgt3__render_pipe_profile__slice6__so6_stall__read);

      intel_perf_query_add_counter_float(query, 3418, 80, percentage_max_float,acmgt3__render_pipe_profile__slice6__hi_depth60_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3419, 84, percentage_max_float,acmgt3__render_pipe_profile__slice6__bc60_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_render_pipe_profile__slice7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile_Slice7";
   query->guid = "71b5ebc0-874f-4ecd-b409-c387a5bb0543";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x178607C0 },
         { .reg = 0x00009888, .val = 0x1703001F },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x13040640 },
         { .reg = 0x00009888, .val = 0x09040021 },
         { .reg = 0x00009888, .val = 0x1D070000 },
         { .reg = 0x00009888, .val = 0x17090000 },
         { .reg = 0x00009888, .val = 0x1D0903C0 },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x170B7C00 },
         { .reg = 0x00009888, .val = 0x05860000 },
         { .reg = 0x00009888, .val = 0x07860400 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x0003FFFD },
         { .reg = 0x00009888, .val = 0x0008FFF3 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5551 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x000BAAA2 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x0B0301C0 },
         { .reg = 0x00009888, .val = 0x110300C0 },
         { .reg = 0x00009888, .val = 0x13030C80 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01040000 },
         { .reg = 0x00009888, .val = 0x0D040080 },
         { .reg = 0x00009888, .val = 0x0F040022 },
         { .reg = 0x00009888, .val = 0x05074000 },
         { .reg = 0x00009888, .val = 0x0B070021 },
         { .reg = 0x00009888, .val = 0x0F0708C0 },
         { .reg = 0x00009888, .val = 0x01070800 },
         { .reg = 0x00009888, .val = 0x030700A0 },
         { .reg = 0x00009888, .val = 0x01083032 },
         { .reg = 0x00009888, .val = 0x03083300 },
         { .reg = 0x00009888, .val = 0x03094003 },
         { .reg = 0x00009888, .val = 0x09090880 },
         { .reg = 0x00009888, .val = 0x0D090001 },
         { .reg = 0x00009888, .val = 0x0F090023 },
         { .reg = 0x00009888, .val = 0x13090003 },
         { .reg = 0x00009888, .val = 0x01090D28 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x150A0940 },
         { .reg = 0x00009888, .val = 0x010A9A91 },
         { .reg = 0x00009888, .val = 0x030A19AA },
         { .reg = 0x00009888, .val = 0x01015044 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B2000 },
         { .reg = 0x00009888, .val = 0x030B2200 },
         { .reg = 0x00009888, .val = 0x01020C20 },
         { .reg = 0x00009888, .val = 0x010C0800 },
         { .reg = 0x00009888, .val = 0x030C00A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAA2 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031241 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x4203180A },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x440300C2 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030200 },
         { .reg = 0x00009888, .val = 0x48030261 },
         { .reg = 0x00009888, .val = 0x4A030C22 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400304C1 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFD },
         { .reg = 0x00009888, .val = 0x00025551 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045551 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055551 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAA2 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__render_pipe_profile__slice7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__render_pipe_profile__slice7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__render_pipe_profile__slice7__avg_gpu_core_frequency__max,acmgt3__render_pipe_profile__slice7__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__render_pipe_profile__slice7__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 3420, 28, percentage_max_float,acmgt3__render_pipe_profile__slice7__vf7_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3421, 32, percentage_max_float,acmgt3__render_pipe_profile__slice7__vs7_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3422, 36, percentage_max_float,acmgt3__render_pipe_profile__slice7__cl7_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3423, 40, percentage_max_float,acmgt3__render_pipe_profile__slice7__hs7_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3424, 44, percentage_max_float,acmgt3__render_pipe_profile__slice7__ds7_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3425, 48, percentage_max_float,acmgt3__render_pipe_profile__slice7__gs7_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3426, 52, percentage_max_float,acmgt3__render_pipe_profile__slice7__sf7_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3427, 56, percentage_max_float,acmgt3__render_pipe_profile__slice7__so7_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3428, 60, percentage_max_float,acmgt3__render_pipe_profile__slice7__cl7_stall__read);

      intel_perf_query_add_counter_float(query, 3429, 64, percentage_max_float,acmgt3__render_pipe_profile__slice7__hs7_stall__read);

      intel_perf_query_add_counter_float(query, 3430, 68, percentage_max_float,acmgt3__render_pipe_profile__slice7__ds7_stall__read);

      intel_perf_query_add_counter_float(query, 3431, 72, percentage_max_float,acmgt3__render_pipe_profile__slice7__sf7_stall__read);

      intel_perf_query_add_counter_float(query, 3432, 76, percentage_max_float,acmgt3__render_pipe_profile__slice7__so7_stall__read);

      intel_perf_query_add_counter_float(query, 3433, 80, percentage_max_float,acmgt3__render_pipe_profile__slice7__hi_depth70_bottleneck__read);

      intel_perf_query_add_counter_float(query, 3434, 84, percentage_max_float,acmgt3__render_pipe_profile__slice7__bc70_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_sampler__slice01_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Sampler_Slice01";
   query->symbol_name = "Sampler_Slice01";
   query->guid = "1fa63cc6-c791-42ae-9db4-4170daefe666";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x14832C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x14A32C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x14C32C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x14E32C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x15832C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x15A32C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x15C32C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x15E32C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x16820024 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x0A830580 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x14A20900 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x0AA30016 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x14C20024 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x08C30580 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x12E20900 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x08E30016 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x13820024 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x07830580 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x07A30016 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x11C20024 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x05C30580 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x0FE20900 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x05E30016 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030863 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031C8A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44031C06 },
         { .reg = 0x00009888, .val = 0x3803F000 },
         { .reg = 0x00009888, .val = 0x460308E1 },
         { .reg = 0x00009888, .val = 0x4803003F },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__sampler__slice01__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__sampler__slice01__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__sampler__slice01__avg_gpu_core_frequency__max,acmgt3__sampler__slice01__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__sampler__slice01__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3435, 28, percentage_max_float,acmgt3__sampler__slice01__sampler00_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3436, 32, percentage_max_float,acmgt3__sampler__slice01__sampler01_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3437, 36, percentage_max_float,acmgt3__sampler__slice01__sampler02_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3438, 40, percentage_max_float,acmgt3__sampler__slice01__sampler03_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3439, 44, percentage_max_float,acmgt3__sampler__slice01__sampler10_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3440, 48, percentage_max_float,acmgt3__sampler__slice01__sampler11_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3441, 52, percentage_max_float,acmgt3__sampler__slice01__sampler12_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3442, 56, percentage_max_float,acmgt3__sampler__slice01__sampler13_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3443, 60, percentage_max_float,acmgt3__sampler__slice01__sampler00_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3444, 64, percentage_max_float,acmgt3__sampler__slice01__sampler01_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3445, 68, percentage_max_float,acmgt3__sampler__slice01__sampler02_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3446, 72, percentage_max_float,acmgt3__sampler__slice01__sampler03_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3447, 76, percentage_max_float,acmgt3__sampler__slice01__sampler10_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3448, 80, percentage_max_float,acmgt3__sampler__slice01__sampler11_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3449, 84, percentage_max_float,acmgt3__sampler__slice01__sampler12_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3450, 88, percentage_max_float,acmgt3__sampler__slice01__sampler13_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_sampler__slice23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Sampler_Slice23";
   query->symbol_name = "Sampler_Slice23";
   query->guid = "c22bbd17-c8bd-4f7e-bb2f-4b045e41f1cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x14832C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x14A32C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x14C32C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x14E32C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x15832C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x15A32C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x15C32C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x15E32C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x16820024 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x0A830580 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x14A20900 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x0AA30016 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x14C20024 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x08C30580 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x12E20900 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x08E30016 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x13820024 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x07830580 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x07A30016 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x11C20024 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x05C30580 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x0FE20900 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x05E30016 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030863 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031C8A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44031C06 },
         { .reg = 0x00009888, .val = 0x3803F000 },
         { .reg = 0x00009888, .val = 0x460308E1 },
         { .reg = 0x00009888, .val = 0x4803003F },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__sampler__slice23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__sampler__slice23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__sampler__slice23__avg_gpu_core_frequency__max,acmgt3__sampler__slice23__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__sampler__slice23__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 654, 28, percentage_max_float,acmgt3__sampler__slice23__sampler20_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 655, 32, percentage_max_float,acmgt3__sampler__slice23__sampler21_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 656, 36, percentage_max_float,acmgt3__sampler__slice23__sampler22_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 657, 40, percentage_max_float,acmgt3__sampler__slice23__sampler23_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 658, 44, percentage_max_float,acmgt3__sampler__slice23__sampler30_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 659, 48, percentage_max_float,acmgt3__sampler__slice23__sampler31_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 660, 52, percentage_max_float,acmgt3__sampler__slice23__sampler32_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 661, 56, percentage_max_float,acmgt3__sampler__slice23__sampler33_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 662, 60, percentage_max_float,acmgt3__sampler__slice23__sampler20_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 663, 64, percentage_max_float,acmgt3__sampler__slice23__sampler21_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 664, 68, percentage_max_float,acmgt3__sampler__slice23__sampler22_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 665, 72, percentage_max_float,acmgt3__sampler__slice23__sampler23_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 666, 76, percentage_max_float,acmgt3__sampler__slice23__sampler30_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 667, 80, percentage_max_float,acmgt3__sampler__slice23__sampler31_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 668, 84, percentage_max_float,acmgt3__sampler__slice23__sampler32_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 669, 88, percentage_max_float,acmgt3__sampler__slice23__sampler33_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_sampler__slice45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Sampler_Slice45";
   query->symbol_name = "Sampler_Slice45";
   query->guid = "3946ded6-dff6-461a-a9cd-5291d9dcce51";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x14832C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x14A32C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x14C32C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x14E32C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x15832C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x15A32C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x15C32C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x15E32C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x16820024 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x0A830580 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x14A20900 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x0AA30016 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x14C20024 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x08C30580 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x12E20900 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x08E30016 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x13820024 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x07830580 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x07A30016 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x11C20024 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x05C30580 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x0FE20900 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x05E30016 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030863 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031C8A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44031C06 },
         { .reg = 0x00009888, .val = 0x3803F000 },
         { .reg = 0x00009888, .val = 0x460308E1 },
         { .reg = 0x00009888, .val = 0x4803003F },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__sampler__slice45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__sampler__slice45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__sampler__slice45__avg_gpu_core_frequency__max,acmgt3__sampler__slice45__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__sampler__slice45__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2161, 28, percentage_max_float,acmgt3__sampler__slice45__sampler40_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2162, 32, percentage_max_float,acmgt3__sampler__slice45__sampler41_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2163, 36, percentage_max_float,acmgt3__sampler__slice45__sampler42_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2164, 40, percentage_max_float,acmgt3__sampler__slice45__sampler43_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2165, 44, percentage_max_float,acmgt3__sampler__slice45__sampler50_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2166, 48, percentage_max_float,acmgt3__sampler__slice45__sampler51_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2167, 52, percentage_max_float,acmgt3__sampler__slice45__sampler52_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2168, 56, percentage_max_float,acmgt3__sampler__slice45__sampler53_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2169, 60, percentage_max_float,acmgt3__sampler__slice45__sampler40_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2170, 64, percentage_max_float,acmgt3__sampler__slice45__sampler41_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2171, 68, percentage_max_float,acmgt3__sampler__slice45__sampler42_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2172, 72, percentage_max_float,acmgt3__sampler__slice45__sampler43_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2173, 76, percentage_max_float,acmgt3__sampler__slice45__sampler50_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2174, 80, percentage_max_float,acmgt3__sampler__slice45__sampler51_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2175, 84, percentage_max_float,acmgt3__sampler__slice45__sampler52_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2176, 88, percentage_max_float,acmgt3__sampler__slice45__sampler53_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_sampler__slice67_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Sampler_Slice67";
   query->symbol_name = "Sampler_Slice67";
   query->guid = "6ab037fb-065e-4f01-b24e-5f425077189c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x14832C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x14A32C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x14C32C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x14E32C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x15832C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x15A32C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x15C32C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x15E32C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x16820024 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x0A830580 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x14A20900 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x0AA30016 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x14C20024 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x08C30580 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x12E20900 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x08E30016 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x13820024 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x07830580 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840808 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x07A30016 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40404 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x11C20024 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x05C30580 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40202 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x0FE20900 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x05E30016 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40101 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F0F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F4F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090303 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010404 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020202 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030863 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031C8A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44031C06 },
         { .reg = 0x00009888, .val = 0x3803F000 },
         { .reg = 0x00009888, .val = 0x460308E1 },
         { .reg = 0x00009888, .val = 0x4803003F },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__sampler__slice67__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__sampler__slice67__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__sampler__slice67__avg_gpu_core_frequency__max,acmgt3__sampler__slice67__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__sampler__slice67__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3451, 28, percentage_max_float,acmgt3__sampler__slice67__sampler60_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3452, 32, percentage_max_float,acmgt3__sampler__slice67__sampler61_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3453, 36, percentage_max_float,acmgt3__sampler__slice67__sampler62_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3454, 40, percentage_max_float,acmgt3__sampler__slice67__sampler63_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3455, 44, percentage_max_float,acmgt3__sampler__slice67__sampler70_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3456, 48, percentage_max_float,acmgt3__sampler__slice67__sampler71_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3457, 52, percentage_max_float,acmgt3__sampler__slice67__sampler72_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3458, 56, percentage_max_float,acmgt3__sampler__slice67__sampler73_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3459, 60, percentage_max_float,acmgt3__sampler__slice67__sampler60_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3460, 64, percentage_max_float,acmgt3__sampler__slice67__sampler61_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3461, 68, percentage_max_float,acmgt3__sampler__slice67__sampler62_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3462, 72, percentage_max_float,acmgt3__sampler__slice67__sampler63_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3463, 76, percentage_max_float,acmgt3__sampler__slice67__sampler70_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3464, 80, percentage_max_float,acmgt3__sampler__slice67__sampler71_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3465, 84, percentage_max_float,acmgt3__sampler__slice67__sampler72_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3466, 88, percentage_max_float,acmgt3__sampler__slice67__sampler73_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice01_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice01_1";
   query->symbol_name = "TDL_Slice01_1";
   query->guid = "f0294ed6-827a-44e0-9f79-1ddc22182899";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810030 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10C00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10030 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10C00 },
         { .reg = 0x00009888, .val = 0x14E10CF4 },
         { .reg = 0x00009888, .val = 0x16E10C72 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810030 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10C00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10030 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10C00 },
         { .reg = 0x00009888, .val = 0x11E10CF4 },
         { .reg = 0x00009888, .val = 0x13E10C72 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40F80 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70055 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x0009F00C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03294A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032007 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40031CE7 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice01_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice01_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice01_1__avg_gpu_core_frequency__max,acmgt3__tdl__slice01_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice01_1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3467, 28, percentage_max_float,acmgt3__tdl__slice01_1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3468, 32, percentage_max_float,acmgt3__tdl__slice01_1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3469, 36, percentage_max_float,acmgt3__tdl__slice01_1__non_ps_thread02_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3470, 40, percentage_max_float,acmgt3__tdl__slice01_1__non_ps_thread03_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3471, 44, percentage_max_float,acmgt3__tdl__slice01_1__non_ps_thread10_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3472, 48, percentage_max_float,acmgt3__tdl__slice01_1__non_ps_thread11_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3473, 52, percentage_max_float,acmgt3__tdl__slice01_1__non_ps_thread12_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3474, 56, percentage_max_float,acmgt3__tdl__slice01_1__non_ps_thread13_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3475, 60, percentage_max_float,acmgt3__tdl__slice01_1__thread_header03_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3476, 64, percentage_max_float,acmgt3__tdl__slice01_1__thread_header03_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3477, 68, percentage_max_float,acmgt3__tdl__slice01_1__thread_header03_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3478, 72, percentage_max_float,acmgt3__tdl__slice01_1__thread_header03_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3479, 76, percentage_max_float,acmgt3__tdl__slice01_1__thread_header13_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3480, 80, percentage_max_float,acmgt3__tdl__slice01_1__thread_header13_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3481, 84, percentage_max_float,acmgt3__tdl__slice01_1__thread_header13_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3482, 88, percentage_max_float,acmgt3__tdl__slice01_1__thread_header13_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice01_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "TDL_Slice01_2";
   query->symbol_name = "TDL_Slice01_2";
   query->guid = "14477b8c-ad25-4351-8c67-e6411cb77bab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice01_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice01_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice01_2__avg_gpu_core_frequency__max,acmgt3__tdl__slice01_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice01_2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3483, 28, percentage_max_float,acmgt3__tdl__slice01_2__ps_thread00_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3484, 32, percentage_max_float,acmgt3__tdl__slice01_2__ps_thread01_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3485, 36, percentage_max_float,acmgt3__tdl__slice01_2__ps_thread02_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3486, 40, percentage_max_float,acmgt3__tdl__slice01_2__ps_thread03_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3487, 44, percentage_max_float,acmgt3__tdl__slice01_2__ps_thread10_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3488, 48, percentage_max_float,acmgt3__tdl__slice01_2__ps_thread11_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3489, 52, percentage_max_float,acmgt3__tdl__slice01_2__ps_thread12_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3490, 56, percentage_max_float,acmgt3__tdl__slice01_2__ps_thread13_ready_for_dispatch__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice01_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice01_3";
   query->symbol_name = "TDL_Slice01_3";
   query->guid = "6b48996e-1179-4955-bd28-d5aefeea1196";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x14810CF4 },
         { .reg = 0x00009888, .val = 0x16810C72 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x02875500 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x10A10CF4 },
         { .reg = 0x00009888, .val = 0x12A10C72 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A70055 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0CC10CF4 },
         { .reg = 0x00009888, .val = 0x0EC10C72 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x08E10CB1 },
         { .reg = 0x00009888, .val = 0x0AE10D33 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice01_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice01_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice01_3__avg_gpu_core_frequency__max,acmgt3__tdl__slice01_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice01_3__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3491, 28, percentage_max_float,acmgt3__tdl__slice01_3__thread_header00_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3492, 32, percentage_max_float,acmgt3__tdl__slice01_3__thread_header00_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3493, 36, percentage_max_float,acmgt3__tdl__slice01_3__thread_header00_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3494, 40, percentage_max_float,acmgt3__tdl__slice01_3__thread_header00_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 3495, 44, percentage_max_float,acmgt3__tdl__slice01_3__thread_header00_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3496, 48, percentage_max_float,acmgt3__tdl__slice01_3__thread_header01_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3497, 52, percentage_max_float,acmgt3__tdl__slice01_3__thread_header01_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3498, 56, percentage_max_float,acmgt3__tdl__slice01_3__thread_header01_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3499, 60, percentage_max_float,acmgt3__tdl__slice01_3__thread_header01_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 3500, 64, percentage_max_float,acmgt3__tdl__slice01_3__thread_header01_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3501, 68, percentage_max_float,acmgt3__tdl__slice01_3__thread_header02_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3502, 72, percentage_max_float,acmgt3__tdl__slice01_3__thread_header02_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3503, 76, percentage_max_float,acmgt3__tdl__slice01_3__thread_header02_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3504, 80, percentage_max_float,acmgt3__tdl__slice01_3__thread_header02_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 3505, 84, percentage_max_float,acmgt3__tdl__slice01_3__thread_header02_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 3506, 88, percentage_max_float,acmgt3__tdl__slice01_3__thread_header03_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice01_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice01_4";
   query->symbol_name = "TDL_Slice01_4";
   query->guid = "6403c3b2-e302-4c1a-a604-7817e846ab2c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x15810CF4 },
         { .reg = 0x00009888, .val = 0x17810C72 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x03875500 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x11A10CF4 },
         { .reg = 0x00009888, .val = 0x13A10C72 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A70055 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0DC10CF4 },
         { .reg = 0x00009888, .val = 0x0FC10C72 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x09E10CB1 },
         { .reg = 0x00009888, .val = 0x0BE10D33 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice01_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice01_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice01_4__avg_gpu_core_frequency__max,acmgt3__tdl__slice01_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice01_4__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3507, 28, percentage_max_float,acmgt3__tdl__slice01_4__thread_header10_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3508, 32, percentage_max_float,acmgt3__tdl__slice01_4__thread_header10_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3509, 36, percentage_max_float,acmgt3__tdl__slice01_4__thread_header10_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3510, 40, percentage_max_float,acmgt3__tdl__slice01_4__thread_header10_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 3511, 44, percentage_max_float,acmgt3__tdl__slice01_4__thread_header10_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3512, 48, percentage_max_float,acmgt3__tdl__slice01_4__thread_header11_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3513, 52, percentage_max_float,acmgt3__tdl__slice01_4__thread_header11_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3514, 56, percentage_max_float,acmgt3__tdl__slice01_4__thread_header11_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3515, 60, percentage_max_float,acmgt3__tdl__slice01_4__thread_header11_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 3516, 64, percentage_max_float,acmgt3__tdl__slice01_4__thread_header11_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3517, 68, percentage_max_float,acmgt3__tdl__slice01_4__thread_header12_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3518, 72, percentage_max_float,acmgt3__tdl__slice01_4__thread_header12_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3519, 76, percentage_max_float,acmgt3__tdl__slice01_4__thread_header12_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3520, 80, percentage_max_float,acmgt3__tdl__slice01_4__thread_header12_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 3521, 84, percentage_max_float,acmgt3__tdl__slice01_4__thread_header12_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 3522, 88, percentage_max_float,acmgt3__tdl__slice01_4__thread_header13_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice23_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice23_1";
   query->symbol_name = "TDL_Slice23_1";
   query->guid = "51d2c1bd-7432-411f-9095-ac97d55dc285";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810030 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10C00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10030 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10C00 },
         { .reg = 0x00009888, .val = 0x14E10CF4 },
         { .reg = 0x00009888, .val = 0x16E10C72 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810030 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10C00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10030 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10C00 },
         { .reg = 0x00009888, .val = 0x11E10CF4 },
         { .reg = 0x00009888, .val = 0x13E10C72 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40F80 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70055 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x0009F00C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03294A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032007 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40031CE7 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice23_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice23_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice23_1__avg_gpu_core_frequency__max,acmgt3__tdl__slice23_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice23_1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 694, 28, percentage_max_float,acmgt3__tdl__slice23_1__non_ps_thread20_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 695, 32, percentage_max_float,acmgt3__tdl__slice23_1__non_ps_thread21_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 696, 36, percentage_max_float,acmgt3__tdl__slice23_1__non_ps_thread22_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 697, 40, percentage_max_float,acmgt3__tdl__slice23_1__non_ps_thread23_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 698, 44, percentage_max_float,acmgt3__tdl__slice23_1__non_ps_thread30_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 699, 48, percentage_max_float,acmgt3__tdl__slice23_1__non_ps_thread31_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 700, 52, percentage_max_float,acmgt3__tdl__slice23_1__non_ps_thread32_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 701, 56, percentage_max_float,acmgt3__tdl__slice23_1__non_ps_thread33_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 702, 60, percentage_max_float,acmgt3__tdl__slice23_1__thread_header23_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 703, 64, percentage_max_float,acmgt3__tdl__slice23_1__thread_header23_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 704, 68, percentage_max_float,acmgt3__tdl__slice23_1__thread_header23_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 705, 72, percentage_max_float,acmgt3__tdl__slice23_1__thread_header23_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 706, 76, percentage_max_float,acmgt3__tdl__slice23_1__thread_header33_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 707, 80, percentage_max_float,acmgt3__tdl__slice23_1__thread_header33_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 708, 84, percentage_max_float,acmgt3__tdl__slice23_1__thread_header33_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 709, 88, percentage_max_float,acmgt3__tdl__slice23_1__thread_header33_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice23_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "TDL_Slice23_2";
   query->symbol_name = "TDL_Slice23_2";
   query->guid = "32e32945-471f-4f17-bae1-9d96f9c54f8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice23_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice23_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice23_2__avg_gpu_core_frequency__max,acmgt3__tdl__slice23_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice23_2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 710, 28, percentage_max_float,acmgt3__tdl__slice23_2__ps_thread20_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 711, 32, percentage_max_float,acmgt3__tdl__slice23_2__ps_thread21_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 712, 36, percentage_max_float,acmgt3__tdl__slice23_2__ps_thread22_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 713, 40, percentage_max_float,acmgt3__tdl__slice23_2__ps_thread23_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 714, 44, percentage_max_float,acmgt3__tdl__slice23_2__ps_thread30_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 715, 48, percentage_max_float,acmgt3__tdl__slice23_2__ps_thread31_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 716, 52, percentage_max_float,acmgt3__tdl__slice23_2__ps_thread32_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 717, 56, percentage_max_float,acmgt3__tdl__slice23_2__ps_thread33_ready_for_dispatch__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice23_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice23_3";
   query->symbol_name = "TDL_Slice23_3";
   query->guid = "34804b9e-0d2b-4e97-ba78-5c2069bc9df9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x14810CF4 },
         { .reg = 0x00009888, .val = 0x16810C72 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x02875500 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x10A10CF4 },
         { .reg = 0x00009888, .val = 0x12A10C72 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A70055 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0CC10CF4 },
         { .reg = 0x00009888, .val = 0x0EC10C72 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x08E10CB1 },
         { .reg = 0x00009888, .val = 0x0AE10D33 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice23_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice23_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice23_3__avg_gpu_core_frequency__max,acmgt3__tdl__slice23_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice23_3__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 718, 28, percentage_max_float,acmgt3__tdl__slice23_3__thread_header20_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 719, 32, percentage_max_float,acmgt3__tdl__slice23_3__thread_header20_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 720, 36, percentage_max_float,acmgt3__tdl__slice23_3__thread_header20_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 721, 40, percentage_max_float,acmgt3__tdl__slice23_3__thread_header20_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 722, 44, percentage_max_float,acmgt3__tdl__slice23_3__thread_header20_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 723, 48, percentage_max_float,acmgt3__tdl__slice23_3__thread_header21_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 724, 52, percentage_max_float,acmgt3__tdl__slice23_3__thread_header21_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 725, 56, percentage_max_float,acmgt3__tdl__slice23_3__thread_header21_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 726, 60, percentage_max_float,acmgt3__tdl__slice23_3__thread_header21_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 727, 64, percentage_max_float,acmgt3__tdl__slice23_3__thread_header21_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 728, 68, percentage_max_float,acmgt3__tdl__slice23_3__thread_header22_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 729, 72, percentage_max_float,acmgt3__tdl__slice23_3__thread_header22_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 730, 76, percentage_max_float,acmgt3__tdl__slice23_3__thread_header22_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 731, 80, percentage_max_float,acmgt3__tdl__slice23_3__thread_header22_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 732, 84, percentage_max_float,acmgt3__tdl__slice23_3__thread_header22_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 733, 88, percentage_max_float,acmgt3__tdl__slice23_3__thread_header23_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice23_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice23_4";
   query->symbol_name = "TDL_Slice23_4";
   query->guid = "97ca0de0-9d3b-4bdd-94f7-662113dfc905";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x15810CF4 },
         { .reg = 0x00009888, .val = 0x17810C72 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x03875500 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x11A10CF4 },
         { .reg = 0x00009888, .val = 0x13A10C72 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A70055 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0DC10CF4 },
         { .reg = 0x00009888, .val = 0x0FC10C72 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x09E10CB1 },
         { .reg = 0x00009888, .val = 0x0BE10D33 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice23_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice23_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice23_4__avg_gpu_core_frequency__max,acmgt3__tdl__slice23_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice23_4__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 734, 28, percentage_max_float,acmgt3__tdl__slice23_4__thread_header30_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 735, 32, percentage_max_float,acmgt3__tdl__slice23_4__thread_header30_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 736, 36, percentage_max_float,acmgt3__tdl__slice23_4__thread_header30_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 737, 40, percentage_max_float,acmgt3__tdl__slice23_4__thread_header30_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 738, 44, percentage_max_float,acmgt3__tdl__slice23_4__thread_header30_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 739, 48, percentage_max_float,acmgt3__tdl__slice23_4__thread_header31_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 740, 52, percentage_max_float,acmgt3__tdl__slice23_4__thread_header31_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 741, 56, percentage_max_float,acmgt3__tdl__slice23_4__thread_header31_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 742, 60, percentage_max_float,acmgt3__tdl__slice23_4__thread_header31_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 743, 64, percentage_max_float,acmgt3__tdl__slice23_4__thread_header31_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 744, 68, percentage_max_float,acmgt3__tdl__slice23_4__thread_header32_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 745, 72, percentage_max_float,acmgt3__tdl__slice23_4__thread_header32_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 746, 76, percentage_max_float,acmgt3__tdl__slice23_4__thread_header32_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 747, 80, percentage_max_float,acmgt3__tdl__slice23_4__thread_header32_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 748, 84, percentage_max_float,acmgt3__tdl__slice23_4__thread_header32_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 749, 88, percentage_max_float,acmgt3__tdl__slice23_4__thread_header33_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice45_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice45_1";
   query->symbol_name = "TDL_Slice45_1";
   query->guid = "f4ba49b6-37a1-4848-88d6-3c63cb8e1c12";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810030 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10C00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10030 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10C00 },
         { .reg = 0x00009888, .val = 0x14E10CF4 },
         { .reg = 0x00009888, .val = 0x16E10C72 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810030 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10C00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10030 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10C00 },
         { .reg = 0x00009888, .val = 0x11E10CF4 },
         { .reg = 0x00009888, .val = 0x13E10C72 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40F80 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70055 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x0009F00C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03294A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032007 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40031CE7 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice45_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice45_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice45_1__avg_gpu_core_frequency__max,acmgt3__tdl__slice45_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice45_1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2201, 28, percentage_max_float,acmgt3__tdl__slice45_1__non_ps_thread40_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2202, 32, percentage_max_float,acmgt3__tdl__slice45_1__non_ps_thread41_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2203, 36, percentage_max_float,acmgt3__tdl__slice45_1__non_ps_thread42_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2204, 40, percentage_max_float,acmgt3__tdl__slice45_1__non_ps_thread43_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2205, 44, percentage_max_float,acmgt3__tdl__slice45_1__non_ps_thread50_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2206, 48, percentage_max_float,acmgt3__tdl__slice45_1__non_ps_thread51_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2207, 52, percentage_max_float,acmgt3__tdl__slice45_1__non_ps_thread52_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2208, 56, percentage_max_float,acmgt3__tdl__slice45_1__non_ps_thread53_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2209, 60, percentage_max_float,acmgt3__tdl__slice45_1__thread_header43_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2210, 64, percentage_max_float,acmgt3__tdl__slice45_1__thread_header43_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2211, 68, percentage_max_float,acmgt3__tdl__slice45_1__thread_header43_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2212, 72, percentage_max_float,acmgt3__tdl__slice45_1__thread_header43_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2213, 76, percentage_max_float,acmgt3__tdl__slice45_1__thread_header53_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2214, 80, percentage_max_float,acmgt3__tdl__slice45_1__thread_header53_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2215, 84, percentage_max_float,acmgt3__tdl__slice45_1__thread_header53_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2216, 88, percentage_max_float,acmgt3__tdl__slice45_1__thread_header53_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice45_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "TDL_Slice45_2";
   query->symbol_name = "TDL_Slice45_2";
   query->guid = "a6969313-fe82-4f0b-9499-b90c98e9ede7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice45_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice45_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice45_2__avg_gpu_core_frequency__max,acmgt3__tdl__slice45_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice45_2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2217, 28, percentage_max_float,acmgt3__tdl__slice45_2__ps_thread40_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2218, 32, percentage_max_float,acmgt3__tdl__slice45_2__ps_thread41_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2219, 36, percentage_max_float,acmgt3__tdl__slice45_2__ps_thread42_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2220, 40, percentage_max_float,acmgt3__tdl__slice45_2__ps_thread43_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2221, 44, percentage_max_float,acmgt3__tdl__slice45_2__ps_thread50_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2222, 48, percentage_max_float,acmgt3__tdl__slice45_2__ps_thread51_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2223, 52, percentage_max_float,acmgt3__tdl__slice45_2__ps_thread52_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2224, 56, percentage_max_float,acmgt3__tdl__slice45_2__ps_thread53_ready_for_dispatch__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice45_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice45_3";
   query->symbol_name = "TDL_Slice45_3";
   query->guid = "8dd20826-657e-43b7-9bba-a48ef4db2d14";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x14810CF4 },
         { .reg = 0x00009888, .val = 0x16810C72 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x02875500 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x10A10CF4 },
         { .reg = 0x00009888, .val = 0x12A10C72 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A70055 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0CC10CF4 },
         { .reg = 0x00009888, .val = 0x0EC10C72 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x08E10CB1 },
         { .reg = 0x00009888, .val = 0x0AE10D33 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice45_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice45_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice45_3__avg_gpu_core_frequency__max,acmgt3__tdl__slice45_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice45_3__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2225, 28, percentage_max_float,acmgt3__tdl__slice45_3__thread_header40_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2226, 32, percentage_max_float,acmgt3__tdl__slice45_3__thread_header40_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2227, 36, percentage_max_float,acmgt3__tdl__slice45_3__thread_header40_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2228, 40, percentage_max_float,acmgt3__tdl__slice45_3__thread_header40_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 2229, 44, percentage_max_float,acmgt3__tdl__slice45_3__thread_header40_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2230, 48, percentage_max_float,acmgt3__tdl__slice45_3__thread_header41_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2231, 52, percentage_max_float,acmgt3__tdl__slice45_3__thread_header41_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2232, 56, percentage_max_float,acmgt3__tdl__slice45_3__thread_header41_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2233, 60, percentage_max_float,acmgt3__tdl__slice45_3__thread_header41_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 2234, 64, percentage_max_float,acmgt3__tdl__slice45_3__thread_header41_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2235, 68, percentage_max_float,acmgt3__tdl__slice45_3__thread_header42_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2236, 72, percentage_max_float,acmgt3__tdl__slice45_3__thread_header42_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2237, 76, percentage_max_float,acmgt3__tdl__slice45_3__thread_header42_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2238, 80, percentage_max_float,acmgt3__tdl__slice45_3__thread_header42_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 2239, 84, percentage_max_float,acmgt3__tdl__slice45_3__thread_header42_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 2240, 88, percentage_max_float,acmgt3__tdl__slice45_3__thread_header43_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice45_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice45_4";
   query->symbol_name = "TDL_Slice45_4";
   query->guid = "e479a02f-fc83-438f-818d-3e11e769fbae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x15810CF4 },
         { .reg = 0x00009888, .val = 0x17810C72 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x03875500 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x11A10CF4 },
         { .reg = 0x00009888, .val = 0x13A10C72 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A70055 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0DC10CF4 },
         { .reg = 0x00009888, .val = 0x0FC10C72 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x09E10CB1 },
         { .reg = 0x00009888, .val = 0x0BE10D33 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice45_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice45_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice45_4__avg_gpu_core_frequency__max,acmgt3__tdl__slice45_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice45_4__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2241, 28, percentage_max_float,acmgt3__tdl__slice45_4__thread_header50_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2242, 32, percentage_max_float,acmgt3__tdl__slice45_4__thread_header50_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2243, 36, percentage_max_float,acmgt3__tdl__slice45_4__thread_header50_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2244, 40, percentage_max_float,acmgt3__tdl__slice45_4__thread_header50_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 2245, 44, percentage_max_float,acmgt3__tdl__slice45_4__thread_header50_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2246, 48, percentage_max_float,acmgt3__tdl__slice45_4__thread_header51_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2247, 52, percentage_max_float,acmgt3__tdl__slice45_4__thread_header51_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2248, 56, percentage_max_float,acmgt3__tdl__slice45_4__thread_header51_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2249, 60, percentage_max_float,acmgt3__tdl__slice45_4__thread_header51_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 2250, 64, percentage_max_float,acmgt3__tdl__slice45_4__thread_header51_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2251, 68, percentage_max_float,acmgt3__tdl__slice45_4__thread_header52_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2252, 72, percentage_max_float,acmgt3__tdl__slice45_4__thread_header52_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2253, 76, percentage_max_float,acmgt3__tdl__slice45_4__thread_header52_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2254, 80, percentage_max_float,acmgt3__tdl__slice45_4__thread_header52_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 2255, 84, percentage_max_float,acmgt3__tdl__slice45_4__thread_header52_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 2256, 88, percentage_max_float,acmgt3__tdl__slice45_4__thread_header53_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice67_1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice67_1";
   query->symbol_name = "TDL_Slice67_1";
   query->guid = "deb1e6dd-bddd-42a4-87f5-c4bd8438a884";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810030 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10C00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10030 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10C00 },
         { .reg = 0x00009888, .val = 0x14E10CF4 },
         { .reg = 0x00009888, .val = 0x16E10C72 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810030 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10C00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10030 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10C00 },
         { .reg = 0x00009888, .val = 0x11E10CF4 },
         { .reg = 0x00009888, .val = 0x13E10C72 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40F80 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70055 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x0009F00C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03294A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032007 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40031CE7 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice67_1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice67_1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice67_1__avg_gpu_core_frequency__max,acmgt3__tdl__slice67_1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice67_1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3523, 28, percentage_max_float,acmgt3__tdl__slice67_1__non_ps_thread60_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3524, 32, percentage_max_float,acmgt3__tdl__slice67_1__non_ps_thread61_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3525, 36, percentage_max_float,acmgt3__tdl__slice67_1__non_ps_thread62_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3526, 40, percentage_max_float,acmgt3__tdl__slice67_1__non_ps_thread63_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3527, 44, percentage_max_float,acmgt3__tdl__slice67_1__non_ps_thread70_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3528, 48, percentage_max_float,acmgt3__tdl__slice67_1__non_ps_thread71_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3529, 52, percentage_max_float,acmgt3__tdl__slice67_1__non_ps_thread72_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3530, 56, percentage_max_float,acmgt3__tdl__slice67_1__non_ps_thread73_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3531, 60, percentage_max_float,acmgt3__tdl__slice67_1__thread_header63_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3532, 64, percentage_max_float,acmgt3__tdl__slice67_1__thread_header63_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3533, 68, percentage_max_float,acmgt3__tdl__slice67_1__thread_header63_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3534, 72, percentage_max_float,acmgt3__tdl__slice67_1__thread_header63_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3535, 76, percentage_max_float,acmgt3__tdl__slice67_1__thread_header73_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3536, 80, percentage_max_float,acmgt3__tdl__slice67_1__thread_header73_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3537, 84, percentage_max_float,acmgt3__tdl__slice67_1__thread_header73_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3538, 88, percentage_max_float,acmgt3__tdl__slice67_1__thread_header73_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice67_2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "TDL_Slice67_2";
   query->symbol_name = "TDL_Slice67_2";
   query->guid = "0a6abc27-343e-4118-b17e-5c5121611b08";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice67_2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice67_2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice67_2__avg_gpu_core_frequency__max,acmgt3__tdl__slice67_2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice67_2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3539, 28, percentage_max_float,acmgt3__tdl__slice67_2__ps_thread60_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3540, 32, percentage_max_float,acmgt3__tdl__slice67_2__ps_thread61_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3541, 36, percentage_max_float,acmgt3__tdl__slice67_2__ps_thread62_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3542, 40, percentage_max_float,acmgt3__tdl__slice67_2__ps_thread63_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3543, 44, percentage_max_float,acmgt3__tdl__slice67_2__ps_thread70_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3544, 48, percentage_max_float,acmgt3__tdl__slice67_2__ps_thread71_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3545, 52, percentage_max_float,acmgt3__tdl__slice67_2__ps_thread72_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3546, 56, percentage_max_float,acmgt3__tdl__slice67_2__ps_thread73_ready_for_dispatch__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice67_3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice67_3";
   query->symbol_name = "TDL_Slice67_3";
   query->guid = "67abb260-55fb-4c66-8469-db2f8700884a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2A81001C },
         { .reg = 0x00009888, .val = 0x2AA1001C },
         { .reg = 0x00009888, .val = 0x2AC1001C },
         { .reg = 0x00009888, .val = 0x2AE1001C },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x14810CF4 },
         { .reg = 0x00009888, .val = 0x16810C72 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x02875500 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x10A10CF4 },
         { .reg = 0x00009888, .val = 0x12A10C72 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A70055 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0CC10CF4 },
         { .reg = 0x00009888, .val = 0x0EC10C72 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x08E10CB1 },
         { .reg = 0x00009888, .val = 0x0AE10D33 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice67_3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice67_3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice67_3__avg_gpu_core_frequency__max,acmgt3__tdl__slice67_3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice67_3__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3547, 28, percentage_max_float,acmgt3__tdl__slice67_3__thread_header60_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3548, 32, percentage_max_float,acmgt3__tdl__slice67_3__thread_header60_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3549, 36, percentage_max_float,acmgt3__tdl__slice67_3__thread_header60_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3550, 40, percentage_max_float,acmgt3__tdl__slice67_3__thread_header60_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 3551, 44, percentage_max_float,acmgt3__tdl__slice67_3__thread_header60_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3552, 48, percentage_max_float,acmgt3__tdl__slice67_3__thread_header61_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3553, 52, percentage_max_float,acmgt3__tdl__slice67_3__thread_header61_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3554, 56, percentage_max_float,acmgt3__tdl__slice67_3__thread_header61_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3555, 60, percentage_max_float,acmgt3__tdl__slice67_3__thread_header61_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 3556, 64, percentage_max_float,acmgt3__tdl__slice67_3__thread_header61_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3557, 68, percentage_max_float,acmgt3__tdl__slice67_3__thread_header62_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3558, 72, percentage_max_float,acmgt3__tdl__slice67_3__thread_header62_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3559, 76, percentage_max_float,acmgt3__tdl__slice67_3__thread_header62_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3560, 80, percentage_max_float,acmgt3__tdl__slice67_3__thread_header62_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 3561, 84, percentage_max_float,acmgt3__tdl__slice67_3__thread_header62_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 3562, 88, percentage_max_float,acmgt3__tdl__slice67_3__thread_header63_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_tdl__slice67_4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "TDL_Slice67_4";
   query->symbol_name = "TDL_Slice67_4";
   query->guid = "7c064e0d-b3ee-4159-9361-8d1da3158d39";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2B81001C },
         { .reg = 0x00009888, .val = 0x2BA1001C },
         { .reg = 0x00009888, .val = 0x2BC1001C },
         { .reg = 0x00009888, .val = 0x2BE1001C },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x15810CF4 },
         { .reg = 0x00009888, .val = 0x17810C72 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x03875500 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x11A10CF4 },
         { .reg = 0x00009888, .val = 0x13A10C72 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A70055 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0DC10CF4 },
         { .reg = 0x00009888, .val = 0x0FC10C72 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x09E10CB1 },
         { .reg = 0x00009888, .val = 0x0BE10D33 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00078000 },
         { .reg = 0x0000D944, .val = 0x00000FFF },
         { .reg = 0x0000D948, .val = 0x00007800 },
         { .reg = 0x0000D94C, .val = 0x0000F0FF },
         { .reg = 0x0000D950, .val = 0x00000780 },
         { .reg = 0x0000D954, .val = 0x0000FF0F },
         { .reg = 0x0000D958, .val = 0x00000078 },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__tdl__slice67_4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__tdl__slice67_4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__tdl__slice67_4__avg_gpu_core_frequency__max,acmgt3__tdl__slice67_4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 540, 24, percentage_max_float,acmgt3__tdl__slice67_4__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3563, 28, percentage_max_float,acmgt3__tdl__slice67_4__thread_header70_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3564, 32, percentage_max_float,acmgt3__tdl__slice67_4__thread_header70_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3565, 36, percentage_max_float,acmgt3__tdl__slice67_4__thread_header70_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3566, 40, percentage_max_float,acmgt3__tdl__slice67_4__thread_header70_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 3567, 44, percentage_max_float,acmgt3__tdl__slice67_4__thread_header70_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3568, 48, percentage_max_float,acmgt3__tdl__slice67_4__thread_header71_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3569, 52, percentage_max_float,acmgt3__tdl__slice67_4__thread_header71_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3570, 56, percentage_max_float,acmgt3__tdl__slice67_4__thread_header71_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3571, 60, percentage_max_float,acmgt3__tdl__slice67_4__thread_header71_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 3572, 64, percentage_max_float,acmgt3__tdl__slice67_4__thread_header71_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3573, 68, percentage_max_float,acmgt3__tdl__slice67_4__thread_header72_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3574, 72, percentage_max_float,acmgt3__tdl__slice67_4__thread_header72_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3575, 76, percentage_max_float,acmgt3__tdl__slice67_4__thread_header72_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3576, 80, percentage_max_float,acmgt3__tdl__slice67_4__thread_header72_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 3577, 84, percentage_max_float,acmgt3__tdl__slice67_4__thread_header72_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 3578, 88, percentage_max_float,acmgt3__tdl__slice67_4__thread_header73_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_compute_overview_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 26);

   query->name = "ComputeOverview";
   query->symbol_name = "ComputeOverview";
   query->guid = "5ae9db29-303b-4e74-8dc8-b9f2eb31aaa1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x280A0000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x290A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x280A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x290A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x280A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x290A0000 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B6000 },
         { .reg = 0x00009888, .val = 0x0B0B1005 },
         { .reg = 0x00009888, .val = 0x092B6005 },
         { .reg = 0x00009888, .val = 0x0B2B1000 },
         { .reg = 0x00009888, .val = 0x094B6000 },
         { .reg = 0x00009888, .val = 0x0B4B1000 },
         { .reg = 0x00009888, .val = 0x096B6000 },
         { .reg = 0x00009888, .val = 0x0B6B1000 },
         { .reg = 0x00009888, .val = 0x090C6000 },
         { .reg = 0x00009888, .val = 0x0B0C1140 },
         { .reg = 0x00009888, .val = 0x092C6140 },
         { .reg = 0x00009888, .val = 0x0B2C1000 },
         { .reg = 0x00009888, .val = 0x094C6000 },
         { .reg = 0x00009888, .val = 0x0B4C1000 },
         { .reg = 0x00009888, .val = 0x096C6000 },
         { .reg = 0x00009888, .val = 0x0B6C1000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x112B000D },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x0F4B000D },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x0D6B000D },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x130C0340 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x112C0340 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x0F4C0340 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x0D6C0340 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26080001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B6000 },
         { .reg = 0x00009888, .val = 0x0B0B1005 },
         { .reg = 0x00009888, .val = 0x092B6005 },
         { .reg = 0x00009888, .val = 0x0B2B1000 },
         { .reg = 0x00009888, .val = 0x094B6000 },
         { .reg = 0x00009888, .val = 0x0B4B1000 },
         { .reg = 0x00009888, .val = 0x096B6000 },
         { .reg = 0x00009888, .val = 0x0B6B1000 },
         { .reg = 0x00009888, .val = 0x090C6000 },
         { .reg = 0x00009888, .val = 0x0B0C1140 },
         { .reg = 0x00009888, .val = 0x092C6140 },
         { .reg = 0x00009888, .val = 0x0B2C1000 },
         { .reg = 0x00009888, .val = 0x094C6000 },
         { .reg = 0x00009888, .val = 0x0B4C1000 },
         { .reg = 0x00009888, .val = 0x096C6000 },
         { .reg = 0x00009888, .val = 0x0B6C1000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x112B000D },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x0F4B000D },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x0D6B000D },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x130C0340 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x112C0340 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x0F4C0340 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x0D6C0340 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B6000 },
         { .reg = 0x00009888, .val = 0x0B0B1005 },
         { .reg = 0x00009888, .val = 0x092B6005 },
         { .reg = 0x00009888, .val = 0x0B2B1000 },
         { .reg = 0x00009888, .val = 0x094B6000 },
         { .reg = 0x00009888, .val = 0x0B4B1000 },
         { .reg = 0x00009888, .val = 0x096B6000 },
         { .reg = 0x00009888, .val = 0x0B6B1000 },
         { .reg = 0x00009888, .val = 0x090C6000 },
         { .reg = 0x00009888, .val = 0x0B0C1140 },
         { .reg = 0x00009888, .val = 0x092C6140 },
         { .reg = 0x00009888, .val = 0x0B2C1000 },
         { .reg = 0x00009888, .val = 0x094C6000 },
         { .reg = 0x00009888, .val = 0x0B4C1000 },
         { .reg = 0x00009888, .val = 0x096C6000 },
         { .reg = 0x00009888, .val = 0x0B6C1000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x112B000D },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x0F4B000D },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x0D6B000D },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x130C0340 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x112C0340 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x0F4C0340 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x0D6C0340 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26080001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B6000 },
         { .reg = 0x00009888, .val = 0x0B0B1005 },
         { .reg = 0x00009888, .val = 0x092B6005 },
         { .reg = 0x00009888, .val = 0x0B2B1000 },
         { .reg = 0x00009888, .val = 0x094B6000 },
         { .reg = 0x00009888, .val = 0x0B4B1000 },
         { .reg = 0x00009888, .val = 0x096B6000 },
         { .reg = 0x00009888, .val = 0x0B6B1000 },
         { .reg = 0x00009888, .val = 0x090C6000 },
         { .reg = 0x00009888, .val = 0x0B0C1140 },
         { .reg = 0x00009888, .val = 0x092C6140 },
         { .reg = 0x00009888, .val = 0x0B2C1000 },
         { .reg = 0x00009888, .val = 0x094C6000 },
         { .reg = 0x00009888, .val = 0x0B4C1000 },
         { .reg = 0x00009888, .val = 0x096C6000 },
         { .reg = 0x00009888, .val = 0x0B6C1000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0032 },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0032 },
         { .reg = 0x00009888, .val = 0x112B000D },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0032 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x0F4B000D },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0032 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x0D6B000D },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x130C0340 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0032 },
         { .reg = 0x00009888, .val = 0x112C0340 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0032 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x0F4C0340 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0032 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x0D6C0340 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0A0 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20101000 },
         { .reg = 0x00009888, .val = 0x26100001 },
         { .reg = 0x00009888, .val = 0x28100001 },
         { .reg = 0x00009888, .val = 0x2A101C2A },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18081000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080020 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20081C2A },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A1000 },
         { .reg = 0x00009888, .val = 0x190A1000 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0020 },
         { .reg = 0x00009888, .val = 0x210A0020 },
         { .reg = 0x00009888, .val = 0x220A0228 },
         { .reg = 0x00009888, .val = 0x230A0228 },
         { .reg = 0x00009888, .val = 0x240A0087 },
         { .reg = 0x00009888, .val = 0x250A0087 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26080001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
         { .reg = 0x0000E658, .val = 0x00009001 },
         { .reg = 0x0000E758, .val = 0x02001002 },
         { .reg = 0x0000E45C, .val = 0x0000A003 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__compute_overview__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__compute_overview__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__compute_overview__avg_gpu_core_frequency__max,acmgt3__compute_overview__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 760, 24, acmgt3__compute_overview__l3_byte_read__max,acmgt3__compute_overview__l3_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 761, 32, acmgt3__compute_overview__l3_byte_write__max,acmgt3__compute_overview__l3_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt3__compute_overview__gpu_memory_byte_read__max,acmgt3__compute_overview__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt3__compute_overview__gpu_memory_byte_write__max,acmgt3__compute_overview__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt3__compute_overview__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt3__compute_overview__xve_stall__read);

      intel_perf_query_add_counter_uint64(query, 766, 64, acmgt3__compute_overview__xve_busy__max,acmgt3__compute_overview__xve_busy__read);

      intel_perf_query_add_counter_float(query, 767, 72, percentage_max_float,acmgt3__compute_overview__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 768, 80, NULL,acmgt3__compute_overview__xve_compute_thread_count__read);

      intel_perf_query_add_counter_uint64(query, 769, 88, NULL,acmgt3__compute_overview__xve_atomic_access_count__read);

      intel_perf_query_add_counter_uint64(query, 770, 96, NULL,acmgt3__compute_overview__xve_barrier_message_count__read);

      intel_perf_query_add_counter_uint64(query, 771, 104, acmgt3__compute_overview__xve_inst_executed_alu0_all__max,acmgt3__compute_overview__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 772, 112, acmgt3__compute_overview__xve_inst_executed_alu1_all__max,acmgt3__compute_overview__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 773, 120, acmgt3__compute_overview__xve_inst_executed_xmx_all__max,acmgt3__compute_overview__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 774, 128, acmgt3__compute_overview__xve_inst_executed_send_all__max,acmgt3__compute_overview__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 775, 136, acmgt3__compute_overview__xve_inst_executed_control_all__max,acmgt3__compute_overview__xve_inst_executed_control_all__read);

      intel_perf_query_add_counter_float(query, 776, 144, percentage_max_float,acmgt3__compute_overview__xve_pipe_alu0_and_alu1_active__read);

      intel_perf_query_add_counter_float(query, 777, 148, percentage_max_float,acmgt3__compute_overview__xve_pipe_alu0_and_xmx_active__read);

      intel_perf_query_add_counter_float(query, 778, 152, percentage_max_float,acmgt3__compute_overview__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 779, 156, percentage_max_float,acmgt3__compute_overview__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 780, 160, percentage_max_float,acmgt3__compute_overview__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 781, 164, percentage_max_float,acmgt3__compute_overview__xve_inst_executed_control_all_utilization__read);

      intel_perf_query_add_counter_float(query, 782, 168, percentage_max_float,acmgt3__compute_overview__xve_inst_executed_xmx_all_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l1_profile_reads__xe_core0_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1ProfileReads";
   query->symbol_name = "L1ProfileReads_XeCore0";
   query->guid = "16047ddf-5ee1-4948-81dc-edbe26576ac1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16870253 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870004 },
         { .reg = 0x00009888, .val = 0x0E870140 },
         { .reg = 0x00009888, .val = 0x108700C4 },
         { .reg = 0x00009888, .val = 0x12870042 },
         { .reg = 0x00009888, .val = 0x148703C0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890387 },
         { .reg = 0x00009888, .val = 0x08890248 },
         { .reg = 0x00009888, .val = 0x0A8902CA },
         { .reg = 0x00009888, .val = 0x0C89034C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17870253 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870004 },
         { .reg = 0x00009888, .val = 0x0F870140 },
         { .reg = 0x00009888, .val = 0x118700C4 },
         { .reg = 0x00009888, .val = 0x13870042 },
         { .reg = 0x00009888, .val = 0x158703C0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890387 },
         { .reg = 0x00009888, .val = 0x09890248 },
         { .reg = 0x00009888, .val = 0x0B8902CA },
         { .reg = 0x00009888, .val = 0x0D89034C },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870253 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870004 },
         { .reg = 0x00009888, .val = 0x0E870140 },
         { .reg = 0x00009888, .val = 0x108700C4 },
         { .reg = 0x00009888, .val = 0x12870042 },
         { .reg = 0x00009888, .val = 0x148703C0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890387 },
         { .reg = 0x00009888, .val = 0x08890248 },
         { .reg = 0x00009888, .val = 0x0A8902CA },
         { .reg = 0x00009888, .val = 0x0C89034C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870253 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870004 },
         { .reg = 0x00009888, .val = 0x0F870140 },
         { .reg = 0x00009888, .val = 0x118700C4 },
         { .reg = 0x00009888, .val = 0x13870042 },
         { .reg = 0x00009888, .val = 0x158703C0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890387 },
         { .reg = 0x00009888, .val = 0x09890248 },
         { .reg = 0x00009888, .val = 0x0B8902CA },
         { .reg = 0x00009888, .val = 0x0D89034C },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870253 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870004 },
         { .reg = 0x00009888, .val = 0x0E870140 },
         { .reg = 0x00009888, .val = 0x108700C4 },
         { .reg = 0x00009888, .val = 0x12870042 },
         { .reg = 0x00009888, .val = 0x148703C0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890387 },
         { .reg = 0x00009888, .val = 0x08890248 },
         { .reg = 0x00009888, .val = 0x0A8902CA },
         { .reg = 0x00009888, .val = 0x0C89034C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870253 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870004 },
         { .reg = 0x00009888, .val = 0x0F870140 },
         { .reg = 0x00009888, .val = 0x118700C4 },
         { .reg = 0x00009888, .val = 0x13870042 },
         { .reg = 0x00009888, .val = 0x158703C0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890387 },
         { .reg = 0x00009888, .val = 0x09890248 },
         { .reg = 0x00009888, .val = 0x0B8902CA },
         { .reg = 0x00009888, .val = 0x0D89034C },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16870253 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870004 },
         { .reg = 0x00009888, .val = 0x0E870140 },
         { .reg = 0x00009888, .val = 0x108700C4 },
         { .reg = 0x00009888, .val = 0x12870042 },
         { .reg = 0x00009888, .val = 0x148703C0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890387 },
         { .reg = 0x00009888, .val = 0x08890248 },
         { .reg = 0x00009888, .val = 0x0A8902CA },
         { .reg = 0x00009888, .val = 0x0C89034C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17870253 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870004 },
         { .reg = 0x00009888, .val = 0x0F870140 },
         { .reg = 0x00009888, .val = 0x118700C4 },
         { .reg = 0x00009888, .val = 0x13870042 },
         { .reg = 0x00009888, .val = 0x158703C0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890387 },
         { .reg = 0x00009888, .val = 0x09890248 },
         { .reg = 0x00009888, .val = 0x0B8902CA },
         { .reg = 0x00009888, .val = 0x0D89034C },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26080000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FE7F },
         { .reg = 0x0000DC00, .val = 0x0000001A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000032 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF9 },
         { .reg = 0x0000DC10, .val = 0x00000052 },
         { .reg = 0x0000DC14, .val = 0x0000FFF5 },
         { .reg = 0x0000DC18, .val = 0x00000092 },
         { .reg = 0x0000DC1C, .val = 0x0000FFED },
         { .reg = 0x0000DC20, .val = 0x00000112 },
         { .reg = 0x0000DC24, .val = 0x0000FFDD },
         { .reg = 0x0000DC28, .val = 0x00000212 },
         { .reg = 0x0000DC2C, .val = 0x0000FFBD },
         { .reg = 0x0000DC30, .val = 0x00000412 },
         { .reg = 0x0000DC34, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l1_profile_reads__xe_core0__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l1_profile_reads__xe_core0__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l1_profile_reads__xe_core0__avg_gpu_core_frequency__max,acmgt3__l1_profile_reads__xe_core0__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 783, 24, acmgt3__l1_profile_reads__xe_core0__load_store_cache_byte_read__max,acmgt3__l1_profile_reads__xe_core0__load_store_cache_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 784, 32, acmgt3__l1_profile_reads__xe_core0__slm_byte_read__max,acmgt3__l1_profile_reads__xe_core0__slm_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_read__max,acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_write__max,acmgt3__l1_profile_reads__xe_core0__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt3__l1_profile_reads__xe_core0__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt3__l1_profile_reads__xe_core0__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 64, percentage_max_float,acmgt3__l1_profile_reads__xe_core0__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt3__l1_profile_reads__xe_core0__xve_busy__max,acmgt3__l1_profile_reads__xe_core0__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l1_profile_reads__xe_core3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1ProfileReads";
   query->symbol_name = "L1ProfileReads_XeCore3";
   query->guid = "224881aa-faa7-4d2d-8161-50dbb10026e8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16E70253 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70004 },
         { .reg = 0x00009888, .val = 0x0EE70140 },
         { .reg = 0x00009888, .val = 0x10E700C4 },
         { .reg = 0x00009888, .val = 0x12E70042 },
         { .reg = 0x00009888, .val = 0x14E703C0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90387 },
         { .reg = 0x00009888, .val = 0x08E90248 },
         { .reg = 0x00009888, .val = 0x0AE902CA },
         { .reg = 0x00009888, .val = 0x0CE9034C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17E70253 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70004 },
         { .reg = 0x00009888, .val = 0x0FE70140 },
         { .reg = 0x00009888, .val = 0x11E700C4 },
         { .reg = 0x00009888, .val = 0x13E70042 },
         { .reg = 0x00009888, .val = 0x15E703C0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90387 },
         { .reg = 0x00009888, .val = 0x09E90248 },
         { .reg = 0x00009888, .val = 0x0BE902CA },
         { .reg = 0x00009888, .val = 0x0DE9034C },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E70253 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70004 },
         { .reg = 0x00009888, .val = 0x0EE70140 },
         { .reg = 0x00009888, .val = 0x10E700C4 },
         { .reg = 0x00009888, .val = 0x12E70042 },
         { .reg = 0x00009888, .val = 0x14E703C0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90387 },
         { .reg = 0x00009888, .val = 0x08E90248 },
         { .reg = 0x00009888, .val = 0x0AE902CA },
         { .reg = 0x00009888, .val = 0x0CE9034C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E70253 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70004 },
         { .reg = 0x00009888, .val = 0x0FE70140 },
         { .reg = 0x00009888, .val = 0x11E700C4 },
         { .reg = 0x00009888, .val = 0x13E70042 },
         { .reg = 0x00009888, .val = 0x15E703C0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90387 },
         { .reg = 0x00009888, .val = 0x09E90248 },
         { .reg = 0x00009888, .val = 0x0BE902CA },
         { .reg = 0x00009888, .val = 0x0DE9034C },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16E70253 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70004 },
         { .reg = 0x00009888, .val = 0x0EE70140 },
         { .reg = 0x00009888, .val = 0x10E700C4 },
         { .reg = 0x00009888, .val = 0x12E70042 },
         { .reg = 0x00009888, .val = 0x14E703C0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90387 },
         { .reg = 0x00009888, .val = 0x08E90248 },
         { .reg = 0x00009888, .val = 0x0AE902CA },
         { .reg = 0x00009888, .val = 0x0CE9034C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17E70253 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70004 },
         { .reg = 0x00009888, .val = 0x0FE70140 },
         { .reg = 0x00009888, .val = 0x11E700C4 },
         { .reg = 0x00009888, .val = 0x13E70042 },
         { .reg = 0x00009888, .val = 0x15E703C0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90387 },
         { .reg = 0x00009888, .val = 0x09E90248 },
         { .reg = 0x00009888, .val = 0x0BE902CA },
         { .reg = 0x00009888, .val = 0x0DE9034C },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16E70253 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70004 },
         { .reg = 0x00009888, .val = 0x0EE70140 },
         { .reg = 0x00009888, .val = 0x10E700C4 },
         { .reg = 0x00009888, .val = 0x12E70042 },
         { .reg = 0x00009888, .val = 0x14E703C0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90387 },
         { .reg = 0x00009888, .val = 0x08E90248 },
         { .reg = 0x00009888, .val = 0x0AE902CA },
         { .reg = 0x00009888, .val = 0x0CE9034C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17E70253 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70004 },
         { .reg = 0x00009888, .val = 0x0FE70140 },
         { .reg = 0x00009888, .val = 0x11E700C4 },
         { .reg = 0x00009888, .val = 0x13E70042 },
         { .reg = 0x00009888, .val = 0x15E703C0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90387 },
         { .reg = 0x00009888, .val = 0x09E90248 },
         { .reg = 0x00009888, .val = 0x0BE902CA },
         { .reg = 0x00009888, .val = 0x0DE9034C },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26080000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FE7F },
         { .reg = 0x0000DC00, .val = 0x0000001A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000032 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF9 },
         { .reg = 0x0000DC10, .val = 0x00000052 },
         { .reg = 0x0000DC14, .val = 0x0000FFF5 },
         { .reg = 0x0000DC18, .val = 0x00000092 },
         { .reg = 0x0000DC1C, .val = 0x0000FFED },
         { .reg = 0x0000DC20, .val = 0x00000112 },
         { .reg = 0x0000DC24, .val = 0x0000FFDD },
         { .reg = 0x0000DC28, .val = 0x00000212 },
         { .reg = 0x0000DC2C, .val = 0x0000FFBD },
         { .reg = 0x0000DC30, .val = 0x00000412 },
         { .reg = 0x0000DC34, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l1_profile_reads__xe_core3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l1_profile_reads__xe_core3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l1_profile_reads__xe_core3__avg_gpu_core_frequency__max,acmgt3__l1_profile_reads__xe_core3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 783, 24, acmgt3__l1_profile_reads__xe_core3__load_store_cache_byte_read__max,acmgt3__l1_profile_reads__xe_core3__load_store_cache_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 784, 32, acmgt3__l1_profile_reads__xe_core3__slm_byte_read__max,acmgt3__l1_profile_reads__xe_core3__slm_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_read__max,acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_write__max,acmgt3__l1_profile_reads__xe_core3__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt3__l1_profile_reads__xe_core3__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt3__l1_profile_reads__xe_core3__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 64, percentage_max_float,acmgt3__l1_profile_reads__xe_core3__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt3__l1_profile_reads__xe_core3__xve_busy__max,acmgt3__l1_profile_reads__xe_core3__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l1_profile_slm_bank_conflicts__xe_core0_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "L1ProfileSlmBankConflicts";
   query->symbol_name = "L1ProfileSlmBankConflicts_XeCore0";
   query->guid = "dc5ee653-2006-48de-8be2-e8b760a4369c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26080000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__max,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 785, 24, NULL,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__slm_bank_conflict_count__read);

      intel_perf_query_add_counter_uint64(query, 762, 32, acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__max,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 40, acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__max,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 48, percentage_max_float,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 52, percentage_max_float,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 56, percentage_max_float,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 64, acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__max,acmgt3__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l1_profile_slm_bank_conflicts__xe_core3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "L1ProfileSlmBankConflicts";
   query->symbol_name = "L1ProfileSlmBankConflicts_XeCore3";
   query->guid = "41302bd4-41dd-4c52-b250-569324d62f1a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100000 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080000 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0000 },
         { .reg = 0x00009888, .val = 0x1F0A0000 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A0000 },
         { .reg = 0x00009888, .val = 0x1B0A0000 },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26080000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__max,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 785, 24, NULL,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__slm_bank_conflict_count__read);

      intel_perf_query_add_counter_uint64(query, 762, 32, acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__max,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 40, acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__max,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 48, percentage_max_float,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 52, percentage_max_float,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 56, percentage_max_float,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 64, acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__max,acmgt3__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l1_profile_writes__xe_core0_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1ProfileWrites";
   query->symbol_name = "L1ProfileWrites_XeCore0";
   query->guid = "a0369d50-1c37-4bf4-97a9-169c92b63483";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16870012 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x0E870180 },
         { .reg = 0x00009888, .val = 0x10870105 },
         { .reg = 0x00009888, .val = 0x12870083 },
         { .reg = 0x00009888, .val = 0x14870001 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890380 },
         { .reg = 0x00009888, .val = 0x08890081 },
         { .reg = 0x00009888, .val = 0x0A890103 },
         { .reg = 0x00009888, .val = 0x0C890185 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17870012 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870000 },
         { .reg = 0x00009888, .val = 0x0F870180 },
         { .reg = 0x00009888, .val = 0x11870105 },
         { .reg = 0x00009888, .val = 0x13870083 },
         { .reg = 0x00009888, .val = 0x15870001 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890380 },
         { .reg = 0x00009888, .val = 0x09890081 },
         { .reg = 0x00009888, .val = 0x0B890103 },
         { .reg = 0x00009888, .val = 0x0D890185 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870012 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x0E870180 },
         { .reg = 0x00009888, .val = 0x10870105 },
         { .reg = 0x00009888, .val = 0x12870083 },
         { .reg = 0x00009888, .val = 0x14870001 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890380 },
         { .reg = 0x00009888, .val = 0x08890081 },
         { .reg = 0x00009888, .val = 0x0A890103 },
         { .reg = 0x00009888, .val = 0x0C890185 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870012 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870000 },
         { .reg = 0x00009888, .val = 0x0F870180 },
         { .reg = 0x00009888, .val = 0x11870105 },
         { .reg = 0x00009888, .val = 0x13870083 },
         { .reg = 0x00009888, .val = 0x15870001 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890380 },
         { .reg = 0x00009888, .val = 0x09890081 },
         { .reg = 0x00009888, .val = 0x0B890103 },
         { .reg = 0x00009888, .val = 0x0D890185 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870012 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x0E870180 },
         { .reg = 0x00009888, .val = 0x10870105 },
         { .reg = 0x00009888, .val = 0x12870083 },
         { .reg = 0x00009888, .val = 0x14870001 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890380 },
         { .reg = 0x00009888, .val = 0x08890081 },
         { .reg = 0x00009888, .val = 0x0A890103 },
         { .reg = 0x00009888, .val = 0x0C890185 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870012 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870000 },
         { .reg = 0x00009888, .val = 0x0F870180 },
         { .reg = 0x00009888, .val = 0x11870105 },
         { .reg = 0x00009888, .val = 0x13870083 },
         { .reg = 0x00009888, .val = 0x15870001 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890380 },
         { .reg = 0x00009888, .val = 0x09890081 },
         { .reg = 0x00009888, .val = 0x0B890103 },
         { .reg = 0x00009888, .val = 0x0D890185 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16870012 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x0E870180 },
         { .reg = 0x00009888, .val = 0x10870105 },
         { .reg = 0x00009888, .val = 0x12870083 },
         { .reg = 0x00009888, .val = 0x14870001 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890380 },
         { .reg = 0x00009888, .val = 0x08890081 },
         { .reg = 0x00009888, .val = 0x0A890103 },
         { .reg = 0x00009888, .val = 0x0C890185 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17870012 },
         { .reg = 0x00009888, .val = 0x19891060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAA8 },
         { .reg = 0x00009888, .val = 0x0184FEFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865554 },
         { .reg = 0x00009888, .val = 0x05870000 },
         { .reg = 0x00009888, .val = 0x0F870180 },
         { .reg = 0x00009888, .val = 0x11870105 },
         { .reg = 0x00009888, .val = 0x13870083 },
         { .reg = 0x00009888, .val = 0x15870001 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03870000 },
         { .reg = 0x00009888, .val = 0x03890054 },
         { .reg = 0x00009888, .val = 0x07890380 },
         { .reg = 0x00009888, .val = 0x09890081 },
         { .reg = 0x00009888, .val = 0x0B890103 },
         { .reg = 0x00009888, .val = 0x0D890185 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA8 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5554 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26080000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FE7F },
         { .reg = 0x0000DC00, .val = 0x0000001A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000032 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF9 },
         { .reg = 0x0000DC10, .val = 0x00000052 },
         { .reg = 0x0000DC14, .val = 0x0000FFF5 },
         { .reg = 0x0000DC18, .val = 0x00000092 },
         { .reg = 0x0000DC1C, .val = 0x0000FFED },
         { .reg = 0x0000DC20, .val = 0x00000112 },
         { .reg = 0x0000DC24, .val = 0x0000FFDD },
         { .reg = 0x0000DC28, .val = 0x00000212 },
         { .reg = 0x0000DC2C, .val = 0x0000FFBD },
         { .reg = 0x0000DC30, .val = 0x00000412 },
         { .reg = 0x0000DC34, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l1_profile_writes__xe_core0__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l1_profile_writes__xe_core0__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l1_profile_writes__xe_core0__avg_gpu_core_frequency__max,acmgt3__l1_profile_writes__xe_core0__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 786, 24, acmgt3__l1_profile_writes__xe_core0__load_store_cache_byte_write__max,acmgt3__l1_profile_writes__xe_core0__load_store_cache_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 787, 32, acmgt3__l1_profile_writes__xe_core0__slm_byte_write__max,acmgt3__l1_profile_writes__xe_core0__slm_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_read__max,acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_write__max,acmgt3__l1_profile_writes__xe_core0__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt3__l1_profile_writes__xe_core0__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt3__l1_profile_writes__xe_core0__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 64, percentage_max_float,acmgt3__l1_profile_writes__xe_core0__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt3__l1_profile_writes__xe_core0__xve_busy__max,acmgt3__l1_profile_writes__xe_core0__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_l1_profile_writes__xe_core3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "L1ProfileWrites";
   query->symbol_name = "L1ProfileWrites_XeCore3";
   query->guid = "ff386ef9-604c-48a5-9fc9-e2281bbd7463";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16E70012 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x0EE70180 },
         { .reg = 0x00009888, .val = 0x10E70105 },
         { .reg = 0x00009888, .val = 0x12E70083 },
         { .reg = 0x00009888, .val = 0x14E70001 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90380 },
         { .reg = 0x00009888, .val = 0x08E90081 },
         { .reg = 0x00009888, .val = 0x0AE90103 },
         { .reg = 0x00009888, .val = 0x0CE90185 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17E70012 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70000 },
         { .reg = 0x00009888, .val = 0x0FE70180 },
         { .reg = 0x00009888, .val = 0x11E70105 },
         { .reg = 0x00009888, .val = 0x13E70083 },
         { .reg = 0x00009888, .val = 0x15E70001 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90380 },
         { .reg = 0x00009888, .val = 0x09E90081 },
         { .reg = 0x00009888, .val = 0x0BE90103 },
         { .reg = 0x00009888, .val = 0x0DE90185 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E70012 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x0EE70180 },
         { .reg = 0x00009888, .val = 0x10E70105 },
         { .reg = 0x00009888, .val = 0x12E70083 },
         { .reg = 0x00009888, .val = 0x14E70001 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90380 },
         { .reg = 0x00009888, .val = 0x08E90081 },
         { .reg = 0x00009888, .val = 0x0AE90103 },
         { .reg = 0x00009888, .val = 0x0CE90185 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E70012 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70000 },
         { .reg = 0x00009888, .val = 0x0FE70180 },
         { .reg = 0x00009888, .val = 0x11E70105 },
         { .reg = 0x00009888, .val = 0x13E70083 },
         { .reg = 0x00009888, .val = 0x15E70001 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90380 },
         { .reg = 0x00009888, .val = 0x09E90081 },
         { .reg = 0x00009888, .val = 0x0BE90103 },
         { .reg = 0x00009888, .val = 0x0DE90185 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16E70012 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x0EE70180 },
         { .reg = 0x00009888, .val = 0x10E70105 },
         { .reg = 0x00009888, .val = 0x12E70083 },
         { .reg = 0x00009888, .val = 0x14E70001 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90380 },
         { .reg = 0x00009888, .val = 0x08E90081 },
         { .reg = 0x00009888, .val = 0x0AE90103 },
         { .reg = 0x00009888, .val = 0x0CE90185 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17E70012 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70000 },
         { .reg = 0x00009888, .val = 0x0FE70180 },
         { .reg = 0x00009888, .val = 0x11E70105 },
         { .reg = 0x00009888, .val = 0x13E70083 },
         { .reg = 0x00009888, .val = 0x15E70001 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90380 },
         { .reg = 0x00009888, .val = 0x09E90081 },
         { .reg = 0x00009888, .val = 0x0BE90103 },
         { .reg = 0x00009888, .val = 0x0DE90185 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16E70012 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x0EE70180 },
         { .reg = 0x00009888, .val = 0x10E70105 },
         { .reg = 0x00009888, .val = 0x12E70083 },
         { .reg = 0x00009888, .val = 0x14E70001 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90380 },
         { .reg = 0x00009888, .val = 0x08E90081 },
         { .reg = 0x00009888, .val = 0x0AE90103 },
         { .reg = 0x00009888, .val = 0x0CE90185 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17E70012 },
         { .reg = 0x00009888, .val = 0x19E91060 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAA8 },
         { .reg = 0x00009888, .val = 0x01E4FEFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65554 },
         { .reg = 0x00009888, .val = 0x05E70000 },
         { .reg = 0x00009888, .val = 0x0FE70180 },
         { .reg = 0x00009888, .val = 0x11E70105 },
         { .reg = 0x00009888, .val = 0x13E70083 },
         { .reg = 0x00009888, .val = 0x15E70001 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E70000 },
         { .reg = 0x00009888, .val = 0x03E90054 },
         { .reg = 0x00009888, .val = 0x07E90380 },
         { .reg = 0x00009888, .val = 0x09E90081 },
         { .reg = 0x00009888, .val = 0x0BE90103 },
         { .reg = 0x00009888, .val = 0x0DE90185 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075554 },
         { .reg = 0x00009888, .val = 0x0109FEFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA8 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x26100003 },
         { .reg = 0x00009888, .val = 0x28100000 },
         { .reg = 0x00009888, .val = 0x2A100000 },
         { .reg = 0x00009888, .val = 0x2C100000 },
         { .reg = 0x00009888, .val = 0x2E100003 },
         { .reg = 0x00009888, .val = 0x22100C63 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x2410060C },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080000 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080000 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080000 },
         { .reg = 0x00009888, .val = 0x24080003 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080C63 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C080C63 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A0063 },
         { .reg = 0x00009888, .val = 0x1F0A0063 },
         { .reg = 0x00009888, .val = 0x200A0000 },
         { .reg = 0x00009888, .val = 0x210A0000 },
         { .reg = 0x00009888, .val = 0x220A0000 },
         { .reg = 0x00009888, .val = 0x230A0000 },
         { .reg = 0x00009888, .val = 0x240A0000 },
         { .reg = 0x00009888, .val = 0x250A0000 },
         { .reg = 0x00009888, .val = 0x260A0060 },
         { .reg = 0x00009888, .val = 0x270A0060 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0183 },
         { .reg = 0x00009888, .val = 0x1D0A0183 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26080000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x007F0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FE7F },
         { .reg = 0x0000DC00, .val = 0x0000001A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000032 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF9 },
         { .reg = 0x0000DC10, .val = 0x00000052 },
         { .reg = 0x0000DC14, .val = 0x0000FFF5 },
         { .reg = 0x0000DC18, .val = 0x00000092 },
         { .reg = 0x0000DC1C, .val = 0x0000FFED },
         { .reg = 0x0000DC20, .val = 0x00000112 },
         { .reg = 0x0000DC24, .val = 0x0000FFDD },
         { .reg = 0x0000DC28, .val = 0x00000212 },
         { .reg = 0x0000DC2C, .val = 0x0000FFBD },
         { .reg = 0x0000DC30, .val = 0x00000412 },
         { .reg = 0x0000DC34, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__l1_profile_writes__xe_core3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__l1_profile_writes__xe_core3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__l1_profile_writes__xe_core3__avg_gpu_core_frequency__max,acmgt3__l1_profile_writes__xe_core3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 786, 24, acmgt3__l1_profile_writes__xe_core3__load_store_cache_byte_write__max,acmgt3__l1_profile_writes__xe_core3__load_store_cache_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 787, 32, acmgt3__l1_profile_writes__xe_core3__slm_byte_write__max,acmgt3__l1_profile_writes__xe_core3__slm_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 40, acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_read__max,acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 48, acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_write__max,acmgt3__l1_profile_writes__xe_core3__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 56, percentage_max_float,acmgt3__l1_profile_writes__xe_core3__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 60, percentage_max_float,acmgt3__l1_profile_writes__xe_core3__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 64, percentage_max_float,acmgt3__l1_profile_writes__xe_core3__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt3__l1_profile_writes__xe_core3__xve_busy__max,acmgt3__l1_profile_writes__xe_core3__xve_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_dataport_reads_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "DataportReads";
   query->symbol_name = "DataportReads";
   query->guid = "c027d083-6448-4ec1-9415-8a1ff807562c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x12091940 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x100903D6 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x04090000 },
         { .reg = 0x00009888, .val = 0x06090000 },
         { .reg = 0x00009888, .val = 0x040A1000 },
         { .reg = 0x00009888, .val = 0x060A0001 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B000 },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B695 },
         { .reg = 0x00009888, .val = 0x12E1A000 },
         { .reg = 0x00009888, .val = 0x14E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x10810617 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830A00 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x00840330 },
         { .reg = 0x00009888, .val = 0x00860500 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00870500 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x0EA106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A000 },
         { .reg = 0x00009888, .val = 0x02A300A0 },
         { .reg = 0x00009888, .val = 0x00A40CC0 },
         { .reg = 0x00009888, .val = 0x00A65000 },
         { .reg = 0x00009888, .val = 0x02A60050 },
         { .reg = 0x00009888, .val = 0x00A75000 },
         { .reg = 0x00009888, .val = 0x02A70050 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3000A },
         { .reg = 0x00009888, .val = 0x02C30A00 },
         { .reg = 0x00009888, .val = 0x00C43003 },
         { .reg = 0x00009888, .val = 0x00C60005 },
         { .reg = 0x00009888, .val = 0x02C60500 },
         { .reg = 0x00009888, .val = 0x00C70005 },
         { .reg = 0x00009888, .val = 0x02C70500 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x0AE10656 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E300A0 },
         { .reg = 0x00009888, .val = 0x02E3A000 },
         { .reg = 0x00009888, .val = 0x00E4C00C },
         { .reg = 0x00009888, .val = 0x00E60050 },
         { .reg = 0x00009888, .val = 0x02E65000 },
         { .reg = 0x00009888, .val = 0x00E70050 },
         { .reg = 0x00009888, .val = 0x02E75000 },
         { .reg = 0x00009888, .val = 0x0007005A },
         { .reg = 0x00009888, .val = 0x02075A00 },
         { .reg = 0x00009888, .val = 0x0008FA00 },
         { .reg = 0x00009888, .val = 0x020800FA },
         { .reg = 0x00009888, .val = 0x0009F00F },
         { .reg = 0x00009888, .val = 0x000A55AA },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010CC0 },
         { .reg = 0x00009888, .val = 0x000B5000 },
         { .reg = 0x00009888, .val = 0x020B0050 },
         { .reg = 0x00009888, .val = 0x00023003 },
         { .reg = 0x00009888, .val = 0x000C0005 },
         { .reg = 0x00009888, .val = 0x020C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B000 },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B695 },
         { .reg = 0x00009888, .val = 0x13E1A000 },
         { .reg = 0x00009888, .val = 0x15E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x11810617 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830A00 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840330 },
         { .reg = 0x00009888, .val = 0x01860500 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01870500 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x0FA106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40CC0 },
         { .reg = 0x00009888, .val = 0x01A65000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x01A75000 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3000A },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43003 },
         { .reg = 0x00009888, .val = 0x01C60005 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x01C70005 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x0BE10656 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E300A0 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C00C },
         { .reg = 0x00009888, .val = 0x01E60050 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x01E70050 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0107005A },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x0108FA00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F00F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010CC0 },
         { .reg = 0x00009888, .val = 0x010B5000 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023003 },
         { .reg = 0x00009888, .val = 0x010C0005 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B000 },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B695 },
         { .reg = 0x00009888, .val = 0x12E1A000 },
         { .reg = 0x00009888, .val = 0x14E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x10810617 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830A00 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x00840330 },
         { .reg = 0x00009888, .val = 0x00860500 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00870500 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x0EA106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A000 },
         { .reg = 0x00009888, .val = 0x02A300A0 },
         { .reg = 0x00009888, .val = 0x00A40CC0 },
         { .reg = 0x00009888, .val = 0x00A65000 },
         { .reg = 0x00009888, .val = 0x02A60050 },
         { .reg = 0x00009888, .val = 0x00A75000 },
         { .reg = 0x00009888, .val = 0x02A70050 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3000A },
         { .reg = 0x00009888, .val = 0x02C30A00 },
         { .reg = 0x00009888, .val = 0x00C43003 },
         { .reg = 0x00009888, .val = 0x00C60005 },
         { .reg = 0x00009888, .val = 0x02C60500 },
         { .reg = 0x00009888, .val = 0x00C70005 },
         { .reg = 0x00009888, .val = 0x02C70500 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x0AE10656 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E300A0 },
         { .reg = 0x00009888, .val = 0x02E3A000 },
         { .reg = 0x00009888, .val = 0x00E4C00C },
         { .reg = 0x00009888, .val = 0x00E60050 },
         { .reg = 0x00009888, .val = 0x02E65000 },
         { .reg = 0x00009888, .val = 0x00E70050 },
         { .reg = 0x00009888, .val = 0x02E75000 },
         { .reg = 0x00009888, .val = 0x0007005A },
         { .reg = 0x00009888, .val = 0x02075A00 },
         { .reg = 0x00009888, .val = 0x0008FA00 },
         { .reg = 0x00009888, .val = 0x020800FA },
         { .reg = 0x00009888, .val = 0x0009F00F },
         { .reg = 0x00009888, .val = 0x000A55AA },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010CC0 },
         { .reg = 0x00009888, .val = 0x000B5000 },
         { .reg = 0x00009888, .val = 0x020B0050 },
         { .reg = 0x00009888, .val = 0x00023003 },
         { .reg = 0x00009888, .val = 0x000C0005 },
         { .reg = 0x00009888, .val = 0x020C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B000 },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B695 },
         { .reg = 0x00009888, .val = 0x13E1A000 },
         { .reg = 0x00009888, .val = 0x15E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x11810617 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830A00 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840330 },
         { .reg = 0x00009888, .val = 0x01860500 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01870500 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x0FA106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40CC0 },
         { .reg = 0x00009888, .val = 0x01A65000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x01A75000 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3000A },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43003 },
         { .reg = 0x00009888, .val = 0x01C60005 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x01C70005 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x0BE10656 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E300A0 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C00C },
         { .reg = 0x00009888, .val = 0x01E60050 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x01E70050 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0107005A },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x0108FA00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F00F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010CC0 },
         { .reg = 0x00009888, .val = 0x010B5000 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023003 },
         { .reg = 0x00009888, .val = 0x010C0005 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B000 },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B695 },
         { .reg = 0x00009888, .val = 0x12E1A000 },
         { .reg = 0x00009888, .val = 0x14E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x10810617 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830A00 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x00840330 },
         { .reg = 0x00009888, .val = 0x00860500 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00870500 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x0EA106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A000 },
         { .reg = 0x00009888, .val = 0x02A300A0 },
         { .reg = 0x00009888, .val = 0x00A40CC0 },
         { .reg = 0x00009888, .val = 0x00A65000 },
         { .reg = 0x00009888, .val = 0x02A60050 },
         { .reg = 0x00009888, .val = 0x00A75000 },
         { .reg = 0x00009888, .val = 0x02A70050 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3000A },
         { .reg = 0x00009888, .val = 0x02C30A00 },
         { .reg = 0x00009888, .val = 0x00C43003 },
         { .reg = 0x00009888, .val = 0x00C60005 },
         { .reg = 0x00009888, .val = 0x02C60500 },
         { .reg = 0x00009888, .val = 0x00C70005 },
         { .reg = 0x00009888, .val = 0x02C70500 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x0AE10656 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E300A0 },
         { .reg = 0x00009888, .val = 0x02E3A000 },
         { .reg = 0x00009888, .val = 0x00E4C00C },
         { .reg = 0x00009888, .val = 0x00E60050 },
         { .reg = 0x00009888, .val = 0x02E65000 },
         { .reg = 0x00009888, .val = 0x00E70050 },
         { .reg = 0x00009888, .val = 0x02E75000 },
         { .reg = 0x00009888, .val = 0x0007005A },
         { .reg = 0x00009888, .val = 0x02075A00 },
         { .reg = 0x00009888, .val = 0x0008FA00 },
         { .reg = 0x00009888, .val = 0x020800FA },
         { .reg = 0x00009888, .val = 0x0009F00F },
         { .reg = 0x00009888, .val = 0x000A55AA },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010CC0 },
         { .reg = 0x00009888, .val = 0x000B5000 },
         { .reg = 0x00009888, .val = 0x020B0050 },
         { .reg = 0x00009888, .val = 0x00023003 },
         { .reg = 0x00009888, .val = 0x000C0005 },
         { .reg = 0x00009888, .val = 0x020C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B000 },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B695 },
         { .reg = 0x00009888, .val = 0x13E1A000 },
         { .reg = 0x00009888, .val = 0x15E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x11810617 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830A00 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840330 },
         { .reg = 0x00009888, .val = 0x01860500 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01870500 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x0FA106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40CC0 },
         { .reg = 0x00009888, .val = 0x01A65000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x01A75000 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3000A },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43003 },
         { .reg = 0x00009888, .val = 0x01C60005 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x01C70005 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x0BE10656 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E300A0 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C00C },
         { .reg = 0x00009888, .val = 0x01E60050 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x01E70050 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0107005A },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x0108FA00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F00F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010CC0 },
         { .reg = 0x00009888, .val = 0x010B5000 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023003 },
         { .reg = 0x00009888, .val = 0x010C0005 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B000 },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B695 },
         { .reg = 0x00009888, .val = 0x12E1A000 },
         { .reg = 0x00009888, .val = 0x14E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x10810617 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830A00 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x00840330 },
         { .reg = 0x00009888, .val = 0x00860500 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00870500 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x0EA106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A000 },
         { .reg = 0x00009888, .val = 0x02A300A0 },
         { .reg = 0x00009888, .val = 0x00A40CC0 },
         { .reg = 0x00009888, .val = 0x00A65000 },
         { .reg = 0x00009888, .val = 0x02A60050 },
         { .reg = 0x00009888, .val = 0x00A75000 },
         { .reg = 0x00009888, .val = 0x02A70050 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3000A },
         { .reg = 0x00009888, .val = 0x02C30A00 },
         { .reg = 0x00009888, .val = 0x00C43003 },
         { .reg = 0x00009888, .val = 0x00C60005 },
         { .reg = 0x00009888, .val = 0x02C60500 },
         { .reg = 0x00009888, .val = 0x00C70005 },
         { .reg = 0x00009888, .val = 0x02C70500 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x0AE10656 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E300A0 },
         { .reg = 0x00009888, .val = 0x02E3A000 },
         { .reg = 0x00009888, .val = 0x00E4C00C },
         { .reg = 0x00009888, .val = 0x00E60050 },
         { .reg = 0x00009888, .val = 0x02E65000 },
         { .reg = 0x00009888, .val = 0x00E70050 },
         { .reg = 0x00009888, .val = 0x02E75000 },
         { .reg = 0x00009888, .val = 0x0007005A },
         { .reg = 0x00009888, .val = 0x02075A00 },
         { .reg = 0x00009888, .val = 0x0008FA00 },
         { .reg = 0x00009888, .val = 0x020800FA },
         { .reg = 0x00009888, .val = 0x0009F00F },
         { .reg = 0x00009888, .val = 0x000A55AA },
         { .reg = 0x00009888, .val = 0x020AAA55 },
         { .reg = 0x00009888, .val = 0x00010CC0 },
         { .reg = 0x00009888, .val = 0x000B5000 },
         { .reg = 0x00009888, .val = 0x020B0050 },
         { .reg = 0x00009888, .val = 0x00023003 },
         { .reg = 0x00009888, .val = 0x000C0005 },
         { .reg = 0x00009888, .val = 0x020C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B000 },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B695 },
         { .reg = 0x00009888, .val = 0x13E1A000 },
         { .reg = 0x00009888, .val = 0x15E1B000 },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x11810617 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830A00 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840330 },
         { .reg = 0x00009888, .val = 0x01860500 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01870500 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x0FA106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40CC0 },
         { .reg = 0x00009888, .val = 0x01A65000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x01A75000 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3000A },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43003 },
         { .reg = 0x00009888, .val = 0x01C60005 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x01C70005 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x0BE10656 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E300A0 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C00C },
         { .reg = 0x00009888, .val = 0x01E60050 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x01E70050 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0107005A },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x0108FA00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F00F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010CC0 },
         { .reg = 0x00009888, .val = 0x010B5000 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023003 },
         { .reg = 0x00009888, .val = 0x010C0005 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100000 },
         { .reg = 0x00009888, .val = 0x2610000A },
         { .reg = 0x00009888, .val = 0x2810154A },
         { .reg = 0x00009888, .val = 0x2A100C00 },
         { .reg = 0x00009888, .val = 0x2C10408C },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22100063 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24101400 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080000 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E082940 },
         { .reg = 0x00009888, .val = 0x0E084000 },
         { .reg = 0x00009888, .val = 0x20080C00 },
         { .reg = 0x00009888, .val = 0x10081000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x22080403 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A080063 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C082940 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0000 },
         { .reg = 0x00009888, .val = 0x190A0000 },
         { .reg = 0x00009888, .val = 0x1E0A014A },
         { .reg = 0x00009888, .val = 0x1F0A014A },
         { .reg = 0x00009888, .val = 0x200A2940 },
         { .reg = 0x00009888, .val = 0x210A2940 },
         { .reg = 0x00009888, .val = 0x220A0081 },
         { .reg = 0x00009888, .val = 0x230A0081 },
         { .reg = 0x00009888, .val = 0x240A5183 },
         { .reg = 0x00009888, .val = 0x250A5183 },
         { .reg = 0x00009888, .val = 0x260A0000 },
         { .reg = 0x00009888, .val = 0x270A0000 },
         { .reg = 0x00009888, .val = 0x1A0A060C },
         { .reg = 0x00009888, .val = 0x1B0A060C },
         { .reg = 0x00009888, .val = 0x1C0A0000 },
         { .reg = 0x00009888, .val = 0x1D0A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26080000 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000DC00, .val = 0x0000000A },
         { .reg = 0x0000DC04, .val = 0x0000FFFC },
         { .reg = 0x0000DC08, .val = 0x00000022 },
         { .reg = 0x0000DC0C, .val = 0x0000FFF3 },
         { .reg = 0x0000DC10, .val = 0x00000082 },
         { .reg = 0x0000DC14, .val = 0x0000FFCF },
         { .reg = 0x0000DC18, .val = 0x00000202 },
         { .reg = 0x0000DC1C, .val = 0x0000FF3F },
         { .reg = 0x0000DC20, .val = 0x00000802 },
         { .reg = 0x0000DC24, .val = 0x0000FCFF },
         { .reg = 0x0000DC28, .val = 0x00002002 },
         { .reg = 0x0000DC2C, .val = 0x0000F3FF },
         { .reg = 0x0000DC30, .val = 0x00008002 },
         { .reg = 0x0000DC34, .val = 0x0000CFFF },
         { .reg = 0x0000DC38, .val = 0x00020002 },
         { .reg = 0x0000DC3C, .val = 0x00003FFF },
         { .reg = 0x0000DC40, .val = 0x00FF0000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__dataport_reads__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__dataport_reads__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__dataport_reads__avg_gpu_core_frequency__max,acmgt3__dataport_reads__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 788, 24, acmgt3__dataport_reads__dataport_byte_read__max,acmgt3__dataport_reads__dataport_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 789, 32, acmgt3__dataport_reads__host_to_gpumem_byte_read__max,acmgt3__dataport_reads__host_to_gpumem_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 790, 40, acmgt3__dataport_reads__host_to_gpumem_byte_write__max,acmgt3__dataport_reads__host_to_gpumem_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 48, acmgt3__dataport_reads__gpu_memory_byte_read__max,acmgt3__dataport_reads__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 56, acmgt3__dataport_reads__gpu_memory_byte_write__max,acmgt3__dataport_reads__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 64, percentage_max_float,acmgt3__dataport_reads__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 68, percentage_max_float,acmgt3__dataport_reads__xve_stall__read);

      intel_perf_query_add_counter_uint64(query, 766, 72, acmgt3__dataport_reads__xve_busy__max,acmgt3__dataport_reads__xve_busy__read);

      intel_perf_query_add_counter_float(query, 767, 80, percentage_max_float,acmgt3__dataport_reads__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 768, 88, NULL,acmgt3__dataport_reads__xve_compute_thread_count__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_dataport_writes_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "DataportWrites";
   query->symbol_name = "DataportWrites";
   query->guid = "57e2e261-2715-4b63-baec-527eba9e06cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x120900A0 },
         { .reg = 0x00009888, .val = 0x00030024 },
         { .reg = 0x00009888, .val = 0x06091490 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x16030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0C810016 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830200 },
         { .reg = 0x00009888, .val = 0x00840010 },
         { .reg = 0x00009888, .val = 0x00860100 },
         { .reg = 0x00009888, .val = 0x00870100 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0CA10580 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30800 },
         { .reg = 0x00009888, .val = 0x00A40020 },
         { .reg = 0x00009888, .val = 0x00A60400 },
         { .reg = 0x00009888, .val = 0x00A70400 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0EC10016 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C32000 },
         { .reg = 0x00009888, .val = 0x00C40040 },
         { .reg = 0x00009888, .val = 0x00C61000 },
         { .reg = 0x00009888, .val = 0x00C71000 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0EE10580 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E38000 },
         { .reg = 0x00009888, .val = 0x00E40080 },
         { .reg = 0x00009888, .val = 0x00E64000 },
         { .reg = 0x00009888, .val = 0x00E74000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x06030000 },
         { .reg = 0x00009888, .val = 0x08030000 },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x0E030000 },
         { .reg = 0x00009888, .val = 0x10030000 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00076000 },
         { .reg = 0x00009888, .val = 0x00080EFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900C0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF2F },
         { .reg = 0x00009888, .val = 0x000B04AA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020040 },
         { .reg = 0x00009888, .val = 0x000C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x17030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810016 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10580 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10016 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10580 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030000 },
         { .reg = 0x00009888, .val = 0x07030000 },
         { .reg = 0x00009888, .val = 0x09030000 },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x0F030000 },
         { .reg = 0x00009888, .val = 0x11030000 },
         { .reg = 0x00009888, .val = 0x13030000 },
         { .reg = 0x00009888, .val = 0x15030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080EFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF2F },
         { .reg = 0x00009888, .val = 0x010B04AA },
         { .reg = 0x00009888, .val = 0x030BAAAA },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x16030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0C810016 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830200 },
         { .reg = 0x00009888, .val = 0x00840010 },
         { .reg = 0x00009888, .val = 0x00860100 },
         { .reg = 0x00009888, .val = 0x00870100 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0CA10580 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30800 },
         { .reg = 0x00009888, .val = 0x00A40020 },
         { .reg = 0x00009888, .val = 0x00A60400 },
         { .reg = 0x00009888, .val = 0x00A70400 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0EC10016 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C32000 },
         { .reg = 0x00009888, .val = 0x00C40040 },
         { .reg = 0x00009888, .val = 0x00C61000 },
         { .reg = 0x00009888, .val = 0x00C71000 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0EE10580 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E38000 },
         { .reg = 0x00009888, .val = 0x00E40080 },
         { .reg = 0x00009888, .val = 0x00E64000 },
         { .reg = 0x00009888, .val = 0x00E74000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x06030000 },
         { .reg = 0x00009888, .val = 0x08030000 },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x0E030000 },
         { .reg = 0x00009888, .val = 0x10030000 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00076000 },
         { .reg = 0x00009888, .val = 0x00080EFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900C0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF2F },
         { .reg = 0x00009888, .val = 0x000B04AA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020040 },
         { .reg = 0x00009888, .val = 0x000C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x17030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810016 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10580 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10016 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10580 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030000 },
         { .reg = 0x00009888, .val = 0x07030000 },
         { .reg = 0x00009888, .val = 0x09030000 },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x0F030000 },
         { .reg = 0x00009888, .val = 0x11030000 },
         { .reg = 0x00009888, .val = 0x13030000 },
         { .reg = 0x00009888, .val = 0x15030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080EFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF2F },
         { .reg = 0x00009888, .val = 0x010B04AA },
         { .reg = 0x00009888, .val = 0x030BAAAA },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x16030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0C810016 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830200 },
         { .reg = 0x00009888, .val = 0x00840010 },
         { .reg = 0x00009888, .val = 0x00860100 },
         { .reg = 0x00009888, .val = 0x00870100 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0CA10580 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30800 },
         { .reg = 0x00009888, .val = 0x00A40020 },
         { .reg = 0x00009888, .val = 0x00A60400 },
         { .reg = 0x00009888, .val = 0x00A70400 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0EC10016 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C32000 },
         { .reg = 0x00009888, .val = 0x00C40040 },
         { .reg = 0x00009888, .val = 0x00C61000 },
         { .reg = 0x00009888, .val = 0x00C71000 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0EE10580 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E38000 },
         { .reg = 0x00009888, .val = 0x00E40080 },
         { .reg = 0x00009888, .val = 0x00E64000 },
         { .reg = 0x00009888, .val = 0x00E74000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x06030000 },
         { .reg = 0x00009888, .val = 0x08030000 },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x0E030000 },
         { .reg = 0x00009888, .val = 0x10030000 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00076000 },
         { .reg = 0x00009888, .val = 0x00080EFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900C0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF2F },
         { .reg = 0x00009888, .val = 0x000B04AA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020040 },
         { .reg = 0x00009888, .val = 0x000C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x17030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810016 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10580 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10016 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10580 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030000 },
         { .reg = 0x00009888, .val = 0x07030000 },
         { .reg = 0x00009888, .val = 0x09030000 },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x0F030000 },
         { .reg = 0x00009888, .val = 0x11030000 },
         { .reg = 0x00009888, .val = 0x13030000 },
         { .reg = 0x00009888, .val = 0x15030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080EFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF2F },
         { .reg = 0x00009888, .val = 0x010B04AA },
         { .reg = 0x00009888, .val = 0x030BAAAA },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x16030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0C810016 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830200 },
         { .reg = 0x00009888, .val = 0x00840010 },
         { .reg = 0x00009888, .val = 0x00860100 },
         { .reg = 0x00009888, .val = 0x00870100 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0CA10580 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30800 },
         { .reg = 0x00009888, .val = 0x00A40020 },
         { .reg = 0x00009888, .val = 0x00A60400 },
         { .reg = 0x00009888, .val = 0x00A70400 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0EC10016 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C32000 },
         { .reg = 0x00009888, .val = 0x00C40040 },
         { .reg = 0x00009888, .val = 0x00C61000 },
         { .reg = 0x00009888, .val = 0x00C71000 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0EE10580 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E38000 },
         { .reg = 0x00009888, .val = 0x00E40080 },
         { .reg = 0x00009888, .val = 0x00E64000 },
         { .reg = 0x00009888, .val = 0x00E74000 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x06030000 },
         { .reg = 0x00009888, .val = 0x08030000 },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x0E030000 },
         { .reg = 0x00009888, .val = 0x10030000 },
         { .reg = 0x00009888, .val = 0x12030000 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00076000 },
         { .reg = 0x00009888, .val = 0x00080EFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900C0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF2F },
         { .reg = 0x00009888, .val = 0x000B04AA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020040 },
         { .reg = 0x00009888, .val = 0x000C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x280A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x17030019 },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0D810016 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0DA10580 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x0FC10016 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x0FE10580 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03030002 },
         { .reg = 0x00009888, .val = 0x05030000 },
         { .reg = 0x00009888, .val = 0x07030000 },
         { .reg = 0x00009888, .val = 0x09030000 },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x0F030000 },
         { .reg = 0x00009888, .val = 0x11030000 },
         { .reg = 0x00009888, .val = 0x13030000 },
         { .reg = 0x00009888, .val = 0x15030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080EFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF2F },
         { .reg = 0x00009888, .val = 0x010B04AA },
         { .reg = 0x00009888, .val = 0x030BAAAA },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12105000 },
         { .reg = 0x00009888, .val = 0x20102C00 },
         { .reg = 0x00009888, .val = 0x261055AB },
         { .reg = 0x00009888, .val = 0x2810056B },
         { .reg = 0x00009888, .val = 0x2A100060 },
         { .reg = 0x00009888, .val = 0x2C1056A8 },
         { .reg = 0x00009888, .val = 0x2E10000B },
         { .reg = 0x00009888, .val = 0x22102D6B },
         { .reg = 0x00009888, .val = 0x14105000 },
         { .reg = 0x00009888, .val = 0x241056AD },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04082000 },
         { .reg = 0x00009888, .val = 0x18082C00 },
         { .reg = 0x00009888, .val = 0x0C085000 },
         { .reg = 0x00009888, .val = 0x1E082D6B },
         { .reg = 0x00009888, .val = 0x0E085000 },
         { .reg = 0x00009888, .val = 0x20080060 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12084000 },
         { .reg = 0x00009888, .val = 0x2208056A },
         { .reg = 0x00009888, .val = 0x2408000B },
         { .reg = 0x00009888, .val = 0x06085000 },
         { .reg = 0x00009888, .val = 0x1A082D6B },
         { .reg = 0x00009888, .val = 0x08085000 },
         { .reg = 0x00009888, .val = 0x1C082D6B },
         { .reg = 0x00009888, .val = 0x0A085000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A4000 },
         { .reg = 0x00009888, .val = 0x170A4000 },
         { .reg = 0x00009888, .val = 0x180A2C00 },
         { .reg = 0x00009888, .val = 0x190A2C00 },
         { .reg = 0x00009888, .val = 0x1E0A556B },
         { .reg = 0x00009888, .val = 0x1F0A556B },
         { .reg = 0x00009888, .val = 0x200A2D6B },
         { .reg = 0x00009888, .val = 0x210A2D6B },
         { .reg = 0x00009888, .val = 0x220A0601 },
         { .reg = 0x00009888, .val = 0x230A0601 },
         { .reg = 0x00009888, .val = 0x240A5500 },
         { .reg = 0x00009888, .val = 0x250A5500 },
         { .reg = 0x00009888, .val = 0x260A016B },
         { .reg = 0x00009888, .val = 0x270A016B },
         { .reg = 0x00009888, .val = 0x1A0A56AD },
         { .reg = 0x00009888, .val = 0x1B0A56AD },
         { .reg = 0x00009888, .val = 0x1C0A55AB },
         { .reg = 0x00009888, .val = 0x1D0A55AB },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x290A0001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C3000 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x070C0000 },
         { .reg = 0x00009888, .val = 0x130C0380 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0180 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00065555 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0FF },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26080001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C3000 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x070C0000 },
         { .reg = 0x00009888, .val = 0x130C0380 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0180 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00065555 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0FF },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26080001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C3000 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x070C0000 },
         { .reg = 0x00009888, .val = 0x130C0380 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0180 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00065555 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0FF },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26080001 },
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C3000 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0032 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x070C0000 },
         { .reg = 0x00009888, .val = 0x130C0380 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0180 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x00065555 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A0FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A0FF },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x12100000 },
         { .reg = 0x00009888, .val = 0x20100400 },
         { .reg = 0x00009888, .val = 0x26100081 },
         { .reg = 0x00009888, .val = 0x28100021 },
         { .reg = 0x00009888, .val = 0x2A100421 },
         { .reg = 0x00009888, .val = 0x2C100804 },
         { .reg = 0x00009888, .val = 0x2E100000 },
         { .reg = 0x00009888, .val = 0x22102801 },
         { .reg = 0x00009888, .val = 0x14100000 },
         { .reg = 0x00009888, .val = 0x24100E04 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x18080400 },
         { .reg = 0x00009888, .val = 0x0C080000 },
         { .reg = 0x00009888, .val = 0x1E080421 },
         { .reg = 0x00009888, .val = 0x0E080000 },
         { .reg = 0x00009888, .val = 0x20080421 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080000 },
         { .reg = 0x00009888, .val = 0x22080081 },
         { .reg = 0x00009888, .val = 0x24080000 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x1A082801 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x1C0804E1 },
         { .reg = 0x00009888, .val = 0x0A080000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A0000 },
         { .reg = 0x00009888, .val = 0x170A0000 },
         { .reg = 0x00009888, .val = 0x180A0400 },
         { .reg = 0x00009888, .val = 0x190A0400 },
         { .reg = 0x00009888, .val = 0x1E0A0027 },
         { .reg = 0x00009888, .val = 0x1F0A0027 },
         { .reg = 0x00009888, .val = 0x200A0421 },
         { .reg = 0x00009888, .val = 0x210A0421 },
         { .reg = 0x00009888, .val = 0x220A0204 },
         { .reg = 0x00009888, .val = 0x230A0204 },
         { .reg = 0x00009888, .val = 0x240A0081 },
         { .reg = 0x00009888, .val = 0x250A0081 },
         { .reg = 0x00009888, .val = 0x260A0004 },
         { .reg = 0x00009888, .val = 0x270A0004 },
         { .reg = 0x00009888, .val = 0x1A0A0004 },
         { .reg = 0x00009888, .val = 0x1B0A0004 },
         { .reg = 0x00009888, .val = 0x1C0A008A },
         { .reg = 0x00009888, .val = 0x1D0A008A },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26080001 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x0000FFF0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__dataport_writes__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__dataport_writes__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__dataport_writes__avg_gpu_core_frequency__max,acmgt3__dataport_writes__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 791, 24, acmgt3__dataport_writes__dataport_byte_write__max,acmgt3__dataport_writes__dataport_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 792, 32, NULL,acmgt3__dataport_writes__sampler_l3_read__read);

      intel_perf_query_add_counter_uint64(query, 793, 40, acmgt3__dataport_writes__sysmem_byte_read__max,acmgt3__dataport_writes__sysmem_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 794, 48, acmgt3__dataport_writes__sysmem_byte_write__max,acmgt3__dataport_writes__sysmem_byte_write__read);

      intel_perf_query_add_counter_uint64(query, 762, 56, acmgt3__dataport_writes__gpu_memory_byte_read__max,acmgt3__dataport_writes__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 763, 64, acmgt3__dataport_writes__gpu_memory_byte_write__max,acmgt3__dataport_writes__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 764, 72, percentage_max_float,acmgt3__dataport_writes__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 76, percentage_max_float,acmgt3__dataport_writes__xve_stall__read);

      intel_perf_query_add_counter_uint64(query, 766, 80, acmgt3__dataport_writes__xve_busy__max,acmgt3__dataport_writes__xve_busy__read);

      intel_perf_query_add_counter_float(query, 767, 88, percentage_max_float,acmgt3__dataport_writes__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 768, 96, NULL,acmgt3__dataport_writes__xve_compute_thread_count__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext1";
   query->symbol_name = "Ext1";
   query->guid = "9e92a393-69c4-46fd-b038-e6183364d8c5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18013800 },
         { .reg = 0x00009888, .val = 0x1A010140 },
         { .reg = 0x00009888, .val = 0x18213800 },
         { .reg = 0x00009888, .val = 0x1A210140 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x1A410140 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x1A610140 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x1A810140 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x1AA10140 },
         { .reg = 0x00009888, .val = 0x18C13800 },
         { .reg = 0x00009888, .val = 0x1AC10140 },
         { .reg = 0x00009888, .val = 0x18E13800 },
         { .reg = 0x00009888, .val = 0x1AE10140 },
         { .reg = 0x00009888, .val = 0x02010106 },
         { .reg = 0x00009888, .val = 0x14010180 },
         { .reg = 0x00009888, .val = 0x1601000D },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02210106 },
         { .reg = 0x00009888, .val = 0x12210180 },
         { .reg = 0x00009888, .val = 0x1421000D },
         { .reg = 0x00009888, .val = 0x00210000 },
         { .reg = 0x00009888, .val = 0x02410106 },
         { .reg = 0x00009888, .val = 0x10410180 },
         { .reg = 0x00009888, .val = 0x1241000D },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610106 },
         { .reg = 0x00009888, .val = 0x0E610180 },
         { .reg = 0x00009888, .val = 0x1061000D },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810106 },
         { .reg = 0x00009888, .val = 0x0C810180 },
         { .reg = 0x00009888, .val = 0x0E81000D },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10106 },
         { .reg = 0x00009888, .val = 0x0AA10180 },
         { .reg = 0x00009888, .val = 0x0CA1000D },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02C10106 },
         { .reg = 0x00009888, .val = 0x08C10180 },
         { .reg = 0x00009888, .val = 0x0AC1000D },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02E10106 },
         { .reg = 0x00009888, .val = 0x06E11800 },
         { .reg = 0x00009888, .val = 0x08E1000D },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x000926E4 },
         { .reg = 0x00009888, .val = 0x0209004A },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A2449 },
         { .reg = 0x00009888, .val = 0x040A2492 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x020B4800 },
         { .reg = 0x00009888, .val = 0x040B149B },
         { .reg = 0x00009888, .val = 0x060B0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030202 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext1__avg_gpu_core_frequency__max,acmgt3__ext1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 800, 24, NULL,acmgt3__ext1__gpu_memory_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 801, 32, NULL,acmgt3__ext1__gpu_memory_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2795, 40, NULL,acmgt3__ext1__gpu_memory_read_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2796, 48, NULL,acmgt3__ext1__gpu_memory_read_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 3579, 56, NULL,acmgt3__ext1__gpu_memory_read_sqidi4__read);

      intel_perf_query_add_counter_uint64(query, 3580, 64, NULL,acmgt3__ext1__gpu_memory_read_sqidi5__read);

      intel_perf_query_add_counter_uint64(query, 3581, 72, NULL,acmgt3__ext1__gpu_memory_read_sqidi6__read);

      intel_perf_query_add_counter_uint64(query, 3582, 80, NULL,acmgt3__ext1__gpu_memory_read_sqidi7__read);

      intel_perf_query_add_counter_uint64(query, 802, 88, NULL,acmgt3__ext1__gpu_memory_read__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Ext2";
   query->symbol_name = "Ext2";
   query->guid = "e8621f59-b8d2-4e00-86a9-472e3848973d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18013800 },
         { .reg = 0x00009888, .val = 0x18213800 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x18C13800 },
         { .reg = 0x00009888, .val = 0x18E13800 },
         { .reg = 0x00009888, .val = 0x02010006 },
         { .reg = 0x00009888, .val = 0x0E010004 },
         { .reg = 0x00009888, .val = 0x16010005 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02210006 },
         { .reg = 0x00009888, .val = 0x0C210100 },
         { .reg = 0x00009888, .val = 0x14210140 },
         { .reg = 0x00009888, .val = 0x00210000 },
         { .reg = 0x00009888, .val = 0x02410006 },
         { .reg = 0x00009888, .val = 0x0C410004 },
         { .reg = 0x00009888, .val = 0x14410005 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610006 },
         { .reg = 0x00009888, .val = 0x0A610100 },
         { .reg = 0x00009888, .val = 0x12610140 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810006 },
         { .reg = 0x00009888, .val = 0x0A810004 },
         { .reg = 0x00009888, .val = 0x12810005 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10006 },
         { .reg = 0x00009888, .val = 0x08A10100 },
         { .reg = 0x00009888, .val = 0x10A10140 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02C10006 },
         { .reg = 0x00009888, .val = 0x08C10004 },
         { .reg = 0x00009888, .val = 0x10C10005 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02E10006 },
         { .reg = 0x00009888, .val = 0x06E11000 },
         { .reg = 0x00009888, .val = 0x0EE10140 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x0009029C },
         { .reg = 0x00009888, .val = 0x02093800 },
         { .reg = 0x00009888, .val = 0x0409000A },
         { .reg = 0x00009888, .val = 0x000A2249 },
         { .reg = 0x00009888, .val = 0x020A1292 },
         { .reg = 0x00009888, .val = 0x040A2489 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x020B0053 },
         { .reg = 0x00009888, .val = 0x040B2700 },
         { .reg = 0x00009888, .val = 0x060B0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030442 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030001 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030402 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext2__avg_gpu_core_frequency__max,acmgt3__ext2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 803, 24, NULL,acmgt3__ext2__gpu_memory_byte_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 804, 32, NULL,acmgt3__ext2__gpu_memory_byte_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2787, 40, NULL,acmgt3__ext2__gpu_memory_byte_read_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2788, 48, NULL,acmgt3__ext2__gpu_memory_byte_read_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 3583, 56, NULL,acmgt3__ext2__gpu_memory_byte_read_sqidi4__read);

      intel_perf_query_add_counter_uint64(query, 3584, 64, NULL,acmgt3__ext2__gpu_memory_byte_read_sqidi5__read);

      intel_perf_query_add_counter_uint64(query, 3585, 72, NULL,acmgt3__ext2__gpu_memory_byte_read_sqidi6__read);

      intel_perf_query_add_counter_uint64(query, 3586, 80, NULL,acmgt3__ext2__gpu_memory_byte_read_sqidi7__read);

      intel_perf_query_add_counter_uint64(query, 762, 88, acmgt3__ext2__gpu_memory_byte_read__max,acmgt3__ext2__gpu_memory_byte_read__read);

      intel_perf_query_add_counter_uint64(query, 795, 96, NULL,acmgt3__ext2__gpu_memory_byte_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 796, 104, NULL,acmgt3__ext2__gpu_memory_byte_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2789, 112, NULL,acmgt3__ext2__gpu_memory_byte_write_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2790, 120, NULL,acmgt3__ext2__gpu_memory_byte_write_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 3587, 128, NULL,acmgt3__ext2__gpu_memory_byte_write_sqidi4__read);

      intel_perf_query_add_counter_uint64(query, 3588, 136, NULL,acmgt3__ext2__gpu_memory_byte_write_sqidi5__read);

      intel_perf_query_add_counter_uint64(query, 3589, 144, NULL,acmgt3__ext2__gpu_memory_byte_write_sqidi6__read);

      intel_perf_query_add_counter_uint64(query, 3590, 152, NULL,acmgt3__ext2__gpu_memory_byte_write_sqidi7__read);

      intel_perf_query_add_counter_uint64(query, 763, 160, acmgt3__ext2__gpu_memory_byte_write__max,acmgt3__ext2__gpu_memory_byte_write__read);

      intel_perf_query_add_counter_float(query, 809, 168, NULL,acmgt3__ext2__gpu_memory_byte_read_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 810, 172, NULL,acmgt3__ext2__gpu_memory_byte_read_bw_sqidi1__read);

      intel_perf_query_add_counter_float(query, 2791, 176, NULL,acmgt3__ext2__gpu_memory_byte_read_bw_sqidi2__read);

      intel_perf_query_add_counter_float(query, 2792, 180, NULL,acmgt3__ext2__gpu_memory_byte_read_bw_sqidi3__read);

      intel_perf_query_add_counter_float(query, 3591, 184, NULL,acmgt3__ext2__gpu_memory_byte_read_bw_sqidi4__read);

      intel_perf_query_add_counter_float(query, 3592, 188, NULL,acmgt3__ext2__gpu_memory_byte_read_bw_sqidi5__read);

      intel_perf_query_add_counter_float(query, 3593, 192, NULL,acmgt3__ext2__gpu_memory_byte_read_bw_sqidi6__read);

      intel_perf_query_add_counter_float(query, 3594, 196, NULL,acmgt3__ext2__gpu_memory_byte_read_bw_sqidi7__read);

      intel_perf_query_add_counter_float(query, 813, 200, NULL,acmgt3__ext2__gpu_memory_byte_read_bw__read);

      intel_perf_query_add_counter_float(query, 811, 204, NULL,acmgt3__ext2__gpu_memory_byte_write_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 812, 208, NULL,acmgt3__ext2__gpu_memory_byte_write_bw_sqidi1__read);

      intel_perf_query_add_counter_float(query, 2793, 212, NULL,acmgt3__ext2__gpu_memory_byte_write_bw_sqidi2__read);

      intel_perf_query_add_counter_float(query, 2794, 216, NULL,acmgt3__ext2__gpu_memory_byte_write_bw_sqidi3__read);

      intel_perf_query_add_counter_float(query, 3595, 220, NULL,acmgt3__ext2__gpu_memory_byte_write_bw_sqidi4__read);

      intel_perf_query_add_counter_float(query, 3596, 224, NULL,acmgt3__ext2__gpu_memory_byte_write_bw_sqidi5__read);

      intel_perf_query_add_counter_float(query, 3597, 228, NULL,acmgt3__ext2__gpu_memory_byte_write_bw_sqidi6__read);

      intel_perf_query_add_counter_float(query, 3598, 232, NULL,acmgt3__ext2__gpu_memory_byte_write_bw_sqidi7__read);

      intel_perf_query_add_counter_float(query, 814, 236, NULL,acmgt3__ext2__gpu_memory_byte_write_bw__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext3";
   query->symbol_name = "Ext3";
   query->guid = "12eee9d0-7d4a-495c-a3b5-7d8ab1b0fe02";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x10020011 },
         { .reg = 0x00009888, .val = 0x10220011 },
         { .reg = 0x00009888, .val = 0x10420011 },
         { .reg = 0x00009888, .val = 0x10620011 },
         { .reg = 0x00009888, .val = 0x10820011 },
         { .reg = 0x00009888, .val = 0x10A20011 },
         { .reg = 0x00009888, .val = 0x10C20011 },
         { .reg = 0x00009888, .val = 0x10E20011 },
         { .reg = 0x00009888, .val = 0x0001C000 },
         { .reg = 0x00009888, .val = 0x0E020185 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00213000 },
         { .reg = 0x00009888, .val = 0x0C220185 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00410C00 },
         { .reg = 0x00009888, .val = 0x0A420185 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00610300 },
         { .reg = 0x00009888, .val = 0x08620185 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x008100C0 },
         { .reg = 0x00009888, .val = 0x06820185 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00A10030 },
         { .reg = 0x00009888, .val = 0x04A20185 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00C1000C },
         { .reg = 0x00009888, .val = 0x02C20185 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00E10003 },
         { .reg = 0x00009888, .val = 0x00E20185 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x000926E4 },
         { .reg = 0x00009888, .val = 0x0209004A },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A2449 },
         { .reg = 0x00009888, .val = 0x040A2492 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x020B4800 },
         { .reg = 0x00009888, .val = 0x040B149B },
         { .reg = 0x00009888, .val = 0x060B0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030202 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext3__avg_gpu_core_frequency__max,acmgt3__ext3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 817, 24, NULL,acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 819, 32, NULL,acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2799, 40, NULL,acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2800, 48, NULL,acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 3599, 56, NULL,acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi4__read);

      intel_perf_query_add_counter_uint64(query, 3600, 64, NULL,acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi5__read);

      intel_perf_query_add_counter_uint64(query, 3601, 72, NULL,acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi6__read);

      intel_perf_query_add_counter_uint64(query, 3602, 80, NULL,acmgt3__ext3__gpu_memory_32_b_transaction_read_sqidi7__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext4";
   query->symbol_name = "Ext4";
   query->guid = "59c0b126-b2dc-4a97-818e-741e6355059c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x10020251 },
         { .reg = 0x00009888, .val = 0x10220251 },
         { .reg = 0x00009888, .val = 0x10420251 },
         { .reg = 0x00009888, .val = 0x10620251 },
         { .reg = 0x00009888, .val = 0x10820251 },
         { .reg = 0x00009888, .val = 0x10A20251 },
         { .reg = 0x00009888, .val = 0x10C20251 },
         { .reg = 0x00009888, .val = 0x10E20251 },
         { .reg = 0x00009888, .val = 0x0001C000 },
         { .reg = 0x00009888, .val = 0x0E020207 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00213000 },
         { .reg = 0x00009888, .val = 0x0C220207 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00410C00 },
         { .reg = 0x00009888, .val = 0x0A420207 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00610300 },
         { .reg = 0x00009888, .val = 0x08620207 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x008100C0 },
         { .reg = 0x00009888, .val = 0x06820207 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00A10030 },
         { .reg = 0x00009888, .val = 0x04A20207 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00C1000C },
         { .reg = 0x00009888, .val = 0x02C20207 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00E10003 },
         { .reg = 0x00009888, .val = 0x00E20207 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x000926E4 },
         { .reg = 0x00009888, .val = 0x0209004A },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A2449 },
         { .reg = 0x00009888, .val = 0x040A2492 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x020B4800 },
         { .reg = 0x00009888, .val = 0x040B149B },
         { .reg = 0x00009888, .val = 0x060B0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030202 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext4__avg_gpu_core_frequency__max,acmgt3__ext4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 818, 24, NULL,acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 820, 32, NULL,acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2801, 40, NULL,acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2802, 48, NULL,acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 3603, 56, NULL,acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi4__read);

      intel_perf_query_add_counter_uint64(query, 3604, 64, NULL,acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi5__read);

      intel_perf_query_add_counter_uint64(query, 3605, 72, NULL,acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi6__read);

      intel_perf_query_add_counter_uint64(query, 3606, 80, NULL,acmgt3__ext4__gpu_memory_64_b_transaction_read_sqidi7__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext5";
   query->symbol_name = "Ext5";
   query->guid = "9da5cb85-6e23-4896-8d99-1b8a87dd8930";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1002000C },
         { .reg = 0x00009888, .val = 0x1022000C },
         { .reg = 0x00009888, .val = 0x1042000C },
         { .reg = 0x00009888, .val = 0x1062000C },
         { .reg = 0x00009888, .val = 0x1082000C },
         { .reg = 0x00009888, .val = 0x10A2000C },
         { .reg = 0x00009888, .val = 0x10C2000C },
         { .reg = 0x00009888, .val = 0x10E2000C },
         { .reg = 0x00009888, .val = 0x00018080 },
         { .reg = 0x00009888, .val = 0x06020100 },
         { .reg = 0x00009888, .val = 0x0E020080 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00214040 },
         { .reg = 0x00009888, .val = 0x06220004 },
         { .reg = 0x00009888, .val = 0x0E220002 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00412020 },
         { .reg = 0x00009888, .val = 0x04420100 },
         { .reg = 0x00009888, .val = 0x0C420080 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00611010 },
         { .reg = 0x00009888, .val = 0x04620004 },
         { .reg = 0x00009888, .val = 0x0C620002 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00810808 },
         { .reg = 0x00009888, .val = 0x02820100 },
         { .reg = 0x00009888, .val = 0x0A820080 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00A10404 },
         { .reg = 0x00009888, .val = 0x02A20004 },
         { .reg = 0x00009888, .val = 0x0AA20002 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00C10202 },
         { .reg = 0x00009888, .val = 0x00C20100 },
         { .reg = 0x00009888, .val = 0x08C20080 },
         { .reg = 0x00009888, .val = 0x00E10101 },
         { .reg = 0x00009888, .val = 0x00E20004 },
         { .reg = 0x00009888, .val = 0x08E20002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x0009029C },
         { .reg = 0x00009888, .val = 0x02093800 },
         { .reg = 0x00009888, .val = 0x0409000A },
         { .reg = 0x00009888, .val = 0x000A2249 },
         { .reg = 0x00009888, .val = 0x020A1292 },
         { .reg = 0x00009888, .val = 0x040A2489 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x020B0053 },
         { .reg = 0x00009888, .val = 0x040B2700 },
         { .reg = 0x00009888, .val = 0x060B0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030442 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030001 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030402 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext5__avg_gpu_core_frequency__max,acmgt3__ext5__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 821, 24, NULL,acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 823, 32, NULL,acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2803, 40, NULL,acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2804, 48, NULL,acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 3607, 56, NULL,acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi4__read);

      intel_perf_query_add_counter_uint64(query, 3608, 64, NULL,acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi5__read);

      intel_perf_query_add_counter_uint64(query, 3609, 72, NULL,acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi6__read);

      intel_perf_query_add_counter_uint64(query, 3610, 80, NULL,acmgt3__ext5__gpu_memory_32_b_transaction_write_sqidi7__read);

      intel_perf_query_add_counter_uint64(query, 822, 88, NULL,acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 824, 96, NULL,acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2805, 104, NULL,acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2806, 112, NULL,acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 3611, 120, NULL,acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi4__read);

      intel_perf_query_add_counter_uint64(query, 3612, 128, NULL,acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi5__read);

      intel_perf_query_add_counter_uint64(query, 3613, 136, NULL,acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi6__read);

      intel_perf_query_add_counter_uint64(query, 3614, 144, NULL,acmgt3__ext5__gpu_memory_64_b_transaction_write_sqidi7__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "Ext6";
   query->symbol_name = "Ext6";
   query->guid = "4cd5fd6b-e82a-44fc-a068-4debac13114f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1601034E },
         { .reg = 0x00009888, .val = 0x1A010140 },
         { .reg = 0x00009888, .val = 0x16210340 },
         { .reg = 0x00009888, .val = 0x1A210140 },
         { .reg = 0x00009888, .val = 0x16410340 },
         { .reg = 0x00009888, .val = 0x1A410140 },
         { .reg = 0x00009888, .val = 0x16610340 },
         { .reg = 0x00009888, .val = 0x1A610140 },
         { .reg = 0x00009888, .val = 0x16810340 },
         { .reg = 0x00009888, .val = 0x1A810140 },
         { .reg = 0x00009888, .val = 0x16A10340 },
         { .reg = 0x00009888, .val = 0x1AA10140 },
         { .reg = 0x00009888, .val = 0x16C10340 },
         { .reg = 0x00009888, .val = 0x1AC10140 },
         { .reg = 0x00009888, .val = 0x16E10340 },
         { .reg = 0x00009888, .val = 0x1AE10140 },
         { .reg = 0x00009888, .val = 0x02010100 },
         { .reg = 0x00009888, .val = 0x0E010002 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02210100 },
         { .reg = 0x00009888, .val = 0x0C210080 },
         { .reg = 0x00009888, .val = 0x14210380 },
         { .reg = 0x00009888, .val = 0x00210000 },
         { .reg = 0x00009888, .val = 0x02410100 },
         { .reg = 0x00009888, .val = 0x0C410002 },
         { .reg = 0x00009888, .val = 0x1441000E },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610100 },
         { .reg = 0x00009888, .val = 0x0A610080 },
         { .reg = 0x00009888, .val = 0x12610380 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810100 },
         { .reg = 0x00009888, .val = 0x0A810002 },
         { .reg = 0x00009888, .val = 0x1281000E },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10100 },
         { .reg = 0x00009888, .val = 0x08A10080 },
         { .reg = 0x00009888, .val = 0x10A10380 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02C10100 },
         { .reg = 0x00009888, .val = 0x08C10002 },
         { .reg = 0x00009888, .val = 0x10C1000E },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02E10100 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x0EE10380 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x0009029C },
         { .reg = 0x00009888, .val = 0x02093800 },
         { .reg = 0x00009888, .val = 0x0409000A },
         { .reg = 0x00009888, .val = 0x000A2249 },
         { .reg = 0x00009888, .val = 0x020A1292 },
         { .reg = 0x00009888, .val = 0x040A2489 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x000B4000 },
         { .reg = 0x00009888, .val = 0x020B0053 },
         { .reg = 0x00009888, .val = 0x040B2700 },
         { .reg = 0x00009888, .val = 0x060B0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030442 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030001 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030402 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext6__avg_gpu_core_frequency__max,acmgt3__ext6__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 805, 24, percentage_max_float,acmgt3__ext6__gpu_memory_active_sqidi0__read);

      intel_perf_query_add_counter_float(query, 806, 28, percentage_max_float,acmgt3__ext6__gpu_memory_active_sqidi1__read);

      intel_perf_query_add_counter_float(query, 2807, 32, percentage_max_float,acmgt3__ext6__gpu_memory_active_sqidi2__read);

      intel_perf_query_add_counter_float(query, 2808, 36, percentage_max_float,acmgt3__ext6__gpu_memory_active_sqidi3__read);

      intel_perf_query_add_counter_float(query, 3615, 40, percentage_max_float,acmgt3__ext6__gpu_memory_active_sqidi4__read);

      intel_perf_query_add_counter_float(query, 3616, 44, percentage_max_float,acmgt3__ext6__gpu_memory_active_sqidi5__read);

      intel_perf_query_add_counter_float(query, 3617, 48, percentage_max_float,acmgt3__ext6__gpu_memory_active_sqidi6__read);

      intel_perf_query_add_counter_float(query, 3618, 52, percentage_max_float,acmgt3__ext6__gpu_memory_active_sqidi7__read);

      intel_perf_query_add_counter_float(query, 815, 56, percentage_max_float,acmgt3__ext6__gpu_memory_request_queue_full_sqidi0__read);

      intel_perf_query_add_counter_float(query, 816, 60, percentage_max_float,acmgt3__ext6__gpu_memory_request_queue_full_sqidi1__read);

      intel_perf_query_add_counter_float(query, 2809, 64, percentage_max_float,acmgt3__ext6__gpu_memory_request_queue_full_sqidi2__read);

      intel_perf_query_add_counter_float(query, 2810, 68, percentage_max_float,acmgt3__ext6__gpu_memory_request_queue_full_sqidi3__read);

      intel_perf_query_add_counter_float(query, 3619, 72, percentage_max_float,acmgt3__ext6__gpu_memory_request_queue_full_sqidi4__read);

      intel_perf_query_add_counter_float(query, 3620, 76, percentage_max_float,acmgt3__ext6__gpu_memory_request_queue_full_sqidi5__read);

      intel_perf_query_add_counter_float(query, 3621, 80, percentage_max_float,acmgt3__ext6__gpu_memory_request_queue_full_sqidi6__read);

      intel_perf_query_add_counter_float(query, 3622, 84, percentage_max_float,acmgt3__ext6__gpu_memory_request_queue_full_sqidi7__read);

      intel_perf_query_add_counter_float(query, 2811, 88, percentage_max_float,acmgt3__ext6__gpu_memory_active__read);

      intel_perf_query_add_counter_float(query, 2812, 92, percentage_max_float,acmgt3__ext6__gpu_memory_request_queue_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext7";
   query->symbol_name = "Ext7";
   query->guid = "29eade65-5f7c-4b51-8006-66852e9f2181";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2000 },
         { .reg = 0x00009888, .val = 0x114B2040 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2000 },
         { .reg = 0x00009888, .val = 0x114C2001 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0D0B0040 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0F2B0040 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0040 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0D0C0001 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x0F2C0001 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x136C0001 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020C00 },
         { .reg = 0x00009888, .val = 0x02032100 },
         { .reg = 0x00009888, .val = 0x0204E600 },
         { .reg = 0x00009888, .val = 0x02055508 },
         { .reg = 0x00009888, .val = 0x02060021 },
         { .reg = 0x00009888, .val = 0x00070500 },
         { .reg = 0x00009888, .val = 0x0208AAD9 },
         { .reg = 0x00009888, .val = 0x00090500 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2000 },
         { .reg = 0x00009888, .val = 0x114B2000 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2000 },
         { .reg = 0x00009888, .val = 0x114C2000 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x050B0040 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x072B0040 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x094B0040 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0B6B0040 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x050C0001 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x072C0001 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x094C0001 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0B6C0001 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x00032100 },
         { .reg = 0x00009888, .val = 0x0004E600 },
         { .reg = 0x00009888, .val = 0x00055508 },
         { .reg = 0x00009888, .val = 0x00060021 },
         { .reg = 0x00009888, .val = 0x00070005 },
         { .reg = 0x00009888, .val = 0x0008AAD9 },
         { .reg = 0x00009888, .val = 0x00090005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032821 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x420304E4 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030001 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030E01 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext7__avg_gpu_core_frequency__max,acmgt3__ext7__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 859, 24, NULL,acmgt3__ext7__l3_hit_l3_bank0__read);

      intel_perf_query_add_counter_uint64(query, 860, 32, NULL,acmgt3__ext7__l3_hit_l3_bank1__read);

      intel_perf_query_add_counter_uint64(query, 861, 40, NULL,acmgt3__ext7__l3_hit_l3_bank2__read);

      intel_perf_query_add_counter_uint64(query, 862, 48, NULL,acmgt3__ext7__l3_hit_l3_bank3__read);

      intel_perf_query_add_counter_uint64(query, 863, 56, NULL,acmgt3__ext7__l3_hit_l3_bank4__read);

      intel_perf_query_add_counter_uint64(query, 864, 64, NULL,acmgt3__ext7__l3_hit_l3_bank5__read);

      intel_perf_query_add_counter_uint64(query, 865, 72, NULL,acmgt3__ext7__l3_hit_l3_bank6__read);

      intel_perf_query_add_counter_uint64(query, 866, 80, NULL,acmgt3__ext7__l3_hit_l3_bank7__read);

      intel_perf_query_add_counter_uint64(query, 2667, 88, NULL,acmgt3__ext7__l3_hit_l3_bank8__read);

      intel_perf_query_add_counter_uint64(query, 2668, 96, NULL,acmgt3__ext7__l3_hit_l3_bank9__read);

      intel_perf_query_add_counter_uint64(query, 2669, 104, NULL,acmgt3__ext7__l3_hit_l3_bank10__read);

      intel_perf_query_add_counter_uint64(query, 2670, 112, NULL,acmgt3__ext7__l3_hit_l3_bank11__read);

      intel_perf_query_add_counter_uint64(query, 2671, 120, NULL,acmgt3__ext7__l3_hit_l3_bank12__read);

      intel_perf_query_add_counter_uint64(query, 2672, 128, NULL,acmgt3__ext7__l3_hit_l3_bank13__read);

      intel_perf_query_add_counter_uint64(query, 2673, 136, NULL,acmgt3__ext7__l3_hit_l3_bank14__read);

      intel_perf_query_add_counter_uint64(query, 2674, 144, NULL,acmgt3__ext7__l3_hit_l3_bank15__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext8";
   query->symbol_name = "Ext8";
   query->guid = "859c2807-55de-47e0-aa30-320c23c9373d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2000 },
         { .reg = 0x00009888, .val = 0x114B2000 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2000 },
         { .reg = 0x00009888, .val = 0x114C2000 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x050B0040 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x072B0040 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x094B0040 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0B6B0040 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x050C0001 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x072C0001 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x094C0001 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0B6C0001 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x00032100 },
         { .reg = 0x00009888, .val = 0x0004E600 },
         { .reg = 0x00009888, .val = 0x00055508 },
         { .reg = 0x00009888, .val = 0x00060021 },
         { .reg = 0x00009888, .val = 0x00070005 },
         { .reg = 0x00009888, .val = 0x0008AAD9 },
         { .reg = 0x00009888, .val = 0x00090005 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2000 },
         { .reg = 0x00009888, .val = 0x114B2040 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2000 },
         { .reg = 0x00009888, .val = 0x114C2001 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0D0B0040 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0F2B0040 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0040 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0D0C0001 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x0F2C0001 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x136C0001 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020C00 },
         { .reg = 0x00009888, .val = 0x02032100 },
         { .reg = 0x00009888, .val = 0x0204E600 },
         { .reg = 0x00009888, .val = 0x02055508 },
         { .reg = 0x00009888, .val = 0x02060021 },
         { .reg = 0x00009888, .val = 0x00070500 },
         { .reg = 0x00009888, .val = 0x0208AAD9 },
         { .reg = 0x00009888, .val = 0x00090500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032821 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x420304E4 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030001 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030E01 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext8__avg_gpu_core_frequency__max,acmgt3__ext8__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3623, 24, NULL,acmgt3__ext8__l3_hit_l3_bank16__read);

      intel_perf_query_add_counter_uint64(query, 3624, 32, NULL,acmgt3__ext8__l3_hit_l3_bank17__read);

      intel_perf_query_add_counter_uint64(query, 3625, 40, NULL,acmgt3__ext8__l3_hit_l3_bank18__read);

      intel_perf_query_add_counter_uint64(query, 3626, 48, NULL,acmgt3__ext8__l3_hit_l3_bank19__read);

      intel_perf_query_add_counter_uint64(query, 3627, 56, NULL,acmgt3__ext8__l3_hit_l3_bank20__read);

      intel_perf_query_add_counter_uint64(query, 3628, 64, NULL,acmgt3__ext8__l3_hit_l3_bank21__read);

      intel_perf_query_add_counter_uint64(query, 3629, 72, NULL,acmgt3__ext8__l3_hit_l3_bank22__read);

      intel_perf_query_add_counter_uint64(query, 3630, 80, NULL,acmgt3__ext8__l3_hit_l3_bank23__read);

      intel_perf_query_add_counter_uint64(query, 3631, 88, NULL,acmgt3__ext8__l3_hit_l3_bank24__read);

      intel_perf_query_add_counter_uint64(query, 3632, 96, NULL,acmgt3__ext8__l3_hit_l3_bank25__read);

      intel_perf_query_add_counter_uint64(query, 3633, 104, NULL,acmgt3__ext8__l3_hit_l3_bank26__read);

      intel_perf_query_add_counter_uint64(query, 3634, 112, NULL,acmgt3__ext8__l3_hit_l3_bank27__read);

      intel_perf_query_add_counter_uint64(query, 3635, 120, NULL,acmgt3__ext8__l3_hit_l3_bank28__read);

      intel_perf_query_add_counter_uint64(query, 3636, 128, NULL,acmgt3__ext8__l3_hit_l3_bank29__read);

      intel_perf_query_add_counter_uint64(query, 3637, 136, NULL,acmgt3__ext8__l3_hit_l3_bank30__read);

      intel_perf_query_add_counter_uint64(query, 3638, 144, NULL,acmgt3__ext8__l3_hit_l3_bank31__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext9";
   query->symbol_name = "Ext9";
   query->guid = "c9c488d0-950c-4a0a-a079-b299cd33aa6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1007 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C11C0 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext9__avg_gpu_core_frequency__max,acmgt3__ext9__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 939, 24, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 940, 28, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 941, 32, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 942, 36, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 943, 40, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 944, 44, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 945, 48, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 946, 52, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2635, 56, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2636, 60, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2637, 64, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2638, 68, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2639, 72, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2640, 76, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2641, 80, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2642, 84, percentage_max_float,acmgt3__ext9__l3_input_available_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext10";
   query->symbol_name = "Ext10";
   query->guid = "4599426b-4cfa-442a-8a59-9eda3dd742db";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1007 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C11C0 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext10__avg_gpu_core_frequency__max,acmgt3__ext10__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3639, 24, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3640, 28, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3641, 32, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3642, 36, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3643, 40, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3644, 44, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3645, 48, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3646, 52, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3647, 56, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3648, 60, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3649, 64, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3650, 68, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3651, 72, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3652, 76, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3653, 80, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3654, 84, percentage_max_float,acmgt3__ext10__l3_input_available_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext11";
   query->symbol_name = "Ext11";
   query->guid = "42107330-c266-42b4-aef5-5c2ab410edc4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0180 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0180 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext11__avg_gpu_core_frequency__max,acmgt3__ext11__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 947, 24, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 948, 28, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 949, 32, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 950, 36, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 951, 40, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 952, 44, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 953, 48, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 954, 52, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2643, 56, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2644, 60, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2645, 64, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2646, 68, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2647, 72, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2648, 76, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2649, 80, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2650, 84, percentage_max_float,acmgt3__ext11__l3_output_ready_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext12";
   query->symbol_name = "Ext12";
   query->guid = "a0add3fe-f028-4e6c-b104-c369fabe2b09";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0180 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0180 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1006 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1180 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext12__avg_gpu_core_frequency__max,acmgt3__ext12__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3655, 24, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3656, 28, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3657, 32, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3658, 36, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3659, 40, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3660, 44, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3661, 48, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3662, 52, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3663, 56, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3664, 60, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3665, 64, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3666, 68, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3667, 72, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3668, 76, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3669, 80, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3670, 84, percentage_max_float,acmgt3__ext12__l3_output_ready_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext13";
   query->symbol_name = "Ext13";
   query->guid = "4aeacf49-91c2-41bf-8d9f-49233689e36a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext13__avg_gpu_core_frequency__max,acmgt3__ext13__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 963, 24, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 964, 28, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 965, 32, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 966, 36, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 967, 40, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 968, 44, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 969, 48, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 970, 52, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2715, 56, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2716, 60, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2717, 64, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2718, 68, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2723, 72, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2724, 76, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2725, 80, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2726, 84, percentage_max_float,acmgt3__ext13__l3_busy_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext14";
   query->symbol_name = "Ext14";
   query->guid = "60e3a9fa-b807-4a8d-8a83-88705d05e2c9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext14__avg_gpu_core_frequency__max,acmgt3__ext14__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3671, 24, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3672, 28, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3673, 32, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3674, 36, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3675, 40, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3676, 44, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3677, 48, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3678, 52, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3679, 56, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3680, 60, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3681, 64, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3682, 68, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3683, 72, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3684, 76, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3685, 80, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3686, 84, percentage_max_float,acmgt3__ext14__l3_busy_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext15";
   query->symbol_name = "Ext15";
   query->guid = "0aab7745-1e24-42af-9c96-c640e4f45aa9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B1001 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x070B0080 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x0D2B0080 },
         { .reg = 0x00009888, .val = 0x0F2B0001 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x050C0042 },
         { .reg = 0x00009888, .val = 0x070C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x0B2C0042 },
         { .reg = 0x00009888, .val = 0x0D2C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x114C0042 },
         { .reg = 0x00009888, .val = 0x134C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x02031500 },
         { .reg = 0x00009888, .val = 0x02042A00 },
         { .reg = 0x00009888, .val = 0x00050A80 },
         { .reg = 0x00009888, .val = 0x02051500 },
         { .reg = 0x00009888, .val = 0x0006A015 },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x000701C7 },
         { .reg = 0x00009888, .val = 0x00085A95 },
         { .reg = 0x00009888, .val = 0x02082AFD },
         { .reg = 0x00009888, .val = 0x000901C7 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032941 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x440300E7 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030207 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A031401 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext15__avg_gpu_core_frequency__max,acmgt3__ext15__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 971, 24, percentage_max_float,acmgt3__ext15__l3_stall_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 972, 28, percentage_max_float,acmgt3__ext15__l3_stall_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 973, 32, percentage_max_float,acmgt3__ext15__l3_stall_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 974, 36, percentage_max_float,acmgt3__ext15__l3_stall_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 975, 40, percentage_max_float,acmgt3__ext15__l3_stall_l3_bank4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext16";
   query->symbol_name = "Ext16";
   query->guid = "97670487-9837-4cd2-9475-dea1d28d34fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x096C1001 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x054B0042 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0B6B0042 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x076C0080 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x0002003F },
         { .reg = 0x00009888, .val = 0x00030A80 },
         { .reg = 0x00009888, .val = 0x0004FA95 },
         { .reg = 0x00009888, .val = 0x02040003 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x110B0042 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0D0C0080 },
         { .reg = 0x00009888, .val = 0x0F0C0001 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x02052A00 },
         { .reg = 0x00009888, .val = 0x02060054 },
         { .reg = 0x00009888, .val = 0x00070E00 },
         { .reg = 0x00009888, .val = 0x02082A54 },
         { .reg = 0x00009888, .val = 0x00090E00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030421 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030204 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031CE7 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext16__avg_gpu_core_frequency__max,acmgt3__ext16__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 976, 24, percentage_max_float,acmgt3__ext16__l3_stall_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 977, 28, percentage_max_float,acmgt3__ext16__l3_stall_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 978, 32, percentage_max_float,acmgt3__ext16__l3_stall_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2719, 36, percentage_max_float,acmgt3__ext16__l3_stall_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2720, 40, percentage_max_float,acmgt3__ext16__l3_stall_l3_bank9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext17";
   query->symbol_name = "Ext17";
   query->guid = "2908914a-a836-44ec-a053-36a7ed383462";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x092B1001 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x072B0080 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0D4B0080 },
         { .reg = 0x00009888, .val = 0x0F4B0001 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x052C0042 },
         { .reg = 0x00009888, .val = 0x072C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0B4C0042 },
         { .reg = 0x00009888, .val = 0x0D4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x116C0042 },
         { .reg = 0x00009888, .val = 0x136C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x020200FC },
         { .reg = 0x00009888, .val = 0x00035000 },
         { .reg = 0x00009888, .val = 0x02032A01 },
         { .reg = 0x00009888, .val = 0x0004A000 },
         { .reg = 0x00009888, .val = 0x02042A56 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0006002A },
         { .reg = 0x00009888, .val = 0x00070007 },
         { .reg = 0x00009888, .val = 0x0008AFD5 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00090007 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030421 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603000A },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030200 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext17__avg_gpu_core_frequency__max,acmgt3__ext17__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2721, 24, percentage_max_float,acmgt3__ext17__l3_stall_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2722, 28, percentage_max_float,acmgt3__ext17__l3_stall_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2727, 32, percentage_max_float,acmgt3__ext17__l3_stall_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2728, 36, percentage_max_float,acmgt3__ext17__l3_stall_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2729, 40, percentage_max_float,acmgt3__ext17__l3_stall_l3_bank14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext18";
   query->symbol_name = "Ext18";
   query->guid = "34f121ae-5907-4fe2-a237-a36940510708";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0042 },
         { .reg = 0x00009888, .val = 0x076B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x0004003F },
         { .reg = 0x00009888, .val = 0x00050015 },
         { .reg = 0x00009888, .val = 0x0008002A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x090C1001 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0042 },
         { .reg = 0x00009888, .val = 0x0D0B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0042 },
         { .reg = 0x00009888, .val = 0x132B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x070C0080 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x0D2C0080 },
         { .reg = 0x00009888, .val = 0x0F2C0001 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x0005A000 },
         { .reg = 0x00009888, .val = 0x02050002 },
         { .reg = 0x00009888, .val = 0x00060540 },
         { .reg = 0x00009888, .val = 0x020600A8 },
         { .reg = 0x00009888, .val = 0x00070E38 },
         { .reg = 0x00009888, .val = 0x0008A540 },
         { .reg = 0x00009888, .val = 0x02083F56 },
         { .reg = 0x00009888, .val = 0x00090E38 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008003F },
         { .reg = 0x00009888, .val = 0x00025540 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00031292 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030004 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031080 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030C00 },
         { .reg = 0x00009888, .val = 0x48030060 },
         { .reg = 0x00009888, .val = 0x4A030006 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032529 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext18__avg_gpu_core_frequency__max,acmgt3__ext18__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2730, 24, percentage_max_float,acmgt3__ext18__l3_stall_l3_bank15__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3687, 28, percentage_max_float,acmgt3__ext18__l3_stall_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3688, 32, percentage_max_float,acmgt3__ext18__l3_stall_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3689, 36, percentage_max_float,acmgt3__ext18__l3_stall_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3690, 40, percentage_max_float,acmgt3__ext18__l3_stall_l3_bank19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext19_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext19";
   query->symbol_name = "Ext19";
   query->guid = "f3893d2b-10f8-48f6-8417-6ed748d3dccd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x094B1001 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0080 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0080 },
         { .reg = 0x00009888, .val = 0x0F6B0001 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x054C0042 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0B6C0042 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x0003A015 },
         { .reg = 0x00009888, .val = 0x02030002 },
         { .reg = 0x00009888, .val = 0x0004A56A },
         { .reg = 0x00009888, .val = 0x020400FE },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x110C0042 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x02061500 },
         { .reg = 0x00009888, .val = 0x00077000 },
         { .reg = 0x00009888, .val = 0x02081500 },
         { .reg = 0x00009888, .val = 0x00097000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02022A55 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031080 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030001 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030800 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030421 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext19__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext19__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext19__avg_gpu_core_frequency__max,acmgt3__ext19__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3691, 24, percentage_max_float,acmgt3__ext19__l3_stall_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3692, 28, percentage_max_float,acmgt3__ext19__l3_stall_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3693, 32, percentage_max_float,acmgt3__ext19__l3_stall_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3694, 36, percentage_max_float,acmgt3__ext19__l3_stall_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3695, 40, percentage_max_float,acmgt3__ext19__l3_stall_l3_bank24__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext20_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext20";
   query->symbol_name = "Ext20";
   query->guid = "6b5ae61c-ceab-4202-b550-8430b037566c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x092C1001 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x050B0042 },
         { .reg = 0x00009888, .val = 0x070B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x0B2B0042 },
         { .reg = 0x00009888, .val = 0x0D2B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x114B0042 },
         { .reg = 0x00009888, .val = 0x134B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x072C0080 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0D4C0080 },
         { .reg = 0x00009888, .val = 0x0F4C0001 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x02023F00 },
         { .reg = 0x00009888, .val = 0x02030054 },
         { .reg = 0x00009888, .val = 0x020415A8 },
         { .reg = 0x00009888, .val = 0x0005002A },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x00060A80 },
         { .reg = 0x00009888, .val = 0x00070038 },
         { .reg = 0x00009888, .val = 0x0008F56A },
         { .reg = 0x00009888, .val = 0x02082AAB },
         { .reg = 0x00009888, .val = 0x00090038 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031CE0 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031401 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030421 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext20__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext20__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext20__avg_gpu_core_frequency__max,acmgt3__ext20__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3696, 24, percentage_max_float,acmgt3__ext20__l3_stall_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3697, 28, percentage_max_float,acmgt3__ext20__l3_stall_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3698, 32, percentage_max_float,acmgt3__ext20__l3_stall_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3699, 36, percentage_max_float,acmgt3__ext20__l3_stall_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3700, 40, percentage_max_float,acmgt3__ext20__l3_stall_l3_bank29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext21";
   query->symbol_name = "Ext21";
   query->guid = "66bbd7d1-f6a2-4189-99f7-8e360e28be45";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B6000 },
         { .reg = 0x00009888, .val = 0x092B6000 },
         { .reg = 0x00009888, .val = 0x094B6000 },
         { .reg = 0x00009888, .val = 0x096B6000 },
         { .reg = 0x00009888, .val = 0x090C6000 },
         { .reg = 0x00009888, .val = 0x092C6000 },
         { .reg = 0x00009888, .val = 0x094C6000 },
         { .reg = 0x00009888, .val = 0x096C6000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0005 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0140 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B6000 },
         { .reg = 0x00009888, .val = 0x092B6005 },
         { .reg = 0x00009888, .val = 0x094B6000 },
         { .reg = 0x00009888, .val = 0x096B6000 },
         { .reg = 0x00009888, .val = 0x090C6000 },
         { .reg = 0x00009888, .val = 0x092C6140 },
         { .reg = 0x00009888, .val = 0x094C6000 },
         { .reg = 0x00009888, .val = 0x096C6000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext21__avg_gpu_core_frequency__max,acmgt3__ext21__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 827, 24, NULL,acmgt3__ext21__l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 828, 32, NULL,acmgt3__ext21__l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 829, 40, NULL,acmgt3__ext21__l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 830, 48, NULL,acmgt3__ext21__l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 831, 56, NULL,acmgt3__ext21__l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 832, 64, NULL,acmgt3__ext21__l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 833, 72, NULL,acmgt3__ext21__l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 834, 80, NULL,acmgt3__ext21__l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2651, 88, NULL,acmgt3__ext21__l3_read_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2652, 96, NULL,acmgt3__ext21__l3_read_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2653, 104, NULL,acmgt3__ext21__l3_read_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2654, 112, NULL,acmgt3__ext21__l3_read_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2655, 120, NULL,acmgt3__ext21__l3_read_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2656, 128, NULL,acmgt3__ext21__l3_read_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2657, 136, NULL,acmgt3__ext21__l3_read_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2658, 144, NULL,acmgt3__ext21__l3_read_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext22";
   query->symbol_name = "Ext22";
   query->guid = "b8a9f40b-5906-46b2-ad95-8d36eb9cf998";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B6000 },
         { .reg = 0x00009888, .val = 0x092B6000 },
         { .reg = 0x00009888, .val = 0x094B6000 },
         { .reg = 0x00009888, .val = 0x096B6000 },
         { .reg = 0x00009888, .val = 0x090C6000 },
         { .reg = 0x00009888, .val = 0x092C6000 },
         { .reg = 0x00009888, .val = 0x094C6000 },
         { .reg = 0x00009888, .val = 0x096C6000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0005 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0140 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B6000 },
         { .reg = 0x00009888, .val = 0x092B6005 },
         { .reg = 0x00009888, .val = 0x094B6000 },
         { .reg = 0x00009888, .val = 0x096B6000 },
         { .reg = 0x00009888, .val = 0x090C6000 },
         { .reg = 0x00009888, .val = 0x092C6140 },
         { .reg = 0x00009888, .val = 0x094C6000 },
         { .reg = 0x00009888, .val = 0x096C6000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext22__avg_gpu_core_frequency__max,acmgt3__ext22__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3701, 24, NULL,acmgt3__ext22__l3_read_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3702, 32, NULL,acmgt3__ext22__l3_read_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3703, 40, NULL,acmgt3__ext22__l3_read_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3704, 48, NULL,acmgt3__ext22__l3_read_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3705, 56, NULL,acmgt3__ext22__l3_read_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3706, 64, NULL,acmgt3__ext22__l3_read_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3707, 72, NULL,acmgt3__ext22__l3_read_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3708, 80, NULL,acmgt3__ext22__l3_read_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3709, 88, NULL,acmgt3__ext22__l3_read_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3710, 96, NULL,acmgt3__ext22__l3_read_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3711, 104, NULL,acmgt3__ext22__l3_read_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3712, 112, NULL,acmgt3__ext22__l3_read_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3713, 120, NULL,acmgt3__ext22__l3_read_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3714, 128, NULL,acmgt3__ext22__l3_read_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3715, 136, NULL,acmgt3__ext22__l3_read_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3716, 144, NULL,acmgt3__ext22__l3_read_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext23";
   query->symbol_name = "Ext23";
   query->guid = "e5d242d2-5bf6-4380-8f7c-cb0ff2372733";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0005 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0140 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1005 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1140 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext23__avg_gpu_core_frequency__max,acmgt3__ext23__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 835, 24, NULL,acmgt3__ext23__l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 836, 32, NULL,acmgt3__ext23__l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 837, 40, NULL,acmgt3__ext23__l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 838, 48, NULL,acmgt3__ext23__l3_write_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 839, 56, NULL,acmgt3__ext23__l3_write_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 840, 64, NULL,acmgt3__ext23__l3_write_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 841, 72, NULL,acmgt3__ext23__l3_write_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 842, 80, NULL,acmgt3__ext23__l3_write_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2659, 88, NULL,acmgt3__ext23__l3_write_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2660, 96, NULL,acmgt3__ext23__l3_write_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2661, 104, NULL,acmgt3__ext23__l3_write_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2662, 112, NULL,acmgt3__ext23__l3_write_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2663, 120, NULL,acmgt3__ext23__l3_write_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2664, 128, NULL,acmgt3__ext23__l3_write_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2665, 136, NULL,acmgt3__ext23__l3_write_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2666, 144, NULL,acmgt3__ext23__l3_write_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext24_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext24";
   query->symbol_name = "Ext24";
   query->guid = "b6096e7e-a2c9-4622-9bd6-2169cdebc490";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0005 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0140 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1005 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1140 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext24__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext24__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext24__avg_gpu_core_frequency__max,acmgt3__ext24__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3717, 24, NULL,acmgt3__ext24__l3_write_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3718, 32, NULL,acmgt3__ext24__l3_write_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3719, 40, NULL,acmgt3__ext24__l3_write_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3720, 48, NULL,acmgt3__ext24__l3_write_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3721, 56, NULL,acmgt3__ext24__l3_write_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3722, 64, NULL,acmgt3__ext24__l3_write_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3723, 72, NULL,acmgt3__ext24__l3_write_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3724, 80, NULL,acmgt3__ext24__l3_write_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3725, 88, NULL,acmgt3__ext24__l3_write_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3726, 96, NULL,acmgt3__ext24__l3_write_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3727, 104, NULL,acmgt3__ext24__l3_write_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3728, 112, NULL,acmgt3__ext24__l3_write_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3729, 120, NULL,acmgt3__ext24__l3_write_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3730, 128, NULL,acmgt3__ext24__l3_write_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3731, 136, NULL,acmgt3__ext24__l3_write_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3732, 144, NULL,acmgt3__ext24__l3_write_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext27_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext27";
   query->symbol_name = "Ext27";
   query->guid = "c7b9f883-12c5-470c-ab75-790961e66be6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2002 },
         { .reg = 0x00009888, .val = 0x114B2000 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2080 },
         { .reg = 0x00009888, .val = 0x114C2000 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0002 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0002 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0002 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0080 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0080 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0080 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2000 },
         { .reg = 0x00009888, .val = 0x114B2000 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2000 },
         { .reg = 0x00009888, .val = 0x114C2000 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0002 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0002 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0002 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0080 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0080 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0080 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0080 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext27__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext27__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext27__avg_gpu_core_frequency__max,acmgt3__ext27__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1774, 24, NULL,acmgt3__ext27__l3_miss_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1775, 32, NULL,acmgt3__ext27__l3_miss_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1776, 40, NULL,acmgt3__ext27__l3_miss_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1777, 48, NULL,acmgt3__ext27__l3_miss_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1778, 56, NULL,acmgt3__ext27__l3_miss_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1779, 64, NULL,acmgt3__ext27__l3_miss_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1780, 72, NULL,acmgt3__ext27__l3_miss_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1781, 80, NULL,acmgt3__ext27__l3_miss_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2675, 88, NULL,acmgt3__ext27__l3_miss_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2676, 96, NULL,acmgt3__ext27__l3_miss_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2677, 104, NULL,acmgt3__ext27__l3_miss_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2678, 112, NULL,acmgt3__ext27__l3_miss_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2679, 120, NULL,acmgt3__ext27__l3_miss_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2680, 128, NULL,acmgt3__ext27__l3_miss_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2681, 136, NULL,acmgt3__ext27__l3_miss_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2682, 144, NULL,acmgt3__ext27__l3_miss_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext28";
   query->symbol_name = "Ext28";
   query->guid = "78161cec-30c8-4b7f-aab8-6f13139f454e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2002 },
         { .reg = 0x00009888, .val = 0x114B2000 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2080 },
         { .reg = 0x00009888, .val = 0x114C2000 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0002 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0002 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0002 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0080 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0080 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0080 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x110B2000 },
         { .reg = 0x00009888, .val = 0x112B2000 },
         { .reg = 0x00009888, .val = 0x114B2000 },
         { .reg = 0x00009888, .val = 0x116B2000 },
         { .reg = 0x00009888, .val = 0x110C2000 },
         { .reg = 0x00009888, .val = 0x112C2000 },
         { .reg = 0x00009888, .val = 0x114C2000 },
         { .reg = 0x00009888, .val = 0x116C2000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0002 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0002 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0002 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0080 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0080 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0080 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0080 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext28__avg_gpu_core_frequency__max,acmgt3__ext28__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3733, 24, NULL,acmgt3__ext28__l3_miss_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3734, 32, NULL,acmgt3__ext28__l3_miss_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3735, 40, NULL,acmgt3__ext28__l3_miss_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3736, 48, NULL,acmgt3__ext28__l3_miss_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3737, 56, NULL,acmgt3__ext28__l3_miss_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3738, 64, NULL,acmgt3__ext28__l3_miss_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3739, 72, NULL,acmgt3__ext28__l3_miss_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3740, 80, NULL,acmgt3__ext28__l3_miss_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3741, 88, NULL,acmgt3__ext28__l3_miss_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3742, 96, NULL,acmgt3__ext28__l3_miss_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3743, 104, NULL,acmgt3__ext28__l3_miss_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3744, 112, NULL,acmgt3__ext28__l3_miss_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3745, 120, NULL,acmgt3__ext28__l3_miss_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3746, 128, NULL,acmgt3__ext28__l3_miss_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3747, 136, NULL,acmgt3__ext28__l3_miss_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3748, 144, NULL,acmgt3__ext28__l3_miss_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext29_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext29";
   query->symbol_name = "Ext29";
   query->guid = "e9ba5301-d2ca-4978-af6e-19096ad16dbb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0004 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0100 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext29__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext29__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext29__avg_gpu_core_frequency__max,acmgt3__ext29__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 843, 24, NULL,acmgt3__ext29__dataport_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 844, 32, NULL,acmgt3__ext29__dataport_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 845, 40, NULL,acmgt3__ext29__dataport_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 846, 48, NULL,acmgt3__ext29__dataport_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 847, 56, NULL,acmgt3__ext29__dataport_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 848, 64, NULL,acmgt3__ext29__dataport_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 849, 72, NULL,acmgt3__ext29__dataport_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 850, 80, NULL,acmgt3__ext29__dataport_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2683, 88, NULL,acmgt3__ext29__dataport_l3_read_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2684, 96, NULL,acmgt3__ext29__dataport_l3_read_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2685, 104, NULL,acmgt3__ext29__dataport_l3_read_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2686, 112, NULL,acmgt3__ext29__dataport_l3_read_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2687, 120, NULL,acmgt3__ext29__dataport_l3_read_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2688, 128, NULL,acmgt3__ext29__dataport_l3_read_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2689, 136, NULL,acmgt3__ext29__dataport_l3_read_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2690, 144, NULL,acmgt3__ext29__dataport_l3_read_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext30_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext30";
   query->symbol_name = "Ext30";
   query->guid = "cae0eb96-c3e6-4a3a-83e2-e939146602b5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0004 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0100 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext30__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext30__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext30__avg_gpu_core_frequency__max,acmgt3__ext30__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3749, 24, NULL,acmgt3__ext30__dataport_l3_read_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3750, 32, NULL,acmgt3__ext30__dataport_l3_read_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3751, 40, NULL,acmgt3__ext30__dataport_l3_read_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3752, 48, NULL,acmgt3__ext30__dataport_l3_read_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3753, 56, NULL,acmgt3__ext30__dataport_l3_read_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3754, 64, NULL,acmgt3__ext30__dataport_l3_read_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3755, 72, NULL,acmgt3__ext30__dataport_l3_read_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3756, 80, NULL,acmgt3__ext30__dataport_l3_read_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3757, 88, NULL,acmgt3__ext30__dataport_l3_read_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3758, 96, NULL,acmgt3__ext30__dataport_l3_read_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3759, 104, NULL,acmgt3__ext30__dataport_l3_read_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3760, 112, NULL,acmgt3__ext30__dataport_l3_read_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3761, 120, NULL,acmgt3__ext30__dataport_l3_read_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3762, 128, NULL,acmgt3__ext30__dataport_l3_read_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3763, 136, NULL,acmgt3__ext30__dataport_l3_read_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3764, 144, NULL,acmgt3__ext30__dataport_l3_read_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext31";
   query->symbol_name = "Ext31";
   query->guid = "002950f1-a311-45f9-b88e-2276f42d8f92";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0003 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0003 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0003 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0003 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C00C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C00C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C00C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C00C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0003 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C00C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0003 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0003 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0003 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C00C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C00C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C00C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext31__avg_gpu_core_frequency__max,acmgt3__ext31__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 851, 24, NULL,acmgt3__ext31__dataport_l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 852, 32, NULL,acmgt3__ext31__dataport_l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 853, 40, NULL,acmgt3__ext31__dataport_l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 854, 48, NULL,acmgt3__ext31__dataport_l3_write_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 855, 56, NULL,acmgt3__ext31__dataport_l3_write_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 856, 64, NULL,acmgt3__ext31__dataport_l3_write_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 857, 72, NULL,acmgt3__ext31__dataport_l3_write_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 858, 80, NULL,acmgt3__ext31__dataport_l3_write_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2691, 88, NULL,acmgt3__ext31__dataport_l3_write_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2692, 96, NULL,acmgt3__ext31__dataport_l3_write_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2693, 104, NULL,acmgt3__ext31__dataport_l3_write_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2694, 112, NULL,acmgt3__ext31__dataport_l3_write_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2695, 120, NULL,acmgt3__ext31__dataport_l3_write_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2696, 128, NULL,acmgt3__ext31__dataport_l3_write_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2697, 136, NULL,acmgt3__ext31__dataport_l3_write_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2698, 144, NULL,acmgt3__ext31__dataport_l3_write_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext32_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext32";
   query->symbol_name = "Ext32";
   query->guid = "98b27683-8d7c-4b3e-92d9-3c3683b2cc38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0003 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0003 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0003 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0003 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C00C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C00C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C00C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C00C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0003 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C00C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0003 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0003 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0003 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C00C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C00C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C00C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext32__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext32__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext32__avg_gpu_core_frequency__max,acmgt3__ext32__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3765, 24, NULL,acmgt3__ext32__dataport_l3_write_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3766, 32, NULL,acmgt3__ext32__dataport_l3_write_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3767, 40, NULL,acmgt3__ext32__dataport_l3_write_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3768, 48, NULL,acmgt3__ext32__dataport_l3_write_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3769, 56, NULL,acmgt3__ext32__dataport_l3_write_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3770, 64, NULL,acmgt3__ext32__dataport_l3_write_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3771, 72, NULL,acmgt3__ext32__dataport_l3_write_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3772, 80, NULL,acmgt3__ext32__dataport_l3_write_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3773, 88, NULL,acmgt3__ext32__dataport_l3_write_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3774, 96, NULL,acmgt3__ext32__dataport_l3_write_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3775, 104, NULL,acmgt3__ext32__dataport_l3_write_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3776, 112, NULL,acmgt3__ext32__dataport_l3_write_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3777, 120, NULL,acmgt3__ext32__dataport_l3_write_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3778, 128, NULL,acmgt3__ext32__dataport_l3_write_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3779, 136, NULL,acmgt3__ext32__dataport_l3_write_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3780, 144, NULL,acmgt3__ext32__dataport_l3_write_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext33_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext33";
   query->symbol_name = "Ext33";
   query->guid = "57d03ea4-1959-4b4f-8a32-abaa96246b1d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0007 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C01C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext33__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext33__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext33__avg_gpu_core_frequency__max,acmgt3__ext33__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 883, 24, NULL,acmgt3__ext33__icache_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 884, 32, NULL,acmgt3__ext33__icache_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 885, 40, NULL,acmgt3__ext33__icache_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 886, 48, NULL,acmgt3__ext33__icache_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 887, 56, NULL,acmgt3__ext33__icache_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 888, 64, NULL,acmgt3__ext33__icache_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 889, 72, NULL,acmgt3__ext33__icache_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 890, 80, NULL,acmgt3__ext33__icache_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2699, 88, NULL,acmgt3__ext33__icache_l3_read_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2700, 96, NULL,acmgt3__ext33__icache_l3_read_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2701, 104, NULL,acmgt3__ext33__icache_l3_read_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2702, 112, NULL,acmgt3__ext33__icache_l3_read_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2703, 120, NULL,acmgt3__ext33__icache_l3_read_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2704, 128, NULL,acmgt3__ext33__icache_l3_read_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2705, 136, NULL,acmgt3__ext33__icache_l3_read_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2706, 144, NULL,acmgt3__ext33__icache_l3_read_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext34_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext34";
   query->symbol_name = "Ext34";
   query->guid = "50fbda4a-d852-437a-9178-432d1373111a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0007 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C01C0 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0007 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C01C0 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0007 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0007 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0007 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C01C0 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C01C0 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C01C0 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext34__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext34__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext34__avg_gpu_core_frequency__max,acmgt3__ext34__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3781, 24, NULL,acmgt3__ext34__icache_l3_read_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3782, 32, NULL,acmgt3__ext34__icache_l3_read_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3783, 40, NULL,acmgt3__ext34__icache_l3_read_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3784, 48, NULL,acmgt3__ext34__icache_l3_read_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3785, 56, NULL,acmgt3__ext34__icache_l3_read_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3786, 64, NULL,acmgt3__ext34__icache_l3_read_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3787, 72, NULL,acmgt3__ext34__icache_l3_read_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3788, 80, NULL,acmgt3__ext34__icache_l3_read_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3789, 88, NULL,acmgt3__ext34__icache_l3_read_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3790, 96, NULL,acmgt3__ext34__icache_l3_read_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3791, 104, NULL,acmgt3__ext34__icache_l3_read_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3792, 112, NULL,acmgt3__ext34__icache_l3_read_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3793, 120, NULL,acmgt3__ext34__icache_l3_read_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3794, 128, NULL,acmgt3__ext34__icache_l3_read_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3795, 136, NULL,acmgt3__ext34__icache_l3_read_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3796, 144, NULL,acmgt3__ext34__icache_l3_read_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext35";
   query->symbol_name = "Ext35";
   query->guid = "8357ba54-bded-48d6-bcb4-0f14a2da9b7b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1004 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1100 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext35__avg_gpu_core_frequency__max,acmgt3__ext35__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 931, 24, NULL,acmgt3__ext35__l3_atomic_access_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 932, 32, NULL,acmgt3__ext35__l3_atomic_access_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 933, 40, NULL,acmgt3__ext35__l3_atomic_access_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 934, 48, NULL,acmgt3__ext35__l3_atomic_access_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 935, 56, NULL,acmgt3__ext35__l3_atomic_access_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 936, 64, NULL,acmgt3__ext35__l3_atomic_access_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 937, 72, NULL,acmgt3__ext35__l3_atomic_access_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 938, 80, NULL,acmgt3__ext35__l3_atomic_access_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2779, 88, NULL,acmgt3__ext35__l3_atomic_access_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2780, 96, NULL,acmgt3__ext35__l3_atomic_access_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2781, 104, NULL,acmgt3__ext35__l3_atomic_access_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2782, 112, NULL,acmgt3__ext35__l3_atomic_access_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2783, 120, NULL,acmgt3__ext35__l3_atomic_access_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2784, 128, NULL,acmgt3__ext35__l3_atomic_access_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2785, 136, NULL,acmgt3__ext35__l3_atomic_access_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2786, 144, NULL,acmgt3__ext35__l3_atomic_access_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext36_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext36";
   query->symbol_name = "Ext36";
   query->guid = "32c9e67d-11d7-45f7-ae53-40fe6349cb5c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1000 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1000 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B1000 },
         { .reg = 0x00009888, .val = 0x092B1004 },
         { .reg = 0x00009888, .val = 0x094B1000 },
         { .reg = 0x00009888, .val = 0x096B1000 },
         { .reg = 0x00009888, .val = 0x090C1000 },
         { .reg = 0x00009888, .val = 0x092C1100 },
         { .reg = 0x00009888, .val = 0x094C1000 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext36__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext36__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext36__avg_gpu_core_frequency__max,acmgt3__ext36__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3797, 24, NULL,acmgt3__ext36__l3_atomic_access_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3798, 32, NULL,acmgt3__ext36__l3_atomic_access_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3799, 40, NULL,acmgt3__ext36__l3_atomic_access_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3800, 48, NULL,acmgt3__ext36__l3_atomic_access_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3801, 56, NULL,acmgt3__ext36__l3_atomic_access_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3802, 64, NULL,acmgt3__ext36__l3_atomic_access_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3803, 72, NULL,acmgt3__ext36__l3_atomic_access_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3804, 80, NULL,acmgt3__ext36__l3_atomic_access_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3805, 88, NULL,acmgt3__ext36__l3_atomic_access_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3806, 96, NULL,acmgt3__ext36__l3_atomic_access_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3807, 104, NULL,acmgt3__ext36__l3_atomic_access_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3808, 112, NULL,acmgt3__ext36__l3_atomic_access_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3809, 120, NULL,acmgt3__ext36__l3_atomic_access_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3810, 128, NULL,acmgt3__ext36__l3_atomic_access_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3811, 136, NULL,acmgt3__ext36__l3_atomic_access_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3812, 144, NULL,acmgt3__ext36__l3_atomic_access_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext37_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext37";
   query->symbol_name = "Ext37";
   query->guid = "53553df5-1d80-4d9a-ad30-d72ef4503603";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0180 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0180 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0006 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0180 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext37__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext37__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext37__avg_gpu_core_frequency__max,acmgt3__ext37__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 867, 24, NULL,acmgt3__ext37__sampler_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 868, 32, NULL,acmgt3__ext37__sampler_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 869, 40, NULL,acmgt3__ext37__sampler_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 870, 48, NULL,acmgt3__ext37__sampler_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 871, 56, NULL,acmgt3__ext37__sampler_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 872, 64, NULL,acmgt3__ext37__sampler_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 873, 72, NULL,acmgt3__ext37__sampler_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 874, 80, NULL,acmgt3__ext37__sampler_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2731, 88, NULL,acmgt3__ext37__sampler_l3_read_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2732, 96, NULL,acmgt3__ext37__sampler_l3_read_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2733, 104, NULL,acmgt3__ext37__sampler_l3_read_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2734, 112, NULL,acmgt3__ext37__sampler_l3_read_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2735, 120, NULL,acmgt3__ext37__sampler_l3_read_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2736, 128, NULL,acmgt3__ext37__sampler_l3_read_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2737, 136, NULL,acmgt3__ext37__sampler_l3_read_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2738, 144, NULL,acmgt3__ext37__sampler_l3_read_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext38_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext38";
   query->symbol_name = "Ext38";
   query->guid = "5e66948b-68ab-4208-93f4-44c4fdd1378e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x130B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x112B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x0F4B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x0D6B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x130C0180 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x112C0180 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x0F4C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x0D6C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x092B0006 },
         { .reg = 0x00009888, .val = 0x094B0000 },
         { .reg = 0x00009888, .val = 0x096B0000 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x092C0180 },
         { .reg = 0x00009888, .val = 0x094C0000 },
         { .reg = 0x00009888, .val = 0x096C0000 },
         { .reg = 0x00009888, .val = 0x010B0002 },
         { .reg = 0x00009888, .val = 0x0B0B0006 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0002 },
         { .reg = 0x00009888, .val = 0x074B0006 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x056B0006 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0002 },
         { .reg = 0x00009888, .val = 0x0B0C0180 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0002 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0002 },
         { .reg = 0x00009888, .val = 0x074C0180 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0180 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext38__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext38__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext38__avg_gpu_core_frequency__max,acmgt3__ext38__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3813, 24, NULL,acmgt3__ext38__sampler_l3_read_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3814, 32, NULL,acmgt3__ext38__sampler_l3_read_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3815, 40, NULL,acmgt3__ext38__sampler_l3_read_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3816, 48, NULL,acmgt3__ext38__sampler_l3_read_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3817, 56, NULL,acmgt3__ext38__sampler_l3_read_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3818, 64, NULL,acmgt3__ext38__sampler_l3_read_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3819, 72, NULL,acmgt3__ext38__sampler_l3_read_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3820, 80, NULL,acmgt3__ext38__sampler_l3_read_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3821, 88, NULL,acmgt3__ext38__sampler_l3_read_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3822, 96, NULL,acmgt3__ext38__sampler_l3_read_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3823, 104, NULL,acmgt3__ext38__sampler_l3_read_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3824, 112, NULL,acmgt3__ext38__sampler_l3_read_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3825, 120, NULL,acmgt3__ext38__sampler_l3_read_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3826, 128, NULL,acmgt3__ext38__sampler_l3_read_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3827, 136, NULL,acmgt3__ext38__sampler_l3_read_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3828, 144, NULL,acmgt3__ext38__sampler_l3_read_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext39";
   query->symbol_name = "Ext39";
   query->guid = "0e04ae60-2cb4-47ea-9b5b-111c25dd9929";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext39__avg_gpu_core_frequency__max,acmgt3__ext39__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 915, 24, NULL,acmgt3__ext39__color_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 916, 32, NULL,acmgt3__ext39__color_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 917, 40, NULL,acmgt3__ext39__color_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 918, 48, NULL,acmgt3__ext39__color_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 919, 56, NULL,acmgt3__ext39__color_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 920, 64, NULL,acmgt3__ext39__color_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 921, 72, NULL,acmgt3__ext39__color_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 922, 80, NULL,acmgt3__ext39__color_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2755, 88, NULL,acmgt3__ext39__color_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2756, 96, NULL,acmgt3__ext39__color_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2757, 104, NULL,acmgt3__ext39__color_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2758, 112, NULL,acmgt3__ext39__color_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2759, 120, NULL,acmgt3__ext39__color_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2760, 128, NULL,acmgt3__ext39__color_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2761, 136, NULL,acmgt3__ext39__color_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2762, 144, NULL,acmgt3__ext39__color_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext40_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext40";
   query->symbol_name = "Ext40";
   query->guid = "46c8c61b-b6e3-4ea7-95d9-3f9861d17133";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0004 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0100 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0004 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0004 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0004 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0004 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0100 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0100 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0100 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0100 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext40__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext40__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext40__avg_gpu_core_frequency__max,acmgt3__ext40__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3829, 24, NULL,acmgt3__ext40__color_l3_hit_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3830, 32, NULL,acmgt3__ext40__color_l3_hit_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3831, 40, NULL,acmgt3__ext40__color_l3_hit_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3832, 48, NULL,acmgt3__ext40__color_l3_hit_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3833, 56, NULL,acmgt3__ext40__color_l3_hit_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3834, 64, NULL,acmgt3__ext40__color_l3_hit_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3835, 72, NULL,acmgt3__ext40__color_l3_hit_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3836, 80, NULL,acmgt3__ext40__color_l3_hit_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3837, 88, NULL,acmgt3__ext40__color_l3_hit_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3838, 96, NULL,acmgt3__ext40__color_l3_hit_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3839, 104, NULL,acmgt3__ext40__color_l3_hit_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3840, 112, NULL,acmgt3__ext40__color_l3_hit_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3841, 120, NULL,acmgt3__ext40__color_l3_hit_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3842, 128, NULL,acmgt3__ext40__color_l3_hit_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3843, 136, NULL,acmgt3__ext40__color_l3_hit_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3844, 144, NULL,acmgt3__ext40__color_l3_hit_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext41_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext41";
   query->symbol_name = "Ext41";
   query->guid = "3c7fdece-0f76-411d-a7e3-583c22965830";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext41__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext41__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext41__avg_gpu_core_frequency__max,acmgt3__ext41__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 907, 24, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 908, 32, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 909, 40, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 910, 48, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 911, 56, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 912, 64, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 913, 72, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 914, 80, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2771, 88, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2772, 96, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2773, 104, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2774, 112, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2775, 120, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2776, 128, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2777, 136, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2778, 144, NULL,acmgt3__ext41__dataport_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext42_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext42";
   query->symbol_name = "Ext42";
   query->guid = "2324903a-33fe-4512-870b-2f8316f85ba1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext42__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext42__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext42__avg_gpu_core_frequency__max,acmgt3__ext42__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3845, 24, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3846, 32, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3847, 40, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3848, 48, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3849, 56, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3850, 64, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3851, 72, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3852, 80, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3853, 88, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3854, 96, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3855, 104, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3856, 112, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3857, 120, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3858, 128, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3859, 136, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3860, 144, NULL,acmgt3__ext42__dataport_l3_hit_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext43_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext43";
   query->symbol_name = "Ext43";
   query->guid = "cc074ca3-3e9f-4924-805e-27d69dbf2bbe";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0002 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0080 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0002 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0002 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0002 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0080 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0080 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0080 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0002 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0002 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0002 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0080 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0080 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0080 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0080 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext43__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext43__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext43__avg_gpu_core_frequency__max,acmgt3__ext43__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 891, 24, NULL,acmgt3__ext43__icache_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 892, 32, NULL,acmgt3__ext43__icache_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 893, 40, NULL,acmgt3__ext43__icache_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 894, 48, NULL,acmgt3__ext43__icache_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 895, 56, NULL,acmgt3__ext43__icache_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 896, 64, NULL,acmgt3__ext43__icache_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 897, 72, NULL,acmgt3__ext43__icache_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 898, 80, NULL,acmgt3__ext43__icache_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2707, 88, NULL,acmgt3__ext43__icache_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2708, 96, NULL,acmgt3__ext43__icache_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2709, 104, NULL,acmgt3__ext43__icache_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2710, 112, NULL,acmgt3__ext43__icache_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2711, 120, NULL,acmgt3__ext43__icache_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2712, 128, NULL,acmgt3__ext43__icache_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2713, 136, NULL,acmgt3__ext43__icache_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2714, 144, NULL,acmgt3__ext43__icache_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext44_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext44";
   query->symbol_name = "Ext44";
   query->guid = "3fd7e51e-732e-41c7-8f9d-b81500a438cf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0002 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0080 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0002 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0002 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0002 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0080 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0080 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0080 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0002 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0002 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0002 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0002 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0080 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0080 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0080 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0080 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext44__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext44__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext44__avg_gpu_core_frequency__max,acmgt3__ext44__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3861, 24, NULL,acmgt3__ext44__icache_l3_hit_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3862, 32, NULL,acmgt3__ext44__icache_l3_hit_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3863, 40, NULL,acmgt3__ext44__icache_l3_hit_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3864, 48, NULL,acmgt3__ext44__icache_l3_hit_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3865, 56, NULL,acmgt3__ext44__icache_l3_hit_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3866, 64, NULL,acmgt3__ext44__icache_l3_hit_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3867, 72, NULL,acmgt3__ext44__icache_l3_hit_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3868, 80, NULL,acmgt3__ext44__icache_l3_hit_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3869, 88, NULL,acmgt3__ext44__icache_l3_hit_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3870, 96, NULL,acmgt3__ext44__icache_l3_hit_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3871, 104, NULL,acmgt3__ext44__icache_l3_hit_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3872, 112, NULL,acmgt3__ext44__icache_l3_hit_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3873, 120, NULL,acmgt3__ext44__icache_l3_hit_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3874, 128, NULL,acmgt3__ext44__icache_l3_hit_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3875, 136, NULL,acmgt3__ext44__icache_l3_hit_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3876, 144, NULL,acmgt3__ext44__icache_l3_hit_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext45";
   query->symbol_name = "Ext45";
   query->guid = "d71b7626-b7fb-49ce-b512-22030d666820";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext45__avg_gpu_core_frequency__max,acmgt3__ext45__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 875, 24, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 876, 32, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 877, 40, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 878, 48, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 879, 56, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 880, 64, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 881, 72, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 882, 80, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2739, 88, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2740, 96, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2741, 104, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2742, 112, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2743, 120, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2744, 128, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2745, 136, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2746, 144, NULL,acmgt3__ext45__sampler_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext46_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext46";
   query->symbol_name = "Ext46";
   query->guid = "e87db70a-571a-4cc6-852f-8929fe2404ca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0000 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0000 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0000 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0000 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0000 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext46__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext46__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext46__avg_gpu_core_frequency__max,acmgt3__ext46__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3877, 24, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3878, 32, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3879, 40, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3880, 48, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3881, 56, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3882, 64, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3883, 72, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3884, 80, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3885, 88, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3886, 96, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3887, 104, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3888, 112, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3889, 120, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3890, 128, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3891, 136, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3892, 144, NULL,acmgt3__ext46__sampler_l3_hit_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext47_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext47";
   query->symbol_name = "Ext47";
   query->guid = "f31ec8fe-7987-48fc-ad8e-ebe0b25374b2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0005 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0140 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0005 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0140 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext47__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext47__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext47__avg_gpu_core_frequency__max,acmgt3__ext47__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 923, 24, NULL,acmgt3__ext47__z_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 924, 32, NULL,acmgt3__ext47__z_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 925, 40, NULL,acmgt3__ext47__z_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 926, 48, NULL,acmgt3__ext47__z_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 927, 56, NULL,acmgt3__ext47__z_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 928, 64, NULL,acmgt3__ext47__z_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 929, 72, NULL,acmgt3__ext47__z_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 930, 80, NULL,acmgt3__ext47__z_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2763, 88, NULL,acmgt3__ext47__z_l3_hit_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2764, 96, NULL,acmgt3__ext47__z_l3_hit_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2765, 104, NULL,acmgt3__ext47__z_l3_hit_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2766, 112, NULL,acmgt3__ext47__z_l3_hit_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2767, 120, NULL,acmgt3__ext47__z_l3_hit_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2768, 128, NULL,acmgt3__ext47__z_l3_hit_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2769, 136, NULL,acmgt3__ext47__z_l3_hit_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2770, 144, NULL,acmgt3__ext47__z_l3_hit_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext48_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext48";
   query->symbol_name = "Ext48";
   query->guid = "add101d4-45eb-4394-9c22-66da145c4731";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0005 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0140 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x130B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x0D6B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x130C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0F4C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x0D6C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x02020030 },
         { .reg = 0x00009888, .val = 0x02030048 },
         { .reg = 0x00009888, .val = 0x0204009B },
         { .reg = 0x00009888, .val = 0x02052055 },
         { .reg = 0x00009888, .val = 0x02064800 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x020867AA },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x110B0000 },
         { .reg = 0x00009888, .val = 0x112B0000 },
         { .reg = 0x00009888, .val = 0x114B0000 },
         { .reg = 0x00009888, .val = 0x116B0000 },
         { .reg = 0x00009888, .val = 0x110C0000 },
         { .reg = 0x00009888, .val = 0x112C0000 },
         { .reg = 0x00009888, .val = 0x114C0000 },
         { .reg = 0x00009888, .val = 0x116C0000 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x0B0B0005 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x092B0005 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x074B0005 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x056B0005 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x0B0C0140 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0140 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x074C0140 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x056C0140 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x00030048 },
         { .reg = 0x00009888, .val = 0x0004009B },
         { .reg = 0x00009888, .val = 0x00052055 },
         { .reg = 0x00009888, .val = 0x00064800 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x000867AA },
         { .reg = 0x00009888, .val = 0x000900A0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030024 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030401 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030140 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030E01 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030004 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031C2A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext48__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext48__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext48__avg_gpu_core_frequency__max,acmgt3__ext48__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3893, 24, NULL,acmgt3__ext48__z_l3_hit_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3894, 32, NULL,acmgt3__ext48__z_l3_hit_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3895, 40, NULL,acmgt3__ext48__z_l3_hit_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3896, 48, NULL,acmgt3__ext48__z_l3_hit_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3897, 56, NULL,acmgt3__ext48__z_l3_hit_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3898, 64, NULL,acmgt3__ext48__z_l3_hit_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3899, 72, NULL,acmgt3__ext48__z_l3_hit_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3900, 80, NULL,acmgt3__ext48__z_l3_hit_l3_bank23__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3901, 88, NULL,acmgt3__ext48__z_l3_hit_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3902, 96, NULL,acmgt3__ext48__z_l3_hit_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3903, 104, NULL,acmgt3__ext48__z_l3_hit_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3904, 112, NULL,acmgt3__ext48__z_l3_hit_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3905, 120, NULL,acmgt3__ext48__z_l3_hit_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3906, 128, NULL,acmgt3__ext48__z_l3_hit_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3907, 136, NULL,acmgt3__ext48__z_l3_hit_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 3908, 144, NULL,acmgt3__ext48__z_l3_hit_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext49_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext49";
   query->symbol_name = "Ext49";
   query->guid = "da4046b1-521a-43cb-8328-c219155e59e5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x110B1000 },
         { .reg = 0x00009888, .val = 0x112B1000 },
         { .reg = 0x00009888, .val = 0x114B1000 },
         { .reg = 0x00009888, .val = 0x116B1000 },
         { .reg = 0x00009888, .val = 0x110C1000 },
         { .reg = 0x00009888, .val = 0x112C1000 },
         { .reg = 0x00009888, .val = 0x114C1000 },
         { .reg = 0x00009888, .val = 0x116C1183 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x070B0183 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0B2B0183 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0183 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0183 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x050C0183 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0183 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0D4C0183 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x020200F0 },
         { .reg = 0x00009888, .val = 0x02030A05 },
         { .reg = 0x00009888, .val = 0x0204FA5A },
         { .reg = 0x00009888, .val = 0x000500A0 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x00060A05 },
         { .reg = 0x00009888, .val = 0x00070033 },
         { .reg = 0x00009888, .val = 0x0008F5A5 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00090033 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030421 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031C24 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030027 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031401 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext49__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext49__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext49__avg_gpu_core_frequency__max,acmgt3__ext49__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 955, 24, percentage_max_float,acmgt3__ext49__l3_superq_full_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 956, 28, percentage_max_float,acmgt3__ext49__l3_superq_full_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 957, 32, percentage_max_float,acmgt3__ext49__l3_superq_full_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 958, 36, percentage_max_float,acmgt3__ext49__l3_superq_full_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 959, 40, percentage_max_float,acmgt3__ext49__l3_superq_full_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 960, 44, percentage_max_float,acmgt3__ext49__l3_superq_full_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 961, 48, percentage_max_float,acmgt3__ext49__l3_superq_full_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 962, 52, percentage_max_float,acmgt3__ext49__l3_superq_full_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext50_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext50";
   query->symbol_name = "Ext50";
   query->guid = "fd655951-07ee-4a28-81d1-fbb62cea041e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x110B1000 },
         { .reg = 0x00009888, .val = 0x112B1000 },
         { .reg = 0x00009888, .val = 0x114B1000 },
         { .reg = 0x00009888, .val = 0x116B1000 },
         { .reg = 0x00009888, .val = 0x110C1000 },
         { .reg = 0x00009888, .val = 0x112C1000 },
         { .reg = 0x00009888, .val = 0x114C1000 },
         { .reg = 0x00009888, .val = 0x116C1183 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x070B0183 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0B2B0183 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0183 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0183 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x050C0183 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0183 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0D4C0183 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x020200F0 },
         { .reg = 0x00009888, .val = 0x02030A05 },
         { .reg = 0x00009888, .val = 0x0204FA5A },
         { .reg = 0x00009888, .val = 0x000500A0 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x00060A05 },
         { .reg = 0x00009888, .val = 0x00070033 },
         { .reg = 0x00009888, .val = 0x0008F5A5 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00090033 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030421 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031C24 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030027 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031401 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext50__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext50__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext50__avg_gpu_core_frequency__max,acmgt3__ext50__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2747, 24, percentage_max_float,acmgt3__ext50__l3_superq_full_l3_bank8__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2748, 28, percentage_max_float,acmgt3__ext50__l3_superq_full_l3_bank9__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2749, 32, percentage_max_float,acmgt3__ext50__l3_superq_full_l3_bank10__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2750, 36, percentage_max_float,acmgt3__ext50__l3_superq_full_l3_bank11__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2751, 40, percentage_max_float,acmgt3__ext50__l3_superq_full_l3_bank12__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2752, 44, percentage_max_float,acmgt3__ext50__l3_superq_full_l3_bank13__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2753, 48, percentage_max_float,acmgt3__ext50__l3_superq_full_l3_bank14__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2754, 52, percentage_max_float,acmgt3__ext50__l3_superq_full_l3_bank15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext51_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext51";
   query->symbol_name = "Ext51";
   query->guid = "22089a93-123e-4b18-80c6-5aca789ae5a6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x110B1000 },
         { .reg = 0x00009888, .val = 0x112B1000 },
         { .reg = 0x00009888, .val = 0x114B1000 },
         { .reg = 0x00009888, .val = 0x116B1000 },
         { .reg = 0x00009888, .val = 0x110C1000 },
         { .reg = 0x00009888, .val = 0x112C1000 },
         { .reg = 0x00009888, .val = 0x114C1000 },
         { .reg = 0x00009888, .val = 0x116C1183 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x070B0183 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0B2B0183 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0183 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0183 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x050C0183 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0183 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0D4C0183 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x020200F0 },
         { .reg = 0x00009888, .val = 0x02030A05 },
         { .reg = 0x00009888, .val = 0x0204FA5A },
         { .reg = 0x00009888, .val = 0x000500A0 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x00060A05 },
         { .reg = 0x00009888, .val = 0x00070033 },
         { .reg = 0x00009888, .val = 0x0008F5A5 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00090033 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030421 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031C24 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030027 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031401 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext51__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext51__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext51__avg_gpu_core_frequency__max,acmgt3__ext51__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3909, 24, percentage_max_float,acmgt3__ext51__l3_superq_full_l3_bank16__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3910, 28, percentage_max_float,acmgt3__ext51__l3_superq_full_l3_bank17__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3911, 32, percentage_max_float,acmgt3__ext51__l3_superq_full_l3_bank18__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3912, 36, percentage_max_float,acmgt3__ext51__l3_superq_full_l3_bank19__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3913, 40, percentage_max_float,acmgt3__ext51__l3_superq_full_l3_bank20__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3914, 44, percentage_max_float,acmgt3__ext51__l3_superq_full_l3_bank21__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3915, 48, percentage_max_float,acmgt3__ext51__l3_superq_full_l3_bank22__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 3916, 52, percentage_max_float,acmgt3__ext51__l3_superq_full_l3_bank23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext52_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext52";
   query->symbol_name = "Ext52";
   query->guid = "b8d0b133-7e12-4338-adf3-41034b6a37cd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x110B1000 },
         { .reg = 0x00009888, .val = 0x112B1000 },
         { .reg = 0x00009888, .val = 0x114B1000 },
         { .reg = 0x00009888, .val = 0x116B1000 },
         { .reg = 0x00009888, .val = 0x110C1000 },
         { .reg = 0x00009888, .val = 0x112C1000 },
         { .reg = 0x00009888, .val = 0x114C1000 },
         { .reg = 0x00009888, .val = 0x116C1183 },
         { .reg = 0x00009888, .val = 0x010B0006 },
         { .reg = 0x00009888, .val = 0x070B0183 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x012B0006 },
         { .reg = 0x00009888, .val = 0x0B2B0183 },
         { .reg = 0x00009888, .val = 0x032B0000 },
         { .reg = 0x00009888, .val = 0x014B0006 },
         { .reg = 0x00009888, .val = 0x0F4B0183 },
         { .reg = 0x00009888, .val = 0x034B0000 },
         { .reg = 0x00009888, .val = 0x016B0006 },
         { .reg = 0x00009888, .val = 0x136B0183 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x010C0006 },
         { .reg = 0x00009888, .val = 0x050C0183 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009888, .val = 0x012C0006 },
         { .reg = 0x00009888, .val = 0x092C0183 },
         { .reg = 0x00009888, .val = 0x032C0000 },
         { .reg = 0x00009888, .val = 0x014C0006 },
         { .reg = 0x00009888, .val = 0x0D4C0183 },
         { .reg = 0x00009888, .val = 0x034C0000 },
         { .reg = 0x00009888, .val = 0x016C0006 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x020200F0 },
         { .reg = 0x00009888, .val = 0x02030A05 },
         { .reg = 0x00009888, .val = 0x0204FA5A },
         { .reg = 0x00009888, .val = 0x000500A0 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x00060A05 },
         { .reg = 0x00009888, .val = 0x00070033 },
         { .reg = 0x00009888, .val = 0x0008F5A5 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00090033 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030421 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031C24 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030027 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031401 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40031000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext52__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext52__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext52__avg_gpu_core_frequency__max,acmgt3__ext52__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3917, 24, percentage_max_float,acmgt3__ext52__l3_superq_full_l3_bank24__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3918, 28, percentage_max_float,acmgt3__ext52__l3_superq_full_l3_bank25__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3919, 32, percentage_max_float,acmgt3__ext52__l3_superq_full_l3_bank26__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3920, 36, percentage_max_float,acmgt3__ext52__l3_superq_full_l3_bank27__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3921, 40, percentage_max_float,acmgt3__ext52__l3_superq_full_l3_bank28__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3922, 44, percentage_max_float,acmgt3__ext52__l3_superq_full_l3_bank29__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3923, 48, percentage_max_float,acmgt3__ext52__l3_superq_full_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 3924, 52, percentage_max_float,acmgt3__ext52__l3_superq_full_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext53_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext53";
   query->symbol_name = "Ext53";
   query->guid = "3012f753-92cb-4f10-b5a8-437ac9bb77f1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext53__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext53__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext53__avg_gpu_core_frequency__max,acmgt3__ext53__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1035, 24, NULL,acmgt3__ext53__xve_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1036, 32, NULL,acmgt3__ext53__xve_load_store_cache_read_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext54_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext54";
   query->symbol_name = "Ext54";
   query->guid = "f585cd71-e1d5-4c8c-912e-399f0680c73f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext54__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext54__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext54__avg_gpu_core_frequency__max,acmgt3__ext54__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1037, 24, NULL,acmgt3__ext54__xve_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1038, 32, NULL,acmgt3__ext54__xve_load_store_cache_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext55_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext55";
   query->symbol_name = "Ext55";
   query->guid = "f16c9548-0371-4a07-9522-44f9289e2756";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext55__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext55__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext55__avg_gpu_core_frequency__max,acmgt3__ext55__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1039, 24, NULL,acmgt3__ext55__xve_load_store_cache_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1040, 32, NULL,acmgt3__ext55__xve_load_store_cache_read_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext56_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext56";
   query->symbol_name = "Ext56";
   query->guid = "806924c4-d2c4-4861-b2cd-6d3ce66586cf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext56__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext56__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext56__avg_gpu_core_frequency__max,acmgt3__ext56__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1041, 24, NULL,acmgt3__ext56__xve_load_store_cache_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1042, 32, NULL,acmgt3__ext56__xve_load_store_cache_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext57_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext57";
   query->symbol_name = "Ext57";
   query->guid = "4a24b85d-8511-468b-98ca-9944600637a8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext57__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext57__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext57__avg_gpu_core_frequency__max,acmgt3__ext57__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2595, 24, NULL,acmgt3__ext57__xve_load_store_cache_read_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2596, 32, NULL,acmgt3__ext57__xve_load_store_cache_read_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext58_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext58";
   query->symbol_name = "Ext58";
   query->guid = "3573dd0a-8981-45a3-85e5-7850871e9eca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext58__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext58__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext58__avg_gpu_core_frequency__max,acmgt3__ext58__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2597, 24, NULL,acmgt3__ext58__xve_load_store_cache_read_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2598, 32, NULL,acmgt3__ext58__xve_load_store_cache_read_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext59_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext59";
   query->symbol_name = "Ext59";
   query->guid = "4dbde56d-e0bb-4f3a-b2a7-0a87baf4462e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext59__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext59__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext59__avg_gpu_core_frequency__max,acmgt3__ext59__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2599, 24, NULL,acmgt3__ext59__xve_load_store_cache_read_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2600, 32, NULL,acmgt3__ext59__xve_load_store_cache_read_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext60_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext60";
   query->symbol_name = "Ext60";
   query->guid = "d24e53df-6340-4a08-8449-54d69fdad628";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext60__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext60__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext60__avg_gpu_core_frequency__max,acmgt3__ext60__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2601, 24, NULL,acmgt3__ext60__xve_load_store_cache_read_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2602, 32, NULL,acmgt3__ext60__xve_load_store_cache_read_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext61_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext61";
   query->symbol_name = "Ext61";
   query->guid = "0e24a924-838e-4f24-bb83-1c6aa4e9a602";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext61__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext61__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext61__avg_gpu_core_frequency__max,acmgt3__ext61__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3925, 24, NULL,acmgt3__ext61__xve_load_store_cache_read_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3926, 32, NULL,acmgt3__ext61__xve_load_store_cache_read_message_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext62_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext62";
   query->symbol_name = "Ext62";
   query->guid = "c6f5a056-c412-4425-9877-a2309ebd61bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext62__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext62__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext62__avg_gpu_core_frequency__max,acmgt3__ext62__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3927, 24, NULL,acmgt3__ext62__xve_load_store_cache_read_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3928, 32, NULL,acmgt3__ext62__xve_load_store_cache_read_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext63_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext63";
   query->symbol_name = "Ext63";
   query->guid = "e301dc02-b677-468a-9038-c741af4d91ed";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext63__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext63__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext63__avg_gpu_core_frequency__max,acmgt3__ext63__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3929, 24, NULL,acmgt3__ext63__xve_load_store_cache_read_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3930, 32, NULL,acmgt3__ext63__xve_load_store_cache_read_message_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext64_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext64";
   query->symbol_name = "Ext64";
   query->guid = "e595dd56-de7c-40ff-bea9-b9a15d893b11";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext64__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext64__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext64__avg_gpu_core_frequency__max,acmgt3__ext64__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3931, 24, NULL,acmgt3__ext64__xve_load_store_cache_read_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3932, 32, NULL,acmgt3__ext64__xve_load_store_cache_read_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext65_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext65";
   query->symbol_name = "Ext65";
   query->guid = "7c8329df-0d11-4685-9762-8530d350aa19";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext65__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext65__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext65__avg_gpu_core_frequency__max,acmgt3__ext65__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 3933, 24, NULL,acmgt3__ext65__xve_load_store_cache_read_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 3934, 32, NULL,acmgt3__ext65__xve_load_store_cache_read_message_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext66_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext66";
   query->symbol_name = "Ext66";
   query->guid = "d02aa389-0a8e-42f0-b62b-7b8091f23fe7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext66__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext66__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext66__avg_gpu_core_frequency__max,acmgt3__ext66__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 3935, 24, NULL,acmgt3__ext66__xve_load_store_cache_read_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 3936, 32, NULL,acmgt3__ext66__xve_load_store_cache_read_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext67_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext67";
   query->symbol_name = "Ext67";
   query->guid = "cf345893-06de-44cb-9d0b-3dde2f62947d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext67__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext67__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext67__avg_gpu_core_frequency__max,acmgt3__ext67__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 3937, 24, NULL,acmgt3__ext67__xve_load_store_cache_read_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 3938, 32, NULL,acmgt3__ext67__xve_load_store_cache_read_message_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext68_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext68";
   query->symbol_name = "Ext68";
   query->guid = "23bd55f6-39b5-48af-8cf8-b7c136e60052";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext68__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext68__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext68__avg_gpu_core_frequency__max,acmgt3__ext68__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 3939, 24, NULL,acmgt3__ext68__xve_load_store_cache_read_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 3940, 32, NULL,acmgt3__ext68__xve_load_store_cache_read_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext69_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext69";
   query->symbol_name = "Ext69";
   query->guid = "464517de-6883-4550-86c5-4e084b2a34dc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext69__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext69__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext69__avg_gpu_core_frequency__max,acmgt3__ext69__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1043, 24, NULL,acmgt3__ext69__xve_load_store_cache_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1044, 32, NULL,acmgt3__ext69__xve_load_store_cache_write_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext70_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext70";
   query->symbol_name = "Ext70";
   query->guid = "ccd967c5-9110-4c66-aabb-435114ebf67a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext70__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext70__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext70__avg_gpu_core_frequency__max,acmgt3__ext70__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1045, 24, NULL,acmgt3__ext70__xve_load_store_cache_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1046, 32, NULL,acmgt3__ext70__xve_load_store_cache_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext71_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext71";
   query->symbol_name = "Ext71";
   query->guid = "df75cd02-66d3-41f2-96ad-d53003d4b0b8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext71__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext71__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext71__avg_gpu_core_frequency__max,acmgt3__ext71__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1047, 24, NULL,acmgt3__ext71__xve_load_store_cache_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1048, 32, NULL,acmgt3__ext71__xve_load_store_cache_write_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext72_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext72";
   query->symbol_name = "Ext72";
   query->guid = "adfba67d-3d40-4b20-92a8-70d11c8cffbb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext72__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext72__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext72__avg_gpu_core_frequency__max,acmgt3__ext72__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1049, 24, NULL,acmgt3__ext72__xve_load_store_cache_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1050, 32, NULL,acmgt3__ext72__xve_load_store_cache_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext73_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext73";
   query->symbol_name = "Ext73";
   query->guid = "e13dd0e5-e6ba-4a86-8e32-d5971abd8571";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext73__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext73__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext73__avg_gpu_core_frequency__max,acmgt3__ext73__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2603, 24, NULL,acmgt3__ext73__xve_load_store_cache_write_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2604, 32, NULL,acmgt3__ext73__xve_load_store_cache_write_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext74_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext74";
   query->symbol_name = "Ext74";
   query->guid = "e75ed2f8-19f0-44d0-ae03-ca2a8afbdbc7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext74__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext74__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext74__avg_gpu_core_frequency__max,acmgt3__ext74__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2605, 24, NULL,acmgt3__ext74__xve_load_store_cache_write_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2606, 32, NULL,acmgt3__ext74__xve_load_store_cache_write_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext75_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext75";
   query->symbol_name = "Ext75";
   query->guid = "ddac10e6-c812-4b70-a61e-e6f9e43e47d1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext75__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext75__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext75__avg_gpu_core_frequency__max,acmgt3__ext75__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2607, 24, NULL,acmgt3__ext75__xve_load_store_cache_write_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2608, 32, NULL,acmgt3__ext75__xve_load_store_cache_write_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext76_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext76";
   query->symbol_name = "Ext76";
   query->guid = "8eea86e6-a456-499a-9c4d-dec0dcfd9a8c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext76__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext76__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext76__avg_gpu_core_frequency__max,acmgt3__ext76__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2609, 24, NULL,acmgt3__ext76__xve_load_store_cache_write_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2610, 32, NULL,acmgt3__ext76__xve_load_store_cache_write_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext77_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext77";
   query->symbol_name = "Ext77";
   query->guid = "fedc5df4-a74e-4de8-9296-96571b72092a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext77__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext77__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext77__avg_gpu_core_frequency__max,acmgt3__ext77__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3941, 24, NULL,acmgt3__ext77__xve_load_store_cache_write_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3942, 32, NULL,acmgt3__ext77__xve_load_store_cache_write_message_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext78_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext78";
   query->symbol_name = "Ext78";
   query->guid = "c144b291-ed97-49e3-beab-2bbbf83353e8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext78__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext78__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext78__avg_gpu_core_frequency__max,acmgt3__ext78__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3943, 24, NULL,acmgt3__ext78__xve_load_store_cache_write_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3944, 32, NULL,acmgt3__ext78__xve_load_store_cache_write_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext79_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext79";
   query->symbol_name = "Ext79";
   query->guid = "15f74cc9-7e20-46fa-bbd5-f8f363c99d8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext79__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext79__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext79__avg_gpu_core_frequency__max,acmgt3__ext79__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3945, 24, NULL,acmgt3__ext79__xve_load_store_cache_write_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3946, 32, NULL,acmgt3__ext79__xve_load_store_cache_write_message_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext80_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext80";
   query->symbol_name = "Ext80";
   query->guid = "8a2cc3e1-3df7-4f4a-ba68-73bd1fd0c371";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext80__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext80__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext80__avg_gpu_core_frequency__max,acmgt3__ext80__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3947, 24, NULL,acmgt3__ext80__xve_load_store_cache_write_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3948, 32, NULL,acmgt3__ext80__xve_load_store_cache_write_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext81_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext81";
   query->symbol_name = "Ext81";
   query->guid = "44a0a4a3-e4c3-4a48-bd62-47154ca53a10";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext81__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext81__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext81__avg_gpu_core_frequency__max,acmgt3__ext81__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 3949, 24, NULL,acmgt3__ext81__xve_load_store_cache_write_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 3950, 32, NULL,acmgt3__ext81__xve_load_store_cache_write_message_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext82_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext82";
   query->symbol_name = "Ext82";
   query->guid = "66cd1f83-fe8c-42ef-9b9b-6674a054e256";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext82__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext82__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext82__avg_gpu_core_frequency__max,acmgt3__ext82__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 3951, 24, NULL,acmgt3__ext82__xve_load_store_cache_write_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 3952, 32, NULL,acmgt3__ext82__xve_load_store_cache_write_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext83_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext83";
   query->symbol_name = "Ext83";
   query->guid = "77059291-c7bb-4048-ab5f-ab239b75f8f3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext83__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext83__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext83__avg_gpu_core_frequency__max,acmgt3__ext83__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 3953, 24, NULL,acmgt3__ext83__xve_load_store_cache_write_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 3954, 32, NULL,acmgt3__ext83__xve_load_store_cache_write_message_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext84_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext84";
   query->symbol_name = "Ext84";
   query->guid = "73d8a4d2-dadb-4b04-b368-d21f1587206d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext84__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext84__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext84__avg_gpu_core_frequency__max,acmgt3__ext84__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 3955, 24, NULL,acmgt3__ext84__xve_load_store_cache_write_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 3956, 32, NULL,acmgt3__ext84__xve_load_store_cache_write_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext85_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext85";
   query->symbol_name = "Ext85";
   query->guid = "463c75f3-e572-4f30-a6e0-86635e2e2bb5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x028300AA },
         { .reg = 0x00009888, .val = 0x00840FFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02860055 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x028700AA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext85__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext85__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext85__avg_gpu_core_frequency__max,acmgt3__ext85__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1059, 24, NULL,acmgt3__ext85__xve_load_store_cache_atomic_message_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext86_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext86";
   query->symbol_name = "Ext86";
   query->guid = "41c4ea0d-eeab-4e80-b8ef-e0bfbbf178e4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40FFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext86__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext86__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext86__avg_gpu_core_frequency__max,acmgt3__ext86__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1061, 24, NULL,acmgt3__ext86__xve_load_store_cache_atomic_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext87_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext87";
   query->symbol_name = "Ext87";
   query->guid = "2d7cb182-179b-4d5e-ac1a-0fb084054a79";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40FFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C700AA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x020700AA },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext87__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext87__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext87__avg_gpu_core_frequency__max,acmgt3__ext87__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1063, 24, NULL,acmgt3__ext87__xve_load_store_cache_atomic_message_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext88_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext88";
   query->symbol_name = "Ext88";
   query->guid = "00c41d05-9419-43a2-baa7-157ba0558803";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E300AA },
         { .reg = 0x00009888, .val = 0x00E40FFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E60055 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E700AA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070055 },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext88__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext88__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext88__avg_gpu_core_frequency__max,acmgt3__ext88__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1065, 24, NULL,acmgt3__ext88__xve_load_store_cache_atomic_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext89_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext89";
   query->symbol_name = "Ext89";
   query->guid = "743a4a2d-4cbc-43d2-870e-bb2ccaf85fef";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x038300AA },
         { .reg = 0x00009888, .val = 0x01840FFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x038700AA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x030800AA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext89__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext89__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext89__avg_gpu_core_frequency__max,acmgt3__ext89__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1067, 24, NULL,acmgt3__ext89__xve_load_store_cache_atomic_message_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext90_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext90";
   query->symbol_name = "Ext90";
   query->guid = "2d4814e9-bbbd-474f-8705-e84b358bb946";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40FFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x030800FF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x01010FFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext90__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext90__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext90__avg_gpu_core_frequency__max,acmgt3__ext90__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1069, 24, NULL,acmgt3__ext90__xve_load_store_cache_atomic_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext91_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext91";
   query->symbol_name = "Ext91";
   query->guid = "cdac43dd-b724-412a-bba3-cbca3655f487";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40FFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C700AA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x030700AA },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01020FFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext91__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext91__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext91__avg_gpu_core_frequency__max,acmgt3__ext91__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1071, 24, NULL,acmgt3__ext91__xve_load_store_cache_atomic_message_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext92_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext92";
   query->symbol_name = "Ext92";
   query->guid = "e8486fa5-fdf7-4629-8f90-cf4365951bab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40FFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E700AA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext92__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext92__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext92__avg_gpu_core_frequency__max,acmgt3__ext92__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1073, 24, NULL,acmgt3__ext92__xve_load_store_cache_atomic_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext93_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext93";
   query->symbol_name = "Ext93";
   query->guid = "808604f1-6872-4afa-9b81-47df20489b9f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x028300AA },
         { .reg = 0x00009888, .val = 0x00840FFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02860055 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x028700AA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext93__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext93__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext93__avg_gpu_core_frequency__max,acmgt3__ext93__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2611, 24, NULL,acmgt3__ext93__xve_load_store_cache_atomic_message_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext94_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext94";
   query->symbol_name = "Ext94";
   query->guid = "a06f53f5-e778-48a7-9bcc-d6aaf9fd6e7b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40FFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext94__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext94__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext94__avg_gpu_core_frequency__max,acmgt3__ext94__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2613, 24, NULL,acmgt3__ext94__xve_load_store_cache_atomic_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext95_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext95";
   query->symbol_name = "Ext95";
   query->guid = "cef87716-edfd-4d06-985f-1d04654dcdca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40FFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C700AA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x020700AA },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext95__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext95__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext95__avg_gpu_core_frequency__max,acmgt3__ext95__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2615, 24, NULL,acmgt3__ext95__xve_load_store_cache_atomic_message_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext96_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext96";
   query->symbol_name = "Ext96";
   query->guid = "20e3d0ca-8d80-4590-997c-818512c59e5d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E300AA },
         { .reg = 0x00009888, .val = 0x00E40FFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E60055 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E700AA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070055 },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext96__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext96__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext96__avg_gpu_core_frequency__max,acmgt3__ext96__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2617, 24, NULL,acmgt3__ext96__xve_load_store_cache_atomic_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext97_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext97";
   query->symbol_name = "Ext97";
   query->guid = "37fc43b8-fce9-4eba-a268-aa8242bba6d7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x038300AA },
         { .reg = 0x00009888, .val = 0x01840FFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x038700AA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x030800AA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext97__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext97__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext97__avg_gpu_core_frequency__max,acmgt3__ext97__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2619, 24, NULL,acmgt3__ext97__xve_load_store_cache_atomic_message_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext98_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext98";
   query->symbol_name = "Ext98";
   query->guid = "c962e059-3012-4bd3-98e6-b25c7306bb38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40FFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x030800FF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x01010FFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext98__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext98__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext98__avg_gpu_core_frequency__max,acmgt3__ext98__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2621, 24, NULL,acmgt3__ext98__xve_load_store_cache_atomic_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext99_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext99";
   query->symbol_name = "Ext99";
   query->guid = "5462b931-faf7-4351-abb9-e31a93cd0c67";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40FFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C700AA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x030700AA },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01020FFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext99__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext99__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext99__avg_gpu_core_frequency__max,acmgt3__ext99__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2623, 24, NULL,acmgt3__ext99__xve_load_store_cache_atomic_message_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext100_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext100";
   query->symbol_name = "Ext100";
   query->guid = "2f212e4b-0dab-40cf-9b07-2ca40d7f8c9c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40FFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E700AA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext100__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext100__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext100__avg_gpu_core_frequency__max,acmgt3__ext100__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2625, 24, NULL,acmgt3__ext100__xve_load_store_cache_atomic_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext101_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext101";
   query->symbol_name = "Ext101";
   query->guid = "945c799b-3062-4a46-995a-2527d8c6a550";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x028300AA },
         { .reg = 0x00009888, .val = 0x00840FFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02860055 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x028700AA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext101__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext101__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext101__avg_gpu_core_frequency__max,acmgt3__ext101__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3957, 24, NULL,acmgt3__ext101__xve_load_store_cache_atomic_message_count_xecore16__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext102_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext102";
   query->symbol_name = "Ext102";
   query->guid = "c2e93414-bb8d-43b4-a992-97f998abfefb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40FFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext102__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext102__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext102__avg_gpu_core_frequency__max,acmgt3__ext102__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3958, 24, NULL,acmgt3__ext102__xve_load_store_cache_atomic_message_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext103_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext103";
   query->symbol_name = "Ext103";
   query->guid = "fd4fca73-0631-42d7-89c1-0821a3e0f3c3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40FFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C700AA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x020700AA },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext103__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext103__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext103__avg_gpu_core_frequency__max,acmgt3__ext103__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3959, 24, NULL,acmgt3__ext103__xve_load_store_cache_atomic_message_count_xecore18__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext104_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext104";
   query->symbol_name = "Ext104";
   query->guid = "4c457fa7-afa6-4ab4-8489-e6eb0d7fbfa7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E300AA },
         { .reg = 0x00009888, .val = 0x00E40FFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E60055 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E700AA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070055 },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext104__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext104__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext104__avg_gpu_core_frequency__max,acmgt3__ext104__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3960, 24, NULL,acmgt3__ext104__xve_load_store_cache_atomic_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext105_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext105";
   query->symbol_name = "Ext105";
   query->guid = "218b02bc-7e36-488f-894d-9d97b9501b1a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x038300AA },
         { .reg = 0x00009888, .val = 0x01840FFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x038700AA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x030800AA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext105__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext105__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext105__avg_gpu_core_frequency__max,acmgt3__ext105__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3961, 24, NULL,acmgt3__ext105__xve_load_store_cache_atomic_message_count_xecore20__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext106_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext106";
   query->symbol_name = "Ext106";
   query->guid = "673836b5-04ac-405b-b85c-cbe99892ba08";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40FFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x030800FF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x01010FFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext106__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext106__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext106__avg_gpu_core_frequency__max,acmgt3__ext106__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3962, 24, NULL,acmgt3__ext106__xve_load_store_cache_atomic_message_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext107_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext107";
   query->symbol_name = "Ext107";
   query->guid = "3fa5d581-bfb6-4afd-a13d-9af9db03938f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40FFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C700AA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x030700AA },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01020FFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext107__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext107__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext107__avg_gpu_core_frequency__max,acmgt3__ext107__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3963, 24, NULL,acmgt3__ext107__xve_load_store_cache_atomic_message_count_xecore22__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext108_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext108";
   query->symbol_name = "Ext108";
   query->guid = "516bd2fc-3b14-4700-97e5-988aac08db2a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40FFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E700AA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext108__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext108__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext108__avg_gpu_core_frequency__max,acmgt3__ext108__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3964, 24, NULL,acmgt3__ext108__xve_load_store_cache_atomic_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext109_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext109";
   query->symbol_name = "Ext109";
   query->guid = "6897c9a4-ae80-4001-915e-9201413ae86f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x028300AA },
         { .reg = 0x00009888, .val = 0x00840FFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02860055 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x028700AA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext109__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext109__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext109__avg_gpu_core_frequency__max,acmgt3__ext109__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 3965, 24, NULL,acmgt3__ext109__xve_load_store_cache_atomic_message_count_xecore24__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext110_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext110";
   query->symbol_name = "Ext110";
   query->guid = "3922417a-c9a0-41fd-83ee-1de270990952";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40FFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext110__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext110__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext110__avg_gpu_core_frequency__max,acmgt3__ext110__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 3966, 24, NULL,acmgt3__ext110__xve_load_store_cache_atomic_message_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext111_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext111";
   query->symbol_name = "Ext111";
   query->guid = "2121affe-e3d8-496f-89cf-e9b21861ca69";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40FFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C700AA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x020700AA },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext111__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext111__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext111__avg_gpu_core_frequency__max,acmgt3__ext111__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 3967, 24, NULL,acmgt3__ext111__xve_load_store_cache_atomic_message_count_xecore26__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext112_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext112";
   query->symbol_name = "Ext112";
   query->guid = "68cc12ab-8876-4071-8e2b-ea662e59d9ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E300AA },
         { .reg = 0x00009888, .val = 0x00E40FFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E60055 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E700AA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070055 },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext112__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext112__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext112__avg_gpu_core_frequency__max,acmgt3__ext112__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 3968, 24, NULL,acmgt3__ext112__xve_load_store_cache_atomic_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext113_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext113";
   query->symbol_name = "Ext113";
   query->guid = "35fe4526-b6a1-438c-8592-b98c00bd5776";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x038300AA },
         { .reg = 0x00009888, .val = 0x01840FFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x038700AA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x030800AA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext113__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext113__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext113__avg_gpu_core_frequency__max,acmgt3__ext113__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 3969, 24, NULL,acmgt3__ext113__xve_load_store_cache_atomic_message_count_xecore28__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext114_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext114";
   query->symbol_name = "Ext114";
   query->guid = "1093f7ed-ac49-48d0-ae94-0985d6a59ad9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40FFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x030800FF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x01010FFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext114__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext114__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext114__avg_gpu_core_frequency__max,acmgt3__ext114__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 3970, 24, NULL,acmgt3__ext114__xve_load_store_cache_atomic_message_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext115_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext115";
   query->symbol_name = "Ext115";
   query->guid = "65011d06-3903-4ec8-9e1d-54cb8ad171de";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40FFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C700AA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x030700AA },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01020FFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext115__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext115__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext115__avg_gpu_core_frequency__max,acmgt3__ext115__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 3971, 24, NULL,acmgt3__ext115__xve_load_store_cache_atomic_message_count_xecore30__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext116_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext116";
   query->symbol_name = "Ext116";
   query->guid = "07a01ff3-9f44-4798-93f7-8defeeee8a20";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40FFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E700AA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext116__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext116__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext116__avg_gpu_core_frequency__max,acmgt3__ext116__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 3972, 24, NULL,acmgt3__ext116__xve_load_store_cache_atomic_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext117_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext117";
   query->symbol_name = "Ext117";
   query->guid = "aeb29684-3152-48c8-8cb7-4bc25712605f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext117__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext117__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext117__avg_gpu_core_frequency__max,acmgt3__ext117__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1051, 24, NULL,acmgt3__ext117__xve_load_store_cache_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1052, 32, NULL,acmgt3__ext117__xve_load_store_cache_fence_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext118_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext118";
   query->symbol_name = "Ext118";
   query->guid = "beffa74f-caca-4b88-8f7d-7f01c3bc033b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext118__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext118__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext118__avg_gpu_core_frequency__max,acmgt3__ext118__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1053, 24, NULL,acmgt3__ext118__xve_load_store_cache_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1054, 32, NULL,acmgt3__ext118__xve_load_store_cache_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext119_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext119";
   query->symbol_name = "Ext119";
   query->guid = "415ffe47-ea31-4697-a982-ee90636ed944";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext119__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext119__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext119__avg_gpu_core_frequency__max,acmgt3__ext119__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1055, 24, NULL,acmgt3__ext119__xve_load_store_cache_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1056, 32, NULL,acmgt3__ext119__xve_load_store_cache_fence_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext120_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext120";
   query->symbol_name = "Ext120";
   query->guid = "8112be50-e97f-44dc-b790-bc09eca28009";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext120__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext120__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext120__avg_gpu_core_frequency__max,acmgt3__ext120__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1057, 24, NULL,acmgt3__ext120__xve_load_store_cache_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1058, 32, NULL,acmgt3__ext120__xve_load_store_cache_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext121_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext121";
   query->symbol_name = "Ext121";
   query->guid = "e4c09690-3425-467a-a9cc-4a858c817c0f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext121__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext121__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext121__avg_gpu_core_frequency__max,acmgt3__ext121__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2612, 24, NULL,acmgt3__ext121__xve_load_store_cache_fence_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2614, 32, NULL,acmgt3__ext121__xve_load_store_cache_fence_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext122_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext122";
   query->symbol_name = "Ext122";
   query->guid = "61157f65-aab4-4b3d-b780-658829e378e2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext122__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext122__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext122__avg_gpu_core_frequency__max,acmgt3__ext122__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2616, 24, NULL,acmgt3__ext122__xve_load_store_cache_fence_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2618, 32, NULL,acmgt3__ext122__xve_load_store_cache_fence_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext123_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext123";
   query->symbol_name = "Ext123";
   query->guid = "4a875c0a-59be-4dc2-bdd1-948745fe142e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext123__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext123__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext123__avg_gpu_core_frequency__max,acmgt3__ext123__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2620, 24, NULL,acmgt3__ext123__xve_load_store_cache_fence_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2622, 32, NULL,acmgt3__ext123__xve_load_store_cache_fence_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext124_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext124";
   query->symbol_name = "Ext124";
   query->guid = "8c1d463d-eee4-4f13-b01b-4b120fbbb4ad";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext124__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext124__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext124__avg_gpu_core_frequency__max,acmgt3__ext124__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2624, 24, NULL,acmgt3__ext124__xve_load_store_cache_fence_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2626, 32, NULL,acmgt3__ext124__xve_load_store_cache_fence_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext125_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext125";
   query->symbol_name = "Ext125";
   query->guid = "b6abefa1-e939-431b-8975-e1c687f437b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext125__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext125__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext125__avg_gpu_core_frequency__max,acmgt3__ext125__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3973, 24, NULL,acmgt3__ext125__xve_load_store_cache_fence_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3974, 32, NULL,acmgt3__ext125__xve_load_store_cache_fence_message_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext126_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext126";
   query->symbol_name = "Ext126";
   query->guid = "7aa427eb-754a-4222-b199-d41bc47ad3c8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext126__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext126__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext126__avg_gpu_core_frequency__max,acmgt3__ext126__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3975, 24, NULL,acmgt3__ext126__xve_load_store_cache_fence_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3976, 32, NULL,acmgt3__ext126__xve_load_store_cache_fence_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext127_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext127";
   query->symbol_name = "Ext127";
   query->guid = "101df6ed-1648-43a4-a44a-21440a9df6b1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext127__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext127__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext127__avg_gpu_core_frequency__max,acmgt3__ext127__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3977, 24, NULL,acmgt3__ext127__xve_load_store_cache_fence_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3978, 32, NULL,acmgt3__ext127__xve_load_store_cache_fence_message_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext128_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext128";
   query->symbol_name = "Ext128";
   query->guid = "edf10822-9b87-4c5a-9d08-de730b73783c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext128__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext128__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext128__avg_gpu_core_frequency__max,acmgt3__ext128__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3979, 24, NULL,acmgt3__ext128__xve_load_store_cache_fence_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3980, 32, NULL,acmgt3__ext128__xve_load_store_cache_fence_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext129_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext129";
   query->symbol_name = "Ext129";
   query->guid = "57adc349-a036-4227-bb0b-f35df5cdefc0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext129__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext129__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext129__avg_gpu_core_frequency__max,acmgt3__ext129__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 3981, 24, NULL,acmgt3__ext129__xve_load_store_cache_fence_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 3982, 32, NULL,acmgt3__ext129__xve_load_store_cache_fence_message_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext130_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext130";
   query->symbol_name = "Ext130";
   query->guid = "fa55a401-6330-4838-ba1d-97d99d1b3dab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext130__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext130__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext130__avg_gpu_core_frequency__max,acmgt3__ext130__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 3983, 24, NULL,acmgt3__ext130__xve_load_store_cache_fence_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 3984, 32, NULL,acmgt3__ext130__xve_load_store_cache_fence_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext131_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext131";
   query->symbol_name = "Ext131";
   query->guid = "b3dcbad6-531c-42f5-be91-de0a33aa7a74";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext131__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext131__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext131__avg_gpu_core_frequency__max,acmgt3__ext131__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 3985, 24, NULL,acmgt3__ext131__xve_load_store_cache_fence_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 3986, 32, NULL,acmgt3__ext131__xve_load_store_cache_fence_message_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext132_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext132";
   query->symbol_name = "Ext132";
   query->guid = "f2043fc3-5aae-42c7-aa3f-eabd0cf24b60";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext132__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext132__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext132__avg_gpu_core_frequency__max,acmgt3__ext132__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 3987, 24, NULL,acmgt3__ext132__xve_load_store_cache_fence_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 3988, 32, NULL,acmgt3__ext132__xve_load_store_cache_fence_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext133_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext133";
   query->symbol_name = "Ext133";
   query->guid = "fc8faaca-0410-41a8-baa5-881d1c172763";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext133__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext133__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext133__avg_gpu_core_frequency__max,acmgt3__ext133__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1083, 24, NULL,acmgt3__ext133__xve_slm_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1084, 32, NULL,acmgt3__ext133__xve_slm_read_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext134_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext134";
   query->symbol_name = "Ext134";
   query->guid = "c87b7319-7935-4642-b124-c14ad8fda69d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext134__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext134__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext134__avg_gpu_core_frequency__max,acmgt3__ext134__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1085, 24, NULL,acmgt3__ext134__xve_slm_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1086, 32, NULL,acmgt3__ext134__xve_slm_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext135_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext135";
   query->symbol_name = "Ext135";
   query->guid = "3e0b0511-a1d8-4bfe-b1ef-48520609b5bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext135__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext135__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext135__avg_gpu_core_frequency__max,acmgt3__ext135__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1087, 24, NULL,acmgt3__ext135__xve_slm_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1088, 32, NULL,acmgt3__ext135__xve_slm_read_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext136_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext136";
   query->symbol_name = "Ext136";
   query->guid = "44085566-4f70-4640-aafd-bbc83062552a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext136__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext136__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext136__avg_gpu_core_frequency__max,acmgt3__ext136__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1089, 24, NULL,acmgt3__ext136__xve_slm_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1090, 32, NULL,acmgt3__ext136__xve_slm_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext137_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext137";
   query->symbol_name = "Ext137";
   query->guid = "c7d9a6b4-b939-4eb2-a272-1737f6f3df45";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext137__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext137__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext137__avg_gpu_core_frequency__max,acmgt3__ext137__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2547, 24, NULL,acmgt3__ext137__xve_slm_read_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2548, 32, NULL,acmgt3__ext137__xve_slm_read_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext138_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext138";
   query->symbol_name = "Ext138";
   query->guid = "428b3770-8cd8-469c-b83f-545610b80760";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext138__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext138__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext138__avg_gpu_core_frequency__max,acmgt3__ext138__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2549, 24, NULL,acmgt3__ext138__xve_slm_read_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2550, 32, NULL,acmgt3__ext138__xve_slm_read_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext139_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext139";
   query->symbol_name = "Ext139";
   query->guid = "4e566d7d-9e9d-439a-9d4c-bc2fd96d7716";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext139__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext139__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext139__avg_gpu_core_frequency__max,acmgt3__ext139__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2551, 24, NULL,acmgt3__ext139__xve_slm_read_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2552, 32, NULL,acmgt3__ext139__xve_slm_read_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext140_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext140";
   query->symbol_name = "Ext140";
   query->guid = "9f0b112a-780a-4e61-9d1f-47f90b536d59";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext140__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext140__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext140__avg_gpu_core_frequency__max,acmgt3__ext140__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2553, 24, NULL,acmgt3__ext140__xve_slm_read_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2554, 32, NULL,acmgt3__ext140__xve_slm_read_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext141_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext141";
   query->symbol_name = "Ext141";
   query->guid = "854fb71e-5727-4f1d-9384-52b395a4d8a3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext141__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext141__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext141__avg_gpu_core_frequency__max,acmgt3__ext141__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 3989, 24, NULL,acmgt3__ext141__xve_slm_read_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 3990, 32, NULL,acmgt3__ext141__xve_slm_read_message_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext142_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext142";
   query->symbol_name = "Ext142";
   query->guid = "fe0561e1-8d92-495c-b849-4d9707cf5682";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext142__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext142__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext142__avg_gpu_core_frequency__max,acmgt3__ext142__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 3991, 24, NULL,acmgt3__ext142__xve_slm_read_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 3992, 32, NULL,acmgt3__ext142__xve_slm_read_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext143_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext143";
   query->symbol_name = "Ext143";
   query->guid = "46dbfe20-297f-437b-a33f-55e3a55b3f49";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext143__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext143__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext143__avg_gpu_core_frequency__max,acmgt3__ext143__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 3993, 24, NULL,acmgt3__ext143__xve_slm_read_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 3994, 32, NULL,acmgt3__ext143__xve_slm_read_message_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext144_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext144";
   query->symbol_name = "Ext144";
   query->guid = "771f932d-6d5d-455a-ac07-95b7944cf0f3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext144__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext144__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext144__avg_gpu_core_frequency__max,acmgt3__ext144__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 3995, 24, NULL,acmgt3__ext144__xve_slm_read_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 3996, 32, NULL,acmgt3__ext144__xve_slm_read_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext145_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext145";
   query->symbol_name = "Ext145";
   query->guid = "8798172d-cd55-4b8b-bdd4-b0e4506f5814";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890004 },
         { .reg = 0x00009888, .val = 0x08890414 },
         { .reg = 0x00009888, .val = 0x0A890824 },
         { .reg = 0x00009888, .val = 0x0C890C34 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90004 },
         { .reg = 0x00009888, .val = 0x10A90414 },
         { .reg = 0x00009888, .val = 0x12A90824 },
         { .reg = 0x00009888, .val = 0x14A90C34 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext145__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext145__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext145__avg_gpu_core_frequency__max,acmgt3__ext145__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 3997, 24, NULL,acmgt3__ext145__xve_slm_read_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 3998, 32, NULL,acmgt3__ext145__xve_slm_read_message_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext146_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext146";
   query->symbol_name = "Ext146";
   query->guid = "cdb10de1-e17b-4a8b-b90c-19de2c4759f9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90004 },
         { .reg = 0x00009888, .val = 0x08C90414 },
         { .reg = 0x00009888, .val = 0x0AC90824 },
         { .reg = 0x00009888, .val = 0x0CC90C34 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90004 },
         { .reg = 0x00009888, .val = 0x10E90414 },
         { .reg = 0x00009888, .val = 0x12E90824 },
         { .reg = 0x00009888, .val = 0x14E90C34 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext146__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext146__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext146__avg_gpu_core_frequency__max,acmgt3__ext146__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 3999, 24, NULL,acmgt3__ext146__xve_slm_read_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4000, 32, NULL,acmgt3__ext146__xve_slm_read_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext147_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext147";
   query->symbol_name = "Ext147";
   query->guid = "23705ec8-4cd3-4907-a1ad-3fe56529d8ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890004 },
         { .reg = 0x00009888, .val = 0x09890414 },
         { .reg = 0x00009888, .val = 0x0B890824 },
         { .reg = 0x00009888, .val = 0x0D890C34 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90004 },
         { .reg = 0x00009888, .val = 0x11A90414 },
         { .reg = 0x00009888, .val = 0x13A90824 },
         { .reg = 0x00009888, .val = 0x15A90C34 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext147__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext147__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext147__avg_gpu_core_frequency__max,acmgt3__ext147__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4001, 24, NULL,acmgt3__ext147__xve_slm_read_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4002, 32, NULL,acmgt3__ext147__xve_slm_read_message_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext148_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext148";
   query->symbol_name = "Ext148";
   query->guid = "dbed477b-2c30-478d-b3fa-b5615416b1af";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90004 },
         { .reg = 0x00009888, .val = 0x09C90414 },
         { .reg = 0x00009888, .val = 0x0BC90824 },
         { .reg = 0x00009888, .val = 0x0DC90C34 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90004 },
         { .reg = 0x00009888, .val = 0x11E90414 },
         { .reg = 0x00009888, .val = 0x13E90824 },
         { .reg = 0x00009888, .val = 0x15E90C34 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext148__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext148__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext148__avg_gpu_core_frequency__max,acmgt3__ext148__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4003, 24, NULL,acmgt3__ext148__xve_slm_read_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4004, 32, NULL,acmgt3__ext148__xve_slm_read_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext149_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext149";
   query->symbol_name = "Ext149";
   query->guid = "8f6adfed-5fbc-42c7-80f2-30904a388408";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext149__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext149__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext149__avg_gpu_core_frequency__max,acmgt3__ext149__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1091, 24, NULL,acmgt3__ext149__xve_slm_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1092, 32, NULL,acmgt3__ext149__xve_slm_write_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext150_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext150";
   query->symbol_name = "Ext150";
   query->guid = "aed081c7-ab5e-46c5-bedf-91477e538dd6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext150__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext150__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext150__avg_gpu_core_frequency__max,acmgt3__ext150__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1093, 24, NULL,acmgt3__ext150__xve_slm_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1094, 32, NULL,acmgt3__ext150__xve_slm_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext151_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext151";
   query->symbol_name = "Ext151";
   query->guid = "a09e1665-c5dd-4819-81fa-04a797f9de26";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext151__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext151__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext151__avg_gpu_core_frequency__max,acmgt3__ext151__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1095, 24, NULL,acmgt3__ext151__xve_slm_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1096, 32, NULL,acmgt3__ext151__xve_slm_write_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext152_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext152";
   query->symbol_name = "Ext152";
   query->guid = "c963fbd4-f12b-4c8b-b5a8-03aff5190950";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext152__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext152__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext152__avg_gpu_core_frequency__max,acmgt3__ext152__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1097, 24, NULL,acmgt3__ext152__xve_slm_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1098, 32, NULL,acmgt3__ext152__xve_slm_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext153_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext153";
   query->symbol_name = "Ext153";
   query->guid = "a7cf7aba-86a2-45dd-baa3-e877df9883f3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext153__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext153__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext153__avg_gpu_core_frequency__max,acmgt3__ext153__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2555, 24, NULL,acmgt3__ext153__xve_slm_write_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2556, 32, NULL,acmgt3__ext153__xve_slm_write_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext154_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext154";
   query->symbol_name = "Ext154";
   query->guid = "5207e446-2d9c-4d66-8afa-2f474c9d403a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext154__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext154__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext154__avg_gpu_core_frequency__max,acmgt3__ext154__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2557, 24, NULL,acmgt3__ext154__xve_slm_write_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2558, 32, NULL,acmgt3__ext154__xve_slm_write_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext155_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext155";
   query->symbol_name = "Ext155";
   query->guid = "446e638a-6570-4b0a-b980-15071ca6a136";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext155__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext155__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext155__avg_gpu_core_frequency__max,acmgt3__ext155__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2559, 24, NULL,acmgt3__ext155__xve_slm_write_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2560, 32, NULL,acmgt3__ext155__xve_slm_write_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext156_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext156";
   query->symbol_name = "Ext156";
   query->guid = "4c6764e2-9e79-4cb7-ae35-03459c6d06e4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext156__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext156__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext156__avg_gpu_core_frequency__max,acmgt3__ext156__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2561, 24, NULL,acmgt3__ext156__xve_slm_write_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2562, 32, NULL,acmgt3__ext156__xve_slm_write_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext157_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext157";
   query->symbol_name = "Ext157";
   query->guid = "c148c5e1-7709-4fbe-ae06-1f23721141c9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext157__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext157__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext157__avg_gpu_core_frequency__max,acmgt3__ext157__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4005, 24, NULL,acmgt3__ext157__xve_slm_write_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4006, 32, NULL,acmgt3__ext157__xve_slm_write_message_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext158_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext158";
   query->symbol_name = "Ext158";
   query->guid = "a733cb3b-6a08-44a2-b732-11e7ba701391";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext158__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext158__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext158__avg_gpu_core_frequency__max,acmgt3__ext158__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4007, 24, NULL,acmgt3__ext158__xve_slm_write_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4008, 32, NULL,acmgt3__ext158__xve_slm_write_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext159_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext159";
   query->symbol_name = "Ext159";
   query->guid = "15186c13-8523-470b-bda5-363a5b4e001a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext159__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext159__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext159__avg_gpu_core_frequency__max,acmgt3__ext159__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4009, 24, NULL,acmgt3__ext159__xve_slm_write_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4010, 32, NULL,acmgt3__ext159__xve_slm_write_message_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext160_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext160";
   query->symbol_name = "Ext160";
   query->guid = "df25a2c1-8375-4034-8ad9-f291c80a3f9c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext160__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext160__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext160__avg_gpu_core_frequency__max,acmgt3__ext160__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4011, 24, NULL,acmgt3__ext160__xve_slm_write_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4012, 32, NULL,acmgt3__ext160__xve_slm_write_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext161_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext161";
   query->symbol_name = "Ext161";
   query->guid = "97bb9d99-1be8-4add-a674-50795062f1a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x06890003 },
         { .reg = 0x00009888, .val = 0x08890413 },
         { .reg = 0x00009888, .val = 0x0A890823 },
         { .reg = 0x00009888, .val = 0x0C890C33 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90003 },
         { .reg = 0x00009888, .val = 0x10A90413 },
         { .reg = 0x00009888, .val = 0x12A90823 },
         { .reg = 0x00009888, .val = 0x14A90C33 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext161__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext161__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext161__avg_gpu_core_frequency__max,acmgt3__ext161__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4013, 24, NULL,acmgt3__ext161__xve_slm_write_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4014, 32, NULL,acmgt3__ext161__xve_slm_write_message_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext162_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext162";
   query->symbol_name = "Ext162";
   query->guid = "725d052c-1ead-4fd5-96fc-68d7db607dc7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x06C90003 },
         { .reg = 0x00009888, .val = 0x08C90413 },
         { .reg = 0x00009888, .val = 0x0AC90823 },
         { .reg = 0x00009888, .val = 0x0CC90C33 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x0EE90003 },
         { .reg = 0x00009888, .val = 0x10E90413 },
         { .reg = 0x00009888, .val = 0x12E90823 },
         { .reg = 0x00009888, .val = 0x14E90C33 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext162__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext162__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext162__avg_gpu_core_frequency__max,acmgt3__ext162__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4015, 24, NULL,acmgt3__ext162__xve_slm_write_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4016, 32, NULL,acmgt3__ext162__xve_slm_write_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext163_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext163";
   query->symbol_name = "Ext163";
   query->guid = "63a891bb-dcce-41a0-8c54-cddd68cd298b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x07890003 },
         { .reg = 0x00009888, .val = 0x09890413 },
         { .reg = 0x00009888, .val = 0x0B890823 },
         { .reg = 0x00009888, .val = 0x0D890C33 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90003 },
         { .reg = 0x00009888, .val = 0x11A90413 },
         { .reg = 0x00009888, .val = 0x13A90823 },
         { .reg = 0x00009888, .val = 0x15A90C33 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext163__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext163__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext163__avg_gpu_core_frequency__max,acmgt3__ext163__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4017, 24, NULL,acmgt3__ext163__xve_slm_write_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4018, 32, NULL,acmgt3__ext163__xve_slm_write_message_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext164_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext164";
   query->symbol_name = "Ext164";
   query->guid = "0d6008ca-0cbb-4be9-a615-e9ecec99f5d7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x07C90003 },
         { .reg = 0x00009888, .val = 0x09C90413 },
         { .reg = 0x00009888, .val = 0x0BC90823 },
         { .reg = 0x00009888, .val = 0x0DC90C33 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x0FE90003 },
         { .reg = 0x00009888, .val = 0x11E90413 },
         { .reg = 0x00009888, .val = 0x13E90823 },
         { .reg = 0x00009888, .val = 0x15E90C33 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext164__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext164__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext164__avg_gpu_core_frequency__max,acmgt3__ext164__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4019, 24, NULL,acmgt3__ext164__xve_slm_write_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4020, 32, NULL,acmgt3__ext164__xve_slm_write_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext165_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext165";
   query->symbol_name = "Ext165";
   query->guid = "7df82e88-2ee2-4fbc-8adb-d727d7642c39";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x028300AA },
         { .reg = 0x00009888, .val = 0x00840FFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02860055 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x028700AA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext165__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext165__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext165__avg_gpu_core_frequency__max,acmgt3__ext165__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1107, 24, NULL,acmgt3__ext165__xve_slm_atomic_message_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext166_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext166";
   query->symbol_name = "Ext166";
   query->guid = "3e04e13c-9dea-45d0-ae38-0596b159f871";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40FFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext166__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext166__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext166__avg_gpu_core_frequency__max,acmgt3__ext166__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1108, 24, NULL,acmgt3__ext166__xve_slm_atomic_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext167_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext167";
   query->symbol_name = "Ext167";
   query->guid = "47678de2-1d55-41be-9fce-6f7d5e771f87";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40FFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C700AA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x020700AA },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext167__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext167__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext167__avg_gpu_core_frequency__max,acmgt3__ext167__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1109, 24, NULL,acmgt3__ext167__xve_slm_atomic_message_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext168_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext168";
   query->symbol_name = "Ext168";
   query->guid = "0dbdebc2-4202-460e-941b-d3b4a321f450";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E300AA },
         { .reg = 0x00009888, .val = 0x00E40FFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E60055 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E700AA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070055 },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext168__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext168__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext168__avg_gpu_core_frequency__max,acmgt3__ext168__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1110, 24, NULL,acmgt3__ext168__xve_slm_atomic_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext169_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext169";
   query->symbol_name = "Ext169";
   query->guid = "406d841d-d415-434e-94d4-5756af4a9e37";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x038300AA },
         { .reg = 0x00009888, .val = 0x01840FFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x038700AA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x030800AA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext169__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext169__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext169__avg_gpu_core_frequency__max,acmgt3__ext169__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1111, 24, NULL,acmgt3__ext169__xve_slm_atomic_message_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext170_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext170";
   query->symbol_name = "Ext170";
   query->guid = "3e3ce4f4-1ead-4705-8243-a7786c061089";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40FFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x030800FF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x01010FFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext170__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext170__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext170__avg_gpu_core_frequency__max,acmgt3__ext170__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1112, 24, NULL,acmgt3__ext170__xve_slm_atomic_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext171_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext171";
   query->symbol_name = "Ext171";
   query->guid = "e9e8cc3e-2c88-4b2c-a8d2-67f00c9699a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40FFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C700AA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x030700AA },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01020FFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext171__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext171__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext171__avg_gpu_core_frequency__max,acmgt3__ext171__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1113, 24, NULL,acmgt3__ext171__xve_slm_atomic_message_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext172_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext172";
   query->symbol_name = "Ext172";
   query->guid = "23e25067-e274-4172-a380-e032c4d685d6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40FFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E700AA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext172__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext172__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext172__avg_gpu_core_frequency__max,acmgt3__ext172__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1114, 24, NULL,acmgt3__ext172__xve_slm_atomic_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext173_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext173";
   query->symbol_name = "Ext173";
   query->guid = "21d3e3ca-2381-47d9-bf55-0aa699ebac4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x028300AA },
         { .reg = 0x00009888, .val = 0x00840FFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02860055 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x028700AA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext173__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext173__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext173__avg_gpu_core_frequency__max,acmgt3__ext173__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2563, 24, NULL,acmgt3__ext173__xve_slm_atomic_message_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext174_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext174";
   query->symbol_name = "Ext174";
   query->guid = "0b4f4666-f7af-484e-8f18-68762db73ad7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40FFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext174__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext174__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext174__avg_gpu_core_frequency__max,acmgt3__ext174__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2565, 24, NULL,acmgt3__ext174__xve_slm_atomic_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext175_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext175";
   query->symbol_name = "Ext175";
   query->guid = "27c6aca7-31ed-477e-a48a-34fefb2a02a8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40FFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C700AA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x020700AA },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext175__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext175__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext175__avg_gpu_core_frequency__max,acmgt3__ext175__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2567, 24, NULL,acmgt3__ext175__xve_slm_atomic_message_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext176_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext176";
   query->symbol_name = "Ext176";
   query->guid = "813597c0-4e8c-408c-8410-e6e5ece2b810";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E300AA },
         { .reg = 0x00009888, .val = 0x00E40FFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E60055 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E700AA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070055 },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext176__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext176__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext176__avg_gpu_core_frequency__max,acmgt3__ext176__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2569, 24, NULL,acmgt3__ext176__xve_slm_atomic_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext177_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext177";
   query->symbol_name = "Ext177";
   query->guid = "a31bccd0-3d2c-4697-8c8b-2e4c0920b30b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x038300AA },
         { .reg = 0x00009888, .val = 0x01840FFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x038700AA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x030800AA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext177__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext177__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext177__avg_gpu_core_frequency__max,acmgt3__ext177__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2571, 24, NULL,acmgt3__ext177__xve_slm_atomic_message_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext178_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext178";
   query->symbol_name = "Ext178";
   query->guid = "d936d62e-18f5-4216-84a6-e419ae29b3c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40FFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x030800FF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x01010FFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext178__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext178__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext178__avg_gpu_core_frequency__max,acmgt3__ext178__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2573, 24, NULL,acmgt3__ext178__xve_slm_atomic_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext179_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext179";
   query->symbol_name = "Ext179";
   query->guid = "49b08c39-b26e-42e8-99b7-f1be426862cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40FFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C700AA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x030700AA },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01020FFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext179__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext179__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext179__avg_gpu_core_frequency__max,acmgt3__ext179__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2575, 24, NULL,acmgt3__ext179__xve_slm_atomic_message_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext180_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext180";
   query->symbol_name = "Ext180";
   query->guid = "2c9db1da-1263-422b-9ae6-b2d59b5ec7b4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40FFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E700AA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext180__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext180__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext180__avg_gpu_core_frequency__max,acmgt3__ext180__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2577, 24, NULL,acmgt3__ext180__xve_slm_atomic_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext181_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext181";
   query->symbol_name = "Ext181";
   query->guid = "135f67bb-5cc5-408c-a5aa-760f9df1a3c1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x028300AA },
         { .reg = 0x00009888, .val = 0x00840FFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02860055 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x028700AA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext181__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext181__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext181__avg_gpu_core_frequency__max,acmgt3__ext181__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4021, 24, NULL,acmgt3__ext181__xve_slm_atomic_message_count_xecore16__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext182_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext182";
   query->symbol_name = "Ext182";
   query->guid = "c106cace-c1ea-4023-a288-f4b0a2487cc3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40FFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext182__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext182__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext182__avg_gpu_core_frequency__max,acmgt3__ext182__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4022, 24, NULL,acmgt3__ext182__xve_slm_atomic_message_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext183_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext183";
   query->symbol_name = "Ext183";
   query->guid = "4483d3ce-c377-4a00-8f10-7159c70fecd1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40FFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C700AA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x020700AA },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext183__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext183__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext183__avg_gpu_core_frequency__max,acmgt3__ext183__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4023, 24, NULL,acmgt3__ext183__xve_slm_atomic_message_count_xecore18__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext184_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext184";
   query->symbol_name = "Ext184";
   query->guid = "eaef6bf8-dd2a-4a07-a948-d837765220ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E300AA },
         { .reg = 0x00009888, .val = 0x00E40FFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E60055 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E700AA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070055 },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext184__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext184__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext184__avg_gpu_core_frequency__max,acmgt3__ext184__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4024, 24, NULL,acmgt3__ext184__xve_slm_atomic_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext185_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext185";
   query->symbol_name = "Ext185";
   query->guid = "00a90659-f144-4e89-b782-5dc13e3b3ca3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x038300AA },
         { .reg = 0x00009888, .val = 0x01840FFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x038700AA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x030800AA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext185__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext185__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext185__avg_gpu_core_frequency__max,acmgt3__ext185__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4025, 24, NULL,acmgt3__ext185__xve_slm_atomic_message_count_xecore20__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext186_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext186";
   query->symbol_name = "Ext186";
   query->guid = "b74242c4-91fb-4fed-a5bf-7154b99fa647";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40FFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x030800FF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x01010FFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext186__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext186__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext186__avg_gpu_core_frequency__max,acmgt3__ext186__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4026, 24, NULL,acmgt3__ext186__xve_slm_atomic_message_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext187_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext187";
   query->symbol_name = "Ext187";
   query->guid = "14d62995-8763-403b-aa49-28c9f09f32c4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40FFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C700AA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x030700AA },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01020FFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext187__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext187__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext187__avg_gpu_core_frequency__max,acmgt3__ext187__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4027, 24, NULL,acmgt3__ext187__xve_slm_atomic_message_count_xecore22__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext188_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext188";
   query->symbol_name = "Ext188";
   query->guid = "1f8abc30-c7f6-469e-9a6c-1b6c62208c75";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40FFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E700AA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext188__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext188__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext188__avg_gpu_core_frequency__max,acmgt3__ext188__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4028, 24, NULL,acmgt3__ext188__xve_slm_atomic_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext189_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext189";
   query->symbol_name = "Ext189";
   query->guid = "b8d49514-56d9-4a63-b5a2-539f97739cf3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x028300AA },
         { .reg = 0x00009888, .val = 0x00840FFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02860055 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x028700AA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890083 },
         { .reg = 0x00009888, .val = 0x088904C8 },
         { .reg = 0x00009888, .val = 0x0A890612 },
         { .reg = 0x00009888, .val = 0x0C8908A3 },
         { .reg = 0x00009888, .val = 0x0E890CE8 },
         { .reg = 0x00009888, .val = 0x10890E32 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext189__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext189__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext189__avg_gpu_core_frequency__max,acmgt3__ext189__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4029, 24, NULL,acmgt3__ext189__xve_slm_atomic_message_count_xecore24__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext190_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext190";
   query->symbol_name = "Ext190";
   query->guid = "1cec7b0a-c4c7-4a32-ae0b-9b809c84a7a0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40FFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x06A90083 },
         { .reg = 0x00009888, .val = 0x08A904C8 },
         { .reg = 0x00009888, .val = 0x0AA90612 },
         { .reg = 0x00009888, .val = 0x0CA908A3 },
         { .reg = 0x00009888, .val = 0x0EA90CE8 },
         { .reg = 0x00009888, .val = 0x10A90E32 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext190__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext190__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext190__avg_gpu_core_frequency__max,acmgt3__ext190__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4030, 24, NULL,acmgt3__ext190__xve_slm_atomic_message_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext191_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext191";
   query->symbol_name = "Ext191";
   query->guid = "3c9f5268-8d6f-4f54-8f76-a5364a32509d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40FFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C700AA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90083 },
         { .reg = 0x00009888, .val = 0x08C904C8 },
         { .reg = 0x00009888, .val = 0x0AC90612 },
         { .reg = 0x00009888, .val = 0x0CC908A3 },
         { .reg = 0x00009888, .val = 0x0EC90CE8 },
         { .reg = 0x00009888, .val = 0x10C90E32 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x020700AA },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext191__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext191__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext191__avg_gpu_core_frequency__max,acmgt3__ext191__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4031, 24, NULL,acmgt3__ext191__xve_slm_atomic_message_count_xecore26__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext192_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext192";
   query->symbol_name = "Ext192";
   query->guid = "fe743705-afe0-4964-8976-ef793e6730c3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E300AA },
         { .reg = 0x00009888, .val = 0x00E40FFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E60055 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E700AA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x06E90083 },
         { .reg = 0x00009888, .val = 0x08E904C8 },
         { .reg = 0x00009888, .val = 0x0AE90612 },
         { .reg = 0x00009888, .val = 0x0CE908A3 },
         { .reg = 0x00009888, .val = 0x0EE90CE8 },
         { .reg = 0x00009888, .val = 0x10E90E32 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070055 },
         { .reg = 0x00009888, .val = 0x00090FFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext192__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext192__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext192__avg_gpu_core_frequency__max,acmgt3__ext192__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4032, 24, NULL,acmgt3__ext192__xve_slm_atomic_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext193_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext193";
   query->symbol_name = "Ext193";
   query->guid = "3764f231-efa0-46c8-8fd1-d7524f7d287d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x038300AA },
         { .reg = 0x00009888, .val = 0x01840FFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03860055 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x038700AA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890083 },
         { .reg = 0x00009888, .val = 0x098904C8 },
         { .reg = 0x00009888, .val = 0x0B890612 },
         { .reg = 0x00009888, .val = 0x0D8908A3 },
         { .reg = 0x00009888, .val = 0x0F890CE8 },
         { .reg = 0x00009888, .val = 0x11890E32 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x030800AA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext193__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext193__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext193__avg_gpu_core_frequency__max,acmgt3__ext193__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4033, 24, NULL,acmgt3__ext193__xve_slm_atomic_message_count_xecore28__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext194_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext194";
   query->symbol_name = "Ext194";
   query->guid = "7ae1c3db-b806-43e8-a5cd-2f9fdbbbdf2e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40FFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x07A90083 },
         { .reg = 0x00009888, .val = 0x09A904C8 },
         { .reg = 0x00009888, .val = 0x0BA90612 },
         { .reg = 0x00009888, .val = 0x0DA908A3 },
         { .reg = 0x00009888, .val = 0x0FA90CE8 },
         { .reg = 0x00009888, .val = 0x11A90E32 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x030800FF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A0055 },
         { .reg = 0x00009888, .val = 0x01010FFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext194__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext194__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext194__avg_gpu_core_frequency__max,acmgt3__ext194__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4034, 24, NULL,acmgt3__ext194__xve_slm_atomic_message_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext195_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext195";
   query->symbol_name = "Ext195";
   query->guid = "addc5fb2-b8e8-4aab-b696-c033136f0207";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40FFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C700AA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90083 },
         { .reg = 0x00009888, .val = 0x09C904C8 },
         { .reg = 0x00009888, .val = 0x0BC90612 },
         { .reg = 0x00009888, .val = 0x0DC908A3 },
         { .reg = 0x00009888, .val = 0x0FC90CE8 },
         { .reg = 0x00009888, .val = 0x11C90E32 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x030700AA },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01020FFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext195__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext195__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext195__avg_gpu_core_frequency__max,acmgt3__ext195__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4035, 24, NULL,acmgt3__ext195__xve_slm_atomic_message_count_xecore30__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext196_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext196";
   query->symbol_name = "Ext196";
   query->guid = "b57b99a2-d4df-46f1-b851-a0ac6e5f728d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E300AA },
         { .reg = 0x00009888, .val = 0x01E40FFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E60055 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E700AA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x09E904C8 },
         { .reg = 0x00009888, .val = 0x0BE90612 },
         { .reg = 0x00009888, .val = 0x0DE908A3 },
         { .reg = 0x00009888, .val = 0x0FE90CE8 },
         { .reg = 0x00009888, .val = 0x11E90E32 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03070055 },
         { .reg = 0x00009888, .val = 0x01090FFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext196__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext196__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext196__avg_gpu_core_frequency__max,acmgt3__ext196__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4036, 24, NULL,acmgt3__ext196__xve_slm_atomic_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext197_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext197";
   query->symbol_name = "Ext197";
   query->guid = "bb509d13-b4b4-4d2e-844d-9f67591c66bd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext197__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext197__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext197__avg_gpu_core_frequency__max,acmgt3__ext197__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1099, 24, NULL,acmgt3__ext197__xve_slm_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1100, 32, NULL,acmgt3__ext197__xve_slm_fence_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext198_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext198";
   query->symbol_name = "Ext198";
   query->guid = "15e524f3-6392-401d-b3be-02b317cbd359";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext198__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext198__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext198__avg_gpu_core_frequency__max,acmgt3__ext198__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1101, 24, NULL,acmgt3__ext198__xve_slm_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1102, 32, NULL,acmgt3__ext198__xve_slm_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext199_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext199";
   query->symbol_name = "Ext199";
   query->guid = "f65fb347-b70a-486e-b1b5-a44da3da8b66";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext199__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext199__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext199__avg_gpu_core_frequency__max,acmgt3__ext199__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1103, 24, NULL,acmgt3__ext199__xve_slm_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1104, 32, NULL,acmgt3__ext199__xve_slm_fence_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext200_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext200";
   query->symbol_name = "Ext200";
   query->guid = "570e0476-84a4-42a2-8022-38fecca851ad";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext200__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext200__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext200__avg_gpu_core_frequency__max,acmgt3__ext200__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1105, 24, NULL,acmgt3__ext200__xve_slm_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1106, 32, NULL,acmgt3__ext200__xve_slm_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext201_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext201";
   query->symbol_name = "Ext201";
   query->guid = "4d7b3d3e-cafe-41f8-bb69-06d3a5d87305";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext201__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext201__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext201__avg_gpu_core_frequency__max,acmgt3__ext201__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2564, 24, NULL,acmgt3__ext201__xve_slm_fence_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2566, 32, NULL,acmgt3__ext201__xve_slm_fence_message_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext202_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext202";
   query->symbol_name = "Ext202";
   query->guid = "356bc819-2d0a-40c6-afcf-531107e99c87";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext202__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext202__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext202__avg_gpu_core_frequency__max,acmgt3__ext202__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2568, 24, NULL,acmgt3__ext202__xve_slm_fence_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2570, 32, NULL,acmgt3__ext202__xve_slm_fence_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext203_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext203";
   query->symbol_name = "Ext203";
   query->guid = "6a08a183-8d09-4e98-a198-b72edf387ceb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext203__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext203__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext203__avg_gpu_core_frequency__max,acmgt3__ext203__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2572, 24, NULL,acmgt3__ext203__xve_slm_fence_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2574, 32, NULL,acmgt3__ext203__xve_slm_fence_message_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext204_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext204";
   query->symbol_name = "Ext204";
   query->guid = "7afa64c7-c65b-4671-b6fc-c99a9b7fe6d4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext204__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext204__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext204__avg_gpu_core_frequency__max,acmgt3__ext204__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2576, 24, NULL,acmgt3__ext204__xve_slm_fence_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2578, 32, NULL,acmgt3__ext204__xve_slm_fence_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext205_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext205";
   query->symbol_name = "Ext205";
   query->guid = "92562fac-284e-4612-b25e-378432c85ad3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext205__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext205__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext205__avg_gpu_core_frequency__max,acmgt3__ext205__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4037, 24, NULL,acmgt3__ext205__xve_slm_fence_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4038, 32, NULL,acmgt3__ext205__xve_slm_fence_message_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext206_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext206";
   query->symbol_name = "Ext206";
   query->guid = "eeeb0ea8-ea9a-42e5-b793-e9143baf6425";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext206__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext206__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext206__avg_gpu_core_frequency__max,acmgt3__ext206__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4039, 24, NULL,acmgt3__ext206__xve_slm_fence_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4040, 32, NULL,acmgt3__ext206__xve_slm_fence_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext207_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext207";
   query->symbol_name = "Ext207";
   query->guid = "de748c4d-cf66-43e6-921e-d9d13b47f817";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext207__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext207__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext207__avg_gpu_core_frequency__max,acmgt3__ext207__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4041, 24, NULL,acmgt3__ext207__xve_slm_fence_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4042, 32, NULL,acmgt3__ext207__xve_slm_fence_message_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext208_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext208";
   query->symbol_name = "Ext208";
   query->guid = "50c6035f-68f0-45a8-b316-1dcda3d00e9a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext208__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext208__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext208__avg_gpu_core_frequency__max,acmgt3__ext208__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4043, 24, NULL,acmgt3__ext208__xve_slm_fence_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4044, 32, NULL,acmgt3__ext208__xve_slm_fence_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext209_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext209";
   query->symbol_name = "Ext209";
   query->guid = "0c6c792b-9f14-44c1-896d-3c122c75ab69";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890001 },
         { .reg = 0x00009888, .val = 0x1E890400 },
         { .reg = 0x00009888, .val = 0x20890000 },
         { .reg = 0x00009888, .val = 0x24890020 },
         { .reg = 0x00009888, .val = 0x2A890001 },
         { .reg = 0x00009888, .val = 0x1AA90001 },
         { .reg = 0x00009888, .val = 0x1EA90400 },
         { .reg = 0x00009888, .val = 0x20A90000 },
         { .reg = 0x00009888, .val = 0x24A90020 },
         { .reg = 0x00009888, .val = 0x2AA90001 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02895476 },
         { .reg = 0x00009888, .val = 0x0489069A },
         { .reg = 0x00009888, .val = 0x06890207 },
         { .reg = 0x00009888, .val = 0x08890617 },
         { .reg = 0x00009888, .val = 0x0A890A27 },
         { .reg = 0x00009888, .val = 0x0C890E37 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A95476 },
         { .reg = 0x00009888, .val = 0x04A9069A },
         { .reg = 0x00009888, .val = 0x0EA90207 },
         { .reg = 0x00009888, .val = 0x10A90617 },
         { .reg = 0x00009888, .val = 0x12A90A27 },
         { .reg = 0x00009888, .val = 0x14A90E37 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext209__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext209__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext209__avg_gpu_core_frequency__max,acmgt3__ext209__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4045, 24, NULL,acmgt3__ext209__xve_slm_fence_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4046, 32, NULL,acmgt3__ext209__xve_slm_fence_message_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext210_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext210";
   query->symbol_name = "Ext210";
   query->guid = "a931106d-e624-4d08-8fda-ecaead88f576";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC90001 },
         { .reg = 0x00009888, .val = 0x1EC90400 },
         { .reg = 0x00009888, .val = 0x20C90000 },
         { .reg = 0x00009888, .val = 0x24C90020 },
         { .reg = 0x00009888, .val = 0x2AC90001 },
         { .reg = 0x00009888, .val = 0x1AE90001 },
         { .reg = 0x00009888, .val = 0x1EE90400 },
         { .reg = 0x00009888, .val = 0x20E90000 },
         { .reg = 0x00009888, .val = 0x24E90020 },
         { .reg = 0x00009888, .val = 0x2AE90001 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C95476 },
         { .reg = 0x00009888, .val = 0x04C9069A },
         { .reg = 0x00009888, .val = 0x06C90207 },
         { .reg = 0x00009888, .val = 0x08C90617 },
         { .reg = 0x00009888, .val = 0x0AC90A27 },
         { .reg = 0x00009888, .val = 0x0CC90E37 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E95476 },
         { .reg = 0x00009888, .val = 0x04E9069A },
         { .reg = 0x00009888, .val = 0x0EE90207 },
         { .reg = 0x00009888, .val = 0x10E90617 },
         { .reg = 0x00009888, .val = 0x12E90A27 },
         { .reg = 0x00009888, .val = 0x14E90E37 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext210__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext210__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext210__avg_gpu_core_frequency__max,acmgt3__ext210__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4047, 24, NULL,acmgt3__ext210__xve_slm_fence_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4048, 32, NULL,acmgt3__ext210__xve_slm_fence_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext211_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext211";
   query->symbol_name = "Ext211";
   query->guid = "baa9de2f-f71f-4824-95f0-5fc9d96c7fc5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890001 },
         { .reg = 0x00009888, .val = 0x1F890400 },
         { .reg = 0x00009888, .val = 0x21890000 },
         { .reg = 0x00009888, .val = 0x25890020 },
         { .reg = 0x00009888, .val = 0x2B890001 },
         { .reg = 0x00009888, .val = 0x1BA90001 },
         { .reg = 0x00009888, .val = 0x1FA90400 },
         { .reg = 0x00009888, .val = 0x21A90000 },
         { .reg = 0x00009888, .val = 0x25A90020 },
         { .reg = 0x00009888, .val = 0x2BA90001 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03895476 },
         { .reg = 0x00009888, .val = 0x0589069A },
         { .reg = 0x00009888, .val = 0x07890207 },
         { .reg = 0x00009888, .val = 0x09890617 },
         { .reg = 0x00009888, .val = 0x0B890A27 },
         { .reg = 0x00009888, .val = 0x0D890E37 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A95476 },
         { .reg = 0x00009888, .val = 0x05A9069A },
         { .reg = 0x00009888, .val = 0x0FA90207 },
         { .reg = 0x00009888, .val = 0x11A90617 },
         { .reg = 0x00009888, .val = 0x13A90A27 },
         { .reg = 0x00009888, .val = 0x15A90E37 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext211__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext211__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext211__avg_gpu_core_frequency__max,acmgt3__ext211__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4049, 24, NULL,acmgt3__ext211__xve_slm_fence_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4050, 32, NULL,acmgt3__ext211__xve_slm_fence_message_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext212_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext212";
   query->symbol_name = "Ext212";
   query->guid = "bbbd7113-221b-4fca-aae2-5c8a259cbc48";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC90001 },
         { .reg = 0x00009888, .val = 0x1FC90400 },
         { .reg = 0x00009888, .val = 0x21C90000 },
         { .reg = 0x00009888, .val = 0x25C90020 },
         { .reg = 0x00009888, .val = 0x2BC90001 },
         { .reg = 0x00009888, .val = 0x1BE90001 },
         { .reg = 0x00009888, .val = 0x1FE90400 },
         { .reg = 0x00009888, .val = 0x21E90000 },
         { .reg = 0x00009888, .val = 0x25E90020 },
         { .reg = 0x00009888, .val = 0x2BE90001 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C95476 },
         { .reg = 0x00009888, .val = 0x05C9069A },
         { .reg = 0x00009888, .val = 0x07C90207 },
         { .reg = 0x00009888, .val = 0x09C90617 },
         { .reg = 0x00009888, .val = 0x0BC90A27 },
         { .reg = 0x00009888, .val = 0x0DC90E37 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E95476 },
         { .reg = 0x00009888, .val = 0x05E9069A },
         { .reg = 0x00009888, .val = 0x0FE90207 },
         { .reg = 0x00009888, .val = 0x11E90617 },
         { .reg = 0x00009888, .val = 0x13E90A27 },
         { .reg = 0x00009888, .val = 0x15E90E37 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext212__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext212__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext212__avg_gpu_core_frequency__max,acmgt3__ext212__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4051, 24, NULL,acmgt3__ext212__xve_slm_fence_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4052, 32, NULL,acmgt3__ext212__xve_slm_fence_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext213_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext213";
   query->symbol_name = "Ext213";
   query->guid = "6ca2babc-de4f-469e-ab01-d291e28d63e7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext213__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext213__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext213__avg_gpu_core_frequency__max,acmgt3__ext213__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 995, 24, NULL,acmgt3__ext213__load_store_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 996, 32, NULL,acmgt3__ext213__load_store_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 997, 40, NULL,acmgt3__ext213__load_store_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 998, 48, NULL,acmgt3__ext213__load_store_cache_access_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext214_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext214";
   query->symbol_name = "Ext214";
   query->guid = "74a2399e-2681-4433-8878-4dfe42324fcc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext214__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext214__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext214__avg_gpu_core_frequency__max,acmgt3__ext214__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 999, 24, NULL,acmgt3__ext214__load_store_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1000, 32, NULL,acmgt3__ext214__load_store_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1001, 40, NULL,acmgt3__ext214__load_store_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1002, 48, NULL,acmgt3__ext214__load_store_cache_access_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext215_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext215";
   query->symbol_name = "Ext215";
   query->guid = "401e46da-ef68-4a45-a2e7-7daa5b376228";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext215__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext215__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext215__avg_gpu_core_frequency__max,acmgt3__ext215__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2507, 24, NULL,acmgt3__ext215__load_store_cache_access_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2508, 32, NULL,acmgt3__ext215__load_store_cache_access_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2509, 40, NULL,acmgt3__ext215__load_store_cache_access_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2510, 48, NULL,acmgt3__ext215__load_store_cache_access_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext216_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext216";
   query->symbol_name = "Ext216";
   query->guid = "b7ae12df-db7e-4936-b449-c52f80ee5d29";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext216__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext216__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext216__avg_gpu_core_frequency__max,acmgt3__ext216__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2511, 24, NULL,acmgt3__ext216__load_store_cache_access_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2512, 32, NULL,acmgt3__ext216__load_store_cache_access_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2513, 40, NULL,acmgt3__ext216__load_store_cache_access_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2514, 48, NULL,acmgt3__ext216__load_store_cache_access_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext217_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext217";
   query->symbol_name = "Ext217";
   query->guid = "c69966b7-9ef1-430a-8936-0976458b2291";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext217__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext217__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext217__avg_gpu_core_frequency__max,acmgt3__ext217__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4053, 24, NULL,acmgt3__ext217__load_store_cache_access_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4054, 32, NULL,acmgt3__ext217__load_store_cache_access_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4055, 40, NULL,acmgt3__ext217__load_store_cache_access_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4056, 48, NULL,acmgt3__ext217__load_store_cache_access_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext218_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext218";
   query->symbol_name = "Ext218";
   query->guid = "01cb7b35-7ed2-43b5-b046-efde9201ca35";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext218__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext218__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext218__avg_gpu_core_frequency__max,acmgt3__ext218__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4057, 24, NULL,acmgt3__ext218__load_store_cache_access_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4058, 32, NULL,acmgt3__ext218__load_store_cache_access_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4059, 40, NULL,acmgt3__ext218__load_store_cache_access_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4060, 48, NULL,acmgt3__ext218__load_store_cache_access_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext219_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext219";
   query->symbol_name = "Ext219";
   query->guid = "c614285f-3ef0-43b8-9b09-1b13adbe2e8f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext219__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext219__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext219__avg_gpu_core_frequency__max,acmgt3__ext219__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4061, 24, NULL,acmgt3__ext219__load_store_cache_access_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4062, 32, NULL,acmgt3__ext219__load_store_cache_access_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4063, 40, NULL,acmgt3__ext219__load_store_cache_access_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4064, 48, NULL,acmgt3__ext219__load_store_cache_access_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext220_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext220";
   query->symbol_name = "Ext220";
   query->guid = "4bdb50d9-dfc5-42d2-86aa-d8592e876856";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext220__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext220__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext220__avg_gpu_core_frequency__max,acmgt3__ext220__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4065, 24, NULL,acmgt3__ext220__load_store_cache_access_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4066, 32, NULL,acmgt3__ext220__load_store_cache_access_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4067, 40, NULL,acmgt3__ext220__load_store_cache_access_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4068, 48, NULL,acmgt3__ext220__load_store_cache_access_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext221_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext221";
   query->symbol_name = "Ext221";
   query->guid = "50714f9c-2bb3-459c-b546-8a374589bf9e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x06870143 },
         { .reg = 0x00009888, .val = 0x08870553 },
         { .reg = 0x00009888, .val = 0x0087AA00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x06880143 },
         { .reg = 0x00009888, .val = 0x08880553 },
         { .reg = 0x00009888, .val = 0x008900F0 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70143 },
         { .reg = 0x00009888, .val = 0x10A70553 },
         { .reg = 0x00009888, .val = 0x02A7AA00 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0EA80143 },
         { .reg = 0x00009888, .val = 0x10A80553 },
         { .reg = 0x00009888, .val = 0x00A9F000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E031083 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030143 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030804 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext221__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext221__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext221__avg_gpu_core_frequency__max,acmgt3__ext221__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1003, 24, NULL,acmgt3__ext221__load_store_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1004, 32, NULL,acmgt3__ext221__load_store_cache_hit_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext222_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext222";
   query->symbol_name = "Ext222";
   query->guid = "fcfd6090-d189-4cd7-9c85-3a5acc193e7f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x06C70143 },
         { .reg = 0x00009888, .val = 0x08C70553 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80143 },
         { .reg = 0x00009888, .val = 0x08C80553 },
         { .reg = 0x00009888, .val = 0x00C900F0 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70143 },
         { .reg = 0x00009888, .val = 0x10E70553 },
         { .reg = 0x00009888, .val = 0x02E7AA00 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0EE80143 },
         { .reg = 0x00009888, .val = 0x10E80553 },
         { .reg = 0x00009888, .val = 0x00E9F000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C64 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203108A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030004 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030623 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext222__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext222__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext222__avg_gpu_core_frequency__max,acmgt3__ext222__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1005, 24, NULL,acmgt3__ext222__load_store_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1006, 32, NULL,acmgt3__ext222__load_store_cache_hit_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext223_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext223";
   query->symbol_name = "Ext223";
   query->guid = "4ed943c0-2d87-4749-876f-811e1b39e607";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x07870143 },
         { .reg = 0x00009888, .val = 0x09870553 },
         { .reg = 0x00009888, .val = 0x0187AA00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x07880143 },
         { .reg = 0x00009888, .val = 0x09880553 },
         { .reg = 0x00009888, .val = 0x018900F0 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0FA70143 },
         { .reg = 0x00009888, .val = 0x11A70553 },
         { .reg = 0x00009888, .val = 0x03A7AA00 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0FA80143 },
         { .reg = 0x00009888, .val = 0x11A80553 },
         { .reg = 0x00009888, .val = 0x01A9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E031083 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030143 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030804 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext223__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext223__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext223__avg_gpu_core_frequency__max,acmgt3__ext223__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1007, 24, NULL,acmgt3__ext223__load_store_cache_hit_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1008, 32, NULL,acmgt3__ext223__load_store_cache_hit_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext224_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext224";
   query->symbol_name = "Ext224";
   query->guid = "2b3af12b-71c7-4f36-bb8f-049547bf5c2d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x07C70143 },
         { .reg = 0x00009888, .val = 0x09C70553 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80143 },
         { .reg = 0x00009888, .val = 0x09C80553 },
         { .reg = 0x00009888, .val = 0x01C900F0 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x0FE70143 },
         { .reg = 0x00009888, .val = 0x11E70553 },
         { .reg = 0x00009888, .val = 0x03E7AA00 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0FE80143 },
         { .reg = 0x00009888, .val = 0x11E80553 },
         { .reg = 0x00009888, .val = 0x01E9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C64 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203108A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030004 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030623 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext224__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext224__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext224__avg_gpu_core_frequency__max,acmgt3__ext224__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1009, 24, NULL,acmgt3__ext224__load_store_cache_hit_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1010, 32, NULL,acmgt3__ext224__load_store_cache_hit_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext225_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext225";
   query->symbol_name = "Ext225";
   query->guid = "1dde6c6e-a7aa-4f8f-aaf4-3b26dd6bca69";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x06870143 },
         { .reg = 0x00009888, .val = 0x08870553 },
         { .reg = 0x00009888, .val = 0x0087AA00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x06880143 },
         { .reg = 0x00009888, .val = 0x08880553 },
         { .reg = 0x00009888, .val = 0x008900F0 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70143 },
         { .reg = 0x00009888, .val = 0x10A70553 },
         { .reg = 0x00009888, .val = 0x02A7AA00 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0EA80143 },
         { .reg = 0x00009888, .val = 0x10A80553 },
         { .reg = 0x00009888, .val = 0x00A9F000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E031083 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030143 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030804 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext225__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext225__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext225__avg_gpu_core_frequency__max,acmgt3__ext225__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2523, 24, NULL,acmgt3__ext225__load_store_cache_hit_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2524, 32, NULL,acmgt3__ext225__load_store_cache_hit_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext226_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext226";
   query->symbol_name = "Ext226";
   query->guid = "d9db7f79-0da3-4ab3-8b28-8dd70416656f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x06C70143 },
         { .reg = 0x00009888, .val = 0x08C70553 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80143 },
         { .reg = 0x00009888, .val = 0x08C80553 },
         { .reg = 0x00009888, .val = 0x00C900F0 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70143 },
         { .reg = 0x00009888, .val = 0x10E70553 },
         { .reg = 0x00009888, .val = 0x02E7AA00 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0EE80143 },
         { .reg = 0x00009888, .val = 0x10E80553 },
         { .reg = 0x00009888, .val = 0x00E9F000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C64 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203108A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030004 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030623 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext226__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext226__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext226__avg_gpu_core_frequency__max,acmgt3__ext226__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2525, 24, NULL,acmgt3__ext226__load_store_cache_hit_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2526, 32, NULL,acmgt3__ext226__load_store_cache_hit_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext227_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext227";
   query->symbol_name = "Ext227";
   query->guid = "d98e7c96-ff33-493f-9e6e-0e5c2ff4d3b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x07870143 },
         { .reg = 0x00009888, .val = 0x09870553 },
         { .reg = 0x00009888, .val = 0x0187AA00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x07880143 },
         { .reg = 0x00009888, .val = 0x09880553 },
         { .reg = 0x00009888, .val = 0x018900F0 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0FA70143 },
         { .reg = 0x00009888, .val = 0x11A70553 },
         { .reg = 0x00009888, .val = 0x03A7AA00 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0FA80143 },
         { .reg = 0x00009888, .val = 0x11A80553 },
         { .reg = 0x00009888, .val = 0x01A9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E031083 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030143 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030804 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext227__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext227__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext227__avg_gpu_core_frequency__max,acmgt3__ext227__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2527, 24, NULL,acmgt3__ext227__load_store_cache_hit_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2528, 32, NULL,acmgt3__ext227__load_store_cache_hit_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext228_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext228";
   query->symbol_name = "Ext228";
   query->guid = "ee084440-5ff3-4348-98aa-69f9bc50bc13";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x07C70143 },
         { .reg = 0x00009888, .val = 0x09C70553 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80143 },
         { .reg = 0x00009888, .val = 0x09C80553 },
         { .reg = 0x00009888, .val = 0x01C900F0 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x0FE70143 },
         { .reg = 0x00009888, .val = 0x11E70553 },
         { .reg = 0x00009888, .val = 0x03E7AA00 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0FE80143 },
         { .reg = 0x00009888, .val = 0x11E80553 },
         { .reg = 0x00009888, .val = 0x01E9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C64 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203108A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030004 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030623 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext228__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext228__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext228__avg_gpu_core_frequency__max,acmgt3__ext228__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2529, 24, NULL,acmgt3__ext228__load_store_cache_hit_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2530, 32, NULL,acmgt3__ext228__load_store_cache_hit_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext229_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext229";
   query->symbol_name = "Ext229";
   query->guid = "8591ba5f-8306-4275-92a8-d9059ad66ed0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x06870143 },
         { .reg = 0x00009888, .val = 0x08870553 },
         { .reg = 0x00009888, .val = 0x0087AA00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x06880143 },
         { .reg = 0x00009888, .val = 0x08880553 },
         { .reg = 0x00009888, .val = 0x008900F0 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70143 },
         { .reg = 0x00009888, .val = 0x10A70553 },
         { .reg = 0x00009888, .val = 0x02A7AA00 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0EA80143 },
         { .reg = 0x00009888, .val = 0x10A80553 },
         { .reg = 0x00009888, .val = 0x00A9F000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E031083 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030143 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030804 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext229__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext229__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext229__avg_gpu_core_frequency__max,acmgt3__ext229__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4069, 24, NULL,acmgt3__ext229__load_store_cache_hit_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4070, 32, NULL,acmgt3__ext229__load_store_cache_hit_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext230_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext230";
   query->symbol_name = "Ext230";
   query->guid = "00e97ab6-80e8-4fb7-8735-d2c9fd2e57e0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x06C70143 },
         { .reg = 0x00009888, .val = 0x08C70553 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80143 },
         { .reg = 0x00009888, .val = 0x08C80553 },
         { .reg = 0x00009888, .val = 0x00C900F0 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70143 },
         { .reg = 0x00009888, .val = 0x10E70553 },
         { .reg = 0x00009888, .val = 0x02E7AA00 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0EE80143 },
         { .reg = 0x00009888, .val = 0x10E80553 },
         { .reg = 0x00009888, .val = 0x00E9F000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C64 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203108A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030004 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030623 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext230__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext230__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext230__avg_gpu_core_frequency__max,acmgt3__ext230__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4071, 24, NULL,acmgt3__ext230__load_store_cache_hit_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4072, 32, NULL,acmgt3__ext230__load_store_cache_hit_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext231_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext231";
   query->symbol_name = "Ext231";
   query->guid = "8843165e-fc6d-4b1a-8356-201b7b0bdb25";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x07870143 },
         { .reg = 0x00009888, .val = 0x09870553 },
         { .reg = 0x00009888, .val = 0x0187AA00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x07880143 },
         { .reg = 0x00009888, .val = 0x09880553 },
         { .reg = 0x00009888, .val = 0x018900F0 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0FA70143 },
         { .reg = 0x00009888, .val = 0x11A70553 },
         { .reg = 0x00009888, .val = 0x03A7AA00 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0FA80143 },
         { .reg = 0x00009888, .val = 0x11A80553 },
         { .reg = 0x00009888, .val = 0x01A9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E031083 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030143 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030804 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext231__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext231__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext231__avg_gpu_core_frequency__max,acmgt3__ext231__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4073, 24, NULL,acmgt3__ext231__load_store_cache_hit_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4074, 32, NULL,acmgt3__ext231__load_store_cache_hit_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext232_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext232";
   query->symbol_name = "Ext232";
   query->guid = "964b5b29-6acf-4be2-b50b-030c7a8c3fc8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x07C70143 },
         { .reg = 0x00009888, .val = 0x09C70553 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80143 },
         { .reg = 0x00009888, .val = 0x09C80553 },
         { .reg = 0x00009888, .val = 0x01C900F0 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x0FE70143 },
         { .reg = 0x00009888, .val = 0x11E70553 },
         { .reg = 0x00009888, .val = 0x03E7AA00 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0FE80143 },
         { .reg = 0x00009888, .val = 0x11E80553 },
         { .reg = 0x00009888, .val = 0x01E9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C64 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203108A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030004 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030623 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext232__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext232__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext232__avg_gpu_core_frequency__max,acmgt3__ext232__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4075, 24, NULL,acmgt3__ext232__load_store_cache_hit_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4076, 32, NULL,acmgt3__ext232__load_store_cache_hit_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext233_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext233";
   query->symbol_name = "Ext233";
   query->guid = "796a2acb-6ddb-4567-9c5e-ad1b18f74271";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x06870143 },
         { .reg = 0x00009888, .val = 0x08870553 },
         { .reg = 0x00009888, .val = 0x0087AA00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x06880143 },
         { .reg = 0x00009888, .val = 0x08880553 },
         { .reg = 0x00009888, .val = 0x008900F0 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70143 },
         { .reg = 0x00009888, .val = 0x10A70553 },
         { .reg = 0x00009888, .val = 0x02A7AA00 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0EA80143 },
         { .reg = 0x00009888, .val = 0x10A80553 },
         { .reg = 0x00009888, .val = 0x00A9F000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E031083 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030143 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030804 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext233__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext233__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext233__avg_gpu_core_frequency__max,acmgt3__ext233__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4077, 24, NULL,acmgt3__ext233__load_store_cache_hit_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4078, 32, NULL,acmgt3__ext233__load_store_cache_hit_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext234_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext234";
   query->symbol_name = "Ext234";
   query->guid = "8c5e4033-e50a-4f55-a17f-2fca9ac26074";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x06C70143 },
         { .reg = 0x00009888, .val = 0x08C70553 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80143 },
         { .reg = 0x00009888, .val = 0x08C80553 },
         { .reg = 0x00009888, .val = 0x00C900F0 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70143 },
         { .reg = 0x00009888, .val = 0x10E70553 },
         { .reg = 0x00009888, .val = 0x02E7AA00 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0EE80143 },
         { .reg = 0x00009888, .val = 0x10E80553 },
         { .reg = 0x00009888, .val = 0x00E9F000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C64 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203108A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030004 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030623 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext234__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext234__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext234__avg_gpu_core_frequency__max,acmgt3__ext234__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4079, 24, NULL,acmgt3__ext234__load_store_cache_hit_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4080, 32, NULL,acmgt3__ext234__load_store_cache_hit_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext235_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext235";
   query->symbol_name = "Ext235";
   query->guid = "6717aa54-589d-4ccc-b40a-a2fb3dd9e11a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x07870143 },
         { .reg = 0x00009888, .val = 0x09870553 },
         { .reg = 0x00009888, .val = 0x0187AA00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x07880143 },
         { .reg = 0x00009888, .val = 0x09880553 },
         { .reg = 0x00009888, .val = 0x018900F0 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x0FA70143 },
         { .reg = 0x00009888, .val = 0x11A70553 },
         { .reg = 0x00009888, .val = 0x03A7AA00 },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0FA80143 },
         { .reg = 0x00009888, .val = 0x11A80553 },
         { .reg = 0x00009888, .val = 0x01A9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E031083 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030143 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030804 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext235__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext235__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext235__avg_gpu_core_frequency__max,acmgt3__ext235__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4081, 24, NULL,acmgt3__ext235__load_store_cache_hit_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4082, 32, NULL,acmgt3__ext235__load_store_cache_hit_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext236_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext236";
   query->symbol_name = "Ext236";
   query->guid = "4e1d6474-b268-4c2e-9437-208ee88b8a46";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x07C70143 },
         { .reg = 0x00009888, .val = 0x09C70553 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80143 },
         { .reg = 0x00009888, .val = 0x09C80553 },
         { .reg = 0x00009888, .val = 0x01C900F0 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x0FE70143 },
         { .reg = 0x00009888, .val = 0x11E70553 },
         { .reg = 0x00009888, .val = 0x03E7AA00 },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x0FE80143 },
         { .reg = 0x00009888, .val = 0x11E80553 },
         { .reg = 0x00009888, .val = 0x01E9F000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C64 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203108A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030004 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030623 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext236__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext236__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext236__avg_gpu_core_frequency__max,acmgt3__ext236__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4083, 24, NULL,acmgt3__ext236__load_store_cache_hit_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4084, 32, NULL,acmgt3__ext236__load_store_cache_hit_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext237_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext237";
   query->symbol_name = "Ext237";
   query->guid = "88f46503-19d1-42d1-be21-a3655e1b0136";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890083 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90083 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90083 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90083 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890083 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90083 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90083 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext237__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext237__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext237__avg_gpu_core_frequency__max,acmgt3__ext237__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1011, 24, NULL,acmgt3__ext237__load_store_cache_l3_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1012, 32, NULL,acmgt3__ext237__load_store_cache_l3_read_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1013, 40, NULL,acmgt3__ext237__load_store_cache_l3_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1014, 48, NULL,acmgt3__ext237__load_store_cache_l3_read_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1015, 56, NULL,acmgt3__ext237__load_store_cache_l3_read_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1016, 64, NULL,acmgt3__ext237__load_store_cache_l3_read_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1017, 72, NULL,acmgt3__ext237__load_store_cache_l3_read_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1018, 80, NULL,acmgt3__ext237__load_store_cache_l3_read_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext238_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext238";
   query->symbol_name = "Ext238";
   query->guid = "5da6f145-39c5-44cc-8329-0998439ee9c5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890083 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90083 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90083 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90083 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890083 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90083 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90083 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext238__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext238__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext238__avg_gpu_core_frequency__max,acmgt3__ext238__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2491, 24, NULL,acmgt3__ext238__load_store_cache_l3_read_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2492, 32, NULL,acmgt3__ext238__load_store_cache_l3_read_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2493, 40, NULL,acmgt3__ext238__load_store_cache_l3_read_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2494, 48, NULL,acmgt3__ext238__load_store_cache_l3_read_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2495, 56, NULL,acmgt3__ext238__load_store_cache_l3_read_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2496, 64, NULL,acmgt3__ext238__load_store_cache_l3_read_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2497, 72, NULL,acmgt3__ext238__load_store_cache_l3_read_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2498, 80, NULL,acmgt3__ext238__load_store_cache_l3_read_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext239_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext239";
   query->symbol_name = "Ext239";
   query->guid = "4543c6ec-412e-4dee-b121-a3b02275a132";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890083 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90083 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90083 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90083 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890083 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90083 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90083 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext239__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext239__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext239__avg_gpu_core_frequency__max,acmgt3__ext239__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4085, 24, NULL,acmgt3__ext239__load_store_cache_l3_read_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4086, 32, NULL,acmgt3__ext239__load_store_cache_l3_read_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4087, 40, NULL,acmgt3__ext239__load_store_cache_l3_read_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4088, 48, NULL,acmgt3__ext239__load_store_cache_l3_read_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4089, 56, NULL,acmgt3__ext239__load_store_cache_l3_read_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4090, 64, NULL,acmgt3__ext239__load_store_cache_l3_read_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4091, 72, NULL,acmgt3__ext239__load_store_cache_l3_read_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4092, 80, NULL,acmgt3__ext239__load_store_cache_l3_read_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext240_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext240";
   query->symbol_name = "Ext240";
   query->guid = "e6b031df-b3fe-4fd4-97c3-7c26f28dac6f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890083 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90083 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90083 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90083 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890083 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90083 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90083 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90083 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext240__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext240__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext240__avg_gpu_core_frequency__max,acmgt3__ext240__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4093, 24, NULL,acmgt3__ext240__load_store_cache_l3_read_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4094, 32, NULL,acmgt3__ext240__load_store_cache_l3_read_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4095, 40, NULL,acmgt3__ext240__load_store_cache_l3_read_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4096, 48, NULL,acmgt3__ext240__load_store_cache_l3_read_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4097, 56, NULL,acmgt3__ext240__load_store_cache_l3_read_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4098, 64, NULL,acmgt3__ext240__load_store_cache_l3_read_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4099, 72, NULL,acmgt3__ext240__load_store_cache_l3_read_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4100, 80, NULL,acmgt3__ext240__load_store_cache_l3_read_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext241_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext241";
   query->symbol_name = "Ext241";
   query->guid = "4ab6ae4f-59e0-4dee-b907-026737066065";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890105 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90105 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90105 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90105 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890105 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90105 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90105 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90105 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext241__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext241__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext241__avg_gpu_core_frequency__max,acmgt3__ext241__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1019, 24, NULL,acmgt3__ext241__load_store_cache_l3_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1020, 32, NULL,acmgt3__ext241__load_store_cache_l3_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1021, 40, NULL,acmgt3__ext241__load_store_cache_l3_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1022, 48, NULL,acmgt3__ext241__load_store_cache_l3_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1023, 56, NULL,acmgt3__ext241__load_store_cache_l3_write_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1024, 64, NULL,acmgt3__ext241__load_store_cache_l3_write_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1025, 72, NULL,acmgt3__ext241__load_store_cache_l3_write_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1026, 80, NULL,acmgt3__ext241__load_store_cache_l3_write_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext242_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext242";
   query->symbol_name = "Ext242";
   query->guid = "db802a4a-11cd-43aa-8baa-3b951ed19672";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890105 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90105 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90105 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90105 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890105 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90105 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90105 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90105 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext242__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext242__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext242__avg_gpu_core_frequency__max,acmgt3__ext242__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2499, 24, NULL,acmgt3__ext242__load_store_cache_l3_write_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2500, 32, NULL,acmgt3__ext242__load_store_cache_l3_write_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2501, 40, NULL,acmgt3__ext242__load_store_cache_l3_write_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2502, 48, NULL,acmgt3__ext242__load_store_cache_l3_write_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2503, 56, NULL,acmgt3__ext242__load_store_cache_l3_write_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2504, 64, NULL,acmgt3__ext242__load_store_cache_l3_write_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2505, 72, NULL,acmgt3__ext242__load_store_cache_l3_write_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2506, 80, NULL,acmgt3__ext242__load_store_cache_l3_write_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext243_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext243";
   query->symbol_name = "Ext243";
   query->guid = "e7f929f5-f382-4bb2-b32b-e808e816a751";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890105 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90105 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90105 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90105 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890105 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90105 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90105 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90105 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext243__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext243__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext243__avg_gpu_core_frequency__max,acmgt3__ext243__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4101, 24, NULL,acmgt3__ext243__load_store_cache_l3_write_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4102, 32, NULL,acmgt3__ext243__load_store_cache_l3_write_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4103, 40, NULL,acmgt3__ext243__load_store_cache_l3_write_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4104, 48, NULL,acmgt3__ext243__load_store_cache_l3_write_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4105, 56, NULL,acmgt3__ext243__load_store_cache_l3_write_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4106, 64, NULL,acmgt3__ext243__load_store_cache_l3_write_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4107, 72, NULL,acmgt3__ext243__load_store_cache_l3_write_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4108, 80, NULL,acmgt3__ext243__load_store_cache_l3_write_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext244_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext244";
   query->symbol_name = "Ext244";
   query->guid = "81a25cda-94c8-4b9a-b9e5-38994ed22ab0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1689001F },
         { .reg = 0x00009888, .val = 0x16A9001F },
         { .reg = 0x00009888, .val = 0x16C9001F },
         { .reg = 0x00009888, .val = 0x16E9001F },
         { .reg = 0x00009888, .val = 0x1789001F },
         { .reg = 0x00009888, .val = 0x17A9001F },
         { .reg = 0x00009888, .val = 0x17C9001F },
         { .reg = 0x00009888, .val = 0x17E9001F },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x0287A000 },
         { .reg = 0x00009888, .val = 0x02890000 },
         { .reg = 0x00009888, .val = 0x14890105 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x02A90000 },
         { .reg = 0x00009888, .val = 0x12A90105 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C700A0 },
         { .reg = 0x00009888, .val = 0x02C90000 },
         { .reg = 0x00009888, .val = 0x10C90105 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x02E90000 },
         { .reg = 0x00009888, .val = 0x0EE90105 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x0187A000 },
         { .reg = 0x00009888, .val = 0x03890000 },
         { .reg = 0x00009888, .val = 0x0D890105 },
         { .reg = 0x00009888, .val = 0x05890000 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70A00 },
         { .reg = 0x00009888, .val = 0x03A90000 },
         { .reg = 0x00009888, .val = 0x0BA90105 },
         { .reg = 0x00009888, .val = 0x05A90000 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C700A0 },
         { .reg = 0x00009888, .val = 0x03C90000 },
         { .reg = 0x00009888, .val = 0x09C90105 },
         { .reg = 0x00009888, .val = 0x05C90000 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x03E90000 },
         { .reg = 0x00009888, .val = 0x07E90105 },
         { .reg = 0x00009888, .val = 0x05E90000 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext244__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext244__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext244__avg_gpu_core_frequency__max,acmgt3__ext244__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4109, 24, NULL,acmgt3__ext244__load_store_cache_l3_write_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4110, 32, NULL,acmgt3__ext244__load_store_cache_l3_write_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4111, 40, NULL,acmgt3__ext244__load_store_cache_l3_write_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4112, 48, NULL,acmgt3__ext244__load_store_cache_l3_write_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4113, 56, NULL,acmgt3__ext244__load_store_cache_l3_write_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4114, 64, NULL,acmgt3__ext244__load_store_cache_l3_write_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4115, 72, NULL,acmgt3__ext244__load_store_cache_l3_write_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4116, 80, NULL,acmgt3__ext244__load_store_cache_l3_write_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext245_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext245";
   query->symbol_name = "Ext245";
   query->guid = "6a234e4e-a4a9-483c-b0b1-f6be43dfb64c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16870005 },
         { .reg = 0x00009888, .val = 0x1A870005 },
         { .reg = 0x00009888, .val = 0x12880005 },
         { .reg = 0x00009888, .val = 0x16880005 },
         { .reg = 0x00009888, .val = 0x16A70005 },
         { .reg = 0x00009888, .val = 0x1AA70005 },
         { .reg = 0x00009888, .val = 0x12A80005 },
         { .reg = 0x00009888, .val = 0x16A80005 },
         { .reg = 0x00009888, .val = 0x16C70005 },
         { .reg = 0x00009888, .val = 0x1AC70005 },
         { .reg = 0x00009888, .val = 0x12C80005 },
         { .reg = 0x00009888, .val = 0x16C80005 },
         { .reg = 0x00009888, .val = 0x16E70005 },
         { .reg = 0x00009888, .val = 0x1AE70005 },
         { .reg = 0x00009888, .val = 0x12E80005 },
         { .reg = 0x00009888, .val = 0x16E80005 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext245__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext245__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext245__avg_gpu_core_frequency__max,acmgt3__ext245__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1027, 24, NULL,acmgt3__ext245__load_store_cache_partial_write_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1028, 32, NULL,acmgt3__ext245__load_store_cache_partial_write_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1029, 40, NULL,acmgt3__ext245__load_store_cache_partial_write_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1030, 48, NULL,acmgt3__ext245__load_store_cache_partial_write_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext246_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext246";
   query->symbol_name = "Ext246";
   query->guid = "94757ea4-0b0b-401f-93a2-b119ed4f5204";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17870005 },
         { .reg = 0x00009888, .val = 0x1B870005 },
         { .reg = 0x00009888, .val = 0x13880005 },
         { .reg = 0x00009888, .val = 0x17880005 },
         { .reg = 0x00009888, .val = 0x17A70005 },
         { .reg = 0x00009888, .val = 0x1BA70005 },
         { .reg = 0x00009888, .val = 0x13A80005 },
         { .reg = 0x00009888, .val = 0x17A80005 },
         { .reg = 0x00009888, .val = 0x17C70005 },
         { .reg = 0x00009888, .val = 0x1BC70005 },
         { .reg = 0x00009888, .val = 0x13C80005 },
         { .reg = 0x00009888, .val = 0x17C80005 },
         { .reg = 0x00009888, .val = 0x17E70005 },
         { .reg = 0x00009888, .val = 0x1BE70005 },
         { .reg = 0x00009888, .val = 0x13E80005 },
         { .reg = 0x00009888, .val = 0x17E80005 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext246__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext246__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext246__avg_gpu_core_frequency__max,acmgt3__ext246__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1031, 24, NULL,acmgt3__ext246__load_store_cache_partial_write_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1032, 32, NULL,acmgt3__ext246__load_store_cache_partial_write_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1033, 40, NULL,acmgt3__ext246__load_store_cache_partial_write_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1034, 48, NULL,acmgt3__ext246__load_store_cache_partial_write_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext247_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext247";
   query->symbol_name = "Ext247";
   query->guid = "b90ea8da-5965-4457-97aa-49a688fb0d39";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870005 },
         { .reg = 0x00009888, .val = 0x1A870005 },
         { .reg = 0x00009888, .val = 0x12880005 },
         { .reg = 0x00009888, .val = 0x16880005 },
         { .reg = 0x00009888, .val = 0x16A70005 },
         { .reg = 0x00009888, .val = 0x1AA70005 },
         { .reg = 0x00009888, .val = 0x12A80005 },
         { .reg = 0x00009888, .val = 0x16A80005 },
         { .reg = 0x00009888, .val = 0x16C70005 },
         { .reg = 0x00009888, .val = 0x1AC70005 },
         { .reg = 0x00009888, .val = 0x12C80005 },
         { .reg = 0x00009888, .val = 0x16C80005 },
         { .reg = 0x00009888, .val = 0x16E70005 },
         { .reg = 0x00009888, .val = 0x1AE70005 },
         { .reg = 0x00009888, .val = 0x12E80005 },
         { .reg = 0x00009888, .val = 0x16E80005 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext247__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext247__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext247__avg_gpu_core_frequency__max,acmgt3__ext247__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2515, 24, NULL,acmgt3__ext247__load_store_cache_partial_write_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2516, 32, NULL,acmgt3__ext247__load_store_cache_partial_write_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2517, 40, NULL,acmgt3__ext247__load_store_cache_partial_write_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2518, 48, NULL,acmgt3__ext247__load_store_cache_partial_write_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext248_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext248";
   query->symbol_name = "Ext248";
   query->guid = "74996160-a911-4eb8-9db3-e83969d92a35";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870005 },
         { .reg = 0x00009888, .val = 0x1B870005 },
         { .reg = 0x00009888, .val = 0x13880005 },
         { .reg = 0x00009888, .val = 0x17880005 },
         { .reg = 0x00009888, .val = 0x17A70005 },
         { .reg = 0x00009888, .val = 0x1BA70005 },
         { .reg = 0x00009888, .val = 0x13A80005 },
         { .reg = 0x00009888, .val = 0x17A80005 },
         { .reg = 0x00009888, .val = 0x17C70005 },
         { .reg = 0x00009888, .val = 0x1BC70005 },
         { .reg = 0x00009888, .val = 0x13C80005 },
         { .reg = 0x00009888, .val = 0x17C80005 },
         { .reg = 0x00009888, .val = 0x17E70005 },
         { .reg = 0x00009888, .val = 0x1BE70005 },
         { .reg = 0x00009888, .val = 0x13E80005 },
         { .reg = 0x00009888, .val = 0x17E80005 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext248__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext248__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext248__avg_gpu_core_frequency__max,acmgt3__ext248__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2519, 24, NULL,acmgt3__ext248__load_store_cache_partial_write_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2520, 32, NULL,acmgt3__ext248__load_store_cache_partial_write_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2521, 40, NULL,acmgt3__ext248__load_store_cache_partial_write_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2522, 48, NULL,acmgt3__ext248__load_store_cache_partial_write_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext249_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext249";
   query->symbol_name = "Ext249";
   query->guid = "f287382f-3de7-43af-a4c5-20ec8d84b7b1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870005 },
         { .reg = 0x00009888, .val = 0x1A870005 },
         { .reg = 0x00009888, .val = 0x12880005 },
         { .reg = 0x00009888, .val = 0x16880005 },
         { .reg = 0x00009888, .val = 0x16A70005 },
         { .reg = 0x00009888, .val = 0x1AA70005 },
         { .reg = 0x00009888, .val = 0x12A80005 },
         { .reg = 0x00009888, .val = 0x16A80005 },
         { .reg = 0x00009888, .val = 0x16C70005 },
         { .reg = 0x00009888, .val = 0x1AC70005 },
         { .reg = 0x00009888, .val = 0x12C80005 },
         { .reg = 0x00009888, .val = 0x16C80005 },
         { .reg = 0x00009888, .val = 0x16E70005 },
         { .reg = 0x00009888, .val = 0x1AE70005 },
         { .reg = 0x00009888, .val = 0x12E80005 },
         { .reg = 0x00009888, .val = 0x16E80005 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext249__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext249__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext249__avg_gpu_core_frequency__max,acmgt3__ext249__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4117, 24, NULL,acmgt3__ext249__load_store_cache_partial_write_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4118, 32, NULL,acmgt3__ext249__load_store_cache_partial_write_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4119, 40, NULL,acmgt3__ext249__load_store_cache_partial_write_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4120, 48, NULL,acmgt3__ext249__load_store_cache_partial_write_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext250_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext250";
   query->symbol_name = "Ext250";
   query->guid = "a92c55c1-352f-44fc-a86c-3f0b0e525d97";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870005 },
         { .reg = 0x00009888, .val = 0x1B870005 },
         { .reg = 0x00009888, .val = 0x13880005 },
         { .reg = 0x00009888, .val = 0x17880005 },
         { .reg = 0x00009888, .val = 0x17A70005 },
         { .reg = 0x00009888, .val = 0x1BA70005 },
         { .reg = 0x00009888, .val = 0x13A80005 },
         { .reg = 0x00009888, .val = 0x17A80005 },
         { .reg = 0x00009888, .val = 0x17C70005 },
         { .reg = 0x00009888, .val = 0x1BC70005 },
         { .reg = 0x00009888, .val = 0x13C80005 },
         { .reg = 0x00009888, .val = 0x17C80005 },
         { .reg = 0x00009888, .val = 0x17E70005 },
         { .reg = 0x00009888, .val = 0x1BE70005 },
         { .reg = 0x00009888, .val = 0x13E80005 },
         { .reg = 0x00009888, .val = 0x17E80005 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext250__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext250__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext250__avg_gpu_core_frequency__max,acmgt3__ext250__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4121, 24, NULL,acmgt3__ext250__load_store_cache_partial_write_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4122, 32, NULL,acmgt3__ext250__load_store_cache_partial_write_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4123, 40, NULL,acmgt3__ext250__load_store_cache_partial_write_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4124, 48, NULL,acmgt3__ext250__load_store_cache_partial_write_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext251_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext251";
   query->symbol_name = "Ext251";
   query->guid = "dd5abc73-e90e-4da0-82ed-53c3a598ccf1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16870005 },
         { .reg = 0x00009888, .val = 0x1A870005 },
         { .reg = 0x00009888, .val = 0x12880005 },
         { .reg = 0x00009888, .val = 0x16880005 },
         { .reg = 0x00009888, .val = 0x16A70005 },
         { .reg = 0x00009888, .val = 0x1AA70005 },
         { .reg = 0x00009888, .val = 0x12A80005 },
         { .reg = 0x00009888, .val = 0x16A80005 },
         { .reg = 0x00009888, .val = 0x16C70005 },
         { .reg = 0x00009888, .val = 0x1AC70005 },
         { .reg = 0x00009888, .val = 0x12C80005 },
         { .reg = 0x00009888, .val = 0x16C80005 },
         { .reg = 0x00009888, .val = 0x16E70005 },
         { .reg = 0x00009888, .val = 0x1AE70005 },
         { .reg = 0x00009888, .val = 0x12E80005 },
         { .reg = 0x00009888, .val = 0x16E80005 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext251__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext251__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext251__avg_gpu_core_frequency__max,acmgt3__ext251__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4125, 24, NULL,acmgt3__ext251__load_store_cache_partial_write_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4126, 32, NULL,acmgt3__ext251__load_store_cache_partial_write_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4127, 40, NULL,acmgt3__ext251__load_store_cache_partial_write_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4128, 48, NULL,acmgt3__ext251__load_store_cache_partial_write_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext252_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext252";
   query->symbol_name = "Ext252";
   query->guid = "f4e6e4c6-94f3-4684-813c-b99cb703a638";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17870005 },
         { .reg = 0x00009888, .val = 0x1B870005 },
         { .reg = 0x00009888, .val = 0x13880005 },
         { .reg = 0x00009888, .val = 0x17880005 },
         { .reg = 0x00009888, .val = 0x17A70005 },
         { .reg = 0x00009888, .val = 0x1BA70005 },
         { .reg = 0x00009888, .val = 0x13A80005 },
         { .reg = 0x00009888, .val = 0x17A80005 },
         { .reg = 0x00009888, .val = 0x17C70005 },
         { .reg = 0x00009888, .val = 0x1BC70005 },
         { .reg = 0x00009888, .val = 0x13C80005 },
         { .reg = 0x00009888, .val = 0x17C80005 },
         { .reg = 0x00009888, .val = 0x17E70005 },
         { .reg = 0x00009888, .val = 0x1BE70005 },
         { .reg = 0x00009888, .val = 0x13E80005 },
         { .reg = 0x00009888, .val = 0x17E80005 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext252__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext252__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext252__avg_gpu_core_frequency__max,acmgt3__ext252__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4129, 24, NULL,acmgt3__ext252__load_store_cache_partial_write_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4130, 32, NULL,acmgt3__ext252__load_store_cache_partial_write_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4131, 40, NULL,acmgt3__ext252__load_store_cache_partial_write_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4132, 48, NULL,acmgt3__ext252__load_store_cache_partial_write_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext253_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext253";
   query->symbol_name = "Ext253";
   query->guid = "9eb32240-9aee-4864-8229-20ddbb84d6f2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext253__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext253__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext253__avg_gpu_core_frequency__max,acmgt3__ext253__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1060, 24, NULL,acmgt3__ext253__xve_load_store_cache_register_request_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1062, 32, NULL,acmgt3__ext253__xve_load_store_cache_register_request_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1064, 40, NULL,acmgt3__ext253__xve_load_store_cache_register_request_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1066, 48, NULL,acmgt3__ext253__xve_load_store_cache_register_request_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext254_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext254";
   query->symbol_name = "Ext254";
   query->guid = "6e1f70bd-36b6-432d-8576-5461e5ce55eb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext254__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext254__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext254__avg_gpu_core_frequency__max,acmgt3__ext254__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1068, 24, NULL,acmgt3__ext254__xve_load_store_cache_register_request_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1070, 32, NULL,acmgt3__ext254__xve_load_store_cache_register_request_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1072, 40, NULL,acmgt3__ext254__xve_load_store_cache_register_request_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1074, 48, NULL,acmgt3__ext254__xve_load_store_cache_register_request_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext255_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext255";
   query->symbol_name = "Ext255";
   query->guid = "0104ce81-df1b-4f1c-acc4-14cb239f06c1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext255__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext255__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext255__avg_gpu_core_frequency__max,acmgt3__ext255__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2579, 24, NULL,acmgt3__ext255__xve_load_store_cache_register_request_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2580, 32, NULL,acmgt3__ext255__xve_load_store_cache_register_request_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2581, 40, NULL,acmgt3__ext255__xve_load_store_cache_register_request_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2582, 48, NULL,acmgt3__ext255__xve_load_store_cache_register_request_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext256_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext256";
   query->symbol_name = "Ext256";
   query->guid = "4baeb5dd-8732-4330-8196-dd8b921d710f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext256__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext256__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext256__avg_gpu_core_frequency__max,acmgt3__ext256__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2583, 24, NULL,acmgt3__ext256__xve_load_store_cache_register_request_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2584, 32, NULL,acmgt3__ext256__xve_load_store_cache_register_request_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2585, 40, NULL,acmgt3__ext256__xve_load_store_cache_register_request_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2586, 48, NULL,acmgt3__ext256__xve_load_store_cache_register_request_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext257_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext257";
   query->symbol_name = "Ext257";
   query->guid = "9e4277a2-341a-4e2b-820d-f53beec1dd6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext257__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext257__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext257__avg_gpu_core_frequency__max,acmgt3__ext257__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4133, 24, NULL,acmgt3__ext257__xve_load_store_cache_register_request_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4134, 32, NULL,acmgt3__ext257__xve_load_store_cache_register_request_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4135, 40, NULL,acmgt3__ext257__xve_load_store_cache_register_request_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4136, 48, NULL,acmgt3__ext257__xve_load_store_cache_register_request_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext258_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext258";
   query->symbol_name = "Ext258";
   query->guid = "e318efaa-f015-4ee9-ae9d-485a352c06f6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext258__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext258__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext258__avg_gpu_core_frequency__max,acmgt3__ext258__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4137, 24, NULL,acmgt3__ext258__xve_load_store_cache_register_request_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4138, 32, NULL,acmgt3__ext258__xve_load_store_cache_register_request_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4139, 40, NULL,acmgt3__ext258__xve_load_store_cache_register_request_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4140, 48, NULL,acmgt3__ext258__xve_load_store_cache_register_request_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext259_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext259";
   query->symbol_name = "Ext259";
   query->guid = "cf9912aa-c74c-40f0-9120-07ef68972190";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890000 },
         { .reg = 0x00009888, .val = 0x1E890000 },
         { .reg = 0x00009888, .val = 0x24890000 },
         { .reg = 0x00009888, .val = 0x2A890000 },
         { .reg = 0x00009888, .val = 0x1AA90000 },
         { .reg = 0x00009888, .val = 0x1EA90000 },
         { .reg = 0x00009888, .val = 0x24A90000 },
         { .reg = 0x00009888, .val = 0x2AA90000 },
         { .reg = 0x00009888, .val = 0x1AC90000 },
         { .reg = 0x00009888, .val = 0x1EC90000 },
         { .reg = 0x00009888, .val = 0x24C90000 },
         { .reg = 0x00009888, .val = 0x2AC90000 },
         { .reg = 0x00009888, .val = 0x1AE90000 },
         { .reg = 0x00009888, .val = 0x1EE90000 },
         { .reg = 0x00009888, .val = 0x24E90000 },
         { .reg = 0x00009888, .val = 0x2AE90000 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext259__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext259__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext259__avg_gpu_core_frequency__max,acmgt3__ext259__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4141, 24, NULL,acmgt3__ext259__xve_load_store_cache_register_request_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4142, 32, NULL,acmgt3__ext259__xve_load_store_cache_register_request_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4143, 40, NULL,acmgt3__ext259__xve_load_store_cache_register_request_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4144, 48, NULL,acmgt3__ext259__xve_load_store_cache_register_request_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext260_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext260";
   query->symbol_name = "Ext260";
   query->guid = "b4b0f306-7714-4fd7-b32f-5bf89d0ea022";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890000 },
         { .reg = 0x00009888, .val = 0x1F890000 },
         { .reg = 0x00009888, .val = 0x25890000 },
         { .reg = 0x00009888, .val = 0x2B890000 },
         { .reg = 0x00009888, .val = 0x1BA90000 },
         { .reg = 0x00009888, .val = 0x1FA90000 },
         { .reg = 0x00009888, .val = 0x25A90000 },
         { .reg = 0x00009888, .val = 0x2BA90000 },
         { .reg = 0x00009888, .val = 0x1BC90000 },
         { .reg = 0x00009888, .val = 0x1FC90000 },
         { .reg = 0x00009888, .val = 0x25C90000 },
         { .reg = 0x00009888, .val = 0x2BC90000 },
         { .reg = 0x00009888, .val = 0x1BE90000 },
         { .reg = 0x00009888, .val = 0x1FE90000 },
         { .reg = 0x00009888, .val = 0x25E90000 },
         { .reg = 0x00009888, .val = 0x2BE90000 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext260__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext260__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext260__avg_gpu_core_frequency__max,acmgt3__ext260__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4145, 24, NULL,acmgt3__ext260__xve_load_store_cache_register_request_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4146, 32, NULL,acmgt3__ext260__xve_load_store_cache_register_request_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4147, 40, NULL,acmgt3__ext260__xve_load_store_cache_register_request_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4148, 48, NULL,acmgt3__ext260__xve_load_store_cache_register_request_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext261_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext261";
   query->symbol_name = "Ext261";
   query->guid = "0a9b31d6-473b-46c9-8ad1-d9ae2e47cc8c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext261__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext261__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext261__avg_gpu_core_frequency__max,acmgt3__ext261__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1075, 24, NULL,acmgt3__ext261__xve_load_store_cache_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1076, 32, NULL,acmgt3__ext261__xve_load_store_cache_register_response_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1077, 40, NULL,acmgt3__ext261__xve_load_store_cache_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1078, 48, NULL,acmgt3__ext261__xve_load_store_cache_register_response_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext262_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext262";
   query->symbol_name = "Ext262";
   query->guid = "17f09c56-52ed-4d95-a2c4-8d364f7f2055";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext262__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext262__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext262__avg_gpu_core_frequency__max,acmgt3__ext262__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1079, 24, NULL,acmgt3__ext262__xve_load_store_cache_register_response_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1080, 32, NULL,acmgt3__ext262__xve_load_store_cache_register_response_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1081, 40, NULL,acmgt3__ext262__xve_load_store_cache_register_response_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1082, 48, NULL,acmgt3__ext262__xve_load_store_cache_register_response_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext263_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext263";
   query->symbol_name = "Ext263";
   query->guid = "755de6ba-8321-4b8e-8b29-30928734d252";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext263__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext263__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext263__avg_gpu_core_frequency__max,acmgt3__ext263__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2587, 24, NULL,acmgt3__ext263__xve_load_store_cache_register_response_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2588, 32, NULL,acmgt3__ext263__xve_load_store_cache_register_response_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2589, 40, NULL,acmgt3__ext263__xve_load_store_cache_register_response_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2590, 48, NULL,acmgt3__ext263__xve_load_store_cache_register_response_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext264_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext264";
   query->symbol_name = "Ext264";
   query->guid = "b622f02d-6710-4412-94f9-4e4abba0bbaa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext264__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext264__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext264__avg_gpu_core_frequency__max,acmgt3__ext264__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2591, 24, NULL,acmgt3__ext264__xve_load_store_cache_register_response_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2592, 32, NULL,acmgt3__ext264__xve_load_store_cache_register_response_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2593, 40, NULL,acmgt3__ext264__xve_load_store_cache_register_response_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2594, 48, NULL,acmgt3__ext264__xve_load_store_cache_register_response_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext265_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext265";
   query->symbol_name = "Ext265";
   query->guid = "e448a51b-7b45-4454-b682-b3488a24b167";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext265__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext265__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext265__avg_gpu_core_frequency__max,acmgt3__ext265__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4149, 24, NULL,acmgt3__ext265__xve_load_store_cache_register_response_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4150, 32, NULL,acmgt3__ext265__xve_load_store_cache_register_response_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4151, 40, NULL,acmgt3__ext265__xve_load_store_cache_register_response_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4152, 48, NULL,acmgt3__ext265__xve_load_store_cache_register_response_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext266_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext266";
   query->symbol_name = "Ext266";
   query->guid = "df480a9e-5d23-4477-b5cf-e89d7590ff9c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext266__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext266__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext266__avg_gpu_core_frequency__max,acmgt3__ext266__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4153, 24, NULL,acmgt3__ext266__xve_load_store_cache_register_response_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4154, 32, NULL,acmgt3__ext266__xve_load_store_cache_register_response_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4155, 40, NULL,acmgt3__ext266__xve_load_store_cache_register_response_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4156, 48, NULL,acmgt3__ext266__xve_load_store_cache_register_response_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext267_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext267";
   query->symbol_name = "Ext267";
   query->guid = "d2569d38-f95c-4996-9f95-aa61ba11015a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890871 },
         { .reg = 0x00009888, .val = 0x14890051 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90871 },
         { .reg = 0x00009888, .val = 0x10A90051 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90871 },
         { .reg = 0x00009888, .val = 0x0CC90051 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90871 },
         { .reg = 0x00009888, .val = 0x08E90051 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext267__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext267__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext267__avg_gpu_core_frequency__max,acmgt3__ext267__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4157, 24, NULL,acmgt3__ext267__xve_load_store_cache_register_response_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4158, 32, NULL,acmgt3__ext267__xve_load_store_cache_register_response_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4159, 40, NULL,acmgt3__ext267__xve_load_store_cache_register_response_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4160, 48, NULL,acmgt3__ext267__xve_load_store_cache_register_response_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext268_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext268";
   query->symbol_name = "Ext268";
   query->guid = "95a739c5-5a9c-47df-836f-3b323b9d8df8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890871 },
         { .reg = 0x00009888, .val = 0x15890051 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90871 },
         { .reg = 0x00009888, .val = 0x11A90051 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90871 },
         { .reg = 0x00009888, .val = 0x0DC90051 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90871 },
         { .reg = 0x00009888, .val = 0x09E90051 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext268__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext268__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext268__avg_gpu_core_frequency__max,acmgt3__ext268__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4161, 24, NULL,acmgt3__ext268__xve_load_store_cache_register_response_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4162, 32, NULL,acmgt3__ext268__xve_load_store_cache_register_response_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4163, 40, NULL,acmgt3__ext268__xve_load_store_cache_register_response_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4164, 48, NULL,acmgt3__ext268__xve_load_store_cache_register_response_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext269_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext269";
   query->symbol_name = "Ext269";
   query->guid = "4ee78f20-69b6-4bcd-9d6f-06ebee2e2f54";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A890002 },
         { .reg = 0x00009888, .val = 0x1E890800 },
         { .reg = 0x00009888, .val = 0x24890040 },
         { .reg = 0x00009888, .val = 0x2A890002 },
         { .reg = 0x00009888, .val = 0x1AA90002 },
         { .reg = 0x00009888, .val = 0x1EA90800 },
         { .reg = 0x00009888, .val = 0x24A90040 },
         { .reg = 0x00009888, .val = 0x2AA90002 },
         { .reg = 0x00009888, .val = 0x1AC90002 },
         { .reg = 0x00009888, .val = 0x1EC90800 },
         { .reg = 0x00009888, .val = 0x24C90040 },
         { .reg = 0x00009888, .val = 0x2AC90002 },
         { .reg = 0x00009888, .val = 0x1AE90002 },
         { .reg = 0x00009888, .val = 0x1EE90800 },
         { .reg = 0x00009888, .val = 0x24E90040 },
         { .reg = 0x00009888, .val = 0x2AE90002 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890975 },
         { .reg = 0x00009888, .val = 0x14890155 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90975 },
         { .reg = 0x00009888, .val = 0x10A90155 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90975 },
         { .reg = 0x00009888, .val = 0x0CC90155 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90975 },
         { .reg = 0x00009888, .val = 0x08E90155 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext269__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext269__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext269__avg_gpu_core_frequency__max,acmgt3__ext269__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 979, 24, percentage_max_float,acmgt3__ext269__load_store_cache_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 980, 28, percentage_max_float,acmgt3__ext269__load_store_cache_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 981, 32, percentage_max_float,acmgt3__ext269__load_store_cache_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 982, 36, percentage_max_float,acmgt3__ext269__load_store_cache_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext270_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext270";
   query->symbol_name = "Ext270";
   query->guid = "e9217a53-0407-4df2-a014-8df62ecd2dcc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B890002 },
         { .reg = 0x00009888, .val = 0x1F890800 },
         { .reg = 0x00009888, .val = 0x25890040 },
         { .reg = 0x00009888, .val = 0x2B890002 },
         { .reg = 0x00009888, .val = 0x1BA90002 },
         { .reg = 0x00009888, .val = 0x1FA90800 },
         { .reg = 0x00009888, .val = 0x25A90040 },
         { .reg = 0x00009888, .val = 0x2BA90002 },
         { .reg = 0x00009888, .val = 0x1BC90002 },
         { .reg = 0x00009888, .val = 0x1FC90800 },
         { .reg = 0x00009888, .val = 0x25C90040 },
         { .reg = 0x00009888, .val = 0x2BC90002 },
         { .reg = 0x00009888, .val = 0x1BE90002 },
         { .reg = 0x00009888, .val = 0x1FE90800 },
         { .reg = 0x00009888, .val = 0x25E90040 },
         { .reg = 0x00009888, .val = 0x2BE90002 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890975 },
         { .reg = 0x00009888, .val = 0x15890155 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90975 },
         { .reg = 0x00009888, .val = 0x11A90155 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90975 },
         { .reg = 0x00009888, .val = 0x0DC90155 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90975 },
         { .reg = 0x00009888, .val = 0x09E90155 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext270__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext270__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext270__avg_gpu_core_frequency__max,acmgt3__ext270__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 983, 24, percentage_max_float,acmgt3__ext270__load_store_cache_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 984, 28, percentage_max_float,acmgt3__ext270__load_store_cache_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 985, 32, percentage_max_float,acmgt3__ext270__load_store_cache_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 986, 36, percentage_max_float,acmgt3__ext270__load_store_cache_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext271_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext271";
   query->symbol_name = "Ext271";
   query->guid = "7d6d9a79-6ddf-4970-9fcd-ece8cfc4f26b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A890002 },
         { .reg = 0x00009888, .val = 0x1E890800 },
         { .reg = 0x00009888, .val = 0x24890040 },
         { .reg = 0x00009888, .val = 0x2A890002 },
         { .reg = 0x00009888, .val = 0x1AA90002 },
         { .reg = 0x00009888, .val = 0x1EA90800 },
         { .reg = 0x00009888, .val = 0x24A90040 },
         { .reg = 0x00009888, .val = 0x2AA90002 },
         { .reg = 0x00009888, .val = 0x1AC90002 },
         { .reg = 0x00009888, .val = 0x1EC90800 },
         { .reg = 0x00009888, .val = 0x24C90040 },
         { .reg = 0x00009888, .val = 0x2AC90002 },
         { .reg = 0x00009888, .val = 0x1AE90002 },
         { .reg = 0x00009888, .val = 0x1EE90800 },
         { .reg = 0x00009888, .val = 0x24E90040 },
         { .reg = 0x00009888, .val = 0x2AE90002 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890975 },
         { .reg = 0x00009888, .val = 0x14890155 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90975 },
         { .reg = 0x00009888, .val = 0x10A90155 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90975 },
         { .reg = 0x00009888, .val = 0x0CC90155 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90975 },
         { .reg = 0x00009888, .val = 0x08E90155 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext271__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext271__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext271__avg_gpu_core_frequency__max,acmgt3__ext271__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 2475, 24, percentage_max_float,acmgt3__ext271__load_store_cache_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 2476, 28, percentage_max_float,acmgt3__ext271__load_store_cache_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 2477, 32, percentage_max_float,acmgt3__ext271__load_store_cache_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 2478, 36, percentage_max_float,acmgt3__ext271__load_store_cache_input_available_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext272_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext272";
   query->symbol_name = "Ext272";
   query->guid = "0ecd2c83-ea1b-4801-b6c0-c571e301477b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B890002 },
         { .reg = 0x00009888, .val = 0x1F890800 },
         { .reg = 0x00009888, .val = 0x25890040 },
         { .reg = 0x00009888, .val = 0x2B890002 },
         { .reg = 0x00009888, .val = 0x1BA90002 },
         { .reg = 0x00009888, .val = 0x1FA90800 },
         { .reg = 0x00009888, .val = 0x25A90040 },
         { .reg = 0x00009888, .val = 0x2BA90002 },
         { .reg = 0x00009888, .val = 0x1BC90002 },
         { .reg = 0x00009888, .val = 0x1FC90800 },
         { .reg = 0x00009888, .val = 0x25C90040 },
         { .reg = 0x00009888, .val = 0x2BC90002 },
         { .reg = 0x00009888, .val = 0x1BE90002 },
         { .reg = 0x00009888, .val = 0x1FE90800 },
         { .reg = 0x00009888, .val = 0x25E90040 },
         { .reg = 0x00009888, .val = 0x2BE90002 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890975 },
         { .reg = 0x00009888, .val = 0x15890155 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90975 },
         { .reg = 0x00009888, .val = 0x11A90155 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90975 },
         { .reg = 0x00009888, .val = 0x0DC90155 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90975 },
         { .reg = 0x00009888, .val = 0x09E90155 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext272__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext272__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext272__avg_gpu_core_frequency__max,acmgt3__ext272__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 2479, 24, percentage_max_float,acmgt3__ext272__load_store_cache_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 2480, 28, percentage_max_float,acmgt3__ext272__load_store_cache_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 2481, 32, percentage_max_float,acmgt3__ext272__load_store_cache_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 2482, 36, percentage_max_float,acmgt3__ext272__load_store_cache_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext273_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext273";
   query->symbol_name = "Ext273";
   query->guid = "377395f6-3e5d-45ab-a2ff-980f1f795590";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A890002 },
         { .reg = 0x00009888, .val = 0x1E890800 },
         { .reg = 0x00009888, .val = 0x24890040 },
         { .reg = 0x00009888, .val = 0x2A890002 },
         { .reg = 0x00009888, .val = 0x1AA90002 },
         { .reg = 0x00009888, .val = 0x1EA90800 },
         { .reg = 0x00009888, .val = 0x24A90040 },
         { .reg = 0x00009888, .val = 0x2AA90002 },
         { .reg = 0x00009888, .val = 0x1AC90002 },
         { .reg = 0x00009888, .val = 0x1EC90800 },
         { .reg = 0x00009888, .val = 0x24C90040 },
         { .reg = 0x00009888, .val = 0x2AC90002 },
         { .reg = 0x00009888, .val = 0x1AE90002 },
         { .reg = 0x00009888, .val = 0x1EE90800 },
         { .reg = 0x00009888, .val = 0x24E90040 },
         { .reg = 0x00009888, .val = 0x2AE90002 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890975 },
         { .reg = 0x00009888, .val = 0x14890155 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90975 },
         { .reg = 0x00009888, .val = 0x10A90155 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90975 },
         { .reg = 0x00009888, .val = 0x0CC90155 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90975 },
         { .reg = 0x00009888, .val = 0x08E90155 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext273__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext273__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext273__avg_gpu_core_frequency__max,acmgt3__ext273__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4165, 24, percentage_max_float,acmgt3__ext273__load_store_cache_input_available_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4166, 28, percentage_max_float,acmgt3__ext273__load_store_cache_input_available_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4167, 32, percentage_max_float,acmgt3__ext273__load_store_cache_input_available_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4168, 36, percentage_max_float,acmgt3__ext273__load_store_cache_input_available_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext274_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext274";
   query->symbol_name = "Ext274";
   query->guid = "ebf4b987-f2e1-45c5-83c1-145baa637929";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B890002 },
         { .reg = 0x00009888, .val = 0x1F890800 },
         { .reg = 0x00009888, .val = 0x25890040 },
         { .reg = 0x00009888, .val = 0x2B890002 },
         { .reg = 0x00009888, .val = 0x1BA90002 },
         { .reg = 0x00009888, .val = 0x1FA90800 },
         { .reg = 0x00009888, .val = 0x25A90040 },
         { .reg = 0x00009888, .val = 0x2BA90002 },
         { .reg = 0x00009888, .val = 0x1BC90002 },
         { .reg = 0x00009888, .val = 0x1FC90800 },
         { .reg = 0x00009888, .val = 0x25C90040 },
         { .reg = 0x00009888, .val = 0x2BC90002 },
         { .reg = 0x00009888, .val = 0x1BE90002 },
         { .reg = 0x00009888, .val = 0x1FE90800 },
         { .reg = 0x00009888, .val = 0x25E90040 },
         { .reg = 0x00009888, .val = 0x2BE90002 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890975 },
         { .reg = 0x00009888, .val = 0x15890155 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90975 },
         { .reg = 0x00009888, .val = 0x11A90155 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90975 },
         { .reg = 0x00009888, .val = 0x0DC90155 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90975 },
         { .reg = 0x00009888, .val = 0x09E90155 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext274__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext274__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext274__avg_gpu_core_frequency__max,acmgt3__ext274__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4169, 24, percentage_max_float,acmgt3__ext274__load_store_cache_input_available_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4170, 28, percentage_max_float,acmgt3__ext274__load_store_cache_input_available_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4171, 32, percentage_max_float,acmgt3__ext274__load_store_cache_input_available_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4172, 36, percentage_max_float,acmgt3__ext274__load_store_cache_input_available_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext275_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext275";
   query->symbol_name = "Ext275";
   query->guid = "e0559ea9-aae3-4ede-8d15-30dcc8c4a202";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A890002 },
         { .reg = 0x00009888, .val = 0x1E890800 },
         { .reg = 0x00009888, .val = 0x24890040 },
         { .reg = 0x00009888, .val = 0x2A890002 },
         { .reg = 0x00009888, .val = 0x1AA90002 },
         { .reg = 0x00009888, .val = 0x1EA90800 },
         { .reg = 0x00009888, .val = 0x24A90040 },
         { .reg = 0x00009888, .val = 0x2AA90002 },
         { .reg = 0x00009888, .val = 0x1AC90002 },
         { .reg = 0x00009888, .val = 0x1EC90800 },
         { .reg = 0x00009888, .val = 0x24C90040 },
         { .reg = 0x00009888, .val = 0x2AC90002 },
         { .reg = 0x00009888, .val = 0x1AE90002 },
         { .reg = 0x00009888, .val = 0x1EE90800 },
         { .reg = 0x00009888, .val = 0x24E90040 },
         { .reg = 0x00009888, .val = 0x2AE90002 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890975 },
         { .reg = 0x00009888, .val = 0x14890155 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90975 },
         { .reg = 0x00009888, .val = 0x10A90155 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90975 },
         { .reg = 0x00009888, .val = 0x0CC90155 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90975 },
         { .reg = 0x00009888, .val = 0x08E90155 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext275__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext275__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext275__avg_gpu_core_frequency__max,acmgt3__ext275__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4173, 24, percentage_max_float,acmgt3__ext275__load_store_cache_input_available_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4174, 28, percentage_max_float,acmgt3__ext275__load_store_cache_input_available_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4175, 32, percentage_max_float,acmgt3__ext275__load_store_cache_input_available_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4176, 36, percentage_max_float,acmgt3__ext275__load_store_cache_input_available_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext276_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext276";
   query->symbol_name = "Ext276";
   query->guid = "180b2a02-9d8c-4bf9-be0b-31cf265c21da";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B890002 },
         { .reg = 0x00009888, .val = 0x1F890800 },
         { .reg = 0x00009888, .val = 0x25890040 },
         { .reg = 0x00009888, .val = 0x2B890002 },
         { .reg = 0x00009888, .val = 0x1BA90002 },
         { .reg = 0x00009888, .val = 0x1FA90800 },
         { .reg = 0x00009888, .val = 0x25A90040 },
         { .reg = 0x00009888, .val = 0x2BA90002 },
         { .reg = 0x00009888, .val = 0x1BC90002 },
         { .reg = 0x00009888, .val = 0x1FC90800 },
         { .reg = 0x00009888, .val = 0x25C90040 },
         { .reg = 0x00009888, .val = 0x2BC90002 },
         { .reg = 0x00009888, .val = 0x1BE90002 },
         { .reg = 0x00009888, .val = 0x1FE90800 },
         { .reg = 0x00009888, .val = 0x25E90040 },
         { .reg = 0x00009888, .val = 0x2BE90002 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890975 },
         { .reg = 0x00009888, .val = 0x15890155 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90975 },
         { .reg = 0x00009888, .val = 0x11A90155 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90975 },
         { .reg = 0x00009888, .val = 0x0DC90155 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90975 },
         { .reg = 0x00009888, .val = 0x09E90155 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext276__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext276__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext276__avg_gpu_core_frequency__max,acmgt3__ext276__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4177, 24, percentage_max_float,acmgt3__ext276__load_store_cache_input_available_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4178, 28, percentage_max_float,acmgt3__ext276__load_store_cache_input_available_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4179, 32, percentage_max_float,acmgt3__ext276__load_store_cache_input_available_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4180, 36, percentage_max_float,acmgt3__ext276__load_store_cache_input_available_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext277_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext277";
   query->symbol_name = "Ext277";
   query->guid = "4e381e22-6068-4a63-9fea-270aee7731af";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890934 },
         { .reg = 0x00009888, .val = 0x14890114 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90934 },
         { .reg = 0x00009888, .val = 0x10A90114 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90934 },
         { .reg = 0x00009888, .val = 0x0CC90114 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90934 },
         { .reg = 0x00009888, .val = 0x08E90114 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext277__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext277__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext277__avg_gpu_core_frequency__max,acmgt3__ext277__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 987, 24, percentage_max_float,acmgt3__ext277__load_store_cache_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 988, 28, percentage_max_float,acmgt3__ext277__load_store_cache_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 989, 32, percentage_max_float,acmgt3__ext277__load_store_cache_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 990, 36, percentage_max_float,acmgt3__ext277__load_store_cache_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext278_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext278";
   query->symbol_name = "Ext278";
   query->guid = "3e47b601-d0e5-4eac-a32a-d4419b455ef6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890934 },
         { .reg = 0x00009888, .val = 0x15890114 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90934 },
         { .reg = 0x00009888, .val = 0x11A90114 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90934 },
         { .reg = 0x00009888, .val = 0x0DC90114 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90934 },
         { .reg = 0x00009888, .val = 0x09E90114 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext278__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext278__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext278__avg_gpu_core_frequency__max,acmgt3__ext278__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 991, 24, percentage_max_float,acmgt3__ext278__load_store_cache_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 992, 28, percentage_max_float,acmgt3__ext278__load_store_cache_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 993, 32, percentage_max_float,acmgt3__ext278__load_store_cache_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 994, 36, percentage_max_float,acmgt3__ext278__load_store_cache_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext279_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext279";
   query->symbol_name = "Ext279";
   query->guid = "45b87d00-391e-46a0-8750-61da7a17db1c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890934 },
         { .reg = 0x00009888, .val = 0x14890114 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90934 },
         { .reg = 0x00009888, .val = 0x10A90114 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90934 },
         { .reg = 0x00009888, .val = 0x0CC90114 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90934 },
         { .reg = 0x00009888, .val = 0x08E90114 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext279__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext279__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext279__avg_gpu_core_frequency__max,acmgt3__ext279__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 2483, 24, percentage_max_float,acmgt3__ext279__load_store_cache_output_ready_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 2484, 28, percentage_max_float,acmgt3__ext279__load_store_cache_output_ready_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 2485, 32, percentage_max_float,acmgt3__ext279__load_store_cache_output_ready_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 2486, 36, percentage_max_float,acmgt3__ext279__load_store_cache_output_ready_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext280_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext280";
   query->symbol_name = "Ext280";
   query->guid = "85c3a4dc-ebc9-45e6-b572-fab58fa5bdd2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890934 },
         { .reg = 0x00009888, .val = 0x15890114 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90934 },
         { .reg = 0x00009888, .val = 0x11A90114 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90934 },
         { .reg = 0x00009888, .val = 0x0DC90114 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90934 },
         { .reg = 0x00009888, .val = 0x09E90114 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext280__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext280__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext280__avg_gpu_core_frequency__max,acmgt3__ext280__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 2487, 24, percentage_max_float,acmgt3__ext280__load_store_cache_output_ready_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 2488, 28, percentage_max_float,acmgt3__ext280__load_store_cache_output_ready_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 2489, 32, percentage_max_float,acmgt3__ext280__load_store_cache_output_ready_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 2490, 36, percentage_max_float,acmgt3__ext280__load_store_cache_output_ready_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext281_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext281";
   query->symbol_name = "Ext281";
   query->guid = "d7725644-0058-46cd-935d-55e1bf8d0e8b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890934 },
         { .reg = 0x00009888, .val = 0x14890114 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90934 },
         { .reg = 0x00009888, .val = 0x10A90114 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90934 },
         { .reg = 0x00009888, .val = 0x0CC90114 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90934 },
         { .reg = 0x00009888, .val = 0x08E90114 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext281__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext281__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext281__avg_gpu_core_frequency__max,acmgt3__ext281__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4181, 24, percentage_max_float,acmgt3__ext281__load_store_cache_output_ready_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4182, 28, percentage_max_float,acmgt3__ext281__load_store_cache_output_ready_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4183, 32, percentage_max_float,acmgt3__ext281__load_store_cache_output_ready_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4184, 36, percentage_max_float,acmgt3__ext281__load_store_cache_output_ready_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext282_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext282";
   query->symbol_name = "Ext282";
   query->guid = "234accb5-7742-4ff5-b3d6-598cc74a4f95";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890934 },
         { .reg = 0x00009888, .val = 0x15890114 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90934 },
         { .reg = 0x00009888, .val = 0x11A90114 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90934 },
         { .reg = 0x00009888, .val = 0x0DC90114 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90934 },
         { .reg = 0x00009888, .val = 0x09E90114 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext282__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext282__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext282__avg_gpu_core_frequency__max,acmgt3__ext282__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4185, 24, percentage_max_float,acmgt3__ext282__load_store_cache_output_ready_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4186, 28, percentage_max_float,acmgt3__ext282__load_store_cache_output_ready_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4187, 32, percentage_max_float,acmgt3__ext282__load_store_cache_output_ready_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4188, 36, percentage_max_float,acmgt3__ext282__load_store_cache_output_ready_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext283_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext283";
   query->symbol_name = "Ext283";
   query->guid = "75c93a0c-e686-4e48-baca-a557d2284a06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A89001C },
         { .reg = 0x00009888, .val = 0x1E897000 },
         { .reg = 0x00009888, .val = 0x24890380 },
         { .reg = 0x00009888, .val = 0x2A89001C },
         { .reg = 0x00009888, .val = 0x1AA9001C },
         { .reg = 0x00009888, .val = 0x1EA97000 },
         { .reg = 0x00009888, .val = 0x24A90380 },
         { .reg = 0x00009888, .val = 0x2AA9001C },
         { .reg = 0x00009888, .val = 0x1AC9001C },
         { .reg = 0x00009888, .val = 0x1EC97000 },
         { .reg = 0x00009888, .val = 0x24C90380 },
         { .reg = 0x00009888, .val = 0x2AC9001C },
         { .reg = 0x00009888, .val = 0x1AE9001C },
         { .reg = 0x00009888, .val = 0x1EE97000 },
         { .reg = 0x00009888, .val = 0x24E90380 },
         { .reg = 0x00009888, .val = 0x2AE9001C },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x0287AA00 },
         { .reg = 0x00009888, .val = 0x02890406 },
         { .reg = 0x00009888, .val = 0x04890082 },
         { .reg = 0x00009888, .val = 0x12890934 },
         { .reg = 0x00009888, .val = 0x14890114 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x02A700AA },
         { .reg = 0x00009888, .val = 0x02A90406 },
         { .reg = 0x00009888, .val = 0x04A90082 },
         { .reg = 0x00009888, .val = 0x0EA90934 },
         { .reg = 0x00009888, .val = 0x10A90114 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x00C7AA00 },
         { .reg = 0x00009888, .val = 0x02C90406 },
         { .reg = 0x00009888, .val = 0x04C90082 },
         { .reg = 0x00009888, .val = 0x0AC90934 },
         { .reg = 0x00009888, .val = 0x0CC90114 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E700AA },
         { .reg = 0x00009888, .val = 0x02E90406 },
         { .reg = 0x00009888, .val = 0x04E90082 },
         { .reg = 0x00009888, .val = 0x06E90934 },
         { .reg = 0x00009888, .val = 0x08E90114 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext283__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext283__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext283__avg_gpu_core_frequency__max,acmgt3__ext283__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4189, 24, percentage_max_float,acmgt3__ext283__load_store_cache_output_ready_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4190, 28, percentage_max_float,acmgt3__ext283__load_store_cache_output_ready_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4191, 32, percentage_max_float,acmgt3__ext283__load_store_cache_output_ready_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4192, 36, percentage_max_float,acmgt3__ext283__load_store_cache_output_ready_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext284_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext284";
   query->symbol_name = "Ext284";
   query->guid = "6059f40a-ba6c-4032-8eb0-a3a60760d22e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B89001C },
         { .reg = 0x00009888, .val = 0x1F897000 },
         { .reg = 0x00009888, .val = 0x25890380 },
         { .reg = 0x00009888, .val = 0x2B89001C },
         { .reg = 0x00009888, .val = 0x1BA9001C },
         { .reg = 0x00009888, .val = 0x1FA97000 },
         { .reg = 0x00009888, .val = 0x25A90380 },
         { .reg = 0x00009888, .val = 0x2BA9001C },
         { .reg = 0x00009888, .val = 0x1BC9001C },
         { .reg = 0x00009888, .val = 0x1FC97000 },
         { .reg = 0x00009888, .val = 0x25C90380 },
         { .reg = 0x00009888, .val = 0x2BC9001C },
         { .reg = 0x00009888, .val = 0x1BE9001C },
         { .reg = 0x00009888, .val = 0x1FE97000 },
         { .reg = 0x00009888, .val = 0x25E90380 },
         { .reg = 0x00009888, .val = 0x2BE9001C },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x0387AA00 },
         { .reg = 0x00009888, .val = 0x03890406 },
         { .reg = 0x00009888, .val = 0x05890082 },
         { .reg = 0x00009888, .val = 0x13890934 },
         { .reg = 0x00009888, .val = 0x15890114 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x03A700AA },
         { .reg = 0x00009888, .val = 0x03A90406 },
         { .reg = 0x00009888, .val = 0x05A90082 },
         { .reg = 0x00009888, .val = 0x0FA90934 },
         { .reg = 0x00009888, .val = 0x11A90114 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x01C7AA00 },
         { .reg = 0x00009888, .val = 0x03C90406 },
         { .reg = 0x00009888, .val = 0x05C90082 },
         { .reg = 0x00009888, .val = 0x0BC90934 },
         { .reg = 0x00009888, .val = 0x0DC90114 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E700AA },
         { .reg = 0x00009888, .val = 0x03E90406 },
         { .reg = 0x00009888, .val = 0x05E90082 },
         { .reg = 0x00009888, .val = 0x07E90934 },
         { .reg = 0x00009888, .val = 0x09E90114 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext284__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext284__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext284__avg_gpu_core_frequency__max,acmgt3__ext284__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4193, 24, percentage_max_float,acmgt3__ext284__load_store_cache_output_ready_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4194, 28, percentage_max_float,acmgt3__ext284__load_store_cache_output_ready_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4195, 32, percentage_max_float,acmgt3__ext284__load_store_cache_output_ready_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4196, 36, percentage_max_float,acmgt3__ext284__load_store_cache_output_ready_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext285_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext285";
   query->symbol_name = "Ext285";
   query->guid = "030a5d74-26a8-40ea-b40e-be5f1e0cd212";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x096B1001 },
         { .reg = 0x00009888, .val = 0x096C1000 },
         { .reg = 0x00009888, .val = 0x016B0002 },
         { .reg = 0x00009888, .val = 0x076B0080 },
         { .reg = 0x00009888, .val = 0x036B0000 },
         { .reg = 0x00009888, .val = 0x016C0002 },
         { .reg = 0x00009888, .val = 0x056C0042 },
         { .reg = 0x00009888, .val = 0x076C0000 },
         { .reg = 0x00009888, .val = 0x036C0000 },
         { .reg = 0x00009888, .val = 0x0003002A },
         { .reg = 0x00009888, .val = 0x00040FEA },
         { .reg = 0x00009888, .val = 0x00050555 },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020AAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext285__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext285__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext285__avg_gpu_core_frequency__max,acmgt3__ext285__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 4197, 24, percentage_max_float,acmgt3__ext285__l3_stall_l3_bank30__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 4198, 28, percentage_max_float,acmgt3__ext285__l3_stall_l3_bank31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext286_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext286";
   query->symbol_name = "Ext286";
   query->guid = "92ecf953-51a1-47dd-b5f4-f942e64b9c7c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x0C030480 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02040008 },
         { .reg = 0x00009888, .val = 0x02050004 },
         { .reg = 0x00009888, .val = 0x0C080012 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x02080008 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x0E030480 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02040080 },
         { .reg = 0x00009888, .val = 0x02050040 },
         { .reg = 0x00009888, .val = 0x0E080012 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x02080080 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x10030480 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02040800 },
         { .reg = 0x00009888, .val = 0x02050400 },
         { .reg = 0x00009888, .val = 0x10080012 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x02080800 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x12030480 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02048000 },
         { .reg = 0x00009888, .val = 0x02054000 },
         { .reg = 0x00009888, .val = 0x12080012 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x020800FA },
         { .reg = 0x00009888, .val = 0x0202A500 },
         { .reg = 0x00009888, .val = 0x02032400 },
         { .reg = 0x00009888, .val = 0x04031252 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x48030200 },
         { .reg = 0x00009888, .val = 0x4A030200 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003280A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext286__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext286__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext286__avg_gpu_core_frequency__max,acmgt3__ext286__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 1760, 24, percentage_max_float,acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 1761, 28, percentage_max_float,acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2287, 32, percentage_max_float,acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2288, 36, percentage_max_float,acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 4199, 40, percentage_max_float,acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 4200, 44, percentage_max_float,acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 4201, 48, percentage_max_float,acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 4202, 52, percentage_max_float,acmgt3__ext286__color_pipe_cache_latency2_stall_l3_node7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext288_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext288";
   query->symbol_name = "Ext288";
   query->guid = "1f9ac2d2-5aee-4e58-acb1-9d609849ac7a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x14833000 },
         { .reg = 0x00009888, .val = 0x14A33000 },
         { .reg = 0x00009888, .val = 0x14C33000 },
         { .reg = 0x00009888, .val = 0x14E33000 },
         { .reg = 0x00009888, .val = 0x04830450 },
         { .reg = 0x00009888, .val = 0x068304D2 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x08A30450 },
         { .reg = 0x00009888, .val = 0x0AA304D2 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x0CC30450 },
         { .reg = 0x00009888, .val = 0x0EC304D2 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x10E30450 },
         { .reg = 0x00009888, .val = 0x12E304D2 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext288__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext288__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext288__avg_gpu_core_frequency__max,acmgt3__ext288__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1203, 24, percentage_max_float,acmgt3__ext288__sampler_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1204, 28, percentage_max_float,acmgt3__ext288__sampler_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1205, 32, percentage_max_float,acmgt3__ext288__sampler_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1206, 36, percentage_max_float,acmgt3__ext288__sampler_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext289_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext289";
   query->symbol_name = "Ext289";
   query->guid = "aa8781c1-b216-4aec-918a-142fe18607ac";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x15833000 },
         { .reg = 0x00009888, .val = 0x15A33000 },
         { .reg = 0x00009888, .val = 0x15C33000 },
         { .reg = 0x00009888, .val = 0x15E33000 },
         { .reg = 0x00009888, .val = 0x05830450 },
         { .reg = 0x00009888, .val = 0x078304D2 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x09A30450 },
         { .reg = 0x00009888, .val = 0x0BA304D2 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x0DC30450 },
         { .reg = 0x00009888, .val = 0x0FC304D2 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x11E30450 },
         { .reg = 0x00009888, .val = 0x13E304D2 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext289__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext289__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext289__avg_gpu_core_frequency__max,acmgt3__ext289__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1207, 24, percentage_max_float,acmgt3__ext289__sampler_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1208, 28, percentage_max_float,acmgt3__ext289__sampler_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1209, 32, percentage_max_float,acmgt3__ext289__sampler_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1210, 36, percentage_max_float,acmgt3__ext289__sampler_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext290_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext290";
   query->symbol_name = "Ext290";
   query->guid = "16a4c831-37d6-4fff-a77f-0e4c5b325510";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x14833000 },
         { .reg = 0x00009888, .val = 0x14A33000 },
         { .reg = 0x00009888, .val = 0x14C33000 },
         { .reg = 0x00009888, .val = 0x14E33000 },
         { .reg = 0x00009888, .val = 0x04830450 },
         { .reg = 0x00009888, .val = 0x068304D2 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x08A30450 },
         { .reg = 0x00009888, .val = 0x0AA304D2 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x0CC30450 },
         { .reg = 0x00009888, .val = 0x0EC304D2 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x10E30450 },
         { .reg = 0x00009888, .val = 0x12E304D2 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext290__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext290__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext290__avg_gpu_core_frequency__max,acmgt3__ext290__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 2991, 24, percentage_max_float,acmgt3__ext290__sampler_output_ready_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 2992, 28, percentage_max_float,acmgt3__ext290__sampler_output_ready_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 2993, 32, percentage_max_float,acmgt3__ext290__sampler_output_ready_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 2994, 36, percentage_max_float,acmgt3__ext290__sampler_output_ready_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext291_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext291";
   query->symbol_name = "Ext291";
   query->guid = "be7c8afd-0a80-4cd9-8266-faf796deb5d8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x15833000 },
         { .reg = 0x00009888, .val = 0x15A33000 },
         { .reg = 0x00009888, .val = 0x15C33000 },
         { .reg = 0x00009888, .val = 0x15E33000 },
         { .reg = 0x00009888, .val = 0x05830450 },
         { .reg = 0x00009888, .val = 0x078304D2 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x09A30450 },
         { .reg = 0x00009888, .val = 0x0BA304D2 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x0DC30450 },
         { .reg = 0x00009888, .val = 0x0FC304D2 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x11E30450 },
         { .reg = 0x00009888, .val = 0x13E304D2 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext291__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext291__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext291__avg_gpu_core_frequency__max,acmgt3__ext291__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 2995, 24, percentage_max_float,acmgt3__ext291__sampler_output_ready_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 2996, 28, percentage_max_float,acmgt3__ext291__sampler_output_ready_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 2997, 32, percentage_max_float,acmgt3__ext291__sampler_output_ready_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 2998, 36, percentage_max_float,acmgt3__ext291__sampler_output_ready_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext292_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext292";
   query->symbol_name = "Ext292";
   query->guid = "d87b1ecd-4ef5-4632-9f83-19ca481f2ece";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x14833000 },
         { .reg = 0x00009888, .val = 0x14A33000 },
         { .reg = 0x00009888, .val = 0x14C33000 },
         { .reg = 0x00009888, .val = 0x14E33000 },
         { .reg = 0x00009888, .val = 0x04830450 },
         { .reg = 0x00009888, .val = 0x068304D2 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x08A30450 },
         { .reg = 0x00009888, .val = 0x0AA304D2 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x0CC30450 },
         { .reg = 0x00009888, .val = 0x0EC304D2 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x10E30450 },
         { .reg = 0x00009888, .val = 0x12E304D2 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext292__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext292__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext292__avg_gpu_core_frequency__max,acmgt3__ext292__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4203, 24, percentage_max_float,acmgt3__ext292__sampler_output_ready_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4204, 28, percentage_max_float,acmgt3__ext292__sampler_output_ready_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4205, 32, percentage_max_float,acmgt3__ext292__sampler_output_ready_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4206, 36, percentage_max_float,acmgt3__ext292__sampler_output_ready_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext293_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext293";
   query->symbol_name = "Ext293";
   query->guid = "918f11cd-e0a7-4503-87b3-0f16c4464d77";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x15833000 },
         { .reg = 0x00009888, .val = 0x15A33000 },
         { .reg = 0x00009888, .val = 0x15C33000 },
         { .reg = 0x00009888, .val = 0x15E33000 },
         { .reg = 0x00009888, .val = 0x05830450 },
         { .reg = 0x00009888, .val = 0x078304D2 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x09A30450 },
         { .reg = 0x00009888, .val = 0x0BA304D2 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x0DC30450 },
         { .reg = 0x00009888, .val = 0x0FC304D2 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x11E30450 },
         { .reg = 0x00009888, .val = 0x13E304D2 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext293__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext293__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext293__avg_gpu_core_frequency__max,acmgt3__ext293__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4207, 24, percentage_max_float,acmgt3__ext293__sampler_output_ready_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4208, 28, percentage_max_float,acmgt3__ext293__sampler_output_ready_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4209, 32, percentage_max_float,acmgt3__ext293__sampler_output_ready_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4210, 36, percentage_max_float,acmgt3__ext293__sampler_output_ready_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext294_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext294";
   query->symbol_name = "Ext294";
   query->guid = "1b1d6474-3018-4d9a-938e-11d81cc70491";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x14833000 },
         { .reg = 0x00009888, .val = 0x14A33000 },
         { .reg = 0x00009888, .val = 0x14C33000 },
         { .reg = 0x00009888, .val = 0x14E33000 },
         { .reg = 0x00009888, .val = 0x04830450 },
         { .reg = 0x00009888, .val = 0x068304D2 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x08A30450 },
         { .reg = 0x00009888, .val = 0x0AA304D2 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x0CC30450 },
         { .reg = 0x00009888, .val = 0x0EC304D2 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x10E30450 },
         { .reg = 0x00009888, .val = 0x12E304D2 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext294__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext294__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext294__avg_gpu_core_frequency__max,acmgt3__ext294__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4211, 24, percentage_max_float,acmgt3__ext294__sampler_output_ready_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4212, 28, percentage_max_float,acmgt3__ext294__sampler_output_ready_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4213, 32, percentage_max_float,acmgt3__ext294__sampler_output_ready_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4214, 36, percentage_max_float,acmgt3__ext294__sampler_output_ready_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext295_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext295";
   query->symbol_name = "Ext295";
   query->guid = "50114a1e-a637-4027-9ee5-42d12d569896";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x15833000 },
         { .reg = 0x00009888, .val = 0x15A33000 },
         { .reg = 0x00009888, .val = 0x15C33000 },
         { .reg = 0x00009888, .val = 0x15E33000 },
         { .reg = 0x00009888, .val = 0x05830450 },
         { .reg = 0x00009888, .val = 0x078304D2 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x09A30450 },
         { .reg = 0x00009888, .val = 0x0BA304D2 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x0DC30450 },
         { .reg = 0x00009888, .val = 0x0FC304D2 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x11E30450 },
         { .reg = 0x00009888, .val = 0x13E304D2 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext295__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext295__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext295__avg_gpu_core_frequency__max,acmgt3__ext295__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4215, 24, percentage_max_float,acmgt3__ext295__sampler_output_ready_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4216, 28, percentage_max_float,acmgt3__ext295__sampler_output_ready_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4217, 32, percentage_max_float,acmgt3__ext295__sampler_output_ready_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4218, 36, percentage_max_float,acmgt3__ext295__sampler_output_ready_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext296_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext296";
   query->symbol_name = "Ext296";
   query->guid = "d67549fb-4308-437b-8c48-662a3782b3fa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830D00 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30034 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30D00 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30034 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830D00 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30034 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30D00 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30034 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830D00 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x0AA30034 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x08C30D00 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x08E30034 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x07830D00 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x07A30034 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x05C30D00 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x05E30034 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext296__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext296__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext296__avg_gpu_core_frequency__max,acmgt3__ext296__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 899, 24, percentage_max_float,acmgt3__ext296__sampler_busy_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 900, 28, percentage_max_float,acmgt3__ext296__sampler_busy_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 901, 32, percentage_max_float,acmgt3__ext296__sampler_busy_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 902, 36, percentage_max_float,acmgt3__ext296__sampler_busy_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 903, 40, percentage_max_float,acmgt3__ext296__sampler_busy_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 904, 44, percentage_max_float,acmgt3__ext296__sampler_busy_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 905, 48, percentage_max_float,acmgt3__ext296__sampler_busy_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 906, 52, percentage_max_float,acmgt3__ext296__sampler_busy_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 2999, 56, percentage_max_float,acmgt3__ext296__sampler_busy_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3000, 60, percentage_max_float,acmgt3__ext296__sampler_busy_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3001, 64, percentage_max_float,acmgt3__ext296__sampler_busy_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3002, 68, percentage_max_float,acmgt3__ext296__sampler_busy_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3003, 72, percentage_max_float,acmgt3__ext296__sampler_busy_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3004, 76, percentage_max_float,acmgt3__ext296__sampler_busy_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3005, 80, percentage_max_float,acmgt3__ext296__sampler_busy_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3006, 84, percentage_max_float,acmgt3__ext296__sampler_busy_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext297_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext297";
   query->symbol_name = "Ext297";
   query->guid = "1b1a9373-ac71-43d2-a428-b02826a6d5bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830D00 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30034 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30D00 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30034 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830D00 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30034 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30D00 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30034 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830D00 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x0AA30034 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x08C30D00 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x08E30034 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x07830D00 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x07A30034 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x05C30D00 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x05E30034 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext297__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext297__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext297__avg_gpu_core_frequency__max,acmgt3__ext297__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4219, 24, percentage_max_float,acmgt3__ext297__sampler_busy_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4220, 28, percentage_max_float,acmgt3__ext297__sampler_busy_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4221, 32, percentage_max_float,acmgt3__ext297__sampler_busy_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4222, 36, percentage_max_float,acmgt3__ext297__sampler_busy_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4223, 40, percentage_max_float,acmgt3__ext297__sampler_busy_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4224, 44, percentage_max_float,acmgt3__ext297__sampler_busy_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4225, 48, percentage_max_float,acmgt3__ext297__sampler_busy_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4226, 52, percentage_max_float,acmgt3__ext297__sampler_busy_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4227, 56, percentage_max_float,acmgt3__ext297__sampler_busy_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4228, 60, percentage_max_float,acmgt3__ext297__sampler_busy_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4229, 64, percentage_max_float,acmgt3__ext297__sampler_busy_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4230, 68, percentage_max_float,acmgt3__ext297__sampler_busy_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4231, 72, percentage_max_float,acmgt3__ext297__sampler_busy_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4232, 76, percentage_max_float,acmgt3__ext297__sampler_busy_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4233, 80, percentage_max_float,acmgt3__ext297__sampler_busy_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4234, 84, percentage_max_float,acmgt3__ext297__sampler_busy_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext298_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext298";
   query->symbol_name = "Ext298";
   query->guid = "87e14c77-8814-4632-941c-567a5aed2b97";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E847400 },
         { .reg = 0x00009888, .val = 0x1EA47400 },
         { .reg = 0x00009888, .val = 0x1EC47400 },
         { .reg = 0x00009888, .val = 0x1EE47400 },
         { .reg = 0x00009888, .val = 0x1F847400 },
         { .reg = 0x00009888, .val = 0x1FA47400 },
         { .reg = 0x00009888, .val = 0x1FC47400 },
         { .reg = 0x00009888, .val = 0x1FE47400 },
         { .reg = 0x00009888, .val = 0x04846810 },
         { .reg = 0x00009888, .val = 0x06840035 },
         { .reg = 0x00009888, .val = 0x02840000 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A40010 },
         { .reg = 0x00009888, .val = 0x06A40D00 },
         { .reg = 0x00009888, .val = 0x08A40035 },
         { .reg = 0x00009888, .val = 0x02A40000 },
         { .reg = 0x00009888, .val = 0x00A40000 },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C40010 },
         { .reg = 0x00009888, .val = 0x08C40D00 },
         { .reg = 0x00009888, .val = 0x0AC40035 },
         { .reg = 0x00009888, .val = 0x02C40000 },
         { .reg = 0x00009888, .val = 0x00C40000 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E40010 },
         { .reg = 0x00009888, .val = 0x0AE40D00 },
         { .reg = 0x00009888, .val = 0x0CE40035 },
         { .reg = 0x00009888, .val = 0x02E40000 },
         { .reg = 0x00009888, .val = 0x00E40000 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05840010 },
         { .reg = 0x00009888, .val = 0x0D840D00 },
         { .reg = 0x00009888, .val = 0x0F840035 },
         { .reg = 0x00009888, .val = 0x03840000 },
         { .reg = 0x00009888, .val = 0x01840000 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A40010 },
         { .reg = 0x00009888, .val = 0x0FA40D00 },
         { .reg = 0x00009888, .val = 0x11A40035 },
         { .reg = 0x00009888, .val = 0x03A40000 },
         { .reg = 0x00009888, .val = 0x01A40000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C40010 },
         { .reg = 0x00009888, .val = 0x11C40D00 },
         { .reg = 0x00009888, .val = 0x13C40035 },
         { .reg = 0x00009888, .val = 0x03C40000 },
         { .reg = 0x00009888, .val = 0x01C40000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E40010 },
         { .reg = 0x00009888, .val = 0x13E40D00 },
         { .reg = 0x00009888, .val = 0x15E40035 },
         { .reg = 0x00009888, .val = 0x03E40000 },
         { .reg = 0x00009888, .val = 0x01E40000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext298__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext298__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext298__avg_gpu_core_frequency__max,acmgt3__ext298__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1211, 24, percentage_max_float,acmgt3__ext298__sampler_memory_latency_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1212, 28, percentage_max_float,acmgt3__ext298__sampler_memory_latency_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1213, 32, percentage_max_float,acmgt3__ext298__sampler_memory_latency_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1214, 36, percentage_max_float,acmgt3__ext298__sampler_memory_latency_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1215, 40, percentage_max_float,acmgt3__ext298__sampler_memory_latency_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1216, 44, percentage_max_float,acmgt3__ext298__sampler_memory_latency_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1217, 48, percentage_max_float,acmgt3__ext298__sampler_memory_latency_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1218, 52, percentage_max_float,acmgt3__ext298__sampler_memory_latency_stall_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext299_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext299";
   query->symbol_name = "Ext299";
   query->guid = "13ce3184-9cd0-4c5b-bedd-a6fa38d76456";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E847400 },
         { .reg = 0x00009888, .val = 0x1EA47400 },
         { .reg = 0x00009888, .val = 0x1EC47400 },
         { .reg = 0x00009888, .val = 0x1EE47400 },
         { .reg = 0x00009888, .val = 0x1F847400 },
         { .reg = 0x00009888, .val = 0x1FA47400 },
         { .reg = 0x00009888, .val = 0x1FC47400 },
         { .reg = 0x00009888, .val = 0x1FE47400 },
         { .reg = 0x00009888, .val = 0x04846810 },
         { .reg = 0x00009888, .val = 0x06840035 },
         { .reg = 0x00009888, .val = 0x02840000 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A40010 },
         { .reg = 0x00009888, .val = 0x06A40D00 },
         { .reg = 0x00009888, .val = 0x08A40035 },
         { .reg = 0x00009888, .val = 0x02A40000 },
         { .reg = 0x00009888, .val = 0x00A40000 },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C40010 },
         { .reg = 0x00009888, .val = 0x08C40D00 },
         { .reg = 0x00009888, .val = 0x0AC40035 },
         { .reg = 0x00009888, .val = 0x02C40000 },
         { .reg = 0x00009888, .val = 0x00C40000 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E40010 },
         { .reg = 0x00009888, .val = 0x0AE40D00 },
         { .reg = 0x00009888, .val = 0x0CE40035 },
         { .reg = 0x00009888, .val = 0x02E40000 },
         { .reg = 0x00009888, .val = 0x00E40000 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05840010 },
         { .reg = 0x00009888, .val = 0x0D840D00 },
         { .reg = 0x00009888, .val = 0x0F840035 },
         { .reg = 0x00009888, .val = 0x03840000 },
         { .reg = 0x00009888, .val = 0x01840000 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A40010 },
         { .reg = 0x00009888, .val = 0x0FA40D00 },
         { .reg = 0x00009888, .val = 0x11A40035 },
         { .reg = 0x00009888, .val = 0x03A40000 },
         { .reg = 0x00009888, .val = 0x01A40000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C40010 },
         { .reg = 0x00009888, .val = 0x11C40D00 },
         { .reg = 0x00009888, .val = 0x13C40035 },
         { .reg = 0x00009888, .val = 0x03C40000 },
         { .reg = 0x00009888, .val = 0x01C40000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E40010 },
         { .reg = 0x00009888, .val = 0x13E40D00 },
         { .reg = 0x00009888, .val = 0x15E40035 },
         { .reg = 0x00009888, .val = 0x03E40000 },
         { .reg = 0x00009888, .val = 0x01E40000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext299__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext299__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext299__avg_gpu_core_frequency__max,acmgt3__ext299__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3007, 24, percentage_max_float,acmgt3__ext299__sampler_memory_latency_stall_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3008, 28, percentage_max_float,acmgt3__ext299__sampler_memory_latency_stall_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3009, 32, percentage_max_float,acmgt3__ext299__sampler_memory_latency_stall_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3010, 36, percentage_max_float,acmgt3__ext299__sampler_memory_latency_stall_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3011, 40, percentage_max_float,acmgt3__ext299__sampler_memory_latency_stall_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3012, 44, percentage_max_float,acmgt3__ext299__sampler_memory_latency_stall_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3013, 48, percentage_max_float,acmgt3__ext299__sampler_memory_latency_stall_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3014, 52, percentage_max_float,acmgt3__ext299__sampler_memory_latency_stall_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext300_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext300";
   query->symbol_name = "Ext300";
   query->guid = "015cec04-576e-496b-b4d8-53409c442065";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E847400 },
         { .reg = 0x00009888, .val = 0x1EA47400 },
         { .reg = 0x00009888, .val = 0x1EC47400 },
         { .reg = 0x00009888, .val = 0x1EE47400 },
         { .reg = 0x00009888, .val = 0x1F847400 },
         { .reg = 0x00009888, .val = 0x1FA47400 },
         { .reg = 0x00009888, .val = 0x1FC47400 },
         { .reg = 0x00009888, .val = 0x1FE47400 },
         { .reg = 0x00009888, .val = 0x04846810 },
         { .reg = 0x00009888, .val = 0x06840035 },
         { .reg = 0x00009888, .val = 0x02840000 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A40010 },
         { .reg = 0x00009888, .val = 0x06A40D00 },
         { .reg = 0x00009888, .val = 0x08A40035 },
         { .reg = 0x00009888, .val = 0x02A40000 },
         { .reg = 0x00009888, .val = 0x00A40000 },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C40010 },
         { .reg = 0x00009888, .val = 0x08C40D00 },
         { .reg = 0x00009888, .val = 0x0AC40035 },
         { .reg = 0x00009888, .val = 0x02C40000 },
         { .reg = 0x00009888, .val = 0x00C40000 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E40010 },
         { .reg = 0x00009888, .val = 0x0AE40D00 },
         { .reg = 0x00009888, .val = 0x0CE40035 },
         { .reg = 0x00009888, .val = 0x02E40000 },
         { .reg = 0x00009888, .val = 0x00E40000 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05840010 },
         { .reg = 0x00009888, .val = 0x0D840D00 },
         { .reg = 0x00009888, .val = 0x0F840035 },
         { .reg = 0x00009888, .val = 0x03840000 },
         { .reg = 0x00009888, .val = 0x01840000 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A40010 },
         { .reg = 0x00009888, .val = 0x0FA40D00 },
         { .reg = 0x00009888, .val = 0x11A40035 },
         { .reg = 0x00009888, .val = 0x03A40000 },
         { .reg = 0x00009888, .val = 0x01A40000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C40010 },
         { .reg = 0x00009888, .val = 0x11C40D00 },
         { .reg = 0x00009888, .val = 0x13C40035 },
         { .reg = 0x00009888, .val = 0x03C40000 },
         { .reg = 0x00009888, .val = 0x01C40000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E40010 },
         { .reg = 0x00009888, .val = 0x13E40D00 },
         { .reg = 0x00009888, .val = 0x15E40035 },
         { .reg = 0x00009888, .val = 0x03E40000 },
         { .reg = 0x00009888, .val = 0x01E40000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext300__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext300__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext300__avg_gpu_core_frequency__max,acmgt3__ext300__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4235, 24, percentage_max_float,acmgt3__ext300__sampler_memory_latency_stall_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4236, 28, percentage_max_float,acmgt3__ext300__sampler_memory_latency_stall_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4237, 32, percentage_max_float,acmgt3__ext300__sampler_memory_latency_stall_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4238, 36, percentage_max_float,acmgt3__ext300__sampler_memory_latency_stall_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4239, 40, percentage_max_float,acmgt3__ext300__sampler_memory_latency_stall_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4240, 44, percentage_max_float,acmgt3__ext300__sampler_memory_latency_stall_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4241, 48, percentage_max_float,acmgt3__ext300__sampler_memory_latency_stall_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4242, 52, percentage_max_float,acmgt3__ext300__sampler_memory_latency_stall_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext301_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext301";
   query->symbol_name = "Ext301";
   query->guid = "8b9a7b9c-a688-43ea-9c4b-fa6ba53852ab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E847400 },
         { .reg = 0x00009888, .val = 0x1EA47400 },
         { .reg = 0x00009888, .val = 0x1EC47400 },
         { .reg = 0x00009888, .val = 0x1EE47400 },
         { .reg = 0x00009888, .val = 0x1F847400 },
         { .reg = 0x00009888, .val = 0x1FA47400 },
         { .reg = 0x00009888, .val = 0x1FC47400 },
         { .reg = 0x00009888, .val = 0x1FE47400 },
         { .reg = 0x00009888, .val = 0x04846810 },
         { .reg = 0x00009888, .val = 0x06840035 },
         { .reg = 0x00009888, .val = 0x02840000 },
         { .reg = 0x00009888, .val = 0x00840000 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A40010 },
         { .reg = 0x00009888, .val = 0x06A40D00 },
         { .reg = 0x00009888, .val = 0x08A40035 },
         { .reg = 0x00009888, .val = 0x02A40000 },
         { .reg = 0x00009888, .val = 0x00A40000 },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C40010 },
         { .reg = 0x00009888, .val = 0x08C40D00 },
         { .reg = 0x00009888, .val = 0x0AC40035 },
         { .reg = 0x00009888, .val = 0x02C40000 },
         { .reg = 0x00009888, .val = 0x00C40000 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E40010 },
         { .reg = 0x00009888, .val = 0x0AE40D00 },
         { .reg = 0x00009888, .val = 0x0CE40035 },
         { .reg = 0x00009888, .val = 0x02E40000 },
         { .reg = 0x00009888, .val = 0x00E40000 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05840010 },
         { .reg = 0x00009888, .val = 0x0D840D00 },
         { .reg = 0x00009888, .val = 0x0F840035 },
         { .reg = 0x00009888, .val = 0x03840000 },
         { .reg = 0x00009888, .val = 0x01840000 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A40010 },
         { .reg = 0x00009888, .val = 0x0FA40D00 },
         { .reg = 0x00009888, .val = 0x11A40035 },
         { .reg = 0x00009888, .val = 0x03A40000 },
         { .reg = 0x00009888, .val = 0x01A40000 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C40010 },
         { .reg = 0x00009888, .val = 0x11C40D00 },
         { .reg = 0x00009888, .val = 0x13C40035 },
         { .reg = 0x00009888, .val = 0x03C40000 },
         { .reg = 0x00009888, .val = 0x01C40000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E40010 },
         { .reg = 0x00009888, .val = 0x13E40D00 },
         { .reg = 0x00009888, .val = 0x15E40035 },
         { .reg = 0x00009888, .val = 0x03E40000 },
         { .reg = 0x00009888, .val = 0x01E40000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext301__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext301__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext301__avg_gpu_core_frequency__max,acmgt3__ext301__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4243, 24, percentage_max_float,acmgt3__ext301__sampler_memory_latency_stall_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4244, 28, percentage_max_float,acmgt3__ext301__sampler_memory_latency_stall_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4245, 32, percentage_max_float,acmgt3__ext301__sampler_memory_latency_stall_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4246, 36, percentage_max_float,acmgt3__ext301__sampler_memory_latency_stall_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4247, 40, percentage_max_float,acmgt3__ext301__sampler_memory_latency_stall_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4248, 44, percentage_max_float,acmgt3__ext301__sampler_memory_latency_stall_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4249, 48, percentage_max_float,acmgt3__ext301__sampler_memory_latency_stall_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4250, 52, percentage_max_float,acmgt3__ext301__sampler_memory_latency_stall_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext302_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext302";
   query->symbol_name = "Ext302";
   query->guid = "7b0d1439-3ea4-48b4-97a7-934789bb750b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824800 },
         { .reg = 0x00009888, .val = 0x08820023 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00830005 },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20900 },
         { .reg = 0x00009888, .val = 0x0AA20023 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A30050 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x0AC20900 },
         { .reg = 0x00009888, .val = 0x0CC20023 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C30500 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0CE20900 },
         { .reg = 0x00009888, .val = 0x0EE20023 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x00E35000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0F820900 },
         { .reg = 0x00009888, .val = 0x11820023 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x03830005 },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x13A20023 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x03A30050 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x13C20900 },
         { .reg = 0x00009888, .val = 0x15C20023 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x03C30500 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x15E20900 },
         { .reg = 0x00009888, .val = 0x17E20023 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x03E35000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext302__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext302__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext302__avg_gpu_core_frequency__max,acmgt3__ext302__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1251, 24, percentage_max_float,acmgt3__ext302__sampler_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1252, 28, percentage_max_float,acmgt3__ext302__sampler_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1253, 32, percentage_max_float,acmgt3__ext302__sampler_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1254, 36, percentage_max_float,acmgt3__ext302__sampler_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1255, 40, percentage_max_float,acmgt3__ext302__sampler_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1256, 44, percentage_max_float,acmgt3__ext302__sampler_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1257, 48, percentage_max_float,acmgt3__ext302__sampler_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1258, 52, percentage_max_float,acmgt3__ext302__sampler_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext303_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext303";
   query->symbol_name = "Ext303";
   query->guid = "ae51b0bc-1de2-472c-915c-ac570a5d25ca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824800 },
         { .reg = 0x00009888, .val = 0x08820023 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00830005 },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20900 },
         { .reg = 0x00009888, .val = 0x0AA20023 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A30050 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x0AC20900 },
         { .reg = 0x00009888, .val = 0x0CC20023 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C30500 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0CE20900 },
         { .reg = 0x00009888, .val = 0x0EE20023 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x00E35000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0F820900 },
         { .reg = 0x00009888, .val = 0x11820023 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x03830005 },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x13A20023 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x03A30050 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x13C20900 },
         { .reg = 0x00009888, .val = 0x15C20023 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x03C30500 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x15E20900 },
         { .reg = 0x00009888, .val = 0x17E20023 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x03E35000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext303__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext303__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext303__avg_gpu_core_frequency__max,acmgt3__ext303__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3015, 24, percentage_max_float,acmgt3__ext303__sampler_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3016, 28, percentage_max_float,acmgt3__ext303__sampler_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3017, 32, percentage_max_float,acmgt3__ext303__sampler_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3018, 36, percentage_max_float,acmgt3__ext303__sampler_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3019, 40, percentage_max_float,acmgt3__ext303__sampler_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3020, 44, percentage_max_float,acmgt3__ext303__sampler_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3021, 48, percentage_max_float,acmgt3__ext303__sampler_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3022, 52, percentage_max_float,acmgt3__ext303__sampler_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext304_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext304";
   query->symbol_name = "Ext304";
   query->guid = "3e837b13-a03e-4f77-8bc0-bfdaed855b49";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824800 },
         { .reg = 0x00009888, .val = 0x08820023 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00830005 },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20900 },
         { .reg = 0x00009888, .val = 0x0AA20023 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A30050 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x0AC20900 },
         { .reg = 0x00009888, .val = 0x0CC20023 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C30500 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0CE20900 },
         { .reg = 0x00009888, .val = 0x0EE20023 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x00E35000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0F820900 },
         { .reg = 0x00009888, .val = 0x11820023 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x03830005 },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x13A20023 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x03A30050 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x13C20900 },
         { .reg = 0x00009888, .val = 0x15C20023 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x03C30500 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x15E20900 },
         { .reg = 0x00009888, .val = 0x17E20023 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x03E35000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext304__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext304__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext304__avg_gpu_core_frequency__max,acmgt3__ext304__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4251, 24, percentage_max_float,acmgt3__ext304__sampler_input_available_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4252, 28, percentage_max_float,acmgt3__ext304__sampler_input_available_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4253, 32, percentage_max_float,acmgt3__ext304__sampler_input_available_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4254, 36, percentage_max_float,acmgt3__ext304__sampler_input_available_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4255, 40, percentage_max_float,acmgt3__ext304__sampler_input_available_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4256, 44, percentage_max_float,acmgt3__ext304__sampler_input_available_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4257, 48, percentage_max_float,acmgt3__ext304__sampler_input_available_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4258, 52, percentage_max_float,acmgt3__ext304__sampler_input_available_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext305_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext305";
   query->symbol_name = "Ext305";
   query->guid = "793a787c-6646-4e56-8bfa-acca313d86f5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1C824C00 },
         { .reg = 0x00009888, .val = 0x1CA24C00 },
         { .reg = 0x00009888, .val = 0x1CC24C00 },
         { .reg = 0x00009888, .val = 0x1CE24C00 },
         { .reg = 0x00009888, .val = 0x1D824C00 },
         { .reg = 0x00009888, .val = 0x1DA24C00 },
         { .reg = 0x00009888, .val = 0x1DC24C00 },
         { .reg = 0x00009888, .val = 0x1DE24C00 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824800 },
         { .reg = 0x00009888, .val = 0x08820023 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00830005 },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20900 },
         { .reg = 0x00009888, .val = 0x0AA20023 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A30050 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x0AC20900 },
         { .reg = 0x00009888, .val = 0x0CC20023 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C30500 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0CE20900 },
         { .reg = 0x00009888, .val = 0x0EE20023 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x00E35000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x05824000 },
         { .reg = 0x00009888, .val = 0x0F820900 },
         { .reg = 0x00009888, .val = 0x11820023 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x03830005 },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x05A24000 },
         { .reg = 0x00009888, .val = 0x11A20900 },
         { .reg = 0x00009888, .val = 0x13A20023 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x03A30050 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x05C24000 },
         { .reg = 0x00009888, .val = 0x13C20900 },
         { .reg = 0x00009888, .val = 0x15C20023 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x03C30500 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x05E24000 },
         { .reg = 0x00009888, .val = 0x15E20900 },
         { .reg = 0x00009888, .val = 0x17E20023 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x03E35000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext305__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext305__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext305__avg_gpu_core_frequency__max,acmgt3__ext305__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4259, 24, percentage_max_float,acmgt3__ext305__sampler_input_available_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4260, 28, percentage_max_float,acmgt3__ext305__sampler_input_available_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4261, 32, percentage_max_float,acmgt3__ext305__sampler_input_available_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4262, 36, percentage_max_float,acmgt3__ext305__sampler_input_available_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4263, 40, percentage_max_float,acmgt3__ext305__sampler_input_available_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4264, 44, percentage_max_float,acmgt3__ext305__sampler_input_available_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4265, 48, percentage_max_float,acmgt3__ext305__sampler_input_available_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4266, 52, percentage_max_float,acmgt3__ext305__sampler_input_available_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext306_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext306";
   query->symbol_name = "Ext306";
   query->guid = "e7767971-3cb4-4a31-8467-0d83cbe7b292";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830CC0 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30033 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30CC0 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30033 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830CC0 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30033 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30CC0 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30033 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830CC0 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x0AA30033 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x08C30CC0 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x08E30033 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x07830CC0 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x07A30033 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x05C30CC0 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x05E30033 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext306__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext306__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext306__avg_gpu_core_frequency__max,acmgt3__ext306__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1235, 24, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1236, 32, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1237, 40, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1238, 48, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1239, 56, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1240, 64, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1241, 72, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1242, 80, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3023, 88, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3024, 96, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3025, 104, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3026, 112, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3027, 120, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3028, 128, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3029, 136, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3030, 144, NULL,acmgt3__ext306__sampler_texture_cache_access_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext307_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext307";
   query->symbol_name = "Ext307";
   query->guid = "9375cccf-e4b4-44cc-b6af-ffc2f51c3bb1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830CC0 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30033 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30CC0 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30033 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830CC0 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30033 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30CC0 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30033 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830CC0 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x0AA30033 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x08C30CC0 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x08E30033 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x07830CC0 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x07A30033 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x05C30CC0 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x05E30033 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext307__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext307__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext307__avg_gpu_core_frequency__max,acmgt3__ext307__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4267, 24, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4268, 32, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4269, 40, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4270, 48, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4271, 56, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4272, 64, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4273, 72, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4274, 80, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4275, 88, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4276, 96, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4277, 104, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4278, 112, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4279, 120, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4280, 128, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4281, 136, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4282, 144, NULL,acmgt3__ext307__sampler_texture_cache_access_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext308_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext308";
   query->symbol_name = "Ext308";
   query->guid = "0218e76e-7c34-4c67-a967-205a817f2435";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830C80 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30032 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30C80 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30032 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830C80 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30032 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30C80 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30032 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830C80 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x0AA30032 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x08C30C80 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x08E30032 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x07830C80 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x07A30032 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x05C30C80 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x05E30032 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext308__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext308__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext308__avg_gpu_core_frequency__max,acmgt3__ext308__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1243, 24, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1244, 32, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1245, 40, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1246, 48, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1247, 56, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1248, 64, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1249, 72, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1250, 80, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3031, 88, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3032, 96, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3033, 104, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3034, 112, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3035, 120, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3036, 128, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3037, 136, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3038, 144, NULL,acmgt3__ext308__sampler_texture_cache_miss_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext309_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext309";
   query->symbol_name = "Ext309";
   query->guid = "7a2ef8ea-0510-4066-b7de-0af99bf5b0b7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x12830C80 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x12A30032 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x10C30C80 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x10E30032 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x0F830C80 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x03830000 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x0FA30032 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x03A30000 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x0DC30C80 },
         { .reg = 0x00009888, .val = 0x05C30000 },
         { .reg = 0x00009888, .val = 0x03C30000 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x0DE30032 },
         { .reg = 0x00009888, .val = 0x05E30000 },
         { .reg = 0x00009888, .val = 0x03E30000 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x19830004 },
         { .reg = 0x00009888, .val = 0x19A30004 },
         { .reg = 0x00009888, .val = 0x19C30004 },
         { .reg = 0x00009888, .val = 0x19E30004 },
         { .reg = 0x00009888, .val = 0x0A830C80 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x0AA30032 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x08C30C80 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x08E30032 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x07830C80 },
         { .reg = 0x00009888, .val = 0x05830000 },
         { .reg = 0x00009888, .val = 0x01830000 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x07A30032 },
         { .reg = 0x00009888, .val = 0x05A30000 },
         { .reg = 0x00009888, .val = 0x01A30000 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x05C30C80 },
         { .reg = 0x00009888, .val = 0x01C30000 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x05E30032 },
         { .reg = 0x00009888, .val = 0x01E30000 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext309__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext309__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext309__avg_gpu_core_frequency__max,acmgt3__ext309__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4283, 24, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4284, 32, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4285, 40, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4286, 48, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4287, 56, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4288, 64, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4289, 72, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4290, 80, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4291, 88, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4292, 96, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4293, 104, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4294, 112, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4295, 120, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4296, 128, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4297, 136, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4298, 144, NULL,acmgt3__ext309__sampler_texture_cache_miss_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext310_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext310";
   query->symbol_name = "Ext310";
   query->guid = "7f6f2cd5-235a-4479-9724-98bc76338071";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x088101C5 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC101C5 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext310__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext310__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext310__avg_gpu_core_frequency__max,acmgt3__ext310__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1163, 24, NULL,acmgt3__ext310__xve_dataport_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1164, 32, NULL,acmgt3__ext310__xve_dataport_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1165, 40, NULL,acmgt3__ext310__xve_dataport_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1166, 48, NULL,acmgt3__ext310__xve_dataport_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext311_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext311";
   query->symbol_name = "Ext311";
   query->guid = "cd5aacba-f72a-44f7-8794-ce2bcf92ec1f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x098101C5 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC101C5 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext311__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext311__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext311__avg_gpu_core_frequency__max,acmgt3__ext311__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1167, 24, NULL,acmgt3__ext311__xve_dataport_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1168, 32, NULL,acmgt3__ext311__xve_dataport_read_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1169, 40, NULL,acmgt3__ext311__xve_dataport_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1170, 48, NULL,acmgt3__ext311__xve_dataport_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext312_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext312";
   query->symbol_name = "Ext312";
   query->guid = "a2f9ee62-175a-4c99-ad05-daa5dd83c268";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x088101C5 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC101C5 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext312__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext312__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext312__avg_gpu_core_frequency__max,acmgt3__ext312__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2307, 24, NULL,acmgt3__ext312__xve_dataport_read_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2308, 32, NULL,acmgt3__ext312__xve_dataport_read_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2315, 40, NULL,acmgt3__ext312__xve_dataport_read_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2316, 48, NULL,acmgt3__ext312__xve_dataport_read_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext313_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext313";
   query->symbol_name = "Ext313";
   query->guid = "8cc89495-676d-46a3-aa5a-d5e50bd8b547";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x098101C5 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC101C5 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext313__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext313__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext313__avg_gpu_core_frequency__max,acmgt3__ext313__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2323, 24, NULL,acmgt3__ext313__xve_dataport_read_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2324, 32, NULL,acmgt3__ext313__xve_dataport_read_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2331, 40, NULL,acmgt3__ext313__xve_dataport_read_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2332, 48, NULL,acmgt3__ext313__xve_dataport_read_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext314_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext314";
   query->symbol_name = "Ext314";
   query->guid = "6a9b6d4b-0ad5-410b-ab23-a755c2069502";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x088101C5 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC101C5 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext314__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext314__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext314__avg_gpu_core_frequency__max,acmgt3__ext314__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4299, 24, NULL,acmgt3__ext314__xve_dataport_read_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4300, 32, NULL,acmgt3__ext314__xve_dataport_read_message_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4301, 40, NULL,acmgt3__ext314__xve_dataport_read_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4302, 48, NULL,acmgt3__ext314__xve_dataport_read_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext315_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext315";
   query->symbol_name = "Ext315";
   query->guid = "ff1b4077-1346-45a5-acae-d08e7651e126";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x098101C5 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC101C5 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext315__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext315__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext315__avg_gpu_core_frequency__max,acmgt3__ext315__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4303, 24, NULL,acmgt3__ext315__xve_dataport_read_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4304, 32, NULL,acmgt3__ext315__xve_dataport_read_message_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4305, 40, NULL,acmgt3__ext315__xve_dataport_read_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4306, 48, NULL,acmgt3__ext315__xve_dataport_read_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext316_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext316";
   query->symbol_name = "Ext316";
   query->guid = "d4367f9e-ceaa-4751-91de-c80918a32d0e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x088101C5 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC101C5 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext316__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext316__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext316__avg_gpu_core_frequency__max,acmgt3__ext316__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4307, 24, NULL,acmgt3__ext316__xve_dataport_read_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4308, 32, NULL,acmgt3__ext316__xve_dataport_read_message_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4309, 40, NULL,acmgt3__ext316__xve_dataport_read_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4310, 48, NULL,acmgt3__ext316__xve_dataport_read_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext317_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext317";
   query->symbol_name = "Ext317";
   query->guid = "ea24cfe9-dca1-4520-b55a-78ac4b9c94b5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x098101C5 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC101C5 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext317__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext317__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext317__avg_gpu_core_frequency__max,acmgt3__ext317__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4311, 24, NULL,acmgt3__ext317__xve_dataport_read_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4312, 32, NULL,acmgt3__ext317__xve_dataport_read_message_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4313, 40, NULL,acmgt3__ext317__xve_dataport_read_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4314, 48, NULL,acmgt3__ext317__xve_dataport_read_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext318_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext318";
   query->symbol_name = "Ext318";
   query->guid = "570970cb-b1ae-499e-9113-73b1489bebe7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810206 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10180 },
         { .reg = 0x00009888, .val = 0x0CA102C8 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10206 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10180 },
         { .reg = 0x00009888, .val = 0x12E102C8 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext318__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext318__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext318__avg_gpu_core_frequency__max,acmgt3__ext318__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1171, 24, NULL,acmgt3__ext318__xve_dataport_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1172, 32, NULL,acmgt3__ext318__xve_dataport_write_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1173, 40, NULL,acmgt3__ext318__xve_dataport_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1174, 48, NULL,acmgt3__ext318__xve_dataport_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext319_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext319";
   query->symbol_name = "Ext319";
   query->guid = "a2b926df-458d-4580-99d9-731b9e9024b1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810206 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10180 },
         { .reg = 0x00009888, .val = 0x0DA102C8 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10206 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10180 },
         { .reg = 0x00009888, .val = 0x13E102C8 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext319__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext319__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext319__avg_gpu_core_frequency__max,acmgt3__ext319__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1175, 24, NULL,acmgt3__ext319__xve_dataport_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1176, 32, NULL,acmgt3__ext319__xve_dataport_write_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1177, 40, NULL,acmgt3__ext319__xve_dataport_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1178, 48, NULL,acmgt3__ext319__xve_dataport_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext320_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext320";
   query->symbol_name = "Ext320";
   query->guid = "b357c635-b799-46d2-8714-4f4fddffe2e9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810206 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10180 },
         { .reg = 0x00009888, .val = 0x0CA102C8 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10206 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10180 },
         { .reg = 0x00009888, .val = 0x12E102C8 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext320__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext320__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext320__avg_gpu_core_frequency__max,acmgt3__ext320__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2309, 24, NULL,acmgt3__ext320__xve_dataport_write_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2310, 32, NULL,acmgt3__ext320__xve_dataport_write_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2317, 40, NULL,acmgt3__ext320__xve_dataport_write_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2318, 48, NULL,acmgt3__ext320__xve_dataport_write_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext321_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext321";
   query->symbol_name = "Ext321";
   query->guid = "a8c3e950-b343-4f27-a434-a49ba7c87254";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810206 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10180 },
         { .reg = 0x00009888, .val = 0x0DA102C8 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10206 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10180 },
         { .reg = 0x00009888, .val = 0x13E102C8 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext321__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext321__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext321__avg_gpu_core_frequency__max,acmgt3__ext321__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2325, 24, NULL,acmgt3__ext321__xve_dataport_write_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2326, 32, NULL,acmgt3__ext321__xve_dataport_write_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2333, 40, NULL,acmgt3__ext321__xve_dataport_write_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2334, 48, NULL,acmgt3__ext321__xve_dataport_write_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext322_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext322";
   query->symbol_name = "Ext322";
   query->guid = "be052c4e-a835-42da-9b67-3917052ada60";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810206 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10180 },
         { .reg = 0x00009888, .val = 0x0CA102C8 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10206 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10180 },
         { .reg = 0x00009888, .val = 0x12E102C8 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext322__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext322__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext322__avg_gpu_core_frequency__max,acmgt3__ext322__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4315, 24, NULL,acmgt3__ext322__xve_dataport_write_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4316, 32, NULL,acmgt3__ext322__xve_dataport_write_message_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4317, 40, NULL,acmgt3__ext322__xve_dataport_write_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4318, 48, NULL,acmgt3__ext322__xve_dataport_write_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext323_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext323";
   query->symbol_name = "Ext323";
   query->guid = "d911722e-b0cd-4b54-92e5-d98dda5b6c90";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810206 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10180 },
         { .reg = 0x00009888, .val = 0x0DA102C8 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10206 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10180 },
         { .reg = 0x00009888, .val = 0x13E102C8 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext323__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext323__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext323__avg_gpu_core_frequency__max,acmgt3__ext323__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4319, 24, NULL,acmgt3__ext323__xve_dataport_write_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4320, 32, NULL,acmgt3__ext323__xve_dataport_write_message_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4321, 40, NULL,acmgt3__ext323__xve_dataport_write_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4322, 48, NULL,acmgt3__ext323__xve_dataport_write_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext324_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext324";
   query->symbol_name = "Ext324";
   query->guid = "0bc72c8f-65c2-4ab7-acd8-c65a40a707ac";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810206 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10180 },
         { .reg = 0x00009888, .val = 0x0CA102C8 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10206 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10180 },
         { .reg = 0x00009888, .val = 0x12E102C8 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext324__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext324__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext324__avg_gpu_core_frequency__max,acmgt3__ext324__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4323, 24, NULL,acmgt3__ext324__xve_dataport_write_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4324, 32, NULL,acmgt3__ext324__xve_dataport_write_message_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4325, 40, NULL,acmgt3__ext324__xve_dataport_write_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4326, 48, NULL,acmgt3__ext324__xve_dataport_write_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext325_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext325";
   query->symbol_name = "Ext325";
   query->guid = "86524707-6f59-4929-ac15-a293133850b0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810206 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10180 },
         { .reg = 0x00009888, .val = 0x0DA102C8 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10206 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10180 },
         { .reg = 0x00009888, .val = 0x13E102C8 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext325__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext325__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext325__avg_gpu_core_frequency__max,acmgt3__ext325__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4327, 24, NULL,acmgt3__ext325__xve_dataport_write_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4328, 32, NULL,acmgt3__ext325__xve_dataport_write_message_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4329, 40, NULL,acmgt3__ext325__xve_dataport_write_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4330, 48, NULL,acmgt3__ext325__xve_dataport_write_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext326_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext326";
   query->symbol_name = "Ext326";
   query->guid = "199027ff-3c22-42d5-a543-a9467be1422c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C6 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10185 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C6 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext326__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext326__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext326__avg_gpu_core_frequency__max,acmgt3__ext326__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1179, 24, NULL,acmgt3__ext326__xve_dataport_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1180, 32, NULL,acmgt3__ext326__xve_dataport_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1181, 40, NULL,acmgt3__ext326__xve_dataport_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1182, 48, NULL,acmgt3__ext326__xve_dataport_atomic_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext327_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext327";
   query->symbol_name = "Ext327";
   query->guid = "38473fe1-ab75-4be0-9cef-c9d84a803787";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C6 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10185 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C6 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext327__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext327__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext327__avg_gpu_core_frequency__max,acmgt3__ext327__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1183, 24, NULL,acmgt3__ext327__xve_dataport_atomic_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1184, 32, NULL,acmgt3__ext327__xve_dataport_atomic_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1185, 40, NULL,acmgt3__ext327__xve_dataport_atomic_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1186, 48, NULL,acmgt3__ext327__xve_dataport_atomic_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext328_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext328";
   query->symbol_name = "Ext328";
   query->guid = "4500f1fd-d762-4a31-88fd-17ae40ee0727";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C6 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10185 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C6 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext328__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext328__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext328__avg_gpu_core_frequency__max,acmgt3__ext328__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2311, 24, NULL,acmgt3__ext328__xve_dataport_atomic_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2312, 32, NULL,acmgt3__ext328__xve_dataport_atomic_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2319, 40, NULL,acmgt3__ext328__xve_dataport_atomic_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2320, 48, NULL,acmgt3__ext328__xve_dataport_atomic_message_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext329_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext329";
   query->symbol_name = "Ext329";
   query->guid = "2458839a-476e-4804-ba6b-a3d06323b800";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C6 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10185 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C6 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext329__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext329__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext329__avg_gpu_core_frequency__max,acmgt3__ext329__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2327, 24, NULL,acmgt3__ext329__xve_dataport_atomic_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2328, 32, NULL,acmgt3__ext329__xve_dataport_atomic_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2335, 40, NULL,acmgt3__ext329__xve_dataport_atomic_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2336, 48, NULL,acmgt3__ext329__xve_dataport_atomic_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext330_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext330";
   query->symbol_name = "Ext330";
   query->guid = "9aa833d4-ba51-487b-a586-a0df6d462909";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C6 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10185 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C6 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext330__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext330__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext330__avg_gpu_core_frequency__max,acmgt3__ext330__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4331, 24, NULL,acmgt3__ext330__xve_dataport_atomic_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4332, 32, NULL,acmgt3__ext330__xve_dataport_atomic_message_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4333, 40, NULL,acmgt3__ext330__xve_dataport_atomic_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4334, 48, NULL,acmgt3__ext330__xve_dataport_atomic_message_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext331_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext331";
   query->symbol_name = "Ext331";
   query->guid = "1ca59138-4493-4e1e-bf2d-452da6a50597";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C6 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10185 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C6 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext331__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext331__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext331__avg_gpu_core_frequency__max,acmgt3__ext331__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4335, 24, NULL,acmgt3__ext331__xve_dataport_atomic_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4336, 32, NULL,acmgt3__ext331__xve_dataport_atomic_message_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4337, 40, NULL,acmgt3__ext331__xve_dataport_atomic_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4338, 48, NULL,acmgt3__ext331__xve_dataport_atomic_message_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext332_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext332";
   query->symbol_name = "Ext332";
   query->guid = "88514dd5-9e66-457e-9493-8ffc78893322";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18812800 },
         { .reg = 0x00009888, .val = 0x1A81000B },
         { .reg = 0x00009888, .val = 0x18A12800 },
         { .reg = 0x00009888, .val = 0x1AA1000B },
         { .reg = 0x00009888, .val = 0x18C12800 },
         { .reg = 0x00009888, .val = 0x1AC1000B },
         { .reg = 0x00009888, .val = 0x18E12800 },
         { .reg = 0x00009888, .val = 0x1AE1000B },
         { .reg = 0x00009888, .val = 0x04810076 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A81000B },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x04A10076 },
         { .reg = 0x00009888, .val = 0x0AA10140 },
         { .reg = 0x00009888, .val = 0x0CA102C6 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04C10076 },
         { .reg = 0x00009888, .val = 0x0EC10185 },
         { .reg = 0x00009888, .val = 0x10C1000B },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x04E10076 },
         { .reg = 0x00009888, .val = 0x10E10140 },
         { .reg = 0x00009888, .val = 0x12E102C6 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext332__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext332__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext332__avg_gpu_core_frequency__max,acmgt3__ext332__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4339, 24, NULL,acmgt3__ext332__xve_dataport_atomic_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4340, 32, NULL,acmgt3__ext332__xve_dataport_atomic_message_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4341, 40, NULL,acmgt3__ext332__xve_dataport_atomic_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4342, 48, NULL,acmgt3__ext332__xve_dataport_atomic_message_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext333_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext333";
   query->symbol_name = "Ext333";
   query->guid = "38fcb336-fc63-4e5e-aa3e-a40f7feb693a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x19812800 },
         { .reg = 0x00009888, .val = 0x1B81000B },
         { .reg = 0x00009888, .val = 0x19A12800 },
         { .reg = 0x00009888, .val = 0x1BA1000B },
         { .reg = 0x00009888, .val = 0x19C12800 },
         { .reg = 0x00009888, .val = 0x1BC1000B },
         { .reg = 0x00009888, .val = 0x19E12800 },
         { .reg = 0x00009888, .val = 0x1BE1000B },
         { .reg = 0x00009888, .val = 0x05810076 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B81000B },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x05A10076 },
         { .reg = 0x00009888, .val = 0x0BA10140 },
         { .reg = 0x00009888, .val = 0x0DA102C6 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05C10076 },
         { .reg = 0x00009888, .val = 0x0FC10185 },
         { .reg = 0x00009888, .val = 0x11C1000B },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x05E10076 },
         { .reg = 0x00009888, .val = 0x11E10140 },
         { .reg = 0x00009888, .val = 0x13E102C6 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext333__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext333__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext333__avg_gpu_core_frequency__max,acmgt3__ext333__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4343, 24, NULL,acmgt3__ext333__xve_dataport_atomic_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4344, 32, NULL,acmgt3__ext333__xve_dataport_atomic_message_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4345, 40, NULL,acmgt3__ext333__xve_dataport_atomic_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4346, 48, NULL,acmgt3__ext333__xve_dataport_atomic_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext334_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext334";
   query->symbol_name = "Ext334";
   query->guid = "b8a9ea64-362d-473b-b9d7-a2175179a0a0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20810011 },
         { .reg = 0x00009888, .val = 0x20A10011 },
         { .reg = 0x00009888, .val = 0x20C10011 },
         { .reg = 0x00009888, .val = 0x20E10011 },
         { .reg = 0x00009888, .val = 0x21810011 },
         { .reg = 0x00009888, .val = 0x21A10011 },
         { .reg = 0x00009888, .val = 0x21C10011 },
         { .reg = 0x00009888, .val = 0x21E10011 },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x16810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x16A10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x14C10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x14E10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x13810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x13A10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x11C10580 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x11E10016 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x20810011 },
         { .reg = 0x00009888, .val = 0x20A10011 },
         { .reg = 0x00009888, .val = 0x20C10011 },
         { .reg = 0x00009888, .val = 0x20E10011 },
         { .reg = 0x00009888, .val = 0x21810011 },
         { .reg = 0x00009888, .val = 0x21A10011 },
         { .reg = 0x00009888, .val = 0x21C10011 },
         { .reg = 0x00009888, .val = 0x21E10011 },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x0E810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x0EA10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x0CC10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x0CE10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x0B810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x0BA10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x09C10580 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x09E10016 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext334__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext334__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext334__avg_gpu_core_frequency__max,acmgt3__ext334__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1784, 24, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1785, 32, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1786, 40, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1787, 48, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1788, 56, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1789, 64, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1790, 72, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1791, 80, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2313, 88, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2314, 96, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2321, 104, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2322, 112, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2329, 120, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2330, 128, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2337, 136, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2338, 144, NULL,acmgt3__ext334__xve_dataport_fence_message_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext335_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext335";
   query->symbol_name = "Ext335";
   query->guid = "6771c5d0-cc06-41ec-b5c9-7d4a8d657bd2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x20810011 },
         { .reg = 0x00009888, .val = 0x20A10011 },
         { .reg = 0x00009888, .val = 0x20C10011 },
         { .reg = 0x00009888, .val = 0x20E10011 },
         { .reg = 0x00009888, .val = 0x21810011 },
         { .reg = 0x00009888, .val = 0x21A10011 },
         { .reg = 0x00009888, .val = 0x21C10011 },
         { .reg = 0x00009888, .val = 0x21E10011 },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x16810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x16A10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x14C10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x14E10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x13810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x13A10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x11C10580 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x11E10016 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x20810011 },
         { .reg = 0x00009888, .val = 0x20A10011 },
         { .reg = 0x00009888, .val = 0x20C10011 },
         { .reg = 0x00009888, .val = 0x20E10011 },
         { .reg = 0x00009888, .val = 0x21810011 },
         { .reg = 0x00009888, .val = 0x21A10011 },
         { .reg = 0x00009888, .val = 0x21C10011 },
         { .reg = 0x00009888, .val = 0x21E10011 },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x0E810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x0EA10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x0CC10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x0CE10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x0B810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x0BA10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x09C10580 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x09E10016 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext335__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext335__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext335__avg_gpu_core_frequency__max,acmgt3__ext335__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4347, 24, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4348, 32, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4349, 40, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4350, 48, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4351, 56, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4352, 64, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4353, 72, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4354, 80, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4355, 88, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4356, 96, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4357, 104, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4358, 112, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4359, 120, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4360, 128, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4361, 136, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4362, 144, NULL,acmgt3__ext335__xve_dataport_fence_message_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext342_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext342";
   query->symbol_name = "Ext342";
   query->guid = "c99de5cb-2a05-4d95-ae63-7465a9fde881";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x188102FD },
         { .reg = 0x00009888, .val = 0x18A102FD },
         { .reg = 0x00009888, .val = 0x18C102FD },
         { .reg = 0x00009888, .val = 0x18E102FD },
         { .reg = 0x00009888, .val = 0x198102FD },
         { .reg = 0x00009888, .val = 0x19A102FD },
         { .reg = 0x00009888, .val = 0x19C102FD },
         { .reg = 0x00009888, .val = 0x19E102FD },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x168103C2 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x02875000 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x14A103C2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70500 },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x12C103C2 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C70050 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E103C2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x0F8103C2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x01875000 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x0DA103C2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70500 },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x0BC103C2 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C70050 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x09E103C2 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E70005 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext342__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext342__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext342__avg_gpu_core_frequency__max,acmgt3__ext342__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1195, 24, NULL,acmgt3__ext342__xve_dataport_register_request_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1196, 32, NULL,acmgt3__ext342__xve_dataport_register_request_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1197, 40, NULL,acmgt3__ext342__xve_dataport_register_request_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1198, 48, NULL,acmgt3__ext342__xve_dataport_register_request_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1199, 56, NULL,acmgt3__ext342__xve_dataport_register_request_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1200, 64, NULL,acmgt3__ext342__xve_dataport_register_request_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1201, 72, NULL,acmgt3__ext342__xve_dataport_register_request_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1202, 80, NULL,acmgt3__ext342__xve_dataport_register_request_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext343_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext343";
   query->symbol_name = "Ext343";
   query->guid = "c83a1e77-4edb-4157-86d2-8ae073b76783";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x188102FD },
         { .reg = 0x00009888, .val = 0x18A102FD },
         { .reg = 0x00009888, .val = 0x18C102FD },
         { .reg = 0x00009888, .val = 0x18E102FD },
         { .reg = 0x00009888, .val = 0x198102FD },
         { .reg = 0x00009888, .val = 0x19A102FD },
         { .reg = 0x00009888, .val = 0x19C102FD },
         { .reg = 0x00009888, .val = 0x19E102FD },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x168103C2 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x02875000 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x14A103C2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70500 },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x12C103C2 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C70050 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E103C2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x0F8103C2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x01875000 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x0DA103C2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70500 },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x0BC103C2 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C70050 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x09E103C2 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E70005 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext343__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext343__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext343__avg_gpu_core_frequency__max,acmgt3__ext343__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2371, 24, NULL,acmgt3__ext343__xve_dataport_register_request_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2372, 32, NULL,acmgt3__ext343__xve_dataport_register_request_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2373, 40, NULL,acmgt3__ext343__xve_dataport_register_request_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2374, 48, NULL,acmgt3__ext343__xve_dataport_register_request_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2375, 56, NULL,acmgt3__ext343__xve_dataport_register_request_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2376, 64, NULL,acmgt3__ext343__xve_dataport_register_request_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2377, 72, NULL,acmgt3__ext343__xve_dataport_register_request_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2378, 80, NULL,acmgt3__ext343__xve_dataport_register_request_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext344_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext344";
   query->symbol_name = "Ext344";
   query->guid = "7bdaf544-993e-4a5e-8040-9391d9be562d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x188102FD },
         { .reg = 0x00009888, .val = 0x18A102FD },
         { .reg = 0x00009888, .val = 0x18C102FD },
         { .reg = 0x00009888, .val = 0x18E102FD },
         { .reg = 0x00009888, .val = 0x198102FD },
         { .reg = 0x00009888, .val = 0x19A102FD },
         { .reg = 0x00009888, .val = 0x19C102FD },
         { .reg = 0x00009888, .val = 0x19E102FD },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x168103C2 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x02875000 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x14A103C2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70500 },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x12C103C2 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C70050 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E103C2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x0F8103C2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x01875000 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x0DA103C2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70500 },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x0BC103C2 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C70050 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x09E103C2 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E70005 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext344__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext344__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext344__avg_gpu_core_frequency__max,acmgt3__ext344__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4363, 24, NULL,acmgt3__ext344__xve_dataport_register_request_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4364, 32, NULL,acmgt3__ext344__xve_dataport_register_request_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4365, 40, NULL,acmgt3__ext344__xve_dataport_register_request_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4366, 48, NULL,acmgt3__ext344__xve_dataport_register_request_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4367, 56, NULL,acmgt3__ext344__xve_dataport_register_request_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4368, 64, NULL,acmgt3__ext344__xve_dataport_register_request_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4369, 72, NULL,acmgt3__ext344__xve_dataport_register_request_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4370, 80, NULL,acmgt3__ext344__xve_dataport_register_request_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext345_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext345";
   query->symbol_name = "Ext345";
   query->guid = "7e311c03-26ed-437c-9f60-28d92df03534";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x188102FD },
         { .reg = 0x00009888, .val = 0x18A102FD },
         { .reg = 0x00009888, .val = 0x18C102FD },
         { .reg = 0x00009888, .val = 0x18E102FD },
         { .reg = 0x00009888, .val = 0x198102FD },
         { .reg = 0x00009888, .val = 0x19A102FD },
         { .reg = 0x00009888, .val = 0x19C102FD },
         { .reg = 0x00009888, .val = 0x19E102FD },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x168103C2 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283A000 },
         { .reg = 0x00009888, .val = 0x0084C000 },
         { .reg = 0x00009888, .val = 0x02865000 },
         { .reg = 0x00009888, .val = 0x02875000 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x14A103C2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A30A00 },
         { .reg = 0x00009888, .val = 0x00A43000 },
         { .reg = 0x00009888, .val = 0x02A60500 },
         { .reg = 0x00009888, .val = 0x02A70500 },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x12C103C2 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300A0 },
         { .reg = 0x00009888, .val = 0x00C40C00 },
         { .reg = 0x00009888, .val = 0x02C60050 },
         { .reg = 0x00009888, .val = 0x02C70050 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E103C2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E40300 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x0F8103C2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183A000 },
         { .reg = 0x00009888, .val = 0x018400C0 },
         { .reg = 0x00009888, .val = 0x01865000 },
         { .reg = 0x00009888, .val = 0x01875000 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x0DA103C2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30A00 },
         { .reg = 0x00009888, .val = 0x01A40030 },
         { .reg = 0x00009888, .val = 0x01A60500 },
         { .reg = 0x00009888, .val = 0x01A70500 },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x0BC103C2 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300A0 },
         { .reg = 0x00009888, .val = 0x01C4000C },
         { .reg = 0x00009888, .val = 0x01C60050 },
         { .reg = 0x00009888, .val = 0x01C70050 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x09E103C2 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E3000A },
         { .reg = 0x00009888, .val = 0x01E40003 },
         { .reg = 0x00009888, .val = 0x01E60005 },
         { .reg = 0x00009888, .val = 0x01E70005 },
         { .reg = 0x00009888, .val = 0x000300FF },
         { .reg = 0x00009888, .val = 0x020700A5 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x00090F00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A55AA },
         { .reg = 0x00009888, .val = 0x000130FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B0500 },
         { .reg = 0x00009888, .val = 0x00020C00 },
         { .reg = 0x00009888, .val = 0x020C0050 },
         { .reg = 0x00009888, .val = 0x010700A5 },
         { .reg = 0x00009888, .val = 0x0108AF00 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A55AA },
         { .reg = 0x00009888, .val = 0x01010030 },
         { .reg = 0x00009888, .val = 0x010B0500 },
         { .reg = 0x00009888, .val = 0x0102000C },
         { .reg = 0x00009888, .val = 0x010C0050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03210A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030423 },
         { .reg = 0x00009888, .val = 0x48030E21 },
         { .reg = 0x00009888, .val = 0x4A030EE7 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext345__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext345__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext345__avg_gpu_core_frequency__max,acmgt3__ext345__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4371, 24, NULL,acmgt3__ext345__xve_dataport_register_request_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4372, 32, NULL,acmgt3__ext345__xve_dataport_register_request_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4373, 40, NULL,acmgt3__ext345__xve_dataport_register_request_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4374, 48, NULL,acmgt3__ext345__xve_dataport_register_request_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4375, 56, NULL,acmgt3__ext345__xve_dataport_register_request_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4376, 64, NULL,acmgt3__ext345__xve_dataport_register_request_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4377, 72, NULL,acmgt3__ext345__xve_dataport_register_request_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4378, 80, NULL,acmgt3__ext345__xve_dataport_register_request_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext346_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext346";
   query->symbol_name = "Ext346";
   query->guid = "e7738d4d-64e4-4a54-81a3-86702c6fdb47";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext346__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext346__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext346__avg_gpu_core_frequency__max,acmgt3__ext346__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 4379, 24, NULL,acmgt3__ext346__xve_dataport_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1188, 28, NULL,acmgt3__ext346__xve_dataport_register_response_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext347_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext347";
   query->symbol_name = "Ext347";
   query->guid = "bc487d2d-a32a-48d7-bce8-96b19d7853ec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext347__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext347__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext347__avg_gpu_core_frequency__max,acmgt3__ext347__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1189, 24, NULL,acmgt3__ext347__xve_dataport_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1190, 28, NULL,acmgt3__ext347__xve_dataport_register_response_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext348_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext348";
   query->symbol_name = "Ext348";
   query->guid = "434a0292-cb9f-46aa-acec-fb56af5aacec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext348__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext348__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext348__avg_gpu_core_frequency__max,acmgt3__ext348__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1191, 24, NULL,acmgt3__ext348__xve_dataport_register_response_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1192, 28, NULL,acmgt3__ext348__xve_dataport_register_response_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext349_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext349";
   query->symbol_name = "Ext349";
   query->guid = "cf3716ea-68c0-470b-b2ed-07dcad433550";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext349__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext349__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext349__avg_gpu_core_frequency__max,acmgt3__ext349__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1193, 24, NULL,acmgt3__ext349__xve_dataport_register_response_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1194, 28, NULL,acmgt3__ext349__xve_dataport_register_response_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext350_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext350";
   query->symbol_name = "Ext350";
   query->guid = "0233f2f1-7ba2-4419-a8e8-90028db78f6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext350__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext350__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext350__avg_gpu_core_frequency__max,acmgt3__ext350__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 4380, 24, NULL,acmgt3__ext350__xve_dataport_register_response_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 2380, 32, NULL,acmgt3__ext350__xve_dataport_register_response_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext351_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext351";
   query->symbol_name = "Ext351";
   query->guid = "86fb99a2-94a0-4830-bd6e-f22db96c9f9f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext351__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext351__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext351__avg_gpu_core_frequency__max,acmgt3__ext351__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 2381, 24, NULL,acmgt3__ext351__xve_dataport_register_response_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 2382, 28, NULL,acmgt3__ext351__xve_dataport_register_response_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext352_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext352";
   query->symbol_name = "Ext352";
   query->guid = "f189613f-66ee-466c-8ede-7fe9319d4aa0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext352__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext352__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext352__avg_gpu_core_frequency__max,acmgt3__ext352__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 2383, 24, NULL,acmgt3__ext352__xve_dataport_register_response_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 2384, 28, NULL,acmgt3__ext352__xve_dataport_register_response_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext353_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext353";
   query->symbol_name = "Ext353";
   query->guid = "0f278998-80a9-4e06-8f01-3d59e0bbfb4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext353__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext353__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext353__avg_gpu_core_frequency__max,acmgt3__ext353__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 2385, 24, NULL,acmgt3__ext353__xve_dataport_register_response_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 2386, 28, NULL,acmgt3__ext353__xve_dataport_register_response_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext354_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext354";
   query->symbol_name = "Ext354";
   query->guid = "9a3c0284-c012-4094-80ed-bfb46ab762a6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext354__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext354__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext354__avg_gpu_core_frequency__max,acmgt3__ext354__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4381, 24, NULL,acmgt3__ext354__xve_dataport_register_response_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4382, 28, NULL,acmgt3__ext354__xve_dataport_register_response_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext355_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext355";
   query->symbol_name = "Ext355";
   query->guid = "21ebf724-d9a5-473d-a173-04923a9014fa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext355__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext355__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext355__avg_gpu_core_frequency__max,acmgt3__ext355__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4383, 24, NULL,acmgt3__ext355__xve_dataport_register_response_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4384, 28, NULL,acmgt3__ext355__xve_dataport_register_response_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext356_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext356";
   query->symbol_name = "Ext356";
   query->guid = "44f5ade0-0120-4af2-9748-1bf550c3550e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext356__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext356__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext356__avg_gpu_core_frequency__max,acmgt3__ext356__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4385, 24, NULL,acmgt3__ext356__xve_dataport_register_response_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4386, 28, NULL,acmgt3__ext356__xve_dataport_register_response_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext357_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext357";
   query->symbol_name = "Ext357";
   query->guid = "feda9279-042d-4ad4-9d09-b08448fb71e2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext357__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext357__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext357__avg_gpu_core_frequency__max,acmgt3__ext357__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4387, 24, NULL,acmgt3__ext357__xve_dataport_register_response_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4388, 28, NULL,acmgt3__ext357__xve_dataport_register_response_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext358_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext358";
   query->symbol_name = "Ext358";
   query->guid = "287a8880-aa97-4a61-bd9c-c4ea26cac685";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext358__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext358__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext358__avg_gpu_core_frequency__max,acmgt3__ext358__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4389, 24, NULL,acmgt3__ext358__xve_dataport_register_response_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4390, 28, NULL,acmgt3__ext358__xve_dataport_register_response_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext359_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext359";
   query->symbol_name = "Ext359";
   query->guid = "6ec0ccb7-2c59-4c56-a541-5cae1577ccef";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext359__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext359__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext359__avg_gpu_core_frequency__max,acmgt3__ext359__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4391, 24, NULL,acmgt3__ext359__xve_dataport_register_response_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4392, 28, NULL,acmgt3__ext359__xve_dataport_register_response_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext360_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext360";
   query->symbol_name = "Ext360";
   query->guid = "3c210e69-5238-4d7f-a875-5526e0d10784";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext360__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext360__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext360__avg_gpu_core_frequency__max,acmgt3__ext360__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4393, 24, NULL,acmgt3__ext360__xve_dataport_register_response_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4394, 28, NULL,acmgt3__ext360__xve_dataport_register_response_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext361_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext361";
   query->symbol_name = "Ext361";
   query->guid = "3c9d3497-fa1a-4120-86fd-3b5c6dce0608";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext361__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext361__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext361__avg_gpu_core_frequency__max,acmgt3__ext361__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4395, 24, NULL,acmgt3__ext361__xve_dataport_register_response_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4396, 28, NULL,acmgt3__ext361__xve_dataport_register_response_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext362_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext362";
   query->symbol_name = "Ext362";
   query->guid = "176224fc-33cb-480b-90b8-91225247a303";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1881039B },
         { .reg = 0x00009888, .val = 0x18A1039B },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A810207 },
         { .reg = 0x00009888, .val = 0x0C810081 },
         { .reg = 0x00009888, .val = 0x0E810103 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x10A10185 },
         { .reg = 0x00009888, .val = 0x12A10207 },
         { .reg = 0x00009888, .val = 0x14A10081 },
         { .reg = 0x00009888, .val = 0x16A10103 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext362__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext362__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext362__avg_gpu_core_frequency__max,acmgt3__ext362__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1115, 24, percentage_max_float,acmgt3__ext362__dataport_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1116, 28, percentage_max_float,acmgt3__ext362__dataport_input_available_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext363_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext363";
   query->symbol_name = "Ext363";
   query->guid = "496b0c36-4849-4398-aad8-131402b38b41";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18C1039B },
         { .reg = 0x00009888, .val = 0x18E1039B },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x08C10185 },
         { .reg = 0x00009888, .val = 0x0AC10207 },
         { .reg = 0x00009888, .val = 0x0CC10081 },
         { .reg = 0x00009888, .val = 0x0EC10103 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E10185 },
         { .reg = 0x00009888, .val = 0x12E10207 },
         { .reg = 0x00009888, .val = 0x14E10081 },
         { .reg = 0x00009888, .val = 0x16E10103 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext363__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext363__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext363__avg_gpu_core_frequency__max,acmgt3__ext363__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1117, 24, percentage_max_float,acmgt3__ext363__dataport_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1118, 28, percentage_max_float,acmgt3__ext363__dataport_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext364_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext364";
   query->symbol_name = "Ext364";
   query->guid = "0a0b4d5c-4cc0-4f18-84b7-bca6fde241b4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1981039B },
         { .reg = 0x00009888, .val = 0x19A1039B },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B810207 },
         { .reg = 0x00009888, .val = 0x0D810081 },
         { .reg = 0x00009888, .val = 0x0F810103 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x11A10185 },
         { .reg = 0x00009888, .val = 0x13A10207 },
         { .reg = 0x00009888, .val = 0x15A10081 },
         { .reg = 0x00009888, .val = 0x17A10103 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext364__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext364__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext364__avg_gpu_core_frequency__max,acmgt3__ext364__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1119, 24, percentage_max_float,acmgt3__ext364__dataport_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1120, 28, percentage_max_float,acmgt3__ext364__dataport_input_available_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext365_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext365";
   query->symbol_name = "Ext365";
   query->guid = "a726bcbf-febf-4840-8d84-d4e6ce3a7fb0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x19C1039B },
         { .reg = 0x00009888, .val = 0x19E1039B },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x09C10185 },
         { .reg = 0x00009888, .val = 0x0BC10207 },
         { .reg = 0x00009888, .val = 0x0DC10081 },
         { .reg = 0x00009888, .val = 0x0FC10103 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x11E10185 },
         { .reg = 0x00009888, .val = 0x13E10207 },
         { .reg = 0x00009888, .val = 0x15E10081 },
         { .reg = 0x00009888, .val = 0x17E10103 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext365__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext365__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext365__avg_gpu_core_frequency__max,acmgt3__ext365__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1121, 24, percentage_max_float,acmgt3__ext365__dataport_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1122, 28, percentage_max_float,acmgt3__ext365__dataport_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext366_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext366";
   query->symbol_name = "Ext366";
   query->guid = "14001989-7d14-47a5-bd85-d1d2b11d15c1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1881039B },
         { .reg = 0x00009888, .val = 0x18A1039B },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A810207 },
         { .reg = 0x00009888, .val = 0x0C810081 },
         { .reg = 0x00009888, .val = 0x0E810103 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x10A10185 },
         { .reg = 0x00009888, .val = 0x12A10207 },
         { .reg = 0x00009888, .val = 0x14A10081 },
         { .reg = 0x00009888, .val = 0x16A10103 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext366__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext366__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext366__avg_gpu_core_frequency__max,acmgt3__ext366__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 2339, 24, percentage_max_float,acmgt3__ext366__dataport_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 2340, 28, percentage_max_float,acmgt3__ext366__dataport_input_available_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext367_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext367";
   query->symbol_name = "Ext367";
   query->guid = "421c3eb4-c4fc-4a3b-91b3-87a99603466e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18C1039B },
         { .reg = 0x00009888, .val = 0x18E1039B },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x08C10185 },
         { .reg = 0x00009888, .val = 0x0AC10207 },
         { .reg = 0x00009888, .val = 0x0CC10081 },
         { .reg = 0x00009888, .val = 0x0EC10103 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E10185 },
         { .reg = 0x00009888, .val = 0x12E10207 },
         { .reg = 0x00009888, .val = 0x14E10081 },
         { .reg = 0x00009888, .val = 0x16E10103 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext367__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext367__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext367__avg_gpu_core_frequency__max,acmgt3__ext367__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 2341, 24, percentage_max_float,acmgt3__ext367__dataport_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 2342, 28, percentage_max_float,acmgt3__ext367__dataport_input_available_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext368_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext368";
   query->symbol_name = "Ext368";
   query->guid = "854ec412-1ca6-4628-a51c-620c0c9297df";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1981039B },
         { .reg = 0x00009888, .val = 0x19A1039B },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B810207 },
         { .reg = 0x00009888, .val = 0x0D810081 },
         { .reg = 0x00009888, .val = 0x0F810103 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x11A10185 },
         { .reg = 0x00009888, .val = 0x13A10207 },
         { .reg = 0x00009888, .val = 0x15A10081 },
         { .reg = 0x00009888, .val = 0x17A10103 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext368__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext368__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext368__avg_gpu_core_frequency__max,acmgt3__ext368__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 2343, 24, percentage_max_float,acmgt3__ext368__dataport_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 2344, 28, percentage_max_float,acmgt3__ext368__dataport_input_available_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext369_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext369";
   query->symbol_name = "Ext369";
   query->guid = "02175256-9f81-41d6-97e1-ace9e4e4cd45";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19C1039B },
         { .reg = 0x00009888, .val = 0x19E1039B },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x09C10185 },
         { .reg = 0x00009888, .val = 0x0BC10207 },
         { .reg = 0x00009888, .val = 0x0DC10081 },
         { .reg = 0x00009888, .val = 0x0FC10103 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x11E10185 },
         { .reg = 0x00009888, .val = 0x13E10207 },
         { .reg = 0x00009888, .val = 0x15E10081 },
         { .reg = 0x00009888, .val = 0x17E10103 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext369__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext369__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext369__avg_gpu_core_frequency__max,acmgt3__ext369__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 2345, 24, percentage_max_float,acmgt3__ext369__dataport_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 2346, 28, percentage_max_float,acmgt3__ext369__dataport_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext370_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext370";
   query->symbol_name = "Ext370";
   query->guid = "5a99d803-48ba-4b76-b689-58bf406ceaa5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1881039B },
         { .reg = 0x00009888, .val = 0x18A1039B },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A810207 },
         { .reg = 0x00009888, .val = 0x0C810081 },
         { .reg = 0x00009888, .val = 0x0E810103 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x10A10185 },
         { .reg = 0x00009888, .val = 0x12A10207 },
         { .reg = 0x00009888, .val = 0x14A10081 },
         { .reg = 0x00009888, .val = 0x16A10103 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext370__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext370__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext370__avg_gpu_core_frequency__max,acmgt3__ext370__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4397, 24, percentage_max_float,acmgt3__ext370__dataport_input_available_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4398, 28, percentage_max_float,acmgt3__ext370__dataport_input_available_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext371_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext371";
   query->symbol_name = "Ext371";
   query->guid = "64b5963c-65cc-4216-8f23-d96e4268dca8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18C1039B },
         { .reg = 0x00009888, .val = 0x18E1039B },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x08C10185 },
         { .reg = 0x00009888, .val = 0x0AC10207 },
         { .reg = 0x00009888, .val = 0x0CC10081 },
         { .reg = 0x00009888, .val = 0x0EC10103 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E10185 },
         { .reg = 0x00009888, .val = 0x12E10207 },
         { .reg = 0x00009888, .val = 0x14E10081 },
         { .reg = 0x00009888, .val = 0x16E10103 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext371__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext371__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext371__avg_gpu_core_frequency__max,acmgt3__ext371__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4399, 24, percentage_max_float,acmgt3__ext371__dataport_input_available_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4400, 28, percentage_max_float,acmgt3__ext371__dataport_input_available_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext372_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext372";
   query->symbol_name = "Ext372";
   query->guid = "7cf2bd19-9c7c-48df-8080-04b324c1a205";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1981039B },
         { .reg = 0x00009888, .val = 0x19A1039B },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B810207 },
         { .reg = 0x00009888, .val = 0x0D810081 },
         { .reg = 0x00009888, .val = 0x0F810103 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x11A10185 },
         { .reg = 0x00009888, .val = 0x13A10207 },
         { .reg = 0x00009888, .val = 0x15A10081 },
         { .reg = 0x00009888, .val = 0x17A10103 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext372__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext372__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext372__avg_gpu_core_frequency__max,acmgt3__ext372__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4401, 24, percentage_max_float,acmgt3__ext372__dataport_input_available_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4402, 28, percentage_max_float,acmgt3__ext372__dataport_input_available_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext373_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext373";
   query->symbol_name = "Ext373";
   query->guid = "2ac3ef91-7515-4519-a5bd-743564e52e46";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19C1039B },
         { .reg = 0x00009888, .val = 0x19E1039B },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x09C10185 },
         { .reg = 0x00009888, .val = 0x0BC10207 },
         { .reg = 0x00009888, .val = 0x0DC10081 },
         { .reg = 0x00009888, .val = 0x0FC10103 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x11E10185 },
         { .reg = 0x00009888, .val = 0x13E10207 },
         { .reg = 0x00009888, .val = 0x15E10081 },
         { .reg = 0x00009888, .val = 0x17E10103 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext373__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext373__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext373__avg_gpu_core_frequency__max,acmgt3__ext373__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4403, 24, percentage_max_float,acmgt3__ext373__dataport_input_available_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4404, 28, percentage_max_float,acmgt3__ext373__dataport_input_available_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext374_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext374";
   query->symbol_name = "Ext374";
   query->guid = "1bd48e5e-2efa-4f4c-b8c1-7600113347ce";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1881039B },
         { .reg = 0x00009888, .val = 0x18A1039B },
         { .reg = 0x00009888, .val = 0x04810054 },
         { .reg = 0x00009888, .val = 0x08810185 },
         { .reg = 0x00009888, .val = 0x0A810207 },
         { .reg = 0x00009888, .val = 0x0C810081 },
         { .reg = 0x00009888, .val = 0x0E810103 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A10054 },
         { .reg = 0x00009888, .val = 0x10A10185 },
         { .reg = 0x00009888, .val = 0x12A10207 },
         { .reg = 0x00009888, .val = 0x14A10081 },
         { .reg = 0x00009888, .val = 0x16A10103 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext374__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext374__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext374__avg_gpu_core_frequency__max,acmgt3__ext374__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4405, 24, percentage_max_float,acmgt3__ext374__dataport_input_available_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4406, 28, percentage_max_float,acmgt3__ext374__dataport_input_available_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext375_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext375";
   query->symbol_name = "Ext375";
   query->guid = "e3e63d50-a2dd-4880-899b-fc676a87853d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18C1039B },
         { .reg = 0x00009888, .val = 0x18E1039B },
         { .reg = 0x00009888, .val = 0x04C10054 },
         { .reg = 0x00009888, .val = 0x08C10185 },
         { .reg = 0x00009888, .val = 0x0AC10207 },
         { .reg = 0x00009888, .val = 0x0CC10081 },
         { .reg = 0x00009888, .val = 0x0EC10103 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E10054 },
         { .reg = 0x00009888, .val = 0x10E10185 },
         { .reg = 0x00009888, .val = 0x12E10207 },
         { .reg = 0x00009888, .val = 0x14E10081 },
         { .reg = 0x00009888, .val = 0x16E10103 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext375__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext375__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext375__avg_gpu_core_frequency__max,acmgt3__ext375__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4407, 24, percentage_max_float,acmgt3__ext375__dataport_input_available_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4408, 28, percentage_max_float,acmgt3__ext375__dataport_input_available_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext376_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext376";
   query->symbol_name = "Ext376";
   query->guid = "eb0b8725-7fc3-481c-b4ce-c53f32c8e828";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1981039B },
         { .reg = 0x00009888, .val = 0x19A1039B },
         { .reg = 0x00009888, .val = 0x05810054 },
         { .reg = 0x00009888, .val = 0x09810185 },
         { .reg = 0x00009888, .val = 0x0B810207 },
         { .reg = 0x00009888, .val = 0x0D810081 },
         { .reg = 0x00009888, .val = 0x0F810103 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A10054 },
         { .reg = 0x00009888, .val = 0x11A10185 },
         { .reg = 0x00009888, .val = 0x13A10207 },
         { .reg = 0x00009888, .val = 0x15A10081 },
         { .reg = 0x00009888, .val = 0x17A10103 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext376__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext376__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext376__avg_gpu_core_frequency__max,acmgt3__ext376__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4409, 24, percentage_max_float,acmgt3__ext376__dataport_input_available_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4410, 28, percentage_max_float,acmgt3__ext376__dataport_input_available_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext377_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext377";
   query->symbol_name = "Ext377";
   query->guid = "dcb8bd26-ed68-483d-b0c9-41a81b3717dd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x19C1039B },
         { .reg = 0x00009888, .val = 0x19E1039B },
         { .reg = 0x00009888, .val = 0x05C10054 },
         { .reg = 0x00009888, .val = 0x09C10185 },
         { .reg = 0x00009888, .val = 0x0BC10207 },
         { .reg = 0x00009888, .val = 0x0DC10081 },
         { .reg = 0x00009888, .val = 0x0FC10103 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E10054 },
         { .reg = 0x00009888, .val = 0x11E10185 },
         { .reg = 0x00009888, .val = 0x13E10207 },
         { .reg = 0x00009888, .val = 0x15E10081 },
         { .reg = 0x00009888, .val = 0x17E10103 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext377__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext377__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext377__avg_gpu_core_frequency__max,acmgt3__ext377__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4411, 24, percentage_max_float,acmgt3__ext377__dataport_input_available_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4412, 28, percentage_max_float,acmgt3__ext377__dataport_input_available_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext378_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext378";
   query->symbol_name = "Ext378";
   query->guid = "2e0b9ef7-89fc-4a49-b8e9-53f2c4c17e1b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1281C000 },
         { .reg = 0x00009888, .val = 0x12A1C000 },
         { .reg = 0x00009888, .val = 0x12C1C4D2 },
         { .reg = 0x00009888, .val = 0x12E1C000 },
         { .reg = 0x00009888, .val = 0x04810200 },
         { .reg = 0x00009888, .val = 0x08810450 },
         { .reg = 0x00009888, .val = 0x0A8104D2 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x04A10200 },
         { .reg = 0x00009888, .val = 0x0CA10450 },
         { .reg = 0x00009888, .val = 0x0EA104D2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x04C10200 },
         { .reg = 0x00009888, .val = 0x10C10450 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x02C70055 },
         { .reg = 0x00009888, .val = 0x04E10200 },
         { .reg = 0x00009888, .val = 0x14E10450 },
         { .reg = 0x00009888, .val = 0x16E104D2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext378__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext378__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext378__avg_gpu_core_frequency__max,acmgt3__ext378__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1123, 24, percentage_max_float,acmgt3__ext378__dataport_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1124, 28, percentage_max_float,acmgt3__ext378__dataport_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1125, 32, percentage_max_float,acmgt3__ext378__dataport_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1126, 36, percentage_max_float,acmgt3__ext378__dataport_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext379_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext379";
   query->symbol_name = "Ext379";
   query->guid = "08199543-f47a-47ac-ae63-c384083ef85d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1381C000 },
         { .reg = 0x00009888, .val = 0x13A1C000 },
         { .reg = 0x00009888, .val = 0x13C1C4D2 },
         { .reg = 0x00009888, .val = 0x13E1C000 },
         { .reg = 0x00009888, .val = 0x05810200 },
         { .reg = 0x00009888, .val = 0x09810450 },
         { .reg = 0x00009888, .val = 0x0B8104D2 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x05A10200 },
         { .reg = 0x00009888, .val = 0x0DA10450 },
         { .reg = 0x00009888, .val = 0x0FA104D2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x05C10200 },
         { .reg = 0x00009888, .val = 0x11C10450 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x03C70055 },
         { .reg = 0x00009888, .val = 0x05E10200 },
         { .reg = 0x00009888, .val = 0x15E10450 },
         { .reg = 0x00009888, .val = 0x17E104D2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x03E75500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext379__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext379__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext379__avg_gpu_core_frequency__max,acmgt3__ext379__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1127, 24, percentage_max_float,acmgt3__ext379__dataport_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1128, 28, percentage_max_float,acmgt3__ext379__dataport_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1129, 32, percentage_max_float,acmgt3__ext379__dataport_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1130, 36, percentage_max_float,acmgt3__ext379__dataport_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext380_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext380";
   query->symbol_name = "Ext380";
   query->guid = "7f7a14d6-3e61-478e-a4a1-8c6cfe0eb323";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281C000 },
         { .reg = 0x00009888, .val = 0x12A1C000 },
         { .reg = 0x00009888, .val = 0x12C1C4D2 },
         { .reg = 0x00009888, .val = 0x12E1C000 },
         { .reg = 0x00009888, .val = 0x04810200 },
         { .reg = 0x00009888, .val = 0x08810450 },
         { .reg = 0x00009888, .val = 0x0A8104D2 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x04A10200 },
         { .reg = 0x00009888, .val = 0x0CA10450 },
         { .reg = 0x00009888, .val = 0x0EA104D2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x04C10200 },
         { .reg = 0x00009888, .val = 0x10C10450 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x02C70055 },
         { .reg = 0x00009888, .val = 0x04E10200 },
         { .reg = 0x00009888, .val = 0x14E10450 },
         { .reg = 0x00009888, .val = 0x16E104D2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext380__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext380__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext380__avg_gpu_core_frequency__max,acmgt3__ext380__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 2347, 24, percentage_max_float,acmgt3__ext380__dataport_output_ready_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 2348, 28, percentage_max_float,acmgt3__ext380__dataport_output_ready_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 2349, 32, percentage_max_float,acmgt3__ext380__dataport_output_ready_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 2350, 36, percentage_max_float,acmgt3__ext380__dataport_output_ready_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext381_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext381";
   query->symbol_name = "Ext381";
   query->guid = "cbcdedd3-06c0-452a-80bc-2657fd042c53";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381C000 },
         { .reg = 0x00009888, .val = 0x13A1C000 },
         { .reg = 0x00009888, .val = 0x13C1C4D2 },
         { .reg = 0x00009888, .val = 0x13E1C000 },
         { .reg = 0x00009888, .val = 0x05810200 },
         { .reg = 0x00009888, .val = 0x09810450 },
         { .reg = 0x00009888, .val = 0x0B8104D2 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x05A10200 },
         { .reg = 0x00009888, .val = 0x0DA10450 },
         { .reg = 0x00009888, .val = 0x0FA104D2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x05C10200 },
         { .reg = 0x00009888, .val = 0x11C10450 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x03C70055 },
         { .reg = 0x00009888, .val = 0x05E10200 },
         { .reg = 0x00009888, .val = 0x15E10450 },
         { .reg = 0x00009888, .val = 0x17E104D2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x03E75500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext381__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext381__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext381__avg_gpu_core_frequency__max,acmgt3__ext381__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 2351, 24, percentage_max_float,acmgt3__ext381__dataport_output_ready_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 2352, 28, percentage_max_float,acmgt3__ext381__dataport_output_ready_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 2353, 32, percentage_max_float,acmgt3__ext381__dataport_output_ready_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 2354, 36, percentage_max_float,acmgt3__ext381__dataport_output_ready_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext382_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext382";
   query->symbol_name = "Ext382";
   query->guid = "a43eac54-7cf5-4d96-8496-514979ca4c9a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1281C000 },
         { .reg = 0x00009888, .val = 0x12A1C000 },
         { .reg = 0x00009888, .val = 0x12C1C4D2 },
         { .reg = 0x00009888, .val = 0x12E1C000 },
         { .reg = 0x00009888, .val = 0x04810200 },
         { .reg = 0x00009888, .val = 0x08810450 },
         { .reg = 0x00009888, .val = 0x0A8104D2 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x04A10200 },
         { .reg = 0x00009888, .val = 0x0CA10450 },
         { .reg = 0x00009888, .val = 0x0EA104D2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x04C10200 },
         { .reg = 0x00009888, .val = 0x10C10450 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x02C70055 },
         { .reg = 0x00009888, .val = 0x04E10200 },
         { .reg = 0x00009888, .val = 0x14E10450 },
         { .reg = 0x00009888, .val = 0x16E104D2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext382__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext382__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext382__avg_gpu_core_frequency__max,acmgt3__ext382__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4413, 24, percentage_max_float,acmgt3__ext382__dataport_output_ready_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4414, 28, percentage_max_float,acmgt3__ext382__dataport_output_ready_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4415, 32, percentage_max_float,acmgt3__ext382__dataport_output_ready_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4416, 36, percentage_max_float,acmgt3__ext382__dataport_output_ready_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext383_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext383";
   query->symbol_name = "Ext383";
   query->guid = "ca5db39c-f550-4965-8402-553fbf5e7920";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1381C000 },
         { .reg = 0x00009888, .val = 0x13A1C000 },
         { .reg = 0x00009888, .val = 0x13C1C4D2 },
         { .reg = 0x00009888, .val = 0x13E1C000 },
         { .reg = 0x00009888, .val = 0x05810200 },
         { .reg = 0x00009888, .val = 0x09810450 },
         { .reg = 0x00009888, .val = 0x0B8104D2 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x05A10200 },
         { .reg = 0x00009888, .val = 0x0DA10450 },
         { .reg = 0x00009888, .val = 0x0FA104D2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x05C10200 },
         { .reg = 0x00009888, .val = 0x11C10450 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x03C70055 },
         { .reg = 0x00009888, .val = 0x05E10200 },
         { .reg = 0x00009888, .val = 0x15E10450 },
         { .reg = 0x00009888, .val = 0x17E104D2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x03E75500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext383__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext383__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext383__avg_gpu_core_frequency__max,acmgt3__ext383__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4417, 24, percentage_max_float,acmgt3__ext383__dataport_output_ready_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4418, 28, percentage_max_float,acmgt3__ext383__dataport_output_ready_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4419, 32, percentage_max_float,acmgt3__ext383__dataport_output_ready_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4420, 36, percentage_max_float,acmgt3__ext383__dataport_output_ready_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext384_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext384";
   query->symbol_name = "Ext384";
   query->guid = "45be76fb-6be9-4028-b98d-5cff32f7a51e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1281C000 },
         { .reg = 0x00009888, .val = 0x12A1C000 },
         { .reg = 0x00009888, .val = 0x12C1C4D2 },
         { .reg = 0x00009888, .val = 0x12E1C000 },
         { .reg = 0x00009888, .val = 0x04810200 },
         { .reg = 0x00009888, .val = 0x08810450 },
         { .reg = 0x00009888, .val = 0x0A8104D2 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x04A10200 },
         { .reg = 0x00009888, .val = 0x0CA10450 },
         { .reg = 0x00009888, .val = 0x0EA104D2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x00A400F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x04C10200 },
         { .reg = 0x00009888, .val = 0x10C10450 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C300AA },
         { .reg = 0x00009888, .val = 0x00C40F00 },
         { .reg = 0x00009888, .val = 0x02C60055 },
         { .reg = 0x00009888, .val = 0x02C70055 },
         { .reg = 0x00009888, .val = 0x04E10200 },
         { .reg = 0x00009888, .val = 0x14E10450 },
         { .reg = 0x00009888, .val = 0x16E104D2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AA00 },
         { .reg = 0x00009888, .val = 0x00E4F000 },
         { .reg = 0x00009888, .val = 0x02E65500 },
         { .reg = 0x00009888, .val = 0x02E75500 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext384__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext384__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext384__avg_gpu_core_frequency__max,acmgt3__ext384__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4421, 24, percentage_max_float,acmgt3__ext384__dataport_output_ready_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4422, 28, percentage_max_float,acmgt3__ext384__dataport_output_ready_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4423, 32, percentage_max_float,acmgt3__ext384__dataport_output_ready_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4424, 36, percentage_max_float,acmgt3__ext384__dataport_output_ready_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext385_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext385";
   query->symbol_name = "Ext385";
   query->guid = "840b7ed8-e148-4503-9f1b-2df3a551c5c3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1381C000 },
         { .reg = 0x00009888, .val = 0x13A1C000 },
         { .reg = 0x00009888, .val = 0x13C1C4D2 },
         { .reg = 0x00009888, .val = 0x13E1C000 },
         { .reg = 0x00009888, .val = 0x05810200 },
         { .reg = 0x00009888, .val = 0x09810450 },
         { .reg = 0x00009888, .val = 0x0B8104D2 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x05A10200 },
         { .reg = 0x00009888, .val = 0x0DA10450 },
         { .reg = 0x00009888, .val = 0x0FA104D2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x01A400F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x05C10200 },
         { .reg = 0x00009888, .val = 0x11C10450 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C300AA },
         { .reg = 0x00009888, .val = 0x01C40F00 },
         { .reg = 0x00009888, .val = 0x03C60055 },
         { .reg = 0x00009888, .val = 0x03C70055 },
         { .reg = 0x00009888, .val = 0x05E10200 },
         { .reg = 0x00009888, .val = 0x15E10450 },
         { .reg = 0x00009888, .val = 0x17E104D2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AA00 },
         { .reg = 0x00009888, .val = 0x01E4F000 },
         { .reg = 0x00009888, .val = 0x03E65500 },
         { .reg = 0x00009888, .val = 0x03E75500 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext385__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext385__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext385__avg_gpu_core_frequency__max,acmgt3__ext385__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4425, 24, percentage_max_float,acmgt3__ext385__dataport_output_ready_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4426, 28, percentage_max_float,acmgt3__ext385__dataport_output_ready_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4427, 32, percentage_max_float,acmgt3__ext385__dataport_output_ready_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4428, 36, percentage_max_float,acmgt3__ext385__dataport_output_ready_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext386_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext386";
   query->symbol_name = "Ext386";
   query->guid = "5475ddd8-8385-4631-a009-45fe26c8658c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext386__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext386__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext386__avg_gpu_core_frequency__max,acmgt3__ext386__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1131, 24, NULL,acmgt3__ext386__dataport_byte_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1132, 32, NULL,acmgt3__ext386__dataport_byte_read_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext387_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext387";
   query->symbol_name = "Ext387";
   query->guid = "0906197a-4ac1-4af4-868f-8172f9b034ac";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext387__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext387__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext387__avg_gpu_core_frequency__max,acmgt3__ext387__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1133, 24, NULL,acmgt3__ext387__dataport_byte_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1134, 32, NULL,acmgt3__ext387__dataport_byte_read_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext388_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext388";
   query->symbol_name = "Ext388";
   query->guid = "ce2dc9cd-b9e9-4c74-934b-d1b3590b473c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext388__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext388__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext388__avg_gpu_core_frequency__max,acmgt3__ext388__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1135, 24, NULL,acmgt3__ext388__dataport_byte_read_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1136, 32, NULL,acmgt3__ext388__dataport_byte_read_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext389_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext389";
   query->symbol_name = "Ext389";
   query->guid = "d87d855d-5896-4c76-b0fe-4120c5ad1a63";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext389__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext389__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext389__avg_gpu_core_frequency__max,acmgt3__ext389__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1137, 24, NULL,acmgt3__ext389__dataport_byte_read_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1138, 32, NULL,acmgt3__ext389__dataport_byte_read_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext390_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext390";
   query->symbol_name = "Ext390";
   query->guid = "d8b0608d-4fe4-4762-8df3-429344ff1a10";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext390__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext390__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext390__avg_gpu_core_frequency__max,acmgt3__ext390__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2355, 24, NULL,acmgt3__ext390__dataport_byte_read_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2356, 32, NULL,acmgt3__ext390__dataport_byte_read_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext391_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext391";
   query->symbol_name = "Ext391";
   query->guid = "1635ad22-5347-4911-a15c-0716a7fd55d0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext391__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext391__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext391__avg_gpu_core_frequency__max,acmgt3__ext391__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2357, 24, NULL,acmgt3__ext391__dataport_byte_read_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2358, 32, NULL,acmgt3__ext391__dataport_byte_read_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext392_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext392";
   query->symbol_name = "Ext392";
   query->guid = "e001e26e-5522-4f0b-a437-e6d6c3144a8c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext392__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext392__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext392__avg_gpu_core_frequency__max,acmgt3__ext392__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2359, 24, NULL,acmgt3__ext392__dataport_byte_read_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2360, 32, NULL,acmgt3__ext392__dataport_byte_read_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext393_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext393";
   query->symbol_name = "Ext393";
   query->guid = "64ea4666-79c3-4e0a-a68e-5a65ed571a8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext393__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext393__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext393__avg_gpu_core_frequency__max,acmgt3__ext393__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2361, 24, NULL,acmgt3__ext393__dataport_byte_read_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2362, 32, NULL,acmgt3__ext393__dataport_byte_read_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext394_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext394";
   query->symbol_name = "Ext394";
   query->guid = "437d1633-c275-49f0-9994-4e94672ac99c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext394__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext394__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext394__avg_gpu_core_frequency__max,acmgt3__ext394__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4429, 24, NULL,acmgt3__ext394__dataport_byte_read_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4430, 32, NULL,acmgt3__ext394__dataport_byte_read_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext395_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext395";
   query->symbol_name = "Ext395";
   query->guid = "ed6321f2-59be-4560-889b-5682128d1177";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext395__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext395__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext395__avg_gpu_core_frequency__max,acmgt3__ext395__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4431, 24, NULL,acmgt3__ext395__dataport_byte_read_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4432, 32, NULL,acmgt3__ext395__dataport_byte_read_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext396_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext396";
   query->symbol_name = "Ext396";
   query->guid = "c3a07e91-05fe-458d-a578-55b67eb8625a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext396__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext396__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext396__avg_gpu_core_frequency__max,acmgt3__ext396__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4433, 24, NULL,acmgt3__ext396__dataport_byte_read_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4434, 32, NULL,acmgt3__ext396__dataport_byte_read_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext397_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext397";
   query->symbol_name = "Ext397";
   query->guid = "25a1e5ce-835d-4659-896b-a7279e2df94e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext397__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext397__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext397__avg_gpu_core_frequency__max,acmgt3__ext397__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4435, 24, NULL,acmgt3__ext397__dataport_byte_read_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4436, 32, NULL,acmgt3__ext397__dataport_byte_read_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext398_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext398";
   query->symbol_name = "Ext398";
   query->guid = "13b89a1d-1377-41f5-ba3f-800afcfb86a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1281A000 },
         { .reg = 0x00009888, .val = 0x1481B000 },
         { .reg = 0x00009888, .val = 0x12A1A656 },
         { .reg = 0x00009888, .val = 0x14A1B695 },
         { .reg = 0x00009888, .val = 0x04813200 },
         { .reg = 0x00009888, .val = 0x08810617 },
         { .reg = 0x00009888, .val = 0x0A810656 },
         { .reg = 0x00009888, .val = 0x0C810695 },
         { .reg = 0x00009888, .val = 0x0E8106D4 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x04A13200 },
         { .reg = 0x00009888, .val = 0x10A10617 },
         { .reg = 0x00009888, .val = 0x16A106D4 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FF00 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x02A75555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext398__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext398__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext398__avg_gpu_core_frequency__max,acmgt3__ext398__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4437, 24, NULL,acmgt3__ext398__dataport_byte_read_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4438, 32, NULL,acmgt3__ext398__dataport_byte_read_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext399_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext399";
   query->symbol_name = "Ext399";
   query->guid = "dea45968-7d62-4989-bb89-ff1ffcf44402";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x12C1A000 },
         { .reg = 0x00009888, .val = 0x14C1B000 },
         { .reg = 0x00009888, .val = 0x12E1A656 },
         { .reg = 0x00009888, .val = 0x14E1B695 },
         { .reg = 0x00009888, .val = 0x04C13200 },
         { .reg = 0x00009888, .val = 0x08C10617 },
         { .reg = 0x00009888, .val = 0x0AC10656 },
         { .reg = 0x00009888, .val = 0x0CC10695 },
         { .reg = 0x00009888, .val = 0x0EC106D4 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x04E13200 },
         { .reg = 0x00009888, .val = 0x10E10617 },
         { .reg = 0x00009888, .val = 0x16E106D4 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FF00 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x02E75555 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext399__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext399__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext399__avg_gpu_core_frequency__max,acmgt3__ext399__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4439, 24, NULL,acmgt3__ext399__dataport_byte_read_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4440, 32, NULL,acmgt3__ext399__dataport_byte_read_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext400_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext400";
   query->symbol_name = "Ext400";
   query->guid = "5df56b7b-4cd0-4f36-b91b-44e4f47ab5da";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1381A000 },
         { .reg = 0x00009888, .val = 0x1581B000 },
         { .reg = 0x00009888, .val = 0x13A1A656 },
         { .reg = 0x00009888, .val = 0x15A1B695 },
         { .reg = 0x00009888, .val = 0x05813200 },
         { .reg = 0x00009888, .val = 0x09810617 },
         { .reg = 0x00009888, .val = 0x0B810656 },
         { .reg = 0x00009888, .val = 0x0D810695 },
         { .reg = 0x00009888, .val = 0x0F8106D4 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x05A13200 },
         { .reg = 0x00009888, .val = 0x11A10617 },
         { .reg = 0x00009888, .val = 0x17A106D4 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FF00 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x03A75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FF00 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032940 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403014A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext400__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext400__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext400__avg_gpu_core_frequency__max,acmgt3__ext400__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4441, 24, NULL,acmgt3__ext400__dataport_byte_read_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4442, 32, NULL,acmgt3__ext400__dataport_byte_read_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext401_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext401";
   query->symbol_name = "Ext401";
   query->guid = "f48f4171-49a5-4a0e-bfcc-9f1f89569138";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x13C1A000 },
         { .reg = 0x00009888, .val = 0x15C1B000 },
         { .reg = 0x00009888, .val = 0x13E1A656 },
         { .reg = 0x00009888, .val = 0x15E1B695 },
         { .reg = 0x00009888, .val = 0x05C13200 },
         { .reg = 0x00009888, .val = 0x09C10617 },
         { .reg = 0x00009888, .val = 0x0BC10656 },
         { .reg = 0x00009888, .val = 0x0DC10695 },
         { .reg = 0x00009888, .val = 0x0FC106D4 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x05E13200 },
         { .reg = 0x00009888, .val = 0x11E10617 },
         { .reg = 0x00009888, .val = 0x17E106D4 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FF00 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x03E75555 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010200FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x4203000A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext401__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext401__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext401__avg_gpu_core_frequency__max,acmgt3__ext401__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4443, 24, NULL,acmgt3__ext401__dataport_byte_read_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4444, 32, NULL,acmgt3__ext401__dataport_byte_read_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext402_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext402";
   query->symbol_name = "Ext402";
   query->guid = "bed2251c-d53e-402c-9100-2f27febc1672";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x16810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x16A10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x14C10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x14E10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x13810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x13A10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x11C10580 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x11E10016 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0E810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0EA10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0CC10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0CE10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0B810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0BA10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x09C10580 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x09E10016 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext402__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext402__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext402__avg_gpu_core_frequency__max,acmgt3__ext402__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1139, 24, NULL,acmgt3__ext402__dataport_byte_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1140, 32, NULL,acmgt3__ext402__dataport_byte_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1141, 40, NULL,acmgt3__ext402__dataport_byte_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1142, 48, NULL,acmgt3__ext402__dataport_byte_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1143, 56, NULL,acmgt3__ext402__dataport_byte_write_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1144, 64, NULL,acmgt3__ext402__dataport_byte_write_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1145, 72, NULL,acmgt3__ext402__dataport_byte_write_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1146, 80, NULL,acmgt3__ext402__dataport_byte_write_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2363, 88, NULL,acmgt3__ext402__dataport_byte_write_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2364, 96, NULL,acmgt3__ext402__dataport_byte_write_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2365, 104, NULL,acmgt3__ext402__dataport_byte_write_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2366, 112, NULL,acmgt3__ext402__dataport_byte_write_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2367, 120, NULL,acmgt3__ext402__dataport_byte_write_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2368, 128, NULL,acmgt3__ext402__dataport_byte_write_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2369, 136, NULL,acmgt3__ext402__dataport_byte_write_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2370, 144, NULL,acmgt3__ext402__dataport_byte_write_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext403_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext403";
   query->symbol_name = "Ext403";
   query->guid = "1894c9d9-8ba5-41df-97ba-6cadd89a8418";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x16810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x16A10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x14C10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x14E10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x13810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x13A10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x11C10580 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x11E10016 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E810340 },
         { .reg = 0x00009888, .val = 0x1EA10340 },
         { .reg = 0x00009888, .val = 0x1EC10340 },
         { .reg = 0x00009888, .val = 0x1EE10340 },
         { .reg = 0x00009888, .val = 0x1F810340 },
         { .reg = 0x00009888, .val = 0x1FA10340 },
         { .reg = 0x00009888, .val = 0x1FC10340 },
         { .reg = 0x00009888, .val = 0x1FE10340 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0E810580 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0EA10016 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0CC10580 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0CE10016 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0B810580 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0BA10016 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x09C10580 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x09E10016 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext403__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext403__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext403__avg_gpu_core_frequency__max,acmgt3__ext403__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4445, 24, NULL,acmgt3__ext403__dataport_byte_write_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4446, 32, NULL,acmgt3__ext403__dataport_byte_write_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4447, 40, NULL,acmgt3__ext403__dataport_byte_write_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4448, 48, NULL,acmgt3__ext403__dataport_byte_write_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4449, 56, NULL,acmgt3__ext403__dataport_byte_write_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4450, 64, NULL,acmgt3__ext403__dataport_byte_write_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4451, 72, NULL,acmgt3__ext403__dataport_byte_write_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4452, 80, NULL,acmgt3__ext403__dataport_byte_write_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4453, 88, NULL,acmgt3__ext403__dataport_byte_write_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4454, 96, NULL,acmgt3__ext403__dataport_byte_write_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4455, 104, NULL,acmgt3__ext403__dataport_byte_write_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4456, 112, NULL,acmgt3__ext403__dataport_byte_write_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4457, 120, NULL,acmgt3__ext403__dataport_byte_write_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4458, 128, NULL,acmgt3__ext403__dataport_byte_write_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4459, 136, NULL,acmgt3__ext403__dataport_byte_write_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4460, 144, NULL,acmgt3__ext403__dataport_byte_write_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext404_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext404";
   query->symbol_name = "Ext404";
   query->guid = "8712ea52-9c71-4036-a736-308b77af503a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E810020 },
         { .reg = 0x00009888, .val = 0x1EA10020 },
         { .reg = 0x00009888, .val = 0x1EC10020 },
         { .reg = 0x00009888, .val = 0x1EE10020 },
         { .reg = 0x00009888, .val = 0x1F810020 },
         { .reg = 0x00009888, .val = 0x1FA10020 },
         { .reg = 0x00009888, .val = 0x1FC10020 },
         { .reg = 0x00009888, .val = 0x1FE10020 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x16810440 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x16A10011 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x14C10440 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x14E10011 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x13810440 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x13A10011 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x11C10440 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x11E10011 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E810020 },
         { .reg = 0x00009888, .val = 0x1EA10020 },
         { .reg = 0x00009888, .val = 0x1EC10020 },
         { .reg = 0x00009888, .val = 0x1EE10020 },
         { .reg = 0x00009888, .val = 0x1F810020 },
         { .reg = 0x00009888, .val = 0x1FA10020 },
         { .reg = 0x00009888, .val = 0x1FC10020 },
         { .reg = 0x00009888, .val = 0x1FE10020 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0E810440 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0EA10011 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0CC10440 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0CE10011 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0B810440 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0BA10011 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x09C10440 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x09E10011 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext404__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext404__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext404__avg_gpu_core_frequency__max,acmgt3__ext404__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1147, 24, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1148, 32, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1149, 40, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1150, 48, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1151, 56, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1152, 64, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1153, 72, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1154, 80, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2387, 88, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2388, 96, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2389, 104, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2390, 112, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2391, 120, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2392, 128, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2393, 136, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2394, 144, NULL,acmgt3__ext404__dataport_texture_cache_access_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext405_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext405";
   query->symbol_name = "Ext405";
   query->guid = "8e9ae82a-577e-4804-b314-de02d7206903";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E810020 },
         { .reg = 0x00009888, .val = 0x1EA10020 },
         { .reg = 0x00009888, .val = 0x1EC10020 },
         { .reg = 0x00009888, .val = 0x1EE10020 },
         { .reg = 0x00009888, .val = 0x1F810020 },
         { .reg = 0x00009888, .val = 0x1FA10020 },
         { .reg = 0x00009888, .val = 0x1FC10020 },
         { .reg = 0x00009888, .val = 0x1FE10020 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x16810440 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x16A10011 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x14C10440 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x14E10011 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x13810440 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x13A10011 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x11C10440 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x11E10011 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E810020 },
         { .reg = 0x00009888, .val = 0x1EA10020 },
         { .reg = 0x00009888, .val = 0x1EC10020 },
         { .reg = 0x00009888, .val = 0x1EE10020 },
         { .reg = 0x00009888, .val = 0x1F810020 },
         { .reg = 0x00009888, .val = 0x1FA10020 },
         { .reg = 0x00009888, .val = 0x1FC10020 },
         { .reg = 0x00009888, .val = 0x1FE10020 },
         { .reg = 0x00009888, .val = 0x04810400 },
         { .reg = 0x00009888, .val = 0x0E810440 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10400 },
         { .reg = 0x00009888, .val = 0x0EA10011 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10400 },
         { .reg = 0x00009888, .val = 0x0CC10440 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10400 },
         { .reg = 0x00009888, .val = 0x0CE10011 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810400 },
         { .reg = 0x00009888, .val = 0x0B810440 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10400 },
         { .reg = 0x00009888, .val = 0x0BA10011 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10400 },
         { .reg = 0x00009888, .val = 0x09C10440 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10400 },
         { .reg = 0x00009888, .val = 0x09E10011 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext405__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext405__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext405__avg_gpu_core_frequency__max,acmgt3__ext405__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4461, 24, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4462, 32, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4463, 40, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4464, 48, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4465, 56, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4466, 64, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4467, 72, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4468, 80, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4469, 88, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4470, 96, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4471, 104, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4472, 112, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4473, 120, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4474, 128, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4475, 136, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4476, 144, NULL,acmgt3__ext405__dataport_texture_cache_access_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext406_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext406";
   query->symbol_name = "Ext406";
   query->guid = "654e925d-2c2a-49a9-bd44-3470039c6e86";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2081001F },
         { .reg = 0x00009888, .val = 0x20A1001F },
         { .reg = 0x00009888, .val = 0x20C1001F },
         { .reg = 0x00009888, .val = 0x20E1001F },
         { .reg = 0x00009888, .val = 0x2181001F },
         { .reg = 0x00009888, .val = 0x21A1001F },
         { .reg = 0x00009888, .val = 0x21C1001F },
         { .reg = 0x00009888, .val = 0x21E1001F },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x16810500 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x16A10014 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x14C10500 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x14E10014 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x13810500 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x13A10014 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x11C10500 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x11E10014 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2081001F },
         { .reg = 0x00009888, .val = 0x20A1001F },
         { .reg = 0x00009888, .val = 0x20C1001F },
         { .reg = 0x00009888, .val = 0x20E1001F },
         { .reg = 0x00009888, .val = 0x2181001F },
         { .reg = 0x00009888, .val = 0x21A1001F },
         { .reg = 0x00009888, .val = 0x21C1001F },
         { .reg = 0x00009888, .val = 0x21E1001F },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x0E810500 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x0EA10014 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x0CC10500 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x0CE10014 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x0B810500 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x0BA10014 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x09C10500 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x09E10014 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext406__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext406__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext406__avg_gpu_core_frequency__max,acmgt3__ext406__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1155, 24, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1156, 32, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1157, 40, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1158, 48, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1159, 56, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1160, 64, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1161, 72, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1162, 80, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2395, 88, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2396, 96, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2397, 104, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2398, 112, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2399, 120, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2400, 128, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2401, 136, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2402, 144, NULL,acmgt3__ext406__dataport_texture_cache_hit_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext407_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext407";
   query->symbol_name = "Ext407";
   query->guid = "f9c431af-992b-4f6c-b068-4e89ca0b3538";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2081001F },
         { .reg = 0x00009888, .val = 0x20A1001F },
         { .reg = 0x00009888, .val = 0x20C1001F },
         { .reg = 0x00009888, .val = 0x20E1001F },
         { .reg = 0x00009888, .val = 0x2181001F },
         { .reg = 0x00009888, .val = 0x21A1001F },
         { .reg = 0x00009888, .val = 0x21C1001F },
         { .reg = 0x00009888, .val = 0x21E1001F },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x16810500 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x16A10014 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x14C10500 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x14E10014 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x13810500 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x13A10014 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x11C10500 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x11E10014 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2081001F },
         { .reg = 0x00009888, .val = 0x20A1001F },
         { .reg = 0x00009888, .val = 0x20C1001F },
         { .reg = 0x00009888, .val = 0x20E1001F },
         { .reg = 0x00009888, .val = 0x2181001F },
         { .reg = 0x00009888, .val = 0x21A1001F },
         { .reg = 0x00009888, .val = 0x21C1001F },
         { .reg = 0x00009888, .val = 0x21E1001F },
         { .reg = 0x00009888, .val = 0x04810600 },
         { .reg = 0x00009888, .val = 0x0E810500 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x04A10600 },
         { .reg = 0x00009888, .val = 0x0EA10014 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x04C10600 },
         { .reg = 0x00009888, .val = 0x0CC10500 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x04E10600 },
         { .reg = 0x00009888, .val = 0x0CE10014 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x05810600 },
         { .reg = 0x00009888, .val = 0x0B810500 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x05A10600 },
         { .reg = 0x00009888, .val = 0x0BA10014 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x05C10600 },
         { .reg = 0x00009888, .val = 0x09C10500 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x05E10600 },
         { .reg = 0x00009888, .val = 0x09E10014 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext407__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext407__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext407__avg_gpu_core_frequency__max,acmgt3__ext407__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4477, 24, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4478, 32, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4479, 40, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4480, 48, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4481, 56, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4482, 64, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4483, 72, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4484, 80, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4485, 88, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4486, 96, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4487, 104, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4488, 112, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4489, 120, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4490, 128, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4491, 136, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4492, 144, NULL,acmgt3__ext407__dataport_texture_cache_hit_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext408_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext408";
   query->symbol_name = "Ext408";
   query->guid = "c7fe43dc-ae1a-45d9-b64d-60fac946a070";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16857FC0 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x08851000 },
         { .reg = 0x00009888, .val = 0x18894740 },
         { .reg = 0x00009888, .val = 0x1E89023A },
         { .reg = 0x00009888, .val = 0x22896800 },
         { .reg = 0x00009888, .val = 0x24890011 },
         { .reg = 0x00009888, .val = 0x28894740 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x02850B2C },
         { .reg = 0x00009888, .val = 0x0E850154 },
         { .reg = 0x00009888, .val = 0x108505D8 },
         { .reg = 0x00009888, .val = 0x128503CE },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0286AAA0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x068903C1 },
         { .reg = 0x00009888, .val = 0x088907D1 },
         { .reg = 0x00009888, .val = 0x0A890BE1 },
         { .reg = 0x00009888, .val = 0x0C890FF1 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext408__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext408__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext408__avg_gpu_core_frequency__max,acmgt3__ext408__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1650, 24, NULL,acmgt3__ext408__rt_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1658, 32, NULL,acmgt3__ext408__rt_load_store_cache_write_from_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1496, 40, NULL,acmgt3__ext408__rt_traversal_input_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1552, 48, NULL,acmgt3__ext408__rt_quad_test_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1576, 56, NULL,acmgt3__ext408__rt_request_collision_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1488, 64, NULL,acmgt3__ext408__rt_input_message_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1568, 72, percentage_max_float,acmgt3__ext408__rt_message_stall_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1560, 80, NULL,acmgt3__ext408__rt_transform_ray_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext409_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext409";
   query->symbol_name = "Ext409";
   query->guid = "0b7c4602-76f0-4a2e-abe4-f0829f2f9b02";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16A57FC0 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x08A51000 },
         { .reg = 0x00009888, .val = 0x18A94740 },
         { .reg = 0x00009888, .val = 0x1EA9023A },
         { .reg = 0x00009888, .val = 0x22A96800 },
         { .reg = 0x00009888, .val = 0x24A90011 },
         { .reg = 0x00009888, .val = 0x28A94740 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x00A400FF },
         { .reg = 0x00009888, .val = 0x02A50B2C },
         { .reg = 0x00009888, .val = 0x0EA50154 },
         { .reg = 0x00009888, .val = 0x10A505D8 },
         { .reg = 0x00009888, .val = 0x12A503CE },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A6AAA0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A903C1 },
         { .reg = 0x00009888, .val = 0x08A907D1 },
         { .reg = 0x00009888, .val = 0x0AA90BE1 },
         { .reg = 0x00009888, .val = 0x0CA90FF1 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext409__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext409__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext409__avg_gpu_core_frequency__max,acmgt3__ext409__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1651, 24, NULL,acmgt3__ext409__rt_load_store_cache_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1659, 32, NULL,acmgt3__ext409__rt_load_store_cache_write_from_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1497, 40, NULL,acmgt3__ext409__rt_traversal_input_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1553, 48, NULL,acmgt3__ext409__rt_quad_test_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1577, 56, NULL,acmgt3__ext409__rt_request_collision_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1489, 64, NULL,acmgt3__ext409__rt_input_message_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1569, 72, percentage_max_float,acmgt3__ext409__rt_message_stall_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1561, 80, NULL,acmgt3__ext409__rt_transform_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext410_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext410";
   query->symbol_name = "Ext410";
   query->guid = "64a617b8-cae0-439e-b014-1e70e72ac75d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16C57FC0 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x08C51000 },
         { .reg = 0x00009888, .val = 0x18C94740 },
         { .reg = 0x00009888, .val = 0x1EC9023A },
         { .reg = 0x00009888, .val = 0x22C96800 },
         { .reg = 0x00009888, .val = 0x24C90011 },
         { .reg = 0x00009888, .val = 0x28C94740 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x02C50B2C },
         { .reg = 0x00009888, .val = 0x0EC50154 },
         { .reg = 0x00009888, .val = 0x10C505D8 },
         { .reg = 0x00009888, .val = 0x12C503CE },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C6AAA0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C903C1 },
         { .reg = 0x00009888, .val = 0x08C907D1 },
         { .reg = 0x00009888, .val = 0x0AC90BE1 },
         { .reg = 0x00009888, .val = 0x0CC90FF1 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FCFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext410__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext410__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext410__avg_gpu_core_frequency__max,acmgt3__ext410__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1652, 24, NULL,acmgt3__ext410__rt_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1660, 32, NULL,acmgt3__ext410__rt_load_store_cache_write_from_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1498, 40, NULL,acmgt3__ext410__rt_traversal_input_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1554, 48, NULL,acmgt3__ext410__rt_quad_test_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1578, 56, NULL,acmgt3__ext410__rt_request_collision_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1490, 64, NULL,acmgt3__ext410__rt_input_message_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1570, 72, percentage_max_float,acmgt3__ext410__rt_message_stall_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1562, 80, NULL,acmgt3__ext410__rt_transform_ray_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext411_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext411";
   query->symbol_name = "Ext411";
   query->guid = "304aa1c9-59be-4f9d-ab68-2d607a9b90ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16E57FC0 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x08E51000 },
         { .reg = 0x00009888, .val = 0x18E94740 },
         { .reg = 0x00009888, .val = 0x1EE9023A },
         { .reg = 0x00009888, .val = 0x22E96800 },
         { .reg = 0x00009888, .val = 0x24E90011 },
         { .reg = 0x00009888, .val = 0x28E94740 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x00E400FF },
         { .reg = 0x00009888, .val = 0x02E50B2C },
         { .reg = 0x00009888, .val = 0x0EE50154 },
         { .reg = 0x00009888, .val = 0x10E505D8 },
         { .reg = 0x00009888, .val = 0x12E503CE },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E6AAA0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E903C1 },
         { .reg = 0x00009888, .val = 0x08E907D1 },
         { .reg = 0x00009888, .val = 0x0AE90BE1 },
         { .reg = 0x00009888, .val = 0x0CE90FF1 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext411__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext411__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext411__avg_gpu_core_frequency__max,acmgt3__ext411__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1653, 24, NULL,acmgt3__ext411__rt_load_store_cache_read_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1661, 32, NULL,acmgt3__ext411__rt_load_store_cache_write_from_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1499, 40, NULL,acmgt3__ext411__rt_traversal_input_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1555, 48, NULL,acmgt3__ext411__rt_quad_test_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1579, 56, NULL,acmgt3__ext411__rt_request_collision_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1491, 64, NULL,acmgt3__ext411__rt_input_message_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1571, 72, percentage_max_float,acmgt3__ext411__rt_message_stall_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1563, 80, NULL,acmgt3__ext411__rt_transform_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext412_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext412";
   query->symbol_name = "Ext412";
   query->guid = "d9a3534a-4dca-4b28-b8e8-d447017b82a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17857FC0 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x09851000 },
         { .reg = 0x00009888, .val = 0x19894740 },
         { .reg = 0x00009888, .val = 0x1F89023A },
         { .reg = 0x00009888, .val = 0x23896800 },
         { .reg = 0x00009888, .val = 0x25890011 },
         { .reg = 0x00009888, .val = 0x29894740 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x03850B2C },
         { .reg = 0x00009888, .val = 0x0F850154 },
         { .reg = 0x00009888, .val = 0x118505D8 },
         { .reg = 0x00009888, .val = 0x138503CE },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0386AAA0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x078903C1 },
         { .reg = 0x00009888, .val = 0x098907D1 },
         { .reg = 0x00009888, .val = 0x0B890BE1 },
         { .reg = 0x00009888, .val = 0x0D890FF1 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext412__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext412__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext412__avg_gpu_core_frequency__max,acmgt3__ext412__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1654, 24, NULL,acmgt3__ext412__rt_load_store_cache_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1662, 32, NULL,acmgt3__ext412__rt_load_store_cache_write_from_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1500, 40, NULL,acmgt3__ext412__rt_traversal_input_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1556, 48, NULL,acmgt3__ext412__rt_quad_test_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1580, 56, NULL,acmgt3__ext412__rt_request_collision_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1492, 64, NULL,acmgt3__ext412__rt_input_message_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1572, 72, percentage_max_float,acmgt3__ext412__rt_message_stall_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1564, 80, NULL,acmgt3__ext412__rt_transform_ray_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext413_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext413";
   query->symbol_name = "Ext413";
   query->guid = "594a085e-c744-4544-b38b-196e9b52d1b0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17A57FC0 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x09A51000 },
         { .reg = 0x00009888, .val = 0x19A94740 },
         { .reg = 0x00009888, .val = 0x1FA9023A },
         { .reg = 0x00009888, .val = 0x23A96800 },
         { .reg = 0x00009888, .val = 0x25A90011 },
         { .reg = 0x00009888, .val = 0x29A94740 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x01A400FF },
         { .reg = 0x00009888, .val = 0x03A50B2C },
         { .reg = 0x00009888, .val = 0x0FA50154 },
         { .reg = 0x00009888, .val = 0x11A505D8 },
         { .reg = 0x00009888, .val = 0x13A503CE },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A6AAA0 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A903C1 },
         { .reg = 0x00009888, .val = 0x09A907D1 },
         { .reg = 0x00009888, .val = 0x0BA90BE1 },
         { .reg = 0x00009888, .val = 0x0DA90FF1 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FCFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext413__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext413__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext413__avg_gpu_core_frequency__max,acmgt3__ext413__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1655, 24, NULL,acmgt3__ext413__rt_load_store_cache_read_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1663, 32, NULL,acmgt3__ext413__rt_load_store_cache_write_from_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1501, 40, NULL,acmgt3__ext413__rt_traversal_input_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1557, 48, NULL,acmgt3__ext413__rt_quad_test_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1581, 56, NULL,acmgt3__ext413__rt_request_collision_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1493, 64, NULL,acmgt3__ext413__rt_input_message_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1573, 72, percentage_max_float,acmgt3__ext413__rt_message_stall_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1565, 80, NULL,acmgt3__ext413__rt_transform_ray_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext414_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext414";
   query->symbol_name = "Ext414";
   query->guid = "99fd5805-5f5e-48ae-95d1-6cb7d5c09bfb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17C57FC0 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x09C51000 },
         { .reg = 0x00009888, .val = 0x19C94740 },
         { .reg = 0x00009888, .val = 0x1FC9023A },
         { .reg = 0x00009888, .val = 0x23C96800 },
         { .reg = 0x00009888, .val = 0x25C90011 },
         { .reg = 0x00009888, .val = 0x29C94740 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x03C50B2C },
         { .reg = 0x00009888, .val = 0x0FC50154 },
         { .reg = 0x00009888, .val = 0x11C505D8 },
         { .reg = 0x00009888, .val = 0x13C503CE },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C6AAA0 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C903C1 },
         { .reg = 0x00009888, .val = 0x09C907D1 },
         { .reg = 0x00009888, .val = 0x0BC90BE1 },
         { .reg = 0x00009888, .val = 0x0DC90FF1 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FCFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext414__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext414__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext414__avg_gpu_core_frequency__max,acmgt3__ext414__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1656, 24, NULL,acmgt3__ext414__rt_load_store_cache_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1664, 32, NULL,acmgt3__ext414__rt_load_store_cache_write_from_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1502, 40, NULL,acmgt3__ext414__rt_traversal_input_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1558, 48, NULL,acmgt3__ext414__rt_quad_test_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1582, 56, NULL,acmgt3__ext414__rt_request_collision_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1494, 64, NULL,acmgt3__ext414__rt_input_message_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1574, 72, percentage_max_float,acmgt3__ext414__rt_message_stall_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1566, 80, NULL,acmgt3__ext414__rt_transform_ray_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext415_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext415";
   query->symbol_name = "Ext415";
   query->guid = "1be807ab-2f67-45bb-901f-9bb9d805d4a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17E57FC0 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x09E51000 },
         { .reg = 0x00009888, .val = 0x19E94740 },
         { .reg = 0x00009888, .val = 0x1FE9023A },
         { .reg = 0x00009888, .val = 0x23E96800 },
         { .reg = 0x00009888, .val = 0x25E90011 },
         { .reg = 0x00009888, .val = 0x29E94740 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x01E400FF },
         { .reg = 0x00009888, .val = 0x03E50B2C },
         { .reg = 0x00009888, .val = 0x0FE50154 },
         { .reg = 0x00009888, .val = 0x11E505D8 },
         { .reg = 0x00009888, .val = 0x13E503CE },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E6AAA0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E903C1 },
         { .reg = 0x00009888, .val = 0x09E907D1 },
         { .reg = 0x00009888, .val = 0x0BE90BE1 },
         { .reg = 0x00009888, .val = 0x0DE90FF1 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext415__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext415__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext415__avg_gpu_core_frequency__max,acmgt3__ext415__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1657, 24, NULL,acmgt3__ext415__rt_load_store_cache_read_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1665, 32, NULL,acmgt3__ext415__rt_load_store_cache_write_from_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1503, 40, NULL,acmgt3__ext415__rt_traversal_input_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1559, 48, NULL,acmgt3__ext415__rt_quad_test_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1583, 56, NULL,acmgt3__ext415__rt_request_collision_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1495, 64, NULL,acmgt3__ext415__rt_input_message_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1575, 72, percentage_max_float,acmgt3__ext415__rt_message_stall_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1567, 80, NULL,acmgt3__ext415__rt_transform_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext416_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext416";
   query->symbol_name = "Ext416";
   query->guid = "8204f26d-37d5-458f-aac4-e1120b674145";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16857FC0 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x08851000 },
         { .reg = 0x00009888, .val = 0x18894740 },
         { .reg = 0x00009888, .val = 0x1E89023A },
         { .reg = 0x00009888, .val = 0x22896800 },
         { .reg = 0x00009888, .val = 0x24890011 },
         { .reg = 0x00009888, .val = 0x28894740 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x02850B2C },
         { .reg = 0x00009888, .val = 0x0E850154 },
         { .reg = 0x00009888, .val = 0x108505D8 },
         { .reg = 0x00009888, .val = 0x128503CE },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0286AAA0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x068903C1 },
         { .reg = 0x00009888, .val = 0x088907D1 },
         { .reg = 0x00009888, .val = 0x0A890BE1 },
         { .reg = 0x00009888, .val = 0x0C890FF1 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext416__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext416__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext416__avg_gpu_core_frequency__max,acmgt3__ext416__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2823, 24, NULL,acmgt3__ext416__rt_load_store_cache_read_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2824, 32, NULL,acmgt3__ext416__rt_load_store_cache_write_from_message_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2825, 40, NULL,acmgt3__ext416__rt_traversal_input_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2826, 48, NULL,acmgt3__ext416__rt_quad_test_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2827, 56, NULL,acmgt3__ext416__rt_request_collision_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2828, 64, NULL,acmgt3__ext416__rt_input_message_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 2829, 72, percentage_max_float,acmgt3__ext416__rt_message_stall_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2830, 80, NULL,acmgt3__ext416__rt_transform_ray_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext417_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext417";
   query->symbol_name = "Ext417";
   query->guid = "7f38c38f-0f80-4e50-9269-dfc0e08b0660";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16A57FC0 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x08A51000 },
         { .reg = 0x00009888, .val = 0x18A94740 },
         { .reg = 0x00009888, .val = 0x1EA9023A },
         { .reg = 0x00009888, .val = 0x22A96800 },
         { .reg = 0x00009888, .val = 0x24A90011 },
         { .reg = 0x00009888, .val = 0x28A94740 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x00A400FF },
         { .reg = 0x00009888, .val = 0x02A50B2C },
         { .reg = 0x00009888, .val = 0x0EA50154 },
         { .reg = 0x00009888, .val = 0x10A505D8 },
         { .reg = 0x00009888, .val = 0x12A503CE },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A6AAA0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A903C1 },
         { .reg = 0x00009888, .val = 0x08A907D1 },
         { .reg = 0x00009888, .val = 0x0AA90BE1 },
         { .reg = 0x00009888, .val = 0x0CA90FF1 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext417__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext417__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext417__avg_gpu_core_frequency__max,acmgt3__ext417__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2831, 24, NULL,acmgt3__ext417__rt_load_store_cache_read_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2832, 32, NULL,acmgt3__ext417__rt_load_store_cache_write_from_message_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2833, 40, NULL,acmgt3__ext417__rt_traversal_input_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2834, 48, NULL,acmgt3__ext417__rt_quad_test_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2835, 56, NULL,acmgt3__ext417__rt_request_collision_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2836, 64, NULL,acmgt3__ext417__rt_input_message_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 2837, 72, percentage_max_float,acmgt3__ext417__rt_message_stall_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2838, 80, NULL,acmgt3__ext417__rt_transform_ray_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext418_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext418";
   query->symbol_name = "Ext418";
   query->guid = "2654399f-54e6-45ca-931d-1f01c9f8ca06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16C57FC0 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x08C51000 },
         { .reg = 0x00009888, .val = 0x18C94740 },
         { .reg = 0x00009888, .val = 0x1EC9023A },
         { .reg = 0x00009888, .val = 0x22C96800 },
         { .reg = 0x00009888, .val = 0x24C90011 },
         { .reg = 0x00009888, .val = 0x28C94740 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x02C50B2C },
         { .reg = 0x00009888, .val = 0x0EC50154 },
         { .reg = 0x00009888, .val = 0x10C505D8 },
         { .reg = 0x00009888, .val = 0x12C503CE },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C6AAA0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C903C1 },
         { .reg = 0x00009888, .val = 0x08C907D1 },
         { .reg = 0x00009888, .val = 0x0AC90BE1 },
         { .reg = 0x00009888, .val = 0x0CC90FF1 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FCFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext418__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext418__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext418__avg_gpu_core_frequency__max,acmgt3__ext418__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2839, 24, NULL,acmgt3__ext418__rt_load_store_cache_read_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2840, 32, NULL,acmgt3__ext418__rt_load_store_cache_write_from_message_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2841, 40, NULL,acmgt3__ext418__rt_traversal_input_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2842, 48, NULL,acmgt3__ext418__rt_quad_test_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2843, 56, NULL,acmgt3__ext418__rt_request_collision_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2844, 64, NULL,acmgt3__ext418__rt_input_message_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 2845, 72, percentage_max_float,acmgt3__ext418__rt_message_stall_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2846, 80, NULL,acmgt3__ext418__rt_transform_ray_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext419_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext419";
   query->symbol_name = "Ext419";
   query->guid = "8a2b3a4e-791f-4f5a-931d-78e3a6c673bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16E57FC0 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x08E51000 },
         { .reg = 0x00009888, .val = 0x18E94740 },
         { .reg = 0x00009888, .val = 0x1EE9023A },
         { .reg = 0x00009888, .val = 0x22E96800 },
         { .reg = 0x00009888, .val = 0x24E90011 },
         { .reg = 0x00009888, .val = 0x28E94740 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x00E400FF },
         { .reg = 0x00009888, .val = 0x02E50B2C },
         { .reg = 0x00009888, .val = 0x0EE50154 },
         { .reg = 0x00009888, .val = 0x10E505D8 },
         { .reg = 0x00009888, .val = 0x12E503CE },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E6AAA0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E903C1 },
         { .reg = 0x00009888, .val = 0x08E907D1 },
         { .reg = 0x00009888, .val = 0x0AE90BE1 },
         { .reg = 0x00009888, .val = 0x0CE90FF1 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext419__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext419__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext419__avg_gpu_core_frequency__max,acmgt3__ext419__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2847, 24, NULL,acmgt3__ext419__rt_load_store_cache_read_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2848, 32, NULL,acmgt3__ext419__rt_load_store_cache_write_from_message_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2849, 40, NULL,acmgt3__ext419__rt_traversal_input_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2850, 48, NULL,acmgt3__ext419__rt_quad_test_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2851, 56, NULL,acmgt3__ext419__rt_request_collision_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2852, 64, NULL,acmgt3__ext419__rt_input_message_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 2853, 72, percentage_max_float,acmgt3__ext419__rt_message_stall_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2854, 80, NULL,acmgt3__ext419__rt_transform_ray_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext420_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext420";
   query->symbol_name = "Ext420";
   query->guid = "d5d2ec61-a953-487d-9e9f-9e15c80ad7ac";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17857FC0 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x09851000 },
         { .reg = 0x00009888, .val = 0x19894740 },
         { .reg = 0x00009888, .val = 0x1F89023A },
         { .reg = 0x00009888, .val = 0x23896800 },
         { .reg = 0x00009888, .val = 0x25890011 },
         { .reg = 0x00009888, .val = 0x29894740 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x03850B2C },
         { .reg = 0x00009888, .val = 0x0F850154 },
         { .reg = 0x00009888, .val = 0x118505D8 },
         { .reg = 0x00009888, .val = 0x138503CE },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0386AAA0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x078903C1 },
         { .reg = 0x00009888, .val = 0x098907D1 },
         { .reg = 0x00009888, .val = 0x0B890BE1 },
         { .reg = 0x00009888, .val = 0x0D890FF1 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext420__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext420__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext420__avg_gpu_core_frequency__max,acmgt3__ext420__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2855, 24, NULL,acmgt3__ext420__rt_load_store_cache_read_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2856, 32, NULL,acmgt3__ext420__rt_load_store_cache_write_from_message_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2857, 40, NULL,acmgt3__ext420__rt_traversal_input_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2858, 48, NULL,acmgt3__ext420__rt_quad_test_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2859, 56, NULL,acmgt3__ext420__rt_request_collision_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2860, 64, NULL,acmgt3__ext420__rt_input_message_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 2861, 72, percentage_max_float,acmgt3__ext420__rt_message_stall_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2862, 80, NULL,acmgt3__ext420__rt_transform_ray_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext421_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext421";
   query->symbol_name = "Ext421";
   query->guid = "581a1d88-3759-4cf4-ba59-4c25377cdece";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17A57FC0 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x09A51000 },
         { .reg = 0x00009888, .val = 0x19A94740 },
         { .reg = 0x00009888, .val = 0x1FA9023A },
         { .reg = 0x00009888, .val = 0x23A96800 },
         { .reg = 0x00009888, .val = 0x25A90011 },
         { .reg = 0x00009888, .val = 0x29A94740 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x01A400FF },
         { .reg = 0x00009888, .val = 0x03A50B2C },
         { .reg = 0x00009888, .val = 0x0FA50154 },
         { .reg = 0x00009888, .val = 0x11A505D8 },
         { .reg = 0x00009888, .val = 0x13A503CE },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A6AAA0 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A903C1 },
         { .reg = 0x00009888, .val = 0x09A907D1 },
         { .reg = 0x00009888, .val = 0x0BA90BE1 },
         { .reg = 0x00009888, .val = 0x0DA90FF1 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FCFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext421__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext421__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext421__avg_gpu_core_frequency__max,acmgt3__ext421__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2863, 24, NULL,acmgt3__ext421__rt_load_store_cache_read_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2864, 32, NULL,acmgt3__ext421__rt_load_store_cache_write_from_message_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2865, 40, NULL,acmgt3__ext421__rt_traversal_input_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2866, 48, NULL,acmgt3__ext421__rt_quad_test_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2867, 56, NULL,acmgt3__ext421__rt_request_collision_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2868, 64, NULL,acmgt3__ext421__rt_input_message_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 2869, 72, percentage_max_float,acmgt3__ext421__rt_message_stall_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2870, 80, NULL,acmgt3__ext421__rt_transform_ray_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext422_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext422";
   query->symbol_name = "Ext422";
   query->guid = "316fefa3-9d16-4eaa-9904-15b2203ec95c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17C57FC0 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x09C51000 },
         { .reg = 0x00009888, .val = 0x19C94740 },
         { .reg = 0x00009888, .val = 0x1FC9023A },
         { .reg = 0x00009888, .val = 0x23C96800 },
         { .reg = 0x00009888, .val = 0x25C90011 },
         { .reg = 0x00009888, .val = 0x29C94740 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x03C50B2C },
         { .reg = 0x00009888, .val = 0x0FC50154 },
         { .reg = 0x00009888, .val = 0x11C505D8 },
         { .reg = 0x00009888, .val = 0x13C503CE },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C6AAA0 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C903C1 },
         { .reg = 0x00009888, .val = 0x09C907D1 },
         { .reg = 0x00009888, .val = 0x0BC90BE1 },
         { .reg = 0x00009888, .val = 0x0DC90FF1 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FCFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext422__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext422__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext422__avg_gpu_core_frequency__max,acmgt3__ext422__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2871, 24, NULL,acmgt3__ext422__rt_load_store_cache_read_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2872, 32, NULL,acmgt3__ext422__rt_load_store_cache_write_from_message_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2873, 40, NULL,acmgt3__ext422__rt_traversal_input_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2874, 48, NULL,acmgt3__ext422__rt_quad_test_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2875, 56, NULL,acmgt3__ext422__rt_request_collision_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2876, 64, NULL,acmgt3__ext422__rt_input_message_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 2877, 72, percentage_max_float,acmgt3__ext422__rt_message_stall_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2878, 80, NULL,acmgt3__ext422__rt_transform_ray_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext423_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext423";
   query->symbol_name = "Ext423";
   query->guid = "6e0a01cd-c537-45e1-aedd-3e181b7a7c01";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17E57FC0 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x09E51000 },
         { .reg = 0x00009888, .val = 0x19E94740 },
         { .reg = 0x00009888, .val = 0x1FE9023A },
         { .reg = 0x00009888, .val = 0x23E96800 },
         { .reg = 0x00009888, .val = 0x25E90011 },
         { .reg = 0x00009888, .val = 0x29E94740 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x01E400FF },
         { .reg = 0x00009888, .val = 0x03E50B2C },
         { .reg = 0x00009888, .val = 0x0FE50154 },
         { .reg = 0x00009888, .val = 0x11E505D8 },
         { .reg = 0x00009888, .val = 0x13E503CE },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E6AAA0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E903C1 },
         { .reg = 0x00009888, .val = 0x09E907D1 },
         { .reg = 0x00009888, .val = 0x0BE90BE1 },
         { .reg = 0x00009888, .val = 0x0DE90FF1 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext423__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext423__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext423__avg_gpu_core_frequency__max,acmgt3__ext423__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2879, 24, NULL,acmgt3__ext423__rt_load_store_cache_read_message_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2880, 32, NULL,acmgt3__ext423__rt_load_store_cache_write_from_message_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2881, 40, NULL,acmgt3__ext423__rt_traversal_input_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2882, 48, NULL,acmgt3__ext423__rt_quad_test_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2883, 56, NULL,acmgt3__ext423__rt_request_collision_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2884, 64, NULL,acmgt3__ext423__rt_input_message_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 2885, 72, percentage_max_float,acmgt3__ext423__rt_message_stall_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2886, 80, NULL,acmgt3__ext423__rt_transform_ray_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext424_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext424";
   query->symbol_name = "Ext424";
   query->guid = "9141c2fe-b37b-4f53-a292-a09a3a54dbd4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16857FC0 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x08851000 },
         { .reg = 0x00009888, .val = 0x18894740 },
         { .reg = 0x00009888, .val = 0x1E89023A },
         { .reg = 0x00009888, .val = 0x22896800 },
         { .reg = 0x00009888, .val = 0x24890011 },
         { .reg = 0x00009888, .val = 0x28894740 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x02850B2C },
         { .reg = 0x00009888, .val = 0x0E850154 },
         { .reg = 0x00009888, .val = 0x108505D8 },
         { .reg = 0x00009888, .val = 0x128503CE },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0286AAA0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x068903C1 },
         { .reg = 0x00009888, .val = 0x088907D1 },
         { .reg = 0x00009888, .val = 0x0A890BE1 },
         { .reg = 0x00009888, .val = 0x0C890FF1 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext424__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext424__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext424__avg_gpu_core_frequency__max,acmgt3__ext424__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4493, 24, NULL,acmgt3__ext424__rt_load_store_cache_read_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4494, 32, NULL,acmgt3__ext424__rt_load_store_cache_write_from_message_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4495, 40, NULL,acmgt3__ext424__rt_traversal_input_ray_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4496, 48, NULL,acmgt3__ext424__rt_quad_test_ray_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4497, 56, NULL,acmgt3__ext424__rt_request_collision_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4498, 64, NULL,acmgt3__ext424__rt_input_message_ray_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4499, 72, percentage_max_float,acmgt3__ext424__rt_message_stall_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4500, 80, NULL,acmgt3__ext424__rt_transform_ray_count_xecore16__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext425_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext425";
   query->symbol_name = "Ext425";
   query->guid = "b655bffc-0284-4ad5-847e-caf886a651bc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16A57FC0 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x08A51000 },
         { .reg = 0x00009888, .val = 0x18A94740 },
         { .reg = 0x00009888, .val = 0x1EA9023A },
         { .reg = 0x00009888, .val = 0x22A96800 },
         { .reg = 0x00009888, .val = 0x24A90011 },
         { .reg = 0x00009888, .val = 0x28A94740 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x00A400FF },
         { .reg = 0x00009888, .val = 0x02A50B2C },
         { .reg = 0x00009888, .val = 0x0EA50154 },
         { .reg = 0x00009888, .val = 0x10A505D8 },
         { .reg = 0x00009888, .val = 0x12A503CE },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A6AAA0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A903C1 },
         { .reg = 0x00009888, .val = 0x08A907D1 },
         { .reg = 0x00009888, .val = 0x0AA90BE1 },
         { .reg = 0x00009888, .val = 0x0CA90FF1 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext425__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext425__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext425__avg_gpu_core_frequency__max,acmgt3__ext425__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4501, 24, NULL,acmgt3__ext425__rt_load_store_cache_read_message_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4502, 32, NULL,acmgt3__ext425__rt_load_store_cache_write_from_message_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4503, 40, NULL,acmgt3__ext425__rt_traversal_input_ray_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4504, 48, NULL,acmgt3__ext425__rt_quad_test_ray_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4505, 56, NULL,acmgt3__ext425__rt_request_collision_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4506, 64, NULL,acmgt3__ext425__rt_input_message_ray_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4507, 72, percentage_max_float,acmgt3__ext425__rt_message_stall_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4508, 80, NULL,acmgt3__ext425__rt_transform_ray_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext426_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext426";
   query->symbol_name = "Ext426";
   query->guid = "5aca86ba-4035-4c53-af84-25152bf169e3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16C57FC0 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x08C51000 },
         { .reg = 0x00009888, .val = 0x18C94740 },
         { .reg = 0x00009888, .val = 0x1EC9023A },
         { .reg = 0x00009888, .val = 0x22C96800 },
         { .reg = 0x00009888, .val = 0x24C90011 },
         { .reg = 0x00009888, .val = 0x28C94740 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x02C50B2C },
         { .reg = 0x00009888, .val = 0x0EC50154 },
         { .reg = 0x00009888, .val = 0x10C505D8 },
         { .reg = 0x00009888, .val = 0x12C503CE },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C6AAA0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C903C1 },
         { .reg = 0x00009888, .val = 0x08C907D1 },
         { .reg = 0x00009888, .val = 0x0AC90BE1 },
         { .reg = 0x00009888, .val = 0x0CC90FF1 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FCFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext426__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext426__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext426__avg_gpu_core_frequency__max,acmgt3__ext426__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4509, 24, NULL,acmgt3__ext426__rt_load_store_cache_read_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4510, 32, NULL,acmgt3__ext426__rt_load_store_cache_write_from_message_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4511, 40, NULL,acmgt3__ext426__rt_traversal_input_ray_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4512, 48, NULL,acmgt3__ext426__rt_quad_test_ray_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4513, 56, NULL,acmgt3__ext426__rt_request_collision_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4514, 64, NULL,acmgt3__ext426__rt_input_message_ray_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4515, 72, percentage_max_float,acmgt3__ext426__rt_message_stall_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4516, 80, NULL,acmgt3__ext426__rt_transform_ray_count_xecore18__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext427_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext427";
   query->symbol_name = "Ext427";
   query->guid = "0ab07bde-21c8-443c-b0b2-0ab740168d29";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16E57FC0 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x08E51000 },
         { .reg = 0x00009888, .val = 0x18E94740 },
         { .reg = 0x00009888, .val = 0x1EE9023A },
         { .reg = 0x00009888, .val = 0x22E96800 },
         { .reg = 0x00009888, .val = 0x24E90011 },
         { .reg = 0x00009888, .val = 0x28E94740 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x00E400FF },
         { .reg = 0x00009888, .val = 0x02E50B2C },
         { .reg = 0x00009888, .val = 0x0EE50154 },
         { .reg = 0x00009888, .val = 0x10E505D8 },
         { .reg = 0x00009888, .val = 0x12E503CE },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E6AAA0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E903C1 },
         { .reg = 0x00009888, .val = 0x08E907D1 },
         { .reg = 0x00009888, .val = 0x0AE90BE1 },
         { .reg = 0x00009888, .val = 0x0CE90FF1 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext427__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext427__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext427__avg_gpu_core_frequency__max,acmgt3__ext427__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4517, 24, NULL,acmgt3__ext427__rt_load_store_cache_read_message_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4518, 32, NULL,acmgt3__ext427__rt_load_store_cache_write_from_message_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4519, 40, NULL,acmgt3__ext427__rt_traversal_input_ray_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4520, 48, NULL,acmgt3__ext427__rt_quad_test_ray_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4521, 56, NULL,acmgt3__ext427__rt_request_collision_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4522, 64, NULL,acmgt3__ext427__rt_input_message_ray_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4523, 72, percentage_max_float,acmgt3__ext427__rt_message_stall_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4524, 80, NULL,acmgt3__ext427__rt_transform_ray_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext428_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext428";
   query->symbol_name = "Ext428";
   query->guid = "62a24a66-2325-40b3-a945-6ef37508674a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17857FC0 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x09851000 },
         { .reg = 0x00009888, .val = 0x19894740 },
         { .reg = 0x00009888, .val = 0x1F89023A },
         { .reg = 0x00009888, .val = 0x23896800 },
         { .reg = 0x00009888, .val = 0x25890011 },
         { .reg = 0x00009888, .val = 0x29894740 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x03850B2C },
         { .reg = 0x00009888, .val = 0x0F850154 },
         { .reg = 0x00009888, .val = 0x118505D8 },
         { .reg = 0x00009888, .val = 0x138503CE },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0386AAA0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x078903C1 },
         { .reg = 0x00009888, .val = 0x098907D1 },
         { .reg = 0x00009888, .val = 0x0B890BE1 },
         { .reg = 0x00009888, .val = 0x0D890FF1 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext428__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext428__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext428__avg_gpu_core_frequency__max,acmgt3__ext428__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4525, 24, NULL,acmgt3__ext428__rt_load_store_cache_read_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4526, 32, NULL,acmgt3__ext428__rt_load_store_cache_write_from_message_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4527, 40, NULL,acmgt3__ext428__rt_traversal_input_ray_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4528, 48, NULL,acmgt3__ext428__rt_quad_test_ray_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4529, 56, NULL,acmgt3__ext428__rt_request_collision_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4530, 64, NULL,acmgt3__ext428__rt_input_message_ray_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4531, 72, percentage_max_float,acmgt3__ext428__rt_message_stall_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4532, 80, NULL,acmgt3__ext428__rt_transform_ray_count_xecore20__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext429_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext429";
   query->symbol_name = "Ext429";
   query->guid = "47acaafe-6b68-4d1d-a674-8d94ed118606";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17A57FC0 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x09A51000 },
         { .reg = 0x00009888, .val = 0x19A94740 },
         { .reg = 0x00009888, .val = 0x1FA9023A },
         { .reg = 0x00009888, .val = 0x23A96800 },
         { .reg = 0x00009888, .val = 0x25A90011 },
         { .reg = 0x00009888, .val = 0x29A94740 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x01A400FF },
         { .reg = 0x00009888, .val = 0x03A50B2C },
         { .reg = 0x00009888, .val = 0x0FA50154 },
         { .reg = 0x00009888, .val = 0x11A505D8 },
         { .reg = 0x00009888, .val = 0x13A503CE },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A6AAA0 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A903C1 },
         { .reg = 0x00009888, .val = 0x09A907D1 },
         { .reg = 0x00009888, .val = 0x0BA90BE1 },
         { .reg = 0x00009888, .val = 0x0DA90FF1 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FCFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext429__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext429__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext429__avg_gpu_core_frequency__max,acmgt3__ext429__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4533, 24, NULL,acmgt3__ext429__rt_load_store_cache_read_message_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4534, 32, NULL,acmgt3__ext429__rt_load_store_cache_write_from_message_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4535, 40, NULL,acmgt3__ext429__rt_traversal_input_ray_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4536, 48, NULL,acmgt3__ext429__rt_quad_test_ray_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4537, 56, NULL,acmgt3__ext429__rt_request_collision_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4538, 64, NULL,acmgt3__ext429__rt_input_message_ray_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 4539, 72, percentage_max_float,acmgt3__ext429__rt_message_stall_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4540, 80, NULL,acmgt3__ext429__rt_transform_ray_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext430_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext430";
   query->symbol_name = "Ext430";
   query->guid = "72cb7918-7248-437c-ad7f-a0b2b8815148";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17C57FC0 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x09C51000 },
         { .reg = 0x00009888, .val = 0x19C94740 },
         { .reg = 0x00009888, .val = 0x1FC9023A },
         { .reg = 0x00009888, .val = 0x23C96800 },
         { .reg = 0x00009888, .val = 0x25C90011 },
         { .reg = 0x00009888, .val = 0x29C94740 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x03C50B2C },
         { .reg = 0x00009888, .val = 0x0FC50154 },
         { .reg = 0x00009888, .val = 0x11C505D8 },
         { .reg = 0x00009888, .val = 0x13C503CE },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C6AAA0 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C903C1 },
         { .reg = 0x00009888, .val = 0x09C907D1 },
         { .reg = 0x00009888, .val = 0x0BC90BE1 },
         { .reg = 0x00009888, .val = 0x0DC90FF1 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FCFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext430__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext430__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext430__avg_gpu_core_frequency__max,acmgt3__ext430__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4541, 24, NULL,acmgt3__ext430__rt_load_store_cache_read_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4542, 32, NULL,acmgt3__ext430__rt_load_store_cache_write_from_message_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4543, 40, NULL,acmgt3__ext430__rt_traversal_input_ray_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4544, 48, NULL,acmgt3__ext430__rt_quad_test_ray_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4545, 56, NULL,acmgt3__ext430__rt_request_collision_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4546, 64, NULL,acmgt3__ext430__rt_input_message_ray_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 4547, 72, percentage_max_float,acmgt3__ext430__rt_message_stall_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4548, 80, NULL,acmgt3__ext430__rt_transform_ray_count_xecore22__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext431_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext431";
   query->symbol_name = "Ext431";
   query->guid = "0ccfdef6-3cdb-485c-9aba-d3e0040e305e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17E57FC0 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x09E51000 },
         { .reg = 0x00009888, .val = 0x19E94740 },
         { .reg = 0x00009888, .val = 0x1FE9023A },
         { .reg = 0x00009888, .val = 0x23E96800 },
         { .reg = 0x00009888, .val = 0x25E90011 },
         { .reg = 0x00009888, .val = 0x29E94740 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x01E400FF },
         { .reg = 0x00009888, .val = 0x03E50B2C },
         { .reg = 0x00009888, .val = 0x0FE50154 },
         { .reg = 0x00009888, .val = 0x11E505D8 },
         { .reg = 0x00009888, .val = 0x13E503CE },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E6AAA0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E903C1 },
         { .reg = 0x00009888, .val = 0x09E907D1 },
         { .reg = 0x00009888, .val = 0x0BE90BE1 },
         { .reg = 0x00009888, .val = 0x0DE90FF1 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext431__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext431__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext431__avg_gpu_core_frequency__max,acmgt3__ext431__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4549, 24, NULL,acmgt3__ext431__rt_load_store_cache_read_message_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4550, 32, NULL,acmgt3__ext431__rt_load_store_cache_write_from_message_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4551, 40, NULL,acmgt3__ext431__rt_traversal_input_ray_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4552, 48, NULL,acmgt3__ext431__rt_quad_test_ray_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4553, 56, NULL,acmgt3__ext431__rt_request_collision_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4554, 64, NULL,acmgt3__ext431__rt_input_message_ray_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 4555, 72, percentage_max_float,acmgt3__ext431__rt_message_stall_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4556, 80, NULL,acmgt3__ext431__rt_transform_ray_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext432_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext432";
   query->symbol_name = "Ext432";
   query->guid = "e9b7707a-c96e-45dd-b513-fae7d7468ddb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16857FC0 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x08851000 },
         { .reg = 0x00009888, .val = 0x18894740 },
         { .reg = 0x00009888, .val = 0x1E89023A },
         { .reg = 0x00009888, .val = 0x22896800 },
         { .reg = 0x00009888, .val = 0x24890011 },
         { .reg = 0x00009888, .val = 0x28894740 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x008400FF },
         { .reg = 0x00009888, .val = 0x02850B2C },
         { .reg = 0x00009888, .val = 0x0E850154 },
         { .reg = 0x00009888, .val = 0x108505D8 },
         { .reg = 0x00009888, .val = 0x128503CE },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x0286AAA0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x068903C1 },
         { .reg = 0x00009888, .val = 0x088907D1 },
         { .reg = 0x00009888, .val = 0x0A890BE1 },
         { .reg = 0x00009888, .val = 0x0C890FF1 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext432__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext432__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext432__avg_gpu_core_frequency__max,acmgt3__ext432__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4557, 24, NULL,acmgt3__ext432__rt_load_store_cache_read_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4558, 32, NULL,acmgt3__ext432__rt_load_store_cache_write_from_message_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4559, 40, NULL,acmgt3__ext432__rt_traversal_input_ray_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4560, 48, NULL,acmgt3__ext432__rt_quad_test_ray_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4561, 56, NULL,acmgt3__ext432__rt_request_collision_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4562, 64, NULL,acmgt3__ext432__rt_input_message_ray_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 4563, 72, percentage_max_float,acmgt3__ext432__rt_message_stall_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4564, 80, NULL,acmgt3__ext432__rt_transform_ray_count_xecore24__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext433_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext433";
   query->symbol_name = "Ext433";
   query->guid = "4ecad344-9bda-4c3e-b310-284a9d249028";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16A57FC0 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x08A51000 },
         { .reg = 0x00009888, .val = 0x18A94740 },
         { .reg = 0x00009888, .val = 0x1EA9023A },
         { .reg = 0x00009888, .val = 0x22A96800 },
         { .reg = 0x00009888, .val = 0x24A90011 },
         { .reg = 0x00009888, .val = 0x28A94740 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x00A400FF },
         { .reg = 0x00009888, .val = 0x02A50B2C },
         { .reg = 0x00009888, .val = 0x0EA50154 },
         { .reg = 0x00009888, .val = 0x10A505D8 },
         { .reg = 0x00009888, .val = 0x12A503CE },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A6AAA0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A903C1 },
         { .reg = 0x00009888, .val = 0x08A907D1 },
         { .reg = 0x00009888, .val = 0x0AA90BE1 },
         { .reg = 0x00009888, .val = 0x0CA90FF1 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext433__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext433__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext433__avg_gpu_core_frequency__max,acmgt3__ext433__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4565, 24, NULL,acmgt3__ext433__rt_load_store_cache_read_message_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4566, 32, NULL,acmgt3__ext433__rt_load_store_cache_write_from_message_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4567, 40, NULL,acmgt3__ext433__rt_traversal_input_ray_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4568, 48, NULL,acmgt3__ext433__rt_quad_test_ray_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4569, 56, NULL,acmgt3__ext433__rt_request_collision_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4570, 64, NULL,acmgt3__ext433__rt_input_message_ray_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 4571, 72, percentage_max_float,acmgt3__ext433__rt_message_stall_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4572, 80, NULL,acmgt3__ext433__rt_transform_ray_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext434_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext434";
   query->symbol_name = "Ext434";
   query->guid = "ddb99956-0871-42f4-8b6b-dbca21a726ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16C57FC0 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x08C51000 },
         { .reg = 0x00009888, .val = 0x18C94740 },
         { .reg = 0x00009888, .val = 0x1EC9023A },
         { .reg = 0x00009888, .val = 0x22C96800 },
         { .reg = 0x00009888, .val = 0x24C90011 },
         { .reg = 0x00009888, .val = 0x28C94740 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x00C400FF },
         { .reg = 0x00009888, .val = 0x02C50B2C },
         { .reg = 0x00009888, .val = 0x0EC50154 },
         { .reg = 0x00009888, .val = 0x10C505D8 },
         { .reg = 0x00009888, .val = 0x12C503CE },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C6AAA0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C903C1 },
         { .reg = 0x00009888, .val = 0x08C907D1 },
         { .reg = 0x00009888, .val = 0x0AC90BE1 },
         { .reg = 0x00009888, .val = 0x0CC90FF1 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FCFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext434__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext434__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext434__avg_gpu_core_frequency__max,acmgt3__ext434__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4573, 24, NULL,acmgt3__ext434__rt_load_store_cache_read_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4574, 32, NULL,acmgt3__ext434__rt_load_store_cache_write_from_message_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4575, 40, NULL,acmgt3__ext434__rt_traversal_input_ray_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4576, 48, NULL,acmgt3__ext434__rt_quad_test_ray_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4577, 56, NULL,acmgt3__ext434__rt_request_collision_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4578, 64, NULL,acmgt3__ext434__rt_input_message_ray_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 4579, 72, percentage_max_float,acmgt3__ext434__rt_message_stall_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4580, 80, NULL,acmgt3__ext434__rt_transform_ray_count_xecore26__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext435_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext435";
   query->symbol_name = "Ext435";
   query->guid = "a992c151-134d-4959-879e-2c5b8dc2b98a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16E57FC0 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x08E51000 },
         { .reg = 0x00009888, .val = 0x18E94740 },
         { .reg = 0x00009888, .val = 0x1EE9023A },
         { .reg = 0x00009888, .val = 0x22E96800 },
         { .reg = 0x00009888, .val = 0x24E90011 },
         { .reg = 0x00009888, .val = 0x28E94740 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x00E400FF },
         { .reg = 0x00009888, .val = 0x02E50B2C },
         { .reg = 0x00009888, .val = 0x0EE50154 },
         { .reg = 0x00009888, .val = 0x10E505D8 },
         { .reg = 0x00009888, .val = 0x12E503CE },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E6AAA0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E903C1 },
         { .reg = 0x00009888, .val = 0x08E907D1 },
         { .reg = 0x00009888, .val = 0x0AE90BE1 },
         { .reg = 0x00009888, .val = 0x0CE90FF1 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FCFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext435__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext435__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext435__avg_gpu_core_frequency__max,acmgt3__ext435__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4581, 24, NULL,acmgt3__ext435__rt_load_store_cache_read_message_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4582, 32, NULL,acmgt3__ext435__rt_load_store_cache_write_from_message_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4583, 40, NULL,acmgt3__ext435__rt_traversal_input_ray_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4584, 48, NULL,acmgt3__ext435__rt_quad_test_ray_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4585, 56, NULL,acmgt3__ext435__rt_request_collision_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4586, 64, NULL,acmgt3__ext435__rt_input_message_ray_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 4587, 72, percentage_max_float,acmgt3__ext435__rt_message_stall_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4588, 80, NULL,acmgt3__ext435__rt_transform_ray_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext436_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext436";
   query->symbol_name = "Ext436";
   query->guid = "05453f6f-3850-4412-9dc5-aacc57dc23ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17857FC0 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x09851000 },
         { .reg = 0x00009888, .val = 0x19894740 },
         { .reg = 0x00009888, .val = 0x1F89023A },
         { .reg = 0x00009888, .val = 0x23896800 },
         { .reg = 0x00009888, .val = 0x25890011 },
         { .reg = 0x00009888, .val = 0x29894740 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x018400FF },
         { .reg = 0x00009888, .val = 0x03850B2C },
         { .reg = 0x00009888, .val = 0x0F850154 },
         { .reg = 0x00009888, .val = 0x118505D8 },
         { .reg = 0x00009888, .val = 0x138503CE },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x0386AAA0 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x078903C1 },
         { .reg = 0x00009888, .val = 0x098907D1 },
         { .reg = 0x00009888, .val = 0x0B890BE1 },
         { .reg = 0x00009888, .val = 0x0D890FF1 },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext436__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext436__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext436__avg_gpu_core_frequency__max,acmgt3__ext436__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4589, 24, NULL,acmgt3__ext436__rt_load_store_cache_read_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4590, 32, NULL,acmgt3__ext436__rt_load_store_cache_write_from_message_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4591, 40, NULL,acmgt3__ext436__rt_traversal_input_ray_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4592, 48, NULL,acmgt3__ext436__rt_quad_test_ray_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4593, 56, NULL,acmgt3__ext436__rt_request_collision_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4594, 64, NULL,acmgt3__ext436__rt_input_message_ray_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 4595, 72, percentage_max_float,acmgt3__ext436__rt_message_stall_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4596, 80, NULL,acmgt3__ext436__rt_transform_ray_count_xecore28__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext437_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext437";
   query->symbol_name = "Ext437";
   query->guid = "6a863ebb-4f0a-4a6f-81a0-979a0a972ce1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17A57FC0 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x09A51000 },
         { .reg = 0x00009888, .val = 0x19A94740 },
         { .reg = 0x00009888, .val = 0x1FA9023A },
         { .reg = 0x00009888, .val = 0x23A96800 },
         { .reg = 0x00009888, .val = 0x25A90011 },
         { .reg = 0x00009888, .val = 0x29A94740 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x01A400FF },
         { .reg = 0x00009888, .val = 0x03A50B2C },
         { .reg = 0x00009888, .val = 0x0FA50154 },
         { .reg = 0x00009888, .val = 0x11A505D8 },
         { .reg = 0x00009888, .val = 0x13A503CE },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A6AAA0 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A903C1 },
         { .reg = 0x00009888, .val = 0x09A907D1 },
         { .reg = 0x00009888, .val = 0x0BA90BE1 },
         { .reg = 0x00009888, .val = 0x0DA90FF1 },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FCFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext437__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext437__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext437__avg_gpu_core_frequency__max,acmgt3__ext437__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4597, 24, NULL,acmgt3__ext437__rt_load_store_cache_read_message_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4598, 32, NULL,acmgt3__ext437__rt_load_store_cache_write_from_message_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4599, 40, NULL,acmgt3__ext437__rt_traversal_input_ray_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4600, 48, NULL,acmgt3__ext437__rt_quad_test_ray_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4601, 56, NULL,acmgt3__ext437__rt_request_collision_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4602, 64, NULL,acmgt3__ext437__rt_input_message_ray_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 4603, 72, percentage_max_float,acmgt3__ext437__rt_message_stall_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4604, 80, NULL,acmgt3__ext437__rt_transform_ray_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext438_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext438";
   query->symbol_name = "Ext438";
   query->guid = "5b95cc2f-5942-4fe3-be28-8940db9b99bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17C57FC0 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x09C51000 },
         { .reg = 0x00009888, .val = 0x19C94740 },
         { .reg = 0x00009888, .val = 0x1FC9023A },
         { .reg = 0x00009888, .val = 0x23C96800 },
         { .reg = 0x00009888, .val = 0x25C90011 },
         { .reg = 0x00009888, .val = 0x29C94740 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x01C400FF },
         { .reg = 0x00009888, .val = 0x03C50B2C },
         { .reg = 0x00009888, .val = 0x0FC50154 },
         { .reg = 0x00009888, .val = 0x11C505D8 },
         { .reg = 0x00009888, .val = 0x13C503CE },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C6AAA0 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C903C1 },
         { .reg = 0x00009888, .val = 0x09C907D1 },
         { .reg = 0x00009888, .val = 0x0BC90BE1 },
         { .reg = 0x00009888, .val = 0x0DC90FF1 },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FCFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext438__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext438__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext438__avg_gpu_core_frequency__max,acmgt3__ext438__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4605, 24, NULL,acmgt3__ext438__rt_load_store_cache_read_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4606, 32, NULL,acmgt3__ext438__rt_load_store_cache_write_from_message_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4607, 40, NULL,acmgt3__ext438__rt_traversal_input_ray_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4608, 48, NULL,acmgt3__ext438__rt_quad_test_ray_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4609, 56, NULL,acmgt3__ext438__rt_request_collision_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4610, 64, NULL,acmgt3__ext438__rt_input_message_ray_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 4611, 72, percentage_max_float,acmgt3__ext438__rt_message_stall_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4612, 80, NULL,acmgt3__ext438__rt_transform_ray_count_xecore30__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext439_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext439";
   query->symbol_name = "Ext439";
   query->guid = "1474625b-322c-439d-90e3-53c245a07f97";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17E57FC0 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x09E51000 },
         { .reg = 0x00009888, .val = 0x19E94740 },
         { .reg = 0x00009888, .val = 0x1FE9023A },
         { .reg = 0x00009888, .val = 0x23E96800 },
         { .reg = 0x00009888, .val = 0x25E90011 },
         { .reg = 0x00009888, .val = 0x29E94740 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x01E400FF },
         { .reg = 0x00009888, .val = 0x03E50B2C },
         { .reg = 0x00009888, .val = 0x0FE50154 },
         { .reg = 0x00009888, .val = 0x11E505D8 },
         { .reg = 0x00009888, .val = 0x13E503CE },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E6AAA0 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E903C1 },
         { .reg = 0x00009888, .val = 0x09E907D1 },
         { .reg = 0x00009888, .val = 0x0BE90BE1 },
         { .reg = 0x00009888, .val = 0x0DE90FF1 },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FCFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FCFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAA0 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x16031000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FCFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x0000000A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000022 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000082 },
         { .reg = 0x0000D974, .val = 0x0000FFCF },
         { .reg = 0x0000D978, .val = 0x00000202 },
         { .reg = 0x0000D97C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext439__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext439__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext439__avg_gpu_core_frequency__max,acmgt3__ext439__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4613, 24, NULL,acmgt3__ext439__rt_load_store_cache_read_message_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4614, 32, NULL,acmgt3__ext439__rt_load_store_cache_write_from_message_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4615, 40, NULL,acmgt3__ext439__rt_traversal_input_ray_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4616, 48, NULL,acmgt3__ext439__rt_quad_test_ray_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4617, 56, NULL,acmgt3__ext439__rt_request_collision_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4618, 64, NULL,acmgt3__ext439__rt_input_message_ray_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 4619, 72, percentage_max_float,acmgt3__ext439__rt_message_stall_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4620, 80, NULL,acmgt3__ext439__rt_transform_ray_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext440_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext440";
   query->symbol_name = "Ext440";
   query->guid = "9112768a-99fd-4861-b1b2-ca7eb9a46228";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E8545E0 },
         { .reg = 0x00009888, .val = 0x1EA545E0 },
         { .reg = 0x00009888, .val = 0x1EC545E0 },
         { .reg = 0x00009888, .val = 0x1EE545E0 },
         { .reg = 0x00009888, .val = 0x0485C70E },
         { .reg = 0x00009888, .val = 0x06850E78 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50C70 },
         { .reg = 0x00009888, .val = 0x0AA50E78 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50C70 },
         { .reg = 0x00009888, .val = 0x0EC50E78 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50C70 },
         { .reg = 0x00009888, .val = 0x12E50E78 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext440__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext440__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext440__avg_gpu_core_frequency__max,acmgt3__ext440__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1544, 24, NULL,acmgt3__ext440__rt_traversal_output_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1545, 32, NULL,acmgt3__ext440__rt_traversal_output_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1546, 40, NULL,acmgt3__ext440__rt_traversal_output_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1547, 48, NULL,acmgt3__ext440__rt_traversal_output_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext441_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext441";
   query->symbol_name = "Ext441";
   query->guid = "f2579b7f-2747-49fd-b5ed-ef10662ce62a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1F8545E0 },
         { .reg = 0x00009888, .val = 0x1FA545E0 },
         { .reg = 0x00009888, .val = 0x1FC545E0 },
         { .reg = 0x00009888, .val = 0x1FE545E0 },
         { .reg = 0x00009888, .val = 0x0585C70E },
         { .reg = 0x00009888, .val = 0x07850E78 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50C70 },
         { .reg = 0x00009888, .val = 0x0BA50E78 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50C70 },
         { .reg = 0x00009888, .val = 0x0FC50E78 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50C70 },
         { .reg = 0x00009888, .val = 0x13E50E78 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext441__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext441__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext441__avg_gpu_core_frequency__max,acmgt3__ext441__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1548, 24, NULL,acmgt3__ext441__rt_traversal_output_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1549, 32, NULL,acmgt3__ext441__rt_traversal_output_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1550, 40, NULL,acmgt3__ext441__rt_traversal_output_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1551, 48, NULL,acmgt3__ext441__rt_traversal_output_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext442_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext442";
   query->symbol_name = "Ext442";
   query->guid = "f572f1c9-3f61-48e8-9bd1-d58a8cd60520";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8545E0 },
         { .reg = 0x00009888, .val = 0x1EA545E0 },
         { .reg = 0x00009888, .val = 0x1EC545E0 },
         { .reg = 0x00009888, .val = 0x1EE545E0 },
         { .reg = 0x00009888, .val = 0x0485C70E },
         { .reg = 0x00009888, .val = 0x06850E78 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50C70 },
         { .reg = 0x00009888, .val = 0x0AA50E78 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50C70 },
         { .reg = 0x00009888, .val = 0x0EC50E78 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50C70 },
         { .reg = 0x00009888, .val = 0x12E50E78 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext442__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext442__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext442__avg_gpu_core_frequency__max,acmgt3__ext442__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2927, 24, NULL,acmgt3__ext442__rt_traversal_output_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2928, 32, NULL,acmgt3__ext442__rt_traversal_output_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2929, 40, NULL,acmgt3__ext442__rt_traversal_output_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2930, 48, NULL,acmgt3__ext442__rt_traversal_output_ray_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext443_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext443";
   query->symbol_name = "Ext443";
   query->guid = "4c923c96-134d-4802-a61f-9c3e50af7e9f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8545E0 },
         { .reg = 0x00009888, .val = 0x1FA545E0 },
         { .reg = 0x00009888, .val = 0x1FC545E0 },
         { .reg = 0x00009888, .val = 0x1FE545E0 },
         { .reg = 0x00009888, .val = 0x0585C70E },
         { .reg = 0x00009888, .val = 0x07850E78 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50C70 },
         { .reg = 0x00009888, .val = 0x0BA50E78 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50C70 },
         { .reg = 0x00009888, .val = 0x0FC50E78 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50C70 },
         { .reg = 0x00009888, .val = 0x13E50E78 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext443__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext443__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext443__avg_gpu_core_frequency__max,acmgt3__ext443__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2931, 24, NULL,acmgt3__ext443__rt_traversal_output_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2932, 32, NULL,acmgt3__ext443__rt_traversal_output_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2933, 40, NULL,acmgt3__ext443__rt_traversal_output_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2934, 48, NULL,acmgt3__ext443__rt_traversal_output_ray_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext444_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext444";
   query->symbol_name = "Ext444";
   query->guid = "c89197d6-8bce-4479-9961-2c50e8ffbcf7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8545E0 },
         { .reg = 0x00009888, .val = 0x1EA545E0 },
         { .reg = 0x00009888, .val = 0x1EC545E0 },
         { .reg = 0x00009888, .val = 0x1EE545E0 },
         { .reg = 0x00009888, .val = 0x0485C70E },
         { .reg = 0x00009888, .val = 0x06850E78 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50C70 },
         { .reg = 0x00009888, .val = 0x0AA50E78 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50C70 },
         { .reg = 0x00009888, .val = 0x0EC50E78 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50C70 },
         { .reg = 0x00009888, .val = 0x12E50E78 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext444__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext444__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext444__avg_gpu_core_frequency__max,acmgt3__ext444__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4621, 24, NULL,acmgt3__ext444__rt_traversal_output_ray_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4622, 32, NULL,acmgt3__ext444__rt_traversal_output_ray_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4623, 40, NULL,acmgt3__ext444__rt_traversal_output_ray_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4624, 48, NULL,acmgt3__ext444__rt_traversal_output_ray_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext445_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext445";
   query->symbol_name = "Ext445";
   query->guid = "87885a48-5d45-47e8-81b3-176db423b454";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8545E0 },
         { .reg = 0x00009888, .val = 0x1FA545E0 },
         { .reg = 0x00009888, .val = 0x1FC545E0 },
         { .reg = 0x00009888, .val = 0x1FE545E0 },
         { .reg = 0x00009888, .val = 0x0585C70E },
         { .reg = 0x00009888, .val = 0x07850E78 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50C70 },
         { .reg = 0x00009888, .val = 0x0BA50E78 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50C70 },
         { .reg = 0x00009888, .val = 0x0FC50E78 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50C70 },
         { .reg = 0x00009888, .val = 0x13E50E78 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext445__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext445__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext445__avg_gpu_core_frequency__max,acmgt3__ext445__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4625, 24, NULL,acmgt3__ext445__rt_traversal_output_ray_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4626, 32, NULL,acmgt3__ext445__rt_traversal_output_ray_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4627, 40, NULL,acmgt3__ext445__rt_traversal_output_ray_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4628, 48, NULL,acmgt3__ext445__rt_traversal_output_ray_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext446_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext446";
   query->symbol_name = "Ext446";
   query->guid = "323e04f8-e194-4032-bd1f-159b0131f1bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E8545E0 },
         { .reg = 0x00009888, .val = 0x1EA545E0 },
         { .reg = 0x00009888, .val = 0x1EC545E0 },
         { .reg = 0x00009888, .val = 0x1EE545E0 },
         { .reg = 0x00009888, .val = 0x0485C70E },
         { .reg = 0x00009888, .val = 0x06850E78 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50C70 },
         { .reg = 0x00009888, .val = 0x0AA50E78 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50C70 },
         { .reg = 0x00009888, .val = 0x0EC50E78 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50C70 },
         { .reg = 0x00009888, .val = 0x12E50E78 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext446__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext446__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext446__avg_gpu_core_frequency__max,acmgt3__ext446__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4629, 24, NULL,acmgt3__ext446__rt_traversal_output_ray_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4630, 32, NULL,acmgt3__ext446__rt_traversal_output_ray_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4631, 40, NULL,acmgt3__ext446__rt_traversal_output_ray_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4632, 48, NULL,acmgt3__ext446__rt_traversal_output_ray_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext447_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext447";
   query->symbol_name = "Ext447";
   query->guid = "1999b632-cd36-49ec-a888-0a458f9f5673";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1F8545E0 },
         { .reg = 0x00009888, .val = 0x1FA545E0 },
         { .reg = 0x00009888, .val = 0x1FC545E0 },
         { .reg = 0x00009888, .val = 0x1FE545E0 },
         { .reg = 0x00009888, .val = 0x0585C70E },
         { .reg = 0x00009888, .val = 0x07850E78 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50C70 },
         { .reg = 0x00009888, .val = 0x0BA50E78 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50C70 },
         { .reg = 0x00009888, .val = 0x0FC50E78 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50C70 },
         { .reg = 0x00009888, .val = 0x13E50E78 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext447__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext447__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext447__avg_gpu_core_frequency__max,acmgt3__ext447__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4633, 24, NULL,acmgt3__ext447__rt_traversal_output_ray_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4634, 32, NULL,acmgt3__ext447__rt_traversal_output_ray_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4635, 40, NULL,acmgt3__ext447__rt_traversal_output_ray_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4636, 48, NULL,acmgt3__ext447__rt_traversal_output_ray_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext448_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext448";
   query->symbol_name = "Ext448";
   query->guid = "71487a9a-9e3f-4bee-95b9-cd42969e4278";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D37E },
         { .reg = 0x00009888, .val = 0x06850F3F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D37 },
         { .reg = 0x00009888, .val = 0x0AA50F3F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D37 },
         { .reg = 0x00009888, .val = 0x0EC50F3F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D37 },
         { .reg = 0x00009888, .val = 0x12E50F3F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext448__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext448__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext448__avg_gpu_core_frequency__max,acmgt3__ext448__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1520, 24, NULL,acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1521, 32, NULL,acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1522, 40, NULL,acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1523, 48, NULL,acmgt3__ext448__rt_any_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext449_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext449";
   query->symbol_name = "Ext449";
   query->guid = "299dff90-c563-48f4-b1b4-eacf678b6727";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D37E },
         { .reg = 0x00009888, .val = 0x07850F3F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D37 },
         { .reg = 0x00009888, .val = 0x0BA50F3F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D37 },
         { .reg = 0x00009888, .val = 0x0FC50F3F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D37 },
         { .reg = 0x00009888, .val = 0x13E50F3F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext449__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext449__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext449__avg_gpu_core_frequency__max,acmgt3__ext449__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1524, 24, NULL,acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1525, 32, NULL,acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1526, 40, NULL,acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1527, 48, NULL,acmgt3__ext449__rt_any_hit_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext450_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext450";
   query->symbol_name = "Ext450";
   query->guid = "85729a73-d105-4f88-9f85-833961661877";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D37E },
         { .reg = 0x00009888, .val = 0x06850F3F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D37 },
         { .reg = 0x00009888, .val = 0x0AA50F3F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D37 },
         { .reg = 0x00009888, .val = 0x0EC50F3F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D37 },
         { .reg = 0x00009888, .val = 0x12E50F3F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext450__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext450__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext450__avg_gpu_core_frequency__max,acmgt3__ext450__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2935, 24, NULL,acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2936, 32, NULL,acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2937, 40, NULL,acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2938, 48, NULL,acmgt3__ext450__rt_any_hit_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext451_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext451";
   query->symbol_name = "Ext451";
   query->guid = "74df82fd-abc3-4934-8cb5-cc71324c1816";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D37E },
         { .reg = 0x00009888, .val = 0x07850F3F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D37 },
         { .reg = 0x00009888, .val = 0x0BA50F3F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D37 },
         { .reg = 0x00009888, .val = 0x0FC50F3F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D37 },
         { .reg = 0x00009888, .val = 0x13E50F3F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext451__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext451__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext451__avg_gpu_core_frequency__max,acmgt3__ext451__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2939, 24, NULL,acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2940, 32, NULL,acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2941, 40, NULL,acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2942, 48, NULL,acmgt3__ext451__rt_any_hit_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext452_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext452";
   query->symbol_name = "Ext452";
   query->guid = "d1c28b9e-8ce0-4750-bf4b-ec446d4c3916";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D37E },
         { .reg = 0x00009888, .val = 0x06850F3F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D37 },
         { .reg = 0x00009888, .val = 0x0AA50F3F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D37 },
         { .reg = 0x00009888, .val = 0x0EC50F3F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D37 },
         { .reg = 0x00009888, .val = 0x12E50F3F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext452__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext452__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext452__avg_gpu_core_frequency__max,acmgt3__ext452__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4637, 24, NULL,acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4638, 32, NULL,acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4639, 40, NULL,acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4640, 48, NULL,acmgt3__ext452__rt_any_hit_thread_ray_dispatch_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext453_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext453";
   query->symbol_name = "Ext453";
   query->guid = "56876ce8-6162-4812-a5ff-acdf8b896a9c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D37E },
         { .reg = 0x00009888, .val = 0x07850F3F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D37 },
         { .reg = 0x00009888, .val = 0x0BA50F3F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D37 },
         { .reg = 0x00009888, .val = 0x0FC50F3F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D37 },
         { .reg = 0x00009888, .val = 0x13E50F3F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext453__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext453__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext453__avg_gpu_core_frequency__max,acmgt3__ext453__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4641, 24, NULL,acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4642, 32, NULL,acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4643, 40, NULL,acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4644, 48, NULL,acmgt3__ext453__rt_any_hit_thread_ray_dispatch_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext454_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext454";
   query->symbol_name = "Ext454";
   query->guid = "4c84ebed-5683-417b-8b31-d60919bdf00e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D37E },
         { .reg = 0x00009888, .val = 0x06850F3F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D37 },
         { .reg = 0x00009888, .val = 0x0AA50F3F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D37 },
         { .reg = 0x00009888, .val = 0x0EC50F3F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D37 },
         { .reg = 0x00009888, .val = 0x12E50F3F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext454__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext454__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext454__avg_gpu_core_frequency__max,acmgt3__ext454__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4645, 24, NULL,acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4646, 32, NULL,acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4647, 40, NULL,acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4648, 48, NULL,acmgt3__ext454__rt_any_hit_thread_ray_dispatch_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext455_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext455";
   query->symbol_name = "Ext455";
   query->guid = "870f786b-e570-427d-868d-bdead22a485d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D37E },
         { .reg = 0x00009888, .val = 0x07850F3F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D37 },
         { .reg = 0x00009888, .val = 0x0BA50F3F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D37 },
         { .reg = 0x00009888, .val = 0x0FC50F3F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D37 },
         { .reg = 0x00009888, .val = 0x13E50F3F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext455__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext455__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext455__avg_gpu_core_frequency__max,acmgt3__ext455__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4649, 24, NULL,acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4650, 32, NULL,acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4651, 40, NULL,acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4652, 48, NULL,acmgt3__ext455__rt_any_hit_thread_ray_dispatch_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext456_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext456";
   query->symbol_name = "Ext456";
   query->guid = "7385d290-7061-4248-8b13-ac4abe1212d6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CB7E },
         { .reg = 0x00009888, .val = 0x06850EBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CB7 },
         { .reg = 0x00009888, .val = 0x0AA50EBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CB7 },
         { .reg = 0x00009888, .val = 0x0EC50EBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CB7 },
         { .reg = 0x00009888, .val = 0x12E50EBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext456__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext456__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext456__avg_gpu_core_frequency__max,acmgt3__ext456__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1536, 24, NULL,acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1537, 32, NULL,acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1538, 40, NULL,acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1539, 48, NULL,acmgt3__ext456__rt_callable_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext457_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext457";
   query->symbol_name = "Ext457";
   query->guid = "e92a854c-ef93-44fe-a9c9-2e564fd57215";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CB7E },
         { .reg = 0x00009888, .val = 0x07850EBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CB7 },
         { .reg = 0x00009888, .val = 0x0BA50EBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CB7 },
         { .reg = 0x00009888, .val = 0x0FC50EBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CB7 },
         { .reg = 0x00009888, .val = 0x13E50EBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext457__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext457__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext457__avg_gpu_core_frequency__max,acmgt3__ext457__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1540, 24, NULL,acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1541, 32, NULL,acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1542, 40, NULL,acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1543, 48, NULL,acmgt3__ext457__rt_callable_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext458_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext458";
   query->symbol_name = "Ext458";
   query->guid = "0839f197-8c02-4ab5-adee-f26d39d57060";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CB7E },
         { .reg = 0x00009888, .val = 0x06850EBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CB7 },
         { .reg = 0x00009888, .val = 0x0AA50EBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CB7 },
         { .reg = 0x00009888, .val = 0x0EC50EBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CB7 },
         { .reg = 0x00009888, .val = 0x12E50EBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext458__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext458__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext458__avg_gpu_core_frequency__max,acmgt3__ext458__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2943, 24, NULL,acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2944, 32, NULL,acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2945, 40, NULL,acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2946, 48, NULL,acmgt3__ext458__rt_callable_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext459_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext459";
   query->symbol_name = "Ext459";
   query->guid = "b39c926c-557f-42d6-9ab8-3dc749774ca2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CB7E },
         { .reg = 0x00009888, .val = 0x07850EBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CB7 },
         { .reg = 0x00009888, .val = 0x0BA50EBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CB7 },
         { .reg = 0x00009888, .val = 0x0FC50EBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CB7 },
         { .reg = 0x00009888, .val = 0x13E50EBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext459__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext459__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext459__avg_gpu_core_frequency__max,acmgt3__ext459__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2947, 24, NULL,acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2948, 32, NULL,acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2949, 40, NULL,acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2950, 48, NULL,acmgt3__ext459__rt_callable_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext460_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext460";
   query->symbol_name = "Ext460";
   query->guid = "9a7989c1-a520-4785-9aeb-f522bb692de6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CB7E },
         { .reg = 0x00009888, .val = 0x06850EBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CB7 },
         { .reg = 0x00009888, .val = 0x0AA50EBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CB7 },
         { .reg = 0x00009888, .val = 0x0EC50EBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CB7 },
         { .reg = 0x00009888, .val = 0x12E50EBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext460__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext460__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext460__avg_gpu_core_frequency__max,acmgt3__ext460__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4653, 24, NULL,acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4654, 32, NULL,acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4655, 40, NULL,acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4656, 48, NULL,acmgt3__ext460__rt_callable_thread_ray_dispatch_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext461_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext461";
   query->symbol_name = "Ext461";
   query->guid = "6eb94cf4-077d-4d52-89c6-272cb33fd9bc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CB7E },
         { .reg = 0x00009888, .val = 0x07850EBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CB7 },
         { .reg = 0x00009888, .val = 0x0BA50EBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CB7 },
         { .reg = 0x00009888, .val = 0x0FC50EBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CB7 },
         { .reg = 0x00009888, .val = 0x13E50EBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext461__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext461__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext461__avg_gpu_core_frequency__max,acmgt3__ext461__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4657, 24, NULL,acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4658, 32, NULL,acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4659, 40, NULL,acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4660, 48, NULL,acmgt3__ext461__rt_callable_thread_ray_dispatch_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext462_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext462";
   query->symbol_name = "Ext462";
   query->guid = "a50d2370-c6ff-4a53-a6dc-b9523562b371";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CB7E },
         { .reg = 0x00009888, .val = 0x06850EBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CB7 },
         { .reg = 0x00009888, .val = 0x0AA50EBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CB7 },
         { .reg = 0x00009888, .val = 0x0EC50EBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CB7 },
         { .reg = 0x00009888, .val = 0x12E50EBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext462__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext462__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext462__avg_gpu_core_frequency__max,acmgt3__ext462__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4661, 24, NULL,acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4662, 32, NULL,acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4663, 40, NULL,acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4664, 48, NULL,acmgt3__ext462__rt_callable_thread_ray_dispatch_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext463_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext463";
   query->symbol_name = "Ext463";
   query->guid = "b737779b-4652-4892-be0b-aa8764d116ba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CB7E },
         { .reg = 0x00009888, .val = 0x07850EBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CB7 },
         { .reg = 0x00009888, .val = 0x0BA50EBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CB7 },
         { .reg = 0x00009888, .val = 0x0FC50EBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CB7 },
         { .reg = 0x00009888, .val = 0x13E50EBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext463__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext463__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext463__avg_gpu_core_frequency__max,acmgt3__ext463__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4665, 24, NULL,acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4666, 32, NULL,acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4667, 40, NULL,acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4668, 48, NULL,acmgt3__ext463__rt_callable_thread_ray_dispatch_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext464_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext464";
   query->symbol_name = "Ext464";
   query->guid = "447d463d-77e3-4bb4-9f02-7523eefa3549";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D77E },
         { .reg = 0x00009888, .val = 0x06850F7F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D77 },
         { .reg = 0x00009888, .val = 0x0AA50F7F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D77 },
         { .reg = 0x00009888, .val = 0x0EC50F7F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D77 },
         { .reg = 0x00009888, .val = 0x12E50F7F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext464__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext464__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext464__avg_gpu_core_frequency__max,acmgt3__ext464__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1504, 24, NULL,acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1505, 32, NULL,acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1506, 40, NULL,acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1507, 48, NULL,acmgt3__ext464__rt_closest_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext465_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext465";
   query->symbol_name = "Ext465";
   query->guid = "0b0dd8de-3217-4d32-9033-988a7a4a2f59";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D77E },
         { .reg = 0x00009888, .val = 0x07850F7F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D77 },
         { .reg = 0x00009888, .val = 0x0BA50F7F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D77 },
         { .reg = 0x00009888, .val = 0x0FC50F7F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D77 },
         { .reg = 0x00009888, .val = 0x13E50F7F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext465__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext465__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext465__avg_gpu_core_frequency__max,acmgt3__ext465__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1508, 24, NULL,acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1509, 32, NULL,acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1510, 40, NULL,acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1511, 48, NULL,acmgt3__ext465__rt_closest_hit_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext466_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext466";
   query->symbol_name = "Ext466";
   query->guid = "46a09e7c-f9e1-4eba-ac1c-4151dc54d51f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D77E },
         { .reg = 0x00009888, .val = 0x06850F7F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D77 },
         { .reg = 0x00009888, .val = 0x0AA50F7F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D77 },
         { .reg = 0x00009888, .val = 0x0EC50F7F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D77 },
         { .reg = 0x00009888, .val = 0x12E50F7F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext466__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext466__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext466__avg_gpu_core_frequency__max,acmgt3__ext466__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2951, 24, NULL,acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2952, 32, NULL,acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2953, 40, NULL,acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2954, 48, NULL,acmgt3__ext466__rt_closest_hit_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext467_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext467";
   query->symbol_name = "Ext467";
   query->guid = "59c513fe-9984-455b-9b07-5b5f02c36e70";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D77E },
         { .reg = 0x00009888, .val = 0x07850F7F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D77 },
         { .reg = 0x00009888, .val = 0x0BA50F7F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D77 },
         { .reg = 0x00009888, .val = 0x0FC50F7F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D77 },
         { .reg = 0x00009888, .val = 0x13E50F7F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext467__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext467__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext467__avg_gpu_core_frequency__max,acmgt3__ext467__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2955, 24, NULL,acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2956, 32, NULL,acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2957, 40, NULL,acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2958, 48, NULL,acmgt3__ext467__rt_closest_hit_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext468_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext468";
   query->symbol_name = "Ext468";
   query->guid = "aa729499-9f35-436d-91ad-7100098dfd47";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D77E },
         { .reg = 0x00009888, .val = 0x06850F7F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D77 },
         { .reg = 0x00009888, .val = 0x0AA50F7F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D77 },
         { .reg = 0x00009888, .val = 0x0EC50F7F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D77 },
         { .reg = 0x00009888, .val = 0x12E50F7F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext468__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext468__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext468__avg_gpu_core_frequency__max,acmgt3__ext468__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4669, 24, NULL,acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4670, 32, NULL,acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4671, 40, NULL,acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4672, 48, NULL,acmgt3__ext468__rt_closest_hit_thread_ray_dispatch_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext469_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext469";
   query->symbol_name = "Ext469";
   query->guid = "dea127d1-19d5-4298-b9d6-cf4a21be1563";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D77E },
         { .reg = 0x00009888, .val = 0x07850F7F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D77 },
         { .reg = 0x00009888, .val = 0x0BA50F7F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D77 },
         { .reg = 0x00009888, .val = 0x0FC50F7F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D77 },
         { .reg = 0x00009888, .val = 0x13E50F7F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext469__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext469__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext469__avg_gpu_core_frequency__max,acmgt3__ext469__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4673, 24, NULL,acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4674, 32, NULL,acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4675, 40, NULL,acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4676, 48, NULL,acmgt3__ext469__rt_closest_hit_thread_ray_dispatch_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext470_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext470";
   query->symbol_name = "Ext470";
   query->guid = "1dc79687-d7a2-4c2d-b810-0a6d5db141f6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485D77E },
         { .reg = 0x00009888, .val = 0x06850F7F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50D77 },
         { .reg = 0x00009888, .val = 0x0AA50F7F },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50D77 },
         { .reg = 0x00009888, .val = 0x0EC50F7F },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50D77 },
         { .reg = 0x00009888, .val = 0x12E50F7F },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext470__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext470__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext470__avg_gpu_core_frequency__max,acmgt3__ext470__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4677, 24, NULL,acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4678, 32, NULL,acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4679, 40, NULL,acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4680, 48, NULL,acmgt3__ext470__rt_closest_hit_thread_ray_dispatch_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext471_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext471";
   query->symbol_name = "Ext471";
   query->guid = "4487fcbd-dcf6-4f08-9512-1cadbd7f246b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585D77E },
         { .reg = 0x00009888, .val = 0x07850F7F },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50D77 },
         { .reg = 0x00009888, .val = 0x0BA50F7F },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50D77 },
         { .reg = 0x00009888, .val = 0x0FC50F7F },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50D77 },
         { .reg = 0x00009888, .val = 0x13E50F7F },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext471__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext471__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext471__avg_gpu_core_frequency__max,acmgt3__ext471__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4681, 24, NULL,acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4682, 32, NULL,acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4683, 40, NULL,acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4684, 48, NULL,acmgt3__ext471__rt_closest_hit_thread_ray_dispatch_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext472_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext472";
   query->symbol_name = "Ext472";
   query->guid = "641f5e4b-0404-456f-9aca-03154415cd34";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CF7E },
         { .reg = 0x00009888, .val = 0x06850EFF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CF7 },
         { .reg = 0x00009888, .val = 0x0AA50EFF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CF7 },
         { .reg = 0x00009888, .val = 0x0EC50EFF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CF7 },
         { .reg = 0x00009888, .val = 0x12E50EFF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext472__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext472__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext472__avg_gpu_core_frequency__max,acmgt3__ext472__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1528, 24, NULL,acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1529, 32, NULL,acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1530, 40, NULL,acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1531, 48, NULL,acmgt3__ext472__rt_intersection_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext473_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext473";
   query->symbol_name = "Ext473";
   query->guid = "2055dfa1-2b3c-4939-b905-dc3cfc8a5124";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CF7E },
         { .reg = 0x00009888, .val = 0x07850EFF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CF7 },
         { .reg = 0x00009888, .val = 0x0BA50EFF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CF7 },
         { .reg = 0x00009888, .val = 0x0FC50EFF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CF7 },
         { .reg = 0x00009888, .val = 0x13E50EFF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext473__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext473__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext473__avg_gpu_core_frequency__max,acmgt3__ext473__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1532, 24, NULL,acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1533, 32, NULL,acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1534, 40, NULL,acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1535, 48, NULL,acmgt3__ext473__rt_intersection_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext474_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext474";
   query->symbol_name = "Ext474";
   query->guid = "c16b25d4-0460-43ca-a0c0-eb198877b615";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CF7E },
         { .reg = 0x00009888, .val = 0x06850EFF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CF7 },
         { .reg = 0x00009888, .val = 0x0AA50EFF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CF7 },
         { .reg = 0x00009888, .val = 0x0EC50EFF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CF7 },
         { .reg = 0x00009888, .val = 0x12E50EFF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext474__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext474__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext474__avg_gpu_core_frequency__max,acmgt3__ext474__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2959, 24, NULL,acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2960, 32, NULL,acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2961, 40, NULL,acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2962, 48, NULL,acmgt3__ext474__rt_intersection_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext475_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext475";
   query->symbol_name = "Ext475";
   query->guid = "939bce80-8718-4d3d-99ff-7908d07f7ca5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CF7E },
         { .reg = 0x00009888, .val = 0x07850EFF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CF7 },
         { .reg = 0x00009888, .val = 0x0BA50EFF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CF7 },
         { .reg = 0x00009888, .val = 0x0FC50EFF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CF7 },
         { .reg = 0x00009888, .val = 0x13E50EFF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext475__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext475__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext475__avg_gpu_core_frequency__max,acmgt3__ext475__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2963, 24, NULL,acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2964, 32, NULL,acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2965, 40, NULL,acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2966, 48, NULL,acmgt3__ext475__rt_intersection_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext476_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext476";
   query->symbol_name = "Ext476";
   query->guid = "d7cce1dc-00c2-4548-a0cd-469134c446b5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CF7E },
         { .reg = 0x00009888, .val = 0x06850EFF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CF7 },
         { .reg = 0x00009888, .val = 0x0AA50EFF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CF7 },
         { .reg = 0x00009888, .val = 0x0EC50EFF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CF7 },
         { .reg = 0x00009888, .val = 0x12E50EFF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext476__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext476__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext476__avg_gpu_core_frequency__max,acmgt3__ext476__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4685, 24, NULL,acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4686, 32, NULL,acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4687, 40, NULL,acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4688, 48, NULL,acmgt3__ext476__rt_intersection_thread_ray_dispatch_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext477_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext477";
   query->symbol_name = "Ext477";
   query->guid = "c939c362-8ff8-4c4c-857f-c429c61dbaee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CF7E },
         { .reg = 0x00009888, .val = 0x07850EFF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CF7 },
         { .reg = 0x00009888, .val = 0x0BA50EFF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CF7 },
         { .reg = 0x00009888, .val = 0x0FC50EFF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CF7 },
         { .reg = 0x00009888, .val = 0x13E50EFF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext477__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext477__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext477__avg_gpu_core_frequency__max,acmgt3__ext477__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4689, 24, NULL,acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4690, 32, NULL,acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4691, 40, NULL,acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4692, 48, NULL,acmgt3__ext477__rt_intersection_thread_ray_dispatch_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext478_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext478";
   query->symbol_name = "Ext478";
   query->guid = "59ec69a0-17fb-4d3a-b303-8463a4631464";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485CF7E },
         { .reg = 0x00009888, .val = 0x06850EFF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50CF7 },
         { .reg = 0x00009888, .val = 0x0AA50EFF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50CF7 },
         { .reg = 0x00009888, .val = 0x0EC50EFF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50CF7 },
         { .reg = 0x00009888, .val = 0x12E50EFF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext478__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext478__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext478__avg_gpu_core_frequency__max,acmgt3__ext478__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4693, 24, NULL,acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4694, 32, NULL,acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4695, 40, NULL,acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4696, 48, NULL,acmgt3__ext478__rt_intersection_thread_ray_dispatch_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext479_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext479";
   query->symbol_name = "Ext479";
   query->guid = "8e1b82ed-be18-45ae-88e5-2e3dfe96935f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585CF7E },
         { .reg = 0x00009888, .val = 0x07850EFF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50CF7 },
         { .reg = 0x00009888, .val = 0x0BA50EFF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50CF7 },
         { .reg = 0x00009888, .val = 0x0FC50EFF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50CF7 },
         { .reg = 0x00009888, .val = 0x13E50EFF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext479__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext479__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext479__avg_gpu_core_frequency__max,acmgt3__ext479__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4697, 24, NULL,acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4698, 32, NULL,acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4699, 40, NULL,acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4700, 48, NULL,acmgt3__ext479__rt_intersection_thread_ray_dispatch_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext480_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext480";
   query->symbol_name = "Ext480";
   query->guid = "c4e0c25a-5e43-4238-a7c9-6cca88251495";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485DB7E },
         { .reg = 0x00009888, .val = 0x06850FBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50DB7 },
         { .reg = 0x00009888, .val = 0x0AA50FBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50DB7 },
         { .reg = 0x00009888, .val = 0x0EC50FBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50DB7 },
         { .reg = 0x00009888, .val = 0x12E50FBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext480__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext480__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext480__avg_gpu_core_frequency__max,acmgt3__ext480__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1512, 24, NULL,acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1513, 32, NULL,acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1514, 40, NULL,acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1515, 48, NULL,acmgt3__ext480__rt_miss_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext481_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext481";
   query->symbol_name = "Ext481";
   query->guid = "d70cd6f5-4ec0-4645-9654-c619926928d3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585DB7E },
         { .reg = 0x00009888, .val = 0x07850FBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50DB7 },
         { .reg = 0x00009888, .val = 0x0BA50FBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50DB7 },
         { .reg = 0x00009888, .val = 0x0FC50FBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50DB7 },
         { .reg = 0x00009888, .val = 0x13E50FBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext481__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext481__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext481__avg_gpu_core_frequency__max,acmgt3__ext481__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1516, 24, NULL,acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1517, 32, NULL,acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1518, 40, NULL,acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1519, 48, NULL,acmgt3__ext481__rt_miss_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext482_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext482";
   query->symbol_name = "Ext482";
   query->guid = "d7028d09-39d0-4009-996f-a4b193ee726a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485DB7E },
         { .reg = 0x00009888, .val = 0x06850FBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50DB7 },
         { .reg = 0x00009888, .val = 0x0AA50FBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50DB7 },
         { .reg = 0x00009888, .val = 0x0EC50FBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50DB7 },
         { .reg = 0x00009888, .val = 0x12E50FBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext482__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext482__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext482__avg_gpu_core_frequency__max,acmgt3__ext482__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2967, 24, NULL,acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2968, 32, NULL,acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2969, 40, NULL,acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2970, 48, NULL,acmgt3__ext482__rt_miss_thread_ray_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext483_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext483";
   query->symbol_name = "Ext483";
   query->guid = "096dd150-0f36-4af1-a2e3-2a309d19ff11";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585DB7E },
         { .reg = 0x00009888, .val = 0x07850FBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50DB7 },
         { .reg = 0x00009888, .val = 0x0BA50FBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50DB7 },
         { .reg = 0x00009888, .val = 0x0FC50FBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50DB7 },
         { .reg = 0x00009888, .val = 0x13E50FBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext483__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext483__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext483__avg_gpu_core_frequency__max,acmgt3__ext483__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2971, 24, NULL,acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2972, 32, NULL,acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2973, 40, NULL,acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2974, 48, NULL,acmgt3__ext483__rt_miss_thread_ray_dispatch_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext484_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext484";
   query->symbol_name = "Ext484";
   query->guid = "a3d45e15-66d1-44f4-8e1d-a0c131cf0c20";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485DB7E },
         { .reg = 0x00009888, .val = 0x06850FBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50DB7 },
         { .reg = 0x00009888, .val = 0x0AA50FBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50DB7 },
         { .reg = 0x00009888, .val = 0x0EC50FBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50DB7 },
         { .reg = 0x00009888, .val = 0x12E50FBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext484__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext484__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext484__avg_gpu_core_frequency__max,acmgt3__ext484__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 4701, 24, NULL,acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 4702, 32, NULL,acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 4703, 40, NULL,acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 4704, 48, NULL,acmgt3__ext484__rt_miss_thread_ray_dispatch_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext485_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext485";
   query->symbol_name = "Ext485";
   query->guid = "26fe4473-14e3-4ec4-825b-edec00c9c60e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585DB7E },
         { .reg = 0x00009888, .val = 0x07850FBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50DB7 },
         { .reg = 0x00009888, .val = 0x0BA50FBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50DB7 },
         { .reg = 0x00009888, .val = 0x0FC50FBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50DB7 },
         { .reg = 0x00009888, .val = 0x13E50FBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext485__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext485__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext485__avg_gpu_core_frequency__max,acmgt3__ext485__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 4705, 24, NULL,acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 4706, 32, NULL,acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 4707, 40, NULL,acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 4708, 48, NULL,acmgt3__ext485__rt_miss_thread_ray_dispatch_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext486_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext486";
   query->symbol_name = "Ext486";
   query->guid = "5743595a-ce3d-4942-b5e1-60f90bfe6d15";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1E8520A0 },
         { .reg = 0x00009888, .val = 0x1EA520A0 },
         { .reg = 0x00009888, .val = 0x1EC520A0 },
         { .reg = 0x00009888, .val = 0x1EE520A0 },
         { .reg = 0x00009888, .val = 0x0485DB7E },
         { .reg = 0x00009888, .val = 0x06850FBF },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x008600AA },
         { .reg = 0x00009888, .val = 0x04A5000E },
         { .reg = 0x00009888, .val = 0x08A50DB7 },
         { .reg = 0x00009888, .val = 0x0AA50FBF },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AA00 },
         { .reg = 0x00009888, .val = 0x04C5000E },
         { .reg = 0x00009888, .val = 0x0CC50DB7 },
         { .reg = 0x00009888, .val = 0x0EC50FBF },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C600AA },
         { .reg = 0x00009888, .val = 0x04E5000E },
         { .reg = 0x00009888, .val = 0x10E50DB7 },
         { .reg = 0x00009888, .val = 0x12E50FBF },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext486__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext486__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext486__avg_gpu_core_frequency__max,acmgt3__ext486__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 4709, 24, NULL,acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 4710, 32, NULL,acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 4711, 40, NULL,acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 4712, 48, NULL,acmgt3__ext486__rt_miss_thread_ray_dispatch_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext487_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext487";
   query->symbol_name = "Ext487";
   query->guid = "bcce765d-4327-4ce9-8dc4-beae0d4c8738";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1F8520A0 },
         { .reg = 0x00009888, .val = 0x1FA520A0 },
         { .reg = 0x00009888, .val = 0x1FC520A0 },
         { .reg = 0x00009888, .val = 0x1FE520A0 },
         { .reg = 0x00009888, .val = 0x0585DB7E },
         { .reg = 0x00009888, .val = 0x07850FBF },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x018600AA },
         { .reg = 0x00009888, .val = 0x05A5000E },
         { .reg = 0x00009888, .val = 0x09A50DB7 },
         { .reg = 0x00009888, .val = 0x0BA50FBF },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AA00 },
         { .reg = 0x00009888, .val = 0x05C5000E },
         { .reg = 0x00009888, .val = 0x0DC50DB7 },
         { .reg = 0x00009888, .val = 0x0FC50FBF },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C600AA },
         { .reg = 0x00009888, .val = 0x05E5000E },
         { .reg = 0x00009888, .val = 0x11E50DB7 },
         { .reg = 0x00009888, .val = 0x13E50FBF },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext487__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext487__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext487__avg_gpu_core_frequency__max,acmgt3__ext487__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 4713, 24, NULL,acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 4714, 32, NULL,acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 4715, 40, NULL,acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 4716, 48, NULL,acmgt3__ext487__rt_miss_thread_ray_dispatch_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext488_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext488";
   query->symbol_name = "Ext488";
   query->guid = "075a4845-117c-4d77-b2b2-b7184a875516";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x100B5500 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x060B0150 },
         { .reg = 0x00009888, .val = 0x120B0493 },
         { .reg = 0x00009888, .val = 0x140B0411 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext488__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext488__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext488__avg_gpu_core_frequency__max,acmgt3__ext488__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1431, 24, NULL,acmgt3__ext488__early_depth_stencil_test_fail_np_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1432, 32, NULL,acmgt3__ext488__early_depth_stencil_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext489_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext489";
   query->symbol_name = "Ext489";
   query->guid = "4a9f4ce9-4ca3-4bbe-ac73-5f4299841575";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x100C5500 },
         { .reg = 0x00009888, .val = 0x00070002 },
         { .reg = 0x00009888, .val = 0x0207AA80 },
         { .reg = 0x00009888, .val = 0x0009F801 },
         { .reg = 0x00009888, .val = 0x000A0002 },
         { .reg = 0x00009888, .val = 0x020AAA80 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x060C0150 },
         { .reg = 0x00009888, .val = 0x120C0493 },
         { .reg = 0x00009888, .val = 0x140C0411 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext489__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext489__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext489__avg_gpu_core_frequency__max,acmgt3__ext489__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1433, 24, NULL,acmgt3__ext489__early_depth_stencil_test_fail_np_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1434, 32, NULL,acmgt3__ext489__early_depth_stencil_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext490_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext490";
   query->symbol_name = "Ext490";
   query->guid = "f24a588d-b6e3-411c-a4ba-7fe5ce65bb18";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x110B5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01080003 },
         { .reg = 0x00009888, .val = 0x0308FFC0 },
         { .reg = 0x00009888, .val = 0x010A0001 },
         { .reg = 0x00009888, .val = 0x030A5540 },
         { .reg = 0x00009888, .val = 0x0101F801 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x070B0150 },
         { .reg = 0x00009888, .val = 0x130B0493 },
         { .reg = 0x00009888, .val = 0x150B0411 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext490__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext490__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext490__avg_gpu_core_frequency__max,acmgt3__ext490__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1435, 24, NULL,acmgt3__ext490__early_depth_stencil_test_fail_np_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1436, 32, NULL,acmgt3__ext490__early_depth_stencil_test_fail_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext491_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext491";
   query->symbol_name = "Ext491";
   query->guid = "70b12fa6-060d-4c67-971b-1c5c6b4fd058";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x110C5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0307AA80 },
         { .reg = 0x00009888, .val = 0x0109F801 },
         { .reg = 0x00009888, .val = 0x010A0002 },
         { .reg = 0x00009888, .val = 0x030AAA80 },
         { .reg = 0x00009888, .val = 0x0102F801 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x070C0150 },
         { .reg = 0x00009888, .val = 0x130C0493 },
         { .reg = 0x00009888, .val = 0x150C0411 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext491__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext491__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext491__avg_gpu_core_frequency__max,acmgt3__ext491__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1437, 24, NULL,acmgt3__ext491__early_depth_stencil_test_fail_np_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1438, 32, NULL,acmgt3__ext491__early_depth_stencil_test_fail_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext492_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext492";
   query->symbol_name = "Ext492";
   query->guid = "0a0b3e8f-9f83-4a85-a594-dd6fb87dc2ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x100B5500 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x060B0150 },
         { .reg = 0x00009888, .val = 0x120B0493 },
         { .reg = 0x00009888, .val = 0x140B0411 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext492__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext492__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext492__avg_gpu_core_frequency__max,acmgt3__ext492__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2403, 24, NULL,acmgt3__ext492__early_depth_stencil_test_fail_np_zpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2404, 32, NULL,acmgt3__ext492__early_depth_stencil_test_fail_p_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext493_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext493";
   query->symbol_name = "Ext493";
   query->guid = "413ee32f-ea00-431f-b325-39bb65fa8a82";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x100C5500 },
         { .reg = 0x00009888, .val = 0x00070002 },
         { .reg = 0x00009888, .val = 0x0207AA80 },
         { .reg = 0x00009888, .val = 0x0009F801 },
         { .reg = 0x00009888, .val = 0x000A0002 },
         { .reg = 0x00009888, .val = 0x020AAA80 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x060C0150 },
         { .reg = 0x00009888, .val = 0x120C0493 },
         { .reg = 0x00009888, .val = 0x140C0411 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext493__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext493__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext493__avg_gpu_core_frequency__max,acmgt3__ext493__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2405, 24, NULL,acmgt3__ext493__early_depth_stencil_test_fail_np_zpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2406, 32, NULL,acmgt3__ext493__early_depth_stencil_test_fail_p_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext494_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext494";
   query->symbol_name = "Ext494";
   query->guid = "7a411505-9241-4b5e-b609-5c4788bbcb6c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x110B5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01080003 },
         { .reg = 0x00009888, .val = 0x0308FFC0 },
         { .reg = 0x00009888, .val = 0x010A0001 },
         { .reg = 0x00009888, .val = 0x030A5540 },
         { .reg = 0x00009888, .val = 0x0101F801 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x070B0150 },
         { .reg = 0x00009888, .val = 0x130B0493 },
         { .reg = 0x00009888, .val = 0x150B0411 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext494__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext494__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext494__avg_gpu_core_frequency__max,acmgt3__ext494__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2407, 24, NULL,acmgt3__ext494__early_depth_stencil_test_fail_np_zpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2408, 32, NULL,acmgt3__ext494__early_depth_stencil_test_fail_p_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext495_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext495";
   query->symbol_name = "Ext495";
   query->guid = "6db60455-95d8-4fe1-8205-194b741b7f9f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x110C5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0307AA80 },
         { .reg = 0x00009888, .val = 0x0109F801 },
         { .reg = 0x00009888, .val = 0x010A0002 },
         { .reg = 0x00009888, .val = 0x030AAA80 },
         { .reg = 0x00009888, .val = 0x0102F801 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x070C0150 },
         { .reg = 0x00009888, .val = 0x130C0493 },
         { .reg = 0x00009888, .val = 0x150C0411 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext495__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext495__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext495__avg_gpu_core_frequency__max,acmgt3__ext495__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2409, 24, NULL,acmgt3__ext495__early_depth_stencil_test_fail_np_zpipe7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2410, 32, NULL,acmgt3__ext495__early_depth_stencil_test_fail_p_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext496_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext496";
   query->symbol_name = "Ext496";
   query->guid = "2b445bfb-5e26-4638-9831-6d3108343565";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x100B5500 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x060B0150 },
         { .reg = 0x00009888, .val = 0x120B0493 },
         { .reg = 0x00009888, .val = 0x140B0411 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext496__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext496__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext496__avg_gpu_core_frequency__max,acmgt3__ext496__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4717, 24, NULL,acmgt3__ext496__early_depth_stencil_test_fail_np_zpipe8__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4718, 32, NULL,acmgt3__ext496__early_depth_stencil_test_fail_p_zpipe8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext497_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext497";
   query->symbol_name = "Ext497";
   query->guid = "5f3eb4c5-fc54-471b-9f82-54de40bcbc96";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x100C5500 },
         { .reg = 0x00009888, .val = 0x00070002 },
         { .reg = 0x00009888, .val = 0x0207AA80 },
         { .reg = 0x00009888, .val = 0x0009F801 },
         { .reg = 0x00009888, .val = 0x000A0002 },
         { .reg = 0x00009888, .val = 0x020AAA80 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x060C0150 },
         { .reg = 0x00009888, .val = 0x120C0493 },
         { .reg = 0x00009888, .val = 0x140C0411 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext497__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext497__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext497__avg_gpu_core_frequency__max,acmgt3__ext497__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4719, 24, NULL,acmgt3__ext497__early_depth_stencil_test_fail_np_zpipe9__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4720, 32, NULL,acmgt3__ext497__early_depth_stencil_test_fail_p_zpipe9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext498_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext498";
   query->symbol_name = "Ext498";
   query->guid = "8ab9e563-9c33-4b0f-adde-029bd2cd484c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x110B5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01080003 },
         { .reg = 0x00009888, .val = 0x0308FFC0 },
         { .reg = 0x00009888, .val = 0x010A0001 },
         { .reg = 0x00009888, .val = 0x030A5540 },
         { .reg = 0x00009888, .val = 0x0101F801 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x070B0150 },
         { .reg = 0x00009888, .val = 0x130B0493 },
         { .reg = 0x00009888, .val = 0x150B0411 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext498__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext498__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext498__avg_gpu_core_frequency__max,acmgt3__ext498__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4721, 24, NULL,acmgt3__ext498__early_depth_stencil_test_fail_np_zpipe10__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4722, 32, NULL,acmgt3__ext498__early_depth_stencil_test_fail_p_zpipe10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext499_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext499";
   query->symbol_name = "Ext499";
   query->guid = "2d96310e-89ce-4f66-b558-0b253531b58f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x110C5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0307AA80 },
         { .reg = 0x00009888, .val = 0x0109F801 },
         { .reg = 0x00009888, .val = 0x010A0002 },
         { .reg = 0x00009888, .val = 0x030AAA80 },
         { .reg = 0x00009888, .val = 0x0102F801 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x070C0150 },
         { .reg = 0x00009888, .val = 0x130C0493 },
         { .reg = 0x00009888, .val = 0x150C0411 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext499__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext499__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext499__avg_gpu_core_frequency__max,acmgt3__ext499__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4723, 24, NULL,acmgt3__ext499__early_depth_stencil_test_fail_np_zpipe11__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4724, 32, NULL,acmgt3__ext499__early_depth_stencil_test_fail_p_zpipe11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext500_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext500";
   query->symbol_name = "Ext500";
   query->guid = "a9c29325-cfab-4d4b-be96-75c69b8ce57f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x100B5500 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x060B0150 },
         { .reg = 0x00009888, .val = 0x120B0493 },
         { .reg = 0x00009888, .val = 0x140B0411 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext500__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext500__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext500__avg_gpu_core_frequency__max,acmgt3__ext500__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4725, 24, NULL,acmgt3__ext500__early_depth_stencil_test_fail_np_zpipe12__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4726, 32, NULL,acmgt3__ext500__early_depth_stencil_test_fail_p_zpipe12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext501_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext501";
   query->symbol_name = "Ext501";
   query->guid = "262f0b30-997e-4ee1-85e6-6d6647a17611";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x100C5500 },
         { .reg = 0x00009888, .val = 0x00070002 },
         { .reg = 0x00009888, .val = 0x0207AA80 },
         { .reg = 0x00009888, .val = 0x0009F801 },
         { .reg = 0x00009888, .val = 0x000A0002 },
         { .reg = 0x00009888, .val = 0x020AAA80 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x060C0150 },
         { .reg = 0x00009888, .val = 0x120C0493 },
         { .reg = 0x00009888, .val = 0x140C0411 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext501__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext501__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext501__avg_gpu_core_frequency__max,acmgt3__ext501__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4727, 24, NULL,acmgt3__ext501__early_depth_stencil_test_fail_np_zpipe13__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4728, 32, NULL,acmgt3__ext501__early_depth_stencil_test_fail_p_zpipe13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext502_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext502";
   query->symbol_name = "Ext502";
   query->guid = "07b710c4-da24-46fa-bd26-5e761066024a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x110B5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01080003 },
         { .reg = 0x00009888, .val = 0x0308FFC0 },
         { .reg = 0x00009888, .val = 0x010A0001 },
         { .reg = 0x00009888, .val = 0x030A5540 },
         { .reg = 0x00009888, .val = 0x0101F801 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x070B0150 },
         { .reg = 0x00009888, .val = 0x130B0493 },
         { .reg = 0x00009888, .val = 0x150B0411 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext502__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext502__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext502__avg_gpu_core_frequency__max,acmgt3__ext502__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4729, 24, NULL,acmgt3__ext502__early_depth_stencil_test_fail_np_zpipe14__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4730, 32, NULL,acmgt3__ext502__early_depth_stencil_test_fail_p_zpipe14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext503_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext503";
   query->symbol_name = "Ext503";
   query->guid = "0b727214-7830-4c26-a3e4-7dd5c446083f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x110C5500 },
         { .reg = 0x00009888, .val = 0x0003F801 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x000A0001 },
         { .reg = 0x00009888, .val = 0x020A5540 },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020BAA80 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0307AA80 },
         { .reg = 0x00009888, .val = 0x0109F801 },
         { .reg = 0x00009888, .val = 0x010A0002 },
         { .reg = 0x00009888, .val = 0x030AAA80 },
         { .reg = 0x00009888, .val = 0x0102F801 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x070C0150 },
         { .reg = 0x00009888, .val = 0x130C0493 },
         { .reg = 0x00009888, .val = 0x150C0411 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F801 },
         { .reg = 0x00009888, .val = 0x00020001 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x00050001 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00080002 },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext503__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext503__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext503__avg_gpu_core_frequency__max,acmgt3__ext503__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4731, 24, NULL,acmgt3__ext503__early_depth_stencil_test_fail_np_zpipe15__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4732, 32, NULL,acmgt3__ext503__early_depth_stencil_test_fail_p_zpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext504_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext504";
   query->symbol_name = "Ext504";
   query->guid = "1864f248-2169-4ae4-aae4-a16c2ddd0a86";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext504__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext504__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext504__avg_gpu_core_frequency__max,acmgt3__ext504__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1439, 24, NULL,acmgt3__ext504__hiz_depth_test_ambig_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext505_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext505";
   query->symbol_name = "Ext505";
   query->guid = "8e644770-9bee-40ab-8a9b-359bf441e5d5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext505__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext505__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext505__avg_gpu_core_frequency__max,acmgt3__ext505__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1440, 24, NULL,acmgt3__ext505__hiz_depth_test_ambig_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext506_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext506";
   query->symbol_name = "Ext506";
   query->guid = "2c979a9c-11b5-4d43-bf6b-6f89a4e93dd6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext506__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext506__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext506__avg_gpu_core_frequency__max,acmgt3__ext506__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1441, 24, NULL,acmgt3__ext506__hiz_depth_test_ambig_np_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext507_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext507";
   query->symbol_name = "Ext507";
   query->guid = "2f346753-30a5-4c6c-b6bb-5b5605a42cb1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext507__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext507__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext507__avg_gpu_core_frequency__max,acmgt3__ext507__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1442, 24, NULL,acmgt3__ext507__hiz_depth_test_ambig_np_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext508_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext508";
   query->symbol_name = "Ext508";
   query->guid = "4e07923a-091a-49c7-b823-b63e43c6fa19";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext508__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext508__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext508__avg_gpu_core_frequency__max,acmgt3__ext508__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2411, 24, NULL,acmgt3__ext508__hiz_depth_test_ambig_np_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext509_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext509";
   query->symbol_name = "Ext509";
   query->guid = "58350136-7dcd-4d4a-84eb-98cf90542527";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext509__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext509__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext509__avg_gpu_core_frequency__max,acmgt3__ext509__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2412, 24, NULL,acmgt3__ext509__hiz_depth_test_ambig_np_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext510_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext510";
   query->symbol_name = "Ext510";
   query->guid = "8048a7fc-5649-47d1-a5d6-eec5249fe69b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext510__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext510__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext510__avg_gpu_core_frequency__max,acmgt3__ext510__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2413, 24, NULL,acmgt3__ext510__hiz_depth_test_ambig_np_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext511_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext511";
   query->symbol_name = "Ext511";
   query->guid = "a9829627-0ebb-4f96-b62c-66c235fb73b5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext511__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext511__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext511__avg_gpu_core_frequency__max,acmgt3__ext511__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2414, 24, NULL,acmgt3__ext511__hiz_depth_test_ambig_np_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext512_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext512";
   query->symbol_name = "Ext512";
   query->guid = "602d5bcc-18e2-4679-a253-b8447ae2934c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext512__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext512__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext512__avg_gpu_core_frequency__max,acmgt3__ext512__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4733, 24, NULL,acmgt3__ext512__hiz_depth_test_ambig_np_zpipe8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext513_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext513";
   query->symbol_name = "Ext513";
   query->guid = "019ce184-cf6d-4457-aa35-e2b78d84b46f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext513__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext513__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext513__avg_gpu_core_frequency__max,acmgt3__ext513__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4734, 24, NULL,acmgt3__ext513__hiz_depth_test_ambig_np_zpipe9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext514_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext514";
   query->symbol_name = "Ext514";
   query->guid = "207d4da9-9398-48d6-8853-c1f6c2162ff8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext514__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext514__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext514__avg_gpu_core_frequency__max,acmgt3__ext514__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4735, 24, NULL,acmgt3__ext514__hiz_depth_test_ambig_np_zpipe10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext515_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext515";
   query->symbol_name = "Ext515";
   query->guid = "17dee536-5513-4419-9551-d4f5dc3bae81";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext515__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext515__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext515__avg_gpu_core_frequency__max,acmgt3__ext515__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4736, 24, NULL,acmgt3__ext515__hiz_depth_test_ambig_np_zpipe11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext516_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext516";
   query->symbol_name = "Ext516";
   query->guid = "59061d86-24fc-4b93-baa8-c1955328ef28";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext516__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext516__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext516__avg_gpu_core_frequency__max,acmgt3__ext516__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4737, 24, NULL,acmgt3__ext516__hiz_depth_test_ambig_np_zpipe12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext517_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext517";
   query->symbol_name = "Ext517";
   query->guid = "e626d1fe-ab2c-4728-a8d8-3be5dd359551";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext517__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext517__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext517__avg_gpu_core_frequency__max,acmgt3__ext517__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4738, 24, NULL,acmgt3__ext517__hiz_depth_test_ambig_np_zpipe13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext518_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext518";
   query->symbol_name = "Ext518";
   query->guid = "10a8e59b-ad36-4def-a007-068dd782a72f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext518__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext518__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext518__avg_gpu_core_frequency__max,acmgt3__ext518__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4739, 24, NULL,acmgt3__ext518__hiz_depth_test_ambig_np_zpipe14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext519_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext519";
   query->symbol_name = "Ext519";
   query->guid = "e433e93a-0a7c-445c-957d-ed4ee1fc2f80";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext519__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext519__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext519__avg_gpu_core_frequency__max,acmgt3__ext519__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4740, 24, NULL,acmgt3__ext519__hiz_depth_test_ambig_np_zpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext520_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext520";
   query->symbol_name = "Ext520";
   query->guid = "19225cc5-e529-4943-a909-3cc9f147129c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext520__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext520__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext520__avg_gpu_core_frequency__max,acmgt3__ext520__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1443, 24, NULL,acmgt3__ext520__hiz_depth_test_ambig_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext521_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext521";
   query->symbol_name = "Ext521";
   query->guid = "b3add843-8502-41a9-a341-95f077741e80";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext521__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext521__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext521__avg_gpu_core_frequency__max,acmgt3__ext521__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1444, 24, NULL,acmgt3__ext521__hiz_depth_test_ambig_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext522_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext522";
   query->symbol_name = "Ext522";
   query->guid = "24c9f0f5-1452-4c1b-9c37-5d5820da5723";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext522__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext522__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext522__avg_gpu_core_frequency__max,acmgt3__ext522__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1445, 24, NULL,acmgt3__ext522__hiz_depth_test_ambig_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext523_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext523";
   query->symbol_name = "Ext523";
   query->guid = "8a3fad35-8f48-492c-a3c0-71d60b35cc9f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext523__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext523__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext523__avg_gpu_core_frequency__max,acmgt3__ext523__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1446, 24, NULL,acmgt3__ext523__hiz_depth_test_ambig_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext524_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext524";
   query->symbol_name = "Ext524";
   query->guid = "d78e5523-29e2-486c-bb2c-f850c02f0538";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext524__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext524__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext524__avg_gpu_core_frequency__max,acmgt3__ext524__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2415, 24, NULL,acmgt3__ext524__hiz_depth_test_ambig_p_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext525_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext525";
   query->symbol_name = "Ext525";
   query->guid = "f9a891a4-ce16-4f09-9d87-4b9462537ac8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext525__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext525__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext525__avg_gpu_core_frequency__max,acmgt3__ext525__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2416, 24, NULL,acmgt3__ext525__hiz_depth_test_ambig_p_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext526_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext526";
   query->symbol_name = "Ext526";
   query->guid = "d09595c4-1c94-406c-94f5-9eaa44a56b63";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext526__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext526__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext526__avg_gpu_core_frequency__max,acmgt3__ext526__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2417, 24, NULL,acmgt3__ext526__hiz_depth_test_ambig_p_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext527_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext527";
   query->symbol_name = "Ext527";
   query->guid = "e1bc7df6-3d10-4f45-881c-398cd9e3e037";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext527__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext527__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext527__avg_gpu_core_frequency__max,acmgt3__ext527__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2418, 24, NULL,acmgt3__ext527__hiz_depth_test_ambig_p_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext528_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext528";
   query->symbol_name = "Ext528";
   query->guid = "2c30a5a4-7ceb-437d-83df-7d9a507060a8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext528__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext528__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext528__avg_gpu_core_frequency__max,acmgt3__ext528__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4741, 24, NULL,acmgt3__ext528__hiz_depth_test_ambig_p_zpipe8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext529_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext529";
   query->symbol_name = "Ext529";
   query->guid = "a87f8d10-83c9-400c-8e56-286b233c8570";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext529__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext529__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext529__avg_gpu_core_frequency__max,acmgt3__ext529__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4742, 24, NULL,acmgt3__ext529__hiz_depth_test_ambig_p_zpipe9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext530_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext530";
   query->symbol_name = "Ext530";
   query->guid = "08cbf4ca-3da9-45a2-897c-1d817e4dfdc1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext530__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext530__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext530__avg_gpu_core_frequency__max,acmgt3__ext530__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4743, 24, NULL,acmgt3__ext530__hiz_depth_test_ambig_p_zpipe10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext531_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext531";
   query->symbol_name = "Ext531";
   query->guid = "8f8bfee8-6aa3-4862-bf42-c2b988bde49d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext531__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext531__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext531__avg_gpu_core_frequency__max,acmgt3__ext531__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4744, 24, NULL,acmgt3__ext531__hiz_depth_test_ambig_p_zpipe11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext532_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext532";
   query->symbol_name = "Ext532";
   query->guid = "4373c554-04d3-4e15-abf9-c6cbe7dcd17a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160B5800 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000B },
         { .reg = 0x00009888, .val = 0x120B000C },
         { .reg = 0x00009888, .val = 0x140B000D },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext532__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext532__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext532__avg_gpu_core_frequency__max,acmgt3__ext532__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4745, 24, NULL,acmgt3__ext532__hiz_depth_test_ambig_p_zpipe12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext533_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext533";
   query->symbol_name = "Ext533";
   query->guid = "b0a3dc10-4fd1-4f5a-92bc-14c53adbd1d9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160C5800 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000B },
         { .reg = 0x00009888, .val = 0x120C000C },
         { .reg = 0x00009888, .val = 0x140C000D },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext533__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext533__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext533__avg_gpu_core_frequency__max,acmgt3__ext533__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4746, 24, NULL,acmgt3__ext533__hiz_depth_test_ambig_p_zpipe13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext534_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext534";
   query->symbol_name = "Ext534";
   query->guid = "ddd0d949-f0ff-4a4f-a36d-a465d5ff0040";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170B5800 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000B },
         { .reg = 0x00009888, .val = 0x130B000C },
         { .reg = 0x00009888, .val = 0x150B000D },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext534__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext534__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext534__avg_gpu_core_frequency__max,acmgt3__ext534__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4747, 24, NULL,acmgt3__ext534__hiz_depth_test_ambig_p_zpipe14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext535_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext535";
   query->symbol_name = "Ext535";
   query->guid = "79d88e98-4d0e-4aa7-bbe4-05039857e623";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170C5800 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000B },
         { .reg = 0x00009888, .val = 0x130C000C },
         { .reg = 0x00009888, .val = 0x150C000D },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext535__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext535__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext535__avg_gpu_core_frequency__max,acmgt3__ext535__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4748, 24, NULL,acmgt3__ext535__hiz_depth_test_ambig_p_zpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext536_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext536";
   query->symbol_name = "Ext536";
   query->guid = "8dcba9b0-7604-491f-811d-ff80bf4e2a6f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext536__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext536__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext536__avg_gpu_core_frequency__max,acmgt3__ext536__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1447, 24, NULL,acmgt3__ext536__hiz_depth_test_fail_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext537_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext537";
   query->symbol_name = "Ext537";
   query->guid = "c0619436-6cce-4029-95ac-f6761b5afdb1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext537__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext537__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext537__avg_gpu_core_frequency__max,acmgt3__ext537__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1448, 24, NULL,acmgt3__ext537__hiz_depth_test_fail_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext538_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext538";
   query->symbol_name = "Ext538";
   query->guid = "f24aba41-66e9-4a6e-8d78-a7ddd46d3d49";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext538__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext538__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext538__avg_gpu_core_frequency__max,acmgt3__ext538__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1449, 24, NULL,acmgt3__ext538__hiz_depth_test_fail_np_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext539_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext539";
   query->symbol_name = "Ext539";
   query->guid = "0e79879a-074e-4ea7-b942-92cdc63855cd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext539__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext539__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext539__avg_gpu_core_frequency__max,acmgt3__ext539__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1450, 24, NULL,acmgt3__ext539__hiz_depth_test_fail_np_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext540_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext540";
   query->symbol_name = "Ext540";
   query->guid = "b3d690ba-d58e-4cc9-9faf-0b51c5ba958e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext540__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext540__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext540__avg_gpu_core_frequency__max,acmgt3__ext540__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2419, 24, NULL,acmgt3__ext540__hiz_depth_test_fail_np_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext541_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext541";
   query->symbol_name = "Ext541";
   query->guid = "b0065120-ac7f-42fe-8ccf-88b32df3e4cf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext541__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext541__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext541__avg_gpu_core_frequency__max,acmgt3__ext541__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2420, 24, NULL,acmgt3__ext541__hiz_depth_test_fail_np_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext542_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext542";
   query->symbol_name = "Ext542";
   query->guid = "ebbb6680-4931-4719-ac03-fba60301a688";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext542__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext542__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext542__avg_gpu_core_frequency__max,acmgt3__ext542__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2421, 24, NULL,acmgt3__ext542__hiz_depth_test_fail_np_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext543_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext543";
   query->symbol_name = "Ext543";
   query->guid = "672eba96-2c76-4056-a7fa-4e73a9d25627";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext543__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext543__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext543__avg_gpu_core_frequency__max,acmgt3__ext543__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2422, 24, NULL,acmgt3__ext543__hiz_depth_test_fail_np_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext544_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext544";
   query->symbol_name = "Ext544";
   query->guid = "de044605-80ac-43b0-b512-5f629a51ebec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext544__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext544__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext544__avg_gpu_core_frequency__max,acmgt3__ext544__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4749, 24, NULL,acmgt3__ext544__hiz_depth_test_fail_np_zpipe8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext545_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext545";
   query->symbol_name = "Ext545";
   query->guid = "720b8b78-896f-4056-88fa-9074d5127dd7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext545__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext545__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext545__avg_gpu_core_frequency__max,acmgt3__ext545__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4750, 24, NULL,acmgt3__ext545__hiz_depth_test_fail_np_zpipe9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext546_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext546";
   query->symbol_name = "Ext546";
   query->guid = "ee7f867c-816e-449f-a330-1b9622b33ae6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext546__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext546__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext546__avg_gpu_core_frequency__max,acmgt3__ext546__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4751, 24, NULL,acmgt3__ext546__hiz_depth_test_fail_np_zpipe10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext547_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext547";
   query->symbol_name = "Ext547";
   query->guid = "671d65a6-32c0-4983-9204-96e9eb7ff8fa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext547__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext547__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext547__avg_gpu_core_frequency__max,acmgt3__ext547__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4752, 24, NULL,acmgt3__ext547__hiz_depth_test_fail_np_zpipe11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext548_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext548";
   query->symbol_name = "Ext548";
   query->guid = "e23b228a-c5ac-4f11-8cb0-bf2353dfffde";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext548__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext548__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext548__avg_gpu_core_frequency__max,acmgt3__ext548__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4753, 24, NULL,acmgt3__ext548__hiz_depth_test_fail_np_zpipe12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext549_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext549";
   query->symbol_name = "Ext549";
   query->guid = "3b521dba-b087-4c2a-bfbe-f043967881b6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext549__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext549__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext549__avg_gpu_core_frequency__max,acmgt3__ext549__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4754, 24, NULL,acmgt3__ext549__hiz_depth_test_fail_np_zpipe13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext550_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext550";
   query->symbol_name = "Ext550";
   query->guid = "b359e8f4-73ed-4da2-9471-2999a6d5473f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext550__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext550__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext550__avg_gpu_core_frequency__max,acmgt3__ext550__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4755, 24, NULL,acmgt3__ext550__hiz_depth_test_fail_np_zpipe14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext551_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext551";
   query->symbol_name = "Ext551";
   query->guid = "4bbd08e1-85c4-4de2-8ff6-9e5342bd0267";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext551__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext551__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext551__avg_gpu_core_frequency__max,acmgt3__ext551__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4756, 24, NULL,acmgt3__ext551__hiz_depth_test_fail_np_zpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext552_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext552";
   query->symbol_name = "Ext552";
   query->guid = "a0320c5d-dcd3-49ca-ba92-c19c068a69c8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext552__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext552__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext552__avg_gpu_core_frequency__max,acmgt3__ext552__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1451, 24, NULL,acmgt3__ext552__hiz_depth_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext553_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext553";
   query->symbol_name = "Ext553";
   query->guid = "5a2dc84d-c4a8-4b4e-af0d-b14a04ffb79e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext553__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext553__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext553__avg_gpu_core_frequency__max,acmgt3__ext553__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1452, 24, NULL,acmgt3__ext553__hiz_depth_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext554_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext554";
   query->symbol_name = "Ext554";
   query->guid = "82287cfa-dddc-4b40-a0ba-feae2d42d826";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext554__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext554__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext554__avg_gpu_core_frequency__max,acmgt3__ext554__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1453, 24, NULL,acmgt3__ext554__hiz_depth_test_fail_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext555_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext555";
   query->symbol_name = "Ext555";
   query->guid = "0a00e087-e302-497d-b832-d04cd048054f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext555__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext555__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext555__avg_gpu_core_frequency__max,acmgt3__ext555__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1454, 24, NULL,acmgt3__ext555__hiz_depth_test_fail_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext556_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext556";
   query->symbol_name = "Ext556";
   query->guid = "204f7d1a-1063-4e39-9c93-d3fe68a48e93";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext556__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext556__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext556__avg_gpu_core_frequency__max,acmgt3__ext556__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2423, 24, NULL,acmgt3__ext556__hiz_depth_test_fail_p_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext557_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext557";
   query->symbol_name = "Ext557";
   query->guid = "67278ee9-56da-4f70-a405-85e27e8922ec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext557__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext557__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext557__avg_gpu_core_frequency__max,acmgt3__ext557__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2424, 24, NULL,acmgt3__ext557__hiz_depth_test_fail_p_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext558_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext558";
   query->symbol_name = "Ext558";
   query->guid = "b8723d61-732a-4c2f-8765-7e7aba97d348";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext558__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext558__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext558__avg_gpu_core_frequency__max,acmgt3__ext558__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2425, 24, NULL,acmgt3__ext558__hiz_depth_test_fail_p_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext559_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext559";
   query->symbol_name = "Ext559";
   query->guid = "d8091fdb-460b-481e-b36f-4bc4c05c542f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext559__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext559__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext559__avg_gpu_core_frequency__max,acmgt3__ext559__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2426, 24, NULL,acmgt3__ext559__hiz_depth_test_fail_p_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext560_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext560";
   query->symbol_name = "Ext560";
   query->guid = "a6c44052-b731-461d-8333-da99eeb8d5de";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext560__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext560__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext560__avg_gpu_core_frequency__max,acmgt3__ext560__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4757, 24, NULL,acmgt3__ext560__hiz_depth_test_fail_p_zpipe8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext561_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext561";
   query->symbol_name = "Ext561";
   query->guid = "f2be6d7c-336b-46dc-8167-fb6e22106fe0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext561__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext561__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext561__avg_gpu_core_frequency__max,acmgt3__ext561__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4758, 24, NULL,acmgt3__ext561__hiz_depth_test_fail_p_zpipe9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext562_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext562";
   query->symbol_name = "Ext562";
   query->guid = "14cbc671-bc91-461f-b36c-11cac04a4368";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext562__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext562__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext562__avg_gpu_core_frequency__max,acmgt3__ext562__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4759, 24, NULL,acmgt3__ext562__hiz_depth_test_fail_p_zpipe10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext563_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext563";
   query->symbol_name = "Ext563";
   query->guid = "e2422880-ab04-429a-9c59-83e7d129cc06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext563__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext563__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext563__avg_gpu_core_frequency__max,acmgt3__ext563__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4760, 24, NULL,acmgt3__ext563__hiz_depth_test_fail_p_zpipe11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext564_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext564";
   query->symbol_name = "Ext564";
   query->guid = "665be155-1110-4a9a-9281-7c3005cdb3ae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160B4400 },
         { .reg = 0x00009888, .val = 0x180B0010 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3C00 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B000C },
         { .reg = 0x00009888, .val = 0x120B000D },
         { .reg = 0x00009888, .val = 0x140B000E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext564__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext564__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext564__avg_gpu_core_frequency__max,acmgt3__ext564__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4761, 24, NULL,acmgt3__ext564__hiz_depth_test_fail_p_zpipe12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext565_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext565";
   query->symbol_name = "Ext565";
   query->guid = "65bfe375-5cb3-4677-81fe-be5cde04a66f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160C4400 },
         { .reg = 0x00009888, .val = 0x180C0010 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3C00 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C000C },
         { .reg = 0x00009888, .val = 0x120C000D },
         { .reg = 0x00009888, .val = 0x140C000E },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext565__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext565__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext565__avg_gpu_core_frequency__max,acmgt3__ext565__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4762, 24, NULL,acmgt3__ext565__hiz_depth_test_fail_p_zpipe13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext566_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext566";
   query->symbol_name = "Ext566";
   query->guid = "a039f0c8-1641-47d8-8e59-6df51100da38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170B4400 },
         { .reg = 0x00009888, .val = 0x190B0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3C00 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B000C },
         { .reg = 0x00009888, .val = 0x130B000D },
         { .reg = 0x00009888, .val = 0x150B000E },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext566__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext566__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext566__avg_gpu_core_frequency__max,acmgt3__ext566__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4763, 24, NULL,acmgt3__ext566__hiz_depth_test_fail_p_zpipe14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext567_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext567";
   query->symbol_name = "Ext567";
   query->guid = "87c6ccd6-4f63-4f59-b3bc-54af974bf7c4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170C4400 },
         { .reg = 0x00009888, .val = 0x190C0010 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3C00 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C000C },
         { .reg = 0x00009888, .val = 0x130C000D },
         { .reg = 0x00009888, .val = 0x150C000E },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext567__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext567__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext567__avg_gpu_core_frequency__max,acmgt3__ext567__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4764, 24, NULL,acmgt3__ext567__hiz_depth_test_fail_p_zpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext568_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext568";
   query->symbol_name = "Ext568";
   query->guid = "fe0cbe07-d685-40d8-ba09-4a5a8fb45b99";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160B6000 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B0008 },
         { .reg = 0x00009888, .val = 0x120B0009 },
         { .reg = 0x00009888, .val = 0x140B000A },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext568__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext568__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext568__avg_gpu_core_frequency__max,acmgt3__ext568__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1455, 24, NULL,acmgt3__ext568__hiz_depth_test_pass_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext569_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext569";
   query->symbol_name = "Ext569";
   query->guid = "05da3d04-5cf9-4ecf-ac16-65cd2c06269c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160C6000 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C0008 },
         { .reg = 0x00009888, .val = 0x120C0009 },
         { .reg = 0x00009888, .val = 0x140C000A },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext569__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext569__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext569__avg_gpu_core_frequency__max,acmgt3__ext569__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1456, 24, NULL,acmgt3__ext569__hiz_depth_test_pass_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext570_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext570";
   query->symbol_name = "Ext570";
   query->guid = "e4576efb-543e-4a05-8ce4-9b8cf86d0d65";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170B6000 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B0008 },
         { .reg = 0x00009888, .val = 0x130B0009 },
         { .reg = 0x00009888, .val = 0x150B000A },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext570__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext570__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext570__avg_gpu_core_frequency__max,acmgt3__ext570__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1457, 24, NULL,acmgt3__ext570__hiz_depth_test_pass_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext571_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext571";
   query->symbol_name = "Ext571";
   query->guid = "07dc1b67-a2ad-45a5-941c-a4f294dc5426";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x170C6000 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C0008 },
         { .reg = 0x00009888, .val = 0x130C0009 },
         { .reg = 0x00009888, .val = 0x150C000A },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext571__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext571__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext571__avg_gpu_core_frequency__max,acmgt3__ext571__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1458, 24, NULL,acmgt3__ext571__hiz_depth_test_pass_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext572_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext572";
   query->symbol_name = "Ext572";
   query->guid = "8c1361cf-3383-4b12-9865-d041c3c7ef80";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0301E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B6000 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B0008 },
         { .reg = 0x00009888, .val = 0x120B0009 },
         { .reg = 0x00009888, .val = 0x140B000A },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext572__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext572__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext572__avg_gpu_core_frequency__max,acmgt3__ext572__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2427, 24, NULL,acmgt3__ext572__hiz_depth_test_pass_p_zpipe4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext573_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext573";
   query->symbol_name = "Ext573";
   query->guid = "7b800152-513a-4d41-bcc9-f79e175f66c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0307E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030060 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160C6000 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C0008 },
         { .reg = 0x00009888, .val = 0x120C0009 },
         { .reg = 0x00009888, .val = 0x140C000A },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext573__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext573__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext573__avg_gpu_core_frequency__max,acmgt3__ext573__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2428, 24, NULL,acmgt3__ext573__hiz_depth_test_pass_p_zpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext574_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext574";
   query->symbol_name = "Ext574";
   query->guid = "089c60d7-18f0-447a-98c9-abaf82aba70b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033DE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303C0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170B6000 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B0008 },
         { .reg = 0x00009888, .val = 0x130B0009 },
         { .reg = 0x00009888, .val = 0x150B000A },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext574__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext574__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext574__avg_gpu_core_frequency__max,acmgt3__ext574__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2429, 24, NULL,acmgt3__ext574__hiz_depth_test_pass_p_zpipe6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext575_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext575";
   query->symbol_name = "Ext575";
   query->guid = "00101c81-f560-4e07-9ac8-7e276798feda";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x170C6000 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C0008 },
         { .reg = 0x00009888, .val = 0x130C0009 },
         { .reg = 0x00009888, .val = 0x150C000A },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext575__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext575__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext575__avg_gpu_core_frequency__max,acmgt3__ext575__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2430, 24, NULL,acmgt3__ext575__hiz_depth_test_pass_p_zpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext576_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext576";
   query->symbol_name = "Ext576";
   query->guid = "bf4a340e-056c-42cc-b1a6-66ace5b2e385";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B6000 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B0008 },
         { .reg = 0x00009888, .val = 0x120B0009 },
         { .reg = 0x00009888, .val = 0x140B000A },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext576__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext576__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext576__avg_gpu_core_frequency__max,acmgt3__ext576__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4765, 24, NULL,acmgt3__ext576__hiz_depth_test_pass_p_zpipe8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext577_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext577";
   query->symbol_name = "Ext577";
   query->guid = "67b34202-9016-4aea-a1f0-5978b11c8636";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160C6000 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C0008 },
         { .reg = 0x00009888, .val = 0x120C0009 },
         { .reg = 0x00009888, .val = 0x140C000A },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext577__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext577__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext577__avg_gpu_core_frequency__max,acmgt3__ext577__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4766, 24, NULL,acmgt3__ext577__hiz_depth_test_pass_p_zpipe9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext578_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext578";
   query->symbol_name = "Ext578";
   query->guid = "fafe97c9-e42c-443c-aa3b-bd18dcc6903c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170B6000 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B0008 },
         { .reg = 0x00009888, .val = 0x130B0009 },
         { .reg = 0x00009888, .val = 0x150B000A },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext578__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext578__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext578__avg_gpu_core_frequency__max,acmgt3__ext578__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4767, 24, NULL,acmgt3__ext578__hiz_depth_test_pass_p_zpipe10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext579_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext579";
   query->symbol_name = "Ext579";
   query->guid = "2d7f6b11-59c1-468a-bcef-131d2cb62a28";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x170C6000 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C0008 },
         { .reg = 0x00009888, .val = 0x130C0009 },
         { .reg = 0x00009888, .val = 0x150C000A },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext579__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext579__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext579__avg_gpu_core_frequency__max,acmgt3__ext579__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4768, 24, NULL,acmgt3__ext579__hiz_depth_test_pass_p_zpipe11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext580_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext580";
   query->symbol_name = "Ext580";
   query->guid = "dee1277c-09d1-49f7-9035-039420ce8f55";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0303E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030020 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160B6000 },
         { .reg = 0x00009888, .val = 0x180B0017 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x040B002C },
         { .reg = 0x00009888, .val = 0x060B3800 },
         { .reg = 0x00009888, .val = 0x080B0081 },
         { .reg = 0x00009888, .val = 0x0A0B0103 },
         { .reg = 0x00009888, .val = 0x0C0B0185 },
         { .reg = 0x00009888, .val = 0x0E0B0007 },
         { .reg = 0x00009888, .val = 0x100B0008 },
         { .reg = 0x00009888, .val = 0x120B0009 },
         { .reg = 0x00009888, .val = 0x140B000A },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext580__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext580__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext580__avg_gpu_core_frequency__max,acmgt3__ext580__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4769, 24, NULL,acmgt3__ext580__hiz_depth_test_pass_p_zpipe12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext581_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext581";
   query->symbol_name = "Ext581";
   query->guid = "97733423-59b0-4de6-9909-39bbe2e5f0b7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0309E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030080 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160C6000 },
         { .reg = 0x00009888, .val = 0x180C0017 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02072222 },
         { .reg = 0x00009888, .val = 0x000955FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2222 },
         { .reg = 0x00009888, .val = 0x000255FF },
         { .reg = 0x00009888, .val = 0x040C002C },
         { .reg = 0x00009888, .val = 0x060C3800 },
         { .reg = 0x00009888, .val = 0x080C0081 },
         { .reg = 0x00009888, .val = 0x0A0C0103 },
         { .reg = 0x00009888, .val = 0x0C0C0185 },
         { .reg = 0x00009888, .val = 0x0E0C0007 },
         { .reg = 0x00009888, .val = 0x100C0008 },
         { .reg = 0x00009888, .val = 0x120C0009 },
         { .reg = 0x00009888, .val = 0x140C000A },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext581__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext581__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext581__avg_gpu_core_frequency__max,acmgt3__ext581__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4770, 24, NULL,acmgt3__ext581__hiz_depth_test_pass_p_zpipe13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext582_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext582";
   query->symbol_name = "Ext582";
   query->guid = "14f60fa0-1209-44d4-8618-c8dd54b8965d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A033FE0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400303E0 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170B6000 },
         { .reg = 0x00009888, .val = 0x190B0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x03083333 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009888, .val = 0x010155FF },
         { .reg = 0x00009888, .val = 0x050B002C },
         { .reg = 0x00009888, .val = 0x070B3800 },
         { .reg = 0x00009888, .val = 0x090B0081 },
         { .reg = 0x00009888, .val = 0x0B0B0103 },
         { .reg = 0x00009888, .val = 0x0D0B0185 },
         { .reg = 0x00009888, .val = 0x0F0B0007 },
         { .reg = 0x00009888, .val = 0x110B0008 },
         { .reg = 0x00009888, .val = 0x130B0009 },
         { .reg = 0x00009888, .val = 0x150B000A },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext582__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext582__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext582__avg_gpu_core_frequency__max,acmgt3__ext582__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4771, 24, NULL,acmgt3__ext582__hiz_depth_test_pass_p_zpipe14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext583_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext583";
   query->symbol_name = "Ext583";
   query->guid = "6297276e-f7c6-4ac7-bc7b-4e1fb4c606a1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030800 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0305E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030040 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x170C6000 },
         { .reg = 0x00009888, .val = 0x190C0017 },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x03072222 },
         { .reg = 0x00009888, .val = 0x010955FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A2222 },
         { .reg = 0x00009888, .val = 0x010255FF },
         { .reg = 0x00009888, .val = 0x050C002C },
         { .reg = 0x00009888, .val = 0x070C3800 },
         { .reg = 0x00009888, .val = 0x090C0081 },
         { .reg = 0x00009888, .val = 0x0B0C0103 },
         { .reg = 0x00009888, .val = 0x0D0C0185 },
         { .reg = 0x00009888, .val = 0x0F0C0007 },
         { .reg = 0x00009888, .val = 0x110C0008 },
         { .reg = 0x00009888, .val = 0x130C0009 },
         { .reg = 0x00009888, .val = 0x150C000A },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext583__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext583__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext583__avg_gpu_core_frequency__max,acmgt3__ext583__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4772, 24, NULL,acmgt3__ext583__hiz_depth_test_pass_p_zpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext584_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext584";
   query->symbol_name = "Ext584";
   query->guid = "812c0cf8-1163-454e-a6ff-36c6b3866b1f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C6000 },
         { .reg = 0x00009888, .val = 0x0D0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C6000 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x00094000 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x0001B000 },
         { .reg = 0x00009888, .val = 0x040B0000 },
         { .reg = 0x00009888, .val = 0x140B0580 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x040C0000 },
         { .reg = 0x00009888, .val = 0x140C0016 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x01012000 },
         { .reg = 0x00009888, .val = 0x050B0000 },
         { .reg = 0x00009888, .val = 0x130B0580 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01021000 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x130C0016 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0C0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C6000 },
         { .reg = 0x00009888, .val = 0x0D0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C6000 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x02070020 },
         { .reg = 0x00009888, .val = 0x020800CF },
         { .reg = 0x00009888, .val = 0x00090400 },
         { .reg = 0x00009888, .val = 0x020A0065 },
         { .reg = 0x00009888, .val = 0x00010B00 },
         { .reg = 0x00009888, .val = 0x040B0000 },
         { .reg = 0x00009888, .val = 0x100B0580 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x00020400 },
         { .reg = 0x00009888, .val = 0x040C0000 },
         { .reg = 0x00009888, .val = 0x100C0016 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x0308000C },
         { .reg = 0x00009888, .val = 0x01090100 },
         { .reg = 0x00009888, .val = 0x030A0006 },
         { .reg = 0x00009888, .val = 0x01010200 },
         { .reg = 0x00009888, .val = 0x050B0000 },
         { .reg = 0x00009888, .val = 0x0F0B0580 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01020100 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x0F0C0016 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0C0B6580 },
         { .reg = 0x00009888, .val = 0x0C0C6016 },
         { .reg = 0x00009888, .val = 0x0D0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C6000 },
         { .reg = 0x00009888, .val = 0x00030030 },
         { .reg = 0x00009888, .val = 0x00072000 },
         { .reg = 0x00009888, .val = 0x0008CF00 },
         { .reg = 0x00009888, .val = 0x00090040 },
         { .reg = 0x00009888, .val = 0x000A6500 },
         { .reg = 0x00009888, .val = 0x000100B0 },
         { .reg = 0x00009888, .val = 0x040B0000 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0A00 },
         { .reg = 0x00009888, .val = 0x00020040 },
         { .reg = 0x00009888, .val = 0x040C0000 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x01070200 },
         { .reg = 0x00009888, .val = 0x01080C00 },
         { .reg = 0x00009888, .val = 0x01090010 },
         { .reg = 0x00009888, .val = 0x010A0600 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x050B0000 },
         { .reg = 0x00009888, .val = 0x0B0B0580 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x01020010 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x0B0C0016 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0C0B6000 },
         { .reg = 0x00009888, .val = 0x0C0C6000 },
         { .reg = 0x00009888, .val = 0x0D0B6000 },
         { .reg = 0x00009888, .val = 0x0D0C6000 },
         { .reg = 0x00009888, .val = 0x00030003 },
         { .reg = 0x00009888, .val = 0x00070020 },
         { .reg = 0x00009888, .val = 0x000800CF },
         { .reg = 0x00009888, .val = 0x00090004 },
         { .reg = 0x00009888, .val = 0x000A0065 },
         { .reg = 0x00009888, .val = 0x0001000B },
         { .reg = 0x00009888, .val = 0x040B0000 },
         { .reg = 0x00009888, .val = 0x080B0580 },
         { .reg = 0x00009888, .val = 0x000B000A },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x040C0000 },
         { .reg = 0x00009888, .val = 0x080C0016 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0108000C },
         { .reg = 0x00009888, .val = 0x01090001 },
         { .reg = 0x00009888, .val = 0x010A0006 },
         { .reg = 0x00009888, .val = 0x01010002 },
         { .reg = 0x00009888, .val = 0x050B0000 },
         { .reg = 0x00009888, .val = 0x070B5800 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x01020001 },
         { .reg = 0x00009888, .val = 0x050C0000 },
         { .reg = 0x00009888, .val = 0x070C0160 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030520 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032061 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031063 },
         { .reg = 0x00009888, .val = 0x48030007 },
         { .reg = 0x00009888, .val = 0x4A030801 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032481 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext584__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext584__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext584__avg_gpu_core_frequency__max,acmgt3__ext584__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1467, 24, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1468, 28, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1469, 32, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1470, 36, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2439, 40, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2440, 44, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2441, 48, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2442, 52, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4773, 56, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe8__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4774, 60, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe9__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4775, 64, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe10__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4776, 68, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe11__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4777, 72, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe12__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4778, 76, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe13__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4779, 80, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe14__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4780, 84, percentage_max_float,acmgt3__ext584__iz_output_ready_zpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext585_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext585";
   query->symbol_name = "Ext585";
   query->guid = "2921d39b-5490-416a-bc1f-61d1782819fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160B2C00 },
         { .reg = 0x00009888, .val = 0x160C2C00 },
         { .reg = 0x00009888, .val = 0x170B2C00 },
         { .reg = 0x00009888, .val = 0x170C2C00 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x00094000 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x0001B000 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x140B0080 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x040C0004 },
         { .reg = 0x00009888, .val = 0x140C0002 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x01012000 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x130B0080 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01021000 },
         { .reg = 0x00009888, .val = 0x050C0004 },
         { .reg = 0x00009888, .val = 0x130C0002 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160B2C00 },
         { .reg = 0x00009888, .val = 0x160C2C00 },
         { .reg = 0x00009888, .val = 0x170B2C00 },
         { .reg = 0x00009888, .val = 0x170C2C00 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x02070020 },
         { .reg = 0x00009888, .val = 0x020800CF },
         { .reg = 0x00009888, .val = 0x00090400 },
         { .reg = 0x00009888, .val = 0x020A0065 },
         { .reg = 0x00009888, .val = 0x00010B00 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x100B0080 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x00020400 },
         { .reg = 0x00009888, .val = 0x040C0004 },
         { .reg = 0x00009888, .val = 0x100C0002 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x0308000C },
         { .reg = 0x00009888, .val = 0x01090100 },
         { .reg = 0x00009888, .val = 0x030A0006 },
         { .reg = 0x00009888, .val = 0x01010200 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x0F0B0080 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01020100 },
         { .reg = 0x00009888, .val = 0x050C0004 },
         { .reg = 0x00009888, .val = 0x0F0C0002 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160B2C00 },
         { .reg = 0x00009888, .val = 0x160C2C00 },
         { .reg = 0x00009888, .val = 0x170B2C00 },
         { .reg = 0x00009888, .val = 0x170C2C00 },
         { .reg = 0x00009888, .val = 0x00030030 },
         { .reg = 0x00009888, .val = 0x00072000 },
         { .reg = 0x00009888, .val = 0x0008CF00 },
         { .reg = 0x00009888, .val = 0x00090040 },
         { .reg = 0x00009888, .val = 0x000A6500 },
         { .reg = 0x00009888, .val = 0x000100B0 },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x0C0B0080 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0A00 },
         { .reg = 0x00009888, .val = 0x00020040 },
         { .reg = 0x00009888, .val = 0x040C0004 },
         { .reg = 0x00009888, .val = 0x0C0C0002 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x01070200 },
         { .reg = 0x00009888, .val = 0x01080C00 },
         { .reg = 0x00009888, .val = 0x01090010 },
         { .reg = 0x00009888, .val = 0x010A0600 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x0B0B0080 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x01020010 },
         { .reg = 0x00009888, .val = 0x050C0004 },
         { .reg = 0x00009888, .val = 0x0B0C0002 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160B2C00 },
         { .reg = 0x00009888, .val = 0x160C2C00 },
         { .reg = 0x00009888, .val = 0x170B2C00 },
         { .reg = 0x00009888, .val = 0x170C2C00 },
         { .reg = 0x00009888, .val = 0x00030003 },
         { .reg = 0x00009888, .val = 0x00070020 },
         { .reg = 0x00009888, .val = 0x000800CF },
         { .reg = 0x00009888, .val = 0x00090004 },
         { .reg = 0x00009888, .val = 0x000A0065 },
         { .reg = 0x00009888, .val = 0x0001000B },
         { .reg = 0x00009888, .val = 0x040B0004 },
         { .reg = 0x00009888, .val = 0x080B0080 },
         { .reg = 0x00009888, .val = 0x000B000A },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x040C0004 },
         { .reg = 0x00009888, .val = 0x080C0002 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0108000C },
         { .reg = 0x00009888, .val = 0x01090001 },
         { .reg = 0x00009888, .val = 0x010A0006 },
         { .reg = 0x00009888, .val = 0x01010002 },
         { .reg = 0x00009888, .val = 0x050B0004 },
         { .reg = 0x00009888, .val = 0x070B0800 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x01020001 },
         { .reg = 0x00009888, .val = 0x050C0004 },
         { .reg = 0x00009888, .val = 0x070C0020 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030520 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032061 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031063 },
         { .reg = 0x00009888, .val = 0x48030007 },
         { .reg = 0x00009888, .val = 0x4A030801 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032481 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext585__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext585__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext585__avg_gpu_core_frequency__max,acmgt3__ext585__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1459, 24, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1460, 28, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1461, 32, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1462, 36, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2431, 40, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2432, 44, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2433, 48, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2434, 52, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4781, 56, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe8__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4782, 60, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe9__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4783, 64, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe10__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4784, 68, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe11__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4785, 72, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe12__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4786, 76, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe13__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4787, 80, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe14__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4788, 84, percentage_max_float,acmgt3__ext585__hiz_subspan_latency_fifofull_zpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext586_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext586";
   query->symbol_name = "Ext586";
   query->guid = "340dd552-3f57-4f94-b8c5-2d7d96c4bbdf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x100B6000 },
         { .reg = 0x00009888, .val = 0x100C6000 },
         { .reg = 0x00009888, .val = 0x110B6000 },
         { .reg = 0x00009888, .val = 0x110C6000 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x00094000 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x0001B000 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x140B0540 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x140C0015 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x01012000 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x130B0540 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01021000 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x130C0015 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x100B6540 },
         { .reg = 0x00009888, .val = 0x100C6015 },
         { .reg = 0x00009888, .val = 0x110B6000 },
         { .reg = 0x00009888, .val = 0x110C6000 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x02070020 },
         { .reg = 0x00009888, .val = 0x020800CF },
         { .reg = 0x00009888, .val = 0x00090400 },
         { .reg = 0x00009888, .val = 0x020A0065 },
         { .reg = 0x00009888, .val = 0x00010B00 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x00020400 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x0308000C },
         { .reg = 0x00009888, .val = 0x01090100 },
         { .reg = 0x00009888, .val = 0x030A0006 },
         { .reg = 0x00009888, .val = 0x01010200 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x0F0B0540 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x030B0000 },
         { .reg = 0x00009888, .val = 0x01020100 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x0F0C0015 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x030C0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x100B6000 },
         { .reg = 0x00009888, .val = 0x100C6000 },
         { .reg = 0x00009888, .val = 0x110B6000 },
         { .reg = 0x00009888, .val = 0x110C6000 },
         { .reg = 0x00009888, .val = 0x00030030 },
         { .reg = 0x00009888, .val = 0x00072000 },
         { .reg = 0x00009888, .val = 0x0008CF00 },
         { .reg = 0x00009888, .val = 0x00090040 },
         { .reg = 0x00009888, .val = 0x000A6500 },
         { .reg = 0x00009888, .val = 0x000100B0 },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x0C0B0540 },
         { .reg = 0x00009888, .val = 0x080B0000 },
         { .reg = 0x00009888, .val = 0x000B0A00 },
         { .reg = 0x00009888, .val = 0x00020040 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x0C0C0015 },
         { .reg = 0x00009888, .val = 0x080C0000 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x01070200 },
         { .reg = 0x00009888, .val = 0x01080C00 },
         { .reg = 0x00009888, .val = 0x01090010 },
         { .reg = 0x00009888, .val = 0x010A0600 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x0B0B0540 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x01020010 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x0B0C0015 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x100B6000 },
         { .reg = 0x00009888, .val = 0x100C6000 },
         { .reg = 0x00009888, .val = 0x110B6000 },
         { .reg = 0x00009888, .val = 0x110C6000 },
         { .reg = 0x00009888, .val = 0x00030003 },
         { .reg = 0x00009888, .val = 0x00070020 },
         { .reg = 0x00009888, .val = 0x000800CF },
         { .reg = 0x00009888, .val = 0x00090004 },
         { .reg = 0x00009888, .val = 0x000A0065 },
         { .reg = 0x00009888, .val = 0x0001000B },
         { .reg = 0x00009888, .val = 0x040B0080 },
         { .reg = 0x00009888, .val = 0x080B0540 },
         { .reg = 0x00009888, .val = 0x000B000A },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x040C0080 },
         { .reg = 0x00009888, .val = 0x080C0015 },
         { .reg = 0x00009888, .val = 0x000C0000 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0108000C },
         { .reg = 0x00009888, .val = 0x01090001 },
         { .reg = 0x00009888, .val = 0x010A0006 },
         { .reg = 0x00009888, .val = 0x01010002 },
         { .reg = 0x00009888, .val = 0x050B0080 },
         { .reg = 0x00009888, .val = 0x070B5400 },
         { .reg = 0x00009888, .val = 0x090B0000 },
         { .reg = 0x00009888, .val = 0x010B0000 },
         { .reg = 0x00009888, .val = 0x01020001 },
         { .reg = 0x00009888, .val = 0x050C0080 },
         { .reg = 0x00009888, .val = 0x070C0150 },
         { .reg = 0x00009888, .val = 0x090C0000 },
         { .reg = 0x00009888, .val = 0x010C0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030520 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032061 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031063 },
         { .reg = 0x00009888, .val = 0x48030007 },
         { .reg = 0x00009888, .val = 0x4A030801 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032481 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext586__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext586__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext586__avg_gpu_core_frequency__max,acmgt3__ext586__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1463, 24, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1464, 28, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1465, 32, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1466, 36, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2435, 40, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2436, 44, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2437, 48, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2438, 52, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4789, 56, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe8__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4790, 60, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe9__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4791, 64, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe10__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4792, 68, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe11__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4793, 72, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe12__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4794, 76, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe13__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4795, 80, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe14__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4796, 84, percentage_max_float,acmgt3__ext586__iz_subspan_latency_fifofull_zpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext587_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext587";
   query->symbol_name = "Ext587";
   query->guid = "09a795b1-15ba-4f83-a662-18804b4eda96";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12011000 },
         { .reg = 0x00009888, .val = 0x12021C00 },
         { .reg = 0x00009888, .val = 0x13011030 },
         { .reg = 0x00009888, .val = 0x13021000 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x00094000 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x14010030 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x05010000 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x05020000 },
         { .reg = 0x00009888, .val = 0x11020C00 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12011000 },
         { .reg = 0x00009888, .val = 0x12021000 },
         { .reg = 0x00009888, .val = 0x13011000 },
         { .reg = 0x00009888, .val = 0x13021000 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x02070020 },
         { .reg = 0x00009888, .val = 0x020800CF },
         { .reg = 0x00009888, .val = 0x00090400 },
         { .reg = 0x00009888, .val = 0x020A0065 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x10010030 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00010300 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x0E020C00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x0308000C },
         { .reg = 0x00009888, .val = 0x01090100 },
         { .reg = 0x00009888, .val = 0x030A0006 },
         { .reg = 0x00009888, .val = 0x05010000 },
         { .reg = 0x00009888, .val = 0x0F010030 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x05020000 },
         { .reg = 0x00009888, .val = 0x0D020C00 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12011000 },
         { .reg = 0x00009888, .val = 0x12021000 },
         { .reg = 0x00009888, .val = 0x13011000 },
         { .reg = 0x00009888, .val = 0x13021000 },
         { .reg = 0x00009888, .val = 0x00030030 },
         { .reg = 0x00009888, .val = 0x00072000 },
         { .reg = 0x00009888, .val = 0x0008CF00 },
         { .reg = 0x00009888, .val = 0x00090040 },
         { .reg = 0x00009888, .val = 0x000A6500 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x0C010030 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00010030 },
         { .reg = 0x00009888, .val = 0x000B0A00 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x0A020C00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x01070200 },
         { .reg = 0x00009888, .val = 0x01080C00 },
         { .reg = 0x00009888, .val = 0x01090010 },
         { .reg = 0x00009888, .val = 0x010A0600 },
         { .reg = 0x00009888, .val = 0x05010000 },
         { .reg = 0x00009888, .val = 0x0B010030 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x05020000 },
         { .reg = 0x00009888, .val = 0x09020C00 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x12011000 },
         { .reg = 0x00009888, .val = 0x12021000 },
         { .reg = 0x00009888, .val = 0x13011000 },
         { .reg = 0x00009888, .val = 0x13021000 },
         { .reg = 0x00009888, .val = 0x00030003 },
         { .reg = 0x00009888, .val = 0x00070020 },
         { .reg = 0x00009888, .val = 0x000800CF },
         { .reg = 0x00009888, .val = 0x00090004 },
         { .reg = 0x00009888, .val = 0x000A0065 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x08010030 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x000B000A },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x06020C00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0108000C },
         { .reg = 0x00009888, .val = 0x01090001 },
         { .reg = 0x00009888, .val = 0x010A0006 },
         { .reg = 0x00009888, .val = 0x05010000 },
         { .reg = 0x00009888, .val = 0x07010030 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x05021800 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030520 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032061 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031063 },
         { .reg = 0x00009888, .val = 0x48030007 },
         { .reg = 0x00009888, .val = 0x4A030801 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032481 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext587__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext587__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext587__avg_gpu_core_frequency__max,acmgt3__ext587__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1375, 24, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1376, 28, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1377, 32, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1378, 36, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2283, 40, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2284, 44, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2285, 48, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2286, 52, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4797, 56, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe8__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4798, 60, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe9__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4799, 64, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe10__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4800, 68, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe11__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4801, 72, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe12__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4802, 76, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe13__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4803, 80, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe14__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4804, 84, percentage_max_float,acmgt3__ext587__color_pipe_cache_latency1_stall_cpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext588_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext588";
   query->symbol_name = "Ext588";
   query->guid = "91a7be1d-3a4d-488f-999a-fd2b9564714e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18010320 },
         { .reg = 0x00009888, .val = 0x18020320 },
         { .reg = 0x00009888, .val = 0x19010320 },
         { .reg = 0x00009888, .val = 0x19020320 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x0008FF0F },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x04011100 },
         { .reg = 0x00009888, .val = 0x06010021 },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x06020880 },
         { .reg = 0x00009888, .val = 0x08020021 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x01080F00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x09010880 },
         { .reg = 0x00009888, .val = 0x0B010021 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x0B020880 },
         { .reg = 0x00009888, .val = 0x0D020021 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18010320 },
         { .reg = 0x00009888, .val = 0x18020320 },
         { .reg = 0x00009888, .val = 0x19010320 },
         { .reg = 0x00009888, .val = 0x19020320 },
         { .reg = 0x00009888, .val = 0x0003F000 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x0208FF0F },
         { .reg = 0x00009888, .val = 0x00090C00 },
         { .reg = 0x00009888, .val = 0x020A55A5 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x0C010880 },
         { .reg = 0x00009888, .val = 0x0E010021 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x0E020880 },
         { .reg = 0x00009888, .val = 0x10020021 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0307A000 },
         { .reg = 0x00009888, .val = 0x03080F00 },
         { .reg = 0x00009888, .val = 0x0109C000 },
         { .reg = 0x00009888, .val = 0x030AA500 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x11010880 },
         { .reg = 0x00009888, .val = 0x13010021 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x13020880 },
         { .reg = 0x00009888, .val = 0x15020021 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030068 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030E00 },
         { .reg = 0x00009888, .val = 0x4A0300E0 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030063 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext588__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext588__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext588__avg_gpu_core_frequency__max,acmgt3__ext588__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1383, 24, percentage_max_float,acmgt3__ext588__ps_output_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1384, 28, percentage_max_float,acmgt3__ext588__ps_output_available_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1385, 32, percentage_max_float,acmgt3__ext588__ps_output_available_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1386, 36, percentage_max_float,acmgt3__ext588__ps_output_available_cpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2293, 40, percentage_max_float,acmgt3__ext588__ps_output_available_cpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2294, 44, percentage_max_float,acmgt3__ext588__ps_output_available_cpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2295, 48, percentage_max_float,acmgt3__ext588__ps_output_available_cpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2296, 52, percentage_max_float,acmgt3__ext588__ps_output_available_cpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext589_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext589";
   query->symbol_name = "Ext589";
   query->guid = "702f4f48-255f-4a82-94b9-2149053fa6c5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18010320 },
         { .reg = 0x00009888, .val = 0x18020320 },
         { .reg = 0x00009888, .val = 0x19010320 },
         { .reg = 0x00009888, .val = 0x19020320 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x000700A0 },
         { .reg = 0x00009888, .val = 0x0008FF0F },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x04011100 },
         { .reg = 0x00009888, .val = 0x06010021 },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x06020880 },
         { .reg = 0x00009888, .val = 0x08020021 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x01080F00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x09010880 },
         { .reg = 0x00009888, .val = 0x0B010021 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x0B020880 },
         { .reg = 0x00009888, .val = 0x0D020021 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18010320 },
         { .reg = 0x00009888, .val = 0x18020320 },
         { .reg = 0x00009888, .val = 0x19010320 },
         { .reg = 0x00009888, .val = 0x19020320 },
         { .reg = 0x00009888, .val = 0x0003F000 },
         { .reg = 0x00009888, .val = 0x020700A0 },
         { .reg = 0x00009888, .val = 0x0208FF0F },
         { .reg = 0x00009888, .val = 0x00090C00 },
         { .reg = 0x00009888, .val = 0x020A55A5 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x0C010880 },
         { .reg = 0x00009888, .val = 0x0E010021 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x0E020880 },
         { .reg = 0x00009888, .val = 0x10020021 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0307A000 },
         { .reg = 0x00009888, .val = 0x03080F00 },
         { .reg = 0x00009888, .val = 0x0109C000 },
         { .reg = 0x00009888, .val = 0x030AA500 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x11010880 },
         { .reg = 0x00009888, .val = 0x13010021 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x13020880 },
         { .reg = 0x00009888, .val = 0x15020021 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030068 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030E00 },
         { .reg = 0x00009888, .val = 0x4A0300E0 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030063 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext589__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext589__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext589__avg_gpu_core_frequency__max,acmgt3__ext589__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4805, 24, percentage_max_float,acmgt3__ext589__ps_output_available_cpipe8__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4806, 28, percentage_max_float,acmgt3__ext589__ps_output_available_cpipe9__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4807, 32, percentage_max_float,acmgt3__ext589__ps_output_available_cpipe10__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4808, 36, percentage_max_float,acmgt3__ext589__ps_output_available_cpipe11__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4809, 40, percentage_max_float,acmgt3__ext589__ps_output_available_cpipe12__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4810, 44, percentage_max_float,acmgt3__ext589__ps_output_available_cpipe13__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4811, 48, percentage_max_float,acmgt3__ext589__ps_output_available_cpipe14__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4812, 52, percentage_max_float,acmgt3__ext589__ps_output_available_cpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext590_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext590";
   query->symbol_name = "Ext590";
   query->guid = "21788d5b-810d-4982-b915-0048962b86e7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16010003 },
         { .reg = 0x00009888, .val = 0x16020003 },
         { .reg = 0x00009888, .val = 0x17010003 },
         { .reg = 0x00009888, .val = 0x17020003 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x02072000 },
         { .reg = 0x00009888, .val = 0x0208CF00 },
         { .reg = 0x00009888, .val = 0x00094000 },
         { .reg = 0x00009888, .val = 0x020A6500 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x14010017 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x120205C0 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x03070200 },
         { .reg = 0x00009888, .val = 0x03080C00 },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A0600 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x13010017 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x110205C0 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16010003 },
         { .reg = 0x00009888, .val = 0x16020003 },
         { .reg = 0x00009888, .val = 0x17010003 },
         { .reg = 0x00009888, .val = 0x17020003 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x02070020 },
         { .reg = 0x00009888, .val = 0x020800CF },
         { .reg = 0x00009888, .val = 0x00090400 },
         { .reg = 0x00009888, .val = 0x020A0065 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x10010017 },
         { .reg = 0x00009888, .val = 0x00010300 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x0E0205C0 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x0308000C },
         { .reg = 0x00009888, .val = 0x01090100 },
         { .reg = 0x00009888, .val = 0x030A0006 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x0F010017 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x0D0205C0 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16010003 },
         { .reg = 0x00009888, .val = 0x16020003 },
         { .reg = 0x00009888, .val = 0x17010003 },
         { .reg = 0x00009888, .val = 0x17020003 },
         { .reg = 0x00009888, .val = 0x00030030 },
         { .reg = 0x00009888, .val = 0x00072000 },
         { .reg = 0x00009888, .val = 0x0008CF00 },
         { .reg = 0x00009888, .val = 0x00090040 },
         { .reg = 0x00009888, .val = 0x000A6500 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x0C010017 },
         { .reg = 0x00009888, .val = 0x00010030 },
         { .reg = 0x00009888, .val = 0x000B0A00 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x0A0205C0 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x01070200 },
         { .reg = 0x00009888, .val = 0x01080C00 },
         { .reg = 0x00009888, .val = 0x01090010 },
         { .reg = 0x00009888, .val = 0x010A0600 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x0B010017 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x090205C0 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16010003 },
         { .reg = 0x00009888, .val = 0x16020003 },
         { .reg = 0x00009888, .val = 0x17010003 },
         { .reg = 0x00009888, .val = 0x17020003 },
         { .reg = 0x00009888, .val = 0x00030003 },
         { .reg = 0x00009888, .val = 0x00070020 },
         { .reg = 0x00009888, .val = 0x000800CF },
         { .reg = 0x00009888, .val = 0x00090004 },
         { .reg = 0x00009888, .val = 0x000A0065 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x08010017 },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x000B000A },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x060205C0 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x01070002 },
         { .reg = 0x00009888, .val = 0x0108000C },
         { .reg = 0x00009888, .val = 0x01090001 },
         { .reg = 0x00009888, .val = 0x010A0006 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x07010017 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03020000 },
         { .reg = 0x00009888, .val = 0x05020B80 },
         { .reg = 0x00009888, .val = 0x01020000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030520 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032061 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031063 },
         { .reg = 0x00009888, .val = 0x48030007 },
         { .reg = 0x00009888, .val = 0x4A030801 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032481 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext590__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext590__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext590__avg_gpu_core_frequency__max,acmgt3__ext590__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1379, 24, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1380, 28, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1381, 32, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1382, 36, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2297, 40, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2298, 44, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2299, 48, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2300, 52, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4813, 56, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe8__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4814, 60, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe9__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4815, 64, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe10__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4816, 68, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe11__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4817, 72, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe12__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4818, 76, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe13__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4819, 80, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe14__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4820, 84, percentage_max_float,acmgt3__ext590__pixel_post_process_output_ready_cpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext591_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext591";
   query->symbol_name = "Ext591";
   query->guid = "d3416b56-6640-4b2a-b81d-295287c90a22";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20860011 },
         { .reg = 0x00009888, .val = 0x20A60011 },
         { .reg = 0x00009888, .val = 0x20C60011 },
         { .reg = 0x00009888, .val = 0x20E60011 },
         { .reg = 0x00009888, .val = 0x04860180 },
         { .reg = 0x00009888, .val = 0x06862800 },
         { .reg = 0x00009888, .val = 0x08860595 },
         { .reg = 0x00009888, .val = 0x0A860017 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x04A60180 },
         { .reg = 0x00009888, .val = 0x0AA60500 },
         { .reg = 0x00009888, .val = 0x0CA60595 },
         { .reg = 0x00009888, .val = 0x0EA60017 },
         { .reg = 0x00009888, .val = 0x00A60000 },
         { .reg = 0x00009888, .val = 0x04C60180 },
         { .reg = 0x00009888, .val = 0x0EC60500 },
         { .reg = 0x00009888, .val = 0x10C60595 },
         { .reg = 0x00009888, .val = 0x12C60017 },
         { .reg = 0x00009888, .val = 0x02C60000 },
         { .reg = 0x00009888, .val = 0x04E60180 },
         { .reg = 0x00009888, .val = 0x12E60500 },
         { .reg = 0x00009888, .val = 0x14E60595 },
         { .reg = 0x00009888, .val = 0x16E60017 },
         { .reg = 0x00009888, .val = 0x02E60000 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext591__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext591__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext591__avg_gpu_core_frequency__max,acmgt3__ext591__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1674, 24, percentage_max_float,acmgt3__ext591__pixel_post_process_input_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1675, 28, percentage_max_float,acmgt3__ext591__pixel_post_process_input_available_cpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext592_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext592";
   query->symbol_name = "Ext592";
   query->guid = "0d6485c1-7bfb-4f49-98a4-6247c0597e31";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x21860011 },
         { .reg = 0x00009888, .val = 0x21A60011 },
         { .reg = 0x00009888, .val = 0x21C60011 },
         { .reg = 0x00009888, .val = 0x21E60011 },
         { .reg = 0x00009888, .val = 0x05860180 },
         { .reg = 0x00009888, .val = 0x07862800 },
         { .reg = 0x00009888, .val = 0x09860595 },
         { .reg = 0x00009888, .val = 0x0B860017 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x05A60180 },
         { .reg = 0x00009888, .val = 0x0BA60500 },
         { .reg = 0x00009888, .val = 0x0DA60595 },
         { .reg = 0x00009888, .val = 0x0FA60017 },
         { .reg = 0x00009888, .val = 0x01A60000 },
         { .reg = 0x00009888, .val = 0x05C60180 },
         { .reg = 0x00009888, .val = 0x0FC60500 },
         { .reg = 0x00009888, .val = 0x11C60595 },
         { .reg = 0x00009888, .val = 0x13C60017 },
         { .reg = 0x00009888, .val = 0x03C60000 },
         { .reg = 0x00009888, .val = 0x05E60180 },
         { .reg = 0x00009888, .val = 0x13E60500 },
         { .reg = 0x00009888, .val = 0x15E60595 },
         { .reg = 0x00009888, .val = 0x17E60017 },
         { .reg = 0x00009888, .val = 0x03E60000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext592__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext592__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext592__avg_gpu_core_frequency__max,acmgt3__ext592__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1676, 24, percentage_max_float,acmgt3__ext592__pixel_post_process_input_available_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1677, 28, percentage_max_float,acmgt3__ext592__pixel_post_process_input_available_cpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext593_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext593";
   query->symbol_name = "Ext593";
   query->guid = "7b4adfcb-b4fe-4e2b-803c-b9cfa2b2cd17";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x20860011 },
         { .reg = 0x00009888, .val = 0x20A60011 },
         { .reg = 0x00009888, .val = 0x20C60011 },
         { .reg = 0x00009888, .val = 0x20E60011 },
         { .reg = 0x00009888, .val = 0x04860180 },
         { .reg = 0x00009888, .val = 0x06862800 },
         { .reg = 0x00009888, .val = 0x08860595 },
         { .reg = 0x00009888, .val = 0x0A860017 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x04A60180 },
         { .reg = 0x00009888, .val = 0x0AA60500 },
         { .reg = 0x00009888, .val = 0x0CA60595 },
         { .reg = 0x00009888, .val = 0x0EA60017 },
         { .reg = 0x00009888, .val = 0x00A60000 },
         { .reg = 0x00009888, .val = 0x04C60180 },
         { .reg = 0x00009888, .val = 0x0EC60500 },
         { .reg = 0x00009888, .val = 0x10C60595 },
         { .reg = 0x00009888, .val = 0x12C60017 },
         { .reg = 0x00009888, .val = 0x02C60000 },
         { .reg = 0x00009888, .val = 0x04E60180 },
         { .reg = 0x00009888, .val = 0x12E60500 },
         { .reg = 0x00009888, .val = 0x14E60595 },
         { .reg = 0x00009888, .val = 0x16E60017 },
         { .reg = 0x00009888, .val = 0x02E60000 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext593__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext593__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext593__avg_gpu_core_frequency__max,acmgt3__ext593__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2289, 24, percentage_max_float,acmgt3__ext593__pixel_post_process_input_available_cpipe4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2290, 28, percentage_max_float,acmgt3__ext593__pixel_post_process_input_available_cpipe5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext594_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext594";
   query->symbol_name = "Ext594";
   query->guid = "35040db3-1214-41dc-b856-f26d3b553905";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x21860011 },
         { .reg = 0x00009888, .val = 0x21A60011 },
         { .reg = 0x00009888, .val = 0x21C60011 },
         { .reg = 0x00009888, .val = 0x21E60011 },
         { .reg = 0x00009888, .val = 0x05860180 },
         { .reg = 0x00009888, .val = 0x07862800 },
         { .reg = 0x00009888, .val = 0x09860595 },
         { .reg = 0x00009888, .val = 0x0B860017 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x05A60180 },
         { .reg = 0x00009888, .val = 0x0BA60500 },
         { .reg = 0x00009888, .val = 0x0DA60595 },
         { .reg = 0x00009888, .val = 0x0FA60017 },
         { .reg = 0x00009888, .val = 0x01A60000 },
         { .reg = 0x00009888, .val = 0x05C60180 },
         { .reg = 0x00009888, .val = 0x0FC60500 },
         { .reg = 0x00009888, .val = 0x11C60595 },
         { .reg = 0x00009888, .val = 0x13C60017 },
         { .reg = 0x00009888, .val = 0x03C60000 },
         { .reg = 0x00009888, .val = 0x05E60180 },
         { .reg = 0x00009888, .val = 0x13E60500 },
         { .reg = 0x00009888, .val = 0x15E60595 },
         { .reg = 0x00009888, .val = 0x17E60017 },
         { .reg = 0x00009888, .val = 0x03E60000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext594__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext594__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext594__avg_gpu_core_frequency__max,acmgt3__ext594__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2291, 24, percentage_max_float,acmgt3__ext594__pixel_post_process_input_available_cpipe6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2292, 28, percentage_max_float,acmgt3__ext594__pixel_post_process_input_available_cpipe7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext595_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext595";
   query->symbol_name = "Ext595";
   query->guid = "3279a141-6b9b-4f1b-a38d-2bd7386c46dc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x20860011 },
         { .reg = 0x00009888, .val = 0x20A60011 },
         { .reg = 0x00009888, .val = 0x20C60011 },
         { .reg = 0x00009888, .val = 0x20E60011 },
         { .reg = 0x00009888, .val = 0x04860180 },
         { .reg = 0x00009888, .val = 0x06862800 },
         { .reg = 0x00009888, .val = 0x08860595 },
         { .reg = 0x00009888, .val = 0x0A860017 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x04A60180 },
         { .reg = 0x00009888, .val = 0x0AA60500 },
         { .reg = 0x00009888, .val = 0x0CA60595 },
         { .reg = 0x00009888, .val = 0x0EA60017 },
         { .reg = 0x00009888, .val = 0x00A60000 },
         { .reg = 0x00009888, .val = 0x04C60180 },
         { .reg = 0x00009888, .val = 0x0EC60500 },
         { .reg = 0x00009888, .val = 0x10C60595 },
         { .reg = 0x00009888, .val = 0x12C60017 },
         { .reg = 0x00009888, .val = 0x02C60000 },
         { .reg = 0x00009888, .val = 0x04E60180 },
         { .reg = 0x00009888, .val = 0x12E60500 },
         { .reg = 0x00009888, .val = 0x14E60595 },
         { .reg = 0x00009888, .val = 0x16E60017 },
         { .reg = 0x00009888, .val = 0x02E60000 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext595__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext595__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext595__avg_gpu_core_frequency__max,acmgt3__ext595__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4821, 24, percentage_max_float,acmgt3__ext595__pixel_post_process_input_available_cpipe8__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4822, 28, percentage_max_float,acmgt3__ext595__pixel_post_process_input_available_cpipe9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext596_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext596";
   query->symbol_name = "Ext596";
   query->guid = "2a08b276-0fb8-4c89-bbed-57892a7c9542";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x21860011 },
         { .reg = 0x00009888, .val = 0x21A60011 },
         { .reg = 0x00009888, .val = 0x21C60011 },
         { .reg = 0x00009888, .val = 0x21E60011 },
         { .reg = 0x00009888, .val = 0x05860180 },
         { .reg = 0x00009888, .val = 0x07862800 },
         { .reg = 0x00009888, .val = 0x09860595 },
         { .reg = 0x00009888, .val = 0x0B860017 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x05A60180 },
         { .reg = 0x00009888, .val = 0x0BA60500 },
         { .reg = 0x00009888, .val = 0x0DA60595 },
         { .reg = 0x00009888, .val = 0x0FA60017 },
         { .reg = 0x00009888, .val = 0x01A60000 },
         { .reg = 0x00009888, .val = 0x05C60180 },
         { .reg = 0x00009888, .val = 0x0FC60500 },
         { .reg = 0x00009888, .val = 0x11C60595 },
         { .reg = 0x00009888, .val = 0x13C60017 },
         { .reg = 0x00009888, .val = 0x03C60000 },
         { .reg = 0x00009888, .val = 0x05E60180 },
         { .reg = 0x00009888, .val = 0x13E60500 },
         { .reg = 0x00009888, .val = 0x15E60595 },
         { .reg = 0x00009888, .val = 0x17E60017 },
         { .reg = 0x00009888, .val = 0x03E60000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext596__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext596__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext596__avg_gpu_core_frequency__max,acmgt3__ext596__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4823, 24, percentage_max_float,acmgt3__ext596__pixel_post_process_input_available_cpipe10__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4824, 28, percentage_max_float,acmgt3__ext596__pixel_post_process_input_available_cpipe11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext597_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext597";
   query->symbol_name = "Ext597";
   query->guid = "2628efb2-4b7c-4d88-8a03-620235fd1014";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x20860011 },
         { .reg = 0x00009888, .val = 0x20A60011 },
         { .reg = 0x00009888, .val = 0x20C60011 },
         { .reg = 0x00009888, .val = 0x20E60011 },
         { .reg = 0x00009888, .val = 0x04860180 },
         { .reg = 0x00009888, .val = 0x06862800 },
         { .reg = 0x00009888, .val = 0x08860595 },
         { .reg = 0x00009888, .val = 0x0A860017 },
         { .reg = 0x00009888, .val = 0x00860000 },
         { .reg = 0x00009888, .val = 0x04A60180 },
         { .reg = 0x00009888, .val = 0x0AA60500 },
         { .reg = 0x00009888, .val = 0x0CA60595 },
         { .reg = 0x00009888, .val = 0x0EA60017 },
         { .reg = 0x00009888, .val = 0x00A60000 },
         { .reg = 0x00009888, .val = 0x04C60180 },
         { .reg = 0x00009888, .val = 0x0EC60500 },
         { .reg = 0x00009888, .val = 0x10C60595 },
         { .reg = 0x00009888, .val = 0x12C60017 },
         { .reg = 0x00009888, .val = 0x02C60000 },
         { .reg = 0x00009888, .val = 0x04E60180 },
         { .reg = 0x00009888, .val = 0x12E60500 },
         { .reg = 0x00009888, .val = 0x14E60595 },
         { .reg = 0x00009888, .val = 0x16E60017 },
         { .reg = 0x00009888, .val = 0x02E60000 },
         { .reg = 0x00009888, .val = 0x020755AA },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0009FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x020C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext597__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext597__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext597__avg_gpu_core_frequency__max,acmgt3__ext597__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4825, 24, percentage_max_float,acmgt3__ext597__pixel_post_process_input_available_cpipe12__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4826, 28, percentage_max_float,acmgt3__ext597__pixel_post_process_input_available_cpipe13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext598_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext598";
   query->symbol_name = "Ext598";
   query->guid = "b45e047d-88d6-4234-89f1-2b3763e2ec7c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x21860011 },
         { .reg = 0x00009888, .val = 0x21A60011 },
         { .reg = 0x00009888, .val = 0x21C60011 },
         { .reg = 0x00009888, .val = 0x21E60011 },
         { .reg = 0x00009888, .val = 0x05860180 },
         { .reg = 0x00009888, .val = 0x07862800 },
         { .reg = 0x00009888, .val = 0x09860595 },
         { .reg = 0x00009888, .val = 0x0B860017 },
         { .reg = 0x00009888, .val = 0x01860000 },
         { .reg = 0x00009888, .val = 0x05A60180 },
         { .reg = 0x00009888, .val = 0x0BA60500 },
         { .reg = 0x00009888, .val = 0x0DA60595 },
         { .reg = 0x00009888, .val = 0x0FA60017 },
         { .reg = 0x00009888, .val = 0x01A60000 },
         { .reg = 0x00009888, .val = 0x05C60180 },
         { .reg = 0x00009888, .val = 0x0FC60500 },
         { .reg = 0x00009888, .val = 0x11C60595 },
         { .reg = 0x00009888, .val = 0x13C60017 },
         { .reg = 0x00009888, .val = 0x03C60000 },
         { .reg = 0x00009888, .val = 0x05E60180 },
         { .reg = 0x00009888, .val = 0x13E60500 },
         { .reg = 0x00009888, .val = 0x15E60595 },
         { .reg = 0x00009888, .val = 0x17E60017 },
         { .reg = 0x00009888, .val = 0x03E60000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x030755AA },
         { .reg = 0x00009888, .val = 0x0108FFAA },
         { .reg = 0x00009888, .val = 0x0109FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x010100F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x01020F00 },
         { .reg = 0x00009888, .val = 0x030C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x4203084A },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030062 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext598__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext598__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext598__avg_gpu_core_frequency__max,acmgt3__ext598__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4827, 24, percentage_max_float,acmgt3__ext598__pixel_post_process_input_available_cpipe14__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4828, 28, percentage_max_float,acmgt3__ext598__pixel_post_process_input_available_cpipe15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext599_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext599";
   query->symbol_name = "Ext599";
   query->guid = "8f41dd6c-778f-4060-b8ab-13e66e76d4ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x14060700 },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x02060010 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x06060081 },
         { .reg = 0x00009888, .val = 0x080603C3 },
         { .reg = 0x00009888, .val = 0x0A06034E },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x00081555 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x16087840 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x0E080C40 },
         { .reg = 0x00009888, .val = 0x10080438 },
         { .reg = 0x00009888, .val = 0x12080BA7 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030012 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030005 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x400314A5 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext599__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext599__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext599__avg_gpu_core_frequency__max,acmgt3__ext599__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1347, 24, percentage_max_float,acmgt3__ext599__amfs_stall_all_input_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1348, 28, percentage_max_float,acmgt3__ext599__amfs_stall_any_input_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1349, 32, NULL,acmgt3__ext599__amfs_cache_hit_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1350, 40, NULL,acmgt3__ext599__amfs_cache_miss_slice0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1351, 48, NULL,acmgt3__ext599__render_cache_hit_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1352, 56, NULL,acmgt3__ext599__render_cache_read_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1353, 64, NULL,acmgt3__ext599__render_cache_write_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 1354, 72, percentage_max_float,acmgt3__ext599__render_cache_input_available_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 1355, 76, percentage_max_float,acmgt3__ext599__render_cache_output_ready_l3_node0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext600_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext600";
   query->symbol_name = "Ext600";
   query->guid = "c0cc46d1-0475-478d-ad6f-cbef207c1ccb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x15060700 },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x03060010 },
         { .reg = 0x00009888, .val = 0x05060000 },
         { .reg = 0x00009888, .val = 0x07060081 },
         { .reg = 0x00009888, .val = 0x090603C3 },
         { .reg = 0x00009888, .val = 0x0B06034E },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01081555 },
         { .reg = 0x00009888, .val = 0x010A1555 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x16037840 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x0E030C40 },
         { .reg = 0x00009888, .val = 0x10030438 },
         { .reg = 0x00009888, .val = 0x12030BA7 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x0204AA80 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030012 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x2003F000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext600__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext600__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext600__avg_gpu_core_frequency__max,acmgt3__ext600__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1356, 24, percentage_max_float,acmgt3__ext600__amfs_stall_all_input_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1357, 28, percentage_max_float,acmgt3__ext600__amfs_stall_any_input_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1358, 32, NULL,acmgt3__ext600__amfs_cache_hit_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1359, 40, NULL,acmgt3__ext600__amfs_cache_miss_slice1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1360, 48, NULL,acmgt3__ext600__render_cache_hit_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1361, 56, NULL,acmgt3__ext600__render_cache_read_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1362, 64, NULL,acmgt3__ext600__render_cache_write_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 1363, 72, percentage_max_float,acmgt3__ext600__render_cache_input_available_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 1364, 76, percentage_max_float,acmgt3__ext600__render_cache_output_ready_l3_node1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext601_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext601";
   query->symbol_name = "Ext601";
   query->guid = "11c7bdc4-a63a-46cb-a967-33ded50ecd42";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x14060700 },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x02060010 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x06060081 },
         { .reg = 0x00009888, .val = 0x080603C3 },
         { .reg = 0x00009888, .val = 0x0A06034E },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x00081555 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x16087840 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x0E080C40 },
         { .reg = 0x00009888, .val = 0x10080438 },
         { .reg = 0x00009888, .val = 0x12080BA7 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030012 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030005 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x400314A5 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext601__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext601__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext601__avg_gpu_core_frequency__max,acmgt3__ext601__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2261, 24, percentage_max_float,acmgt3__ext601__amfs_stall_all_input_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2260, 28, percentage_max_float,acmgt3__ext601__amfs_stall_any_input_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2257, 32, NULL,acmgt3__ext601__amfs_cache_hit_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2258, 40, NULL,acmgt3__ext601__amfs_cache_miss_slice2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2273, 48, NULL,acmgt3__ext601__render_cache_hit_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2274, 56, NULL,acmgt3__ext601__render_cache_read_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2275, 64, NULL,acmgt3__ext601__render_cache_write_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2276, 72, percentage_max_float,acmgt3__ext601__render_cache_input_available_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2277, 76, percentage_max_float,acmgt3__ext601__render_cache_output_ready_l3_node2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext602_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext602";
   query->symbol_name = "Ext602";
   query->guid = "d7899495-d4d2-4235-8670-dd0ee48cc477";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x15060700 },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x03060010 },
         { .reg = 0x00009888, .val = 0x05060000 },
         { .reg = 0x00009888, .val = 0x07060081 },
         { .reg = 0x00009888, .val = 0x090603C3 },
         { .reg = 0x00009888, .val = 0x0B06034E },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01081555 },
         { .reg = 0x00009888, .val = 0x010A1555 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x16037840 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x0E030C40 },
         { .reg = 0x00009888, .val = 0x10030438 },
         { .reg = 0x00009888, .val = 0x12030BA7 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x0204AA80 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x0208FFC0 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030012 },
         { .reg = 0x00009888, .val = 0x04032490 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x2003F000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext602__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext602__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext602__avg_gpu_core_frequency__max,acmgt3__ext602__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2266, 24, percentage_max_float,acmgt3__ext602__amfs_stall_all_input_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2265, 28, percentage_max_float,acmgt3__ext602__amfs_stall_any_input_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2262, 32, NULL,acmgt3__ext602__amfs_cache_hit_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2263, 40, NULL,acmgt3__ext602__amfs_cache_miss_slice3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2278, 48, NULL,acmgt3__ext602__render_cache_hit_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2279, 56, NULL,acmgt3__ext602__render_cache_read_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2280, 64, NULL,acmgt3__ext602__render_cache_write_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2281, 72, percentage_max_float,acmgt3__ext602__render_cache_input_available_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_float(query, 2282, 76, percentage_max_float,acmgt3__ext602__render_cache_output_ready_l3_node3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext603_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext603";
   query->symbol_name = "Ext603";
   query->guid = "b58e27fd-3505-4a89-a83f-0767b2f949fd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x14060700 },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x02060010 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x06060081 },
         { .reg = 0x00009888, .val = 0x080603C3 },
         { .reg = 0x00009888, .val = 0x0A06034E },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x00081555 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x16087840 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x0E080C40 },
         { .reg = 0x00009888, .val = 0x10080438 },
         { .reg = 0x00009888, .val = 0x12080BA7 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030009 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030005 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x400314A5 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext603__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext603__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext603__avg_gpu_core_frequency__max,acmgt3__ext603__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4829, 24, percentage_max_float,acmgt3__ext603__amfs_stall_all_input_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4830, 28, percentage_max_float,acmgt3__ext603__amfs_stall_any_input_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4831, 32, NULL,acmgt3__ext603__amfs_cache_hit_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4832, 40, NULL,acmgt3__ext603__amfs_cache_miss_slice4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4833, 48, NULL,acmgt3__ext603__render_cache_hit_l3_node4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4834, 56, NULL,acmgt3__ext603__render_cache_read_l3_node4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4835, 64, NULL,acmgt3__ext603__render_cache_write_l3_node4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 4836, 72, percentage_max_float,acmgt3__ext603__render_cache_input_available_l3_node4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 4837, 76, percentage_max_float,acmgt3__ext603__render_cache_output_ready_l3_node4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext604_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext604";
   query->symbol_name = "Ext604";
   query->guid = "abf8d7f4-395b-4c43-aaf7-e327cb5a3dc6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x15060700 },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x03060010 },
         { .reg = 0x00009888, .val = 0x05060000 },
         { .reg = 0x00009888, .val = 0x07060081 },
         { .reg = 0x00009888, .val = 0x090603C3 },
         { .reg = 0x00009888, .val = 0x0B06034E },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01081555 },
         { .reg = 0x00009888, .val = 0x010A1555 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x16037840 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x0E030C40 },
         { .reg = 0x00009888, .val = 0x10030438 },
         { .reg = 0x00009888, .val = 0x12030BA7 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x0204AA80 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x02025540 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030009 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x2003F000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext604__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext604__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext604__avg_gpu_core_frequency__max,acmgt3__ext604__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4838, 24, percentage_max_float,acmgt3__ext604__amfs_stall_all_input_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4839, 28, percentage_max_float,acmgt3__ext604__amfs_stall_any_input_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4840, 32, NULL,acmgt3__ext604__amfs_cache_hit_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4841, 40, NULL,acmgt3__ext604__amfs_cache_miss_slice5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4842, 48, NULL,acmgt3__ext604__render_cache_hit_l3_node5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4843, 56, NULL,acmgt3__ext604__render_cache_read_l3_node5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4844, 64, NULL,acmgt3__ext604__render_cache_write_l3_node5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 4845, 72, percentage_max_float,acmgt3__ext604__render_cache_input_available_l3_node5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_float(query, 4846, 76, percentage_max_float,acmgt3__ext604__render_cache_output_ready_l3_node5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext605_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext605";
   query->symbol_name = "Ext605";
   query->guid = "44fa1922-0aca-4a6b-8adc-78e764982068";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x14060700 },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x02060010 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x06060081 },
         { .reg = 0x00009888, .val = 0x080603C3 },
         { .reg = 0x00009888, .val = 0x0A06034E },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x00081555 },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x14087800 },
         { .reg = 0x00009888, .val = 0x16087840 },
         { .reg = 0x00009888, .val = 0x18080126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x0E080C40 },
         { .reg = 0x00009888, .val = 0x10080438 },
         { .reg = 0x00009888, .val = 0x12080BA7 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00022AAA },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030009 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030005 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x400314A5 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext605__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext605__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext605__avg_gpu_core_frequency__max,acmgt3__ext605__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4847, 24, percentage_max_float,acmgt3__ext605__amfs_stall_all_input_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4848, 28, percentage_max_float,acmgt3__ext605__amfs_stall_any_input_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4849, 32, NULL,acmgt3__ext605__amfs_cache_hit_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4850, 40, NULL,acmgt3__ext605__amfs_cache_miss_slice6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4851, 48, NULL,acmgt3__ext605__render_cache_hit_l3_node6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4852, 56, NULL,acmgt3__ext605__render_cache_read_l3_node6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4853, 64, NULL,acmgt3__ext605__render_cache_write_l3_node6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 4854, 72, percentage_max_float,acmgt3__ext605__render_cache_input_available_l3_node6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 4855, 76, percentage_max_float,acmgt3__ext605__render_cache_output_ready_l3_node6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext606_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext606";
   query->symbol_name = "Ext606";
   query->guid = "1d5881b6-188f-4dfd-9a06-08df383da728";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x15060700 },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x0003007F },
         { .reg = 0x00009888, .val = 0x00083FFF },
         { .reg = 0x00009888, .val = 0x000A1555 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x000B2AAA },
         { .reg = 0x00009888, .val = 0x03060010 },
         { .reg = 0x00009888, .val = 0x05060000 },
         { .reg = 0x00009888, .val = 0x07060081 },
         { .reg = 0x00009888, .val = 0x090603C3 },
         { .reg = 0x00009888, .val = 0x0B06034E },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01081555 },
         { .reg = 0x00009888, .val = 0x010A1555 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x14037800 },
         { .reg = 0x00009888, .val = 0x16037840 },
         { .reg = 0x00009888, .val = 0x18030126 },
         { .reg = 0x00009888, .val = 0x0001007F },
         { .reg = 0x00009888, .val = 0x00021555 },
         { .reg = 0x00009888, .val = 0x0E030C40 },
         { .reg = 0x00009888, .val = 0x10030438 },
         { .reg = 0x00009888, .val = 0x12030BA7 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x0204AA80 },
         { .reg = 0x00009888, .val = 0x00051555 },
         { .reg = 0x00009888, .val = 0x02055540 },
         { .reg = 0x00009888, .val = 0x00082AAA },
         { .reg = 0x00009888, .val = 0x0208AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00022AAA },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030009 },
         { .reg = 0x00009888, .val = 0x04031248 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A03F000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E03F000 },
         { .reg = 0x00009888, .val = 0x2003F000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00100030 },
         { .reg = 0x0000D944, .val = 0x0000FFF9 },
         { .reg = 0x0000D948, .val = 0x0000001A },
         { .reg = 0x0000D94C, .val = 0x0000FFFC },
         { .reg = 0x0000D950, .val = 0x00000062 },
         { .reg = 0x0000D954, .val = 0x0000FFF3 },
         { .reg = 0x0000D958, .val = 0x0000007A },
         { .reg = 0x0000D95C, .val = 0x0000FFF0 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext606__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext606__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext606__avg_gpu_core_frequency__max,acmgt3__ext606__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4856, 24, percentage_max_float,acmgt3__ext606__amfs_stall_all_input_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4857, 28, percentage_max_float,acmgt3__ext606__amfs_stall_any_input_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4858, 32, NULL,acmgt3__ext606__amfs_cache_hit_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4859, 40, NULL,acmgt3__ext606__amfs_cache_miss_slice7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4860, 48, NULL,acmgt3__ext606__render_cache_hit_l3_node7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4861, 56, NULL,acmgt3__ext606__render_cache_read_l3_node7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 4862, 64, NULL,acmgt3__ext606__render_cache_write_l3_node7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 4863, 72, percentage_max_float,acmgt3__ext606__render_cache_input_available_l3_node7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_float(query, 4864, 76, percentage_max_float,acmgt3__ext606__render_cache_output_ready_l3_node7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext607_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext607";
   query->symbol_name = "Ext607";
   query->guid = "4542bc83-0786-4a99-977c-52a7f0418de1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x0003000C },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x04060E00 },
         { .reg = 0x00009888, .val = 0x06060006 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x000800F5 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000C },
         { .reg = 0x00009888, .val = 0x000B00A0 },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x070601C0 },
         { .reg = 0x00009888, .val = 0x09060006 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01080050 },
         { .reg = 0x00009888, .val = 0x010A0050 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x000300C0 },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x080601C0 },
         { .reg = 0x00009888, .val = 0x0A060006 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0008F500 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x000100C0 },
         { .reg = 0x00009888, .val = 0x000BA000 },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x0B0601C0 },
         { .reg = 0x00009888, .val = 0x0D060006 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01085000 },
         { .reg = 0x00009888, .val = 0x010A5000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x00030C00 },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x0C0601C0 },
         { .reg = 0x00009888, .val = 0x0E060006 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x020800F5 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010C00 },
         { .reg = 0x00009888, .val = 0x020B00A0 },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x0F0601C0 },
         { .reg = 0x00009888, .val = 0x11060006 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03080050 },
         { .reg = 0x00009888, .val = 0x030A0050 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1606001A },
         { .reg = 0x00009888, .val = 0x1706001A },
         { .reg = 0x00009888, .val = 0x0003C000 },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x100601C0 },
         { .reg = 0x00009888, .val = 0x12060006 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0208F500 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001C000 },
         { .reg = 0x00009888, .val = 0x020BA000 },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x130601C0 },
         { .reg = 0x00009888, .val = 0x15060006 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03085000 },
         { .reg = 0x00009888, .val = 0x030A5000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0202AA55 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030009 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42030520 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030D21 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030209 },
         { .reg = 0x00009888, .val = 0x48030610 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40030108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext607__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext607__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext607__avg_gpu_core_frequency__max,acmgt3__ext607__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1373, 24, NULL,acmgt3__ext607__amfs_4_x4_shading_request_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1374, 32, NULL,acmgt3__ext607__amfs_4_x4_shading_request_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2259, 40, NULL,acmgt3__ext607__amfs_4_x4_shading_request_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2264, 48, NULL,acmgt3__ext607__amfs_4_x4_shading_request_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4865, 56, NULL,acmgt3__ext607__amfs_4_x4_shading_request_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4866, 64, NULL,acmgt3__ext607__amfs_4_x4_shading_request_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4867, 72, NULL,acmgt3__ext607__amfs_4_x4_shading_request_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4868, 80, NULL,acmgt3__ext607__amfs_4_x4_shading_request_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext608_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext608";
   query->symbol_name = "Ext608";
   query->guid = "8dcf0fe7-8df6-4abc-a15d-26dcdb7634f0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1606014C },
         { .reg = 0x00009888, .val = 0x1706014C },
         { .reg = 0x00009888, .val = 0x0003000C },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x04060E00 },
         { .reg = 0x00009888, .val = 0x06060008 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x000800F5 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000C },
         { .reg = 0x00009888, .val = 0x000B00A0 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x070601C0 },
         { .reg = 0x00009888, .val = 0x09060008 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01080050 },
         { .reg = 0x00009888, .val = 0x010A0050 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1606014C },
         { .reg = 0x00009888, .val = 0x1706014C },
         { .reg = 0x00009888, .val = 0x000300C0 },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x080601C0 },
         { .reg = 0x00009888, .val = 0x0A060008 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0008F500 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x000100C0 },
         { .reg = 0x00009888, .val = 0x000BA000 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x0B0601C0 },
         { .reg = 0x00009888, .val = 0x0D060008 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01085000 },
         { .reg = 0x00009888, .val = 0x010A5000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1606014C },
         { .reg = 0x00009888, .val = 0x1706014C },
         { .reg = 0x00009888, .val = 0x00030C00 },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x0C0601C0 },
         { .reg = 0x00009888, .val = 0x0E060008 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x020800F5 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010C00 },
         { .reg = 0x00009888, .val = 0x020B00A0 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x0F0601C0 },
         { .reg = 0x00009888, .val = 0x11060008 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03080050 },
         { .reg = 0x00009888, .val = 0x030A0050 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1606014C },
         { .reg = 0x00009888, .val = 0x1706014C },
         { .reg = 0x00009888, .val = 0x0003C000 },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x100601C0 },
         { .reg = 0x00009888, .val = 0x12060008 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0208F500 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001C000 },
         { .reg = 0x00009888, .val = 0x020BA000 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x130601C0 },
         { .reg = 0x00009888, .val = 0x15060008 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03085000 },
         { .reg = 0x00009888, .val = 0x030A5000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0202AA55 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030009 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42030520 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030D21 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030209 },
         { .reg = 0x00009888, .val = 0x48030610 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40030108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext608__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext608__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext608__avg_gpu_core_frequency__max,acmgt3__ext608__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1389, 24, NULL,acmgt3__ext608__amfs_l3_atomic_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1390, 32, NULL,acmgt3__ext608__amfs_l3_atomic_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2267, 40, NULL,acmgt3__ext608__amfs_l3_atomic_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2268, 48, NULL,acmgt3__ext608__amfs_l3_atomic_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4869, 56, NULL,acmgt3__ext608__amfs_l3_atomic_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4870, 64, NULL,acmgt3__ext608__amfs_l3_atomic_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4871, 72, NULL,acmgt3__ext608__amfs_l3_atomic_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4872, 80, NULL,acmgt3__ext608__amfs_l3_atomic_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext609_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext609";
   query->symbol_name = "Ext609";
   query->guid = "ee320b1d-1350-4b3a-bcbf-9de658bcd8f5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1606000C },
         { .reg = 0x00009888, .val = 0x1706000C },
         { .reg = 0x00009888, .val = 0x00034000 },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x14060007 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x02087000 },
         { .reg = 0x00009888, .val = 0x020A5000 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x130601C0 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03081000 },
         { .reg = 0x00009888, .val = 0x030A1000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1606000C },
         { .reg = 0x00009888, .val = 0x1706000C },
         { .reg = 0x00009888, .val = 0x00031000 },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x12060007 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x02080700 },
         { .reg = 0x00009888, .val = 0x020A0500 },
         { .reg = 0x00009888, .val = 0x00011000 },
         { .reg = 0x00009888, .val = 0x020B0200 },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x110601C0 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03080100 },
         { .reg = 0x00009888, .val = 0x030A0100 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1606000C },
         { .reg = 0x00009888, .val = 0x1706000C },
         { .reg = 0x00009888, .val = 0x00030400 },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x10060007 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x02080070 },
         { .reg = 0x00009888, .val = 0x020A0050 },
         { .reg = 0x00009888, .val = 0x00010400 },
         { .reg = 0x00009888, .val = 0x020B0020 },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x0F0601C0 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03080010 },
         { .reg = 0x00009888, .val = 0x030A0010 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1606000C },
         { .reg = 0x00009888, .val = 0x1706000C },
         { .reg = 0x00009888, .val = 0x00030100 },
         { .reg = 0x00009888, .val = 0x02060002 },
         { .reg = 0x00009888, .val = 0x0E060007 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x02080007 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x00010100 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x03060002 },
         { .reg = 0x00009888, .val = 0x0D0601C0 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03080001 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x0202005A },
         { .reg = 0x00009888, .val = 0x02031200 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x3E032000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030521 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009888, .val = 0x42030009 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001C000 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x02050500 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010C00 },
         { .reg = 0x00009888, .val = 0x02020050 },
         { .reg = 0x00009888, .val = 0x02040050 },
         { .reg = 0x00009888, .val = 0x02050050 },
         { .reg = 0x00009888, .val = 0x020800A0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010300 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext609__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext609__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext609__avg_gpu_core_frequency__max,acmgt3__ext609__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1387, 24, NULL,acmgt3__ext609__amfs_l3_access_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1388, 32, NULL,acmgt3__ext609__amfs_l3_access_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2269, 40, NULL,acmgt3__ext609__amfs_l3_access_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2270, 48, NULL,acmgt3__ext609__amfs_l3_access_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4873, 56, NULL,acmgt3__ext609__amfs_l3_access_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4874, 64, NULL,acmgt3__ext609__amfs_l3_access_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4875, 72, NULL,acmgt3__ext609__amfs_l3_access_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4876, 80, NULL,acmgt3__ext609__amfs_l3_access_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext610_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext610";
   query->symbol_name = "Ext610";
   query->guid = "2530a673-a35d-4646-82c3-a8c3330c1baf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1606014C },
         { .reg = 0x00009888, .val = 0x1706014C },
         { .reg = 0x00009888, .val = 0x0003000C },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x04060E00 },
         { .reg = 0x00009888, .val = 0x06060008 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x000800F5 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000C },
         { .reg = 0x00009888, .val = 0x000B00A0 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x070601C0 },
         { .reg = 0x00009888, .val = 0x09060008 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01080050 },
         { .reg = 0x00009888, .val = 0x010A0050 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1606014C },
         { .reg = 0x00009888, .val = 0x1706014C },
         { .reg = 0x00009888, .val = 0x000300C0 },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x080601C0 },
         { .reg = 0x00009888, .val = 0x0A060008 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0008F500 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x000100C0 },
         { .reg = 0x00009888, .val = 0x000BA000 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x0B0601C0 },
         { .reg = 0x00009888, .val = 0x0D060008 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x01085000 },
         { .reg = 0x00009888, .val = 0x010A5000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1606014C },
         { .reg = 0x00009888, .val = 0x1706014C },
         { .reg = 0x00009888, .val = 0x00030C00 },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x0C0601C0 },
         { .reg = 0x00009888, .val = 0x0E060008 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x020800F5 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010C00 },
         { .reg = 0x00009888, .val = 0x020B00A0 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x0F0601C0 },
         { .reg = 0x00009888, .val = 0x11060008 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03080050 },
         { .reg = 0x00009888, .val = 0x030A0050 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1606014C },
         { .reg = 0x00009888, .val = 0x1706014C },
         { .reg = 0x00009888, .val = 0x0003C000 },
         { .reg = 0x00009888, .val = 0x0206001A },
         { .reg = 0x00009888, .val = 0x100601C0 },
         { .reg = 0x00009888, .val = 0x12060008 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0208F500 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001C000 },
         { .reg = 0x00009888, .val = 0x020BA000 },
         { .reg = 0x00009888, .val = 0x0306001A },
         { .reg = 0x00009888, .val = 0x130601C0 },
         { .reg = 0x00009888, .val = 0x15060008 },
         { .reg = 0x00009888, .val = 0x01060000 },
         { .reg = 0x00009888, .val = 0x03085000 },
         { .reg = 0x00009888, .val = 0x030A5000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0202AA55 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030009 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42030520 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030D21 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030209 },
         { .reg = 0x00009888, .val = 0x48030610 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40030108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext610__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext610__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext610__avg_gpu_core_frequency__max,acmgt3__ext610__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1782, 24, NULL,acmgt3__ext610__amfs_l3_write_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1783, 32, NULL,acmgt3__ext610__amfs_l3_write_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2271, 40, NULL,acmgt3__ext610__amfs_l3_write_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2272, 48, NULL,acmgt3__ext610__amfs_l3_write_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4877, 56, NULL,acmgt3__ext610__amfs_l3_write_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4878, 64, NULL,acmgt3__ext610__amfs_l3_write_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4879, 72, NULL,acmgt3__ext610__amfs_l3_write_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4880, 80, NULL,acmgt3__ext610__amfs_l3_write_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext611_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext611";
   query->symbol_name = "Ext611";
   query->guid = "bb03aede-d6b2-4a50-a851-cdbaaa918df9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C073C00 },
         { .reg = 0x00009888, .val = 0x14090440 },
         { .reg = 0x00009888, .val = 0x16090013 },
         { .reg = 0x00009888, .val = 0x1D073C00 },
         { .reg = 0x00009888, .val = 0x15090440 },
         { .reg = 0x00009888, .val = 0x17090013 },
         { .reg = 0x00009888, .val = 0x00034038 },
         { .reg = 0x00009888, .val = 0x06070000 },
         { .reg = 0x00009888, .val = 0x16070034 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009888, .val = 0x02090010 },
         { .reg = 0x00009888, .val = 0x04090A00 },
         { .reg = 0x00009888, .val = 0x0609034A },
         { .reg = 0x00009888, .val = 0x00098000 },
         { .reg = 0x00009888, .val = 0x000A056A },
         { .reg = 0x00009888, .val = 0x020A9000 },
         { .reg = 0x00009888, .val = 0x00014038 },
         { .reg = 0x00009888, .val = 0x000B0A80 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x07070000 },
         { .reg = 0x00009888, .val = 0x15070D00 },
         { .reg = 0x00009888, .val = 0x05070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x03090010 },
         { .reg = 0x00009888, .val = 0x09090285 },
         { .reg = 0x00009888, .val = 0x0B09000D },
         { .reg = 0x00009888, .val = 0x01094000 },
         { .reg = 0x00009888, .val = 0x010A0A80 },
         { .reg = 0x00009888, .val = 0x030A2000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C073C00 },
         { .reg = 0x00009888, .val = 0x14090440 },
         { .reg = 0x00009888, .val = 0x16090013 },
         { .reg = 0x00009888, .val = 0x1D073C00 },
         { .reg = 0x00009888, .val = 0x15090440 },
         { .reg = 0x00009888, .val = 0x17090013 },
         { .reg = 0x00009888, .val = 0x00031E00 },
         { .reg = 0x00009888, .val = 0x06070000 },
         { .reg = 0x00009888, .val = 0x14070034 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x020803FC },
         { .reg = 0x00009888, .val = 0x02090010 },
         { .reg = 0x00009888, .val = 0x0A090140 },
         { .reg = 0x00009888, .val = 0x0C09034A },
         { .reg = 0x00009888, .val = 0x00092000 },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020A0956 },
         { .reg = 0x00009888, .val = 0x00011E00 },
         { .reg = 0x00009888, .val = 0x020B02A8 },
         { .reg = 0x00009888, .val = 0x07070000 },
         { .reg = 0x00009888, .val = 0x13070D00 },
         { .reg = 0x00009888, .val = 0x05070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x03090010 },
         { .reg = 0x00009888, .val = 0x0F090285 },
         { .reg = 0x00009888, .val = 0x1109000D },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A02A8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FAAA },
         { .reg = 0x00009888, .val = 0x0208AFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E031081 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42030428 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x460302E4 },
         { .reg = 0x00009888, .val = 0x48030E17 },
         { .reg = 0x00009888, .val = 0x4A030801 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030100 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001C03F },
         { .reg = 0x00009888, .val = 0x00020555 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00050555 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00013FC0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02020555 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040555 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02050555 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x02080AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x0000000A },
         { .reg = 0x0000D94C, .val = 0x0000FFFA },
         { .reg = 0x0000D950, .val = 0x000000C2 },
         { .reg = 0x0000D954, .val = 0x0000FFE7 },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000FFD7 },
         { .reg = 0x0000D960, .val = 0x00000602 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FEBF },
         { .reg = 0x0000D970, .val = 0x00003002 },
         { .reg = 0x0000D974, .val = 0x0000F9FF },
         { .reg = 0x0000D978, .val = 0x00001002 },
         { .reg = 0x0000D97C, .val = 0x0000F5FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext611__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext611__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext611__avg_gpu_core_frequency__max,acmgt3__ext611__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1395, 24, NULL,acmgt3__ext611__clipper_input_vertex_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1396, 32, NULL,acmgt3__ext611__clipper_input_vertex_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2447, 40, NULL,acmgt3__ext611__clipper_input_vertex_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2448, 48, NULL,acmgt3__ext611__clipper_input_vertex_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1397, 56, NULL,acmgt3__ext611__streamout_output_vertex_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1398, 64, NULL,acmgt3__ext611__streamout_output_vertex_count_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2449, 72, NULL,acmgt3__ext611__streamout_output_vertex_count_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2450, 80, NULL,acmgt3__ext611__streamout_output_vertex_count_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext612_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext612";
   query->symbol_name = "Ext612";
   query->guid = "c9b9305f-5bbd-49cb-8835-f351efcc48ce";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1C073C00 },
         { .reg = 0x00009888, .val = 0x14090440 },
         { .reg = 0x00009888, .val = 0x16090013 },
         { .reg = 0x00009888, .val = 0x1D073C00 },
         { .reg = 0x00009888, .val = 0x15090440 },
         { .reg = 0x00009888, .val = 0x17090013 },
         { .reg = 0x00009888, .val = 0x00034038 },
         { .reg = 0x00009888, .val = 0x06070000 },
         { .reg = 0x00009888, .val = 0x16070034 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009888, .val = 0x02090010 },
         { .reg = 0x00009888, .val = 0x04090A00 },
         { .reg = 0x00009888, .val = 0x0609034A },
         { .reg = 0x00009888, .val = 0x00098000 },
         { .reg = 0x00009888, .val = 0x000A056A },
         { .reg = 0x00009888, .val = 0x020A9000 },
         { .reg = 0x00009888, .val = 0x00014038 },
         { .reg = 0x00009888, .val = 0x000B0A80 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x07070000 },
         { .reg = 0x00009888, .val = 0x15070D00 },
         { .reg = 0x00009888, .val = 0x05070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x03090010 },
         { .reg = 0x00009888, .val = 0x09090285 },
         { .reg = 0x00009888, .val = 0x0B09000D },
         { .reg = 0x00009888, .val = 0x01094000 },
         { .reg = 0x00009888, .val = 0x010A0A80 },
         { .reg = 0x00009888, .val = 0x030A2000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1C073C00 },
         { .reg = 0x00009888, .val = 0x14090440 },
         { .reg = 0x00009888, .val = 0x16090013 },
         { .reg = 0x00009888, .val = 0x1D073C00 },
         { .reg = 0x00009888, .val = 0x15090440 },
         { .reg = 0x00009888, .val = 0x17090013 },
         { .reg = 0x00009888, .val = 0x00031E00 },
         { .reg = 0x00009888, .val = 0x06070000 },
         { .reg = 0x00009888, .val = 0x14070034 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x020803FC },
         { .reg = 0x00009888, .val = 0x02090010 },
         { .reg = 0x00009888, .val = 0x0A090140 },
         { .reg = 0x00009888, .val = 0x0C09034A },
         { .reg = 0x00009888, .val = 0x00092000 },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020A0956 },
         { .reg = 0x00009888, .val = 0x00011E00 },
         { .reg = 0x00009888, .val = 0x020B02A8 },
         { .reg = 0x00009888, .val = 0x07070000 },
         { .reg = 0x00009888, .val = 0x13070D00 },
         { .reg = 0x00009888, .val = 0x05070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x03090010 },
         { .reg = 0x00009888, .val = 0x0F090285 },
         { .reg = 0x00009888, .val = 0x1109000D },
         { .reg = 0x00009888, .val = 0x01091000 },
         { .reg = 0x00009888, .val = 0x030A02A8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002A555 },
         { .reg = 0x00009888, .val = 0x02025AAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E031081 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42030428 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x460302E4 },
         { .reg = 0x00009888, .val = 0x48030E17 },
         { .reg = 0x00009888, .val = 0x4A030801 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030100 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001C03F },
         { .reg = 0x00009888, .val = 0x00020555 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00050555 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00013FC0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02020555 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040555 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02050555 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x02080AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x0000000A },
         { .reg = 0x0000D94C, .val = 0x0000FFFA },
         { .reg = 0x0000D950, .val = 0x000000C2 },
         { .reg = 0x0000D954, .val = 0x0000FFE7 },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000FFD7 },
         { .reg = 0x0000D960, .val = 0x00000602 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FEBF },
         { .reg = 0x0000D970, .val = 0x00003002 },
         { .reg = 0x0000D974, .val = 0x0000F9FF },
         { .reg = 0x0000D978, .val = 0x00001002 },
         { .reg = 0x0000D97C, .val = 0x0000F5FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext612__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext612__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext612__avg_gpu_core_frequency__max,acmgt3__ext612__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4881, 24, NULL,acmgt3__ext612__clipper_input_vertex_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4882, 32, NULL,acmgt3__ext612__clipper_input_vertex_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4883, 40, NULL,acmgt3__ext612__clipper_input_vertex_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4884, 48, NULL,acmgt3__ext612__clipper_input_vertex_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4885, 56, NULL,acmgt3__ext612__streamout_output_vertex_count_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4886, 64, NULL,acmgt3__ext612__streamout_output_vertex_count_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4887, 72, NULL,acmgt3__ext612__streamout_output_vertex_count_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4888, 80, NULL,acmgt3__ext612__streamout_output_vertex_count_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext613_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext613";
   query->symbol_name = "Ext613";
   query->guid = "d5d3fda8-e845-4038-a746-538432843c47";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x180A001F },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x190A001F },
         { .reg = 0x00009888, .val = 0x00034002 },
         { .reg = 0x00009888, .val = 0x0008000C },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x060A0027 },
         { .reg = 0x00009888, .val = 0x140A0D80 },
         { .reg = 0x00009888, .val = 0x000A0004 },
         { .reg = 0x00009888, .val = 0x020A1000 },
         { .reg = 0x00009888, .val = 0x00014002 },
         { .reg = 0x00009888, .val = 0x000B0008 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x070A09C0 },
         { .reg = 0x00009888, .val = 0x150A0036 },
         { .reg = 0x00009888, .val = 0x010A0000 },
         { .reg = 0x00009888, .val = 0x030A0000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x180A001F },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x190A001F },
         { .reg = 0x00009888, .val = 0x00031008 },
         { .reg = 0x00009888, .val = 0x000800C0 },
         { .reg = 0x00009888, .val = 0x02080300 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x080A0027 },
         { .reg = 0x00009888, .val = 0x120A0D80 },
         { .reg = 0x00009888, .val = 0x000A0040 },
         { .reg = 0x00009888, .val = 0x020A0100 },
         { .reg = 0x00009888, .val = 0x00011008 },
         { .reg = 0x00009888, .val = 0x000B0080 },
         { .reg = 0x00009888, .val = 0x020B0200 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x090A09C0 },
         { .reg = 0x00009888, .val = 0x130A0036 },
         { .reg = 0x00009888, .val = 0x010A0000 },
         { .reg = 0x00009888, .val = 0x030A0000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x180A001F },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x190A001F },
         { .reg = 0x00009888, .val = 0x00030420 },
         { .reg = 0x00009888, .val = 0x00080C00 },
         { .reg = 0x00009888, .val = 0x02080030 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x0A0A0027 },
         { .reg = 0x00009888, .val = 0x100A0D80 },
         { .reg = 0x00009888, .val = 0x000A0400 },
         { .reg = 0x00009888, .val = 0x020A0010 },
         { .reg = 0x00009888, .val = 0x00010420 },
         { .reg = 0x00009888, .val = 0x000B0800 },
         { .reg = 0x00009888, .val = 0x020B0020 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x0B0A09C0 },
         { .reg = 0x00009888, .val = 0x110A0036 },
         { .reg = 0x00009888, .val = 0x010A0000 },
         { .reg = 0x00009888, .val = 0x030A0000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160A01F0 },
         { .reg = 0x00009888, .val = 0x180A001F },
         { .reg = 0x00009888, .val = 0x170A01F0 },
         { .reg = 0x00009888, .val = 0x190A001F },
         { .reg = 0x00009888, .val = 0x00030180 },
         { .reg = 0x00009888, .val = 0x0008C000 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x0C0A0027 },
         { .reg = 0x00009888, .val = 0x0E0A0D80 },
         { .reg = 0x00009888, .val = 0x000A4000 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x00010180 },
         { .reg = 0x00009888, .val = 0x000B8000 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x050A0200 },
         { .reg = 0x00009888, .val = 0x0D0A09C0 },
         { .reg = 0x00009888, .val = 0x0F0A0036 },
         { .reg = 0x00009888, .val = 0x010A0000 },
         { .reg = 0x00009888, .val = 0x030A0000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x0002A500 },
         { .reg = 0x00009888, .val = 0x0202005A },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032009 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032429 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030101 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031060 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030521 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001C003 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001300C },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x02050500 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010C30 },
         { .reg = 0x00009888, .val = 0x00020500 },
         { .reg = 0x00009888, .val = 0x02020050 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040050 },
         { .reg = 0x00009888, .val = 0x00050500 },
         { .reg = 0x00009888, .val = 0x02050050 },
         { .reg = 0x00009888, .val = 0x00080A00 },
         { .reg = 0x00009888, .val = 0x020800A0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000103C0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext613__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext613__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext613__avg_gpu_core_frequency__max,acmgt3__ext613__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1391, 24, percentage_max_float,acmgt3__ext613__vertex_fetch_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1392, 28, percentage_max_float,acmgt3__ext613__vertex_fetch_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2451, 32, percentage_max_float,acmgt3__ext613__vertex_fetch_input_available_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2452, 36, percentage_max_float,acmgt3__ext613__vertex_fetch_input_available_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4889, 40, percentage_max_float,acmgt3__ext613__vertex_fetch_input_available_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4890, 44, percentage_max_float,acmgt3__ext613__vertex_fetch_input_available_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4891, 48, percentage_max_float,acmgt3__ext613__vertex_fetch_input_available_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4892, 52, percentage_max_float,acmgt3__ext613__vertex_fetch_input_available_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1393, 56, percentage_max_float,acmgt3__ext613__vertex_fetch_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1394, 60, percentage_max_float,acmgt3__ext613__vertex_fetch_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2453, 64, percentage_max_float,acmgt3__ext613__vertex_fetch_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2454, 68, percentage_max_float,acmgt3__ext613__vertex_fetch_output_ready_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4893, 72, percentage_max_float,acmgt3__ext613__vertex_fetch_output_ready_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4894, 76, percentage_max_float,acmgt3__ext613__vertex_fetch_output_ready_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4895, 80, percentage_max_float,acmgt3__ext613__vertex_fetch_output_ready_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4896, 84, percentage_max_float,acmgt3__ext613__vertex_fetch_output_ready_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext614_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext614";
   query->symbol_name = "Ext614";
   query->guid = "2183a6ac-d667-4b20-a851-b97ccb5d5b21";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x16090340 },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x17090340 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x14030031 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00034040 },
         { .reg = 0x00009888, .val = 0x00083000 },
         { .reg = 0x00009888, .val = 0x0208F000 },
         { .reg = 0x00009888, .val = 0x02090003 },
         { .reg = 0x00009888, .val = 0x0C090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A9000 },
         { .reg = 0x00009888, .val = 0x020A5000 },
         { .reg = 0x00009888, .val = 0x0001C040 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x020BA000 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x13030C40 },
         { .reg = 0x00009888, .val = 0x03030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x03083000 },
         { .reg = 0x00009888, .val = 0x03090003 },
         { .reg = 0x00009888, .val = 0x0B090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A2000 },
         { .reg = 0x00009888, .val = 0x030A1000 },
         { .reg = 0x00009888, .val = 0x01014000 },
         { .reg = 0x00009888, .val = 0x030B2000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x16090340 },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x17090340 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x12030031 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00031010 },
         { .reg = 0x00009888, .val = 0x00080300 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009888, .val = 0x02090003 },
         { .reg = 0x00009888, .val = 0x0A090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0900 },
         { .reg = 0x00009888, .val = 0x020A0500 },
         { .reg = 0x00009888, .val = 0x00013010 },
         { .reg = 0x00009888, .val = 0x000B0200 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x11030C40 },
         { .reg = 0x00009888, .val = 0x03030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x03080300 },
         { .reg = 0x00009888, .val = 0x03090003 },
         { .reg = 0x00009888, .val = 0x09090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0200 },
         { .reg = 0x00009888, .val = 0x030A0100 },
         { .reg = 0x00009888, .val = 0x01011000 },
         { .reg = 0x00009888, .val = 0x030B0200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x16090340 },
         { .reg = 0x00009888, .val = 0x0D030000 },
         { .reg = 0x00009888, .val = 0x17090340 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x10030031 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00030404 },
         { .reg = 0x00009888, .val = 0x00080030 },
         { .reg = 0x00009888, .val = 0x020800F0 },
         { .reg = 0x00009888, .val = 0x02090003 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0090 },
         { .reg = 0x00009888, .val = 0x020A0050 },
         { .reg = 0x00009888, .val = 0x00010C04 },
         { .reg = 0x00009888, .val = 0x000B0020 },
         { .reg = 0x00009888, .val = 0x020B00A0 },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x0F030C40 },
         { .reg = 0x00009888, .val = 0x03030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x03080030 },
         { .reg = 0x00009888, .val = 0x03090003 },
         { .reg = 0x00009888, .val = 0x07090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0020 },
         { .reg = 0x00009888, .val = 0x030A0010 },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0020 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0C030000 },
         { .reg = 0x00009888, .val = 0x16090340 },
         { .reg = 0x00009888, .val = 0x0D030C40 },
         { .reg = 0x00009888, .val = 0x17090340 },
         { .reg = 0x00009888, .val = 0x04030010 },
         { .reg = 0x00009888, .val = 0x0E030031 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x00030101 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x02090003 },
         { .reg = 0x00009888, .val = 0x06090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0009 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x00010301 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x05030010 },
         { .reg = 0x00009888, .val = 0x03030000 },
         { .reg = 0x00009888, .val = 0x01030000 },
         { .reg = 0x00009888, .val = 0x03080003 },
         { .reg = 0x00009888, .val = 0x03090003 },
         { .reg = 0x00009888, .val = 0x05090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0002 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009888, .val = 0x01010100 },
         { .reg = 0x00009888, .val = 0x030B0002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AF00 },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x0002005A },
         { .reg = 0x00009888, .val = 0x0202005A },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032005 },
         { .reg = 0x00009888, .val = 0x2603F000 },
         { .reg = 0x00009888, .val = 0x42031449 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x3203F000 },
         { .reg = 0x00009888, .val = 0x44033CC2 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030C23 },
         { .reg = 0x00009888, .val = 0x4803003F },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030521 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001C0C0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00013030 },
         { .reg = 0x00009888, .val = 0x00020500 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x00050500 },
         { .reg = 0x00009888, .val = 0x02050500 },
         { .reg = 0x00009888, .val = 0x00080A00 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010C0C },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x02020050 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02040050 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x02050050 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009888, .val = 0x020800A0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010303 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext614__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext614__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext614__avg_gpu_core_frequency__max,acmgt3__ext614__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1399, 24, percentage_max_float,acmgt3__ext614__vs_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1400, 28, percentage_max_float,acmgt3__ext614__vs_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2461, 32, percentage_max_float,acmgt3__ext614__vs_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2462, 36, percentage_max_float,acmgt3__ext614__vs_output_ready_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4897, 40, percentage_max_float,acmgt3__ext614__vs_output_ready_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4898, 44, percentage_max_float,acmgt3__ext614__vs_output_ready_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4899, 48, percentage_max_float,acmgt3__ext614__vs_output_ready_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4900, 52, percentage_max_float,acmgt3__ext614__vs_output_ready_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1401, 56, percentage_max_float,acmgt3__ext614__clipper_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1402, 60, percentage_max_float,acmgt3__ext614__clipper_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2455, 64, percentage_max_float,acmgt3__ext614__clipper_input_available_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2456, 68, percentage_max_float,acmgt3__ext614__clipper_input_available_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4901, 72, percentage_max_float,acmgt3__ext614__clipper_input_available_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4902, 76, percentage_max_float,acmgt3__ext614__clipper_input_available_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4903, 80, percentage_max_float,acmgt3__ext614__clipper_input_available_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4904, 84, percentage_max_float,acmgt3__ext614__clipper_input_available_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext615_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext615";
   query->symbol_name = "Ext615";
   query->guid = "736b7243-3c5a-41c7-a212-d506ebdf2fe2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18091800 },
         { .reg = 0x00009888, .val = 0x19091800 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x0008000C },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x04092400 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0006 },
         { .reg = 0x00009888, .val = 0x00010002 },
         { .reg = 0x00009888, .val = 0x000B0008 },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x07090012 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0008 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18091800 },
         { .reg = 0x00009888, .val = 0x19091800 },
         { .reg = 0x00009888, .val = 0x00030008 },
         { .reg = 0x00009888, .val = 0x000800C0 },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x06090480 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0060 },
         { .reg = 0x00009888, .val = 0x00010008 },
         { .reg = 0x00009888, .val = 0x000B0080 },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x09090012 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0080 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18091800 },
         { .reg = 0x00009888, .val = 0x19091800 },
         { .reg = 0x00009888, .val = 0x00030020 },
         { .reg = 0x00009888, .val = 0x00080C00 },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x08090480 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0600 },
         { .reg = 0x00009888, .val = 0x00010020 },
         { .reg = 0x00009888, .val = 0x000B0800 },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x0B090012 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0800 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18091800 },
         { .reg = 0x00009888, .val = 0x19091800 },
         { .reg = 0x00009888, .val = 0x00030080 },
         { .reg = 0x00009888, .val = 0x0008C000 },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x0A090480 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A6000 },
         { .reg = 0x00009888, .val = 0x00010080 },
         { .reg = 0x00009888, .val = 0x000B8000 },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x0D090012 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A8000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0002A500 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030009 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032420 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030101 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031060 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000C },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010030 },
         { .reg = 0x00009888, .val = 0x00020500 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x00050500 },
         { .reg = 0x00009888, .val = 0x00080A00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100C0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext615__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext615__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext615__avg_gpu_core_frequency__max,acmgt3__ext615__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1403, 24, percentage_max_float,acmgt3__ext615__clipper_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1404, 28, percentage_max_float,acmgt3__ext615__clipper_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2457, 32, percentage_max_float,acmgt3__ext615__clipper_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2458, 36, percentage_max_float,acmgt3__ext615__clipper_output_ready_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4905, 40, percentage_max_float,acmgt3__ext615__clipper_output_ready_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4906, 44, percentage_max_float,acmgt3__ext615__clipper_output_ready_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4907, 48, percentage_max_float,acmgt3__ext615__clipper_output_ready_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4908, 52, percentage_max_float,acmgt3__ext615__clipper_output_ready_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext616_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext616";
   query->symbol_name = "Ext616";
   query->guid = "bebf8f78-b673-479f-803c-2e1f403454b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18013800 },
         { .reg = 0x00009888, .val = 0x18213800 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x18C13800 },
         { .reg = 0x00009888, .val = 0x18E13800 },
         { .reg = 0x00009888, .val = 0x02010006 },
         { .reg = 0x00009888, .val = 0x0E0101C0 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02210006 },
         { .reg = 0x00009888, .val = 0x10210007 },
         { .reg = 0x00009888, .val = 0x00210000 },
         { .reg = 0x00009888, .val = 0x02410006 },
         { .reg = 0x00009888, .val = 0x104101C0 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610006 },
         { .reg = 0x00009888, .val = 0x12610007 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02810006 },
         { .reg = 0x00009888, .val = 0x128101C0 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10006 },
         { .reg = 0x00009888, .val = 0x14A10007 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02C10006 },
         { .reg = 0x00009888, .val = 0x14C101C0 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02E10006 },
         { .reg = 0x00009888, .val = 0x16E10007 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02034800 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x04093440 },
         { .reg = 0x00009888, .val = 0x06090004 },
         { .reg = 0x00009888, .val = 0x020A2400 },
         { .reg = 0x00009888, .val = 0x040A1252 },
         { .reg = 0x00009888, .val = 0x060A0001 },
         { .reg = 0x00009888, .val = 0x020B2200 },
         { .reg = 0x00009888, .val = 0x040B0023 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030841 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext616__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext616__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext616__avg_gpu_core_frequency__max,acmgt3__ext616__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 797, 24, NULL,acmgt3__ext616__gpu_memory_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 798, 32, NULL,acmgt3__ext616__gpu_memory_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 2797, 40, NULL,acmgt3__ext616__gpu_memory_write_sqidi2__read);

      intel_perf_query_add_counter_uint64(query, 2798, 48, NULL,acmgt3__ext616__gpu_memory_write_sqidi3__read);

      intel_perf_query_add_counter_uint64(query, 4909, 56, NULL,acmgt3__ext616__gpu_memory_write_sqidi4__read);

      intel_perf_query_add_counter_uint64(query, 4910, 64, NULL,acmgt3__ext616__gpu_memory_write_sqidi5__read);

      intel_perf_query_add_counter_uint64(query, 4911, 72, NULL,acmgt3__ext616__gpu_memory_write_sqidi6__read);

      intel_perf_query_add_counter_uint64(query, 4912, 80, NULL,acmgt3__ext616__gpu_memory_write_sqidi7__read);

      intel_perf_query_add_counter_uint64(query, 799, 88, NULL,acmgt3__ext616__gpu_memory_write__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext617_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext617";
   query->symbol_name = "Ext617";
   query->guid = "3a2d5424-78f7-445d-857f-fbea361be3fb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C0903E0 },
         { .reg = 0x00009888, .val = 0x1D0903E0 },
         { .reg = 0x00009888, .val = 0x00030040 },
         { .reg = 0x00009888, .val = 0x00083000 },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x0C090025 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A9000 },
         { .reg = 0x00009888, .val = 0x00010040 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x0B090940 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A2000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C0903E0 },
         { .reg = 0x00009888, .val = 0x1D0903E0 },
         { .reg = 0x00009888, .val = 0x00030010 },
         { .reg = 0x00009888, .val = 0x00080300 },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x0A090025 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0900 },
         { .reg = 0x00009888, .val = 0x00010010 },
         { .reg = 0x00009888, .val = 0x000B0200 },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x09090940 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1C0903E0 },
         { .reg = 0x00009888, .val = 0x1D0903E0 },
         { .reg = 0x00009888, .val = 0x00030004 },
         { .reg = 0x00009888, .val = 0x00080030 },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x08090025 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0090 },
         { .reg = 0x00009888, .val = 0x00010004 },
         { .reg = 0x00009888, .val = 0x000B0020 },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x07090940 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0020 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1C0903E0 },
         { .reg = 0x00009888, .val = 0x1D0903E0 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x00080003 },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x06090025 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0009 },
         { .reg = 0x00009888, .val = 0x00010001 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x05094A00 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AF00 },
         { .reg = 0x00009888, .val = 0x0002005A },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42030100 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030C28 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030209 },
         { .reg = 0x00009888, .val = 0x48030093 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000100C0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010030 },
         { .reg = 0x00009888, .val = 0x00020500 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x00050500 },
         { .reg = 0x00009888, .val = 0x00080A00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000C },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext617__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext617__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext617__avg_gpu_core_frequency__max,acmgt3__ext617__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1405, 24, NULL,acmgt3__ext617__clipper_primitive_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1406, 32, NULL,acmgt3__ext617__clipper_primitive_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2467, 40, NULL,acmgt3__ext617__clipper_primitive_output_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2468, 48, NULL,acmgt3__ext617__clipper_primitive_output_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4913, 56, NULL,acmgt3__ext617__clipper_primitive_output_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4914, 64, NULL,acmgt3__ext617__clipper_primitive_output_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4915, 72, NULL,acmgt3__ext617__clipper_primitive_output_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4916, 80, NULL,acmgt3__ext617__clipper_primitive_output_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext618_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext618";
   query->symbol_name = "Ext618";
   query->guid = "43c7733d-9c5e-48c8-a1a6-4c82e487dab9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18090000 },
         { .reg = 0x00009888, .val = 0x19090000 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x12090480 },
         { .reg = 0x00009888, .val = 0x14090013 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x020AA500 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x11090480 },
         { .reg = 0x00009888, .val = 0x13090013 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x030A0A00 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18090000 },
         { .reg = 0x00009888, .val = 0x19090000 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x0E090480 },
         { .reg = 0x00009888, .val = 0x10090013 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x020A00A5 },
         { .reg = 0x00009888, .val = 0x00010300 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x0D090480 },
         { .reg = 0x00009888, .val = 0x0F090013 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18090000 },
         { .reg = 0x00009888, .val = 0x19090000 },
         { .reg = 0x00009888, .val = 0x00030030 },
         { .reg = 0x00009888, .val = 0x00080F00 },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x0A090480 },
         { .reg = 0x00009888, .val = 0x0C090013 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000AA500 },
         { .reg = 0x00009888, .val = 0x00010030 },
         { .reg = 0x00009888, .val = 0x000B0A00 },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x09090480 },
         { .reg = 0x00009888, .val = 0x0B090013 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0A00 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18090000 },
         { .reg = 0x00009888, .val = 0x19090000 },
         { .reg = 0x00009888, .val = 0x00030003 },
         { .reg = 0x00009888, .val = 0x0008000F },
         { .reg = 0x00009888, .val = 0x02090040 },
         { .reg = 0x00009888, .val = 0x06090480 },
         { .reg = 0x00009888, .val = 0x08090013 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A00A5 },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x000B000A },
         { .reg = 0x00009888, .val = 0x03090040 },
         { .reg = 0x00009888, .val = 0x05092400 },
         { .reg = 0x00009888, .val = 0x07090013 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032520 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032009 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030008 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031060 },
         { .reg = 0x00009888, .val = 0x48030083 },
         { .reg = 0x00009888, .val = 0x4A030201 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032421 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext618__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext618__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext618__avg_gpu_core_frequency__max,acmgt3__ext618__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1423, 24, NULL,acmgt3__ext618__clipper_primitive_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1424, 32, NULL,acmgt3__ext618__clipper_primitive_cull_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2463, 40, NULL,acmgt3__ext618__clipper_primitive_cull_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2464, 48, NULL,acmgt3__ext618__clipper_primitive_cull_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4917, 56, NULL,acmgt3__ext618__clipper_primitive_cull_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4918, 64, NULL,acmgt3__ext618__clipper_primitive_cull_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4919, 72, NULL,acmgt3__ext618__clipper_primitive_cull_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4920, 80, NULL,acmgt3__ext618__clipper_primitive_cull_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext619_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext619";
   query->symbol_name = "Ext619";
   query->guid = "51f2492c-e8fb-4f62-b4a7-3acd0301e2f2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x160929C0 },
         { .reg = 0x00009888, .val = 0x170929C0 },
         { .reg = 0x00009888, .val = 0x00030038 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009888, .val = 0x02090023 },
         { .reg = 0x00009888, .val = 0x04090C00 },
         { .reg = 0x00009888, .val = 0x060902CC },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A056A },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0A80 },
         { .reg = 0x00009888, .val = 0x03090023 },
         { .reg = 0x00009888, .val = 0x09090306 },
         { .reg = 0x00009888, .val = 0x0B09000B },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0A80 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x160929C0 },
         { .reg = 0x00009888, .val = 0x170929C0 },
         { .reg = 0x00009888, .val = 0x00030E00 },
         { .reg = 0x00009888, .val = 0x020800FC },
         { .reg = 0x00009888, .val = 0x02090023 },
         { .reg = 0x00009888, .val = 0x0A090180 },
         { .reg = 0x00009888, .val = 0x0C0902CC },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020A0056 },
         { .reg = 0x00009888, .val = 0x00010E00 },
         { .reg = 0x00009888, .val = 0x020B00A8 },
         { .reg = 0x00009888, .val = 0x03090023 },
         { .reg = 0x00009888, .val = 0x0F090306 },
         { .reg = 0x00009888, .val = 0x1109000B },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x030A00A8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FAAA },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031060 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001003F },
         { .reg = 0x00009888, .val = 0x00020555 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x00050555 },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FC0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x0000002A },
         { .reg = 0x0000D94C, .val = 0x0000FFFA },
         { .reg = 0x0000D950, .val = 0x000000C2 },
         { .reg = 0x0000D954, .val = 0x0000FFE7 },
         { .reg = 0x0000D958, .val = 0x00000142 },
         { .reg = 0x0000D95C, .val = 0x0000FFD7 },
         { .reg = 0x0000D960, .val = 0x00000602 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00000A02 },
         { .reg = 0x0000D96C, .val = 0x0000FEBF },
         { .reg = 0x0000D970, .val = 0x00003002 },
         { .reg = 0x0000D974, .val = 0x0000F9FF },
         { .reg = 0x0000D978, .val = 0x00005002 },
         { .reg = 0x0000D97C, .val = 0x0000F5FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext619__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext619__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext619__avg_gpu_core_frequency__max,acmgt3__ext619__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1421, 24, NULL,acmgt3__ext619__clipper_primitive_far_near_clip_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1422, 32, NULL,acmgt3__ext619__clipper_primitive_far_near_clip_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2465, 40, NULL,acmgt3__ext619__clipper_primitive_far_near_clip_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2466, 48, NULL,acmgt3__ext619__clipper_primitive_far_near_clip_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext620_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext620";
   query->symbol_name = "Ext620";
   query->guid = "dd87d3c7-2f33-41ba-a19f-36cc5eecf723";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x160929C0 },
         { .reg = 0x00009888, .val = 0x170929C0 },
         { .reg = 0x00009888, .val = 0x00030038 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009888, .val = 0x02090023 },
         { .reg = 0x00009888, .val = 0x04090C00 },
         { .reg = 0x00009888, .val = 0x060902CC },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A056A },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0A80 },
         { .reg = 0x00009888, .val = 0x03090023 },
         { .reg = 0x00009888, .val = 0x09090306 },
         { .reg = 0x00009888, .val = 0x0B09000B },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0A80 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x160929C0 },
         { .reg = 0x00009888, .val = 0x170929C0 },
         { .reg = 0x00009888, .val = 0x00030E00 },
         { .reg = 0x00009888, .val = 0x020800FC },
         { .reg = 0x00009888, .val = 0x02090023 },
         { .reg = 0x00009888, .val = 0x0A090180 },
         { .reg = 0x00009888, .val = 0x0C0902CC },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020A0056 },
         { .reg = 0x00009888, .val = 0x00010E00 },
         { .reg = 0x00009888, .val = 0x020B00A8 },
         { .reg = 0x00009888, .val = 0x03090023 },
         { .reg = 0x00009888, .val = 0x0F090306 },
         { .reg = 0x00009888, .val = 0x1109000B },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x030A00A8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002A555 },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031060 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001003F },
         { .reg = 0x00009888, .val = 0x00020555 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x00050555 },
         { .reg = 0x00009888, .val = 0x00080AAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FC0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x0000002A },
         { .reg = 0x0000D94C, .val = 0x0000FFFA },
         { .reg = 0x0000D950, .val = 0x000000C2 },
         { .reg = 0x0000D954, .val = 0x0000FFE7 },
         { .reg = 0x0000D958, .val = 0x00000142 },
         { .reg = 0x0000D95C, .val = 0x0000FFD7 },
         { .reg = 0x0000D960, .val = 0x00000602 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00000A02 },
         { .reg = 0x0000D96C, .val = 0x0000FEBF },
         { .reg = 0x0000D970, .val = 0x00003002 },
         { .reg = 0x0000D974, .val = 0x0000F9FF },
         { .reg = 0x0000D978, .val = 0x00005002 },
         { .reg = 0x0000D97C, .val = 0x0000F5FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext620__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext620__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext620__avg_gpu_core_frequency__max,acmgt3__ext620__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4921, 24, NULL,acmgt3__ext620__clipper_primitive_far_near_clip_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4922, 32, NULL,acmgt3__ext620__clipper_primitive_far_near_clip_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4923, 40, NULL,acmgt3__ext620__clipper_primitive_far_near_clip_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4924, 48, NULL,acmgt3__ext620__clipper_primitive_far_near_clip_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext621_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext621";
   query->symbol_name = "Ext621";
   query->guid = "5762280f-381f-4c9a-99dd-96811abec85d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x14090000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x15090000 },
         { .reg = 0x00009888, .val = 0x0003400C },
         { .reg = 0x00009888, .val = 0x00058000 },
         { .reg = 0x00009888, .val = 0x020530C8 },
         { .reg = 0x00009888, .val = 0x00060003 },
         { .reg = 0x00009888, .val = 0x000800F5 },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A9000 },
         { .reg = 0x00009888, .val = 0x0001400C },
         { .reg = 0x00009888, .val = 0x000B00A0 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x01058000 },
         { .reg = 0x00009888, .val = 0x05050C32 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x0106000C },
         { .reg = 0x00009888, .val = 0x01080050 },
         { .reg = 0x00009888, .val = 0x03090000 },
         { .reg = 0x00009888, .val = 0x13090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0050 },
         { .reg = 0x00009888, .val = 0x030A2000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x14090000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x15090000 },
         { .reg = 0x00009888, .val = 0x000310C0 },
         { .reg = 0x00009888, .val = 0x00058000 },
         { .reg = 0x00009888, .val = 0x06050C32 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00060030 },
         { .reg = 0x00009888, .val = 0x0008F500 },
         { .reg = 0x00009888, .val = 0x02080300 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x12090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0900 },
         { .reg = 0x00009888, .val = 0x000110C0 },
         { .reg = 0x00009888, .val = 0x000BA000 },
         { .reg = 0x00009888, .val = 0x020B0200 },
         { .reg = 0x00009888, .val = 0x01058000 },
         { .reg = 0x00009888, .val = 0x09050C32 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x010600C0 },
         { .reg = 0x00009888, .val = 0x01085000 },
         { .reg = 0x00009888, .val = 0x03090000 },
         { .reg = 0x00009888, .val = 0x11090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A5000 },
         { .reg = 0x00009888, .val = 0x030A0200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x14090000 },
         { .reg = 0x00009888, .val = 0x15090000 },
         { .reg = 0x00009888, .val = 0x00030400 },
         { .reg = 0x00009888, .val = 0x02080030 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x10090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x020A0090 },
         { .reg = 0x00009888, .val = 0x00010400 },
         { .reg = 0x00009888, .val = 0x020B0020 },
         { .reg = 0x00009888, .val = 0x03090000 },
         { .reg = 0x00009888, .val = 0x0F090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x030A0020 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x14090000 },
         { .reg = 0x00009888, .val = 0x15090000 },
         { .reg = 0x00009888, .val = 0x00030100 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x0E090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x020A0009 },
         { .reg = 0x00009888, .val = 0x00010100 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x03090000 },
         { .reg = 0x00009888, .val = 0x0D090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x0202005A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E0310E8 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42030105 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030008 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0308E7 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x400320A8 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001C00F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000130F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010C00 },
         { .reg = 0x00009888, .val = 0x02020050 },
         { .reg = 0x00009888, .val = 0x02040050 },
         { .reg = 0x00009888, .val = 0x02050050 },
         { .reg = 0x00009888, .val = 0x020800A0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010300 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext621__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext621__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext621__avg_gpu_core_frequency__max,acmgt3__ext621__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1407, 24, NULL,acmgt3__ext621__clipper_transaction_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1408, 32, NULL,acmgt3__ext621__clipper_transaction_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2473, 40, NULL,acmgt3__ext621__clipper_transaction_output_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2474, 48, NULL,acmgt3__ext621__clipper_transaction_output_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4925, 56, NULL,acmgt3__ext621__clipper_transaction_output_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4926, 64, NULL,acmgt3__ext621__clipper_transaction_output_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4927, 72, NULL,acmgt3__ext621__clipper_transaction_output_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4928, 80, NULL,acmgt3__ext621__clipper_transaction_output_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1417, 88, percentage_max_float,acmgt3__ext621__rasterizer_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1418, 92, percentage_max_float,acmgt3__ext621__rasterizer_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2817, 96, percentage_max_float,acmgt3__ext621__rasterizer_input_available_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2818, 100, percentage_max_float,acmgt3__ext621__rasterizer_input_available_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext622_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext622";
   query->symbol_name = "Ext622";
   query->guid = "21c9f2d3-9ffa-48a0-8f77-b25bc916b889";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A057C00 },
         { .reg = 0x00009888, .val = 0x1C050013 },
         { .reg = 0x00009888, .val = 0x1B057C00 },
         { .reg = 0x00009888, .val = 0x1D050013 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x10050F31 },
         { .reg = 0x00009888, .val = 0x0006C000 },
         { .reg = 0x00009888, .val = 0x02085F00 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03050001 },
         { .reg = 0x00009888, .val = 0x0F050F31 },
         { .reg = 0x00009888, .val = 0x01063000 },
         { .reg = 0x00009888, .val = 0x03080500 },
         { .reg = 0x00009888, .val = 0x030A0500 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A057C00 },
         { .reg = 0x00009888, .val = 0x1C050013 },
         { .reg = 0x00009888, .val = 0x1B057C00 },
         { .reg = 0x00009888, .val = 0x1D050013 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0C050F31 },
         { .reg = 0x00009888, .val = 0x00060C00 },
         { .reg = 0x00009888, .val = 0x0208005F },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010300 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03050001 },
         { .reg = 0x00009888, .val = 0x0B050F31 },
         { .reg = 0x00009888, .val = 0x01060300 },
         { .reg = 0x00009888, .val = 0x03080005 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x0003000C },
         { .reg = 0x00009888, .val = 0x00058000 },
         { .reg = 0x00009888, .val = 0x020530C8 },
         { .reg = 0x00009888, .val = 0x00060003 },
         { .reg = 0x00009888, .val = 0x000800F5 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000C },
         { .reg = 0x00009888, .val = 0x000B00A0 },
         { .reg = 0x00009888, .val = 0x01058000 },
         { .reg = 0x00009888, .val = 0x05050C32 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x0106000C },
         { .reg = 0x00009888, .val = 0x01080050 },
         { .reg = 0x00009888, .val = 0x010A0050 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1C050000 },
         { .reg = 0x00009888, .val = 0x1D050000 },
         { .reg = 0x00009888, .val = 0x000300C0 },
         { .reg = 0x00009888, .val = 0x00058000 },
         { .reg = 0x00009888, .val = 0x06050C32 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00060030 },
         { .reg = 0x00009888, .val = 0x0008F500 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x000100C0 },
         { .reg = 0x00009888, .val = 0x000BA000 },
         { .reg = 0x00009888, .val = 0x01058000 },
         { .reg = 0x00009888, .val = 0x09050C32 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x010600C0 },
         { .reg = 0x00009888, .val = 0x01085000 },
         { .reg = 0x00009888, .val = 0x010A5000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x0002AA55 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032449 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032528 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42030109 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030008 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030201 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032421 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext622__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext622__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext622__avg_gpu_core_frequency__max,acmgt3__ext622__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4929, 24, percentage_max_float,acmgt3__ext622__rasterizer_input_available_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4930, 28, percentage_max_float,acmgt3__ext622__rasterizer_input_available_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4931, 32, percentage_max_float,acmgt3__ext622__rasterizer_input_available_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4932, 36, percentage_max_float,acmgt3__ext622__rasterizer_input_available_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1415, 40, NULL,acmgt3__ext622__rasterizer_transaction_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1416, 48, NULL,acmgt3__ext622__rasterizer_transaction_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2821, 56, NULL,acmgt3__ext622__rasterizer_transaction_output_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2822, 64, NULL,acmgt3__ext622__rasterizer_transaction_output_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext623_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext623";
   query->symbol_name = "Ext623";
   query->guid = "fa526e5f-fd03-4a7c-a49f-fda2ade7305c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C097FC0 },
         { .reg = 0x00009888, .val = 0x1D097FC0 },
         { .reg = 0x00009888, .val = 0x00030030 },
         { .reg = 0x00009888, .val = 0x00080F00 },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x04090005 },
         { .reg = 0x00009888, .val = 0x0A090940 },
         { .reg = 0x00009888, .val = 0x0C09002A },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000AA500 },
         { .reg = 0x00009888, .val = 0x00010030 },
         { .reg = 0x00009888, .val = 0x000B0A00 },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x05090005 },
         { .reg = 0x00009888, .val = 0x09090940 },
         { .reg = 0x00009888, .val = 0x0B09002A },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0A00 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1C097FC0 },
         { .reg = 0x00009888, .val = 0x1D097FC0 },
         { .reg = 0x00009888, .val = 0x00030003 },
         { .reg = 0x00009888, .val = 0x0008000F },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x04090005 },
         { .reg = 0x00009888, .val = 0x06090940 },
         { .reg = 0x00009888, .val = 0x0809002A },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A00A5 },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x000B000A },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x05094A05 },
         { .reg = 0x00009888, .val = 0x0709002A },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A000A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A057C00 },
         { .reg = 0x00009888, .val = 0x1C050013 },
         { .reg = 0x00009888, .val = 0x1B057C00 },
         { .reg = 0x00009888, .val = 0x1D050013 },
         { .reg = 0x00009888, .val = 0x00033000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x10050F31 },
         { .reg = 0x00009888, .val = 0x0006C000 },
         { .reg = 0x00009888, .val = 0x02085F00 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x00013000 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03050001 },
         { .reg = 0x00009888, .val = 0x0F050F31 },
         { .reg = 0x00009888, .val = 0x01063000 },
         { .reg = 0x00009888, .val = 0x03080500 },
         { .reg = 0x00009888, .val = 0x030A0500 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A057C00 },
         { .reg = 0x00009888, .val = 0x1C050013 },
         { .reg = 0x00009888, .val = 0x1B057C00 },
         { .reg = 0x00009888, .val = 0x1D050013 },
         { .reg = 0x00009888, .val = 0x00030300 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0C050F31 },
         { .reg = 0x00009888, .val = 0x00060C00 },
         { .reg = 0x00009888, .val = 0x0208005F },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010300 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03050001 },
         { .reg = 0x00009888, .val = 0x0B050F31 },
         { .reg = 0x00009888, .val = 0x01060300 },
         { .reg = 0x00009888, .val = 0x03080005 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAFF },
         { .reg = 0x00009888, .val = 0x020255AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032109 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42031928 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030126 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030CE9 },
         { .reg = 0x00009888, .val = 0x48030067 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000100F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext623__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext623__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext623__avg_gpu_core_frequency__max,acmgt3__ext623__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4933, 24, NULL,acmgt3__ext623__rasterizer_transaction_output_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4934, 32, NULL,acmgt3__ext623__rasterizer_transaction_output_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4935, 40, NULL,acmgt3__ext623__rasterizer_transaction_output_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4936, 48, NULL,acmgt3__ext623__rasterizer_transaction_output_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1411, 56, NULL,acmgt3__ext623__stripsfan_objects_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1412, 64, NULL,acmgt3__ext623__stripsfan_objects_cull_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2469, 72, NULL,acmgt3__ext623__stripsfan_objects_cull_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2470, 80, NULL,acmgt3__ext623__stripsfan_objects_cull_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext624_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext624";
   query->symbol_name = "Ext624";
   query->guid = "4fffc158-263b-4d29-afd1-1aa0dd09f1e3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12057C00 },
         { .reg = 0x00009888, .val = 0x1A057800 },
         { .reg = 0x00009888, .val = 0x13057C00 },
         { .reg = 0x00009888, .val = 0x1B057800 },
         { .reg = 0x00009888, .val = 0x00034040 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x08050D00 },
         { .reg = 0x00009888, .val = 0x10050080 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00068080 },
         { .reg = 0x00009888, .val = 0x00087000 },
         { .reg = 0x00009888, .val = 0x02087000 },
         { .reg = 0x00009888, .val = 0x000A5000 },
         { .reg = 0x00009888, .val = 0x020A5000 },
         { .reg = 0x00009888, .val = 0x00014040 },
         { .reg = 0x00009888, .val = 0x000B2000 },
         { .reg = 0x00009888, .val = 0x020B2000 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x09050034 },
         { .reg = 0x00009888, .val = 0x11050002 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01064040 },
         { .reg = 0x00009888, .val = 0x01081000 },
         { .reg = 0x00009888, .val = 0x03081000 },
         { .reg = 0x00009888, .val = 0x010A1000 },
         { .reg = 0x00009888, .val = 0x030A1000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x12057C00 },
         { .reg = 0x00009888, .val = 0x1A057800 },
         { .reg = 0x00009888, .val = 0x13057C00 },
         { .reg = 0x00009888, .val = 0x1B057800 },
         { .reg = 0x00009888, .val = 0x00031010 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x06050D00 },
         { .reg = 0x00009888, .val = 0x0E050080 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00062020 },
         { .reg = 0x00009888, .val = 0x00080700 },
         { .reg = 0x00009888, .val = 0x02080700 },
         { .reg = 0x00009888, .val = 0x000A0500 },
         { .reg = 0x00009888, .val = 0x020A0500 },
         { .reg = 0x00009888, .val = 0x00011010 },
         { .reg = 0x00009888, .val = 0x000B0200 },
         { .reg = 0x00009888, .val = 0x020B0200 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x07050034 },
         { .reg = 0x00009888, .val = 0x0F050002 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01061010 },
         { .reg = 0x00009888, .val = 0x01080100 },
         { .reg = 0x00009888, .val = 0x03080100 },
         { .reg = 0x00009888, .val = 0x010A0100 },
         { .reg = 0x00009888, .val = 0x030A0100 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x12057C00 },
         { .reg = 0x00009888, .val = 0x1A057800 },
         { .reg = 0x00009888, .val = 0x13057C00 },
         { .reg = 0x00009888, .val = 0x1B057800 },
         { .reg = 0x00009888, .val = 0x00030404 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x04050D00 },
         { .reg = 0x00009888, .val = 0x0C050080 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00060808 },
         { .reg = 0x00009888, .val = 0x00080070 },
         { .reg = 0x00009888, .val = 0x02080070 },
         { .reg = 0x00009888, .val = 0x000A0050 },
         { .reg = 0x00009888, .val = 0x020A0050 },
         { .reg = 0x00009888, .val = 0x00010404 },
         { .reg = 0x00009888, .val = 0x000B0020 },
         { .reg = 0x00009888, .val = 0x020B0020 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x05050034 },
         { .reg = 0x00009888, .val = 0x0D050002 },
         { .reg = 0x00009888, .val = 0x03050000 },
         { .reg = 0x00009888, .val = 0x01060404 },
         { .reg = 0x00009888, .val = 0x01080010 },
         { .reg = 0x00009888, .val = 0x03080010 },
         { .reg = 0x00009888, .val = 0x010A0010 },
         { .reg = 0x00009888, .val = 0x030A0010 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x12057C00 },
         { .reg = 0x00009888, .val = 0x1A057800 },
         { .reg = 0x00009888, .val = 0x13057C00 },
         { .reg = 0x00009888, .val = 0x1B057800 },
         { .reg = 0x00009888, .val = 0x00030101 },
         { .reg = 0x00009888, .val = 0x00050002 },
         { .reg = 0x00009888, .val = 0x02053400 },
         { .reg = 0x00009888, .val = 0x0A050080 },
         { .reg = 0x00009888, .val = 0x00060202 },
         { .reg = 0x00009888, .val = 0x00080007 },
         { .reg = 0x00009888, .val = 0x02080007 },
         { .reg = 0x00009888, .val = 0x000A0005 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x00010101 },
         { .reg = 0x00009888, .val = 0x000B0002 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x01050002 },
         { .reg = 0x00009888, .val = 0x030500D0 },
         { .reg = 0x00009888, .val = 0x0B050002 },
         { .reg = 0x00009888, .val = 0x01060101 },
         { .reg = 0x00009888, .val = 0x01080001 },
         { .reg = 0x00009888, .val = 0x03080001 },
         { .reg = 0x00009888, .val = 0x010A0001 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AF00 },
         { .reg = 0x00009888, .val = 0x0208AF00 },
         { .reg = 0x00009888, .val = 0x0002005A },
         { .reg = 0x00009888, .val = 0x0202005A },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04032489 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032000 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42030109 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030C28 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030209 },
         { .reg = 0x00009888, .val = 0x48030093 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030521 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001C0C0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00013030 },
         { .reg = 0x00009888, .val = 0x00020500 },
         { .reg = 0x00009888, .val = 0x02020500 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x00050500 },
         { .reg = 0x00009888, .val = 0x02050500 },
         { .reg = 0x00009888, .val = 0x00080A00 },
         { .reg = 0x00009888, .val = 0x02080A00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010C0C },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x02020050 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02040050 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x02050050 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009888, .val = 0x020800A0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010303 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext624__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext624__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext624__avg_gpu_core_frequency__max,acmgt3__ext624__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1409, 24, NULL,acmgt3__ext624__stripsfan_object_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1410, 32, NULL,acmgt3__ext624__stripsfan_object_count_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2471, 40, NULL,acmgt3__ext624__stripsfan_object_count_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2472, 48, NULL,acmgt3__ext624__stripsfan_object_count_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4937, 56, NULL,acmgt3__ext624__stripsfan_object_count_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4938, 64, NULL,acmgt3__ext624__stripsfan_object_count_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4939, 72, NULL,acmgt3__ext624__stripsfan_object_count_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4940, 80, NULL,acmgt3__ext624__stripsfan_object_count_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1419, 88, percentage_max_float,acmgt3__ext624__rasterizer_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1420, 92, percentage_max_float,acmgt3__ext624__rasterizer_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2819, 96, percentage_max_float,acmgt3__ext624__rasterizer_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2820, 100, percentage_max_float,acmgt3__ext624__rasterizer_output_ready_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4941, 104, percentage_max_float,acmgt3__ext624__rasterizer_output_ready_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4942, 108, percentage_max_float,acmgt3__ext624__rasterizer_output_ready_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4943, 112, percentage_max_float,acmgt3__ext624__rasterizer_output_ready_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4944, 116, percentage_max_float,acmgt3__ext624__rasterizer_output_ready_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext625_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext625";
   query->symbol_name = "Ext625";
   query->guid = "84cc7f2d-8833-4508-b075-965fc4d88ee2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E09000A },
         { .reg = 0x00009888, .val = 0x1F09000A },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x0008000C },
         { .reg = 0x00009888, .val = 0x04096800 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0006 },
         { .reg = 0x00009888, .val = 0x00010002 },
         { .reg = 0x00009888, .val = 0x000B0008 },
         { .reg = 0x00009888, .val = 0x05090000 },
         { .reg = 0x00009888, .val = 0x07090034 },
         { .reg = 0x00009888, .val = 0x03090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0008 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1E09000A },
         { .reg = 0x00009888, .val = 0x1F09000A },
         { .reg = 0x00009888, .val = 0x00030008 },
         { .reg = 0x00009888, .val = 0x000800C0 },
         { .reg = 0x00009888, .val = 0x04090000 },
         { .reg = 0x00009888, .val = 0x06090D00 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0060 },
         { .reg = 0x00009888, .val = 0x00010008 },
         { .reg = 0x00009888, .val = 0x000B0080 },
         { .reg = 0x00009888, .val = 0x05090000 },
         { .reg = 0x00009888, .val = 0x09090034 },
         { .reg = 0x00009888, .val = 0x03090000 },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0080 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1C097FC0 },
         { .reg = 0x00009888, .val = 0x1E09000A },
         { .reg = 0x00009888, .val = 0x1D097FC0 },
         { .reg = 0x00009888, .val = 0x1F09000A },
         { .reg = 0x00009888, .val = 0x00033020 },
         { .reg = 0x00009888, .val = 0x00080C00 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x04090005 },
         { .reg = 0x00009888, .val = 0x08090D00 },
         { .reg = 0x00009888, .val = 0x12090940 },
         { .reg = 0x00009888, .val = 0x1409002A },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A0600 },
         { .reg = 0x00009888, .val = 0x020AA500 },
         { .reg = 0x00009888, .val = 0x00013020 },
         { .reg = 0x00009888, .val = 0x000B0800 },
         { .reg = 0x00009888, .val = 0x020B0A00 },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x05090005 },
         { .reg = 0x00009888, .val = 0x0B090034 },
         { .reg = 0x00009888, .val = 0x11090940 },
         { .reg = 0x00009888, .val = 0x1309002A },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A0800 },
         { .reg = 0x00009888, .val = 0x030A0A00 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1C097FC0 },
         { .reg = 0x00009888, .val = 0x1E09000A },
         { .reg = 0x00009888, .val = 0x1D097FC0 },
         { .reg = 0x00009888, .val = 0x1F09000A },
         { .reg = 0x00009888, .val = 0x00030380 },
         { .reg = 0x00009888, .val = 0x0008C000 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x02094000 },
         { .reg = 0x00009888, .val = 0x04090005 },
         { .reg = 0x00009888, .val = 0x0A090D00 },
         { .reg = 0x00009888, .val = 0x0E090940 },
         { .reg = 0x00009888, .val = 0x1009002A },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x000A6000 },
         { .reg = 0x00009888, .val = 0x020A00A5 },
         { .reg = 0x00009888, .val = 0x00010380 },
         { .reg = 0x00009888, .val = 0x000B8000 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x03094000 },
         { .reg = 0x00009888, .val = 0x05090005 },
         { .reg = 0x00009888, .val = 0x0D090974 },
         { .reg = 0x00009888, .val = 0x0F09002A },
         { .reg = 0x00009888, .val = 0x01090000 },
         { .reg = 0x00009888, .val = 0x010A8000 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0002A500 },
         { .reg = 0x00009888, .val = 0x020255AA },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032109 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032428 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030101 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031060 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010003 },
         { .reg = 0x00009888, .val = 0x00020005 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x00050005 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000C },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F030 },
         { .reg = 0x00009888, .val = 0x00020500 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00050500 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x00080A00 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FC0 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext625__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext625__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext625__avg_gpu_core_frequency__max,acmgt3__ext625__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4945, 24, NULL,acmgt3__ext625__stripsfan_objects_cull_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4946, 32, NULL,acmgt3__ext625__stripsfan_objects_cull_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4947, 40, NULL,acmgt3__ext625__stripsfan_objects_cull_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4948, 48, NULL,acmgt3__ext625__stripsfan_objects_cull_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 1413, 56, percentage_max_float,acmgt3__ext625__stripsfan_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 1414, 60, percentage_max_float,acmgt3__ext625__stripsfan_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_float(query, 2459, 64, percentage_max_float,acmgt3__ext625__stripsfan_output_ready_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_float(query, 2460, 68, percentage_max_float,acmgt3__ext625__stripsfan_output_ready_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_float(query, 4949, 72, percentage_max_float,acmgt3__ext625__stripsfan_output_ready_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_float(query, 4950, 76, percentage_max_float,acmgt3__ext625__stripsfan_output_ready_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_float(query, 4951, 80, percentage_max_float,acmgt3__ext625__stripsfan_output_ready_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_float(query, 4952, 84, percentage_max_float,acmgt3__ext625__stripsfan_output_ready_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext626_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext626";
   query->symbol_name = "Ext626";
   query->guid = "0a6dbfd2-9294-4638-98ca-730eb9906e7f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x180703C0 },
         { .reg = 0x00009888, .val = 0x1A070180 },
         { .reg = 0x00009888, .val = 0x18080F00 },
         { .reg = 0x00009888, .val = 0x1A080180 },
         { .reg = 0x00009888, .val = 0x04072100 },
         { .reg = 0x00009888, .val = 0x08070840 },
         { .reg = 0x00009888, .val = 0x0A070020 },
         { .reg = 0x00009888, .val = 0x0E0704D4 },
         { .reg = 0x00009888, .val = 0x10070012 },
         { .reg = 0x00009888, .val = 0x14070597 },
         { .reg = 0x00009888, .val = 0x16070015 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0608C310 },
         { .reg = 0x00009888, .val = 0x0A0808E4 },
         { .reg = 0x00009888, .val = 0x0C080022 },
         { .reg = 0x00009888, .val = 0x100809A7 },
         { .reg = 0x00009888, .val = 0x12080025 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0009E38C },
         { .reg = 0x00009888, .val = 0x000A95A5 },
         { .reg = 0x00009888, .val = 0x020AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C63 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030060 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext626__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext626__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext626__avg_gpu_core_frequency__max,acmgt3__ext626__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1425, 24, NULL,acmgt3__ext626__urb_read_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1426, 32, NULL,acmgt3__ext626__urb_write_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1427, 40, NULL,acmgt3__ext626__urb_cross_slice_read_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext627_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext627";
   query->symbol_name = "Ext627";
   query->guid = "59af2a26-e755-437d-9bf0-8ce5ac59c5e3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x190703C0 },
         { .reg = 0x00009888, .val = 0x1B070180 },
         { .reg = 0x00009888, .val = 0x19080F00 },
         { .reg = 0x00009888, .val = 0x1B080180 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x05072100 },
         { .reg = 0x00009888, .val = 0x09070840 },
         { .reg = 0x00009888, .val = 0x0B070020 },
         { .reg = 0x00009888, .val = 0x0F0704D4 },
         { .reg = 0x00009888, .val = 0x11070012 },
         { .reg = 0x00009888, .val = 0x15070597 },
         { .reg = 0x00009888, .val = 0x17070015 },
         { .reg = 0x00009888, .val = 0x01070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x05080000 },
         { .reg = 0x00009888, .val = 0x0708C310 },
         { .reg = 0x00009888, .val = 0x0B0808E4 },
         { .reg = 0x00009888, .val = 0x0D080022 },
         { .reg = 0x00009888, .val = 0x110809A7 },
         { .reg = 0x00009888, .val = 0x13080025 },
         { .reg = 0x00009888, .val = 0x09080000 },
         { .reg = 0x00009888, .val = 0x01080000 },
         { .reg = 0x00009888, .val = 0x03080000 },
         { .reg = 0x00009888, .val = 0x0109E38C },
         { .reg = 0x00009888, .val = 0x010A95A5 },
         { .reg = 0x00009888, .val = 0x030AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C63 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030060 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext627__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext627__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext627__avg_gpu_core_frequency__max,acmgt3__ext627__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1428, 24, NULL,acmgt3__ext627__urb_read_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1429, 32, NULL,acmgt3__ext627__urb_write_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1430, 40, NULL,acmgt3__ext627__urb_cross_slice_read_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext628_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext628";
   query->symbol_name = "Ext628";
   query->guid = "07ea29bd-3559-458b-8aa8-75bbdde0f619";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x180703C0 },
         { .reg = 0x00009888, .val = 0x1A070180 },
         { .reg = 0x00009888, .val = 0x18080F00 },
         { .reg = 0x00009888, .val = 0x1A080180 },
         { .reg = 0x00009888, .val = 0x04072100 },
         { .reg = 0x00009888, .val = 0x08070840 },
         { .reg = 0x00009888, .val = 0x0A070020 },
         { .reg = 0x00009888, .val = 0x0E0704D4 },
         { .reg = 0x00009888, .val = 0x10070012 },
         { .reg = 0x00009888, .val = 0x14070597 },
         { .reg = 0x00009888, .val = 0x16070015 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0608C310 },
         { .reg = 0x00009888, .val = 0x0A0808E4 },
         { .reg = 0x00009888, .val = 0x0C080022 },
         { .reg = 0x00009888, .val = 0x100809A7 },
         { .reg = 0x00009888, .val = 0x12080025 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0009E38C },
         { .reg = 0x00009888, .val = 0x000A95A5 },
         { .reg = 0x00009888, .val = 0x020AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C63 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030060 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext628__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext628__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext628__avg_gpu_core_frequency__max,acmgt3__ext628__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 3151, 24, NULL,acmgt3__ext628__urb_read_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 3152, 32, NULL,acmgt3__ext628__urb_write_slice2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 3153, 40, NULL,acmgt3__ext628__urb_cross_slice_read_slice2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext629_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext629";
   query->symbol_name = "Ext629";
   query->guid = "c0a396af-30c1-458b-ae7f-e39cd59e6e99";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x190703C0 },
         { .reg = 0x00009888, .val = 0x1B070180 },
         { .reg = 0x00009888, .val = 0x19080F00 },
         { .reg = 0x00009888, .val = 0x1B080180 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x05072100 },
         { .reg = 0x00009888, .val = 0x09070840 },
         { .reg = 0x00009888, .val = 0x0B070020 },
         { .reg = 0x00009888, .val = 0x0F0704D4 },
         { .reg = 0x00009888, .val = 0x11070012 },
         { .reg = 0x00009888, .val = 0x15070597 },
         { .reg = 0x00009888, .val = 0x17070015 },
         { .reg = 0x00009888, .val = 0x01070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x05080000 },
         { .reg = 0x00009888, .val = 0x0708C310 },
         { .reg = 0x00009888, .val = 0x0B0808E4 },
         { .reg = 0x00009888, .val = 0x0D080022 },
         { .reg = 0x00009888, .val = 0x110809A7 },
         { .reg = 0x00009888, .val = 0x13080025 },
         { .reg = 0x00009888, .val = 0x09080000 },
         { .reg = 0x00009888, .val = 0x01080000 },
         { .reg = 0x00009888, .val = 0x03080000 },
         { .reg = 0x00009888, .val = 0x0109E38C },
         { .reg = 0x00009888, .val = 0x010A95A5 },
         { .reg = 0x00009888, .val = 0x030AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C63 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030060 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext629__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext629__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext629__avg_gpu_core_frequency__max,acmgt3__ext629__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 3154, 24, NULL,acmgt3__ext629__urb_read_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 3155, 32, NULL,acmgt3__ext629__urb_write_slice3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 3156, 40, NULL,acmgt3__ext629__urb_cross_slice_read_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext630_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext630";
   query->symbol_name = "Ext630";
   query->guid = "fdbc72a7-fd96-4120-b5fb-f7340e4ef6aa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x180703C0 },
         { .reg = 0x00009888, .val = 0x1A070180 },
         { .reg = 0x00009888, .val = 0x18080F00 },
         { .reg = 0x00009888, .val = 0x1A080180 },
         { .reg = 0x00009888, .val = 0x04072100 },
         { .reg = 0x00009888, .val = 0x08070840 },
         { .reg = 0x00009888, .val = 0x0A070020 },
         { .reg = 0x00009888, .val = 0x0E0704D4 },
         { .reg = 0x00009888, .val = 0x10070012 },
         { .reg = 0x00009888, .val = 0x14070597 },
         { .reg = 0x00009888, .val = 0x16070015 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0608C310 },
         { .reg = 0x00009888, .val = 0x0A0808E4 },
         { .reg = 0x00009888, .val = 0x0C080022 },
         { .reg = 0x00009888, .val = 0x100809A7 },
         { .reg = 0x00009888, .val = 0x12080025 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0009E38C },
         { .reg = 0x00009888, .val = 0x000A95A5 },
         { .reg = 0x00009888, .val = 0x020AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C63 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030060 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext630__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext630__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext630__avg_gpu_core_frequency__max,acmgt3__ext630__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4953, 24, NULL,acmgt3__ext630__urb_read_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4954, 32, NULL,acmgt3__ext630__urb_write_slice4__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 4955, 40, NULL,acmgt3__ext630__urb_cross_slice_read_slice4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext631_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext631";
   query->symbol_name = "Ext631";
   query->guid = "8a190eb3-4bf6-456f-ba97-6ad3dd9f9041";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x190703C0 },
         { .reg = 0x00009888, .val = 0x1B070180 },
         { .reg = 0x00009888, .val = 0x19080F00 },
         { .reg = 0x00009888, .val = 0x1B080180 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x05072100 },
         { .reg = 0x00009888, .val = 0x09070840 },
         { .reg = 0x00009888, .val = 0x0B070020 },
         { .reg = 0x00009888, .val = 0x0F0704D4 },
         { .reg = 0x00009888, .val = 0x11070012 },
         { .reg = 0x00009888, .val = 0x15070597 },
         { .reg = 0x00009888, .val = 0x17070015 },
         { .reg = 0x00009888, .val = 0x01070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x05080000 },
         { .reg = 0x00009888, .val = 0x0708C310 },
         { .reg = 0x00009888, .val = 0x0B0808E4 },
         { .reg = 0x00009888, .val = 0x0D080022 },
         { .reg = 0x00009888, .val = 0x110809A7 },
         { .reg = 0x00009888, .val = 0x13080025 },
         { .reg = 0x00009888, .val = 0x09080000 },
         { .reg = 0x00009888, .val = 0x01080000 },
         { .reg = 0x00009888, .val = 0x03080000 },
         { .reg = 0x00009888, .val = 0x0109E38C },
         { .reg = 0x00009888, .val = 0x010A95A5 },
         { .reg = 0x00009888, .val = 0x030AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C63 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030060 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext631__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext631__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext631__avg_gpu_core_frequency__max,acmgt3__ext631__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4956, 24, NULL,acmgt3__ext631__urb_read_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4957, 32, NULL,acmgt3__ext631__urb_write_slice5__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 4958, 40, NULL,acmgt3__ext631__urb_cross_slice_read_slice5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext632_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext632";
   query->symbol_name = "Ext632";
   query->guid = "690cf267-acc5-4f2a-a9d9-e424d39d0085";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x180703C0 },
         { .reg = 0x00009888, .val = 0x1A070180 },
         { .reg = 0x00009888, .val = 0x18080F00 },
         { .reg = 0x00009888, .val = 0x1A080180 },
         { .reg = 0x00009888, .val = 0x04072100 },
         { .reg = 0x00009888, .val = 0x08070840 },
         { .reg = 0x00009888, .val = 0x0A070020 },
         { .reg = 0x00009888, .val = 0x0E0704D4 },
         { .reg = 0x00009888, .val = 0x10070012 },
         { .reg = 0x00009888, .val = 0x14070597 },
         { .reg = 0x00009888, .val = 0x16070015 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0608C310 },
         { .reg = 0x00009888, .val = 0x0A0808E4 },
         { .reg = 0x00009888, .val = 0x0C080022 },
         { .reg = 0x00009888, .val = 0x100809A7 },
         { .reg = 0x00009888, .val = 0x12080025 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0009E38C },
         { .reg = 0x00009888, .val = 0x000A95A5 },
         { .reg = 0x00009888, .val = 0x020AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C63 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030060 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext632__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext632__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext632__avg_gpu_core_frequency__max,acmgt3__ext632__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4959, 24, NULL,acmgt3__ext632__urb_read_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4960, 32, NULL,acmgt3__ext632__urb_write_slice6__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 4961, 40, NULL,acmgt3__ext632__urb_cross_slice_read_slice6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext633_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext633";
   query->symbol_name = "Ext633";
   query->guid = "7dfd1792-f14e-47cb-b3c3-969deb04e830";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x190703C0 },
         { .reg = 0x00009888, .val = 0x1B070180 },
         { .reg = 0x00009888, .val = 0x19080F00 },
         { .reg = 0x00009888, .val = 0x1B080180 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x05072100 },
         { .reg = 0x00009888, .val = 0x09070840 },
         { .reg = 0x00009888, .val = 0x0B070020 },
         { .reg = 0x00009888, .val = 0x0F0704D4 },
         { .reg = 0x00009888, .val = 0x11070012 },
         { .reg = 0x00009888, .val = 0x15070597 },
         { .reg = 0x00009888, .val = 0x17070015 },
         { .reg = 0x00009888, .val = 0x01070000 },
         { .reg = 0x00009888, .val = 0x03070000 },
         { .reg = 0x00009888, .val = 0x05080000 },
         { .reg = 0x00009888, .val = 0x0708C310 },
         { .reg = 0x00009888, .val = 0x0B0808E4 },
         { .reg = 0x00009888, .val = 0x0D080022 },
         { .reg = 0x00009888, .val = 0x110809A7 },
         { .reg = 0x00009888, .val = 0x13080025 },
         { .reg = 0x00009888, .val = 0x09080000 },
         { .reg = 0x00009888, .val = 0x01080000 },
         { .reg = 0x00009888, .val = 0x03080000 },
         { .reg = 0x00009888, .val = 0x0109E38C },
         { .reg = 0x00009888, .val = 0x010A95A5 },
         { .reg = 0x00009888, .val = 0x030AA95A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C63 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030060 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030060 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030003 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext633__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext633__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext633__avg_gpu_core_frequency__max,acmgt3__ext633__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4962, 24, NULL,acmgt3__ext633__urb_read_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4963, 32, NULL,acmgt3__ext633__urb_write_slice7__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 4964, 40, NULL,acmgt3__ext633__urb_cross_slice_read_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext634_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext634";
   query->symbol_name = "Ext634";
   query->guid = "255faebf-ef8b-4fa1-9d3c-d82b46a8a9f1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14040400 },
         { .reg = 0x00009888, .val = 0x1C040200 },
         { .reg = 0x00009888, .val = 0x24040200 },
         { .reg = 0x00009888, .val = 0x2C040200 },
         { .reg = 0x00009888, .val = 0x38040010 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x000401C0 },
         { .reg = 0x00009888, .val = 0x020400CE },
         { .reg = 0x00009888, .val = 0x04040000 },
         { .reg = 0x00009888, .val = 0x06040081 },
         { .reg = 0x00009888, .val = 0x08040248 },
         { .reg = 0x00009888, .val = 0x0A04040A },
         { .reg = 0x00009888, .val = 0x0C040491 },
         { .reg = 0x00009888, .val = 0x0E040658 },
         { .reg = 0x00009888, .val = 0x1004081A },
         { .reg = 0x00009888, .val = 0x120408A1 },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081555 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext634__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext634__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext634__avg_gpu_core_frequency__max,acmgt3__ext634__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 1471, 24, percentage_max_float,acmgt3__ext634__command_parser_compute_engine_busy_ccs0__read);

      intel_perf_query_add_counter_float(query, 1472, 28, percentage_max_float,acmgt3__ext634__command_parser_compute_engine_busy_ccs1__read);

      intel_perf_query_add_counter_float(query, 1473, 32, percentage_max_float,acmgt3__ext634__command_parser_compute_engine_busy_ccs2__read);

      intel_perf_query_add_counter_float(query, 1474, 36, percentage_max_float,acmgt3__ext634__command_parser_compute_engine_busy_ccs3__read);

      intel_perf_query_add_counter_float(query, 2443, 40, percentage_max_float,acmgt3__ext634__command_parser_compute_engine_busy__read);

      intel_perf_query_add_counter_float(query, 1475, 44, percentage_max_float,acmgt3__ext634__command_parser_render_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext635_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext635";
   query->symbol_name = "Ext635";
   query->guid = "53827355-f253-40a1-b02d-b07b591aa394";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x420A0010 },
         { .reg = 0x00009888, .val = 0x18130100 },
         { .reg = 0x00009888, .val = 0x040A001E },
         { .reg = 0x00009888, .val = 0x0C0A0400 },
         { .reg = 0x00009888, .val = 0x0E0A0491 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x00105A80 },
         { .reg = 0x00009888, .val = 0x02100001 },
         { .reg = 0x00009888, .val = 0x00125000 },
         { .reg = 0x00009888, .val = 0x02120001 },
         { .reg = 0x00009888, .val = 0x00130000 },
         { .reg = 0x00009888, .val = 0x08130800 },
         { .reg = 0x00009888, .val = 0x0A1308A1 },
         { .reg = 0x00009884, .val = 0x00000005 },
         { .reg = 0x00009888, .val = 0x420A0010 },
         { .reg = 0x00009888, .val = 0x18130100 },
         { .reg = 0x00009888, .val = 0x040A001E },
         { .reg = 0x00009888, .val = 0x120A0400 },
         { .reg = 0x00009888, .val = 0x140A0491 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x021015A8 },
         { .reg = 0x00009888, .val = 0x02121500 },
         { .reg = 0x00009888, .val = 0x00130000 },
         { .reg = 0x00009888, .val = 0x0E130800 },
         { .reg = 0x00009888, .val = 0x101308A1 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x18010010 },
         { .reg = 0x00009888, .val = 0x02010002 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x08010081 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x00080015 },
         { .reg = 0x00009888, .val = 0x00055540 },
         { .reg = 0x00009888, .val = 0x02052AA9 },
         { .reg = 0x00009888, .val = 0x00035A92 },
         { .reg = 0x00009888, .val = 0x02035B6D },
         { .reg = 0x00009888, .val = 0x04035B6D },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030846 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x420318C0 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030002 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00038000 },
         { .reg = 0x0000D964, .val = 0x00008FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext635__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext635__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext635__avg_gpu_core_frequency__max,acmgt3__ext635__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 1483, 24, percentage_max_float,acmgt3__ext635__command_parser_copy_engine_busy__read);

      intel_perf_query_add_counter_float(query, 1484, 28, percentage_max_float,acmgt3__ext635__command_parser_video_engine_busy_vdbox0__read);

      intel_perf_query_add_counter_float(query, 1486, 32, percentage_max_float,acmgt3__ext635__command_parser_video_enhancement_engine_busy_vebox0__read);

      intel_perf_query_add_counter_float(query, 1485, 36, percentage_max_float,acmgt3__ext635__command_parser_video_engine_busy_vdbox1__read);

      intel_perf_query_add_counter_float(query, 1487, 40, percentage_max_float,acmgt3__ext635__command_parser_video_enhancement_engine_busy_vebox1__read);

      intel_perf_query_add_counter_float(query, 2444, 44, percentage_max_float,acmgt3__ext635__command_parser_video_engine_busy__read);

      intel_perf_query_add_counter_float(query, 2445, 48, percentage_max_float,acmgt3__ext635__command_parser_video_enhancement_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext636_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext636";
   query->symbol_name = "Ext636";
   query->guid = "1902b796-e21e-40b4-8132-0fd73e341735";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C04001F },
         { .reg = 0x00009888, .val = 0x2404001F },
         { .reg = 0x00009888, .val = 0x2C04001F },
         { .reg = 0x00009888, .val = 0x340403E0 },
         { .reg = 0x00009888, .val = 0x4004001F },
         { .reg = 0x00009888, .val = 0x0001FC03 },
         { .reg = 0x00009888, .val = 0x000435BB },
         { .reg = 0x00009888, .val = 0x02040660 },
         { .reg = 0x00009888, .val = 0x04048C00 },
         { .reg = 0x00009888, .val = 0x06040022 },
         { .reg = 0x00009888, .val = 0x0E040900 },
         { .reg = 0x00009888, .val = 0x10040A20 },
         { .reg = 0x00009888, .val = 0x12040010 },
         { .reg = 0x00009888, .val = 0x14040008 },
         { .reg = 0x00009888, .val = 0x00080005 },
         { .reg = 0x00009888, .val = 0x02085550 },
         { .reg = 0x00009888, .val = 0x00030012 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext636__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext636__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext636__avg_gpu_core_frequency__max,acmgt3__ext636__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1476, 24, NULL,acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs0__read);

      intel_perf_query_add_counter_uint64(query, 1477, 32, NULL,acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs1__read);

      intel_perf_query_add_counter_uint64(query, 1478, 40, NULL,acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs2__read);

      intel_perf_query_add_counter_uint64(query, 1479, 48, NULL,acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count_ccs3__read);

      intel_perf_query_add_counter_uint64(query, 2446, 56, NULL,acmgt3__ext636__command_parser_compute_engine_dispatch_kernel_count__read);

      intel_perf_query_add_counter_uint64(query, 1480, 64, NULL,acmgt3__ext636__command_parser_render_engine_dispatch_kernel_count__read);

      intel_perf_query_add_counter_uint64(query, 1482, 72, NULL,acmgt3__ext636__command_parser_flush_count__read);

      intel_perf_query_add_counter_uint64(query, 1481, 80, NULL,acmgt3__ext636__command_parser_render_engine_draw_count__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext637_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext637";
   query->symbol_name = "Ext637";
   query->guid = "7ec62259-93dc-464b-99ea-629737cf9861";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0A900236 },
         { .reg = 0x00009888, .val = 0x0C90016A },
         { .reg = 0x00009888, .val = 0x009042B2 },
         { .reg = 0x00009888, .val = 0x02904E9C },
         { .reg = 0x00009888, .val = 0x04900717 },
         { .reg = 0x00009888, .val = 0x069000E6 },
         { .reg = 0x00009888, .val = 0x08900840 },
         { .reg = 0x00009888, .val = 0x00815555 },
         { .reg = 0x00009888, .val = 0x02815415 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283A82A },
         { .reg = 0x00009888, .val = 0x0084E7FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865415 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x02875415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext637__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext637__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext637__avg_gpu_core_frequency__max,acmgt3__ext637__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1584, 24, percentage_max_float,acmgt3__ext637__xve_stall_aluwr_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1585, 28, percentage_max_float,acmgt3__ext637__xve_stall_barrier_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1586, 32, percentage_max_float,acmgt3__ext637__xve_stall_instfetch_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1587, 36, percentage_max_float,acmgt3__ext637__xve_stall_other_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1588, 40, percentage_max_float,acmgt3__ext637__xve_stall_sbid_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1589, 44, percentage_max_float,acmgt3__ext637__xve_stall_sendwr_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1590, 48, percentage_max_float,acmgt3__ext637__xve_shared_function_access_hold_xecore0_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext638_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext638";
   query->symbol_name = "Ext638";
   query->guid = "32b54940-c66d-4636-b61a-a8f6b46d32d0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0AB00236 },
         { .reg = 0x00009888, .val = 0x0CB0016A },
         { .reg = 0x00009888, .val = 0x00B042B2 },
         { .reg = 0x00009888, .val = 0x02B04E9C },
         { .reg = 0x00009888, .val = 0x04B00717 },
         { .reg = 0x00009888, .val = 0x06B000E6 },
         { .reg = 0x00009888, .val = 0x08B00840 },
         { .reg = 0x00009888, .val = 0x00A15555 },
         { .reg = 0x00009888, .val = 0x02A15415 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3A82A },
         { .reg = 0x00009888, .val = 0x00A4E7FF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65415 },
         { .reg = 0x00009888, .val = 0x00A75555 },
         { .reg = 0x00009888, .val = 0x02A75415 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext638__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext638__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext638__avg_gpu_core_frequency__max,acmgt3__ext638__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1591, 24, percentage_max_float,acmgt3__ext638__xve_stall_aluwr_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1592, 28, percentage_max_float,acmgt3__ext638__xve_stall_barrier_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1593, 32, percentage_max_float,acmgt3__ext638__xve_stall_instfetch_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1594, 36, percentage_max_float,acmgt3__ext638__xve_stall_other_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1595, 40, percentage_max_float,acmgt3__ext638__xve_stall_sbid_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1596, 44, percentage_max_float,acmgt3__ext638__xve_stall_sendwr_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1597, 48, percentage_max_float,acmgt3__ext638__xve_shared_function_access_hold_xecore1_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext639_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext639";
   query->symbol_name = "Ext639";
   query->guid = "10e959bd-ef25-44ff-9d2b-b8c773e6087c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0AD00236 },
         { .reg = 0x00009888, .val = 0x0CD0016A },
         { .reg = 0x00009888, .val = 0x00D042B2 },
         { .reg = 0x00009888, .val = 0x02D04E9C },
         { .reg = 0x00009888, .val = 0x04D00717 },
         { .reg = 0x00009888, .val = 0x06D000E6 },
         { .reg = 0x00009888, .val = 0x08D00840 },
         { .reg = 0x00009888, .val = 0x00C15555 },
         { .reg = 0x00009888, .val = 0x02C15415 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3A82A },
         { .reg = 0x00009888, .val = 0x00C4E7FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65415 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x02C75415 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207A82A },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009888, .val = 0x0002E7FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext639__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext639__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext639__avg_gpu_core_frequency__max,acmgt3__ext639__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1598, 24, percentage_max_float,acmgt3__ext639__xve_stall_aluwr_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1599, 28, percentage_max_float,acmgt3__ext639__xve_stall_barrier_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1600, 32, percentage_max_float,acmgt3__ext639__xve_stall_instfetch_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1601, 36, percentage_max_float,acmgt3__ext639__xve_stall_other_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1602, 40, percentage_max_float,acmgt3__ext639__xve_stall_sbid_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1603, 44, percentage_max_float,acmgt3__ext639__xve_stall_sendwr_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1604, 48, percentage_max_float,acmgt3__ext639__xve_shared_function_access_hold_xecore2_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext640_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext640";
   query->symbol_name = "Ext640";
   query->guid = "371d7a11-3eef-4da8-88e5-fd25d85d10d6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0AF00236 },
         { .reg = 0x00009888, .val = 0x0CF0016A },
         { .reg = 0x00009888, .val = 0x00F042B2 },
         { .reg = 0x00009888, .val = 0x02F04E9C },
         { .reg = 0x00009888, .val = 0x04F00717 },
         { .reg = 0x00009888, .val = 0x06F000E6 },
         { .reg = 0x00009888, .val = 0x08F00840 },
         { .reg = 0x00009888, .val = 0x00E15555 },
         { .reg = 0x00009888, .val = 0x02E15415 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3A82A },
         { .reg = 0x00009888, .val = 0x00E4E7FF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65415 },
         { .reg = 0x00009888, .val = 0x00E75555 },
         { .reg = 0x00009888, .val = 0x02E75415 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075415 },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext640__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext640__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext640__avg_gpu_core_frequency__max,acmgt3__ext640__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1605, 24, percentage_max_float,acmgt3__ext640__xve_stall_aluwr_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1606, 28, percentage_max_float,acmgt3__ext640__xve_stall_barrier_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1607, 32, percentage_max_float,acmgt3__ext640__xve_stall_instfetch_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1608, 36, percentage_max_float,acmgt3__ext640__xve_stall_other_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1609, 40, percentage_max_float,acmgt3__ext640__xve_stall_sbid_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1610, 44, percentage_max_float,acmgt3__ext640__xve_stall_sendwr_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1611, 48, percentage_max_float,acmgt3__ext640__xve_shared_function_access_hold_xecore3_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext641_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext641";
   query->symbol_name = "Ext641";
   query->guid = "a5be5bd5-b23d-48bb-b56b-ae9fd49acca4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B900236 },
         { .reg = 0x00009888, .val = 0x0D90016A },
         { .reg = 0x00009888, .val = 0x019042B2 },
         { .reg = 0x00009888, .val = 0x03904E9C },
         { .reg = 0x00009888, .val = 0x05900717 },
         { .reg = 0x00009888, .val = 0x079000E6 },
         { .reg = 0x00009888, .val = 0x09900840 },
         { .reg = 0x00009888, .val = 0x01815555 },
         { .reg = 0x00009888, .val = 0x03815415 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383A82A },
         { .reg = 0x00009888, .val = 0x0184E7FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865415 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x03875415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308A82A },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext641__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext641__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext641__avg_gpu_core_frequency__max,acmgt3__ext641__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1612, 24, percentage_max_float,acmgt3__ext641__xve_stall_aluwr_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1613, 28, percentage_max_float,acmgt3__ext641__xve_stall_barrier_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1614, 32, percentage_max_float,acmgt3__ext641__xve_stall_instfetch_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1615, 36, percentage_max_float,acmgt3__ext641__xve_stall_other_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1616, 40, percentage_max_float,acmgt3__ext641__xve_stall_sbid_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1617, 44, percentage_max_float,acmgt3__ext641__xve_stall_sendwr_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1618, 48, percentage_max_float,acmgt3__ext641__xve_shared_function_access_hold_xecore4_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext642_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext642";
   query->symbol_name = "Ext642";
   query->guid = "dd277896-494e-4db9-8da4-9efb89846b6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0BB00236 },
         { .reg = 0x00009888, .val = 0x0DB0016A },
         { .reg = 0x00009888, .val = 0x01B042B2 },
         { .reg = 0x00009888, .val = 0x03B04E9C },
         { .reg = 0x00009888, .val = 0x05B00717 },
         { .reg = 0x00009888, .val = 0x07B000E6 },
         { .reg = 0x00009888, .val = 0x09B00840 },
         { .reg = 0x00009888, .val = 0x01A15555 },
         { .reg = 0x00009888, .val = 0x03A15415 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3A82A },
         { .reg = 0x00009888, .val = 0x01A4E7FF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65415 },
         { .reg = 0x00009888, .val = 0x01A75555 },
         { .reg = 0x00009888, .val = 0x03A75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FC3F },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009888, .val = 0x0101E7FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext642__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext642__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext642__avg_gpu_core_frequency__max,acmgt3__ext642__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1619, 24, percentage_max_float,acmgt3__ext642__xve_stall_aluwr_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1620, 28, percentage_max_float,acmgt3__ext642__xve_stall_barrier_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1621, 32, percentage_max_float,acmgt3__ext642__xve_stall_instfetch_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1622, 36, percentage_max_float,acmgt3__ext642__xve_stall_other_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1623, 40, percentage_max_float,acmgt3__ext642__xve_stall_sbid_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1624, 44, percentage_max_float,acmgt3__ext642__xve_stall_sendwr_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1625, 48, percentage_max_float,acmgt3__ext642__xve_shared_function_access_hold_xecore5_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext643_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext643";
   query->symbol_name = "Ext643";
   query->guid = "4a13f620-9b8f-41e8-9189-0712948bc7ed";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0BD00236 },
         { .reg = 0x00009888, .val = 0x0DD0016A },
         { .reg = 0x00009888, .val = 0x01D042B2 },
         { .reg = 0x00009888, .val = 0x03D04E9C },
         { .reg = 0x00009888, .val = 0x05D00717 },
         { .reg = 0x00009888, .val = 0x07D000E6 },
         { .reg = 0x00009888, .val = 0x09D00840 },
         { .reg = 0x00009888, .val = 0x01C15555 },
         { .reg = 0x00009888, .val = 0x03C15415 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3A82A },
         { .reg = 0x00009888, .val = 0x01C4E7FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65415 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x03C75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307A82A },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009888, .val = 0x0102E7FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext643__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext643__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext643__avg_gpu_core_frequency__max,acmgt3__ext643__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1626, 24, percentage_max_float,acmgt3__ext643__xve_stall_aluwr_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1627, 28, percentage_max_float,acmgt3__ext643__xve_stall_barrier_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1628, 32, percentage_max_float,acmgt3__ext643__xve_stall_instfetch_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1629, 36, percentage_max_float,acmgt3__ext643__xve_stall_other_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1630, 40, percentage_max_float,acmgt3__ext643__xve_stall_sbid_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1631, 44, percentage_max_float,acmgt3__ext643__xve_stall_sendwr_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1632, 48, percentage_max_float,acmgt3__ext643__xve_shared_function_access_hold_xecore6_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext644_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext644";
   query->symbol_name = "Ext644";
   query->guid = "c6b5a675-c1a9-4e9c-bf68-af0b1ad8dc08";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0BF00236 },
         { .reg = 0x00009888, .val = 0x0DF0016A },
         { .reg = 0x00009888, .val = 0x01F042B2 },
         { .reg = 0x00009888, .val = 0x03F04E9C },
         { .reg = 0x00009888, .val = 0x05F00717 },
         { .reg = 0x00009888, .val = 0x07F000E6 },
         { .reg = 0x00009888, .val = 0x09F00840 },
         { .reg = 0x00009888, .val = 0x01E15555 },
         { .reg = 0x00009888, .val = 0x03E15415 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3A82A },
         { .reg = 0x00009888, .val = 0x01E4E7FF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65415 },
         { .reg = 0x00009888, .val = 0x01E75555 },
         { .reg = 0x00009888, .val = 0x03E75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075415 },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext644__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext644__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext644__avg_gpu_core_frequency__max,acmgt3__ext644__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1633, 24, percentage_max_float,acmgt3__ext644__xve_stall_aluwr_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1634, 28, percentage_max_float,acmgt3__ext644__xve_stall_barrier_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1635, 32, percentage_max_float,acmgt3__ext644__xve_stall_instfetch_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1636, 36, percentage_max_float,acmgt3__ext644__xve_stall_other_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1637, 40, percentage_max_float,acmgt3__ext644__xve_stall_sbid_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1638, 44, percentage_max_float,acmgt3__ext644__xve_stall_sendwr_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1639, 48, percentage_max_float,acmgt3__ext644__xve_shared_function_access_hold_xecore7_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext645_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext645";
   query->symbol_name = "Ext645";
   query->guid = "81a0ff81-482c-4fea-93c8-f2ad4cc6a42e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0A900236 },
         { .reg = 0x00009888, .val = 0x0C90016A },
         { .reg = 0x00009888, .val = 0x009042B2 },
         { .reg = 0x00009888, .val = 0x02904E9C },
         { .reg = 0x00009888, .val = 0x04900717 },
         { .reg = 0x00009888, .val = 0x069000E6 },
         { .reg = 0x00009888, .val = 0x08900840 },
         { .reg = 0x00009888, .val = 0x00815555 },
         { .reg = 0x00009888, .val = 0x02815415 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283A82A },
         { .reg = 0x00009888, .val = 0x0084E7FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865415 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x02875415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext645__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext645__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext645__avg_gpu_core_frequency__max,acmgt3__ext645__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3157, 24, percentage_max_float,acmgt3__ext645__xve_stall_aluwr_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3158, 28, percentage_max_float,acmgt3__ext645__xve_stall_barrier_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3159, 32, percentage_max_float,acmgt3__ext645__xve_stall_instfetch_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3160, 36, percentage_max_float,acmgt3__ext645__xve_stall_other_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3161, 40, percentage_max_float,acmgt3__ext645__xve_stall_sbid_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3162, 44, percentage_max_float,acmgt3__ext645__xve_stall_sendwr_xecore8_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3163, 48, percentage_max_float,acmgt3__ext645__xve_shared_function_access_hold_xecore8_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext646_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext646";
   query->symbol_name = "Ext646";
   query->guid = "51ef51ba-0cec-4c46-8cf9-65b6b366a20f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AB00236 },
         { .reg = 0x00009888, .val = 0x0CB0016A },
         { .reg = 0x00009888, .val = 0x00B042B2 },
         { .reg = 0x00009888, .val = 0x02B04E9C },
         { .reg = 0x00009888, .val = 0x04B00717 },
         { .reg = 0x00009888, .val = 0x06B000E6 },
         { .reg = 0x00009888, .val = 0x08B00840 },
         { .reg = 0x00009888, .val = 0x00A15555 },
         { .reg = 0x00009888, .val = 0x02A15415 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3A82A },
         { .reg = 0x00009888, .val = 0x00A4E7FF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65415 },
         { .reg = 0x00009888, .val = 0x00A75555 },
         { .reg = 0x00009888, .val = 0x02A75415 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext646__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext646__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext646__avg_gpu_core_frequency__max,acmgt3__ext646__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3164, 24, percentage_max_float,acmgt3__ext646__xve_stall_aluwr_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3165, 28, percentage_max_float,acmgt3__ext646__xve_stall_barrier_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3166, 32, percentage_max_float,acmgt3__ext646__xve_stall_instfetch_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3167, 36, percentage_max_float,acmgt3__ext646__xve_stall_other_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3168, 40, percentage_max_float,acmgt3__ext646__xve_stall_sbid_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3169, 44, percentage_max_float,acmgt3__ext646__xve_stall_sendwr_xecore9_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3170, 48, percentage_max_float,acmgt3__ext646__xve_shared_function_access_hold_xecore9_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext647_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext647";
   query->symbol_name = "Ext647";
   query->guid = "80b23cbe-5ff0-49aa-9591-7f63c958e510";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AD00236 },
         { .reg = 0x00009888, .val = 0x0CD0016A },
         { .reg = 0x00009888, .val = 0x00D042B2 },
         { .reg = 0x00009888, .val = 0x02D04E9C },
         { .reg = 0x00009888, .val = 0x04D00717 },
         { .reg = 0x00009888, .val = 0x06D000E6 },
         { .reg = 0x00009888, .val = 0x08D00840 },
         { .reg = 0x00009888, .val = 0x00C15555 },
         { .reg = 0x00009888, .val = 0x02C15415 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3A82A },
         { .reg = 0x00009888, .val = 0x00C4E7FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65415 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x02C75415 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207A82A },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009888, .val = 0x0002E7FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext647__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext647__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext647__avg_gpu_core_frequency__max,acmgt3__ext647__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3171, 24, percentage_max_float,acmgt3__ext647__xve_stall_aluwr_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3172, 28, percentage_max_float,acmgt3__ext647__xve_stall_barrier_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3173, 32, percentage_max_float,acmgt3__ext647__xve_stall_instfetch_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3174, 36, percentage_max_float,acmgt3__ext647__xve_stall_other_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3175, 40, percentage_max_float,acmgt3__ext647__xve_stall_sbid_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3176, 44, percentage_max_float,acmgt3__ext647__xve_stall_sendwr_xecore10_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3177, 48, percentage_max_float,acmgt3__ext647__xve_shared_function_access_hold_xecore10_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext648_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext648";
   query->symbol_name = "Ext648";
   query->guid = "c8baa82f-efca-44de-9464-75f7653c1ecd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AF00236 },
         { .reg = 0x00009888, .val = 0x0CF0016A },
         { .reg = 0x00009888, .val = 0x00F042B2 },
         { .reg = 0x00009888, .val = 0x02F04E9C },
         { .reg = 0x00009888, .val = 0x04F00717 },
         { .reg = 0x00009888, .val = 0x06F000E6 },
         { .reg = 0x00009888, .val = 0x08F00840 },
         { .reg = 0x00009888, .val = 0x00E15555 },
         { .reg = 0x00009888, .val = 0x02E15415 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3A82A },
         { .reg = 0x00009888, .val = 0x00E4E7FF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65415 },
         { .reg = 0x00009888, .val = 0x00E75555 },
         { .reg = 0x00009888, .val = 0x02E75415 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075415 },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext648__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext648__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext648__avg_gpu_core_frequency__max,acmgt3__ext648__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3178, 24, percentage_max_float,acmgt3__ext648__xve_stall_aluwr_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3179, 28, percentage_max_float,acmgt3__ext648__xve_stall_barrier_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3180, 32, percentage_max_float,acmgt3__ext648__xve_stall_instfetch_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3181, 36, percentage_max_float,acmgt3__ext648__xve_stall_other_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3182, 40, percentage_max_float,acmgt3__ext648__xve_stall_sbid_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3183, 44, percentage_max_float,acmgt3__ext648__xve_stall_sendwr_xecore11_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3184, 48, percentage_max_float,acmgt3__ext648__xve_shared_function_access_hold_xecore11_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext649_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext649";
   query->symbol_name = "Ext649";
   query->guid = "417cd1e9-b680-4389-99a0-d11bd6076465";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0B900236 },
         { .reg = 0x00009888, .val = 0x0D90016A },
         { .reg = 0x00009888, .val = 0x019042B2 },
         { .reg = 0x00009888, .val = 0x03904E9C },
         { .reg = 0x00009888, .val = 0x05900717 },
         { .reg = 0x00009888, .val = 0x079000E6 },
         { .reg = 0x00009888, .val = 0x09900840 },
         { .reg = 0x00009888, .val = 0x01815555 },
         { .reg = 0x00009888, .val = 0x03815415 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383A82A },
         { .reg = 0x00009888, .val = 0x0184E7FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865415 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x03875415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308A82A },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext649__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext649__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext649__avg_gpu_core_frequency__max,acmgt3__ext649__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3185, 24, percentage_max_float,acmgt3__ext649__xve_stall_aluwr_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3186, 28, percentage_max_float,acmgt3__ext649__xve_stall_barrier_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3187, 32, percentage_max_float,acmgt3__ext649__xve_stall_instfetch_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3188, 36, percentage_max_float,acmgt3__ext649__xve_stall_other_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3189, 40, percentage_max_float,acmgt3__ext649__xve_stall_sbid_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3190, 44, percentage_max_float,acmgt3__ext649__xve_stall_sendwr_xecore12_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3191, 48, percentage_max_float,acmgt3__ext649__xve_shared_function_access_hold_xecore12_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext650_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext650";
   query->symbol_name = "Ext650";
   query->guid = "5513c6b2-2b34-43f9-aa42-66ec99231838";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BB00236 },
         { .reg = 0x00009888, .val = 0x0DB0016A },
         { .reg = 0x00009888, .val = 0x01B042B2 },
         { .reg = 0x00009888, .val = 0x03B04E9C },
         { .reg = 0x00009888, .val = 0x05B00717 },
         { .reg = 0x00009888, .val = 0x07B000E6 },
         { .reg = 0x00009888, .val = 0x09B00840 },
         { .reg = 0x00009888, .val = 0x01A15555 },
         { .reg = 0x00009888, .val = 0x03A15415 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3A82A },
         { .reg = 0x00009888, .val = 0x01A4E7FF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65415 },
         { .reg = 0x00009888, .val = 0x01A75555 },
         { .reg = 0x00009888, .val = 0x03A75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FC3F },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009888, .val = 0x0101E7FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext650__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext650__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext650__avg_gpu_core_frequency__max,acmgt3__ext650__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3192, 24, percentage_max_float,acmgt3__ext650__xve_stall_aluwr_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3193, 28, percentage_max_float,acmgt3__ext650__xve_stall_barrier_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3194, 32, percentage_max_float,acmgt3__ext650__xve_stall_instfetch_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3195, 36, percentage_max_float,acmgt3__ext650__xve_stall_other_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3196, 40, percentage_max_float,acmgt3__ext650__xve_stall_sbid_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3197, 44, percentage_max_float,acmgt3__ext650__xve_stall_sendwr_xecore13_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3198, 48, percentage_max_float,acmgt3__ext650__xve_shared_function_access_hold_xecore13_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext651_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext651";
   query->symbol_name = "Ext651";
   query->guid = "e219ac69-3ea7-4ef4-90fc-43da93940404";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BD00236 },
         { .reg = 0x00009888, .val = 0x0DD0016A },
         { .reg = 0x00009888, .val = 0x01D042B2 },
         { .reg = 0x00009888, .val = 0x03D04E9C },
         { .reg = 0x00009888, .val = 0x05D00717 },
         { .reg = 0x00009888, .val = 0x07D000E6 },
         { .reg = 0x00009888, .val = 0x09D00840 },
         { .reg = 0x00009888, .val = 0x01C15555 },
         { .reg = 0x00009888, .val = 0x03C15415 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3A82A },
         { .reg = 0x00009888, .val = 0x01C4E7FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65415 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x03C75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307A82A },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009888, .val = 0x0102E7FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext651__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext651__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext651__avg_gpu_core_frequency__max,acmgt3__ext651__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3199, 24, percentage_max_float,acmgt3__ext651__xve_stall_aluwr_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3200, 28, percentage_max_float,acmgt3__ext651__xve_stall_barrier_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3201, 32, percentage_max_float,acmgt3__ext651__xve_stall_instfetch_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3202, 36, percentage_max_float,acmgt3__ext651__xve_stall_other_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3203, 40, percentage_max_float,acmgt3__ext651__xve_stall_sbid_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3204, 44, percentage_max_float,acmgt3__ext651__xve_stall_sendwr_xecore14_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3205, 48, percentage_max_float,acmgt3__ext651__xve_shared_function_access_hold_xecore14_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext652_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext652";
   query->symbol_name = "Ext652";
   query->guid = "bd0f78e6-755f-495f-a530-2181a36e202b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BF00236 },
         { .reg = 0x00009888, .val = 0x0DF0016A },
         { .reg = 0x00009888, .val = 0x01F042B2 },
         { .reg = 0x00009888, .val = 0x03F04E9C },
         { .reg = 0x00009888, .val = 0x05F00717 },
         { .reg = 0x00009888, .val = 0x07F000E6 },
         { .reg = 0x00009888, .val = 0x09F00840 },
         { .reg = 0x00009888, .val = 0x01E15555 },
         { .reg = 0x00009888, .val = 0x03E15415 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3A82A },
         { .reg = 0x00009888, .val = 0x01E4E7FF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65415 },
         { .reg = 0x00009888, .val = 0x01E75555 },
         { .reg = 0x00009888, .val = 0x03E75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075415 },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032402 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext652__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext652__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext652__avg_gpu_core_frequency__max,acmgt3__ext652__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3206, 24, percentage_max_float,acmgt3__ext652__xve_stall_aluwr_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3207, 28, percentage_max_float,acmgt3__ext652__xve_stall_barrier_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3208, 32, percentage_max_float,acmgt3__ext652__xve_stall_instfetch_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3209, 36, percentage_max_float,acmgt3__ext652__xve_stall_other_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3210, 40, percentage_max_float,acmgt3__ext652__xve_stall_sbid_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3211, 44, percentage_max_float,acmgt3__ext652__xve_stall_sendwr_xecore15_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3212, 48, percentage_max_float,acmgt3__ext652__xve_shared_function_access_hold_xecore15_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext653_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext653";
   query->symbol_name = "Ext653";
   query->guid = "ee687e64-5d49-4f00-8487-7f29ce84112b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0A900236 },
         { .reg = 0x00009888, .val = 0x0C90016A },
         { .reg = 0x00009888, .val = 0x009042B2 },
         { .reg = 0x00009888, .val = 0x02904E9C },
         { .reg = 0x00009888, .val = 0x04900717 },
         { .reg = 0x00009888, .val = 0x069000E6 },
         { .reg = 0x00009888, .val = 0x08900840 },
         { .reg = 0x00009888, .val = 0x00815555 },
         { .reg = 0x00009888, .val = 0x02815415 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283A82A },
         { .reg = 0x00009888, .val = 0x0084E7FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865415 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x02875415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext653__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext653__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext653__avg_gpu_core_frequency__max,acmgt3__ext653__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4965, 24, percentage_max_float,acmgt3__ext653__xve_stall_aluwr_xecore16_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4966, 28, percentage_max_float,acmgt3__ext653__xve_stall_barrier_xecore16_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4967, 32, percentage_max_float,acmgt3__ext653__xve_stall_instfetch_xecore16_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4968, 36, percentage_max_float,acmgt3__ext653__xve_stall_other_xecore16_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4969, 40, percentage_max_float,acmgt3__ext653__xve_stall_sbid_xecore16_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4970, 44, percentage_max_float,acmgt3__ext653__xve_stall_sendwr_xecore16_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 4971, 48, percentage_max_float,acmgt3__ext653__xve_shared_function_access_hold_xecore16_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext654_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext654";
   query->symbol_name = "Ext654";
   query->guid = "7fa4182a-6679-43a8-863d-20bf117c2f6e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0AB00236 },
         { .reg = 0x00009888, .val = 0x0CB0016A },
         { .reg = 0x00009888, .val = 0x00B042B2 },
         { .reg = 0x00009888, .val = 0x02B04E9C },
         { .reg = 0x00009888, .val = 0x04B00717 },
         { .reg = 0x00009888, .val = 0x06B000E6 },
         { .reg = 0x00009888, .val = 0x08B00840 },
         { .reg = 0x00009888, .val = 0x00A15555 },
         { .reg = 0x00009888, .val = 0x02A15415 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3A82A },
         { .reg = 0x00009888, .val = 0x00A4E7FF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65415 },
         { .reg = 0x00009888, .val = 0x00A75555 },
         { .reg = 0x00009888, .val = 0x02A75415 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext654__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext654__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext654__avg_gpu_core_frequency__max,acmgt3__ext654__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4972, 24, percentage_max_float,acmgt3__ext654__xve_stall_aluwr_xecore17_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4973, 28, percentage_max_float,acmgt3__ext654__xve_stall_barrier_xecore17_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4974, 32, percentage_max_float,acmgt3__ext654__xve_stall_instfetch_xecore17_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4975, 36, percentage_max_float,acmgt3__ext654__xve_stall_other_xecore17_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4976, 40, percentage_max_float,acmgt3__ext654__xve_stall_sbid_xecore17_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4977, 44, percentage_max_float,acmgt3__ext654__xve_stall_sendwr_xecore17_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 4978, 48, percentage_max_float,acmgt3__ext654__xve_shared_function_access_hold_xecore17_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext655_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext655";
   query->symbol_name = "Ext655";
   query->guid = "4776e4a6-e322-4a93-8492-f9e5c7ae25a9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0AD00236 },
         { .reg = 0x00009888, .val = 0x0CD0016A },
         { .reg = 0x00009888, .val = 0x00D042B2 },
         { .reg = 0x00009888, .val = 0x02D04E9C },
         { .reg = 0x00009888, .val = 0x04D00717 },
         { .reg = 0x00009888, .val = 0x06D000E6 },
         { .reg = 0x00009888, .val = 0x08D00840 },
         { .reg = 0x00009888, .val = 0x00C15555 },
         { .reg = 0x00009888, .val = 0x02C15415 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3A82A },
         { .reg = 0x00009888, .val = 0x00C4E7FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65415 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x02C75415 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207A82A },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009888, .val = 0x0002E7FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext655__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext655__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext655__avg_gpu_core_frequency__max,acmgt3__ext655__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4979, 24, percentage_max_float,acmgt3__ext655__xve_stall_aluwr_xecore18_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4980, 28, percentage_max_float,acmgt3__ext655__xve_stall_barrier_xecore18_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4981, 32, percentage_max_float,acmgt3__ext655__xve_stall_instfetch_xecore18_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4982, 36, percentage_max_float,acmgt3__ext655__xve_stall_other_xecore18_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4983, 40, percentage_max_float,acmgt3__ext655__xve_stall_sbid_xecore18_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4984, 44, percentage_max_float,acmgt3__ext655__xve_stall_sendwr_xecore18_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 4985, 48, percentage_max_float,acmgt3__ext655__xve_shared_function_access_hold_xecore18_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext656_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext656";
   query->symbol_name = "Ext656";
   query->guid = "7e54fcd8-7d05-4a6e-a564-77da9ee3d948";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0AF00236 },
         { .reg = 0x00009888, .val = 0x0CF0016A },
         { .reg = 0x00009888, .val = 0x00F042B2 },
         { .reg = 0x00009888, .val = 0x02F04E9C },
         { .reg = 0x00009888, .val = 0x04F00717 },
         { .reg = 0x00009888, .val = 0x06F000E6 },
         { .reg = 0x00009888, .val = 0x08F00840 },
         { .reg = 0x00009888, .val = 0x00E15555 },
         { .reg = 0x00009888, .val = 0x02E15415 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3A82A },
         { .reg = 0x00009888, .val = 0x00E4E7FF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65415 },
         { .reg = 0x00009888, .val = 0x00E75555 },
         { .reg = 0x00009888, .val = 0x02E75415 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075415 },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext656__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext656__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext656__avg_gpu_core_frequency__max,acmgt3__ext656__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4986, 24, percentage_max_float,acmgt3__ext656__xve_stall_aluwr_xecore19_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4987, 28, percentage_max_float,acmgt3__ext656__xve_stall_barrier_xecore19_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4988, 32, percentage_max_float,acmgt3__ext656__xve_stall_instfetch_xecore19_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4989, 36, percentage_max_float,acmgt3__ext656__xve_stall_other_xecore19_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4990, 40, percentage_max_float,acmgt3__ext656__xve_stall_sbid_xecore19_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4991, 44, percentage_max_float,acmgt3__ext656__xve_stall_sendwr_xecore19_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 4992, 48, percentage_max_float,acmgt3__ext656__xve_shared_function_access_hold_xecore19_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext657_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext657";
   query->symbol_name = "Ext657";
   query->guid = "616a2406-05c9-412d-a3aa-a524acd66aa0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0B900236 },
         { .reg = 0x00009888, .val = 0x0D90016A },
         { .reg = 0x00009888, .val = 0x019042B2 },
         { .reg = 0x00009888, .val = 0x03904E9C },
         { .reg = 0x00009888, .val = 0x05900717 },
         { .reg = 0x00009888, .val = 0x079000E6 },
         { .reg = 0x00009888, .val = 0x09900840 },
         { .reg = 0x00009888, .val = 0x01815555 },
         { .reg = 0x00009888, .val = 0x03815415 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383A82A },
         { .reg = 0x00009888, .val = 0x0184E7FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865415 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x03875415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308A82A },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext657__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext657__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext657__avg_gpu_core_frequency__max,acmgt3__ext657__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4993, 24, percentage_max_float,acmgt3__ext657__xve_stall_aluwr_xecore20_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4994, 28, percentage_max_float,acmgt3__ext657__xve_stall_barrier_xecore20_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4995, 32, percentage_max_float,acmgt3__ext657__xve_stall_instfetch_xecore20_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4996, 36, percentage_max_float,acmgt3__ext657__xve_stall_other_xecore20_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4997, 40, percentage_max_float,acmgt3__ext657__xve_stall_sbid_xecore20_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4998, 44, percentage_max_float,acmgt3__ext657__xve_stall_sendwr_xecore20_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 4999, 48, percentage_max_float,acmgt3__ext657__xve_shared_function_access_hold_xecore20_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext658_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext658";
   query->symbol_name = "Ext658";
   query->guid = "0902fe2b-216e-4634-ae60-349382ded3ce";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0BB00236 },
         { .reg = 0x00009888, .val = 0x0DB0016A },
         { .reg = 0x00009888, .val = 0x01B042B2 },
         { .reg = 0x00009888, .val = 0x03B04E9C },
         { .reg = 0x00009888, .val = 0x05B00717 },
         { .reg = 0x00009888, .val = 0x07B000E6 },
         { .reg = 0x00009888, .val = 0x09B00840 },
         { .reg = 0x00009888, .val = 0x01A15555 },
         { .reg = 0x00009888, .val = 0x03A15415 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3A82A },
         { .reg = 0x00009888, .val = 0x01A4E7FF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65415 },
         { .reg = 0x00009888, .val = 0x01A75555 },
         { .reg = 0x00009888, .val = 0x03A75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FC3F },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009888, .val = 0x0101E7FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext658__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext658__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext658__avg_gpu_core_frequency__max,acmgt3__ext658__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5000, 24, percentage_max_float,acmgt3__ext658__xve_stall_aluwr_xecore21_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5001, 28, percentage_max_float,acmgt3__ext658__xve_stall_barrier_xecore21_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5002, 32, percentage_max_float,acmgt3__ext658__xve_stall_instfetch_xecore21_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5003, 36, percentage_max_float,acmgt3__ext658__xve_stall_other_xecore21_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5004, 40, percentage_max_float,acmgt3__ext658__xve_stall_sbid_xecore21_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5005, 44, percentage_max_float,acmgt3__ext658__xve_stall_sendwr_xecore21_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5006, 48, percentage_max_float,acmgt3__ext658__xve_shared_function_access_hold_xecore21_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext659_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext659";
   query->symbol_name = "Ext659";
   query->guid = "3ed655a3-105d-438b-912a-438fb8953965";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0BD00236 },
         { .reg = 0x00009888, .val = 0x0DD0016A },
         { .reg = 0x00009888, .val = 0x01D042B2 },
         { .reg = 0x00009888, .val = 0x03D04E9C },
         { .reg = 0x00009888, .val = 0x05D00717 },
         { .reg = 0x00009888, .val = 0x07D000E6 },
         { .reg = 0x00009888, .val = 0x09D00840 },
         { .reg = 0x00009888, .val = 0x01C15555 },
         { .reg = 0x00009888, .val = 0x03C15415 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3A82A },
         { .reg = 0x00009888, .val = 0x01C4E7FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65415 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x03C75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307A82A },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009888, .val = 0x0102E7FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext659__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext659__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext659__avg_gpu_core_frequency__max,acmgt3__ext659__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5007, 24, percentage_max_float,acmgt3__ext659__xve_stall_aluwr_xecore22_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5008, 28, percentage_max_float,acmgt3__ext659__xve_stall_barrier_xecore22_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5009, 32, percentage_max_float,acmgt3__ext659__xve_stall_instfetch_xecore22_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5010, 36, percentage_max_float,acmgt3__ext659__xve_stall_other_xecore22_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5011, 40, percentage_max_float,acmgt3__ext659__xve_stall_sbid_xecore22_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5012, 44, percentage_max_float,acmgt3__ext659__xve_stall_sendwr_xecore22_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5013, 48, percentage_max_float,acmgt3__ext659__xve_shared_function_access_hold_xecore22_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext660_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext660";
   query->symbol_name = "Ext660";
   query->guid = "609bdc17-fa1d-4dc1-b1f9-04d959d9502d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0BF00236 },
         { .reg = 0x00009888, .val = 0x0DF0016A },
         { .reg = 0x00009888, .val = 0x01F042B2 },
         { .reg = 0x00009888, .val = 0x03F04E9C },
         { .reg = 0x00009888, .val = 0x05F00717 },
         { .reg = 0x00009888, .val = 0x07F000E6 },
         { .reg = 0x00009888, .val = 0x09F00840 },
         { .reg = 0x00009888, .val = 0x01E15555 },
         { .reg = 0x00009888, .val = 0x03E15415 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3A82A },
         { .reg = 0x00009888, .val = 0x01E4E7FF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65415 },
         { .reg = 0x00009888, .val = 0x01E75555 },
         { .reg = 0x00009888, .val = 0x03E75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075415 },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext660__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext660__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext660__avg_gpu_core_frequency__max,acmgt3__ext660__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5014, 24, percentage_max_float,acmgt3__ext660__xve_stall_aluwr_xecore23_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5015, 28, percentage_max_float,acmgt3__ext660__xve_stall_barrier_xecore23_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5016, 32, percentage_max_float,acmgt3__ext660__xve_stall_instfetch_xecore23_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5017, 36, percentage_max_float,acmgt3__ext660__xve_stall_other_xecore23_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5018, 40, percentage_max_float,acmgt3__ext660__xve_stall_sbid_xecore23_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5019, 44, percentage_max_float,acmgt3__ext660__xve_stall_sendwr_xecore23_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5020, 48, percentage_max_float,acmgt3__ext660__xve_shared_function_access_hold_xecore23_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext661_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext661";
   query->symbol_name = "Ext661";
   query->guid = "8670adf5-1083-4e44-9b34-1ad5f7187e4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0A900236 },
         { .reg = 0x00009888, .val = 0x0C90016A },
         { .reg = 0x00009888, .val = 0x009042B2 },
         { .reg = 0x00009888, .val = 0x02904E9C },
         { .reg = 0x00009888, .val = 0x04900717 },
         { .reg = 0x00009888, .val = 0x069000E6 },
         { .reg = 0x00009888, .val = 0x08900840 },
         { .reg = 0x00009888, .val = 0x00815555 },
         { .reg = 0x00009888, .val = 0x02815415 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283A82A },
         { .reg = 0x00009888, .val = 0x0084E7FF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865415 },
         { .reg = 0x00009888, .val = 0x00875555 },
         { .reg = 0x00009888, .val = 0x02875415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext661__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext661__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext661__avg_gpu_core_frequency__max,acmgt3__ext661__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5021, 24, percentage_max_float,acmgt3__ext661__xve_stall_aluwr_xecore24_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5022, 28, percentage_max_float,acmgt3__ext661__xve_stall_barrier_xecore24_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5023, 32, percentage_max_float,acmgt3__ext661__xve_stall_instfetch_xecore24_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5024, 36, percentage_max_float,acmgt3__ext661__xve_stall_other_xecore24_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5025, 40, percentage_max_float,acmgt3__ext661__xve_stall_sbid_xecore24_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5026, 44, percentage_max_float,acmgt3__ext661__xve_stall_sendwr_xecore24_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5027, 48, percentage_max_float,acmgt3__ext661__xve_shared_function_access_hold_xecore24_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext662_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext662";
   query->symbol_name = "Ext662";
   query->guid = "6295fd5c-e29f-4522-a7bf-83be283e0bbb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0AB00236 },
         { .reg = 0x00009888, .val = 0x0CB0016A },
         { .reg = 0x00009888, .val = 0x00B042B2 },
         { .reg = 0x00009888, .val = 0x02B04E9C },
         { .reg = 0x00009888, .val = 0x04B00717 },
         { .reg = 0x00009888, .val = 0x06B000E6 },
         { .reg = 0x00009888, .val = 0x08B00840 },
         { .reg = 0x00009888, .val = 0x00A15555 },
         { .reg = 0x00009888, .val = 0x02A15415 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3A82A },
         { .reg = 0x00009888, .val = 0x00A4E7FF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65415 },
         { .reg = 0x00009888, .val = 0x00A75555 },
         { .reg = 0x00009888, .val = 0x02A75415 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext662__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext662__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext662__avg_gpu_core_frequency__max,acmgt3__ext662__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5028, 24, percentage_max_float,acmgt3__ext662__xve_stall_aluwr_xecore25_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5029, 28, percentage_max_float,acmgt3__ext662__xve_stall_barrier_xecore25_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5030, 32, percentage_max_float,acmgt3__ext662__xve_stall_instfetch_xecore25_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5031, 36, percentage_max_float,acmgt3__ext662__xve_stall_other_xecore25_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5032, 40, percentage_max_float,acmgt3__ext662__xve_stall_sbid_xecore25_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5033, 44, percentage_max_float,acmgt3__ext662__xve_stall_sendwr_xecore25_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5034, 48, percentage_max_float,acmgt3__ext662__xve_shared_function_access_hold_xecore25_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext663_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext663";
   query->symbol_name = "Ext663";
   query->guid = "a50eb103-f419-4fdc-bdc5-cabcf1f5f799";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0AD00236 },
         { .reg = 0x00009888, .val = 0x0CD0016A },
         { .reg = 0x00009888, .val = 0x00D042B2 },
         { .reg = 0x00009888, .val = 0x02D04E9C },
         { .reg = 0x00009888, .val = 0x04D00717 },
         { .reg = 0x00009888, .val = 0x06D000E6 },
         { .reg = 0x00009888, .val = 0x08D00840 },
         { .reg = 0x00009888, .val = 0x00C15555 },
         { .reg = 0x00009888, .val = 0x02C15415 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3A82A },
         { .reg = 0x00009888, .val = 0x00C4E7FF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65415 },
         { .reg = 0x00009888, .val = 0x00C75555 },
         { .reg = 0x00009888, .val = 0x02C75415 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207A82A },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009888, .val = 0x0002E7FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext663__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext663__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext663__avg_gpu_core_frequency__max,acmgt3__ext663__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5035, 24, percentage_max_float,acmgt3__ext663__xve_stall_aluwr_xecore26_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5036, 28, percentage_max_float,acmgt3__ext663__xve_stall_barrier_xecore26_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5037, 32, percentage_max_float,acmgt3__ext663__xve_stall_instfetch_xecore26_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5038, 36, percentage_max_float,acmgt3__ext663__xve_stall_other_xecore26_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5039, 40, percentage_max_float,acmgt3__ext663__xve_stall_sbid_xecore26_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5040, 44, percentage_max_float,acmgt3__ext663__xve_stall_sendwr_xecore26_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5041, 48, percentage_max_float,acmgt3__ext663__xve_shared_function_access_hold_xecore26_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext664_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext664";
   query->symbol_name = "Ext664";
   query->guid = "8a026261-ef0f-4331-8a07-161022e4d2a4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0AF00236 },
         { .reg = 0x00009888, .val = 0x0CF0016A },
         { .reg = 0x00009888, .val = 0x00F042B2 },
         { .reg = 0x00009888, .val = 0x02F04E9C },
         { .reg = 0x00009888, .val = 0x04F00717 },
         { .reg = 0x00009888, .val = 0x06F000E6 },
         { .reg = 0x00009888, .val = 0x08F00840 },
         { .reg = 0x00009888, .val = 0x00E15555 },
         { .reg = 0x00009888, .val = 0x02E15415 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3A82A },
         { .reg = 0x00009888, .val = 0x00E4E7FF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65415 },
         { .reg = 0x00009888, .val = 0x00E75555 },
         { .reg = 0x00009888, .val = 0x02E75415 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075415 },
         { .reg = 0x00009888, .val = 0x0009E7FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext664__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext664__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext664__avg_gpu_core_frequency__max,acmgt3__ext664__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5042, 24, percentage_max_float,acmgt3__ext664__xve_stall_aluwr_xecore27_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5043, 28, percentage_max_float,acmgt3__ext664__xve_stall_barrier_xecore27_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5044, 32, percentage_max_float,acmgt3__ext664__xve_stall_instfetch_xecore27_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5045, 36, percentage_max_float,acmgt3__ext664__xve_stall_other_xecore27_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5046, 40, percentage_max_float,acmgt3__ext664__xve_stall_sbid_xecore27_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5047, 44, percentage_max_float,acmgt3__ext664__xve_stall_sendwr_xecore27_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5048, 48, percentage_max_float,acmgt3__ext664__xve_shared_function_access_hold_xecore27_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext665_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext665";
   query->symbol_name = "Ext665";
   query->guid = "73c5b3d6-f3f9-45d5-8c88-3c3bc7cb2a7b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0B900236 },
         { .reg = 0x00009888, .val = 0x0D90016A },
         { .reg = 0x00009888, .val = 0x019042B2 },
         { .reg = 0x00009888, .val = 0x03904E9C },
         { .reg = 0x00009888, .val = 0x05900717 },
         { .reg = 0x00009888, .val = 0x079000E6 },
         { .reg = 0x00009888, .val = 0x09900840 },
         { .reg = 0x00009888, .val = 0x01815555 },
         { .reg = 0x00009888, .val = 0x03815415 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383A82A },
         { .reg = 0x00009888, .val = 0x0184E7FF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865415 },
         { .reg = 0x00009888, .val = 0x01875555 },
         { .reg = 0x00009888, .val = 0x03875415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308A82A },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext665__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext665__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext665__avg_gpu_core_frequency__max,acmgt3__ext665__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5049, 24, percentage_max_float,acmgt3__ext665__xve_stall_aluwr_xecore28_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5050, 28, percentage_max_float,acmgt3__ext665__xve_stall_barrier_xecore28_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5051, 32, percentage_max_float,acmgt3__ext665__xve_stall_instfetch_xecore28_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5052, 36, percentage_max_float,acmgt3__ext665__xve_stall_other_xecore28_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5053, 40, percentage_max_float,acmgt3__ext665__xve_stall_sbid_xecore28_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5054, 44, percentage_max_float,acmgt3__ext665__xve_stall_sendwr_xecore28_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5055, 48, percentage_max_float,acmgt3__ext665__xve_shared_function_access_hold_xecore28_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext666_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext666";
   query->symbol_name = "Ext666";
   query->guid = "28f09392-e361-444e-984a-35bc2cd7319e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0BB00236 },
         { .reg = 0x00009888, .val = 0x0DB0016A },
         { .reg = 0x00009888, .val = 0x01B042B2 },
         { .reg = 0x00009888, .val = 0x03B04E9C },
         { .reg = 0x00009888, .val = 0x05B00717 },
         { .reg = 0x00009888, .val = 0x07B000E6 },
         { .reg = 0x00009888, .val = 0x09B00840 },
         { .reg = 0x00009888, .val = 0x01A15555 },
         { .reg = 0x00009888, .val = 0x03A15415 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3A82A },
         { .reg = 0x00009888, .val = 0x01A4E7FF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65415 },
         { .reg = 0x00009888, .val = 0x01A75555 },
         { .reg = 0x00009888, .val = 0x03A75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FC3F },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5415 },
         { .reg = 0x00009888, .val = 0x0101E7FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext666__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext666__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext666__avg_gpu_core_frequency__max,acmgt3__ext666__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5056, 24, percentage_max_float,acmgt3__ext666__xve_stall_aluwr_xecore29_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5057, 28, percentage_max_float,acmgt3__ext666__xve_stall_barrier_xecore29_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5058, 32, percentage_max_float,acmgt3__ext666__xve_stall_instfetch_xecore29_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5059, 36, percentage_max_float,acmgt3__ext666__xve_stall_other_xecore29_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5060, 40, percentage_max_float,acmgt3__ext666__xve_stall_sbid_xecore29_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5061, 44, percentage_max_float,acmgt3__ext666__xve_stall_sendwr_xecore29_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5062, 48, percentage_max_float,acmgt3__ext666__xve_shared_function_access_hold_xecore29_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext667_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext667";
   query->symbol_name = "Ext667";
   query->guid = "b5bd5646-7215-4cfb-a393-012e42f86e6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0BD00236 },
         { .reg = 0x00009888, .val = 0x0DD0016A },
         { .reg = 0x00009888, .val = 0x01D042B2 },
         { .reg = 0x00009888, .val = 0x03D04E9C },
         { .reg = 0x00009888, .val = 0x05D00717 },
         { .reg = 0x00009888, .val = 0x07D000E6 },
         { .reg = 0x00009888, .val = 0x09D00840 },
         { .reg = 0x00009888, .val = 0x01C15555 },
         { .reg = 0x00009888, .val = 0x03C15415 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3A82A },
         { .reg = 0x00009888, .val = 0x01C4E7FF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65415 },
         { .reg = 0x00009888, .val = 0x01C75555 },
         { .reg = 0x00009888, .val = 0x03C75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307A82A },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009888, .val = 0x0102E7FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5415 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext667__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext667__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext667__avg_gpu_core_frequency__max,acmgt3__ext667__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5063, 24, percentage_max_float,acmgt3__ext667__xve_stall_aluwr_xecore30_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5064, 28, percentage_max_float,acmgt3__ext667__xve_stall_barrier_xecore30_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5065, 32, percentage_max_float,acmgt3__ext667__xve_stall_instfetch_xecore30_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5066, 36, percentage_max_float,acmgt3__ext667__xve_stall_other_xecore30_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5067, 40, percentage_max_float,acmgt3__ext667__xve_stall_sbid_xecore30_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5068, 44, percentage_max_float,acmgt3__ext667__xve_stall_sendwr_xecore30_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5069, 48, percentage_max_float,acmgt3__ext667__xve_shared_function_access_hold_xecore30_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext668_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext668";
   query->symbol_name = "Ext668";
   query->guid = "e3b9472f-95b7-49b7-9f95-96d9cfcea28f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0BF00236 },
         { .reg = 0x00009888, .val = 0x0DF0016A },
         { .reg = 0x00009888, .val = 0x01F042B2 },
         { .reg = 0x00009888, .val = 0x03F04E9C },
         { .reg = 0x00009888, .val = 0x05F00717 },
         { .reg = 0x00009888, .val = 0x07F000E6 },
         { .reg = 0x00009888, .val = 0x09F00840 },
         { .reg = 0x00009888, .val = 0x01E15555 },
         { .reg = 0x00009888, .val = 0x03E15415 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3A82A },
         { .reg = 0x00009888, .val = 0x01E4E7FF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65415 },
         { .reg = 0x00009888, .val = 0x01E75555 },
         { .reg = 0x00009888, .val = 0x03E75415 },
         { .reg = 0x00009888, .val = 0x0003E7FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FC3F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5415 },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BA82A },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075415 },
         { .reg = 0x00009888, .val = 0x0109E7FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AA82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202A82A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031201 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001E7FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025415 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045415 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055415 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208A82A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000042 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000F80 },
         { .reg = 0x0000D954, .val = 0x0000FE0F },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000F9FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext668__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext668__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext668__avg_gpu_core_frequency__max,acmgt3__ext668__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5070, 24, percentage_max_float,acmgt3__ext668__xve_stall_aluwr_xecore31_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5071, 28, percentage_max_float,acmgt3__ext668__xve_stall_barrier_xecore31_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5072, 32, percentage_max_float,acmgt3__ext668__xve_stall_instfetch_xecore31_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5073, 36, percentage_max_float,acmgt3__ext668__xve_stall_other_xecore31_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5074, 40, percentage_max_float,acmgt3__ext668__xve_stall_sbid_xecore31_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5075, 44, percentage_max_float,acmgt3__ext668__xve_stall_sendwr_xecore31_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5076, 48, percentage_max_float,acmgt3__ext668__xve_shared_function_access_hold_xecore31_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext669_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext669";
   query->symbol_name = "Ext669";
   query->guid = "41aa8222-8353-458f-809f-88b87bb3205a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0A906F40 },
         { .reg = 0x00009888, .val = 0x0C900006 },
         { .reg = 0x00009888, .val = 0x0AB06F40 },
         { .reg = 0x00009888, .val = 0x0CB00006 },
         { .reg = 0x00009888, .val = 0x0AD06F40 },
         { .reg = 0x00009888, .val = 0x0CD00006 },
         { .reg = 0x00009888, .val = 0x00904EB4 },
         { .reg = 0x00009888, .val = 0x02900166 },
         { .reg = 0x00009888, .val = 0x00810155 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x02B05000 },
         { .reg = 0x00009888, .val = 0x04B01A75 },
         { .reg = 0x00009888, .val = 0x06B0000B },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A15400 },
         { .reg = 0x00009888, .val = 0x02A10005 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x06D05680 },
         { .reg = 0x00009888, .val = 0x08D02CD3 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x02C11550 },
         { .reg = 0x00009888, .val = 0x02C32AA0 },
         { .reg = 0x00009888, .val = 0x00C47C00 },
         { .reg = 0x00009888, .val = 0x02C61550 },
         { .reg = 0x00009888, .val = 0x02C71550 },
         { .reg = 0x00009888, .val = 0x02072AA0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x00097C00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A2AA5 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020B0005 },
         { .reg = 0x00009888, .val = 0x00027C00 },
         { .reg = 0x00009888, .val = 0x020C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext669__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext669__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext669__avg_gpu_core_frequency__max,acmgt3__ext669__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1640, 24, NULL,acmgt3__ext669__xve_inst_issued_all_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1641, 32, NULL,acmgt3__ext669__xve_inst_issued_all_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1642, 40, NULL,acmgt3__ext669__xve_inst_issued_all_xecore2_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext670_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext670";
   query->symbol_name = "Ext670";
   query->guid = "811a2fd2-eabe-421a-822c-9a3187bae218";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0AF06F40 },
         { .reg = 0x00009888, .val = 0x0CF00006 },
         { .reg = 0x00009888, .val = 0x0B906F40 },
         { .reg = 0x00009888, .val = 0x0D900006 },
         { .reg = 0x00009888, .val = 0x0BB06F40 },
         { .reg = 0x00009888, .val = 0x0DB00006 },
         { .reg = 0x00009888, .val = 0x00F04EB4 },
         { .reg = 0x00009888, .val = 0x02F00166 },
         { .reg = 0x00009888, .val = 0x00E10155 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x03905000 },
         { .reg = 0x00009888, .val = 0x05901A75 },
         { .reg = 0x00009888, .val = 0x0790000B },
         { .reg = 0x00009888, .val = 0x01900000 },
         { .reg = 0x00009888, .val = 0x01815400 },
         { .reg = 0x00009888, .val = 0x03810005 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07B05680 },
         { .reg = 0x00009888, .val = 0x09B02CD3 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x03A11550 },
         { .reg = 0x00009888, .val = 0x03A32AA0 },
         { .reg = 0x00009888, .val = 0x01A47C00 },
         { .reg = 0x00009888, .val = 0x03A61550 },
         { .reg = 0x00009888, .val = 0x03A71550 },
         { .reg = 0x00009888, .val = 0x00037FE0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x03083FFA },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A1555 },
         { .reg = 0x00009888, .val = 0x01017C00 },
         { .reg = 0x00009888, .val = 0x030B1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030004 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42031080 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext670__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext670__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext670__avg_gpu_core_frequency__max,acmgt3__ext670__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1643, 24, NULL,acmgt3__ext670__xve_inst_issued_all_xecore3_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1644, 32, NULL,acmgt3__ext670__xve_inst_issued_all_xecore4_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1645, 40, NULL,acmgt3__ext670__xve_inst_issued_all_xecore5_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext671_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext671";
   query->symbol_name = "Ext671";
   query->guid = "22d6be5d-b649-4df4-87d3-e9e00f221d5a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0BD06F40 },
         { .reg = 0x00009888, .val = 0x0DD00006 },
         { .reg = 0x00009888, .val = 0x0BF06F40 },
         { .reg = 0x00009888, .val = 0x0DF00006 },
         { .reg = 0x00009888, .val = 0x01D04EB4 },
         { .reg = 0x00009888, .val = 0x03D00166 },
         { .reg = 0x00009888, .val = 0x01C10155 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x03F05000 },
         { .reg = 0x00009888, .val = 0x05F01A75 },
         { .reg = 0x00009888, .val = 0x07F0000B },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x01E15400 },
         { .reg = 0x00009888, .val = 0x03E10005 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x010756AA },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0A906F40 },
         { .reg = 0x00009888, .val = 0x0C900006 },
         { .reg = 0x00009888, .val = 0x06905680 },
         { .reg = 0x00009888, .val = 0x08902CD3 },
         { .reg = 0x00009888, .val = 0x00900000 },
         { .reg = 0x00009888, .val = 0x02811550 },
         { .reg = 0x00009888, .val = 0x02832AA0 },
         { .reg = 0x00009888, .val = 0x00847C00 },
         { .reg = 0x00009888, .val = 0x02861550 },
         { .reg = 0x00009888, .val = 0x02871550 },
         { .reg = 0x00009888, .val = 0x02082AA0 },
         { .reg = 0x00009888, .val = 0x020A1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02083FFA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017C00 },
         { .reg = 0x00009888, .val = 0x02021550 },
         { .reg = 0x00009888, .val = 0x02041550 },
         { .reg = 0x00009888, .val = 0x02051550 },
         { .reg = 0x00009888, .val = 0x02082AA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext671__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext671__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext671__avg_gpu_core_frequency__max,acmgt3__ext671__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1646, 24, NULL,acmgt3__ext671__xve_inst_issued_all_xecore6_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1647, 32, NULL,acmgt3__ext671__xve_inst_issued_all_xecore7_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3285, 40, NULL,acmgt3__ext671__xve_inst_issued_all_xecore8_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext672_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext672";
   query->symbol_name = "Ext672";
   query->guid = "0e76590d-a922-4979-9f18-e04bf3619109";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0AB06F40 },
         { .reg = 0x00009888, .val = 0x0CB00006 },
         { .reg = 0x00009888, .val = 0x0AD06F40 },
         { .reg = 0x00009888, .val = 0x0CD00006 },
         { .reg = 0x00009888, .val = 0x0AF06F40 },
         { .reg = 0x00009888, .val = 0x0CF00006 },
         { .reg = 0x00009888, .val = 0x00B04EB4 },
         { .reg = 0x00009888, .val = 0x02B00166 },
         { .reg = 0x00009888, .val = 0x00A10155 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x02D05000 },
         { .reg = 0x00009888, .val = 0x04D01A75 },
         { .reg = 0x00009888, .val = 0x06D0000B },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x00C15400 },
         { .reg = 0x00009888, .val = 0x02C10005 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x06F05680 },
         { .reg = 0x00009888, .val = 0x08F02CD3 },
         { .reg = 0x00009888, .val = 0x00F00000 },
         { .reg = 0x00009888, .val = 0x02E11550 },
         { .reg = 0x00009888, .val = 0x02E32AA0 },
         { .reg = 0x00009888, .val = 0x00E47C00 },
         { .reg = 0x00009888, .val = 0x02E61550 },
         { .reg = 0x00009888, .val = 0x02E71550 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207155A },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00097FE0 },
         { .reg = 0x00009888, .val = 0x000AA955 },
         { .reg = 0x00009888, .val = 0x020A2AAA },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B0155 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032943 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext672__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext672__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext672__avg_gpu_core_frequency__max,acmgt3__ext672__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3286, 24, NULL,acmgt3__ext672__xve_inst_issued_all_xecore9_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3287, 32, NULL,acmgt3__ext672__xve_inst_issued_all_xecore10_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3288, 40, NULL,acmgt3__ext672__xve_inst_issued_all_xecore11_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext673_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext673";
   query->symbol_name = "Ext673";
   query->guid = "1b1b6054-62b3-4811-b3af-7430310b36f7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0B906F40 },
         { .reg = 0x00009888, .val = 0x0D900006 },
         { .reg = 0x00009888, .val = 0x0BB06F40 },
         { .reg = 0x00009888, .val = 0x0DB00006 },
         { .reg = 0x00009888, .val = 0x0BD06F40 },
         { .reg = 0x00009888, .val = 0x0DD00006 },
         { .reg = 0x00009888, .val = 0x01904EB4 },
         { .reg = 0x00009888, .val = 0x03900166 },
         { .reg = 0x00009888, .val = 0x01810155 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x03B05000 },
         { .reg = 0x00009888, .val = 0x05B01A75 },
         { .reg = 0x00009888, .val = 0x07B0000B },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x01A15400 },
         { .reg = 0x00009888, .val = 0x03A10005 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x07D05680 },
         { .reg = 0x00009888, .val = 0x09D02CD3 },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x03C11550 },
         { .reg = 0x00009888, .val = 0x03C32AA0 },
         { .reg = 0x00009888, .val = 0x01C47C00 },
         { .reg = 0x00009888, .val = 0x03C61550 },
         { .reg = 0x00009888, .val = 0x03C71550 },
         { .reg = 0x00009888, .val = 0x00037FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x03072AA0 },
         { .reg = 0x00009888, .val = 0x0108FEAA },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x01097C00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A2AA5 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009888, .val = 0x01027C00 },
         { .reg = 0x00009888, .val = 0x030C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext673__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext673__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext673__avg_gpu_core_frequency__max,acmgt3__ext673__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3289, 24, NULL,acmgt3__ext673__xve_inst_issued_all_xecore12_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3290, 32, NULL,acmgt3__ext673__xve_inst_issued_all_xecore13_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3291, 40, NULL,acmgt3__ext673__xve_inst_issued_all_xecore14_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext674_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext674";
   query->symbol_name = "Ext674";
   query->guid = "8485658d-80cd-44e4-b275-e24c659732d4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0BF06F40 },
         { .reg = 0x00009888, .val = 0x0DF00006 },
         { .reg = 0x00009888, .val = 0x01F04EB4 },
         { .reg = 0x00009888, .val = 0x03F00166 },
         { .reg = 0x00009888, .val = 0x01E10155 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0A906F40 },
         { .reg = 0x00009888, .val = 0x0C900006 },
         { .reg = 0x00009888, .val = 0x0AB06F40 },
         { .reg = 0x00009888, .val = 0x0CB00006 },
         { .reg = 0x00009888, .val = 0x02905000 },
         { .reg = 0x00009888, .val = 0x04901A75 },
         { .reg = 0x00009888, .val = 0x0690000B },
         { .reg = 0x00009888, .val = 0x00900000 },
         { .reg = 0x00009888, .val = 0x00815400 },
         { .reg = 0x00009888, .val = 0x02810005 },
         { .reg = 0x00009888, .val = 0x0083A800 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x008403E0 },
         { .reg = 0x00009888, .val = 0x00865400 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00875400 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x06B05680 },
         { .reg = 0x00009888, .val = 0x08B02CD3 },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x02A11550 },
         { .reg = 0x00009888, .val = 0x02A32AA0 },
         { .reg = 0x00009888, .val = 0x00A47C00 },
         { .reg = 0x00009888, .val = 0x02A61550 },
         { .reg = 0x00009888, .val = 0x02A71550 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x02083FFA },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017C00 },
         { .reg = 0x00009888, .val = 0x020B1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603146A },
         { .reg = 0x00009888, .val = 0x480306A3 },
         { .reg = 0x00009888, .val = 0x4A03146A },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext674__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext674__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext674__avg_gpu_core_frequency__max,acmgt3__ext674__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3292, 24, NULL,acmgt3__ext674__xve_inst_issued_all_xecore15_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5077, 32, NULL,acmgt3__ext674__xve_inst_issued_all_xecore16_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5078, 40, NULL,acmgt3__ext674__xve_inst_issued_all_xecore17_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext675_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext675";
   query->symbol_name = "Ext675";
   query->guid = "90e30b6c-ee34-4fac-8b0c-28afe0397b18";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0AD06F40 },
         { .reg = 0x00009888, .val = 0x0CD00006 },
         { .reg = 0x00009888, .val = 0x0AF06F40 },
         { .reg = 0x00009888, .val = 0x0CF00006 },
         { .reg = 0x00009888, .val = 0x0B906F40 },
         { .reg = 0x00009888, .val = 0x0D900006 },
         { .reg = 0x00009888, .val = 0x00D04EB4 },
         { .reg = 0x00009888, .val = 0x02D00166 },
         { .reg = 0x00009888, .val = 0x00C10155 },
         { .reg = 0x00009888, .val = 0x00C302AA },
         { .reg = 0x00009888, .val = 0x00C4001F },
         { .reg = 0x00009888, .val = 0x00C60155 },
         { .reg = 0x00009888, .val = 0x00C70155 },
         { .reg = 0x00009888, .val = 0x02F05000 },
         { .reg = 0x00009888, .val = 0x04F01A75 },
         { .reg = 0x00009888, .val = 0x06F0000B },
         { .reg = 0x00009888, .val = 0x00F00000 },
         { .reg = 0x00009888, .val = 0x00E15400 },
         { .reg = 0x00009888, .val = 0x02E10005 },
         { .reg = 0x00009888, .val = 0x00E3A800 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E403E0 },
         { .reg = 0x00009888, .val = 0x00E65400 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x00E75400 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x07905680 },
         { .reg = 0x00009888, .val = 0x09902CD3 },
         { .reg = 0x00009888, .val = 0x01900000 },
         { .reg = 0x00009888, .val = 0x03811550 },
         { .reg = 0x00009888, .val = 0x03832AA0 },
         { .reg = 0x00009888, .val = 0x01847C00 },
         { .reg = 0x00009888, .val = 0x03861550 },
         { .reg = 0x00009888, .val = 0x03871550 },
         { .reg = 0x00009888, .val = 0x00037C00 },
         { .reg = 0x00009888, .val = 0x000756AA },
         { .reg = 0x00009888, .val = 0x02070005 },
         { .reg = 0x00009888, .val = 0x02083FF0 },
         { .reg = 0x00009888, .val = 0x000903FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A155A },
         { .reg = 0x00009888, .val = 0x00017C00 },
         { .reg = 0x00009888, .val = 0x020B2AA0 },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x000C0155 },
         { .reg = 0x00009888, .val = 0x03082AA0 },
         { .reg = 0x00009888, .val = 0x030A1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030006 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x420318C0 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CC6 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030A65 },
         { .reg = 0x00009888, .val = 0x48030653 },
         { .reg = 0x00009888, .val = 0x4A030A65 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext675__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext675__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext675__avg_gpu_core_frequency__max,acmgt3__ext675__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5079, 24, NULL,acmgt3__ext675__xve_inst_issued_all_xecore18_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5080, 32, NULL,acmgt3__ext675__xve_inst_issued_all_xecore19_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5081, 40, NULL,acmgt3__ext675__xve_inst_issued_all_xecore20_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext676_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext676";
   query->symbol_name = "Ext676";
   query->guid = "ac420c4f-90eb-42ec-9be9-75aaa09c99ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0BB06F40 },
         { .reg = 0x00009888, .val = 0x0DB00006 },
         { .reg = 0x00009888, .val = 0x0BD06F40 },
         { .reg = 0x00009888, .val = 0x0DD00006 },
         { .reg = 0x00009888, .val = 0x0BF06F40 },
         { .reg = 0x00009888, .val = 0x0DF00006 },
         { .reg = 0x00009888, .val = 0x01B04EB4 },
         { .reg = 0x00009888, .val = 0x03B00166 },
         { .reg = 0x00009888, .val = 0x01A10155 },
         { .reg = 0x00009888, .val = 0x01A302AA },
         { .reg = 0x00009888, .val = 0x01A4001F },
         { .reg = 0x00009888, .val = 0x01A60155 },
         { .reg = 0x00009888, .val = 0x01A70155 },
         { .reg = 0x00009888, .val = 0x03D05000 },
         { .reg = 0x00009888, .val = 0x05D01A75 },
         { .reg = 0x00009888, .val = 0x07D0000B },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x01C15400 },
         { .reg = 0x00009888, .val = 0x03C10005 },
         { .reg = 0x00009888, .val = 0x01C3A800 },
         { .reg = 0x00009888, .val = 0x03C3000A },
         { .reg = 0x00009888, .val = 0x01C403E0 },
         { .reg = 0x00009888, .val = 0x01C65400 },
         { .reg = 0x00009888, .val = 0x03C60005 },
         { .reg = 0x00009888, .val = 0x01C75400 },
         { .reg = 0x00009888, .val = 0x03C70005 },
         { .reg = 0x00009888, .val = 0x07F05680 },
         { .reg = 0x00009888, .val = 0x09F02CD3 },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x03E11550 },
         { .reg = 0x00009888, .val = 0x03E32AA0 },
         { .reg = 0x00009888, .val = 0x01E47C00 },
         { .reg = 0x00009888, .val = 0x03E61550 },
         { .reg = 0x00009888, .val = 0x03E71550 },
         { .reg = 0x00009888, .val = 0x00037FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0107A800 },
         { .reg = 0x00009888, .val = 0x0307155A },
         { .reg = 0x00009888, .val = 0x010803FF },
         { .reg = 0x00009888, .val = 0x01097FE0 },
         { .reg = 0x00009888, .val = 0x010AA955 },
         { .reg = 0x00009888, .val = 0x030A2AAA },
         { .reg = 0x00009888, .val = 0x0101001F },
         { .reg = 0x00009888, .val = 0x010B0155 },
         { .reg = 0x00009888, .val = 0x010203E0 },
         { .reg = 0x00009888, .val = 0x010C5400 },
         { .reg = 0x00009888, .val = 0x030C0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032943 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext676__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext676__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext676__avg_gpu_core_frequency__max,acmgt3__ext676__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5082, 24, NULL,acmgt3__ext676__xve_inst_issued_all_xecore21_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5083, 32, NULL,acmgt3__ext676__xve_inst_issued_all_xecore22_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5084, 40, NULL,acmgt3__ext676__xve_inst_issued_all_xecore23_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext677_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext677";
   query->symbol_name = "Ext677";
   query->guid = "cded2a1d-8dce-4b4d-91cf-b51859474310";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0A906F40 },
         { .reg = 0x00009888, .val = 0x0C900006 },
         { .reg = 0x00009888, .val = 0x0AB06F40 },
         { .reg = 0x00009888, .val = 0x0CB00006 },
         { .reg = 0x00009888, .val = 0x0AD06F40 },
         { .reg = 0x00009888, .val = 0x0CD00006 },
         { .reg = 0x00009888, .val = 0x00904EB4 },
         { .reg = 0x00009888, .val = 0x02900166 },
         { .reg = 0x00009888, .val = 0x00810155 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x02B05000 },
         { .reg = 0x00009888, .val = 0x04B01A75 },
         { .reg = 0x00009888, .val = 0x06B0000B },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A15400 },
         { .reg = 0x00009888, .val = 0x02A10005 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x06D05680 },
         { .reg = 0x00009888, .val = 0x08D02CD3 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x02C11550 },
         { .reg = 0x00009888, .val = 0x02C32AA0 },
         { .reg = 0x00009888, .val = 0x00C47C00 },
         { .reg = 0x00009888, .val = 0x02C61550 },
         { .reg = 0x00009888, .val = 0x02C71550 },
         { .reg = 0x00009888, .val = 0x02072AA0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x00097C00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A2AA5 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020B0005 },
         { .reg = 0x00009888, .val = 0x00027C00 },
         { .reg = 0x00009888, .val = 0x020C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext677__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext677__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext677__avg_gpu_core_frequency__max,acmgt3__ext677__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5085, 24, NULL,acmgt3__ext677__xve_inst_issued_all_xecore24_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5086, 32, NULL,acmgt3__ext677__xve_inst_issued_all_xecore25_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5087, 40, NULL,acmgt3__ext677__xve_inst_issued_all_xecore26_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext678_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext678";
   query->symbol_name = "Ext678";
   query->guid = "c1339b79-a656-4338-ab32-99638d7cea0a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0AF06F40 },
         { .reg = 0x00009888, .val = 0x0CF00006 },
         { .reg = 0x00009888, .val = 0x0B906F40 },
         { .reg = 0x00009888, .val = 0x0D900006 },
         { .reg = 0x00009888, .val = 0x0BB06F40 },
         { .reg = 0x00009888, .val = 0x0DB00006 },
         { .reg = 0x00009888, .val = 0x00F04EB4 },
         { .reg = 0x00009888, .val = 0x02F00166 },
         { .reg = 0x00009888, .val = 0x00E10155 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x03905000 },
         { .reg = 0x00009888, .val = 0x05901A75 },
         { .reg = 0x00009888, .val = 0x0790000B },
         { .reg = 0x00009888, .val = 0x01900000 },
         { .reg = 0x00009888, .val = 0x01815400 },
         { .reg = 0x00009888, .val = 0x03810005 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07B05680 },
         { .reg = 0x00009888, .val = 0x09B02CD3 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x03A11550 },
         { .reg = 0x00009888, .val = 0x03A32AA0 },
         { .reg = 0x00009888, .val = 0x01A47C00 },
         { .reg = 0x00009888, .val = 0x03A61550 },
         { .reg = 0x00009888, .val = 0x03A71550 },
         { .reg = 0x00009888, .val = 0x00037FE0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x03083FFA },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A1555 },
         { .reg = 0x00009888, .val = 0x01017C00 },
         { .reg = 0x00009888, .val = 0x030B1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030004 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42031080 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E002 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext678__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext678__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext678__avg_gpu_core_frequency__max,acmgt3__ext678__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5088, 24, NULL,acmgt3__ext678__xve_inst_issued_all_xecore27_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5089, 32, NULL,acmgt3__ext678__xve_inst_issued_all_xecore28_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5090, 40, NULL,acmgt3__ext678__xve_inst_issued_all_xecore29_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext679_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext679";
   query->symbol_name = "Ext679";
   query->guid = "26d16b76-0337-479c-aa3c-c47a7a10eb23";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0BD06F40 },
         { .reg = 0x00009888, .val = 0x0DD00006 },
         { .reg = 0x00009888, .val = 0x0BF06F40 },
         { .reg = 0x00009888, .val = 0x0DF00006 },
         { .reg = 0x00009888, .val = 0x01D04EB4 },
         { .reg = 0x00009888, .val = 0x03D00166 },
         { .reg = 0x00009888, .val = 0x01C10155 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x03F05000 },
         { .reg = 0x00009888, .val = 0x05F01A75 },
         { .reg = 0x00009888, .val = 0x07F0000B },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x01E15400 },
         { .reg = 0x00009888, .val = 0x03E10005 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x010756AA },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202000A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000FA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F02 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext679__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext679__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext679__avg_gpu_core_frequency__max,acmgt3__ext679__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5091, 24, NULL,acmgt3__ext679__xve_inst_issued_all_xecore30_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5092, 32, NULL,acmgt3__ext679__xve_inst_issued_all_xecore31_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext680_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext680";
   query->symbol_name = "Ext680";
   query->guid = "99d71df4-d88a-4169-a019-2b2758eea5c8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x180301E9 },
         { .reg = 0x00009888, .val = 0x180801E9 },
         { .reg = 0x00009888, .val = 0x06030E30 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x000400A0 },
         { .reg = 0x00009888, .val = 0x00050050 },
         { .reg = 0x00009888, .val = 0x04080E30 },
         { .reg = 0x00009888, .val = 0x000800A0 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x180301E9 },
         { .reg = 0x00009888, .val = 0x180801E9 },
         { .reg = 0x00009888, .val = 0x0A030E30 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x0004A000 },
         { .reg = 0x00009888, .val = 0x00055000 },
         { .reg = 0x00009888, .val = 0x08080E30 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x180301E9 },
         { .reg = 0x00009888, .val = 0x180801E9 },
         { .reg = 0x00009888, .val = 0x0E030E30 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x020400A0 },
         { .reg = 0x00009888, .val = 0x02050050 },
         { .reg = 0x00009888, .val = 0x0C080E30 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x020800A0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x180301E9 },
         { .reg = 0x00009888, .val = 0x180801E9 },
         { .reg = 0x00009888, .val = 0x12030E30 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x0204A000 },
         { .reg = 0x00009888, .val = 0x02055000 },
         { .reg = 0x00009888, .val = 0x10080E30 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFAA },
         { .reg = 0x00009888, .val = 0x0202AA55 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031292 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030400 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030401 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030200 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003014A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext680__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext680__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext680__avg_gpu_core_frequency__max,acmgt3__ext680__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1648, 24, NULL,acmgt3__ext680__render_cache_alloc_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 1649, 32, NULL,acmgt3__ext680__render_cache_alloc_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2301, 40, NULL,acmgt3__ext680__render_cache_alloc_l3_node2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (1 * 2))) {
         intel_perf_query_add_counter_uint64(query, 2302, 48, NULL,acmgt3__ext680__render_cache_alloc_l3_node3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5093, 56, NULL,acmgt3__ext680__render_cache_alloc_l3_node4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (2 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5094, 64, NULL,acmgt3__ext680__render_cache_alloc_l3_node5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5095, 72, NULL,acmgt3__ext680__render_cache_alloc_l3_node6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (3 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5096, 80, NULL,acmgt3__ext680__render_cache_alloc_l3_node7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext681_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext681";
   query->symbol_name = "Ext681";
   query->guid = "1f921826-65ba-4ab6-a1d7-48eba4eedd34";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001D },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x08810CF2 },
         { .reg = 0x00009888, .val = 0x0A810D74 },
         { .reg = 0x00009888, .val = 0x0C810039 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810C80 },
         { .reg = 0x00009888, .val = 0x0F810D33 },
         { .reg = 0x00009888, .val = 0x11810FB5 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x0308000A },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x12810C70 },
         { .reg = 0x00009888, .val = 0x14810CF2 },
         { .reg = 0x00009888, .val = 0x16810DB7 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AAA0 },
         { .reg = 0x00009888, .val = 0x0084FC00 },
         { .reg = 0x00009888, .val = 0x02865550 },
         { .reg = 0x00009888, .val = 0x02875550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032108 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032108 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext681__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext681__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext681__avg_gpu_core_frequency__max,acmgt3__ext681__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1279, 24, NULL,acmgt3__ext681__gpgpu_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1294, 32, NULL,acmgt3__ext681__async_gpgpu_threadgroup_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3039, 40, NULL,acmgt3__ext681__async_gpgpu_thread_exit_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext682_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext682";
   query->symbol_name = "Ext682";
   query->guid = "69e3df50-90cf-4346-a55d-1eed069efda7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001D },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x08A10CF2 },
         { .reg = 0x00009888, .val = 0x0AA10D74 },
         { .reg = 0x00009888, .val = 0x0CA10039 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10C80 },
         { .reg = 0x00009888, .val = 0x0FA10D33 },
         { .reg = 0x00009888, .val = 0x11A10FB5 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BA955 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108FC00 },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x12A10C70 },
         { .reg = 0x00009888, .val = 0x14A10CF2 },
         { .reg = 0x00009888, .val = 0x16A10DB7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAA0 },
         { .reg = 0x00009888, .val = 0x00A4FC00 },
         { .reg = 0x00009888, .val = 0x02A65550 },
         { .reg = 0x00009888, .val = 0x02A75550 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032108 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032108 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext682__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext682__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext682__avg_gpu_core_frequency__max,acmgt3__ext682__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1280, 24, NULL,acmgt3__ext682__gpgpu_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1297, 32, NULL,acmgt3__ext682__async_gpgpu_threadgroup_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3040, 40, NULL,acmgt3__ext682__async_gpgpu_thread_exit_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext683_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext683";
   query->symbol_name = "Ext683";
   query->guid = "469421c9-dc97-4550-b37f-7c173053b76c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001D },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x08C10CF2 },
         { .reg = 0x00009888, .val = 0x0AC10D74 },
         { .reg = 0x00009888, .val = 0x0CC10039 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C302AA },
         { .reg = 0x00009888, .val = 0x00C4001F },
         { .reg = 0x00009888, .val = 0x00C60155 },
         { .reg = 0x00009888, .val = 0x00C70155 },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10C80 },
         { .reg = 0x00009888, .val = 0x0FC10D33 },
         { .reg = 0x00009888, .val = 0x11C10FB5 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A800 },
         { .reg = 0x00009888, .val = 0x03C3000A },
         { .reg = 0x00009888, .val = 0x01C403E0 },
         { .reg = 0x00009888, .val = 0x01C65400 },
         { .reg = 0x00009888, .val = 0x03C60005 },
         { .reg = 0x00009888, .val = 0x01C75400 },
         { .reg = 0x00009888, .val = 0x03C70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x000702AA },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x000C0155 },
         { .reg = 0x00009888, .val = 0x0107A800 },
         { .reg = 0x00009888, .val = 0x0307000A },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x010203E0 },
         { .reg = 0x00009888, .val = 0x010C5400 },
         { .reg = 0x00009888, .val = 0x030C0005 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C70 },
         { .reg = 0x00009888, .val = 0x14C10CF2 },
         { .reg = 0x00009888, .val = 0x16C10DB7 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C3AAA0 },
         { .reg = 0x00009888, .val = 0x00C4FC00 },
         { .reg = 0x00009888, .val = 0x02C65550 },
         { .reg = 0x00009888, .val = 0x02C75550 },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032108 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032108 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext683__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext683__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext683__avg_gpu_core_frequency__max,acmgt3__ext683__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1261, 24, NULL,acmgt3__ext683__gpgpu_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1285, 32, NULL,acmgt3__ext683__async_gpgpu_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3041, 40, NULL,acmgt3__ext683__async_gpgpu_thread_exit_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext684_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext684";
   query->symbol_name = "Ext684";
   query->guid = "286faab2-da2e-4608-bd2f-39da15cb678c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001D },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x08E10CF2 },
         { .reg = 0x00009888, .val = 0x0AE10D74 },
         { .reg = 0x00009888, .val = 0x0CE10039 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10C80 },
         { .reg = 0x00009888, .val = 0x0FE10D33 },
         { .reg = 0x00009888, .val = 0x11E10FB5 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01075400 },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x12E10C70 },
         { .reg = 0x00009888, .val = 0x14E10CF2 },
         { .reg = 0x00009888, .val = 0x16E10DB7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAA0 },
         { .reg = 0x00009888, .val = 0x00E4FC00 },
         { .reg = 0x00009888, .val = 0x02E65550 },
         { .reg = 0x00009888, .val = 0x02E75550 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032108 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032108 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext684__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext684__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext684__avg_gpu_core_frequency__max,acmgt3__ext684__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1262, 24, NULL,acmgt3__ext684__gpgpu_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1286, 32, NULL,acmgt3__ext684__async_gpgpu_threadgroup_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3042, 40, NULL,acmgt3__ext684__async_gpgpu_thread_exit_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext685_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext685";
   query->symbol_name = "Ext685";
   query->guid = "49c8e6b6-5244-4b9f-85cf-2547d6d20a79";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x09810CF2 },
         { .reg = 0x00009888, .val = 0x0B810D74 },
         { .reg = 0x00009888, .val = 0x0D810039 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010802AA },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001D },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810C80 },
         { .reg = 0x00009888, .val = 0x0E810D33 },
         { .reg = 0x00009888, .val = 0x10810FB5 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A800 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x008403E0 },
         { .reg = 0x00009888, .val = 0x00865400 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00875400 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C70 },
         { .reg = 0x00009888, .val = 0x15810CF2 },
         { .reg = 0x00009888, .val = 0x17810DB7 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AAA0 },
         { .reg = 0x00009888, .val = 0x0184FC00 },
         { .reg = 0x00009888, .val = 0x03865550 },
         { .reg = 0x00009888, .val = 0x03875550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext685__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext685__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext685__avg_gpu_core_frequency__max,acmgt3__ext685__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1267, 24, NULL,acmgt3__ext685__gpgpu_threadgroup_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3043, 32, NULL,acmgt3__ext685__async_gpgpu_threadgroup_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3044, 40, NULL,acmgt3__ext685__async_gpgpu_thread_exit_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext686_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext686";
   query->symbol_name = "Ext686";
   query->guid = "79941e03-5bdc-46e4-b142-84d418628e99";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x09A10CF2 },
         { .reg = 0x00009888, .val = 0x0BA10D74 },
         { .reg = 0x00009888, .val = 0x0DA10039 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A302AA },
         { .reg = 0x00009888, .val = 0x01A4001F },
         { .reg = 0x00009888, .val = 0x01A60155 },
         { .reg = 0x00009888, .val = 0x01A70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010803FF },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009888, .val = 0x0101001F },
         { .reg = 0x00009888, .val = 0x010B0155 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001D },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10C80 },
         { .reg = 0x00009888, .val = 0x0EA10D33 },
         { .reg = 0x00009888, .val = 0x10A10FB5 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10C70 },
         { .reg = 0x00009888, .val = 0x15A10CF2 },
         { .reg = 0x00009888, .val = 0x17A10DB7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAA0 },
         { .reg = 0x00009888, .val = 0x01A4FC00 },
         { .reg = 0x00009888, .val = 0x03A65550 },
         { .reg = 0x00009888, .val = 0x03A75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020BAAA5 },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FC00 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext686__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext686__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext686__avg_gpu_core_frequency__max,acmgt3__ext686__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1268, 24, NULL,acmgt3__ext686__gpgpu_threadgroup_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3045, 32, NULL,acmgt3__ext686__async_gpgpu_threadgroup_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3046, 40, NULL,acmgt3__ext686__async_gpgpu_thread_exit_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext687_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext687";
   query->symbol_name = "Ext687";
   query->guid = "9e53769d-3d3b-4a27-ab3f-f524dca94ac8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x09C10CF2 },
         { .reg = 0x00009888, .val = 0x0BC10D74 },
         { .reg = 0x00009888, .val = 0x0DC10039 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010702AA },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001D },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10C80 },
         { .reg = 0x00009888, .val = 0x0EC10D33 },
         { .reg = 0x00009888, .val = 0x10C10FB5 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x13C10C70 },
         { .reg = 0x00009888, .val = 0x15C10CF2 },
         { .reg = 0x00009888, .val = 0x17C10DB7 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C3AAA0 },
         { .reg = 0x00009888, .val = 0x01C4FC00 },
         { .reg = 0x00009888, .val = 0x03C65550 },
         { .reg = 0x00009888, .val = 0x03C75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207000A },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FC00 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext687__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext687__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext687__avg_gpu_core_frequency__max,acmgt3__ext687__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1273, 24, NULL,acmgt3__ext687__gpgpu_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3047, 32, NULL,acmgt3__ext687__async_gpgpu_threadgroup_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3048, 40, NULL,acmgt3__ext687__async_gpgpu_thread_exit_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext688_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext688";
   query->symbol_name = "Ext688";
   query->guid = "30301f6f-0a43-4ba9-a9d5-28aebf205bdf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x09E10CF2 },
         { .reg = 0x00009888, .val = 0x0BE10D74 },
         { .reg = 0x00009888, .val = 0x0DE10039 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001D },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10C80 },
         { .reg = 0x00009888, .val = 0x0EE10D33 },
         { .reg = 0x00009888, .val = 0x10E10FB5 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3A800 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E403E0 },
         { .reg = 0x00009888, .val = 0x00E65400 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x00E75400 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x13E10C70 },
         { .reg = 0x00009888, .val = 0x15E10CF2 },
         { .reg = 0x00009888, .val = 0x17E10DB7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAA0 },
         { .reg = 0x00009888, .val = 0x01E4FC00 },
         { .reg = 0x00009888, .val = 0x03E65550 },
         { .reg = 0x00009888, .val = 0x03E75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x00075400 },
         { .reg = 0x00009888, .val = 0x02070005 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext688__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext688__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext688__avg_gpu_core_frequency__max,acmgt3__ext688__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1274, 24, NULL,acmgt3__ext688__gpgpu_threadgroup_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3049, 32, NULL,acmgt3__ext688__async_gpgpu_threadgroup_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3050, 40, NULL,acmgt3__ext688__async_gpgpu_thread_exit_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext689_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext689";
   query->symbol_name = "Ext689";
   query->guid = "1d483608-9139-4903-a3af-e3ed4efc0992";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001D },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x08810CF2 },
         { .reg = 0x00009888, .val = 0x0A810D74 },
         { .reg = 0x00009888, .val = 0x0C810039 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810C80 },
         { .reg = 0x00009888, .val = 0x0F810D33 },
         { .reg = 0x00009888, .val = 0x11810FB5 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x0308000A },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x12810C70 },
         { .reg = 0x00009888, .val = 0x14810CF2 },
         { .reg = 0x00009888, .val = 0x16810DB7 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AAA0 },
         { .reg = 0x00009888, .val = 0x0084FC00 },
         { .reg = 0x00009888, .val = 0x02865550 },
         { .reg = 0x00009888, .val = 0x02875550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E031CE8 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032107 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40031CE7 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext689__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext689__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext689__avg_gpu_core_frequency__max,acmgt3__ext689__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3051, 24, NULL,acmgt3__ext689__gpgpu_threadgroup_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3052, 32, NULL,acmgt3__ext689__async_gpgpu_threadgroup_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5097, 40, NULL,acmgt3__ext689__async_gpgpu_thread_exit_count_xecore16__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext690_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext690";
   query->symbol_name = "Ext690";
   query->guid = "a9cf3d9a-04ab-40d7-ab88-0eb97a8ddcca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001D },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x08A10CF2 },
         { .reg = 0x00009888, .val = 0x0AA10D74 },
         { .reg = 0x00009888, .val = 0x0CA10039 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10C80 },
         { .reg = 0x00009888, .val = 0x0FA10D33 },
         { .reg = 0x00009888, .val = 0x11A10FB5 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BA955 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108FC00 },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x12A10C70 },
         { .reg = 0x00009888, .val = 0x14A10CF2 },
         { .reg = 0x00009888, .val = 0x16A10DB7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAA0 },
         { .reg = 0x00009888, .val = 0x00A4FC00 },
         { .reg = 0x00009888, .val = 0x02A65550 },
         { .reg = 0x00009888, .val = 0x02A75550 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E031CE8 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032107 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40031CE7 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext690__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext690__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext690__avg_gpu_core_frequency__max,acmgt3__ext690__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3053, 24, NULL,acmgt3__ext690__gpgpu_threadgroup_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3054, 32, NULL,acmgt3__ext690__async_gpgpu_threadgroup_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5098, 40, NULL,acmgt3__ext690__async_gpgpu_thread_exit_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext691_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext691";
   query->symbol_name = "Ext691";
   query->guid = "191874c3-d6af-4243-9b01-2b0f85bee6e4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001D },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x08C10CF2 },
         { .reg = 0x00009888, .val = 0x0AC10D74 },
         { .reg = 0x00009888, .val = 0x0CC10039 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C302AA },
         { .reg = 0x00009888, .val = 0x00C4001F },
         { .reg = 0x00009888, .val = 0x00C60155 },
         { .reg = 0x00009888, .val = 0x00C70155 },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10C80 },
         { .reg = 0x00009888, .val = 0x0FC10D33 },
         { .reg = 0x00009888, .val = 0x11C10FB5 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A800 },
         { .reg = 0x00009888, .val = 0x03C3000A },
         { .reg = 0x00009888, .val = 0x01C403E0 },
         { .reg = 0x00009888, .val = 0x01C65400 },
         { .reg = 0x00009888, .val = 0x03C60005 },
         { .reg = 0x00009888, .val = 0x01C75400 },
         { .reg = 0x00009888, .val = 0x03C70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x000702AA },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x000C0155 },
         { .reg = 0x00009888, .val = 0x0107A800 },
         { .reg = 0x00009888, .val = 0x0307000A },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x010203E0 },
         { .reg = 0x00009888, .val = 0x010C5400 },
         { .reg = 0x00009888, .val = 0x030C0005 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C70 },
         { .reg = 0x00009888, .val = 0x14C10CF2 },
         { .reg = 0x00009888, .val = 0x16C10DB7 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C3AAA0 },
         { .reg = 0x00009888, .val = 0x00C4FC00 },
         { .reg = 0x00009888, .val = 0x02C65550 },
         { .reg = 0x00009888, .val = 0x02C75550 },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E031CE8 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032107 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40031CE7 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext691__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext691__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext691__avg_gpu_core_frequency__max,acmgt3__ext691__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3055, 24, NULL,acmgt3__ext691__gpgpu_threadgroup_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3056, 32, NULL,acmgt3__ext691__async_gpgpu_threadgroup_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5099, 40, NULL,acmgt3__ext691__async_gpgpu_thread_exit_count_xecore18__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext692_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext692";
   query->symbol_name = "Ext692";
   query->guid = "0bcd4036-fa21-4cd9-8f17-dc709ee95db0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001D },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x08E10CF2 },
         { .reg = 0x00009888, .val = 0x0AE10D74 },
         { .reg = 0x00009888, .val = 0x0CE10039 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10C80 },
         { .reg = 0x00009888, .val = 0x0FE10D33 },
         { .reg = 0x00009888, .val = 0x11E10FB5 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01075400 },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x12E10C70 },
         { .reg = 0x00009888, .val = 0x14E10CF2 },
         { .reg = 0x00009888, .val = 0x16E10DB7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAA0 },
         { .reg = 0x00009888, .val = 0x00E4FC00 },
         { .reg = 0x00009888, .val = 0x02E65550 },
         { .reg = 0x00009888, .val = 0x02E75550 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E031CE8 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032107 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40031CE7 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext692__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext692__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext692__avg_gpu_core_frequency__max,acmgt3__ext692__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3057, 24, NULL,acmgt3__ext692__gpgpu_threadgroup_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3058, 32, NULL,acmgt3__ext692__async_gpgpu_threadgroup_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5100, 40, NULL,acmgt3__ext692__async_gpgpu_thread_exit_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext693_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext693";
   query->symbol_name = "Ext693";
   query->guid = "b7b13b5c-1e45-4127-9bc9-fabd732ec407";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x09810CF2 },
         { .reg = 0x00009888, .val = 0x0B810D74 },
         { .reg = 0x00009888, .val = 0x0D810039 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010802AA },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001D },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810C80 },
         { .reg = 0x00009888, .val = 0x0E810D33 },
         { .reg = 0x00009888, .val = 0x10810FB5 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A800 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x008403E0 },
         { .reg = 0x00009888, .val = 0x00865400 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00875400 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C70 },
         { .reg = 0x00009888, .val = 0x15810CF2 },
         { .reg = 0x00009888, .val = 0x17810DB7 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AAA0 },
         { .reg = 0x00009888, .val = 0x0184FC00 },
         { .reg = 0x00009888, .val = 0x03865550 },
         { .reg = 0x00009888, .val = 0x03875550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C21 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext693__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext693__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext693__avg_gpu_core_frequency__max,acmgt3__ext693__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3059, 24, NULL,acmgt3__ext693__gpgpu_threadgroup_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5101, 32, NULL,acmgt3__ext693__async_gpgpu_threadgroup_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5102, 40, NULL,acmgt3__ext693__async_gpgpu_thread_exit_count_xecore20__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext694_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext694";
   query->symbol_name = "Ext694";
   query->guid = "e1c1db08-2425-4276-9b36-13831ce7774a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x09A10CF2 },
         { .reg = 0x00009888, .val = 0x0BA10D74 },
         { .reg = 0x00009888, .val = 0x0DA10039 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A302AA },
         { .reg = 0x00009888, .val = 0x01A4001F },
         { .reg = 0x00009888, .val = 0x01A60155 },
         { .reg = 0x00009888, .val = 0x01A70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010803FF },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009888, .val = 0x0101001F },
         { .reg = 0x00009888, .val = 0x010B0155 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001D },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10C80 },
         { .reg = 0x00009888, .val = 0x0EA10D33 },
         { .reg = 0x00009888, .val = 0x10A10FB5 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10C70 },
         { .reg = 0x00009888, .val = 0x15A10CF2 },
         { .reg = 0x00009888, .val = 0x17A10DB7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAA0 },
         { .reg = 0x00009888, .val = 0x01A4FC00 },
         { .reg = 0x00009888, .val = 0x03A65550 },
         { .reg = 0x00009888, .val = 0x03A75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020BAAA5 },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FC00 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C21 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext694__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext694__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext694__avg_gpu_core_frequency__max,acmgt3__ext694__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3060, 24, NULL,acmgt3__ext694__gpgpu_threadgroup_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5103, 32, NULL,acmgt3__ext694__async_gpgpu_threadgroup_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5104, 40, NULL,acmgt3__ext694__async_gpgpu_thread_exit_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext695_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext695";
   query->symbol_name = "Ext695";
   query->guid = "84e85a65-8a55-41ac-90af-3c4fe98910a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x09C10CF2 },
         { .reg = 0x00009888, .val = 0x0BC10D74 },
         { .reg = 0x00009888, .val = 0x0DC10039 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010702AA },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001D },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10C80 },
         { .reg = 0x00009888, .val = 0x0EC10D33 },
         { .reg = 0x00009888, .val = 0x10C10FB5 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x13C10C70 },
         { .reg = 0x00009888, .val = 0x15C10CF2 },
         { .reg = 0x00009888, .val = 0x17C10DB7 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C3AAA0 },
         { .reg = 0x00009888, .val = 0x01C4FC00 },
         { .reg = 0x00009888, .val = 0x03C65550 },
         { .reg = 0x00009888, .val = 0x03C75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207000A },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FC00 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C21 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext695__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext695__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext695__avg_gpu_core_frequency__max,acmgt3__ext695__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3061, 24, NULL,acmgt3__ext695__gpgpu_threadgroup_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5105, 32, NULL,acmgt3__ext695__async_gpgpu_threadgroup_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5106, 40, NULL,acmgt3__ext695__async_gpgpu_thread_exit_count_xecore22__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext696_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext696";
   query->symbol_name = "Ext696";
   query->guid = "58ee0229-4bdc-4d5b-beaa-12bdff92eb97";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x09E10CF2 },
         { .reg = 0x00009888, .val = 0x0BE10D74 },
         { .reg = 0x00009888, .val = 0x0DE10039 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001D },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10C80 },
         { .reg = 0x00009888, .val = 0x0EE10D33 },
         { .reg = 0x00009888, .val = 0x10E10FB5 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3A800 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E403E0 },
         { .reg = 0x00009888, .val = 0x00E65400 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x00E75400 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x13E10C70 },
         { .reg = 0x00009888, .val = 0x15E10CF2 },
         { .reg = 0x00009888, .val = 0x17E10DB7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAA0 },
         { .reg = 0x00009888, .val = 0x01E4FC00 },
         { .reg = 0x00009888, .val = 0x03E65550 },
         { .reg = 0x00009888, .val = 0x03E75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x00075400 },
         { .reg = 0x00009888, .val = 0x02070005 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C21 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext696__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext696__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext696__avg_gpu_core_frequency__max,acmgt3__ext696__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3062, 24, NULL,acmgt3__ext696__gpgpu_threadgroup_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5107, 32, NULL,acmgt3__ext696__async_gpgpu_threadgroup_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5108, 40, NULL,acmgt3__ext696__async_gpgpu_thread_exit_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext697_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext697";
   query->symbol_name = "Ext697";
   query->guid = "76811470-81d5-4807-9f02-f1c61785015f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001D },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x08810CF2 },
         { .reg = 0x00009888, .val = 0x0A810D74 },
         { .reg = 0x00009888, .val = 0x0C810039 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810C80 },
         { .reg = 0x00009888, .val = 0x0F810D33 },
         { .reg = 0x00009888, .val = 0x11810FB5 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x0308000A },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x12810C70 },
         { .reg = 0x00009888, .val = 0x14810CF2 },
         { .reg = 0x00009888, .val = 0x16810DB7 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AAA0 },
         { .reg = 0x00009888, .val = 0x0084FC00 },
         { .reg = 0x00009888, .val = 0x02865550 },
         { .reg = 0x00009888, .val = 0x02875550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x0202AAA5 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032108 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032108 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext697__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext697__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext697__avg_gpu_core_frequency__max,acmgt3__ext697__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5109, 24, NULL,acmgt3__ext697__gpgpu_threadgroup_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5110, 32, NULL,acmgt3__ext697__async_gpgpu_threadgroup_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5111, 40, NULL,acmgt3__ext697__async_gpgpu_thread_exit_count_xecore24__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext698_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext698";
   query->symbol_name = "Ext698";
   query->guid = "ee3d62c3-7921-453e-9e17-4de797e22de6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001D },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x08A10CF2 },
         { .reg = 0x00009888, .val = 0x0AA10D74 },
         { .reg = 0x00009888, .val = 0x0CA10039 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10C80 },
         { .reg = 0x00009888, .val = 0x0FA10D33 },
         { .reg = 0x00009888, .val = 0x11A10FB5 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BA955 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108FC00 },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x12A10C70 },
         { .reg = 0x00009888, .val = 0x14A10CF2 },
         { .reg = 0x00009888, .val = 0x16A10DB7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAA0 },
         { .reg = 0x00009888, .val = 0x00A4FC00 },
         { .reg = 0x00009888, .val = 0x02A65550 },
         { .reg = 0x00009888, .val = 0x02A75550 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x0202AAA5 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032108 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032108 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext698__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext698__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext698__avg_gpu_core_frequency__max,acmgt3__ext698__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5112, 24, NULL,acmgt3__ext698__gpgpu_threadgroup_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5113, 32, NULL,acmgt3__ext698__async_gpgpu_threadgroup_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5114, 40, NULL,acmgt3__ext698__async_gpgpu_thread_exit_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext699_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext699";
   query->symbol_name = "Ext699";
   query->guid = "c53174bb-fbdc-4c0a-8132-75c1a668b433";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001D },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x08C10CF2 },
         { .reg = 0x00009888, .val = 0x0AC10D74 },
         { .reg = 0x00009888, .val = 0x0CC10039 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C302AA },
         { .reg = 0x00009888, .val = 0x00C4001F },
         { .reg = 0x00009888, .val = 0x00C60155 },
         { .reg = 0x00009888, .val = 0x00C70155 },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10C80 },
         { .reg = 0x00009888, .val = 0x0FC10D33 },
         { .reg = 0x00009888, .val = 0x11C10FB5 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A800 },
         { .reg = 0x00009888, .val = 0x03C3000A },
         { .reg = 0x00009888, .val = 0x01C403E0 },
         { .reg = 0x00009888, .val = 0x01C65400 },
         { .reg = 0x00009888, .val = 0x03C60005 },
         { .reg = 0x00009888, .val = 0x01C75400 },
         { .reg = 0x00009888, .val = 0x03C70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x000702AA },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x000C0155 },
         { .reg = 0x00009888, .val = 0x0107A800 },
         { .reg = 0x00009888, .val = 0x0307000A },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x010203E0 },
         { .reg = 0x00009888, .val = 0x010C5400 },
         { .reg = 0x00009888, .val = 0x030C0005 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C70 },
         { .reg = 0x00009888, .val = 0x14C10CF2 },
         { .reg = 0x00009888, .val = 0x16C10DB7 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C3AAA0 },
         { .reg = 0x00009888, .val = 0x00C4FC00 },
         { .reg = 0x00009888, .val = 0x02C65550 },
         { .reg = 0x00009888, .val = 0x02C75550 },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x0202AAA5 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032108 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032108 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext699__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext699__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext699__avg_gpu_core_frequency__max,acmgt3__ext699__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5115, 24, NULL,acmgt3__ext699__gpgpu_threadgroup_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5116, 32, NULL,acmgt3__ext699__async_gpgpu_threadgroup_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5117, 40, NULL,acmgt3__ext699__async_gpgpu_thread_exit_count_xecore26__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext700_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext700";
   query->symbol_name = "Ext700";
   query->guid = "642d68f5-312a-44d6-9bae-2bd1e3b3e617";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001D },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x08E10CF2 },
         { .reg = 0x00009888, .val = 0x0AE10D74 },
         { .reg = 0x00009888, .val = 0x0CE10039 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10C80 },
         { .reg = 0x00009888, .val = 0x0FE10D33 },
         { .reg = 0x00009888, .val = 0x11E10FB5 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01075400 },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x12E10C70 },
         { .reg = 0x00009888, .val = 0x14E10CF2 },
         { .reg = 0x00009888, .val = 0x16E10DB7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAA0 },
         { .reg = 0x00009888, .val = 0x00E4FC00 },
         { .reg = 0x00009888, .val = 0x02E65550 },
         { .reg = 0x00009888, .val = 0x02E75550 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x0202AAA5 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032108 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032108 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext700__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext700__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext700__avg_gpu_core_frequency__max,acmgt3__ext700__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5118, 24, NULL,acmgt3__ext700__gpgpu_threadgroup_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5119, 32, NULL,acmgt3__ext700__async_gpgpu_threadgroup_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5120, 40, NULL,acmgt3__ext700__async_gpgpu_thread_exit_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext701_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext701";
   query->symbol_name = "Ext701";
   query->guid = "5269dd1e-6831-4902-8ca4-592b23c58ef2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x09810CF2 },
         { .reg = 0x00009888, .val = 0x0B810D74 },
         { .reg = 0x00009888, .val = 0x0D810039 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010802AA },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001D },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810C80 },
         { .reg = 0x00009888, .val = 0x0E810D33 },
         { .reg = 0x00009888, .val = 0x10810FB5 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A800 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x008403E0 },
         { .reg = 0x00009888, .val = 0x00865400 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00875400 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C70 },
         { .reg = 0x00009888, .val = 0x15810CF2 },
         { .reg = 0x00009888, .val = 0x17810DB7 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AAA0 },
         { .reg = 0x00009888, .val = 0x0184FC00 },
         { .reg = 0x00009888, .val = 0x03865550 },
         { .reg = 0x00009888, .val = 0x03875550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002A955 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext701__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext701__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext701__avg_gpu_core_frequency__max,acmgt3__ext701__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5121, 24, NULL,acmgt3__ext701__gpgpu_threadgroup_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5122, 32, NULL,acmgt3__ext701__async_gpgpu_threadgroup_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5123, 40, NULL,acmgt3__ext701__async_gpgpu_thread_exit_count_xecore28__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext702_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext702";
   query->symbol_name = "Ext702";
   query->guid = "b1b5a799-4514-4027-9223-f51839cab382";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x09A10CF2 },
         { .reg = 0x00009888, .val = 0x0BA10D74 },
         { .reg = 0x00009888, .val = 0x0DA10039 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A302AA },
         { .reg = 0x00009888, .val = 0x01A4001F },
         { .reg = 0x00009888, .val = 0x01A60155 },
         { .reg = 0x00009888, .val = 0x01A70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010803FF },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009888, .val = 0x0101001F },
         { .reg = 0x00009888, .val = 0x010B0155 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001D },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10C80 },
         { .reg = 0x00009888, .val = 0x0EA10D33 },
         { .reg = 0x00009888, .val = 0x10A10FB5 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10C70 },
         { .reg = 0x00009888, .val = 0x15A10CF2 },
         { .reg = 0x00009888, .val = 0x17A10DB7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAA0 },
         { .reg = 0x00009888, .val = 0x01A4FC00 },
         { .reg = 0x00009888, .val = 0x03A65550 },
         { .reg = 0x00009888, .val = 0x03A75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020BAAA5 },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FC00 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002A955 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext702__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext702__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext702__avg_gpu_core_frequency__max,acmgt3__ext702__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5124, 24, NULL,acmgt3__ext702__gpgpu_threadgroup_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5125, 32, NULL,acmgt3__ext702__async_gpgpu_threadgroup_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5126, 40, NULL,acmgt3__ext702__async_gpgpu_thread_exit_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext703_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext703";
   query->symbol_name = "Ext703";
   query->guid = "6357ffd6-fe33-463d-8251-2113c8a90e6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x09C10CF2 },
         { .reg = 0x00009888, .val = 0x0BC10D74 },
         { .reg = 0x00009888, .val = 0x0DC10039 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010702AA },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001D },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10C80 },
         { .reg = 0x00009888, .val = 0x0EC10D33 },
         { .reg = 0x00009888, .val = 0x10C10FB5 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x13C10C70 },
         { .reg = 0x00009888, .val = 0x15C10CF2 },
         { .reg = 0x00009888, .val = 0x17C10DB7 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C3AAA0 },
         { .reg = 0x00009888, .val = 0x01C4FC00 },
         { .reg = 0x00009888, .val = 0x03C65550 },
         { .reg = 0x00009888, .val = 0x03C75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207000A },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FC00 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002A955 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext703__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext703__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext703__avg_gpu_core_frequency__max,acmgt3__ext703__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5127, 24, NULL,acmgt3__ext703__gpgpu_threadgroup_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5128, 32, NULL,acmgt3__ext703__async_gpgpu_threadgroup_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5129, 40, NULL,acmgt3__ext703__async_gpgpu_thread_exit_count_xecore30__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext704_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext704";
   query->symbol_name = "Ext704";
   query->guid = "06b581a0-09fb-4a45-a8d8-bd77234eedf5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x09E10CF2 },
         { .reg = 0x00009888, .val = 0x0BE10D74 },
         { .reg = 0x00009888, .val = 0x0DE10039 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001D },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10C80 },
         { .reg = 0x00009888, .val = 0x0EE10D33 },
         { .reg = 0x00009888, .val = 0x10E10FB5 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3A800 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E403E0 },
         { .reg = 0x00009888, .val = 0x00E65400 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x00E75400 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x13E10C70 },
         { .reg = 0x00009888, .val = 0x15E10CF2 },
         { .reg = 0x00009888, .val = 0x17E10DB7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAA0 },
         { .reg = 0x00009888, .val = 0x01E4FC00 },
         { .reg = 0x00009888, .val = 0x03E65550 },
         { .reg = 0x00009888, .val = 0x03E75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x00075400 },
         { .reg = 0x00009888, .val = 0x02070005 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002A955 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A031068 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext704__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext704__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext704__avg_gpu_core_frequency__max,acmgt3__ext704__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5130, 24, NULL,acmgt3__ext704__gpgpu_threadgroup_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5131, 32, NULL,acmgt3__ext704__async_gpgpu_threadgroup_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5132, 40, NULL,acmgt3__ext704__async_gpgpu_thread_exit_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext705_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext705";
   query->symbol_name = "Ext705";
   query->guid = "8c310d10-71e6-461c-92cb-4b33e359c923";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x12810C70 },
         { .reg = 0x00009888, .val = 0x14810CF2 },
         { .reg = 0x00009888, .val = 0x16810DB7 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0283AAA0 },
         { .reg = 0x00009888, .val = 0x0084FC00 },
         { .reg = 0x00009888, .val = 0x02865550 },
         { .reg = 0x00009888, .val = 0x02875550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001D },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x08810CF2 },
         { .reg = 0x00009888, .val = 0x0A810D74 },
         { .reg = 0x00009888, .val = 0x0C810039 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810C80 },
         { .reg = 0x00009888, .val = 0x0F810D33 },
         { .reg = 0x00009888, .val = 0x11810FB5 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x0308000A },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202000A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032528 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032109 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032529 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext705__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext705__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext705__avg_gpu_core_frequency__max,acmgt3__ext705__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5133, 24, NULL,acmgt3__ext705__gpgpu_threadgroup_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5134, 32, NULL,acmgt3__ext705__async_gpgpu_threadgroup_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1259, 40, NULL,acmgt3__ext705__async_gpgpu_thread_exit_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext706_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext706";
   query->symbol_name = "Ext706";
   query->guid = "01126493-600a-4768-aa3e-283509f04aaa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x12A10C70 },
         { .reg = 0x00009888, .val = 0x14A10CF2 },
         { .reg = 0x00009888, .val = 0x16A10DB7 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A3AAA0 },
         { .reg = 0x00009888, .val = 0x00A4FC00 },
         { .reg = 0x00009888, .val = 0x02A65550 },
         { .reg = 0x00009888, .val = 0x02A75550 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x020A5550 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020B5550 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001D },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x08A10CF2 },
         { .reg = 0x00009888, .val = 0x0AA10D74 },
         { .reg = 0x00009888, .val = 0x0CA10039 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10C80 },
         { .reg = 0x00009888, .val = 0x0FA10D33 },
         { .reg = 0x00009888, .val = 0x11A10FB5 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BA955 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0108FC00 },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A0005 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202000A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032528 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032109 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032529 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext706__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext706__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext706__avg_gpu_core_frequency__max,acmgt3__ext706__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5135, 24, NULL,acmgt3__ext706__gpgpu_threadgroup_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5136, 32, NULL,acmgt3__ext706__async_gpgpu_threadgroup_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1265, 40, NULL,acmgt3__ext706__async_gpgpu_thread_exit_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext707_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext707";
   query->symbol_name = "Ext707";
   query->guid = "516486d7-89fc-4a00-a8ac-8cd23b9fc260";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C70 },
         { .reg = 0x00009888, .val = 0x14C10CF2 },
         { .reg = 0x00009888, .val = 0x16C10DB7 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C3AAA0 },
         { .reg = 0x00009888, .val = 0x00C4FC00 },
         { .reg = 0x00009888, .val = 0x02C65550 },
         { .reg = 0x00009888, .val = 0x02C75550 },
         { .reg = 0x00009888, .val = 0x0207AAA0 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x020C5550 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001D },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x08C10CF2 },
         { .reg = 0x00009888, .val = 0x0AC10D74 },
         { .reg = 0x00009888, .val = 0x0CC10039 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C302AA },
         { .reg = 0x00009888, .val = 0x00C4001F },
         { .reg = 0x00009888, .val = 0x00C60155 },
         { .reg = 0x00009888, .val = 0x00C70155 },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10C80 },
         { .reg = 0x00009888, .val = 0x0FC10D33 },
         { .reg = 0x00009888, .val = 0x11C10FB5 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A800 },
         { .reg = 0x00009888, .val = 0x03C3000A },
         { .reg = 0x00009888, .val = 0x01C403E0 },
         { .reg = 0x00009888, .val = 0x01C65400 },
         { .reg = 0x00009888, .val = 0x03C60005 },
         { .reg = 0x00009888, .val = 0x01C75400 },
         { .reg = 0x00009888, .val = 0x03C70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x000702AA },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x000C0155 },
         { .reg = 0x00009888, .val = 0x0107A800 },
         { .reg = 0x00009888, .val = 0x0307000A },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x010203E0 },
         { .reg = 0x00009888, .val = 0x010C5400 },
         { .reg = 0x00009888, .val = 0x030C0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202000A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032528 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032109 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032529 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext707__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext707__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext707__avg_gpu_core_frequency__max,acmgt3__ext707__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5137, 24, NULL,acmgt3__ext707__gpgpu_threadgroup_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5138, 32, NULL,acmgt3__ext707__async_gpgpu_threadgroup_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1271, 40, NULL,acmgt3__ext707__async_gpgpu_thread_exit_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext708_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext708";
   query->symbol_name = "Ext708";
   query->guid = "61ba9e98-48b7-4081-8907-a5f9f6a16244";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x12E10C70 },
         { .reg = 0x00009888, .val = 0x14E10CF2 },
         { .reg = 0x00009888, .val = 0x16E10DB7 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E3AAA0 },
         { .reg = 0x00009888, .val = 0x00E4FC00 },
         { .reg = 0x00009888, .val = 0x02E65550 },
         { .reg = 0x00009888, .val = 0x02E75550 },
         { .reg = 0x00009888, .val = 0x02075550 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001D },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x08E10CF2 },
         { .reg = 0x00009888, .val = 0x0AE10D74 },
         { .reg = 0x00009888, .val = 0x0CE10039 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10C80 },
         { .reg = 0x00009888, .val = 0x0FE10D33 },
         { .reg = 0x00009888, .val = 0x11E10FB5 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303E0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x01075400 },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903E0 },
         { .reg = 0x00009888, .val = 0x010AA800 },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202000A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E032528 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032109 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030108 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032529 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009888, .val = 0x20033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x02025550 },
         { .reg = 0x00009888, .val = 0x02045550 },
         { .reg = 0x00009888, .val = 0x02055550 },
         { .reg = 0x00009888, .val = 0x0208AAA0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext708__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext708__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext708__avg_gpu_core_frequency__max,acmgt3__ext708__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5139, 24, NULL,acmgt3__ext708__gpgpu_threadgroup_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5140, 32, NULL,acmgt3__ext708__async_gpgpu_threadgroup_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1277, 40, NULL,acmgt3__ext708__async_gpgpu_thread_exit_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext709_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext709";
   query->symbol_name = "Ext709";
   query->guid = "a638ef3a-2575-4dcf-93dc-8d351b712a73";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001D },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810C80 },
         { .reg = 0x00009888, .val = 0x0E810D33 },
         { .reg = 0x00009888, .val = 0x10810FB5 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A800 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x008403E0 },
         { .reg = 0x00009888, .val = 0x00865400 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00875400 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C70 },
         { .reg = 0x00009888, .val = 0x15810CF2 },
         { .reg = 0x00009888, .val = 0x17810DB7 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383AAA0 },
         { .reg = 0x00009888, .val = 0x0184FC00 },
         { .reg = 0x00009888, .val = 0x03865550 },
         { .reg = 0x00009888, .val = 0x03875550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208FFFA },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x0308AAA0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x09810CF2 },
         { .reg = 0x00009888, .val = 0x0B810D74 },
         { .reg = 0x00009888, .val = 0x0D810039 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010802AA },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000202AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030001 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031269 },
         { .reg = 0x00009888, .val = 0x48030693 },
         { .reg = 0x00009888, .val = 0x4A031269 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030421 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext709__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext709__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext709__avg_gpu_core_frequency__max,acmgt3__ext709__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5141, 24, NULL,acmgt3__ext709__gpgpu_threadgroup_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1298, 32, NULL,acmgt3__ext709__async_gpgpu_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1283, 40, NULL,acmgt3__ext709__async_gpgpu_thread_exit_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext710_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext710";
   query->symbol_name = "Ext710";
   query->guid = "3b04d5c5-301a-4089-ac8b-71ab483ead8b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001D },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10C80 },
         { .reg = 0x00009888, .val = 0x0EA10D33 },
         { .reg = 0x00009888, .val = 0x10A10FB5 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10C70 },
         { .reg = 0x00009888, .val = 0x15A10CF2 },
         { .reg = 0x00009888, .val = 0x17A10DB7 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A3AAA0 },
         { .reg = 0x00009888, .val = 0x01A4FC00 },
         { .reg = 0x00009888, .val = 0x03A65550 },
         { .reg = 0x00009888, .val = 0x03A75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020BAAA5 },
         { .reg = 0x00009888, .val = 0x0308FFF0 },
         { .reg = 0x00009888, .val = 0x030A5550 },
         { .reg = 0x00009888, .val = 0x0101FC00 },
         { .reg = 0x00009888, .val = 0x030B5550 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x09A10CF2 },
         { .reg = 0x00009888, .val = 0x0BA10D74 },
         { .reg = 0x00009888, .val = 0x0DA10039 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A302AA },
         { .reg = 0x00009888, .val = 0x01A4001F },
         { .reg = 0x00009888, .val = 0x01A60155 },
         { .reg = 0x00009888, .val = 0x01A70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010803FF },
         { .reg = 0x00009888, .val = 0x010A0155 },
         { .reg = 0x00009888, .val = 0x0101001F },
         { .reg = 0x00009888, .val = 0x010B0155 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000202AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030001 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031269 },
         { .reg = 0x00009888, .val = 0x48030693 },
         { .reg = 0x00009888, .val = 0x4A031269 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030421 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext710__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext710__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext710__avg_gpu_core_frequency__max,acmgt3__ext710__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5142, 24, NULL,acmgt3__ext710__gpgpu_threadgroup_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1289, 32, NULL,acmgt3__ext710__async_gpgpu_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1287, 40, NULL,acmgt3__ext710__async_gpgpu_thread_exit_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext711_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext711";
   query->symbol_name = "Ext711";
   query->guid = "80168138-f069-490d-8e12-81c65d059597";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001D },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10C80 },
         { .reg = 0x00009888, .val = 0x0EC10D33 },
         { .reg = 0x00009888, .val = 0x10C10FB5 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x13C10C70 },
         { .reg = 0x00009888, .val = 0x15C10CF2 },
         { .reg = 0x00009888, .val = 0x17C10DB7 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C3AAA0 },
         { .reg = 0x00009888, .val = 0x01C4FC00 },
         { .reg = 0x00009888, .val = 0x03C65550 },
         { .reg = 0x00009888, .val = 0x03C75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207000A },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009888, .val = 0x0307AAA0 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009888, .val = 0x0102FC00 },
         { .reg = 0x00009888, .val = 0x030C5550 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x09C10CF2 },
         { .reg = 0x00009888, .val = 0x0BC10D74 },
         { .reg = 0x00009888, .val = 0x0DC10039 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x010702AA },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000202AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030001 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031269 },
         { .reg = 0x00009888, .val = 0x48030693 },
         { .reg = 0x00009888, .val = 0x4A031269 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030421 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext711__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext711__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext711__avg_gpu_core_frequency__max,acmgt3__ext711__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5143, 24, NULL,acmgt3__ext711__gpgpu_threadgroup_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1290, 32, NULL,acmgt3__ext711__async_gpgpu_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1291, 40, NULL,acmgt3__ext711__async_gpgpu_thread_exit_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext712_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext712";
   query->symbol_name = "Ext712";
   query->guid = "26fb9ee1-06c9-488f-9454-6506a7fd0843";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001D },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10C80 },
         { .reg = 0x00009888, .val = 0x0EE10D33 },
         { .reg = 0x00009888, .val = 0x10E10FB5 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3A800 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E403E0 },
         { .reg = 0x00009888, .val = 0x00E65400 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x00E75400 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x13E10C70 },
         { .reg = 0x00009888, .val = 0x15E10CF2 },
         { .reg = 0x00009888, .val = 0x17E10DB7 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3AAA0 },
         { .reg = 0x00009888, .val = 0x01E4FC00 },
         { .reg = 0x00009888, .val = 0x03E65550 },
         { .reg = 0x00009888, .val = 0x03E75550 },
         { .reg = 0x00009888, .val = 0x0003FC00 },
         { .reg = 0x00009888, .val = 0x00075400 },
         { .reg = 0x00009888, .val = 0x02070005 },
         { .reg = 0x00009888, .val = 0x0208FFF0 },
         { .reg = 0x00009888, .val = 0x000903E0 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A555A },
         { .reg = 0x00009888, .val = 0x0001FC00 },
         { .reg = 0x00009888, .val = 0x020BAAA0 },
         { .reg = 0x00009888, .val = 0x03075550 },
         { .reg = 0x00009888, .val = 0x0109FC00 },
         { .reg = 0x00009888, .val = 0x030AAAA0 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x09E10CF2 },
         { .reg = 0x00009888, .val = 0x0BE10D74 },
         { .reg = 0x00009888, .val = 0x0DE10039 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000202AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030001 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46031269 },
         { .reg = 0x00009888, .val = 0x48030693 },
         { .reg = 0x00009888, .val = 0x4A031269 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030421 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x00030002 },
         { .reg = 0x0000D954, .val = 0x000003FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext712__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext712__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext712__avg_gpu_core_frequency__max,acmgt3__ext712__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5144, 24, NULL,acmgt3__ext712__gpgpu_threadgroup_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1293, 32, NULL,acmgt3__ext712__async_gpgpu_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1295, 40, NULL,acmgt3__ext712__async_gpgpu_thread_exit_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext713_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext713";
   query->symbol_name = "Ext713";
   query->guid = "bf21f1d0-886c-4295-a1ee-dcf1fe02a78b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810CF2 },
         { .reg = 0x00009888, .val = 0x0E810D74 },
         { .reg = 0x00009888, .val = 0x10810039 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083AA00 },
         { .reg = 0x00009888, .val = 0x02830002 },
         { .reg = 0x00009888, .val = 0x008401F0 },
         { .reg = 0x00009888, .val = 0x00865500 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x00875500 },
         { .reg = 0x00009888, .val = 0x02870001 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x13810CB1 },
         { .reg = 0x00009888, .val = 0x15810DF3 },
         { .reg = 0x00009888, .val = 0x17810036 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03832AA8 },
         { .reg = 0x00009888, .val = 0x01847E00 },
         { .reg = 0x00009888, .val = 0x03861554 },
         { .reg = 0x00009888, .val = 0x03871554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03082AA8 },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810DB7 },
         { .reg = 0x00009888, .val = 0x0A810CF5 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAFF },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D08 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext713__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext713__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext713__avg_gpu_core_frequency__max,acmgt3__ext713__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1281, 24, NULL,acmgt3__ext713__task_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1284, 32, NULL,acmgt3__ext713__task_thread_exit_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3063, 40, percentage_max_float,acmgt3__ext713__threadgroup_dispatch_resource_stall_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext714_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext714";
   query->symbol_name = "Ext714";
   query->guid = "b2bc5d5d-269d-429b-823a-50fbb0515f9c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10CF2 },
         { .reg = 0x00009888, .val = 0x0EA10D74 },
         { .reg = 0x00009888, .val = 0x10A10039 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x02A30002 },
         { .reg = 0x00009888, .val = 0x00A401F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x02A60001 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x02A70001 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x11A10C00 },
         { .reg = 0x00009888, .val = 0x13A10CB1 },
         { .reg = 0x00009888, .val = 0x15A10DF3 },
         { .reg = 0x00009888, .val = 0x17A10036 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32AA8 },
         { .reg = 0x00009888, .val = 0x01A47E00 },
         { .reg = 0x00009888, .val = 0x03A61554 },
         { .reg = 0x00009888, .val = 0x03A71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x020B2AA9 },
         { .reg = 0x00009888, .val = 0x03083FFC },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009888, .val = 0x01017E00 },
         { .reg = 0x00009888, .val = 0x030B1554 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10DB7 },
         { .reg = 0x00009888, .val = 0x0AA10CF5 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300AA },
         { .reg = 0x00009888, .val = 0x00A4000F },
         { .reg = 0x00009888, .val = 0x00A60055 },
         { .reg = 0x00009888, .val = 0x00A70055 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAFF },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D08 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext714__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext714__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext714__avg_gpu_core_frequency__max,acmgt3__ext714__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1282, 24, NULL,acmgt3__ext714__task_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1288, 32, NULL,acmgt3__ext714__task_thread_exit_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3064, 40, percentage_max_float,acmgt3__ext714__threadgroup_dispatch_resource_stall_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext715_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext715";
   query->symbol_name = "Ext715";
   query->guid = "bfa11009-8e53-4adf-9cdd-68469b9831dc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10CF2 },
         { .reg = 0x00009888, .val = 0x0EC10D74 },
         { .reg = 0x00009888, .val = 0x10C10039 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10C00 },
         { .reg = 0x00009888, .val = 0x13C10CB1 },
         { .reg = 0x00009888, .val = 0x15C10DF3 },
         { .reg = 0x00009888, .val = 0x17C10036 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32AA8 },
         { .reg = 0x00009888, .val = 0x01C47E00 },
         { .reg = 0x00009888, .val = 0x03C61554 },
         { .reg = 0x00009888, .val = 0x03C71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0007AA00 },
         { .reg = 0x00009888, .val = 0x02070002 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x000201F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009888, .val = 0x03072AA8 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009888, .val = 0x01027E00 },
         { .reg = 0x00009888, .val = 0x030C1554 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x08C10DB7 },
         { .reg = 0x00009888, .val = 0x0AC10CF5 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C300AA },
         { .reg = 0x00009888, .val = 0x00C4000F },
         { .reg = 0x00009888, .val = 0x00C60055 },
         { .reg = 0x00009888, .val = 0x00C70055 },
         { .reg = 0x00009888, .val = 0x000700AA },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009888, .val = 0x0002000F },
         { .reg = 0x00009888, .val = 0x000C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAFF },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D08 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext715__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext715__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext715__avg_gpu_core_frequency__max,acmgt3__ext715__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1263, 24, NULL,acmgt3__ext715__task_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1292, 32, NULL,acmgt3__ext715__task_thread_exit_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3065, 40, percentage_max_float,acmgt3__ext715__threadgroup_dispatch_resource_stall_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext716_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext716";
   query->symbol_name = "Ext716";
   query->guid = "cfdbeec4-9757-4bbc-88df-c239c4cfd596";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10CF2 },
         { .reg = 0x00009888, .val = 0x0EE10D74 },
         { .reg = 0x00009888, .val = 0x10E10039 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3AA00 },
         { .reg = 0x00009888, .val = 0x02E30002 },
         { .reg = 0x00009888, .val = 0x00E401F0 },
         { .reg = 0x00009888, .val = 0x00E65500 },
         { .reg = 0x00009888, .val = 0x02E60001 },
         { .reg = 0x00009888, .val = 0x00E75500 },
         { .reg = 0x00009888, .val = 0x02E70001 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10C00 },
         { .reg = 0x00009888, .val = 0x13E10CB1 },
         { .reg = 0x00009888, .val = 0x15E10DF3 },
         { .reg = 0x00009888, .val = 0x17E10036 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E32AA8 },
         { .reg = 0x00009888, .val = 0x01E47E00 },
         { .reg = 0x00009888, .val = 0x03E61554 },
         { .reg = 0x00009888, .val = 0x03E71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x00075500 },
         { .reg = 0x00009888, .val = 0x02070001 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03071554 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10DB7 },
         { .reg = 0x00009888, .val = 0x0AE10CF5 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x00070055 },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAFF },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D08 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext716__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext716__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext716__avg_gpu_core_frequency__max,acmgt3__ext716__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1264, 24, NULL,acmgt3__ext716__task_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1296, 32, NULL,acmgt3__ext716__task_thread_exit_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3066, 40, percentage_max_float,acmgt3__ext716__threadgroup_dispatch_resource_stall_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext717_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext717";
   query->symbol_name = "Ext717";
   query->guid = "f846da31-bf9f-4bbd-a0ed-c4b4d5847aa0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810CF2 },
         { .reg = 0x00009888, .val = 0x0F810D74 },
         { .reg = 0x00009888, .val = 0x11810039 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183AA00 },
         { .reg = 0x00009888, .val = 0x03830002 },
         { .reg = 0x00009888, .val = 0x018401F0 },
         { .reg = 0x00009888, .val = 0x01865500 },
         { .reg = 0x00009888, .val = 0x03860001 },
         { .reg = 0x00009888, .val = 0x01875500 },
         { .reg = 0x00009888, .val = 0x03870001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108AA00 },
         { .reg = 0x00009888, .val = 0x03080002 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x10810C00 },
         { .reg = 0x00009888, .val = 0x12810CB1 },
         { .reg = 0x00009888, .val = 0x14810DF3 },
         { .reg = 0x00009888, .val = 0x16810036 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02832AA8 },
         { .reg = 0x00009888, .val = 0x00847E00 },
         { .reg = 0x00009888, .val = 0x02861554 },
         { .reg = 0x00009888, .val = 0x02871554 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810DB7 },
         { .reg = 0x00009888, .val = 0x0B810CF5 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x010800AA },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAFF },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext717__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext717__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext717__avg_gpu_core_frequency__max,acmgt3__ext717__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1269, 24, NULL,acmgt3__ext717__task_threadgroup_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3067, 32, NULL,acmgt3__ext717__task_thread_exit_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3068, 40, percentage_max_float,acmgt3__ext717__threadgroup_dispatch_resource_stall_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext718_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext718";
   query->symbol_name = "Ext718";
   query->guid = "894bbe73-d0e2-41ae-86e4-26f2b865b04e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10CF2 },
         { .reg = 0x00009888, .val = 0x0FA10D74 },
         { .reg = 0x00009888, .val = 0x11A10039 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x03A30002 },
         { .reg = 0x00009888, .val = 0x01A401F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x03A60001 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x03A70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108FF00 },
         { .reg = 0x00009888, .val = 0x03080003 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009888, .val = 0x010101F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x030B0001 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x10A10C00 },
         { .reg = 0x00009888, .val = 0x12A10CB1 },
         { .reg = 0x00009888, .val = 0x14A10DF3 },
         { .reg = 0x00009888, .val = 0x16A10036 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32AA8 },
         { .reg = 0x00009888, .val = 0x00A47E00 },
         { .reg = 0x00009888, .val = 0x02A61554 },
         { .reg = 0x00009888, .val = 0x02A71554 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x09A10DB7 },
         { .reg = 0x00009888, .val = 0x0BA10CF5 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A300AA },
         { .reg = 0x00009888, .val = 0x01A4000F },
         { .reg = 0x00009888, .val = 0x01A60055 },
         { .reg = 0x00009888, .val = 0x01A70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x020B1554 },
         { .reg = 0x00009888, .val = 0x010800FF },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009888, .val = 0x0101000F },
         { .reg = 0x00009888, .val = 0x010B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAFF },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext718__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext718__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext718__avg_gpu_core_frequency__max,acmgt3__ext718__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1270, 24, NULL,acmgt3__ext718__task_threadgroup_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3069, 32, NULL,acmgt3__ext718__task_thread_exit_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3070, 40, percentage_max_float,acmgt3__ext718__threadgroup_dispatch_resource_stall_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext719_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext719";
   query->symbol_name = "Ext719";
   query->guid = "59118cde-ff58-4cfc-96f8-bc4339f59ca4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10CF2 },
         { .reg = 0x00009888, .val = 0x0FC10D74 },
         { .reg = 0x00009888, .val = 0x11C10039 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0107AA00 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009888, .val = 0x010201F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x10C10C00 },
         { .reg = 0x00009888, .val = 0x12C10CB1 },
         { .reg = 0x00009888, .val = 0x14C10DF3 },
         { .reg = 0x00009888, .val = 0x16C10036 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA8 },
         { .reg = 0x00009888, .val = 0x00C47E00 },
         { .reg = 0x00009888, .val = 0x02C61554 },
         { .reg = 0x00009888, .val = 0x02C71554 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10DB7 },
         { .reg = 0x00009888, .val = 0x0BC10CF5 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300AA },
         { .reg = 0x00009888, .val = 0x01C4000F },
         { .reg = 0x00009888, .val = 0x01C60055 },
         { .reg = 0x00009888, .val = 0x01C70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02072AA8 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x00027E00 },
         { .reg = 0x00009888, .val = 0x020C1554 },
         { .reg = 0x00009888, .val = 0x010700AA },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009888, .val = 0x0102000F },
         { .reg = 0x00009888, .val = 0x010C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAFF },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext719__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext719__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext719__avg_gpu_core_frequency__max,acmgt3__ext719__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1275, 24, NULL,acmgt3__ext719__task_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3071, 32, NULL,acmgt3__ext719__task_thread_exit_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3072, 40, percentage_max_float,acmgt3__ext719__threadgroup_dispatch_resource_stall_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext720_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext720";
   query->symbol_name = "Ext720";
   query->guid = "93b6fbd9-7440-4806-be39-642fa92233b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10CF2 },
         { .reg = 0x00009888, .val = 0x0FE10D74 },
         { .reg = 0x00009888, .val = 0x11E10039 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3AA00 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E401F0 },
         { .reg = 0x00009888, .val = 0x01E65500 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E75500 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x01075500 },
         { .reg = 0x00009888, .val = 0x03070001 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x10E10C00 },
         { .reg = 0x00009888, .val = 0x12E10CB1 },
         { .reg = 0x00009888, .val = 0x14E10DF3 },
         { .reg = 0x00009888, .val = 0x16E10036 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E32AA8 },
         { .reg = 0x00009888, .val = 0x00E47E00 },
         { .reg = 0x00009888, .val = 0x02E61554 },
         { .reg = 0x00009888, .val = 0x02E71554 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10DB7 },
         { .reg = 0x00009888, .val = 0x0BE10CF5 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02071554 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x01070055 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAFF },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext720__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext720__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext720__avg_gpu_core_frequency__max,acmgt3__ext720__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1276, 24, NULL,acmgt3__ext720__task_threadgroup_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3073, 32, NULL,acmgt3__ext720__task_thread_exit_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3074, 40, percentage_max_float,acmgt3__ext720__threadgroup_dispatch_resource_stall_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext721_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext721";
   query->symbol_name = "Ext721";
   query->guid = "cede3ea4-0edd-4d1f-9cec-0ef818ed889f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810CF2 },
         { .reg = 0x00009888, .val = 0x0E810D74 },
         { .reg = 0x00009888, .val = 0x10810039 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083AA00 },
         { .reg = 0x00009888, .val = 0x02830002 },
         { .reg = 0x00009888, .val = 0x008401F0 },
         { .reg = 0x00009888, .val = 0x00865500 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x00875500 },
         { .reg = 0x00009888, .val = 0x02870001 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x13810CB1 },
         { .reg = 0x00009888, .val = 0x15810DF3 },
         { .reg = 0x00009888, .val = 0x17810036 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03832AA8 },
         { .reg = 0x00009888, .val = 0x01847E00 },
         { .reg = 0x00009888, .val = 0x03861554 },
         { .reg = 0x00009888, .val = 0x03871554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03082AA8 },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810DB7 },
         { .reg = 0x00009888, .val = 0x0A810CF5 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42031CE0 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D07 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext721__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext721__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext721__avg_gpu_core_frequency__max,acmgt3__ext721__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3075, 24, NULL,acmgt3__ext721__task_threadgroup_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3076, 32, NULL,acmgt3__ext721__task_thread_exit_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5145, 40, percentage_max_float,acmgt3__ext721__threadgroup_dispatch_resource_stall_xecore16__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext722_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext722";
   query->symbol_name = "Ext722";
   query->guid = "dce7b950-36f2-44fd-b054-0a0329f3f3f6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10CF2 },
         { .reg = 0x00009888, .val = 0x0EA10D74 },
         { .reg = 0x00009888, .val = 0x10A10039 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x02A30002 },
         { .reg = 0x00009888, .val = 0x00A401F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x02A60001 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x02A70001 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x11A10C00 },
         { .reg = 0x00009888, .val = 0x13A10CB1 },
         { .reg = 0x00009888, .val = 0x15A10DF3 },
         { .reg = 0x00009888, .val = 0x17A10036 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32AA8 },
         { .reg = 0x00009888, .val = 0x01A47E00 },
         { .reg = 0x00009888, .val = 0x03A61554 },
         { .reg = 0x00009888, .val = 0x03A71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x020B2AA9 },
         { .reg = 0x00009888, .val = 0x03083FFC },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009888, .val = 0x01017E00 },
         { .reg = 0x00009888, .val = 0x030B1554 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10DB7 },
         { .reg = 0x00009888, .val = 0x0AA10CF5 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300AA },
         { .reg = 0x00009888, .val = 0x00A4000F },
         { .reg = 0x00009888, .val = 0x00A60055 },
         { .reg = 0x00009888, .val = 0x00A70055 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42031CE0 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D07 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext722__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext722__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext722__avg_gpu_core_frequency__max,acmgt3__ext722__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3077, 24, NULL,acmgt3__ext722__task_threadgroup_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3078, 32, NULL,acmgt3__ext722__task_thread_exit_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5146, 40, percentage_max_float,acmgt3__ext722__threadgroup_dispatch_resource_stall_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext723_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext723";
   query->symbol_name = "Ext723";
   query->guid = "c3af1c92-2c04-4d33-99a6-20c5354f499d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10CF2 },
         { .reg = 0x00009888, .val = 0x0EC10D74 },
         { .reg = 0x00009888, .val = 0x10C10039 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10C00 },
         { .reg = 0x00009888, .val = 0x13C10CB1 },
         { .reg = 0x00009888, .val = 0x15C10DF3 },
         { .reg = 0x00009888, .val = 0x17C10036 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32AA8 },
         { .reg = 0x00009888, .val = 0x01C47E00 },
         { .reg = 0x00009888, .val = 0x03C61554 },
         { .reg = 0x00009888, .val = 0x03C71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0007AA00 },
         { .reg = 0x00009888, .val = 0x02070002 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x000201F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009888, .val = 0x03072AA8 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009888, .val = 0x01027E00 },
         { .reg = 0x00009888, .val = 0x030C1554 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x08C10DB7 },
         { .reg = 0x00009888, .val = 0x0AC10CF5 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C300AA },
         { .reg = 0x00009888, .val = 0x00C4000F },
         { .reg = 0x00009888, .val = 0x00C60055 },
         { .reg = 0x00009888, .val = 0x00C70055 },
         { .reg = 0x00009888, .val = 0x000700AA },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009888, .val = 0x0002000F },
         { .reg = 0x00009888, .val = 0x000C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42031CE0 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D07 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext723__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext723__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext723__avg_gpu_core_frequency__max,acmgt3__ext723__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3079, 24, NULL,acmgt3__ext723__task_threadgroup_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3080, 32, NULL,acmgt3__ext723__task_thread_exit_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5147, 40, percentage_max_float,acmgt3__ext723__threadgroup_dispatch_resource_stall_xecore18__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext724_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext724";
   query->symbol_name = "Ext724";
   query->guid = "e2e9e72d-9eb9-493e-b8c6-27a4b3864ca0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10CF2 },
         { .reg = 0x00009888, .val = 0x0EE10D74 },
         { .reg = 0x00009888, .val = 0x10E10039 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3AA00 },
         { .reg = 0x00009888, .val = 0x02E30002 },
         { .reg = 0x00009888, .val = 0x00E401F0 },
         { .reg = 0x00009888, .val = 0x00E65500 },
         { .reg = 0x00009888, .val = 0x02E60001 },
         { .reg = 0x00009888, .val = 0x00E75500 },
         { .reg = 0x00009888, .val = 0x02E70001 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10C00 },
         { .reg = 0x00009888, .val = 0x13E10CB1 },
         { .reg = 0x00009888, .val = 0x15E10DF3 },
         { .reg = 0x00009888, .val = 0x17E10036 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E32AA8 },
         { .reg = 0x00009888, .val = 0x01E47E00 },
         { .reg = 0x00009888, .val = 0x03E61554 },
         { .reg = 0x00009888, .val = 0x03E71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x00075500 },
         { .reg = 0x00009888, .val = 0x02070001 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03071554 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10DB7 },
         { .reg = 0x00009888, .val = 0x0AE10CF5 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x00070055 },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030007 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42031CE0 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D07 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext724__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext724__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext724__avg_gpu_core_frequency__max,acmgt3__ext724__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3081, 24, NULL,acmgt3__ext724__task_threadgroup_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3082, 32, NULL,acmgt3__ext724__task_thread_exit_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5148, 40, percentage_max_float,acmgt3__ext724__threadgroup_dispatch_resource_stall_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext725_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext725";
   query->symbol_name = "Ext725";
   query->guid = "0511f93b-3bf2-48f7-afc4-9c4783a17d65";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810CF2 },
         { .reg = 0x00009888, .val = 0x0F810D74 },
         { .reg = 0x00009888, .val = 0x11810039 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183AA00 },
         { .reg = 0x00009888, .val = 0x03830002 },
         { .reg = 0x00009888, .val = 0x018401F0 },
         { .reg = 0x00009888, .val = 0x01865500 },
         { .reg = 0x00009888, .val = 0x03860001 },
         { .reg = 0x00009888, .val = 0x01875500 },
         { .reg = 0x00009888, .val = 0x03870001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108AA00 },
         { .reg = 0x00009888, .val = 0x03080002 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x10810C00 },
         { .reg = 0x00009888, .val = 0x12810CB1 },
         { .reg = 0x00009888, .val = 0x14810DF3 },
         { .reg = 0x00009888, .val = 0x16810036 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02832AA8 },
         { .reg = 0x00009888, .val = 0x00847E00 },
         { .reg = 0x00009888, .val = 0x02861554 },
         { .reg = 0x00009888, .val = 0x02871554 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810DB7 },
         { .reg = 0x00009888, .val = 0x0B810CF5 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x010800AA },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030020 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A031061 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext725__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext725__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext725__avg_gpu_core_frequency__max,acmgt3__ext725__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3083, 24, NULL,acmgt3__ext725__task_threadgroup_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5149, 32, NULL,acmgt3__ext725__task_thread_exit_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5150, 40, percentage_max_float,acmgt3__ext725__threadgroup_dispatch_resource_stall_xecore20__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext726_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext726";
   query->symbol_name = "Ext726";
   query->guid = "eca95fe1-d70f-46a0-b997-858695f87ed2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10CF2 },
         { .reg = 0x00009888, .val = 0x0FA10D74 },
         { .reg = 0x00009888, .val = 0x11A10039 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x03A30002 },
         { .reg = 0x00009888, .val = 0x01A401F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x03A60001 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x03A70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108FF00 },
         { .reg = 0x00009888, .val = 0x03080003 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009888, .val = 0x010101F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x030B0001 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x10A10C00 },
         { .reg = 0x00009888, .val = 0x12A10CB1 },
         { .reg = 0x00009888, .val = 0x14A10DF3 },
         { .reg = 0x00009888, .val = 0x16A10036 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32AA8 },
         { .reg = 0x00009888, .val = 0x00A47E00 },
         { .reg = 0x00009888, .val = 0x02A61554 },
         { .reg = 0x00009888, .val = 0x02A71554 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x09A10DB7 },
         { .reg = 0x00009888, .val = 0x0BA10CF5 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A300AA },
         { .reg = 0x00009888, .val = 0x01A4000F },
         { .reg = 0x00009888, .val = 0x01A60055 },
         { .reg = 0x00009888, .val = 0x01A70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x020B1554 },
         { .reg = 0x00009888, .val = 0x010800FF },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009888, .val = 0x0101000F },
         { .reg = 0x00009888, .val = 0x010B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030020 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A031061 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext726__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext726__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext726__avg_gpu_core_frequency__max,acmgt3__ext726__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3084, 24, NULL,acmgt3__ext726__task_threadgroup_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5151, 32, NULL,acmgt3__ext726__task_thread_exit_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5152, 40, percentage_max_float,acmgt3__ext726__threadgroup_dispatch_resource_stall_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext727_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext727";
   query->symbol_name = "Ext727";
   query->guid = "d8a1a2c8-b8bf-40bd-b752-7413f227b6b9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10CF2 },
         { .reg = 0x00009888, .val = 0x0FC10D74 },
         { .reg = 0x00009888, .val = 0x11C10039 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0107AA00 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009888, .val = 0x010201F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x10C10C00 },
         { .reg = 0x00009888, .val = 0x12C10CB1 },
         { .reg = 0x00009888, .val = 0x14C10DF3 },
         { .reg = 0x00009888, .val = 0x16C10036 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA8 },
         { .reg = 0x00009888, .val = 0x00C47E00 },
         { .reg = 0x00009888, .val = 0x02C61554 },
         { .reg = 0x00009888, .val = 0x02C71554 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10DB7 },
         { .reg = 0x00009888, .val = 0x0BC10CF5 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300AA },
         { .reg = 0x00009888, .val = 0x01C4000F },
         { .reg = 0x00009888, .val = 0x01C60055 },
         { .reg = 0x00009888, .val = 0x01C70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02072AA8 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x00027E00 },
         { .reg = 0x00009888, .val = 0x020C1554 },
         { .reg = 0x00009888, .val = 0x010700AA },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009888, .val = 0x0102000F },
         { .reg = 0x00009888, .val = 0x010C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030020 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A031061 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext727__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext727__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext727__avg_gpu_core_frequency__max,acmgt3__ext727__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3085, 24, NULL,acmgt3__ext727__task_threadgroup_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5153, 32, NULL,acmgt3__ext727__task_thread_exit_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5154, 40, percentage_max_float,acmgt3__ext727__threadgroup_dispatch_resource_stall_xecore22__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext728_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext728";
   query->symbol_name = "Ext728";
   query->guid = "8b036b26-9616-4a12-84f7-5a59e54dbd95";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10CF2 },
         { .reg = 0x00009888, .val = 0x0FE10D74 },
         { .reg = 0x00009888, .val = 0x11E10039 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3AA00 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E401F0 },
         { .reg = 0x00009888, .val = 0x01E65500 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E75500 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x01075500 },
         { .reg = 0x00009888, .val = 0x03070001 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x10E10C00 },
         { .reg = 0x00009888, .val = 0x12E10CB1 },
         { .reg = 0x00009888, .val = 0x14E10DF3 },
         { .reg = 0x00009888, .val = 0x16E10036 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E32AA8 },
         { .reg = 0x00009888, .val = 0x00E47E00 },
         { .reg = 0x00009888, .val = 0x02E61554 },
         { .reg = 0x00009888, .val = 0x02E71554 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10DB7 },
         { .reg = 0x00009888, .val = 0x0BE10CF5 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02071554 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x01070055 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00032249 },
         { .reg = 0x00009888, .val = 0x02031492 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030020 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A031061 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext728__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext728__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext728__avg_gpu_core_frequency__max,acmgt3__ext728__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3086, 24, NULL,acmgt3__ext728__task_threadgroup_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5155, 32, NULL,acmgt3__ext728__task_thread_exit_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5156, 40, percentage_max_float,acmgt3__ext728__threadgroup_dispatch_resource_stall_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext729_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext729";
   query->symbol_name = "Ext729";
   query->guid = "627a650a-b847-4f3b-8e74-5cbe7eded518";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810CF2 },
         { .reg = 0x00009888, .val = 0x0E810D74 },
         { .reg = 0x00009888, .val = 0x10810039 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083AA00 },
         { .reg = 0x00009888, .val = 0x02830002 },
         { .reg = 0x00009888, .val = 0x008401F0 },
         { .reg = 0x00009888, .val = 0x00865500 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x00875500 },
         { .reg = 0x00009888, .val = 0x02870001 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x13810CB1 },
         { .reg = 0x00009888, .val = 0x15810DF3 },
         { .reg = 0x00009888, .val = 0x17810036 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03832AA8 },
         { .reg = 0x00009888, .val = 0x01847E00 },
         { .reg = 0x00009888, .val = 0x03861554 },
         { .reg = 0x00009888, .val = 0x03871554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03082AA8 },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810DB7 },
         { .reg = 0x00009888, .val = 0x0A810CF5 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D08 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext729__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext729__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext729__avg_gpu_core_frequency__max,acmgt3__ext729__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5157, 24, NULL,acmgt3__ext729__task_threadgroup_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5158, 32, NULL,acmgt3__ext729__task_thread_exit_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5159, 40, percentage_max_float,acmgt3__ext729__threadgroup_dispatch_resource_stall_xecore24__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext730_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext730";
   query->symbol_name = "Ext730";
   query->guid = "44ca23da-3f5a-4b64-8dd3-5dc743588b63";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10CF2 },
         { .reg = 0x00009888, .val = 0x0EA10D74 },
         { .reg = 0x00009888, .val = 0x10A10039 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x02A30002 },
         { .reg = 0x00009888, .val = 0x00A401F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x02A60001 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x02A70001 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x11A10C00 },
         { .reg = 0x00009888, .val = 0x13A10CB1 },
         { .reg = 0x00009888, .val = 0x15A10DF3 },
         { .reg = 0x00009888, .val = 0x17A10036 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32AA8 },
         { .reg = 0x00009888, .val = 0x01A47E00 },
         { .reg = 0x00009888, .val = 0x03A61554 },
         { .reg = 0x00009888, .val = 0x03A71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x020B2AA9 },
         { .reg = 0x00009888, .val = 0x03083FFC },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009888, .val = 0x01017E00 },
         { .reg = 0x00009888, .val = 0x030B1554 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10DB7 },
         { .reg = 0x00009888, .val = 0x0AA10CF5 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300AA },
         { .reg = 0x00009888, .val = 0x00A4000F },
         { .reg = 0x00009888, .val = 0x00A60055 },
         { .reg = 0x00009888, .val = 0x00A70055 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D08 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext730__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext730__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext730__avg_gpu_core_frequency__max,acmgt3__ext730__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5160, 24, NULL,acmgt3__ext730__task_threadgroup_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5161, 32, NULL,acmgt3__ext730__task_thread_exit_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5162, 40, percentage_max_float,acmgt3__ext730__threadgroup_dispatch_resource_stall_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext731_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext731";
   query->symbol_name = "Ext731";
   query->guid = "c1327b57-650a-46c6-a7a1-50567953b8ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10CF2 },
         { .reg = 0x00009888, .val = 0x0EC10D74 },
         { .reg = 0x00009888, .val = 0x10C10039 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10C00 },
         { .reg = 0x00009888, .val = 0x13C10CB1 },
         { .reg = 0x00009888, .val = 0x15C10DF3 },
         { .reg = 0x00009888, .val = 0x17C10036 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32AA8 },
         { .reg = 0x00009888, .val = 0x01C47E00 },
         { .reg = 0x00009888, .val = 0x03C61554 },
         { .reg = 0x00009888, .val = 0x03C71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0007AA00 },
         { .reg = 0x00009888, .val = 0x02070002 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x000201F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009888, .val = 0x03072AA8 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009888, .val = 0x01027E00 },
         { .reg = 0x00009888, .val = 0x030C1554 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x08C10DB7 },
         { .reg = 0x00009888, .val = 0x0AC10CF5 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C300AA },
         { .reg = 0x00009888, .val = 0x00C4000F },
         { .reg = 0x00009888, .val = 0x00C60055 },
         { .reg = 0x00009888, .val = 0x00C70055 },
         { .reg = 0x00009888, .val = 0x000700AA },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009888, .val = 0x0002000F },
         { .reg = 0x00009888, .val = 0x000C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D08 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext731__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext731__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext731__avg_gpu_core_frequency__max,acmgt3__ext731__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5163, 24, NULL,acmgt3__ext731__task_threadgroup_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5164, 32, NULL,acmgt3__ext731__task_thread_exit_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5165, 40, percentage_max_float,acmgt3__ext731__threadgroup_dispatch_resource_stall_xecore26__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext732_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext732";
   query->symbol_name = "Ext732";
   query->guid = "8029fecc-6327-44c7-8d6a-e793609f2c4d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10CF2 },
         { .reg = 0x00009888, .val = 0x0EE10D74 },
         { .reg = 0x00009888, .val = 0x10E10039 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3AA00 },
         { .reg = 0x00009888, .val = 0x02E30002 },
         { .reg = 0x00009888, .val = 0x00E401F0 },
         { .reg = 0x00009888, .val = 0x00E65500 },
         { .reg = 0x00009888, .val = 0x02E60001 },
         { .reg = 0x00009888, .val = 0x00E75500 },
         { .reg = 0x00009888, .val = 0x02E70001 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10C00 },
         { .reg = 0x00009888, .val = 0x13E10CB1 },
         { .reg = 0x00009888, .val = 0x15E10DF3 },
         { .reg = 0x00009888, .val = 0x17E10036 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E32AA8 },
         { .reg = 0x00009888, .val = 0x01E47E00 },
         { .reg = 0x00009888, .val = 0x03E61554 },
         { .reg = 0x00009888, .val = 0x03E71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x00075500 },
         { .reg = 0x00009888, .val = 0x02070001 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03071554 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10DB7 },
         { .reg = 0x00009888, .val = 0x0AE10CF5 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x00070055 },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030008 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032100 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D08 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext732__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext732__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext732__avg_gpu_core_frequency__max,acmgt3__ext732__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5166, 24, NULL,acmgt3__ext732__task_threadgroup_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5167, 32, NULL,acmgt3__ext732__task_thread_exit_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5168, 40, percentage_max_float,acmgt3__ext732__threadgroup_dispatch_resource_stall_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext733_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext733";
   query->symbol_name = "Ext733";
   query->guid = "6743fa5a-d2cc-4434-84bb-98ff69765e2e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810CF2 },
         { .reg = 0x00009888, .val = 0x0F810D74 },
         { .reg = 0x00009888, .val = 0x11810039 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183AA00 },
         { .reg = 0x00009888, .val = 0x03830002 },
         { .reg = 0x00009888, .val = 0x018401F0 },
         { .reg = 0x00009888, .val = 0x01865500 },
         { .reg = 0x00009888, .val = 0x03860001 },
         { .reg = 0x00009888, .val = 0x01875500 },
         { .reg = 0x00009888, .val = 0x03870001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108AA00 },
         { .reg = 0x00009888, .val = 0x03080002 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x10810C00 },
         { .reg = 0x00009888, .val = 0x12810CB1 },
         { .reg = 0x00009888, .val = 0x14810DF3 },
         { .reg = 0x00009888, .val = 0x16810036 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02832AA8 },
         { .reg = 0x00009888, .val = 0x00847E00 },
         { .reg = 0x00009888, .val = 0x02861554 },
         { .reg = 0x00009888, .val = 0x02871554 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810DB7 },
         { .reg = 0x00009888, .val = 0x0B810CF5 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x010800AA },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x02022AA9 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext733__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext733__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext733__avg_gpu_core_frequency__max,acmgt3__ext733__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5169, 24, NULL,acmgt3__ext733__task_threadgroup_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5170, 32, NULL,acmgt3__ext733__task_thread_exit_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5171, 40, percentage_max_float,acmgt3__ext733__threadgroup_dispatch_resource_stall_xecore28__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext734_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext734";
   query->symbol_name = "Ext734";
   query->guid = "993468bb-355c-44f1-90e2-1aeeff3d2b4e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10CF2 },
         { .reg = 0x00009888, .val = 0x0FA10D74 },
         { .reg = 0x00009888, .val = 0x11A10039 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x03A30002 },
         { .reg = 0x00009888, .val = 0x01A401F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x03A60001 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x03A70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108FF00 },
         { .reg = 0x00009888, .val = 0x03080003 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009888, .val = 0x010101F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x030B0001 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x10A10C00 },
         { .reg = 0x00009888, .val = 0x12A10CB1 },
         { .reg = 0x00009888, .val = 0x14A10DF3 },
         { .reg = 0x00009888, .val = 0x16A10036 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32AA8 },
         { .reg = 0x00009888, .val = 0x00A47E00 },
         { .reg = 0x00009888, .val = 0x02A61554 },
         { .reg = 0x00009888, .val = 0x02A71554 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x09A10DB7 },
         { .reg = 0x00009888, .val = 0x0BA10CF5 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A300AA },
         { .reg = 0x00009888, .val = 0x01A4000F },
         { .reg = 0x00009888, .val = 0x01A60055 },
         { .reg = 0x00009888, .val = 0x01A70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x020B1554 },
         { .reg = 0x00009888, .val = 0x010800FF },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009888, .val = 0x0101000F },
         { .reg = 0x00009888, .val = 0x010B0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x02022AA9 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext734__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext734__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext734__avg_gpu_core_frequency__max,acmgt3__ext734__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5172, 24, NULL,acmgt3__ext734__task_threadgroup_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5173, 32, NULL,acmgt3__ext734__task_thread_exit_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5174, 40, percentage_max_float,acmgt3__ext734__threadgroup_dispatch_resource_stall_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext735_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext735";
   query->symbol_name = "Ext735";
   query->guid = "3fffa1b9-22e8-49f0-9f52-6f393fe33471";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10CF2 },
         { .reg = 0x00009888, .val = 0x0FC10D74 },
         { .reg = 0x00009888, .val = 0x11C10039 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0107AA00 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009888, .val = 0x010201F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x10C10C00 },
         { .reg = 0x00009888, .val = 0x12C10CB1 },
         { .reg = 0x00009888, .val = 0x14C10DF3 },
         { .reg = 0x00009888, .val = 0x16C10036 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA8 },
         { .reg = 0x00009888, .val = 0x00C47E00 },
         { .reg = 0x00009888, .val = 0x02C61554 },
         { .reg = 0x00009888, .val = 0x02C71554 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10DB7 },
         { .reg = 0x00009888, .val = 0x0BC10CF5 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300AA },
         { .reg = 0x00009888, .val = 0x01C4000F },
         { .reg = 0x00009888, .val = 0x01C60055 },
         { .reg = 0x00009888, .val = 0x01C70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02072AA8 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x00027E00 },
         { .reg = 0x00009888, .val = 0x020C1554 },
         { .reg = 0x00009888, .val = 0x010700AA },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009888, .val = 0x0102000F },
         { .reg = 0x00009888, .val = 0x010C0055 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x02022AA9 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext735__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext735__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext735__avg_gpu_core_frequency__max,acmgt3__ext735__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5175, 24, NULL,acmgt3__ext735__task_threadgroup_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5176, 32, NULL,acmgt3__ext735__task_thread_exit_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5177, 40, percentage_max_float,acmgt3__ext735__threadgroup_dispatch_resource_stall_xecore30__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext736_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext736";
   query->symbol_name = "Ext736";
   query->guid = "3a9252e0-711a-4c7d-9103-d67ccba0a84c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10CF2 },
         { .reg = 0x00009888, .val = 0x0FE10D74 },
         { .reg = 0x00009888, .val = 0x11E10039 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3AA00 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E401F0 },
         { .reg = 0x00009888, .val = 0x01E65500 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E75500 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x01075500 },
         { .reg = 0x00009888, .val = 0x03070001 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x10E10C00 },
         { .reg = 0x00009888, .val = 0x12E10CB1 },
         { .reg = 0x00009888, .val = 0x14E10DF3 },
         { .reg = 0x00009888, .val = 0x16E10036 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E32AA8 },
         { .reg = 0x00009888, .val = 0x00E47E00 },
         { .reg = 0x00009888, .val = 0x02E61554 },
         { .reg = 0x00009888, .val = 0x02E71554 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10DB7 },
         { .reg = 0x00009888, .val = 0x0BE10CF5 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02071554 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x01070055 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000255AA },
         { .reg = 0x00009888, .val = 0x02022AA9 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032100 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031060 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032108 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext736__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext736__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext736__avg_gpu_core_frequency__max,acmgt3__ext736__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5178, 24, NULL,acmgt3__ext736__task_threadgroup_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5179, 32, NULL,acmgt3__ext736__task_thread_exit_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5180, 40, percentage_max_float,acmgt3__ext736__threadgroup_dispatch_resource_stall_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext737_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext737";
   query->symbol_name = "Ext737";
   query->guid = "7a784b26-20ec-45bd-9e65-cb91454a0529";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810DB7 },
         { .reg = 0x00009888, .val = 0x0A810CF5 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008300AA },
         { .reg = 0x00009888, .val = 0x0084000F },
         { .reg = 0x00009888, .val = 0x00860055 },
         { .reg = 0x00009888, .val = 0x00870055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2C812800 },
         { .reg = 0x00009888, .val = 0x2E81001E },
         { .reg = 0x00009888, .val = 0x2D813000 },
         { .reg = 0x00009888, .val = 0x06819800 },
         { .reg = 0x00009888, .val = 0x0C810CF2 },
         { .reg = 0x00009888, .val = 0x0E810D74 },
         { .reg = 0x00009888, .val = 0x10810039 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083AA00 },
         { .reg = 0x00009888, .val = 0x02830002 },
         { .reg = 0x00009888, .val = 0x008401F0 },
         { .reg = 0x00009888, .val = 0x00865500 },
         { .reg = 0x00009888, .val = 0x02860001 },
         { .reg = 0x00009888, .val = 0x00875500 },
         { .reg = 0x00009888, .val = 0x02870001 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x11810C00 },
         { .reg = 0x00009888, .val = 0x13810CB1 },
         { .reg = 0x00009888, .val = 0x15810DF3 },
         { .reg = 0x00009888, .val = 0x17810036 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03832AA8 },
         { .reg = 0x00009888, .val = 0x01847E00 },
         { .reg = 0x00009888, .val = 0x03861554 },
         { .reg = 0x00009888, .val = 0x03871554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02083FFE },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03082AA8 },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030009 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032520 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D09 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext737__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext737__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext737__avg_gpu_core_frequency__max,acmgt3__ext737__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5181, 24, NULL,acmgt3__ext737__task_threadgroup_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5182, 32, NULL,acmgt3__ext737__task_thread_exit_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1339, 40, percentage_max_float,acmgt3__ext737__threadgroup_dispatch_resource_stall_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext738_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext738";
   query->symbol_name = "Ext738";
   query->guid = "2012b848-bd30-4c0e-8c20-b76c9be7411d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10DB7 },
         { .reg = 0x00009888, .val = 0x0AA10CF5 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300AA },
         { .reg = 0x00009888, .val = 0x00A4000F },
         { .reg = 0x00009888, .val = 0x00A60055 },
         { .reg = 0x00009888, .val = 0x00A70055 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B0055 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CA12800 },
         { .reg = 0x00009888, .val = 0x2EA1001E },
         { .reg = 0x00009888, .val = 0x2DA13000 },
         { .reg = 0x00009888, .val = 0x06A19800 },
         { .reg = 0x00009888, .val = 0x0CA10CF2 },
         { .reg = 0x00009888, .val = 0x0EA10D74 },
         { .reg = 0x00009888, .val = 0x10A10039 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3AA00 },
         { .reg = 0x00009888, .val = 0x02A30002 },
         { .reg = 0x00009888, .val = 0x00A401F0 },
         { .reg = 0x00009888, .val = 0x00A65500 },
         { .reg = 0x00009888, .val = 0x02A60001 },
         { .reg = 0x00009888, .val = 0x00A75500 },
         { .reg = 0x00009888, .val = 0x02A70001 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x11A10C00 },
         { .reg = 0x00009888, .val = 0x13A10CB1 },
         { .reg = 0x00009888, .val = 0x15A10DF3 },
         { .reg = 0x00009888, .val = 0x17A10036 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32AA8 },
         { .reg = 0x00009888, .val = 0x01A47E00 },
         { .reg = 0x00009888, .val = 0x03A61554 },
         { .reg = 0x00009888, .val = 0x03A71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x000B5500 },
         { .reg = 0x00009888, .val = 0x020B2AA9 },
         { .reg = 0x00009888, .val = 0x03083FFC },
         { .reg = 0x00009888, .val = 0x030A1554 },
         { .reg = 0x00009888, .val = 0x01017E00 },
         { .reg = 0x00009888, .val = 0x030B1554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030009 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032520 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D09 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext738__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext738__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext738__avg_gpu_core_frequency__max,acmgt3__ext738__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5183, 24, NULL,acmgt3__ext738__task_threadgroup_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5184, 32, NULL,acmgt3__ext738__task_thread_exit_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1340, 40, percentage_max_float,acmgt3__ext738__threadgroup_dispatch_resource_stall_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext739_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext739";
   query->symbol_name = "Ext739";
   query->guid = "c66cdb98-dfcf-4493-97e9-4c779e039ece";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x08C10DB7 },
         { .reg = 0x00009888, .val = 0x0AC10CF5 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C300AA },
         { .reg = 0x00009888, .val = 0x00C4000F },
         { .reg = 0x00009888, .val = 0x00C60055 },
         { .reg = 0x00009888, .val = 0x00C70055 },
         { .reg = 0x00009888, .val = 0x000700AA },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009888, .val = 0x0002000F },
         { .reg = 0x00009888, .val = 0x000C0055 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CC12800 },
         { .reg = 0x00009888, .val = 0x2EC1001E },
         { .reg = 0x00009888, .val = 0x2DC13000 },
         { .reg = 0x00009888, .val = 0x06C19800 },
         { .reg = 0x00009888, .val = 0x0CC10CF2 },
         { .reg = 0x00009888, .val = 0x0EC10D74 },
         { .reg = 0x00009888, .val = 0x10C10039 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75500 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10C00 },
         { .reg = 0x00009888, .val = 0x13C10CB1 },
         { .reg = 0x00009888, .val = 0x15C10DF3 },
         { .reg = 0x00009888, .val = 0x17C10036 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32AA8 },
         { .reg = 0x00009888, .val = 0x01C47E00 },
         { .reg = 0x00009888, .val = 0x03C61554 },
         { .reg = 0x00009888, .val = 0x03C71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x0007AA00 },
         { .reg = 0x00009888, .val = 0x02070002 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x000201F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009888, .val = 0x03072AA8 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009888, .val = 0x01027E00 },
         { .reg = 0x00009888, .val = 0x030C1554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030009 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032520 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D09 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext739__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext739__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext739__avg_gpu_core_frequency__max,acmgt3__ext739__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5185, 24, NULL,acmgt3__ext739__task_threadgroup_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5186, 32, NULL,acmgt3__ext739__task_thread_exit_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1341, 40, percentage_max_float,acmgt3__ext739__threadgroup_dispatch_resource_stall_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext740_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext740";
   query->symbol_name = "Ext740";
   query->guid = "d38b4fa2-475c-44de-afc2-53bed3d44761";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10DB7 },
         { .reg = 0x00009888, .val = 0x0AE10CF5 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x00E70055 },
         { .reg = 0x00009888, .val = 0x00070055 },
         { .reg = 0x00009888, .val = 0x0009000F },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CE12800 },
         { .reg = 0x00009888, .val = 0x2EE1001E },
         { .reg = 0x00009888, .val = 0x2DE13000 },
         { .reg = 0x00009888, .val = 0x06E19800 },
         { .reg = 0x00009888, .val = 0x0CE10CF2 },
         { .reg = 0x00009888, .val = 0x0EE10D74 },
         { .reg = 0x00009888, .val = 0x10E10039 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3AA00 },
         { .reg = 0x00009888, .val = 0x02E30002 },
         { .reg = 0x00009888, .val = 0x00E401F0 },
         { .reg = 0x00009888, .val = 0x00E65500 },
         { .reg = 0x00009888, .val = 0x02E60001 },
         { .reg = 0x00009888, .val = 0x00E75500 },
         { .reg = 0x00009888, .val = 0x02E70001 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10C00 },
         { .reg = 0x00009888, .val = 0x13E10CB1 },
         { .reg = 0x00009888, .val = 0x15E10DF3 },
         { .reg = 0x00009888, .val = 0x17E10036 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E32AA8 },
         { .reg = 0x00009888, .val = 0x01E47E00 },
         { .reg = 0x00009888, .val = 0x03E61554 },
         { .reg = 0x00009888, .val = 0x03E71554 },
         { .reg = 0x00009888, .val = 0x00037E00 },
         { .reg = 0x00009888, .val = 0x00075500 },
         { .reg = 0x00009888, .val = 0x02070001 },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000901F0 },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020A1556 },
         { .reg = 0x00009888, .val = 0x00017E00 },
         { .reg = 0x00009888, .val = 0x020B2AA8 },
         { .reg = 0x00009888, .val = 0x03071554 },
         { .reg = 0x00009888, .val = 0x01097E00 },
         { .reg = 0x00009888, .val = 0x030A2AA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x3E030009 },
         { .reg = 0x00009888, .val = 0x26033000 },
         { .reg = 0x00009888, .val = 0x42032520 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32033000 },
         { .reg = 0x00009888, .val = 0x44030D09 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46031068 },
         { .reg = 0x00009888, .val = 0x48030683 },
         { .reg = 0x00009888, .val = 0x4A030008 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017FF0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext740__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext740__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext740__avg_gpu_core_frequency__max,acmgt3__ext740__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5187, 24, NULL,acmgt3__ext740__task_threadgroup_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5188, 32, NULL,acmgt3__ext740__task_thread_exit_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1342, 40, percentage_max_float,acmgt3__ext740__threadgroup_dispatch_resource_stall_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext741_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext741";
   query->symbol_name = "Ext741";
   query->guid = "b11e2740-3d43-422c-8593-3739b66cdee5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C813000 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x10810C00 },
         { .reg = 0x00009888, .val = 0x12810CB1 },
         { .reg = 0x00009888, .val = 0x14810DF3 },
         { .reg = 0x00009888, .val = 0x16810036 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02832AA8 },
         { .reg = 0x00009888, .val = 0x00847E00 },
         { .reg = 0x00009888, .val = 0x02861554 },
         { .reg = 0x00009888, .val = 0x02871554 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810DB7 },
         { .reg = 0x00009888, .val = 0x0B810CF5 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018300AA },
         { .reg = 0x00009888, .val = 0x0184000F },
         { .reg = 0x00009888, .val = 0x01860055 },
         { .reg = 0x00009888, .val = 0x01870055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x010800AA },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2D812800 },
         { .reg = 0x00009888, .val = 0x2F81001E },
         { .reg = 0x00009888, .val = 0x07819800 },
         { .reg = 0x00009888, .val = 0x0D810CF2 },
         { .reg = 0x00009888, .val = 0x0F810D74 },
         { .reg = 0x00009888, .val = 0x11810039 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183AA00 },
         { .reg = 0x00009888, .val = 0x03830002 },
         { .reg = 0x00009888, .val = 0x018401F0 },
         { .reg = 0x00009888, .val = 0x01865500 },
         { .reg = 0x00009888, .val = 0x03860001 },
         { .reg = 0x00009888, .val = 0x01875500 },
         { .reg = 0x00009888, .val = 0x03870001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108AA00 },
         { .reg = 0x00009888, .val = 0x03080002 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x02020002 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032521 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030001 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031260 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032529 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext741__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext741__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext741__avg_gpu_core_frequency__max,acmgt3__ext741__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5189, 24, NULL,acmgt3__ext741__task_threadgroup_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1260, 32, NULL,acmgt3__ext741__task_thread_exit_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1343, 40, percentage_max_float,acmgt3__ext741__threadgroup_dispatch_resource_stall_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext742_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext742";
   query->symbol_name = "Ext742";
   query->guid = "3530dd8c-3c07-4b30-bb10-94efd308113e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CA13000 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x10A10C00 },
         { .reg = 0x00009888, .val = 0x12A10CB1 },
         { .reg = 0x00009888, .val = 0x14A10DF3 },
         { .reg = 0x00009888, .val = 0x16A10036 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32AA8 },
         { .reg = 0x00009888, .val = 0x00A47E00 },
         { .reg = 0x00009888, .val = 0x02A61554 },
         { .reg = 0x00009888, .val = 0x02A71554 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x09A10DB7 },
         { .reg = 0x00009888, .val = 0x0BA10CF5 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A300AA },
         { .reg = 0x00009888, .val = 0x01A4000F },
         { .reg = 0x00009888, .val = 0x01A60055 },
         { .reg = 0x00009888, .val = 0x01A70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x02083FFC },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A1554 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x020B1554 },
         { .reg = 0x00009888, .val = 0x010800FF },
         { .reg = 0x00009888, .val = 0x010A0055 },
         { .reg = 0x00009888, .val = 0x0101000F },
         { .reg = 0x00009888, .val = 0x010B0055 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2DA12800 },
         { .reg = 0x00009888, .val = 0x2FA1001E },
         { .reg = 0x00009888, .val = 0x07A19800 },
         { .reg = 0x00009888, .val = 0x0DA10CF2 },
         { .reg = 0x00009888, .val = 0x0FA10D74 },
         { .reg = 0x00009888, .val = 0x11A10039 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3AA00 },
         { .reg = 0x00009888, .val = 0x03A30002 },
         { .reg = 0x00009888, .val = 0x01A401F0 },
         { .reg = 0x00009888, .val = 0x01A65500 },
         { .reg = 0x00009888, .val = 0x03A60001 },
         { .reg = 0x00009888, .val = 0x01A75500 },
         { .reg = 0x00009888, .val = 0x03A70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0108FF00 },
         { .reg = 0x00009888, .val = 0x03080003 },
         { .reg = 0x00009888, .val = 0x010A5500 },
         { .reg = 0x00009888, .val = 0x030A0001 },
         { .reg = 0x00009888, .val = 0x010101F0 },
         { .reg = 0x00009888, .val = 0x010B5500 },
         { .reg = 0x00009888, .val = 0x030B0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x02020002 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032521 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030001 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031260 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032529 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext742__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext742__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext742__avg_gpu_core_frequency__max,acmgt3__ext742__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5190, 24, NULL,acmgt3__ext742__task_threadgroup_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1266, 32, NULL,acmgt3__ext742__task_thread_exit_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1344, 40, percentage_max_float,acmgt3__ext742__threadgroup_dispatch_resource_stall_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext743_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext743";
   query->symbol_name = "Ext743";
   query->guid = "fec76475-ec48-42b1-b794-8fca6c8d3f68";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CC13000 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x10C10C00 },
         { .reg = 0x00009888, .val = 0x12C10CB1 },
         { .reg = 0x00009888, .val = 0x14C10DF3 },
         { .reg = 0x00009888, .val = 0x16C10036 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA8 },
         { .reg = 0x00009888, .val = 0x00C47E00 },
         { .reg = 0x00009888, .val = 0x02C61554 },
         { .reg = 0x00009888, .val = 0x02C71554 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10DB7 },
         { .reg = 0x00009888, .val = 0x0BC10CF5 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C300AA },
         { .reg = 0x00009888, .val = 0x01C4000F },
         { .reg = 0x00009888, .val = 0x01C60055 },
         { .reg = 0x00009888, .val = 0x01C70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02072AA8 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x00027E00 },
         { .reg = 0x00009888, .val = 0x020C1554 },
         { .reg = 0x00009888, .val = 0x010700AA },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009888, .val = 0x0102000F },
         { .reg = 0x00009888, .val = 0x010C0055 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2DC12800 },
         { .reg = 0x00009888, .val = 0x2FC1001E },
         { .reg = 0x00009888, .val = 0x07C19800 },
         { .reg = 0x00009888, .val = 0x0DC10CF2 },
         { .reg = 0x00009888, .val = 0x0FC10D74 },
         { .reg = 0x00009888, .val = 0x11C10039 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75500 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0107AA00 },
         { .reg = 0x00009888, .val = 0x03070002 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009888, .val = 0x010201F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x02020002 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032521 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030001 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031260 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032529 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext743__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext743__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext743__avg_gpu_core_frequency__max,acmgt3__ext743__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5191, 24, NULL,acmgt3__ext743__task_threadgroup_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1272, 32, NULL,acmgt3__ext743__task_thread_exit_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1345, 40, percentage_max_float,acmgt3__ext743__threadgroup_dispatch_resource_stall_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext744_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext744";
   query->symbol_name = "Ext744";
   query->guid = "8b8d31ad-8dd7-492a-9339-3f735afeb52d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CE13000 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x10E10C00 },
         { .reg = 0x00009888, .val = 0x12E10CB1 },
         { .reg = 0x00009888, .val = 0x14E10DF3 },
         { .reg = 0x00009888, .val = 0x16E10036 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E32AA8 },
         { .reg = 0x00009888, .val = 0x00E47E00 },
         { .reg = 0x00009888, .val = 0x02E61554 },
         { .reg = 0x00009888, .val = 0x02E71554 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10DB7 },
         { .reg = 0x00009888, .val = 0x0BE10CF5 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x01E70055 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x02071554 },
         { .reg = 0x00009888, .val = 0x000800FF },
         { .reg = 0x00009888, .val = 0x00097E00 },
         { .reg = 0x00009888, .val = 0x000A0055 },
         { .reg = 0x00009888, .val = 0x020A2AA8 },
         { .reg = 0x00009888, .val = 0x0001000F },
         { .reg = 0x00009888, .val = 0x000B00AA },
         { .reg = 0x00009888, .val = 0x01070055 },
         { .reg = 0x00009888, .val = 0x0109000F },
         { .reg = 0x00009888, .val = 0x010A00AA },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2DE12800 },
         { .reg = 0x00009888, .val = 0x2FE1001E },
         { .reg = 0x00009888, .val = 0x07E19800 },
         { .reg = 0x00009888, .val = 0x0DE10CF2 },
         { .reg = 0x00009888, .val = 0x0FE10D74 },
         { .reg = 0x00009888, .val = 0x11E10039 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3AA00 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E401F0 },
         { .reg = 0x00009888, .val = 0x01E65500 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E75500 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x000301F0 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009888, .val = 0x000A5500 },
         { .reg = 0x00009888, .val = 0x020A0001 },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x000BAA00 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x01075500 },
         { .reg = 0x00009888, .val = 0x03070001 },
         { .reg = 0x00009888, .val = 0x010901F0 },
         { .reg = 0x00009888, .val = 0x010AAA00 },
         { .reg = 0x00009888, .val = 0x030A0002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x02020002 },
         { .reg = 0x00009888, .val = 0x00031492 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032521 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030001 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031260 },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40032529 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017E0F },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02021554 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02041554 },
         { .reg = 0x00009888, .val = 0x00050055 },
         { .reg = 0x00009888, .val = 0x02051554 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x02082AA8 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000101F0 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02020001 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x00055500 },
         { .reg = 0x00009888, .val = 0x02050001 },
         { .reg = 0x00009888, .val = 0x0008AA00 },
         { .reg = 0x00009888, .val = 0x02080002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000882 },
         { .reg = 0x0000D94C, .val = 0x0000FE0F },
         { .reg = 0x0000D950, .val = 0x00011002 },
         { .reg = 0x0000D954, .val = 0x000081FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext744__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext744__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext744__avg_gpu_core_frequency__max,acmgt3__ext744__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5192, 24, NULL,acmgt3__ext744__task_threadgroup_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1278, 32, NULL,acmgt3__ext744__task_thread_exit_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1346, 40, percentage_max_float,acmgt3__ext744__threadgroup_dispatch_resource_stall_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext745_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext745";
   query->symbol_name = "Ext745";
   query->guid = "4273606f-d838-4bcd-a192-87ec29f55cb2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x16810C00 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x16A10030 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x14C10C00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x14E10030 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10030 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10C00 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10030 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x0E810C00 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0EA10030 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x0CC10C00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x0CE10030 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x0B810C00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0BA10030 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10C00 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10030 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext745__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext745__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext745__avg_gpu_core_frequency__max,acmgt3__ext745__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1299, 24, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1300, 28, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1301, 32, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1302, 36, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1303, 40, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1304, 44, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1305, 48, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1306, 52, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3087, 56, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3088, 60, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3089, 64, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3090, 68, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3091, 72, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3092, 76, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3093, 80, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3094, 84, percentage_max_float,acmgt3__ext745__threadgroup_dispatch_queue0_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext746_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext746";
   query->symbol_name = "Ext746";
   query->guid = "e0518ba4-65e7-4855-83dd-81d0a77f939b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x16810C00 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x16A10030 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x14C10C00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x14E10030 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10030 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10C00 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10030 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2C817800 },
         { .reg = 0x00009888, .val = 0x2CA17800 },
         { .reg = 0x00009888, .val = 0x2CC17800 },
         { .reg = 0x00009888, .val = 0x2CE17800 },
         { .reg = 0x00009888, .val = 0x2D817800 },
         { .reg = 0x00009888, .val = 0x2DA17800 },
         { .reg = 0x00009888, .val = 0x2DC17800 },
         { .reg = 0x00009888, .val = 0x2DE17800 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x0E810C00 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0EA10030 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x0CC10C00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x0CE10030 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x0B810C00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0BA10030 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10C00 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10030 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext746__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext746__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext746__avg_gpu_core_frequency__max,acmgt3__ext746__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5193, 24, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5194, 28, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5195, 32, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5196, 36, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5197, 40, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5198, 44, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5199, 48, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5200, 52, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5201, 56, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5202, 60, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5203, 64, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5204, 68, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5205, 72, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5206, 76, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5207, 80, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5208, 84, percentage_max_float,acmgt3__ext746__threadgroup_dispatch_queue0_input_available_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext747_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext747";
   query->symbol_name = "Ext747";
   query->guid = "bde1c4bb-6237-4038-becf-218c1c17d872";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C817400 },
         { .reg = 0x00009888, .val = 0x2CA17400 },
         { .reg = 0x00009888, .val = 0x2CC17400 },
         { .reg = 0x00009888, .val = 0x2CE17400 },
         { .reg = 0x00009888, .val = 0x2D817400 },
         { .reg = 0x00009888, .val = 0x2DA17400 },
         { .reg = 0x00009888, .val = 0x2DC17400 },
         { .reg = 0x00009888, .val = 0x2DE17400 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x16810DC0 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x16A10037 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x14C10DC0 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x14E10037 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810DC0 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10037 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10DC0 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10037 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C817400 },
         { .reg = 0x00009888, .val = 0x2CA17400 },
         { .reg = 0x00009888, .val = 0x2CC17400 },
         { .reg = 0x00009888, .val = 0x2CE17400 },
         { .reg = 0x00009888, .val = 0x2D817400 },
         { .reg = 0x00009888, .val = 0x2DA17400 },
         { .reg = 0x00009888, .val = 0x2DC17400 },
         { .reg = 0x00009888, .val = 0x2DE17400 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x0E810DC0 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0EA10037 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x0CC10DC0 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x0CE10037 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x0B810DC0 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0BA10037 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10DC0 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10037 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext747__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext747__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext747__avg_gpu_core_frequency__max,acmgt3__ext747__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1307, 24, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1308, 28, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1309, 32, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1310, 36, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1311, 40, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1312, 44, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1313, 48, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1314, 52, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3095, 56, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3096, 60, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3097, 64, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3098, 68, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3099, 72, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3100, 76, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3101, 80, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3102, 84, percentage_max_float,acmgt3__ext747__threadgroup_dispatch_queue1_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext748_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext748";
   query->symbol_name = "Ext748";
   query->guid = "331329d1-35f6-421d-9bdb-528bb0e20659";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C817400 },
         { .reg = 0x00009888, .val = 0x2CA17400 },
         { .reg = 0x00009888, .val = 0x2CC17400 },
         { .reg = 0x00009888, .val = 0x2CE17400 },
         { .reg = 0x00009888, .val = 0x2D817400 },
         { .reg = 0x00009888, .val = 0x2DA17400 },
         { .reg = 0x00009888, .val = 0x2DC17400 },
         { .reg = 0x00009888, .val = 0x2DE17400 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x16810DC0 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x16A10037 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x14C10DC0 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x14E10037 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810DC0 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10037 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x11C10DC0 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x11E10037 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2C817400 },
         { .reg = 0x00009888, .val = 0x2CA17400 },
         { .reg = 0x00009888, .val = 0x2CC17400 },
         { .reg = 0x00009888, .val = 0x2CE17400 },
         { .reg = 0x00009888, .val = 0x2D817400 },
         { .reg = 0x00009888, .val = 0x2DA17400 },
         { .reg = 0x00009888, .val = 0x2DC17400 },
         { .reg = 0x00009888, .val = 0x2DE17400 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x0E810DC0 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0EA10037 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x0CC10DC0 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x0CE10037 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x0B810DC0 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0BA10037 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10DC0 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10037 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext748__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext748__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext748__avg_gpu_core_frequency__max,acmgt3__ext748__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5209, 24, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5210, 28, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5211, 32, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5212, 36, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5213, 40, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5214, 44, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5215, 48, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5216, 52, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5217, 56, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5218, 60, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5219, 64, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5220, 68, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5221, 72, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5222, 76, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5223, 80, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5224, 84, percentage_max_float,acmgt3__ext748__threadgroup_dispatch_queue1_input_available_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext749_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext749";
   query->symbol_name = "Ext749";
   query->guid = "c4cb0cd8-a65d-44f7-b06d-f94cd7c99eb7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2A810002 },
         { .reg = 0x00009888, .val = 0x2AA10002 },
         { .reg = 0x00009888, .val = 0x2AC10002 },
         { .reg = 0x00009888, .val = 0x2AE10002 },
         { .reg = 0x00009888, .val = 0x2B810002 },
         { .reg = 0x00009888, .val = 0x2BA10002 },
         { .reg = 0x00009888, .val = 0x2BC10002 },
         { .reg = 0x00009888, .val = 0x2BE10002 },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810034 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10D00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10034 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10D00 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810034 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10D00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10034 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10D00 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext749__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext749__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext749__avg_gpu_core_frequency__max,acmgt3__ext749__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1323, 24, percentage_max_float,acmgt3__ext749__thread_dispatch_queue0_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1324, 28, percentage_max_float,acmgt3__ext749__thread_dispatch_queue0_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1325, 32, percentage_max_float,acmgt3__ext749__thread_dispatch_queue0_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1326, 36, percentage_max_float,acmgt3__ext749__thread_dispatch_queue0_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1327, 40, percentage_max_float,acmgt3__ext749__thread_dispatch_queue0_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1328, 44, percentage_max_float,acmgt3__ext749__thread_dispatch_queue0_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1329, 48, percentage_max_float,acmgt3__ext749__thread_dispatch_queue0_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1330, 52, percentage_max_float,acmgt3__ext749__thread_dispatch_queue0_active_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext750_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext750";
   query->symbol_name = "Ext750";
   query->guid = "2d70235d-0d5a-4aa5-8af5-e027f2a3eb6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2A810002 },
         { .reg = 0x00009888, .val = 0x2AA10002 },
         { .reg = 0x00009888, .val = 0x2AC10002 },
         { .reg = 0x00009888, .val = 0x2AE10002 },
         { .reg = 0x00009888, .val = 0x2B810002 },
         { .reg = 0x00009888, .val = 0x2BA10002 },
         { .reg = 0x00009888, .val = 0x2BC10002 },
         { .reg = 0x00009888, .val = 0x2BE10002 },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810034 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10D00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10034 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10D00 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810034 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10D00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10034 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10D00 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext750__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext750__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext750__avg_gpu_core_frequency__max,acmgt3__ext750__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3103, 24, percentage_max_float,acmgt3__ext750__thread_dispatch_queue0_active_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3104, 28, percentage_max_float,acmgt3__ext750__thread_dispatch_queue0_active_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3105, 32, percentage_max_float,acmgt3__ext750__thread_dispatch_queue0_active_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3106, 36, percentage_max_float,acmgt3__ext750__thread_dispatch_queue0_active_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3107, 40, percentage_max_float,acmgt3__ext750__thread_dispatch_queue0_active_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3108, 44, percentage_max_float,acmgt3__ext750__thread_dispatch_queue0_active_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3109, 48, percentage_max_float,acmgt3__ext750__thread_dispatch_queue0_active_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3110, 52, percentage_max_float,acmgt3__ext750__thread_dispatch_queue0_active_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext751_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext751";
   query->symbol_name = "Ext751";
   query->guid = "5673e7be-0e2f-4ef4-882d-7c8c10026603";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2A810002 },
         { .reg = 0x00009888, .val = 0x2AA10002 },
         { .reg = 0x00009888, .val = 0x2AC10002 },
         { .reg = 0x00009888, .val = 0x2AE10002 },
         { .reg = 0x00009888, .val = 0x2B810002 },
         { .reg = 0x00009888, .val = 0x2BA10002 },
         { .reg = 0x00009888, .val = 0x2BC10002 },
         { .reg = 0x00009888, .val = 0x2BE10002 },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810034 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10D00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10034 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10D00 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810034 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10D00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10034 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10D00 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext751__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext751__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext751__avg_gpu_core_frequency__max,acmgt3__ext751__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5225, 24, percentage_max_float,acmgt3__ext751__thread_dispatch_queue0_active_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5226, 28, percentage_max_float,acmgt3__ext751__thread_dispatch_queue0_active_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5227, 32, percentage_max_float,acmgt3__ext751__thread_dispatch_queue0_active_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5228, 36, percentage_max_float,acmgt3__ext751__thread_dispatch_queue0_active_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5229, 40, percentage_max_float,acmgt3__ext751__thread_dispatch_queue0_active_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5230, 44, percentage_max_float,acmgt3__ext751__thread_dispatch_queue0_active_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5231, 48, percentage_max_float,acmgt3__ext751__thread_dispatch_queue0_active_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5232, 52, percentage_max_float,acmgt3__ext751__thread_dispatch_queue0_active_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext752_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext752";
   query->symbol_name = "Ext752";
   query->guid = "c95a1628-c0a7-4cd5-98ca-212a6eeb480d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2A810002 },
         { .reg = 0x00009888, .val = 0x2AA10002 },
         { .reg = 0x00009888, .val = 0x2AC10002 },
         { .reg = 0x00009888, .val = 0x2AE10002 },
         { .reg = 0x00009888, .val = 0x2B810002 },
         { .reg = 0x00009888, .val = 0x2BA10002 },
         { .reg = 0x00009888, .val = 0x2BC10002 },
         { .reg = 0x00009888, .val = 0x2BE10002 },
         { .reg = 0x00009888, .val = 0x06810300 },
         { .reg = 0x00009888, .val = 0x08810034 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x00840001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x06A10300 },
         { .reg = 0x00009888, .val = 0x08A10D00 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x00A40002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x06C10300 },
         { .reg = 0x00009888, .val = 0x0AC10034 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x00C40004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x06E10300 },
         { .reg = 0x00009888, .val = 0x0AE10D00 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x00E40008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x07810300 },
         { .reg = 0x00009888, .val = 0x0D810034 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x01840010 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x07A10300 },
         { .reg = 0x00009888, .val = 0x0DA10D00 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x01A40020 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x07C10300 },
         { .reg = 0x00009888, .val = 0x0FC10034 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x01C40040 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x07E10300 },
         { .reg = 0x00009888, .val = 0x0FE10D00 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x01E40080 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x000300F0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0009000C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x000100F2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x00020004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x010900C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x01010020 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x01020040 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03000A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42032000 },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext752__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext752__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext752__avg_gpu_core_frequency__max,acmgt3__ext752__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5233, 24, percentage_max_float,acmgt3__ext752__thread_dispatch_queue0_active_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5234, 28, percentage_max_float,acmgt3__ext752__thread_dispatch_queue0_active_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5235, 32, percentage_max_float,acmgt3__ext752__thread_dispatch_queue0_active_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5236, 36, percentage_max_float,acmgt3__ext752__thread_dispatch_queue0_active_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5237, 40, percentage_max_float,acmgt3__ext752__thread_dispatch_queue0_active_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5238, 44, percentage_max_float,acmgt3__ext752__thread_dispatch_queue0_active_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5239, 48, percentage_max_float,acmgt3__ext752__thread_dispatch_queue0_active_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5240, 52, percentage_max_float,acmgt3__ext752__thread_dispatch_queue0_active_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext753_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext753";
   query->symbol_name = "Ext753";
   query->guid = "35169b45-6470-430f-b450-25c6edbc722c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x2A810004 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x2AA10004 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x2AC10004 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x2AE10004 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x2B810004 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x2BA10004 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x2BC10004 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x2BE10004 },
         { .reg = 0x00009888, .val = 0x06811300 },
         { .reg = 0x00009888, .val = 0x08810035 },
         { .reg = 0x00009888, .val = 0x16810F00 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A11300 },
         { .reg = 0x00009888, .val = 0x08A10D40 },
         { .reg = 0x00009888, .val = 0x16A1003C },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C11300 },
         { .reg = 0x00009888, .val = 0x0AC10035 },
         { .reg = 0x00009888, .val = 0x14C10F00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E11300 },
         { .reg = 0x00009888, .val = 0x0AE10D40 },
         { .reg = 0x00009888, .val = 0x14E1003C },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07811300 },
         { .reg = 0x00009888, .val = 0x0D810035 },
         { .reg = 0x00009888, .val = 0x13810F00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A11300 },
         { .reg = 0x00009888, .val = 0x0DA10D40 },
         { .reg = 0x00009888, .val = 0x13A1003C },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C11300 },
         { .reg = 0x00009888, .val = 0x0FC10035 },
         { .reg = 0x00009888, .val = 0x11C10F00 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E11300 },
         { .reg = 0x00009888, .val = 0x0FE10D40 },
         { .reg = 0x00009888, .val = 0x11E1003C },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext753__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext753__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext753__avg_gpu_core_frequency__max,acmgt3__ext753__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1331, 24, percentage_max_float,acmgt3__ext753__thread_dispatch_queue1_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1332, 28, percentage_max_float,acmgt3__ext753__thread_dispatch_queue1_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1333, 32, percentage_max_float,acmgt3__ext753__thread_dispatch_queue1_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1334, 36, percentage_max_float,acmgt3__ext753__thread_dispatch_queue1_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1335, 40, percentage_max_float,acmgt3__ext753__thread_dispatch_queue1_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1336, 44, percentage_max_float,acmgt3__ext753__thread_dispatch_queue1_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1337, 48, percentage_max_float,acmgt3__ext753__thread_dispatch_queue1_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1338, 52, percentage_max_float,acmgt3__ext753__thread_dispatch_queue1_active_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1219, 56, percentage_max_float,acmgt3__ext753__thread_dispatch_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1220, 60, percentage_max_float,acmgt3__ext753__thread_dispatch_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1221, 64, percentage_max_float,acmgt3__ext753__thread_dispatch_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1222, 68, percentage_max_float,acmgt3__ext753__thread_dispatch_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1223, 72, percentage_max_float,acmgt3__ext753__thread_dispatch_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1224, 76, percentage_max_float,acmgt3__ext753__thread_dispatch_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1225, 80, percentage_max_float,acmgt3__ext753__thread_dispatch_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1226, 84, percentage_max_float,acmgt3__ext753__thread_dispatch_stall_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext754_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext754";
   query->symbol_name = "Ext754";
   query->guid = "654777a6-f5d0-4360-804e-8add6b37700a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x2A810004 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x2AA10004 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x2AC10004 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x2AE10004 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x2B810004 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x2BA10004 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x2BC10004 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x2BE10004 },
         { .reg = 0x00009888, .val = 0x06811300 },
         { .reg = 0x00009888, .val = 0x08810035 },
         { .reg = 0x00009888, .val = 0x16810F00 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A11300 },
         { .reg = 0x00009888, .val = 0x08A10D40 },
         { .reg = 0x00009888, .val = 0x16A1003C },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C11300 },
         { .reg = 0x00009888, .val = 0x0AC10035 },
         { .reg = 0x00009888, .val = 0x14C10F00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E11300 },
         { .reg = 0x00009888, .val = 0x0AE10D40 },
         { .reg = 0x00009888, .val = 0x14E1003C },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07811300 },
         { .reg = 0x00009888, .val = 0x0D810035 },
         { .reg = 0x00009888, .val = 0x13810F00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A11300 },
         { .reg = 0x00009888, .val = 0x0DA10D40 },
         { .reg = 0x00009888, .val = 0x13A1003C },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C11300 },
         { .reg = 0x00009888, .val = 0x0FC10035 },
         { .reg = 0x00009888, .val = 0x11C10F00 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E11300 },
         { .reg = 0x00009888, .val = 0x0FE10D40 },
         { .reg = 0x00009888, .val = 0x11E1003C },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext754__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext754__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext754__avg_gpu_core_frequency__max,acmgt3__ext754__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3119, 24, percentage_max_float,acmgt3__ext754__thread_dispatch_queue1_active_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3120, 28, percentage_max_float,acmgt3__ext754__thread_dispatch_queue1_active_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3121, 32, percentage_max_float,acmgt3__ext754__thread_dispatch_queue1_active_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3122, 36, percentage_max_float,acmgt3__ext754__thread_dispatch_queue1_active_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3123, 40, percentage_max_float,acmgt3__ext754__thread_dispatch_queue1_active_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3124, 44, percentage_max_float,acmgt3__ext754__thread_dispatch_queue1_active_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3125, 48, percentage_max_float,acmgt3__ext754__thread_dispatch_queue1_active_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3126, 52, percentage_max_float,acmgt3__ext754__thread_dispatch_queue1_active_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3111, 56, percentage_max_float,acmgt3__ext754__thread_dispatch_stall_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3112, 60, percentage_max_float,acmgt3__ext754__thread_dispatch_stall_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3113, 64, percentage_max_float,acmgt3__ext754__thread_dispatch_stall_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3114, 68, percentage_max_float,acmgt3__ext754__thread_dispatch_stall_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3115, 72, percentage_max_float,acmgt3__ext754__thread_dispatch_stall_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3116, 76, percentage_max_float,acmgt3__ext754__thread_dispatch_stall_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3117, 80, percentage_max_float,acmgt3__ext754__thread_dispatch_stall_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3118, 84, percentage_max_float,acmgt3__ext754__thread_dispatch_stall_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext755_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext755";
   query->symbol_name = "Ext755";
   query->guid = "e5ff2f98-6a0a-4a1e-9c6f-fd7e37a4acfd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x2A810004 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x2AA10004 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x2AC10004 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x2AE10004 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x2B810004 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x2BA10004 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x2BC10004 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x2BE10004 },
         { .reg = 0x00009888, .val = 0x06811300 },
         { .reg = 0x00009888, .val = 0x08810035 },
         { .reg = 0x00009888, .val = 0x16810F00 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A11300 },
         { .reg = 0x00009888, .val = 0x08A10D40 },
         { .reg = 0x00009888, .val = 0x16A1003C },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C11300 },
         { .reg = 0x00009888, .val = 0x0AC10035 },
         { .reg = 0x00009888, .val = 0x14C10F00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E11300 },
         { .reg = 0x00009888, .val = 0x0AE10D40 },
         { .reg = 0x00009888, .val = 0x14E1003C },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07811300 },
         { .reg = 0x00009888, .val = 0x0D810035 },
         { .reg = 0x00009888, .val = 0x13810F00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A11300 },
         { .reg = 0x00009888, .val = 0x0DA10D40 },
         { .reg = 0x00009888, .val = 0x13A1003C },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C11300 },
         { .reg = 0x00009888, .val = 0x0FC10035 },
         { .reg = 0x00009888, .val = 0x11C10F00 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E11300 },
         { .reg = 0x00009888, .val = 0x0FE10D40 },
         { .reg = 0x00009888, .val = 0x11E1003C },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext755__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext755__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext755__avg_gpu_core_frequency__max,acmgt3__ext755__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5241, 24, percentage_max_float,acmgt3__ext755__thread_dispatch_queue1_active_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5242, 28, percentage_max_float,acmgt3__ext755__thread_dispatch_queue1_active_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5243, 32, percentage_max_float,acmgt3__ext755__thread_dispatch_queue1_active_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5244, 36, percentage_max_float,acmgt3__ext755__thread_dispatch_queue1_active_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5245, 40, percentage_max_float,acmgt3__ext755__thread_dispatch_queue1_active_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5246, 44, percentage_max_float,acmgt3__ext755__thread_dispatch_queue1_active_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5247, 48, percentage_max_float,acmgt3__ext755__thread_dispatch_queue1_active_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5248, 52, percentage_max_float,acmgt3__ext755__thread_dispatch_queue1_active_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5249, 56, percentage_max_float,acmgt3__ext755__thread_dispatch_stall_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5250, 60, percentage_max_float,acmgt3__ext755__thread_dispatch_stall_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5251, 64, percentage_max_float,acmgt3__ext755__thread_dispatch_stall_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5252, 68, percentage_max_float,acmgt3__ext755__thread_dispatch_stall_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5253, 72, percentage_max_float,acmgt3__ext755__thread_dispatch_stall_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5254, 76, percentage_max_float,acmgt3__ext755__thread_dispatch_stall_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5255, 80, percentage_max_float,acmgt3__ext755__thread_dispatch_stall_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5256, 84, percentage_max_float,acmgt3__ext755__thread_dispatch_stall_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext756_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext756";
   query->symbol_name = "Ext756";
   query->guid = "c5ef0564-f5ee-4c47-81d1-82f9e3c5356e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x2A810004 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x2AA10004 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x2AC10004 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x2AE10004 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x2B810004 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x2BA10004 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x2BC10004 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x2BE10004 },
         { .reg = 0x00009888, .val = 0x06811300 },
         { .reg = 0x00009888, .val = 0x08810035 },
         { .reg = 0x00009888, .val = 0x16810F00 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00830002 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x00870001 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A11300 },
         { .reg = 0x00009888, .val = 0x08A10D40 },
         { .reg = 0x00009888, .val = 0x16A1003C },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A30008 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x00A70004 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C11300 },
         { .reg = 0x00009888, .val = 0x0AC10035 },
         { .reg = 0x00009888, .val = 0x14C10F00 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C30020 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x00C70010 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E11300 },
         { .reg = 0x00009888, .val = 0x0AE10D40 },
         { .reg = 0x00009888, .val = 0x14E1003C },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E30080 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x00E70040 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07811300 },
         { .reg = 0x00009888, .val = 0x0D810035 },
         { .reg = 0x00009888, .val = 0x13810F00 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01830200 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x01870100 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A11300 },
         { .reg = 0x00009888, .val = 0x0DA10D40 },
         { .reg = 0x00009888, .val = 0x13A1003C },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A30800 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x01A70400 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C11300 },
         { .reg = 0x00009888, .val = 0x0FC10035 },
         { .reg = 0x00009888, .val = 0x11C10F00 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C32000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x01C71000 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E11300 },
         { .reg = 0x00009888, .val = 0x0FE10D40 },
         { .reg = 0x00009888, .val = 0x11E1003C },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E38000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x01E74000 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
         { .reg = 0x0000D968, .val = 0x00000002 },
         { .reg = 0x0000D96C, .val = 0x0000FFDF },
         { .reg = 0x0000D970, .val = 0x00000002 },
         { .reg = 0x0000D974, .val = 0x0000FFBF },
         { .reg = 0x0000D978, .val = 0x00000002 },
         { .reg = 0x0000D97C, .val = 0x0000FF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext756__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext756__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext756__avg_gpu_core_frequency__max,acmgt3__ext756__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5257, 24, percentage_max_float,acmgt3__ext756__thread_dispatch_queue1_active_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5258, 28, percentage_max_float,acmgt3__ext756__thread_dispatch_queue1_active_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5259, 32, percentage_max_float,acmgt3__ext756__thread_dispatch_queue1_active_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5260, 36, percentage_max_float,acmgt3__ext756__thread_dispatch_queue1_active_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5261, 40, percentage_max_float,acmgt3__ext756__thread_dispatch_queue1_active_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5262, 44, percentage_max_float,acmgt3__ext756__thread_dispatch_queue1_active_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5263, 48, percentage_max_float,acmgt3__ext756__thread_dispatch_queue1_active_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5264, 52, percentage_max_float,acmgt3__ext756__thread_dispatch_queue1_active_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5265, 56, percentage_max_float,acmgt3__ext756__thread_dispatch_stall_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5266, 60, percentage_max_float,acmgt3__ext756__thread_dispatch_stall_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5267, 64, percentage_max_float,acmgt3__ext756__thread_dispatch_stall_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5268, 68, percentage_max_float,acmgt3__ext756__thread_dispatch_stall_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5269, 72, percentage_max_float,acmgt3__ext756__thread_dispatch_stall_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5270, 76, percentage_max_float,acmgt3__ext756__thread_dispatch_stall_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5271, 80, percentage_max_float,acmgt3__ext756__thread_dispatch_stall_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5272, 84, percentage_max_float,acmgt3__ext756__thread_dispatch_stall_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext757_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext757";
   query->symbol_name = "Ext757";
   query->guid = "4b9def4f-6c45-4b4c-aebb-b258b1432dd2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x16810C80 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x16A10032 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x14C10C80 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x14E10032 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x13810C80 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10032 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x11C10C80 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x11E10032 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x0E810C80 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0EA10032 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C80 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0CE10032 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x0B810C80 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x0BA10032 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x09C10C80 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x09E10032 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext757__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext757__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext757__avg_gpu_core_frequency__max,acmgt3__ext757__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1227, 24, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1228, 28, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1229, 32, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1230, 36, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1231, 40, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1232, 44, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1233, 48, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1234, 52, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3127, 56, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3128, 60, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3129, 64, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3130, 68, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3131, 72, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3132, 76, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3133, 80, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3134, 84, percentage_max_float,acmgt3__ext757__thread_dispatch_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext758_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext758";
   query->symbol_name = "Ext758";
   query->guid = "4baa43ef-46f0-4563-a23c-23f7a7831777";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x16810C80 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02838000 },
         { .reg = 0x00009888, .val = 0x00848000 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x02874000 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x16A10032 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32000 },
         { .reg = 0x00009888, .val = 0x00A44000 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x02A71000 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x14C10C80 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C30800 },
         { .reg = 0x00009888, .val = 0x00C42000 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x02C70400 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x14E10032 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E30200 },
         { .reg = 0x00009888, .val = 0x00E41000 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x02E70100 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x13810C80 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03830080 },
         { .reg = 0x00009888, .val = 0x01840800 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x03870040 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10032 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A30020 },
         { .reg = 0x00009888, .val = 0x01A40400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x03A70010 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x11C10C80 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30008 },
         { .reg = 0x00009888, .val = 0x01C40200 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x03C70004 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x11E10032 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E30002 },
         { .reg = 0x00009888, .val = 0x01E40100 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x03E70001 },
         { .reg = 0x00009888, .val = 0x00030F00 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x00093000 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014F00 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022000 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x01090300 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020200 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x28810320 },
         { .reg = 0x00009888, .val = 0x28A10320 },
         { .reg = 0x00009888, .val = 0x28C10320 },
         { .reg = 0x00009888, .val = 0x28E10320 },
         { .reg = 0x00009888, .val = 0x29810320 },
         { .reg = 0x00009888, .val = 0x29A10320 },
         { .reg = 0x00009888, .val = 0x29C10320 },
         { .reg = 0x00009888, .val = 0x29E10320 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x0E810C80 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x00838000 },
         { .reg = 0x00009888, .val = 0x00840080 },
         { .reg = 0x00009888, .val = 0x00864000 },
         { .reg = 0x00009888, .val = 0x00874000 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0EA10032 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A32000 },
         { .reg = 0x00009888, .val = 0x00A40040 },
         { .reg = 0x00009888, .val = 0x00A61000 },
         { .reg = 0x00009888, .val = 0x00A71000 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C80 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30800 },
         { .reg = 0x00009888, .val = 0x00C40020 },
         { .reg = 0x00009888, .val = 0x00C60400 },
         { .reg = 0x00009888, .val = 0x00C70400 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0CE10032 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E30200 },
         { .reg = 0x00009888, .val = 0x00E40010 },
         { .reg = 0x00009888, .val = 0x00E60100 },
         { .reg = 0x00009888, .val = 0x00E70100 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x0B810C80 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x01830080 },
         { .reg = 0x00009888, .val = 0x01840008 },
         { .reg = 0x00009888, .val = 0x01860040 },
         { .reg = 0x00009888, .val = 0x01870040 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x0BA10032 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A30020 },
         { .reg = 0x00009888, .val = 0x01A40004 },
         { .reg = 0x00009888, .val = 0x01A60010 },
         { .reg = 0x00009888, .val = 0x01A70010 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x09C10C80 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C30008 },
         { .reg = 0x00009888, .val = 0x01C40002 },
         { .reg = 0x00009888, .val = 0x01C60004 },
         { .reg = 0x00009888, .val = 0x01C70004 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x09E10032 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E30002 },
         { .reg = 0x00009888, .val = 0x01E40001 },
         { .reg = 0x00009888, .val = 0x01E60001 },
         { .reg = 0x00009888, .val = 0x01E70001 },
         { .reg = 0x00009888, .val = 0x0003000F },
         { .reg = 0x00009888, .val = 0x00070900 },
         { .reg = 0x00009888, .val = 0x0008B0FF },
         { .reg = 0x00009888, .val = 0x00090030 },
         { .reg = 0x00009888, .val = 0x000A5A55 },
         { .reg = 0x00009888, .val = 0x0001004F },
         { .reg = 0x00009888, .val = 0x000B10AA },
         { .reg = 0x00009888, .val = 0x00020020 },
         { .reg = 0x00009888, .val = 0x000C0400 },
         { .reg = 0x00009888, .val = 0x01070009 },
         { .reg = 0x00009888, .val = 0x010800B0 },
         { .reg = 0x00009888, .val = 0x01090003 },
         { .reg = 0x00009888, .val = 0x010A005A },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x010B0010 },
         { .reg = 0x00009888, .val = 0x01020002 },
         { .reg = 0x00009888, .val = 0x010C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C0A },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CE2 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x460300E8 },
         { .reg = 0x00009888, .val = 0x480300A7 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext758__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext758__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext758__avg_gpu_core_frequency__max,acmgt3__ext758__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5273, 24, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5274, 28, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5275, 32, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5276, 36, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5277, 40, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5278, 44, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5279, 48, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5280, 52, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5281, 56, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5282, 60, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5283, 64, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5284, 68, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5285, 72, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5286, 76, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5287, 80, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5288, 84, percentage_max_float,acmgt3__ext758__thread_dispatch_input_available_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext759_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext759";
   query->symbol_name = "Ext759";
   query->guid = "a41a6cba-5801-4b99-b6ca-522ab27bcc09";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext759__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext759__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext759__avg_gpu_core_frequency__max,acmgt3__ext759__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1315, 24, percentage_max_float,acmgt3__ext759__thread_dispatch_ps_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1316, 28, percentage_max_float,acmgt3__ext759__thread_dispatch_ps_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1317, 32, percentage_max_float,acmgt3__ext759__thread_dispatch_ps_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1318, 36, percentage_max_float,acmgt3__ext759__thread_dispatch_ps_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1319, 40, percentage_max_float,acmgt3__ext759__thread_dispatch_ps_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1320, 44, percentage_max_float,acmgt3__ext759__thread_dispatch_ps_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1321, 48, percentage_max_float,acmgt3__ext759__thread_dispatch_ps_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1322, 52, percentage_max_float,acmgt3__ext759__thread_dispatch_ps_active_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext760_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext760";
   query->symbol_name = "Ext760";
   query->guid = "ea5c0abd-cb97-4408-b10c-5b1e5cedfa44";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext760__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext760__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext760__avg_gpu_core_frequency__max,acmgt3__ext760__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3135, 24, percentage_max_float,acmgt3__ext760__thread_dispatch_ps_active_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3136, 28, percentage_max_float,acmgt3__ext760__thread_dispatch_ps_active_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3137, 32, percentage_max_float,acmgt3__ext760__thread_dispatch_ps_active_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3138, 36, percentage_max_float,acmgt3__ext760__thread_dispatch_ps_active_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3139, 40, percentage_max_float,acmgt3__ext760__thread_dispatch_ps_active_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3140, 44, percentage_max_float,acmgt3__ext760__thread_dispatch_ps_active_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3141, 48, percentage_max_float,acmgt3__ext760__thread_dispatch_ps_active_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3142, 52, percentage_max_float,acmgt3__ext760__thread_dispatch_ps_active_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext761_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext761";
   query->symbol_name = "Ext761";
   query->guid = "7d0f9d56-a46e-4af8-80c5-60bad08a9465";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext761__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext761__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext761__avg_gpu_core_frequency__max,acmgt3__ext761__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5289, 24, percentage_max_float,acmgt3__ext761__thread_dispatch_ps_active_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5290, 28, percentage_max_float,acmgt3__ext761__thread_dispatch_ps_active_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5291, 32, percentage_max_float,acmgt3__ext761__thread_dispatch_ps_active_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5292, 36, percentage_max_float,acmgt3__ext761__thread_dispatch_ps_active_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5293, 40, percentage_max_float,acmgt3__ext761__thread_dispatch_ps_active_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5294, 44, percentage_max_float,acmgt3__ext761__thread_dispatch_ps_active_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5295, 48, percentage_max_float,acmgt3__ext761__thread_dispatch_ps_active_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5296, 52, percentage_max_float,acmgt3__ext761__thread_dispatch_ps_active_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext762_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext762";
   query->symbol_name = "Ext762";
   query->guid = "1471b5b1-3c7f-45a5-b57b-ff70ede916ca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x28810340 },
         { .reg = 0x00009888, .val = 0x28A10340 },
         { .reg = 0x00009888, .val = 0x28C10340 },
         { .reg = 0x00009888, .val = 0x28E10340 },
         { .reg = 0x00009888, .val = 0x29810340 },
         { .reg = 0x00009888, .val = 0x29A10340 },
         { .reg = 0x00009888, .val = 0x29C10340 },
         { .reg = 0x00009888, .val = 0x29E10340 },
         { .reg = 0x00009888, .val = 0x06810100 },
         { .reg = 0x00009888, .val = 0x08810C31 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0083000A },
         { .reg = 0x00009888, .val = 0x00840003 },
         { .reg = 0x00009888, .val = 0x00860005 },
         { .reg = 0x00009888, .val = 0x00870005 },
         { .reg = 0x00009888, .val = 0x06A10100 },
         { .reg = 0x00009888, .val = 0x0AA10C31 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A300A0 },
         { .reg = 0x00009888, .val = 0x00A4000C },
         { .reg = 0x00009888, .val = 0x00A60050 },
         { .reg = 0x00009888, .val = 0x00A70050 },
         { .reg = 0x00009888, .val = 0x06C10100 },
         { .reg = 0x00009888, .val = 0x0CC10C31 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C30A00 },
         { .reg = 0x00009888, .val = 0x00C40030 },
         { .reg = 0x00009888, .val = 0x00C60500 },
         { .reg = 0x00009888, .val = 0x00C70500 },
         { .reg = 0x00009888, .val = 0x06E10100 },
         { .reg = 0x00009888, .val = 0x0EE10C31 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E3A000 },
         { .reg = 0x00009888, .val = 0x00E400C0 },
         { .reg = 0x00009888, .val = 0x00E65000 },
         { .reg = 0x00009888, .val = 0x00E75000 },
         { .reg = 0x00009888, .val = 0x07810100 },
         { .reg = 0x00009888, .val = 0x11810C31 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x01840300 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10100 },
         { .reg = 0x00009888, .val = 0x13A10C31 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A300A0 },
         { .reg = 0x00009888, .val = 0x01A40C00 },
         { .reg = 0x00009888, .val = 0x03A60050 },
         { .reg = 0x00009888, .val = 0x03A70050 },
         { .reg = 0x00009888, .val = 0x07C10100 },
         { .reg = 0x00009888, .val = 0x15C10C31 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C30A00 },
         { .reg = 0x00009888, .val = 0x01C43000 },
         { .reg = 0x00009888, .val = 0x03C60500 },
         { .reg = 0x00009888, .val = 0x03C70500 },
         { .reg = 0x00009888, .val = 0x07E10100 },
         { .reg = 0x00009888, .val = 0x17E10C31 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E3A000 },
         { .reg = 0x00009888, .val = 0x01E4C000 },
         { .reg = 0x00009888, .val = 0x03E65000 },
         { .reg = 0x00009888, .val = 0x03E75000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00000000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00000000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00000000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext762__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext762__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext762__avg_gpu_core_frequency__max,acmgt3__ext762__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5297, 24, percentage_max_float,acmgt3__ext762__thread_dispatch_ps_active_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5298, 28, percentage_max_float,acmgt3__ext762__thread_dispatch_ps_active_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5299, 32, percentage_max_float,acmgt3__ext762__thread_dispatch_ps_active_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5300, 36, percentage_max_float,acmgt3__ext762__thread_dispatch_ps_active_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5301, 40, percentage_max_float,acmgt3__ext762__thread_dispatch_ps_active_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5302, 44, percentage_max_float,acmgt3__ext762__thread_dispatch_ps_active_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5303, 48, percentage_max_float,acmgt3__ext762__thread_dispatch_ps_active_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5304, 52, percentage_max_float,acmgt3__ext762__thread_dispatch_ps_active_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext763_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext763";
   query->symbol_name = "Ext763";
   query->guid = "cafc80ac-ba40-47b1-8e73-aad5b08d65fe";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x12091580 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x100903D6 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x04090000 },
         { .reg = 0x00009888, .val = 0x06090000 },
         { .reg = 0x00009888, .val = 0x040A1000 },
         { .reg = 0x00009888, .val = 0x060A0001 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext763__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext763__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext763__avg_gpu_core_frequency__max,acmgt3__ext763__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 825, 24, NULL,acmgt3__ext763__host_to_gpumem_transaction_read__read);

      intel_perf_query_add_counter_uint64(query, 826, 32, NULL,acmgt3__ext763__host_to_gpumem_transaction_write__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext764_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext764";
   query->symbol_name = "Ext764";
   query->guid = "0af2df6b-39f4-4104-b2d0-c3e4077f81db";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x120900A0 },
         { .reg = 0x00009888, .val = 0x04034000 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x10090254 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x04090000 },
         { .reg = 0x00009888, .val = 0x06090000 },
         { .reg = 0x00009888, .val = 0x040A1000 },
         { .reg = 0x00009888, .val = 0x060A0001 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext764__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext764__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext764__avg_gpu_core_frequency__max,acmgt3__ext764__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 808, 24, NULL,acmgt3__ext764__sysmem_transaction_read__read);

      intel_perf_query_add_counter_uint64(query, 807, 32, NULL,acmgt3__ext764__sysmem_transaction_write__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext765_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext765";
   query->symbol_name = "Ext765";
   query->guid = "3e45edea-81f9-4d7b-879b-5b4097bdd786";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C813C00 },
         { .reg = 0x00009888, .val = 0x2CA13C00 },
         { .reg = 0x00009888, .val = 0x2CC13C00 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810C37 },
         { .reg = 0x00009888, .val = 0x0A810CB1 },
         { .reg = 0x00009888, .val = 0x0C810033 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0CA10DC0 },
         { .reg = 0x00009888, .val = 0x0EA10C70 },
         { .reg = 0x00009888, .val = 0x10A10CF2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C37 },
         { .reg = 0x00009888, .val = 0x14C10CB1 },
         { .reg = 0x00009888, .val = 0x16C10033 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA0 },
         { .reg = 0x00009888, .val = 0x00C47C00 },
         { .reg = 0x00009888, .val = 0x02C61550 },
         { .reg = 0x00009888, .val = 0x02C71550 },
         { .reg = 0x00009888, .val = 0x02072AA0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x00097C00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A2AA5 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020B0005 },
         { .reg = 0x00009888, .val = 0x00027C00 },
         { .reg = 0x00009888, .val = 0x020C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext765__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext765__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext765__avg_gpu_core_frequency__max,acmgt3__ext765__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1686, 24, NULL,acmgt3__ext765__gpgpu_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1687, 32, NULL,acmgt3__ext765__gpgpu_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1688, 40, NULL,acmgt3__ext765__gpgpu_dispatch_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext766_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext766";
   query->symbol_name = "Ext766";
   query->guid = "eeb406e5-89ec-40f8-98d3-26deaad17507";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CE13C00 },
         { .reg = 0x00009888, .val = 0x2D813C00 },
         { .reg = 0x00009888, .val = 0x2DA13C00 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10C37 },
         { .reg = 0x00009888, .val = 0x0AE10CB1 },
         { .reg = 0x00009888, .val = 0x0CE10033 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x0D810DC0 },
         { .reg = 0x00009888, .val = 0x0F810C70 },
         { .reg = 0x00009888, .val = 0x11810CF2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10C37 },
         { .reg = 0x00009888, .val = 0x15A10CB1 },
         { .reg = 0x00009888, .val = 0x17A10033 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32AA0 },
         { .reg = 0x00009888, .val = 0x01A47C00 },
         { .reg = 0x00009888, .val = 0x03A61550 },
         { .reg = 0x00009888, .val = 0x03A71550 },
         { .reg = 0x00009888, .val = 0x00037FE0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x03083FFA },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A1555 },
         { .reg = 0x00009888, .val = 0x01017C00 },
         { .reg = 0x00009888, .val = 0x030B1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030004 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42031080 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext766__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext766__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext766__avg_gpu_core_frequency__max,acmgt3__ext766__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1689, 24, NULL,acmgt3__ext766__gpgpu_dispatch_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1690, 32, NULL,acmgt3__ext766__gpgpu_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1691, 40, NULL,acmgt3__ext766__gpgpu_dispatch_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext767_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext767";
   query->symbol_name = "Ext767";
   query->guid = "d68aea6c-1a71-4cec-89cf-9904b9b5707d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2DC13C00 },
         { .reg = 0x00009888, .val = 0x2DE13C00 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10C37 },
         { .reg = 0x00009888, .val = 0x0BC10CB1 },
         { .reg = 0x00009888, .val = 0x0DC10033 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x0DE10DC0 },
         { .reg = 0x00009888, .val = 0x0FE10C70 },
         { .reg = 0x00009888, .val = 0x11E10CF2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x010756AA },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2C813C00 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x12810C37 },
         { .reg = 0x00009888, .val = 0x14810CB1 },
         { .reg = 0x00009888, .val = 0x16810033 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x02832AA0 },
         { .reg = 0x00009888, .val = 0x00847C00 },
         { .reg = 0x00009888, .val = 0x02861550 },
         { .reg = 0x00009888, .val = 0x02871550 },
         { .reg = 0x00009888, .val = 0x02082AA0 },
         { .reg = 0x00009888, .val = 0x020A1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02083FFA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032940 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16037000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017C00 },
         { .reg = 0x00009888, .val = 0x02021550 },
         { .reg = 0x00009888, .val = 0x02041550 },
         { .reg = 0x00009888, .val = 0x02051550 },
         { .reg = 0x00009888, .val = 0x02082AA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext767__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext767__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext767__avg_gpu_core_frequency__max,acmgt3__ext767__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1692, 24, NULL,acmgt3__ext767__gpgpu_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1693, 32, NULL,acmgt3__ext767__gpgpu_dispatch_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3143, 40, NULL,acmgt3__ext767__gpgpu_dispatch_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext768_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext768";
   query->symbol_name = "Ext768";
   query->guid = "9a25cdbe-0af1-4586-859b-d8f03c5a4c38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2CA13C00 },
         { .reg = 0x00009888, .val = 0x2CC13C00 },
         { .reg = 0x00009888, .val = 0x2CE13C00 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x08A10C37 },
         { .reg = 0x00009888, .val = 0x0AA10CB1 },
         { .reg = 0x00009888, .val = 0x0CA10033 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x00A302AA },
         { .reg = 0x00009888, .val = 0x00A4001F },
         { .reg = 0x00009888, .val = 0x00A60155 },
         { .reg = 0x00009888, .val = 0x00A70155 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x0CC10DC0 },
         { .reg = 0x00009888, .val = 0x0EC10C70 },
         { .reg = 0x00009888, .val = 0x10C10CF2 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C3A800 },
         { .reg = 0x00009888, .val = 0x02C3000A },
         { .reg = 0x00009888, .val = 0x00C403E0 },
         { .reg = 0x00009888, .val = 0x00C65400 },
         { .reg = 0x00009888, .val = 0x02C60005 },
         { .reg = 0x00009888, .val = 0x00C75400 },
         { .reg = 0x00009888, .val = 0x02C70005 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x12E10C37 },
         { .reg = 0x00009888, .val = 0x14E10CB1 },
         { .reg = 0x00009888, .val = 0x16E10033 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x02E32AA0 },
         { .reg = 0x00009888, .val = 0x00E47C00 },
         { .reg = 0x00009888, .val = 0x02E61550 },
         { .reg = 0x00009888, .val = 0x02E71550 },
         { .reg = 0x00009888, .val = 0x0007A800 },
         { .reg = 0x00009888, .val = 0x0207155A },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00097FE0 },
         { .reg = 0x00009888, .val = 0x000AA955 },
         { .reg = 0x00009888, .val = 0x020A2AAA },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B0155 },
         { .reg = 0x00009888, .val = 0x000203E0 },
         { .reg = 0x00009888, .val = 0x000C5400 },
         { .reg = 0x00009888, .val = 0x020C0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032943 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext768__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext768__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext768__avg_gpu_core_frequency__max,acmgt3__ext768__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3144, 24, NULL,acmgt3__ext768__gpgpu_dispatch_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3145, 32, NULL,acmgt3__ext768__gpgpu_dispatch_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3146, 40, NULL,acmgt3__ext768__gpgpu_dispatch_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext769_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext769";
   query->symbol_name = "Ext769";
   query->guid = "d20aa948-8455-42ca-a4df-cc3040f89330";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2D813C00 },
         { .reg = 0x00009888, .val = 0x2DA13C00 },
         { .reg = 0x00009888, .val = 0x2DC13C00 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x09810C37 },
         { .reg = 0x00009888, .val = 0x0B810CB1 },
         { .reg = 0x00009888, .val = 0x0D810033 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x018302AA },
         { .reg = 0x00009888, .val = 0x0184001F },
         { .reg = 0x00009888, .val = 0x01860155 },
         { .reg = 0x00009888, .val = 0x01870155 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x0DA10DC0 },
         { .reg = 0x00009888, .val = 0x0FA10C70 },
         { .reg = 0x00009888, .val = 0x11A10CF2 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01A3A800 },
         { .reg = 0x00009888, .val = 0x03A3000A },
         { .reg = 0x00009888, .val = 0x01A403E0 },
         { .reg = 0x00009888, .val = 0x01A65400 },
         { .reg = 0x00009888, .val = 0x03A60005 },
         { .reg = 0x00009888, .val = 0x01A75400 },
         { .reg = 0x00009888, .val = 0x03A70005 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x13C10C37 },
         { .reg = 0x00009888, .val = 0x15C10CB1 },
         { .reg = 0x00009888, .val = 0x17C10033 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03C32AA0 },
         { .reg = 0x00009888, .val = 0x01C47C00 },
         { .reg = 0x00009888, .val = 0x03C61550 },
         { .reg = 0x00009888, .val = 0x03C71550 },
         { .reg = 0x00009888, .val = 0x00037FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x03072AA0 },
         { .reg = 0x00009888, .val = 0x0108FEAA },
         { .reg = 0x00009888, .val = 0x0308000F },
         { .reg = 0x00009888, .val = 0x01097C00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A2AA5 },
         { .reg = 0x00009888, .val = 0x010103E0 },
         { .reg = 0x00009888, .val = 0x010B5400 },
         { .reg = 0x00009888, .val = 0x030B0005 },
         { .reg = 0x00009888, .val = 0x01027C00 },
         { .reg = 0x00009888, .val = 0x030C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext769__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext769__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext769__avg_gpu_core_frequency__max,acmgt3__ext769__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3147, 24, NULL,acmgt3__ext769__gpgpu_dispatch_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3148, 32, NULL,acmgt3__ext769__gpgpu_dispatch_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3149, 40, NULL,acmgt3__ext769__gpgpu_dispatch_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext770_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext770";
   query->symbol_name = "Ext770";
   query->guid = "adc02df6-b299-43fa-946e-2de9d979fb39";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x2DE13C00 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x09E10C37 },
         { .reg = 0x00009888, .val = 0x0BE10CB1 },
         { .reg = 0x00009888, .val = 0x0DE10033 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x01E302AA },
         { .reg = 0x00009888, .val = 0x01E4001F },
         { .reg = 0x00009888, .val = 0x01E60155 },
         { .reg = 0x00009888, .val = 0x01E70155 },
         { .reg = 0x00009888, .val = 0x0003001F },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x000A0155 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x000B02AA },
         { .reg = 0x00009888, .val = 0x01070155 },
         { .reg = 0x00009888, .val = 0x0109001F },
         { .reg = 0x00009888, .val = 0x010A02AA },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2C813C00 },
         { .reg = 0x00009888, .val = 0x2CA13C00 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x0C810DC0 },
         { .reg = 0x00009888, .val = 0x0E810C70 },
         { .reg = 0x00009888, .val = 0x10810CF2 },
         { .reg = 0x00009888, .val = 0x08810000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x0083A800 },
         { .reg = 0x00009888, .val = 0x0283000A },
         { .reg = 0x00009888, .val = 0x008403E0 },
         { .reg = 0x00009888, .val = 0x00865400 },
         { .reg = 0x00009888, .val = 0x02860005 },
         { .reg = 0x00009888, .val = 0x00875400 },
         { .reg = 0x00009888, .val = 0x02870005 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x12A10C37 },
         { .reg = 0x00009888, .val = 0x14A10CB1 },
         { .reg = 0x00009888, .val = 0x16A10033 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x02A32AA0 },
         { .reg = 0x00009888, .val = 0x00A47C00 },
         { .reg = 0x00009888, .val = 0x02A61550 },
         { .reg = 0x00009888, .val = 0x02A71550 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x02083FFA },
         { .reg = 0x00009888, .val = 0x000A5400 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017C00 },
         { .reg = 0x00009888, .val = 0x020B1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030C00 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603146A },
         { .reg = 0x00009888, .val = 0x480306A3 },
         { .reg = 0x00009888, .val = 0x4A03146A },
         { .reg = 0x00009888, .val = 0x16033000 },
         { .reg = 0x00009888, .val = 0x18033000 },
         { .reg = 0x00009888, .val = 0x1A033000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E033000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001001F },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00050155 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x00025400 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055400 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext770__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext770__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext770__avg_gpu_core_frequency__max,acmgt3__ext770__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3150, 24, NULL,acmgt3__ext770__gpgpu_dispatch_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5305, 32, NULL,acmgt3__ext770__gpgpu_dispatch_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5306, 40, NULL,acmgt3__ext770__gpgpu_dispatch_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext771_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext771";
   query->symbol_name = "Ext771";
   query->guid = "a5d13667-8d40-4986-bf3c-60c7cdeab38f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2CC13C00 },
         { .reg = 0x00009888, .val = 0x2CE13C00 },
         { .reg = 0x00009888, .val = 0x2D813C00 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x08C10C37 },
         { .reg = 0x00009888, .val = 0x0AC10CB1 },
         { .reg = 0x00009888, .val = 0x0CC10033 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x00C302AA },
         { .reg = 0x00009888, .val = 0x00C4001F },
         { .reg = 0x00009888, .val = 0x00C60155 },
         { .reg = 0x00009888, .val = 0x00C70155 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x0CE10DC0 },
         { .reg = 0x00009888, .val = 0x0EE10C70 },
         { .reg = 0x00009888, .val = 0x10E10CF2 },
         { .reg = 0x00009888, .val = 0x08E10000 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E3A800 },
         { .reg = 0x00009888, .val = 0x02E3000A },
         { .reg = 0x00009888, .val = 0x00E403E0 },
         { .reg = 0x00009888, .val = 0x00E65400 },
         { .reg = 0x00009888, .val = 0x02E60005 },
         { .reg = 0x00009888, .val = 0x00E75400 },
         { .reg = 0x00009888, .val = 0x02E70005 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x13810C37 },
         { .reg = 0x00009888, .val = 0x15810CB1 },
         { .reg = 0x00009888, .val = 0x17810033 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03832AA0 },
         { .reg = 0x00009888, .val = 0x01847C00 },
         { .reg = 0x00009888, .val = 0x03861550 },
         { .reg = 0x00009888, .val = 0x03871550 },
         { .reg = 0x00009888, .val = 0x00037C00 },
         { .reg = 0x00009888, .val = 0x000756AA },
         { .reg = 0x00009888, .val = 0x02070005 },
         { .reg = 0x00009888, .val = 0x02083FF0 },
         { .reg = 0x00009888, .val = 0x000903FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A155A },
         { .reg = 0x00009888, .val = 0x00017C00 },
         { .reg = 0x00009888, .val = 0x020B2AA0 },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x000C0155 },
         { .reg = 0x00009888, .val = 0x03082AA0 },
         { .reg = 0x00009888, .val = 0x030A1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030006 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x420318C0 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030CC6 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030A65 },
         { .reg = 0x00009888, .val = 0x48030653 },
         { .reg = 0x00009888, .val = 0x4A030A65 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext771__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext771__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext771__avg_gpu_core_frequency__max,acmgt3__ext771__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5307, 24, NULL,acmgt3__ext771__gpgpu_dispatch_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5308, 32, NULL,acmgt3__ext771__gpgpu_dispatch_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5309, 40, NULL,acmgt3__ext771__gpgpu_dispatch_xecore20__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext772_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext772";
   query->symbol_name = "Ext772";
   query->guid = "534443d5-42af-4388-8594-e1ff0f90dc3c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x2DA13C00 },
         { .reg = 0x00009888, .val = 0x2DC13C00 },
         { .reg = 0x00009888, .val = 0x2DE13C00 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x09A10C37 },
         { .reg = 0x00009888, .val = 0x0BA10CB1 },
         { .reg = 0x00009888, .val = 0x0DA10033 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x01A302AA },
         { .reg = 0x00009888, .val = 0x01A4001F },
         { .reg = 0x00009888, .val = 0x01A60155 },
         { .reg = 0x00009888, .val = 0x01A70155 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x0DC10DC0 },
         { .reg = 0x00009888, .val = 0x0FC10C70 },
         { .reg = 0x00009888, .val = 0x11C10CF2 },
         { .reg = 0x00009888, .val = 0x09C10000 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01C3A800 },
         { .reg = 0x00009888, .val = 0x03C3000A },
         { .reg = 0x00009888, .val = 0x01C403E0 },
         { .reg = 0x00009888, .val = 0x01C65400 },
         { .reg = 0x00009888, .val = 0x03C60005 },
         { .reg = 0x00009888, .val = 0x01C75400 },
         { .reg = 0x00009888, .val = 0x03C70005 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x13E10C37 },
         { .reg = 0x00009888, .val = 0x15E10CB1 },
         { .reg = 0x00009888, .val = 0x17E10033 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x03E32AA0 },
         { .reg = 0x00009888, .val = 0x01E47C00 },
         { .reg = 0x00009888, .val = 0x03E61550 },
         { .reg = 0x00009888, .val = 0x03E71550 },
         { .reg = 0x00009888, .val = 0x00037FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0107A800 },
         { .reg = 0x00009888, .val = 0x0307155A },
         { .reg = 0x00009888, .val = 0x010803FF },
         { .reg = 0x00009888, .val = 0x01097FE0 },
         { .reg = 0x00009888, .val = 0x010AA955 },
         { .reg = 0x00009888, .val = 0x030A2AAA },
         { .reg = 0x00009888, .val = 0x0101001F },
         { .reg = 0x00009888, .val = 0x010B0155 },
         { .reg = 0x00009888, .val = 0x010203E0 },
         { .reg = 0x00009888, .val = 0x010C5400 },
         { .reg = 0x00009888, .val = 0x030C0005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032943 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030C60 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x4003294A },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext772__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext772__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext772__avg_gpu_core_frequency__max,acmgt3__ext772__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5310, 24, NULL,acmgt3__ext772__gpgpu_dispatch_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5311, 32, NULL,acmgt3__ext772__gpgpu_dispatch_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5312, 40, NULL,acmgt3__ext772__gpgpu_dispatch_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext773_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext773";
   query->symbol_name = "Ext773";
   query->guid = "ff303167-7860-456a-bb57-3f33a851b1be";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2C813C00 },
         { .reg = 0x00009888, .val = 0x2CA13C00 },
         { .reg = 0x00009888, .val = 0x2CC13C00 },
         { .reg = 0x00009888, .val = 0x06810800 },
         { .reg = 0x00009888, .val = 0x08810C37 },
         { .reg = 0x00009888, .val = 0x0A810CB1 },
         { .reg = 0x00009888, .val = 0x0C810033 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x008302AA },
         { .reg = 0x00009888, .val = 0x0084001F },
         { .reg = 0x00009888, .val = 0x00860155 },
         { .reg = 0x00009888, .val = 0x00870155 },
         { .reg = 0x00009888, .val = 0x06A10800 },
         { .reg = 0x00009888, .val = 0x0CA10DC0 },
         { .reg = 0x00009888, .val = 0x0EA10C70 },
         { .reg = 0x00009888, .val = 0x10A10CF2 },
         { .reg = 0x00009888, .val = 0x08A10000 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A3A800 },
         { .reg = 0x00009888, .val = 0x02A3000A },
         { .reg = 0x00009888, .val = 0x00A403E0 },
         { .reg = 0x00009888, .val = 0x00A65400 },
         { .reg = 0x00009888, .val = 0x02A60005 },
         { .reg = 0x00009888, .val = 0x00A75400 },
         { .reg = 0x00009888, .val = 0x02A70005 },
         { .reg = 0x00009888, .val = 0x06C10800 },
         { .reg = 0x00009888, .val = 0x12C10C37 },
         { .reg = 0x00009888, .val = 0x14C10CB1 },
         { .reg = 0x00009888, .val = 0x16C10033 },
         { .reg = 0x00009888, .val = 0x08C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x02C32AA0 },
         { .reg = 0x00009888, .val = 0x00C47C00 },
         { .reg = 0x00009888, .val = 0x02C61550 },
         { .reg = 0x00009888, .val = 0x02C71550 },
         { .reg = 0x00009888, .val = 0x02072AA0 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x00097C00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A2AA5 },
         { .reg = 0x00009888, .val = 0x000103E0 },
         { .reg = 0x00009888, .val = 0x000B5400 },
         { .reg = 0x00009888, .val = 0x020B0005 },
         { .reg = 0x00009888, .val = 0x00027C00 },
         { .reg = 0x00009888, .val = 0x020C1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E030002 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030042 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030603 },
         { .reg = 0x00009888, .val = 0x48030030 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext773__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext773__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext773__avg_gpu_core_frequency__max,acmgt3__ext773__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5313, 24, NULL,acmgt3__ext773__gpgpu_dispatch_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5314, 32, NULL,acmgt3__ext773__gpgpu_dispatch_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5315, 40, NULL,acmgt3__ext773__gpgpu_dispatch_xecore26__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext774_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext774";
   query->symbol_name = "Ext774";
   query->guid = "7bef3eac-1836-440d-be35-4c9b66eb30d5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2CE13C00 },
         { .reg = 0x00009888, .val = 0x2D813C00 },
         { .reg = 0x00009888, .val = 0x2DA13C00 },
         { .reg = 0x00009888, .val = 0x06E10800 },
         { .reg = 0x00009888, .val = 0x08E10C37 },
         { .reg = 0x00009888, .val = 0x0AE10CB1 },
         { .reg = 0x00009888, .val = 0x0CE10033 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x00E302AA },
         { .reg = 0x00009888, .val = 0x00E4001F },
         { .reg = 0x00009888, .val = 0x00E60155 },
         { .reg = 0x00009888, .val = 0x00E70155 },
         { .reg = 0x00009888, .val = 0x07810800 },
         { .reg = 0x00009888, .val = 0x0D810DC0 },
         { .reg = 0x00009888, .val = 0x0F810C70 },
         { .reg = 0x00009888, .val = 0x11810CF2 },
         { .reg = 0x00009888, .val = 0x09810000 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0183A800 },
         { .reg = 0x00009888, .val = 0x0383000A },
         { .reg = 0x00009888, .val = 0x018403E0 },
         { .reg = 0x00009888, .val = 0x01865400 },
         { .reg = 0x00009888, .val = 0x03860005 },
         { .reg = 0x00009888, .val = 0x01875400 },
         { .reg = 0x00009888, .val = 0x03870005 },
         { .reg = 0x00009888, .val = 0x07A10800 },
         { .reg = 0x00009888, .val = 0x13A10C37 },
         { .reg = 0x00009888, .val = 0x15A10CB1 },
         { .reg = 0x00009888, .val = 0x17A10033 },
         { .reg = 0x00009888, .val = 0x09A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03A32AA0 },
         { .reg = 0x00009888, .val = 0x01A47C00 },
         { .reg = 0x00009888, .val = 0x03A61550 },
         { .reg = 0x00009888, .val = 0x03A71550 },
         { .reg = 0x00009888, .val = 0x00037FE0 },
         { .reg = 0x00009888, .val = 0x00070155 },
         { .reg = 0x00009888, .val = 0x0008FC00 },
         { .reg = 0x00009888, .val = 0x02083FFF },
         { .reg = 0x00009888, .val = 0x0009001F },
         { .reg = 0x00009888, .val = 0x000A56AA },
         { .reg = 0x00009888, .val = 0x020A1555 },
         { .reg = 0x00009888, .val = 0x00017FE0 },
         { .reg = 0x00009888, .val = 0x000BA800 },
         { .reg = 0x00009888, .val = 0x020B2AAA },
         { .reg = 0x00009888, .val = 0x0108A800 },
         { .reg = 0x00009888, .val = 0x03083FFA },
         { .reg = 0x00009888, .val = 0x010A5400 },
         { .reg = 0x00009888, .val = 0x030A1555 },
         { .reg = 0x00009888, .val = 0x01017C00 },
         { .reg = 0x00009888, .val = 0x030B1550 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030004 },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x42031080 },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030084 },
         { .reg = 0x00009888, .val = 0x38037000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00017FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
         { .reg = 0x0000D960, .val = 0x0001E002 },
         { .reg = 0x0000D964, .val = 0x000083FF },
         { .reg = 0x0000D968, .val = 0x00022002 },
         { .reg = 0x0000D96C, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext774__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext774__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext774__avg_gpu_core_frequency__max,acmgt3__ext774__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5316, 24, NULL,acmgt3__ext774__gpgpu_dispatch_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5317, 32, NULL,acmgt3__ext774__gpgpu_dispatch_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5318, 40, NULL,acmgt3__ext774__gpgpu_dispatch_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext775_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext775";
   query->symbol_name = "Ext775";
   query->guid = "e92a471e-0ed7-49c0-a3c0-fbb3ada6b722";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x2DC13C00 },
         { .reg = 0x00009888, .val = 0x2DE13C00 },
         { .reg = 0x00009888, .val = 0x07C10800 },
         { .reg = 0x00009888, .val = 0x09C10C37 },
         { .reg = 0x00009888, .val = 0x0BC10CB1 },
         { .reg = 0x00009888, .val = 0x0DC10033 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x01C302AA },
         { .reg = 0x00009888, .val = 0x01C4001F },
         { .reg = 0x00009888, .val = 0x01C60155 },
         { .reg = 0x00009888, .val = 0x01C70155 },
         { .reg = 0x00009888, .val = 0x07E10800 },
         { .reg = 0x00009888, .val = 0x0DE10DC0 },
         { .reg = 0x00009888, .val = 0x0FE10C70 },
         { .reg = 0x00009888, .val = 0x11E10CF2 },
         { .reg = 0x00009888, .val = 0x09E10000 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x01E3A800 },
         { .reg = 0x00009888, .val = 0x03E3000A },
         { .reg = 0x00009888, .val = 0x01E403E0 },
         { .reg = 0x00009888, .val = 0x01E65400 },
         { .reg = 0x00009888, .val = 0x03E60005 },
         { .reg = 0x00009888, .val = 0x01E75400 },
         { .reg = 0x00009888, .val = 0x03E70005 },
         { .reg = 0x00009888, .val = 0x000303FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0005 },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B000A },
         { .reg = 0x00009888, .val = 0x010756AA },
         { .reg = 0x00009888, .val = 0x03070005 },
         { .reg = 0x00009888, .val = 0x010903FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A000A },
         { .reg = 0x00009888, .val = 0x0102001F },
         { .reg = 0x00009888, .val = 0x010C0155 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202000A },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x4603140A },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03140A },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000103FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020005 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050005 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00000F02 },
         { .reg = 0x0000D954, .val = 0x0000FC1F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000FC1F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext775__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext775__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext775__avg_gpu_core_frequency__max,acmgt3__ext775__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5319, 24, NULL,acmgt3__ext775__gpgpu_dispatch_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5320, 32, NULL,acmgt3__ext775__gpgpu_dispatch_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext776_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext776";
   query->symbol_name = "Ext776";
   query->guid = "4a97778b-b9b8-4d0b-925a-82aea8f47efd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0A902960 },
         { .reg = 0x00009888, .val = 0x0AB02960 },
         { .reg = 0x00009888, .val = 0x0AD02960 },
         { .reg = 0x00009888, .val = 0x0AF02960 },
         { .reg = 0x00009888, .val = 0x009039E0 },
         { .reg = 0x00009888, .val = 0x00810015 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x02B039E0 },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A10540 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04D039E0 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x00C15000 },
         { .reg = 0x00009888, .val = 0x02C10001 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x06F039E0 },
         { .reg = 0x00009888, .val = 0x00F00000 },
         { .reg = 0x00009888, .val = 0x02E10054 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext776__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext776__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext776__avg_gpu_core_frequency__max,acmgt3__ext776__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1678, 24, percentage_max_float,acmgt3__ext776__xve_multiple_pipe_active_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1679, 28, percentage_max_float,acmgt3__ext776__xve_multiple_pipe_active_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1680, 32, percentage_max_float,acmgt3__ext776__xve_multiple_pipe_active_xecore2_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1681, 36, percentage_max_float,acmgt3__ext776__xve_multiple_pipe_active_xecore3_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext777_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext777";
   query->symbol_name = "Ext777";
   query->guid = "56abdb73-a247-461c-b516-667a353dba66";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B902960 },
         { .reg = 0x00009888, .val = 0x0BB02960 },
         { .reg = 0x00009888, .val = 0x0BD02960 },
         { .reg = 0x00009888, .val = 0x0BF02960 },
         { .reg = 0x00009888, .val = 0x019039E0 },
         { .reg = 0x00009888, .val = 0x01810015 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x03B039E0 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x01A10540 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05D039E0 },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x01C15000 },
         { .reg = 0x00009888, .val = 0x03C10001 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x07F039E0 },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x03E10054 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext777__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext777__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext777__avg_gpu_core_frequency__max,acmgt3__ext777__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1682, 24, percentage_max_float,acmgt3__ext777__xve_multiple_pipe_active_xecore4_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1683, 28, percentage_max_float,acmgt3__ext777__xve_multiple_pipe_active_xecore5_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1684, 32, percentage_max_float,acmgt3__ext777__xve_multiple_pipe_active_xecore6_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1685, 36, percentage_max_float,acmgt3__ext777__xve_multiple_pipe_active_xecore7_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext778_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext778";
   query->symbol_name = "Ext778";
   query->guid = "adb95c52-6732-4701-bf82-b19e40610730";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0A902960 },
         { .reg = 0x00009888, .val = 0x0AB02960 },
         { .reg = 0x00009888, .val = 0x0AD02960 },
         { .reg = 0x00009888, .val = 0x0AF02960 },
         { .reg = 0x00009888, .val = 0x009039E0 },
         { .reg = 0x00009888, .val = 0x00810015 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x02B039E0 },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A10540 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04D039E0 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x00C15000 },
         { .reg = 0x00009888, .val = 0x02C10001 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x06F039E0 },
         { .reg = 0x00009888, .val = 0x00F00000 },
         { .reg = 0x00009888, .val = 0x02E10054 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext778__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext778__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext778__avg_gpu_core_frequency__max,acmgt3__ext778__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 3277, 24, percentage_max_float,acmgt3__ext778__xve_multiple_pipe_active_xecore8_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 3278, 28, percentage_max_float,acmgt3__ext778__xve_multiple_pipe_active_xecore9_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 3279, 32, percentage_max_float,acmgt3__ext778__xve_multiple_pipe_active_xecore10_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 3280, 36, percentage_max_float,acmgt3__ext778__xve_multiple_pipe_active_xecore11_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext779_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext779";
   query->symbol_name = "Ext779";
   query->guid = "25f4ce6e-3e46-47c5-9fab-ba1503e64779";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x0B902960 },
         { .reg = 0x00009888, .val = 0x0BB02960 },
         { .reg = 0x00009888, .val = 0x0BD02960 },
         { .reg = 0x00009888, .val = 0x0BF02960 },
         { .reg = 0x00009888, .val = 0x019039E0 },
         { .reg = 0x00009888, .val = 0x01810015 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x03B039E0 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x01A10540 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05D039E0 },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x01C15000 },
         { .reg = 0x00009888, .val = 0x03C10001 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x07F039E0 },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x03E10054 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04030012 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext779__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext779__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext779__avg_gpu_core_frequency__max,acmgt3__ext779__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 3281, 24, percentage_max_float,acmgt3__ext779__xve_multiple_pipe_active_xecore12_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 3282, 28, percentage_max_float,acmgt3__ext779__xve_multiple_pipe_active_xecore13_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 3283, 32, percentage_max_float,acmgt3__ext779__xve_multiple_pipe_active_xecore14_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 3284, 36, percentage_max_float,acmgt3__ext779__xve_multiple_pipe_active_xecore15_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext780_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext780";
   query->symbol_name = "Ext780";
   query->guid = "1c363007-b280-4450-bf7a-89b2f26bfa87";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0A902960 },
         { .reg = 0x00009888, .val = 0x0AB02960 },
         { .reg = 0x00009888, .val = 0x0AD02960 },
         { .reg = 0x00009888, .val = 0x0AF02960 },
         { .reg = 0x00009888, .val = 0x009039E0 },
         { .reg = 0x00009888, .val = 0x00810015 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x02B039E0 },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A10540 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04D039E0 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x00C15000 },
         { .reg = 0x00009888, .val = 0x02C10001 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x06F039E0 },
         { .reg = 0x00009888, .val = 0x00F00000 },
         { .reg = 0x00009888, .val = 0x02E10054 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext780__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext780__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext780__avg_gpu_core_frequency__max,acmgt3__ext780__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5321, 24, percentage_max_float,acmgt3__ext780__xve_multiple_pipe_active_xecore16_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5322, 28, percentage_max_float,acmgt3__ext780__xve_multiple_pipe_active_xecore17_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5323, 32, percentage_max_float,acmgt3__ext780__xve_multiple_pipe_active_xecore18_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5324, 36, percentage_max_float,acmgt3__ext780__xve_multiple_pipe_active_xecore19_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext781_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext781";
   query->symbol_name = "Ext781";
   query->guid = "16822061-bdb0-4337-97f9-621fa82266f5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x0B902960 },
         { .reg = 0x00009888, .val = 0x0BB02960 },
         { .reg = 0x00009888, .val = 0x0BD02960 },
         { .reg = 0x00009888, .val = 0x0BF02960 },
         { .reg = 0x00009888, .val = 0x019039E0 },
         { .reg = 0x00009888, .val = 0x01810015 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x03B039E0 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x01A10540 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05D039E0 },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x01C15000 },
         { .reg = 0x00009888, .val = 0x03C10001 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x07F039E0 },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x03E10054 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext781__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext781__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext781__avg_gpu_core_frequency__max,acmgt3__ext781__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5325, 24, percentage_max_float,acmgt3__ext781__xve_multiple_pipe_active_xecore20_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5326, 28, percentage_max_float,acmgt3__ext781__xve_multiple_pipe_active_xecore21_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5327, 32, percentage_max_float,acmgt3__ext781__xve_multiple_pipe_active_xecore22_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5328, 36, percentage_max_float,acmgt3__ext781__xve_multiple_pipe_active_xecore23_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext782_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext782";
   query->symbol_name = "Ext782";
   query->guid = "1d540165-56a1-4bac-925e-b5f85c930662";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0A902960 },
         { .reg = 0x00009888, .val = 0x0AB02960 },
         { .reg = 0x00009888, .val = 0x0AD02960 },
         { .reg = 0x00009888, .val = 0x0AF02960 },
         { .reg = 0x00009888, .val = 0x009039E0 },
         { .reg = 0x00009888, .val = 0x00810015 },
         { .reg = 0x00009888, .val = 0x0083002A },
         { .reg = 0x00009888, .val = 0x00840007 },
         { .reg = 0x00009888, .val = 0x00860015 },
         { .reg = 0x00009888, .val = 0x00870015 },
         { .reg = 0x00009888, .val = 0x02B039E0 },
         { .reg = 0x00009888, .val = 0x00B00000 },
         { .reg = 0x00009888, .val = 0x00A10540 },
         { .reg = 0x00009888, .val = 0x00A30A80 },
         { .reg = 0x00009888, .val = 0x00A40038 },
         { .reg = 0x00009888, .val = 0x00A60540 },
         { .reg = 0x00009888, .val = 0x00A70540 },
         { .reg = 0x00009888, .val = 0x04D039E0 },
         { .reg = 0x00009888, .val = 0x00D00000 },
         { .reg = 0x00009888, .val = 0x00C15000 },
         { .reg = 0x00009888, .val = 0x02C10001 },
         { .reg = 0x00009888, .val = 0x00C3A000 },
         { .reg = 0x00009888, .val = 0x02C30002 },
         { .reg = 0x00009888, .val = 0x00C401C0 },
         { .reg = 0x00009888, .val = 0x00C65000 },
         { .reg = 0x00009888, .val = 0x02C60001 },
         { .reg = 0x00009888, .val = 0x00C75000 },
         { .reg = 0x00009888, .val = 0x02C70001 },
         { .reg = 0x00009888, .val = 0x06F039E0 },
         { .reg = 0x00009888, .val = 0x00F00000 },
         { .reg = 0x00009888, .val = 0x02E10054 },
         { .reg = 0x00009888, .val = 0x02E300A8 },
         { .reg = 0x00009888, .val = 0x00E40E00 },
         { .reg = 0x00009888, .val = 0x02E60054 },
         { .reg = 0x00009888, .val = 0x02E70054 },
         { .reg = 0x00009888, .val = 0x0007A000 },
         { .reg = 0x00009888, .val = 0x02070056 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x00090FC0 },
         { .reg = 0x00009888, .val = 0x000AA555 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009888, .val = 0x00010038 },
         { .reg = 0x00009888, .val = 0x000B0540 },
         { .reg = 0x00009888, .val = 0x000201C0 },
         { .reg = 0x00009888, .val = 0x000C5000 },
         { .reg = 0x00009888, .val = 0x020C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext782__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext782__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext782__avg_gpu_core_frequency__max,acmgt3__ext782__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5329, 24, percentage_max_float,acmgt3__ext782__xve_multiple_pipe_active_xecore24_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5330, 28, percentage_max_float,acmgt3__ext782__xve_multiple_pipe_active_xecore25_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5331, 32, percentage_max_float,acmgt3__ext782__xve_multiple_pipe_active_xecore26_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5332, 36, percentage_max_float,acmgt3__ext782__xve_multiple_pipe_active_xecore27_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext783_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext783";
   query->symbol_name = "Ext783";
   query->guid = "ded56000-0bad-417e-a357-3e96ff672775";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x0B902960 },
         { .reg = 0x00009888, .val = 0x0BB02960 },
         { .reg = 0x00009888, .val = 0x0BD02960 },
         { .reg = 0x00009888, .val = 0x0BF02960 },
         { .reg = 0x00009888, .val = 0x019039E0 },
         { .reg = 0x00009888, .val = 0x01810015 },
         { .reg = 0x00009888, .val = 0x0183002A },
         { .reg = 0x00009888, .val = 0x01840007 },
         { .reg = 0x00009888, .val = 0x01860015 },
         { .reg = 0x00009888, .val = 0x01870015 },
         { .reg = 0x00009888, .val = 0x03B039E0 },
         { .reg = 0x00009888, .val = 0x01B00000 },
         { .reg = 0x00009888, .val = 0x01A10540 },
         { .reg = 0x00009888, .val = 0x01A30A80 },
         { .reg = 0x00009888, .val = 0x01A40038 },
         { .reg = 0x00009888, .val = 0x01A60540 },
         { .reg = 0x00009888, .val = 0x01A70540 },
         { .reg = 0x00009888, .val = 0x05D039E0 },
         { .reg = 0x00009888, .val = 0x01D00000 },
         { .reg = 0x00009888, .val = 0x01C15000 },
         { .reg = 0x00009888, .val = 0x03C10001 },
         { .reg = 0x00009888, .val = 0x01C3A000 },
         { .reg = 0x00009888, .val = 0x03C30002 },
         { .reg = 0x00009888, .val = 0x01C401C0 },
         { .reg = 0x00009888, .val = 0x01C65000 },
         { .reg = 0x00009888, .val = 0x03C60001 },
         { .reg = 0x00009888, .val = 0x01C75000 },
         { .reg = 0x00009888, .val = 0x03C70001 },
         { .reg = 0x00009888, .val = 0x07F039E0 },
         { .reg = 0x00009888, .val = 0x01F00000 },
         { .reg = 0x00009888, .val = 0x03E10054 },
         { .reg = 0x00009888, .val = 0x03E300A8 },
         { .reg = 0x00009888, .val = 0x01E40E00 },
         { .reg = 0x00009888, .val = 0x03E60054 },
         { .reg = 0x00009888, .val = 0x03E70054 },
         { .reg = 0x00009888, .val = 0x00030FFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A0055 },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B00AA },
         { .reg = 0x00009888, .val = 0x0107A000 },
         { .reg = 0x00009888, .val = 0x03070056 },
         { .reg = 0x00009888, .val = 0x01080FEA },
         { .reg = 0x00009888, .val = 0x01090FC0 },
         { .reg = 0x00009888, .val = 0x010AA555 },
         { .reg = 0x00009888, .val = 0x030A00AA },
         { .reg = 0x00009888, .val = 0x01010038 },
         { .reg = 0x00009888, .val = 0x010B0540 },
         { .reg = 0x00009888, .val = 0x010201C0 },
         { .reg = 0x00009888, .val = 0x010C5000 },
         { .reg = 0x00009888, .val = 0x030C0001 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04030009 },
         { .reg = 0x00009888, .val = 0x14031000 },
         { .reg = 0x00009888, .val = 0x3E032942 },
         { .reg = 0x00009888, .val = 0x26031000 },
         { .reg = 0x00009888, .val = 0x42030840 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030063 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A031400 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x00010FFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02050055 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x020800AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext783__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext783__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext783__avg_gpu_core_frequency__max,acmgt3__ext783__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5333, 24, percentage_max_float,acmgt3__ext783__xve_multiple_pipe_active_xecore28_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5334, 28, percentage_max_float,acmgt3__ext783__xve_multiple_pipe_active_xecore29_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5335, 32, percentage_max_float,acmgt3__ext783__xve_multiple_pipe_active_xecore30_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5336, 36, percentage_max_float,acmgt3__ext783__xve_multiple_pipe_active_xecore31_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext784_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext784";
   query->symbol_name = "Ext784";
   query->guid = "32b605b2-1b0d-4637-9570-7cf8fe65fc4b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0310E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030100 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext784__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext784__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext784__avg_gpu_core_frequency__max,acmgt3__ext784__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1762, 24, NULL,acmgt3__ext784__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext785_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext785";
   query->symbol_name = "Ext785";
   query->guid = "c75ec9a3-1b38-4b79-84ec-5978b66a2025";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E036C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0337E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030360 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext785__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext785__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext785__avg_gpu_core_frequency__max,acmgt3__ext785__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1763, 24, NULL,acmgt3__ext785__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext786_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext786";
   query->symbol_name = "Ext786";
   query->guid = "91bd53aa-441f-4ac9-98a0-7736d2e0b114";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0310E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030100 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext786__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext786__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext786__avg_gpu_core_frequency__max,acmgt3__ext786__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2303, 24, NULL,acmgt3__ext786__pixel_2x2_lit_post_rasterizer_early_depth_slice2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext787_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext787";
   query->symbol_name = "Ext787";
   query->guid = "94f9a5a7-03a9-4b7c-9dbd-9c21a8cf812d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E036C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0337E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030360 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext787__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext787__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext787__avg_gpu_core_frequency__max,acmgt3__ext787__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2304, 24, NULL,acmgt3__ext787__pixel_2x2_lit_post_rasterizer_early_depth_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext788_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext788";
   query->symbol_name = "Ext788";
   query->guid = "4f1c78e4-d2fd-4830-aefc-bfb88842abaf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0312E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030120 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext788__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext788__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext788__avg_gpu_core_frequency__max,acmgt3__ext788__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 5337, 24, NULL,acmgt3__ext788__pixel_2x2_lit_post_rasterizer_early_depth_slice4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext789_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext789";
   query->symbol_name = "Ext789";
   query->guid = "c5e2f4a2-6f3e-4639-b894-2c45e1a9f0a8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0339E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030380 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext789__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext789__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext789__avg_gpu_core_frequency__max,acmgt3__ext789__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 5338, 24, NULL,acmgt3__ext789__pixel_2x2_lit_post_rasterizer_early_depth_slice5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext790_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext790";
   query->symbol_name = "Ext790";
   query->guid = "3b972302-7e1a-4da0-a144-6bd89d47dba6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0312E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030120 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext790__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext790__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext790__avg_gpu_core_frequency__max,acmgt3__ext790__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 5339, 24, NULL,acmgt3__ext790__pixel_2x2_lit_post_rasterizer_early_depth_slice6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext791_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext791";
   query->symbol_name = "Ext791";
   query->guid = "3cc5aaa1-5cb8-49d5-ac8f-51520b860975";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0339E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030380 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext791__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext791__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext791__avg_gpu_core_frequency__max,acmgt3__ext791__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 5340, 24, NULL,acmgt3__ext791__pixel_2x2_lit_post_rasterizer_early_depth_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext792_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext792";
   query->symbol_name = "Ext792";
   query->guid = "ccd1df98-fb94-4b65-94d5-25c3a1d39be5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0310E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030100 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext792__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext792__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext792__avg_gpu_core_frequency__max,acmgt3__ext792__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 1764, 24, NULL,acmgt3__ext792__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext793_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext793";
   query->symbol_name = "Ext793";
   query->guid = "317b6732-6990-422c-960b-1a82ee3b02d2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E036C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0337E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030360 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext793__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext793__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext793__avg_gpu_core_frequency__max,acmgt3__ext793__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 1765, 24, NULL,acmgt3__ext793__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext794_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext794";
   query->symbol_name = "Ext794";
   query->guid = "d4d3594d-4c78-4a8f-b663-2781c6aef1f7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0310E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030100 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext794__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext794__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext794__avg_gpu_core_frequency__max,acmgt3__ext794__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 2)) {
         intel_perf_query_add_counter_uint64(query, 2305, 24, NULL,acmgt3__ext794__pixel_2x2_lit_post_rasterizer_late_depth_slice2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext795_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext795";
   query->symbol_name = "Ext795";
   query->guid = "9d5f4e50-1050-47ea-8876-02e8d2a71e3f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E036C00 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0337E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030360 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext795__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext795__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext795__avg_gpu_core_frequency__max,acmgt3__ext795__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 3)) {
         intel_perf_query_add_counter_uint64(query, 2306, 24, NULL,acmgt3__ext795__pixel_2x2_lit_post_rasterizer_late_depth_slice3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext796_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext796";
   query->symbol_name = "Ext796";
   query->guid = "5b6d809b-26ee-4832-86bf-970d1678489b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0312E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030120 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext796__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext796__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext796__avg_gpu_core_frequency__max,acmgt3__ext796__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 4)) {
         intel_perf_query_add_counter_uint64(query, 5341, 24, NULL,acmgt3__ext796__pixel_2x2_lit_post_rasterizer_late_depth_slice4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext797_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext797";
   query->symbol_name = "Ext797";
   query->guid = "5da0a308-98ff-4ff0-9481-4971aa263b06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0339E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030380 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext797__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext797__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext797__avg_gpu_core_frequency__max,acmgt3__ext797__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 5)) {
         intel_perf_query_add_counter_uint64(query, 5342, 24, NULL,acmgt3__ext797__pixel_2x2_lit_post_rasterizer_late_depth_slice5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext798_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext798";
   query->symbol_name = "Ext798";
   query->guid = "34cac917-42ff-4860-babe-cd0952722cd5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E032400 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0312E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18037000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030120 },
         { .reg = 0x00009888, .val = 0x1C037000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A052800 },
         { .reg = 0x00009888, .val = 0x1C05001C },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02053FC1 },
         { .reg = 0x00009888, .val = 0x04050CB1 },
         { .reg = 0x00009888, .val = 0x06050D33 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x0C05003C },
         { .reg = 0x00009888, .val = 0x0E05003D },
         { .reg = 0x00009888, .val = 0x1005003E },
         { .reg = 0x00009888, .val = 0x000655FF },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02081111 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext798__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext798__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext798__avg_gpu_core_frequency__max,acmgt3__ext798__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 6)) {
         intel_perf_query_add_counter_uint64(query, 5343, 24, NULL,acmgt3__ext798__pixel_2x2_lit_post_rasterizer_late_depth_slice6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext799_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext799";
   query->symbol_name = "Ext799";
   query->guid = "c7dcda7c-388d-4a21-8e24-dad58512c79d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2E080400 },
         { .reg = 0x00009888, .val = 0x30080018 },
         { .reg = 0x00009888, .val = 0x06081000 },
         { .reg = 0x00009888, .val = 0x10080CC0 },
         { .reg = 0x00009888, .val = 0x12080C80 },
         { .reg = 0x00009888, .val = 0x14080EC0 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022222 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02032249 },
         { .reg = 0x00009888, .val = 0x04031451 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E037000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A0339E0 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x1803F000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030380 },
         { .reg = 0x00009888, .val = 0x1C03F000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B052800 },
         { .reg = 0x00009888, .val = 0x1D05001C },
         { .reg = 0x00009888, .val = 0x000355FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02083333 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A1111 },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020B2222 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03053FC1 },
         { .reg = 0x00009888, .val = 0x05050CB1 },
         { .reg = 0x00009888, .val = 0x07050D33 },
         { .reg = 0x00009888, .val = 0x09050DB5 },
         { .reg = 0x00009888, .val = 0x0B05003B },
         { .reg = 0x00009888, .val = 0x0D05003C },
         { .reg = 0x00009888, .val = 0x0F05003D },
         { .reg = 0x00009888, .val = 0x1105003E },
         { .reg = 0x00009888, .val = 0x010655FF },
         { .reg = 0x00009888, .val = 0x01085555 },
         { .reg = 0x00009888, .val = 0x03081111 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A1111 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x000155FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02021111 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02041111 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02051111 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x02082222 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF080FEFE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF08000FE },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
         { .reg = 0x0000D908, .val = 0x1111111C },
         { .reg = 0x0000D91C, .val = 0x1111111E },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext799__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext799__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext799__avg_gpu_core_frequency__max,acmgt3__ext799__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 7)) {
         intel_perf_query_add_counter_uint64(query, 5344, 24, NULL,acmgt3__ext799__pixel_2x2_lit_post_rasterizer_late_depth_slice7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext800_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext800";
   query->symbol_name = "Ext800";
   query->guid = "1528d417-08e6-4356-863b-c860637abf66";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04858240 },
         { .reg = 0x00009888, .val = 0x06850B28 },
         { .reg = 0x00009888, .val = 0x088508A6 },
         { .reg = 0x00009888, .val = 0x0A850BAA },
         { .reg = 0x00009888, .val = 0x10850BEB },
         { .reg = 0x00009888, .val = 0x128509E3 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext800__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext800__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext800__avg_gpu_core_frequency__max,acmgt3__ext800__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1704, 24, NULL,acmgt3__ext800__rt_instance_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1705, 32, NULL,acmgt3__ext800__rt_internal_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1706, 40, NULL,acmgt3__ext800__rt_traversal_step_ray_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext801_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext801";
   query->symbol_name = "Ext801";
   query->guid = "b2263f12-501d-42b8-bcda-f63faa1ba105";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A58240 },
         { .reg = 0x00009888, .val = 0x06A50B28 },
         { .reg = 0x00009888, .val = 0x08A508A6 },
         { .reg = 0x00009888, .val = 0x0AA50BAA },
         { .reg = 0x00009888, .val = 0x10A50BEB },
         { .reg = 0x00009888, .val = 0x12A509E3 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AA00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext801__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext801__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext801__avg_gpu_core_frequency__max,acmgt3__ext801__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1707, 24, NULL,acmgt3__ext801__rt_instance_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1708, 32, NULL,acmgt3__ext801__rt_internal_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1709, 40, NULL,acmgt3__ext801__rt_traversal_step_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext802_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext802";
   query->symbol_name = "Ext802";
   query->guid = "5db30c72-78f5-4150-87c8-264d72199699";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C58240 },
         { .reg = 0x00009888, .val = 0x06C50B28 },
         { .reg = 0x00009888, .val = 0x08C508A6 },
         { .reg = 0x00009888, .val = 0x0AC50BAA },
         { .reg = 0x00009888, .val = 0x10C50BEB },
         { .reg = 0x00009888, .val = 0x12C509E3 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AA00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AA00 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext802__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext802__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext802__avg_gpu_core_frequency__max,acmgt3__ext802__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1710, 24, NULL,acmgt3__ext802__rt_instance_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1711, 32, NULL,acmgt3__ext802__rt_internal_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1712, 40, NULL,acmgt3__ext802__rt_traversal_step_ray_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext803_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext803";
   query->symbol_name = "Ext803";
   query->guid = "85f9346c-6b1e-4eb1-8ab7-69cdfcee678d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E58240 },
         { .reg = 0x00009888, .val = 0x06E50B28 },
         { .reg = 0x00009888, .val = 0x08E508A6 },
         { .reg = 0x00009888, .val = 0x0AE50BAA },
         { .reg = 0x00009888, .val = 0x10E50BEB },
         { .reg = 0x00009888, .val = 0x12E509E3 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext803__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext803__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext803__avg_gpu_core_frequency__max,acmgt3__ext803__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1713, 24, NULL,acmgt3__ext803__rt_instance_node_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1714, 32, NULL,acmgt3__ext803__rt_internal_node_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1715, 40, NULL,acmgt3__ext803__rt_traversal_step_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext804_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext804";
   query->symbol_name = "Ext804";
   query->guid = "ba52d055-bcb2-48ba-8c21-9f41517f81e7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05858240 },
         { .reg = 0x00009888, .val = 0x07850B28 },
         { .reg = 0x00009888, .val = 0x098508A6 },
         { .reg = 0x00009888, .val = 0x0B850BAA },
         { .reg = 0x00009888, .val = 0x11850BEB },
         { .reg = 0x00009888, .val = 0x138509E3 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AA00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext804__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext804__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext804__avg_gpu_core_frequency__max,acmgt3__ext804__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1716, 24, NULL,acmgt3__ext804__rt_instance_node_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1717, 32, NULL,acmgt3__ext804__rt_internal_node_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1718, 40, NULL,acmgt3__ext804__rt_traversal_step_ray_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext805_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext805";
   query->symbol_name = "Ext805";
   query->guid = "4b9170d3-8599-49da-a448-461ab6847b01";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A58240 },
         { .reg = 0x00009888, .val = 0x07A50B28 },
         { .reg = 0x00009888, .val = 0x09A508A6 },
         { .reg = 0x00009888, .val = 0x0BA50BAA },
         { .reg = 0x00009888, .val = 0x11A50BEB },
         { .reg = 0x00009888, .val = 0x13A509E3 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009888, .val = 0x0101F0FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext805__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext805__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext805__avg_gpu_core_frequency__max,acmgt3__ext805__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1719, 24, NULL,acmgt3__ext805__rt_instance_node_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1720, 32, NULL,acmgt3__ext805__rt_internal_node_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1721, 40, NULL,acmgt3__ext805__rt_traversal_step_ray_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext806_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext806";
   query->symbol_name = "Ext806";
   query->guid = "01f56dac-1c55-4720-8ecf-de58c295648a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C58240 },
         { .reg = 0x00009888, .val = 0x07C50B28 },
         { .reg = 0x00009888, .val = 0x09C508A6 },
         { .reg = 0x00009888, .val = 0x0BC50BAA },
         { .reg = 0x00009888, .val = 0x11C50BEB },
         { .reg = 0x00009888, .val = 0x13C509E3 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AA00 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009888, .val = 0x0102F0FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext806__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext806__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext806__avg_gpu_core_frequency__max,acmgt3__ext806__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1722, 24, NULL,acmgt3__ext806__rt_instance_node_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1723, 32, NULL,acmgt3__ext806__rt_internal_node_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1724, 40, NULL,acmgt3__ext806__rt_traversal_step_ray_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext807_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext807";
   query->symbol_name = "Ext807";
   query->guid = "bba5c945-2c0c-4e5a-8a85-233623f5a46e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E58240 },
         { .reg = 0x00009888, .val = 0x07E50B28 },
         { .reg = 0x00009888, .val = 0x09E508A6 },
         { .reg = 0x00009888, .val = 0x0BE50BAA },
         { .reg = 0x00009888, .val = 0x11E50BEB },
         { .reg = 0x00009888, .val = 0x13E509E3 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075500 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext807__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext807__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext807__avg_gpu_core_frequency__max,acmgt3__ext807__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1725, 24, NULL,acmgt3__ext807__rt_instance_node_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1726, 32, NULL,acmgt3__ext807__rt_internal_node_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1727, 40, NULL,acmgt3__ext807__rt_traversal_step_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext808_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext808";
   query->symbol_name = "Ext808";
   query->guid = "cbd45de0-0a72-4273-a133-04075a1b6606";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04858240 },
         { .reg = 0x00009888, .val = 0x06850B28 },
         { .reg = 0x00009888, .val = 0x088508A6 },
         { .reg = 0x00009888, .val = 0x0A850BAA },
         { .reg = 0x00009888, .val = 0x10850BEB },
         { .reg = 0x00009888, .val = 0x128509E3 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext808__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext808__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext808__avg_gpu_core_frequency__max,acmgt3__ext808__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2887, 24, NULL,acmgt3__ext808__rt_instance_node_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2888, 32, NULL,acmgt3__ext808__rt_internal_node_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2889, 40, NULL,acmgt3__ext808__rt_traversal_step_ray_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext809_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext809";
   query->symbol_name = "Ext809";
   query->guid = "c5dd3d85-c642-4bab-9b0d-a5cf7516fd9b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A58240 },
         { .reg = 0x00009888, .val = 0x06A50B28 },
         { .reg = 0x00009888, .val = 0x08A508A6 },
         { .reg = 0x00009888, .val = 0x0AA50BAA },
         { .reg = 0x00009888, .val = 0x10A50BEB },
         { .reg = 0x00009888, .val = 0x12A509E3 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AA00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext809__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext809__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext809__avg_gpu_core_frequency__max,acmgt3__ext809__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2890, 24, NULL,acmgt3__ext809__rt_instance_node_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2891, 32, NULL,acmgt3__ext809__rt_internal_node_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2892, 40, NULL,acmgt3__ext809__rt_traversal_step_ray_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext810_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext810";
   query->symbol_name = "Ext810";
   query->guid = "311d6164-1ed7-416c-b029-e4ce8b6c7bf2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C58240 },
         { .reg = 0x00009888, .val = 0x06C50B28 },
         { .reg = 0x00009888, .val = 0x08C508A6 },
         { .reg = 0x00009888, .val = 0x0AC50BAA },
         { .reg = 0x00009888, .val = 0x10C50BEB },
         { .reg = 0x00009888, .val = 0x12C509E3 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AA00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AA00 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext810__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext810__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext810__avg_gpu_core_frequency__max,acmgt3__ext810__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2893, 24, NULL,acmgt3__ext810__rt_instance_node_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2894, 32, NULL,acmgt3__ext810__rt_internal_node_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2895, 40, NULL,acmgt3__ext810__rt_traversal_step_ray_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext811_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext811";
   query->symbol_name = "Ext811";
   query->guid = "a75430da-ab08-4b44-abf4-21de4a98210d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E58240 },
         { .reg = 0x00009888, .val = 0x06E50B28 },
         { .reg = 0x00009888, .val = 0x08E508A6 },
         { .reg = 0x00009888, .val = 0x0AE50BAA },
         { .reg = 0x00009888, .val = 0x10E50BEB },
         { .reg = 0x00009888, .val = 0x12E509E3 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext811__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext811__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext811__avg_gpu_core_frequency__max,acmgt3__ext811__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2896, 24, NULL,acmgt3__ext811__rt_instance_node_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2897, 32, NULL,acmgt3__ext811__rt_internal_node_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2898, 40, NULL,acmgt3__ext811__rt_traversal_step_ray_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext812_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext812";
   query->symbol_name = "Ext812";
   query->guid = "b50ad38b-7555-47d2-a46c-257ba01fa79e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05858240 },
         { .reg = 0x00009888, .val = 0x07850B28 },
         { .reg = 0x00009888, .val = 0x098508A6 },
         { .reg = 0x00009888, .val = 0x0B850BAA },
         { .reg = 0x00009888, .val = 0x11850BEB },
         { .reg = 0x00009888, .val = 0x138509E3 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AA00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext812__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext812__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext812__avg_gpu_core_frequency__max,acmgt3__ext812__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2899, 24, NULL,acmgt3__ext812__rt_instance_node_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2900, 32, NULL,acmgt3__ext812__rt_internal_node_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2901, 40, NULL,acmgt3__ext812__rt_traversal_step_ray_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext813_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext813";
   query->symbol_name = "Ext813";
   query->guid = "04682809-a9ee-4ef2-a4a7-9d65454305df";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A58240 },
         { .reg = 0x00009888, .val = 0x07A50B28 },
         { .reg = 0x00009888, .val = 0x09A508A6 },
         { .reg = 0x00009888, .val = 0x0BA50BAA },
         { .reg = 0x00009888, .val = 0x11A50BEB },
         { .reg = 0x00009888, .val = 0x13A509E3 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009888, .val = 0x0101F0FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext813__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext813__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext813__avg_gpu_core_frequency__max,acmgt3__ext813__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2902, 24, NULL,acmgt3__ext813__rt_instance_node_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2903, 32, NULL,acmgt3__ext813__rt_internal_node_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2904, 40, NULL,acmgt3__ext813__rt_traversal_step_ray_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext814_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext814";
   query->symbol_name = "Ext814";
   query->guid = "b8213dc4-d664-4c60-8a93-4eefb9a35c72";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C58240 },
         { .reg = 0x00009888, .val = 0x07C50B28 },
         { .reg = 0x00009888, .val = 0x09C508A6 },
         { .reg = 0x00009888, .val = 0x0BC50BAA },
         { .reg = 0x00009888, .val = 0x11C50BEB },
         { .reg = 0x00009888, .val = 0x13C509E3 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AA00 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009888, .val = 0x0102F0FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext814__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext814__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext814__avg_gpu_core_frequency__max,acmgt3__ext814__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2905, 24, NULL,acmgt3__ext814__rt_instance_node_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2906, 32, NULL,acmgt3__ext814__rt_internal_node_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2907, 40, NULL,acmgt3__ext814__rt_traversal_step_ray_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext815_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext815";
   query->symbol_name = "Ext815";
   query->guid = "b62ea20f-c05b-4817-81c1-d79e28df757c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E58240 },
         { .reg = 0x00009888, .val = 0x07E50B28 },
         { .reg = 0x00009888, .val = 0x09E508A6 },
         { .reg = 0x00009888, .val = 0x0BE50BAA },
         { .reg = 0x00009888, .val = 0x11E50BEB },
         { .reg = 0x00009888, .val = 0x13E509E3 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075500 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02030092 },
         { .reg = 0x00009888, .val = 0x04032480 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext815__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext815__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext815__avg_gpu_core_frequency__max,acmgt3__ext815__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2908, 24, NULL,acmgt3__ext815__rt_instance_node_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2909, 32, NULL,acmgt3__ext815__rt_internal_node_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2910, 40, NULL,acmgt3__ext815__rt_traversal_step_ray_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext816_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext816";
   query->symbol_name = "Ext816";
   query->guid = "6670d652-d39b-4d76-98f5-c12c50440f15";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04858240 },
         { .reg = 0x00009888, .val = 0x06850B28 },
         { .reg = 0x00009888, .val = 0x088508A6 },
         { .reg = 0x00009888, .val = 0x0A850BAA },
         { .reg = 0x00009888, .val = 0x10850BEB },
         { .reg = 0x00009888, .val = 0x128509E3 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext816__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext816__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext816__avg_gpu_core_frequency__max,acmgt3__ext816__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5345, 24, NULL,acmgt3__ext816__rt_instance_node_ray_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5346, 32, NULL,acmgt3__ext816__rt_internal_node_ray_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5347, 40, NULL,acmgt3__ext816__rt_traversal_step_ray_count_xecore16__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext817_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext817";
   query->symbol_name = "Ext817";
   query->guid = "5e08ce48-10e9-4321-b042-480df816d469";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A58240 },
         { .reg = 0x00009888, .val = 0x06A50B28 },
         { .reg = 0x00009888, .val = 0x08A508A6 },
         { .reg = 0x00009888, .val = 0x0AA50BAA },
         { .reg = 0x00009888, .val = 0x10A50BEB },
         { .reg = 0x00009888, .val = 0x12A509E3 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AA00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext817__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext817__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext817__avg_gpu_core_frequency__max,acmgt3__ext817__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5348, 24, NULL,acmgt3__ext817__rt_instance_node_ray_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5349, 32, NULL,acmgt3__ext817__rt_internal_node_ray_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5350, 40, NULL,acmgt3__ext817__rt_traversal_step_ray_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext818_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext818";
   query->symbol_name = "Ext818";
   query->guid = "c422c5d1-a02c-48b4-96df-9b8875974dc3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C58240 },
         { .reg = 0x00009888, .val = 0x06C50B28 },
         { .reg = 0x00009888, .val = 0x08C508A6 },
         { .reg = 0x00009888, .val = 0x0AC50BAA },
         { .reg = 0x00009888, .val = 0x10C50BEB },
         { .reg = 0x00009888, .val = 0x12C509E3 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AA00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AA00 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext818__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext818__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext818__avg_gpu_core_frequency__max,acmgt3__ext818__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5351, 24, NULL,acmgt3__ext818__rt_instance_node_ray_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5352, 32, NULL,acmgt3__ext818__rt_internal_node_ray_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5353, 40, NULL,acmgt3__ext818__rt_traversal_step_ray_count_xecore18__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext819_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext819";
   query->symbol_name = "Ext819";
   query->guid = "4a75128f-63bb-48d5-a888-ab44203de10a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E58240 },
         { .reg = 0x00009888, .val = 0x06E50B28 },
         { .reg = 0x00009888, .val = 0x08E508A6 },
         { .reg = 0x00009888, .val = 0x0AE50BAA },
         { .reg = 0x00009888, .val = 0x10E50BEB },
         { .reg = 0x00009888, .val = 0x12E509E3 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext819__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext819__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext819__avg_gpu_core_frequency__max,acmgt3__ext819__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5354, 24, NULL,acmgt3__ext819__rt_instance_node_ray_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5355, 32, NULL,acmgt3__ext819__rt_internal_node_ray_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5356, 40, NULL,acmgt3__ext819__rt_traversal_step_ray_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext820_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext820";
   query->symbol_name = "Ext820";
   query->guid = "43ba1de5-4b19-4c2c-b009-0cdf4c84c85f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05858240 },
         { .reg = 0x00009888, .val = 0x07850B28 },
         { .reg = 0x00009888, .val = 0x098508A6 },
         { .reg = 0x00009888, .val = 0x0B850BAA },
         { .reg = 0x00009888, .val = 0x11850BEB },
         { .reg = 0x00009888, .val = 0x138509E3 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AA00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext820__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext820__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext820__avg_gpu_core_frequency__max,acmgt3__ext820__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5357, 24, NULL,acmgt3__ext820__rt_instance_node_ray_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5358, 32, NULL,acmgt3__ext820__rt_internal_node_ray_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5359, 40, NULL,acmgt3__ext820__rt_traversal_step_ray_count_xecore20__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext821_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext821";
   query->symbol_name = "Ext821";
   query->guid = "f9881b7a-0445-44f3-a681-38a8a96179d5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A58240 },
         { .reg = 0x00009888, .val = 0x07A50B28 },
         { .reg = 0x00009888, .val = 0x09A508A6 },
         { .reg = 0x00009888, .val = 0x0BA50BAA },
         { .reg = 0x00009888, .val = 0x11A50BEB },
         { .reg = 0x00009888, .val = 0x13A509E3 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009888, .val = 0x0101F0FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext821__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext821__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext821__avg_gpu_core_frequency__max,acmgt3__ext821__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5360, 24, NULL,acmgt3__ext821__rt_instance_node_ray_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5361, 32, NULL,acmgt3__ext821__rt_internal_node_ray_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5362, 40, NULL,acmgt3__ext821__rt_traversal_step_ray_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext822_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext822";
   query->symbol_name = "Ext822";
   query->guid = "0ba4ce29-a0aa-4a5e-8a95-005675a4a7d2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C58240 },
         { .reg = 0x00009888, .val = 0x07C50B28 },
         { .reg = 0x00009888, .val = 0x09C508A6 },
         { .reg = 0x00009888, .val = 0x0BC50BAA },
         { .reg = 0x00009888, .val = 0x11C50BEB },
         { .reg = 0x00009888, .val = 0x13C509E3 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AA00 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009888, .val = 0x0102F0FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext822__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext822__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext822__avg_gpu_core_frequency__max,acmgt3__ext822__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5363, 24, NULL,acmgt3__ext822__rt_instance_node_ray_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5364, 32, NULL,acmgt3__ext822__rt_internal_node_ray_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5365, 40, NULL,acmgt3__ext822__rt_traversal_step_ray_count_xecore22__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext823_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext823";
   query->symbol_name = "Ext823";
   query->guid = "a6008e79-794a-433b-8236-5b0cc13bb166";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E58240 },
         { .reg = 0x00009888, .val = 0x07E50B28 },
         { .reg = 0x00009888, .val = 0x09E508A6 },
         { .reg = 0x00009888, .val = 0x0BE50BAA },
         { .reg = 0x00009888, .val = 0x11E50BEB },
         { .reg = 0x00009888, .val = 0x13E509E3 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075500 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext823__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext823__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext823__avg_gpu_core_frequency__max,acmgt3__ext823__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5366, 24, NULL,acmgt3__ext823__rt_instance_node_ray_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5367, 32, NULL,acmgt3__ext823__rt_internal_node_ray_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5368, 40, NULL,acmgt3__ext823__rt_traversal_step_ray_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext824_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext824";
   query->symbol_name = "Ext824";
   query->guid = "7293c8c9-c859-4f6d-a9e1-7245a5dd2ad5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04858240 },
         { .reg = 0x00009888, .val = 0x06850B28 },
         { .reg = 0x00009888, .val = 0x088508A6 },
         { .reg = 0x00009888, .val = 0x0A850BAA },
         { .reg = 0x00009888, .val = 0x10850BEB },
         { .reg = 0x00009888, .val = 0x128509E3 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext824__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext824__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext824__avg_gpu_core_frequency__max,acmgt3__ext824__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5369, 24, NULL,acmgt3__ext824__rt_instance_node_ray_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5370, 32, NULL,acmgt3__ext824__rt_internal_node_ray_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5371, 40, NULL,acmgt3__ext824__rt_traversal_step_ray_count_xecore24__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext825_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext825";
   query->symbol_name = "Ext825";
   query->guid = "703e8945-2aba-4163-be6d-46dfc2026a4c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A58240 },
         { .reg = 0x00009888, .val = 0x06A50B28 },
         { .reg = 0x00009888, .val = 0x08A508A6 },
         { .reg = 0x00009888, .val = 0x0AA50BAA },
         { .reg = 0x00009888, .val = 0x10A50BEB },
         { .reg = 0x00009888, .val = 0x12A509E3 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AA00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext825__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext825__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext825__avg_gpu_core_frequency__max,acmgt3__ext825__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5372, 24, NULL,acmgt3__ext825__rt_instance_node_ray_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5373, 32, NULL,acmgt3__ext825__rt_internal_node_ray_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5374, 40, NULL,acmgt3__ext825__rt_traversal_step_ray_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext826_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext826";
   query->symbol_name = "Ext826";
   query->guid = "86fe7724-e6d6-4cb8-be2f-e5974a7f09c3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C58240 },
         { .reg = 0x00009888, .val = 0x06C50B28 },
         { .reg = 0x00009888, .val = 0x08C508A6 },
         { .reg = 0x00009888, .val = 0x0AC50BAA },
         { .reg = 0x00009888, .val = 0x10C50BEB },
         { .reg = 0x00009888, .val = 0x12C509E3 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AA00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AA00 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext826__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext826__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext826__avg_gpu_core_frequency__max,acmgt3__ext826__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5375, 24, NULL,acmgt3__ext826__rt_instance_node_ray_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5376, 32, NULL,acmgt3__ext826__rt_internal_node_ray_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5377, 40, NULL,acmgt3__ext826__rt_traversal_step_ray_count_xecore26__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext827_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext827";
   query->symbol_name = "Ext827";
   query->guid = "7cdb9b53-1702-4343-bbe1-f82a5a7f0e90";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E58240 },
         { .reg = 0x00009888, .val = 0x06E50B28 },
         { .reg = 0x00009888, .val = 0x08E508A6 },
         { .reg = 0x00009888, .val = 0x0AE50BAA },
         { .reg = 0x00009888, .val = 0x10E50BEB },
         { .reg = 0x00009888, .val = 0x12E509E3 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AA00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075500 },
         { .reg = 0x00009888, .val = 0x0009F0FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext827__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext827__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext827__avg_gpu_core_frequency__max,acmgt3__ext827__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5378, 24, NULL,acmgt3__ext827__rt_instance_node_ray_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5379, 32, NULL,acmgt3__ext827__rt_internal_node_ray_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5380, 40, NULL,acmgt3__ext827__rt_traversal_step_ray_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext828_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext828";
   query->symbol_name = "Ext828";
   query->guid = "49835d12-bfcd-41c8-aab2-623fb75e5af1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05858240 },
         { .reg = 0x00009888, .val = 0x07850B28 },
         { .reg = 0x00009888, .val = 0x098508A6 },
         { .reg = 0x00009888, .val = 0x0B850BAA },
         { .reg = 0x00009888, .val = 0x11850BEB },
         { .reg = 0x00009888, .val = 0x138509E3 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AA00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext828__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext828__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext828__avg_gpu_core_frequency__max,acmgt3__ext828__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5381, 24, NULL,acmgt3__ext828__rt_instance_node_ray_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5382, 32, NULL,acmgt3__ext828__rt_internal_node_ray_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5383, 40, NULL,acmgt3__ext828__rt_traversal_step_ray_count_xecore28__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext829_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext829";
   query->symbol_name = "Ext829";
   query->guid = "bfdd0f51-5128-4a1f-aaa0-02fca7613300";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A58240 },
         { .reg = 0x00009888, .val = 0x07A50B28 },
         { .reg = 0x00009888, .val = 0x09A508A6 },
         { .reg = 0x00009888, .val = 0x0BA50BAA },
         { .reg = 0x00009888, .val = 0x11A50BEB },
         { .reg = 0x00009888, .val = 0x13A509E3 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FF00 },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5500 },
         { .reg = 0x00009888, .val = 0x0101F0FF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext829__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext829__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext829__avg_gpu_core_frequency__max,acmgt3__ext829__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5384, 24, NULL,acmgt3__ext829__rt_instance_node_ray_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5385, 32, NULL,acmgt3__ext829__rt_internal_node_ray_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5386, 40, NULL,acmgt3__ext829__rt_traversal_step_ray_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext830_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext830";
   query->symbol_name = "Ext830";
   query->guid = "2b893c3a-2f78-4e0e-aa92-bc332d6d1f0f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C58240 },
         { .reg = 0x00009888, .val = 0x07C50B28 },
         { .reg = 0x00009888, .val = 0x09C508A6 },
         { .reg = 0x00009888, .val = 0x0BC50BAA },
         { .reg = 0x00009888, .val = 0x11C50BEB },
         { .reg = 0x00009888, .val = 0x13C509E3 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AA00 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009888, .val = 0x0102F0FF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext830__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext830__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext830__avg_gpu_core_frequency__max,acmgt3__ext830__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5387, 24, NULL,acmgt3__ext830__rt_instance_node_ray_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5388, 32, NULL,acmgt3__ext830__rt_internal_node_ray_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5389, 40, NULL,acmgt3__ext830__rt_traversal_step_ray_count_xecore30__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext831_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext831";
   query->symbol_name = "Ext831";
   query->guid = "df89b9fa-509e-4980-be3f-a9fc3604e079";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E58240 },
         { .reg = 0x00009888, .val = 0x07E50B28 },
         { .reg = 0x00009888, .val = 0x09E508A6 },
         { .reg = 0x00009888, .val = 0x0BE50BAA },
         { .reg = 0x00009888, .val = 0x11E50BEB },
         { .reg = 0x00009888, .val = 0x13E509E3 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AA00 },
         { .reg = 0x00009888, .val = 0x0003F0FF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5500 },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAA00 },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075500 },
         { .reg = 0x00009888, .val = 0x0109F0FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02030049 },
         { .reg = 0x00009888, .val = 0x04031240 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001F0FF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055500 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00020012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00008022 },
         { .reg = 0x0000D954, .val = 0x0000EFFB },
         { .reg = 0x0000D958, .val = 0x00010042 },
         { .reg = 0x0000D95C, .val = 0x0000DFF7 },
         { .reg = 0x0000D960, .val = 0x00040082 },
         { .reg = 0x0000D964, .val = 0x00007FEF },
         { .reg = 0x0000D968, .val = 0x00020102 },
         { .reg = 0x0000D96C, .val = 0x0000BFDF },
         { .reg = 0x0000D970, .val = 0x00008202 },
         { .reg = 0x0000D974, .val = 0x0000EFBF },
         { .reg = 0x0000D978, .val = 0x00010402 },
         { .reg = 0x0000D97C, .val = 0x0000DF7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext831__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext831__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext831__avg_gpu_core_frequency__max,acmgt3__ext831__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5390, 24, NULL,acmgt3__ext831__rt_instance_node_ray_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5391, 32, NULL,acmgt3__ext831__rt_internal_node_ray_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5392, 40, NULL,acmgt3__ext831__rt_traversal_step_ray_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext832_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext832";
   query->symbol_name = "Ext832";
   query->guid = "d6a49316-ce8d-467e-930f-66f89748d7f6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04859A70 },
         { .reg = 0x00009888, .val = 0x06850925 },
         { .reg = 0x00009888, .val = 0x088508A3 },
         { .reg = 0x00009888, .val = 0x0A850821 },
         { .reg = 0x00009888, .val = 0x0C850BAF },
         { .reg = 0x00009888, .val = 0x0E850B2D },
         { .reg = 0x00009888, .val = 0x10850AAB },
         { .reg = 0x00009888, .val = 0x12850A29 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AAAA },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext832__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext832__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext832__avg_gpu_core_frequency__max,acmgt3__ext832__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1728, 24, NULL,acmgt3__ext832__rt_quad_leaf_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1729, 32, NULL,acmgt3__ext832__rt_procedural_node_ray_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext833_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext833";
   query->symbol_name = "Ext833";
   query->guid = "82b22389-9176-4be3-8cf7-ebeb1db973fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A59A70 },
         { .reg = 0x00009888, .val = 0x06A50925 },
         { .reg = 0x00009888, .val = 0x08A508A3 },
         { .reg = 0x00009888, .val = 0x0AA50821 },
         { .reg = 0x00009888, .val = 0x0CA50BAF },
         { .reg = 0x00009888, .val = 0x0EA50B2D },
         { .reg = 0x00009888, .val = 0x10A50AAB },
         { .reg = 0x00009888, .val = 0x12A50A29 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AAAA },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext833__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext833__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext833__avg_gpu_core_frequency__max,acmgt3__ext833__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1730, 24, NULL,acmgt3__ext833__rt_quad_leaf_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1731, 32, NULL,acmgt3__ext833__rt_procedural_node_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext834_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext834";
   query->symbol_name = "Ext834";
   query->guid = "c1e9d6fe-8cd9-4c83-b9ec-5669c16e51ca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C59A70 },
         { .reg = 0x00009888, .val = 0x06C50925 },
         { .reg = 0x00009888, .val = 0x08C508A3 },
         { .reg = 0x00009888, .val = 0x0AC50821 },
         { .reg = 0x00009888, .val = 0x0CC50BAF },
         { .reg = 0x00009888, .val = 0x0EC50B2D },
         { .reg = 0x00009888, .val = 0x10C50AAB },
         { .reg = 0x00009888, .val = 0x12C50A29 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AAAA },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext834__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext834__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext834__avg_gpu_core_frequency__max,acmgt3__ext834__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1732, 24, NULL,acmgt3__ext834__rt_quad_leaf_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1733, 32, NULL,acmgt3__ext834__rt_procedural_node_ray_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext835_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext835";
   query->symbol_name = "Ext835";
   query->guid = "ef2c993e-ea71-4d00-81eb-a4192d00cd5d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E59A70 },
         { .reg = 0x00009888, .val = 0x06E50925 },
         { .reg = 0x00009888, .val = 0x08E508A3 },
         { .reg = 0x00009888, .val = 0x0AE50821 },
         { .reg = 0x00009888, .val = 0x0CE50BAF },
         { .reg = 0x00009888, .val = 0x0EE50B2D },
         { .reg = 0x00009888, .val = 0x10E50AAB },
         { .reg = 0x00009888, .val = 0x12E50A29 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AAAA },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext835__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext835__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext835__avg_gpu_core_frequency__max,acmgt3__ext835__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1734, 24, NULL,acmgt3__ext835__rt_quad_leaf_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1735, 32, NULL,acmgt3__ext835__rt_procedural_node_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext836_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext836";
   query->symbol_name = "Ext836";
   query->guid = "e4a9361e-d864-4368-8129-9171a70c6ab3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05859A70 },
         { .reg = 0x00009888, .val = 0x07850925 },
         { .reg = 0x00009888, .val = 0x098508A3 },
         { .reg = 0x00009888, .val = 0x0B850821 },
         { .reg = 0x00009888, .val = 0x0D850BAF },
         { .reg = 0x00009888, .val = 0x0F850B2D },
         { .reg = 0x00009888, .val = 0x11850AAB },
         { .reg = 0x00009888, .val = 0x13850A29 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext836__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext836__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext836__avg_gpu_core_frequency__max,acmgt3__ext836__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1736, 24, NULL,acmgt3__ext836__rt_quad_leaf_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1737, 32, NULL,acmgt3__ext836__rt_procedural_node_ray_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext837_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext837";
   query->symbol_name = "Ext837";
   query->guid = "5157b0b6-6842-4d74-afc5-e9cfc011b13f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A59A70 },
         { .reg = 0x00009888, .val = 0x07A50925 },
         { .reg = 0x00009888, .val = 0x09A508A3 },
         { .reg = 0x00009888, .val = 0x0BA50821 },
         { .reg = 0x00009888, .val = 0x0DA50BAF },
         { .reg = 0x00009888, .val = 0x0FA50B2D },
         { .reg = 0x00009888, .val = 0x11A50AAB },
         { .reg = 0x00009888, .val = 0x13A50A29 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext837__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext837__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext837__avg_gpu_core_frequency__max,acmgt3__ext837__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1738, 24, NULL,acmgt3__ext837__rt_quad_leaf_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1739, 32, NULL,acmgt3__ext837__rt_procedural_node_ray_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext838_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext838";
   query->symbol_name = "Ext838";
   query->guid = "317eb78e-5fd5-4c28-8d28-c0b9e7ec3f4c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C59A70 },
         { .reg = 0x00009888, .val = 0x07C50925 },
         { .reg = 0x00009888, .val = 0x09C508A3 },
         { .reg = 0x00009888, .val = 0x0BC50821 },
         { .reg = 0x00009888, .val = 0x0DC50BAF },
         { .reg = 0x00009888, .val = 0x0FC50B2D },
         { .reg = 0x00009888, .val = 0x11C50AAB },
         { .reg = 0x00009888, .val = 0x13C50A29 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext838__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext838__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext838__avg_gpu_core_frequency__max,acmgt3__ext838__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1740, 24, NULL,acmgt3__ext838__rt_quad_leaf_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1741, 32, NULL,acmgt3__ext838__rt_procedural_node_ray_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext839_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext839";
   query->symbol_name = "Ext839";
   query->guid = "e92851dc-f040-4f09-8241-78bc01faeb85";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E59A70 },
         { .reg = 0x00009888, .val = 0x07E50925 },
         { .reg = 0x00009888, .val = 0x09E508A3 },
         { .reg = 0x00009888, .val = 0x0BE50821 },
         { .reg = 0x00009888, .val = 0x0DE50BAF },
         { .reg = 0x00009888, .val = 0x0FE50B2D },
         { .reg = 0x00009888, .val = 0x11E50AAB },
         { .reg = 0x00009888, .val = 0x13E50A29 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext839__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext839__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext839__avg_gpu_core_frequency__max,acmgt3__ext839__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1742, 24, NULL,acmgt3__ext839__rt_quad_leaf_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1743, 32, NULL,acmgt3__ext839__rt_procedural_node_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext840_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext840";
   query->symbol_name = "Ext840";
   query->guid = "79e2fa72-7478-4392-bdf7-9b5f13d97dde";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04859A70 },
         { .reg = 0x00009888, .val = 0x06850925 },
         { .reg = 0x00009888, .val = 0x088508A3 },
         { .reg = 0x00009888, .val = 0x0A850821 },
         { .reg = 0x00009888, .val = 0x0C850BAF },
         { .reg = 0x00009888, .val = 0x0E850B2D },
         { .reg = 0x00009888, .val = 0x10850AAB },
         { .reg = 0x00009888, .val = 0x12850A29 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AAAA },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext840__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext840__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext840__avg_gpu_core_frequency__max,acmgt3__ext840__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2911, 24, NULL,acmgt3__ext840__rt_quad_leaf_ray_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2912, 32, NULL,acmgt3__ext840__rt_procedural_node_ray_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext841_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext841";
   query->symbol_name = "Ext841";
   query->guid = "8f581530-9676-4f41-9eab-c14b99208ff1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A59A70 },
         { .reg = 0x00009888, .val = 0x06A50925 },
         { .reg = 0x00009888, .val = 0x08A508A3 },
         { .reg = 0x00009888, .val = 0x0AA50821 },
         { .reg = 0x00009888, .val = 0x0CA50BAF },
         { .reg = 0x00009888, .val = 0x0EA50B2D },
         { .reg = 0x00009888, .val = 0x10A50AAB },
         { .reg = 0x00009888, .val = 0x12A50A29 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AAAA },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext841__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext841__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext841__avg_gpu_core_frequency__max,acmgt3__ext841__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2913, 24, NULL,acmgt3__ext841__rt_quad_leaf_ray_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2914, 32, NULL,acmgt3__ext841__rt_procedural_node_ray_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext842_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext842";
   query->symbol_name = "Ext842";
   query->guid = "48da56da-a122-4bde-8004-d5db9d488322";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C59A70 },
         { .reg = 0x00009888, .val = 0x06C50925 },
         { .reg = 0x00009888, .val = 0x08C508A3 },
         { .reg = 0x00009888, .val = 0x0AC50821 },
         { .reg = 0x00009888, .val = 0x0CC50BAF },
         { .reg = 0x00009888, .val = 0x0EC50B2D },
         { .reg = 0x00009888, .val = 0x10C50AAB },
         { .reg = 0x00009888, .val = 0x12C50A29 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AAAA },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext842__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext842__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext842__avg_gpu_core_frequency__max,acmgt3__ext842__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2915, 24, NULL,acmgt3__ext842__rt_quad_leaf_ray_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2916, 32, NULL,acmgt3__ext842__rt_procedural_node_ray_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext843_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext843";
   query->symbol_name = "Ext843";
   query->guid = "b101af1b-2ecb-4f87-b85f-d3fb1e7d081f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E59A70 },
         { .reg = 0x00009888, .val = 0x06E50925 },
         { .reg = 0x00009888, .val = 0x08E508A3 },
         { .reg = 0x00009888, .val = 0x0AE50821 },
         { .reg = 0x00009888, .val = 0x0CE50BAF },
         { .reg = 0x00009888, .val = 0x0EE50B2D },
         { .reg = 0x00009888, .val = 0x10E50AAB },
         { .reg = 0x00009888, .val = 0x12E50A29 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AAAA },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext843__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext843__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext843__avg_gpu_core_frequency__max,acmgt3__ext843__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2917, 24, NULL,acmgt3__ext843__rt_quad_leaf_ray_count_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2918, 32, NULL,acmgt3__ext843__rt_procedural_node_ray_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext844_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext844";
   query->symbol_name = "Ext844";
   query->guid = "2cbe2a2f-61bf-4dde-9fa6-89fbe658cbe8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05859A70 },
         { .reg = 0x00009888, .val = 0x07850925 },
         { .reg = 0x00009888, .val = 0x098508A3 },
         { .reg = 0x00009888, .val = 0x0B850821 },
         { .reg = 0x00009888, .val = 0x0D850BAF },
         { .reg = 0x00009888, .val = 0x0F850B2D },
         { .reg = 0x00009888, .val = 0x11850AAB },
         { .reg = 0x00009888, .val = 0x13850A29 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext844__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext844__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext844__avg_gpu_core_frequency__max,acmgt3__ext844__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2919, 24, NULL,acmgt3__ext844__rt_quad_leaf_ray_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2920, 32, NULL,acmgt3__ext844__rt_procedural_node_ray_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext845_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext845";
   query->symbol_name = "Ext845";
   query->guid = "57ac6b30-2145-47c9-a05d-51cde53af72d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A59A70 },
         { .reg = 0x00009888, .val = 0x07A50925 },
         { .reg = 0x00009888, .val = 0x09A508A3 },
         { .reg = 0x00009888, .val = 0x0BA50821 },
         { .reg = 0x00009888, .val = 0x0DA50BAF },
         { .reg = 0x00009888, .val = 0x0FA50B2D },
         { .reg = 0x00009888, .val = 0x11A50AAB },
         { .reg = 0x00009888, .val = 0x13A50A29 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext845__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext845__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext845__avg_gpu_core_frequency__max,acmgt3__ext845__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2921, 24, NULL,acmgt3__ext845__rt_quad_leaf_ray_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2922, 32, NULL,acmgt3__ext845__rt_procedural_node_ray_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext846_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext846";
   query->symbol_name = "Ext846";
   query->guid = "4477cd4a-90b5-4ae4-b910-4ffe26ce08eb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C59A70 },
         { .reg = 0x00009888, .val = 0x07C50925 },
         { .reg = 0x00009888, .val = 0x09C508A3 },
         { .reg = 0x00009888, .val = 0x0BC50821 },
         { .reg = 0x00009888, .val = 0x0DC50BAF },
         { .reg = 0x00009888, .val = 0x0FC50B2D },
         { .reg = 0x00009888, .val = 0x11C50AAB },
         { .reg = 0x00009888, .val = 0x13C50A29 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext846__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext846__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext846__avg_gpu_core_frequency__max,acmgt3__ext846__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2923, 24, NULL,acmgt3__ext846__rt_quad_leaf_ray_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2924, 32, NULL,acmgt3__ext846__rt_procedural_node_ray_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext847_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext847";
   query->symbol_name = "Ext847";
   query->guid = "9c491ff6-caca-48c7-8f9a-9e2fcdff732d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E59A70 },
         { .reg = 0x00009888, .val = 0x07E50925 },
         { .reg = 0x00009888, .val = 0x09E508A3 },
         { .reg = 0x00009888, .val = 0x0BE50821 },
         { .reg = 0x00009888, .val = 0x0DE50BAF },
         { .reg = 0x00009888, .val = 0x0FE50B2D },
         { .reg = 0x00009888, .val = 0x11E50AAB },
         { .reg = 0x00009888, .val = 0x13E50A29 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext847__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext847__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext847__avg_gpu_core_frequency__max,acmgt3__ext847__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2925, 24, NULL,acmgt3__ext847__rt_quad_leaf_ray_count_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2926, 32, NULL,acmgt3__ext847__rt_procedural_node_ray_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext848_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext848";
   query->symbol_name = "Ext848";
   query->guid = "5d9982c1-e290-475d-8a42-460a08e42b71";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04859A70 },
         { .reg = 0x00009888, .val = 0x06850925 },
         { .reg = 0x00009888, .val = 0x088508A3 },
         { .reg = 0x00009888, .val = 0x0A850821 },
         { .reg = 0x00009888, .val = 0x0C850BAF },
         { .reg = 0x00009888, .val = 0x0E850B2D },
         { .reg = 0x00009888, .val = 0x10850AAB },
         { .reg = 0x00009888, .val = 0x12850A29 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AAAA },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext848__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext848__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext848__avg_gpu_core_frequency__max,acmgt3__ext848__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5393, 24, NULL,acmgt3__ext848__rt_quad_leaf_ray_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5394, 32, NULL,acmgt3__ext848__rt_procedural_node_ray_count_xecore16__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext849_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext849";
   query->symbol_name = "Ext849";
   query->guid = "86619a01-e374-4120-91c3-77009f623ebf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A59A70 },
         { .reg = 0x00009888, .val = 0x06A50925 },
         { .reg = 0x00009888, .val = 0x08A508A3 },
         { .reg = 0x00009888, .val = 0x0AA50821 },
         { .reg = 0x00009888, .val = 0x0CA50BAF },
         { .reg = 0x00009888, .val = 0x0EA50B2D },
         { .reg = 0x00009888, .val = 0x10A50AAB },
         { .reg = 0x00009888, .val = 0x12A50A29 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AAAA },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext849__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext849__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext849__avg_gpu_core_frequency__max,acmgt3__ext849__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5395, 24, NULL,acmgt3__ext849__rt_quad_leaf_ray_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5396, 32, NULL,acmgt3__ext849__rt_procedural_node_ray_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext850_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext850";
   query->symbol_name = "Ext850";
   query->guid = "0bd94d4e-4ad7-4fb3-bc31-5a602fb2712a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C59A70 },
         { .reg = 0x00009888, .val = 0x06C50925 },
         { .reg = 0x00009888, .val = 0x08C508A3 },
         { .reg = 0x00009888, .val = 0x0AC50821 },
         { .reg = 0x00009888, .val = 0x0CC50BAF },
         { .reg = 0x00009888, .val = 0x0EC50B2D },
         { .reg = 0x00009888, .val = 0x10C50AAB },
         { .reg = 0x00009888, .val = 0x12C50A29 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AAAA },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext850__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext850__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext850__avg_gpu_core_frequency__max,acmgt3__ext850__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5397, 24, NULL,acmgt3__ext850__rt_quad_leaf_ray_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5398, 32, NULL,acmgt3__ext850__rt_procedural_node_ray_count_xecore18__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext851_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext851";
   query->symbol_name = "Ext851";
   query->guid = "ce2ff90c-1370-44ef-8cf4-00af4b13faa5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E59A70 },
         { .reg = 0x00009888, .val = 0x06E50925 },
         { .reg = 0x00009888, .val = 0x08E508A3 },
         { .reg = 0x00009888, .val = 0x0AE50821 },
         { .reg = 0x00009888, .val = 0x0CE50BAF },
         { .reg = 0x00009888, .val = 0x0EE50B2D },
         { .reg = 0x00009888, .val = 0x10E50AAB },
         { .reg = 0x00009888, .val = 0x12E50A29 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AAAA },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext851__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext851__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext851__avg_gpu_core_frequency__max,acmgt3__ext851__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5399, 24, NULL,acmgt3__ext851__rt_quad_leaf_ray_count_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5400, 32, NULL,acmgt3__ext851__rt_procedural_node_ray_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext852_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext852";
   query->symbol_name = "Ext852";
   query->guid = "33a19e51-f39f-4933-8aa7-a475e82a38e0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05859A70 },
         { .reg = 0x00009888, .val = 0x07850925 },
         { .reg = 0x00009888, .val = 0x098508A3 },
         { .reg = 0x00009888, .val = 0x0B850821 },
         { .reg = 0x00009888, .val = 0x0D850BAF },
         { .reg = 0x00009888, .val = 0x0F850B2D },
         { .reg = 0x00009888, .val = 0x11850AAB },
         { .reg = 0x00009888, .val = 0x13850A29 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext852__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext852__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext852__avg_gpu_core_frequency__max,acmgt3__ext852__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5401, 24, NULL,acmgt3__ext852__rt_quad_leaf_ray_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5402, 32, NULL,acmgt3__ext852__rt_procedural_node_ray_count_xecore20__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext853_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext853";
   query->symbol_name = "Ext853";
   query->guid = "cb81b489-bf38-423d-b4c6-b43360549140";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A59A70 },
         { .reg = 0x00009888, .val = 0x07A50925 },
         { .reg = 0x00009888, .val = 0x09A508A3 },
         { .reg = 0x00009888, .val = 0x0BA50821 },
         { .reg = 0x00009888, .val = 0x0DA50BAF },
         { .reg = 0x00009888, .val = 0x0FA50B2D },
         { .reg = 0x00009888, .val = 0x11A50AAB },
         { .reg = 0x00009888, .val = 0x13A50A29 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext853__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext853__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext853__avg_gpu_core_frequency__max,acmgt3__ext853__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5403, 24, NULL,acmgt3__ext853__rt_quad_leaf_ray_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5404, 32, NULL,acmgt3__ext853__rt_procedural_node_ray_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext854_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext854";
   query->symbol_name = "Ext854";
   query->guid = "5ed494ff-0fec-4980-960d-897413ec11b9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C59A70 },
         { .reg = 0x00009888, .val = 0x07C50925 },
         { .reg = 0x00009888, .val = 0x09C508A3 },
         { .reg = 0x00009888, .val = 0x0BC50821 },
         { .reg = 0x00009888, .val = 0x0DC50BAF },
         { .reg = 0x00009888, .val = 0x0FC50B2D },
         { .reg = 0x00009888, .val = 0x11C50AAB },
         { .reg = 0x00009888, .val = 0x13C50A29 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext854__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext854__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext854__avg_gpu_core_frequency__max,acmgt3__ext854__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5405, 24, NULL,acmgt3__ext854__rt_quad_leaf_ray_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5406, 32, NULL,acmgt3__ext854__rt_procedural_node_ray_count_xecore22__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext855_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext855";
   query->symbol_name = "Ext855";
   query->guid = "bc52aa18-e2ae-4254-ac8a-15c8b90f4e5b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E59A70 },
         { .reg = 0x00009888, .val = 0x07E50925 },
         { .reg = 0x00009888, .val = 0x09E508A3 },
         { .reg = 0x00009888, .val = 0x0BE50821 },
         { .reg = 0x00009888, .val = 0x0DE50BAF },
         { .reg = 0x00009888, .val = 0x0FE50B2D },
         { .reg = 0x00009888, .val = 0x11E50AAB },
         { .reg = 0x00009888, .val = 0x13E50A29 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext855__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext855__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext855__avg_gpu_core_frequency__max,acmgt3__ext855__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5407, 24, NULL,acmgt3__ext855__rt_quad_leaf_ray_count_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5408, 32, NULL,acmgt3__ext855__rt_procedural_node_ray_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext856_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext856";
   query->symbol_name = "Ext856";
   query->guid = "fe9d46b1-9ef7-4381-bea4-cd258cd0476f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1A8503E0 },
         { .reg = 0x00009888, .val = 0x1C85001F },
         { .reg = 0x00009888, .val = 0x02858000 },
         { .reg = 0x00009888, .val = 0x04859A70 },
         { .reg = 0x00009888, .val = 0x06850925 },
         { .reg = 0x00009888, .val = 0x088508A3 },
         { .reg = 0x00009888, .val = 0x0A850821 },
         { .reg = 0x00009888, .val = 0x0C850BAF },
         { .reg = 0x00009888, .val = 0x0E850B2D },
         { .reg = 0x00009888, .val = 0x10850AAB },
         { .reg = 0x00009888, .val = 0x12850A29 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086AAAA },
         { .reg = 0x00009888, .val = 0x0286AAAA },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext856__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext856__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext856__avg_gpu_core_frequency__max,acmgt3__ext856__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5409, 24, NULL,acmgt3__ext856__rt_quad_leaf_ray_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5410, 32, NULL,acmgt3__ext856__rt_procedural_node_ray_count_xecore24__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext857_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext857";
   query->symbol_name = "Ext857";
   query->guid = "eac16312-bd15-4486-aa9a-7430b13ec682";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AA503E0 },
         { .reg = 0x00009888, .val = 0x1CA5001F },
         { .reg = 0x00009888, .val = 0x02A58000 },
         { .reg = 0x00009888, .val = 0x04A59A70 },
         { .reg = 0x00009888, .val = 0x06A50925 },
         { .reg = 0x00009888, .val = 0x08A508A3 },
         { .reg = 0x00009888, .val = 0x0AA50821 },
         { .reg = 0x00009888, .val = 0x0CA50BAF },
         { .reg = 0x00009888, .val = 0x0EA50B2D },
         { .reg = 0x00009888, .val = 0x10A50AAB },
         { .reg = 0x00009888, .val = 0x12A50A29 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A6AAAA },
         { .reg = 0x00009888, .val = 0x02A6AAAA },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext857__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext857__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext857__avg_gpu_core_frequency__max,acmgt3__ext857__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5411, 24, NULL,acmgt3__ext857__rt_quad_leaf_ray_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5412, 32, NULL,acmgt3__ext857__rt_procedural_node_ray_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext858_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext858";
   query->symbol_name = "Ext858";
   query->guid = "6ace67c0-1c29-46ea-ae7a-63591d19d94d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AC503E0 },
         { .reg = 0x00009888, .val = 0x1CC5001F },
         { .reg = 0x00009888, .val = 0x02C58000 },
         { .reg = 0x00009888, .val = 0x04C59A70 },
         { .reg = 0x00009888, .val = 0x06C50925 },
         { .reg = 0x00009888, .val = 0x08C508A3 },
         { .reg = 0x00009888, .val = 0x0AC50821 },
         { .reg = 0x00009888, .val = 0x0CC50BAF },
         { .reg = 0x00009888, .val = 0x0EC50B2D },
         { .reg = 0x00009888, .val = 0x10C50AAB },
         { .reg = 0x00009888, .val = 0x12C50A29 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AAAA },
         { .reg = 0x00009888, .val = 0x02C6AAAA },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext858__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext858__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext858__avg_gpu_core_frequency__max,acmgt3__ext858__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5413, 24, NULL,acmgt3__ext858__rt_quad_leaf_ray_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5414, 32, NULL,acmgt3__ext858__rt_procedural_node_ray_count_xecore26__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext859_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext859";
   query->symbol_name = "Ext859";
   query->guid = "21ade297-b5e4-444d-8e59-8aebc60d9d8f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1AE503E0 },
         { .reg = 0x00009888, .val = 0x1CE5001F },
         { .reg = 0x00009888, .val = 0x02E58000 },
         { .reg = 0x00009888, .val = 0x04E59A70 },
         { .reg = 0x00009888, .val = 0x06E50925 },
         { .reg = 0x00009888, .val = 0x08E508A3 },
         { .reg = 0x00009888, .val = 0x0AE50821 },
         { .reg = 0x00009888, .val = 0x0CE50BAF },
         { .reg = 0x00009888, .val = 0x0EE50B2D },
         { .reg = 0x00009888, .val = 0x10E50AAB },
         { .reg = 0x00009888, .val = 0x12E50A29 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6AAAA },
         { .reg = 0x00009888, .val = 0x02E6AAAA },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext859__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext859__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext859__avg_gpu_core_frequency__max,acmgt3__ext859__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5415, 24, NULL,acmgt3__ext859__rt_quad_leaf_ray_count_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5416, 32, NULL,acmgt3__ext859__rt_procedural_node_ray_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext860_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext860";
   query->symbol_name = "Ext860";
   query->guid = "143bd38c-0888-4f91-8d74-56a4fb91aaa4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1B8503E0 },
         { .reg = 0x00009888, .val = 0x1D85001F },
         { .reg = 0x00009888, .val = 0x03858000 },
         { .reg = 0x00009888, .val = 0x05859A70 },
         { .reg = 0x00009888, .val = 0x07850925 },
         { .reg = 0x00009888, .val = 0x098508A3 },
         { .reg = 0x00009888, .val = 0x0B850821 },
         { .reg = 0x00009888, .val = 0x0D850BAF },
         { .reg = 0x00009888, .val = 0x0F850B2D },
         { .reg = 0x00009888, .val = 0x11850AAB },
         { .reg = 0x00009888, .val = 0x13850A29 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0186AAAA },
         { .reg = 0x00009888, .val = 0x0386AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext860__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext860__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext860__avg_gpu_core_frequency__max,acmgt3__ext860__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5417, 24, NULL,acmgt3__ext860__rt_quad_leaf_ray_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5418, 32, NULL,acmgt3__ext860__rt_procedural_node_ray_count_xecore28__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext861_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext861";
   query->symbol_name = "Ext861";
   query->guid = "a7c3ffb6-6925-4fed-88a7-5d06c1d20291";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BA503E0 },
         { .reg = 0x00009888, .val = 0x1DA5001F },
         { .reg = 0x00009888, .val = 0x03A58000 },
         { .reg = 0x00009888, .val = 0x05A59A70 },
         { .reg = 0x00009888, .val = 0x07A50925 },
         { .reg = 0x00009888, .val = 0x09A508A3 },
         { .reg = 0x00009888, .val = 0x0BA50821 },
         { .reg = 0x00009888, .val = 0x0DA50BAF },
         { .reg = 0x00009888, .val = 0x0FA50B2D },
         { .reg = 0x00009888, .val = 0x11A50AAB },
         { .reg = 0x00009888, .val = 0x13A50A29 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x01A6AAAA },
         { .reg = 0x00009888, .val = 0x03A6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext861__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext861__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext861__avg_gpu_core_frequency__max,acmgt3__ext861__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5419, 24, NULL,acmgt3__ext861__rt_quad_leaf_ray_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5420, 32, NULL,acmgt3__ext861__rt_procedural_node_ray_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext862_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext862";
   query->symbol_name = "Ext862";
   query->guid = "e3c34149-03bc-4d72-8477-261483c6b40e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BC503E0 },
         { .reg = 0x00009888, .val = 0x1DC5001F },
         { .reg = 0x00009888, .val = 0x03C58000 },
         { .reg = 0x00009888, .val = 0x05C59A70 },
         { .reg = 0x00009888, .val = 0x07C50925 },
         { .reg = 0x00009888, .val = 0x09C508A3 },
         { .reg = 0x00009888, .val = 0x0BC50821 },
         { .reg = 0x00009888, .val = 0x0DC50BAF },
         { .reg = 0x00009888, .val = 0x0FC50B2D },
         { .reg = 0x00009888, .val = 0x11C50AAB },
         { .reg = 0x00009888, .val = 0x13C50A29 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AAAA },
         { .reg = 0x00009888, .val = 0x03C6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext862__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext862__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext862__avg_gpu_core_frequency__max,acmgt3__ext862__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5421, 24, NULL,acmgt3__ext862__rt_quad_leaf_ray_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5422, 32, NULL,acmgt3__ext862__rt_procedural_node_ray_count_xecore30__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext863_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext863";
   query->symbol_name = "Ext863";
   query->guid = "0b4dff70-5115-468b-8dcc-e6e21b9468ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1BE503E0 },
         { .reg = 0x00009888, .val = 0x1DE5001F },
         { .reg = 0x00009888, .val = 0x03E58000 },
         { .reg = 0x00009888, .val = 0x05E59A70 },
         { .reg = 0x00009888, .val = 0x07E50925 },
         { .reg = 0x00009888, .val = 0x09E508A3 },
         { .reg = 0x00009888, .val = 0x0BE50821 },
         { .reg = 0x00009888, .val = 0x0DE50BAF },
         { .reg = 0x00009888, .val = 0x0FE50B2D },
         { .reg = 0x00009888, .val = 0x11E50AAB },
         { .reg = 0x00009888, .val = 0x13E50A29 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E6AAAA },
         { .reg = 0x00009888, .val = 0x03E6AAAA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00000802 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00008002 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
         { .reg = 0x0000D960, .val = 0x0000002A },
         { .reg = 0x0000D964, .val = 0x0000FFFA },
         { .reg = 0x0000D968, .val = 0x00000282 },
         { .reg = 0x0000D96C, .val = 0x0000FFAF },
         { .reg = 0x0000D970, .val = 0x00028002 },
         { .reg = 0x0000D974, .val = 0x0000AFFF },
         { .reg = 0x0000D978, .val = 0x00002802 },
         { .reg = 0x0000D97C, .val = 0x0000FAFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext863__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext863__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext863__avg_gpu_core_frequency__max,acmgt3__ext863__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5423, 24, NULL,acmgt3__ext863__rt_quad_leaf_ray_count_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5424, 32, NULL,acmgt3__ext863__rt_procedural_node_ray_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext864_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext864";
   query->symbol_name = "Ext864";
   query->guid = "85869032-aa5e-4109-baff-f124584720c8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x14850000 },
         { .reg = 0x00009888, .val = 0x14A50000 },
         { .reg = 0x00009888, .val = 0x14C50000 },
         { .reg = 0x00009888, .val = 0x14E50000 },
         { .reg = 0x00009888, .val = 0x02850002 },
         { .reg = 0x00009888, .val = 0x10850083 },
         { .reg = 0x00009888, .val = 0x12850001 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x02A50002 },
         { .reg = 0x00009888, .val = 0x0CA50083 },
         { .reg = 0x00009888, .val = 0x0EA50001 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A600AA },
         { .reg = 0x00009888, .val = 0x02C50002 },
         { .reg = 0x00009888, .val = 0x08C50083 },
         { .reg = 0x00009888, .val = 0x0AC50001 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AA00 },
         { .reg = 0x00009888, .val = 0x02E50002 },
         { .reg = 0x00009888, .val = 0x04E50830 },
         { .reg = 0x00009888, .val = 0x06E50001 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E600AA },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext864__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext864__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext864__avg_gpu_core_frequency__max,acmgt3__ext864__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1744, 24, NULL,acmgt3__ext864__rt_bvh_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1745, 32, NULL,acmgt3__ext864__rt_bvh_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1746, 40, NULL,acmgt3__ext864__rt_bvh_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1747, 48, NULL,acmgt3__ext864__rt_bvh_cache_miss_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext865_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext865";
   query->symbol_name = "Ext865";
   query->guid = "5dd2de9a-2dc8-4f38-8aee-48d720ee1d08";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x15850000 },
         { .reg = 0x00009888, .val = 0x15A50000 },
         { .reg = 0x00009888, .val = 0x15C50000 },
         { .reg = 0x00009888, .val = 0x15E50000 },
         { .reg = 0x00009888, .val = 0x03850002 },
         { .reg = 0x00009888, .val = 0x11850083 },
         { .reg = 0x00009888, .val = 0x13850001 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x03A50002 },
         { .reg = 0x00009888, .val = 0x0DA50083 },
         { .reg = 0x00009888, .val = 0x0FA50001 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600AA },
         { .reg = 0x00009888, .val = 0x03C50002 },
         { .reg = 0x00009888, .val = 0x09C50083 },
         { .reg = 0x00009888, .val = 0x0BC50001 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AA00 },
         { .reg = 0x00009888, .val = 0x03E50002 },
         { .reg = 0x00009888, .val = 0x05E50830 },
         { .reg = 0x00009888, .val = 0x07E50001 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E600AA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext865__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext865__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext865__avg_gpu_core_frequency__max,acmgt3__ext865__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1748, 24, NULL,acmgt3__ext865__rt_bvh_cache_miss_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1749, 32, NULL,acmgt3__ext865__rt_bvh_cache_miss_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1750, 40, NULL,acmgt3__ext865__rt_bvh_cache_miss_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1751, 48, NULL,acmgt3__ext865__rt_bvh_cache_miss_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext866_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext866";
   query->symbol_name = "Ext866";
   query->guid = "16098b83-88a3-451d-8c1e-f2b92ef1c2a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x14850000 },
         { .reg = 0x00009888, .val = 0x14A50000 },
         { .reg = 0x00009888, .val = 0x14C50000 },
         { .reg = 0x00009888, .val = 0x14E50000 },
         { .reg = 0x00009888, .val = 0x02850002 },
         { .reg = 0x00009888, .val = 0x10850083 },
         { .reg = 0x00009888, .val = 0x12850001 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x02A50002 },
         { .reg = 0x00009888, .val = 0x0CA50083 },
         { .reg = 0x00009888, .val = 0x0EA50001 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A600AA },
         { .reg = 0x00009888, .val = 0x02C50002 },
         { .reg = 0x00009888, .val = 0x08C50083 },
         { .reg = 0x00009888, .val = 0x0AC50001 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AA00 },
         { .reg = 0x00009888, .val = 0x02E50002 },
         { .reg = 0x00009888, .val = 0x04E50830 },
         { .reg = 0x00009888, .val = 0x06E50001 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E600AA },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext866__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext866__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext866__avg_gpu_core_frequency__max,acmgt3__ext866__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2975, 24, NULL,acmgt3__ext866__rt_bvh_cache_miss_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2976, 32, NULL,acmgt3__ext866__rt_bvh_cache_miss_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2977, 40, NULL,acmgt3__ext866__rt_bvh_cache_miss_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2978, 48, NULL,acmgt3__ext866__rt_bvh_cache_miss_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext867_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext867";
   query->symbol_name = "Ext867";
   query->guid = "12e157ed-ca6a-4cc2-a3e7-5c35b9238f54";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x15850000 },
         { .reg = 0x00009888, .val = 0x15A50000 },
         { .reg = 0x00009888, .val = 0x15C50000 },
         { .reg = 0x00009888, .val = 0x15E50000 },
         { .reg = 0x00009888, .val = 0x03850002 },
         { .reg = 0x00009888, .val = 0x11850083 },
         { .reg = 0x00009888, .val = 0x13850001 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x03A50002 },
         { .reg = 0x00009888, .val = 0x0DA50083 },
         { .reg = 0x00009888, .val = 0x0FA50001 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600AA },
         { .reg = 0x00009888, .val = 0x03C50002 },
         { .reg = 0x00009888, .val = 0x09C50083 },
         { .reg = 0x00009888, .val = 0x0BC50001 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AA00 },
         { .reg = 0x00009888, .val = 0x03E50002 },
         { .reg = 0x00009888, .val = 0x05E50830 },
         { .reg = 0x00009888, .val = 0x07E50001 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E600AA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext867__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext867__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext867__avg_gpu_core_frequency__max,acmgt3__ext867__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2979, 24, NULL,acmgt3__ext867__rt_bvh_cache_miss_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2980, 32, NULL,acmgt3__ext867__rt_bvh_cache_miss_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2981, 40, NULL,acmgt3__ext867__rt_bvh_cache_miss_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2982, 48, NULL,acmgt3__ext867__rt_bvh_cache_miss_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext868_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext868";
   query->symbol_name = "Ext868";
   query->guid = "7bb5d7df-919a-4c1c-9029-5b34dec3b0a1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x14850000 },
         { .reg = 0x00009888, .val = 0x14A50000 },
         { .reg = 0x00009888, .val = 0x14C50000 },
         { .reg = 0x00009888, .val = 0x14E50000 },
         { .reg = 0x00009888, .val = 0x02850002 },
         { .reg = 0x00009888, .val = 0x10850083 },
         { .reg = 0x00009888, .val = 0x12850001 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x02A50002 },
         { .reg = 0x00009888, .val = 0x0CA50083 },
         { .reg = 0x00009888, .val = 0x0EA50001 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A600AA },
         { .reg = 0x00009888, .val = 0x02C50002 },
         { .reg = 0x00009888, .val = 0x08C50083 },
         { .reg = 0x00009888, .val = 0x0AC50001 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AA00 },
         { .reg = 0x00009888, .val = 0x02E50002 },
         { .reg = 0x00009888, .val = 0x04E50830 },
         { .reg = 0x00009888, .val = 0x06E50001 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E600AA },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext868__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext868__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext868__avg_gpu_core_frequency__max,acmgt3__ext868__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5425, 24, NULL,acmgt3__ext868__rt_bvh_cache_miss_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5426, 32, NULL,acmgt3__ext868__rt_bvh_cache_miss_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5427, 40, NULL,acmgt3__ext868__rt_bvh_cache_miss_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5428, 48, NULL,acmgt3__ext868__rt_bvh_cache_miss_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext869_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext869";
   query->symbol_name = "Ext869";
   query->guid = "f090fb53-717d-4bcc-8ac0-515ef2e9e732";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x15850000 },
         { .reg = 0x00009888, .val = 0x15A50000 },
         { .reg = 0x00009888, .val = 0x15C50000 },
         { .reg = 0x00009888, .val = 0x15E50000 },
         { .reg = 0x00009888, .val = 0x03850002 },
         { .reg = 0x00009888, .val = 0x11850083 },
         { .reg = 0x00009888, .val = 0x13850001 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x03A50002 },
         { .reg = 0x00009888, .val = 0x0DA50083 },
         { .reg = 0x00009888, .val = 0x0FA50001 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600AA },
         { .reg = 0x00009888, .val = 0x03C50002 },
         { .reg = 0x00009888, .val = 0x09C50083 },
         { .reg = 0x00009888, .val = 0x0BC50001 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AA00 },
         { .reg = 0x00009888, .val = 0x03E50002 },
         { .reg = 0x00009888, .val = 0x05E50830 },
         { .reg = 0x00009888, .val = 0x07E50001 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E600AA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext869__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext869__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext869__avg_gpu_core_frequency__max,acmgt3__ext869__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5429, 24, NULL,acmgt3__ext869__rt_bvh_cache_miss_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5430, 32, NULL,acmgt3__ext869__rt_bvh_cache_miss_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5431, 40, NULL,acmgt3__ext869__rt_bvh_cache_miss_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5432, 48, NULL,acmgt3__ext869__rt_bvh_cache_miss_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext870_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext870";
   query->symbol_name = "Ext870";
   query->guid = "aaeae265-2220-4838-947e-98558d911858";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x14850000 },
         { .reg = 0x00009888, .val = 0x14A50000 },
         { .reg = 0x00009888, .val = 0x14C50000 },
         { .reg = 0x00009888, .val = 0x14E50000 },
         { .reg = 0x00009888, .val = 0x02850002 },
         { .reg = 0x00009888, .val = 0x10850083 },
         { .reg = 0x00009888, .val = 0x12850001 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0286AA00 },
         { .reg = 0x00009888, .val = 0x02A50002 },
         { .reg = 0x00009888, .val = 0x0CA50083 },
         { .reg = 0x00009888, .val = 0x0EA50001 },
         { .reg = 0x00009888, .val = 0x06A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A600AA },
         { .reg = 0x00009888, .val = 0x02C50002 },
         { .reg = 0x00009888, .val = 0x08C50083 },
         { .reg = 0x00009888, .val = 0x0AC50001 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C6AA00 },
         { .reg = 0x00009888, .val = 0x02E50002 },
         { .reg = 0x00009888, .val = 0x04E50830 },
         { .reg = 0x00009888, .val = 0x06E50001 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E600AA },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext870__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext870__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext870__avg_gpu_core_frequency__max,acmgt3__ext870__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5433, 24, NULL,acmgt3__ext870__rt_bvh_cache_miss_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5434, 32, NULL,acmgt3__ext870__rt_bvh_cache_miss_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5435, 40, NULL,acmgt3__ext870__rt_bvh_cache_miss_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5436, 48, NULL,acmgt3__ext870__rt_bvh_cache_miss_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext871_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext871";
   query->symbol_name = "Ext871";
   query->guid = "662d8774-3e66-4c9b-b5e2-5be8747980d8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x15850000 },
         { .reg = 0x00009888, .val = 0x15A50000 },
         { .reg = 0x00009888, .val = 0x15C50000 },
         { .reg = 0x00009888, .val = 0x15E50000 },
         { .reg = 0x00009888, .val = 0x03850002 },
         { .reg = 0x00009888, .val = 0x11850083 },
         { .reg = 0x00009888, .val = 0x13850001 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386AA00 },
         { .reg = 0x00009888, .val = 0x03A50002 },
         { .reg = 0x00009888, .val = 0x0DA50083 },
         { .reg = 0x00009888, .val = 0x0FA50001 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600AA },
         { .reg = 0x00009888, .val = 0x03C50002 },
         { .reg = 0x00009888, .val = 0x09C50083 },
         { .reg = 0x00009888, .val = 0x0BC50001 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x01C6AA00 },
         { .reg = 0x00009888, .val = 0x03E50002 },
         { .reg = 0x00009888, .val = 0x05E50830 },
         { .reg = 0x00009888, .val = 0x07E50001 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x01E600AA },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42032942 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x4403000A },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40030842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext871__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext871__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext871__avg_gpu_core_frequency__max,acmgt3__ext871__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5437, 24, NULL,acmgt3__ext871__rt_bvh_cache_miss_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5438, 32, NULL,acmgt3__ext871__rt_bvh_cache_miss_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5439, 40, NULL,acmgt3__ext871__rt_bvh_cache_miss_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5440, 48, NULL,acmgt3__ext871__rt_bvh_cache_miss_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext872_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext872";
   query->symbol_name = "Ext872";
   query->guid = "2c69a291-9d76-46de-9db5-ceab2dccda57";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1687000F },
         { .reg = 0x00009888, .val = 0x1A87000F },
         { .reg = 0x00009888, .val = 0x1288000F },
         { .reg = 0x00009888, .val = 0x1688000F },
         { .reg = 0x00009888, .val = 0x16A7000F },
         { .reg = 0x00009888, .val = 0x1AA7000F },
         { .reg = 0x00009888, .val = 0x12A8000F },
         { .reg = 0x00009888, .val = 0x16A8000F },
         { .reg = 0x00009888, .val = 0x16C7000F },
         { .reg = 0x00009888, .val = 0x1AC7000F },
         { .reg = 0x00009888, .val = 0x12C8000F },
         { .reg = 0x00009888, .val = 0x16C8000F },
         { .reg = 0x00009888, .val = 0x16E7000F },
         { .reg = 0x00009888, .val = 0x1AE7000F },
         { .reg = 0x00009888, .val = 0x12E8000F },
         { .reg = 0x00009888, .val = 0x16E8000F },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext872__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext872__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext872__avg_gpu_core_frequency__max,acmgt3__ext872__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1696, 24, NULL,acmgt3__ext872__slm_access_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1695, 32, NULL,acmgt3__ext872__slm_access_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1694, 40, NULL,acmgt3__ext872__slm_access_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1697, 48, NULL,acmgt3__ext872__slm_access_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext873_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext873";
   query->symbol_name = "Ext873";
   query->guid = "0f86e589-8993-42a0-b344-e2b667565ede";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1787000F },
         { .reg = 0x00009888, .val = 0x1B87000F },
         { .reg = 0x00009888, .val = 0x1388000F },
         { .reg = 0x00009888, .val = 0x1788000F },
         { .reg = 0x00009888, .val = 0x17A7000F },
         { .reg = 0x00009888, .val = 0x1BA7000F },
         { .reg = 0x00009888, .val = 0x13A8000F },
         { .reg = 0x00009888, .val = 0x17A8000F },
         { .reg = 0x00009888, .val = 0x17C7000F },
         { .reg = 0x00009888, .val = 0x1BC7000F },
         { .reg = 0x00009888, .val = 0x13C8000F },
         { .reg = 0x00009888, .val = 0x17C8000F },
         { .reg = 0x00009888, .val = 0x17E7000F },
         { .reg = 0x00009888, .val = 0x1BE7000F },
         { .reg = 0x00009888, .val = 0x13E8000F },
         { .reg = 0x00009888, .val = 0x17E8000F },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext873__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext873__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext873__avg_gpu_core_frequency__max,acmgt3__ext873__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1698, 24, NULL,acmgt3__ext873__slm_access_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1699, 32, NULL,acmgt3__ext873__slm_access_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1700, 40, NULL,acmgt3__ext873__slm_access_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1701, 48, NULL,acmgt3__ext873__slm_access_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext874_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext874";
   query->symbol_name = "Ext874";
   query->guid = "d11c464b-ef9a-4da5-9322-1e57cb0e0897";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1687000F },
         { .reg = 0x00009888, .val = 0x1A87000F },
         { .reg = 0x00009888, .val = 0x1288000F },
         { .reg = 0x00009888, .val = 0x1688000F },
         { .reg = 0x00009888, .val = 0x16A7000F },
         { .reg = 0x00009888, .val = 0x1AA7000F },
         { .reg = 0x00009888, .val = 0x12A8000F },
         { .reg = 0x00009888, .val = 0x16A8000F },
         { .reg = 0x00009888, .val = 0x16C7000F },
         { .reg = 0x00009888, .val = 0x1AC7000F },
         { .reg = 0x00009888, .val = 0x12C8000F },
         { .reg = 0x00009888, .val = 0x16C8000F },
         { .reg = 0x00009888, .val = 0x16E7000F },
         { .reg = 0x00009888, .val = 0x1AE7000F },
         { .reg = 0x00009888, .val = 0x12E8000F },
         { .reg = 0x00009888, .val = 0x16E8000F },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext874__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext874__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext874__avg_gpu_core_frequency__max,acmgt3__ext874__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2539, 24, NULL,acmgt3__ext874__slm_access_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2540, 32, NULL,acmgt3__ext874__slm_access_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2541, 40, NULL,acmgt3__ext874__slm_access_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2542, 48, NULL,acmgt3__ext874__slm_access_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext875_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext875";
   query->symbol_name = "Ext875";
   query->guid = "49a40c7a-1037-479e-a24c-4e9f4e8ff55a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1787000F },
         { .reg = 0x00009888, .val = 0x1B87000F },
         { .reg = 0x00009888, .val = 0x1388000F },
         { .reg = 0x00009888, .val = 0x1788000F },
         { .reg = 0x00009888, .val = 0x17A7000F },
         { .reg = 0x00009888, .val = 0x1BA7000F },
         { .reg = 0x00009888, .val = 0x13A8000F },
         { .reg = 0x00009888, .val = 0x17A8000F },
         { .reg = 0x00009888, .val = 0x17C7000F },
         { .reg = 0x00009888, .val = 0x1BC7000F },
         { .reg = 0x00009888, .val = 0x13C8000F },
         { .reg = 0x00009888, .val = 0x17C8000F },
         { .reg = 0x00009888, .val = 0x17E7000F },
         { .reg = 0x00009888, .val = 0x1BE7000F },
         { .reg = 0x00009888, .val = 0x13E8000F },
         { .reg = 0x00009888, .val = 0x17E8000F },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext875__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext875__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext875__avg_gpu_core_frequency__max,acmgt3__ext875__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2543, 24, NULL,acmgt3__ext875__slm_access_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2544, 32, NULL,acmgt3__ext875__slm_access_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2545, 40, NULL,acmgt3__ext875__slm_access_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2546, 48, NULL,acmgt3__ext875__slm_access_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext876_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext876";
   query->symbol_name = "Ext876";
   query->guid = "80397a0b-40b5-4d6f-bc14-297a9094c5ca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1687000F },
         { .reg = 0x00009888, .val = 0x1A87000F },
         { .reg = 0x00009888, .val = 0x1288000F },
         { .reg = 0x00009888, .val = 0x1688000F },
         { .reg = 0x00009888, .val = 0x16A7000F },
         { .reg = 0x00009888, .val = 0x1AA7000F },
         { .reg = 0x00009888, .val = 0x12A8000F },
         { .reg = 0x00009888, .val = 0x16A8000F },
         { .reg = 0x00009888, .val = 0x16C7000F },
         { .reg = 0x00009888, .val = 0x1AC7000F },
         { .reg = 0x00009888, .val = 0x12C8000F },
         { .reg = 0x00009888, .val = 0x16C8000F },
         { .reg = 0x00009888, .val = 0x16E7000F },
         { .reg = 0x00009888, .val = 0x1AE7000F },
         { .reg = 0x00009888, .val = 0x12E8000F },
         { .reg = 0x00009888, .val = 0x16E8000F },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext876__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext876__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext876__avg_gpu_core_frequency__max,acmgt3__ext876__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5441, 24, NULL,acmgt3__ext876__slm_access_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5442, 32, NULL,acmgt3__ext876__slm_access_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5443, 40, NULL,acmgt3__ext876__slm_access_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5444, 48, NULL,acmgt3__ext876__slm_access_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext877_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext877";
   query->symbol_name = "Ext877";
   query->guid = "4dd595cc-86a2-4abf-bda8-aaebda8bebe4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1787000F },
         { .reg = 0x00009888, .val = 0x1B87000F },
         { .reg = 0x00009888, .val = 0x1388000F },
         { .reg = 0x00009888, .val = 0x1788000F },
         { .reg = 0x00009888, .val = 0x17A7000F },
         { .reg = 0x00009888, .val = 0x1BA7000F },
         { .reg = 0x00009888, .val = 0x13A8000F },
         { .reg = 0x00009888, .val = 0x17A8000F },
         { .reg = 0x00009888, .val = 0x17C7000F },
         { .reg = 0x00009888, .val = 0x1BC7000F },
         { .reg = 0x00009888, .val = 0x13C8000F },
         { .reg = 0x00009888, .val = 0x17C8000F },
         { .reg = 0x00009888, .val = 0x17E7000F },
         { .reg = 0x00009888, .val = 0x1BE7000F },
         { .reg = 0x00009888, .val = 0x13E8000F },
         { .reg = 0x00009888, .val = 0x17E8000F },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext877__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext877__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext877__avg_gpu_core_frequency__max,acmgt3__ext877__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5445, 24, NULL,acmgt3__ext877__slm_access_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5446, 32, NULL,acmgt3__ext877__slm_access_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5447, 40, NULL,acmgt3__ext877__slm_access_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5448, 48, NULL,acmgt3__ext877__slm_access_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext878_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext878";
   query->symbol_name = "Ext878";
   query->guid = "4bd452af-bdfc-4d44-a607-3f2b867b5ae5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1687000F },
         { .reg = 0x00009888, .val = 0x1A87000F },
         { .reg = 0x00009888, .val = 0x1288000F },
         { .reg = 0x00009888, .val = 0x1688000F },
         { .reg = 0x00009888, .val = 0x16A7000F },
         { .reg = 0x00009888, .val = 0x1AA7000F },
         { .reg = 0x00009888, .val = 0x12A8000F },
         { .reg = 0x00009888, .val = 0x16A8000F },
         { .reg = 0x00009888, .val = 0x16C7000F },
         { .reg = 0x00009888, .val = 0x1AC7000F },
         { .reg = 0x00009888, .val = 0x12C8000F },
         { .reg = 0x00009888, .val = 0x16C8000F },
         { .reg = 0x00009888, .val = 0x16E7000F },
         { .reg = 0x00009888, .val = 0x1AE7000F },
         { .reg = 0x00009888, .val = 0x12E8000F },
         { .reg = 0x00009888, .val = 0x16E8000F },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x148701D7 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E8801D7 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A701D7 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA801D7 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC701D7 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C801D7 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E701D7 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E801D7 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext878__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext878__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext878__avg_gpu_core_frequency__max,acmgt3__ext878__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5449, 24, NULL,acmgt3__ext878__slm_access_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5450, 32, NULL,acmgt3__ext878__slm_access_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5451, 40, NULL,acmgt3__ext878__slm_access_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5452, 48, NULL,acmgt3__ext878__slm_access_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext879_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext879";
   query->symbol_name = "Ext879";
   query->guid = "6793871f-9574-4605-b748-50f227dc8d0d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1787000F },
         { .reg = 0x00009888, .val = 0x1B87000F },
         { .reg = 0x00009888, .val = 0x1388000F },
         { .reg = 0x00009888, .val = 0x1788000F },
         { .reg = 0x00009888, .val = 0x17A7000F },
         { .reg = 0x00009888, .val = 0x1BA7000F },
         { .reg = 0x00009888, .val = 0x13A8000F },
         { .reg = 0x00009888, .val = 0x17A8000F },
         { .reg = 0x00009888, .val = 0x17C7000F },
         { .reg = 0x00009888, .val = 0x1BC7000F },
         { .reg = 0x00009888, .val = 0x13C8000F },
         { .reg = 0x00009888, .val = 0x17C8000F },
         { .reg = 0x00009888, .val = 0x17E7000F },
         { .reg = 0x00009888, .val = 0x1BE7000F },
         { .reg = 0x00009888, .val = 0x13E8000F },
         { .reg = 0x00009888, .val = 0x17E8000F },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x158701D7 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F8801D7 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A701D7 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA801D7 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC701D7 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C801D7 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E701D7 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E801D7 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext879__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext879__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext879__avg_gpu_core_frequency__max,acmgt3__ext879__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5453, 24, NULL,acmgt3__ext879__slm_access_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5454, 32, NULL,acmgt3__ext879__slm_access_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5455, 40, NULL,acmgt3__ext879__slm_access_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5456, 48, NULL,acmgt3__ext879__slm_access_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext880_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext880";
   query->symbol_name = "Ext880";
   query->guid = "eda73924-faa7-4e99-b942-e571db97ffd9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18013800 },
         { .reg = 0x00009888, .val = 0x1A01000F },
         { .reg = 0x00009888, .val = 0x020100E6 },
         { .reg = 0x00009888, .val = 0x06011C00 },
         { .reg = 0x00009888, .val = 0x08010248 },
         { .reg = 0x00009888, .val = 0x0A0102CA },
         { .reg = 0x00009888, .val = 0x0C01034C },
         { .reg = 0x00009888, .val = 0x0E0103CE },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02030924 },
         { .reg = 0x00009888, .val = 0x000A2492 },
         { .reg = 0x00009888, .val = 0x020A0492 },
         { .reg = 0x00009888, .val = 0x000B1249 },
         { .reg = 0x00009888, .val = 0x020B0249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext880__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext880__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext880__avg_gpu_core_frequency__max,acmgt3__ext880__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1702, 24, NULL,acmgt3__ext880__gpu_memory_l3_write_sqidi0__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext881_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext881";
   query->symbol_name = "Ext881";
   query->guid = "4c4c41af-23de-4ac2-adbc-db69aa7c7a59";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18213800 },
         { .reg = 0x00009888, .val = 0x1A21000F },
         { .reg = 0x00009888, .val = 0x022100E6 },
         { .reg = 0x00009888, .val = 0x06211C00 },
         { .reg = 0x00009888, .val = 0x08210248 },
         { .reg = 0x00009888, .val = 0x0A2102CA },
         { .reg = 0x00009888, .val = 0x0C21034C },
         { .reg = 0x00009888, .val = 0x0E2103CE },
         { .reg = 0x00009888, .val = 0x00210000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02030924 },
         { .reg = 0x00009888, .val = 0x000A2492 },
         { .reg = 0x00009888, .val = 0x020A0492 },
         { .reg = 0x00009888, .val = 0x000B2492 },
         { .reg = 0x00009888, .val = 0x020B0492 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext881__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext881__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext881__avg_gpu_core_frequency__max,acmgt3__ext881__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1703, 24, NULL,acmgt3__ext881__gpu_memory_l3_write_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext882_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext882";
   query->symbol_name = "Ext882";
   query->guid = "3d734ca7-99c2-4cc6-a42b-0678c30adafd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x1A41000F },
         { .reg = 0x00009888, .val = 0x024100E6 },
         { .reg = 0x00009888, .val = 0x06411C00 },
         { .reg = 0x00009888, .val = 0x08410248 },
         { .reg = 0x00009888, .val = 0x0A4102CA },
         { .reg = 0x00009888, .val = 0x0C41034C },
         { .reg = 0x00009888, .val = 0x0E4103CE },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02030924 },
         { .reg = 0x00009888, .val = 0x000A2492 },
         { .reg = 0x00009888, .val = 0x020A0492 },
         { .reg = 0x00009888, .val = 0x000B36DB },
         { .reg = 0x00009888, .val = 0x020B06DB },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext882__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext882__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext882__avg_gpu_core_frequency__max,acmgt3__ext882__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2813, 24, NULL,acmgt3__ext882__gpu_memory_l3_write_sqidi2__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext883_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext883";
   query->symbol_name = "Ext883";
   query->guid = "c435cabd-1edf-47e1-a0b8-e952e4144f14";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x1A61000F },
         { .reg = 0x00009888, .val = 0x026100E6 },
         { .reg = 0x00009888, .val = 0x06611C00 },
         { .reg = 0x00009888, .val = 0x08610248 },
         { .reg = 0x00009888, .val = 0x0A6102CA },
         { .reg = 0x00009888, .val = 0x0C61034C },
         { .reg = 0x00009888, .val = 0x0E6103CE },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02030924 },
         { .reg = 0x00009888, .val = 0x000A2492 },
         { .reg = 0x00009888, .val = 0x020A0492 },
         { .reg = 0x00009888, .val = 0x000B4924 },
         { .reg = 0x00009888, .val = 0x020B0924 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext883__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext883__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext883__avg_gpu_core_frequency__max,acmgt3__ext883__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2814, 24, NULL,acmgt3__ext883__gpu_memory_l3_write_sqidi3__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext884_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext884";
   query->symbol_name = "Ext884";
   query->guid = "b51c6d34-8b88-48c1-a88d-d3114cc750a7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x1A81000F },
         { .reg = 0x00009888, .val = 0x028100E6 },
         { .reg = 0x00009888, .val = 0x06811C00 },
         { .reg = 0x00009888, .val = 0x08810248 },
         { .reg = 0x00009888, .val = 0x0A8102CA },
         { .reg = 0x00009888, .val = 0x0C81034C },
         { .reg = 0x00009888, .val = 0x0E8103CE },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02030924 },
         { .reg = 0x00009888, .val = 0x00091249 },
         { .reg = 0x00009888, .val = 0x02090249 },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A0249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext884__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext884__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext884__avg_gpu_core_frequency__max,acmgt3__ext884__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5457, 24, NULL,acmgt3__ext884__gpu_memory_l3_write_sqidi4__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext885_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext885";
   query->symbol_name = "Ext885";
   query->guid = "cc13457c-3aef-4c2c-9b3b-d07058268807";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x1AA1000F },
         { .reg = 0x00009888, .val = 0x02A100E6 },
         { .reg = 0x00009888, .val = 0x06A11C00 },
         { .reg = 0x00009888, .val = 0x08A10248 },
         { .reg = 0x00009888, .val = 0x0AA102CA },
         { .reg = 0x00009888, .val = 0x0CA1034C },
         { .reg = 0x00009888, .val = 0x0EA103CE },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02030924 },
         { .reg = 0x00009888, .val = 0x00092492 },
         { .reg = 0x00009888, .val = 0x02090492 },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A0249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext885__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext885__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext885__avg_gpu_core_frequency__max,acmgt3__ext885__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5458, 24, NULL,acmgt3__ext885__gpu_memory_l3_write_sqidi5__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext886_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext886";
   query->symbol_name = "Ext886";
   query->guid = "3b526aaf-5919-4a41-ba31-2e6fb7205765";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18C13800 },
         { .reg = 0x00009888, .val = 0x1AC1000F },
         { .reg = 0x00009888, .val = 0x02C100E6 },
         { .reg = 0x00009888, .val = 0x06C11C00 },
         { .reg = 0x00009888, .val = 0x08C10248 },
         { .reg = 0x00009888, .val = 0x0AC102CA },
         { .reg = 0x00009888, .val = 0x0CC1034C },
         { .reg = 0x00009888, .val = 0x0EC103CE },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02030924 },
         { .reg = 0x00009888, .val = 0x000936DB },
         { .reg = 0x00009888, .val = 0x020906DB },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A0249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext886__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext886__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext886__avg_gpu_core_frequency__max,acmgt3__ext886__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5459, 24, NULL,acmgt3__ext886__gpu_memory_l3_write_sqidi6__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext887_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext887";
   query->symbol_name = "Ext887";
   query->guid = "4e1fdf9d-9a97-45ad-92d5-c4dbf0b6b6c4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18E13800 },
         { .reg = 0x00009888, .val = 0x1AE1000F },
         { .reg = 0x00009888, .val = 0x02E100E6 },
         { .reg = 0x00009888, .val = 0x06E11C00 },
         { .reg = 0x00009888, .val = 0x08E10248 },
         { .reg = 0x00009888, .val = 0x0AE102CA },
         { .reg = 0x00009888, .val = 0x0CE1034C },
         { .reg = 0x00009888, .val = 0x0EE103CE },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02030924 },
         { .reg = 0x00009888, .val = 0x00094924 },
         { .reg = 0x00009888, .val = 0x02090924 },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A0249 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext887__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext887__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext887__avg_gpu_core_frequency__max,acmgt3__ext887__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5460, 24, NULL,acmgt3__ext887__gpu_memory_l3_write_sqidi7__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext888_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext888";
   query->symbol_name = "Ext888";
   query->guid = "51d516e5-4f18-4d23-abef-d4fe43d2cedd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext888__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext888__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext888__avg_gpu_core_frequency__max,acmgt3__ext888__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1752, 24, NULL,acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1753, 32, NULL,acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1754, 40, NULL,acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1755, 48, NULL,acmgt3__ext888__load_store_cache_number_of_bank_access_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext889_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext889";
   query->symbol_name = "Ext889";
   query->guid = "69746c29-88ae-4e33-9d89-832f961ce4d0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext889__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext889__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext889__avg_gpu_core_frequency__max,acmgt3__ext889__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1756, 24, NULL,acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1757, 32, NULL,acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1758, 40, NULL,acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1759, 48, NULL,acmgt3__ext889__load_store_cache_number_of_bank_access_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext890_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext890";
   query->symbol_name = "Ext890";
   query->guid = "3772217c-5bfa-4b4f-8ce6-c1d70e1e7409";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext890__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext890__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext890__avg_gpu_core_frequency__max,acmgt3__ext890__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2627, 24, NULL,acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2628, 32, NULL,acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2629, 40, NULL,acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2630, 48, NULL,acmgt3__ext890__load_store_cache_number_of_bank_access_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext891_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext891";
   query->symbol_name = "Ext891";
   query->guid = "f0a9580b-73ae-4ae7-994f-4b6d5d265291";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext891__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext891__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext891__avg_gpu_core_frequency__max,acmgt3__ext891__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2631, 24, NULL,acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2632, 32, NULL,acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2633, 40, NULL,acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2634, 48, NULL,acmgt3__ext891__load_store_cache_number_of_bank_access_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext892_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext892";
   query->symbol_name = "Ext892";
   query->guid = "52064d17-d36d-4f45-ab86-8732a72ab376";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext892__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext892__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext892__avg_gpu_core_frequency__max,acmgt3__ext892__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5461, 24, NULL,acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5462, 32, NULL,acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5463, 40, NULL,acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5464, 48, NULL,acmgt3__ext892__load_store_cache_number_of_bank_access_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext893_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext893";
   query->symbol_name = "Ext893";
   query->guid = "4b2771bf-21cc-4d4f-b0c5-70b3ff4144d3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext893__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext893__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext893__avg_gpu_core_frequency__max,acmgt3__ext893__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5465, 24, NULL,acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5466, 32, NULL,acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5467, 40, NULL,acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5468, 48, NULL,acmgt3__ext893__load_store_cache_number_of_bank_access_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext894_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext894";
   query->symbol_name = "Ext894";
   query->guid = "d028b5f8-993c-4c35-9d86-2601fa6a78e9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x16870004 },
         { .reg = 0x00009888, .val = 0x1A870004 },
         { .reg = 0x00009888, .val = 0x12880004 },
         { .reg = 0x00009888, .val = 0x16880004 },
         { .reg = 0x00009888, .val = 0x16A70004 },
         { .reg = 0x00009888, .val = 0x1AA70004 },
         { .reg = 0x00009888, .val = 0x12A80004 },
         { .reg = 0x00009888, .val = 0x16A80004 },
         { .reg = 0x00009888, .val = 0x16C70004 },
         { .reg = 0x00009888, .val = 0x1AC70004 },
         { .reg = 0x00009888, .val = 0x12C80004 },
         { .reg = 0x00009888, .val = 0x16C80004 },
         { .reg = 0x00009888, .val = 0x16E70004 },
         { .reg = 0x00009888, .val = 0x1AE70004 },
         { .reg = 0x00009888, .val = 0x12E80004 },
         { .reg = 0x00009888, .val = 0x16E80004 },
         { .reg = 0x00009888, .val = 0x0283AA00 },
         { .reg = 0x00009888, .val = 0x0084F000 },
         { .reg = 0x00009888, .val = 0x02865500 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x14870010 },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0E880010 },
         { .reg = 0x00009888, .val = 0x00893000 },
         { .reg = 0x00009888, .val = 0x02A300AA },
         { .reg = 0x00009888, .val = 0x00A40F00 },
         { .reg = 0x00009888, .val = 0x02A60055 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x10A70010 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80010 },
         { .reg = 0x00009888, .val = 0x00A90300 },
         { .reg = 0x00009888, .val = 0x00C3AA00 },
         { .reg = 0x00009888, .val = 0x00C400F0 },
         { .reg = 0x00009888, .val = 0x00C65500 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0CC70010 },
         { .reg = 0x00009888, .val = 0x00C70A00 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x06C80010 },
         { .reg = 0x00009888, .val = 0x00C90030 },
         { .reg = 0x00009888, .val = 0x00E300AA },
         { .reg = 0x00009888, .val = 0x00E4000F },
         { .reg = 0x00009888, .val = 0x00E60055 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x08E70010 },
         { .reg = 0x00009888, .val = 0x00E7000A },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x02E80010 },
         { .reg = 0x00009888, .val = 0x00E90003 },
         { .reg = 0x00009888, .val = 0x0007AA55 },
         { .reg = 0x00009888, .val = 0x0208AAFF },
         { .reg = 0x00009888, .val = 0x000900FF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x00010F00 },
         { .reg = 0x00009888, .val = 0x020B0055 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x000C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext894__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext894__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext894__avg_gpu_core_frequency__max,acmgt3__ext894__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5469, 24, NULL,acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5470, 32, NULL,acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5471, 40, NULL,acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5472, 48, NULL,acmgt3__ext894__load_store_cache_number_of_bank_access_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext895_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext895";
   query->symbol_name = "Ext895";
   query->guid = "1cd63d28-50ed-4c69-8683-44eba28275b6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x17870004 },
         { .reg = 0x00009888, .val = 0x1B870004 },
         { .reg = 0x00009888, .val = 0x13880004 },
         { .reg = 0x00009888, .val = 0x17880004 },
         { .reg = 0x00009888, .val = 0x17A70004 },
         { .reg = 0x00009888, .val = 0x1BA70004 },
         { .reg = 0x00009888, .val = 0x13A80004 },
         { .reg = 0x00009888, .val = 0x17A80004 },
         { .reg = 0x00009888, .val = 0x17C70004 },
         { .reg = 0x00009888, .val = 0x1BC70004 },
         { .reg = 0x00009888, .val = 0x13C80004 },
         { .reg = 0x00009888, .val = 0x17C80004 },
         { .reg = 0x00009888, .val = 0x17E70004 },
         { .reg = 0x00009888, .val = 0x1BE70004 },
         { .reg = 0x00009888, .val = 0x13E80004 },
         { .reg = 0x00009888, .val = 0x17E80004 },
         { .reg = 0x00009888, .val = 0x0383AA00 },
         { .reg = 0x00009888, .val = 0x0184F000 },
         { .reg = 0x00009888, .val = 0x03865500 },
         { .reg = 0x00009888, .val = 0x05870020 },
         { .reg = 0x00009888, .val = 0x15870010 },
         { .reg = 0x00009888, .val = 0x03870A00 },
         { .reg = 0x00009888, .val = 0x01880020 },
         { .reg = 0x00009888, .val = 0x0F880010 },
         { .reg = 0x00009888, .val = 0x01893000 },
         { .reg = 0x00009888, .val = 0x03A300AA },
         { .reg = 0x00009888, .val = 0x01A40F00 },
         { .reg = 0x00009888, .val = 0x03A60055 },
         { .reg = 0x00009888, .val = 0x05A70020 },
         { .reg = 0x00009888, .val = 0x11A70010 },
         { .reg = 0x00009888, .val = 0x03A7000A },
         { .reg = 0x00009888, .val = 0x01A80020 },
         { .reg = 0x00009888, .val = 0x0BA80010 },
         { .reg = 0x00009888, .val = 0x01A90300 },
         { .reg = 0x00009888, .val = 0x01C3AA00 },
         { .reg = 0x00009888, .val = 0x01C400F0 },
         { .reg = 0x00009888, .val = 0x01C65500 },
         { .reg = 0x00009888, .val = 0x05C70020 },
         { .reg = 0x00009888, .val = 0x0DC70010 },
         { .reg = 0x00009888, .val = 0x01C70A00 },
         { .reg = 0x00009888, .val = 0x01C80020 },
         { .reg = 0x00009888, .val = 0x07C80010 },
         { .reg = 0x00009888, .val = 0x01C90030 },
         { .reg = 0x00009888, .val = 0x01E300AA },
         { .reg = 0x00009888, .val = 0x01E4000F },
         { .reg = 0x00009888, .val = 0x01E60055 },
         { .reg = 0x00009888, .val = 0x05E70020 },
         { .reg = 0x00009888, .val = 0x09E70010 },
         { .reg = 0x00009888, .val = 0x01E7000A },
         { .reg = 0x00009888, .val = 0x01E80020 },
         { .reg = 0x00009888, .val = 0x03E80010 },
         { .reg = 0x00009888, .val = 0x01E90003 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AA55 },
         { .reg = 0x00009888, .val = 0x0308AAFF },
         { .reg = 0x00009888, .val = 0x010900FF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x01010F00 },
         { .reg = 0x00009888, .val = 0x030B0055 },
         { .reg = 0x00009888, .val = 0x010200F0 },
         { .reg = 0x00009888, .val = 0x010C5500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E031CEA },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030D46 },
         { .reg = 0x00009888, .val = 0x2C031000 },
         { .reg = 0x00009888, .val = 0x32031000 },
         { .reg = 0x00009888, .val = 0x44030003 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030800 },
         { .reg = 0x00009888, .val = 0x48030040 },
         { .reg = 0x00009888, .val = 0x4A030603 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A031000 },
         { .reg = 0x00009888, .val = 0x40031842 },
         { .reg = 0x00009888, .val = 0x1C031000 },
         { .reg = 0x00009888, .val = 0x1E031000 },
         { .reg = 0x00009888, .val = 0x20031000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext895__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext895__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext895__avg_gpu_core_frequency__max,acmgt3__ext895__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5473, 24, NULL,acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5474, 32, NULL,acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5475, 40, NULL,acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5476, 48, NULL,acmgt3__ext895__load_store_cache_number_of_bank_access_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext896_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext896";
   query->symbol_name = "Ext896";
   query->guid = "ebd6f029-7260-4c80-9698-f18439c74959";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1882000C },
         { .reg = 0x00009888, .val = 0x18A2000C },
         { .reg = 0x00009888, .val = 0x18C2000C },
         { .reg = 0x00009888, .val = 0x18E2000C },
         { .reg = 0x00009888, .val = 0x1982000C },
         { .reg = 0x00009888, .val = 0x19A2000C },
         { .reg = 0x00009888, .val = 0x19C2000C },
         { .reg = 0x00009888, .val = 0x19E2000C },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext896__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext896__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext896__avg_gpu_core_frequency__max,acmgt3__ext896__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1794, 24, NULL,acmgt3__ext896__icache_hit_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1796, 32, NULL,acmgt3__ext896__icache_hit_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1798, 40, NULL,acmgt3__ext896__icache_hit_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1800, 48, NULL,acmgt3__ext896__icache_hit_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1802, 56, NULL,acmgt3__ext896__icache_hit_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1804, 64, NULL,acmgt3__ext896__icache_hit_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1806, 72, NULL,acmgt3__ext896__icache_hit_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1808, 80, NULL,acmgt3__ext896__icache_hit_bank0_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1795, 88, NULL,acmgt3__ext896__icache_miss_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1797, 96, NULL,acmgt3__ext896__icache_miss_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1799, 104, NULL,acmgt3__ext896__icache_miss_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1801, 112, NULL,acmgt3__ext896__icache_miss_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1803, 120, NULL,acmgt3__ext896__icache_miss_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1805, 128, NULL,acmgt3__ext896__icache_miss_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1807, 136, NULL,acmgt3__ext896__icache_miss_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1809, 144, NULL,acmgt3__ext896__icache_miss_bank0_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext897_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext897";
   query->symbol_name = "Ext897";
   query->guid = "4fef4fe4-17ad-4869-bef4-2ebdebff9f9d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1882000C },
         { .reg = 0x00009888, .val = 0x18A2000C },
         { .reg = 0x00009888, .val = 0x18C2000C },
         { .reg = 0x00009888, .val = 0x18E2000C },
         { .reg = 0x00009888, .val = 0x1982000C },
         { .reg = 0x00009888, .val = 0x19A2000C },
         { .reg = 0x00009888, .val = 0x19C2000C },
         { .reg = 0x00009888, .val = 0x19E2000C },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext897__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext897__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext897__avg_gpu_core_frequency__max,acmgt3__ext897__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3213, 24, NULL,acmgt3__ext897__icache_hit_bank0_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3214, 32, NULL,acmgt3__ext897__icache_hit_bank0_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3215, 40, NULL,acmgt3__ext897__icache_hit_bank0_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3216, 48, NULL,acmgt3__ext897__icache_hit_bank0_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3217, 56, NULL,acmgt3__ext897__icache_hit_bank0_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3218, 64, NULL,acmgt3__ext897__icache_hit_bank0_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3219, 72, NULL,acmgt3__ext897__icache_hit_bank0_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3220, 80, NULL,acmgt3__ext897__icache_hit_bank0_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3221, 88, NULL,acmgt3__ext897__icache_miss_bank0_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3222, 96, NULL,acmgt3__ext897__icache_miss_bank0_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3223, 104, NULL,acmgt3__ext897__icache_miss_bank0_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3224, 112, NULL,acmgt3__ext897__icache_miss_bank0_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3225, 120, NULL,acmgt3__ext897__icache_miss_bank0_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3226, 128, NULL,acmgt3__ext897__icache_miss_bank0_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3227, 136, NULL,acmgt3__ext897__icache_miss_bank0_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3228, 144, NULL,acmgt3__ext897__icache_miss_bank0_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext898_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext898";
   query->symbol_name = "Ext898";
   query->guid = "cca4086b-edba-4819-ab17-70039adaa90f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1882000C },
         { .reg = 0x00009888, .val = 0x18A2000C },
         { .reg = 0x00009888, .val = 0x18C2000C },
         { .reg = 0x00009888, .val = 0x18E2000C },
         { .reg = 0x00009888, .val = 0x1982000C },
         { .reg = 0x00009888, .val = 0x19A2000C },
         { .reg = 0x00009888, .val = 0x19C2000C },
         { .reg = 0x00009888, .val = 0x19E2000C },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext898__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext898__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext898__avg_gpu_core_frequency__max,acmgt3__ext898__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5477, 24, NULL,acmgt3__ext898__icache_hit_bank0_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5478, 32, NULL,acmgt3__ext898__icache_hit_bank0_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5479, 40, NULL,acmgt3__ext898__icache_hit_bank0_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5480, 48, NULL,acmgt3__ext898__icache_hit_bank0_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5481, 56, NULL,acmgt3__ext898__icache_hit_bank0_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5482, 64, NULL,acmgt3__ext898__icache_hit_bank0_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5483, 72, NULL,acmgt3__ext898__icache_hit_bank0_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5484, 80, NULL,acmgt3__ext898__icache_hit_bank0_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5485, 88, NULL,acmgt3__ext898__icache_miss_bank0_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5486, 96, NULL,acmgt3__ext898__icache_miss_bank0_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5487, 104, NULL,acmgt3__ext898__icache_miss_bank0_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5488, 112, NULL,acmgt3__ext898__icache_miss_bank0_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5489, 120, NULL,acmgt3__ext898__icache_miss_bank0_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5490, 128, NULL,acmgt3__ext898__icache_miss_bank0_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5491, 136, NULL,acmgt3__ext898__icache_miss_bank0_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5492, 144, NULL,acmgt3__ext898__icache_miss_bank0_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext899_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext899";
   query->symbol_name = "Ext899";
   query->guid = "de978459-938a-4d54-8a6f-0860fba80b44";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1882000C },
         { .reg = 0x00009888, .val = 0x18A2000C },
         { .reg = 0x00009888, .val = 0x18C2000C },
         { .reg = 0x00009888, .val = 0x18E2000C },
         { .reg = 0x00009888, .val = 0x1982000C },
         { .reg = 0x00009888, .val = 0x19A2000C },
         { .reg = 0x00009888, .val = 0x19C2000C },
         { .reg = 0x00009888, .val = 0x19E2000C },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext899__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext899__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext899__avg_gpu_core_frequency__max,acmgt3__ext899__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5493, 24, NULL,acmgt3__ext899__icache_hit_bank0_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5494, 32, NULL,acmgt3__ext899__icache_hit_bank0_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5495, 40, NULL,acmgt3__ext899__icache_hit_bank0_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5496, 48, NULL,acmgt3__ext899__icache_hit_bank0_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5497, 56, NULL,acmgt3__ext899__icache_hit_bank0_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5498, 64, NULL,acmgt3__ext899__icache_hit_bank0_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5499, 72, NULL,acmgt3__ext899__icache_hit_bank0_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5500, 80, NULL,acmgt3__ext899__icache_hit_bank0_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5501, 88, NULL,acmgt3__ext899__icache_miss_bank0_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5502, 96, NULL,acmgt3__ext899__icache_miss_bank0_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5503, 104, NULL,acmgt3__ext899__icache_miss_bank0_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5504, 112, NULL,acmgt3__ext899__icache_miss_bank0_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5505, 120, NULL,acmgt3__ext899__icache_miss_bank0_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5506, 128, NULL,acmgt3__ext899__icache_miss_bank0_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5507, 136, NULL,acmgt3__ext899__icache_miss_bank0_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5508, 144, NULL,acmgt3__ext899__icache_miss_bank0_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext900_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext900";
   query->symbol_name = "Ext900";
   query->guid = "31c70c2d-ab25-4333-8242-c980e65fe83b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18820011 },
         { .reg = 0x00009888, .val = 0x18A20011 },
         { .reg = 0x00009888, .val = 0x18C20011 },
         { .reg = 0x00009888, .val = 0x18E20011 },
         { .reg = 0x00009888, .val = 0x19820011 },
         { .reg = 0x00009888, .val = 0x19A20011 },
         { .reg = 0x00009888, .val = 0x19C20011 },
         { .reg = 0x00009888, .val = 0x19E20011 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext900__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext900__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext900__avg_gpu_core_frequency__max,acmgt3__ext900__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1810, 24, NULL,acmgt3__ext900__icache_hit_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1812, 32, NULL,acmgt3__ext900__icache_hit_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1814, 40, NULL,acmgt3__ext900__icache_hit_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1816, 48, NULL,acmgt3__ext900__icache_hit_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1818, 56, NULL,acmgt3__ext900__icache_hit_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1820, 64, NULL,acmgt3__ext900__icache_hit_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1822, 72, NULL,acmgt3__ext900__icache_hit_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1824, 80, NULL,acmgt3__ext900__icache_hit_bank1_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1811, 88, NULL,acmgt3__ext900__icache_miss_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1813, 96, NULL,acmgt3__ext900__icache_miss_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1815, 104, NULL,acmgt3__ext900__icache_miss_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1817, 112, NULL,acmgt3__ext900__icache_miss_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1819, 120, NULL,acmgt3__ext900__icache_miss_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1821, 128, NULL,acmgt3__ext900__icache_miss_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1823, 136, NULL,acmgt3__ext900__icache_miss_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1825, 144, NULL,acmgt3__ext900__icache_miss_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext901_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext901";
   query->symbol_name = "Ext901";
   query->guid = "bcf7ff4e-50dc-45f7-8c63-d649dc126717";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18820011 },
         { .reg = 0x00009888, .val = 0x18A20011 },
         { .reg = 0x00009888, .val = 0x18C20011 },
         { .reg = 0x00009888, .val = 0x18E20011 },
         { .reg = 0x00009888, .val = 0x19820011 },
         { .reg = 0x00009888, .val = 0x19A20011 },
         { .reg = 0x00009888, .val = 0x19C20011 },
         { .reg = 0x00009888, .val = 0x19E20011 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext901__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext901__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext901__avg_gpu_core_frequency__max,acmgt3__ext901__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3229, 24, NULL,acmgt3__ext901__icache_hit_bank1_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3230, 32, NULL,acmgt3__ext901__icache_hit_bank1_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3231, 40, NULL,acmgt3__ext901__icache_hit_bank1_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3232, 48, NULL,acmgt3__ext901__icache_hit_bank1_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3233, 56, NULL,acmgt3__ext901__icache_hit_bank1_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3234, 64, NULL,acmgt3__ext901__icache_hit_bank1_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3235, 72, NULL,acmgt3__ext901__icache_hit_bank1_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3236, 80, NULL,acmgt3__ext901__icache_hit_bank1_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3237, 88, NULL,acmgt3__ext901__icache_miss_bank1_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3238, 96, NULL,acmgt3__ext901__icache_miss_bank1_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3239, 104, NULL,acmgt3__ext901__icache_miss_bank1_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3240, 112, NULL,acmgt3__ext901__icache_miss_bank1_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3241, 120, NULL,acmgt3__ext901__icache_miss_bank1_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3242, 128, NULL,acmgt3__ext901__icache_miss_bank1_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3243, 136, NULL,acmgt3__ext901__icache_miss_bank1_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3244, 144, NULL,acmgt3__ext901__icache_miss_bank1_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext902_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext902";
   query->symbol_name = "Ext902";
   query->guid = "c79fc1e5-c7b5-4dae-ba39-4861365060f3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18820011 },
         { .reg = 0x00009888, .val = 0x18A20011 },
         { .reg = 0x00009888, .val = 0x18C20011 },
         { .reg = 0x00009888, .val = 0x18E20011 },
         { .reg = 0x00009888, .val = 0x19820011 },
         { .reg = 0x00009888, .val = 0x19A20011 },
         { .reg = 0x00009888, .val = 0x19C20011 },
         { .reg = 0x00009888, .val = 0x19E20011 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext902__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext902__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext902__avg_gpu_core_frequency__max,acmgt3__ext902__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5509, 24, NULL,acmgt3__ext902__icache_hit_bank1_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5510, 32, NULL,acmgt3__ext902__icache_hit_bank1_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5511, 40, NULL,acmgt3__ext902__icache_hit_bank1_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5512, 48, NULL,acmgt3__ext902__icache_hit_bank1_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5513, 56, NULL,acmgt3__ext902__icache_hit_bank1_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5514, 64, NULL,acmgt3__ext902__icache_hit_bank1_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5515, 72, NULL,acmgt3__ext902__icache_hit_bank1_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5516, 80, NULL,acmgt3__ext902__icache_hit_bank1_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5517, 88, NULL,acmgt3__ext902__icache_miss_bank1_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5518, 96, NULL,acmgt3__ext902__icache_miss_bank1_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5519, 104, NULL,acmgt3__ext902__icache_miss_bank1_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5520, 112, NULL,acmgt3__ext902__icache_miss_bank1_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5521, 120, NULL,acmgt3__ext902__icache_miss_bank1_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5522, 128, NULL,acmgt3__ext902__icache_miss_bank1_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5523, 136, NULL,acmgt3__ext902__icache_miss_bank1_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5524, 144, NULL,acmgt3__ext902__icache_miss_bank1_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext903_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext903";
   query->symbol_name = "Ext903";
   query->guid = "a213b5c5-965f-4daf-8a43-a254fec22419";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18820011 },
         { .reg = 0x00009888, .val = 0x18A20011 },
         { .reg = 0x00009888, .val = 0x18C20011 },
         { .reg = 0x00009888, .val = 0x18E20011 },
         { .reg = 0x00009888, .val = 0x19820011 },
         { .reg = 0x00009888, .val = 0x19A20011 },
         { .reg = 0x00009888, .val = 0x19C20011 },
         { .reg = 0x00009888, .val = 0x19E20011 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext903__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext903__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext903__avg_gpu_core_frequency__max,acmgt3__ext903__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5525, 24, NULL,acmgt3__ext903__icache_hit_bank1_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5526, 32, NULL,acmgt3__ext903__icache_hit_bank1_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5527, 40, NULL,acmgt3__ext903__icache_hit_bank1_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5528, 48, NULL,acmgt3__ext903__icache_hit_bank1_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5529, 56, NULL,acmgt3__ext903__icache_hit_bank1_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5530, 64, NULL,acmgt3__ext903__icache_hit_bank1_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5531, 72, NULL,acmgt3__ext903__icache_hit_bank1_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5532, 80, NULL,acmgt3__ext903__icache_hit_bank1_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5533, 88, NULL,acmgt3__ext903__icache_miss_bank1_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5534, 96, NULL,acmgt3__ext903__icache_miss_bank1_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5535, 104, NULL,acmgt3__ext903__icache_miss_bank1_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5536, 112, NULL,acmgt3__ext903__icache_miss_bank1_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5537, 120, NULL,acmgt3__ext903__icache_miss_bank1_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5538, 128, NULL,acmgt3__ext903__icache_miss_bank1_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5539, 136, NULL,acmgt3__ext903__icache_miss_bank1_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5540, 144, NULL,acmgt3__ext903__icache_miss_bank1_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext904_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext904";
   query->symbol_name = "Ext904";
   query->guid = "3a901be2-0b46-4e5e-8852-dc0187f7a829";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18820016 },
         { .reg = 0x00009888, .val = 0x18A20016 },
         { .reg = 0x00009888, .val = 0x18C20016 },
         { .reg = 0x00009888, .val = 0x18E20016 },
         { .reg = 0x00009888, .val = 0x19820016 },
         { .reg = 0x00009888, .val = 0x19A20016 },
         { .reg = 0x00009888, .val = 0x19C20016 },
         { .reg = 0x00009888, .val = 0x19E20016 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext904__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext904__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext904__avg_gpu_core_frequency__max,acmgt3__ext904__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1826, 24, NULL,acmgt3__ext904__icache_hit_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1828, 32, NULL,acmgt3__ext904__icache_hit_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1830, 40, NULL,acmgt3__ext904__icache_hit_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1832, 48, NULL,acmgt3__ext904__icache_hit_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1834, 56, NULL,acmgt3__ext904__icache_hit_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1836, 64, NULL,acmgt3__ext904__icache_hit_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1838, 72, NULL,acmgt3__ext904__icache_hit_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1840, 80, NULL,acmgt3__ext904__icache_hit_bank2_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1827, 88, NULL,acmgt3__ext904__icache_miss_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1829, 96, NULL,acmgt3__ext904__icache_miss_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1831, 104, NULL,acmgt3__ext904__icache_miss_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1833, 112, NULL,acmgt3__ext904__icache_miss_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1835, 120, NULL,acmgt3__ext904__icache_miss_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1837, 128, NULL,acmgt3__ext904__icache_miss_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1839, 136, NULL,acmgt3__ext904__icache_miss_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1841, 144, NULL,acmgt3__ext904__icache_miss_bank2_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext905_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext905";
   query->symbol_name = "Ext905";
   query->guid = "9c547e29-18b8-408c-8c43-bcc3c756eed3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18820016 },
         { .reg = 0x00009888, .val = 0x18A20016 },
         { .reg = 0x00009888, .val = 0x18C20016 },
         { .reg = 0x00009888, .val = 0x18E20016 },
         { .reg = 0x00009888, .val = 0x19820016 },
         { .reg = 0x00009888, .val = 0x19A20016 },
         { .reg = 0x00009888, .val = 0x19C20016 },
         { .reg = 0x00009888, .val = 0x19E20016 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext905__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext905__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext905__avg_gpu_core_frequency__max,acmgt3__ext905__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3245, 24, NULL,acmgt3__ext905__icache_hit_bank2_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3246, 32, NULL,acmgt3__ext905__icache_hit_bank2_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3247, 40, NULL,acmgt3__ext905__icache_hit_bank2_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3248, 48, NULL,acmgt3__ext905__icache_hit_bank2_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3249, 56, NULL,acmgt3__ext905__icache_hit_bank2_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3250, 64, NULL,acmgt3__ext905__icache_hit_bank2_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3251, 72, NULL,acmgt3__ext905__icache_hit_bank2_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3252, 80, NULL,acmgt3__ext905__icache_hit_bank2_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3253, 88, NULL,acmgt3__ext905__icache_miss_bank2_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3254, 96, NULL,acmgt3__ext905__icache_miss_bank2_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3255, 104, NULL,acmgt3__ext905__icache_miss_bank2_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3256, 112, NULL,acmgt3__ext905__icache_miss_bank2_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3257, 120, NULL,acmgt3__ext905__icache_miss_bank2_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3258, 128, NULL,acmgt3__ext905__icache_miss_bank2_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3259, 136, NULL,acmgt3__ext905__icache_miss_bank2_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3260, 144, NULL,acmgt3__ext905__icache_miss_bank2_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext906_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext906";
   query->symbol_name = "Ext906";
   query->guid = "64ce4293-1f46-434d-a9e4-709b2fa8b0db";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18820016 },
         { .reg = 0x00009888, .val = 0x18A20016 },
         { .reg = 0x00009888, .val = 0x18C20016 },
         { .reg = 0x00009888, .val = 0x18E20016 },
         { .reg = 0x00009888, .val = 0x19820016 },
         { .reg = 0x00009888, .val = 0x19A20016 },
         { .reg = 0x00009888, .val = 0x19C20016 },
         { .reg = 0x00009888, .val = 0x19E20016 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext906__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext906__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext906__avg_gpu_core_frequency__max,acmgt3__ext906__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5541, 24, NULL,acmgt3__ext906__icache_hit_bank2_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5542, 32, NULL,acmgt3__ext906__icache_hit_bank2_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5543, 40, NULL,acmgt3__ext906__icache_hit_bank2_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5544, 48, NULL,acmgt3__ext906__icache_hit_bank2_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5545, 56, NULL,acmgt3__ext906__icache_hit_bank2_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5546, 64, NULL,acmgt3__ext906__icache_hit_bank2_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5547, 72, NULL,acmgt3__ext906__icache_hit_bank2_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5548, 80, NULL,acmgt3__ext906__icache_hit_bank2_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5549, 88, NULL,acmgt3__ext906__icache_miss_bank2_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5550, 96, NULL,acmgt3__ext906__icache_miss_bank2_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5551, 104, NULL,acmgt3__ext906__icache_miss_bank2_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5552, 112, NULL,acmgt3__ext906__icache_miss_bank2_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5553, 120, NULL,acmgt3__ext906__icache_miss_bank2_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5554, 128, NULL,acmgt3__ext906__icache_miss_bank2_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5555, 136, NULL,acmgt3__ext906__icache_miss_bank2_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5556, 144, NULL,acmgt3__ext906__icache_miss_bank2_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext907_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext907";
   query->symbol_name = "Ext907";
   query->guid = "73dc617b-8971-4a76-96e9-2cf205acc81e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18820016 },
         { .reg = 0x00009888, .val = 0x18A20016 },
         { .reg = 0x00009888, .val = 0x18C20016 },
         { .reg = 0x00009888, .val = 0x18E20016 },
         { .reg = 0x00009888, .val = 0x19820016 },
         { .reg = 0x00009888, .val = 0x19A20016 },
         { .reg = 0x00009888, .val = 0x19C20016 },
         { .reg = 0x00009888, .val = 0x19E20016 },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext907__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext907__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext907__avg_gpu_core_frequency__max,acmgt3__ext907__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5557, 24, NULL,acmgt3__ext907__icache_hit_bank2_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5558, 32, NULL,acmgt3__ext907__icache_hit_bank2_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5559, 40, NULL,acmgt3__ext907__icache_hit_bank2_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5560, 48, NULL,acmgt3__ext907__icache_hit_bank2_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5561, 56, NULL,acmgt3__ext907__icache_hit_bank2_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5562, 64, NULL,acmgt3__ext907__icache_hit_bank2_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5563, 72, NULL,acmgt3__ext907__icache_hit_bank2_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5564, 80, NULL,acmgt3__ext907__icache_hit_bank2_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5565, 88, NULL,acmgt3__ext907__icache_miss_bank2_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5566, 96, NULL,acmgt3__ext907__icache_miss_bank2_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5567, 104, NULL,acmgt3__ext907__icache_miss_bank2_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5568, 112, NULL,acmgt3__ext907__icache_miss_bank2_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5569, 120, NULL,acmgt3__ext907__icache_miss_bank2_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5570, 128, NULL,acmgt3__ext907__icache_miss_bank2_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5571, 136, NULL,acmgt3__ext907__icache_miss_bank2_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5572, 144, NULL,acmgt3__ext907__icache_miss_bank2_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext908_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext908";
   query->symbol_name = "Ext908";
   query->guid = "9eef500b-7077-4fc2-9101-dd900833104f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1882001B },
         { .reg = 0x00009888, .val = 0x18A2001B },
         { .reg = 0x00009888, .val = 0x18C2001B },
         { .reg = 0x00009888, .val = 0x18E2001B },
         { .reg = 0x00009888, .val = 0x1982001B },
         { .reg = 0x00009888, .val = 0x19A2001B },
         { .reg = 0x00009888, .val = 0x19C2001B },
         { .reg = 0x00009888, .val = 0x19E2001B },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext908__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext908__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext908__avg_gpu_core_frequency__max,acmgt3__ext908__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1842, 24, NULL,acmgt3__ext908__icache_hit_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1844, 32, NULL,acmgt3__ext908__icache_hit_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1846, 40, NULL,acmgt3__ext908__icache_hit_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1848, 48, NULL,acmgt3__ext908__icache_hit_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1850, 56, NULL,acmgt3__ext908__icache_hit_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1852, 64, NULL,acmgt3__ext908__icache_hit_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1854, 72, NULL,acmgt3__ext908__icache_hit_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1856, 80, NULL,acmgt3__ext908__icache_hit_bank3_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1843, 88, NULL,acmgt3__ext908__icache_miss_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1845, 96, NULL,acmgt3__ext908__icache_miss_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1847, 104, NULL,acmgt3__ext908__icache_miss_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1849, 112, NULL,acmgt3__ext908__icache_miss_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1851, 120, NULL,acmgt3__ext908__icache_miss_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1853, 128, NULL,acmgt3__ext908__icache_miss_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1855, 136, NULL,acmgt3__ext908__icache_miss_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1857, 144, NULL,acmgt3__ext908__icache_miss_bank3_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext909_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext909";
   query->symbol_name = "Ext909";
   query->guid = "d1160adc-3cd3-4dd0-825b-7bc15e319191";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x1882001B },
         { .reg = 0x00009888, .val = 0x18A2001B },
         { .reg = 0x00009888, .val = 0x18C2001B },
         { .reg = 0x00009888, .val = 0x18E2001B },
         { .reg = 0x00009888, .val = 0x1982001B },
         { .reg = 0x00009888, .val = 0x19A2001B },
         { .reg = 0x00009888, .val = 0x19C2001B },
         { .reg = 0x00009888, .val = 0x19E2001B },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext909__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext909__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext909__avg_gpu_core_frequency__max,acmgt3__ext909__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3261, 24, NULL,acmgt3__ext909__icache_hit_bank3_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3262, 32, NULL,acmgt3__ext909__icache_hit_bank3_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3263, 40, NULL,acmgt3__ext909__icache_hit_bank3_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3264, 48, NULL,acmgt3__ext909__icache_hit_bank3_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3265, 56, NULL,acmgt3__ext909__icache_hit_bank3_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3266, 64, NULL,acmgt3__ext909__icache_hit_bank3_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3267, 72, NULL,acmgt3__ext909__icache_hit_bank3_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3268, 80, NULL,acmgt3__ext909__icache_hit_bank3_xecore15__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 3269, 88, NULL,acmgt3__ext909__icache_miss_bank3_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 3270, 96, NULL,acmgt3__ext909__icache_miss_bank3_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 3271, 104, NULL,acmgt3__ext909__icache_miss_bank3_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 3272, 112, NULL,acmgt3__ext909__icache_miss_bank3_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 3273, 120, NULL,acmgt3__ext909__icache_miss_bank3_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 3274, 128, NULL,acmgt3__ext909__icache_miss_bank3_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 3275, 136, NULL,acmgt3__ext909__icache_miss_bank3_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 3276, 144, NULL,acmgt3__ext909__icache_miss_bank3_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext910_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext910";
   query->symbol_name = "Ext910";
   query->guid = "6ba0f6ff-cc07-4ba5-81c6-87e4279c9867";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x1882001B },
         { .reg = 0x00009888, .val = 0x18A2001B },
         { .reg = 0x00009888, .val = 0x18C2001B },
         { .reg = 0x00009888, .val = 0x18E2001B },
         { .reg = 0x00009888, .val = 0x1982001B },
         { .reg = 0x00009888, .val = 0x19A2001B },
         { .reg = 0x00009888, .val = 0x19C2001B },
         { .reg = 0x00009888, .val = 0x19E2001B },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext910__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext910__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext910__avg_gpu_core_frequency__max,acmgt3__ext910__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5573, 24, NULL,acmgt3__ext910__icache_hit_bank3_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5574, 32, NULL,acmgt3__ext910__icache_hit_bank3_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5575, 40, NULL,acmgt3__ext910__icache_hit_bank3_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5576, 48, NULL,acmgt3__ext910__icache_hit_bank3_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5577, 56, NULL,acmgt3__ext910__icache_hit_bank3_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5578, 64, NULL,acmgt3__ext910__icache_hit_bank3_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5579, 72, NULL,acmgt3__ext910__icache_hit_bank3_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5580, 80, NULL,acmgt3__ext910__icache_hit_bank3_xecore23__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5581, 88, NULL,acmgt3__ext910__icache_miss_bank3_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5582, 96, NULL,acmgt3__ext910__icache_miss_bank3_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5583, 104, NULL,acmgt3__ext910__icache_miss_bank3_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5584, 112, NULL,acmgt3__ext910__icache_miss_bank3_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5585, 120, NULL,acmgt3__ext910__icache_miss_bank3_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5586, 128, NULL,acmgt3__ext910__icache_miss_bank3_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5587, 136, NULL,acmgt3__ext910__icache_miss_bank3_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5588, 144, NULL,acmgt3__ext910__icache_miss_bank3_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext911_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext911";
   query->symbol_name = "Ext911";
   query->guid = "09a68225-f72f-4750-b6f1-b7f2a7b7bf7e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x1882001B },
         { .reg = 0x00009888, .val = 0x18A2001B },
         { .reg = 0x00009888, .val = 0x18C2001B },
         { .reg = 0x00009888, .val = 0x18E2001B },
         { .reg = 0x00009888, .val = 0x1982001B },
         { .reg = 0x00009888, .val = 0x19A2001B },
         { .reg = 0x00009888, .val = 0x19C2001B },
         { .reg = 0x00009888, .val = 0x19E2001B },
         { .reg = 0x00009888, .val = 0x04820002 },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x16820005 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00830001 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x00848001 },
         { .reg = 0x00009888, .val = 0x00860001 },
         { .reg = 0x00009888, .val = 0x02864000 },
         { .reg = 0x00009888, .val = 0x04A20002 },
         { .reg = 0x00009888, .val = 0x08A20006 },
         { .reg = 0x00009888, .val = 0x14A20140 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A30004 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x00A44002 },
         { .reg = 0x00009888, .val = 0x00A60004 },
         { .reg = 0x00009888, .val = 0x02A61000 },
         { .reg = 0x00009888, .val = 0x04C20002 },
         { .reg = 0x00009888, .val = 0x08C20180 },
         { .reg = 0x00009888, .val = 0x14C20005 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C30010 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x00C42004 },
         { .reg = 0x00009888, .val = 0x00C60010 },
         { .reg = 0x00009888, .val = 0x02C60400 },
         { .reg = 0x00009888, .val = 0x04E20002 },
         { .reg = 0x00009888, .val = 0x0AE20006 },
         { .reg = 0x00009888, .val = 0x12E20140 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E30040 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E41008 },
         { .reg = 0x00009888, .val = 0x00E60040 },
         { .reg = 0x00009888, .val = 0x02E60100 },
         { .reg = 0x00009888, .val = 0x05820002 },
         { .reg = 0x00009888, .val = 0x0B820180 },
         { .reg = 0x00009888, .val = 0x13820005 },
         { .reg = 0x00009888, .val = 0x01820000 },
         { .reg = 0x00009888, .val = 0x03820000 },
         { .reg = 0x00009888, .val = 0x01830100 },
         { .reg = 0x00009888, .val = 0x03830040 },
         { .reg = 0x00009888, .val = 0x01840810 },
         { .reg = 0x00009888, .val = 0x01860100 },
         { .reg = 0x00009888, .val = 0x03860040 },
         { .reg = 0x00009888, .val = 0x05A20002 },
         { .reg = 0x00009888, .val = 0x0DA20006 },
         { .reg = 0x00009888, .val = 0x11A20140 },
         { .reg = 0x00009888, .val = 0x01A20000 },
         { .reg = 0x00009888, .val = 0x03A20000 },
         { .reg = 0x00009888, .val = 0x01A30400 },
         { .reg = 0x00009888, .val = 0x03A30010 },
         { .reg = 0x00009888, .val = 0x01A40420 },
         { .reg = 0x00009888, .val = 0x01A60400 },
         { .reg = 0x00009888, .val = 0x03A60010 },
         { .reg = 0x00009888, .val = 0x05C20002 },
         { .reg = 0x00009888, .val = 0x0DC20180 },
         { .reg = 0x00009888, .val = 0x11C20005 },
         { .reg = 0x00009888, .val = 0x01C20000 },
         { .reg = 0x00009888, .val = 0x03C20000 },
         { .reg = 0x00009888, .val = 0x01C31000 },
         { .reg = 0x00009888, .val = 0x03C30004 },
         { .reg = 0x00009888, .val = 0x01C40240 },
         { .reg = 0x00009888, .val = 0x01C61000 },
         { .reg = 0x00009888, .val = 0x03C60004 },
         { .reg = 0x00009888, .val = 0x05E20002 },
         { .reg = 0x00009888, .val = 0x0FE20146 },
         { .reg = 0x00009888, .val = 0x01E20000 },
         { .reg = 0x00009888, .val = 0x03E20000 },
         { .reg = 0x00009888, .val = 0x01E34000 },
         { .reg = 0x00009888, .val = 0x03E30001 },
         { .reg = 0x00009888, .val = 0x01E40180 },
         { .reg = 0x00009888, .val = 0x01E64000 },
         { .reg = 0x00009888, .val = 0x03E60001 },
         { .reg = 0x00009888, .val = 0x00030FF0 },
         { .reg = 0x00009888, .val = 0x00070060 },
         { .reg = 0x00009888, .val = 0x02070900 },
         { .reg = 0x00009888, .val = 0x0008FF0E },
         { .reg = 0x00009888, .val = 0x0208B0FF },
         { .reg = 0x00009888, .val = 0x0009300C },
         { .reg = 0x00009888, .val = 0x000A55A5 },
         { .reg = 0x00009888, .val = 0x020A5A55 },
         { .reg = 0x00009888, .val = 0x00014FF2 },
         { .reg = 0x00009888, .val = 0x000BAA04 },
         { .reg = 0x00009888, .val = 0x020B10AA },
         { .reg = 0x00009888, .val = 0x00022004 },
         { .reg = 0x00009888, .val = 0x000C0010 },
         { .reg = 0x00009888, .val = 0x020C0400 },
         { .reg = 0x00009888, .val = 0x01076000 },
         { .reg = 0x00009888, .val = 0x03070009 },
         { .reg = 0x00009888, .val = 0x01080E00 },
         { .reg = 0x00009888, .val = 0x030800B0 },
         { .reg = 0x00009888, .val = 0x010903C0 },
         { .reg = 0x00009888, .val = 0x010AA500 },
         { .reg = 0x00009888, .val = 0x030A005A },
         { .reg = 0x00009888, .val = 0x01010420 },
         { .reg = 0x00009888, .val = 0x010B0400 },
         { .reg = 0x00009888, .val = 0x030B0010 },
         { .reg = 0x00009888, .val = 0x01020240 },
         { .reg = 0x00009888, .val = 0x010C1000 },
         { .reg = 0x00009888, .val = 0x030C0004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E03086A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203200A },
         { .reg = 0x00009888, .val = 0x2C033000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030047 },
         { .reg = 0x00009888, .val = 0x38031000 },
         { .reg = 0x00009888, .val = 0x46030003 },
         { .reg = 0x00009888, .val = 0x480300A0 },
         { .reg = 0x00009888, .val = 0x4A03000A },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18031000 },
         { .reg = 0x00009888, .val = 0x1A037000 },
         { .reg = 0x00009888, .val = 0x40030107 },
         { .reg = 0x00009888, .val = 0x1C033000 },
         { .reg = 0x00009888, .val = 0x1E037000 },
         { .reg = 0x00009888, .val = 0x20037000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000F7EF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FBDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FDBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext911__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext911__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext911__avg_gpu_core_frequency__max,acmgt3__ext911__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5589, 24, NULL,acmgt3__ext911__icache_hit_bank3_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5590, 32, NULL,acmgt3__ext911__icache_hit_bank3_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5591, 40, NULL,acmgt3__ext911__icache_hit_bank3_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5592, 48, NULL,acmgt3__ext911__icache_hit_bank3_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5593, 56, NULL,acmgt3__ext911__icache_hit_bank3_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5594, 64, NULL,acmgt3__ext911__icache_hit_bank3_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5595, 72, NULL,acmgt3__ext911__icache_hit_bank3_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5596, 80, NULL,acmgt3__ext911__icache_hit_bank3_xecore31__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5597, 88, NULL,acmgt3__ext911__icache_miss_bank3_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5598, 96, NULL,acmgt3__ext911__icache_miss_bank3_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5599, 104, NULL,acmgt3__ext911__icache_miss_bank3_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5600, 112, NULL,acmgt3__ext911__icache_miss_bank3_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5601, 120, NULL,acmgt3__ext911__icache_miss_bank3_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5602, 128, NULL,acmgt3__ext911__icache_miss_bank3_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5603, 136, NULL,acmgt3__ext911__icache_miss_bank3_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5604, 144, NULL,acmgt3__ext911__icache_miss_bank3_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext912_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext912";
   query->symbol_name = "Ext912";
   query->guid = "76e4db74-d6d2-4774-80cd-702f27e15675";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext912__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext912__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext912__avg_gpu_core_frequency__max,acmgt3__ext912__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1766, 24, NULL,acmgt3__ext912__slm_bank_conflict_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext913_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext913";
   query->symbol_name = "Ext913";
   query->guid = "3506a146-a056-484d-bc76-191ba6ed5036";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18A914C0 },
         { .reg = 0x00009888, .val = 0x1EA900A6 },
         { .reg = 0x00009888, .val = 0x22A91800 },
         { .reg = 0x00009888, .val = 0x24A90005 },
         { .reg = 0x00009888, .val = 0x28A914C0 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A90C31 },
         { .reg = 0x00009888, .val = 0x08A90FBF },
         { .reg = 0x00009888, .val = 0x0AA90821 },
         { .reg = 0x00009888, .val = 0x0CA90BAF },
         { .reg = 0x00009888, .val = 0x0EA90411 },
         { .reg = 0x00009888, .val = 0x10A9079F },
         { .reg = 0x00009888, .val = 0x12A90001 },
         { .reg = 0x00009888, .val = 0x14A9038F },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext913__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext913__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext913__avg_gpu_core_frequency__max,acmgt3__ext913__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1767, 24, NULL,acmgt3__ext913__slm_bank_conflict_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext914_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext914";
   query->symbol_name = "Ext914";
   query->guid = "3846aa70-3952-4ad3-af8a-6463b74c38c5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18C914C0 },
         { .reg = 0x00009888, .val = 0x1EC900A6 },
         { .reg = 0x00009888, .val = 0x22C91800 },
         { .reg = 0x00009888, .val = 0x24C90005 },
         { .reg = 0x00009888, .val = 0x28C914C0 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C90C31 },
         { .reg = 0x00009888, .val = 0x08C90FBF },
         { .reg = 0x00009888, .val = 0x0AC90821 },
         { .reg = 0x00009888, .val = 0x0CC90BAF },
         { .reg = 0x00009888, .val = 0x0EC90411 },
         { .reg = 0x00009888, .val = 0x10C9079F },
         { .reg = 0x00009888, .val = 0x12C90001 },
         { .reg = 0x00009888, .val = 0x14C9038F },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext914__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext914__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext914__avg_gpu_core_frequency__max,acmgt3__ext914__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1768, 24, NULL,acmgt3__ext914__slm_bank_conflict_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext915_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext915";
   query->symbol_name = "Ext915";
   query->guid = "e2a3f9b4-7fc0-4229-8f7f-2f8bf4f381e5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext915__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext915__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext915__avg_gpu_core_frequency__max,acmgt3__ext915__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1769, 24, NULL,acmgt3__ext915__slm_bank_conflict_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext916_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext916";
   query->symbol_name = "Ext916";
   query->guid = "ae92f979-3dfd-4172-9fd3-6551c9c938cb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext916__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext916__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext916__avg_gpu_core_frequency__max,acmgt3__ext916__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 1770, 24, NULL,acmgt3__ext916__slm_bank_conflict_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext917_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext917";
   query->symbol_name = "Ext917";
   query->guid = "2f2acb42-910b-4312-b86d-2f3e13ea5e1c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x19A914C0 },
         { .reg = 0x00009888, .val = 0x1FA900A6 },
         { .reg = 0x00009888, .val = 0x23A91800 },
         { .reg = 0x00009888, .val = 0x25A90005 },
         { .reg = 0x00009888, .val = 0x29A914C0 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A90C31 },
         { .reg = 0x00009888, .val = 0x09A90FBF },
         { .reg = 0x00009888, .val = 0x0BA90821 },
         { .reg = 0x00009888, .val = 0x0DA90BAF },
         { .reg = 0x00009888, .val = 0x0FA90411 },
         { .reg = 0x00009888, .val = 0x11A9079F },
         { .reg = 0x00009888, .val = 0x13A90001 },
         { .reg = 0x00009888, .val = 0x15A9038F },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext917__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext917__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext917__avg_gpu_core_frequency__max,acmgt3__ext917__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 1771, 24, NULL,acmgt3__ext917__slm_bank_conflict_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext918_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext918";
   query->symbol_name = "Ext918";
   query->guid = "40216875-613d-4693-ba6d-1c6a37157b32";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x19C914C0 },
         { .reg = 0x00009888, .val = 0x1FC900A6 },
         { .reg = 0x00009888, .val = 0x23C91800 },
         { .reg = 0x00009888, .val = 0x25C90005 },
         { .reg = 0x00009888, .val = 0x29C914C0 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C90C31 },
         { .reg = 0x00009888, .val = 0x09C90FBF },
         { .reg = 0x00009888, .val = 0x0BC90821 },
         { .reg = 0x00009888, .val = 0x0DC90BAF },
         { .reg = 0x00009888, .val = 0x0FC90411 },
         { .reg = 0x00009888, .val = 0x11C9079F },
         { .reg = 0x00009888, .val = 0x13C90001 },
         { .reg = 0x00009888, .val = 0x15C9038F },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext918__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext918__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext918__avg_gpu_core_frequency__max,acmgt3__ext918__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 1772, 24, NULL,acmgt3__ext918__slm_bank_conflict_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext919_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext919";
   query->symbol_name = "Ext919";
   query->guid = "db527284-999a-4f23-b319-4ccac15c54c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext919__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext919__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext919__avg_gpu_core_frequency__max,acmgt3__ext919__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 1773, 24, NULL,acmgt3__ext919__slm_bank_conflict_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext920_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext920";
   query->symbol_name = "Ext920";
   query->guid = "17b8db25-a815-4616-9251-caa558af0db1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext920__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext920__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext920__avg_gpu_core_frequency__max,acmgt3__ext920__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_uint64(query, 2531, 24, NULL,acmgt3__ext920__slm_bank_conflict_count_xecore8__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext921_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext921";
   query->symbol_name = "Ext921";
   query->guid = "7c5214fa-e627-46dd-bf73-96b97e3b46cd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18A914C0 },
         { .reg = 0x00009888, .val = 0x1EA900A6 },
         { .reg = 0x00009888, .val = 0x22A91800 },
         { .reg = 0x00009888, .val = 0x24A90005 },
         { .reg = 0x00009888, .val = 0x28A914C0 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A90C31 },
         { .reg = 0x00009888, .val = 0x08A90FBF },
         { .reg = 0x00009888, .val = 0x0AA90821 },
         { .reg = 0x00009888, .val = 0x0CA90BAF },
         { .reg = 0x00009888, .val = 0x0EA90411 },
         { .reg = 0x00009888, .val = 0x10A9079F },
         { .reg = 0x00009888, .val = 0x12A90001 },
         { .reg = 0x00009888, .val = 0x14A9038F },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext921__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext921__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext921__avg_gpu_core_frequency__max,acmgt3__ext921__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_uint64(query, 2532, 24, NULL,acmgt3__ext921__slm_bank_conflict_count_xecore9__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext922_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext922";
   query->symbol_name = "Ext922";
   query->guid = "044b808a-b7f2-4e2c-bcf9-34c161b9def4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18C914C0 },
         { .reg = 0x00009888, .val = 0x1EC900A6 },
         { .reg = 0x00009888, .val = 0x22C91800 },
         { .reg = 0x00009888, .val = 0x24C90005 },
         { .reg = 0x00009888, .val = 0x28C914C0 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C90C31 },
         { .reg = 0x00009888, .val = 0x08C90FBF },
         { .reg = 0x00009888, .val = 0x0AC90821 },
         { .reg = 0x00009888, .val = 0x0CC90BAF },
         { .reg = 0x00009888, .val = 0x0EC90411 },
         { .reg = 0x00009888, .val = 0x10C9079F },
         { .reg = 0x00009888, .val = 0x12C90001 },
         { .reg = 0x00009888, .val = 0x14C9038F },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext922__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext922__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext922__avg_gpu_core_frequency__max,acmgt3__ext922__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_uint64(query, 2533, 24, NULL,acmgt3__ext922__slm_bank_conflict_count_xecore10__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext923_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext923";
   query->symbol_name = "Ext923";
   query->guid = "7a09a646-9e0f-495d-b768-fd55dd0ccc75";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext923__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext923__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext923__avg_gpu_core_frequency__max,acmgt3__ext923__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_uint64(query, 2534, 24, NULL,acmgt3__ext923__slm_bank_conflict_count_xecore11__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext924_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext924";
   query->symbol_name = "Ext924";
   query->guid = "5339dcea-309f-4df0-8858-c9e668536425";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext924__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext924__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext924__avg_gpu_core_frequency__max,acmgt3__ext924__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_uint64(query, 2535, 24, NULL,acmgt3__ext924__slm_bank_conflict_count_xecore12__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext925_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext925";
   query->symbol_name = "Ext925";
   query->guid = "9b59db08-b7d6-4544-a8e5-486158a6377d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19A914C0 },
         { .reg = 0x00009888, .val = 0x1FA900A6 },
         { .reg = 0x00009888, .val = 0x23A91800 },
         { .reg = 0x00009888, .val = 0x25A90005 },
         { .reg = 0x00009888, .val = 0x29A914C0 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A90C31 },
         { .reg = 0x00009888, .val = 0x09A90FBF },
         { .reg = 0x00009888, .val = 0x0BA90821 },
         { .reg = 0x00009888, .val = 0x0DA90BAF },
         { .reg = 0x00009888, .val = 0x0FA90411 },
         { .reg = 0x00009888, .val = 0x11A9079F },
         { .reg = 0x00009888, .val = 0x13A90001 },
         { .reg = 0x00009888, .val = 0x15A9038F },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext925__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext925__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext925__avg_gpu_core_frequency__max,acmgt3__ext925__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_uint64(query, 2536, 24, NULL,acmgt3__ext925__slm_bank_conflict_count_xecore13__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext926_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext926";
   query->symbol_name = "Ext926";
   query->guid = "5f31c335-12b6-4e4f-abc3-cdc650168def";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19C914C0 },
         { .reg = 0x00009888, .val = 0x1FC900A6 },
         { .reg = 0x00009888, .val = 0x23C91800 },
         { .reg = 0x00009888, .val = 0x25C90005 },
         { .reg = 0x00009888, .val = 0x29C914C0 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C90C31 },
         { .reg = 0x00009888, .val = 0x09C90FBF },
         { .reg = 0x00009888, .val = 0x0BC90821 },
         { .reg = 0x00009888, .val = 0x0DC90BAF },
         { .reg = 0x00009888, .val = 0x0FC90411 },
         { .reg = 0x00009888, .val = 0x11C9079F },
         { .reg = 0x00009888, .val = 0x13C90001 },
         { .reg = 0x00009888, .val = 0x15C9038F },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext926__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext926__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext926__avg_gpu_core_frequency__max,acmgt3__ext926__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_uint64(query, 2537, 24, NULL,acmgt3__ext926__slm_bank_conflict_count_xecore14__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext927_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext927";
   query->symbol_name = "Ext927";
   query->guid = "c413bffe-ef29-40b0-899a-d23dfb0718a2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext927__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext927__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext927__avg_gpu_core_frequency__max,acmgt3__ext927__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_uint64(query, 2538, 24, NULL,acmgt3__ext927__slm_bank_conflict_count_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext928_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext928";
   query->symbol_name = "Ext928";
   query->guid = "42ae6e37-0810-46c4-8d78-b76e28e7a7f8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext928__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext928__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext928__avg_gpu_core_frequency__max,acmgt3__ext928__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_uint64(query, 5605, 24, NULL,acmgt3__ext928__slm_bank_conflict_count_xecore16__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext929_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext929";
   query->symbol_name = "Ext929";
   query->guid = "cf938b48-3aa4-4b8a-ba01-ec993f0f4c92";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18A914C0 },
         { .reg = 0x00009888, .val = 0x1EA900A6 },
         { .reg = 0x00009888, .val = 0x22A91800 },
         { .reg = 0x00009888, .val = 0x24A90005 },
         { .reg = 0x00009888, .val = 0x28A914C0 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A90C31 },
         { .reg = 0x00009888, .val = 0x08A90FBF },
         { .reg = 0x00009888, .val = 0x0AA90821 },
         { .reg = 0x00009888, .val = 0x0CA90BAF },
         { .reg = 0x00009888, .val = 0x0EA90411 },
         { .reg = 0x00009888, .val = 0x10A9079F },
         { .reg = 0x00009888, .val = 0x12A90001 },
         { .reg = 0x00009888, .val = 0x14A9038F },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext929__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext929__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext929__avg_gpu_core_frequency__max,acmgt3__ext929__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_uint64(query, 5606, 24, NULL,acmgt3__ext929__slm_bank_conflict_count_xecore17__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext930_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext930";
   query->symbol_name = "Ext930";
   query->guid = "39e1edcd-5c27-4f20-b460-5b506bab2c5b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18C914C0 },
         { .reg = 0x00009888, .val = 0x1EC900A6 },
         { .reg = 0x00009888, .val = 0x22C91800 },
         { .reg = 0x00009888, .val = 0x24C90005 },
         { .reg = 0x00009888, .val = 0x28C914C0 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C90C31 },
         { .reg = 0x00009888, .val = 0x08C90FBF },
         { .reg = 0x00009888, .val = 0x0AC90821 },
         { .reg = 0x00009888, .val = 0x0CC90BAF },
         { .reg = 0x00009888, .val = 0x0EC90411 },
         { .reg = 0x00009888, .val = 0x10C9079F },
         { .reg = 0x00009888, .val = 0x12C90001 },
         { .reg = 0x00009888, .val = 0x14C9038F },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext930__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext930__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext930__avg_gpu_core_frequency__max,acmgt3__ext930__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_uint64(query, 5607, 24, NULL,acmgt3__ext930__slm_bank_conflict_count_xecore18__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext931_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext931";
   query->symbol_name = "Ext931";
   query->guid = "1e3ee19b-dfbc-483a-b1b6-8df99fa18f9a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext931__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext931__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext931__avg_gpu_core_frequency__max,acmgt3__ext931__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_uint64(query, 5608, 24, NULL,acmgt3__ext931__slm_bank_conflict_count_xecore19__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext932_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext932";
   query->symbol_name = "Ext932";
   query->guid = "8c63d2ab-71c0-4b22-b9d7-1b74ed86b77f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext932__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext932__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext932__avg_gpu_core_frequency__max,acmgt3__ext932__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_uint64(query, 5609, 24, NULL,acmgt3__ext932__slm_bank_conflict_count_xecore20__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext933_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext933";
   query->symbol_name = "Ext933";
   query->guid = "32abbaf3-3fa0-4bf2-b455-21bc065a470a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19A914C0 },
         { .reg = 0x00009888, .val = 0x1FA900A6 },
         { .reg = 0x00009888, .val = 0x23A91800 },
         { .reg = 0x00009888, .val = 0x25A90005 },
         { .reg = 0x00009888, .val = 0x29A914C0 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A90C31 },
         { .reg = 0x00009888, .val = 0x09A90FBF },
         { .reg = 0x00009888, .val = 0x0BA90821 },
         { .reg = 0x00009888, .val = 0x0DA90BAF },
         { .reg = 0x00009888, .val = 0x0FA90411 },
         { .reg = 0x00009888, .val = 0x11A9079F },
         { .reg = 0x00009888, .val = 0x13A90001 },
         { .reg = 0x00009888, .val = 0x15A9038F },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext933__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext933__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext933__avg_gpu_core_frequency__max,acmgt3__ext933__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_uint64(query, 5610, 24, NULL,acmgt3__ext933__slm_bank_conflict_count_xecore21__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext934_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext934";
   query->symbol_name = "Ext934";
   query->guid = "36ec10c5-30d6-4ed5-80fc-7fca5bfc8db2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19C914C0 },
         { .reg = 0x00009888, .val = 0x1FC900A6 },
         { .reg = 0x00009888, .val = 0x23C91800 },
         { .reg = 0x00009888, .val = 0x25C90005 },
         { .reg = 0x00009888, .val = 0x29C914C0 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C90C31 },
         { .reg = 0x00009888, .val = 0x09C90FBF },
         { .reg = 0x00009888, .val = 0x0BC90821 },
         { .reg = 0x00009888, .val = 0x0DC90BAF },
         { .reg = 0x00009888, .val = 0x0FC90411 },
         { .reg = 0x00009888, .val = 0x11C9079F },
         { .reg = 0x00009888, .val = 0x13C90001 },
         { .reg = 0x00009888, .val = 0x15C9038F },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext934__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext934__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext934__avg_gpu_core_frequency__max,acmgt3__ext934__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_uint64(query, 5611, 24, NULL,acmgt3__ext934__slm_bank_conflict_count_xecore22__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext935_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext935";
   query->symbol_name = "Ext935";
   query->guid = "93f4ca26-8eb8-45af-acc7-ade95a86bf4e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext935__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext935__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext935__avg_gpu_core_frequency__max,acmgt3__ext935__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_uint64(query, 5612, 24, NULL,acmgt3__ext935__slm_bank_conflict_count_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext936_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext936";
   query->symbol_name = "Ext936";
   query->guid = "6411422a-9ae7-4d23-83b4-27a0f571daea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x188914C0 },
         { .reg = 0x00009888, .val = 0x1E8900A6 },
         { .reg = 0x00009888, .val = 0x22891800 },
         { .reg = 0x00009888, .val = 0x24890005 },
         { .reg = 0x00009888, .val = 0x288914C0 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAAA },
         { .reg = 0x00009888, .val = 0x0084FFFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865555 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAAA },
         { .reg = 0x00009888, .val = 0x02893254 },
         { .reg = 0x00009888, .val = 0x04890208 },
         { .reg = 0x00009888, .val = 0x06890C31 },
         { .reg = 0x00009888, .val = 0x08890FBF },
         { .reg = 0x00009888, .val = 0x0A890821 },
         { .reg = 0x00009888, .val = 0x0C890BAF },
         { .reg = 0x00009888, .val = 0x0E890411 },
         { .reg = 0x00009888, .val = 0x1089079F },
         { .reg = 0x00009888, .val = 0x12890001 },
         { .reg = 0x00009888, .val = 0x1489038F },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext936__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext936__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext936__avg_gpu_core_frequency__max,acmgt3__ext936__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_uint64(query, 5613, 24, NULL,acmgt3__ext936__slm_bank_conflict_count_xecore24__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext937_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext937";
   query->symbol_name = "Ext937";
   query->guid = "2a21eaf2-0ff9-4d72-a54b-d47b31a09202";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18A914C0 },
         { .reg = 0x00009888, .val = 0x1EA900A6 },
         { .reg = 0x00009888, .val = 0x22A91800 },
         { .reg = 0x00009888, .val = 0x24A90005 },
         { .reg = 0x00009888, .val = 0x28A914C0 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAAA },
         { .reg = 0x00009888, .val = 0x00A4FFFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65555 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAAA },
         { .reg = 0x00009888, .val = 0x02A93254 },
         { .reg = 0x00009888, .val = 0x04A90208 },
         { .reg = 0x00009888, .val = 0x06A90C31 },
         { .reg = 0x00009888, .val = 0x08A90FBF },
         { .reg = 0x00009888, .val = 0x0AA90821 },
         { .reg = 0x00009888, .val = 0x0CA90BAF },
         { .reg = 0x00009888, .val = 0x0EA90411 },
         { .reg = 0x00009888, .val = 0x10A9079F },
         { .reg = 0x00009888, .val = 0x12A90001 },
         { .reg = 0x00009888, .val = 0x14A9038F },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext937__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext937__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext937__avg_gpu_core_frequency__max,acmgt3__ext937__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_uint64(query, 5614, 24, NULL,acmgt3__ext937__slm_bank_conflict_count_xecore25__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext938_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext938";
   query->symbol_name = "Ext938";
   query->guid = "13073d0f-fa11-4814-9bcd-139958585128";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18C914C0 },
         { .reg = 0x00009888, .val = 0x1EC900A6 },
         { .reg = 0x00009888, .val = 0x22C91800 },
         { .reg = 0x00009888, .val = 0x24C90005 },
         { .reg = 0x00009888, .val = 0x28C914C0 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAAA },
         { .reg = 0x00009888, .val = 0x00C4FFFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65555 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAAA },
         { .reg = 0x00009888, .val = 0x02C93254 },
         { .reg = 0x00009888, .val = 0x04C90208 },
         { .reg = 0x00009888, .val = 0x06C90C31 },
         { .reg = 0x00009888, .val = 0x08C90FBF },
         { .reg = 0x00009888, .val = 0x0AC90821 },
         { .reg = 0x00009888, .val = 0x0CC90BAF },
         { .reg = 0x00009888, .val = 0x0EC90411 },
         { .reg = 0x00009888, .val = 0x10C9079F },
         { .reg = 0x00009888, .val = 0x12C90001 },
         { .reg = 0x00009888, .val = 0x14C9038F },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext938__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext938__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext938__avg_gpu_core_frequency__max,acmgt3__ext938__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_uint64(query, 5615, 24, NULL,acmgt3__ext938__slm_bank_conflict_count_xecore26__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext939_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext939";
   query->symbol_name = "Ext939";
   query->guid = "43a8b6e0-50ff-486e-812b-42a4d00ec5f7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x18E914C0 },
         { .reg = 0x00009888, .val = 0x1EE900A6 },
         { .reg = 0x00009888, .val = 0x22E91800 },
         { .reg = 0x00009888, .val = 0x24E90005 },
         { .reg = 0x00009888, .val = 0x28E914C0 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAAA },
         { .reg = 0x00009888, .val = 0x00E4FFFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65555 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAAA },
         { .reg = 0x00009888, .val = 0x02E93254 },
         { .reg = 0x00009888, .val = 0x04E90208 },
         { .reg = 0x00009888, .val = 0x06E90C31 },
         { .reg = 0x00009888, .val = 0x08E90FBF },
         { .reg = 0x00009888, .val = 0x0AE90821 },
         { .reg = 0x00009888, .val = 0x0CE90BAF },
         { .reg = 0x00009888, .val = 0x0EE90411 },
         { .reg = 0x00009888, .val = 0x10E9079F },
         { .reg = 0x00009888, .val = 0x12E90001 },
         { .reg = 0x00009888, .val = 0x14E9038F },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext939__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext939__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext939__avg_gpu_core_frequency__max,acmgt3__ext939__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_uint64(query, 5616, 24, NULL,acmgt3__ext939__slm_bank_conflict_count_xecore27__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext940_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext940";
   query->symbol_name = "Ext940";
   query->guid = "61e98434-0a16-40c8-9b7d-371652eb33cd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x198914C0 },
         { .reg = 0x00009888, .val = 0x1F8900A6 },
         { .reg = 0x00009888, .val = 0x23891800 },
         { .reg = 0x00009888, .val = 0x25890005 },
         { .reg = 0x00009888, .val = 0x298914C0 },
         { .reg = 0x00009888, .val = 0x0183AAAA },
         { .reg = 0x00009888, .val = 0x0383AAAA },
         { .reg = 0x00009888, .val = 0x0184FFFF },
         { .reg = 0x00009888, .val = 0x01865555 },
         { .reg = 0x00009888, .val = 0x03865555 },
         { .reg = 0x00009888, .val = 0x0187AAAA },
         { .reg = 0x00009888, .val = 0x0387AAAA },
         { .reg = 0x00009888, .val = 0x03893254 },
         { .reg = 0x00009888, .val = 0x05890208 },
         { .reg = 0x00009888, .val = 0x07890C31 },
         { .reg = 0x00009888, .val = 0x09890FBF },
         { .reg = 0x00009888, .val = 0x0B890821 },
         { .reg = 0x00009888, .val = 0x0D890BAF },
         { .reg = 0x00009888, .val = 0x0F890411 },
         { .reg = 0x00009888, .val = 0x1189079F },
         { .reg = 0x00009888, .val = 0x13890001 },
         { .reg = 0x00009888, .val = 0x1589038F },
         { .reg = 0x00009888, .val = 0x01890000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108AAAA },
         { .reg = 0x00009888, .val = 0x0308AAAA },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext940__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext940__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext940__avg_gpu_core_frequency__max,acmgt3__ext940__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_uint64(query, 5617, 24, NULL,acmgt3__ext940__slm_bank_conflict_count_xecore28__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext941_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext941";
   query->symbol_name = "Ext941";
   query->guid = "1c13d9d5-c6f4-47a1-b695-8273b93037fe";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x19A914C0 },
         { .reg = 0x00009888, .val = 0x1FA900A6 },
         { .reg = 0x00009888, .val = 0x23A91800 },
         { .reg = 0x00009888, .val = 0x25A90005 },
         { .reg = 0x00009888, .val = 0x29A914C0 },
         { .reg = 0x00009888, .val = 0x01A3AAAA },
         { .reg = 0x00009888, .val = 0x03A3AAAA },
         { .reg = 0x00009888, .val = 0x01A4FFFF },
         { .reg = 0x00009888, .val = 0x01A65555 },
         { .reg = 0x00009888, .val = 0x03A65555 },
         { .reg = 0x00009888, .val = 0x01A7AAAA },
         { .reg = 0x00009888, .val = 0x03A7AAAA },
         { .reg = 0x00009888, .val = 0x03A93254 },
         { .reg = 0x00009888, .val = 0x05A90208 },
         { .reg = 0x00009888, .val = 0x07A90C31 },
         { .reg = 0x00009888, .val = 0x09A90FBF },
         { .reg = 0x00009888, .val = 0x0BA90821 },
         { .reg = 0x00009888, .val = 0x0DA90BAF },
         { .reg = 0x00009888, .val = 0x0FA90411 },
         { .reg = 0x00009888, .val = 0x11A9079F },
         { .reg = 0x00009888, .val = 0x13A90001 },
         { .reg = 0x00009888, .val = 0x15A9038F },
         { .reg = 0x00009888, .val = 0x01A90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0108FFFF },
         { .reg = 0x00009888, .val = 0x0308FFFF },
         { .reg = 0x00009888, .val = 0x010A5555 },
         { .reg = 0x00009888, .val = 0x030A5555 },
         { .reg = 0x00009888, .val = 0x0101FFFF },
         { .reg = 0x00009888, .val = 0x010B5555 },
         { .reg = 0x00009888, .val = 0x030B5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext941__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext941__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext941__avg_gpu_core_frequency__max,acmgt3__ext941__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_uint64(query, 5618, 24, NULL,acmgt3__ext941__slm_bank_conflict_count_xecore29__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext942_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext942";
   query->symbol_name = "Ext942";
   query->guid = "9efa16a4-a3ae-4be2-a616-7b6164ed850b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x19C914C0 },
         { .reg = 0x00009888, .val = 0x1FC900A6 },
         { .reg = 0x00009888, .val = 0x23C91800 },
         { .reg = 0x00009888, .val = 0x25C90005 },
         { .reg = 0x00009888, .val = 0x29C914C0 },
         { .reg = 0x00009888, .val = 0x01C3AAAA },
         { .reg = 0x00009888, .val = 0x03C3AAAA },
         { .reg = 0x00009888, .val = 0x01C4FFFF },
         { .reg = 0x00009888, .val = 0x01C65555 },
         { .reg = 0x00009888, .val = 0x03C65555 },
         { .reg = 0x00009888, .val = 0x01C7AAAA },
         { .reg = 0x00009888, .val = 0x03C7AAAA },
         { .reg = 0x00009888, .val = 0x03C93254 },
         { .reg = 0x00009888, .val = 0x05C90208 },
         { .reg = 0x00009888, .val = 0x07C90C31 },
         { .reg = 0x00009888, .val = 0x09C90FBF },
         { .reg = 0x00009888, .val = 0x0BC90821 },
         { .reg = 0x00009888, .val = 0x0DC90BAF },
         { .reg = 0x00009888, .val = 0x0FC90411 },
         { .reg = 0x00009888, .val = 0x11C9079F },
         { .reg = 0x00009888, .val = 0x13C90001 },
         { .reg = 0x00009888, .val = 0x15C9038F },
         { .reg = 0x00009888, .val = 0x01C90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x0107AAAA },
         { .reg = 0x00009888, .val = 0x0307AAAA },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009888, .val = 0x0102FFFF },
         { .reg = 0x00009888, .val = 0x010C5555 },
         { .reg = 0x00009888, .val = 0x030C5555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext942__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext942__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext942__avg_gpu_core_frequency__max,acmgt3__ext942__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_uint64(query, 5619, 24, NULL,acmgt3__ext942__slm_bank_conflict_count_xecore30__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext943_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext943";
   query->symbol_name = "Ext943";
   query->guid = "e0e775d6-908a-4410-8ed1-a26b1d316700";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x19E914C0 },
         { .reg = 0x00009888, .val = 0x1FE900A6 },
         { .reg = 0x00009888, .val = 0x23E91800 },
         { .reg = 0x00009888, .val = 0x25E90005 },
         { .reg = 0x00009888, .val = 0x29E914C0 },
         { .reg = 0x00009888, .val = 0x01E3AAAA },
         { .reg = 0x00009888, .val = 0x03E3AAAA },
         { .reg = 0x00009888, .val = 0x01E4FFFF },
         { .reg = 0x00009888, .val = 0x01E65555 },
         { .reg = 0x00009888, .val = 0x03E65555 },
         { .reg = 0x00009888, .val = 0x01E7AAAA },
         { .reg = 0x00009888, .val = 0x03E7AAAA },
         { .reg = 0x00009888, .val = 0x03E93254 },
         { .reg = 0x00009888, .val = 0x05E90208 },
         { .reg = 0x00009888, .val = 0x07E90C31 },
         { .reg = 0x00009888, .val = 0x09E90FBF },
         { .reg = 0x00009888, .val = 0x0BE90821 },
         { .reg = 0x00009888, .val = 0x0DE90BAF },
         { .reg = 0x00009888, .val = 0x0FE90411 },
         { .reg = 0x00009888, .val = 0x11E9079F },
         { .reg = 0x00009888, .val = 0x13E90001 },
         { .reg = 0x00009888, .val = 0x15E9038F },
         { .reg = 0x00009888, .val = 0x01E90000 },
         { .reg = 0x00009888, .val = 0x0003FFFF },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000BAAAA },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x01075555 },
         { .reg = 0x00009888, .val = 0x03075555 },
         { .reg = 0x00009888, .val = 0x0109FFFF },
         { .reg = 0x00009888, .val = 0x010AAAAA },
         { .reg = 0x00009888, .val = 0x030AAAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext943__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext943__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext943__avg_gpu_core_frequency__max,acmgt3__ext943__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_uint64(query, 5620, 24, NULL,acmgt3__ext943__slm_bank_conflict_count_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext944_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext944";
   query->symbol_name = "Ext944";
   query->guid = "5e825890-c584-4545-bf82-6a8ded48393c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16870253 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870004 },
         { .reg = 0x00009888, .val = 0x0E870140 },
         { .reg = 0x00009888, .val = 0x108700C4 },
         { .reg = 0x00009888, .val = 0x12870042 },
         { .reg = 0x00009888, .val = 0x148703C0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890387 },
         { .reg = 0x00009888, .val = 0x08890248 },
         { .reg = 0x00009888, .val = 0x0A8902CA },
         { .reg = 0x00009888, .val = 0x0C89034C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext944__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext944__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext944__avg_gpu_core_frequency__max,acmgt3__ext944__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1858, 24, NULL,acmgt3__ext944__slm_byte_read_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1859, 32, NULL,acmgt3__ext944__load_store_cache_byte_read_bank0_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext945_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext945";
   query->symbol_name = "Ext945";
   query->guid = "07f8b9c7-a909-4ea1-ab0e-d1a1b72fba23";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16A70253 },
         { .reg = 0x00009888, .val = 0x18A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A70004 },
         { .reg = 0x00009888, .val = 0x0EA70140 },
         { .reg = 0x00009888, .val = 0x10A700C4 },
         { .reg = 0x00009888, .val = 0x12A70042 },
         { .reg = 0x00009888, .val = 0x14A703C0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A90054 },
         { .reg = 0x00009888, .val = 0x06A90387 },
         { .reg = 0x00009888, .val = 0x08A90248 },
         { .reg = 0x00009888, .val = 0x0AA902CA },
         { .reg = 0x00009888, .val = 0x0CA9034C },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext945__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext945__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext945__avg_gpu_core_frequency__max,acmgt3__ext945__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1860, 24, NULL,acmgt3__ext945__slm_byte_read_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1861, 32, NULL,acmgt3__ext945__load_store_cache_byte_read_bank0_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext946_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext946";
   query->symbol_name = "Ext946";
   query->guid = "01c4a3bf-e61c-459a-8eed-c736edf29117";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16C70253 },
         { .reg = 0x00009888, .val = 0x18C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C70004 },
         { .reg = 0x00009888, .val = 0x0EC70140 },
         { .reg = 0x00009888, .val = 0x10C700C4 },
         { .reg = 0x00009888, .val = 0x12C70042 },
         { .reg = 0x00009888, .val = 0x14C703C0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C90054 },
         { .reg = 0x00009888, .val = 0x06C90387 },
         { .reg = 0x00009888, .val = 0x08C90248 },
         { .reg = 0x00009888, .val = 0x0AC902CA },
         { .reg = 0x00009888, .val = 0x0CC9034C },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext946__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext946__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext946__avg_gpu_core_frequency__max,acmgt3__ext946__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1862, 24, NULL,acmgt3__ext946__slm_byte_read_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1863, 32, NULL,acmgt3__ext946__load_store_cache_byte_read_bank0_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext947_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext947";
   query->symbol_name = "Ext947";
   query->guid = "37906cb5-0da3-49d3-875e-d11e3584e4dd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16E70253 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70004 },
         { .reg = 0x00009888, .val = 0x0EE70140 },
         { .reg = 0x00009888, .val = 0x10E700C4 },
         { .reg = 0x00009888, .val = 0x12E70042 },
         { .reg = 0x00009888, .val = 0x14E703C0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90387 },
         { .reg = 0x00009888, .val = 0x08E90248 },
         { .reg = 0x00009888, .val = 0x0AE902CA },
         { .reg = 0x00009888, .val = 0x0CE9034C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext947__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext947__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext947__avg_gpu_core_frequency__max,acmgt3__ext947__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1864, 24, NULL,acmgt3__ext947__slm_byte_read_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1865, 32, NULL,acmgt3__ext947__load_store_cache_byte_read_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext948_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext948";
   query->symbol_name = "Ext948";
   query->guid = "12e4baf7-6d8d-46c0-acd7-5f94223dddc8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A870253 },
         { .reg = 0x00009888, .val = 0x1E890083 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x048700E0 },
         { .reg = 0x00009888, .val = 0x0E870540 },
         { .reg = 0x00009888, .val = 0x108704D4 },
         { .reg = 0x00009888, .val = 0x12870452 },
         { .reg = 0x00009888, .val = 0x148707D0 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02893200 },
         { .reg = 0x00009888, .val = 0x06890797 },
         { .reg = 0x00009888, .val = 0x08890658 },
         { .reg = 0x00009888, .val = 0x0A8906DA },
         { .reg = 0x00009888, .val = 0x0C89075C },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext948__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext948__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext948__avg_gpu_core_frequency__max,acmgt3__ext948__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1874, 24, NULL,acmgt3__ext948__slm_byte_read_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1875, 32, NULL,acmgt3__ext948__load_store_cache_byte_read_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext949_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext949";
   query->symbol_name = "Ext949";
   query->guid = "b616fbb5-c0d3-4e63-bcff-61bcf8ba8ff9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AA70253 },
         { .reg = 0x00009888, .val = 0x1EA90083 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A700E0 },
         { .reg = 0x00009888, .val = 0x0EA70540 },
         { .reg = 0x00009888, .val = 0x10A704D4 },
         { .reg = 0x00009888, .val = 0x12A70452 },
         { .reg = 0x00009888, .val = 0x14A707D0 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A93200 },
         { .reg = 0x00009888, .val = 0x06A90797 },
         { .reg = 0x00009888, .val = 0x08A90658 },
         { .reg = 0x00009888, .val = 0x0AA906DA },
         { .reg = 0x00009888, .val = 0x0CA9075C },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext949__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext949__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext949__avg_gpu_core_frequency__max,acmgt3__ext949__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1876, 24, NULL,acmgt3__ext949__slm_byte_read_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1877, 32, NULL,acmgt3__ext949__load_store_cache_byte_read_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext950_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext950";
   query->symbol_name = "Ext950";
   query->guid = "5e7edb7d-ba9b-4574-9bac-abd4742e186e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC70253 },
         { .reg = 0x00009888, .val = 0x1EC90083 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C700E0 },
         { .reg = 0x00009888, .val = 0x0EC70540 },
         { .reg = 0x00009888, .val = 0x10C704D4 },
         { .reg = 0x00009888, .val = 0x12C70452 },
         { .reg = 0x00009888, .val = 0x14C707D0 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C93200 },
         { .reg = 0x00009888, .val = 0x06C90797 },
         { .reg = 0x00009888, .val = 0x08C90658 },
         { .reg = 0x00009888, .val = 0x0AC906DA },
         { .reg = 0x00009888, .val = 0x0CC9075C },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext950__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext950__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext950__avg_gpu_core_frequency__max,acmgt3__ext950__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1878, 24, NULL,acmgt3__ext950__slm_byte_read_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1879, 32, NULL,acmgt3__ext950__load_store_cache_byte_read_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext951_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext951";
   query->symbol_name = "Ext951";
   query->guid = "24ad6a9c-cb37-4e16-b25b-3cc444e081a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AE70253 },
         { .reg = 0x00009888, .val = 0x1EE90083 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E700E0 },
         { .reg = 0x00009888, .val = 0x0EE70540 },
         { .reg = 0x00009888, .val = 0x10E704D4 },
         { .reg = 0x00009888, .val = 0x12E70452 },
         { .reg = 0x00009888, .val = 0x14E707D0 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E93200 },
         { .reg = 0x00009888, .val = 0x06E90797 },
         { .reg = 0x00009888, .val = 0x08E90658 },
         { .reg = 0x00009888, .val = 0x0AE906DA },
         { .reg = 0x00009888, .val = 0x0CE9075C },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext951__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext951__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext951__avg_gpu_core_frequency__max,acmgt3__ext951__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1880, 24, NULL,acmgt3__ext951__slm_byte_read_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1881, 32, NULL,acmgt3__ext951__load_store_cache_byte_read_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext952_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext952";
   query->symbol_name = "Ext952";
   query->guid = "526b1c1e-b636-4231-9d4c-6e6987c4b24b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12880253 },
         { .reg = 0x00009888, .val = 0x22890C00 },
         { .reg = 0x00009888, .val = 0x24890004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x00880004 },
         { .reg = 0x00009888, .val = 0x0A880140 },
         { .reg = 0x00009888, .val = 0x0C8800C4 },
         { .reg = 0x00009888, .val = 0x0E880042 },
         { .reg = 0x00009888, .val = 0x108803C0 },
         { .reg = 0x00009888, .val = 0x04890008 },
         { .reg = 0x00009888, .val = 0x06890BA7 },
         { .reg = 0x00009888, .val = 0x08890A68 },
         { .reg = 0x00009888, .val = 0x0A890AEA },
         { .reg = 0x00009888, .val = 0x0C890B6C },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext952__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext952__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext952__avg_gpu_core_frequency__max,acmgt3__ext952__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1890, 24, NULL,acmgt3__ext952__slm_byte_read_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1891, 32, NULL,acmgt3__ext952__load_store_cache_byte_read_bank2_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext953_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext953";
   query->symbol_name = "Ext953";
   query->guid = "da7fb135-174a-41fb-a6fd-0bdc44732d9e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12A80253 },
         { .reg = 0x00009888, .val = 0x22A90C00 },
         { .reg = 0x00009888, .val = 0x24A90004 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A80004 },
         { .reg = 0x00009888, .val = 0x0AA80140 },
         { .reg = 0x00009888, .val = 0x0CA800C4 },
         { .reg = 0x00009888, .val = 0x0EA80042 },
         { .reg = 0x00009888, .val = 0x10A803C0 },
         { .reg = 0x00009888, .val = 0x04A90008 },
         { .reg = 0x00009888, .val = 0x06A90BA7 },
         { .reg = 0x00009888, .val = 0x08A90A68 },
         { .reg = 0x00009888, .val = 0x0AA90AEA },
         { .reg = 0x00009888, .val = 0x0CA90B6C },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext953__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext953__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext953__avg_gpu_core_frequency__max,acmgt3__ext953__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1892, 24, NULL,acmgt3__ext953__slm_byte_read_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1893, 32, NULL,acmgt3__ext953__load_store_cache_byte_read_bank2_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext954_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext954";
   query->symbol_name = "Ext954";
   query->guid = "7499a841-6a6a-45ce-9c27-9bf6080ea900";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12C80253 },
         { .reg = 0x00009888, .val = 0x22C90C00 },
         { .reg = 0x00009888, .val = 0x24C90004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C80004 },
         { .reg = 0x00009888, .val = 0x0AC80140 },
         { .reg = 0x00009888, .val = 0x0CC800C4 },
         { .reg = 0x00009888, .val = 0x0EC80042 },
         { .reg = 0x00009888, .val = 0x10C803C0 },
         { .reg = 0x00009888, .val = 0x04C90008 },
         { .reg = 0x00009888, .val = 0x06C90BA7 },
         { .reg = 0x00009888, .val = 0x08C90A68 },
         { .reg = 0x00009888, .val = 0x0AC90AEA },
         { .reg = 0x00009888, .val = 0x0CC90B6C },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext954__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext954__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext954__avg_gpu_core_frequency__max,acmgt3__ext954__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1894, 24, NULL,acmgt3__ext954__slm_byte_read_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1895, 32, NULL,acmgt3__ext954__load_store_cache_byte_read_bank2_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext955_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext955";
   query->symbol_name = "Ext955";
   query->guid = "4b6cce94-cbf0-4b56-9b24-6c2ebd167755";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12E80253 },
         { .reg = 0x00009888, .val = 0x22E90C00 },
         { .reg = 0x00009888, .val = 0x24E90004 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E80004 },
         { .reg = 0x00009888, .val = 0x0AE80140 },
         { .reg = 0x00009888, .val = 0x0CE800C4 },
         { .reg = 0x00009888, .val = 0x0EE80042 },
         { .reg = 0x00009888, .val = 0x10E803C0 },
         { .reg = 0x00009888, .val = 0x04E90008 },
         { .reg = 0x00009888, .val = 0x06E90BA7 },
         { .reg = 0x00009888, .val = 0x08E90A68 },
         { .reg = 0x00009888, .val = 0x0AE90AEA },
         { .reg = 0x00009888, .val = 0x0CE90B6C },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext955__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext955__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext955__avg_gpu_core_frequency__max,acmgt3__ext955__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1896, 24, NULL,acmgt3__ext955__slm_byte_read_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1897, 32, NULL,acmgt3__ext955__load_store_cache_byte_read_bank2_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext956_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext956";
   query->symbol_name = "Ext956";
   query->guid = "c648eaa7-cac1-4c84-a2ea-c3448f108ab2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16880253 },
         { .reg = 0x00009888, .val = 0x28891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x008800E0 },
         { .reg = 0x00009888, .val = 0x0A880540 },
         { .reg = 0x00009888, .val = 0x0C8804D4 },
         { .reg = 0x00009888, .val = 0x0E880452 },
         { .reg = 0x00009888, .val = 0x108807D0 },
         { .reg = 0x00009888, .val = 0x04890200 },
         { .reg = 0x00009888, .val = 0x06890FB7 },
         { .reg = 0x00009888, .val = 0x08890E78 },
         { .reg = 0x00009888, .val = 0x0A890EFA },
         { .reg = 0x00009888, .val = 0x0C890F7C },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext956__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext956__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext956__avg_gpu_core_frequency__max,acmgt3__ext956__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1906, 24, NULL,acmgt3__ext956__slm_byte_read_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1907, 32, NULL,acmgt3__ext956__load_store_cache_byte_read_bank3_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext957_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext957";
   query->symbol_name = "Ext957";
   query->guid = "37b143ab-aba8-4537-a735-14cccb02f079";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16A80253 },
         { .reg = 0x00009888, .val = 0x28A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A800E0 },
         { .reg = 0x00009888, .val = 0x0AA80540 },
         { .reg = 0x00009888, .val = 0x0CA804D4 },
         { .reg = 0x00009888, .val = 0x0EA80452 },
         { .reg = 0x00009888, .val = 0x10A807D0 },
         { .reg = 0x00009888, .val = 0x04A90200 },
         { .reg = 0x00009888, .val = 0x06A90FB7 },
         { .reg = 0x00009888, .val = 0x08A90E78 },
         { .reg = 0x00009888, .val = 0x0AA90EFA },
         { .reg = 0x00009888, .val = 0x0CA90F7C },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext957__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext957__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext957__avg_gpu_core_frequency__max,acmgt3__ext957__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1908, 24, NULL,acmgt3__ext957__slm_byte_read_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1909, 32, NULL,acmgt3__ext957__load_store_cache_byte_read_bank3_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext958_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext958";
   query->symbol_name = "Ext958";
   query->guid = "98d49ba7-236c-410e-958a-3f08c09b74c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16C80253 },
         { .reg = 0x00009888, .val = 0x28C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C800E0 },
         { .reg = 0x00009888, .val = 0x0AC80540 },
         { .reg = 0x00009888, .val = 0x0CC804D4 },
         { .reg = 0x00009888, .val = 0x0EC80452 },
         { .reg = 0x00009888, .val = 0x10C807D0 },
         { .reg = 0x00009888, .val = 0x04C90200 },
         { .reg = 0x00009888, .val = 0x06C90FB7 },
         { .reg = 0x00009888, .val = 0x08C90E78 },
         { .reg = 0x00009888, .val = 0x0AC90EFA },
         { .reg = 0x00009888, .val = 0x0CC90F7C },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext958__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext958__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext958__avg_gpu_core_frequency__max,acmgt3__ext958__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1910, 24, NULL,acmgt3__ext958__slm_byte_read_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1911, 32, NULL,acmgt3__ext958__load_store_cache_byte_read_bank3_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext959_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext959";
   query->symbol_name = "Ext959";
   query->guid = "5d40ca14-33f7-4fc8-a9cd-7cd5d3aa58b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16E80253 },
         { .reg = 0x00009888, .val = 0x28E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E800E0 },
         { .reg = 0x00009888, .val = 0x0AE80540 },
         { .reg = 0x00009888, .val = 0x0CE804D4 },
         { .reg = 0x00009888, .val = 0x0EE80452 },
         { .reg = 0x00009888, .val = 0x10E807D0 },
         { .reg = 0x00009888, .val = 0x04E90200 },
         { .reg = 0x00009888, .val = 0x06E90FB7 },
         { .reg = 0x00009888, .val = 0x08E90E78 },
         { .reg = 0x00009888, .val = 0x0AE90EFA },
         { .reg = 0x00009888, .val = 0x0CE90F7C },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext959__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext959__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext959__avg_gpu_core_frequency__max,acmgt3__ext959__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1912, 24, NULL,acmgt3__ext959__slm_byte_read_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1913, 32, NULL,acmgt3__ext959__load_store_cache_byte_read_bank3_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext960_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext960";
   query->symbol_name = "Ext960";
   query->guid = "04f3962b-a11a-4aa4-a263-d545823df4af";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16870012 },
         { .reg = 0x00009888, .val = 0x18891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x0E870180 },
         { .reg = 0x00009888, .val = 0x10870105 },
         { .reg = 0x00009888, .val = 0x12870083 },
         { .reg = 0x00009888, .val = 0x14870001 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02890054 },
         { .reg = 0x00009888, .val = 0x06890380 },
         { .reg = 0x00009888, .val = 0x08890081 },
         { .reg = 0x00009888, .val = 0x0A890103 },
         { .reg = 0x00009888, .val = 0x0C890185 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext960__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext960__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext960__avg_gpu_core_frequency__max,acmgt3__ext960__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1922, 24, NULL,acmgt3__ext960__slm_byte_write_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1923, 32, NULL,acmgt3__ext960__load_store_cache_byte_write_bank0_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext961_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext961";
   query->symbol_name = "Ext961";
   query->guid = "b07a3402-0c0e-4ea8-af95-738c3445e5df";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16A70012 },
         { .reg = 0x00009888, .val = 0x18A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x0EA70180 },
         { .reg = 0x00009888, .val = 0x10A70105 },
         { .reg = 0x00009888, .val = 0x12A70083 },
         { .reg = 0x00009888, .val = 0x14A70001 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A90054 },
         { .reg = 0x00009888, .val = 0x06A90380 },
         { .reg = 0x00009888, .val = 0x08A90081 },
         { .reg = 0x00009888, .val = 0x0AA90103 },
         { .reg = 0x00009888, .val = 0x0CA90185 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext961__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext961__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext961__avg_gpu_core_frequency__max,acmgt3__ext961__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1924, 24, NULL,acmgt3__ext961__slm_byte_write_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1925, 32, NULL,acmgt3__ext961__load_store_cache_byte_write_bank0_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext962_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext962";
   query->symbol_name = "Ext962";
   query->guid = "fcab665c-5dda-47b6-9052-99f992805980";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16C70012 },
         { .reg = 0x00009888, .val = 0x18C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x0EC70180 },
         { .reg = 0x00009888, .val = 0x10C70105 },
         { .reg = 0x00009888, .val = 0x12C70083 },
         { .reg = 0x00009888, .val = 0x14C70001 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C90054 },
         { .reg = 0x00009888, .val = 0x06C90380 },
         { .reg = 0x00009888, .val = 0x08C90081 },
         { .reg = 0x00009888, .val = 0x0AC90103 },
         { .reg = 0x00009888, .val = 0x0CC90185 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext962__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext962__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext962__avg_gpu_core_frequency__max,acmgt3__ext962__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1926, 24, NULL,acmgt3__ext962__slm_byte_write_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1927, 32, NULL,acmgt3__ext962__load_store_cache_byte_write_bank0_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext963_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext963";
   query->symbol_name = "Ext963";
   query->guid = "88e912b5-3333-46e1-86e2-b7c5ebfff84a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16E70012 },
         { .reg = 0x00009888, .val = 0x18E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x0EE70180 },
         { .reg = 0x00009888, .val = 0x10E70105 },
         { .reg = 0x00009888, .val = 0x12E70083 },
         { .reg = 0x00009888, .val = 0x14E70001 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E90054 },
         { .reg = 0x00009888, .val = 0x06E90380 },
         { .reg = 0x00009888, .val = 0x08E90081 },
         { .reg = 0x00009888, .val = 0x0AE90103 },
         { .reg = 0x00009888, .val = 0x0CE90185 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext963__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext963__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext963__avg_gpu_core_frequency__max,acmgt3__ext963__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1928, 24, NULL,acmgt3__ext963__slm_byte_write_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1929, 32, NULL,acmgt3__ext963__load_store_cache_byte_write_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext964_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext964";
   query->symbol_name = "Ext964";
   query->guid = "00a17d53-6cda-47b5-95fe-36770dab66c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1A870012 },
         { .reg = 0x00009888, .val = 0x1E890083 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x04870020 },
         { .reg = 0x00009888, .val = 0x0E870580 },
         { .reg = 0x00009888, .val = 0x10870515 },
         { .reg = 0x00009888, .val = 0x12870493 },
         { .reg = 0x00009888, .val = 0x14870411 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x02870000 },
         { .reg = 0x00009888, .val = 0x02893200 },
         { .reg = 0x00009888, .val = 0x06890790 },
         { .reg = 0x00009888, .val = 0x08890491 },
         { .reg = 0x00009888, .val = 0x0A890513 },
         { .reg = 0x00009888, .val = 0x0C890595 },
         { .reg = 0x00009888, .val = 0x04890000 },
         { .reg = 0x00009888, .val = 0x00890000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext964__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext964__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext964__avg_gpu_core_frequency__max,acmgt3__ext964__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1938, 24, NULL,acmgt3__ext964__slm_byte_write_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1939, 32, NULL,acmgt3__ext964__load_store_cache_byte_write_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext965_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext965";
   query->symbol_name = "Ext965";
   query->guid = "3259b467-758c-42e9-a86f-a35e44003569";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AA70012 },
         { .reg = 0x00009888, .val = 0x1EA90083 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x04A70020 },
         { .reg = 0x00009888, .val = 0x0EA70580 },
         { .reg = 0x00009888, .val = 0x10A70515 },
         { .reg = 0x00009888, .val = 0x12A70493 },
         { .reg = 0x00009888, .val = 0x14A70411 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A70000 },
         { .reg = 0x00009888, .val = 0x02A93200 },
         { .reg = 0x00009888, .val = 0x06A90790 },
         { .reg = 0x00009888, .val = 0x08A90491 },
         { .reg = 0x00009888, .val = 0x0AA90513 },
         { .reg = 0x00009888, .val = 0x0CA90595 },
         { .reg = 0x00009888, .val = 0x04A90000 },
         { .reg = 0x00009888, .val = 0x00A90000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext965__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext965__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext965__avg_gpu_core_frequency__max,acmgt3__ext965__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1940, 24, NULL,acmgt3__ext965__slm_byte_write_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1941, 32, NULL,acmgt3__ext965__load_store_cache_byte_write_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext966_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext966";
   query->symbol_name = "Ext966";
   query->guid = "a96fef9c-bc3d-4986-b2b9-d2233b157ac7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AC70012 },
         { .reg = 0x00009888, .val = 0x1EC90083 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x04C70020 },
         { .reg = 0x00009888, .val = 0x0EC70580 },
         { .reg = 0x00009888, .val = 0x10C70515 },
         { .reg = 0x00009888, .val = 0x12C70493 },
         { .reg = 0x00009888, .val = 0x14C70411 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C70000 },
         { .reg = 0x00009888, .val = 0x02C93200 },
         { .reg = 0x00009888, .val = 0x06C90790 },
         { .reg = 0x00009888, .val = 0x08C90491 },
         { .reg = 0x00009888, .val = 0x0AC90513 },
         { .reg = 0x00009888, .val = 0x0CC90595 },
         { .reg = 0x00009888, .val = 0x04C90000 },
         { .reg = 0x00009888, .val = 0x00C90000 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext966__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext966__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext966__avg_gpu_core_frequency__max,acmgt3__ext966__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1942, 24, NULL,acmgt3__ext966__slm_byte_write_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1943, 32, NULL,acmgt3__ext966__load_store_cache_byte_write_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext967_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext967";
   query->symbol_name = "Ext967";
   query->guid = "cffa549c-1997-4b02-adfc-81fbff2971c2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1AE70012 },
         { .reg = 0x00009888, .val = 0x1EE90083 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x04E70020 },
         { .reg = 0x00009888, .val = 0x0EE70580 },
         { .reg = 0x00009888, .val = 0x10E70515 },
         { .reg = 0x00009888, .val = 0x12E70493 },
         { .reg = 0x00009888, .val = 0x14E70411 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E70000 },
         { .reg = 0x00009888, .val = 0x02E93200 },
         { .reg = 0x00009888, .val = 0x06E90790 },
         { .reg = 0x00009888, .val = 0x08E90491 },
         { .reg = 0x00009888, .val = 0x0AE90513 },
         { .reg = 0x00009888, .val = 0x0CE90595 },
         { .reg = 0x00009888, .val = 0x04E90000 },
         { .reg = 0x00009888, .val = 0x00E90000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030C60 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030003 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030600 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030C63 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext967__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext967__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext967__avg_gpu_core_frequency__max,acmgt3__ext967__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1944, 24, NULL,acmgt3__ext967__slm_byte_write_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1945, 32, NULL,acmgt3__ext967__load_store_cache_byte_write_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext968_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext968";
   query->symbol_name = "Ext968";
   query->guid = "97bb78db-526f-45e9-b302-e71bdb354a51";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12880012 },
         { .reg = 0x00009888, .val = 0x22890C00 },
         { .reg = 0x00009888, .val = 0x24890004 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x0A880180 },
         { .reg = 0x00009888, .val = 0x0C880105 },
         { .reg = 0x00009888, .val = 0x0E880083 },
         { .reg = 0x00009888, .val = 0x10880001 },
         { .reg = 0x00009888, .val = 0x04890008 },
         { .reg = 0x00009888, .val = 0x06890BA0 },
         { .reg = 0x00009888, .val = 0x088908A1 },
         { .reg = 0x00009888, .val = 0x0A890923 },
         { .reg = 0x00009888, .val = 0x0C8909A5 },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext968__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext968__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext968__avg_gpu_core_frequency__max,acmgt3__ext968__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1954, 24, NULL,acmgt3__ext968__slm_byte_write_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1955, 32, NULL,acmgt3__ext968__load_store_cache_byte_write_bank2_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext969_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext969";
   query->symbol_name = "Ext969";
   query->guid = "0f12e897-1e98-49e9-bd01-463aec885b06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12A80012 },
         { .reg = 0x00009888, .val = 0x22A90C00 },
         { .reg = 0x00009888, .val = 0x24A90004 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x0AA80180 },
         { .reg = 0x00009888, .val = 0x0CA80105 },
         { .reg = 0x00009888, .val = 0x0EA80083 },
         { .reg = 0x00009888, .val = 0x10A80001 },
         { .reg = 0x00009888, .val = 0x04A90008 },
         { .reg = 0x00009888, .val = 0x06A90BA0 },
         { .reg = 0x00009888, .val = 0x08A908A1 },
         { .reg = 0x00009888, .val = 0x0AA90923 },
         { .reg = 0x00009888, .val = 0x0CA909A5 },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext969__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext969__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext969__avg_gpu_core_frequency__max,acmgt3__ext969__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1956, 24, NULL,acmgt3__ext969__slm_byte_write_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1957, 32, NULL,acmgt3__ext969__load_store_cache_byte_write_bank2_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext970_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext970";
   query->symbol_name = "Ext970";
   query->guid = "742767ec-da64-414c-9f32-f59d97dd9c30";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12C80012 },
         { .reg = 0x00009888, .val = 0x22C90C00 },
         { .reg = 0x00009888, .val = 0x24C90004 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x0AC80180 },
         { .reg = 0x00009888, .val = 0x0CC80105 },
         { .reg = 0x00009888, .val = 0x0EC80083 },
         { .reg = 0x00009888, .val = 0x10C80001 },
         { .reg = 0x00009888, .val = 0x04C90008 },
         { .reg = 0x00009888, .val = 0x06C90BA0 },
         { .reg = 0x00009888, .val = 0x08C908A1 },
         { .reg = 0x00009888, .val = 0x0AC90923 },
         { .reg = 0x00009888, .val = 0x0CC909A5 },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext970__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext970__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext970__avg_gpu_core_frequency__max,acmgt3__ext970__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1958, 24, NULL,acmgt3__ext970__slm_byte_write_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1959, 32, NULL,acmgt3__ext970__load_store_cache_byte_write_bank2_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext971_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext971";
   query->symbol_name = "Ext971";
   query->guid = "b8132d7c-7b59-4906-bea4-7401dd0eea38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x12E80012 },
         { .reg = 0x00009888, .val = 0x22E90C00 },
         { .reg = 0x00009888, .val = 0x24E90004 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x0AE80180 },
         { .reg = 0x00009888, .val = 0x0CE80105 },
         { .reg = 0x00009888, .val = 0x0EE80083 },
         { .reg = 0x00009888, .val = 0x10E80001 },
         { .reg = 0x00009888, .val = 0x04E90008 },
         { .reg = 0x00009888, .val = 0x06E90BA0 },
         { .reg = 0x00009888, .val = 0x08E908A1 },
         { .reg = 0x00009888, .val = 0x0AE90923 },
         { .reg = 0x00009888, .val = 0x0CE909A5 },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext971__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext971__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext971__avg_gpu_core_frequency__max,acmgt3__ext971__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1960, 24, NULL,acmgt3__ext971__slm_byte_write_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1961, 32, NULL,acmgt3__ext971__load_store_cache_byte_write_bank2_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext972_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext972";
   query->symbol_name = "Ext972";
   query->guid = "cbcadae5-b72e-462b-9b5a-b06880be86c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16880012 },
         { .reg = 0x00009888, .val = 0x28891060 },
         { .reg = 0x00009888, .val = 0x0083AAAA },
         { .reg = 0x00009888, .val = 0x0283AAA8 },
         { .reg = 0x00009888, .val = 0x0084FEFF },
         { .reg = 0x00009888, .val = 0x00865555 },
         { .reg = 0x00009888, .val = 0x02865554 },
         { .reg = 0x00009888, .val = 0x0087AAAA },
         { .reg = 0x00009888, .val = 0x0287AAA8 },
         { .reg = 0x00009888, .val = 0x00880020 },
         { .reg = 0x00009888, .val = 0x0A880580 },
         { .reg = 0x00009888, .val = 0x0C880515 },
         { .reg = 0x00009888, .val = 0x0E880493 },
         { .reg = 0x00009888, .val = 0x10880411 },
         { .reg = 0x00009888, .val = 0x04890200 },
         { .reg = 0x00009888, .val = 0x06890FB0 },
         { .reg = 0x00009888, .val = 0x08890CB1 },
         { .reg = 0x00009888, .val = 0x0A890D33 },
         { .reg = 0x00009888, .val = 0x0C890DB5 },
         { .reg = 0x00009888, .val = 0x0089FE00 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext972__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext972__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext972__avg_gpu_core_frequency__max,acmgt3__ext972__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1970, 24, NULL,acmgt3__ext972__slm_byte_write_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 1971, 32, NULL,acmgt3__ext972__load_store_cache_byte_write_bank3_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext973_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext973";
   query->symbol_name = "Ext973";
   query->guid = "03be681d-684c-4f4d-8a09-18e0a605c864";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16A80012 },
         { .reg = 0x00009888, .val = 0x28A91060 },
         { .reg = 0x00009888, .val = 0x00A3AAAA },
         { .reg = 0x00009888, .val = 0x02A3AAA8 },
         { .reg = 0x00009888, .val = 0x00A4FEFF },
         { .reg = 0x00009888, .val = 0x00A65555 },
         { .reg = 0x00009888, .val = 0x02A65554 },
         { .reg = 0x00009888, .val = 0x00A7AAAA },
         { .reg = 0x00009888, .val = 0x02A7AAA8 },
         { .reg = 0x00009888, .val = 0x00A80020 },
         { .reg = 0x00009888, .val = 0x0AA80580 },
         { .reg = 0x00009888, .val = 0x0CA80515 },
         { .reg = 0x00009888, .val = 0x0EA80493 },
         { .reg = 0x00009888, .val = 0x10A80411 },
         { .reg = 0x00009888, .val = 0x04A90200 },
         { .reg = 0x00009888, .val = 0x06A90FB0 },
         { .reg = 0x00009888, .val = 0x08A90CB1 },
         { .reg = 0x00009888, .val = 0x0AA90D33 },
         { .reg = 0x00009888, .val = 0x0CA90DB5 },
         { .reg = 0x00009888, .val = 0x00A9FE00 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFC },
         { .reg = 0x00009888, .val = 0x000A5555 },
         { .reg = 0x00009888, .val = 0x020A5554 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x000B5555 },
         { .reg = 0x00009888, .val = 0x020B5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext973__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext973__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext973__avg_gpu_core_frequency__max,acmgt3__ext973__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1972, 24, NULL,acmgt3__ext973__slm_byte_write_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 1973, 32, NULL,acmgt3__ext973__load_store_cache_byte_write_bank3_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext974_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext974";
   query->symbol_name = "Ext974";
   query->guid = "acca3492-bdac-49b9-aa54-9d7033f6d46d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16C80012 },
         { .reg = 0x00009888, .val = 0x28C91060 },
         { .reg = 0x00009888, .val = 0x00C3AAAA },
         { .reg = 0x00009888, .val = 0x02C3AAA8 },
         { .reg = 0x00009888, .val = 0x00C4FEFF },
         { .reg = 0x00009888, .val = 0x00C65555 },
         { .reg = 0x00009888, .val = 0x02C65554 },
         { .reg = 0x00009888, .val = 0x00C7AAAA },
         { .reg = 0x00009888, .val = 0x02C7AAA8 },
         { .reg = 0x00009888, .val = 0x00C80020 },
         { .reg = 0x00009888, .val = 0x0AC80580 },
         { .reg = 0x00009888, .val = 0x0CC80515 },
         { .reg = 0x00009888, .val = 0x0EC80493 },
         { .reg = 0x00009888, .val = 0x10C80411 },
         { .reg = 0x00009888, .val = 0x04C90200 },
         { .reg = 0x00009888, .val = 0x06C90FB0 },
         { .reg = 0x00009888, .val = 0x08C90CB1 },
         { .reg = 0x00009888, .val = 0x0AC90D33 },
         { .reg = 0x00009888, .val = 0x0CC90DB5 },
         { .reg = 0x00009888, .val = 0x00C9FE00 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207AAA8 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009888, .val = 0x0002FEFF },
         { .reg = 0x00009888, .val = 0x000C5555 },
         { .reg = 0x00009888, .val = 0x020C5554 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext974__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext974__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext974__avg_gpu_core_frequency__max,acmgt3__ext974__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1974, 24, NULL,acmgt3__ext974__slm_byte_write_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 1975, 32, NULL,acmgt3__ext974__load_store_cache_byte_write_bank3_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext975_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext975";
   query->symbol_name = "Ext975";
   query->guid = "2c53a11a-5077-487c-bf6d-894ac78600c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16E80012 },
         { .reg = 0x00009888, .val = 0x28E91060 },
         { .reg = 0x00009888, .val = 0x00E3AAAA },
         { .reg = 0x00009888, .val = 0x02E3AAA8 },
         { .reg = 0x00009888, .val = 0x00E4FEFF },
         { .reg = 0x00009888, .val = 0x00E65555 },
         { .reg = 0x00009888, .val = 0x02E65554 },
         { .reg = 0x00009888, .val = 0x00E7AAAA },
         { .reg = 0x00009888, .val = 0x02E7AAA8 },
         { .reg = 0x00009888, .val = 0x00E80020 },
         { .reg = 0x00009888, .val = 0x0AE80580 },
         { .reg = 0x00009888, .val = 0x0CE80515 },
         { .reg = 0x00009888, .val = 0x0EE80493 },
         { .reg = 0x00009888, .val = 0x10E80411 },
         { .reg = 0x00009888, .val = 0x04E90200 },
         { .reg = 0x00009888, .val = 0x06E90FB0 },
         { .reg = 0x00009888, .val = 0x08E90CB1 },
         { .reg = 0x00009888, .val = 0x0AE90D33 },
         { .reg = 0x00009888, .val = 0x0CE90DB5 },
         { .reg = 0x00009888, .val = 0x00E9FE00 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02075554 },
         { .reg = 0x00009888, .val = 0x0009FEFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032092 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FEFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025554 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045554 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055554 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x70800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext975__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext975__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext975__avg_gpu_core_frequency__max,acmgt3__ext975__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1976, 24, NULL,acmgt3__ext975__slm_byte_write_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 1977, 32, NULL,acmgt3__ext975__load_store_cache_byte_write_bank3_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext976_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext976";
   query->symbol_name = "Ext976";
   query->guid = "ce390b14-0e8c-4f97-afd8-d3296ca986c4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x168502A0 },
         { .reg = 0x00009888, .val = 0x16A502A0 },
         { .reg = 0x00009888, .val = 0x16C502A0 },
         { .reg = 0x00009888, .val = 0x16E502A0 },
         { .reg = 0x00009888, .val = 0x178502A0 },
         { .reg = 0x00009888, .val = 0x17A502A0 },
         { .reg = 0x00009888, .val = 0x17C502A0 },
         { .reg = 0x00009888, .val = 0x17E502A0 },
         { .reg = 0x00009888, .val = 0x02850004 },
         { .reg = 0x00009888, .val = 0x04850C20 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086000A },
         { .reg = 0x00009888, .val = 0x02A50004 },
         { .reg = 0x00009888, .val = 0x06A500C2 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A600A0 },
         { .reg = 0x00009888, .val = 0x02C50004 },
         { .reg = 0x00009888, .val = 0x08C500C2 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C60A00 },
         { .reg = 0x00009888, .val = 0x02E50004 },
         { .reg = 0x00009888, .val = 0x0AE500C2 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6A000 },
         { .reg = 0x00009888, .val = 0x03850004 },
         { .reg = 0x00009888, .val = 0x0D8500C2 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386000A },
         { .reg = 0x00009888, .val = 0x03A50004 },
         { .reg = 0x00009888, .val = 0x0FA500C2 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600A0 },
         { .reg = 0x00009888, .val = 0x03C50004 },
         { .reg = 0x00009888, .val = 0x11C500C2 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C60A00 },
         { .reg = 0x00009888, .val = 0x03E50004 },
         { .reg = 0x00009888, .val = 0x13E500C2 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6A000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001805 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006005 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018005 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060005 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext976__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext976__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext976__avg_gpu_core_frequency__max,acmgt3__ext976__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 1666, 24, percentage_max_float,acmgt3__ext976__rt_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 1667, 28, percentage_max_float,acmgt3__ext976__rt_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 1668, 32, percentage_max_float,acmgt3__ext976__rt_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 1669, 36, percentage_max_float,acmgt3__ext976__rt_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 1670, 40, percentage_max_float,acmgt3__ext976__rt_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 1671, 44, percentage_max_float,acmgt3__ext976__rt_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 1672, 48, percentage_max_float,acmgt3__ext976__rt_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 1673, 52, percentage_max_float,acmgt3__ext976__rt_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext977_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext977";
   query->symbol_name = "Ext977";
   query->guid = "f638017d-bd81-4359-9f9b-daafcd5b9492";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000D },
         { .reg = 0x00009888, .val = 0x168502A0 },
         { .reg = 0x00009888, .val = 0x16A502A0 },
         { .reg = 0x00009888, .val = 0x16C502A0 },
         { .reg = 0x00009888, .val = 0x16E502A0 },
         { .reg = 0x00009888, .val = 0x178502A0 },
         { .reg = 0x00009888, .val = 0x17A502A0 },
         { .reg = 0x00009888, .val = 0x17C502A0 },
         { .reg = 0x00009888, .val = 0x17E502A0 },
         { .reg = 0x00009888, .val = 0x02850004 },
         { .reg = 0x00009888, .val = 0x04850C20 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086000A },
         { .reg = 0x00009888, .val = 0x02A50004 },
         { .reg = 0x00009888, .val = 0x06A500C2 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A600A0 },
         { .reg = 0x00009888, .val = 0x02C50004 },
         { .reg = 0x00009888, .val = 0x08C500C2 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C60A00 },
         { .reg = 0x00009888, .val = 0x02E50004 },
         { .reg = 0x00009888, .val = 0x0AE500C2 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6A000 },
         { .reg = 0x00009888, .val = 0x03850004 },
         { .reg = 0x00009888, .val = 0x0D8500C2 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386000A },
         { .reg = 0x00009888, .val = 0x03A50004 },
         { .reg = 0x00009888, .val = 0x0FA500C2 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600A0 },
         { .reg = 0x00009888, .val = 0x03C50004 },
         { .reg = 0x00009888, .val = 0x11C500C2 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C60A00 },
         { .reg = 0x00009888, .val = 0x03E50004 },
         { .reg = 0x00009888, .val = 0x13E500C2 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6A000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x00032492 },
         { .reg = 0x00009888, .val = 0x02032492 },
         { .reg = 0x00009888, .val = 0x04032492 },
         { .reg = 0x00009888, .val = 0x06030002 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001805 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006005 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018005 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060005 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext977__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext977__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext977__avg_gpu_core_frequency__max,acmgt3__ext977__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 0)) {
         intel_perf_query_add_counter_float(query, 2983, 24, percentage_max_float,acmgt3__ext977__rt_input_available_xecore8__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 1)) {
         intel_perf_query_add_counter_float(query, 2984, 28, percentage_max_float,acmgt3__ext977__rt_input_available_xecore9__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 2)) {
         intel_perf_query_add_counter_float(query, 2985, 32, percentage_max_float,acmgt3__ext977__rt_input_available_xecore10__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 2, 3)) {
         intel_perf_query_add_counter_float(query, 2986, 36, percentage_max_float,acmgt3__ext977__rt_input_available_xecore11__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 0)) {
         intel_perf_query_add_counter_float(query, 2987, 40, percentage_max_float,acmgt3__ext977__rt_input_available_xecore12__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 1)) {
         intel_perf_query_add_counter_float(query, 2988, 44, percentage_max_float,acmgt3__ext977__rt_input_available_xecore13__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 2)) {
         intel_perf_query_add_counter_float(query, 2989, 48, percentage_max_float,acmgt3__ext977__rt_input_available_xecore14__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 3, 3)) {
         intel_perf_query_add_counter_float(query, 2990, 52, percentage_max_float,acmgt3__ext977__rt_input_available_xecore15__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext978_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext978";
   query->symbol_name = "Ext978";
   query->guid = "28b23f45-71a2-44d2-9661-423be5a6831d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000E },
         { .reg = 0x00009888, .val = 0x168502A0 },
         { .reg = 0x00009888, .val = 0x16A502A0 },
         { .reg = 0x00009888, .val = 0x16C502A0 },
         { .reg = 0x00009888, .val = 0x16E502A0 },
         { .reg = 0x00009888, .val = 0x178502A0 },
         { .reg = 0x00009888, .val = 0x17A502A0 },
         { .reg = 0x00009888, .val = 0x17C502A0 },
         { .reg = 0x00009888, .val = 0x17E502A0 },
         { .reg = 0x00009888, .val = 0x02850004 },
         { .reg = 0x00009888, .val = 0x04850C20 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086000A },
         { .reg = 0x00009888, .val = 0x02A50004 },
         { .reg = 0x00009888, .val = 0x06A500C2 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A600A0 },
         { .reg = 0x00009888, .val = 0x02C50004 },
         { .reg = 0x00009888, .val = 0x08C500C2 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C60A00 },
         { .reg = 0x00009888, .val = 0x02E50004 },
         { .reg = 0x00009888, .val = 0x0AE500C2 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6A000 },
         { .reg = 0x00009888, .val = 0x03850004 },
         { .reg = 0x00009888, .val = 0x0D8500C2 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386000A },
         { .reg = 0x00009888, .val = 0x03A50004 },
         { .reg = 0x00009888, .val = 0x0FA500C2 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600A0 },
         { .reg = 0x00009888, .val = 0x03C50004 },
         { .reg = 0x00009888, .val = 0x11C500C2 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C60A00 },
         { .reg = 0x00009888, .val = 0x03E50004 },
         { .reg = 0x00009888, .val = 0x13E500C2 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6A000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001805 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006005 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018005 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060005 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext978__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext978__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext978__avg_gpu_core_frequency__max,acmgt3__ext978__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 0)) {
         intel_perf_query_add_counter_float(query, 5621, 24, percentage_max_float,acmgt3__ext978__rt_input_available_xecore16__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 1)) {
         intel_perf_query_add_counter_float(query, 5622, 28, percentage_max_float,acmgt3__ext978__rt_input_available_xecore17__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 2)) {
         intel_perf_query_add_counter_float(query, 5623, 32, percentage_max_float,acmgt3__ext978__rt_input_available_xecore18__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 4, 3)) {
         intel_perf_query_add_counter_float(query, 5624, 36, percentage_max_float,acmgt3__ext978__rt_input_available_xecore19__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 0)) {
         intel_perf_query_add_counter_float(query, 5625, 40, percentage_max_float,acmgt3__ext978__rt_input_available_xecore20__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 1)) {
         intel_perf_query_add_counter_float(query, 5626, 44, percentage_max_float,acmgt3__ext978__rt_input_available_xecore21__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 2)) {
         intel_perf_query_add_counter_float(query, 5627, 48, percentage_max_float,acmgt3__ext978__rt_input_available_xecore22__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 5, 3)) {
         intel_perf_query_add_counter_float(query, 5628, 52, percentage_max_float,acmgt3__ext978__rt_input_available_xecore23__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext979_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext979";
   query->symbol_name = "Ext979";
   query->guid = "88f7e719-828f-466e-8c74-61c31b885975";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000F },
         { .reg = 0x00009888, .val = 0x168502A0 },
         { .reg = 0x00009888, .val = 0x16A502A0 },
         { .reg = 0x00009888, .val = 0x16C502A0 },
         { .reg = 0x00009888, .val = 0x16E502A0 },
         { .reg = 0x00009888, .val = 0x178502A0 },
         { .reg = 0x00009888, .val = 0x17A502A0 },
         { .reg = 0x00009888, .val = 0x17C502A0 },
         { .reg = 0x00009888, .val = 0x17E502A0 },
         { .reg = 0x00009888, .val = 0x02850004 },
         { .reg = 0x00009888, .val = 0x04850C20 },
         { .reg = 0x00009888, .val = 0x06850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x0086000A },
         { .reg = 0x00009888, .val = 0x02A50004 },
         { .reg = 0x00009888, .val = 0x06A500C2 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A600A0 },
         { .reg = 0x00009888, .val = 0x02C50004 },
         { .reg = 0x00009888, .val = 0x08C500C2 },
         { .reg = 0x00009888, .val = 0x06C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C60A00 },
         { .reg = 0x00009888, .val = 0x02E50004 },
         { .reg = 0x00009888, .val = 0x0AE500C2 },
         { .reg = 0x00009888, .val = 0x06E50000 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E6A000 },
         { .reg = 0x00009888, .val = 0x03850004 },
         { .reg = 0x00009888, .val = 0x0D8500C2 },
         { .reg = 0x00009888, .val = 0x07850000 },
         { .reg = 0x00009888, .val = 0x01850000 },
         { .reg = 0x00009888, .val = 0x0386000A },
         { .reg = 0x00009888, .val = 0x03A50004 },
         { .reg = 0x00009888, .val = 0x0FA500C2 },
         { .reg = 0x00009888, .val = 0x07A50000 },
         { .reg = 0x00009888, .val = 0x01A50000 },
         { .reg = 0x00009888, .val = 0x03A600A0 },
         { .reg = 0x00009888, .val = 0x03C50004 },
         { .reg = 0x00009888, .val = 0x11C500C2 },
         { .reg = 0x00009888, .val = 0x07C50000 },
         { .reg = 0x00009888, .val = 0x01C50000 },
         { .reg = 0x00009888, .val = 0x03C60A00 },
         { .reg = 0x00009888, .val = 0x03E50004 },
         { .reg = 0x00009888, .val = 0x13E500C2 },
         { .reg = 0x00009888, .val = 0x07E50000 },
         { .reg = 0x00009888, .val = 0x01E50000 },
         { .reg = 0x00009888, .val = 0x03E6A000 },
         { .reg = 0x00009888, .val = 0x0003FF00 },
         { .reg = 0x00009888, .val = 0x00075A00 },
         { .reg = 0x00009888, .val = 0x000800FA },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009888, .val = 0x000900F0 },
         { .reg = 0x00009888, .val = 0x000AAA55 },
         { .reg = 0x00009888, .val = 0x020A5555 },
         { .reg = 0x00009888, .val = 0x0001FF0C },
         { .reg = 0x00009888, .val = 0x000B0050 },
         { .reg = 0x00009888, .val = 0x020BAAAA },
         { .reg = 0x00009888, .val = 0x00020030 },
         { .reg = 0x00009888, .val = 0x000C0500 },
         { .reg = 0x00009888, .val = 0x03075A00 },
         { .reg = 0x00009888, .val = 0x030800FA },
         { .reg = 0x00009888, .val = 0x0109F000 },
         { .reg = 0x00009888, .val = 0x030AAA55 },
         { .reg = 0x00009888, .val = 0x01010C00 },
         { .reg = 0x00009888, .val = 0x030B0050 },
         { .reg = 0x00009888, .val = 0x01023000 },
         { .reg = 0x00009888, .val = 0x030C0500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009888, .val = 0x00031249 },
         { .reg = 0x00009888, .val = 0x02031249 },
         { .reg = 0x00009888, .val = 0x04031249 },
         { .reg = 0x00009888, .val = 0x06030001 },
         { .reg = 0x00009888, .val = 0x14037000 },
         { .reg = 0x00009888, .val = 0x3E030C6A },
         { .reg = 0x00009888, .val = 0x26037000 },
         { .reg = 0x00009888, .val = 0x4203014A },
         { .reg = 0x00009888, .val = 0x2C037000 },
         { .reg = 0x00009888, .val = 0x32037000 },
         { .reg = 0x00009888, .val = 0x44030D00 },
         { .reg = 0x00009888, .val = 0x38033000 },
         { .reg = 0x00009888, .val = 0x46030EE8 },
         { .reg = 0x00009888, .val = 0x48030277 },
         { .reg = 0x00009888, .val = 0x4A030422 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40032800 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x00055555 },
         { .reg = 0x00009888, .val = 0x02055555 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001805 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006005 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018005 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060005 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext979__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext979__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext979__avg_gpu_core_frequency__max,acmgt3__ext979__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 0)) {
         intel_perf_query_add_counter_float(query, 5629, 24, percentage_max_float,acmgt3__ext979__rt_input_available_xecore24__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 1)) {
         intel_perf_query_add_counter_float(query, 5630, 28, percentage_max_float,acmgt3__ext979__rt_input_available_xecore25__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 2)) {
         intel_perf_query_add_counter_float(query, 5631, 32, percentage_max_float,acmgt3__ext979__rt_input_available_xecore26__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 6, 3)) {
         intel_perf_query_add_counter_float(query, 5632, 36, percentage_max_float,acmgt3__ext979__rt_input_available_xecore27__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 0)) {
         intel_perf_query_add_counter_float(query, 5633, 40, percentage_max_float,acmgt3__ext979__rt_input_available_xecore28__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 1)) {
         intel_perf_query_add_counter_float(query, 5634, 44, percentage_max_float,acmgt3__ext979__rt_input_available_xecore29__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 2)) {
         intel_perf_query_add_counter_float(query, 5635, 48, percentage_max_float,acmgt3__ext979__rt_input_available_xecore30__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 7, 3)) {
         intel_perf_query_add_counter_float(query, 5636, 52, percentage_max_float,acmgt3__ext979__rt_input_available_xecore31__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext980_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext980";
   query->symbol_name = "Ext980";
   query->guid = "8ac802cf-f221-461c-aedd-7a45bcb63165";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1A012540 },
         { .reg = 0x00009888, .val = 0x18213800 },
         { .reg = 0x00009888, .val = 0x1A21000F },
         { .reg = 0x00009888, .val = 0x02010128 },
         { .reg = 0x00009888, .val = 0x06011400 },
         { .reg = 0x00009888, .val = 0x08010288 },
         { .reg = 0x00009888, .val = 0x0A01030B },
         { .reg = 0x00009888, .val = 0x0C01038D },
         { .reg = 0x00009888, .val = 0x0E01000F },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x022100E6 },
         { .reg = 0x00009888, .val = 0x0E210180 },
         { .reg = 0x00009888, .val = 0x10210288 },
         { .reg = 0x00009888, .val = 0x1221030B },
         { .reg = 0x00009888, .val = 0x1421038D },
         { .reg = 0x00009888, .val = 0x1621000F },
         { .reg = 0x00009888, .val = 0x00210000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x000A2492 },
         { .reg = 0x00009888, .val = 0x020A2492 },
         { .reg = 0x00009888, .val = 0x040A2492 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x000B1249 },
         { .reg = 0x00009888, .val = 0x020B2449 },
         { .reg = 0x00009888, .val = 0x040B2492 },
         { .reg = 0x00009888, .val = 0x060B0002 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext980__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext980__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext980__avg_gpu_core_frequency__max,acmgt3__ext980__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1792, 24, NULL,acmgt3__ext980__gpu_memory_l3_read_sqidi0__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext981_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext981";
   query->symbol_name = "Ext981";
   query->guid = "1bcb5260-ee4d-4c39-ba59-033b7bd84271";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18013800 },
         { .reg = 0x00009888, .val = 0x1A01000F },
         { .reg = 0x00009888, .val = 0x1A212540 },
         { .reg = 0x00009888, .val = 0x020100E6 },
         { .reg = 0x00009888, .val = 0x0E010180 },
         { .reg = 0x00009888, .val = 0x10010288 },
         { .reg = 0x00009888, .val = 0x1201030B },
         { .reg = 0x00009888, .val = 0x1401038D },
         { .reg = 0x00009888, .val = 0x1601000F },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02210128 },
         { .reg = 0x00009888, .val = 0x06211400 },
         { .reg = 0x00009888, .val = 0x08210288 },
         { .reg = 0x00009888, .val = 0x0A21030B },
         { .reg = 0x00009888, .val = 0x0C21038D },
         { .reg = 0x00009888, .val = 0x0E21000F },
         { .reg = 0x00009888, .val = 0x00210000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x000A2492 },
         { .reg = 0x00009888, .val = 0x020A2492 },
         { .reg = 0x00009888, .val = 0x040A2492 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x000B2492 },
         { .reg = 0x00009888, .val = 0x020B1292 },
         { .reg = 0x00009888, .val = 0x040B1249 },
         { .reg = 0x00009888, .val = 0x060B0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext981__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext981__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext981__avg_gpu_core_frequency__max,acmgt3__ext981__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1793, 24, NULL,acmgt3__ext981__gpu_memory_l3_read_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext982_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext982";
   query->symbol_name = "Ext982";
   query->guid = "7480a976-6f5e-46e3-babb-01cc4b34cd75";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1A412540 },
         { .reg = 0x00009888, .val = 0x18613800 },
         { .reg = 0x00009888, .val = 0x1A61000F },
         { .reg = 0x00009888, .val = 0x02410128 },
         { .reg = 0x00009888, .val = 0x06411400 },
         { .reg = 0x00009888, .val = 0x08410288 },
         { .reg = 0x00009888, .val = 0x0A41030B },
         { .reg = 0x00009888, .val = 0x0C41038D },
         { .reg = 0x00009888, .val = 0x0E41000F },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x026100E6 },
         { .reg = 0x00009888, .val = 0x0E610180 },
         { .reg = 0x00009888, .val = 0x10610288 },
         { .reg = 0x00009888, .val = 0x1261030B },
         { .reg = 0x00009888, .val = 0x1461038D },
         { .reg = 0x00009888, .val = 0x1661000F },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x000A2492 },
         { .reg = 0x00009888, .val = 0x020A2492 },
         { .reg = 0x00009888, .val = 0x040A2492 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x000B36DB },
         { .reg = 0x00009888, .val = 0x020B48DB },
         { .reg = 0x00009888, .val = 0x040B4924 },
         { .reg = 0x00009888, .val = 0x060B0004 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext982__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext982__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext982__avg_gpu_core_frequency__max,acmgt3__ext982__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2815, 24, NULL,acmgt3__ext982__gpu_memory_l3_read_sqidi2__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext983_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext983";
   query->symbol_name = "Ext983";
   query->guid = "599cd4bb-5fd9-4586-b813-fcb44b53b648";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18413800 },
         { .reg = 0x00009888, .val = 0x1A41000F },
         { .reg = 0x00009888, .val = 0x1A612540 },
         { .reg = 0x00009888, .val = 0x024100E6 },
         { .reg = 0x00009888, .val = 0x0E410180 },
         { .reg = 0x00009888, .val = 0x10410288 },
         { .reg = 0x00009888, .val = 0x1241030B },
         { .reg = 0x00009888, .val = 0x1441038D },
         { .reg = 0x00009888, .val = 0x1641000F },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02610128 },
         { .reg = 0x00009888, .val = 0x06611400 },
         { .reg = 0x00009888, .val = 0x08610288 },
         { .reg = 0x00009888, .val = 0x0A61030B },
         { .reg = 0x00009888, .val = 0x0C61038D },
         { .reg = 0x00009888, .val = 0x0E61000F },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x000A2492 },
         { .reg = 0x00009888, .val = 0x020A2492 },
         { .reg = 0x00009888, .val = 0x040A2492 },
         { .reg = 0x00009888, .val = 0x060A0002 },
         { .reg = 0x00009888, .val = 0x000B4924 },
         { .reg = 0x00009888, .val = 0x020B3724 },
         { .reg = 0x00009888, .val = 0x040B36DB },
         { .reg = 0x00009888, .val = 0x060B0003 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext983__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext983__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext983__avg_gpu_core_frequency__max,acmgt3__ext983__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2816, 24, NULL,acmgt3__ext983__gpu_memory_l3_read_sqidi3__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext984_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext984";
   query->symbol_name = "Ext984";
   query->guid = "3661cc06-7370-4d4d-9838-6ba6847fb2af";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1A812540 },
         { .reg = 0x00009888, .val = 0x18A13800 },
         { .reg = 0x00009888, .val = 0x1AA1000F },
         { .reg = 0x00009888, .val = 0x02810128 },
         { .reg = 0x00009888, .val = 0x06811400 },
         { .reg = 0x00009888, .val = 0x08810288 },
         { .reg = 0x00009888, .val = 0x0A81030B },
         { .reg = 0x00009888, .val = 0x0C81038D },
         { .reg = 0x00009888, .val = 0x0E81000F },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A100E6 },
         { .reg = 0x00009888, .val = 0x0EA10180 },
         { .reg = 0x00009888, .val = 0x10A10288 },
         { .reg = 0x00009888, .val = 0x12A1030B },
         { .reg = 0x00009888, .val = 0x14A1038D },
         { .reg = 0x00009888, .val = 0x16A1000F },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x00091249 },
         { .reg = 0x00009888, .val = 0x02092449 },
         { .reg = 0x00009888, .val = 0x04092492 },
         { .reg = 0x00009888, .val = 0x06090002 },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A1249 },
         { .reg = 0x00009888, .val = 0x040A1249 },
         { .reg = 0x00009888, .val = 0x060A0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030420 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030001 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030201 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030421 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext984__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext984__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext984__avg_gpu_core_frequency__max,acmgt3__ext984__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5637, 24, NULL,acmgt3__ext984__gpu_memory_l3_read_sqidi4__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext985_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext985";
   query->symbol_name = "Ext985";
   query->guid = "3a7100ab-0b38-4148-9fc3-15b735b80668";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18813800 },
         { .reg = 0x00009888, .val = 0x1A81000F },
         { .reg = 0x00009888, .val = 0x1AA12540 },
         { .reg = 0x00009888, .val = 0x028100E6 },
         { .reg = 0x00009888, .val = 0x0E810180 },
         { .reg = 0x00009888, .val = 0x10810288 },
         { .reg = 0x00009888, .val = 0x1281030B },
         { .reg = 0x00009888, .val = 0x1481038D },
         { .reg = 0x00009888, .val = 0x1681000F },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02A10128 },
         { .reg = 0x00009888, .val = 0x06A11400 },
         { .reg = 0x00009888, .val = 0x08A10288 },
         { .reg = 0x00009888, .val = 0x0AA1030B },
         { .reg = 0x00009888, .val = 0x0CA1038D },
         { .reg = 0x00009888, .val = 0x0EA1000F },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x00092492 },
         { .reg = 0x00009888, .val = 0x02091292 },
         { .reg = 0x00009888, .val = 0x04091249 },
         { .reg = 0x00009888, .val = 0x06090001 },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A1249 },
         { .reg = 0x00009888, .val = 0x040A1249 },
         { .reg = 0x00009888, .val = 0x060A0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030001 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030420 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030021 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030201 },
         { .reg = 0x00009888, .val = 0x48030010 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext985__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext985__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext985__avg_gpu_core_frequency__max,acmgt3__ext985__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5638, 24, NULL,acmgt3__ext985__gpu_memory_l3_read_sqidi5__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext986_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext986";
   query->symbol_name = "Ext986";
   query->guid = "ea7e1fea-e645-42b6-875a-170eadcf6716";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x1AC12540 },
         { .reg = 0x00009888, .val = 0x18E13800 },
         { .reg = 0x00009888, .val = 0x1AE1000F },
         { .reg = 0x00009888, .val = 0x02C10128 },
         { .reg = 0x00009888, .val = 0x06C11400 },
         { .reg = 0x00009888, .val = 0x08C10288 },
         { .reg = 0x00009888, .val = 0x0AC1030B },
         { .reg = 0x00009888, .val = 0x0CC1038D },
         { .reg = 0x00009888, .val = 0x0EC1000F },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02E100E6 },
         { .reg = 0x00009888, .val = 0x0EE10180 },
         { .reg = 0x00009888, .val = 0x10E10288 },
         { .reg = 0x00009888, .val = 0x12E1030B },
         { .reg = 0x00009888, .val = 0x14E1038D },
         { .reg = 0x00009888, .val = 0x16E1000F },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x000936DB },
         { .reg = 0x00009888, .val = 0x020948DB },
         { .reg = 0x00009888, .val = 0x04094924 },
         { .reg = 0x00009888, .val = 0x06090004 },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A1249 },
         { .reg = 0x00009888, .val = 0x040A1249 },
         { .reg = 0x00009888, .val = 0x060A0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext986__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext986__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext986__avg_gpu_core_frequency__max,acmgt3__ext986__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5639, 24, NULL,acmgt3__ext986__gpu_memory_l3_read_sqidi6__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext987_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext987";
   query->symbol_name = "Ext987";
   query->guid = "0cc6ded2-c760-49d1-80c2-0ecd33484aca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000001 },
         { .reg = 0x00009888, .val = 0x18C13800 },
         { .reg = 0x00009888, .val = 0x1AC1000F },
         { .reg = 0x00009888, .val = 0x1AE12540 },
         { .reg = 0x00009888, .val = 0x02C100E6 },
         { .reg = 0x00009888, .val = 0x0EC10180 },
         { .reg = 0x00009888, .val = 0x10C10288 },
         { .reg = 0x00009888, .val = 0x12C1030B },
         { .reg = 0x00009888, .val = 0x14C1038D },
         { .reg = 0x00009888, .val = 0x16C1000F },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02E10128 },
         { .reg = 0x00009888, .val = 0x06E11400 },
         { .reg = 0x00009888, .val = 0x08E10288 },
         { .reg = 0x00009888, .val = 0x0AE1030B },
         { .reg = 0x00009888, .val = 0x0CE1038D },
         { .reg = 0x00009888, .val = 0x0EE1000F },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00034924 },
         { .reg = 0x00009888, .val = 0x02034924 },
         { .reg = 0x00009888, .val = 0x04034924 },
         { .reg = 0x00009888, .val = 0x06030004 },
         { .reg = 0x00009888, .val = 0x00094924 },
         { .reg = 0x00009888, .val = 0x02093724 },
         { .reg = 0x00009888, .val = 0x040936DB },
         { .reg = 0x00009888, .val = 0x06090003 },
         { .reg = 0x00009888, .val = 0x000A1249 },
         { .reg = 0x00009888, .val = 0x020A1249 },
         { .reg = 0x00009888, .val = 0x040A1249 },
         { .reg = 0x00009888, .val = 0x060A0001 },
         { .reg = 0x00009888, .val = 0x14030000 },
         { .reg = 0x00009888, .val = 0x3E030000 },
         { .reg = 0x00009888, .val = 0x26030000 },
         { .reg = 0x00009888, .val = 0x42030000 },
         { .reg = 0x00009888, .val = 0x2C030000 },
         { .reg = 0x00009888, .val = 0x32030000 },
         { .reg = 0x00009888, .val = 0x44030000 },
         { .reg = 0x00009888, .val = 0x38030000 },
         { .reg = 0x00009888, .val = 0x46030000 },
         { .reg = 0x00009888, .val = 0x48030000 },
         { .reg = 0x00009888, .val = 0x4A030000 },
         { .reg = 0x00009888, .val = 0x16030000 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x40030000 },
         { .reg = 0x00009888, .val = 0x1C030000 },
         { .reg = 0x00009888, .val = 0x1E030000 },
         { .reg = 0x00009888, .val = 0x20030000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x5C030002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext987__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext987__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext987__avg_gpu_core_frequency__max,acmgt3__ext987__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5640, 24, NULL,acmgt3__ext987__gpu_memory_l3_read_sqidi7__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext1000_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1000";
   query->symbol_name = "Ext1000";
   query->guid = "6ed6774b-beba-4a52-baae-04188cd01cc0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00002009 },
         { .reg = 0x0000E758, .val = 0x01008001 },
         { .reg = 0x0000E45C, .val = 0x0000300A },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext1000__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext1000__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext1000__avg_gpu_core_frequency__max,acmgt3__ext1000__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 764, 24, percentage_max_float,acmgt3__ext1000__xve_active__read);

      intel_perf_query_add_counter_float(query, 765, 28, percentage_max_float,acmgt3__ext1000__xve_stall__read);

      intel_perf_query_add_counter_float(query, 767, 32, percentage_max_float,acmgt3__ext1000__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 771, 40, acmgt3__ext1000__xve_inst_executed_alu0_all__max,acmgt3__ext1000__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 772, 48, acmgt3__ext1000__xve_inst_executed_alu1_all__max,acmgt3__ext1000__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 773, 56, acmgt3__ext1000__xve_inst_executed_xmx_all__max,acmgt3__ext1000__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 774, 64, acmgt3__ext1000__xve_inst_executed_send_all__max,acmgt3__ext1000__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 775, 72, acmgt3__ext1000__xve_inst_executed_control_all__max,acmgt3__ext1000__xve_inst_executed_control_all__read);

      intel_perf_query_add_counter_float(query, 776, 80, percentage_max_float,acmgt3__ext1000__xve_pipe_alu0_and_alu1_active__read);

      intel_perf_query_add_counter_float(query, 777, 84, percentage_max_float,acmgt3__ext1000__xve_pipe_alu0_and_xmx_active__read);

      intel_perf_query_add_counter_float(query, 778, 88, percentage_max_float,acmgt3__ext1000__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 779, 92, percentage_max_float,acmgt3__ext1000__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 782, 96, percentage_max_float,acmgt3__ext1000__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 780, 100, percentage_max_float,acmgt3__ext1000__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 781, 104, percentage_max_float,acmgt3__ext1000__xve_inst_executed_control_all_utilization__read);

      intel_perf_query_add_counter_uint64(query, 1986, 112, acmgt3__ext1000__xve_active_cycles__max,acmgt3__ext1000__xve_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 1987, 120, acmgt3__ext1000__xve_stall_cycles__max,acmgt3__ext1000__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 1988, 128, acmgt3__ext1000__xve_threads_occupancy_cycles_all__max,acmgt3__ext1000__xve_threads_occupancy_cycles_all__read);

      intel_perf_query_add_counter_uint64(query, 1989, 136, acmgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max,acmgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 1990, 144, acmgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max,acmgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext1001_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Ext1001";
   query->symbol_name = "Ext1001";
   query->guid = "28009d66-9dae-4325-8339-06b19af58abd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00020010 },
         { .reg = 0x0000E558, .val = 0x00050030 },
         { .reg = 0x0000E658, .val = 0x00090060 },
         { .reg = 0x0000E758, .val = 0x00031011 },
         { .reg = 0x0000E45C, .val = 0x00051021 },
         { .reg = 0x0000E55C, .val = 0x00091061 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext1001__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext1001__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext1001__avg_gpu_core_frequency__max,acmgt3__ext1001__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 1991, 24, acmgt3__ext1001__xve_inst_executed_alu0_vs__max,acmgt3__ext1001__xve_inst_executed_alu0_vs__read);

      intel_perf_query_add_counter_uint64(query, 1992, 32, acmgt3__ext1001__xve_inst_executed_alu0_hs__max,acmgt3__ext1001__xve_inst_executed_alu0_hs__read);

      intel_perf_query_add_counter_uint64(query, 1993, 40, acmgt3__ext1001__xve_inst_executed_alu0_ds__max,acmgt3__ext1001__xve_inst_executed_alu0_ds__read);

      intel_perf_query_add_counter_uint64(query, 1994, 48, acmgt3__ext1001__xve_inst_executed_alu0_ps__max,acmgt3__ext1001__xve_inst_executed_alu0_ps__read);

      intel_perf_query_add_counter_uint64(query, 1995, 56, acmgt3__ext1001__xve_inst_executed_alu0_cs__max,acmgt3__ext1001__xve_inst_executed_alu0_cs__read);

      intel_perf_query_add_counter_uint64(query, 1996, 64, acmgt3__ext1001__xve_inst_executed_alu0_async_cs__max,acmgt3__ext1001__xve_inst_executed_alu0_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 1997, 72, acmgt3__ext1001__xve_inst_executed_alu1_vs__max,acmgt3__ext1001__xve_inst_executed_alu1_vs__read);

      intel_perf_query_add_counter_uint64(query, 1998, 80, acmgt3__ext1001__xve_inst_executed_alu1_hs__max,acmgt3__ext1001__xve_inst_executed_alu1_hs__read);

      intel_perf_query_add_counter_uint64(query, 1999, 88, acmgt3__ext1001__xve_inst_executed_alu1_ds__max,acmgt3__ext1001__xve_inst_executed_alu1_ds__read);

      intel_perf_query_add_counter_uint64(query, 2000, 96, acmgt3__ext1001__xve_inst_executed_alu1_ps__max,acmgt3__ext1001__xve_inst_executed_alu1_ps__read);

      intel_perf_query_add_counter_uint64(query, 2001, 104, acmgt3__ext1001__xve_inst_executed_alu1_cs__max,acmgt3__ext1001__xve_inst_executed_alu1_cs__read);

      intel_perf_query_add_counter_uint64(query, 2002, 112, acmgt3__ext1001__xve_inst_executed_alu1_async_cs__max,acmgt3__ext1001__xve_inst_executed_alu1_async_cs__read);

      intel_perf_query_add_counter_float(query, 2003, 120, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu0_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 2004, 124, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu0_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 2005, 128, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu0_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 2006, 132, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu0_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 2007, 136, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu0_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2008, 140, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu0_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2009, 144, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu1_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 2010, 148, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu1_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 2011, 152, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu1_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 2012, 156, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu1_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 2013, 160, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu1_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2014, 164, percentage_max_float,acmgt3__ext1001__xve_inst_executed_alu1_async_cs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext1002_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "Ext1002";
   query->symbol_name = "Ext1002";
   query->guid = "75ef7f1c-7b1f-4d06-b666-6e09a69fc16d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x000C10C0 },
         { .reg = 0x0000E558, .val = 0x000D00C2 },
         { .reg = 0x0000E658, .val = 0x000D20D1 },
         { .reg = 0x0000E758, .val = 0x000E10E0 },
         { .reg = 0x0000E45C, .val = 0x000000E2 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext1002__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext1002__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext1002__avg_gpu_core_frequency__max,acmgt3__ext1002__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 2015, 24, percentage_max_float,acmgt3__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 2016, 28, percentage_max_float,acmgt3__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 2017, 32, percentage_max_float,acmgt3__ext1002__xve_inst_executed_send_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 2018, 36, percentage_max_float,acmgt3__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 2019, 40, percentage_max_float,acmgt3__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 2020, 44, percentage_max_float,acmgt3__ext1002__xve_inst_executed_send_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 2021, 48, percentage_max_float,acmgt3__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2022, 52, percentage_max_float,acmgt3__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2023, 56, percentage_max_float,acmgt3__ext1002__xve_inst_executed_send_rt_ms_utilization__read);

      intel_perf_query_add_counter_uint64(query, 2024, 64, acmgt3__ext1002__xve_inst_executed_alu0_rt_ahs__max,acmgt3__ext1002__xve_inst_executed_alu0_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 2025, 72, acmgt3__ext1002__xve_inst_executed_alu1_rt_ahs__max,acmgt3__ext1002__xve_inst_executed_alu1_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 2026, 80, acmgt3__ext1002__xve_inst_executed_send_rt_ahs__max,acmgt3__ext1002__xve_inst_executed_send_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 2027, 88, acmgt3__ext1002__xve_inst_executed_alu0_rt_chs__max,acmgt3__ext1002__xve_inst_executed_alu0_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 2028, 96, acmgt3__ext1002__xve_inst_executed_alu1_rt_chs__max,acmgt3__ext1002__xve_inst_executed_alu1_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 2029, 104, acmgt3__ext1002__xve_inst_executed_send_rt_chs__max,acmgt3__ext1002__xve_inst_executed_send_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 2030, 112, acmgt3__ext1002__xve_inst_executed_alu0_rt_ms__max,acmgt3__ext1002__xve_inst_executed_alu0_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 2031, 120, acmgt3__ext1002__xve_inst_executed_alu1_rt_ms__max,acmgt3__ext1002__xve_inst_executed_alu1_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 2032, 128, acmgt3__ext1002__xve_inst_executed_send_rt_ms__max,acmgt3__ext1002__xve_inst_executed_send_rt_ms__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext1004_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1004";
   query->symbol_name = "Ext1004";
   query->guid = "4994b075-c659-48ab-b167-84cdb120c759";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00015005 },
         { .reg = 0x0000E558, .val = 0x000550A5 },
         { .reg = 0x0000E658, .val = 0x000250B5 },
         { .reg = 0x0000E758, .val = 0x00065035 },
         { .reg = 0x0000E45C, .val = 0x00000095 },
         { .reg = 0x0000E55C, .val = 0x000C5000 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext1004__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext1004__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext1004__avg_gpu_core_frequency__max,acmgt3__ext1004__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 765, 24, percentage_max_float,acmgt3__ext1004__xve_stall__read);

      intel_perf_query_add_counter_float(query, 2033, 28, percentage_max_float,acmgt3__ext1004__xve_stall_async_cs__read);

      intel_perf_query_add_counter_float(query, 2034, 32, percentage_max_float,acmgt3__ext1004__xve_stall_cs__read);

      intel_perf_query_add_counter_float(query, 2035, 36, percentage_max_float,acmgt3__ext1004__xve_stall_ds__read);

      intel_perf_query_add_counter_float(query, 2036, 40, percentage_max_float,acmgt3__ext1004__xve_stall_hs__read);

      intel_perf_query_add_counter_float(query, 2037, 44, percentage_max_float,acmgt3__ext1004__xve_stall_ms__read);

      intel_perf_query_add_counter_float(query, 2038, 48, percentage_max_float,acmgt3__ext1004__xve_stall_ps__read);

      intel_perf_query_add_counter_float(query, 2039, 52, percentage_max_float,acmgt3__ext1004__xve_stall_ts__read);

      intel_perf_query_add_counter_float(query, 2040, 56, percentage_max_float,acmgt3__ext1004__xve_stall_vs__read);

      intel_perf_query_add_counter_float(query, 2041, 60, percentage_max_float,acmgt3__ext1004__xve_stall_rt__read);

      intel_perf_query_add_counter_uint64(query, 1987, 64, acmgt3__ext1004__xve_stall_cycles__max,acmgt3__ext1004__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 2042, 72, acmgt3__ext1004__xve_stall_cycles_async_cs__max,acmgt3__ext1004__xve_stall_cycles_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 2043, 80, acmgt3__ext1004__xve_stall_cycles_cs__max,acmgt3__ext1004__xve_stall_cycles_cs__read);

      intel_perf_query_add_counter_uint64(query, 2044, 88, acmgt3__ext1004__xve_stall_cycles_ds__max,acmgt3__ext1004__xve_stall_cycles_ds__read);

      intel_perf_query_add_counter_uint64(query, 2045, 96, acmgt3__ext1004__xve_stall_cycles_hs__max,acmgt3__ext1004__xve_stall_cycles_hs__read);

      intel_perf_query_add_counter_uint64(query, 2046, 104, acmgt3__ext1004__xve_stall_cycles_ms__max,acmgt3__ext1004__xve_stall_cycles_ms__read);

      intel_perf_query_add_counter_uint64(query, 2047, 112, acmgt3__ext1004__xve_stall_cycles_ps__max,acmgt3__ext1004__xve_stall_cycles_ps__read);

      intel_perf_query_add_counter_uint64(query, 2048, 120, acmgt3__ext1004__xve_stall_cycles_ts__max,acmgt3__ext1004__xve_stall_cycles_ts__read);

      intel_perf_query_add_counter_uint64(query, 2049, 128, acmgt3__ext1004__xve_stall_cycles_vs__max,acmgt3__ext1004__xve_stall_cycles_vs__read);

      intel_perf_query_add_counter_uint64(query, 2050, 136, acmgt3__ext1004__xve_stall_cycles_rt__max,acmgt3__ext1004__xve_stall_cycles_rt__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext1005_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Ext1005";
   query->symbol_name = "Ext1005";
   query->guid = "b82ec6e0-2be7-4b30-a3db-21bd725849df";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x0000700B },
         { .reg = 0x0000E558, .val = 0x02000006 },
         { .reg = 0x0000E658, .val = 0x0000C00D },
         { .reg = 0x0000E758, .val = 0x0200200F },
         { .reg = 0x0000E45C, .val = 0x0000000E },
         { .reg = 0x0000E55C, .val = 0x00009001 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext1005__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext1005__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext1005__avg_gpu_core_frequency__max,acmgt3__ext1005__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 771, 24, acmgt3__ext1005__xve_inst_executed_alu0_all__max,acmgt3__ext1005__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 2051, 32, acmgt3__ext1005__xve_inst_executed_fp16__max,acmgt3__ext1005__xve_inst_executed_fp16__read);

      intel_perf_query_add_counter_uint64(query, 2052, 40, acmgt3__ext1005__xve_inst_executed_fp32__max,acmgt3__ext1005__xve_inst_executed_fp32__read);

      intel_perf_query_add_counter_uint64(query, 2053, 48, acmgt3__ext1005__xve_inst_executed_fp64__max,acmgt3__ext1005__xve_inst_executed_fp64__read);

      intel_perf_query_add_counter_uint64(query, 772, 56, acmgt3__ext1005__xve_inst_executed_alu1_all__max,acmgt3__ext1005__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 2054, 64, acmgt3__ext1005__xve_inst_executed_int16__max,acmgt3__ext1005__xve_inst_executed_int16__read);

      intel_perf_query_add_counter_uint64(query, 2055, 72, acmgt3__ext1005__xve_inst_executed_int32__max,acmgt3__ext1005__xve_inst_executed_int32__read);

      intel_perf_query_add_counter_uint64(query, 2056, 80, acmgt3__ext1005__xve_inst_executed_math__max,acmgt3__ext1005__xve_inst_executed_math__read);

      intel_perf_query_add_counter_uint64(query, 773, 88, acmgt3__ext1005__xve_inst_executed_xmx_all__max,acmgt3__ext1005__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 2057, 96, acmgt3__ext1005__xve_inst_executed_xmx_bf16__max,acmgt3__ext1005__xve_inst_executed_xmx_bf16__read);

      intel_perf_query_add_counter_uint64(query, 2058, 104, acmgt3__ext1005__xve_inst_executed_xmx_fp16__max,acmgt3__ext1005__xve_inst_executed_xmx_fp16__read);

      intel_perf_query_add_counter_uint64(query, 2059, 112, acmgt3__ext1005__xve_inst_executed_xmx_int8__max,acmgt3__ext1005__xve_inst_executed_xmx_int8__read);

      intel_perf_query_add_counter_float(query, 778, 120, percentage_max_float,acmgt3__ext1005__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2060, 124, percentage_max_float,acmgt3__ext1005__xve_inst_executed_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 2061, 128, percentage_max_float,acmgt3__ext1005__xve_inst_executed_fp32_utilization__read);

      intel_perf_query_add_counter_float(query, 2062, 132, percentage_max_float,acmgt3__ext1005__xve_inst_executed_fp64_utilization__read);

      intel_perf_query_add_counter_float(query, 779, 136, percentage_max_float,acmgt3__ext1005__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2063, 140, percentage_max_float,acmgt3__ext1005__xve_inst_executed_int16_utilization__read);

      intel_perf_query_add_counter_float(query, 2064, 144, percentage_max_float,acmgt3__ext1005__xve_inst_executed_int32_utilization__read);

      intel_perf_query_add_counter_float(query, 2065, 148, percentage_max_float,acmgt3__ext1005__xve_inst_executed_math_utilization__read);

      intel_perf_query_add_counter_float(query, 782, 152, percentage_max_float,acmgt3__ext1005__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2066, 156, percentage_max_float,acmgt3__ext1005__xve_inst_executed_xmx_bf16_utilization__read);

      intel_perf_query_add_counter_float(query, 2067, 160, percentage_max_float,acmgt3__ext1005__xve_inst_executed_xmx_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 2068, 164, percentage_max_float,acmgt3__ext1005__xve_inst_executed_xmx_int8_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext1006_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1006";
   query->symbol_name = "Ext1006";
   query->guid = "a864bceb-7b38-4248-9fc8-0f0f7b8c6426";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x000A2012 },
         { .reg = 0x0000E558, .val = 0x000B2052 },
         { .reg = 0x0000E658, .val = 0x00042022 },
         { .reg = 0x0000E758, .val = 0x00062032 },
         { .reg = 0x0000E45C, .val = 0x00002092 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext1006__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext1006__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext1006__avg_gpu_core_frequency__max,acmgt3__ext1006__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 774, 24, acmgt3__ext1006__xve_inst_executed_send_all__max,acmgt3__ext1006__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 2069, 32, acmgt3__ext1006__xve_inst_executed_send_async_cs__max,acmgt3__ext1006__xve_inst_executed_send_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 2070, 40, acmgt3__ext1006__xve_inst_executed_send_cs__max,acmgt3__ext1006__xve_inst_executed_send_cs__read);

      intel_perf_query_add_counter_uint64(query, 2071, 48, acmgt3__ext1006__xve_inst_executed_send_ds__max,acmgt3__ext1006__xve_inst_executed_send_ds__read);

      intel_perf_query_add_counter_uint64(query, 2072, 56, acmgt3__ext1006__xve_inst_executed_send_gs__max,acmgt3__ext1006__xve_inst_executed_send_gs__read);

      intel_perf_query_add_counter_uint64(query, 2073, 64, acmgt3__ext1006__xve_inst_executed_send_hs__max,acmgt3__ext1006__xve_inst_executed_send_hs__read);

      intel_perf_query_add_counter_uint64(query, 2074, 72, acmgt3__ext1006__xve_inst_executed_send_ms__max,acmgt3__ext1006__xve_inst_executed_send_ms__read);

      intel_perf_query_add_counter_uint64(query, 2075, 80, acmgt3__ext1006__xve_inst_executed_send_ps__max,acmgt3__ext1006__xve_inst_executed_send_ps__read);

      intel_perf_query_add_counter_uint64(query, 2076, 88, acmgt3__ext1006__xve_inst_executed_send_ts__max,acmgt3__ext1006__xve_inst_executed_send_ts__read);

      intel_perf_query_add_counter_uint64(query, 2077, 96, acmgt3__ext1006__xve_inst_executed_send_vs__max,acmgt3__ext1006__xve_inst_executed_send_vs__read);

      intel_perf_query_add_counter_float(query, 780, 104, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 2078, 108, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2079, 112, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 2080, 116, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 2081, 120, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 2082, 124, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 2083, 128, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2084, 132, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 2085, 136, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 2086, 140, percentage_max_float,acmgt3__ext1006__xve_inst_executed_send_vs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext1007_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 17);

   query->name = "Ext1007";
   query->symbol_name = "Ext1007";
   query->guid = "361fc5ef-d568-4a9b-8ca2-d34707d10575";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00045000 },
         { .reg = 0x0000E558, .val = 0x00040041 },
         { .reg = 0x0000E658, .val = 0x000B10A1 },
         { .reg = 0x0000E758, .val = 0x000B00A0 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext1007__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext1007__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext1007__avg_gpu_core_frequency__max,acmgt3__ext1007__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 2087, 24, percentage_max_float,acmgt3__ext1007__xve_stall_gs__read);

      intel_perf_query_add_counter_uint64(query, 2088, 32, acmgt3__ext1007__xve_inst_executed_alu0_gs__max,acmgt3__ext1007__xve_inst_executed_alu0_gs__read);

      intel_perf_query_add_counter_uint64(query, 2089, 40, acmgt3__ext1007__xve_inst_executed_alu1_gs__max,acmgt3__ext1007__xve_inst_executed_alu1_gs__read);

      intel_perf_query_add_counter_uint64(query, 2090, 48, acmgt3__ext1007__xve_stall_cycles_gs__max,acmgt3__ext1007__xve_stall_cycles_gs__read);

      intel_perf_query_add_counter_uint64(query, 2091, 56, acmgt3__ext1007__xve_inst_executed_alu0_ms__max,acmgt3__ext1007__xve_inst_executed_alu0_ms__read);

      intel_perf_query_add_counter_uint64(query, 2092, 64, acmgt3__ext1007__xve_inst_executed_alu0_ts__max,acmgt3__ext1007__xve_inst_executed_alu0_ts__read);

      intel_perf_query_add_counter_uint64(query, 2093, 72, acmgt3__ext1007__xve_inst_executed_alu1_ms__max,acmgt3__ext1007__xve_inst_executed_alu1_ms__read);

      intel_perf_query_add_counter_uint64(query, 2094, 80, acmgt3__ext1007__xve_inst_executed_alu1_ts__max,acmgt3__ext1007__xve_inst_executed_alu1_ts__read);

      intel_perf_query_add_counter_float(query, 2095, 88, percentage_max_float,acmgt3__ext1007__xve_inst_executed_alu0_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 2096, 92, percentage_max_float,acmgt3__ext1007__xve_inst_executed_alu1_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 2097, 96, percentage_max_float,acmgt3__ext1007__xve_inst_executed_alu0_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2098, 100, percentage_max_float,acmgt3__ext1007__xve_inst_executed_alu0_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 2099, 104, percentage_max_float,acmgt3__ext1007__xve_inst_executed_alu1_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 2100, 108, percentage_max_float,acmgt3__ext1007__xve_inst_executed_alu1_ts_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
acmgt3_register_ext1010_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext1010";
   query->symbol_name = "Ext1010";
   query->guid = "b5663ed9-0a8f-4a22-a3d4-a1ab08fad60f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,acmgt3__ext1010__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,acmgt3__ext1010__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, acmgt3__ext1010__avg_gpu_core_frequency__max,acmgt3__ext1010__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 2101, 24, NULL,acmgt3__ext1010__sampler_2_x2_read__read);

      intel_perf_query_add_counter_uint64(query, 2102, 32, NULL,acmgt3__ext1010__pixel_write__read);

      intel_perf_query_add_counter_uint64(query, 2103, 40, NULL,acmgt3__ext1010__pixel_blend__read);

      intel_perf_query_add_counter_uint64(query, 2104, 48, NULL,acmgt3__ext1010__rasterizer_sample_output__read);

      intel_perf_query_add_counter_uint64(query, 2105, 56, NULL,acmgt3__ext1010__postps_depth_stencil_alpha_test_fail__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_acmgt3(struct intel_perf_config *perf)
{
   acmgt3_register_render_basic_counter_query(perf);
   acmgt3_register_compute_basic_counter_query(perf);
   acmgt3_register_async_compute_counter_query(perf);
   acmgt3_register_xve_activity1_counter_query(perf);
   acmgt3_register_gpu_busyness_counter_query(perf);
   acmgt3_register_test_oa_counter_query(perf);
   acmgt3_register_hdc_and_sf__slice01_counter_query(perf);
   acmgt3_register_hdc_and_sf__slice23_counter_query(perf);
   acmgt3_register_hdc_and_sf__slice45_counter_query(perf);
   acmgt3_register_hdc_and_sf__slice67_counter_query(perf);
   acmgt3_register_hdc_and_sf1_counter_query(perf);
   acmgt3_register_l3__slice01_counter_query(perf);
   acmgt3_register_l3__slice23_counter_query(perf);
   acmgt3_register_l3__slice45_counter_query(perf);
   acmgt3_register_l3__slice67_counter_query(perf);
   acmgt3_register_rasterizer_and_pixel_backend1_counter_query(perf);
   acmgt3_register_rasterizer_and_pixel_backend2_counter_query(perf);
   acmgt3_register_rasterizer_and_pixel_backend3_counter_query(perf);
   acmgt3_register_rasterizer_and_pixel_backend4_counter_query(perf);
   acmgt3_register_rasterizer_and_pixel_backend5_counter_query(perf);
   acmgt3_register_render_pipe_profile__slice0_counter_query(perf);
   acmgt3_register_render_pipe_profile__slice1_counter_query(perf);
   acmgt3_register_render_pipe_profile__slice2_counter_query(perf);
   acmgt3_register_render_pipe_profile__slice3_counter_query(perf);
   acmgt3_register_render_pipe_profile__slice4_counter_query(perf);
   acmgt3_register_render_pipe_profile__slice5_counter_query(perf);
   acmgt3_register_render_pipe_profile__slice6_counter_query(perf);
   acmgt3_register_render_pipe_profile__slice7_counter_query(perf);
   acmgt3_register_sampler__slice01_counter_query(perf);
   acmgt3_register_sampler__slice23_counter_query(perf);
   acmgt3_register_sampler__slice45_counter_query(perf);
   acmgt3_register_sampler__slice67_counter_query(perf);
   acmgt3_register_tdl__slice01_1_counter_query(perf);
   acmgt3_register_tdl__slice01_2_counter_query(perf);
   acmgt3_register_tdl__slice01_3_counter_query(perf);
   acmgt3_register_tdl__slice01_4_counter_query(perf);
   acmgt3_register_tdl__slice23_1_counter_query(perf);
   acmgt3_register_tdl__slice23_2_counter_query(perf);
   acmgt3_register_tdl__slice23_3_counter_query(perf);
   acmgt3_register_tdl__slice23_4_counter_query(perf);
   acmgt3_register_tdl__slice45_1_counter_query(perf);
   acmgt3_register_tdl__slice45_2_counter_query(perf);
   acmgt3_register_tdl__slice45_3_counter_query(perf);
   acmgt3_register_tdl__slice45_4_counter_query(perf);
   acmgt3_register_tdl__slice67_1_counter_query(perf);
   acmgt3_register_tdl__slice67_2_counter_query(perf);
   acmgt3_register_tdl__slice67_3_counter_query(perf);
   acmgt3_register_tdl__slice67_4_counter_query(perf);
   acmgt3_register_compute_overview_counter_query(perf);
   acmgt3_register_l1_profile_reads__xe_core0_counter_query(perf);
   acmgt3_register_l1_profile_reads__xe_core3_counter_query(perf);
   acmgt3_register_l1_profile_slm_bank_conflicts__xe_core0_counter_query(perf);
   acmgt3_register_l1_profile_slm_bank_conflicts__xe_core3_counter_query(perf);
   acmgt3_register_l1_profile_writes__xe_core0_counter_query(perf);
   acmgt3_register_l1_profile_writes__xe_core3_counter_query(perf);
   acmgt3_register_dataport_reads_counter_query(perf);
   acmgt3_register_dataport_writes_counter_query(perf);
   acmgt3_register_ext1_counter_query(perf);
   acmgt3_register_ext2_counter_query(perf);
   acmgt3_register_ext3_counter_query(perf);
   acmgt3_register_ext4_counter_query(perf);
   acmgt3_register_ext5_counter_query(perf);
   acmgt3_register_ext6_counter_query(perf);
   acmgt3_register_ext7_counter_query(perf);
   acmgt3_register_ext8_counter_query(perf);
   acmgt3_register_ext9_counter_query(perf);
   acmgt3_register_ext10_counter_query(perf);
   acmgt3_register_ext11_counter_query(perf);
   acmgt3_register_ext12_counter_query(perf);
   acmgt3_register_ext13_counter_query(perf);
   acmgt3_register_ext14_counter_query(perf);
   acmgt3_register_ext15_counter_query(perf);
   acmgt3_register_ext16_counter_query(perf);
   acmgt3_register_ext17_counter_query(perf);
   acmgt3_register_ext18_counter_query(perf);
   acmgt3_register_ext19_counter_query(perf);
   acmgt3_register_ext20_counter_query(perf);
   acmgt3_register_ext21_counter_query(perf);
   acmgt3_register_ext22_counter_query(perf);
   acmgt3_register_ext23_counter_query(perf);
   acmgt3_register_ext24_counter_query(perf);
   acmgt3_register_ext27_counter_query(perf);
   acmgt3_register_ext28_counter_query(perf);
   acmgt3_register_ext29_counter_query(perf);
   acmgt3_register_ext30_counter_query(perf);
   acmgt3_register_ext31_counter_query(perf);
   acmgt3_register_ext32_counter_query(perf);
   acmgt3_register_ext33_counter_query(perf);
   acmgt3_register_ext34_counter_query(perf);
   acmgt3_register_ext35_counter_query(perf);
   acmgt3_register_ext36_counter_query(perf);
   acmgt3_register_ext37_counter_query(perf);
   acmgt3_register_ext38_counter_query(perf);
   acmgt3_register_ext39_counter_query(perf);
   acmgt3_register_ext40_counter_query(perf);
   acmgt3_register_ext41_counter_query(perf);
   acmgt3_register_ext42_counter_query(perf);
   acmgt3_register_ext43_counter_query(perf);
   acmgt3_register_ext44_counter_query(perf);
   acmgt3_register_ext45_counter_query(perf);
   acmgt3_register_ext46_counter_query(perf);
   acmgt3_register_ext47_counter_query(perf);
   acmgt3_register_ext48_counter_query(perf);
   acmgt3_register_ext49_counter_query(perf);
   acmgt3_register_ext50_counter_query(perf);
   acmgt3_register_ext51_counter_query(perf);
   acmgt3_register_ext52_counter_query(perf);
   acmgt3_register_ext53_counter_query(perf);
   acmgt3_register_ext54_counter_query(perf);
   acmgt3_register_ext55_counter_query(perf);
   acmgt3_register_ext56_counter_query(perf);
   acmgt3_register_ext57_counter_query(perf);
   acmgt3_register_ext58_counter_query(perf);
   acmgt3_register_ext59_counter_query(perf);
   acmgt3_register_ext60_counter_query(perf);
   acmgt3_register_ext61_counter_query(perf);
   acmgt3_register_ext62_counter_query(perf);
   acmgt3_register_ext63_counter_query(perf);
   acmgt3_register_ext64_counter_query(perf);
   acmgt3_register_ext65_counter_query(perf);
   acmgt3_register_ext66_counter_query(perf);
   acmgt3_register_ext67_counter_query(perf);
   acmgt3_register_ext68_counter_query(perf);
   acmgt3_register_ext69_counter_query(perf);
   acmgt3_register_ext70_counter_query(perf);
   acmgt3_register_ext71_counter_query(perf);
   acmgt3_register_ext72_counter_query(perf);
   acmgt3_register_ext73_counter_query(perf);
   acmgt3_register_ext74_counter_query(perf);
   acmgt3_register_ext75_counter_query(perf);
   acmgt3_register_ext76_counter_query(perf);
   acmgt3_register_ext77_counter_query(perf);
   acmgt3_register_ext78_counter_query(perf);
   acmgt3_register_ext79_counter_query(perf);
   acmgt3_register_ext80_counter_query(perf);
   acmgt3_register_ext81_counter_query(perf);
   acmgt3_register_ext82_counter_query(perf);
   acmgt3_register_ext83_counter_query(perf);
   acmgt3_register_ext84_counter_query(perf);
   acmgt3_register_ext85_counter_query(perf);
   acmgt3_register_ext86_counter_query(perf);
   acmgt3_register_ext87_counter_query(perf);
   acmgt3_register_ext88_counter_query(perf);
   acmgt3_register_ext89_counter_query(perf);
   acmgt3_register_ext90_counter_query(perf);
   acmgt3_register_ext91_counter_query(perf);
   acmgt3_register_ext92_counter_query(perf);
   acmgt3_register_ext93_counter_query(perf);
   acmgt3_register_ext94_counter_query(perf);
   acmgt3_register_ext95_counter_query(perf);
   acmgt3_register_ext96_counter_query(perf);
   acmgt3_register_ext97_counter_query(perf);
   acmgt3_register_ext98_counter_query(perf);
   acmgt3_register_ext99_counter_query(perf);
   acmgt3_register_ext100_counter_query(perf);
   acmgt3_register_ext101_counter_query(perf);
   acmgt3_register_ext102_counter_query(perf);
   acmgt3_register_ext103_counter_query(perf);
   acmgt3_register_ext104_counter_query(perf);
   acmgt3_register_ext105_counter_query(perf);
   acmgt3_register_ext106_counter_query(perf);
   acmgt3_register_ext107_counter_query(perf);
   acmgt3_register_ext108_counter_query(perf);
   acmgt3_register_ext109_counter_query(perf);
   acmgt3_register_ext110_counter_query(perf);
   acmgt3_register_ext111_counter_query(perf);
   acmgt3_register_ext112_counter_query(perf);
   acmgt3_register_ext113_counter_query(perf);
   acmgt3_register_ext114_counter_query(perf);
   acmgt3_register_ext115_counter_query(perf);
   acmgt3_register_ext116_counter_query(perf);
   acmgt3_register_ext117_counter_query(perf);
   acmgt3_register_ext118_counter_query(perf);
   acmgt3_register_ext119_counter_query(perf);
   acmgt3_register_ext120_counter_query(perf);
   acmgt3_register_ext121_counter_query(perf);
   acmgt3_register_ext122_counter_query(perf);
   acmgt3_register_ext123_counter_query(perf);
   acmgt3_register_ext124_counter_query(perf);
   acmgt3_register_ext125_counter_query(perf);
   acmgt3_register_ext126_counter_query(perf);
   acmgt3_register_ext127_counter_query(perf);
   acmgt3_register_ext128_counter_query(perf);
   acmgt3_register_ext129_counter_query(perf);
   acmgt3_register_ext130_counter_query(perf);
   acmgt3_register_ext131_counter_query(perf);
   acmgt3_register_ext132_counter_query(perf);
   acmgt3_register_ext133_counter_query(perf);
   acmgt3_register_ext134_counter_query(perf);
   acmgt3_register_ext135_counter_query(perf);
   acmgt3_register_ext136_counter_query(perf);
   acmgt3_register_ext137_counter_query(perf);
   acmgt3_register_ext138_counter_query(perf);
   acmgt3_register_ext139_counter_query(perf);
   acmgt3_register_ext140_counter_query(perf);
   acmgt3_register_ext141_counter_query(perf);
   acmgt3_register_ext142_counter_query(perf);
   acmgt3_register_ext143_counter_query(perf);
   acmgt3_register_ext144_counter_query(perf);
   acmgt3_register_ext145_counter_query(perf);
   acmgt3_register_ext146_counter_query(perf);
   acmgt3_register_ext147_counter_query(perf);
   acmgt3_register_ext148_counter_query(perf);
   acmgt3_register_ext149_counter_query(perf);
   acmgt3_register_ext150_counter_query(perf);
   acmgt3_register_ext151_counter_query(perf);
   acmgt3_register_ext152_counter_query(perf);
   acmgt3_register_ext153_counter_query(perf);
   acmgt3_register_ext154_counter_query(perf);
   acmgt3_register_ext155_counter_query(perf);
   acmgt3_register_ext156_counter_query(perf);
   acmgt3_register_ext157_counter_query(perf);
   acmgt3_register_ext158_counter_query(perf);
   acmgt3_register_ext159_counter_query(perf);
   acmgt3_register_ext160_counter_query(perf);
   acmgt3_register_ext161_counter_query(perf);
   acmgt3_register_ext162_counter_query(perf);
   acmgt3_register_ext163_counter_query(perf);
   acmgt3_register_ext164_counter_query(perf);
   acmgt3_register_ext165_counter_query(perf);
   acmgt3_register_ext166_counter_query(perf);
   acmgt3_register_ext167_counter_query(perf);
   acmgt3_register_ext168_counter_query(perf);
   acmgt3_register_ext169_counter_query(perf);
   acmgt3_register_ext170_counter_query(perf);
   acmgt3_register_ext171_counter_query(perf);
   acmgt3_register_ext172_counter_query(perf);
   acmgt3_register_ext173_counter_query(perf);
   acmgt3_register_ext174_counter_query(perf);
   acmgt3_register_ext175_counter_query(perf);
   acmgt3_register_ext176_counter_query(perf);
   acmgt3_register_ext177_counter_query(perf);
   acmgt3_register_ext178_counter_query(perf);
   acmgt3_register_ext179_counter_query(perf);
   acmgt3_register_ext180_counter_query(perf);
   acmgt3_register_ext181_counter_query(perf);
   acmgt3_register_ext182_counter_query(perf);
   acmgt3_register_ext183_counter_query(perf);
   acmgt3_register_ext184_counter_query(perf);
   acmgt3_register_ext185_counter_query(perf);
   acmgt3_register_ext186_counter_query(perf);
   acmgt3_register_ext187_counter_query(perf);
   acmgt3_register_ext188_counter_query(perf);
   acmgt3_register_ext189_counter_query(perf);
   acmgt3_register_ext190_counter_query(perf);
   acmgt3_register_ext191_counter_query(perf);
   acmgt3_register_ext192_counter_query(perf);
   acmgt3_register_ext193_counter_query(perf);
   acmgt3_register_ext194_counter_query(perf);
   acmgt3_register_ext195_counter_query(perf);
   acmgt3_register_ext196_counter_query(perf);
   acmgt3_register_ext197_counter_query(perf);
   acmgt3_register_ext198_counter_query(perf);
   acmgt3_register_ext199_counter_query(perf);
   acmgt3_register_ext200_counter_query(perf);
   acmgt3_register_ext201_counter_query(perf);
   acmgt3_register_ext202_counter_query(perf);
   acmgt3_register_ext203_counter_query(perf);
   acmgt3_register_ext204_counter_query(perf);
   acmgt3_register_ext205_counter_query(perf);
   acmgt3_register_ext206_counter_query(perf);
   acmgt3_register_ext207_counter_query(perf);
   acmgt3_register_ext208_counter_query(perf);
   acmgt3_register_ext209_counter_query(perf);
   acmgt3_register_ext210_counter_query(perf);
   acmgt3_register_ext211_counter_query(perf);
   acmgt3_register_ext212_counter_query(perf);
   acmgt3_register_ext213_counter_query(perf);
   acmgt3_register_ext214_counter_query(perf);
   acmgt3_register_ext215_counter_query(perf);
   acmgt3_register_ext216_counter_query(perf);
   acmgt3_register_ext217_counter_query(perf);
   acmgt3_register_ext218_counter_query(perf);
   acmgt3_register_ext219_counter_query(perf);
   acmgt3_register_ext220_counter_query(perf);
   acmgt3_register_ext221_counter_query(perf);
   acmgt3_register_ext222_counter_query(perf);
   acmgt3_register_ext223_counter_query(perf);
   acmgt3_register_ext224_counter_query(perf);
   acmgt3_register_ext225_counter_query(perf);
   acmgt3_register_ext226_counter_query(perf);
   acmgt3_register_ext227_counter_query(perf);
   acmgt3_register_ext228_counter_query(perf);
   acmgt3_register_ext229_counter_query(perf);
   acmgt3_register_ext230_counter_query(perf);
   acmgt3_register_ext231_counter_query(perf);
   acmgt3_register_ext232_counter_query(perf);
   acmgt3_register_ext233_counter_query(perf);
   acmgt3_register_ext234_counter_query(perf);
   acmgt3_register_ext235_counter_query(perf);
   acmgt3_register_ext236_counter_query(perf);
   acmgt3_register_ext237_counter_query(perf);
   acmgt3_register_ext238_counter_query(perf);
   acmgt3_register_ext239_counter_query(perf);
   acmgt3_register_ext240_counter_query(perf);
   acmgt3_register_ext241_counter_query(perf);
   acmgt3_register_ext242_counter_query(perf);
   acmgt3_register_ext243_counter_query(perf);
   acmgt3_register_ext244_counter_query(perf);
   acmgt3_register_ext245_counter_query(perf);
   acmgt3_register_ext246_counter_query(perf);
   acmgt3_register_ext247_counter_query(perf);
   acmgt3_register_ext248_counter_query(perf);
   acmgt3_register_ext249_counter_query(perf);
   acmgt3_register_ext250_counter_query(perf);
   acmgt3_register_ext251_counter_query(perf);
   acmgt3_register_ext252_counter_query(perf);
   acmgt3_register_ext253_counter_query(perf);
   acmgt3_register_ext254_counter_query(perf);
   acmgt3_register_ext255_counter_query(perf);
   acmgt3_register_ext256_counter_query(perf);
   acmgt3_register_ext257_counter_query(perf);
   acmgt3_register_ext258_counter_query(perf);
   acmgt3_register_ext259_counter_query(perf);
   acmgt3_register_ext260_counter_query(perf);
   acmgt3_register_ext261_counter_query(perf);
   acmgt3_register_ext262_counter_query(perf);
   acmgt3_register_ext263_counter_query(perf);
   acmgt3_register_ext264_counter_query(perf);
   acmgt3_register_ext265_counter_query(perf);
   acmgt3_register_ext266_counter_query(perf);
   acmgt3_register_ext267_counter_query(perf);
   acmgt3_register_ext268_counter_query(perf);
   acmgt3_register_ext269_counter_query(perf);
   acmgt3_register_ext270_counter_query(perf);
   acmgt3_register_ext271_counter_query(perf);
   acmgt3_register_ext272_counter_query(perf);
   acmgt3_register_ext273_counter_query(perf);
   acmgt3_register_ext274_counter_query(perf);
   acmgt3_register_ext275_counter_query(perf);
   acmgt3_register_ext276_counter_query(perf);
   acmgt3_register_ext277_counter_query(perf);
   acmgt3_register_ext278_counter_query(perf);
   acmgt3_register_ext279_counter_query(perf);
   acmgt3_register_ext280_counter_query(perf);
   acmgt3_register_ext281_counter_query(perf);
   acmgt3_register_ext282_counter_query(perf);
   acmgt3_register_ext283_counter_query(perf);
   acmgt3_register_ext284_counter_query(perf);
   acmgt3_register_ext285_counter_query(perf);
   acmgt3_register_ext286_counter_query(perf);
   acmgt3_register_ext288_counter_query(perf);
   acmgt3_register_ext289_counter_query(perf);
   acmgt3_register_ext290_counter_query(perf);
   acmgt3_register_ext291_counter_query(perf);
   acmgt3_register_ext292_counter_query(perf);
   acmgt3_register_ext293_counter_query(perf);
   acmgt3_register_ext294_counter_query(perf);
   acmgt3_register_ext295_counter_query(perf);
   acmgt3_register_ext296_counter_query(perf);
   acmgt3_register_ext297_counter_query(perf);
   acmgt3_register_ext298_counter_query(perf);
   acmgt3_register_ext299_counter_query(perf);
   acmgt3_register_ext300_counter_query(perf);
   acmgt3_register_ext301_counter_query(perf);
   acmgt3_register_ext302_counter_query(perf);
   acmgt3_register_ext303_counter_query(perf);
   acmgt3_register_ext304_counter_query(perf);
   acmgt3_register_ext305_counter_query(perf);
   acmgt3_register_ext306_counter_query(perf);
   acmgt3_register_ext307_counter_query(perf);
   acmgt3_register_ext308_counter_query(perf);
   acmgt3_register_ext309_counter_query(perf);
   acmgt3_register_ext310_counter_query(perf);
   acmgt3_register_ext311_counter_query(perf);
   acmgt3_register_ext312_counter_query(perf);
   acmgt3_register_ext313_counter_query(perf);
   acmgt3_register_ext314_counter_query(perf);
   acmgt3_register_ext315_counter_query(perf);
   acmgt3_register_ext316_counter_query(perf);
   acmgt3_register_ext317_counter_query(perf);
   acmgt3_register_ext318_counter_query(perf);
   acmgt3_register_ext319_counter_query(perf);
   acmgt3_register_ext320_counter_query(perf);
   acmgt3_register_ext321_counter_query(perf);
   acmgt3_register_ext322_counter_query(perf);
   acmgt3_register_ext323_counter_query(perf);
   acmgt3_register_ext324_counter_query(perf);
   acmgt3_register_ext325_counter_query(perf);
   acmgt3_register_ext326_counter_query(perf);
   acmgt3_register_ext327_counter_query(perf);
   acmgt3_register_ext328_counter_query(perf);
   acmgt3_register_ext329_counter_query(perf);
   acmgt3_register_ext330_counter_query(perf);
   acmgt3_register_ext331_counter_query(perf);
   acmgt3_register_ext332_counter_query(perf);
   acmgt3_register_ext333_counter_query(perf);
   acmgt3_register_ext334_counter_query(perf);
   acmgt3_register_ext335_counter_query(perf);
   acmgt3_register_ext342_counter_query(perf);
   acmgt3_register_ext343_counter_query(perf);
   acmgt3_register_ext344_counter_query(perf);
   acmgt3_register_ext345_counter_query(perf);
   acmgt3_register_ext346_counter_query(perf);
   acmgt3_register_ext347_counter_query(perf);
   acmgt3_register_ext348_counter_query(perf);
   acmgt3_register_ext349_counter_query(perf);
   acmgt3_register_ext350_counter_query(perf);
   acmgt3_register_ext351_counter_query(perf);
   acmgt3_register_ext352_counter_query(perf);
   acmgt3_register_ext353_counter_query(perf);
   acmgt3_register_ext354_counter_query(perf);
   acmgt3_register_ext355_counter_query(perf);
   acmgt3_register_ext356_counter_query(perf);
   acmgt3_register_ext357_counter_query(perf);
   acmgt3_register_ext358_counter_query(perf);
   acmgt3_register_ext359_counter_query(perf);
   acmgt3_register_ext360_counter_query(perf);
   acmgt3_register_ext361_counter_query(perf);
   acmgt3_register_ext362_counter_query(perf);
   acmgt3_register_ext363_counter_query(perf);
   acmgt3_register_ext364_counter_query(perf);
   acmgt3_register_ext365_counter_query(perf);
   acmgt3_register_ext366_counter_query(perf);
   acmgt3_register_ext367_counter_query(perf);
   acmgt3_register_ext368_counter_query(perf);
   acmgt3_register_ext369_counter_query(perf);
   acmgt3_register_ext370_counter_query(perf);
   acmgt3_register_ext371_counter_query(perf);
   acmgt3_register_ext372_counter_query(perf);
   acmgt3_register_ext373_counter_query(perf);
   acmgt3_register_ext374_counter_query(perf);
   acmgt3_register_ext375_counter_query(perf);
   acmgt3_register_ext376_counter_query(perf);
   acmgt3_register_ext377_counter_query(perf);
   acmgt3_register_ext378_counter_query(perf);
   acmgt3_register_ext379_counter_query(perf);
   acmgt3_register_ext380_counter_query(perf);
   acmgt3_register_ext381_counter_query(perf);
   acmgt3_register_ext382_counter_query(perf);
   acmgt3_register_ext383_counter_query(perf);
   acmgt3_register_ext384_counter_query(perf);
   acmgt3_register_ext385_counter_query(perf);
   acmgt3_register_ext386_counter_query(perf);
   acmgt3_register_ext387_counter_query(perf);
   acmgt3_register_ext388_counter_query(perf);
   acmgt3_register_ext389_counter_query(perf);
   acmgt3_register_ext390_counter_query(perf);
   acmgt3_register_ext391_counter_query(perf);
   acmgt3_register_ext392_counter_query(perf);
   acmgt3_register_ext393_counter_query(perf);
   acmgt3_register_ext394_counter_query(perf);
   acmgt3_register_ext395_counter_query(perf);
   acmgt3_register_ext396_counter_query(perf);
   acmgt3_register_ext397_counter_query(perf);
   acmgt3_register_ext398_counter_query(perf);
   acmgt3_register_ext399_counter_query(perf);
   acmgt3_register_ext400_counter_query(perf);
   acmgt3_register_ext401_counter_query(perf);
   acmgt3_register_ext402_counter_query(perf);
   acmgt3_register_ext403_counter_query(perf);
   acmgt3_register_ext404_counter_query(perf);
   acmgt3_register_ext405_counter_query(perf);
   acmgt3_register_ext406_counter_query(perf);
   acmgt3_register_ext407_counter_query(perf);
   acmgt3_register_ext408_counter_query(perf);
   acmgt3_register_ext409_counter_query(perf);
   acmgt3_register_ext410_counter_query(perf);
   acmgt3_register_ext411_counter_query(perf);
   acmgt3_register_ext412_counter_query(perf);
   acmgt3_register_ext413_counter_query(perf);
   acmgt3_register_ext414_counter_query(perf);
   acmgt3_register_ext415_counter_query(perf);
   acmgt3_register_ext416_counter_query(perf);
   acmgt3_register_ext417_counter_query(perf);
   acmgt3_register_ext418_counter_query(perf);
   acmgt3_register_ext419_counter_query(perf);
   acmgt3_register_ext420_counter_query(perf);
   acmgt3_register_ext421_counter_query(perf);
   acmgt3_register_ext422_counter_query(perf);
   acmgt3_register_ext423_counter_query(perf);
   acmgt3_register_ext424_counter_query(perf);
   acmgt3_register_ext425_counter_query(perf);
   acmgt3_register_ext426_counter_query(perf);
   acmgt3_register_ext427_counter_query(perf);
   acmgt3_register_ext428_counter_query(perf);
   acmgt3_register_ext429_counter_query(perf);
   acmgt3_register_ext430_counter_query(perf);
   acmgt3_register_ext431_counter_query(perf);
   acmgt3_register_ext432_counter_query(perf);
   acmgt3_register_ext433_counter_query(perf);
   acmgt3_register_ext434_counter_query(perf);
   acmgt3_register_ext435_counter_query(perf);
   acmgt3_register_ext436_counter_query(perf);
   acmgt3_register_ext437_counter_query(perf);
   acmgt3_register_ext438_counter_query(perf);
   acmgt3_register_ext439_counter_query(perf);
   acmgt3_register_ext440_counter_query(perf);
   acmgt3_register_ext441_counter_query(perf);
   acmgt3_register_ext442_counter_query(perf);
   acmgt3_register_ext443_counter_query(perf);
   acmgt3_register_ext444_counter_query(perf);
   acmgt3_register_ext445_counter_query(perf);
   acmgt3_register_ext446_counter_query(perf);
   acmgt3_register_ext447_counter_query(perf);
   acmgt3_register_ext448_counter_query(perf);
   acmgt3_register_ext449_counter_query(perf);
   acmgt3_register_ext450_counter_query(perf);
   acmgt3_register_ext451_counter_query(perf);
   acmgt3_register_ext452_counter_query(perf);
   acmgt3_register_ext453_counter_query(perf);
   acmgt3_register_ext454_counter_query(perf);
   acmgt3_register_ext455_counter_query(perf);
   acmgt3_register_ext456_counter_query(perf);
   acmgt3_register_ext457_counter_query(perf);
   acmgt3_register_ext458_counter_query(perf);
   acmgt3_register_ext459_counter_query(perf);
   acmgt3_register_ext460_counter_query(perf);
   acmgt3_register_ext461_counter_query(perf);
   acmgt3_register_ext462_counter_query(perf);
   acmgt3_register_ext463_counter_query(perf);
   acmgt3_register_ext464_counter_query(perf);
   acmgt3_register_ext465_counter_query(perf);
   acmgt3_register_ext466_counter_query(perf);
   acmgt3_register_ext467_counter_query(perf);
   acmgt3_register_ext468_counter_query(perf);
   acmgt3_register_ext469_counter_query(perf);
   acmgt3_register_ext470_counter_query(perf);
   acmgt3_register_ext471_counter_query(perf);
   acmgt3_register_ext472_counter_query(perf);
   acmgt3_register_ext473_counter_query(perf);
   acmgt3_register_ext474_counter_query(perf);
   acmgt3_register_ext475_counter_query(perf);
   acmgt3_register_ext476_counter_query(perf);
   acmgt3_register_ext477_counter_query(perf);
   acmgt3_register_ext478_counter_query(perf);
   acmgt3_register_ext479_counter_query(perf);
   acmgt3_register_ext480_counter_query(perf);
   acmgt3_register_ext481_counter_query(perf);
   acmgt3_register_ext482_counter_query(perf);
   acmgt3_register_ext483_counter_query(perf);
   acmgt3_register_ext484_counter_query(perf);
   acmgt3_register_ext485_counter_query(perf);
   acmgt3_register_ext486_counter_query(perf);
   acmgt3_register_ext487_counter_query(perf);
   acmgt3_register_ext488_counter_query(perf);
   acmgt3_register_ext489_counter_query(perf);
   acmgt3_register_ext490_counter_query(perf);
   acmgt3_register_ext491_counter_query(perf);
   acmgt3_register_ext492_counter_query(perf);
   acmgt3_register_ext493_counter_query(perf);
   acmgt3_register_ext494_counter_query(perf);
   acmgt3_register_ext495_counter_query(perf);
   acmgt3_register_ext496_counter_query(perf);
   acmgt3_register_ext497_counter_query(perf);
   acmgt3_register_ext498_counter_query(perf);
   acmgt3_register_ext499_counter_query(perf);
   acmgt3_register_ext500_counter_query(perf);
   acmgt3_register_ext501_counter_query(perf);
   acmgt3_register_ext502_counter_query(perf);
   acmgt3_register_ext503_counter_query(perf);
   acmgt3_register_ext504_counter_query(perf);
   acmgt3_register_ext505_counter_query(perf);
   acmgt3_register_ext506_counter_query(perf);
   acmgt3_register_ext507_counter_query(perf);
   acmgt3_register_ext508_counter_query(perf);
   acmgt3_register_ext509_counter_query(perf);
   acmgt3_register_ext510_counter_query(perf);
   acmgt3_register_ext511_counter_query(perf);
   acmgt3_register_ext512_counter_query(perf);
   acmgt3_register_ext513_counter_query(perf);
   acmgt3_register_ext514_counter_query(perf);
   acmgt3_register_ext515_counter_query(perf);
   acmgt3_register_ext516_counter_query(perf);
   acmgt3_register_ext517_counter_query(perf);
   acmgt3_register_ext518_counter_query(perf);
   acmgt3_register_ext519_counter_query(perf);
   acmgt3_register_ext520_counter_query(perf);
   acmgt3_register_ext521_counter_query(perf);
   acmgt3_register_ext522_counter_query(perf);
   acmgt3_register_ext523_counter_query(perf);
   acmgt3_register_ext524_counter_query(perf);
   acmgt3_register_ext525_counter_query(perf);
   acmgt3_register_ext526_counter_query(perf);
   acmgt3_register_ext527_counter_query(perf);
   acmgt3_register_ext528_counter_query(perf);
   acmgt3_register_ext529_counter_query(perf);
   acmgt3_register_ext530_counter_query(perf);
   acmgt3_register_ext531_counter_query(perf);
   acmgt3_register_ext532_counter_query(perf);
   acmgt3_register_ext533_counter_query(perf);
   acmgt3_register_ext534_counter_query(perf);
   acmgt3_register_ext535_counter_query(perf);
   acmgt3_register_ext536_counter_query(perf);
   acmgt3_register_ext537_counter_query(perf);
   acmgt3_register_ext538_counter_query(perf);
   acmgt3_register_ext539_counter_query(perf);
   acmgt3_register_ext540_counter_query(perf);
   acmgt3_register_ext541_counter_query(perf);
   acmgt3_register_ext542_counter_query(perf);
   acmgt3_register_ext543_counter_query(perf);
   acmgt3_register_ext544_counter_query(perf);
   acmgt3_register_ext545_counter_query(perf);
   acmgt3_register_ext546_counter_query(perf);
   acmgt3_register_ext547_counter_query(perf);
   acmgt3_register_ext548_counter_query(perf);
   acmgt3_register_ext549_counter_query(perf);
   acmgt3_register_ext550_counter_query(perf);
   acmgt3_register_ext551_counter_query(perf);
   acmgt3_register_ext552_counter_query(perf);
   acmgt3_register_ext553_counter_query(perf);
   acmgt3_register_ext554_counter_query(perf);
   acmgt3_register_ext555_counter_query(perf);
   acmgt3_register_ext556_counter_query(perf);
   acmgt3_register_ext557_counter_query(perf);
   acmgt3_register_ext558_counter_query(perf);
   acmgt3_register_ext559_counter_query(perf);
   acmgt3_register_ext560_counter_query(perf);
   acmgt3_register_ext561_counter_query(perf);
   acmgt3_register_ext562_counter_query(perf);
   acmgt3_register_ext563_counter_query(perf);
   acmgt3_register_ext564_counter_query(perf);
   acmgt3_register_ext565_counter_query(perf);
   acmgt3_register_ext566_counter_query(perf);
   acmgt3_register_ext567_counter_query(perf);
   acmgt3_register_ext568_counter_query(perf);
   acmgt3_register_ext569_counter_query(perf);
   acmgt3_register_ext570_counter_query(perf);
   acmgt3_register_ext571_counter_query(perf);
   acmgt3_register_ext572_counter_query(perf);
   acmgt3_register_ext573_counter_query(perf);
   acmgt3_register_ext574_counter_query(perf);
   acmgt3_register_ext575_counter_query(perf);
   acmgt3_register_ext576_counter_query(perf);
   acmgt3_register_ext577_counter_query(perf);
   acmgt3_register_ext578_counter_query(perf);
   acmgt3_register_ext579_counter_query(perf);
   acmgt3_register_ext580_counter_query(perf);
   acmgt3_register_ext581_counter_query(perf);
   acmgt3_register_ext582_counter_query(perf);
   acmgt3_register_ext583_counter_query(perf);
   acmgt3_register_ext584_counter_query(perf);
   acmgt3_register_ext585_counter_query(perf);
   acmgt3_register_ext586_counter_query(perf);
   acmgt3_register_ext587_counter_query(perf);
   acmgt3_register_ext588_counter_query(perf);
   acmgt3_register_ext589_counter_query(perf);
   acmgt3_register_ext590_counter_query(perf);
   acmgt3_register_ext591_counter_query(perf);
   acmgt3_register_ext592_counter_query(perf);
   acmgt3_register_ext593_counter_query(perf);
   acmgt3_register_ext594_counter_query(perf);
   acmgt3_register_ext595_counter_query(perf);
   acmgt3_register_ext596_counter_query(perf);
   acmgt3_register_ext597_counter_query(perf);
   acmgt3_register_ext598_counter_query(perf);
   acmgt3_register_ext599_counter_query(perf);
   acmgt3_register_ext600_counter_query(perf);
   acmgt3_register_ext601_counter_query(perf);
   acmgt3_register_ext602_counter_query(perf);
   acmgt3_register_ext603_counter_query(perf);
   acmgt3_register_ext604_counter_query(perf);
   acmgt3_register_ext605_counter_query(perf);
   acmgt3_register_ext606_counter_query(perf);
   acmgt3_register_ext607_counter_query(perf);
   acmgt3_register_ext608_counter_query(perf);
   acmgt3_register_ext609_counter_query(perf);
   acmgt3_register_ext610_counter_query(perf);
   acmgt3_register_ext611_counter_query(perf);
   acmgt3_register_ext612_counter_query(perf);
   acmgt3_register_ext613_counter_query(perf);
   acmgt3_register_ext614_counter_query(perf);
   acmgt3_register_ext615_counter_query(perf);
   acmgt3_register_ext616_counter_query(perf);
   acmgt3_register_ext617_counter_query(perf);
   acmgt3_register_ext618_counter_query(perf);
   acmgt3_register_ext619_counter_query(perf);
   acmgt3_register_ext620_counter_query(perf);
   acmgt3_register_ext621_counter_query(perf);
   acmgt3_register_ext622_counter_query(perf);
   acmgt3_register_ext623_counter_query(perf);
   acmgt3_register_ext624_counter_query(perf);
   acmgt3_register_ext625_counter_query(perf);
   acmgt3_register_ext626_counter_query(perf);
   acmgt3_register_ext627_counter_query(perf);
   acmgt3_register_ext628_counter_query(perf);
   acmgt3_register_ext629_counter_query(perf);
   acmgt3_register_ext630_counter_query(perf);
   acmgt3_register_ext631_counter_query(perf);
   acmgt3_register_ext632_counter_query(perf);
   acmgt3_register_ext633_counter_query(perf);
   acmgt3_register_ext634_counter_query(perf);
   acmgt3_register_ext635_counter_query(perf);
   acmgt3_register_ext636_counter_query(perf);
   acmgt3_register_ext637_counter_query(perf);
   acmgt3_register_ext638_counter_query(perf);
   acmgt3_register_ext639_counter_query(perf);
   acmgt3_register_ext640_counter_query(perf);
   acmgt3_register_ext641_counter_query(perf);
   acmgt3_register_ext642_counter_query(perf);
   acmgt3_register_ext643_counter_query(perf);
   acmgt3_register_ext644_counter_query(perf);
   acmgt3_register_ext645_counter_query(perf);
   acmgt3_register_ext646_counter_query(perf);
   acmgt3_register_ext647_counter_query(perf);
   acmgt3_register_ext648_counter_query(perf);
   acmgt3_register_ext649_counter_query(perf);
   acmgt3_register_ext650_counter_query(perf);
   acmgt3_register_ext651_counter_query(perf);
   acmgt3_register_ext652_counter_query(perf);
   acmgt3_register_ext653_counter_query(perf);
   acmgt3_register_ext654_counter_query(perf);
   acmgt3_register_ext655_counter_query(perf);
   acmgt3_register_ext656_counter_query(perf);
   acmgt3_register_ext657_counter_query(perf);
   acmgt3_register_ext658_counter_query(perf);
   acmgt3_register_ext659_counter_query(perf);
   acmgt3_register_ext660_counter_query(perf);
   acmgt3_register_ext661_counter_query(perf);
   acmgt3_register_ext662_counter_query(perf);
   acmgt3_register_ext663_counter_query(perf);
   acmgt3_register_ext664_counter_query(perf);
   acmgt3_register_ext665_counter_query(perf);
   acmgt3_register_ext666_counter_query(perf);
   acmgt3_register_ext667_counter_query(perf);
   acmgt3_register_ext668_counter_query(perf);
   acmgt3_register_ext669_counter_query(perf);
   acmgt3_register_ext670_counter_query(perf);
   acmgt3_register_ext671_counter_query(perf);
   acmgt3_register_ext672_counter_query(perf);
   acmgt3_register_ext673_counter_query(perf);
   acmgt3_register_ext674_counter_query(perf);
   acmgt3_register_ext675_counter_query(perf);
   acmgt3_register_ext676_counter_query(perf);
   acmgt3_register_ext677_counter_query(perf);
   acmgt3_register_ext678_counter_query(perf);
   acmgt3_register_ext679_counter_query(perf);
   acmgt3_register_ext680_counter_query(perf);
   acmgt3_register_ext681_counter_query(perf);
   acmgt3_register_ext682_counter_query(perf);
   acmgt3_register_ext683_counter_query(perf);
   acmgt3_register_ext684_counter_query(perf);
   acmgt3_register_ext685_counter_query(perf);
   acmgt3_register_ext686_counter_query(perf);
   acmgt3_register_ext687_counter_query(perf);
   acmgt3_register_ext688_counter_query(perf);
   acmgt3_register_ext689_counter_query(perf);
   acmgt3_register_ext690_counter_query(perf);
   acmgt3_register_ext691_counter_query(perf);
   acmgt3_register_ext692_counter_query(perf);
   acmgt3_register_ext693_counter_query(perf);
   acmgt3_register_ext694_counter_query(perf);
   acmgt3_register_ext695_counter_query(perf);
   acmgt3_register_ext696_counter_query(perf);
   acmgt3_register_ext697_counter_query(perf);
   acmgt3_register_ext698_counter_query(perf);
   acmgt3_register_ext699_counter_query(perf);
   acmgt3_register_ext700_counter_query(perf);
   acmgt3_register_ext701_counter_query(perf);
   acmgt3_register_ext702_counter_query(perf);
   acmgt3_register_ext703_counter_query(perf);
   acmgt3_register_ext704_counter_query(perf);
   acmgt3_register_ext705_counter_query(perf);
   acmgt3_register_ext706_counter_query(perf);
   acmgt3_register_ext707_counter_query(perf);
   acmgt3_register_ext708_counter_query(perf);
   acmgt3_register_ext709_counter_query(perf);
   acmgt3_register_ext710_counter_query(perf);
   acmgt3_register_ext711_counter_query(perf);
   acmgt3_register_ext712_counter_query(perf);
   acmgt3_register_ext713_counter_query(perf);
   acmgt3_register_ext714_counter_query(perf);
   acmgt3_register_ext715_counter_query(perf);
   acmgt3_register_ext716_counter_query(perf);
   acmgt3_register_ext717_counter_query(perf);
   acmgt3_register_ext718_counter_query(perf);
   acmgt3_register_ext719_counter_query(perf);
   acmgt3_register_ext720_counter_query(perf);
   acmgt3_register_ext721_counter_query(perf);
   acmgt3_register_ext722_counter_query(perf);
   acmgt3_register_ext723_counter_query(perf);
   acmgt3_register_ext724_counter_query(perf);
   acmgt3_register_ext725_counter_query(perf);
   acmgt3_register_ext726_counter_query(perf);
   acmgt3_register_ext727_counter_query(perf);
   acmgt3_register_ext728_counter_query(perf);
   acmgt3_register_ext729_counter_query(perf);
   acmgt3_register_ext730_counter_query(perf);
   acmgt3_register_ext731_counter_query(perf);
   acmgt3_register_ext732_counter_query(perf);
   acmgt3_register_ext733_counter_query(perf);
   acmgt3_register_ext734_counter_query(perf);
   acmgt3_register_ext735_counter_query(perf);
   acmgt3_register_ext736_counter_query(perf);
   acmgt3_register_ext737_counter_query(perf);
   acmgt3_register_ext738_counter_query(perf);
   acmgt3_register_ext739_counter_query(perf);
   acmgt3_register_ext740_counter_query(perf);
   acmgt3_register_ext741_counter_query(perf);
   acmgt3_register_ext742_counter_query(perf);
   acmgt3_register_ext743_counter_query(perf);
   acmgt3_register_ext744_counter_query(perf);
   acmgt3_register_ext745_counter_query(perf);
   acmgt3_register_ext746_counter_query(perf);
   acmgt3_register_ext747_counter_query(perf);
   acmgt3_register_ext748_counter_query(perf);
   acmgt3_register_ext749_counter_query(perf);
   acmgt3_register_ext750_counter_query(perf);
   acmgt3_register_ext751_counter_query(perf);
   acmgt3_register_ext752_counter_query(perf);
   acmgt3_register_ext753_counter_query(perf);
   acmgt3_register_ext754_counter_query(perf);
   acmgt3_register_ext755_counter_query(perf);
   acmgt3_register_ext756_counter_query(perf);
   acmgt3_register_ext757_counter_query(perf);
   acmgt3_register_ext758_counter_query(perf);
   acmgt3_register_ext759_counter_query(perf);
   acmgt3_register_ext760_counter_query(perf);
   acmgt3_register_ext761_counter_query(perf);
   acmgt3_register_ext762_counter_query(perf);
   acmgt3_register_ext763_counter_query(perf);
   acmgt3_register_ext764_counter_query(perf);
   acmgt3_register_ext765_counter_query(perf);
   acmgt3_register_ext766_counter_query(perf);
   acmgt3_register_ext767_counter_query(perf);
   acmgt3_register_ext768_counter_query(perf);
   acmgt3_register_ext769_counter_query(perf);
   acmgt3_register_ext770_counter_query(perf);
   acmgt3_register_ext771_counter_query(perf);
   acmgt3_register_ext772_counter_query(perf);
   acmgt3_register_ext773_counter_query(perf);
   acmgt3_register_ext774_counter_query(perf);
   acmgt3_register_ext775_counter_query(perf);
   acmgt3_register_ext776_counter_query(perf);
   acmgt3_register_ext777_counter_query(perf);
   acmgt3_register_ext778_counter_query(perf);
   acmgt3_register_ext779_counter_query(perf);
   acmgt3_register_ext780_counter_query(perf);
   acmgt3_register_ext781_counter_query(perf);
   acmgt3_register_ext782_counter_query(perf);
   acmgt3_register_ext783_counter_query(perf);
   acmgt3_register_ext784_counter_query(perf);
   acmgt3_register_ext785_counter_query(perf);
   acmgt3_register_ext786_counter_query(perf);
   acmgt3_register_ext787_counter_query(perf);
   acmgt3_register_ext788_counter_query(perf);
   acmgt3_register_ext789_counter_query(perf);
   acmgt3_register_ext790_counter_query(perf);
   acmgt3_register_ext791_counter_query(perf);
   acmgt3_register_ext792_counter_query(perf);
   acmgt3_register_ext793_counter_query(perf);
   acmgt3_register_ext794_counter_query(perf);
   acmgt3_register_ext795_counter_query(perf);
   acmgt3_register_ext796_counter_query(perf);
   acmgt3_register_ext797_counter_query(perf);
   acmgt3_register_ext798_counter_query(perf);
   acmgt3_register_ext799_counter_query(perf);
   acmgt3_register_ext800_counter_query(perf);
   acmgt3_register_ext801_counter_query(perf);
   acmgt3_register_ext802_counter_query(perf);
   acmgt3_register_ext803_counter_query(perf);
   acmgt3_register_ext804_counter_query(perf);
   acmgt3_register_ext805_counter_query(perf);
   acmgt3_register_ext806_counter_query(perf);
   acmgt3_register_ext807_counter_query(perf);
   acmgt3_register_ext808_counter_query(perf);
   acmgt3_register_ext809_counter_query(perf);
   acmgt3_register_ext810_counter_query(perf);
   acmgt3_register_ext811_counter_query(perf);
   acmgt3_register_ext812_counter_query(perf);
   acmgt3_register_ext813_counter_query(perf);
   acmgt3_register_ext814_counter_query(perf);
   acmgt3_register_ext815_counter_query(perf);
   acmgt3_register_ext816_counter_query(perf);
   acmgt3_register_ext817_counter_query(perf);
   acmgt3_register_ext818_counter_query(perf);
   acmgt3_register_ext819_counter_query(perf);
   acmgt3_register_ext820_counter_query(perf);
   acmgt3_register_ext821_counter_query(perf);
   acmgt3_register_ext822_counter_query(perf);
   acmgt3_register_ext823_counter_query(perf);
   acmgt3_register_ext824_counter_query(perf);
   acmgt3_register_ext825_counter_query(perf);
   acmgt3_register_ext826_counter_query(perf);
   acmgt3_register_ext827_counter_query(perf);
   acmgt3_register_ext828_counter_query(perf);
   acmgt3_register_ext829_counter_query(perf);
   acmgt3_register_ext830_counter_query(perf);
   acmgt3_register_ext831_counter_query(perf);
   acmgt3_register_ext832_counter_query(perf);
   acmgt3_register_ext833_counter_query(perf);
   acmgt3_register_ext834_counter_query(perf);
   acmgt3_register_ext835_counter_query(perf);
   acmgt3_register_ext836_counter_query(perf);
   acmgt3_register_ext837_counter_query(perf);
   acmgt3_register_ext838_counter_query(perf);
   acmgt3_register_ext839_counter_query(perf);
   acmgt3_register_ext840_counter_query(perf);
   acmgt3_register_ext841_counter_query(perf);
   acmgt3_register_ext842_counter_query(perf);
   acmgt3_register_ext843_counter_query(perf);
   acmgt3_register_ext844_counter_query(perf);
   acmgt3_register_ext845_counter_query(perf);
   acmgt3_register_ext846_counter_query(perf);
   acmgt3_register_ext847_counter_query(perf);
   acmgt3_register_ext848_counter_query(perf);
   acmgt3_register_ext849_counter_query(perf);
   acmgt3_register_ext850_counter_query(perf);
   acmgt3_register_ext851_counter_query(perf);
   acmgt3_register_ext852_counter_query(perf);
   acmgt3_register_ext853_counter_query(perf);
   acmgt3_register_ext854_counter_query(perf);
   acmgt3_register_ext855_counter_query(perf);
   acmgt3_register_ext856_counter_query(perf);
   acmgt3_register_ext857_counter_query(perf);
   acmgt3_register_ext858_counter_query(perf);
   acmgt3_register_ext859_counter_query(perf);
   acmgt3_register_ext860_counter_query(perf);
   acmgt3_register_ext861_counter_query(perf);
   acmgt3_register_ext862_counter_query(perf);
   acmgt3_register_ext863_counter_query(perf);
   acmgt3_register_ext864_counter_query(perf);
   acmgt3_register_ext865_counter_query(perf);
   acmgt3_register_ext866_counter_query(perf);
   acmgt3_register_ext867_counter_query(perf);
   acmgt3_register_ext868_counter_query(perf);
   acmgt3_register_ext869_counter_query(perf);
   acmgt3_register_ext870_counter_query(perf);
   acmgt3_register_ext871_counter_query(perf);
   acmgt3_register_ext872_counter_query(perf);
   acmgt3_register_ext873_counter_query(perf);
   acmgt3_register_ext874_counter_query(perf);
   acmgt3_register_ext875_counter_query(perf);
   acmgt3_register_ext876_counter_query(perf);
   acmgt3_register_ext877_counter_query(perf);
   acmgt3_register_ext878_counter_query(perf);
   acmgt3_register_ext879_counter_query(perf);
   acmgt3_register_ext880_counter_query(perf);
   acmgt3_register_ext881_counter_query(perf);
   acmgt3_register_ext882_counter_query(perf);
   acmgt3_register_ext883_counter_query(perf);
   acmgt3_register_ext884_counter_query(perf);
   acmgt3_register_ext885_counter_query(perf);
   acmgt3_register_ext886_counter_query(perf);
   acmgt3_register_ext887_counter_query(perf);
   acmgt3_register_ext888_counter_query(perf);
   acmgt3_register_ext889_counter_query(perf);
   acmgt3_register_ext890_counter_query(perf);
   acmgt3_register_ext891_counter_query(perf);
   acmgt3_register_ext892_counter_query(perf);
   acmgt3_register_ext893_counter_query(perf);
   acmgt3_register_ext894_counter_query(perf);
   acmgt3_register_ext895_counter_query(perf);
   acmgt3_register_ext896_counter_query(perf);
   acmgt3_register_ext897_counter_query(perf);
   acmgt3_register_ext898_counter_query(perf);
   acmgt3_register_ext899_counter_query(perf);
   acmgt3_register_ext900_counter_query(perf);
   acmgt3_register_ext901_counter_query(perf);
   acmgt3_register_ext902_counter_query(perf);
   acmgt3_register_ext903_counter_query(perf);
   acmgt3_register_ext904_counter_query(perf);
   acmgt3_register_ext905_counter_query(perf);
   acmgt3_register_ext906_counter_query(perf);
   acmgt3_register_ext907_counter_query(perf);
   acmgt3_register_ext908_counter_query(perf);
   acmgt3_register_ext909_counter_query(perf);
   acmgt3_register_ext910_counter_query(perf);
   acmgt3_register_ext911_counter_query(perf);
   acmgt3_register_ext912_counter_query(perf);
   acmgt3_register_ext913_counter_query(perf);
   acmgt3_register_ext914_counter_query(perf);
   acmgt3_register_ext915_counter_query(perf);
   acmgt3_register_ext916_counter_query(perf);
   acmgt3_register_ext917_counter_query(perf);
   acmgt3_register_ext918_counter_query(perf);
   acmgt3_register_ext919_counter_query(perf);
   acmgt3_register_ext920_counter_query(perf);
   acmgt3_register_ext921_counter_query(perf);
   acmgt3_register_ext922_counter_query(perf);
   acmgt3_register_ext923_counter_query(perf);
   acmgt3_register_ext924_counter_query(perf);
   acmgt3_register_ext925_counter_query(perf);
   acmgt3_register_ext926_counter_query(perf);
   acmgt3_register_ext927_counter_query(perf);
   acmgt3_register_ext928_counter_query(perf);
   acmgt3_register_ext929_counter_query(perf);
   acmgt3_register_ext930_counter_query(perf);
   acmgt3_register_ext931_counter_query(perf);
   acmgt3_register_ext932_counter_query(perf);
   acmgt3_register_ext933_counter_query(perf);
   acmgt3_register_ext934_counter_query(perf);
   acmgt3_register_ext935_counter_query(perf);
   acmgt3_register_ext936_counter_query(perf);
   acmgt3_register_ext937_counter_query(perf);
   acmgt3_register_ext938_counter_query(perf);
   acmgt3_register_ext939_counter_query(perf);
   acmgt3_register_ext940_counter_query(perf);
   acmgt3_register_ext941_counter_query(perf);
   acmgt3_register_ext942_counter_query(perf);
   acmgt3_register_ext943_counter_query(perf);
   acmgt3_register_ext944_counter_query(perf);
   acmgt3_register_ext945_counter_query(perf);
   acmgt3_register_ext946_counter_query(perf);
   acmgt3_register_ext947_counter_query(perf);
   acmgt3_register_ext948_counter_query(perf);
   acmgt3_register_ext949_counter_query(perf);
   acmgt3_register_ext950_counter_query(perf);
   acmgt3_register_ext951_counter_query(perf);
   acmgt3_register_ext952_counter_query(perf);
   acmgt3_register_ext953_counter_query(perf);
   acmgt3_register_ext954_counter_query(perf);
   acmgt3_register_ext955_counter_query(perf);
   acmgt3_register_ext956_counter_query(perf);
   acmgt3_register_ext957_counter_query(perf);
   acmgt3_register_ext958_counter_query(perf);
   acmgt3_register_ext959_counter_query(perf);
   acmgt3_register_ext960_counter_query(perf);
   acmgt3_register_ext961_counter_query(perf);
   acmgt3_register_ext962_counter_query(perf);
   acmgt3_register_ext963_counter_query(perf);
   acmgt3_register_ext964_counter_query(perf);
   acmgt3_register_ext965_counter_query(perf);
   acmgt3_register_ext966_counter_query(perf);
   acmgt3_register_ext967_counter_query(perf);
   acmgt3_register_ext968_counter_query(perf);
   acmgt3_register_ext969_counter_query(perf);
   acmgt3_register_ext970_counter_query(perf);
   acmgt3_register_ext971_counter_query(perf);
   acmgt3_register_ext972_counter_query(perf);
   acmgt3_register_ext973_counter_query(perf);
   acmgt3_register_ext974_counter_query(perf);
   acmgt3_register_ext975_counter_query(perf);
   acmgt3_register_ext976_counter_query(perf);
   acmgt3_register_ext977_counter_query(perf);
   acmgt3_register_ext978_counter_query(perf);
   acmgt3_register_ext979_counter_query(perf);
   acmgt3_register_ext980_counter_query(perf);
   acmgt3_register_ext981_counter_query(perf);
   acmgt3_register_ext982_counter_query(perf);
   acmgt3_register_ext983_counter_query(perf);
   acmgt3_register_ext984_counter_query(perf);
   acmgt3_register_ext985_counter_query(perf);
   acmgt3_register_ext986_counter_query(perf);
   acmgt3_register_ext987_counter_query(perf);
   acmgt3_register_ext1000_counter_query(perf);
   acmgt3_register_ext1001_counter_query(perf);
   acmgt3_register_ext1002_counter_query(perf);
   acmgt3_register_ext1004_counter_query(perf);
   acmgt3_register_ext1005_counter_query(perf);
   acmgt3_register_ext1006_counter_query(perf);
   acmgt3_register_ext1007_counter_query(perf);
   acmgt3_register_ext1010_counter_query(perf);
}


static void
mtlgt2_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Render Metrics Basic";
   query->symbol_name = "RenderBasic";
   query->guid = "232e858b-7116-44e8-a4be-856c59026650";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1E040000 },
         { .reg = 0x00009888, .val = 0x20042800 },
         { .reg = 0x00009888, .val = 0x04042000 },
         { .reg = 0x00009888, .val = 0x06040000 },
         { .reg = 0x00009888, .val = 0x14040800 },
         { .reg = 0x00009888, .val = 0x16040037 },
         { .reg = 0x00009888, .val = 0x02040000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0201F000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00003008 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__render_basic__avg_gpu_core_frequency__max,mtlgt2__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,mtlgt2__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,mtlgt2__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,mtlgt2__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,mtlgt2__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,mtlgt2__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,mtlgt2__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,mtlgt2__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 5641, 76, percentage_max_float,mtlgt2__render_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 5642, 80, percentage_max_float,mtlgt2__render_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 5643, 84, percentage_max_float,mtlgt2__render_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 5644, 88, percentage_max_float,mtlgt2__render_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 5645, 92, percentage_max_float,mtlgt2__render_basic__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5646, 96, percentage_max_float,mtlgt2__render_basic__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 5647, 100, percentage_max_float,mtlgt2__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 5648, 104, percentage_max_float,mtlgt2__render_basic__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5649, 108, percentage_max_float,mtlgt2__render_basic__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 5650, 112, percentage_max_float,mtlgt2__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,mtlgt2__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,mtlgt2__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,mtlgt2__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,mtlgt2__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,mtlgt2__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,mtlgt2__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,mtlgt2__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,mtlgt2__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,mtlgt2__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 5651, 192, mtlgt2__render_basic__slm_reads__max,mtlgt2__render_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 5652, 200, mtlgt2__render_basic__slm_writes__max,mtlgt2__render_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,mtlgt2__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,mtlgt2__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,mtlgt2__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 232, mtlgt2__render_basic__gti_read_throughput__max,mtlgt2__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 240, mtlgt2__render_basic__gti_write_throughput__max,mtlgt2__render_basic__gti_write_throughput__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 563, 248, percentage_max_float,mtlgt2__render_basic__samplers_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 565, 252, percentage_max_float,mtlgt2__render_basic__sampler_bottleneck__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic";
   query->symbol_name = "ComputeBasic";
   query->guid = "fea2b2b7-a072-41c5-9092-2d7c48bb56c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00003009 },
         { .reg = 0x0000E758, .val = 0x0000200A },
         { .reg = 0x0000E45C, .val = 0x00006008 },
         { .reg = 0x0000E55C, .val = 0x0000B007 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__compute_basic__avg_gpu_core_frequency__max,mtlgt2__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,mtlgt2__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,mtlgt2__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,mtlgt2__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,mtlgt2__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,mtlgt2__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,mtlgt2__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 5641, 80, percentage_max_float,mtlgt2__compute_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 5642, 84, percentage_max_float,mtlgt2__compute_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 5653, 88, percentage_max_float,mtlgt2__compute_basic__fpu_active__read);

      intel_perf_query_add_counter_float(query, 5654, 92, percentage_max_float,mtlgt2__compute_basic__em_active__read);

      intel_perf_query_add_counter_float(query, 5655, 96, percentage_max_float,mtlgt2__compute_basic__xmx_active__read);

      intel_perf_query_add_counter_float(query, 5644, 100, percentage_max_float,mtlgt2__compute_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 5656, 104, percentage_max_float,mtlgt2__compute_basic__xve_fpu_xmx_active__read);

      intel_perf_query_add_counter_float(query, 5657, 108, mtlgt2__compute_basic__xve_avg_ipc_rate__max,mtlgt2__compute_basic__xve_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 5658, 112, percentage_max_float,mtlgt2__compute_basic__send_active__read);

      intel_perf_query_add_counter_float(query, 5643, 116, percentage_max_float,mtlgt2__compute_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 5659, 120, percentage_max_float,mtlgt2__compute_basic__xve_fpu_flt16__read);

      intel_perf_query_add_counter_float(query, 5660, 124, percentage_max_float,mtlgt2__compute_basic__xve_fpu_flt32__read);

      intel_perf_query_add_counter_float(query, 5661, 128, percentage_max_float,mtlgt2__compute_basic__xve_fpu_flt64__read);

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,mtlgt2__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,mtlgt2__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,mtlgt2__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,mtlgt2__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,mtlgt2__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,mtlgt2__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,mtlgt2__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,mtlgt2__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,mtlgt2__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 5651, 208, mtlgt2__compute_basic__slm_reads__max,mtlgt2__compute_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 5652, 216, mtlgt2__compute_basic__slm_writes__max,mtlgt2__compute_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 142, 224, NULL,mtlgt2__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 232, NULL,mtlgt2__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 240, NULL,mtlgt2__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 248, mtlgt2__compute_basic__gti_read_throughput__max,mtlgt2__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 256, mtlgt2__compute_basic__gti_write_throughput__max,mtlgt2__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "011e5c80-c877-46fd-90ff-fd0bb29cb5ec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00010000 },
         { .reg = 0x0000E558, .val = 0x00060050 },
         { .reg = 0x0000E658, .val = 0x00001090 },
         { .reg = 0x0000E758, .val = 0x00051011 },
         { .reg = 0x0000E45C, .val = 0x00091061 },
         { .reg = 0x0000E55C, .val = 0x00004008 },
         { .reg = 0x0000E65C, .val = 0x00000005 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__async_compute__avg_gpu_core_frequency__max,mtlgt2__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,mtlgt2__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,mtlgt2__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,mtlgt2__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,mtlgt2__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,mtlgt2__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,mtlgt2__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 5653, 80, percentage_max_float,mtlgt2__async_compute__fpu_active__read);

      intel_perf_query_add_counter_float(query, 5645, 84, percentage_max_float,mtlgt2__async_compute__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5648, 88, percentage_max_float,mtlgt2__async_compute__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5662, 92, percentage_max_float,mtlgt2__async_compute__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5663, 96, percentage_max_float,mtlgt2__async_compute__async_cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5654, 100, percentage_max_float,mtlgt2__async_compute__em_active__read);

      intel_perf_query_add_counter_float(query, 5646, 104, percentage_max_float,mtlgt2__async_compute__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 5649, 108, percentage_max_float,mtlgt2__async_compute__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 5664, 112, percentage_max_float,mtlgt2__async_compute__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 5665, 116, percentage_max_float,mtlgt2__async_compute__async_cs_em_active__read);

      intel_perf_query_add_counter_float(query, 5643, 120, percentage_max_float,mtlgt2__async_compute__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 5641, 124, percentage_max_float,mtlgt2__async_compute__xve_active__read);

      intel_perf_query_add_counter_float(query, 5642, 128, percentage_max_float,mtlgt2__async_compute__xve_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_xve_activity_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "XveActivity";
   query->symbol_name = "XveActivity";
   query->guid = "5f430543-ba1e-487c-b217-90570cfb85f9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00030020 },
         { .reg = 0x0000E558, .val = 0x00021040 },
         { .reg = 0x0000E658, .val = 0x00041031 },
         { .reg = 0x0000E758, .val = 0x00032022 },
         { .reg = 0x0000E45C, .val = 0x00062042 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__xve_activity__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__xve_activity__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__xve_activity__avg_gpu_core_frequency__max,mtlgt2__xve_activity__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__xve_activity__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,mtlgt2__xve_activity__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,mtlgt2__xve_activity__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,mtlgt2__xve_activity__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,mtlgt2__xve_activity__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,mtlgt2__xve_activity__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,mtlgt2__xve_activity__cs_threads__read);

      intel_perf_query_add_counter_float(query, 5666, 80, percentage_max_float,mtlgt2__xve_activity__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5667, 84, percentage_max_float,mtlgt2__xve_activity__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5668, 88, percentage_max_float,mtlgt2__xve_activity__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5669, 92, percentage_max_float,mtlgt2__xve_activity__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 5670, 96, percentage_max_float,mtlgt2__xve_activity__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 5671, 100, percentage_max_float,mtlgt2__xve_activity__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 5672, 104, percentage_max_float,mtlgt2__xve_activity__hs_send_active__read);

      intel_perf_query_add_counter_float(query, 5673, 108, percentage_max_float,mtlgt2__xve_activity__ds_send_active__read);

      intel_perf_query_add_counter_float(query, 5674, 112, percentage_max_float,mtlgt2__xve_activity__gs_send_active__read);

      intel_perf_query_add_counter_float(query, 5675, 116, percentage_max_float,mtlgt2__xve_activity__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 16);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "3cb64fed-0f61-4e41-a754-b9c5b4892f77";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1A022400 },
         { .reg = 0x00009888, .val = 0x1C012400 },
         { .reg = 0x00009888, .val = 0x26010009 },
         { .reg = 0x00009888, .val = 0x04020006 },
         { .reg = 0x00009888, .val = 0x16020004 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x04010C09 },
         { .reg = 0x00009888, .val = 0x16010100 },
         { .reg = 0x00009888, .val = 0x18010014 },
         { .reg = 0x00009888, .val = 0x02010400 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010200 },
         { .reg = 0x00009888, .val = 0x56010010 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__gpu_busyness__avg_gpu_core_frequency__max,mtlgt2__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 5641, 28, percentage_max_float,mtlgt2__gpu_busyness__xve_active__read);

      intel_perf_query_add_counter_float(query, 5642, 32, percentage_max_float,mtlgt2__gpu_busyness__xve_stall__read);

      intel_perf_query_add_counter_float(query, 5643, 36, percentage_max_float,mtlgt2__gpu_busyness__xve_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,mtlgt2__gpu_busyness__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,mtlgt2__gpu_busyness__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,mtlgt2__gpu_busyness__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,mtlgt2__gpu_busyness__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,mtlgt2__gpu_busyness__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,mtlgt2__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 88, percentage_max_float,mtlgt2__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 5676, 92, percentage_max_float,mtlgt2__gpu_busyness__compute_engine0_busy__read);

      intel_perf_query_add_counter_float(query, 313, 96, percentage_max_float,mtlgt2__gpu_busyness__blitter_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_hdc_and_sf_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set HDCAndSF";
   query->symbol_name = "HDCAndSF";
   query->guid = "27d6eda4-aabc-4203-8848-aef69658ae74";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C023800 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x06024E00 },
         { .reg = 0x00009888, .val = 0x0002000C },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x0008000C },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C023800 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x08020027 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00040004 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C023800 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x080209C0 },
         { .reg = 0x00009888, .val = 0x000200C0 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x000800C0 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C023800 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x0A020027 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00040040 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C106400 },
         { .reg = 0x00009888, .val = 0x2607001E },
         { .reg = 0x00009888, .val = 0x2E07001E },
         { .reg = 0x00009888, .val = 0x2208001E },
         { .reg = 0x00009888, .val = 0x2A08001E },
         { .reg = 0x00009888, .val = 0x001301A0 },
         { .reg = 0x00009888, .val = 0x00140050 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x00160150 },
         { .reg = 0x00009888, .val = 0x001700A0 },
         { .reg = 0x00009888, .val = 0x00100000 },
         { .reg = 0x00009888, .val = 0x061009C0 },
         { .reg = 0x00009888, .val = 0x000C001C },
         { .reg = 0x00009888, .val = 0x000E001C },
         { .reg = 0x00009888, .val = 0x000D00A0 },
         { .reg = 0x00009888, .val = 0x000602A0 },
         { .reg = 0x00009888, .val = 0x02065500 },
         { .reg = 0x00009888, .val = 0x000102AF },
         { .reg = 0x00009888, .val = 0x0201AA00 },
         { .reg = 0x00009888, .val = 0x04070B00 },
         { .reg = 0x00009888, .val = 0x0607000B },
         { .reg = 0x00009888, .val = 0x160705A6 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070500 },
         { .reg = 0x00009888, .val = 0x00080B00 },
         { .reg = 0x00009888, .val = 0x0208000B },
         { .reg = 0x00009888, .val = 0x100805A6 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010609 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010009 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010211 },
         { .reg = 0x00009888, .val = 0x54010221 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__hdc_and_sf__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__hdc_and_sf__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__hdc_and_sf__avg_gpu_core_frequency__max,mtlgt2__hdc_and_sf__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__hdc_and_sf__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5677, 28, percentage_max_float,mtlgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5678, 32, percentage_max_float,mtlgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5679, 36, percentage_max_float,mtlgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5680, 40, percentage_max_float,mtlgt2__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read);
      }

      intel_perf_query_add_counter_float(query, 5681, 44, percentage_max_float,mtlgt2__hdc_and_sf__poly0_data_ready__read);

      intel_perf_query_add_counter_float(query, 5682, 48, percentage_max_float,mtlgt2__hdc_and_sf__gt_request_queue00_full__read);

      intel_perf_query_add_counter_float(query, 5683, 52, percentage_max_float,mtlgt2__hdc_and_sf__gt_request_queue01_full__read);

      intel_perf_query_add_counter_float(query, 5684, 56, percentage_max_float,mtlgt2__hdc_and_sf__gt_request_queue10_full__read);

      intel_perf_query_add_counter_float(query, 5685, 60, percentage_max_float,mtlgt2__hdc_and_sf__gt_request_queue11_full__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_l3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "L3";
   query->symbol_name = "L3";
   query->guid = "50b898ad-44ae-4d02-ba5b-a7d2a024a480";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04011000 },
         { .reg = 0x00009888, .val = 0x04411000 },
         { .reg = 0x00009888, .val = 0x04811000 },
         { .reg = 0x00009888, .val = 0x04C11000 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x0E010180 },
         { .reg = 0x00009888, .val = 0x120101C0 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x0E410006 },
         { .reg = 0x00009888, .val = 0x12410007 },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0C810180 },
         { .reg = 0x00009888, .val = 0x108101C0 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x0CC10006 },
         { .reg = 0x00009888, .val = 0x10C10007 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124400 },
         { .reg = 0x00009888, .val = 0x0213BABA },
         { .reg = 0x00009888, .val = 0x02144949 },
         { .reg = 0x00009888, .val = 0x02158383 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x021A2020 },
         { .reg = 0x00009888, .val = 0x001B2200 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__l3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__l3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__l3__avg_gpu_core_frequency__max,mtlgt2__l3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__l3__gpu_busy__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5686, 28, percentage_max_float,mtlgt2__l3__l3_input_available_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5687, 32, percentage_max_float,mtlgt2__l3__l3_input_available_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5688, 36, percentage_max_float,mtlgt2__l3__l3_input_available_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5689, 40, percentage_max_float,mtlgt2__l3__l3_input_available_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5690, 44, percentage_max_float,mtlgt2__l3__l3_output_ready_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5691, 48, percentage_max_float,mtlgt2__l3__l3_output_ready_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5692, 52, percentage_max_float,mtlgt2__l3__l3_output_ready_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5693, 56, percentage_max_float,mtlgt2__l3__l3_output_ready_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_rasterizer_and_pixel_backend1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Metric set RasterizerAndPixelBackend1";
   query->symbol_name = "RasterizerAndPixelBackend1";
   query->guid = "29adb364-f161-40cb-929d-c14036447c4f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x161224C0 },
         { .reg = 0x00009888, .val = 0x24107000 },
         { .reg = 0x00009888, .val = 0x0A0E7000 },
         { .reg = 0x00009888, .val = 0x0C0E6000 },
         { .reg = 0x00009888, .val = 0x080F7000 },
         { .reg = 0x00009888, .val = 0x0A0F6000 },
         { .reg = 0x00009888, .val = 0x10120E31 },
         { .reg = 0x00009888, .val = 0x02120000 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x001300A0 },
         { .reg = 0x00009888, .val = 0x02137C00 },
         { .reg = 0x00009888, .val = 0x00140050 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x00160050 },
         { .reg = 0x00009888, .val = 0x02165400 },
         { .reg = 0x00009888, .val = 0x001700A0 },
         { .reg = 0x00009888, .val = 0x02100020 },
         { .reg = 0x00009888, .val = 0x12100037 },
         { .reg = 0x00009888, .val = 0x00100000 },
         { .reg = 0x00009888, .val = 0x000CE00F },
         { .reg = 0x00009888, .val = 0x020E0200 },
         { .reg = 0x00009888, .val = 0x040E7D00 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000EE00C },
         { .reg = 0x00009888, .val = 0x000D0050 },
         { .reg = 0x00009888, .val = 0x000F0200 },
         { .reg = 0x00009888, .val = 0x040F07D0 },
         { .reg = 0x00009888, .val = 0x000600AA },
         { .reg = 0x00009888, .val = 0x0206A800 },
         { .reg = 0x00009888, .val = 0x000100AA },
         { .reg = 0x00009888, .val = 0x0201A800 },
         { .reg = 0x00009888, .val = 0x4E010060 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009888, .val = 0x58010006 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__rasterizer_and_pixel_backend1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__rasterizer_and_pixel_backend1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max,mtlgt2__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend1__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 261, 28, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend1__rasterizer0_output_ready__read);
      }

      intel_perf_query_add_counter_float(query, 360, 32, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend1__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 361, 36, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend1__pixel_data01_ready__read);

      intel_perf_query_add_counter_float(query, 5694, 40, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend1__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 5695, 44, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend1__pixel_values00_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_rasterizer_and_pixel_backend2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Metric set RasterizerAndPixelBackend2";
   query->symbol_name = "RasterizerAndPixelBackend2";
   query->guid = "787c682f-68be-4a64-b998-77d8a30b4ea6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x161224C0 },
         { .reg = 0x00009888, .val = 0x24106000 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x0A0E7000 },
         { .reg = 0x00009888, .val = 0x0C0E6000 },
         { .reg = 0x00009888, .val = 0x080F701F },
         { .reg = 0x00009888, .val = 0x0A0F6000 },
         { .reg = 0x00009888, .val = 0x10120C40 },
         { .reg = 0x00009888, .val = 0x12120038 },
         { .reg = 0x00009888, .val = 0x02120000 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x00132815 },
         { .reg = 0x00009888, .val = 0x0213F000 },
         { .reg = 0x00009888, .val = 0x00141400 },
         { .reg = 0x00009888, .val = 0x00151400 },
         { .reg = 0x00009888, .val = 0x00161415 },
         { .reg = 0x00009888, .val = 0x02165000 },
         { .reg = 0x00009888, .val = 0x00172800 },
         { .reg = 0x00009888, .val = 0x021069A0 },
         { .reg = 0x00009888, .val = 0x04100FB5 },
         { .reg = 0x00009888, .val = 0x00100000 },
         { .reg = 0x00009888, .val = 0x000CC07F },
         { .reg = 0x00009888, .val = 0x020E0200 },
         { .reg = 0x00009888, .val = 0x060E0400 },
         { .reg = 0x00009888, .val = 0x080E001F },
         { .reg = 0x00009888, .val = 0x000EC067 },
         { .reg = 0x00009888, .val = 0x000D1400 },
         { .reg = 0x00009888, .val = 0x000F0200 },
         { .reg = 0x00009888, .val = 0x060F0400 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x00062AAA },
         { .reg = 0x00009888, .val = 0x0206A000 },
         { .reg = 0x00009888, .val = 0x00012AAA },
         { .reg = 0x00009888, .val = 0x0201A000 },
         { .reg = 0x00009888, .val = 0x4E010040 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010804 },
         { .reg = 0x00009888, .val = 0x5A010060 },
         { .reg = 0x00009888, .val = 0x5C010006 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x54010600 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFE7 },
         { .reg = 0x0000D950, .val = 0x00000300 },
         { .reg = 0x0000D954, .val = 0x0000FF9F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__rasterizer_and_pixel_backend2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__rasterizer_and_pixel_backend2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max,mtlgt2__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend2__gpu_busy__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 266, 28, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend2__rasterizer0_input_available__read);
      }

      intel_perf_query_add_counter_float(query, 360, 32, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend2__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 361, 36, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend2__pixel_data01_ready__read);

      intel_perf_query_add_counter_float(query, 5694, 40, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend2__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 5695, 44, percentage_max_float,mtlgt2__rasterizer_and_pixel_backend2__pixel_values00_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_render_pipe_profile_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile";
   query->guid = "1269ddfd-22a6-47ca-9a1a-dc37b8c38490";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1807001F },
         { .reg = 0x00009888, .val = 0x02043000 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x16070002 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1A150000 },
         { .reg = 0x00009888, .val = 0x221503C0 },
         { .reg = 0x00009888, .val = 0x24150000 },
         { .reg = 0x00009888, .val = 0x161601F0 },
         { .reg = 0x00009888, .val = 0x16170640 },
         { .reg = 0x00009888, .val = 0x0C170002 },
         { .reg = 0x00009888, .val = 0x1418001F },
         { .reg = 0x00009888, .val = 0x0A180000 },
         { .reg = 0x00009888, .val = 0x140E2400 },
         { .reg = 0x00009888, .val = 0x120F2400 },
         { .reg = 0x00009888, .val = 0x0013AAA8 },
         { .reg = 0x00009888, .val = 0x021382AA },
         { .reg = 0x00009888, .val = 0x00145554 },
         { .reg = 0x00009888, .val = 0x02144155 },
         { .reg = 0x00009888, .val = 0x04150003 },
         { .reg = 0x00009888, .val = 0x06150020 },
         { .reg = 0x00009888, .val = 0x0A150003 },
         { .reg = 0x00009888, .val = 0x0E150AE3 },
         { .reg = 0x00009888, .val = 0x10150001 },
         { .reg = 0x00009888, .val = 0x12150880 },
         { .reg = 0x00009888, .val = 0x14150029 },
         { .reg = 0x00009888, .val = 0x00150544 },
         { .reg = 0x00009888, .val = 0x02154014 },
         { .reg = 0x00009888, .val = 0x04160200 },
         { .reg = 0x00009888, .val = 0x06160025 },
         { .reg = 0x00009888, .val = 0x00165554 },
         { .reg = 0x00009888, .val = 0x02164155 },
         { .reg = 0x00009888, .val = 0x04170000 },
         { .reg = 0x00009888, .val = 0x0A170880 },
         { .reg = 0x00009888, .val = 0x10170840 },
         { .reg = 0x00009888, .val = 0x00170044 },
         { .reg = 0x00009888, .val = 0x02178004 },
         { .reg = 0x00009888, .val = 0x00180002 },
         { .reg = 0x00009888, .val = 0x02180010 },
         { .reg = 0x00009888, .val = 0x04180032 },
         { .reg = 0x00009888, .val = 0x06180003 },
         { .reg = 0x00009888, .val = 0x0C180007 },
         { .reg = 0x00009888, .val = 0x000CBFFF },
         { .reg = 0x00009888, .val = 0x020E0004 },
         { .reg = 0x00009888, .val = 0x100E01C0 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000E9FFF },
         { .reg = 0x00009888, .val = 0x020D4000 },
         { .reg = 0x00009888, .val = 0x000F0004 },
         { .reg = 0x00009888, .val = 0x100F01C0 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x02068AAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201BAAA },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010401 },
         { .reg = 0x00009888, .val = 0x5A010010 },
         { .reg = 0x00009888, .val = 0x5C010201 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010010 },
         { .reg = 0x00009888, .val = 0x50010401 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010E06 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__render_pipe_profile__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__render_pipe_profile__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__render_pipe_profile__avg_gpu_core_frequency__max,mtlgt2__render_pipe_profile__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__render_pipe_profile__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 5696, 28, percentage_max_float,mtlgt2__render_pipe_profile__vf0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5697, 32, percentage_max_float,mtlgt2__render_pipe_profile__vs0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5698, 36, percentage_max_float,mtlgt2__render_pipe_profile__cl0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5699, 40, percentage_max_float,mtlgt2__render_pipe_profile__hs0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5700, 44, percentage_max_float,mtlgt2__render_pipe_profile__ds0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5701, 48, percentage_max_float,mtlgt2__render_pipe_profile__gs0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5702, 52, percentage_max_float,mtlgt2__render_pipe_profile__sf0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5703, 56, percentage_max_float,mtlgt2__render_pipe_profile__so0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5704, 60, percentage_max_float,mtlgt2__render_pipe_profile__cl0_stall__read);

      intel_perf_query_add_counter_float(query, 5705, 64, percentage_max_float,mtlgt2__render_pipe_profile__hs0_stall__read);

      intel_perf_query_add_counter_float(query, 5706, 68, percentage_max_float,mtlgt2__render_pipe_profile__ds0_stall__read);

      intel_perf_query_add_counter_float(query, 5707, 72, percentage_max_float,mtlgt2__render_pipe_profile__sf0_stall__read);

      intel_perf_query_add_counter_float(query, 5708, 76, percentage_max_float,mtlgt2__render_pipe_profile__so0_stall__read);

      intel_perf_query_add_counter_float(query, 5709, 80, percentage_max_float,mtlgt2__render_pipe_profile__hi_depth00_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5710, 84, percentage_max_float,mtlgt2__render_pipe_profile__hi_depth01_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5711, 88, percentage_max_float,mtlgt2__render_pipe_profile__bc00_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Sampler_Slice0";
   query->symbol_name = "Sampler";
   query->guid = "3c304c3b-9ada-4d92-9b54-34ec4e70aea6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1A010013 },
         { .reg = 0x00009888, .val = 0x14032C00 },
         { .reg = 0x00009888, .val = 0x02012000 },
         { .reg = 0x00009888, .val = 0x14010024 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02027030 },
         { .reg = 0x00009888, .val = 0x0E030580 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02045090 },
         { .reg = 0x00009888, .val = 0x02083030 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1A010013 },
         { .reg = 0x00009888, .val = 0x14032C00 },
         { .reg = 0x00009888, .val = 0x02012000 },
         { .reg = 0x00009888, .val = 0x12010900 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02021000 },
         { .reg = 0x00009888, .val = 0x0E030016 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02041020 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1A010013 },
         { .reg = 0x00009888, .val = 0x14032C00 },
         { .reg = 0x00009888, .val = 0x02012000 },
         { .reg = 0x00009888, .val = 0x12010024 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02020703 },
         { .reg = 0x00009888, .val = 0x0C030580 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02040509 },
         { .reg = 0x00009888, .val = 0x02080303 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1A010013 },
         { .reg = 0x00009888, .val = 0x14032C00 },
         { .reg = 0x00009888, .val = 0x02012000 },
         { .reg = 0x00009888, .val = 0x10010900 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02020100 },
         { .reg = 0x00009888, .val = 0x0C030016 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02040102 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02130A0A },
         { .reg = 0x00009888, .val = 0x02140505 },
         { .reg = 0x00009888, .val = 0x02150505 },
         { .reg = 0x00009888, .val = 0x02160505 },
         { .reg = 0x00009888, .val = 0x02170A0A },
         { .reg = 0x00009888, .val = 0x000C3300 },
         { .reg = 0x00009888, .val = 0x000E3300 },
         { .reg = 0x00009888, .val = 0x020D0A0A },
         { .reg = 0x00009888, .val = 0x02060A0A },
         { .reg = 0x00009888, .val = 0x0201FAFA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010200 },
         { .reg = 0x00009888, .val = 0x62010040 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x5001042A },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__sampler__avg_gpu_core_frequency__max,mtlgt2__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__sampler__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5712, 28, percentage_max_float,mtlgt2__sampler__sampler00_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5713, 32, percentage_max_float,mtlgt2__sampler__sampler01_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5714, 36, percentage_max_float,mtlgt2__sampler__sampler02_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5715, 40, percentage_max_float,mtlgt2__sampler__sampler03_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5716, 44, percentage_max_float,mtlgt2__sampler__sampler00_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5717, 48, percentage_max_float,mtlgt2__sampler__sampler01_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5718, 52, percentage_max_float,mtlgt2__sampler__sampler02_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5719, 56, percentage_max_float,mtlgt2__sampler__sampler03_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_tdl1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "TDL1";
   query->symbol_name = "TDL1";
   query->guid = "616fc1b0-53bb-4411-93b0-b34ab2b0bfb8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x2C070400 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0204FF55 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x080708E2 },
         { .reg = 0x00009888, .val = 0x0A070821 },
         { .reg = 0x00009888, .val = 0x14070CB3 },
         { .reg = 0x00009888, .val = 0x16070C31 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x2C070400 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x020400FF },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x0C0708E2 },
         { .reg = 0x00009888, .val = 0x0E070821 },
         { .reg = 0x00009888, .val = 0x10070CB3 },
         { .reg = 0x00009888, .val = 0x12070C31 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00078000 },
         { .reg = 0x0000D954, .val = 0x00000FFF },
         { .reg = 0x0000D958, .val = 0x00000180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00007800 },
         { .reg = 0x0000D96C, .val = 0x0000F0FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__tdl1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__tdl1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__tdl1__avg_gpu_core_frequency__max,mtlgt2__tdl1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__tdl1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5720, 28, percentage_max_float,mtlgt2__tdl1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5721, 32, percentage_max_float,mtlgt2__tdl1__ps_thread00_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5722, 36, percentage_max_float,mtlgt2__tdl1__thread_header00_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5723, 40, percentage_max_float,mtlgt2__tdl1__thread_header00_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5724, 44, percentage_max_float,mtlgt2__tdl1__thread_header00_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5725, 48, percentage_max_float,mtlgt2__tdl1__thread_header00_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5726, 52, percentage_max_float,mtlgt2__tdl1__thread_header00_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5727, 56, percentage_max_float,mtlgt2__tdl1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5728, 60, percentage_max_float,mtlgt2__tdl1__ps_thread01_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5729, 64, percentage_max_float,mtlgt2__tdl1__thread_header01_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5730, 68, percentage_max_float,mtlgt2__tdl1__thread_header01_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5731, 72, percentage_max_float,mtlgt2__tdl1__thread_header01_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5732, 76, percentage_max_float,mtlgt2__tdl1__thread_header01_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5733, 80, percentage_max_float,mtlgt2__tdl1__thread_header01_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_tdl2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "TDL2";
   query->symbol_name = "TDL2";
   query->guid = "952fa513-550e-49bc-a355-22fadbea5455";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x2C070400 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x0204FF55 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x080708E2 },
         { .reg = 0x00009888, .val = 0x0A070821 },
         { .reg = 0x00009888, .val = 0x14070CB3 },
         { .reg = 0x00009888, .val = 0x16070C31 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x2C070400 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x020400FF },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x0C0708E2 },
         { .reg = 0x00009888, .val = 0x0E070821 },
         { .reg = 0x00009888, .val = 0x10070CB3 },
         { .reg = 0x00009888, .val = 0x12070C31 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00078000 },
         { .reg = 0x0000D954, .val = 0x00000FFF },
         { .reg = 0x0000D958, .val = 0x00000180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00007800 },
         { .reg = 0x0000D96C, .val = 0x0000F0FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__tdl2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__tdl2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__tdl2__avg_gpu_core_frequency__max,mtlgt2__tdl2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt2__tdl2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5734, 28, percentage_max_float,mtlgt2__tdl2__non_ps_thread02_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5735, 32, percentage_max_float,mtlgt2__tdl2__ps_thread02_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5736, 36, percentage_max_float,mtlgt2__tdl2__thread_header02_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5737, 40, percentage_max_float,mtlgt2__tdl2__thread_header02_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5738, 44, percentage_max_float,mtlgt2__tdl2__thread_header02_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5739, 48, percentage_max_float,mtlgt2__tdl2__thread_header02_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5740, 52, percentage_max_float,mtlgt2__tdl2__thread_header02_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5741, 56, percentage_max_float,mtlgt2__tdl2__non_ps_thread03_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5742, 60, percentage_max_float,mtlgt2__tdl2__ps_thread03_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5743, 64, percentage_max_float,mtlgt2__tdl2__thread_header03_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5744, 68, percentage_max_float,mtlgt2__tdl2__thread_header03_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5745, 72, percentage_max_float,mtlgt2__tdl2__thread_header03_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5746, 76, percentage_max_float,mtlgt2__tdl2__thread_header03_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5747, 80, percentage_max_float,mtlgt2__tdl2__thread_header03_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "d0ed8afd-ad64-4774-8788-1a15f4ab7829";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x46020000 },
         { .reg = 0x00009888, .val = 0x46010000 },
         { .reg = 0x00009888, .val = 0x0802000E },
         { .reg = 0x00009888, .val = 0x18020033 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x0801000C },
         { .reg = 0x00009888, .val = 0x16010DC0 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x54010200 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__test_oa__avg_gpu_core_frequency__max,mtlgt2__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,mtlgt2__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,mtlgt2__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,mtlgt2__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,mtlgt2__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 415, 56, NULL,mtlgt2__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 416, 64, NULL,mtlgt2__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 417, 72, NULL,mtlgt2__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 418, 80, NULL,mtlgt2__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 488, 88, NULL,mtlgt2__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 489, 96, NULL,mtlgt2__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext1";
   query->symbol_name = "Ext1";
   query->guid = "fc82db3d-d6a7-413a-8349-b31f02251d2f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C070007 },
         { .reg = 0x00009888, .val = 0x18080007 },
         { .reg = 0x00009888, .val = 0x00065500 },
         { .reg = 0x00009888, .val = 0x02065555 },
         { .reg = 0x00009888, .val = 0x0001AA00 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x04070076 },
         { .reg = 0x00009888, .val = 0x0C070180 },
         { .reg = 0x00009888, .val = 0x0E070380 },
         { .reg = 0x00009888, .val = 0x12070147 },
         { .reg = 0x00009888, .val = 0x140703C0 },
         { .reg = 0x00009888, .val = 0x16070340 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00071100 },
         { .reg = 0x00009888, .val = 0x02071105 },
         { .reg = 0x00009888, .val = 0x00080076 },
         { .reg = 0x00009888, .val = 0x08080006 },
         { .reg = 0x00009888, .val = 0x0A08000E },
         { .reg = 0x00009888, .val = 0x0C080147 },
         { .reg = 0x00009888, .val = 0x1008000F },
         { .reg = 0x00009888, .val = 0x1208000D },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1__avg_gpu_core_frequency__max,mtlgt2__ext1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5748, 24, NULL,mtlgt2__ext1__gpu_memory_byte_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 5749, 32, NULL,mtlgt2__ext1__gpu_memory_byte_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 5750, 40, NULL,mtlgt2__ext1__gpu_memory_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 5751, 48, NULL,mtlgt2__ext1__gpu_memory_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 5752, 56, NULL,mtlgt2__ext1__gpu_memory_write__read);

      intel_perf_query_add_counter_uint64(query, 5753, 64, NULL,mtlgt2__ext1__gpu_memory_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 5754, 72, NULL,mtlgt2__ext1__gpu_memory_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 5755, 80, NULL,mtlgt2__ext1__gpu_memory_read__read);

      intel_perf_query_add_counter_uint64(query, 5756, 88, NULL,mtlgt2__ext1__gpu_memory_byte_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 5757, 96, NULL,mtlgt2__ext1__gpu_memory_byte_read_sqidi1__read);

      intel_perf_query_add_counter_float(query, 5758, 104, percentage_max_float,mtlgt2__ext1__gpu_memory_active_sqidi0__read);

      intel_perf_query_add_counter_float(query, 5759, 108, percentage_max_float,mtlgt2__ext1__gpu_memory_active_sqidi1__read);

      intel_perf_query_add_counter_float(query, 5760, 112, NULL,mtlgt2__ext1__gpu_memory_byte_read_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 5761, 116, NULL,mtlgt2__ext1__gpu_memory_byte_read_bw_sqidi1__read);

      intel_perf_query_add_counter_float(query, 5762, 120, NULL,mtlgt2__ext1__gpu_memory_byte_write_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 5763, 124, NULL,mtlgt2__ext1__gpu_memory_byte_write_bw_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext4";
   query->symbol_name = "Ext4";
   query->guid = "3479a81d-9017-4930-af0c-14f7fabadb38";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04011000 },
         { .reg = 0x00009888, .val = 0x06016000 },
         { .reg = 0x00009888, .val = 0x04411000 },
         { .reg = 0x00009888, .val = 0x06416000 },
         { .reg = 0x00009888, .val = 0x04811000 },
         { .reg = 0x00009888, .val = 0x06816000 },
         { .reg = 0x00009888, .val = 0x04C11000 },
         { .reg = 0x00009888, .val = 0x06C16000 },
         { .reg = 0x00009888, .val = 0x00010010 },
         { .reg = 0x00009888, .val = 0x0C010005 },
         { .reg = 0x00009888, .val = 0x12010340 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410010 },
         { .reg = 0x00009888, .val = 0x0C410140 },
         { .reg = 0x00009888, .val = 0x1241000D },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810010 },
         { .reg = 0x00009888, .val = 0x0E810005 },
         { .reg = 0x00009888, .val = 0x10810340 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10010 },
         { .reg = 0x00009888, .val = 0x0EC10140 },
         { .reg = 0x00009888, .val = 0x10C1000D },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124200 },
         { .reg = 0x00009888, .val = 0x0213BAAE },
         { .reg = 0x00009888, .val = 0x02144961 },
         { .reg = 0x00009888, .val = 0x021583C2 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x021A2008 },
         { .reg = 0x00009888, .val = 0x001B2400 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext4__avg_gpu_core_frequency__max,mtlgt2__ext4__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5764, 24, NULL,mtlgt2__ext4__l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5765, 32, NULL,mtlgt2__ext4__l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5766, 40, NULL,mtlgt2__ext4__l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5767, 48, NULL,mtlgt2__ext4__l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5768, 56, NULL,mtlgt2__ext4__l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5769, 64, NULL,mtlgt2__ext4__l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5770, 72, NULL,mtlgt2__ext4__l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5771, 80, NULL,mtlgt2__ext4__l3_write_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext5";
   query->symbol_name = "Ext5";
   query->guid = "e4701256-cd06-48f7-a005-d4d1f9e895c1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x0C012000 },
         { .reg = 0x00009888, .val = 0x04410000 },
         { .reg = 0x00009888, .val = 0x0C412000 },
         { .reg = 0x00009888, .val = 0x04810000 },
         { .reg = 0x00009888, .val = 0x0C8122C0 },
         { .reg = 0x00009888, .val = 0x04C10000 },
         { .reg = 0x00009888, .val = 0x0CC1200B },
         { .reg = 0x00009888, .val = 0x00010004 },
         { .reg = 0x00009888, .val = 0x0A010040 },
         { .reg = 0x00009888, .val = 0x0E0102C0 },
         { .reg = 0x00009888, .val = 0x12010300 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410004 },
         { .reg = 0x00009888, .val = 0x0A410001 },
         { .reg = 0x00009888, .val = 0x0E41000B },
         { .reg = 0x00009888, .val = 0x1241000C },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810004 },
         { .reg = 0x00009888, .val = 0x08810040 },
         { .reg = 0x00009888, .val = 0x10810300 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10004 },
         { .reg = 0x00009888, .val = 0x08C10001 },
         { .reg = 0x00009888, .val = 0x10C1000C },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124440 },
         { .reg = 0x00009888, .val = 0x0013BA00 },
         { .reg = 0x00009888, .val = 0x0213BABA },
         { .reg = 0x00009888, .val = 0x00144900 },
         { .reg = 0x00009888, .val = 0x02144949 },
         { .reg = 0x00009888, .val = 0x00158300 },
         { .reg = 0x00009888, .val = 0x02158383 },
         { .reg = 0x00009888, .val = 0x00165500 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x000CFFF0 },
         { .reg = 0x00009888, .val = 0x000EFFF0 },
         { .reg = 0x00009888, .val = 0x001A2000 },
         { .reg = 0x00009888, .val = 0x021A2020 },
         { .reg = 0x00009888, .val = 0x001B2220 },
         { .reg = 0x00009888, .val = 0x0006AA00 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AA00 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext5__avg_gpu_core_frequency__max,mtlgt2__ext5__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5772, 24, NULL,mtlgt2__ext5__dataport_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5773, 32, NULL,mtlgt2__ext5__dataport_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5774, 40, NULL,mtlgt2__ext5__dataport_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5775, 48, NULL,mtlgt2__ext5__dataport_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5776, 56, NULL,mtlgt2__ext5__dataport_l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5777, 64, NULL,mtlgt2__ext5__dataport_l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5778, 72, NULL,mtlgt2__ext5__dataport_l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5779, 80, NULL,mtlgt2__ext5__dataport_l3_write_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5780, 88, NULL,mtlgt2__ext5__l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5781, 96, NULL,mtlgt2__ext5__l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5782, 104, NULL,mtlgt2__ext5__l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5783, 112, NULL,mtlgt2__ext5__l3_hit_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext7";
   query->symbol_name = "Ext7";
   query->guid = "3e47d0e8-5414-4496-8746-37e36fefc777";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x00023000 },
         { .reg = 0x00009888, .val = 0x0A030D00 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00049000 },
         { .reg = 0x00009888, .val = 0x00083000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x0A030034 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00042000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x00020300 },
         { .reg = 0x00009888, .val = 0x08030D00 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040900 },
         { .reg = 0x00009888, .val = 0x00080300 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x08030034 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x0C010000 },
         { .reg = 0x00009888, .val = 0x04410000 },
         { .reg = 0x00009888, .val = 0x0C410000 },
         { .reg = 0x00009888, .val = 0x04810000 },
         { .reg = 0x00009888, .val = 0x0C810040 },
         { .reg = 0x00009888, .val = 0x04C10000 },
         { .reg = 0x00009888, .val = 0x0CC10001 },
         { .reg = 0x00009888, .val = 0x00010004 },
         { .reg = 0x00009888, .val = 0x0E010040 },
         { .reg = 0x00009888, .val = 0x12010380 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410004 },
         { .reg = 0x00009888, .val = 0x0E410001 },
         { .reg = 0x00009888, .val = 0x1241000E },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810004 },
         { .reg = 0x00009888, .val = 0x10810380 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10004 },
         { .reg = 0x00009888, .val = 0x10C1000E },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124400 },
         { .reg = 0x00009888, .val = 0x00130A00 },
         { .reg = 0x00009888, .val = 0x0213BABA },
         { .reg = 0x00009888, .val = 0x00140500 },
         { .reg = 0x00009888, .val = 0x02144949 },
         { .reg = 0x00009888, .val = 0x00150500 },
         { .reg = 0x00009888, .val = 0x02158383 },
         { .reg = 0x00009888, .val = 0x00160500 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x00170A00 },
         { .reg = 0x00009888, .val = 0x000CFF30 },
         { .reg = 0x00009888, .val = 0x000EFF30 },
         { .reg = 0x00009888, .val = 0x000D0A00 },
         { .reg = 0x00009888, .val = 0x021A2020 },
         { .reg = 0x00009888, .val = 0x001B2200 },
         { .reg = 0x00009888, .val = 0x00060A00 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FA00 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010290 },
         { .reg = 0x00009888, .val = 0x60010E01 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010070 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010E07 },
         { .reg = 0x00009888, .val = 0x52010070 },
         { .reg = 0x00009888, .val = 0x54010E07 },
         { .reg = 0x00009888, .val = 0x56010070 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext7__avg_gpu_core_frequency__max,mtlgt2__ext7__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5784, 24, NULL,mtlgt2__ext7__sampler_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5785, 32, NULL,mtlgt2__ext7__sampler_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5786, 40, NULL,mtlgt2__ext7__sampler_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5787, 48, NULL,mtlgt2__ext7__sampler_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5788, 56, NULL,mtlgt2__ext7__sampler_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5789, 64, NULL,mtlgt2__ext7__sampler_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5790, 72, NULL,mtlgt2__ext7__sampler_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5791, 80, NULL,mtlgt2__ext7__sampler_l3_hit_l3_bank3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5792, 88, percentage_max_float,mtlgt2__ext7__sampler_busy_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5793, 92, percentage_max_float,mtlgt2__ext7__sampler_busy_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5794, 96, percentage_max_float,mtlgt2__ext7__sampler_busy_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5795, 100, percentage_max_float,mtlgt2__ext7__sampler_busy_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext8";
   query->symbol_name = "Ext8";
   query->guid = "5aa36c1f-c6da-45ab-ab21-397d9a4b6a06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x0C010000 },
         { .reg = 0x00009888, .val = 0x04410000 },
         { .reg = 0x00009888, .val = 0x0C410000 },
         { .reg = 0x00009888, .val = 0x04810000 },
         { .reg = 0x00009888, .val = 0x0C810080 },
         { .reg = 0x00009888, .val = 0x04C10000 },
         { .reg = 0x00009888, .val = 0x0CC10002 },
         { .reg = 0x00009888, .val = 0x00010004 },
         { .reg = 0x00009888, .val = 0x0E010080 },
         { .reg = 0x00009888, .val = 0x120103C0 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410004 },
         { .reg = 0x00009888, .val = 0x0E410002 },
         { .reg = 0x00009888, .val = 0x1241000F },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810004 },
         { .reg = 0x00009888, .val = 0x108103C0 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10004 },
         { .reg = 0x00009888, .val = 0x10C1000F },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124400 },
         { .reg = 0x00009888, .val = 0x0213BABA },
         { .reg = 0x00009888, .val = 0x02144949 },
         { .reg = 0x00009888, .val = 0x02158383 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x021A2020 },
         { .reg = 0x00009888, .val = 0x001B2200 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext8__avg_gpu_core_frequency__max,mtlgt2__ext8__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5796, 24, NULL,mtlgt2__ext8__icache_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5797, 32, NULL,mtlgt2__ext8__icache_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5798, 40, NULL,mtlgt2__ext8__icache_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5799, 48, NULL,mtlgt2__ext8__icache_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5800, 56, NULL,mtlgt2__ext8__icache_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5801, 64, NULL,mtlgt2__ext8__icache_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5802, 72, NULL,mtlgt2__ext8__icache_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5803, 80, NULL,mtlgt2__ext8__icache_l3_hit_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext10";
   query->symbol_name = "Ext10";
   query->guid = "1df59d79-16d8-471c-b3da-f0f62862f89e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04012000 },
         { .reg = 0x00009888, .val = 0x0C010000 },
         { .reg = 0x00009888, .val = 0x04412000 },
         { .reg = 0x00009888, .val = 0x0C410000 },
         { .reg = 0x00009888, .val = 0x04812000 },
         { .reg = 0x00009888, .val = 0x0C810300 },
         { .reg = 0x00009888, .val = 0x04C12000 },
         { .reg = 0x00009888, .val = 0x0CC1000C },
         { .reg = 0x00009888, .val = 0x00010040 },
         { .reg = 0x00009888, .val = 0x0A0101C0 },
         { .reg = 0x00009888, .val = 0x0E010300 },
         { .reg = 0x00009888, .val = 0x12010200 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410040 },
         { .reg = 0x00009888, .val = 0x0A410007 },
         { .reg = 0x00009888, .val = 0x0E41000C },
         { .reg = 0x00009888, .val = 0x12410008 },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810040 },
         { .reg = 0x00009888, .val = 0x088101C0 },
         { .reg = 0x00009888, .val = 0x10810200 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10040 },
         { .reg = 0x00009888, .val = 0x08C10007 },
         { .reg = 0x00009888, .val = 0x10C10008 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124440 },
         { .reg = 0x00009888, .val = 0x0013BA00 },
         { .reg = 0x00009888, .val = 0x0213BABA },
         { .reg = 0x00009888, .val = 0x00144900 },
         { .reg = 0x00009888, .val = 0x02144949 },
         { .reg = 0x00009888, .val = 0x00158300 },
         { .reg = 0x00009888, .val = 0x02158383 },
         { .reg = 0x00009888, .val = 0x00165500 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x000CFFF0 },
         { .reg = 0x00009888, .val = 0x000EFFF0 },
         { .reg = 0x00009888, .val = 0x001A2000 },
         { .reg = 0x00009888, .val = 0x021A2020 },
         { .reg = 0x00009888, .val = 0x001B2220 },
         { .reg = 0x00009888, .val = 0x0006AA00 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AA00 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext10__avg_gpu_core_frequency__max,mtlgt2__ext10__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5804, 24, NULL,mtlgt2__ext10__dataport_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5805, 32, NULL,mtlgt2__ext10__dataport_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5806, 40, NULL,mtlgt2__ext10__dataport_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5807, 48, NULL,mtlgt2__ext10__dataport_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5808, 56, NULL,mtlgt2__ext10__color_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5809, 64, NULL,mtlgt2__ext10__color_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5810, 72, NULL,mtlgt2__ext10__color_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5811, 80, NULL,mtlgt2__ext10__color_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5812, 88, NULL,mtlgt2__ext10__z_l3_access_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5813, 96, NULL,mtlgt2__ext10__z_l3_access_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5814, 104, NULL,mtlgt2__ext10__z_l3_access_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5815, 112, NULL,mtlgt2__ext10__z_l3_access_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext11";
   query->symbol_name = "Ext11";
   query->guid = "d05d3d84-ba16-41b5-b825-5a3d2aaabbfc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04011000 },
         { .reg = 0x00009888, .val = 0x0C010000 },
         { .reg = 0x00009888, .val = 0x04411000 },
         { .reg = 0x00009888, .val = 0x0C410000 },
         { .reg = 0x00009888, .val = 0x04811000 },
         { .reg = 0x00009888, .val = 0x0C810100 },
         { .reg = 0x00009888, .val = 0x04C11000 },
         { .reg = 0x00009888, .val = 0x0CC10004 },
         { .reg = 0x00009888, .val = 0x00010040 },
         { .reg = 0x00009888, .val = 0x0E010100 },
         { .reg = 0x00009888, .val = 0x12010340 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410040 },
         { .reg = 0x00009888, .val = 0x0E410004 },
         { .reg = 0x00009888, .val = 0x1241000D },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810040 },
         { .reg = 0x00009888, .val = 0x10810340 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10040 },
         { .reg = 0x00009888, .val = 0x10C1000D },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124400 },
         { .reg = 0x00009888, .val = 0x0213BABA },
         { .reg = 0x00009888, .val = 0x02144949 },
         { .reg = 0x00009888, .val = 0x02158383 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x021A2020 },
         { .reg = 0x00009888, .val = 0x001B2200 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext11__avg_gpu_core_frequency__max,mtlgt2__ext11__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5816, 24, NULL,mtlgt2__ext11__z_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5817, 32, NULL,mtlgt2__ext11__z_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5818, 40, NULL,mtlgt2__ext11__z_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5819, 48, NULL,mtlgt2__ext11__z_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5820, 56, NULL,mtlgt2__ext11__l3_atomic_access_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5821, 64, NULL,mtlgt2__ext11__l3_atomic_access_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5822, 72, NULL,mtlgt2__ext11__l3_atomic_access_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5823, 80, NULL,mtlgt2__ext11__l3_atomic_access_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext12";
   query->symbol_name = "Ext12";
   query->guid = "a49e7038-1e78-4b49-bc55-e7e7d04e4074";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04011000 },
         { .reg = 0x00009888, .val = 0x04411000 },
         { .reg = 0x00009888, .val = 0x04811000 },
         { .reg = 0x00009888, .val = 0x04C11000 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x0E010180 },
         { .reg = 0x00009888, .val = 0x120101C0 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x0E410006 },
         { .reg = 0x00009888, .val = 0x12410007 },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x0C810180 },
         { .reg = 0x00009888, .val = 0x108101C0 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x0CC10006 },
         { .reg = 0x00009888, .val = 0x10C10007 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124400 },
         { .reg = 0x00009888, .val = 0x0213BABA },
         { .reg = 0x00009888, .val = 0x02144949 },
         { .reg = 0x00009888, .val = 0x02158383 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x021A2020 },
         { .reg = 0x00009888, .val = 0x001B2200 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext12__avg_gpu_core_frequency__max,mtlgt2__ext12__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5686, 24, percentage_max_float,mtlgt2__ext12__l3_input_available_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5687, 28, percentage_max_float,mtlgt2__ext12__l3_input_available_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5688, 32, percentage_max_float,mtlgt2__ext12__l3_input_available_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5689, 36, percentage_max_float,mtlgt2__ext12__l3_input_available_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5690, 40, percentage_max_float,mtlgt2__ext12__l3_output_ready_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5691, 44, percentage_max_float,mtlgt2__ext12__l3_output_ready_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5692, 48, percentage_max_float,mtlgt2__ext12__l3_output_ready_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5693, 52, percentage_max_float,mtlgt2__ext12__l3_output_ready_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext13";
   query->symbol_name = "Ext13";
   query->guid = "10f4cba5-2db8-46a9-a211-391dca810ea0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04013183 },
         { .reg = 0x00009888, .val = 0x0C011000 },
         { .reg = 0x00009888, .val = 0x04413000 },
         { .reg = 0x00009888, .val = 0x0C411000 },
         { .reg = 0x00009888, .val = 0x04813000 },
         { .reg = 0x00009888, .val = 0x0C811000 },
         { .reg = 0x00009888, .val = 0x04C13000 },
         { .reg = 0x00009888, .val = 0x0CC11000 },
         { .reg = 0x00009888, .val = 0x00010004 },
         { .reg = 0x00009888, .val = 0x120103C0 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410004 },
         { .reg = 0x00009888, .val = 0x06410183 },
         { .reg = 0x00009888, .val = 0x1241000F },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810004 },
         { .reg = 0x00009888, .val = 0x08810183 },
         { .reg = 0x00009888, .val = 0x108103C0 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10004 },
         { .reg = 0x00009888, .val = 0x0AC10183 },
         { .reg = 0x00009888, .val = 0x10C1000F },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0012400C },
         { .reg = 0x00009888, .val = 0x0013AAFA },
         { .reg = 0x00009888, .val = 0x0213BA00 },
         { .reg = 0x00009888, .val = 0x00145A05 },
         { .reg = 0x00009888, .val = 0x02144900 },
         { .reg = 0x00009888, .val = 0x0015F00A },
         { .reg = 0x00009888, .val = 0x02158300 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165500 },
         { .reg = 0x00009888, .val = 0x000CF0FF },
         { .reg = 0x00009888, .val = 0x000EF0FF },
         { .reg = 0x00009888, .val = 0x001A00A0 },
         { .reg = 0x00009888, .val = 0x021A2000 },
         { .reg = 0x00009888, .val = 0x001B2030 },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AA00 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AA00 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext13__avg_gpu_core_frequency__max,mtlgt2__ext13__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5824, 24, percentage_max_float,mtlgt2__ext13__l3_superq_full_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5825, 28, percentage_max_float,mtlgt2__ext13__l3_superq_full_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5826, 32, percentage_max_float,mtlgt2__ext13__l3_superq_full_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5827, 36, percentage_max_float,mtlgt2__ext13__l3_superq_full_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5828, 40, NULL,mtlgt2__ext13__color_l3_access_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5829, 48, NULL,mtlgt2__ext13__color_l3_access_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5830, 56, NULL,mtlgt2__ext13__color_l3_access_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5831, 64, NULL,mtlgt2__ext13__color_l3_access_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext14";
   query->symbol_name = "Ext14";
   query->guid = "36c1995a-e670-4c2a-ab94-74b9e7360fb2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x04011042 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x04411000 },
         { .reg = 0x00009888, .val = 0x06410080 },
         { .reg = 0x00009888, .val = 0x04811000 },
         { .reg = 0x00009888, .val = 0x06810000 },
         { .reg = 0x00009888, .val = 0x04C11000 },
         { .reg = 0x00009888, .val = 0x06C10000 },
         { .reg = 0x00009888, .val = 0x00010010 },
         { .reg = 0x00009888, .val = 0x12010200 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410010 },
         { .reg = 0x00009888, .val = 0x08410001 },
         { .reg = 0x00009888, .val = 0x12410008 },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810010 },
         { .reg = 0x00009888, .val = 0x0A810042 },
         { .reg = 0x00009888, .val = 0x0C810000 },
         { .reg = 0x00009888, .val = 0x10810200 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10010 },
         { .reg = 0x00009888, .val = 0x0CC10080 },
         { .reg = 0x00009888, .val = 0x0EC10001 },
         { .reg = 0x00009888, .val = 0x10C10008 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124038 },
         { .reg = 0x00009888, .val = 0x0013AFEA },
         { .reg = 0x00009888, .val = 0x0213BAAA },
         { .reg = 0x00009888, .val = 0x0014A015 },
         { .reg = 0x00009888, .val = 0x02144956 },
         { .reg = 0x00009888, .val = 0x0015002A },
         { .reg = 0x00009888, .val = 0x021583FC },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x001A0A80 },
         { .reg = 0x00009888, .val = 0x021A2000 },
         { .reg = 0x00009888, .val = 0x001B21C0 },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext14__avg_gpu_core_frequency__max,mtlgt2__ext14__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5832, 24, percentage_max_float,mtlgt2__ext14__l3_busy_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5833, 28, percentage_max_float,mtlgt2__ext14__l3_busy_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5834, 32, percentage_max_float,mtlgt2__ext14__l3_busy_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5835, 36, percentage_max_float,mtlgt2__ext14__l3_busy_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5836, 40, percentage_max_float,mtlgt2__ext14__l3_stall_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5837, 44, percentage_max_float,mtlgt2__ext14__l3_stall_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5838, 48, percentage_max_float,mtlgt2__ext14__l3_stall_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5839, 52, percentage_max_float,mtlgt2__ext14__l3_stall_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext17";
   query->symbol_name = "Ext17";
   query->guid = "a04168f6-637e-44af-a1b6-e5f005708df4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x2808005E },
         { .reg = 0x00009888, .val = 0x2C087800 },
         { .reg = 0x00009888, .val = 0x2E080002 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x0E080830 },
         { .reg = 0x00009888, .val = 0x16080B7D },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080F00 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x2808005E },
         { .reg = 0x00009888, .val = 0x2C087800 },
         { .reg = 0x00009888, .val = 0x2E080002 },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x0C080830 },
         { .reg = 0x00009888, .val = 0x14080B7D },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x2808005E },
         { .reg = 0x00009888, .val = 0x2C087800 },
         { .reg = 0x00009888, .val = 0x2E080002 },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x0A080830 },
         { .reg = 0x00009888, .val = 0x12080B7D },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008000F },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x2808005E },
         { .reg = 0x00009888, .val = 0x2C087800 },
         { .reg = 0x00009888, .val = 0x2E080002 },
         { .reg = 0x00009888, .val = 0x0002000F },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x08080830 },
         { .reg = 0x00009888, .val = 0x10080B7D },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x001300AA },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00140055 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00150055 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00160055 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x001700AA },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0F0F },
         { .reg = 0x00009888, .val = 0x000E0F0F },
         { .reg = 0x00009888, .val = 0x000D00AA },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x000600AA },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001FFAA },
         { .reg = 0x00009888, .val = 0x0201FFAA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010600 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010211 },
         { .reg = 0x00009888, .val = 0x60010001 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010090 },
         { .reg = 0x00009888, .val = 0x54010229 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext17__avg_gpu_core_frequency__max,mtlgt2__ext17__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5840, 24, percentage_max_float,mtlgt2__ext17__load_store_cache_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5841, 28, percentage_max_float,mtlgt2__ext17__load_store_cache_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5842, 32, percentage_max_float,mtlgt2__ext17__load_store_cache_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5843, 36, percentage_max_float,mtlgt2__ext17__load_store_cache_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5844, 40, percentage_max_float,mtlgt2__ext17__load_store_cache_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5845, 44, percentage_max_float,mtlgt2__ext17__load_store_cache_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5846, 48, percentage_max_float,mtlgt2__ext17__load_store_cache_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5847, 52, percentage_max_float,mtlgt2__ext17__load_store_cache_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext21";
   query->symbol_name = "Ext21";
   query->guid = "0486a0e0-3522-4689-bdf9-623603f8e3c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18080006 },
         { .reg = 0x00009888, .val = 0x1C081800 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x04080808 },
         { .reg = 0x00009888, .val = 0x0E080493 },
         { .reg = 0x00009888, .val = 0x16080200 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080F00 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18080006 },
         { .reg = 0x00009888, .val = 0x1C081800 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x04080808 },
         { .reg = 0x00009888, .val = 0x0C080493 },
         { .reg = 0x00009888, .val = 0x14080200 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18080006 },
         { .reg = 0x00009888, .val = 0x1C081800 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x04080808 },
         { .reg = 0x00009888, .val = 0x0A080493 },
         { .reg = 0x00009888, .val = 0x12080200 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008000F },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18080006 },
         { .reg = 0x00009888, .val = 0x1C081800 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x0002000F },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x04080808 },
         { .reg = 0x00009888, .val = 0x08080493 },
         { .reg = 0x00009888, .val = 0x10080200 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x001300AA },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00140055 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00150055 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00160055 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x001700AA },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0F0F },
         { .reg = 0x00009888, .val = 0x000E0F0F },
         { .reg = 0x00009888, .val = 0x000D00AA },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x000600AA },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001FFAA },
         { .reg = 0x00009888, .val = 0x0201FFAA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010600 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010211 },
         { .reg = 0x00009888, .val = 0x60010001 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010090 },
         { .reg = 0x00009888, .val = 0x54010229 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext21__avg_gpu_core_frequency__max,mtlgt2__ext21__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5848, 24, NULL,mtlgt2__ext21__load_store_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5849, 32, NULL,mtlgt2__ext21__load_store_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5850, 40, NULL,mtlgt2__ext21__load_store_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5851, 48, NULL,mtlgt2__ext21__load_store_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5852, 56, NULL,mtlgt2__ext21__load_store_cache_l3_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5853, 64, NULL,mtlgt2__ext21__load_store_cache_l3_read_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5854, 72, NULL,mtlgt2__ext21__load_store_cache_l3_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5855, 80, NULL,mtlgt2__ext21__load_store_cache_l3_read_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext23";
   query->symbol_name = "Ext23";
   query->guid = "b30ba7fb-fe8f-4e81-b271-3d6f52edc257";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x04080080 },
         { .reg = 0x00009888, .val = 0x080800C2 },
         { .reg = 0x00009888, .val = 0x0A0802CA },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x04080080 },
         { .reg = 0x00009888, .val = 0x0C0800C2 },
         { .reg = 0x00009888, .val = 0x0E0802CA },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080080 },
         { .reg = 0x00009888, .val = 0x100800C2 },
         { .reg = 0x00009888, .val = 0x120802CA },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x04080080 },
         { .reg = 0x00009888, .val = 0x140800C2 },
         { .reg = 0x00009888, .val = 0x160802CA },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext23__avg_gpu_core_frequency__max,mtlgt2__ext23__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5856, 24, NULL,mtlgt2__ext23__load_store_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5857, 32, NULL,mtlgt2__ext23__load_store_cache_hit_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5858, 40, NULL,mtlgt2__ext23__load_store_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5859, 48, NULL,mtlgt2__ext23__load_store_cache_hit_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext28";
   query->symbol_name = "Ext28";
   query->guid = "053ca218-0961-4bb2-b689-9fe2cb090fdc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x04080808 },
         { .reg = 0x00009888, .val = 0x0E080304 },
         { .reg = 0x00009888, .val = 0x16080515 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080F00 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x00020F00 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x04080808 },
         { .reg = 0x00009888, .val = 0x0C080304 },
         { .reg = 0x00009888, .val = 0x14080515 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x04080808 },
         { .reg = 0x00009888, .val = 0x0A080304 },
         { .reg = 0x00009888, .val = 0x12080515 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008000F },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x0002000F },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x04080808 },
         { .reg = 0x00009888, .val = 0x08080304 },
         { .reg = 0x00009888, .val = 0x10080515 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x001300AA },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00140055 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00150055 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00160055 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x001700AA },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0F0F },
         { .reg = 0x00009888, .val = 0x000E0F0F },
         { .reg = 0x00009888, .val = 0x000D00AA },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x000600AA },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001FFAA },
         { .reg = 0x00009888, .val = 0x0201FFAA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010600 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010211 },
         { .reg = 0x00009888, .val = 0x60010001 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010090 },
         { .reg = 0x00009888, .val = 0x54010229 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext28__avg_gpu_core_frequency__max,mtlgt2__ext28__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5860, 24, NULL,mtlgt2__ext28__load_store_cache_l3_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5861, 32, NULL,mtlgt2__ext28__load_store_cache_l3_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5862, 40, NULL,mtlgt2__ext28__load_store_cache_l3_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5863, 48, NULL,mtlgt2__ext28__load_store_cache_l3_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5864, 56, NULL,mtlgt2__ext28__load_store_cache_partial_write_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5865, 64, NULL,mtlgt2__ext28__load_store_cache_partial_write_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5866, 72, NULL,mtlgt2__ext28__load_store_cache_partial_write_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5867, 80, NULL,mtlgt2__ext28__load_store_cache_partial_write_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext31";
   query->symbol_name = "Ext31";
   query->guid = "7a4a45f1-e844-460b-8800-91b62eb47124";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x08080824 },
         { .reg = 0x00009888, .val = 0x0A080C34 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x0C080824 },
         { .reg = 0x00009888, .val = 0x0E080C34 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x10080824 },
         { .reg = 0x00009888, .val = 0x12080C34 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x14080824 },
         { .reg = 0x00009888, .val = 0x16080C34 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext31__avg_gpu_core_frequency__max,mtlgt2__ext31__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5868, 24, NULL,mtlgt2__ext31__xve_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5869, 32, NULL,mtlgt2__ext31__xve_load_store_cache_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5870, 40, NULL,mtlgt2__ext31__xve_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5871, 48, NULL,mtlgt2__ext31__xve_load_store_cache_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext35";
   query->symbol_name = "Ext35";
   query->guid = "fd99f6f4-d418-4d86-800b-52998df4eb00";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x08080823 },
         { .reg = 0x00009888, .val = 0x0A080C33 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x0C080823 },
         { .reg = 0x00009888, .val = 0x0E080C33 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x10080823 },
         { .reg = 0x00009888, .val = 0x12080C33 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x14080823 },
         { .reg = 0x00009888, .val = 0x16080C33 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext35__avg_gpu_core_frequency__max,mtlgt2__ext35__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5872, 24, NULL,mtlgt2__ext35__xve_load_store_cache_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5873, 32, NULL,mtlgt2__ext35__xve_load_store_cache_write_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5874, 40, NULL,mtlgt2__ext35__xve_load_store_cache_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5875, 48, NULL,mtlgt2__ext35__xve_load_store_cache_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext39";
   query->symbol_name = "Ext39";
   query->guid = "10f4436b-83c7-4e38-867d-82144311e412";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x08080A27 },
         { .reg = 0x00009888, .val = 0x0A080E37 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x0C080A27 },
         { .reg = 0x00009888, .val = 0x0E080E37 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x10080A27 },
         { .reg = 0x00009888, .val = 0x12080E37 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x14080A27 },
         { .reg = 0x00009888, .val = 0x16080E37 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext39__avg_gpu_core_frequency__max,mtlgt2__ext39__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5876, 24, NULL,mtlgt2__ext39__xve_load_store_cache_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5877, 32, NULL,mtlgt2__ext39__xve_load_store_cache_fence_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5878, 40, NULL,mtlgt2__ext39__xve_load_store_cache_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5879, 48, NULL,mtlgt2__ext39__xve_load_store_cache_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext43_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext43";
   query->symbol_name = "Ext43";
   query->guid = "ab8c937a-a24c-4b7b-94d2-7cdf4cf3829f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x080808A3 },
         { .reg = 0x00009888, .val = 0x0A080CE8 },
         { .reg = 0x00009888, .val = 0x0C080E32 },
         { .reg = 0x00009888, .val = 0x16080A79 },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x02080FFF },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x02020FFF },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040555 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x0E0808A3 },
         { .reg = 0x00009888, .val = 0x10080CE8 },
         { .reg = 0x00009888, .val = 0x12080E32 },
         { .reg = 0x00009888, .val = 0x14080A79 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010600 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext43__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext43__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext43__avg_gpu_core_frequency__max,mtlgt2__ext43__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5880, 24, NULL,mtlgt2__ext43__xve_load_store_cache_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5881, 32, NULL,mtlgt2__ext43__xve_load_store_cache_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5882, 40, NULL,mtlgt2__ext43__xve_load_store_cache_register_request_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5883, 48, NULL,mtlgt2__ext43__xve_load_store_cache_register_request_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext45";
   query->symbol_name = "Ext45";
   query->guid = "aa3ac820-b824-4681-94ff-3425eee63648";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x080808A3 },
         { .reg = 0x00009888, .val = 0x0A080CE8 },
         { .reg = 0x00009888, .val = 0x0C080E32 },
         { .reg = 0x00009888, .val = 0x16080A79 },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x02080FFF },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x02020FFF },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040555 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x0E0808A3 },
         { .reg = 0x00009888, .val = 0x10080CE8 },
         { .reg = 0x00009888, .val = 0x12080E32 },
         { .reg = 0x00009888, .val = 0x14080A79 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010600 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext45__avg_gpu_core_frequency__max,mtlgt2__ext45__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5884, 24, NULL,mtlgt2__ext45__xve_load_store_cache_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5885, 32, NULL,mtlgt2__ext45__xve_load_store_cache_atomic_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5886, 40, NULL,mtlgt2__ext45__xve_load_store_cache_register_request_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5887, 48, NULL,mtlgt2__ext45__xve_load_store_cache_register_request_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext51_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext51";
   query->symbol_name = "Ext51";
   query->guid = "3a093546-2929-4b79-87f4-97df02c1fe8e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x2808001D },
         { .reg = 0x00009888, .val = 0x2C087400 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x16080975 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x2808001D },
         { .reg = 0x00009888, .val = 0x2C087400 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x14080975 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x2808001D },
         { .reg = 0x00009888, .val = 0x2C087400 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x12080975 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x2808001D },
         { .reg = 0x00009888, .val = 0x2C087400 },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x10080975 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0F00 },
         { .reg = 0x00009888, .val = 0x000E0F00 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0201FFAA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010090 },
         { .reg = 0x00009888, .val = 0x54010229 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext51__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext51__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext51__avg_gpu_core_frequency__max,mtlgt2__ext51__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5888, 24, NULL,mtlgt2__ext51__xve_load_store_cache_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5889, 32, NULL,mtlgt2__ext51__xve_load_store_cache_register_response_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5890, 40, NULL,mtlgt2__ext51__xve_load_store_cache_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5891, 48, NULL,mtlgt2__ext51__xve_load_store_cache_register_response_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext53_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext53";
   query->symbol_name = "Ext53";
   query->guid = "2ccdac56-9683-4eb5-89fd-7d42e77c117f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x08080824 },
         { .reg = 0x00009888, .val = 0x0A080C34 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x0C080824 },
         { .reg = 0x00009888, .val = 0x0E080C34 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x10080824 },
         { .reg = 0x00009888, .val = 0x12080C34 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x14080824 },
         { .reg = 0x00009888, .val = 0x16080C34 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext53__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext53__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext53__avg_gpu_core_frequency__max,mtlgt2__ext53__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5892, 24, NULL,mtlgt2__ext53__xve_slm_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5893, 32, NULL,mtlgt2__ext53__xve_slm_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5894, 40, NULL,mtlgt2__ext53__xve_slm_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5895, 48, NULL,mtlgt2__ext53__xve_slm_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext57_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext57";
   query->symbol_name = "Ext57";
   query->guid = "d297b1e3-fc04-45a7-a5c5-f92ab4357eb2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x08080823 },
         { .reg = 0x00009888, .val = 0x0A080C33 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x0C080823 },
         { .reg = 0x00009888, .val = 0x0E080C33 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x10080823 },
         { .reg = 0x00009888, .val = 0x12080C33 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x14080823 },
         { .reg = 0x00009888, .val = 0x16080C33 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext57__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext57__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext57__avg_gpu_core_frequency__max,mtlgt2__ext57__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5896, 24, NULL,mtlgt2__ext57__xve_slm_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5897, 32, NULL,mtlgt2__ext57__xve_slm_write_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5898, 40, NULL,mtlgt2__ext57__xve_slm_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5899, 48, NULL,mtlgt2__ext57__xve_slm_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext61_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext61";
   query->symbol_name = "Ext61";
   query->guid = "bc372334-fe31-452e-843a-515328c75fd2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x08080A27 },
         { .reg = 0x00009888, .val = 0x0A080E37 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x0C080A27 },
         { .reg = 0x00009888, .val = 0x0E080E37 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x10080A27 },
         { .reg = 0x00009888, .val = 0x12080E37 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x14080A27 },
         { .reg = 0x00009888, .val = 0x16080E37 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext61__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext61__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext61__avg_gpu_core_frequency__max,mtlgt2__ext61__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5900, 24, NULL,mtlgt2__ext61__xve_slm_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5901, 32, NULL,mtlgt2__ext61__xve_slm_fence_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5902, 40, NULL,mtlgt2__ext61__xve_slm_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5903, 48, NULL,mtlgt2__ext61__xve_slm_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext65_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext65";
   query->symbol_name = "Ext65";
   query->guid = "8a5ca732-17d3-4336-a33c-292a7f625237";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x080808A3 },
         { .reg = 0x00009888, .val = 0x0A080CE8 },
         { .reg = 0x00009888, .val = 0x0C080E32 },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x0E0808A3 },
         { .reg = 0x00009888, .val = 0x10080CE8 },
         { .reg = 0x00009888, .val = 0x12080E32 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext65__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext65__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext65__avg_gpu_core_frequency__max,mtlgt2__ext65__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5904, 24, NULL,mtlgt2__ext65__xve_slm_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5905, 32, NULL,mtlgt2__ext65__xve_slm_atomic_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext66_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext66";
   query->symbol_name = "Ext66";
   query->guid = "2e72f570-378b-4672-a615-374c1a3d524c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x080808A3 },
         { .reg = 0x00009888, .val = 0x0A080CE8 },
         { .reg = 0x00009888, .val = 0x0C080E32 },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x020800FF },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x06083254 },
         { .reg = 0x00009888, .val = 0x0E0808A3 },
         { .reg = 0x00009888, .val = 0x10080CE8 },
         { .reg = 0x00009888, .val = 0x12080E32 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0FFF },
         { .reg = 0x00009888, .val = 0x000E0FFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x020100AA },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext66__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext66__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext66__avg_gpu_core_frequency__max,mtlgt2__ext66__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5906, 24, NULL,mtlgt2__ext66__xve_slm_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5907, 32, NULL,mtlgt2__ext66__xve_slm_atomic_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext73_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext73";
   query->symbol_name = "Ext73";
   query->guid = "8f63bf05-fccb-45c2-89c1-cf1226c4fb80";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1602E6C0 },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x06020A00 },
         { .reg = 0x00009888, .val = 0x080201C6 },
         { .reg = 0x00009888, .val = 0x0A020048 },
         { .reg = 0x00009888, .val = 0x0C0200C2 },
         { .reg = 0x00009888, .val = 0x0E020004 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1602E6C4 },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x0E020140 },
         { .reg = 0x00009888, .val = 0x100201C6 },
         { .reg = 0x00009888, .val = 0x12020048 },
         { .reg = 0x00009888, .val = 0x140200C2 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010003 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext73__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext73__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext73__avg_gpu_core_frequency__max,mtlgt2__ext73__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5908, 24, percentage_max_float,mtlgt2__ext73__dataport_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5909, 28, percentage_max_float,mtlgt2__ext73__dataport_input_available_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext74_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext74";
   query->symbol_name = "Ext74";
   query->guid = "2e5b5a64-580f-4cfc-ac3b-e6ccc55a1260";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1602E6C0 },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x06020A00 },
         { .reg = 0x00009888, .val = 0x080201C6 },
         { .reg = 0x00009888, .val = 0x0A020048 },
         { .reg = 0x00009888, .val = 0x0C0200C2 },
         { .reg = 0x00009888, .val = 0x0E020004 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1602E6C4 },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x0E020140 },
         { .reg = 0x00009888, .val = 0x100201C6 },
         { .reg = 0x00009888, .val = 0x12020048 },
         { .reg = 0x00009888, .val = 0x140200C2 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010003 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext74__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext74__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext74__avg_gpu_core_frequency__max,mtlgt2__ext74__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5910, 24, percentage_max_float,mtlgt2__ext74__dataport_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5911, 28, percentage_max_float,mtlgt2__ext74__dataport_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext77_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext77";
   query->symbol_name = "Ext77";
   query->guid = "1e7215b8-72b7-460b-99d1-9be3984e9f6c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0C02C000 },
         { .reg = 0x00009888, .val = 0x04020100 },
         { .reg = 0x00009888, .val = 0x06022000 },
         { .reg = 0x00009888, .val = 0x08020491 },
         { .reg = 0x00009888, .val = 0x0A020013 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0C02C491 },
         { .reg = 0x00009888, .val = 0x04020100 },
         { .reg = 0x00009888, .val = 0x0A020400 },
         { .reg = 0x00009888, .val = 0x0E020013 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0C02C000 },
         { .reg = 0x00009888, .val = 0x04020100 },
         { .reg = 0x00009888, .val = 0x0E020400 },
         { .reg = 0x00009888, .val = 0x10020491 },
         { .reg = 0x00009888, .val = 0x12020013 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0C02C000 },
         { .reg = 0x00009888, .val = 0x04020100 },
         { .reg = 0x00009888, .val = 0x12020400 },
         { .reg = 0x00009888, .val = 0x14020491 },
         { .reg = 0x00009888, .val = 0x16020013 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext77__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext77__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext77__avg_gpu_core_frequency__max,mtlgt2__ext77__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5912, 24, percentage_max_float,mtlgt2__ext77__dataport_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5913, 28, percentage_max_float,mtlgt2__ext77__dataport_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5914, 32, percentage_max_float,mtlgt2__ext77__dataport_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5915, 36, percentage_max_float,mtlgt2__ext77__dataport_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext79_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext79";
   query->symbol_name = "Ext79";
   query->guid = "a1a1cc95-7466-461d-a3a4-a04818bb5d74";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0C02A51A },
         { .reg = 0x00009888, .val = 0x0E02B01B },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x06022E00 },
         { .reg = 0x00009888, .val = 0x08020598 },
         { .reg = 0x00009888, .val = 0x0A020559 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0C02A000 },
         { .reg = 0x00009888, .val = 0x0E02B5C0 },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x10020598 },
         { .reg = 0x00009888, .val = 0x12020559 },
         { .reg = 0x00009888, .val = 0x1402051A },
         { .reg = 0x00009888, .val = 0x1602001B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010003 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext79__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext79__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext79__avg_gpu_core_frequency__max,mtlgt2__ext79__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5916, 24, NULL,mtlgt2__ext79__dataport_byte_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5917, 32, NULL,mtlgt2__ext79__dataport_byte_read_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext80_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext80";
   query->symbol_name = "Ext80";
   query->guid = "06d62e44-cf58-4e35-a8cf-c76ee2b4fd7f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0C02A51A },
         { .reg = 0x00009888, .val = 0x0E02B01B },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x06022E00 },
         { .reg = 0x00009888, .val = 0x08020598 },
         { .reg = 0x00009888, .val = 0x0A020559 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0C02A000 },
         { .reg = 0x00009888, .val = 0x0E02B5C0 },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x10020598 },
         { .reg = 0x00009888, .val = 0x12020559 },
         { .reg = 0x00009888, .val = 0x1402051A },
         { .reg = 0x00009888, .val = 0x1602001B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010003 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext80__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext80__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext80__avg_gpu_core_frequency__max,mtlgt2__ext80__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5918, 24, NULL,mtlgt2__ext80__dataport_byte_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5919, 32, NULL,mtlgt2__ext80__dataport_byte_read_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext83_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext83";
   query->symbol_name = "Ext83";
   query->guid = "428a93d8-3475-4efc-960e-3402b062d8f0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C020400 },
         { .reg = 0x00009888, .val = 0x1E02001A },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x06020001 },
         { .reg = 0x00009888, .val = 0x12020021 },
         { .reg = 0x00009888, .val = 0x1602002A },
         { .reg = 0x00009888, .val = 0x02023030 },
         { .reg = 0x00009888, .val = 0x02045050 },
         { .reg = 0x00009888, .val = 0x02083030 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C020400 },
         { .reg = 0x00009888, .val = 0x1E02001A },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x06020001 },
         { .reg = 0x00009888, .val = 0x10020840 },
         { .reg = 0x00009888, .val = 0x14020A80 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02041010 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C020400 },
         { .reg = 0x00009888, .val = 0x1E02001A },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x06020001 },
         { .reg = 0x00009888, .val = 0x10020021 },
         { .reg = 0x00009888, .val = 0x1402002A },
         { .reg = 0x00009888, .val = 0x02020303 },
         { .reg = 0x00009888, .val = 0x02040505 },
         { .reg = 0x00009888, .val = 0x02080303 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C020400 },
         { .reg = 0x00009888, .val = 0x1E02001A },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x06020001 },
         { .reg = 0x00009888, .val = 0x0E020840 },
         { .reg = 0x00009888, .val = 0x12020A80 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02040101 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02130A0A },
         { .reg = 0x00009888, .val = 0x02140505 },
         { .reg = 0x00009888, .val = 0x02150505 },
         { .reg = 0x00009888, .val = 0x02160505 },
         { .reg = 0x00009888, .val = 0x02170A0A },
         { .reg = 0x00009888, .val = 0x000C3300 },
         { .reg = 0x00009888, .val = 0x000E3300 },
         { .reg = 0x00009888, .val = 0x020D0A0A },
         { .reg = 0x00009888, .val = 0x02060A0A },
         { .reg = 0x00009888, .val = 0x0201FAFA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010229 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext83__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext83__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext83__avg_gpu_core_frequency__max,mtlgt2__ext83__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5920, 24, NULL,mtlgt2__ext83__dataport_byte_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5921, 32, NULL,mtlgt2__ext83__dataport_byte_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5922, 40, NULL,mtlgt2__ext83__dataport_byte_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5923, 48, NULL,mtlgt2__ext83__dataport_byte_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5924, 56, NULL,mtlgt2__ext83__dataport_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5925, 64, NULL,mtlgt2__ext83__dataport_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5926, 72, NULL,mtlgt2__ext83__dataport_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5927, 80, NULL,mtlgt2__ext83__dataport_texture_cache_access_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext85_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext85";
   query->symbol_name = "Ext85";
   query->guid = "e6db7a16-f214-4cd0-91e9-94d8036c20ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x1C020000 },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x06020A00 },
         { .reg = 0x00009888, .val = 0x080202C7 },
         { .reg = 0x00009888, .val = 0x16020027 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x1C020000 },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x0A0201C5 },
         { .reg = 0x00009888, .val = 0x0C02000B },
         { .reg = 0x00009888, .val = 0x140209C0 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00040540 },
         { .reg = 0x00009888, .val = 0x02041000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x1C020000 },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x0C020140 },
         { .reg = 0x00009888, .val = 0x0E0202C7 },
         { .reg = 0x00009888, .val = 0x14020027 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x020203FC },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040555 },
         { .reg = 0x00009888, .val = 0x020803FC },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x1C020000 },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x100201C5 },
         { .reg = 0x00009888, .val = 0x120209CB },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02040154 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013A000 },
         { .reg = 0x00009888, .val = 0x02130AAA },
         { .reg = 0x00009888, .val = 0x00145000 },
         { .reg = 0x00009888, .val = 0x02140555 },
         { .reg = 0x00009888, .val = 0x00155000 },
         { .reg = 0x00009888, .val = 0x02150555 },
         { .reg = 0x00009888, .val = 0x00165000 },
         { .reg = 0x00009888, .val = 0x02160555 },
         { .reg = 0x00009888, .val = 0x0017A000 },
         { .reg = 0x00009888, .val = 0x02170AAA },
         { .reg = 0x00009888, .val = 0x000C3FC0 },
         { .reg = 0x00009888, .val = 0x000E3FC0 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x020D0AAA },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x02060AAA },
         { .reg = 0x00009888, .val = 0x0001AFFF },
         { .reg = 0x00009888, .val = 0x0201FAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010211 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext85__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext85__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext85__avg_gpu_core_frequency__max,mtlgt2__ext85__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5928, 24, NULL,mtlgt2__ext85__xve_dataport_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5929, 32, NULL,mtlgt2__ext85__xve_dataport_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5930, 40, NULL,mtlgt2__ext85__xve_dataport_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5931, 48, NULL,mtlgt2__ext85__xve_dataport_read_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5932, 56, NULL,mtlgt2__ext85__dataport_texture_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5933, 64, NULL,mtlgt2__ext85__dataport_texture_cache_hit_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5934, 72, NULL,mtlgt2__ext85__dataport_texture_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5935, 80, NULL,mtlgt2__ext85__dataport_texture_cache_hit_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext87_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext87";
   query->symbol_name = "Ext87";
   query->guid = "b96d78d7-c0c8-4941-9f28-e746f36627e4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x06020C00 },
         { .reg = 0x00009888, .val = 0x080202C8 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x0A020206 },
         { .reg = 0x00009888, .val = 0x0C02000B },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00040540 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x0C020180 },
         { .reg = 0x00009888, .val = 0x0E0202C8 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x020200FC },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x020800FC },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x10020206 },
         { .reg = 0x00009888, .val = 0x1202000B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02040054 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013A000 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00145000 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00155000 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00165000 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x0017A000 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0FC0 },
         { .reg = 0x00009888, .val = 0x000E0FC0 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001AFFF },
         { .reg = 0x00009888, .val = 0x020100AA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext87__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext87__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext87__avg_gpu_core_frequency__max,mtlgt2__ext87__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5936, 24, NULL,mtlgt2__ext87__xve_dataport_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5937, 32, NULL,mtlgt2__ext87__xve_dataport_write_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5938, 40, NULL,mtlgt2__ext87__xve_dataport_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5939, 48, NULL,mtlgt2__ext87__xve_dataport_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext91_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext91";
   query->symbol_name = "Ext91";
   query->guid = "55e5926a-364e-45f0-bbcd-69375ac61391";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x06020A00 },
         { .reg = 0x00009888, .val = 0x080202C6 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x0A020185 },
         { .reg = 0x00009888, .val = 0x0C02000B },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00040540 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x0C020140 },
         { .reg = 0x00009888, .val = 0x0E0202C6 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x020200FC },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x020800FC },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x10020185 },
         { .reg = 0x00009888, .val = 0x1202000B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02040054 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013A000 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00145000 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00155000 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00165000 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x0017A000 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0FC0 },
         { .reg = 0x00009888, .val = 0x000E0FC0 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001AFFF },
         { .reg = 0x00009888, .val = 0x020100AA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext91__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext91__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext91__avg_gpu_core_frequency__max,mtlgt2__ext91__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5940, 24, NULL,mtlgt2__ext91__xve_dataport_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5941, 32, NULL,mtlgt2__ext91__xve_dataport_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5942, 40, NULL,mtlgt2__ext91__xve_dataport_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5943, 48, NULL,mtlgt2__ext91__xve_dataport_atomic_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext93_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext93";
   query->symbol_name = "Ext93";
   query->guid = "a06cf71c-ad14-49b8-8a22-b367118514bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0C02A51A },
         { .reg = 0x00009888, .val = 0x0E02B01B },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x06022E00 },
         { .reg = 0x00009888, .val = 0x08020598 },
         { .reg = 0x00009888, .val = 0x0A020559 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0C02A000 },
         { .reg = 0x00009888, .val = 0x0E02B5C0 },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x10020598 },
         { .reg = 0x00009888, .val = 0x12020559 },
         { .reg = 0x00009888, .val = 0x1402051A },
         { .reg = 0x00009888, .val = 0x1602001B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010003 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext93__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext93__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext93__avg_gpu_core_frequency__max,mtlgt2__ext93__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5944, 24, NULL,mtlgt2__ext93__xve_dataport_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5945, 32, NULL,mtlgt2__ext93__xve_dataport_register_response_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext94_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext94";
   query->symbol_name = "Ext94";
   query->guid = "a05152f2-80f2-47cc-add7-70f4664b58e8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0C02A51A },
         { .reg = 0x00009888, .val = 0x0E02B01B },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x06022E00 },
         { .reg = 0x00009888, .val = 0x08020598 },
         { .reg = 0x00009888, .val = 0x0A020559 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0C02A000 },
         { .reg = 0x00009888, .val = 0x0E02B5C0 },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x10020598 },
         { .reg = 0x00009888, .val = 0x12020559 },
         { .reg = 0x00009888, .val = 0x1402051A },
         { .reg = 0x00009888, .val = 0x1602001B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010003 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext94__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext94__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext94__avg_gpu_core_frequency__max,mtlgt2__ext94__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5946, 24, NULL,mtlgt2__ext94__xve_dataport_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5947, 28, NULL,mtlgt2__ext94__xve_dataport_register_response_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext97_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext97";
   query->symbol_name = "Ext97";
   query->guid = "39f8d4d2-b28d-40a3-b545-a57865d7714e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1602BF4F },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x14020080 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1602BF40 },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x12020080 },
         { .reg = 0x00009888, .val = 0x1402000F },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1602BF40 },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x10020080 },
         { .reg = 0x00009888, .val = 0x1202000F },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1602BF40 },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x0E020080 },
         { .reg = 0x00009888, .val = 0x1002000F },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0F00 },
         { .reg = 0x00009888, .val = 0x000E0F00 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0201FFAA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010090 },
         { .reg = 0x00009888, .val = 0x54010229 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext97__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext97__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext97__avg_gpu_core_frequency__max,mtlgt2__ext97__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5948, 24, NULL,mtlgt2__ext97__xve_dataport_register_request_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5949, 32, NULL,mtlgt2__ext97__xve_dataport_register_request_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5950, 40, NULL,mtlgt2__ext97__xve_dataport_register_request_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5951, 48, NULL,mtlgt2__ext97__xve_dataport_register_request_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext98_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext98";
   query->symbol_name = "Ext98";
   query->guid = "ee9377fe-2623-4588-8ffc-517e34c2eb75";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x04030450 },
         { .reg = 0x00009888, .val = 0x060304D2 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x000455AA },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x08030450 },
         { .reg = 0x00009888, .val = 0x0A0304D2 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x0004AA00 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x0C030450 },
         { .reg = 0x00009888, .val = 0x0E0304D2 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x020455AA },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x10030450 },
         { .reg = 0x00009888, .val = 0x120304D2 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x0204AA00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext98__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext98__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext98__avg_gpu_core_frequency__max,mtlgt2__ext98__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5952, 24, percentage_max_float,mtlgt2__ext98__sampler_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5953, 28, percentage_max_float,mtlgt2__ext98__sampler_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5954, 32, percentage_max_float,mtlgt2__ext98__sampler_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5955, 36, percentage_max_float,mtlgt2__ext98__sampler_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext100_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext100";
   query->symbol_name = "Ext100";
   query->guid = "b5533650-f6f1-4f66-ad40-6b4aba600102";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1A010013 },
         { .reg = 0x00009888, .val = 0x02012000 },
         { .reg = 0x00009888, .val = 0x04011204 },
         { .reg = 0x00009888, .val = 0x06010023 },
         { .reg = 0x00009888, .val = 0x14010029 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x000200F5 },
         { .reg = 0x00009888, .val = 0x02027000 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x000800F0 },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1A010013 },
         { .reg = 0x00009888, .val = 0x02012000 },
         { .reg = 0x00009888, .val = 0x04010004 },
         { .reg = 0x00009888, .val = 0x06010900 },
         { .reg = 0x00009888, .val = 0x08010023 },
         { .reg = 0x00009888, .val = 0x12010A40 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x00020050 },
         { .reg = 0x00009888, .val = 0x02021000 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02041000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1A010013 },
         { .reg = 0x00009888, .val = 0x02012000 },
         { .reg = 0x00009888, .val = 0x04010004 },
         { .reg = 0x00009888, .val = 0x08010900 },
         { .reg = 0x00009888, .val = 0x0A010023 },
         { .reg = 0x00009888, .val = 0x12010029 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x0002F500 },
         { .reg = 0x00009888, .val = 0x02020700 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x02080300 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1A010013 },
         { .reg = 0x00009888, .val = 0x02012000 },
         { .reg = 0x00009888, .val = 0x04010004 },
         { .reg = 0x00009888, .val = 0x0A010900 },
         { .reg = 0x00009888, .val = 0x0C010023 },
         { .reg = 0x00009888, .val = 0x10010A40 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02020100 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040100 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AA00 },
         { .reg = 0x00009888, .val = 0x02130A00 },
         { .reg = 0x00009888, .val = 0x00145500 },
         { .reg = 0x00009888, .val = 0x02140500 },
         { .reg = 0x00009888, .val = 0x00155500 },
         { .reg = 0x00009888, .val = 0x02150500 },
         { .reg = 0x00009888, .val = 0x00165500 },
         { .reg = 0x00009888, .val = 0x02160500 },
         { .reg = 0x00009888, .val = 0x0017AA00 },
         { .reg = 0x00009888, .val = 0x02170A00 },
         { .reg = 0x00009888, .val = 0x000C30F0 },
         { .reg = 0x00009888, .val = 0x000E30F0 },
         { .reg = 0x00009888, .val = 0x000DAA00 },
         { .reg = 0x00009888, .val = 0x020D0A00 },
         { .reg = 0x00009888, .val = 0x0006AA00 },
         { .reg = 0x00009888, .val = 0x02060A00 },
         { .reg = 0x00009888, .val = 0x0001AAFF },
         { .reg = 0x00009888, .val = 0x0201FA00 },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010211 },
         { .reg = 0x00009888, .val = 0x58011201 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext100__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext100__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext100__avg_gpu_core_frequency__max,mtlgt2__ext100__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5956, 24, percentage_max_float,mtlgt2__ext100__sampler_memory_latency_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5957, 28, percentage_max_float,mtlgt2__ext100__sampler_memory_latency_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5958, 32, percentage_max_float,mtlgt2__ext100__sampler_memory_latency_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5959, 36, percentage_max_float,mtlgt2__ext100__sampler_memory_latency_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5960, 40, percentage_max_float,mtlgt2__ext100__sampler_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5961, 44, percentage_max_float,mtlgt2__ext100__sampler_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5962, 48, percentage_max_float,mtlgt2__ext100__sampler_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5963, 52, percentage_max_float,mtlgt2__ext100__sampler_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext101_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext101";
   query->symbol_name = "Ext101";
   query->guid = "136839ab-66a3-42ac-bca4-1cfca1d3088e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x02023030 },
         { .reg = 0x00009888, .val = 0x0204D0D0 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x12070900 },
         { .reg = 0x00009888, .val = 0x16070940 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x02083030 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x02043030 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x12070024 },
         { .reg = 0x00009888, .val = 0x16070025 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x02020303 },
         { .reg = 0x00009888, .val = 0x02040D0D },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x10070900 },
         { .reg = 0x00009888, .val = 0x14070940 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x02080303 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x02040303 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x10070024 },
         { .reg = 0x00009888, .val = 0x14070025 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02130A0A },
         { .reg = 0x00009888, .val = 0x02140505 },
         { .reg = 0x00009888, .val = 0x02150505 },
         { .reg = 0x00009888, .val = 0x02160505 },
         { .reg = 0x00009888, .val = 0x02170A0A },
         { .reg = 0x00009888, .val = 0x000C3300 },
         { .reg = 0x00009888, .val = 0x000E3300 },
         { .reg = 0x00009888, .val = 0x020D0A0A },
         { .reg = 0x00009888, .val = 0x02060A0A },
         { .reg = 0x00009888, .val = 0x0201FAFA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010229 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext101__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext101__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext101__avg_gpu_core_frequency__max,mtlgt2__ext101__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5964, 24, percentage_max_float,mtlgt2__ext101__thread_dispatch_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5965, 28, percentage_max_float,mtlgt2__ext101__thread_dispatch_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5966, 32, percentage_max_float,mtlgt2__ext101__thread_dispatch_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5967, 36, percentage_max_float,mtlgt2__ext101__thread_dispatch_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5968, 40, percentage_max_float,mtlgt2__ext101__thread_dispatch_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5969, 44, percentage_max_float,mtlgt2__ext101__thread_dispatch_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5970, 48, percentage_max_float,mtlgt2__ext101__thread_dispatch_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5971, 52, percentage_max_float,mtlgt2__ext101__thread_dispatch_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext102_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext102";
   query->symbol_name = "Ext102";
   query->guid = "bd8e9b37-35b3-4a94-8ff7-bbad7d67642c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x02023030 },
         { .reg = 0x00009888, .val = 0x0E030C80 },
         { .reg = 0x00009888, .val = 0x12030CC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02049090 },
         { .reg = 0x00009888, .val = 0x02083030 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x0E030032 },
         { .reg = 0x00009888, .val = 0x12030033 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02042020 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x02020303 },
         { .reg = 0x00009888, .val = 0x0C030C80 },
         { .reg = 0x00009888, .val = 0x10030CC0 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02040909 },
         { .reg = 0x00009888, .val = 0x02080303 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x0C030032 },
         { .reg = 0x00009888, .val = 0x10030033 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02040202 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02130A0A },
         { .reg = 0x00009888, .val = 0x02140505 },
         { .reg = 0x00009888, .val = 0x02150505 },
         { .reg = 0x00009888, .val = 0x02160505 },
         { .reg = 0x00009888, .val = 0x02170A0A },
         { .reg = 0x00009888, .val = 0x000C3300 },
         { .reg = 0x00009888, .val = 0x000E3300 },
         { .reg = 0x00009888, .val = 0x020D0A0A },
         { .reg = 0x00009888, .val = 0x02060A0A },
         { .reg = 0x00009888, .val = 0x0201FAFA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010229 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext102__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext102__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext102__avg_gpu_core_frequency__max,mtlgt2__ext102__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5972, 24, NULL,mtlgt2__ext102__sampler_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5973, 32, NULL,mtlgt2__ext102__sampler_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5974, 40, NULL,mtlgt2__ext102__sampler_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5975, 48, NULL,mtlgt2__ext102__sampler_texture_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5976, 56, NULL,mtlgt2__ext102__sampler_texture_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5977, 64, NULL,mtlgt2__ext102__sampler_texture_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5978, 72, NULL,mtlgt2__ext102__sampler_texture_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5979, 80, NULL,mtlgt2__ext102__sampler_texture_cache_miss_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext104_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext104";
   query->symbol_name = "Ext104";
   query->guid = "576a210f-b921-46dc-9af7-7f34eb1d368e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x32070180 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x06070800 },
         { .reg = 0x00009888, .val = 0x08070C70 },
         { .reg = 0x00009888, .val = 0x0A070CF2 },
         { .reg = 0x00009888, .val = 0x0C070DB7 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x32077940 },
         { .reg = 0x00009888, .val = 0x0004F000 },
         { .reg = 0x00009888, .val = 0x0204003F },
         { .reg = 0x00009888, .val = 0x06079800 },
         { .reg = 0x00009888, .val = 0x0E070CF2 },
         { .reg = 0x00009888, .val = 0x10070D74 },
         { .reg = 0x00009888, .val = 0x12070039 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013A000 },
         { .reg = 0x00009888, .val = 0x0213002A },
         { .reg = 0x00009888, .val = 0x00145000 },
         { .reg = 0x00009888, .val = 0x02140015 },
         { .reg = 0x00009888, .val = 0x00155000 },
         { .reg = 0x00009888, .val = 0x02150015 },
         { .reg = 0x00009888, .val = 0x00165000 },
         { .reg = 0x00009888, .val = 0x02160015 },
         { .reg = 0x00009888, .val = 0x0017A000 },
         { .reg = 0x00009888, .val = 0x0217002A },
         { .reg = 0x00009888, .val = 0x000C07C0 },
         { .reg = 0x00009888, .val = 0x000E07C0 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x020D002A },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x0206002A },
         { .reg = 0x00009888, .val = 0x0001AFFF },
         { .reg = 0x00009888, .val = 0x0201002A },
         { .reg = 0x00009888, .val = 0x4E010090 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58011209 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext104__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext104__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext104__avg_gpu_core_frequency__max,mtlgt2__ext104__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5980, 24, NULL,mtlgt2__ext104__async_gpgpu_thread_exit_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5981, 32, NULL,mtlgt2__ext104__task_thread_exit_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5982, 40, NULL,mtlgt2__ext104__gpgpu_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5983, 48, NULL,mtlgt2__ext104__task_threadgroup_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext105_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext105";
   query->symbol_name = "Ext105";
   query->guid = "96b32930-859d-4fa8-8d81-4d26a160f0e8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x32070180 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x06070800 },
         { .reg = 0x00009888, .val = 0x08070C70 },
         { .reg = 0x00009888, .val = 0x0A070CF2 },
         { .reg = 0x00009888, .val = 0x0C070DB7 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x32077940 },
         { .reg = 0x00009888, .val = 0x0004F000 },
         { .reg = 0x00009888, .val = 0x0204003F },
         { .reg = 0x00009888, .val = 0x06079800 },
         { .reg = 0x00009888, .val = 0x0E070CF2 },
         { .reg = 0x00009888, .val = 0x10070D74 },
         { .reg = 0x00009888, .val = 0x12070039 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x00080FFF },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x0202003F },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040015 },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x0208003F },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013A000 },
         { .reg = 0x00009888, .val = 0x0213002A },
         { .reg = 0x00009888, .val = 0x00145000 },
         { .reg = 0x00009888, .val = 0x02140015 },
         { .reg = 0x00009888, .val = 0x00155000 },
         { .reg = 0x00009888, .val = 0x02150015 },
         { .reg = 0x00009888, .val = 0x00165000 },
         { .reg = 0x00009888, .val = 0x02160015 },
         { .reg = 0x00009888, .val = 0x0017A000 },
         { .reg = 0x00009888, .val = 0x0217002A },
         { .reg = 0x00009888, .val = 0x000C07C0 },
         { .reg = 0x00009888, .val = 0x000E07C0 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x020D002A },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x0206002A },
         { .reg = 0x00009888, .val = 0x0001AFFF },
         { .reg = 0x00009888, .val = 0x0201002A },
         { .reg = 0x00009888, .val = 0x4E010090 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58011209 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext105__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext105__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext105__avg_gpu_core_frequency__max,mtlgt2__ext105__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5984, 24, NULL,mtlgt2__ext105__async_gpgpu_thread_exit_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5985, 32, NULL,mtlgt2__ext105__task_thread_exit_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5986, 40, NULL,mtlgt2__ext105__gpgpu_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5987, 48, NULL,mtlgt2__ext105__task_threadgroup_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext106_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext106";
   query->symbol_name = "Ext106";
   query->guid = "bbe4bf0d-03a3-482a-869c-1c6e71d52dac";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x32077940 },
         { .reg = 0x00009888, .val = 0x0004F000 },
         { .reg = 0x00009888, .val = 0x0204003F },
         { .reg = 0x00009888, .val = 0x06079800 },
         { .reg = 0x00009888, .val = 0x0E070CF2 },
         { .reg = 0x00009888, .val = 0x10070D74 },
         { .reg = 0x00009888, .val = 0x12070039 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x32070180 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x06070800 },
         { .reg = 0x00009888, .val = 0x08070C70 },
         { .reg = 0x00009888, .val = 0x0A070CF2 },
         { .reg = 0x00009888, .val = 0x0C070DB7 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00130AAA },
         { .reg = 0x00009888, .val = 0x00140555 },
         { .reg = 0x00009888, .val = 0x00150555 },
         { .reg = 0x00009888, .val = 0x00160555 },
         { .reg = 0x00009888, .val = 0x00170AAA },
         { .reg = 0x00009888, .val = 0x000C003F },
         { .reg = 0x00009888, .val = 0x000E003F },
         { .reg = 0x00009888, .val = 0x000D0AAA },
         { .reg = 0x00009888, .val = 0x00060AAA },
         { .reg = 0x00009888, .val = 0x0001FAAA },
         { .reg = 0x00009888, .val = 0x0201003F },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60011209 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010090 },
         { .reg = 0x00009888, .val = 0x50010009 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext106__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext106__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext106__avg_gpu_core_frequency__max,mtlgt2__ext106__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5988, 24, NULL,mtlgt2__ext106__async_gpgpu_thread_exit_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5989, 32, NULL,mtlgt2__ext106__task_thread_exit_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5990, 40, NULL,mtlgt2__ext106__gpgpu_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5991, 48, NULL,mtlgt2__ext106__task_threadgroup_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext107_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext107";
   query->symbol_name = "Ext107";
   query->guid = "02eafe17-886d-4559-b18d-c661fd6914c0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x32077940 },
         { .reg = 0x00009888, .val = 0x0004F000 },
         { .reg = 0x00009888, .val = 0x0204003F },
         { .reg = 0x00009888, .val = 0x06079800 },
         { .reg = 0x00009888, .val = 0x0E070CF2 },
         { .reg = 0x00009888, .val = 0x10070D74 },
         { .reg = 0x00009888, .val = 0x12070039 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x32070180 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x06070800 },
         { .reg = 0x00009888, .val = 0x08070C70 },
         { .reg = 0x00009888, .val = 0x0A070CF2 },
         { .reg = 0x00009888, .val = 0x0C070DB7 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x0202003F },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040015 },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x0208003F },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x00080FFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00130AAA },
         { .reg = 0x00009888, .val = 0x00140555 },
         { .reg = 0x00009888, .val = 0x00150555 },
         { .reg = 0x00009888, .val = 0x00160555 },
         { .reg = 0x00009888, .val = 0x00170AAA },
         { .reg = 0x00009888, .val = 0x000C003F },
         { .reg = 0x00009888, .val = 0x000E003F },
         { .reg = 0x00009888, .val = 0x000D0AAA },
         { .reg = 0x00009888, .val = 0x00060AAA },
         { .reg = 0x00009888, .val = 0x0001FAAA },
         { .reg = 0x00009888, .val = 0x0201003F },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60011209 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010090 },
         { .reg = 0x00009888, .val = 0x50010009 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext107__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext107__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext107__avg_gpu_core_frequency__max,mtlgt2__ext107__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5992, 24, NULL,mtlgt2__ext107__async_gpgpu_thread_exit_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5993, 32, NULL,mtlgt2__ext107__task_thread_exit_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5994, 40, NULL,mtlgt2__ext107__gpgpu_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5995, 48, NULL,mtlgt2__ext107__task_threadgroup_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext113_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext113";
   query->symbol_name = "Ext113";
   query->guid = "8cb51ae4-6d00-44d5-9d24-29521022f02b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x32077BA0 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x0004005F },
         { .reg = 0x00009888, .val = 0x0204F500 },
         { .reg = 0x00009888, .val = 0x06079806 },
         { .reg = 0x00009888, .val = 0x08070821 },
         { .reg = 0x00009888, .val = 0x16070E37 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x000800F0 },
         { .reg = 0x00009888, .val = 0x02080F00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x32077BA0 },
         { .reg = 0x00009888, .val = 0x000400F0 },
         { .reg = 0x00009888, .val = 0x02040F00 },
         { .reg = 0x00009888, .val = 0x06079806 },
         { .reg = 0x00009888, .val = 0x0A070821 },
         { .reg = 0x00009888, .val = 0x14070E37 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x32077BA0 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00045F00 },
         { .reg = 0x00009888, .val = 0x020400F5 },
         { .reg = 0x00009888, .val = 0x06079806 },
         { .reg = 0x00009888, .val = 0x0C070821 },
         { .reg = 0x00009888, .val = 0x12070E37 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x0008F000 },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x32077BA0 },
         { .reg = 0x00009888, .val = 0x0004F000 },
         { .reg = 0x00009888, .val = 0x0204000F },
         { .reg = 0x00009888, .val = 0x06079806 },
         { .reg = 0x00009888, .val = 0x0E070821 },
         { .reg = 0x00009888, .val = 0x10070E37 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AA00 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00145500 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00155500 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00165500 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x0017AA00 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0FF0 },
         { .reg = 0x00009888, .val = 0x000E0FF0 },
         { .reg = 0x00009888, .val = 0x000DAA00 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x0006AA00 },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001AAFF },
         { .reg = 0x00009888, .val = 0x0201FFAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010211 },
         { .reg = 0x00009888, .val = 0x58011201 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010090 },
         { .reg = 0x00009888, .val = 0x54010229 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext113__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext113__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext113__avg_gpu_core_frequency__max,mtlgt2__ext113__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5996, 24, percentage_max_float,mtlgt2__ext113__thread_dispatch_ps_active_cycles_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5997, 28, percentage_max_float,mtlgt2__ext113__thread_dispatch_ps_active_cycles_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5998, 32, percentage_max_float,mtlgt2__ext113__thread_dispatch_ps_active_cycles_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5999, 36, percentage_max_float,mtlgt2__ext113__thread_dispatch_ps_active_cycles_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6000, 40, percentage_max_float,mtlgt2__ext113__thread_dispatch_queue0_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6001, 44, percentage_max_float,mtlgt2__ext113__thread_dispatch_queue1_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6002, 48, percentage_max_float,mtlgt2__ext113__thread_dispatch_queue0_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6003, 52, percentage_max_float,mtlgt2__ext113__thread_dispatch_queue1_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6004, 56, percentage_max_float,mtlgt2__ext113__thread_dispatch_queue0_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6005, 60, percentage_max_float,mtlgt2__ext113__thread_dispatch_queue1_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6006, 64, percentage_max_float,mtlgt2__ext113__thread_dispatch_queue0_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6007, 68, percentage_max_float,mtlgt2__ext113__thread_dispatch_queue1_active_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext116_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext116";
   query->symbol_name = "Ext116";
   query->guid = "c50c1328-01a4-44a4-bc10-cea109a86100";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x320703C0 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x000455FF },
         { .reg = 0x00009888, .val = 0x06070800 },
         { .reg = 0x00009888, .val = 0x08070DB7 },
         { .reg = 0x00009888, .val = 0x0A070CF5 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x320703C0 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x06070800 },
         { .reg = 0x00009888, .val = 0x0C070DB7 },
         { .reg = 0x00009888, .val = 0x0E070CF5 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x320703C0 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x020455FF },
         { .reg = 0x00009888, .val = 0x06070800 },
         { .reg = 0x00009888, .val = 0x10070DB7 },
         { .reg = 0x00009888, .val = 0x12070CF5 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x320703C0 },
         { .reg = 0x00009888, .val = 0x0204FF00 },
         { .reg = 0x00009888, .val = 0x06070800 },
         { .reg = 0x00009888, .val = 0x14070DB7 },
         { .reg = 0x00009888, .val = 0x16070CF5 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000401 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00004001 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00040001 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext116__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext116__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext116__avg_gpu_core_frequency__max,mtlgt2__ext116__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6008, 24, percentage_max_float,mtlgt2__ext116__threadgroup_dispatch_resource_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6009, 28, percentage_max_float,mtlgt2__ext116__threadgroup_dispatch_resource_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6010, 32, percentage_max_float,mtlgt2__ext116__threadgroup_dispatch_resource_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6011, 36, percentage_max_float,mtlgt2__ext116__threadgroup_dispatch_resource_stall_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext118_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext118";
   query->symbol_name = "Ext118";
   query->guid = "3ac7b553-9dd8-4588-be88-8a50d4aa8497";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14127800 },
         { .reg = 0x00009888, .val = 0x161224C0 },
         { .reg = 0x00009888, .val = 0x12100700 },
         { .reg = 0x00009888, .val = 0x1410001A },
         { .reg = 0x00009888, .val = 0x0E120E31 },
         { .reg = 0x00009888, .val = 0x101208E4 },
         { .reg = 0x00009888, .val = 0x12120026 },
         { .reg = 0x00009888, .val = 0x02120000 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x00131555 },
         { .reg = 0x00009888, .val = 0x0213FFC0 },
         { .reg = 0x00009888, .val = 0x00161555 },
         { .reg = 0x00009888, .val = 0x02165540 },
         { .reg = 0x00009888, .val = 0x00100010 },
         { .reg = 0x00009888, .val = 0x02100000 },
         { .reg = 0x00009888, .val = 0x04100081 },
         { .reg = 0x00009888, .val = 0x061003C3 },
         { .reg = 0x00009888, .val = 0x0810034E },
         { .reg = 0x00009888, .val = 0x000CF87F },
         { .reg = 0x00009888, .val = 0x000EF87F },
         { .reg = 0x00009888, .val = 0x00062AAA },
         { .reg = 0x00009888, .val = 0x0206AA80 },
         { .reg = 0x00009888, .val = 0x00012AAA },
         { .reg = 0x00009888, .val = 0x0201AA80 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010201 },
         { .reg = 0x00009888, .val = 0x5A010010 },
         { .reg = 0x00009888, .val = 0x5C010201 },
         { .reg = 0x00009888, .val = 0x5E010010 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00100060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x0000001A },
         { .reg = 0x0000D954, .val = 0x0000FFFC },
         { .reg = 0x0000D958, .val = 0x00000062 },
         { .reg = 0x0000D95C, .val = 0x0000FFF3 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext118__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext118__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext118__avg_gpu_core_frequency__max,mtlgt2__ext118__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6012, 24, percentage_max_float,mtlgt2__ext118__amfs_stall_all_input_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6013, 28, percentage_max_float,mtlgt2__ext118__amfs_stall_any_input_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6014, 32, NULL,mtlgt2__ext118__amfs_cache_hit_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6015, 40, NULL,mtlgt2__ext118__amfs_cache_miss_slice0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6016, 48, NULL,mtlgt2__ext118__render_cache_hit_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6017, 56, NULL,mtlgt2__ext118__render_cache_read_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6018, 64, NULL,mtlgt2__ext118__render_cache_write_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6019, 72, percentage_max_float,mtlgt2__ext118__render_cache_input_available_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6020, 76, percentage_max_float,mtlgt2__ext118__render_cache_output_ready_l3_node0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext120_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext120";
   query->symbol_name = "Ext120";
   query->guid = "39bbba4c-b77d-424a-9156-ede3d325df25";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18060005 },
         { .reg = 0x00009888, .val = 0x0002FFAA },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02060020 },
         { .reg = 0x00009888, .val = 0x04060554 },
         { .reg = 0x00009888, .val = 0x060605D6 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18060005 },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02060020 },
         { .reg = 0x00009888, .val = 0x08060554 },
         { .reg = 0x00009888, .val = 0x0A0605D6 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18060005 },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02060020 },
         { .reg = 0x00009888, .val = 0x0C060554 },
         { .reg = 0x00009888, .val = 0x0E0605D6 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18060005 },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02060020 },
         { .reg = 0x00009888, .val = 0x10060554 },
         { .reg = 0x00009888, .val = 0x120605D6 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext120__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext120__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext120__avg_gpu_core_frequency__max,mtlgt2__ext120__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6021, 24, percentage_max_float,mtlgt2__ext120__pixel_post_process_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6022, 28, percentage_max_float,mtlgt2__ext120__pixel_post_process_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6023, 32, percentage_max_float,mtlgt2__ext120__pixel_post_process_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6024, 36, percentage_max_float,mtlgt2__ext120__pixel_post_process_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext122_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext122";
   query->symbol_name = "Ext122";
   query->guid = "1c2b42f8-2763-4c20-85d9-5a5bd7381eb8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14121000 },
         { .reg = 0x00009888, .val = 0x161224C0 },
         { .reg = 0x00009888, .val = 0x1410001A },
         { .reg = 0x00009888, .val = 0x140C01F0 },
         { .reg = 0x00009888, .val = 0x120C1000 },
         { .reg = 0x00009888, .val = 0x160D01C0 },
         { .reg = 0x00009888, .val = 0x1E0D0400 },
         { .reg = 0x00009888, .val = 0x0E120E31 },
         { .reg = 0x00009888, .val = 0x10120020 },
         { .reg = 0x00009888, .val = 0x02120000 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x00130A05 },
         { .reg = 0x00009888, .val = 0x02132FC0 },
         { .reg = 0x00009888, .val = 0x00140500 },
         { .reg = 0x00009888, .val = 0x02141000 },
         { .reg = 0x00009888, .val = 0x00150500 },
         { .reg = 0x00009888, .val = 0x02151000 },
         { .reg = 0x00009888, .val = 0x00160505 },
         { .reg = 0x00009888, .val = 0x02161540 },
         { .reg = 0x00009888, .val = 0x00170A00 },
         { .reg = 0x00009888, .val = 0x02172000 },
         { .reg = 0x00009888, .val = 0x00100002 },
         { .reg = 0x00009888, .val = 0x02100E00 },
         { .reg = 0x00009888, .val = 0x04100006 },
         { .reg = 0x00009888, .val = 0x020C0004 },
         { .reg = 0x00009888, .val = 0x040C0000 },
         { .reg = 0x00009888, .val = 0x060C0100 },
         { .reg = 0x00009888, .val = 0x080C0003 },
         { .reg = 0x00009888, .val = 0x000C7833 },
         { .reg = 0x00009888, .val = 0x000E7833 },
         { .reg = 0x00009888, .val = 0x040D0000 },
         { .reg = 0x00009888, .val = 0x060D0010 },
         { .reg = 0x00009888, .val = 0x0A0D0500 },
         { .reg = 0x00009888, .val = 0x0C0D0013 },
         { .reg = 0x00009888, .val = 0x140D0C00 },
         { .reg = 0x00009888, .val = 0x000D0000 },
         { .reg = 0x00009888, .val = 0x020D0000 },
         { .reg = 0x00009888, .val = 0x00060AAA },
         { .reg = 0x00009888, .val = 0x0206AA80 },
         { .reg = 0x00009888, .val = 0x00010AAA },
         { .reg = 0x00009888, .val = 0x0201AA80 },
         { .reg = 0x00009888, .val = 0x4E010040 },
         { .reg = 0x00009888, .val = 0x56010070 },
         { .reg = 0x00009888, .val = 0x58010E04 },
         { .reg = 0x00009888, .val = 0x5A010070 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x50010600 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010003 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext122__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext122__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext122__avg_gpu_core_frequency__max,mtlgt2__ext122__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6025, 24, NULL,mtlgt2__ext122__amfs_4_x4_shading_request_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6026, 32, percentage_max_float,mtlgt2__ext122__color_pipe_cache_latency1_stall_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6027, 36, percentage_max_float,mtlgt2__ext122__color_pipe_cache_latency1_stall_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6028, 40, percentage_max_float,mtlgt2__ext122__pixel_post_process_output_ready_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6029, 44, percentage_max_float,mtlgt2__ext122__pixel_post_process_output_ready_cpipe1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6030, 48, percentage_max_float,mtlgt2__ext122__color_pipe_cache_latency2_stall_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6031, 52, percentage_max_float,mtlgt2__ext122__pixel_backend_input_available_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6032, 56, percentage_max_float,mtlgt2__ext122__pixel_backend_output_ready_l3_node0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext123_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext123";
   query->symbol_name = "Ext123";
   query->guid = "80240cbe-83d5-44dd-a03a-c498a6928be5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x18155013 },
         { .reg = 0x00009888, .val = 0x1410018A },
         { .reg = 0x00009888, .val = 0x180C0320 },
         { .reg = 0x00009888, .val = 0x1A0D6400 },
         { .reg = 0x00009888, .val = 0x001305A0 },
         { .reg = 0x00009888, .val = 0x02136800 },
         { .reg = 0x00009888, .val = 0x00140050 },
         { .reg = 0x00009888, .val = 0x02141400 },
         { .reg = 0x00009888, .val = 0x04150020 },
         { .reg = 0x00009888, .val = 0x141501C0 },
         { .reg = 0x00009888, .val = 0x16150008 },
         { .reg = 0x00009888, .val = 0x06150000 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x02150000 },
         { .reg = 0x00009888, .val = 0x00160550 },
         { .reg = 0x00009888, .val = 0x02165400 },
         { .reg = 0x00009888, .val = 0x001700A0 },
         { .reg = 0x00009888, .val = 0x0010001A },
         { .reg = 0x00009888, .val = 0x06100000 },
         { .reg = 0x00009888, .val = 0x0810000D },
         { .reg = 0x00009888, .val = 0x1210000F },
         { .reg = 0x00009888, .val = 0x020C0000 },
         { .reg = 0x00009888, .val = 0x040C1100 },
         { .reg = 0x00009888, .val = 0x060C0021 },
         { .reg = 0x00009888, .val = 0x000CE03C },
         { .reg = 0x00009888, .val = 0x000EE03C },
         { .reg = 0x00009888, .val = 0x040D2000 },
         { .reg = 0x00009888, .val = 0x080D0880 },
         { .reg = 0x00009888, .val = 0x0A0D0021 },
         { .reg = 0x00009888, .val = 0x000D0000 },
         { .reg = 0x00009888, .val = 0x00060AAA },
         { .reg = 0x00009888, .val = 0x0206A800 },
         { .reg = 0x00009888, .val = 0x00010AAA },
         { .reg = 0x00009888, .val = 0x0201A800 },
         { .reg = 0x00009888, .val = 0x4E010070 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009888, .val = 0x58010007 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010402 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00040182 },
         { .reg = 0x0000D954, .val = 0x00007FCF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext123__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext123__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext123__avg_gpu_core_frequency__max,mtlgt2__ext123__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6033, 24, percentage_max_float,mtlgt2__ext123__ps_output_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6034, 28, percentage_max_float,mtlgt2__ext123__ps_output_available_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6035, 32, NULL,mtlgt2__ext123__amfs_l3_access_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6036, 40, NULL,mtlgt2__ext123__amfs_l3_atomic_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6037, 48, NULL,mtlgt2__ext123__clipper_primitive_far_near_clip_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext124_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext124";
   query->symbol_name = "Ext124";
   query->guid = "f8d36c8e-4129-4962-afce-7917f98e9b2d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x18155414 },
         { .reg = 0x00009888, .val = 0x2415041F },
         { .reg = 0x00009888, .val = 0x161601F0 },
         { .reg = 0x00009888, .val = 0x1816001F },
         { .reg = 0x00009888, .val = 0x0A180000 },
         { .reg = 0x00009888, .val = 0x00138000 },
         { .reg = 0x00009888, .val = 0x02132AAA },
         { .reg = 0x00009888, .val = 0x00144000 },
         { .reg = 0x00009888, .val = 0x02141555 },
         { .reg = 0x00009888, .val = 0x04150020 },
         { .reg = 0x00009888, .val = 0x06150022 },
         { .reg = 0x00009888, .val = 0x0E150800 },
         { .reg = 0x00009888, .val = 0x101500C1 },
         { .reg = 0x00009888, .val = 0x1215000A },
         { .reg = 0x00009888, .val = 0x14150268 },
         { .reg = 0x00009888, .val = 0x16150008 },
         { .reg = 0x00009888, .val = 0x00150000 },
         { .reg = 0x00009888, .val = 0x02150040 },
         { .reg = 0x00009888, .val = 0x04160200 },
         { .reg = 0x00009888, .val = 0x06160027 },
         { .reg = 0x00009888, .val = 0x14160D80 },
         { .reg = 0x00009888, .val = 0x00164000 },
         { .reg = 0x00009888, .val = 0x02161555 },
         { .reg = 0x00009888, .val = 0x02170040 },
         { .reg = 0x00009888, .val = 0x02180010 },
         { .reg = 0x00009888, .val = 0x0E180031 },
         { .reg = 0x00009888, .val = 0x00180000 },
         { .reg = 0x00009888, .val = 0x000CFF81 },
         { .reg = 0x00009888, .val = 0x000EFF81 },
         { .reg = 0x00009888, .val = 0x00068002 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x00018002 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010040 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010201 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010010 },
         { .reg = 0x00009888, .val = 0x50010001 },
         { .reg = 0x00009888, .val = 0x52010010 },
         { .reg = 0x00009888, .val = 0x54010201 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext124__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext124__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext124__avg_gpu_core_frequency__max,mtlgt2__ext124__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6038, 24, percentage_max_float,mtlgt2__ext124__vertex_fetch_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6039, 28, percentage_max_float,mtlgt2__ext124__vertex_fetch_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6040, 32, NULL,mtlgt2__ext124__clipper_input_vertex_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6041, 40, NULL,mtlgt2__ext124__streamout_output_vertex_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6042, 48, percentage_max_float,mtlgt2__ext124__vs_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6043, 52, percentage_max_float,mtlgt2__ext124__clipper_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6044, 56, percentage_max_float,mtlgt2__ext124__clipper_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6045, 64, NULL,mtlgt2__ext124__clipper_primitive_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6046, 72, percentage_max_float,mtlgt2__ext124__stripsfan_output_ready_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext126_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext126";
   query->symbol_name = "Ext126";
   query->guid = "08670eec-8015-4c40-b900-d47b9824ec83";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C150000 },
         { .reg = 0x00009888, .val = 0x18150014 },
         { .reg = 0x00009888, .val = 0x22157FC0 },
         { .reg = 0x00009888, .val = 0x24107800 },
         { .reg = 0x00009888, .val = 0x26100000 },
         { .reg = 0x00009888, .val = 0x140E0400 },
         { .reg = 0x00009888, .val = 0x120F0400 },
         { .reg = 0x00009888, .val = 0x001305A0 },
         { .reg = 0x00009888, .val = 0x0213AAA4 },
         { .reg = 0x00009888, .val = 0x00140050 },
         { .reg = 0x00009888, .val = 0x02145550 },
         { .reg = 0x00009888, .val = 0x04150007 },
         { .reg = 0x00009888, .val = 0x06150008 },
         { .reg = 0x00009888, .val = 0x121500C2 },
         { .reg = 0x00009888, .val = 0x1415094B },
         { .reg = 0x00009888, .val = 0x16150B6A },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x02150000 },
         { .reg = 0x00009888, .val = 0x00160550 },
         { .reg = 0x00009888, .val = 0x02165554 },
         { .reg = 0x00009888, .val = 0x001700A0 },
         { .reg = 0x00009888, .val = 0x02100130 },
         { .reg = 0x00009888, .val = 0x06100C80 },
         { .reg = 0x00009888, .val = 0x08100030 },
         { .reg = 0x00009888, .val = 0x0C10003C },
         { .reg = 0x00009888, .val = 0x00100000 },
         { .reg = 0x00009888, .val = 0x000CFE3F },
         { .reg = 0x00009888, .val = 0x020E0004 },
         { .reg = 0x00009888, .val = 0x040E1870 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000EFE3C },
         { .reg = 0x00009888, .val = 0x000D0050 },
         { .reg = 0x00009888, .val = 0x000F0004 },
         { .reg = 0x00009888, .val = 0x040F0187 },
         { .reg = 0x00009888, .val = 0x00060AAA },
         { .reg = 0x00009888, .val = 0x0206AAA8 },
         { .reg = 0x00009888, .val = 0x00010AAA },
         { .reg = 0x00009888, .val = 0x0201AAA8 },
         { .reg = 0x00009888, .val = 0x4E010060 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010006 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010040 },
         { .reg = 0x00009888, .val = 0x50010402 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010402 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext126__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext126__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext126__avg_gpu_core_frequency__max,mtlgt2__ext126__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6047, 24, NULL,mtlgt2__ext126__stripsfan_object_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6048, 32, NULL,mtlgt2__ext126__stripsfan_objects_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6049, 40, NULL,mtlgt2__ext126__clipper_transaction_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6050, 48, NULL,mtlgt2__ext126__rasterizer_transaction_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6051, 56, NULL,mtlgt2__ext126__clipper_primitive_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6052, 64, percentage_max_float,mtlgt2__ext126__rasterizer_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6053, 68, percentage_max_float,mtlgt2__ext126__rasterizer_output_ready_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext128_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext128";
   query->symbol_name = "Ext128";
   query->guid = "7d149ad7-90bd-4201-8791-2e8c1c4359e8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1213F79F },
         { .reg = 0x00009888, .val = 0x1C130030 },
         { .reg = 0x00009888, .val = 0x1614F000 },
         { .reg = 0x00009888, .val = 0x18141800 },
         { .reg = 0x00009888, .val = 0x04132600 },
         { .reg = 0x00009888, .val = 0x08130411 },
         { .reg = 0x00009888, .val = 0x0C1306DC },
         { .reg = 0x00009888, .val = 0x0E13001A },
         { .reg = 0x00009888, .val = 0x1413001D },
         { .reg = 0x00009888, .val = 0x06130000 },
         { .reg = 0x00009888, .val = 0x001380A0 },
         { .reg = 0x00009888, .val = 0x0213A80A },
         { .reg = 0x00009888, .val = 0x04140000 },
         { .reg = 0x00009888, .val = 0x06140000 },
         { .reg = 0x00009888, .val = 0x08140C31 },
         { .reg = 0x00009888, .val = 0x0C140900 },
         { .reg = 0x00009888, .val = 0x0E1408A3 },
         { .reg = 0x00009888, .val = 0x121409C0 },
         { .reg = 0x00009888, .val = 0x14140966 },
         { .reg = 0x00009888, .val = 0x00140000 },
         { .reg = 0x00009888, .val = 0x02140000 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010001 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010201 },
         { .reg = 0x00009888, .val = 0x5E010010 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010201 },
         { .reg = 0x00009888, .val = 0x52010010 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext128__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext128__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext128__avg_gpu_core_frequency__max,mtlgt2__ext128__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6054, 24, NULL,mtlgt2__ext128__urb_read_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6055, 32, NULL,mtlgt2__ext128__urb_write_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6056, 40, NULL,mtlgt2__ext128__urb_cross_slice_read_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext130_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext130";
   query->symbol_name = "Ext130";
   query->guid = "52597b67-dea9-411c-845e-c7f7befa744e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0E0E5500 },
         { .reg = 0x00009888, .val = 0x000CF801 },
         { .reg = 0x00009888, .val = 0x020E0080 },
         { .reg = 0x00009888, .val = 0x040E0150 },
         { .reg = 0x00009888, .val = 0x100E0493 },
         { .reg = 0x00009888, .val = 0x120E0411 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x00060002 },
         { .reg = 0x00009888, .val = 0x0206AA80 },
         { .reg = 0x00009888, .val = 0x00010002 },
         { .reg = 0x00009888, .val = 0x0201AA80 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext130__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext130__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext130__avg_gpu_core_frequency__max,mtlgt2__ext130__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6057, 24, NULL,mtlgt2__ext130__early_depth_stencil_test_fail_np_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6058, 32, NULL,mtlgt2__ext130__early_depth_stencil_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext131_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext131";
   query->symbol_name = "Ext131";
   query->guid = "56b5eb77-117c-4392-a4ed-6a809598c28f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0C0F5500 },
         { .reg = 0x00009888, .val = 0x00130002 },
         { .reg = 0x00009888, .val = 0x0213AA80 },
         { .reg = 0x00009888, .val = 0x00140001 },
         { .reg = 0x00009888, .val = 0x02145540 },
         { .reg = 0x00009888, .val = 0x00150001 },
         { .reg = 0x00009888, .val = 0x02155540 },
         { .reg = 0x00009888, .val = 0x00160001 },
         { .reg = 0x00009888, .val = 0x02165540 },
         { .reg = 0x00009888, .val = 0x00170002 },
         { .reg = 0x00009888, .val = 0x0217AA80 },
         { .reg = 0x00009888, .val = 0x000CF801 },
         { .reg = 0x00009888, .val = 0x000EF801 },
         { .reg = 0x00009888, .val = 0x000D0001 },
         { .reg = 0x00009888, .val = 0x020D5540 },
         { .reg = 0x00009888, .val = 0x000F0080 },
         { .reg = 0x00009888, .val = 0x020F0150 },
         { .reg = 0x00009888, .val = 0x0E0F0493 },
         { .reg = 0x00009888, .val = 0x100F0411 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x00060002 },
         { .reg = 0x00009888, .val = 0x0206AA80 },
         { .reg = 0x00009888, .val = 0x00010002 },
         { .reg = 0x00009888, .val = 0x0201AA80 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext131__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext131__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext131__avg_gpu_core_frequency__max,mtlgt2__ext131__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6059, 24, NULL,mtlgt2__ext131__early_depth_stencil_test_fail_np_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6060, 32, NULL,mtlgt2__ext131__early_depth_stencil_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext134_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext134";
   query->symbol_name = "Ext134";
   query->guid = "d4f5b1c3-553d-46f6-abb8-8535ee5e4c90";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x140E5C00 },
         { .reg = 0x00009888, .val = 0x160E001F },
         { .reg = 0x00009888, .val = 0x000CFFE0 },
         { .reg = 0x00009888, .val = 0x020E002C },
         { .reg = 0x00009888, .val = 0x080E0140 },
         { .reg = 0x00009888, .val = 0x0A0E00C4 },
         { .reg = 0x00009888, .val = 0x0C0E038F },
         { .reg = 0x00009888, .val = 0x0E0E030D },
         { .reg = 0x00009888, .val = 0x100E028B },
         { .reg = 0x00009888, .val = 0x120E0209 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x0006A800 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A800 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext134__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext134__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext134__avg_gpu_core_frequency__max,mtlgt2__ext134__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6061, 24, NULL,mtlgt2__ext134__hiz_depth_test_ambig_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext135_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext135";
   query->symbol_name = "Ext135";
   query->guid = "2aa7d46b-8b53-4693-9e5b-1245dc85cb90";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x120F5C00 },
         { .reg = 0x00009888, .val = 0x140F001F },
         { .reg = 0x00009888, .val = 0x0013A800 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145400 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155400 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165400 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017A800 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFE0 },
         { .reg = 0x00009888, .val = 0x000EFFE0 },
         { .reg = 0x00009888, .val = 0x000D5400 },
         { .reg = 0x00009888, .val = 0x020D5555 },
         { .reg = 0x00009888, .val = 0x000F002C },
         { .reg = 0x00009888, .val = 0x060F0140 },
         { .reg = 0x00009888, .val = 0x080F00C4 },
         { .reg = 0x00009888, .val = 0x0A0F038F },
         { .reg = 0x00009888, .val = 0x0C0F030D },
         { .reg = 0x00009888, .val = 0x0E0F028B },
         { .reg = 0x00009888, .val = 0x100F0209 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x0006A800 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A800 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext135__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext135__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext135__avg_gpu_core_frequency__max,mtlgt2__ext135__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6062, 24, NULL,mtlgt2__ext135__hiz_depth_test_ambig_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext138_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext138";
   query->symbol_name = "Ext138";
   query->guid = "18d95a38-b79c-42ac-a1c1-f6f3ef5ee213";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x140E5C00 },
         { .reg = 0x00009888, .val = 0x160E0016 },
         { .reg = 0x00009888, .val = 0x000CFFE0 },
         { .reg = 0x00009888, .val = 0x020E002C },
         { .reg = 0x00009888, .val = 0x080E0080 },
         { .reg = 0x00009888, .val = 0x0A0E0001 },
         { .reg = 0x00009888, .val = 0x0C0E038F },
         { .reg = 0x00009888, .val = 0x0E0E030D },
         { .reg = 0x00009888, .val = 0x100E028B },
         { .reg = 0x00009888, .val = 0x120E0209 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x0006A800 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A800 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext138__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext138__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext138__avg_gpu_core_frequency__max,mtlgt2__ext138__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6063, 24, NULL,mtlgt2__ext138__hiz_depth_test_ambig_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext139_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext139";
   query->symbol_name = "Ext139";
   query->guid = "7869d90b-8a61-40c5-b705-91ce55b64cd8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x120F5C00 },
         { .reg = 0x00009888, .val = 0x140F0016 },
         { .reg = 0x00009888, .val = 0x0013A800 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145400 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155400 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165400 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017A800 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFE0 },
         { .reg = 0x00009888, .val = 0x000EFFE0 },
         { .reg = 0x00009888, .val = 0x000D5400 },
         { .reg = 0x00009888, .val = 0x020D5555 },
         { .reg = 0x00009888, .val = 0x000F002C },
         { .reg = 0x00009888, .val = 0x060F0080 },
         { .reg = 0x00009888, .val = 0x080F0001 },
         { .reg = 0x00009888, .val = 0x0A0F038F },
         { .reg = 0x00009888, .val = 0x0C0F030D },
         { .reg = 0x00009888, .val = 0x0E0F028B },
         { .reg = 0x00009888, .val = 0x100F0209 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x0006A800 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A800 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext139__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext139__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext139__avg_gpu_core_frequency__max,mtlgt2__ext139__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6064, 24, NULL,mtlgt2__ext139__hiz_depth_test_ambig_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext142_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext142";
   query->symbol_name = "Ext142";
   query->guid = "c9f005ff-957d-471f-b6d3-98ebfd423f88";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x140E4800 },
         { .reg = 0x00009888, .val = 0x160E0010 },
         { .reg = 0x00009888, .val = 0x000CFFE0 },
         { .reg = 0x00009888, .val = 0x020E002C },
         { .reg = 0x00009888, .val = 0x080E0140 },
         { .reg = 0x00009888, .val = 0x0A0E00C4 },
         { .reg = 0x00009888, .val = 0x0C0E038F },
         { .reg = 0x00009888, .val = 0x0E0E030D },
         { .reg = 0x00009888, .val = 0x100E028B },
         { .reg = 0x00009888, .val = 0x120E0209 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x0006A800 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A800 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext142__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext142__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext142__avg_gpu_core_frequency__max,mtlgt2__ext142__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6065, 24, NULL,mtlgt2__ext142__hiz_depth_test_fail_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext143_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext143";
   query->symbol_name = "Ext143";
   query->guid = "bf8f687e-d93f-439a-904e-14758015b273";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x120F4800 },
         { .reg = 0x00009888, .val = 0x140F0010 },
         { .reg = 0x00009888, .val = 0x0013A800 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145400 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155400 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165400 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017A800 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFE0 },
         { .reg = 0x00009888, .val = 0x000EFFE0 },
         { .reg = 0x00009888, .val = 0x000D5400 },
         { .reg = 0x00009888, .val = 0x020D5555 },
         { .reg = 0x00009888, .val = 0x000F002C },
         { .reg = 0x00009888, .val = 0x060F0140 },
         { .reg = 0x00009888, .val = 0x080F00C4 },
         { .reg = 0x00009888, .val = 0x0A0F038F },
         { .reg = 0x00009888, .val = 0x0C0F030D },
         { .reg = 0x00009888, .val = 0x0E0F028B },
         { .reg = 0x00009888, .val = 0x100F0209 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x0006A800 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A800 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext143__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext143__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext143__avg_gpu_core_frequency__max,mtlgt2__ext143__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6066, 24, NULL,mtlgt2__ext143__hiz_depth_test_fail_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext146_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext146";
   query->symbol_name = "Ext146";
   query->guid = "38cb3c8a-b6b1-46e9-b18e-331afd4faad6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x140E4800 },
         { .reg = 0x00009888, .val = 0x160E0011 },
         { .reg = 0x00009888, .val = 0x000CFFE0 },
         { .reg = 0x00009888, .val = 0x020E002C },
         { .reg = 0x00009888, .val = 0x080E0080 },
         { .reg = 0x00009888, .val = 0x0A0E0001 },
         { .reg = 0x00009888, .val = 0x0C0E038F },
         { .reg = 0x00009888, .val = 0x0E0E030D },
         { .reg = 0x00009888, .val = 0x100E028B },
         { .reg = 0x00009888, .val = 0x120E0209 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x0006A800 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A800 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext146__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext146__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext146__avg_gpu_core_frequency__max,mtlgt2__ext146__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6067, 24, NULL,mtlgt2__ext146__hiz_depth_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext147_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext147";
   query->symbol_name = "Ext147";
   query->guid = "f0624b43-b429-4be9-9cef-1a9c966b9bf5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x120F4800 },
         { .reg = 0x00009888, .val = 0x140F0011 },
         { .reg = 0x00009888, .val = 0x0013A800 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145400 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155400 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165400 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017A800 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFE0 },
         { .reg = 0x00009888, .val = 0x000EFFE0 },
         { .reg = 0x00009888, .val = 0x000D5400 },
         { .reg = 0x00009888, .val = 0x020D5555 },
         { .reg = 0x00009888, .val = 0x000F002C },
         { .reg = 0x00009888, .val = 0x060F0080 },
         { .reg = 0x00009888, .val = 0x080F0001 },
         { .reg = 0x00009888, .val = 0x0A0F038F },
         { .reg = 0x00009888, .val = 0x0C0F030D },
         { .reg = 0x00009888, .val = 0x0E0F028B },
         { .reg = 0x00009888, .val = 0x100F0209 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x0006A800 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A800 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext147__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext147__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext147__avg_gpu_core_frequency__max,mtlgt2__ext147__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6068, 24, NULL,mtlgt2__ext147__hiz_depth_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext150_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext150";
   query->symbol_name = "Ext150";
   query->guid = "9be51bc5-540f-4a51-80b9-a6e8f849107c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x140E5C00 },
         { .reg = 0x00009888, .val = 0x160E0018 },
         { .reg = 0x00009888, .val = 0x000CFFC0 },
         { .reg = 0x00009888, .val = 0x020E002C },
         { .reg = 0x00009888, .val = 0x0A0E0187 },
         { .reg = 0x00009888, .val = 0x0C0E038F },
         { .reg = 0x00009888, .val = 0x0E0E030D },
         { .reg = 0x00009888, .val = 0x100E028B },
         { .reg = 0x00009888, .val = 0x120E0209 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000E0000 },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A000 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext150__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext150__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext150__avg_gpu_core_frequency__max,mtlgt2__ext150__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6069, 24, NULL,mtlgt2__ext150__hiz_depth_test_pass_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext151_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext151";
   query->symbol_name = "Ext151";
   query->guid = "5303f1e7-b41b-4f48-a638-02293743f84d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x120F5C00 },
         { .reg = 0x00009888, .val = 0x140F0018 },
         { .reg = 0x00009888, .val = 0x0013A000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145000 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155000 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165000 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017A000 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFC0 },
         { .reg = 0x00009888, .val = 0x000EFFC0 },
         { .reg = 0x00009888, .val = 0x000D5000 },
         { .reg = 0x00009888, .val = 0x020D5555 },
         { .reg = 0x00009888, .val = 0x000F002C },
         { .reg = 0x00009888, .val = 0x080F0187 },
         { .reg = 0x00009888, .val = 0x0A0F038F },
         { .reg = 0x00009888, .val = 0x0C0F030D },
         { .reg = 0x00009888, .val = 0x0E0F028B },
         { .reg = 0x00009888, .val = 0x100F0209 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001A000 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext151__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext151__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext151__avg_gpu_core_frequency__max,mtlgt2__ext151__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6070, 24, NULL,mtlgt2__ext151__hiz_depth_test_pass_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext154_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext154";
   query->symbol_name = "Ext154";
   query->guid = "269bfd75-1e50-4717-959c-f72de6c5e37e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x140E2C00 },
         { .reg = 0x00009888, .val = 0x0A0E6000 },
         { .reg = 0x00009888, .val = 0x0E0E6580 },
         { .reg = 0x00009888, .val = 0x120F2C00 },
         { .reg = 0x00009888, .val = 0x080F6000 },
         { .reg = 0x00009888, .val = 0x0C0F6016 },
         { .reg = 0x00009888, .val = 0x02132220 },
         { .reg = 0x00009888, .val = 0x02141110 },
         { .reg = 0x00009888, .val = 0x02151110 },
         { .reg = 0x00009888, .val = 0x02161110 },
         { .reg = 0x00009888, .val = 0x02172220 },
         { .reg = 0x00009888, .val = 0x000CFC00 },
         { .reg = 0x00009888, .val = 0x020E0404 },
         { .reg = 0x00009888, .val = 0x100E0740 },
         { .reg = 0x00009888, .val = 0x120E0080 },
         { .reg = 0x00009888, .val = 0x060E0000 },
         { .reg = 0x00009888, .val = 0x000E5400 },
         { .reg = 0x00009888, .val = 0x020D1110 },
         { .reg = 0x00009888, .val = 0x000F0404 },
         { .reg = 0x00009888, .val = 0x0E0F001D },
         { .reg = 0x00009888, .val = 0x100F0002 },
         { .reg = 0x00009888, .val = 0x040F0000 },
         { .reg = 0x00009888, .val = 0x0206AAA0 },
         { .reg = 0x00009888, .val = 0x0201AAA0 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010C00 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010006 },
         { .reg = 0x00009888, .val = 0x56010060 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext154__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext154__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext154__avg_gpu_core_frequency__max,mtlgt2__ext154__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6071, 24, percentage_max_float,mtlgt2__ext154__hiz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6072, 28, percentage_max_float,mtlgt2__ext154__hiz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6073, 32, percentage_max_float,mtlgt2__ext154__iz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6074, 36, percentage_max_float,mtlgt2__ext154__iz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6075, 40, percentage_max_float,mtlgt2__ext154__iz_output_ready_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6076, 44, percentage_max_float,mtlgt2__ext154__iz_output_ready_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext155_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext155";
   query->symbol_name = "Ext155";
   query->guid = "77c2e8f4-297f-46ed-95a9-370e21e131c6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1A020010 },
         { .reg = 0x00009888, .val = 0x18010400 },
         { .reg = 0x00009888, .val = 0x20010200 },
         { .reg = 0x00009888, .val = 0x04020002 },
         { .reg = 0x00009888, .val = 0x0E020000 },
         { .reg = 0x00009888, .val = 0x10020081 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x04010240 },
         { .reg = 0x00009888, .val = 0x08010000 },
         { .reg = 0x00009888, .val = 0x0A010081 },
         { .reg = 0x00009888, .val = 0x0C010248 },
         { .reg = 0x00009888, .val = 0x0E01000A },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x02010001 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010201 },
         { .reg = 0x00009888, .val = 0x5A010010 },
         { .reg = 0x00009888, .val = 0x5C010201 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext155__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext155__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext155__avg_gpu_core_frequency__max,mtlgt2__ext155__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6077, 24, percentage_max_float,mtlgt2__ext155__command_parser_compute_engine_busy_ccs0__read);

      intel_perf_query_add_counter_float(query, 6078, 28, percentage_max_float,mtlgt2__ext155__command_parser_render_engine_busy__read);

      intel_perf_query_add_counter_float(query, 6079, 32, percentage_max_float,mtlgt2__ext155__command_parser_copy_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext156_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext156";
   query->symbol_name = "Ext156";
   query->guid = "dea81dd8-3792-4245-9ce3-4591a6ff2d31";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2001001F },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x040101A4 },
         { .reg = 0x00009888, .val = 0x08010000 },
         { .reg = 0x00009888, .val = 0x0A01028B },
         { .reg = 0x00009888, .val = 0x16010300 },
         { .reg = 0x00009888, .val = 0x18010008 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000030 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext156__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext156__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext156__avg_gpu_core_frequency__max,mtlgt2__ext156__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6080, 24, NULL,mtlgt2__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs0__read);

      intel_perf_query_add_counter_uint64(query, 6081, 32, NULL,mtlgt2__ext156__command_parser_render_engine_dispatch_kernel_count__read);

      intel_perf_query_add_counter_uint64(query, 6082, 40, NULL,mtlgt2__ext156__command_parser_render_engine_draw_count__read);

      intel_perf_query_add_counter_uint64(query, 6083, 48, NULL,mtlgt2__ext156__command_parser_flush_count__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext158_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext158";
   query->symbol_name = "Ext158";
   query->guid = "0f6dfbfe-33f8-4910-996a-8b639c57066f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x160503E0 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02050004 },
         { .reg = 0x00009888, .val = 0x120501C6 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085F00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x160503E0 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x02050004 },
         { .reg = 0x00009888, .val = 0x100501C6 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02080500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x160503E0 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050004 },
         { .reg = 0x00009888, .val = 0x0E0501C6 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208005F },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x160503E0 },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x02050004 },
         { .reg = 0x00009888, .val = 0x0C0501C6 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02080005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0F00 },
         { .reg = 0x00009888, .val = 0x000E0F00 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0201FFAA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010090 },
         { .reg = 0x00009888, .val = 0x54010229 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext158__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext158__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext158__avg_gpu_core_frequency__max,mtlgt2__ext158__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6084, 24, NULL,mtlgt2__ext158__rt_input_message_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6085, 32, NULL,mtlgt2__ext158__rt_input_message_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6086, 40, NULL,mtlgt2__ext158__rt_input_message_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6087, 48, NULL,mtlgt2__ext158__rt_input_message_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext159_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext159";
   query->symbol_name = "Ext159";
   query->guid = "7b4a0c8f-f35d-49e2-b1a7-243740c4d888";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x040535DF },
         { .reg = 0x00009888, .val = 0x06050F7F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0008FF55 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x08050D77 },
         { .reg = 0x00009888, .val = 0x0A050F7F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x0C050D77 },
         { .reg = 0x00009888, .val = 0x0E050F7F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208FF55 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x10050D77 },
         { .reg = 0x00009888, .val = 0x12050F7F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext159__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext159__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext159__avg_gpu_core_frequency__max,mtlgt2__ext159__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6088, 24, NULL,mtlgt2__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6089, 32, NULL,mtlgt2__ext159__rt_closest_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6090, 40, NULL,mtlgt2__ext159__rt_closest_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6091, 48, NULL,mtlgt2__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext161_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext161";
   query->symbol_name = "Ext161";
   query->guid = "bf4c98bf-1930-408b-87ad-2674e6e617c0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x040536DF },
         { .reg = 0x00009888, .val = 0x06050FBF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0008FF55 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x08050DB7 },
         { .reg = 0x00009888, .val = 0x0A050FBF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x0C050DB7 },
         { .reg = 0x00009888, .val = 0x0E050FBF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208FF55 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x10050DB7 },
         { .reg = 0x00009888, .val = 0x12050FBF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext161__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext161__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext161__avg_gpu_core_frequency__max,mtlgt2__ext161__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6092, 24, NULL,mtlgt2__ext161__rt_miss_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6093, 32, NULL,mtlgt2__ext161__rt_miss_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6094, 40, NULL,mtlgt2__ext161__rt_miss_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6095, 48, NULL,mtlgt2__ext161__rt_miss_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext163_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext163";
   query->symbol_name = "Ext163";
   query->guid = "2826204b-5835-4b64-840f-133d1ca5b03a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x040534DF },
         { .reg = 0x00009888, .val = 0x06050F3F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0008FF55 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x08050D37 },
         { .reg = 0x00009888, .val = 0x0A050F3F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x0C050D37 },
         { .reg = 0x00009888, .val = 0x0E050F3F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208FF55 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x10050D37 },
         { .reg = 0x00009888, .val = 0x12050F3F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext163__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext163__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext163__avg_gpu_core_frequency__max,mtlgt2__ext163__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6096, 24, NULL,mtlgt2__ext163__rt_any_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6097, 32, NULL,mtlgt2__ext163__rt_any_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6098, 40, NULL,mtlgt2__ext163__rt_any_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6099, 48, NULL,mtlgt2__ext163__rt_any_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext165_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext165";
   query->symbol_name = "Ext165";
   query->guid = "b9e7193e-99b9-4e9f-9738-de7144ea3b39";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x040533DF },
         { .reg = 0x00009888, .val = 0x06050EFF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0008FF55 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x08050CF7 },
         { .reg = 0x00009888, .val = 0x0A050EFF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x0C050CF7 },
         { .reg = 0x00009888, .val = 0x0E050EFF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208FF55 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x10050CF7 },
         { .reg = 0x00009888, .val = 0x12050EFF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext165__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext165__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext165__avg_gpu_core_frequency__max,mtlgt2__ext165__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6100, 24, NULL,mtlgt2__ext165__rt_intersection_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6101, 32, NULL,mtlgt2__ext165__rt_intersection_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6102, 40, NULL,mtlgt2__ext165__rt_intersection_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6103, 48, NULL,mtlgt2__ext165__rt_intersection_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext167_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext167";
   query->symbol_name = "Ext167";
   query->guid = "4797cea4-4618-42c1-aa36-0f8210b42a47";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x040532DF },
         { .reg = 0x00009888, .val = 0x06050EBF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0008FF55 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x08050CB7 },
         { .reg = 0x00009888, .val = 0x0A050EBF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x0C050CB7 },
         { .reg = 0x00009888, .val = 0x0E050EBF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208FF55 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C051400 },
         { .reg = 0x00009888, .val = 0x1E050008 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x10050CB7 },
         { .reg = 0x00009888, .val = 0x12050EBF },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext167__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext167__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext167__avg_gpu_core_frequency__max,mtlgt2__ext167__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6104, 24, NULL,mtlgt2__ext167__rt_callable_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6105, 32, NULL,mtlgt2__ext167__rt_callable_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6106, 40, NULL,mtlgt2__ext167__rt_callable_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6107, 48, NULL,mtlgt2__ext167__rt_callable_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext169_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext169";
   query->symbol_name = "Ext169";
   query->guid = "daeb4a53-f0ba-4bec-9462-8025cc17ca8b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C053C00 },
         { .reg = 0x00009888, .val = 0x1E050011 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x040531C3 },
         { .reg = 0x00009888, .val = 0x06050E78 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0008FF55 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C053C00 },
         { .reg = 0x00009888, .val = 0x1E050011 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x08050C70 },
         { .reg = 0x00009888, .val = 0x0A050E78 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C053C00 },
         { .reg = 0x00009888, .val = 0x1E050011 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x0C050C70 },
         { .reg = 0x00009888, .val = 0x0E050E78 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208FF55 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C053C00 },
         { .reg = 0x00009888, .val = 0x1E050011 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02058000 },
         { .reg = 0x00009888, .val = 0x04050003 },
         { .reg = 0x00009888, .val = 0x10050C70 },
         { .reg = 0x00009888, .val = 0x12050E78 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext169__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext169__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext169__avg_gpu_core_frequency__max,mtlgt2__ext169__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6108, 24, NULL,mtlgt2__ext169__rt_traversal_output_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6109, 32, NULL,mtlgt2__ext169__rt_traversal_output_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6110, 40, NULL,mtlgt2__ext169__rt_traversal_output_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6111, 48, NULL,mtlgt2__ext169__rt_traversal_output_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext171_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext171";
   query->symbol_name = "Ext171";
   query->guid = "2aeaff8e-ce08-49f1-aacf-c9631dc3c756";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x160503C0 },
         { .reg = 0x00009888, .val = 0x06051140 },
         { .reg = 0x00009888, .val = 0x0002F0F0 },
         { .reg = 0x00009888, .val = 0x0202F0F0 },
         { .reg = 0x00009888, .val = 0x00045050 },
         { .reg = 0x00009888, .val = 0x02045050 },
         { .reg = 0x00009888, .val = 0x02051004 },
         { .reg = 0x00009888, .val = 0x0A050800 },
         { .reg = 0x00009888, .val = 0x0E050B00 },
         { .reg = 0x00009888, .val = 0x12050BC0 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00087070 },
         { .reg = 0x00009888, .val = 0x02087070 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x160503C0 },
         { .reg = 0x00009888, .val = 0x06051005 },
         { .reg = 0x00009888, .val = 0x00023030 },
         { .reg = 0x00009888, .val = 0x02023030 },
         { .reg = 0x00009888, .val = 0x00041010 },
         { .reg = 0x00009888, .val = 0x02041010 },
         { .reg = 0x00009888, .val = 0x02051004 },
         { .reg = 0x00009888, .val = 0x0A050020 },
         { .reg = 0x00009888, .val = 0x0E05002C },
         { .reg = 0x00009888, .val = 0x1205002F },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00081010 },
         { .reg = 0x00009888, .val = 0x02081010 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x160503C0 },
         { .reg = 0x00009888, .val = 0x06051000 },
         { .reg = 0x00009888, .val = 0x00020F0F },
         { .reg = 0x00009888, .val = 0x02020F0F },
         { .reg = 0x00009888, .val = 0x00040505 },
         { .reg = 0x00009888, .val = 0x02040505 },
         { .reg = 0x00009888, .val = 0x02051004 },
         { .reg = 0x00009888, .val = 0x04050500 },
         { .reg = 0x00009888, .val = 0x08050800 },
         { .reg = 0x00009888, .val = 0x0C050B00 },
         { .reg = 0x00009888, .val = 0x10050BC0 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080707 },
         { .reg = 0x00009888, .val = 0x02080707 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x160503C0 },
         { .reg = 0x00009888, .val = 0x06051000 },
         { .reg = 0x00009888, .val = 0x00020303 },
         { .reg = 0x00009888, .val = 0x02020303 },
         { .reg = 0x00009888, .val = 0x00040101 },
         { .reg = 0x00009888, .val = 0x02040101 },
         { .reg = 0x00009888, .val = 0x02051004 },
         { .reg = 0x00009888, .val = 0x04050014 },
         { .reg = 0x00009888, .val = 0x08050020 },
         { .reg = 0x00009888, .val = 0x0C05002C },
         { .reg = 0x00009888, .val = 0x1005002F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080101 },
         { .reg = 0x00009888, .val = 0x02080101 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00130A0A },
         { .reg = 0x00009888, .val = 0x02130A0A },
         { .reg = 0x00009888, .val = 0x00140505 },
         { .reg = 0x00009888, .val = 0x02140505 },
         { .reg = 0x00009888, .val = 0x00150505 },
         { .reg = 0x00009888, .val = 0x02150505 },
         { .reg = 0x00009888, .val = 0x00160505 },
         { .reg = 0x00009888, .val = 0x02160505 },
         { .reg = 0x00009888, .val = 0x00170A0A },
         { .reg = 0x00009888, .val = 0x02170A0A },
         { .reg = 0x00009888, .val = 0x000C3333 },
         { .reg = 0x00009888, .val = 0x000E3333 },
         { .reg = 0x00009888, .val = 0x000D0A0A },
         { .reg = 0x00009888, .val = 0x020D0A0A },
         { .reg = 0x00009888, .val = 0x00060A0A },
         { .reg = 0x00009888, .val = 0x02060A0A },
         { .reg = 0x00009888, .val = 0x0001FAFA },
         { .reg = 0x00009888, .val = 0x0201FAFA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58011203 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010290 },
         { .reg = 0x00009888, .val = 0x60010001 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010229 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext171__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext171__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext171__avg_gpu_core_frequency__max,mtlgt2__ext171__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6112, 24, NULL,mtlgt2__ext171__rt_quad_test_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6113, 32, NULL,mtlgt2__ext171__rt_quad_test_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6114, 40, NULL,mtlgt2__ext171__rt_quad_test_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6115, 48, NULL,mtlgt2__ext171__rt_quad_test_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6116, 56, NULL,mtlgt2__ext171__rt_transform_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6117, 64, NULL,mtlgt2__ext171__rt_transform_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6118, 72, NULL,mtlgt2__ext171__rt_transform_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6119, 80, NULL,mtlgt2__ext171__rt_transform_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6120, 88, NULL,mtlgt2__ext171__rt_request_collision_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6121, 96, NULL,mtlgt2__ext171__rt_request_collision_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6122, 104, NULL,mtlgt2__ext171__rt_request_collision_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6123, 112, NULL,mtlgt2__ext171__rt_request_collision_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6124, 120, percentage_max_float,mtlgt2__ext171__rt_message_stall_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6125, 124, percentage_max_float,mtlgt2__ext171__rt_message_stall_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6126, 128, percentage_max_float,mtlgt2__ext171__rt_message_stall_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6127, 132, percentage_max_float,mtlgt2__ext171__rt_message_stall_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext173_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext173";
   query->symbol_name = "Ext173";
   query->guid = "5005db3a-31a9-498c-8153-bf47147473b1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0A200236 },
         { .reg = 0x00009888, .val = 0x0C20016A },
         { .reg = 0x00009888, .val = 0x002052B2 },
         { .reg = 0x00009888, .val = 0x022062F3 },
         { .reg = 0x00009888, .val = 0x04201CC1 },
         { .reg = 0x00009888, .val = 0x08204051 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF03 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045501 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA02 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FF03 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext173__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext173__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext173__avg_gpu_core_frequency__max,mtlgt2__ext173__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6128, 24, percentage_max_float,mtlgt2__ext173__xve_stall_aluwr_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6129, 28, percentage_max_float,mtlgt2__ext173__xve_stall_barrier_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6130, 32, percentage_max_float,mtlgt2__ext173__xve_stall_instfetch_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6131, 36, percentage_max_float,mtlgt2__ext173__xve_stall_other_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6132, 40, percentage_max_float,mtlgt2__ext173__xve_stall_sbid_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6133, 44, percentage_max_float,mtlgt2__ext173__xve_shared_function_access_hold_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6134, 48, percentage_max_float,mtlgt2__ext173__xve_stall_control_xecore0_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext174_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext174";
   query->symbol_name = "Ext174";
   query->guid = "3e2a351c-3f4f-461a-a6cf-64f099b83fc5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0A200236 },
         { .reg = 0x00009888, .val = 0x0C20016A },
         { .reg = 0x00009888, .val = 0x002052B2 },
         { .reg = 0x00009888, .val = 0x022062F3 },
         { .reg = 0x00009888, .val = 0x04201CC1 },
         { .reg = 0x00009888, .val = 0x08204051 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF03 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045501 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA02 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF03 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045501 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF03 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FF03 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext174__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext174__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext174__avg_gpu_core_frequency__max,mtlgt2__ext174__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6135, 24, percentage_max_float,mtlgt2__ext174__xve_stall_aluwr_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6136, 28, percentage_max_float,mtlgt2__ext174__xve_stall_barrier_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6137, 32, percentage_max_float,mtlgt2__ext174__xve_stall_instfetch_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6138, 36, percentage_max_float,mtlgt2__ext174__xve_stall_other_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6139, 40, percentage_max_float,mtlgt2__ext174__xve_stall_sbid_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6140, 44, percentage_max_float,mtlgt2__ext174__xve_shared_function_access_hold_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6141, 48, percentage_max_float,mtlgt2__ext174__xve_stall_control_xecore1_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext175_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext175";
   query->symbol_name = "Ext175";
   query->guid = "14c17f9b-021b-41e5-a4f0-ab8daaad56a4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0A200236 },
         { .reg = 0x00009888, .val = 0x0C20016A },
         { .reg = 0x00009888, .val = 0x002052B2 },
         { .reg = 0x00009888, .val = 0x022062F3 },
         { .reg = 0x00009888, .val = 0x04201CC1 },
         { .reg = 0x00009888, .val = 0x08204051 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF03 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045501 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA02 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AA02 },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145501 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155501 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165501 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AA02 },
         { .reg = 0x00009888, .val = 0x000CF1FF },
         { .reg = 0x00009888, .val = 0x000EF1FF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAA02 },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AA02 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AA02 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext175__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext175__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext175__avg_gpu_core_frequency__max,mtlgt2__ext175__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6142, 24, percentage_max_float,mtlgt2__ext175__xve_stall_aluwr_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6143, 28, percentage_max_float,mtlgt2__ext175__xve_stall_barrier_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6144, 32, percentage_max_float,mtlgt2__ext175__xve_stall_instfetch_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6145, 36, percentage_max_float,mtlgt2__ext175__xve_stall_other_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6146, 40, percentage_max_float,mtlgt2__ext175__xve_stall_sbid_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6147, 44, percentage_max_float,mtlgt2__ext175__xve_shared_function_access_hold_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6148, 48, percentage_max_float,mtlgt2__ext175__xve_stall_control_xecore2_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext176_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext176";
   query->symbol_name = "Ext176";
   query->guid = "a258d429-a165-4fed-bbcb-c743a09dd68f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0A200236 },
         { .reg = 0x00009888, .val = 0x0C20016A },
         { .reg = 0x00009888, .val = 0x002052B2 },
         { .reg = 0x00009888, .val = 0x022062F3 },
         { .reg = 0x00009888, .val = 0x04201CC1 },
         { .reg = 0x00009888, .val = 0x08204051 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF03 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045501 },
         { .reg = 0x00009888, .val = 0x0008AAAA },
         { .reg = 0x00009888, .val = 0x0208AA02 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF03 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045501 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FF03 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AA02 },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145501 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155501 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165501 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AA02 },
         { .reg = 0x00009888, .val = 0x000CF1FF },
         { .reg = 0x00009888, .val = 0x000EF1FF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAA02 },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AA02 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AA02 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext176__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext176__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext176__avg_gpu_core_frequency__max,mtlgt2__ext176__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6149, 24, percentage_max_float,mtlgt2__ext176__xve_stall_aluwr_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6150, 28, percentage_max_float,mtlgt2__ext176__xve_stall_barrier_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6151, 32, percentage_max_float,mtlgt2__ext176__xve_stall_instfetch_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6152, 36, percentage_max_float,mtlgt2__ext176__xve_stall_other_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6153, 40, percentage_max_float,mtlgt2__ext176__xve_stall_sbid_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6154, 44, percentage_max_float,mtlgt2__ext176__xve_shared_function_access_hold_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6155, 48, percentage_max_float,mtlgt2__ext176__xve_stall_control_xecore3_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext177_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext177";
   query->symbol_name = "Ext177";
   query->guid = "986b3512-df42-4300-a3fb-3a0d5835b5dc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0C200006 },
         { .reg = 0x00009888, .val = 0x0A200016 },
         { .reg = 0x00009888, .val = 0x00200000 },
         { .reg = 0x00009888, .val = 0x0202F000 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x0208B000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0C200006 },
         { .reg = 0x00009888, .val = 0x08205800 },
         { .reg = 0x00009888, .val = 0x00200000 },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x02041000 },
         { .reg = 0x00009888, .val = 0x02082000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0C200006 },
         { .reg = 0x00009888, .val = 0x082002C0 },
         { .reg = 0x00009888, .val = 0x00200000 },
         { .reg = 0x00009888, .val = 0x000203FF },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x000803FF },
         { .reg = 0x00009888, .val = 0x02080B00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0A206F40 },
         { .reg = 0x00009888, .val = 0x0C200006 },
         { .reg = 0x00009888, .val = 0x00204EB4 },
         { .reg = 0x00009888, .val = 0x02200166 },
         { .reg = 0x00009888, .val = 0x08200016 },
         { .reg = 0x00009888, .val = 0x000203FF },
         { .reg = 0x00009888, .val = 0x02020300 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x02040100 },
         { .reg = 0x00009888, .val = 0x000802AA },
         { .reg = 0x00009888, .val = 0x02080200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x14127800 },
         { .reg = 0x00009888, .val = 0x0E120025 },
         { .reg = 0x00009888, .val = 0x02120000 },
         { .reg = 0x00009888, .val = 0x00120000 },
         { .reg = 0x00009888, .val = 0x001302AA },
         { .reg = 0x00009888, .val = 0x02130AC0 },
         { .reg = 0x00009888, .val = 0x00140155 },
         { .reg = 0x00009888, .val = 0x02140500 },
         { .reg = 0x00009888, .val = 0x00150155 },
         { .reg = 0x00009888, .val = 0x02150500 },
         { .reg = 0x00009888, .val = 0x00160155 },
         { .reg = 0x00009888, .val = 0x02160540 },
         { .reg = 0x00009888, .val = 0x001702AA },
         { .reg = 0x00009888, .val = 0x02170A00 },
         { .reg = 0x00009888, .val = 0x000C381F },
         { .reg = 0x00009888, .val = 0x000E381F },
         { .reg = 0x00009888, .val = 0x000D02AA },
         { .reg = 0x00009888, .val = 0x020D0A00 },
         { .reg = 0x00009888, .val = 0x000602AA },
         { .reg = 0x00009888, .val = 0x02060A80 },
         { .reg = 0x00009888, .val = 0x000102AA },
         { .reg = 0x00009888, .val = 0x0201FA80 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x50011200 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000F8 },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext177__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext177__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext177__avg_gpu_core_frequency__max,mtlgt2__ext177__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6156, 24, percentage_max_float,mtlgt2__ext177__xve_stall_pipestall_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6157, 28, percentage_max_float,mtlgt2__ext177__xve_stall_pipestall_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6158, 32, percentage_max_float,mtlgt2__ext177__xve_stall_pipestall_xecore2_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6159, 36, percentage_max_float,mtlgt2__ext177__xve_stall_pipestall_xecore3_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6160, 40, NULL,mtlgt2__ext177__xve_inst_issued_all_xecore3_xve0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6161, 48, NULL,mtlgt2__ext177__render_cache_alloc_l3_node0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext181_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext181";
   query->symbol_name = "Ext181";
   query->guid = "29b4890b-203f-44d7-a007-270354d414ed";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0A206F40 },
         { .reg = 0x00009888, .val = 0x0C200006 },
         { .reg = 0x00009888, .val = 0x00204EB4 },
         { .reg = 0x00009888, .val = 0x02200166 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x0008FEAA },
         { .reg = 0x00009888, .val = 0x0208000F },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0A206F40 },
         { .reg = 0x00009888, .val = 0x0C200006 },
         { .reg = 0x00009888, .val = 0x02205000 },
         { .reg = 0x00009888, .val = 0x04201A75 },
         { .reg = 0x00009888, .val = 0x0620000B },
         { .reg = 0x00009888, .val = 0x00200000 },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208000A },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0A206F40 },
         { .reg = 0x00009888, .val = 0x0C200006 },
         { .reg = 0x00009888, .val = 0x06205680 },
         { .reg = 0x00009888, .val = 0x08202CD3 },
         { .reg = 0x00009888, .val = 0x00200000 },
         { .reg = 0x00009888, .val = 0x02023FF0 },
         { .reg = 0x00009888, .val = 0x02041550 },
         { .reg = 0x00009888, .val = 0x02082AA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02132AA0 },
         { .reg = 0x00009888, .val = 0x02141550 },
         { .reg = 0x00009888, .val = 0x02151550 },
         { .reg = 0x00009888, .val = 0x02161550 },
         { .reg = 0x00009888, .val = 0x02172AA0 },
         { .reg = 0x00009888, .val = 0x000C7C00 },
         { .reg = 0x00009888, .val = 0x000E7C00 },
         { .reg = 0x00009888, .val = 0x020D2AA0 },
         { .reg = 0x00009888, .val = 0x02062AA0 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x02012AAF },
         { .reg = 0x00009888, .val = 0x4E010090 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58011209 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C010C09 },
         { .reg = 0x00009888, .val = 0x5E010060 },
         { .reg = 0x00009888, .val = 0x60010C06 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010060 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000F8 },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F00 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E000 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext181__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext181__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext181__avg_gpu_core_frequency__max,mtlgt2__ext181__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6162, 24, NULL,mtlgt2__ext181__xve_inst_issued_all_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6163, 32, NULL,mtlgt2__ext181__xve_inst_issued_all_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6164, 40, NULL,mtlgt2__ext181__xve_inst_issued_all_xecore2_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext184_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext184";
   query->symbol_name = "Ext184";
   query->guid = "87ec0ca0-a406-4ddb-9fb9-60beed37e12a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x08080BE7 },
         { .reg = 0x00009888, .val = 0x0A080FF7 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x0C080BE7 },
         { .reg = 0x00009888, .val = 0x0E080FF7 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x10080BE7 },
         { .reg = 0x00009888, .val = 0x12080FF7 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x14080BE7 },
         { .reg = 0x00009888, .val = 0x16080FF7 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext184__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext184__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext184__avg_gpu_core_frequency__max,mtlgt2__ext184__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6165, 24, NULL,mtlgt2__ext184__rt_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6166, 32, NULL,mtlgt2__ext184__rt_load_store_cache_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6167, 40, NULL,mtlgt2__ext184__rt_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6168, 48, NULL,mtlgt2__ext184__rt_load_store_cache_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext188_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext188";
   query->symbol_name = "Ext188";
   query->guid = "11c77c80-498e-4cad-9e2d-565a52fd3578";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x08080BE7 },
         { .reg = 0x00009888, .val = 0x0A080FF7 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x0C080BE7 },
         { .reg = 0x00009888, .val = 0x0E080FF7 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x10080BE7 },
         { .reg = 0x00009888, .val = 0x12080FF7 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x14080BE7 },
         { .reg = 0x00009888, .val = 0x16080FF7 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext188__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext188__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext188__avg_gpu_core_frequency__max,mtlgt2__ext188__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6169, 24, NULL,mtlgt2__ext188__rt_load_store_cache_write_from_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6170, 32, NULL,mtlgt2__ext188__rt_load_store_cache_write_from_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6171, 40, NULL,mtlgt2__ext188__rt_load_store_cache_write_from_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6172, 48, NULL,mtlgt2__ext188__rt_load_store_cache_write_from_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext190_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext190";
   query->symbol_name = "Ext190";
   query->guid = "123714d3-5d52-49de-91eb-0c909557d221";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18060005 },
         { .reg = 0x00009888, .val = 0x0002FFAA },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02060020 },
         { .reg = 0x00009888, .val = 0x04060554 },
         { .reg = 0x00009888, .val = 0x060605D6 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0008FF00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18060005 },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02060020 },
         { .reg = 0x00009888, .val = 0x08060554 },
         { .reg = 0x00009888, .val = 0x0A0605D6 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18060005 },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02060020 },
         { .reg = 0x00009888, .val = 0x0C060554 },
         { .reg = 0x00009888, .val = 0x0E0605D6 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x0208FF00 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18060005 },
         { .reg = 0x00009888, .val = 0x0202AA00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02060020 },
         { .reg = 0x00009888, .val = 0x10060554 },
         { .reg = 0x00009888, .val = 0x120605D6 },
         { .reg = 0x00009888, .val = 0x04060000 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext190__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext190__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext190__avg_gpu_core_frequency__max,mtlgt2__ext190__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6173, 24, percentage_max_float,mtlgt2__ext190__pixel_post_process_input_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6174, 28, percentage_max_float,mtlgt2__ext190__pixel_post_process_input_available_cpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext192_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext192";
   query->symbol_name = "Ext192";
   query->guid = "d2741830-1ee3-42ab-b578-2b9c31a69c1c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x160502A0 },
         { .reg = 0x00009888, .val = 0x1A055F80 },
         { .reg = 0x00009888, .val = 0x000200FF },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02053804 },
         { .reg = 0x00009888, .val = 0x04050308 },
         { .reg = 0x00009888, .val = 0x12050A20 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x000800F5 },
         { .reg = 0x00009888, .val = 0x02085F00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x160502A0 },
         { .reg = 0x00009888, .val = 0x1A055F80 },
         { .reg = 0x00009888, .val = 0x000200F0 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x02053804 },
         { .reg = 0x00009888, .val = 0x060500C2 },
         { .reg = 0x00009888, .val = 0x10050A20 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080050 },
         { .reg = 0x00009888, .val = 0x02080500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x160502A0 },
         { .reg = 0x00009888, .val = 0x1A055F80 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02053804 },
         { .reg = 0x00009888, .val = 0x080500C2 },
         { .reg = 0x00009888, .val = 0x0E050A20 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0008F500 },
         { .reg = 0x00009888, .val = 0x0208005F },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x160502A0 },
         { .reg = 0x00009888, .val = 0x1A055F80 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x02053804 },
         { .reg = 0x00009888, .val = 0x0A0500C2 },
         { .reg = 0x00009888, .val = 0x0C050A20 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085000 },
         { .reg = 0x00009888, .val = 0x02080005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AA00 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00145500 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00155500 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00165500 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x0017AA00 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0FF0 },
         { .reg = 0x00009888, .val = 0x000E0FF0 },
         { .reg = 0x00009888, .val = 0x000DAA00 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x0006AA00 },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001AAFF },
         { .reg = 0x00009888, .val = 0x0201FFAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010211 },
         { .reg = 0x00009888, .val = 0x58011201 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010090 },
         { .reg = 0x00009888, .val = 0x54010229 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext192__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext192__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext192__avg_gpu_core_frequency__max,mtlgt2__ext192__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6175, 24, percentage_max_float,mtlgt2__ext192__rt_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6176, 28, percentage_max_float,mtlgt2__ext192__rt_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6177, 32, percentage_max_float,mtlgt2__ext192__rt_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6178, 36, percentage_max_float,mtlgt2__ext192__rt_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6179, 40, NULL,mtlgt2__ext192__rt_traversal_step_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6180, 48, NULL,mtlgt2__ext192__rt_traversal_step_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6181, 56, NULL,mtlgt2__ext192__rt_traversal_step_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6182, 64, NULL,mtlgt2__ext192__rt_traversal_step_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext195_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext195";
   query->symbol_name = "Ext195";
   query->guid = "d41508b5-921c-4033-a2f0-8a88aad4e718";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0A202960 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x002039E0 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x0204D000 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x16070980 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x00080FEA },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x0A202960 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x022039E0 },
         { .reg = 0x00009888, .val = 0x00200000 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x00040540 },
         { .reg = 0x00009888, .val = 0x02043000 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x16070026 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x00080A80 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0A202960 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x042039E0 },
         { .reg = 0x00009888, .val = 0x00200000 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x020203FF },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040D55 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x14070980 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x020803FE },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x0A202960 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x062039E0 },
         { .reg = 0x00009888, .val = 0x00200000 },
         { .reg = 0x00009888, .val = 0x020200FC },
         { .reg = 0x00009888, .val = 0x02040354 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x14070026 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x020800A8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013A000 },
         { .reg = 0x00009888, .val = 0x02130AAA },
         { .reg = 0x00009888, .val = 0x00145000 },
         { .reg = 0x00009888, .val = 0x02140555 },
         { .reg = 0x00009888, .val = 0x00155000 },
         { .reg = 0x00009888, .val = 0x02150555 },
         { .reg = 0x00009888, .val = 0x00165000 },
         { .reg = 0x00009888, .val = 0x02160555 },
         { .reg = 0x00009888, .val = 0x0017A000 },
         { .reg = 0x00009888, .val = 0x02170AAA },
         { .reg = 0x00009888, .val = 0x000C3FC0 },
         { .reg = 0x00009888, .val = 0x000E3FC0 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x020D0AAA },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x02060AAA },
         { .reg = 0x00009888, .val = 0x0001AFFF },
         { .reg = 0x00009888, .val = 0x0201FAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010221 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010010 },
         { .reg = 0x00009888, .val = 0x54011404 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext195__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext195__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext195__avg_gpu_core_frequency__max,mtlgt2__ext195__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6183, 24, percentage_max_float,mtlgt2__ext195__xve_multiple_pipe_active_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6184, 28, percentage_max_float,mtlgt2__ext195__xve_multiple_pipe_active_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6185, 32, percentage_max_float,mtlgt2__ext195__xve_multiple_pipe_active_xecore2_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6186, 36, percentage_max_float,mtlgt2__ext195__xve_multiple_pipe_active_xecore3_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6187, 40, NULL,mtlgt2__ext195__gpgpu_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6188, 48, NULL,mtlgt2__ext195__gpgpu_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6189, 56, NULL,mtlgt2__ext195__gpgpu_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6190, 64, NULL,mtlgt2__ext195__gpgpu_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext200_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext200";
   query->symbol_name = "Ext200";
   query->guid = "73a53c50-0922-4d77-87d9-13b18d368e4e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x180802D5 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x080801C6 },
         { .reg = 0x00009888, .val = 0x0A080008 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x180802D5 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x00040540 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x0A080180 },
         { .reg = 0x00009888, .val = 0x0C080207 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x180802D5 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x0E0801C6 },
         { .reg = 0x00009888, .val = 0x10080008 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x020800FC },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x180802D5 },
         { .reg = 0x00009888, .val = 0x020200FC },
         { .reg = 0x00009888, .val = 0x02040054 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x10080180 },
         { .reg = 0x00009888, .val = 0x12080207 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013A000 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00145000 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00155000 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00165000 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x0017A000 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0FC0 },
         { .reg = 0x00009888, .val = 0x000E0FC0 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001AFFF },
         { .reg = 0x00009888, .val = 0x020100AA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext200__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext200__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext200__avg_gpu_core_frequency__max,mtlgt2__ext200__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6191, 24, NULL,mtlgt2__ext200__slm_access_count_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6192, 32, NULL,mtlgt2__ext200__slm_access_count_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6193, 40, NULL,mtlgt2__ext200__slm_access_count_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6194, 48, NULL,mtlgt2__ext200__slm_access_count_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext201_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext201";
   query->symbol_name = "Ext201";
   query->guid = "32b9a4f4-b1f0-478f-8998-d86e5c5c458f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x1E080016 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x04080098 },
         { .reg = 0x00009888, .val = 0x080801C6 },
         { .reg = 0x00009888, .val = 0x0A080008 },
         { .reg = 0x00009888, .val = 0x00080FC0 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x1E080016 },
         { .reg = 0x00009888, .val = 0x00020FC0 },
         { .reg = 0x00009888, .val = 0x00040540 },
         { .reg = 0x00009888, .val = 0x04080098 },
         { .reg = 0x00009888, .val = 0x0A080180 },
         { .reg = 0x00009888, .val = 0x0C080207 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x1E080016 },
         { .reg = 0x00009888, .val = 0x0002F000 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x04080098 },
         { .reg = 0x00009888, .val = 0x0E0801C6 },
         { .reg = 0x00009888, .val = 0x10080008 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x020800FC },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x1E080016 },
         { .reg = 0x00009888, .val = 0x020200FC },
         { .reg = 0x00009888, .val = 0x02040054 },
         { .reg = 0x00009888, .val = 0x04080098 },
         { .reg = 0x00009888, .val = 0x10080180 },
         { .reg = 0x00009888, .val = 0x12080207 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013A000 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x00145000 },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x00155000 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x00165000 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x0017A000 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0FC0 },
         { .reg = 0x00009888, .val = 0x000E0FC0 },
         { .reg = 0x00009888, .val = 0x000DA000 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x0006A000 },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0001AFFF },
         { .reg = 0x00009888, .val = 0x020100AA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010090 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext201__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext201__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext201__avg_gpu_core_frequency__max,mtlgt2__ext201__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6195, 24, NULL,mtlgt2__ext201__slm_access_count_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6196, 32, NULL,mtlgt2__ext201__slm_access_count_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6197, 40, NULL,mtlgt2__ext201__slm_access_count_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6198, 48, NULL,mtlgt2__ext201__slm_access_count_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext202_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext202";
   query->symbol_name = "Ext202";
   query->guid = "e1606d82-b67b-4fd8-9b07-a769dd6e6581";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C0700A0 },
         { .reg = 0x00009888, .val = 0x00065555 },
         { .reg = 0x00009888, .val = 0x02060001 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x02010002 },
         { .reg = 0x00009888, .val = 0x04070076 },
         { .reg = 0x00009888, .val = 0x08070207 },
         { .reg = 0x00009888, .val = 0x0A070289 },
         { .reg = 0x00009888, .val = 0x0C07030B },
         { .reg = 0x00009888, .val = 0x0E07038D },
         { .reg = 0x00009888, .val = 0x1007000F },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext202__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext202__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext202__avg_gpu_core_frequency__max,mtlgt2__ext202__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6199, 24, NULL,mtlgt2__ext202__gpu_memory_l3_write_sqidi0__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext203_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext203";
   query->symbol_name = "Ext203";
   query->guid = "16647b5e-c9e4-4201-afc2-cb47a9f3f4d2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x180800A0 },
         { .reg = 0x00009888, .val = 0x00065555 },
         { .reg = 0x00009888, .val = 0x02060001 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x02010002 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070001 },
         { .reg = 0x00009888, .val = 0x00080076 },
         { .reg = 0x00009888, .val = 0x04080207 },
         { .reg = 0x00009888, .val = 0x06080289 },
         { .reg = 0x00009888, .val = 0x0808030B },
         { .reg = 0x00009888, .val = 0x0A08038D },
         { .reg = 0x00009888, .val = 0x0C08000F },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext203__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext203__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext203__avg_gpu_core_frequency__max,mtlgt2__ext203__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6200, 24, NULL,mtlgt2__ext203__gpu_memory_l3_write_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext204_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext204";
   query->symbol_name = "Ext204";
   query->guid = "639a17e1-f339-49ab-9884-6b9a91a5a0c8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x04052580 },
         { .reg = 0x00009888, .val = 0x06050B68 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0008FF55 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x08050960 },
         { .reg = 0x00009888, .val = 0x0A050B68 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x0C050960 },
         { .reg = 0x00009888, .val = 0x0E050B68 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208FF55 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x10050960 },
         { .reg = 0x00009888, .val = 0x12050B68 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext204__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext204__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext204__avg_gpu_core_frequency__max,mtlgt2__ext204__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6201, 24, NULL,mtlgt2__ext204__rt_internal_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6202, 32, NULL,mtlgt2__ext204__rt_internal_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6203, 40, NULL,mtlgt2__ext204__rt_internal_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6204, 48, NULL,mtlgt2__ext204__rt_internal_node_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext205_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext205";
   query->symbol_name = "Ext205";
   query->guid = "7420acf6-1809-41e3-b5d1-49455c60aa66";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x04052780 },
         { .reg = 0x00009888, .val = 0x06050BE8 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0008FF55 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x080509E0 },
         { .reg = 0x00009888, .val = 0x0A050BE8 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x0C0509E0 },
         { .reg = 0x00009888, .val = 0x0E050BE8 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208FF55 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x100509E0 },
         { .reg = 0x00009888, .val = 0x12050BE8 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFF00 },
         { .reg = 0x00009888, .val = 0x000EFF00 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010200 },
         { .reg = 0x00009888, .val = 0x58010221 },
         { .reg = 0x00009888, .val = 0x5A010011 },
         { .reg = 0x00009888, .val = 0x5C011209 },
         { .reg = 0x00009888, .val = 0x5E010090 },
         { .reg = 0x00009888, .val = 0x60010609 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext205__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext205__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext205__avg_gpu_core_frequency__max,mtlgt2__ext205__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6205, 24, NULL,mtlgt2__ext205__rt_instance_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6206, 32, NULL,mtlgt2__ext205__rt_instance_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6207, 40, NULL,mtlgt2__ext205__rt_instance_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6208, 48, NULL,mtlgt2__ext205__rt_instance_node_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext212_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext212";
   query->symbol_name = "Ext212";
   query->guid = "015d134a-1b6e-4969-b972-b904c1d0cc85";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x04052580 },
         { .reg = 0x00009888, .val = 0x060509E6 },
         { .reg = 0x00009888, .val = 0x08050B68 },
         { .reg = 0x00009888, .val = 0x0A050BEE },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x0C050960 },
         { .reg = 0x00009888, .val = 0x0E0509E6 },
         { .reg = 0x00009888, .val = 0x10050B68 },
         { .reg = 0x00009888, .val = 0x12050BEE },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010003 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x0000002A },
         { .reg = 0x0000D954, .val = 0x0000FFFA },
         { .reg = 0x0000D958, .val = 0x00000282 },
         { .reg = 0x0000D95C, .val = 0x0000FFAF },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000F0FF },
         { .reg = 0x0000D968, .val = 0x00008002 },
         { .reg = 0x0000D96C, .val = 0x00000FFF },
         { .reg = 0x0000D970, .val = 0x00002802 },
         { .reg = 0x0000D974, .val = 0x0000FAFF },
         { .reg = 0x0000D978, .val = 0x00028002 },
         { .reg = 0x0000D97C, .val = 0x0000AFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext212__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext212__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext212__avg_gpu_core_frequency__max,mtlgt2__ext212__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6209, 24, NULL,mtlgt2__ext212__rt_quad_leaf_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6210, 32, NULL,mtlgt2__ext212__rt_procedural_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6211, 40, NULL,mtlgt2__ext212__rt_quad_leaf_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6212, 48, NULL,mtlgt2__ext212__rt_procedural_node_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext214_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext214";
   query->symbol_name = "Ext214";
   query->guid = "191eb41b-6180-4cf9-b3fb-048bf4da8b94";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x04052580 },
         { .reg = 0x00009888, .val = 0x060509E6 },
         { .reg = 0x00009888, .val = 0x08050B68 },
         { .reg = 0x00009888, .val = 0x0A050BEE },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1A0572E0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x02053800 },
         { .reg = 0x00009888, .val = 0x0C050960 },
         { .reg = 0x00009888, .val = 0x0E0509E6 },
         { .reg = 0x00009888, .val = 0x10050B68 },
         { .reg = 0x00009888, .val = 0x12050BEE },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085555 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x60010003 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x0000002A },
         { .reg = 0x0000D954, .val = 0x0000FFFA },
         { .reg = 0x0000D958, .val = 0x00000282 },
         { .reg = 0x0000D95C, .val = 0x0000FFAF },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000F0FF },
         { .reg = 0x0000D968, .val = 0x00008002 },
         { .reg = 0x0000D96C, .val = 0x00000FFF },
         { .reg = 0x0000D970, .val = 0x00002802 },
         { .reg = 0x0000D974, .val = 0x0000FAFF },
         { .reg = 0x0000D978, .val = 0x00028002 },
         { .reg = 0x0000D97C, .val = 0x0000AFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext214__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext214__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext214__avg_gpu_core_frequency__max,mtlgt2__ext214__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6213, 24, NULL,mtlgt2__ext214__rt_quad_leaf_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6214, 32, NULL,mtlgt2__ext214__rt_procedural_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6215, 40, NULL,mtlgt2__ext214__rt_quad_leaf_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6216, 48, NULL,mtlgt2__ext214__rt_procedural_node_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext220_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext220";
   query->symbol_name = "Ext220";
   query->guid = "840ad20c-c8ba-4dd5-bc42-674987d6ec79";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x14050000 },
         { .reg = 0x00009888, .val = 0x0202FF00 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x02050002 },
         { .reg = 0x00009888, .val = 0x12050001 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02085F00 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x14050000 },
         { .reg = 0x00009888, .val = 0x02020F00 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x02050002 },
         { .reg = 0x00009888, .val = 0x10050001 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02080500 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x14050000 },
         { .reg = 0x00009888, .val = 0x020200FF },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x02050002 },
         { .reg = 0x00009888, .val = 0x0E050001 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x0208005F },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x14050000 },
         { .reg = 0x00009888, .val = 0x0202000F },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x02050002 },
         { .reg = 0x00009888, .val = 0x0C050001 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02080005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x021300AA },
         { .reg = 0x00009888, .val = 0x02140055 },
         { .reg = 0x00009888, .val = 0x02150055 },
         { .reg = 0x00009888, .val = 0x02160055 },
         { .reg = 0x00009888, .val = 0x021700AA },
         { .reg = 0x00009888, .val = 0x000C0F00 },
         { .reg = 0x00009888, .val = 0x000E0F00 },
         { .reg = 0x00009888, .val = 0x020D00AA },
         { .reg = 0x00009888, .val = 0x020600AA },
         { .reg = 0x00009888, .val = 0x0201FFAA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010090 },
         { .reg = 0x00009888, .val = 0x54010229 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext220__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext220__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext220__avg_gpu_core_frequency__max,mtlgt2__ext220__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6217, 24, NULL,mtlgt2__ext220__rt_bvh_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6218, 32, NULL,mtlgt2__ext220__rt_bvh_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6219, 40, NULL,mtlgt2__ext220__rt_bvh_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6220, 48, NULL,mtlgt2__ext220__rt_bvh_cache_miss_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext225_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext225";
   query->symbol_name = "Ext225";
   query->guid = "a8bfddc1-d469-45d6-8790-7d8c649ada41";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x24106C00 },
         { .reg = 0x00009888, .val = 0x2610001C },
         { .reg = 0x00009888, .val = 0x46020040 },
         { .reg = 0x00009888, .val = 0x00135555 },
         { .reg = 0x00009888, .val = 0x02130011 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02160011 },
         { .reg = 0x00009888, .val = 0x02106F60 },
         { .reg = 0x00009888, .val = 0x04100E35 },
         { .reg = 0x00009888, .val = 0x06100EB9 },
         { .reg = 0x00009888, .val = 0x08100F3B },
         { .reg = 0x00009888, .val = 0x0A100FBD },
         { .reg = 0x00009888, .val = 0x0C100FC0 },
         { .reg = 0x00009888, .val = 0x00100000 },
         { .reg = 0x00009888, .val = 0x000C05FF },
         { .reg = 0x00009888, .val = 0x000E05FF },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x02060022 },
         { .reg = 0x00009888, .val = 0x0802000E },
         { .reg = 0x00009888, .val = 0x12020033 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x02010026 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010040 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext225__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext225__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext225__avg_gpu_core_frequency__max,mtlgt2__ext225__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6221, 24, NULL,mtlgt2__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext227_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext227";
   query->symbol_name = "Ext227";
   query->guid = "325e5e9b-a055-4c22-8997-98d546a31afe";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x24106C00 },
         { .reg = 0x00009888, .val = 0x2610001C },
         { .reg = 0x00009888, .val = 0x46020040 },
         { .reg = 0x00009888, .val = 0x00135555 },
         { .reg = 0x00009888, .val = 0x02130011 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02160011 },
         { .reg = 0x00009888, .val = 0x02106F60 },
         { .reg = 0x00009888, .val = 0x04100E35 },
         { .reg = 0x00009888, .val = 0x06100EB9 },
         { .reg = 0x00009888, .val = 0x08100F3B },
         { .reg = 0x00009888, .val = 0x0A100FBD },
         { .reg = 0x00009888, .val = 0x0C100FC0 },
         { .reg = 0x00009888, .val = 0x00100000 },
         { .reg = 0x00009888, .val = 0x000C05FF },
         { .reg = 0x00009888, .val = 0x000E05FF },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x02060022 },
         { .reg = 0x00009888, .val = 0x0802000E },
         { .reg = 0x00009888, .val = 0x12020033 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x02010026 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010040 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF08000FE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext227__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext227__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext227__avg_gpu_core_frequency__max,mtlgt2__ext227__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6222, 24, NULL,mtlgt2__ext227__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext229_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext229";
   query->symbol_name = "Ext229";
   query->guid = "94537bb4-60fd-45fe-b172-29ed90c9abac";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x260814C0 },
         { .reg = 0x00009888, .val = 0x2C0800A6 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x10080C31 },
         { .reg = 0x00009888, .val = 0x12080FBF },
         { .reg = 0x00009888, .val = 0x14080821 },
         { .reg = 0x00009888, .val = 0x16080BAF },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x260814C0 },
         { .reg = 0x00009888, .val = 0x2C0800A6 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x08080C31 },
         { .reg = 0x00009888, .val = 0x0A080FBF },
         { .reg = 0x00009888, .val = 0x0C080821 },
         { .reg = 0x00009888, .val = 0x0E080BAF },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010600 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext229__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext229__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext229__avg_gpu_core_frequency__max,mtlgt2__ext229__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6223, 24, NULL,mtlgt2__ext229__slm_bank_conflict_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6224, 32, NULL,mtlgt2__ext229__slm_bank_conflict_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext231_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext231";
   query->symbol_name = "Ext231";
   query->guid = "7fceb68b-57e6-480d-81d1-991d8d6f7c4d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x260814C0 },
         { .reg = 0x00009888, .val = 0x2C0800A6 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x10080C31 },
         { .reg = 0x00009888, .val = 0x12080FBF },
         { .reg = 0x00009888, .val = 0x14080821 },
         { .reg = 0x00009888, .val = 0x16080BAF },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x260814C0 },
         { .reg = 0x00009888, .val = 0x2C0800A6 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x06081032 },
         { .reg = 0x00009888, .val = 0x08080C31 },
         { .reg = 0x00009888, .val = 0x0A080FBF },
         { .reg = 0x00009888, .val = 0x0C080821 },
         { .reg = 0x00009888, .val = 0x0E080BAF },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010600 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext231__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext231__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext231__avg_gpu_core_frequency__max,mtlgt2__ext231__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6225, 24, NULL,mtlgt2__ext231__slm_bank_conflict_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6226, 32, NULL,mtlgt2__ext231__slm_bank_conflict_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext237_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext237";
   query->symbol_name = "Ext237";
   query->guid = "ad62dc60-987b-415e-9f7d-6976fbe82dac";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0C012000 },
         { .reg = 0x00009888, .val = 0x0C412000 },
         { .reg = 0x00009888, .val = 0x0C812000 },
         { .reg = 0x00009888, .val = 0x0CC12000 },
         { .reg = 0x00009888, .val = 0x00010004 },
         { .reg = 0x00009888, .val = 0x12010080 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00410004 },
         { .reg = 0x00009888, .val = 0x12410002 },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00810004 },
         { .reg = 0x00009888, .val = 0x10810080 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00C10004 },
         { .reg = 0x00009888, .val = 0x10C10002 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00124000 },
         { .reg = 0x00009888, .val = 0x0213BA00 },
         { .reg = 0x00009888, .val = 0x02144900 },
         { .reg = 0x00009888, .val = 0x02158300 },
         { .reg = 0x00009888, .val = 0x02165500 },
         { .reg = 0x00009888, .val = 0x000CF000 },
         { .reg = 0x00009888, .val = 0x000EF000 },
         { .reg = 0x00009888, .val = 0x021A2000 },
         { .reg = 0x00009888, .val = 0x001B2000 },
         { .reg = 0x00009888, .val = 0x0206AA00 },
         { .reg = 0x00009888, .val = 0x0201AA00 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext237__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext237__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext237__avg_gpu_core_frequency__max,mtlgt2__ext237__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6227, 24, NULL,mtlgt2__ext237__l3_miss_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6228, 32, NULL,mtlgt2__ext237__l3_miss_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6229, 40, NULL,mtlgt2__ext237__l3_miss_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6230, 48, NULL,mtlgt2__ext237__l3_miss_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext238_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext238";
   query->symbol_name = "Ext238";
   query->guid = "e630dd77-cf9e-4deb-8f52-57506b306b63";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1E020220 },
         { .reg = 0x00009888, .val = 0x04022000 },
         { .reg = 0x00009888, .val = 0x16020026 },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1E020220 },
         { .reg = 0x00009888, .val = 0x04022000 },
         { .reg = 0x00009888, .val = 0x14020980 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02041000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1E020220 },
         { .reg = 0x00009888, .val = 0x04022000 },
         { .reg = 0x00009888, .val = 0x14020026 },
         { .reg = 0x00009888, .val = 0x02020300 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x02080300 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1E020220 },
         { .reg = 0x00009888, .val = 0x04022000 },
         { .reg = 0x00009888, .val = 0x12020980 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02040100 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1410014C },
         { .reg = 0x00009888, .val = 0x00130005 },
         { .reg = 0x00009888, .val = 0x02130A00 },
         { .reg = 0x00009888, .val = 0x02140500 },
         { .reg = 0x00009888, .val = 0x02150500 },
         { .reg = 0x00009888, .val = 0x00160005 },
         { .reg = 0x00009888, .val = 0x02160500 },
         { .reg = 0x00009888, .val = 0x02170A00 },
         { .reg = 0x00009888, .val = 0x0010001A },
         { .reg = 0x00009888, .val = 0x02100E00 },
         { .reg = 0x00009888, .val = 0x04100008 },
         { .reg = 0x00009888, .val = 0x000C3003 },
         { .reg = 0x00009888, .val = 0x000E3003 },
         { .reg = 0x00009888, .val = 0x020D0A00 },
         { .reg = 0x00009888, .val = 0x0006000A },
         { .reg = 0x00009888, .val = 0x02060A00 },
         { .reg = 0x00009888, .val = 0x0001000A },
         { .reg = 0x00009888, .val = 0x0201FA00 },
         { .reg = 0x00009888, .val = 0x4E010090 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010009 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext238__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext238__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext238__avg_gpu_core_frequency__max,mtlgt2__ext238__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6231, 24, NULL,mtlgt2__ext238__amfs_l3_write_slice0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6232, 32, NULL,mtlgt2__ext238__xve_dataport_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6233, 40, NULL,mtlgt2__ext238__xve_dataport_fence_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6234, 48, NULL,mtlgt2__ext238__xve_dataport_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6235, 56, NULL,mtlgt2__ext238__xve_dataport_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext239_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext239";
   query->symbol_name = "Ext239";
   query->guid = "6dfee12d-6bfc-434a-8873-bc076a47d80b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C0700C7 },
         { .reg = 0x00009888, .val = 0x180800A7 },
         { .reg = 0x00009888, .val = 0x00065555 },
         { .reg = 0x00009888, .val = 0x02065555 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x04070076 },
         { .reg = 0x00009888, .val = 0x08070205 },
         { .reg = 0x00009888, .val = 0x0A0702CA },
         { .reg = 0x00009888, .val = 0x0C07034C },
         { .reg = 0x00009888, .val = 0x0E0703CE },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x02075555 },
         { .reg = 0x00009888, .val = 0x00080076 },
         { .reg = 0x00009888, .val = 0x0C080207 },
         { .reg = 0x00009888, .val = 0x0E0802CA },
         { .reg = 0x00009888, .val = 0x1008034C },
         { .reg = 0x00009888, .val = 0x120803CE },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext239__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext239__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext239__avg_gpu_core_frequency__max,mtlgt2__ext239__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6236, 24, NULL,mtlgt2__ext239__gpu_memory_l3_read_sqidi0__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext240_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext240";
   query->symbol_name = "Ext240";
   query->guid = "5edd0480-7a46-49f7-8709-7f737d0cc42a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x1C0700A7 },
         { .reg = 0x00009888, .val = 0x180800C7 },
         { .reg = 0x00009888, .val = 0x00065555 },
         { .reg = 0x00009888, .val = 0x02065555 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x04070076 },
         { .reg = 0x00009888, .val = 0x10070207 },
         { .reg = 0x00009888, .val = 0x120702CA },
         { .reg = 0x00009888, .val = 0x1407034C },
         { .reg = 0x00009888, .val = 0x160703CE },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x00075555 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x00080076 },
         { .reg = 0x00009888, .val = 0x04080205 },
         { .reg = 0x00009888, .val = 0x060802CA },
         { .reg = 0x00009888, .val = 0x0808034C },
         { .reg = 0x00009888, .val = 0x0A0803CE },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext240__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext240__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext240__avg_gpu_core_frequency__max,mtlgt2__ext240__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6237, 24, NULL,mtlgt2__ext240__gpu_memory_l3_read_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext500_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext500";
   query->symbol_name = "Ext500";
   query->guid = "a7cd6b7e-e8ee-4853-b2d3-269bf3ed73c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x20020006 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x06024C00 },
         { .reg = 0x00009888, .val = 0x16020025 },
         { .reg = 0x00009888, .val = 0x0002000C },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x0008000C },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x20020006 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08020026 },
         { .reg = 0x00009888, .val = 0x14020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00040004 },
         { .reg = 0x00009888, .val = 0x02041000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x20020006 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08020980 },
         { .reg = 0x00009888, .val = 0x14020025 },
         { .reg = 0x00009888, .val = 0x000200C0 },
         { .reg = 0x00009888, .val = 0x02020300 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x000800C0 },
         { .reg = 0x00009888, .val = 0x02080300 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x20020006 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x0A020026 },
         { .reg = 0x00009888, .val = 0x12020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00040040 },
         { .reg = 0x00009888, .val = 0x02040100 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x001300A0 },
         { .reg = 0x00009888, .val = 0x02130A00 },
         { .reg = 0x00009888, .val = 0x00140050 },
         { .reg = 0x00009888, .val = 0x02140500 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x02150500 },
         { .reg = 0x00009888, .val = 0x00160050 },
         { .reg = 0x00009888, .val = 0x02160500 },
         { .reg = 0x00009888, .val = 0x001700A0 },
         { .reg = 0x00009888, .val = 0x02170A00 },
         { .reg = 0x00009888, .val = 0x000C300C },
         { .reg = 0x00009888, .val = 0x000E300C },
         { .reg = 0x00009888, .val = 0x000D00A0 },
         { .reg = 0x00009888, .val = 0x020D0A00 },
         { .reg = 0x00009888, .val = 0x000600A0 },
         { .reg = 0x00009888, .val = 0x02060A00 },
         { .reg = 0x00009888, .val = 0x000100AF },
         { .reg = 0x00009888, .val = 0x0201FA00 },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010609 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext500__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext500__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext500__avg_gpu_core_frequency__max,mtlgt2__ext500__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6238, 24, NULL,mtlgt2__ext500__icache_hit_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6239, 32, NULL,mtlgt2__ext500__icache_miss_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6240, 40, NULL,mtlgt2__ext500__icache_hit_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6241, 48, NULL,mtlgt2__ext500__icache_miss_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6242, 56, NULL,mtlgt2__ext500__icache_hit_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6243, 64, NULL,mtlgt2__ext500__icache_miss_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6244, 72, NULL,mtlgt2__ext500__icache_hit_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6245, 80, NULL,mtlgt2__ext500__icache_miss_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext501_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext501";
   query->symbol_name = "Ext501";
   query->guid = "8e09a7a1-b0e8-464a-a28d-90250f64ec9e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x2002000D },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x06024C00 },
         { .reg = 0x00009888, .val = 0x16020025 },
         { .reg = 0x00009888, .val = 0x0002000C },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x0008000C },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x2002000D },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08020026 },
         { .reg = 0x00009888, .val = 0x14020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00040004 },
         { .reg = 0x00009888, .val = 0x02041000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x2002000D },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08020980 },
         { .reg = 0x00009888, .val = 0x14020025 },
         { .reg = 0x00009888, .val = 0x000200C0 },
         { .reg = 0x00009888, .val = 0x02020300 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x000800C0 },
         { .reg = 0x00009888, .val = 0x02080300 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x2002000D },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x0A020026 },
         { .reg = 0x00009888, .val = 0x12020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00040040 },
         { .reg = 0x00009888, .val = 0x02040100 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x001300A0 },
         { .reg = 0x00009888, .val = 0x02130A00 },
         { .reg = 0x00009888, .val = 0x00140050 },
         { .reg = 0x00009888, .val = 0x02140500 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x02150500 },
         { .reg = 0x00009888, .val = 0x00160050 },
         { .reg = 0x00009888, .val = 0x02160500 },
         { .reg = 0x00009888, .val = 0x001700A0 },
         { .reg = 0x00009888, .val = 0x02170A00 },
         { .reg = 0x00009888, .val = 0x000C300C },
         { .reg = 0x00009888, .val = 0x000E300C },
         { .reg = 0x00009888, .val = 0x000D00A0 },
         { .reg = 0x00009888, .val = 0x020D0A00 },
         { .reg = 0x00009888, .val = 0x000600A0 },
         { .reg = 0x00009888, .val = 0x02060A00 },
         { .reg = 0x00009888, .val = 0x000100AF },
         { .reg = 0x00009888, .val = 0x0201FA00 },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010609 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext501__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext501__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext501__avg_gpu_core_frequency__max,mtlgt2__ext501__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6246, 24, NULL,mtlgt2__ext501__icache_hit_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6247, 32, NULL,mtlgt2__ext501__icache_miss_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6248, 40, NULL,mtlgt2__ext501__icache_hit_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6249, 48, NULL,mtlgt2__ext501__icache_miss_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6250, 56, NULL,mtlgt2__ext501__icache_hit_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6251, 64, NULL,mtlgt2__ext501__icache_miss_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6252, 72, NULL,mtlgt2__ext501__icache_hit_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6253, 80, NULL,mtlgt2__ext501__icache_miss_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext502_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext502";
   query->symbol_name = "Ext502";
   query->guid = "57a19b6a-1b7d-4337-a9c9-710c56c46f84";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x20020014 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x06024C00 },
         { .reg = 0x00009888, .val = 0x16020025 },
         { .reg = 0x00009888, .val = 0x0002000C },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x0008000C },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x20020014 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08020026 },
         { .reg = 0x00009888, .val = 0x14020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00040004 },
         { .reg = 0x00009888, .val = 0x02041000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x20020014 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08020980 },
         { .reg = 0x00009888, .val = 0x14020025 },
         { .reg = 0x00009888, .val = 0x000200C0 },
         { .reg = 0x00009888, .val = 0x02020300 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x000800C0 },
         { .reg = 0x00009888, .val = 0x02080300 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x20020014 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x0A020026 },
         { .reg = 0x00009888, .val = 0x12020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00040040 },
         { .reg = 0x00009888, .val = 0x02040100 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x001300A0 },
         { .reg = 0x00009888, .val = 0x02130A00 },
         { .reg = 0x00009888, .val = 0x00140050 },
         { .reg = 0x00009888, .val = 0x02140500 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x02150500 },
         { .reg = 0x00009888, .val = 0x00160050 },
         { .reg = 0x00009888, .val = 0x02160500 },
         { .reg = 0x00009888, .val = 0x001700A0 },
         { .reg = 0x00009888, .val = 0x02170A00 },
         { .reg = 0x00009888, .val = 0x000C300C },
         { .reg = 0x00009888, .val = 0x000E300C },
         { .reg = 0x00009888, .val = 0x000D00A0 },
         { .reg = 0x00009888, .val = 0x020D0A00 },
         { .reg = 0x00009888, .val = 0x000600A0 },
         { .reg = 0x00009888, .val = 0x02060A00 },
         { .reg = 0x00009888, .val = 0x000100AF },
         { .reg = 0x00009888, .val = 0x0201FA00 },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010609 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext502__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext502__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext502__avg_gpu_core_frequency__max,mtlgt2__ext502__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6254, 24, NULL,mtlgt2__ext502__icache_hit_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6255, 32, NULL,mtlgt2__ext502__icache_miss_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6256, 40, NULL,mtlgt2__ext502__icache_hit_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6257, 48, NULL,mtlgt2__ext502__icache_miss_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6258, 56, NULL,mtlgt2__ext502__icache_hit_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6259, 64, NULL,mtlgt2__ext502__icache_miss_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6260, 72, NULL,mtlgt2__ext502__icache_hit_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6261, 80, NULL,mtlgt2__ext502__icache_miss_bank2_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext503_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext503";
   query->symbol_name = "Ext503";
   query->guid = "394b21ab-311c-47a5-9b10-88159f5ac999";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x2002001B },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x06024C00 },
         { .reg = 0x00009888, .val = 0x16020025 },
         { .reg = 0x00009888, .val = 0x0002000C },
         { .reg = 0x00009888, .val = 0x02023000 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x0008000C },
         { .reg = 0x00009888, .val = 0x02083000 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x2002001B },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08020026 },
         { .reg = 0x00009888, .val = 0x14020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00040004 },
         { .reg = 0x00009888, .val = 0x02041000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x2002001B },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x08020980 },
         { .reg = 0x00009888, .val = 0x14020025 },
         { .reg = 0x00009888, .val = 0x000200C0 },
         { .reg = 0x00009888, .val = 0x02020300 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02040500 },
         { .reg = 0x00009888, .val = 0x000800C0 },
         { .reg = 0x00009888, .val = 0x02080300 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x2002001B },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x0A020026 },
         { .reg = 0x00009888, .val = 0x12020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00040040 },
         { .reg = 0x00009888, .val = 0x02040100 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x001300A0 },
         { .reg = 0x00009888, .val = 0x02130A00 },
         { .reg = 0x00009888, .val = 0x00140050 },
         { .reg = 0x00009888, .val = 0x02140500 },
         { .reg = 0x00009888, .val = 0x00150050 },
         { .reg = 0x00009888, .val = 0x02150500 },
         { .reg = 0x00009888, .val = 0x00160050 },
         { .reg = 0x00009888, .val = 0x02160500 },
         { .reg = 0x00009888, .val = 0x001700A0 },
         { .reg = 0x00009888, .val = 0x02170A00 },
         { .reg = 0x00009888, .val = 0x000C300C },
         { .reg = 0x00009888, .val = 0x000E300C },
         { .reg = 0x00009888, .val = 0x000D00A0 },
         { .reg = 0x00009888, .val = 0x020D0A00 },
         { .reg = 0x00009888, .val = 0x000600A0 },
         { .reg = 0x00009888, .val = 0x02060A00 },
         { .reg = 0x00009888, .val = 0x000100AF },
         { .reg = 0x00009888, .val = 0x0201FA00 },
         { .reg = 0x00009888, .val = 0x4E010011 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009888, .val = 0x58010609 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext503__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext503__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext503__avg_gpu_core_frequency__max,mtlgt2__ext503__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6262, 24, NULL,mtlgt2__ext503__icache_hit_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6263, 32, NULL,mtlgt2__ext503__icache_miss_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6264, 40, NULL,mtlgt2__ext503__icache_hit_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6265, 48, NULL,mtlgt2__ext503__icache_miss_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6266, 56, NULL,mtlgt2__ext503__icache_hit_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6267, 64, NULL,mtlgt2__ext503__icache_miss_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6268, 72, NULL,mtlgt2__ext503__icache_hit_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6269, 80, NULL,mtlgt2__ext503__icache_miss_bank3_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext508_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext508";
   query->symbol_name = "Ext508";
   query->guid = "143440a0-d7e2-4f41-8372-8fdca1ecc2a8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18080295 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x10080180 },
         { .reg = 0x00009888, .val = 0x12080105 },
         { .reg = 0x00009888, .val = 0x14080083 },
         { .reg = 0x00009888, .val = 0x160803C1 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFF0 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18080295 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x02020003 },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x0A080146 },
         { .reg = 0x00009888, .val = 0x0C0800C4 },
         { .reg = 0x00009888, .val = 0x0E080042 },
         { .reg = 0x00009888, .val = 0x1008000F },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFF0 },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext508__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext508__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext508__avg_gpu_core_frequency__max,mtlgt2__ext508__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6270, 24, NULL,mtlgt2__ext508__slm_byte_read_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6271, 32, NULL,mtlgt2__ext508__slm_byte_read_bank0_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext509_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext509";
   query->symbol_name = "Ext509";
   query->guid = "7c5d3f41-b690-44b2-8352-00215ac94bae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x10080180 },
         { .reg = 0x00009888, .val = 0x12080105 },
         { .reg = 0x00009888, .val = 0x14080083 },
         { .reg = 0x00009888, .val = 0x16080001 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFF0 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x02020003 },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x0A080146 },
         { .reg = 0x00009888, .val = 0x0C0800C4 },
         { .reg = 0x00009888, .val = 0x0E080042 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFF0 },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext509__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext509__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext509__avg_gpu_core_frequency__max,mtlgt2__ext509__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6272, 24, NULL,mtlgt2__ext509__slm_byte_read_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6273, 32, NULL,mtlgt2__ext509__slm_byte_read_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext510_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext510";
   query->symbol_name = "Ext510";
   query->guid = "02f43996-feff-4e13-a8fd-eea9de2f13fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18080295 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x10080180 },
         { .reg = 0x00009888, .val = 0x12080105 },
         { .reg = 0x00009888, .val = 0x14080083 },
         { .reg = 0x00009888, .val = 0x160803C1 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFF0 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18080295 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x02020003 },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x0A080146 },
         { .reg = 0x00009888, .val = 0x0C0800C4 },
         { .reg = 0x00009888, .val = 0x0E080042 },
         { .reg = 0x00009888, .val = 0x1008000F },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAA0 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145550 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155550 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165550 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAA0 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFC },
         { .reg = 0x00009888, .val = 0x000EFFFC },
         { .reg = 0x00009888, .val = 0x000DAAA0 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAA0 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAA0 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext510__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext510__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext510__avg_gpu_core_frequency__max,mtlgt2__ext510__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6274, 24, NULL,mtlgt2__ext510__slm_byte_read_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6275, 32, NULL,mtlgt2__ext510__slm_byte_read_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext511_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext511";
   query->symbol_name = "Ext511";
   query->guid = "2cbd327c-40e2-452b-a9fc-c7787869a352";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x10080180 },
         { .reg = 0x00009888, .val = 0x12080105 },
         { .reg = 0x00009888, .val = 0x14080083 },
         { .reg = 0x00009888, .val = 0x16080001 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x0008FFF0 },
         { .reg = 0x00009888, .val = 0x02080003 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x02020003 },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x0A080146 },
         { .reg = 0x00009888, .val = 0x0C0800C4 },
         { .reg = 0x00009888, .val = 0x0E080042 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAA0 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145550 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155550 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165550 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAA0 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFC },
         { .reg = 0x00009888, .val = 0x000EFFFC },
         { .reg = 0x00009888, .val = 0x000DAAA0 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAA0 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAA0 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext511__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext511__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext511__avg_gpu_core_frequency__max,mtlgt2__ext511__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6276, 24, NULL,mtlgt2__ext511__slm_byte_read_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6277, 32, NULL,mtlgt2__ext511__slm_byte_read_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext516_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext516";
   query->symbol_name = "Ext516";
   query->guid = "3a9dba68-9402-48b0-a8ec-28e4e4a534de";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18080004 },
         { .reg = 0x00009888, .val = 0x1C081000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x08080187 },
         { .reg = 0x00009888, .val = 0x0A080105 },
         { .reg = 0x00009888, .val = 0x0C080083 },
         { .reg = 0x00009888, .val = 0x0E080001 },
         { .reg = 0x00009888, .val = 0x1008038F },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext516__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext516__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext516__avg_gpu_core_frequency__max,mtlgt2__ext516__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6278, 24, NULL,mtlgt2__ext516__load_store_cache_byte_read_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6279, 32, NULL,mtlgt2__ext516__load_store_cache_byte_read_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext517_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext517";
   query->symbol_name = "Ext517";
   query->guid = "ea503506-9afa-42dc-b85b-1237dce6e8af";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18080005 },
         { .reg = 0x00009888, .val = 0x1C081400 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x08080187 },
         { .reg = 0x00009888, .val = 0x0A080105 },
         { .reg = 0x00009888, .val = 0x0C080083 },
         { .reg = 0x00009888, .val = 0x0E080001 },
         { .reg = 0x00009888, .val = 0x1008038F },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext517__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext517__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext517__avg_gpu_core_frequency__max,mtlgt2__ext517__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6280, 24, NULL,mtlgt2__ext517__load_store_cache_byte_write_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6281, 32, NULL,mtlgt2__ext517__load_store_cache_byte_write_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext518_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext518";
   query->symbol_name = "Ext518";
   query->guid = "5056524c-12e3-4ba6-8788-eb934f284753";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18080004 },
         { .reg = 0x00009888, .val = 0x1C081000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x08080187 },
         { .reg = 0x00009888, .val = 0x0A080105 },
         { .reg = 0x00009888, .val = 0x0C080083 },
         { .reg = 0x00009888, .val = 0x0E080001 },
         { .reg = 0x00009888, .val = 0x1008038F },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext518__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext518__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext518__avg_gpu_core_frequency__max,mtlgt2__ext518__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6282, 24, NULL,mtlgt2__ext518__load_store_cache_byte_read_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6283, 32, NULL,mtlgt2__ext518__load_store_cache_byte_read_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext519_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext519";
   query->symbol_name = "Ext519";
   query->guid = "13f8665d-c5aa-47b4-ae3e-af80dd134e1b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18080005 },
         { .reg = 0x00009888, .val = 0x1C081400 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x08080187 },
         { .reg = 0x00009888, .val = 0x0A080105 },
         { .reg = 0x00009888, .val = 0x0C080083 },
         { .reg = 0x00009888, .val = 0x0E080001 },
         { .reg = 0x00009888, .val = 0x1008038F },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext519__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext519__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext519__avg_gpu_core_frequency__max,mtlgt2__ext519__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6284, 24, NULL,mtlgt2__ext519__load_store_cache_byte_write_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6285, 32, NULL,mtlgt2__ext519__load_store_cache_byte_write_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext520_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext520";
   query->symbol_name = "Ext520";
   query->guid = "4d5b4699-5a6a-4a85-81e1-3ad75d735476";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18080004 },
         { .reg = 0x00009888, .val = 0x1C081000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x08080187 },
         { .reg = 0x00009888, .val = 0x0A080105 },
         { .reg = 0x00009888, .val = 0x0C080083 },
         { .reg = 0x00009888, .val = 0x0E080001 },
         { .reg = 0x00009888, .val = 0x1008038F },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext520__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext520__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext520__avg_gpu_core_frequency__max,mtlgt2__ext520__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6286, 24, NULL,mtlgt2__ext520__load_store_cache_byte_read_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6287, 32, NULL,mtlgt2__ext520__load_store_cache_byte_read_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext521_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext521";
   query->symbol_name = "Ext521";
   query->guid = "f9cc9e2c-c517-49a1-b27c-f81b08b411fc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18080005 },
         { .reg = 0x00009888, .val = 0x1C081400 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x08080187 },
         { .reg = 0x00009888, .val = 0x0A080105 },
         { .reg = 0x00009888, .val = 0x0C080083 },
         { .reg = 0x00009888, .val = 0x0E080001 },
         { .reg = 0x00009888, .val = 0x1008038F },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext521__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext521__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext521__avg_gpu_core_frequency__max,mtlgt2__ext521__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6288, 24, NULL,mtlgt2__ext521__load_store_cache_byte_write_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6289, 32, NULL,mtlgt2__ext521__load_store_cache_byte_write_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext522_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext522";
   query->symbol_name = "Ext522";
   query->guid = "f5fe71de-58e0-4fba-a75a-111906d8fb5b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18080004 },
         { .reg = 0x00009888, .val = 0x1C081000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x08080187 },
         { .reg = 0x00009888, .val = 0x0A080105 },
         { .reg = 0x00009888, .val = 0x0C080083 },
         { .reg = 0x00009888, .val = 0x0E080001 },
         { .reg = 0x00009888, .val = 0x1008038F },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext522__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext522__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext522__avg_gpu_core_frequency__max,mtlgt2__ext522__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6290, 24, NULL,mtlgt2__ext522__load_store_cache_byte_read_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6291, 32, NULL,mtlgt2__ext522__load_store_cache_byte_read_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext523_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext523";
   query->symbol_name = "Ext523";
   query->guid = "46d82207-1235-45ea-a0e6-f71fa55a3380";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18080005 },
         { .reg = 0x00009888, .val = 0x1C081400 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x08080187 },
         { .reg = 0x00009888, .val = 0x0A080105 },
         { .reg = 0x00009888, .val = 0x0C080083 },
         { .reg = 0x00009888, .val = 0x0E080001 },
         { .reg = 0x00009888, .val = 0x1008038F },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0008FFFF },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAAA },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145555 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155555 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165555 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAAA },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFF },
         { .reg = 0x00009888, .val = 0x000EFFFF },
         { .reg = 0x00009888, .val = 0x000DAAAA },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAAA },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext523__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext523__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext523__avg_gpu_core_frequency__max,mtlgt2__ext523__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6292, 24, NULL,mtlgt2__ext523__load_store_cache_byte_write_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6293, 32, NULL,mtlgt2__ext523__load_store_cache_byte_write_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext540_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext540";
   query->symbol_name = "Ext540";
   query->guid = "0ea54a28-5052-4c2a-a18a-8cc17383a072";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18080014 },
         { .reg = 0x00009888, .val = 0x1C085000 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x0A080146 },
         { .reg = 0x00009888, .val = 0x0C0800C4 },
         { .reg = 0x00009888, .val = 0x0E080042 },
         { .reg = 0x00009888, .val = 0x10080380 },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFF0 },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext540__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext540__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext540__avg_gpu_core_frequency__max,mtlgt2__ext540__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6294, 24, NULL,mtlgt2__ext540__slm_byte_write_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6295, 32, NULL,mtlgt2__ext540__slm_byte_write_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext541_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext541";
   query->symbol_name = "Ext541";
   query->guid = "9cd9ba1c-3c59-483d-9ce3-136c8898f09d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x18080014 },
         { .reg = 0x00009888, .val = 0x1C085000 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x0A080146 },
         { .reg = 0x00009888, .val = 0x0C0800C4 },
         { .reg = 0x00009888, .val = 0x0E080042 },
         { .reg = 0x00009888, .val = 0x10080380 },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0008FFF0 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0001FFF0 },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext541__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext541__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext541__avg_gpu_core_frequency__max,mtlgt2__ext541__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6296, 24, NULL,mtlgt2__ext541__slm_byte_write_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6297, 32, NULL,mtlgt2__ext541__slm_byte_write_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext542_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext542";
   query->symbol_name = "Ext542";
   query->guid = "ab29d0d9-3388-4316-af23-932aeef1ed23";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x18080014 },
         { .reg = 0x00009888, .val = 0x1C085000 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x0A080146 },
         { .reg = 0x00009888, .val = 0x0C0800C4 },
         { .reg = 0x00009888, .val = 0x0E080042 },
         { .reg = 0x00009888, .val = 0x10080380 },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAA0 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145550 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155550 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165550 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAA0 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFC },
         { .reg = 0x00009888, .val = 0x000EFFFC },
         { .reg = 0x00009888, .val = 0x000DAAA0 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAA0 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAA0 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext542__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext542__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext542__avg_gpu_core_frequency__max,mtlgt2__ext542__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6298, 24, NULL,mtlgt2__ext542__slm_byte_write_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6299, 32, NULL,mtlgt2__ext542__slm_byte_write_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext543_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext543";
   query->symbol_name = "Ext543";
   query->guid = "16bf4ba3-2204-4d52-8f5e-d49ef8f571bb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x18080014 },
         { .reg = 0x00009888, .val = 0x1C085000 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x0A080146 },
         { .reg = 0x00009888, .val = 0x0C0800C4 },
         { .reg = 0x00009888, .val = 0x0E080042 },
         { .reg = 0x00009888, .val = 0x10080380 },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x08080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x0008FFF0 },
         { .reg = 0x00009888, .val = 0x0208FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0013AAA0 },
         { .reg = 0x00009888, .val = 0x0213AAAA },
         { .reg = 0x00009888, .val = 0x00145550 },
         { .reg = 0x00009888, .val = 0x02145555 },
         { .reg = 0x00009888, .val = 0x00155550 },
         { .reg = 0x00009888, .val = 0x02155555 },
         { .reg = 0x00009888, .val = 0x00165550 },
         { .reg = 0x00009888, .val = 0x02165555 },
         { .reg = 0x00009888, .val = 0x0017AAA0 },
         { .reg = 0x00009888, .val = 0x0217AAAA },
         { .reg = 0x00009888, .val = 0x000CFFFC },
         { .reg = 0x00009888, .val = 0x000EFFFC },
         { .reg = 0x00009888, .val = 0x000DAAA0 },
         { .reg = 0x00009888, .val = 0x020DAAAA },
         { .reg = 0x00009888, .val = 0x0006AAA0 },
         { .reg = 0x00009888, .val = 0x0206AAAA },
         { .reg = 0x00009888, .val = 0x0001AAA0 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x62010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext543__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext543__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext543__avg_gpu_core_frequency__max,mtlgt2__ext543__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6300, 24, NULL,mtlgt2__ext543__slm_byte_write_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6301, 32, NULL,mtlgt2__ext543__slm_byte_write_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext604_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext604";
   query->symbol_name = "Ext604";
   query->guid = "66331aff-0aaf-41e7-ad18-fa61060d3af6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x02023030 },
         { .reg = 0x00009888, .val = 0x0204D0D0 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x120708C0 },
         { .reg = 0x00009888, .val = 0x16070880 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x02083030 },
         { .reg = 0x00009884, .val = 0x00000009 },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x02043030 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x12070023 },
         { .reg = 0x00009888, .val = 0x16070022 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x0000000A },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x02020303 },
         { .reg = 0x00009888, .val = 0x02040D0D },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x100708C0 },
         { .reg = 0x00009888, .val = 0x14070880 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009888, .val = 0x02080303 },
         { .reg = 0x00009884, .val = 0x0000000B },
         { .reg = 0x00009888, .val = 0x2A070000 },
         { .reg = 0x00009888, .val = 0x02040303 },
         { .reg = 0x00009888, .val = 0x06070006 },
         { .reg = 0x00009888, .val = 0x10070023 },
         { .reg = 0x00009888, .val = 0x14070022 },
         { .reg = 0x00009888, .val = 0x08070000 },
         { .reg = 0x00009888, .val = 0x02070000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x02130A0A },
         { .reg = 0x00009888, .val = 0x02140505 },
         { .reg = 0x00009888, .val = 0x02150505 },
         { .reg = 0x00009888, .val = 0x02160505 },
         { .reg = 0x00009888, .val = 0x02170A0A },
         { .reg = 0x00009888, .val = 0x000C3300 },
         { .reg = 0x00009888, .val = 0x000E3300 },
         { .reg = 0x00009888, .val = 0x020D0A0A },
         { .reg = 0x00009888, .val = 0x02060A0A },
         { .reg = 0x00009888, .val = 0x0201FAFA },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x62010030 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010229 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54011203 },
         { .reg = 0x00009888, .val = 0x56010011 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x74010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext604__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext604__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext604__avg_gpu_core_frequency__max,mtlgt2__ext604__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6302, 24, percentage_max_float,mtlgt2__ext604__threadgroup_dispatch_queue0_active_cycles_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6303, 28, percentage_max_float,mtlgt2__ext604__threadgroup_dispatch_queue0_active_cycles_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6304, 32, percentage_max_float,mtlgt2__ext604__threadgroup_dispatch_queue0_active_cycles_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6305, 36, percentage_max_float,mtlgt2__ext604__threadgroup_dispatch_queue0_active_cycles_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6306, 40, percentage_max_float,mtlgt2__ext604__threadgroup_dispatch_queue1_active_cycles_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6307, 44, percentage_max_float,mtlgt2__ext604__threadgroup_dispatch_queue1_active_cycles_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6308, 48, percentage_max_float,mtlgt2__ext604__threadgroup_dispatch_queue1_active_cycles_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6309, 52, percentage_max_float,mtlgt2__ext604__threadgroup_dispatch_queue1_active_cycles_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1000_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1000";
   query->symbol_name = "Ext1000";
   query->guid = "2d24479d-6766-4632-8d2b-f440c9bf53c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00002009 },
         { .reg = 0x0000E758, .val = 0x01008001 },
         { .reg = 0x0000E45C, .val = 0x0000300A },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1000__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1000__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1000__avg_gpu_core_frequency__max,mtlgt2__ext1000__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6310, 24, percentage_max_float,mtlgt2__ext1000__xve_active__read);

      intel_perf_query_add_counter_float(query, 6311, 28, percentage_max_float,mtlgt2__ext1000__xve_stall__read);

      intel_perf_query_add_counter_float(query, 6312, 32, percentage_max_float,mtlgt2__ext1000__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 6313, 40, mtlgt2__ext1000__xve_inst_executed_alu0_all__max,mtlgt2__ext1000__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 6314, 48, mtlgt2__ext1000__xve_inst_executed_alu1_all__max,mtlgt2__ext1000__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 6315, 56, mtlgt2__ext1000__xve_inst_executed_xmx_all__max,mtlgt2__ext1000__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 6316, 64, mtlgt2__ext1000__xve_inst_executed_send_all__max,mtlgt2__ext1000__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 6317, 72, mtlgt2__ext1000__xve_inst_executed_control_all__max,mtlgt2__ext1000__xve_inst_executed_control_all__read);

      intel_perf_query_add_counter_float(query, 6318, 80, percentage_max_float,mtlgt2__ext1000__xve_pipe_alu0_and_alu1_active__read);

      intel_perf_query_add_counter_float(query, 6319, 84, percentage_max_float,mtlgt2__ext1000__xve_pipe_alu0_and_xmx_active__read);

      intel_perf_query_add_counter_float(query, 6320, 88, percentage_max_float,mtlgt2__ext1000__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6321, 92, percentage_max_float,mtlgt2__ext1000__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6322, 96, percentage_max_float,mtlgt2__ext1000__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6323, 100, percentage_max_float,mtlgt2__ext1000__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6324, 104, percentage_max_float,mtlgt2__ext1000__xve_inst_executed_control_all_utilization__read);

      intel_perf_query_add_counter_uint64(query, 6325, 112, mtlgt2__ext1000__xve_active_cycles__max,mtlgt2__ext1000__xve_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6326, 120, mtlgt2__ext1000__xve_stall_cycles__max,mtlgt2__ext1000__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6327, 128, mtlgt2__ext1000__xve_threads_occupancy_cycles_all__max,mtlgt2__ext1000__xve_threads_occupancy_cycles_all__read);

      intel_perf_query_add_counter_uint64(query, 6328, 136, mtlgt2__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max,mtlgt2__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6329, 144, mtlgt2__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max,mtlgt2__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1001_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Ext1001";
   query->symbol_name = "Ext1001";
   query->guid = "15aa1ce0-6750-4566-8b2b-6d71a6ac4039";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00020010 },
         { .reg = 0x0000E558, .val = 0x00050030 },
         { .reg = 0x0000E658, .val = 0x00090060 },
         { .reg = 0x0000E758, .val = 0x00031011 },
         { .reg = 0x0000E45C, .val = 0x00051021 },
         { .reg = 0x0000E55C, .val = 0x00091061 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1001__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1001__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1001__avg_gpu_core_frequency__max,mtlgt2__ext1001__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6330, 24, mtlgt2__ext1001__xve_inst_executed_alu0_vs__max,mtlgt2__ext1001__xve_inst_executed_alu0_vs__read);

      intel_perf_query_add_counter_uint64(query, 6331, 32, mtlgt2__ext1001__xve_inst_executed_alu0_hs__max,mtlgt2__ext1001__xve_inst_executed_alu0_hs__read);

      intel_perf_query_add_counter_uint64(query, 6332, 40, mtlgt2__ext1001__xve_inst_executed_alu0_ds__max,mtlgt2__ext1001__xve_inst_executed_alu0_ds__read);

      intel_perf_query_add_counter_uint64(query, 6333, 48, mtlgt2__ext1001__xve_inst_executed_alu0_ps__max,mtlgt2__ext1001__xve_inst_executed_alu0_ps__read);

      intel_perf_query_add_counter_uint64(query, 6334, 56, mtlgt2__ext1001__xve_inst_executed_alu0_cs__max,mtlgt2__ext1001__xve_inst_executed_alu0_cs__read);

      intel_perf_query_add_counter_uint64(query, 6335, 64, mtlgt2__ext1001__xve_inst_executed_alu0_async_cs__max,mtlgt2__ext1001__xve_inst_executed_alu0_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 6336, 72, mtlgt2__ext1001__xve_inst_executed_alu1_vs__max,mtlgt2__ext1001__xve_inst_executed_alu1_vs__read);

      intel_perf_query_add_counter_uint64(query, 6337, 80, mtlgt2__ext1001__xve_inst_executed_alu1_hs__max,mtlgt2__ext1001__xve_inst_executed_alu1_hs__read);

      intel_perf_query_add_counter_uint64(query, 6338, 88, mtlgt2__ext1001__xve_inst_executed_alu1_ds__max,mtlgt2__ext1001__xve_inst_executed_alu1_ds__read);

      intel_perf_query_add_counter_uint64(query, 6339, 96, mtlgt2__ext1001__xve_inst_executed_alu1_ps__max,mtlgt2__ext1001__xve_inst_executed_alu1_ps__read);

      intel_perf_query_add_counter_uint64(query, 6340, 104, mtlgt2__ext1001__xve_inst_executed_alu1_cs__max,mtlgt2__ext1001__xve_inst_executed_alu1_cs__read);

      intel_perf_query_add_counter_uint64(query, 6341, 112, mtlgt2__ext1001__xve_inst_executed_alu1_async_cs__max,mtlgt2__ext1001__xve_inst_executed_alu1_async_cs__read);

      intel_perf_query_add_counter_float(query, 6342, 120, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu0_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 6343, 124, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu0_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 6344, 128, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu0_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 6345, 132, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu0_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 6346, 136, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu0_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6347, 140, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu0_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6348, 144, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu1_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 6349, 148, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu1_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 6350, 152, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu1_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 6351, 156, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu1_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 6352, 160, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu1_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6353, 164, percentage_max_float,mtlgt2__ext1001__xve_inst_executed_alu1_async_cs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1002_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "Ext1002";
   query->symbol_name = "Ext1002";
   query->guid = "23131267-15c5-47bc-bcb3-4c05fc452e0e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x000C10C0 },
         { .reg = 0x0000E558, .val = 0x000D00C2 },
         { .reg = 0x0000E658, .val = 0x000D20D1 },
         { .reg = 0x0000E758, .val = 0x000E10E0 },
         { .reg = 0x0000E45C, .val = 0x000000E2 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1002__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1002__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1002__avg_gpu_core_frequency__max,mtlgt2__ext1002__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6354, 24, percentage_max_float,mtlgt2__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 6355, 28, percentage_max_float,mtlgt2__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 6356, 32, percentage_max_float,mtlgt2__ext1002__xve_inst_executed_send_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 6357, 36, percentage_max_float,mtlgt2__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 6358, 40, percentage_max_float,mtlgt2__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 6359, 44, percentage_max_float,mtlgt2__ext1002__xve_inst_executed_send_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 6360, 48, percentage_max_float,mtlgt2__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6361, 52, percentage_max_float,mtlgt2__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6362, 56, percentage_max_float,mtlgt2__ext1002__xve_inst_executed_send_rt_ms_utilization__read);

      intel_perf_query_add_counter_uint64(query, 6363, 64, mtlgt2__ext1002__xve_inst_executed_alu0_rt_ahs__max,mtlgt2__ext1002__xve_inst_executed_alu0_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 6364, 72, mtlgt2__ext1002__xve_inst_executed_alu1_rt_ahs__max,mtlgt2__ext1002__xve_inst_executed_alu1_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 6365, 80, mtlgt2__ext1002__xve_inst_executed_send_rt_ahs__max,mtlgt2__ext1002__xve_inst_executed_send_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 6366, 88, mtlgt2__ext1002__xve_inst_executed_alu0_rt_chs__max,mtlgt2__ext1002__xve_inst_executed_alu0_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 6367, 96, mtlgt2__ext1002__xve_inst_executed_alu1_rt_chs__max,mtlgt2__ext1002__xve_inst_executed_alu1_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 6368, 104, mtlgt2__ext1002__xve_inst_executed_send_rt_chs__max,mtlgt2__ext1002__xve_inst_executed_send_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 6369, 112, mtlgt2__ext1002__xve_inst_executed_alu0_rt_ms__max,mtlgt2__ext1002__xve_inst_executed_alu0_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 6370, 120, mtlgt2__ext1002__xve_inst_executed_alu1_rt_ms__max,mtlgt2__ext1002__xve_inst_executed_alu1_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 6371, 128, mtlgt2__ext1002__xve_inst_executed_send_rt_ms__max,mtlgt2__ext1002__xve_inst_executed_send_rt_ms__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1003_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1003";
   query->symbol_name = "Ext1003";
   query->guid = "605d1ee1-c160-46ee-9e31-6daf3885401c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00054014 },
         { .reg = 0x0000E558, .val = 0x00034024 },
         { .reg = 0x0000E658, .val = 0x00094064 },
         { .reg = 0x0000E758, .val = 0x000B40A4 },
         { .reg = 0x0000E45C, .val = 0x00000004 },
         { .reg = 0x0000E55C, .val = 0x000C4000 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1003__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1003__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1003__avg_gpu_core_frequency__max,mtlgt2__ext1003__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6310, 24, percentage_max_float,mtlgt2__ext1003__xve_active__read);

      intel_perf_query_add_counter_float(query, 6372, 28, percentage_max_float,mtlgt2__ext1003__xve_active_ds__read);

      intel_perf_query_add_counter_float(query, 6373, 32, percentage_max_float,mtlgt2__ext1003__xve_active_hs__read);

      intel_perf_query_add_counter_float(query, 6374, 36, percentage_max_float,mtlgt2__ext1003__xve_active_ps__read);

      intel_perf_query_add_counter_float(query, 6375, 40, percentage_max_float,mtlgt2__ext1003__xve_active_vs__read);

      intel_perf_query_add_counter_float(query, 6376, 44, percentage_max_float,mtlgt2__ext1003__xve_active_async_cs__read);

      intel_perf_query_add_counter_float(query, 6377, 48, percentage_max_float,mtlgt2__ext1003__xve_active_cs__read);

      intel_perf_query_add_counter_float(query, 6378, 52, percentage_max_float,mtlgt2__ext1003__xve_active_ms__read);

      intel_perf_query_add_counter_float(query, 6379, 56, percentage_max_float,mtlgt2__ext1003__xve_active_ts__read);

      intel_perf_query_add_counter_float(query, 6380, 60, percentage_max_float,mtlgt2__ext1003__xve_active_rt__read);

      intel_perf_query_add_counter_uint64(query, 6325, 64, mtlgt2__ext1003__xve_active_cycles__max,mtlgt2__ext1003__xve_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6381, 72, mtlgt2__ext1003__xve_active_cycles_async_cs__max,mtlgt2__ext1003__xve_active_cycles_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 6382, 80, mtlgt2__ext1003__xve_active_cycles_cs__max,mtlgt2__ext1003__xve_active_cycles_cs__read);

      intel_perf_query_add_counter_uint64(query, 6383, 88, percentage_max_uint64,mtlgt2__ext1003__xve_active_cycles_hs__read);

      intel_perf_query_add_counter_uint64(query, 6384, 96, mtlgt2__ext1003__xve_active_cycles_ps__max,mtlgt2__ext1003__xve_active_cycles_ps__read);

      intel_perf_query_add_counter_uint64(query, 6385, 104, mtlgt2__ext1003__xve_active_cycles_vs__max,mtlgt2__ext1003__xve_active_cycles_vs__read);

      intel_perf_query_add_counter_uint64(query, 6386, 112, mtlgt2__ext1003__xve_active_cycles_ds__max,mtlgt2__ext1003__xve_active_cycles_ds__read);

      intel_perf_query_add_counter_uint64(query, 6387, 120, mtlgt2__ext1003__xve_active_cycles_ms__max,mtlgt2__ext1003__xve_active_cycles_ms__read);

      intel_perf_query_add_counter_uint64(query, 6388, 128, mtlgt2__ext1003__xve_active_cycles_ts__max,mtlgt2__ext1003__xve_active_cycles_ts__read);

      intel_perf_query_add_counter_uint64(query, 6389, 136, mtlgt2__ext1003__xve_active_cycles_rt__max,mtlgt2__ext1003__xve_active_cycles_rt__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1004_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1004";
   query->symbol_name = "Ext1004";
   query->guid = "40f4dcae-3ed1-4f3e-bddf-dbb87bc4279b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00015005 },
         { .reg = 0x0000E558, .val = 0x000550A5 },
         { .reg = 0x0000E658, .val = 0x000250B5 },
         { .reg = 0x0000E758, .val = 0x00065035 },
         { .reg = 0x0000E45C, .val = 0x00000095 },
         { .reg = 0x0000E55C, .val = 0x000C5000 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1004__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1004__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1004__avg_gpu_core_frequency__max,mtlgt2__ext1004__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6311, 24, percentage_max_float,mtlgt2__ext1004__xve_stall__read);

      intel_perf_query_add_counter_float(query, 6390, 28, percentage_max_float,mtlgt2__ext1004__xve_stall_async_cs__read);

      intel_perf_query_add_counter_float(query, 6391, 32, percentage_max_float,mtlgt2__ext1004__xve_stall_cs__read);

      intel_perf_query_add_counter_float(query, 6392, 36, percentage_max_float,mtlgt2__ext1004__xve_stall_ds__read);

      intel_perf_query_add_counter_float(query, 6393, 40, percentage_max_float,mtlgt2__ext1004__xve_stall_hs__read);

      intel_perf_query_add_counter_float(query, 6394, 44, percentage_max_float,mtlgt2__ext1004__xve_stall_ms__read);

      intel_perf_query_add_counter_float(query, 6395, 48, percentage_max_float,mtlgt2__ext1004__xve_stall_ps__read);

      intel_perf_query_add_counter_float(query, 6396, 52, percentage_max_float,mtlgt2__ext1004__xve_stall_ts__read);

      intel_perf_query_add_counter_float(query, 6397, 56, percentage_max_float,mtlgt2__ext1004__xve_stall_vs__read);

      intel_perf_query_add_counter_float(query, 6398, 60, percentage_max_float,mtlgt2__ext1004__xve_stall_rt__read);

      intel_perf_query_add_counter_uint64(query, 6326, 64, mtlgt2__ext1004__xve_stall_cycles__max,mtlgt2__ext1004__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6399, 72, mtlgt2__ext1004__xve_stall_cycles_async_cs__max,mtlgt2__ext1004__xve_stall_cycles_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 6400, 80, mtlgt2__ext1004__xve_stall_cycles_cs__max,mtlgt2__ext1004__xve_stall_cycles_cs__read);

      intel_perf_query_add_counter_uint64(query, 6401, 88, mtlgt2__ext1004__xve_stall_cycles_ds__max,mtlgt2__ext1004__xve_stall_cycles_ds__read);

      intel_perf_query_add_counter_uint64(query, 6402, 96, mtlgt2__ext1004__xve_stall_cycles_hs__max,mtlgt2__ext1004__xve_stall_cycles_hs__read);

      intel_perf_query_add_counter_uint64(query, 6403, 104, mtlgt2__ext1004__xve_stall_cycles_ms__max,mtlgt2__ext1004__xve_stall_cycles_ms__read);

      intel_perf_query_add_counter_uint64(query, 6404, 112, mtlgt2__ext1004__xve_stall_cycles_ps__max,mtlgt2__ext1004__xve_stall_cycles_ps__read);

      intel_perf_query_add_counter_uint64(query, 6405, 120, mtlgt2__ext1004__xve_stall_cycles_ts__max,mtlgt2__ext1004__xve_stall_cycles_ts__read);

      intel_perf_query_add_counter_uint64(query, 6406, 128, mtlgt2__ext1004__xve_stall_cycles_vs__max,mtlgt2__ext1004__xve_stall_cycles_vs__read);

      intel_perf_query_add_counter_uint64(query, 6407, 136, mtlgt2__ext1004__xve_stall_cycles_rt__max,mtlgt2__ext1004__xve_stall_cycles_rt__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1005_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Ext1005";
   query->symbol_name = "Ext1005";
   query->guid = "099da490-3594-4baa-98af-cea30d4d6c15";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x0000700B },
         { .reg = 0x0000E558, .val = 0x02000006 },
         { .reg = 0x0000E658, .val = 0x0000C00D },
         { .reg = 0x0000E758, .val = 0x0200200F },
         { .reg = 0x0000E45C, .val = 0x0000000E },
         { .reg = 0x0000E55C, .val = 0x00009001 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1005__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1005__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1005__avg_gpu_core_frequency__max,mtlgt2__ext1005__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6313, 24, mtlgt2__ext1005__xve_inst_executed_alu0_all__max,mtlgt2__ext1005__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 6408, 32, mtlgt2__ext1005__xve_inst_executed_fp16__max,mtlgt2__ext1005__xve_inst_executed_fp16__read);

      intel_perf_query_add_counter_uint64(query, 6409, 40, mtlgt2__ext1005__xve_inst_executed_fp32__max,mtlgt2__ext1005__xve_inst_executed_fp32__read);

      intel_perf_query_add_counter_uint64(query, 6410, 48, mtlgt2__ext1005__xve_inst_executed_fp64__max,mtlgt2__ext1005__xve_inst_executed_fp64__read);

      intel_perf_query_add_counter_uint64(query, 6314, 56, mtlgt2__ext1005__xve_inst_executed_alu1_all__max,mtlgt2__ext1005__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 6411, 64, mtlgt2__ext1005__xve_inst_executed_int16__max,mtlgt2__ext1005__xve_inst_executed_int16__read);

      intel_perf_query_add_counter_uint64(query, 6412, 72, mtlgt2__ext1005__xve_inst_executed_int32__max,mtlgt2__ext1005__xve_inst_executed_int32__read);

      intel_perf_query_add_counter_uint64(query, 6413, 80, mtlgt2__ext1005__xve_inst_executed_math__max,mtlgt2__ext1005__xve_inst_executed_math__read);

      intel_perf_query_add_counter_uint64(query, 6315, 88, mtlgt2__ext1005__xve_inst_executed_xmx_all__max,mtlgt2__ext1005__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 6414, 96, mtlgt2__ext1005__xve_inst_executed_xmx_bf16__max,mtlgt2__ext1005__xve_inst_executed_xmx_bf16__read);

      intel_perf_query_add_counter_uint64(query, 6415, 104, mtlgt2__ext1005__xve_inst_executed_xmx_fp16__max,mtlgt2__ext1005__xve_inst_executed_xmx_fp16__read);

      intel_perf_query_add_counter_uint64(query, 6416, 112, mtlgt2__ext1005__xve_inst_executed_xmx_int8__max,mtlgt2__ext1005__xve_inst_executed_xmx_int8__read);

      intel_perf_query_add_counter_float(query, 6320, 120, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6417, 124, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 6418, 128, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_fp32_utilization__read);

      intel_perf_query_add_counter_float(query, 6419, 132, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_fp64_utilization__read);

      intel_perf_query_add_counter_float(query, 6321, 136, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6420, 140, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_int16_utilization__read);

      intel_perf_query_add_counter_float(query, 6421, 144, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_int32_utilization__read);

      intel_perf_query_add_counter_float(query, 6422, 148, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_math_utilization__read);

      intel_perf_query_add_counter_float(query, 6322, 152, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6423, 156, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_xmx_bf16_utilization__read);

      intel_perf_query_add_counter_float(query, 6424, 160, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_xmx_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 6425, 164, percentage_max_float,mtlgt2__ext1005__xve_inst_executed_xmx_int8_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1006_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1006";
   query->symbol_name = "Ext1006";
   query->guid = "ab298da4-5917-4592-bbe0-1c21dedf000b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x000A2012 },
         { .reg = 0x0000E558, .val = 0x000B2052 },
         { .reg = 0x0000E658, .val = 0x00042022 },
         { .reg = 0x0000E758, .val = 0x00062032 },
         { .reg = 0x0000E45C, .val = 0x00002092 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1006__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1006__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1006__avg_gpu_core_frequency__max,mtlgt2__ext1006__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6316, 24, mtlgt2__ext1006__xve_inst_executed_send_all__max,mtlgt2__ext1006__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 6426, 32, mtlgt2__ext1006__xve_inst_executed_send_async_cs__max,mtlgt2__ext1006__xve_inst_executed_send_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 6427, 40, mtlgt2__ext1006__xve_inst_executed_send_cs__max,mtlgt2__ext1006__xve_inst_executed_send_cs__read);

      intel_perf_query_add_counter_uint64(query, 6428, 48, mtlgt2__ext1006__xve_inst_executed_send_ds__max,mtlgt2__ext1006__xve_inst_executed_send_ds__read);

      intel_perf_query_add_counter_uint64(query, 6429, 56, mtlgt2__ext1006__xve_inst_executed_send_gs__max,mtlgt2__ext1006__xve_inst_executed_send_gs__read);

      intel_perf_query_add_counter_uint64(query, 6430, 64, mtlgt2__ext1006__xve_inst_executed_send_hs__max,mtlgt2__ext1006__xve_inst_executed_send_hs__read);

      intel_perf_query_add_counter_uint64(query, 6431, 72, mtlgt2__ext1006__xve_inst_executed_send_ms__max,mtlgt2__ext1006__xve_inst_executed_send_ms__read);

      intel_perf_query_add_counter_uint64(query, 6432, 80, mtlgt2__ext1006__xve_inst_executed_send_ps__max,mtlgt2__ext1006__xve_inst_executed_send_ps__read);

      intel_perf_query_add_counter_uint64(query, 6433, 88, mtlgt2__ext1006__xve_inst_executed_send_ts__max,mtlgt2__ext1006__xve_inst_executed_send_ts__read);

      intel_perf_query_add_counter_uint64(query, 6434, 96, mtlgt2__ext1006__xve_inst_executed_send_vs__max,mtlgt2__ext1006__xve_inst_executed_send_vs__read);

      intel_perf_query_add_counter_float(query, 6323, 104, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6435, 108, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6436, 112, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6437, 116, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 6438, 120, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 6439, 124, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 6440, 128, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6441, 132, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 6442, 136, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 6443, 140, percentage_max_float,mtlgt2__ext1006__xve_inst_executed_send_vs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1007_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext1007";
   query->symbol_name = "Ext1007";
   query->guid = "1b429688-49f8-48f2-8a06-18ba5c6a2b52";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00045044 },
         { .reg = 0x0000E558, .val = 0x00040041 },
         { .reg = 0x0000E658, .val = 0x000B10A1 },
         { .reg = 0x0000E758, .val = 0x000B00A0 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1007__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1007__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1007__avg_gpu_core_frequency__max,mtlgt2__ext1007__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6444, 24, percentage_max_float,mtlgt2__ext1007__xve_active_gs__read);

      intel_perf_query_add_counter_float(query, 6445, 28, percentage_max_float,mtlgt2__ext1007__xve_stall_gs__read);

      intel_perf_query_add_counter_uint64(query, 6446, 32, mtlgt2__ext1007__xve_inst_executed_alu0_gs__max,mtlgt2__ext1007__xve_inst_executed_alu0_gs__read);

      intel_perf_query_add_counter_uint64(query, 6447, 40, mtlgt2__ext1007__xve_inst_executed_alu1_gs__max,mtlgt2__ext1007__xve_inst_executed_alu1_gs__read);

      intel_perf_query_add_counter_uint64(query, 6448, 48, mtlgt2__ext1007__xve_active_cycles_gs__max,mtlgt2__ext1007__xve_active_cycles_gs__read);

      intel_perf_query_add_counter_uint64(query, 6449, 56, mtlgt2__ext1007__xve_stall_cycles_gs__max,mtlgt2__ext1007__xve_stall_cycles_gs__read);

      intel_perf_query_add_counter_uint64(query, 6450, 64, mtlgt2__ext1007__xve_inst_executed_alu0_ms__max,mtlgt2__ext1007__xve_inst_executed_alu0_ms__read);

      intel_perf_query_add_counter_uint64(query, 6451, 72, mtlgt2__ext1007__xve_inst_executed_alu0_ts__max,mtlgt2__ext1007__xve_inst_executed_alu0_ts__read);

      intel_perf_query_add_counter_uint64(query, 6452, 80, mtlgt2__ext1007__xve_inst_executed_alu1_ms__max,mtlgt2__ext1007__xve_inst_executed_alu1_ms__read);

      intel_perf_query_add_counter_uint64(query, 6453, 88, mtlgt2__ext1007__xve_inst_executed_alu1_ts__max,mtlgt2__ext1007__xve_inst_executed_alu1_ts__read);

      intel_perf_query_add_counter_float(query, 6454, 96, percentage_max_float,mtlgt2__ext1007__xve_inst_executed_alu0_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 6455, 100, percentage_max_float,mtlgt2__ext1007__xve_inst_executed_alu1_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 6456, 104, percentage_max_float,mtlgt2__ext1007__xve_inst_executed_alu0_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6457, 108, percentage_max_float,mtlgt2__ext1007__xve_inst_executed_alu0_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 6458, 112, percentage_max_float,mtlgt2__ext1007__xve_inst_executed_alu1_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6459, 116, percentage_max_float,mtlgt2__ext1007__xve_inst_executed_alu1_ts_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt2_register_ext1010_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext1010";
   query->symbol_name = "Ext1010";
   query->guid = "a4717f34-1c8b-40d8-a022-abbcf03cc6e5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt2__ext1010__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt2__ext1010__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt2__ext1010__avg_gpu_core_frequency__max,mtlgt2__ext1010__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6460, 24, NULL,mtlgt2__ext1010__sampler_2_x2_read__read);

      intel_perf_query_add_counter_uint64(query, 6461, 32, NULL,mtlgt2__ext1010__pixel_write__read);

      intel_perf_query_add_counter_uint64(query, 6462, 40, NULL,mtlgt2__ext1010__pixel_blend__read);

      intel_perf_query_add_counter_uint64(query, 6463, 48, NULL,mtlgt2__ext1010__rasterizer_sample_output__read);

      intel_perf_query_add_counter_uint64(query, 6464, 56, NULL,mtlgt2__ext1010__postps_depth_stencil_alpha_test_fail__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_mtlgt2(struct intel_perf_config *perf)
{
   mtlgt2_register_render_basic_counter_query(perf);
   mtlgt2_register_compute_basic_counter_query(perf);
   mtlgt2_register_async_compute_counter_query(perf);
   mtlgt2_register_xve_activity_counter_query(perf);
   mtlgt2_register_gpu_busyness_counter_query(perf);
   mtlgt2_register_hdc_and_sf_counter_query(perf);
   mtlgt2_register_l3_counter_query(perf);
   mtlgt2_register_rasterizer_and_pixel_backend1_counter_query(perf);
   mtlgt2_register_rasterizer_and_pixel_backend2_counter_query(perf);
   mtlgt2_register_render_pipe_profile_counter_query(perf);
   mtlgt2_register_sampler_counter_query(perf);
   mtlgt2_register_tdl1_counter_query(perf);
   mtlgt2_register_tdl2_counter_query(perf);
   mtlgt2_register_test_oa_counter_query(perf);
   mtlgt2_register_ext1_counter_query(perf);
   mtlgt2_register_ext4_counter_query(perf);
   mtlgt2_register_ext5_counter_query(perf);
   mtlgt2_register_ext7_counter_query(perf);
   mtlgt2_register_ext8_counter_query(perf);
   mtlgt2_register_ext10_counter_query(perf);
   mtlgt2_register_ext11_counter_query(perf);
   mtlgt2_register_ext12_counter_query(perf);
   mtlgt2_register_ext13_counter_query(perf);
   mtlgt2_register_ext14_counter_query(perf);
   mtlgt2_register_ext17_counter_query(perf);
   mtlgt2_register_ext21_counter_query(perf);
   mtlgt2_register_ext23_counter_query(perf);
   mtlgt2_register_ext28_counter_query(perf);
   mtlgt2_register_ext31_counter_query(perf);
   mtlgt2_register_ext35_counter_query(perf);
   mtlgt2_register_ext39_counter_query(perf);
   mtlgt2_register_ext43_counter_query(perf);
   mtlgt2_register_ext45_counter_query(perf);
   mtlgt2_register_ext51_counter_query(perf);
   mtlgt2_register_ext53_counter_query(perf);
   mtlgt2_register_ext57_counter_query(perf);
   mtlgt2_register_ext61_counter_query(perf);
   mtlgt2_register_ext65_counter_query(perf);
   mtlgt2_register_ext66_counter_query(perf);
   mtlgt2_register_ext73_counter_query(perf);
   mtlgt2_register_ext74_counter_query(perf);
   mtlgt2_register_ext77_counter_query(perf);
   mtlgt2_register_ext79_counter_query(perf);
   mtlgt2_register_ext80_counter_query(perf);
   mtlgt2_register_ext83_counter_query(perf);
   mtlgt2_register_ext85_counter_query(perf);
   mtlgt2_register_ext87_counter_query(perf);
   mtlgt2_register_ext91_counter_query(perf);
   mtlgt2_register_ext93_counter_query(perf);
   mtlgt2_register_ext94_counter_query(perf);
   mtlgt2_register_ext97_counter_query(perf);
   mtlgt2_register_ext98_counter_query(perf);
   mtlgt2_register_ext100_counter_query(perf);
   mtlgt2_register_ext101_counter_query(perf);
   mtlgt2_register_ext102_counter_query(perf);
   mtlgt2_register_ext104_counter_query(perf);
   mtlgt2_register_ext105_counter_query(perf);
   mtlgt2_register_ext106_counter_query(perf);
   mtlgt2_register_ext107_counter_query(perf);
   mtlgt2_register_ext113_counter_query(perf);
   mtlgt2_register_ext116_counter_query(perf);
   mtlgt2_register_ext118_counter_query(perf);
   mtlgt2_register_ext120_counter_query(perf);
   mtlgt2_register_ext122_counter_query(perf);
   mtlgt2_register_ext123_counter_query(perf);
   mtlgt2_register_ext124_counter_query(perf);
   mtlgt2_register_ext126_counter_query(perf);
   mtlgt2_register_ext128_counter_query(perf);
   mtlgt2_register_ext130_counter_query(perf);
   mtlgt2_register_ext131_counter_query(perf);
   mtlgt2_register_ext134_counter_query(perf);
   mtlgt2_register_ext135_counter_query(perf);
   mtlgt2_register_ext138_counter_query(perf);
   mtlgt2_register_ext139_counter_query(perf);
   mtlgt2_register_ext142_counter_query(perf);
   mtlgt2_register_ext143_counter_query(perf);
   mtlgt2_register_ext146_counter_query(perf);
   mtlgt2_register_ext147_counter_query(perf);
   mtlgt2_register_ext150_counter_query(perf);
   mtlgt2_register_ext151_counter_query(perf);
   mtlgt2_register_ext154_counter_query(perf);
   mtlgt2_register_ext155_counter_query(perf);
   mtlgt2_register_ext156_counter_query(perf);
   mtlgt2_register_ext158_counter_query(perf);
   mtlgt2_register_ext159_counter_query(perf);
   mtlgt2_register_ext161_counter_query(perf);
   mtlgt2_register_ext163_counter_query(perf);
   mtlgt2_register_ext165_counter_query(perf);
   mtlgt2_register_ext167_counter_query(perf);
   mtlgt2_register_ext169_counter_query(perf);
   mtlgt2_register_ext171_counter_query(perf);
   mtlgt2_register_ext173_counter_query(perf);
   mtlgt2_register_ext174_counter_query(perf);
   mtlgt2_register_ext175_counter_query(perf);
   mtlgt2_register_ext176_counter_query(perf);
   mtlgt2_register_ext177_counter_query(perf);
   mtlgt2_register_ext181_counter_query(perf);
   mtlgt2_register_ext184_counter_query(perf);
   mtlgt2_register_ext188_counter_query(perf);
   mtlgt2_register_ext190_counter_query(perf);
   mtlgt2_register_ext192_counter_query(perf);
   mtlgt2_register_ext195_counter_query(perf);
   mtlgt2_register_ext200_counter_query(perf);
   mtlgt2_register_ext201_counter_query(perf);
   mtlgt2_register_ext202_counter_query(perf);
   mtlgt2_register_ext203_counter_query(perf);
   mtlgt2_register_ext204_counter_query(perf);
   mtlgt2_register_ext205_counter_query(perf);
   mtlgt2_register_ext212_counter_query(perf);
   mtlgt2_register_ext214_counter_query(perf);
   mtlgt2_register_ext220_counter_query(perf);
   mtlgt2_register_ext225_counter_query(perf);
   mtlgt2_register_ext227_counter_query(perf);
   mtlgt2_register_ext229_counter_query(perf);
   mtlgt2_register_ext231_counter_query(perf);
   mtlgt2_register_ext237_counter_query(perf);
   mtlgt2_register_ext238_counter_query(perf);
   mtlgt2_register_ext239_counter_query(perf);
   mtlgt2_register_ext240_counter_query(perf);
   mtlgt2_register_ext500_counter_query(perf);
   mtlgt2_register_ext501_counter_query(perf);
   mtlgt2_register_ext502_counter_query(perf);
   mtlgt2_register_ext503_counter_query(perf);
   mtlgt2_register_ext508_counter_query(perf);
   mtlgt2_register_ext509_counter_query(perf);
   mtlgt2_register_ext510_counter_query(perf);
   mtlgt2_register_ext511_counter_query(perf);
   mtlgt2_register_ext516_counter_query(perf);
   mtlgt2_register_ext517_counter_query(perf);
   mtlgt2_register_ext518_counter_query(perf);
   mtlgt2_register_ext519_counter_query(perf);
   mtlgt2_register_ext520_counter_query(perf);
   mtlgt2_register_ext521_counter_query(perf);
   mtlgt2_register_ext522_counter_query(perf);
   mtlgt2_register_ext523_counter_query(perf);
   mtlgt2_register_ext540_counter_query(perf);
   mtlgt2_register_ext541_counter_query(perf);
   mtlgt2_register_ext542_counter_query(perf);
   mtlgt2_register_ext543_counter_query(perf);
   mtlgt2_register_ext604_counter_query(perf);
   mtlgt2_register_ext1000_counter_query(perf);
   mtlgt2_register_ext1001_counter_query(perf);
   mtlgt2_register_ext1002_counter_query(perf);
   mtlgt2_register_ext1003_counter_query(perf);
   mtlgt2_register_ext1004_counter_query(perf);
   mtlgt2_register_ext1005_counter_query(perf);
   mtlgt2_register_ext1006_counter_query(perf);
   mtlgt2_register_ext1007_counter_query(perf);
   mtlgt2_register_ext1010_counter_query(perf);
}


static void
mtlgt3_register_render_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 38);

   query->name = "Render Metrics Basic";
   query->symbol_name = "RenderBasic";
   query->guid = "1124d1b6-6182-4b5a-950b-27b38ef7c996";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E040000 },
         { .reg = 0x00009888, .val = 0x20042800 },
         { .reg = 0x00009888, .val = 0x02015000 },
         { .reg = 0x00009888, .val = 0x02025000 },
         { .reg = 0x00009888, .val = 0x02035000 },
         { .reg = 0x00009888, .val = 0x04042000 },
         { .reg = 0x00009888, .val = 0x06040000 },
         { .reg = 0x00009888, .val = 0x14040800 },
         { .reg = 0x00009888, .val = 0x16040037 },
         { .reg = 0x00009888, .val = 0x02040000 },
         { .reg = 0x00009888, .val = 0x02085000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x02015000 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x000BC000 },
         { .reg = 0x00009888, .val = 0x0209A000 },
         { .reg = 0x00009888, .val = 0x020AA000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0202A000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002C000 },
         { .reg = 0x00009888, .val = 0x02015000 },
         { .reg = 0x00009888, .val = 0x0203A000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00003008 },
         { .reg = 0x0000E658, .val = 0x00011010 },
         { .reg = 0x0000E758, .val = 0x00050012 },
         { .reg = 0x0000E45C, .val = 0x00052051 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__render_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__render_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__render_basic__avg_gpu_core_frequency__max,mtlgt3__render_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 3, 24, NULL,mtlgt3__render_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 32, NULL,mtlgt3__render_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 40, NULL,mtlgt3__render_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 48, NULL,mtlgt3__render_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 56, NULL,mtlgt3__render_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 64, NULL,mtlgt3__render_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 9, 72, percentage_max_float,mtlgt3__render_basic__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 5641, 76, percentage_max_float,mtlgt3__render_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 5642, 80, percentage_max_float,mtlgt3__render_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 5643, 84, percentage_max_float,mtlgt3__render_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 5644, 88, percentage_max_float,mtlgt3__render_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 5645, 92, percentage_max_float,mtlgt3__render_basic__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5646, 96, percentage_max_float,mtlgt3__render_basic__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 5647, 100, percentage_max_float,mtlgt3__render_basic__vs_send_active__read);

      intel_perf_query_add_counter_float(query, 5648, 104, percentage_max_float,mtlgt3__render_basic__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5649, 108, percentage_max_float,mtlgt3__render_basic__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 5650, 112, percentage_max_float,mtlgt3__render_basic__ps_send_active__read);

      intel_perf_query_add_counter_uint64(query, 139, 120, NULL,mtlgt3__render_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 128, NULL,mtlgt3__render_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 136, NULL,mtlgt3__render_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 144, NULL,mtlgt3__render_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 152, NULL,mtlgt3__render_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 160, NULL,mtlgt3__render_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 168, NULL,mtlgt3__render_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 176, NULL,mtlgt3__render_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 184, NULL,mtlgt3__render_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 5651, 192, mtlgt3__render_basic__slm_reads__max,mtlgt3__render_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 5652, 200, mtlgt3__render_basic__slm_writes__max,mtlgt3__render_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 142, 208, NULL,mtlgt3__render_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 216, NULL,mtlgt3__render_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 224, NULL,mtlgt3__render_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 232, mtlgt3__render_basic__gti_read_throughput__max,mtlgt3__render_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 240, mtlgt3__render_basic__gti_write_throughput__max,mtlgt3__render_basic__gti_write_throughput__read);

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 563, 248, percentage_max_float,mtlgt3__render_basic__samplers_busy__read);
      }

      if (perf->sys_vars.subslice_mask & 1) {
         intel_perf_query_add_counter_float(query, 565, 252, percentage_max_float,mtlgt3__render_basic__sampler_bottleneck__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_compute_basic_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 39);

   query->name = "Compute Metrics Basic";
   query->symbol_name = "ComputeBasic";
   query->guid = "522743d7-4e01-461a-8600-7904e8ddc80c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00003009 },
         { .reg = 0x0000E758, .val = 0x0000200A },
         { .reg = 0x0000E45C, .val = 0x00006008 },
         { .reg = 0x0000E55C, .val = 0x0000B007 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__compute_basic__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__compute_basic__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__compute_basic__avg_gpu_core_frequency__max,mtlgt3__compute_basic__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__compute_basic__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,mtlgt3__compute_basic__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,mtlgt3__compute_basic__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,mtlgt3__compute_basic__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,mtlgt3__compute_basic__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,mtlgt3__compute_basic__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,mtlgt3__compute_basic__cs_threads__read);

      intel_perf_query_add_counter_float(query, 5641, 80, percentage_max_float,mtlgt3__compute_basic__xve_active__read);

      intel_perf_query_add_counter_float(query, 5642, 84, percentage_max_float,mtlgt3__compute_basic__xve_stall__read);

      intel_perf_query_add_counter_float(query, 5653, 88, percentage_max_float,mtlgt3__compute_basic__fpu_active__read);

      intel_perf_query_add_counter_float(query, 5654, 92, percentage_max_float,mtlgt3__compute_basic__em_active__read);

      intel_perf_query_add_counter_float(query, 5655, 96, percentage_max_float,mtlgt3__compute_basic__xmx_active__read);

      intel_perf_query_add_counter_float(query, 5644, 100, percentage_max_float,mtlgt3__compute_basic__xve_fpu_em_active__read);

      intel_perf_query_add_counter_float(query, 5656, 104, percentage_max_float,mtlgt3__compute_basic__xve_fpu_xmx_active__read);

      intel_perf_query_add_counter_float(query, 5657, 108, mtlgt3__compute_basic__xve_avg_ipc_rate__max,mtlgt3__compute_basic__xve_avg_ipc_rate__read);

      intel_perf_query_add_counter_float(query, 5658, 112, percentage_max_float,mtlgt3__compute_basic__send_active__read);

      intel_perf_query_add_counter_float(query, 5643, 116, percentage_max_float,mtlgt3__compute_basic__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 5659, 120, percentage_max_float,mtlgt3__compute_basic__xve_fpu_flt16__read);

      intel_perf_query_add_counter_float(query, 5660, 124, percentage_max_float,mtlgt3__compute_basic__xve_fpu_flt32__read);

      intel_perf_query_add_counter_float(query, 5661, 128, percentage_max_float,mtlgt3__compute_basic__xve_fpu_flt64__read);

      intel_perf_query_add_counter_uint64(query, 139, 136, NULL,mtlgt3__compute_basic__rasterized_pixels__read);

      intel_perf_query_add_counter_uint64(query, 45, 144, NULL,mtlgt3__compute_basic__hi_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 46, 152, NULL,mtlgt3__compute_basic__early_depth_test_fails__read);

      intel_perf_query_add_counter_uint64(query, 47, 160, NULL,mtlgt3__compute_basic__samples_killed_in_ps__read);

      intel_perf_query_add_counter_uint64(query, 140, 168, NULL,mtlgt3__compute_basic__pixels_failing_post_ps_tests__read);

      intel_perf_query_add_counter_uint64(query, 51, 176, NULL,mtlgt3__compute_basic__samples_written__read);

      intel_perf_query_add_counter_uint64(query, 52, 184, NULL,mtlgt3__compute_basic__samples_blended__read);

      intel_perf_query_add_counter_uint64(query, 136, 192, NULL,mtlgt3__compute_basic__sampler_texels__read);

      intel_perf_query_add_counter_uint64(query, 137, 200, NULL,mtlgt3__compute_basic__sampler_texel_misses__read);

      intel_perf_query_add_counter_uint64(query, 5651, 208, mtlgt3__compute_basic__slm_reads__max,mtlgt3__compute_basic__slm_reads__read);

      intel_perf_query_add_counter_uint64(query, 5652, 216, mtlgt3__compute_basic__slm_writes__max,mtlgt3__compute_basic__slm_writes__read);

      intel_perf_query_add_counter_uint64(query, 142, 224, NULL,mtlgt3__compute_basic__shader_memory_accesses__read);

      intel_perf_query_add_counter_uint64(query, 143, 232, NULL,mtlgt3__compute_basic__shader_atomics__read);

      intel_perf_query_add_counter_uint64(query, 147, 240, NULL,mtlgt3__compute_basic__shader_barriers__read);

      intel_perf_query_add_counter_uint64(query, 57, 248, mtlgt3__compute_basic__gti_read_throughput__max,mtlgt3__compute_basic__gti_read_throughput__read);

      intel_perf_query_add_counter_uint64(query, 58, 256, mtlgt3__compute_basic__gti_write_throughput__max,mtlgt3__compute_basic__gti_write_throughput__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_async_compute_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "AsyncCompute";
   query->symbol_name = "AsyncCompute";
   query->guid = "d9edd254-60e8-4ce0-82b1-7b3de3bc79a6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00010000 },
         { .reg = 0x0000E558, .val = 0x00060050 },
         { .reg = 0x0000E658, .val = 0x00001090 },
         { .reg = 0x0000E758, .val = 0x00051011 },
         { .reg = 0x0000E45C, .val = 0x00091061 },
         { .reg = 0x0000E55C, .val = 0x00004008 },
         { .reg = 0x0000E65C, .val = 0x00000005 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__async_compute__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__async_compute__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__async_compute__avg_gpu_core_frequency__max,mtlgt3__async_compute__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__async_compute__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,mtlgt3__async_compute__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,mtlgt3__async_compute__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,mtlgt3__async_compute__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,mtlgt3__async_compute__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,mtlgt3__async_compute__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,mtlgt3__async_compute__cs_threads__read);

      intel_perf_query_add_counter_float(query, 5653, 80, percentage_max_float,mtlgt3__async_compute__fpu_active__read);

      intel_perf_query_add_counter_float(query, 5645, 84, percentage_max_float,mtlgt3__async_compute__vs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5648, 88, percentage_max_float,mtlgt3__async_compute__ps_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5662, 92, percentage_max_float,mtlgt3__async_compute__cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5663, 96, percentage_max_float,mtlgt3__async_compute__async_cs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5654, 100, percentage_max_float,mtlgt3__async_compute__em_active__read);

      intel_perf_query_add_counter_float(query, 5646, 104, percentage_max_float,mtlgt3__async_compute__vs_em_active__read);

      intel_perf_query_add_counter_float(query, 5649, 108, percentage_max_float,mtlgt3__async_compute__ps_em_active__read);

      intel_perf_query_add_counter_float(query, 5664, 112, percentage_max_float,mtlgt3__async_compute__cs_em_active__read);

      intel_perf_query_add_counter_float(query, 5665, 116, percentage_max_float,mtlgt3__async_compute__async_cs_em_active__read);

      intel_perf_query_add_counter_float(query, 5643, 120, percentage_max_float,mtlgt3__async_compute__xve_thread_occupancy__read);

      intel_perf_query_add_counter_float(query, 5641, 124, percentage_max_float,mtlgt3__async_compute__xve_active__read);

      intel_perf_query_add_counter_float(query, 5642, 128, percentage_max_float,mtlgt3__async_compute__xve_stall__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_xve_activity_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "XveActivity";
   query->symbol_name = "XveActivity";
   query->guid = "703a9693-1444-4e7c-a235-1c4d6ee01943";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00030020 },
         { .reg = 0x0000E558, .val = 0x00021040 },
         { .reg = 0x0000E658, .val = 0x00041031 },
         { .reg = 0x0000E758, .val = 0x00032022 },
         { .reg = 0x0000E45C, .val = 0x00062042 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__xve_activity__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__xve_activity__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__xve_activity__avg_gpu_core_frequency__max,mtlgt3__xve_activity__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__xve_activity__gpu_busy__read);

      intel_perf_query_add_counter_uint64(query, 3, 32, NULL,mtlgt3__xve_activity__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 40, NULL,mtlgt3__xve_activity__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 48, NULL,mtlgt3__xve_activity__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 56, NULL,mtlgt3__xve_activity__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 64, NULL,mtlgt3__xve_activity__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 72, NULL,mtlgt3__xve_activity__cs_threads__read);

      intel_perf_query_add_counter_float(query, 5666, 80, percentage_max_float,mtlgt3__xve_activity__hs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5667, 84, percentage_max_float,mtlgt3__xve_activity__ds_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5668, 88, percentage_max_float,mtlgt3__xve_activity__gs_fpu_active__read);

      intel_perf_query_add_counter_float(query, 5669, 92, percentage_max_float,mtlgt3__xve_activity__hs_em_active__read);

      intel_perf_query_add_counter_float(query, 5670, 96, percentage_max_float,mtlgt3__xve_activity__ds_em_active__read);

      intel_perf_query_add_counter_float(query, 5671, 100, percentage_max_float,mtlgt3__xve_activity__gs_em_active__read);

      intel_perf_query_add_counter_float(query, 5672, 104, percentage_max_float,mtlgt3__xve_activity__hs_send_active__read);

      intel_perf_query_add_counter_float(query, 5673, 108, percentage_max_float,mtlgt3__xve_activity__ds_send_active__read);

      intel_perf_query_add_counter_float(query, 5674, 112, percentage_max_float,mtlgt3__xve_activity__gs_send_active__read);

      intel_perf_query_add_counter_float(query, 5675, 116, percentage_max_float,mtlgt3__xve_activity__cs_send_active__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_gpu_busyness_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 16);

   query->name = "GpuBusyness";
   query->symbol_name = "GpuBusyness";
   query->guid = "edae72d3-bb06-47af-87b4-7585274c6076";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x18022400 },
         { .reg = 0x00009888, .val = 0x1C012400 },
         { .reg = 0x00009888, .val = 0x26010009 },
         { .reg = 0x00009888, .val = 0x02020006 },
         { .reg = 0x00009888, .val = 0x14020004 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x04011409 },
         { .reg = 0x00009888, .val = 0x16010100 },
         { .reg = 0x00009888, .val = 0x18010014 },
         { .reg = 0x00009888, .val = 0x02010400 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010201 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00000008 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__gpu_busyness__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__gpu_busyness__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__gpu_busyness__avg_gpu_core_frequency__max,mtlgt3__gpu_busyness__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__gpu_busyness__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 5641, 28, percentage_max_float,mtlgt3__gpu_busyness__xve_active__read);

      intel_perf_query_add_counter_float(query, 5642, 32, percentage_max_float,mtlgt3__gpu_busyness__xve_stall__read);

      intel_perf_query_add_counter_float(query, 5643, 36, percentage_max_float,mtlgt3__gpu_busyness__xve_thread_occupancy__read);

      intel_perf_query_add_counter_uint64(query, 3, 40, NULL,mtlgt3__gpu_busyness__vs_threads__read);

      intel_perf_query_add_counter_uint64(query, 121, 48, NULL,mtlgt3__gpu_busyness__hs_threads__read);

      intel_perf_query_add_counter_uint64(query, 122, 56, NULL,mtlgt3__gpu_busyness__ds_threads__read);

      intel_perf_query_add_counter_uint64(query, 6, 64, NULL,mtlgt3__gpu_busyness__gs_threads__read);

      intel_perf_query_add_counter_uint64(query, 7, 72, NULL,mtlgt3__gpu_busyness__ps_threads__read);

      intel_perf_query_add_counter_uint64(query, 8, 80, NULL,mtlgt3__gpu_busyness__cs_threads__read);

      intel_perf_query_add_counter_float(query, 309, 88, percentage_max_float,mtlgt3__gpu_busyness__render_busy__read);

      intel_perf_query_add_counter_float(query, 5676, 92, percentage_max_float,mtlgt3__gpu_busyness__compute_engine0_busy__read);

      intel_perf_query_add_counter_float(query, 313, 96, percentage_max_float,mtlgt3__gpu_busyness__blitter_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_hdc_and_sf1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Metric set HDCAndSF1";
   query->symbol_name = "HDCAndSF1";
   query->guid = "e1a408d6-aece-4bde-8bbd-1c7fbfff02cf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C023800 },
         { .reg = 0x00009888, .val = 0x1C223800 },
         { .reg = 0x00009888, .val = 0x1C423800 },
         { .reg = 0x00009888, .val = 0x1C623800 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x0A0209C0 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00080100 },
         { .reg = 0x00009888, .val = 0x04220000 },
         { .reg = 0x00009888, .val = 0x0A220027 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00280040 },
         { .reg = 0x00009888, .val = 0x04420000 },
         { .reg = 0x00009888, .val = 0x084209C0 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00480010 },
         { .reg = 0x00009888, .val = 0x04620000 },
         { .reg = 0x00009888, .val = 0x08620027 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00680004 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x1E0B6400 },
         { .reg = 0x00009888, .val = 0x00010171 },
         { .reg = 0x00009888, .val = 0x00040141 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009888, .val = 0x040B4E00 },
         { .reg = 0x00009888, .val = 0x000B0018 },
         { .reg = 0x00009888, .val = 0x000902C0 },
         { .reg = 0x00009888, .val = 0x000A02A2 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000202AE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x00010155 },
         { .reg = 0x00009888, .val = 0x000302AA },
         { .reg = 0x00009888, .val = 0x4C010E00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010003 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__hdc_and_sf1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__hdc_and_sf1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__hdc_and_sf1__avg_gpu_core_frequency__max,mtlgt3__hdc_and_sf1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__hdc_and_sf1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5677, 28, percentage_max_float,mtlgt3__hdc_and_sf1__non_sampler_shader00_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5678, 32, percentage_max_float,mtlgt3__hdc_and_sf1__non_sampler_shader01_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5679, 36, percentage_max_float,mtlgt3__hdc_and_sf1__non_sampler_shader02_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5680, 40, percentage_max_float,mtlgt3__hdc_and_sf1__non_sampler_shader03_access_stalled_on_l3__read);
      }

      intel_perf_query_add_counter_float(query, 5681, 44, percentage_max_float,mtlgt3__hdc_and_sf1__poly0_data_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_hdc_and_sf2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Metric set HDCAndSF2";
   query->symbol_name = "HDCAndSF2";
   query->guid = "374e8aa3-09df-4d69-ad32-3133f6ad3c86";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C823800 },
         { .reg = 0x00009888, .val = 0x1CA23800 },
         { .reg = 0x00009888, .val = 0x1CC23800 },
         { .reg = 0x00009888, .val = 0x1CE23800 },
         { .reg = 0x00009888, .val = 0x04820000 },
         { .reg = 0x00009888, .val = 0x0A820027 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00880040 },
         { .reg = 0x00009888, .val = 0x04A20000 },
         { .reg = 0x00009888, .val = 0x08A209C0 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A80010 },
         { .reg = 0x00009888, .val = 0x04C20000 },
         { .reg = 0x00009888, .val = 0x08C20027 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C80004 },
         { .reg = 0x00009888, .val = 0x04E20000 },
         { .reg = 0x00009888, .val = 0x06E24E00 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x00E80001 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x1E2B6400 },
         { .reg = 0x00009888, .val = 0x0021015C },
         { .reg = 0x00009888, .val = 0x00240150 },
         { .reg = 0x00009888, .val = 0x022B0000 },
         { .reg = 0x00009888, .val = 0x082B09C0 },
         { .reg = 0x00009888, .val = 0x002B000C },
         { .reg = 0x00009888, .val = 0x002900B0 },
         { .reg = 0x00009888, .val = 0x002A02A8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x008202AB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005001F },
         { .reg = 0x00009888, .val = 0x0002001F },
         { .reg = 0x00009888, .val = 0x00010155 },
         { .reg = 0x00009888, .val = 0x00030155 },
         { .reg = 0x00009888, .val = 0x0004001F },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010070 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000002 },
         { .reg = 0x0000D94C, .val = 0x0000FFFD },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFFB },
         { .reg = 0x0000D958, .val = 0x00000002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00000002 },
         { .reg = 0x0000D964, .val = 0x0000FFEF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__hdc_and_sf2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__hdc_and_sf2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__hdc_and_sf2__avg_gpu_core_frequency__max,mtlgt3__hdc_and_sf2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__hdc_and_sf2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6465, 28, percentage_max_float,mtlgt3__hdc_and_sf2__non_sampler_shader10_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6466, 32, percentage_max_float,mtlgt3__hdc_and_sf2__non_sampler_shader11_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6467, 36, percentage_max_float,mtlgt3__hdc_and_sf2__non_sampler_shader12_access_stalled_on_l3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6468, 40, percentage_max_float,mtlgt3__hdc_and_sf2__non_sampler_shader13_access_stalled_on_l3__read);
      }

      intel_perf_query_add_counter_float(query, 6469, 44, percentage_max_float,mtlgt3__hdc_and_sf2__poly1_data_ready__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_l3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "L3";
   query->symbol_name = "L3";
   query->guid = "580d5311-4e9d-4210-b419-37259ffcd3f2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03012000 },
         { .reg = 0x00009888, .val = 0x03212000 },
         { .reg = 0x00009888, .val = 0x03412000 },
         { .reg = 0x00009888, .val = 0x03612000 },
         { .reg = 0x00009888, .val = 0x03812000 },
         { .reg = 0x00009888, .val = 0x03A12000 },
         { .reg = 0x00009888, .val = 0x03C12000 },
         { .reg = 0x00009888, .val = 0x03E12000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02825555 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x05010006 },
         { .reg = 0x00009888, .val = 0x09010007 },
         { .reg = 0x00009888, .val = 0x01210000 },
         { .reg = 0x00009888, .val = 0x05210180 },
         { .reg = 0x00009888, .val = 0x092101C0 },
         { .reg = 0x00009888, .val = 0x01410000 },
         { .reg = 0x00009888, .val = 0x07410006 },
         { .reg = 0x00009888, .val = 0x0B410007 },
         { .reg = 0x00009888, .val = 0x01610000 },
         { .reg = 0x00009888, .val = 0x07610180 },
         { .reg = 0x00009888, .val = 0x0B6101C0 },
         { .reg = 0x00009888, .val = 0x00012B1A },
         { .reg = 0x00009888, .val = 0x02010163 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0F8101C0 },
         { .reg = 0x00009888, .val = 0x11810006 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x0FA10007 },
         { .reg = 0x00009888, .val = 0x11A10180 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x0DC101C0 },
         { .reg = 0x00009888, .val = 0x13C10006 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x0DE10007 },
         { .reg = 0x00009888, .val = 0x13E10180 },
         { .reg = 0x00009888, .val = 0x02814A00 },
         { .reg = 0x00009888, .val = 0x04814693 },
         { .reg = 0x00009888, .val = 0x06810005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009888, .val = 0x58010604 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010400 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010402 },
         { .reg = 0x00009888, .val = 0x52010010 },
         { .reg = 0x00009888, .val = 0x54010002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__l3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__l3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__l3__avg_gpu_core_frequency__max,mtlgt3__l3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__l3__gpu_busy__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5686, 28, percentage_max_float,mtlgt3__l3__l3_input_available_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5687, 32, percentage_max_float,mtlgt3__l3__l3_input_available_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5688, 36, percentage_max_float,mtlgt3__l3__l3_input_available_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5689, 40, percentage_max_float,mtlgt3__l3__l3_input_available_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6470, 44, percentage_max_float,mtlgt3__l3__l3_input_available_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6471, 48, percentage_max_float,mtlgt3__l3__l3_input_available_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6472, 52, percentage_max_float,mtlgt3__l3__l3_input_available_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6473, 56, percentage_max_float,mtlgt3__l3__l3_input_available_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5690, 60, percentage_max_float,mtlgt3__l3__l3_output_ready_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5691, 64, percentage_max_float,mtlgt3__l3__l3_output_ready_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5692, 68, percentage_max_float,mtlgt3__l3__l3_output_ready_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5693, 72, percentage_max_float,mtlgt3__l3__l3_output_ready_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6474, 76, percentage_max_float,mtlgt3__l3__l3_output_ready_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6475, 80, percentage_max_float,mtlgt3__l3__l3_output_ready_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6476, 84, percentage_max_float,mtlgt3__l3__l3_output_ready_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6477, 88, percentage_max_float,mtlgt3__l3__l3_output_ready_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_rasterizer_and_pixel_backend1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Metric set RasterizerAndPixelBackend1";
   query->symbol_name = "RasterizerAndPixelBackend1";
   query->guid = "4286bd8f-f9db-45e5-aa37-51dd7067f751";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x260B6000 },
         { .reg = 0x00009888, .val = 0x280B0000 },
         { .reg = 0x00009888, .val = 0x0C0977D0 },
         { .reg = 0x00009888, .val = 0x0E096000 },
         { .reg = 0x00009888, .val = 0x0C0A7000 },
         { .reg = 0x00009888, .val = 0x0E0A6400 },
         { .reg = 0x00009888, .val = 0x262B6000 },
         { .reg = 0x00009888, .val = 0x282B0000 },
         { .reg = 0x00009888, .val = 0x0C297000 },
         { .reg = 0x00009888, .val = 0x0E296000 },
         { .reg = 0x00009888, .val = 0x0C2A7000 },
         { .reg = 0x00009888, .val = 0x0E2A6000 },
         { .reg = 0x00009888, .val = 0x00015540 },
         { .reg = 0x00009888, .val = 0x00045540 },
         { .reg = 0x00009888, .val = 0x040B01A0 },
         { .reg = 0x00009888, .val = 0x080B0D74 },
         { .reg = 0x00009888, .val = 0x0A0B003E },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009888, .val = 0x000B00C0 },
         { .reg = 0x00009888, .val = 0x04090200 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x040A0200 },
         { .reg = 0x00009888, .val = 0x100A001F },
         { .reg = 0x00009888, .val = 0x000AAA80 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009888, .val = 0x00210015 },
         { .reg = 0x00009888, .val = 0x02210500 },
         { .reg = 0x00009888, .val = 0x00240015 },
         { .reg = 0x00009888, .val = 0x02240500 },
         { .reg = 0x00009888, .val = 0x042B69A0 },
         { .reg = 0x00009888, .val = 0x062B0FB5 },
         { .reg = 0x00009888, .val = 0x022B0000 },
         { .reg = 0x00009888, .val = 0x002B3000 },
         { .reg = 0x00009888, .val = 0x04290200 },
         { .reg = 0x00009888, .val = 0x122907D0 },
         { .reg = 0x00009888, .val = 0x08290000 },
         { .reg = 0x00009888, .val = 0x02290000 },
         { .reg = 0x00009888, .val = 0x042A0200 },
         { .reg = 0x00009888, .val = 0x102A0400 },
         { .reg = 0x00009888, .val = 0x122A001F },
         { .reg = 0x00009888, .val = 0x002A002A },
         { .reg = 0x00009888, .val = 0x022A0A00 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AA80 },
         { .reg = 0x00009888, .val = 0x0202000A },
         { .reg = 0x00009888, .val = 0x0082002A },
         { .reg = 0x00009888, .val = 0x02820AA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00053C07 },
         { .reg = 0x00009888, .val = 0x00023FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010555 },
         { .reg = 0x00009888, .val = 0x0003AA95 },
         { .reg = 0x00009888, .val = 0x0203055A },
         { .reg = 0x00009888, .val = 0x00043C07 },
         { .reg = 0x00009888, .val = 0x4C010200 },
         { .reg = 0x00009888, .val = 0x56010010 },
         { .reg = 0x00009888, .val = 0x58010601 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010403 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010C06 },
         { .reg = 0x00009888, .val = 0x4E010040 },
         { .reg = 0x00009888, .val = 0x50010004 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000600 },
         { .reg = 0x0000D954, .val = 0x0000FF3F },
         { .reg = 0x0000D958, .val = 0x00001800 },
         { .reg = 0x0000D95C, .val = 0x0000FCFF },
         { .reg = 0x0000D960, .val = 0x00006000 },
         { .reg = 0x0000D964, .val = 0x0000F3FF },
         { .reg = 0x0000D968, .val = 0x00018000 },
         { .reg = 0x0000D96C, .val = 0x0000CFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__rasterizer_and_pixel_backend1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__rasterizer_and_pixel_backend1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max,mtlgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 6478, 28, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend1__pixel_data10_ready__read);

      intel_perf_query_add_counter_float(query, 6479, 32, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend1__pixel_data11_ready__read);

      intel_perf_query_add_counter_float(query, 360, 36, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend1__pixel_data00_ready__read);

      intel_perf_query_add_counter_float(query, 361, 40, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend1__pixel_data01_ready__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 264, 44, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend1__rasterizer1_input_available__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 266, 48, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend1__rasterizer0_input_available__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_rasterizer_and_pixel_backend2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Metric set RasterizerAndPixelBackend2";
   query->symbol_name = "RasterizerAndPixelBackend2";
   query->guid = "ac90f98d-14a6-4dcc-b5d7-31ee157bb6e2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x260B7000 },
         { .reg = 0x00009888, .val = 0x262B7000 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x02044000 },
         { .reg = 0x00009888, .val = 0x040B0020 },
         { .reg = 0x00009888, .val = 0x140B0037 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x020A8000 },
         { .reg = 0x00009888, .val = 0x02211000 },
         { .reg = 0x00009888, .val = 0x02241000 },
         { .reg = 0x00009888, .val = 0x042B0020 },
         { .reg = 0x00009888, .val = 0x122B0DC0 },
         { .reg = 0x00009888, .val = 0x022B0000 },
         { .reg = 0x00009888, .val = 0x002B0000 },
         { .reg = 0x00009888, .val = 0x022A2000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x1A020126 },
         { .reg = 0x00009888, .val = 0x1A820126 },
         { .reg = 0x00009888, .val = 0x04020800 },
         { .reg = 0x00009888, .val = 0x10020E31 },
         { .reg = 0x00009888, .val = 0x02028000 },
         { .reg = 0x00009888, .val = 0x04820800 },
         { .reg = 0x00009888, .val = 0x12820E31 },
         { .reg = 0x00009888, .val = 0x02822000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00057000 },
         { .reg = 0x00009888, .val = 0x0002FC00 },
         { .reg = 0x00009888, .val = 0x02015550 },
         { .reg = 0x00009888, .val = 0x020395A0 },
         { .reg = 0x00009888, .val = 0x00047000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010060 },
         { .reg = 0x00009888, .val = 0x50010806 },
         { .reg = 0x00009888, .val = 0x52010040 },
         { .reg = 0x00009888, .val = 0x54010400 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__rasterizer_and_pixel_backend2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__rasterizer_and_pixel_backend2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max,mtlgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend2__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 5694, 28, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend2__ps_output00_available__read);

      intel_perf_query_add_counter_float(query, 5695, 32, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend2__pixel_values00_ready__read);

      intel_perf_query_add_counter_float(query, 6480, 36, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend2__ps_output01_available__read);

      intel_perf_query_add_counter_float(query, 6481, 40, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend2__pixel_values01_ready__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 261, 44, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend2__rasterizer0_output_ready__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 265, 48, percentage_max_float,mtlgt3__rasterizer_and_pixel_backend2__rasterizer1_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_render_pipe_profile1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile1";
   query->guid = "f15b97f6-eb1b-43a8-839c-7bd956c143c4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1407001F },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x06070080 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x00080080 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x18030000 },
         { .reg = 0x00009888, .val = 0x200303C0 },
         { .reg = 0x00009888, .val = 0x22030000 },
         { .reg = 0x00009888, .val = 0x160401F0 },
         { .reg = 0x00009888, .val = 0x14050640 },
         { .reg = 0x00009888, .val = 0x0A050000 },
         { .reg = 0x00009888, .val = 0x1406001F },
         { .reg = 0x00009888, .val = 0x0A0600C0 },
         { .reg = 0x00009888, .val = 0x16092400 },
         { .reg = 0x00009888, .val = 0x180A0009 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02011555 },
         { .reg = 0x00009888, .val = 0x02030003 },
         { .reg = 0x00009888, .val = 0x04030020 },
         { .reg = 0x00009888, .val = 0x06030880 },
         { .reg = 0x00009888, .val = 0x08030029 },
         { .reg = 0x00009888, .val = 0x0C030001 },
         { .reg = 0x00009888, .val = 0x0E0300C0 },
         { .reg = 0x00009888, .val = 0x100308EB },
         { .reg = 0x00009888, .val = 0x000331A1 },
         { .reg = 0x00009888, .val = 0x04040200 },
         { .reg = 0x00009888, .val = 0x14040025 },
         { .reg = 0x00009888, .val = 0x0004A96A },
         { .reg = 0x00009888, .val = 0x02040AAA },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x04054200 },
         { .reg = 0x00009888, .val = 0x0C050002 },
         { .reg = 0x00009888, .val = 0x10050880 },
         { .reg = 0x00009888, .val = 0x00052120 },
         { .reg = 0x00009888, .val = 0x00060002 },
         { .reg = 0x00009888, .val = 0x02060010 },
         { .reg = 0x00009888, .val = 0x08060007 },
         { .reg = 0x00009888, .val = 0x10060032 },
         { .reg = 0x00009888, .val = 0x000B0018 },
         { .reg = 0x00009888, .val = 0x04090004 },
         { .reg = 0x00009888, .val = 0x0A090007 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090080 },
         { .reg = 0x00009888, .val = 0x040A0004 },
         { .reg = 0x00009888, .val = 0x160A0007 },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2AAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010800 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010005 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010A04 },
         { .reg = 0x00009888, .val = 0x5E010040 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A04 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010805 },
         { .reg = 0x00009888, .val = 0x52010040 },
         { .reg = 0x00009888, .val = 0x54011207 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__render_pipe_profile1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__render_pipe_profile1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__render_pipe_profile1__avg_gpu_core_frequency__max,mtlgt3__render_pipe_profile1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__render_pipe_profile1__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 5696, 28, percentage_max_float,mtlgt3__render_pipe_profile1__vf0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5697, 32, percentage_max_float,mtlgt3__render_pipe_profile1__vs0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5698, 36, percentage_max_float,mtlgt3__render_pipe_profile1__cl0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5699, 40, percentage_max_float,mtlgt3__render_pipe_profile1__hs0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5700, 44, percentage_max_float,mtlgt3__render_pipe_profile1__ds0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5701, 48, percentage_max_float,mtlgt3__render_pipe_profile1__gs0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5702, 52, percentage_max_float,mtlgt3__render_pipe_profile1__sf0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5703, 56, percentage_max_float,mtlgt3__render_pipe_profile1__so0_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5704, 60, percentage_max_float,mtlgt3__render_pipe_profile1__cl0_stall__read);

      intel_perf_query_add_counter_float(query, 5705, 64, percentage_max_float,mtlgt3__render_pipe_profile1__hs0_stall__read);

      intel_perf_query_add_counter_float(query, 5706, 68, percentage_max_float,mtlgt3__render_pipe_profile1__ds0_stall__read);

      intel_perf_query_add_counter_float(query, 5707, 72, percentage_max_float,mtlgt3__render_pipe_profile1__sf0_stall__read);

      intel_perf_query_add_counter_float(query, 5708, 76, percentage_max_float,mtlgt3__render_pipe_profile1__so0_stall__read);

      intel_perf_query_add_counter_float(query, 5709, 80, percentage_max_float,mtlgt3__render_pipe_profile1__hi_depth00_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5710, 84, percentage_max_float,mtlgt3__render_pipe_profile1__hi_depth01_bottleneck__read);

      intel_perf_query_add_counter_float(query, 5711, 88, percentage_max_float,mtlgt3__render_pipe_profile1__bc00_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_render_pipe_profile2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Render Metrics for 3D Pipeline Profile";
   query->symbol_name = "RenderPipeProfile2";
   query->guid = "86b9199d-8a44-4694-bbde-6fd35bada236";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1487001F },
         { .reg = 0x00009888, .val = 0x00870000 },
         { .reg = 0x00009888, .val = 0x04870002 },
         { .reg = 0x00009888, .val = 0x00880002 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x18230000 },
         { .reg = 0x00009888, .val = 0x202303C0 },
         { .reg = 0x00009888, .val = 0x22230000 },
         { .reg = 0x00009888, .val = 0x162401F0 },
         { .reg = 0x00009888, .val = 0x14250640 },
         { .reg = 0x00009888, .val = 0x0A250021 },
         { .reg = 0x00009888, .val = 0x1426001F },
         { .reg = 0x00009888, .val = 0x0A260000 },
         { .reg = 0x00009888, .val = 0x16292400 },
         { .reg = 0x00009888, .val = 0x182A0009 },
         { .reg = 0x00009888, .val = 0x00215551 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x02230003 },
         { .reg = 0x00009888, .val = 0x04230004 },
         { .reg = 0x00009888, .val = 0x08230840 },
         { .reg = 0x00009888, .val = 0x0A23002A },
         { .reg = 0x00009888, .val = 0x0C230040 },
         { .reg = 0x00009888, .val = 0x0E230AE3 },
         { .reg = 0x00009888, .val = 0x122300C0 },
         { .reg = 0x00009888, .val = 0x00235C60 },
         { .reg = 0x00009888, .val = 0x04240200 },
         { .reg = 0x00009888, .val = 0x14240940 },
         { .reg = 0x00009888, .val = 0x0024AA91 },
         { .reg = 0x00009888, .val = 0x02242AAA },
         { .reg = 0x00009888, .val = 0x02250000 },
         { .reg = 0x00009888, .val = 0x0E250080 },
         { .reg = 0x00009888, .val = 0x10250022 },
         { .reg = 0x00009888, .val = 0x00255040 },
         { .reg = 0x00009888, .val = 0x00260002 },
         { .reg = 0x00009888, .val = 0x02260010 },
         { .reg = 0x00009888, .val = 0x082601C0 },
         { .reg = 0x00009888, .val = 0x0E2600C0 },
         { .reg = 0x00009888, .val = 0x10260C80 },
         { .reg = 0x00009888, .val = 0x002B0005 },
         { .reg = 0x00009888, .val = 0x04290004 },
         { .reg = 0x00009888, .val = 0x08290007 },
         { .reg = 0x00009888, .val = 0x00290002 },
         { .reg = 0x00009888, .val = 0x042A0004 },
         { .reg = 0x00009888, .val = 0x082A0007 },
         { .reg = 0x00009888, .val = 0x002AAAA2 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010090 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x5E010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010040 },
         { .reg = 0x00009888, .val = 0x50010804 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010E04 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__render_pipe_profile2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__render_pipe_profile2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__render_pipe_profile2__avg_gpu_core_frequency__max,mtlgt3__render_pipe_profile2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__render_pipe_profile2__gpu_busy__read);

      intel_perf_query_add_counter_float(query, 6482, 28, percentage_max_float,mtlgt3__render_pipe_profile2__vf1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6483, 32, percentage_max_float,mtlgt3__render_pipe_profile2__vs1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6484, 36, percentage_max_float,mtlgt3__render_pipe_profile2__cl1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6485, 40, percentage_max_float,mtlgt3__render_pipe_profile2__hs1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6486, 44, percentage_max_float,mtlgt3__render_pipe_profile2__ds1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6487, 48, percentage_max_float,mtlgt3__render_pipe_profile2__gs1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6488, 52, percentage_max_float,mtlgt3__render_pipe_profile2__sf1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6489, 56, percentage_max_float,mtlgt3__render_pipe_profile2__so1_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6490, 60, percentage_max_float,mtlgt3__render_pipe_profile2__cl1_stall__read);

      intel_perf_query_add_counter_float(query, 6491, 64, percentage_max_float,mtlgt3__render_pipe_profile2__hs1_stall__read);

      intel_perf_query_add_counter_float(query, 6492, 68, percentage_max_float,mtlgt3__render_pipe_profile2__ds1_stall__read);

      intel_perf_query_add_counter_float(query, 6493, 72, percentage_max_float,mtlgt3__render_pipe_profile2__sf1_stall__read);

      intel_perf_query_add_counter_float(query, 6494, 76, percentage_max_float,mtlgt3__render_pipe_profile2__so1_stall__read);

      intel_perf_query_add_counter_float(query, 6495, 80, percentage_max_float,mtlgt3__render_pipe_profile2__hi_depth10_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6496, 84, percentage_max_float,mtlgt3__render_pipe_profile2__hi_depth11_bottleneck__read);

      intel_perf_query_add_counter_float(query, 6497, 88, percentage_max_float,mtlgt3__render_pipe_profile2__bc10_bottleneck__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_sampler_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 20);

   query->name = "Sampler_Slice0";
   query->symbol_name = "Sampler";
   query->guid = "ae70a69c-341d-492a-b703-afa08a3497ba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C010013 },
         { .reg = 0x00009888, .val = 0x14032C00 },
         { .reg = 0x00009888, .val = 0x1C210013 },
         { .reg = 0x00009888, .val = 0x14232C00 },
         { .reg = 0x00009888, .val = 0x1C410013 },
         { .reg = 0x00009888, .val = 0x14432C00 },
         { .reg = 0x00009888, .val = 0x1C610013 },
         { .reg = 0x00009888, .val = 0x14632C00 },
         { .reg = 0x00009888, .val = 0x1C810013 },
         { .reg = 0x00009888, .val = 0x14832C00 },
         { .reg = 0x00009888, .val = 0x1CA10013 },
         { .reg = 0x00009888, .val = 0x14A32C00 },
         { .reg = 0x00009888, .val = 0x1CC10013 },
         { .reg = 0x00009888, .val = 0x14C32C00 },
         { .reg = 0x00009888, .val = 0x1CE10013 },
         { .reg = 0x00009888, .val = 0x14E32C00 },
         { .reg = 0x00009888, .val = 0x04012000 },
         { .reg = 0x00009888, .val = 0x06011200 },
         { .reg = 0x00009888, .val = 0x00010100 },
         { .reg = 0x00009888, .val = 0x00020101 },
         { .reg = 0x00009888, .val = 0x08030016 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00080101 },
         { .reg = 0x00009888, .val = 0x04212000 },
         { .reg = 0x00009888, .val = 0x08210024 },
         { .reg = 0x00009888, .val = 0x00210400 },
         { .reg = 0x00009888, .val = 0x00220404 },
         { .reg = 0x00009888, .val = 0x08230580 },
         { .reg = 0x00009888, .val = 0x04230000 },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x00280404 },
         { .reg = 0x00009888, .val = 0x04412000 },
         { .reg = 0x00009888, .val = 0x08410900 },
         { .reg = 0x00009888, .val = 0x00411000 },
         { .reg = 0x00009888, .val = 0x00421010 },
         { .reg = 0x00009888, .val = 0x0A430016 },
         { .reg = 0x00009888, .val = 0x04430000 },
         { .reg = 0x00009888, .val = 0x00430000 },
         { .reg = 0x00009888, .val = 0x00481010 },
         { .reg = 0x00009888, .val = 0x04612000 },
         { .reg = 0x00009888, .val = 0x0A610024 },
         { .reg = 0x00009888, .val = 0x00614000 },
         { .reg = 0x00009888, .val = 0x00624040 },
         { .reg = 0x00009888, .val = 0x0A630580 },
         { .reg = 0x00009888, .val = 0x04630000 },
         { .reg = 0x00009888, .val = 0x00630000 },
         { .reg = 0x00009888, .val = 0x00684040 },
         { .reg = 0x00009888, .val = 0x04812000 },
         { .reg = 0x00009888, .val = 0x16810024 },
         { .reg = 0x00009888, .val = 0x02810040 },
         { .reg = 0x00009888, .val = 0x02824040 },
         { .reg = 0x00009888, .val = 0x0E830580 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x02830000 },
         { .reg = 0x00009888, .val = 0x02884040 },
         { .reg = 0x00009888, .val = 0x04A12000 },
         { .reg = 0x00009888, .val = 0x14A10900 },
         { .reg = 0x00009888, .val = 0x02A10010 },
         { .reg = 0x00009888, .val = 0x02A21010 },
         { .reg = 0x00009888, .val = 0x0EA30016 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x02A30000 },
         { .reg = 0x00009888, .val = 0x02A81010 },
         { .reg = 0x00009888, .val = 0x04C12000 },
         { .reg = 0x00009888, .val = 0x14C10024 },
         { .reg = 0x00009888, .val = 0x02C10004 },
         { .reg = 0x00009888, .val = 0x02C20404 },
         { .reg = 0x00009888, .val = 0x0CC30580 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x02C80404 },
         { .reg = 0x00009888, .val = 0x04E12000 },
         { .reg = 0x00009888, .val = 0x12E10900 },
         { .reg = 0x00009888, .val = 0x02E10001 },
         { .reg = 0x00009888, .val = 0x02E20101 },
         { .reg = 0x00009888, .val = 0x0CE30016 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x02E80101 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00013535 },
         { .reg = 0x00009888, .val = 0x00040505 },
         { .reg = 0x00009888, .val = 0x000B0033 },
         { .reg = 0x00009888, .val = 0x00090E0E },
         { .reg = 0x00009888, .val = 0x000A2A2A },
         { .reg = 0x00009888, .val = 0x02215C5C },
         { .reg = 0x00009888, .val = 0x02245050 },
         { .reg = 0x00009888, .val = 0x002BCC00 },
         { .reg = 0x00009888, .val = 0x0229B0B0 },
         { .reg = 0x00009888, .val = 0x022AA8A8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002EAEA },
         { .reg = 0x00009888, .val = 0x0282ABAB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010800 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009888, .val = 0x58011207 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010A02 },
         { .reg = 0x00009888, .val = 0x5E010070 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010605 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010E00 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010402 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__sampler__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__sampler__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__sampler__avg_gpu_core_frequency__max,mtlgt3__sampler__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__sampler__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5712, 28, percentage_max_float,mtlgt3__sampler__sampler00_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5713, 32, percentage_max_float,mtlgt3__sampler__sampler01_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5714, 36, percentage_max_float,mtlgt3__sampler__sampler02_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5715, 40, percentage_max_float,mtlgt3__sampler__sampler03_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5716, 44, percentage_max_float,mtlgt3__sampler__sampler00_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5717, 48, percentage_max_float,mtlgt3__sampler__sampler01_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5718, 52, percentage_max_float,mtlgt3__sampler__sampler02_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5719, 56, percentage_max_float,mtlgt3__sampler__sampler03_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6498, 60, percentage_max_float,mtlgt3__sampler__sampler10_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6499, 64, percentage_max_float,mtlgt3__sampler__sampler11_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6500, 68, percentage_max_float,mtlgt3__sampler__sampler12_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6501, 72, percentage_max_float,mtlgt3__sampler__sampler13_input_available__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6502, 76, percentage_max_float,mtlgt3__sampler__sampler10_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6503, 80, percentage_max_float,mtlgt3__sampler__sampler11_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6504, 84, percentage_max_float,mtlgt3__sampler__sampler12_output_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6505, 88, percentage_max_float,mtlgt3__sampler__sampler13_output_ready__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_tdl1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "TDL1";
   query->symbol_name = "TDL1";
   query->guid = "cf27081a-d750-4c9d-8a19-154f976992ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C070000 },
         { .reg = 0x00009888, .val = 0x2E070020 },
         { .reg = 0x00009888, .val = 0x2C270000 },
         { .reg = 0x00009888, .val = 0x2E270020 },
         { .reg = 0x00009888, .val = 0x0207020A },
         { .reg = 0x00009888, .val = 0x040708E2 },
         { .reg = 0x00009888, .val = 0x06070821 },
         { .reg = 0x00009888, .val = 0x10070CB3 },
         { .reg = 0x00009888, .val = 0x12070C31 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x0227020A },
         { .reg = 0x00009888, .val = 0x082708E2 },
         { .reg = 0x00009888, .val = 0x0A270821 },
         { .reg = 0x00009888, .val = 0x0C270CB3 },
         { .reg = 0x00009888, .val = 0x0E270C31 },
         { .reg = 0x00009888, .val = 0x04270000 },
         { .reg = 0x00009888, .val = 0x0028AA00 },
         { .reg = 0x00009888, .val = 0x022800AA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00078000 },
         { .reg = 0x0000D954, .val = 0x00000FFF },
         { .reg = 0x0000D958, .val = 0x00000180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00007800 },
         { .reg = 0x0000D96C, .val = 0x0000F0FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__tdl1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__tdl1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__tdl1__avg_gpu_core_frequency__max,mtlgt3__tdl1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__tdl1__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5720, 28, percentage_max_float,mtlgt3__tdl1__non_ps_thread00_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5721, 32, percentage_max_float,mtlgt3__tdl1__ps_thread00_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5722, 36, percentage_max_float,mtlgt3__tdl1__thread_header00_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5723, 40, percentage_max_float,mtlgt3__tdl1__thread_header00_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5724, 44, percentage_max_float,mtlgt3__tdl1__thread_header00_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5725, 48, percentage_max_float,mtlgt3__tdl1__thread_header00_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5726, 52, percentage_max_float,mtlgt3__tdl1__thread_header00_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5727, 56, percentage_max_float,mtlgt3__tdl1__non_ps_thread01_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5728, 60, percentage_max_float,mtlgt3__tdl1__ps_thread01_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5729, 64, percentage_max_float,mtlgt3__tdl1__thread_header01_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5730, 68, percentage_max_float,mtlgt3__tdl1__thread_header01_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5731, 72, percentage_max_float,mtlgt3__tdl1__thread_header01_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5732, 76, percentage_max_float,mtlgt3__tdl1__thread_header01_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5733, 80, percentage_max_float,mtlgt3__tdl1__thread_header01_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_tdl2_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "TDL2";
   query->symbol_name = "TDL2";
   query->guid = "fa292653-8b18-448b-b57e-8e8ff92fac11";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C470000 },
         { .reg = 0x00009888, .val = 0x2E470020 },
         { .reg = 0x00009888, .val = 0x2C670000 },
         { .reg = 0x00009888, .val = 0x2E670020 },
         { .reg = 0x00009888, .val = 0x0247020A },
         { .reg = 0x00009888, .val = 0x044708E2 },
         { .reg = 0x00009888, .val = 0x06470821 },
         { .reg = 0x00009888, .val = 0x10470CB3 },
         { .reg = 0x00009888, .val = 0x12470C31 },
         { .reg = 0x00009888, .val = 0x004800AA },
         { .reg = 0x00009888, .val = 0x0248AA00 },
         { .reg = 0x00009888, .val = 0x0267020A },
         { .reg = 0x00009888, .val = 0x086708E2 },
         { .reg = 0x00009888, .val = 0x0A670821 },
         { .reg = 0x00009888, .val = 0x0C670CB3 },
         { .reg = 0x00009888, .val = 0x0E670C31 },
         { .reg = 0x00009888, .val = 0x04670000 },
         { .reg = 0x00009888, .val = 0x0068AA00 },
         { .reg = 0x00009888, .val = 0x026800AA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x000100FF },
         { .reg = 0x00009888, .val = 0x0201FF00 },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFAA },
         { .reg = 0x00009888, .val = 0x0202AAFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010020 },
         { .reg = 0x00009888, .val = 0x50010002 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00078000 },
         { .reg = 0x0000D954, .val = 0x00000FFF },
         { .reg = 0x0000D958, .val = 0x00000180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00007800 },
         { .reg = 0x0000D96C, .val = 0x0000F0FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__tdl2__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__tdl2__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__tdl2__avg_gpu_core_frequency__max,mtlgt3__tdl2__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__tdl2__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5734, 28, percentage_max_float,mtlgt3__tdl2__non_ps_thread02_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5735, 32, percentage_max_float,mtlgt3__tdl2__ps_thread02_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5736, 36, percentage_max_float,mtlgt3__tdl2__thread_header02_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5737, 40, percentage_max_float,mtlgt3__tdl2__thread_header02_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5738, 44, percentage_max_float,mtlgt3__tdl2__thread_header02_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5739, 48, percentage_max_float,mtlgt3__tdl2__thread_header02_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5740, 52, percentage_max_float,mtlgt3__tdl2__thread_header02_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5741, 56, percentage_max_float,mtlgt3__tdl2__non_ps_thread03_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5742, 60, percentage_max_float,mtlgt3__tdl2__ps_thread03_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5743, 64, percentage_max_float,mtlgt3__tdl2__thread_header03_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5744, 68, percentage_max_float,mtlgt3__tdl2__thread_header03_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5745, 72, percentage_max_float,mtlgt3__tdl2__thread_header03_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5746, 76, percentage_max_float,mtlgt3__tdl2__thread_header03_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5747, 80, percentage_max_float,mtlgt3__tdl2__thread_header03_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_tdl3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "TDL3";
   query->symbol_name = "TDL3";
   query->guid = "9604dfeb-2724-459c-a25b-5e5e06d93fd8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C870000 },
         { .reg = 0x00009888, .val = 0x2E870020 },
         { .reg = 0x00009888, .val = 0x2CA70000 },
         { .reg = 0x00009888, .val = 0x2EA70020 },
         { .reg = 0x00009888, .val = 0x0287020A },
         { .reg = 0x00009888, .val = 0x048708E2 },
         { .reg = 0x00009888, .val = 0x06870821 },
         { .reg = 0x00009888, .val = 0x10870CB3 },
         { .reg = 0x00009888, .val = 0x12870C31 },
         { .reg = 0x00009888, .val = 0x008800AA },
         { .reg = 0x00009888, .val = 0x0288AA00 },
         { .reg = 0x00009888, .val = 0x02A7020A },
         { .reg = 0x00009888, .val = 0x08A708E2 },
         { .reg = 0x00009888, .val = 0x0AA70821 },
         { .reg = 0x00009888, .val = 0x0CA70CB3 },
         { .reg = 0x00009888, .val = 0x0EA70C31 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x00A8AA00 },
         { .reg = 0x00009888, .val = 0x02A800AA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x0229AAFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00078000 },
         { .reg = 0x0000D954, .val = 0x00000FFF },
         { .reg = 0x0000D958, .val = 0x00000180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00007800 },
         { .reg = 0x0000D96C, .val = 0x0000F0FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__tdl3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__tdl3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__tdl3__avg_gpu_core_frequency__max,mtlgt3__tdl3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__tdl3__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6506, 28, percentage_max_float,mtlgt3__tdl3__non_ps_thread10_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6507, 32, percentage_max_float,mtlgt3__tdl3__ps_thread10_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6508, 36, percentage_max_float,mtlgt3__tdl3__thread_header10_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6509, 40, percentage_max_float,mtlgt3__tdl3__thread_header10_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6510, 44, percentage_max_float,mtlgt3__tdl3__thread_header10_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6511, 48, percentage_max_float,mtlgt3__tdl3__thread_header10_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6512, 52, percentage_max_float,mtlgt3__tdl3__thread_header10_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6513, 56, percentage_max_float,mtlgt3__tdl3__non_ps_thread11_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6514, 60, percentage_max_float,mtlgt3__tdl3__ps_thread11_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6515, 64, percentage_max_float,mtlgt3__tdl3__thread_header11_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6516, 68, percentage_max_float,mtlgt3__tdl3__thread_header11_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6517, 72, percentage_max_float,mtlgt3__tdl3__thread_header11_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6518, 76, percentage_max_float,mtlgt3__tdl3__thread_header11_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6519, 80, percentage_max_float,mtlgt3__tdl3__thread_header11_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_tdl4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 18);

   query->name = "TDL4";
   query->symbol_name = "TDL4";
   query->guid = "b5333a47-add0-46a5-82d9-e62dcee14e81";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2CC70000 },
         { .reg = 0x00009888, .val = 0x2EC70020 },
         { .reg = 0x00009888, .val = 0x2CE70000 },
         { .reg = 0x00009888, .val = 0x2EE70020 },
         { .reg = 0x00009888, .val = 0x02C7020A },
         { .reg = 0x00009888, .val = 0x04C708E2 },
         { .reg = 0x00009888, .val = 0x06C70821 },
         { .reg = 0x00009888, .val = 0x10C70CB3 },
         { .reg = 0x00009888, .val = 0x12C70C31 },
         { .reg = 0x00009888, .val = 0x00C800AA },
         { .reg = 0x00009888, .val = 0x02C8AA00 },
         { .reg = 0x00009888, .val = 0x02E7020A },
         { .reg = 0x00009888, .val = 0x08E708E2 },
         { .reg = 0x00009888, .val = 0x0AE70821 },
         { .reg = 0x00009888, .val = 0x0CE70CB3 },
         { .reg = 0x00009888, .val = 0x0EE70C31 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x00E8AA00 },
         { .reg = 0x00009888, .val = 0x02E800AA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x002100FF },
         { .reg = 0x00009888, .val = 0x0221FF00 },
         { .reg = 0x00009888, .val = 0x002A00AA },
         { .reg = 0x00009888, .val = 0x022AAA00 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FFAA },
         { .reg = 0x00009888, .val = 0x0282AAFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010020 },
         { .reg = 0x00009888, .val = 0x50010002 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00078000 },
         { .reg = 0x0000D954, .val = 0x00000FFF },
         { .reg = 0x0000D958, .val = 0x00000180 },
         { .reg = 0x0000D95C, .val = 0x0000FFCF },
         { .reg = 0x0000D960, .val = 0x00000000 },
         { .reg = 0x0000D964, .val = 0x0000FF3F },
         { .reg = 0x0000D968, .val = 0x00007800 },
         { .reg = 0x0000D96C, .val = 0x0000F0FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__tdl4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__tdl4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__tdl4__avg_gpu_core_frequency__max,mtlgt3__tdl4__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 9, 24, percentage_max_float,mtlgt3__tdl4__gpu_busy__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6520, 28, percentage_max_float,mtlgt3__tdl4__non_ps_thread12_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6521, 32, percentage_max_float,mtlgt3__tdl4__ps_thread12_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6522, 36, percentage_max_float,mtlgt3__tdl4__thread_header12_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6523, 40, percentage_max_float,mtlgt3__tdl4__thread_header12_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6524, 44, percentage_max_float,mtlgt3__tdl4__thread_header12_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6525, 48, percentage_max_float,mtlgt3__tdl4__thread_header12_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6526, 52, percentage_max_float,mtlgt3__tdl4__thread_header12_ready_port3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6527, 56, percentage_max_float,mtlgt3__tdl4__non_ps_thread13_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6528, 60, percentage_max_float,mtlgt3__tdl4__ps_thread13_ready_for_dispatch__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6529, 64, percentage_max_float,mtlgt3__tdl4__thread_header13_ready__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6530, 68, percentage_max_float,mtlgt3__tdl4__thread_header13_ready_port0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6531, 72, percentage_max_float,mtlgt3__tdl4__thread_header13_ready_port1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6532, 76, percentage_max_float,mtlgt3__tdl4__thread_header13_ready_port2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6533, 80, percentage_max_float,mtlgt3__tdl4__thread_header13_ready_port3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_test_oa_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Metric set TestOa";
   query->symbol_name = "TestOa";
   query->guid = "7272a7b8-6df2-4180-a95f-2ef7ad4412cc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42020000 },
         { .reg = 0x00009888, .val = 0x46010000 },
         { .reg = 0x00009888, .val = 0x0602000E },
         { .reg = 0x00009888, .val = 0x0E020CC0 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x0801000C },
         { .reg = 0x00009888, .val = 0x12010037 },
         { .reg = 0x00009888, .val = 0x04010000 },
         { .reg = 0x00009888, .val = 0x02010001 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000004 },
         { .reg = 0x0000D944, .val = 0x0000FFFF },
         { .reg = 0x0000D948, .val = 0x00000003 },
         { .reg = 0x0000D94C, .val = 0x0000FFFF },
         { .reg = 0x0000D950, .val = 0x00000007 },
         { .reg = 0x0000D954, .val = 0x0000FFFF },
         { .reg = 0x0000D958, .val = 0x00100002 },
         { .reg = 0x0000D95C, .val = 0x0000FFF7 },
         { .reg = 0x0000D960, .val = 0x00100002 },
         { .reg = 0x0000D964, .val = 0x0000FFCF },
         { .reg = 0x0000D968, .val = 0x00100082 },
         { .reg = 0x0000D96C, .val = 0x0000FFEF },
         { .reg = 0x0000D970, .val = 0x001000C2 },
         { .reg = 0x0000D974, .val = 0x0000FFE7 },
         { .reg = 0x0000D978, .val = 0x00100001 },
         { .reg = 0x0000D97C, .val = 0x0000FFE7 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__test_oa__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__test_oa__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__test_oa__avg_gpu_core_frequency__max,mtlgt3__test_oa__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 315, 24, NULL,mtlgt3__test_oa__counter0__read);

      intel_perf_query_add_counter_uint64(query, 316, 32, NULL,mtlgt3__test_oa__counter1__read);

      intel_perf_query_add_counter_uint64(query, 317, 40, NULL,mtlgt3__test_oa__counter2__read);

      intel_perf_query_add_counter_uint64(query, 318, 48, NULL,mtlgt3__test_oa__counter3__read);

      intel_perf_query_add_counter_uint64(query, 415, 56, NULL,mtlgt3__test_oa__counter4__read);

      intel_perf_query_add_counter_uint64(query, 416, 64, NULL,mtlgt3__test_oa__counter5__read);

      intel_perf_query_add_counter_uint64(query, 417, 72, NULL,mtlgt3__test_oa__counter6__read);

      intel_perf_query_add_counter_uint64(query, 418, 80, NULL,mtlgt3__test_oa__counter7__read);

      intel_perf_query_add_counter_uint64(query, 488, 88, NULL,mtlgt3__test_oa__counter8__read);

      intel_perf_query_add_counter_uint64(query, 489, 96, NULL,mtlgt3__test_oa__counter9__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "Ext1";
   query->symbol_name = "Ext1";
   query->guid = "682c3520-dffc-4a76-8e17-1d9effc01a1a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x15010007 },
         { .reg = 0x00009888, .val = 0x17053400 },
         { .reg = 0x00009888, .val = 0x15210007 },
         { .reg = 0x00009888, .val = 0x17253400 },
         { .reg = 0x00009888, .val = 0x0007BBE0 },
         { .reg = 0x00009888, .val = 0x0207BBAF },
         { .reg = 0x00009888, .val = 0x0001AAA0 },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x03010004 },
         { .reg = 0x00009888, .val = 0x09010180 },
         { .reg = 0x00009888, .val = 0x0B010380 },
         { .reg = 0x00009888, .val = 0x0F010147 },
         { .reg = 0x00009888, .val = 0x110103C0 },
         { .reg = 0x00009888, .val = 0x13010340 },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x03050004 },
         { .reg = 0x00009888, .val = 0x07050080 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x03210004 },
         { .reg = 0x00009888, .val = 0x09210006 },
         { .reg = 0x00009888, .val = 0x0B21000E },
         { .reg = 0x00009888, .val = 0x0D210147 },
         { .reg = 0x00009888, .val = 0x1121000F },
         { .reg = 0x00009888, .val = 0x1321000D },
         { .reg = 0x00009888, .val = 0x01210008 },
         { .reg = 0x00009888, .val = 0x03250004 },
         { .reg = 0x00009888, .val = 0x09250002 },
         { .reg = 0x00009888, .val = 0x01250000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010010 },
         { .reg = 0x00009888, .val = 0x5C010201 },
         { .reg = 0x00009888, .val = 0x5E010010 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010201 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010201 },
         { .reg = 0x00009888, .val = 0x52010010 },
         { .reg = 0x00009888, .val = 0x54010201 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1__avg_gpu_core_frequency__max,mtlgt3__ext1__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 5748, 24, NULL,mtlgt3__ext1__gpu_memory_byte_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 5749, 32, NULL,mtlgt3__ext1__gpu_memory_byte_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 5750, 40, NULL,mtlgt3__ext1__gpu_memory_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 5751, 48, NULL,mtlgt3__ext1__gpu_memory_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 5752, 56, NULL,mtlgt3__ext1__gpu_memory_write__read);

      intel_perf_query_add_counter_uint64(query, 5753, 64, NULL,mtlgt3__ext1__gpu_memory_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 5754, 72, NULL,mtlgt3__ext1__gpu_memory_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 5755, 80, NULL,mtlgt3__ext1__gpu_memory_read__read);

      intel_perf_query_add_counter_uint64(query, 5756, 88, NULL,mtlgt3__ext1__gpu_memory_byte_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 5757, 96, NULL,mtlgt3__ext1__gpu_memory_byte_read_sqidi1__read);

      intel_perf_query_add_counter_float(query, 5758, 104, percentage_max_float,mtlgt3__ext1__gpu_memory_active_sqidi0__read);

      intel_perf_query_add_counter_float(query, 5759, 108, percentage_max_float,mtlgt3__ext1__gpu_memory_active_sqidi1__read);

      intel_perf_query_add_counter_float(query, 5760, 112, NULL,mtlgt3__ext1__gpu_memory_byte_read_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 5761, 116, NULL,mtlgt3__ext1__gpu_memory_byte_read_bw_sqidi1__read);

      intel_perf_query_add_counter_float(query, 5762, 120, NULL,mtlgt3__ext1__gpu_memory_byte_write_bw_sqidi0__read);

      intel_perf_query_add_counter_float(query, 5763, 124, NULL,mtlgt3__ext1__gpu_memory_byte_write_bw_sqidi1__read);

      intel_perf_query_add_counter_float(query, 6534, 128, percentage_max_float,mtlgt3__ext1__gpu_memory_request_queue_full_sqidi0__read);

      intel_perf_query_add_counter_float(query, 6535, 132, percentage_max_float,mtlgt3__ext1__gpu_memory_request_queue_full_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext3_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext3";
   query->symbol_name = "Ext3";
   query->guid = "b24b7052-70a1-4ef7-b61d-7ee4d7e159ab";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x17050000 },
         { .reg = 0x00009888, .val = 0x17250000 },
         { .reg = 0x00009888, .val = 0x0207EEEE },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x01015500 },
         { .reg = 0x00009888, .val = 0x03050004 },
         { .reg = 0x00009888, .val = 0x0D050140 },
         { .reg = 0x00009888, .val = 0x0F0501C0 },
         { .reg = 0x00009888, .val = 0x11050100 },
         { .reg = 0x00009888, .val = 0x13050180 },
         { .reg = 0x00009888, .val = 0x01050000 },
         { .reg = 0x00009888, .val = 0x0121AA00 },
         { .reg = 0x00009888, .val = 0x03250004 },
         { .reg = 0x00009888, .val = 0x0F250005 },
         { .reg = 0x00009888, .val = 0x11250007 },
         { .reg = 0x00009888, .val = 0x13250004 },
         { .reg = 0x00009888, .val = 0x15250006 },
         { .reg = 0x00009888, .val = 0x01250000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext3__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext3__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext3__avg_gpu_core_frequency__max,mtlgt3__ext3__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6536, 24, NULL,mtlgt3__ext3__gpu_memory_32_b_transaction_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 6537, 32, NULL,mtlgt3__ext3__gpu_memory_32_b_transaction_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 6538, 40, NULL,mtlgt3__ext3__gpu_memory_64_b_transaction_read_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 6539, 48, NULL,mtlgt3__ext3__gpu_memory_64_b_transaction_read_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 6540, 56, NULL,mtlgt3__ext3__gpu_memory_32_b_transaction_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 6541, 64, NULL,mtlgt3__ext3__gpu_memory_32_b_transaction_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 6542, 72, NULL,mtlgt3__ext3__gpu_memory_64_b_transaction_write_sqidi0__read);

      intel_perf_query_add_counter_uint64(query, 6543, 80, NULL,mtlgt3__ext3__gpu_memory_64_b_transaction_write_sqidi1__read);

      intel_perf_query_add_counter_uint64(query, 6544, 88, NULL,mtlgt3__ext3__gpu_memory_32_b_transaction_read__read);

      intel_perf_query_add_counter_uint64(query, 6545, 96, NULL,mtlgt3__ext3__gpu_memory_64_b_transaction_read__read);

      intel_perf_query_add_counter_uint64(query, 6546, 104, NULL,mtlgt3__ext3__gpu_memory_32_b_transaction_write__read);

      intel_perf_query_add_counter_uint64(query, 6547, 112, NULL,mtlgt3__ext3__gpu_memory_64_b_transaction_write__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext4_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext4";
   query->symbol_name = "Ext4";
   query->guid = "205ab9ab-56fd-4fdc-b3b3-91dc57be0fd3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03012000 },
         { .reg = 0x00009888, .val = 0x05016005 },
         { .reg = 0x00009888, .val = 0x03212000 },
         { .reg = 0x00009888, .val = 0x05216140 },
         { .reg = 0x00009888, .val = 0x03412000 },
         { .reg = 0x00009888, .val = 0x05416000 },
         { .reg = 0x00009888, .val = 0x03612000 },
         { .reg = 0x00009888, .val = 0x05616000 },
         { .reg = 0x00009888, .val = 0x03812000 },
         { .reg = 0x00009888, .val = 0x05816000 },
         { .reg = 0x00009888, .val = 0x03A12000 },
         { .reg = 0x00009888, .val = 0x05A16000 },
         { .reg = 0x00009888, .val = 0x03C12000 },
         { .reg = 0x00009888, .val = 0x05C16000 },
         { .reg = 0x00009888, .val = 0x03E12000 },
         { .reg = 0x00009888, .val = 0x05E16000 },
         { .reg = 0x00009888, .val = 0x00020055 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00825500 },
         { .reg = 0x00009888, .val = 0x02820055 },
         { .reg = 0x00009888, .val = 0x01010010 },
         { .reg = 0x00009888, .val = 0x13010340 },
         { .reg = 0x00009888, .val = 0x01210010 },
         { .reg = 0x00009888, .val = 0x1321000D },
         { .reg = 0x00009888, .val = 0x01410010 },
         { .reg = 0x00009888, .val = 0x07410005 },
         { .reg = 0x00009888, .val = 0x11410340 },
         { .reg = 0x00009888, .val = 0x01610010 },
         { .reg = 0x00009888, .val = 0x07610140 },
         { .reg = 0x00009888, .val = 0x1161000D },
         { .reg = 0x00009888, .val = 0x00010B1A },
         { .reg = 0x00009888, .val = 0x04013940 },
         { .reg = 0x00009888, .val = 0x06010002 },
         { .reg = 0x00009888, .val = 0x01810010 },
         { .reg = 0x00009888, .val = 0x0B810140 },
         { .reg = 0x00009888, .val = 0x0F810340 },
         { .reg = 0x00009888, .val = 0x01A10010 },
         { .reg = 0x00009888, .val = 0x0BA10005 },
         { .reg = 0x00009888, .val = 0x0FA1000D },
         { .reg = 0x00009888, .val = 0x01C10010 },
         { .reg = 0x00009888, .val = 0x09C10140 },
         { .reg = 0x00009888, .val = 0x0DC10340 },
         { .reg = 0x00009888, .val = 0x01E10010 },
         { .reg = 0x00009888, .val = 0x09E10005 },
         { .reg = 0x00009888, .val = 0x0DE1000D },
         { .reg = 0x00009888, .val = 0x00815000 },
         { .reg = 0x00009888, .val = 0x02814A9C },
         { .reg = 0x00009888, .val = 0x04810013 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050FF0 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x000355AA },
         { .reg = 0x00009888, .val = 0x0203AA55 },
         { .reg = 0x00009888, .val = 0x00040FF0 },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009888, .val = 0x58010604 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010202 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010400 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010602 },
         { .reg = 0x00009888, .val = 0x52010040 },
         { .reg = 0x00009888, .val = 0x54010404 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext4__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext4__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext4__avg_gpu_core_frequency__max,mtlgt3__ext4__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5764, 24, NULL,mtlgt3__ext4__l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5765, 32, NULL,mtlgt3__ext4__l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5766, 40, NULL,mtlgt3__ext4__l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5767, 48, NULL,mtlgt3__ext4__l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6548, 56, NULL,mtlgt3__ext4__l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6549, 64, NULL,mtlgt3__ext4__l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6550, 72, NULL,mtlgt3__ext4__l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6551, 80, NULL,mtlgt3__ext4__l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5768, 88, NULL,mtlgt3__ext4__l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5769, 96, NULL,mtlgt3__ext4__l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5770, 104, NULL,mtlgt3__ext4__l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5771, 112, NULL,mtlgt3__ext4__l3_write_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6552, 120, NULL,mtlgt3__ext4__l3_write_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6553, 128, NULL,mtlgt3__ext4__l3_write_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6554, 136, NULL,mtlgt3__ext4__l3_write_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6555, 144, NULL,mtlgt3__ext4__l3_write_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext5_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext5";
   query->symbol_name = "Ext5";
   query->guid = "26cb7ee1-a26d-410a-9283-e07d6ced5fce";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x03210000 },
         { .reg = 0x00009888, .val = 0x03410000 },
         { .reg = 0x00009888, .val = 0x03610000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00820055 },
         { .reg = 0x00009888, .val = 0x02820055 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x0B0100C0 },
         { .reg = 0x00009888, .val = 0x13010100 },
         { .reg = 0x00009888, .val = 0x01210000 },
         { .reg = 0x00009888, .val = 0x0B210003 },
         { .reg = 0x00009888, .val = 0x13210004 },
         { .reg = 0x00009888, .val = 0x01410000 },
         { .reg = 0x00009888, .val = 0x094100C0 },
         { .reg = 0x00009888, .val = 0x11410100 },
         { .reg = 0x00009888, .val = 0x01610000 },
         { .reg = 0x00009888, .val = 0x09610003 },
         { .reg = 0x00009888, .val = 0x11610004 },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x0201009C },
         { .reg = 0x00009888, .val = 0x04013940 },
         { .reg = 0x00009888, .val = 0x06010002 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x078100C0 },
         { .reg = 0x00009888, .val = 0x0F810100 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x07A10003 },
         { .reg = 0x00009888, .val = 0x0FA10004 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x05C100C0 },
         { .reg = 0x00009888, .val = 0x0DC10100 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x05E10003 },
         { .reg = 0x00009888, .val = 0x0DE10004 },
         { .reg = 0x00009888, .val = 0x008104E5 },
         { .reg = 0x00009888, .val = 0x02814A00 },
         { .reg = 0x00009888, .val = 0x04810013 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050F0F },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AA55 },
         { .reg = 0x00009888, .val = 0x0203AA55 },
         { .reg = 0x00009888, .val = 0x00040F0F },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010401 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010400 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010602 },
         { .reg = 0x00009888, .val = 0x52010040 },
         { .reg = 0x00009888, .val = 0x54010404 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext5__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext5__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext5__avg_gpu_core_frequency__max,mtlgt3__ext5__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5772, 24, NULL,mtlgt3__ext5__dataport_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5773, 32, NULL,mtlgt3__ext5__dataport_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5774, 40, NULL,mtlgt3__ext5__dataport_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5775, 48, NULL,mtlgt3__ext5__dataport_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6556, 56, NULL,mtlgt3__ext5__dataport_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6557, 64, NULL,mtlgt3__ext5__dataport_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6558, 72, NULL,mtlgt3__ext5__dataport_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6559, 80, NULL,mtlgt3__ext5__dataport_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5776, 88, NULL,mtlgt3__ext5__dataport_l3_write_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5777, 96, NULL,mtlgt3__ext5__dataport_l3_write_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5778, 104, NULL,mtlgt3__ext5__dataport_l3_write_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5779, 112, NULL,mtlgt3__ext5__dataport_l3_write_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6560, 120, NULL,mtlgt3__ext5__dataport_l3_write_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6561, 128, NULL,mtlgt3__ext5__dataport_l3_write_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6562, 136, NULL,mtlgt3__ext5__dataport_l3_write_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6563, 144, NULL,mtlgt3__ext5__dataport_l3_write_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext6_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext6";
   query->symbol_name = "Ext6";
   query->guid = "e62c9cd7-ada7-487d-87aa-b1ad4ab9a2c5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x18230004 },
         { .reg = 0x00009888, .val = 0x18430004 },
         { .reg = 0x00009888, .val = 0x18630004 },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x00014000 },
         { .reg = 0x00009888, .val = 0x00024000 },
         { .reg = 0x00009888, .val = 0x0A030D00 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00084000 },
         { .reg = 0x00009888, .val = 0x00211000 },
         { .reg = 0x00009888, .val = 0x00221000 },
         { .reg = 0x00009888, .val = 0x0A230034 },
         { .reg = 0x00009888, .val = 0x04230000 },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x00281000 },
         { .reg = 0x00009888, .val = 0x00410400 },
         { .reg = 0x00009888, .val = 0x00420400 },
         { .reg = 0x00009888, .val = 0x08430D00 },
         { .reg = 0x00009888, .val = 0x04430000 },
         { .reg = 0x00009888, .val = 0x00430000 },
         { .reg = 0x00009888, .val = 0x00480400 },
         { .reg = 0x00009888, .val = 0x00610100 },
         { .reg = 0x00009888, .val = 0x00620100 },
         { .reg = 0x00009888, .val = 0x08630034 },
         { .reg = 0x00009888, .val = 0x04630000 },
         { .reg = 0x00009888, .val = 0x00630000 },
         { .reg = 0x00009888, .val = 0x00680100 },
         { .reg = 0x00009888, .val = 0x00810040 },
         { .reg = 0x00009888, .val = 0x00820040 },
         { .reg = 0x00009888, .val = 0x06830D00 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00880040 },
         { .reg = 0x00009888, .val = 0x00A10010 },
         { .reg = 0x00009888, .val = 0x00A20010 },
         { .reg = 0x00009888, .val = 0x06A30034 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A80010 },
         { .reg = 0x00009888, .val = 0x00C10004 },
         { .reg = 0x00009888, .val = 0x00C20004 },
         { .reg = 0x00009888, .val = 0x04C30D00 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C80004 },
         { .reg = 0x00009888, .val = 0x00E10001 },
         { .reg = 0x00009888, .val = 0x00E20001 },
         { .reg = 0x00009888, .val = 0x04E30034 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E80001 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0B012000 },
         { .reg = 0x00009888, .val = 0x0B212000 },
         { .reg = 0x00009888, .val = 0x0B412000 },
         { .reg = 0x00009888, .val = 0x0B612000 },
         { .reg = 0x00009888, .val = 0x0B812000 },
         { .reg = 0x00009888, .val = 0x0BA12000 },
         { .reg = 0x00009888, .val = 0x0BC12000 },
         { .reg = 0x00009888, .val = 0x0BE12000 },
         { .reg = 0x00009888, .val = 0x0002AB00 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x008200AB },
         { .reg = 0x00009888, .val = 0x02820055 },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x13010040 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x01210004 },
         { .reg = 0x00009888, .val = 0x13210001 },
         { .reg = 0x00009888, .val = 0x03210000 },
         { .reg = 0x00009888, .val = 0x01410004 },
         { .reg = 0x00009888, .val = 0x11410040 },
         { .reg = 0x00009888, .val = 0x03410000 },
         { .reg = 0x00009888, .val = 0x01610004 },
         { .reg = 0x00009888, .val = 0x11610001 },
         { .reg = 0x00009888, .val = 0x03610000 },
         { .reg = 0x00009888, .val = 0x04013940 },
         { .reg = 0x00009888, .val = 0x06010002 },
         { .reg = 0x00009888, .val = 0x01810004 },
         { .reg = 0x00009888, .val = 0x0F810040 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01A10004 },
         { .reg = 0x00009888, .val = 0x0FA10001 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01C10004 },
         { .reg = 0x00009888, .val = 0x0DC10040 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01E10004 },
         { .reg = 0x00009888, .val = 0x0DE10001 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x02814A00 },
         { .reg = 0x00009888, .val = 0x04810013 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015C00 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x000B00C0 },
         { .reg = 0x00009888, .val = 0x0009B000 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x0021005C },
         { .reg = 0x00009888, .val = 0x00240050 },
         { .reg = 0x00009888, .val = 0x002B000C },
         { .reg = 0x00009888, .val = 0x002900B0 },
         { .reg = 0x00009888, .val = 0x002A00A8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050F0F },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AA55 },
         { .reg = 0x00009888, .val = 0x0203AA55 },
         { .reg = 0x00009888, .val = 0x00040F0F },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010070 },
         { .reg = 0x00009888, .val = 0x5C010405 },
         { .reg = 0x00009888, .val = 0x5E010220 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010420 },
         { .reg = 0x00009888, .val = 0x4E010211 },
         { .reg = 0x00009888, .val = 0x50010622 },
         { .reg = 0x00009888, .val = 0x52010241 },
         { .reg = 0x00009888, .val = 0x54010424 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext6__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext6__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext6__avg_gpu_core_frequency__max,mtlgt3__ext6__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5780, 24, NULL,mtlgt3__ext6__l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5781, 32, NULL,mtlgt3__ext6__l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5782, 40, NULL,mtlgt3__ext6__l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5783, 48, NULL,mtlgt3__ext6__l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6564, 56, NULL,mtlgt3__ext6__l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6565, 64, NULL,mtlgt3__ext6__l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6566, 72, NULL,mtlgt3__ext6__l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6567, 80, NULL,mtlgt3__ext6__l3_hit_l3_bank7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5792, 88, percentage_max_float,mtlgt3__ext6__sampler_busy_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5793, 92, percentage_max_float,mtlgt3__ext6__sampler_busy_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5794, 96, percentage_max_float,mtlgt3__ext6__sampler_busy_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5795, 100, percentage_max_float,mtlgt3__ext6__sampler_busy_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6568, 104, percentage_max_float,mtlgt3__ext6__sampler_busy_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6569, 108, percentage_max_float,mtlgt3__ext6__sampler_busy_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6570, 112, percentage_max_float,mtlgt3__ext6__sampler_busy_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6571, 116, percentage_max_float,mtlgt3__ext6__sampler_busy_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext7_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext7";
   query->symbol_name = "Ext7";
   query->guid = "714e9d80-e4e3-40e6-9e79-2ca6d1d0a5a5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x0B010040 },
         { .reg = 0x00009888, .val = 0x03210000 },
         { .reg = 0x00009888, .val = 0x0B210001 },
         { .reg = 0x00009888, .val = 0x03410000 },
         { .reg = 0x00009888, .val = 0x0B410000 },
         { .reg = 0x00009888, .val = 0x03610000 },
         { .reg = 0x00009888, .val = 0x0B610000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0B810000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x0BA10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x0BC10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x0BE10000 },
         { .reg = 0x00009888, .val = 0x00025500 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x00820055 },
         { .reg = 0x00009888, .val = 0x02820055 },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x13010380 },
         { .reg = 0x00009888, .val = 0x01210004 },
         { .reg = 0x00009888, .val = 0x1321000E },
         { .reg = 0x00009888, .val = 0x01410004 },
         { .reg = 0x00009888, .val = 0x09410040 },
         { .reg = 0x00009888, .val = 0x11410380 },
         { .reg = 0x00009888, .val = 0x01610004 },
         { .reg = 0x00009888, .val = 0x09610001 },
         { .reg = 0x00009888, .val = 0x1161000E },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x0201009C },
         { .reg = 0x00009888, .val = 0x04013940 },
         { .reg = 0x00009888, .val = 0x06010002 },
         { .reg = 0x00009888, .val = 0x01810004 },
         { .reg = 0x00009888, .val = 0x07810040 },
         { .reg = 0x00009888, .val = 0x0F810380 },
         { .reg = 0x00009888, .val = 0x01A10004 },
         { .reg = 0x00009888, .val = 0x07A10001 },
         { .reg = 0x00009888, .val = 0x0FA1000E },
         { .reg = 0x00009888, .val = 0x01C10004 },
         { .reg = 0x00009888, .val = 0x05C10040 },
         { .reg = 0x00009888, .val = 0x0DC10380 },
         { .reg = 0x00009888, .val = 0x01E10004 },
         { .reg = 0x00009888, .val = 0x05E10001 },
         { .reg = 0x00009888, .val = 0x0DE1000E },
         { .reg = 0x00009888, .val = 0x008104E5 },
         { .reg = 0x00009888, .val = 0x02814A00 },
         { .reg = 0x00009888, .val = 0x04810013 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050F0F },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AA55 },
         { .reg = 0x00009888, .val = 0x0203AA55 },
         { .reg = 0x00009888, .val = 0x00040F0F },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010401 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010400 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010602 },
         { .reg = 0x00009888, .val = 0x52010040 },
         { .reg = 0x00009888, .val = 0x54010404 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext7__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext7__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext7__avg_gpu_core_frequency__max,mtlgt3__ext7__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5784, 24, NULL,mtlgt3__ext7__sampler_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5785, 32, NULL,mtlgt3__ext7__sampler_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5786, 40, NULL,mtlgt3__ext7__sampler_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5787, 48, NULL,mtlgt3__ext7__sampler_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6572, 56, NULL,mtlgt3__ext7__sampler_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6573, 64, NULL,mtlgt3__ext7__sampler_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6574, 72, NULL,mtlgt3__ext7__sampler_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6575, 80, NULL,mtlgt3__ext7__sampler_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5788, 88, NULL,mtlgt3__ext7__sampler_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5789, 96, NULL,mtlgt3__ext7__sampler_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5790, 104, NULL,mtlgt3__ext7__sampler_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5791, 112, NULL,mtlgt3__ext7__sampler_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6576, 120, NULL,mtlgt3__ext7__sampler_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6577, 128, NULL,mtlgt3__ext7__sampler_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6578, 136, NULL,mtlgt3__ext7__sampler_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6579, 144, NULL,mtlgt3__ext7__sampler_l3_hit_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext8_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext8";
   query->symbol_name = "Ext8";
   query->guid = "30499dfb-3977-4808-a34c-93e7b50e0454";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x0B010280 },
         { .reg = 0x00009888, .val = 0x03210000 },
         { .reg = 0x00009888, .val = 0x0B21000A },
         { .reg = 0x00009888, .val = 0x03410000 },
         { .reg = 0x00009888, .val = 0x0B410000 },
         { .reg = 0x00009888, .val = 0x03610000 },
         { .reg = 0x00009888, .val = 0x0B610000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x0B810000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x0BA10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x0BC10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x0BE10000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02825555 },
         { .reg = 0x00009888, .val = 0x01010040 },
         { .reg = 0x00009888, .val = 0x070101C0 },
         { .reg = 0x00009888, .val = 0x01210040 },
         { .reg = 0x00009888, .val = 0x07210007 },
         { .reg = 0x00009888, .val = 0x01410040 },
         { .reg = 0x00009888, .val = 0x054101C0 },
         { .reg = 0x00009888, .val = 0x09410280 },
         { .reg = 0x00009888, .val = 0x01610040 },
         { .reg = 0x00009888, .val = 0x05610007 },
         { .reg = 0x00009888, .val = 0x0961000A },
         { .reg = 0x00009888, .val = 0x000154E5 },
         { .reg = 0x00009888, .val = 0x0201009C },
         { .reg = 0x00009888, .val = 0x01810004 },
         { .reg = 0x00009888, .val = 0x0F810080 },
         { .reg = 0x00009888, .val = 0x138103C0 },
         { .reg = 0x00009888, .val = 0x01A10004 },
         { .reg = 0x00009888, .val = 0x0FA10002 },
         { .reg = 0x00009888, .val = 0x13A1000F },
         { .reg = 0x00009888, .val = 0x01C10004 },
         { .reg = 0x00009888, .val = 0x0DC10080 },
         { .reg = 0x00009888, .val = 0x11C103C0 },
         { .reg = 0x00009888, .val = 0x01E10004 },
         { .reg = 0x00009888, .val = 0x0DE10002 },
         { .reg = 0x00009888, .val = 0x11E1000F },
         { .reg = 0x00009888, .val = 0x02814A00 },
         { .reg = 0x00009888, .val = 0x04813953 },
         { .reg = 0x00009888, .val = 0x06810002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010600 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009888, .val = 0x58010404 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010400 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010002 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010401 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext8__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext8__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext8__avg_gpu_core_frequency__max,mtlgt3__ext8__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5796, 24, NULL,mtlgt3__ext8__icache_l3_read_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5797, 32, NULL,mtlgt3__ext8__icache_l3_read_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5798, 40, NULL,mtlgt3__ext8__icache_l3_read_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5799, 48, NULL,mtlgt3__ext8__icache_l3_read_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6580, 56, NULL,mtlgt3__ext8__icache_l3_read_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6581, 64, NULL,mtlgt3__ext8__icache_l3_read_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6582, 72, NULL,mtlgt3__ext8__icache_l3_read_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6583, 80, NULL,mtlgt3__ext8__icache_l3_read_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5800, 88, NULL,mtlgt3__ext8__icache_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5801, 96, NULL,mtlgt3__ext8__icache_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5802, 104, NULL,mtlgt3__ext8__icache_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5803, 112, NULL,mtlgt3__ext8__icache_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6584, 120, NULL,mtlgt3__ext8__icache_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6585, 128, NULL,mtlgt3__ext8__icache_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6586, 136, NULL,mtlgt3__ext8__icache_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6587, 144, NULL,mtlgt3__ext8__icache_l3_hit_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext9_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext9";
   query->symbol_name = "Ext9";
   query->guid = "417618f2-7a87-4745-bccd-6ba14d17bfa4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03014000 },
         { .reg = 0x00009888, .val = 0x03214000 },
         { .reg = 0x00009888, .val = 0x03414000 },
         { .reg = 0x00009888, .val = 0x03614000 },
         { .reg = 0x00009888, .val = 0x03814000 },
         { .reg = 0x00009888, .val = 0x03A14000 },
         { .reg = 0x00009888, .val = 0x03C14000 },
         { .reg = 0x00009888, .val = 0x03E14000 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02825500 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x0F0101C0 },
         { .reg = 0x00009888, .val = 0x01210000 },
         { .reg = 0x00009888, .val = 0x0F210007 },
         { .reg = 0x00009888, .val = 0x01410000 },
         { .reg = 0x00009888, .val = 0x0D4101C0 },
         { .reg = 0x00009888, .val = 0x01610000 },
         { .reg = 0x00009888, .val = 0x0D610007 },
         { .reg = 0x00009888, .val = 0x02014A00 },
         { .reg = 0x00009888, .val = 0x04010013 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x138101C0 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x13A10007 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x11C101C0 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x11E10007 },
         { .reg = 0x00009888, .val = 0x04813940 },
         { .reg = 0x00009888, .val = 0x06810002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x020355AA },
         { .reg = 0x00009888, .val = 0x0004F000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010803 },
         { .reg = 0x00009888, .val = 0x4E010040 },
         { .reg = 0x00009888, .val = 0x50010002 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010401 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext9__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext9__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext9__avg_gpu_core_frequency__max,mtlgt3__ext9__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5812, 24, NULL,mtlgt3__ext9__z_l3_access_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5813, 32, NULL,mtlgt3__ext9__z_l3_access_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5814, 40, NULL,mtlgt3__ext9__z_l3_access_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5815, 48, NULL,mtlgt3__ext9__z_l3_access_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6588, 56, NULL,mtlgt3__ext9__z_l3_access_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6589, 64, NULL,mtlgt3__ext9__z_l3_access_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6590, 72, NULL,mtlgt3__ext9__z_l3_access_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6591, 80, NULL,mtlgt3__ext9__z_l3_access_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext10_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext10";
   query->symbol_name = "Ext10";
   query->guid = "443c32c7-e5e4-43da-b4f2-77efe45a60ed";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0B010000 },
         { .reg = 0x00009888, .val = 0x0B210000 },
         { .reg = 0x00009888, .val = 0x0B410000 },
         { .reg = 0x00009888, .val = 0x0B610000 },
         { .reg = 0x00009888, .val = 0x0B810000 },
         { .reg = 0x00009888, .val = 0x0BA10000 },
         { .reg = 0x00009888, .val = 0x0BC10000 },
         { .reg = 0x00009888, .val = 0x0BE10000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02825555 },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x05010004 },
         { .reg = 0x00009888, .val = 0x09010000 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x01210004 },
         { .reg = 0x00009888, .val = 0x05210100 },
         { .reg = 0x00009888, .val = 0x09210000 },
         { .reg = 0x00009888, .val = 0x03210000 },
         { .reg = 0x00009888, .val = 0x01410004 },
         { .reg = 0x00009888, .val = 0x07410004 },
         { .reg = 0x00009888, .val = 0x03410000 },
         { .reg = 0x00009888, .val = 0x01610004 },
         { .reg = 0x00009888, .val = 0x07610100 },
         { .reg = 0x00009888, .val = 0x03610000 },
         { .reg = 0x00009888, .val = 0x00012B1A },
         { .reg = 0x00009888, .val = 0x02010163 },
         { .reg = 0x00009888, .val = 0x01810004 },
         { .reg = 0x00009888, .val = 0x0F810100 },
         { .reg = 0x00009888, .val = 0x13810000 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01A10004 },
         { .reg = 0x00009888, .val = 0x0FA10004 },
         { .reg = 0x00009888, .val = 0x13A10000 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01C10004 },
         { .reg = 0x00009888, .val = 0x0DC10100 },
         { .reg = 0x00009888, .val = 0x11C10000 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01E10004 },
         { .reg = 0x00009888, .val = 0x0DE10004 },
         { .reg = 0x00009888, .val = 0x11E10000 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x02814A00 },
         { .reg = 0x00009888, .val = 0x04813953 },
         { .reg = 0x00009888, .val = 0x06810002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009888, .val = 0x58010604 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010400 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010002 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010401 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext10__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext10__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext10__avg_gpu_core_frequency__max,mtlgt3__ext10__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5804, 24, NULL,mtlgt3__ext10__dataport_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5805, 32, NULL,mtlgt3__ext10__dataport_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5806, 40, NULL,mtlgt3__ext10__dataport_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5807, 48, NULL,mtlgt3__ext10__dataport_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6592, 56, NULL,mtlgt3__ext10__dataport_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6593, 64, NULL,mtlgt3__ext10__dataport_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6594, 72, NULL,mtlgt3__ext10__dataport_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6595, 80, NULL,mtlgt3__ext10__dataport_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5808, 88, NULL,mtlgt3__ext10__color_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5809, 96, NULL,mtlgt3__ext10__color_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5810, 104, NULL,mtlgt3__ext10__color_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5811, 112, NULL,mtlgt3__ext10__color_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6596, 120, NULL,mtlgt3__ext10__color_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6597, 128, NULL,mtlgt3__ext10__color_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6598, 136, NULL,mtlgt3__ext10__color_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6599, 144, NULL,mtlgt3__ext10__color_l3_hit_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext11_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext11";
   query->symbol_name = "Ext11";
   query->guid = "3833e442-880a-4746-9df1-6347b7e5a081";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03012000 },
         { .reg = 0x00009888, .val = 0x0B010300 },
         { .reg = 0x00009888, .val = 0x03212000 },
         { .reg = 0x00009888, .val = 0x0B21000C },
         { .reg = 0x00009888, .val = 0x03412000 },
         { .reg = 0x00009888, .val = 0x0B410000 },
         { .reg = 0x00009888, .val = 0x03612000 },
         { .reg = 0x00009888, .val = 0x0B610000 },
         { .reg = 0x00009888, .val = 0x03812000 },
         { .reg = 0x00009888, .val = 0x0B810000 },
         { .reg = 0x00009888, .val = 0x03A12000 },
         { .reg = 0x00009888, .val = 0x0BA10000 },
         { .reg = 0x00009888, .val = 0x03C12000 },
         { .reg = 0x00009888, .val = 0x0BC10000 },
         { .reg = 0x00009888, .val = 0x03E12000 },
         { .reg = 0x00009888, .val = 0x0BE10000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02825555 },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x07010140 },
         { .reg = 0x00009888, .val = 0x01210004 },
         { .reg = 0x00009888, .val = 0x07210005 },
         { .reg = 0x00009888, .val = 0x01410004 },
         { .reg = 0x00009888, .val = 0x05410140 },
         { .reg = 0x00009888, .val = 0x09410300 },
         { .reg = 0x00009888, .val = 0x01610004 },
         { .reg = 0x00009888, .val = 0x05610005 },
         { .reg = 0x00009888, .val = 0x0961000C },
         { .reg = 0x00009888, .val = 0x000154E5 },
         { .reg = 0x00009888, .val = 0x0201009C },
         { .reg = 0x00009888, .val = 0x01810040 },
         { .reg = 0x00009888, .val = 0x0F810100 },
         { .reg = 0x00009888, .val = 0x13810340 },
         { .reg = 0x00009888, .val = 0x01A10040 },
         { .reg = 0x00009888, .val = 0x0FA10004 },
         { .reg = 0x00009888, .val = 0x13A1000D },
         { .reg = 0x00009888, .val = 0x01C10040 },
         { .reg = 0x00009888, .val = 0x0DC10100 },
         { .reg = 0x00009888, .val = 0x11C10340 },
         { .reg = 0x00009888, .val = 0x01E10040 },
         { .reg = 0x00009888, .val = 0x0DE10004 },
         { .reg = 0x00009888, .val = 0x11E1000D },
         { .reg = 0x00009888, .val = 0x02814A00 },
         { .reg = 0x00009888, .val = 0x04813953 },
         { .reg = 0x00009888, .val = 0x06810002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010600 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009888, .val = 0x58010404 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010400 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010002 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010401 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext11__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext11__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext11__avg_gpu_core_frequency__max,mtlgt3__ext11__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5816, 24, NULL,mtlgt3__ext11__z_l3_hit_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5817, 32, NULL,mtlgt3__ext11__z_l3_hit_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5818, 40, NULL,mtlgt3__ext11__z_l3_hit_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5819, 48, NULL,mtlgt3__ext11__z_l3_hit_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6600, 56, NULL,mtlgt3__ext11__z_l3_hit_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6601, 64, NULL,mtlgt3__ext11__z_l3_hit_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6602, 72, NULL,mtlgt3__ext11__z_l3_hit_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6603, 80, NULL,mtlgt3__ext11__z_l3_hit_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5820, 88, NULL,mtlgt3__ext11__l3_atomic_access_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5821, 96, NULL,mtlgt3__ext11__l3_atomic_access_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5822, 104, NULL,mtlgt3__ext11__l3_atomic_access_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5823, 112, NULL,mtlgt3__ext11__l3_atomic_access_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6604, 120, NULL,mtlgt3__ext11__l3_atomic_access_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6605, 128, NULL,mtlgt3__ext11__l3_atomic_access_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6606, 136, NULL,mtlgt3__ext11__l3_atomic_access_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6607, 144, NULL,mtlgt3__ext11__l3_atomic_access_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext12_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext12";
   query->symbol_name = "Ext12";
   query->guid = "931bb082-6f87-450e-8910-fd6a4ab206f7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03012000 },
         { .reg = 0x00009888, .val = 0x03212000 },
         { .reg = 0x00009888, .val = 0x03412000 },
         { .reg = 0x00009888, .val = 0x03612000 },
         { .reg = 0x00009888, .val = 0x03812000 },
         { .reg = 0x00009888, .val = 0x03A12000 },
         { .reg = 0x00009888, .val = 0x03C12000 },
         { .reg = 0x00009888, .val = 0x03E12000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02825555 },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x05010007 },
         { .reg = 0x00009888, .val = 0x09010006 },
         { .reg = 0x00009888, .val = 0x01210000 },
         { .reg = 0x00009888, .val = 0x052101C0 },
         { .reg = 0x00009888, .val = 0x09210180 },
         { .reg = 0x00009888, .val = 0x01410000 },
         { .reg = 0x00009888, .val = 0x07410007 },
         { .reg = 0x00009888, .val = 0x0B410006 },
         { .reg = 0x00009888, .val = 0x01610000 },
         { .reg = 0x00009888, .val = 0x076101C0 },
         { .reg = 0x00009888, .val = 0x0B610180 },
         { .reg = 0x00009888, .val = 0x00012B1A },
         { .reg = 0x00009888, .val = 0x02010163 },
         { .reg = 0x00009888, .val = 0x01810000 },
         { .reg = 0x00009888, .val = 0x0F810180 },
         { .reg = 0x00009888, .val = 0x138101C0 },
         { .reg = 0x00009888, .val = 0x01A10000 },
         { .reg = 0x00009888, .val = 0x0FA10006 },
         { .reg = 0x00009888, .val = 0x13A10007 },
         { .reg = 0x00009888, .val = 0x01C10000 },
         { .reg = 0x00009888, .val = 0x0DC10180 },
         { .reg = 0x00009888, .val = 0x11C101C0 },
         { .reg = 0x00009888, .val = 0x01E10000 },
         { .reg = 0x00009888, .val = 0x0DE10006 },
         { .reg = 0x00009888, .val = 0x11E10007 },
         { .reg = 0x00009888, .val = 0x02814A00 },
         { .reg = 0x00009888, .val = 0x04813953 },
         { .reg = 0x00009888, .val = 0x06810002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010040 },
         { .reg = 0x00009888, .val = 0x58010604 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010804 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010400 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010002 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010401 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext12__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext12__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext12__avg_gpu_core_frequency__max,mtlgt3__ext12__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5686, 24, percentage_max_float,mtlgt3__ext12__l3_input_available_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5687, 28, percentage_max_float,mtlgt3__ext12__l3_input_available_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5688, 32, percentage_max_float,mtlgt3__ext12__l3_input_available_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5689, 36, percentage_max_float,mtlgt3__ext12__l3_input_available_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6470, 40, percentage_max_float,mtlgt3__ext12__l3_input_available_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6471, 44, percentage_max_float,mtlgt3__ext12__l3_input_available_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6472, 48, percentage_max_float,mtlgt3__ext12__l3_input_available_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6473, 52, percentage_max_float,mtlgt3__ext12__l3_input_available_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5690, 56, percentage_max_float,mtlgt3__ext12__l3_output_ready_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5691, 60, percentage_max_float,mtlgt3__ext12__l3_output_ready_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5692, 64, percentage_max_float,mtlgt3__ext12__l3_output_ready_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5693, 68, percentage_max_float,mtlgt3__ext12__l3_output_ready_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6474, 72, percentage_max_float,mtlgt3__ext12__l3_output_ready_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6475, 76, percentage_max_float,mtlgt3__ext12__l3_output_ready_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6476, 80, percentage_max_float,mtlgt3__ext12__l3_output_ready_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6477, 84, percentage_max_float,mtlgt3__ext12__l3_output_ready_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext13_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext13";
   query->symbol_name = "Ext13";
   query->guid = "f7fdd159-e273-47ab-99bc-f4fc410c6053";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03016000 },
         { .reg = 0x00009888, .val = 0x0B011183 },
         { .reg = 0x00009888, .val = 0x03216000 },
         { .reg = 0x00009888, .val = 0x0B211000 },
         { .reg = 0x00009888, .val = 0x03416000 },
         { .reg = 0x00009888, .val = 0x0B411000 },
         { .reg = 0x00009888, .val = 0x03616000 },
         { .reg = 0x00009888, .val = 0x0B611000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x130103C0 },
         { .reg = 0x00009888, .val = 0x01210004 },
         { .reg = 0x00009888, .val = 0x09210183 },
         { .reg = 0x00009888, .val = 0x1321000F },
         { .reg = 0x00009888, .val = 0x01410004 },
         { .reg = 0x00009888, .val = 0x07410183 },
         { .reg = 0x00009888, .val = 0x114103C0 },
         { .reg = 0x00009888, .val = 0x01610004 },
         { .reg = 0x00009888, .val = 0x05610183 },
         { .reg = 0x00009888, .val = 0x1161000F },
         { .reg = 0x00009888, .val = 0x0001392D },
         { .reg = 0x00009888, .val = 0x02010093 },
         { .reg = 0x00009888, .val = 0x04013940 },
         { .reg = 0x00009888, .val = 0x06010002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015500 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AA00 },
         { .reg = 0x00009888, .val = 0x4C010200 },
         { .reg = 0x00009888, .val = 0x56010010 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010002 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x50010200 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext13__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext13__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext13__avg_gpu_core_frequency__max,mtlgt3__ext13__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5824, 24, percentage_max_float,mtlgt3__ext13__l3_superq_full_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5825, 28, percentage_max_float,mtlgt3__ext13__l3_superq_full_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5826, 32, percentage_max_float,mtlgt3__ext13__l3_superq_full_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5827, 36, percentage_max_float,mtlgt3__ext13__l3_superq_full_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5828, 40, NULL,mtlgt3__ext13__color_l3_access_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5829, 48, NULL,mtlgt3__ext13__color_l3_access_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5830, 56, NULL,mtlgt3__ext13__color_l3_access_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 5831, 64, NULL,mtlgt3__ext13__color_l3_access_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext14_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext14";
   query->symbol_name = "Ext14";
   query->guid = "423732fb-f20a-4549-b632-53ac587668d9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03816000 },
         { .reg = 0x00009888, .val = 0x0B811000 },
         { .reg = 0x00009888, .val = 0x03A16000 },
         { .reg = 0x00009888, .val = 0x0BA11000 },
         { .reg = 0x00009888, .val = 0x03C16000 },
         { .reg = 0x00009888, .val = 0x0BC11000 },
         { .reg = 0x00009888, .val = 0x03E16000 },
         { .reg = 0x00009888, .val = 0x0BE11183 },
         { .reg = 0x00009888, .val = 0x00825555 },
         { .reg = 0x00009888, .val = 0x02825500 },
         { .reg = 0x00009888, .val = 0x01810004 },
         { .reg = 0x00009888, .val = 0x05810183 },
         { .reg = 0x00009888, .val = 0x138103C0 },
         { .reg = 0x00009888, .val = 0x01A10004 },
         { .reg = 0x00009888, .val = 0x07A10183 },
         { .reg = 0x00009888, .val = 0x13A1000F },
         { .reg = 0x00009888, .val = 0x01C10004 },
         { .reg = 0x00009888, .val = 0x09C10183 },
         { .reg = 0x00009888, .val = 0x11C103C0 },
         { .reg = 0x00009888, .val = 0x01E10004 },
         { .reg = 0x00009888, .val = 0x11E1000F },
         { .reg = 0x00009888, .val = 0x008146D2 },
         { .reg = 0x00009888, .val = 0x0281016C },
         { .reg = 0x00009888, .val = 0x04813940 },
         { .reg = 0x00009888, .val = 0x06810002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F0FF },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015500 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010201 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010002 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010401 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext14__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext14__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext14__avg_gpu_core_frequency__max,mtlgt3__ext14__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6608, 24, percentage_max_float,mtlgt3__ext14__l3_superq_full_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6609, 28, percentage_max_float,mtlgt3__ext14__l3_superq_full_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6610, 32, percentage_max_float,mtlgt3__ext14__l3_superq_full_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6611, 36, percentage_max_float,mtlgt3__ext14__l3_superq_full_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6612, 40, NULL,mtlgt3__ext14__color_l3_access_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6613, 48, NULL,mtlgt3__ext14__color_l3_access_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6614, 56, NULL,mtlgt3__ext14__color_l3_access_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6615, 64, NULL,mtlgt3__ext14__color_l3_access_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext15_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext15";
   query->symbol_name = "Ext15";
   query->guid = "0fa8f991-d412-4014-a7a7-be08ccf5fc4c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03012000 },
         { .reg = 0x00009888, .val = 0x05010042 },
         { .reg = 0x00009888, .val = 0x03212000 },
         { .reg = 0x00009888, .val = 0x05210000 },
         { .reg = 0x00009888, .val = 0x03412000 },
         { .reg = 0x00009888, .val = 0x05410000 },
         { .reg = 0x00009888, .val = 0x03612000 },
         { .reg = 0x00009888, .val = 0x05610000 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025555 },
         { .reg = 0x00009888, .val = 0x01010010 },
         { .reg = 0x00009888, .val = 0x07010000 },
         { .reg = 0x00009888, .val = 0x11010008 },
         { .reg = 0x00009888, .val = 0x01210010 },
         { .reg = 0x00009888, .val = 0x07210080 },
         { .reg = 0x00009888, .val = 0x09210001 },
         { .reg = 0x00009888, .val = 0x11210200 },
         { .reg = 0x00009888, .val = 0x01410010 },
         { .reg = 0x00009888, .val = 0x0B410042 },
         { .reg = 0x00009888, .val = 0x0D410000 },
         { .reg = 0x00009888, .val = 0x13410008 },
         { .reg = 0x00009888, .val = 0x01610010 },
         { .reg = 0x00009888, .val = 0x0D610080 },
         { .reg = 0x00009888, .val = 0x0F610001 },
         { .reg = 0x00009888, .val = 0x13610200 },
         { .reg = 0x00009888, .val = 0x00013692 },
         { .reg = 0x00009888, .val = 0x02015923 },
         { .reg = 0x00009888, .val = 0x040146AD },
         { .reg = 0x00009888, .val = 0x06010005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010400 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010202 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010001 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010202 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext15__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext15__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext15__avg_gpu_core_frequency__max,mtlgt3__ext15__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5832, 24, percentage_max_float,mtlgt3__ext15__l3_busy_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5833, 28, percentage_max_float,mtlgt3__ext15__l3_busy_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5834, 32, percentage_max_float,mtlgt3__ext15__l3_busy_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5835, 36, percentage_max_float,mtlgt3__ext15__l3_busy_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5836, 40, percentage_max_float,mtlgt3__ext15__l3_stall_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5837, 44, percentage_max_float,mtlgt3__ext15__l3_stall_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5838, 48, percentage_max_float,mtlgt3__ext15__l3_stall_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 5839, 52, percentage_max_float,mtlgt3__ext15__l3_stall_l3_bank3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext16_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext16";
   query->symbol_name = "Ext16";
   query->guid = "e37de2da-c16f-4b2a-82bc-e1062fabfa2a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x03812000 },
         { .reg = 0x00009888, .val = 0x05810042 },
         { .reg = 0x00009888, .val = 0x03A12000 },
         { .reg = 0x00009888, .val = 0x05A10000 },
         { .reg = 0x00009888, .val = 0x03C12000 },
         { .reg = 0x00009888, .val = 0x05C10000 },
         { .reg = 0x00009888, .val = 0x03E12000 },
         { .reg = 0x00009888, .val = 0x05E10000 },
         { .reg = 0x00009888, .val = 0x00825555 },
         { .reg = 0x00009888, .val = 0x02825555 },
         { .reg = 0x00009888, .val = 0x01810010 },
         { .reg = 0x00009888, .val = 0x07810000 },
         { .reg = 0x00009888, .val = 0x13810200 },
         { .reg = 0x00009888, .val = 0x01A10010 },
         { .reg = 0x00009888, .val = 0x07A10080 },
         { .reg = 0x00009888, .val = 0x09A10001 },
         { .reg = 0x00009888, .val = 0x13A10008 },
         { .reg = 0x00009888, .val = 0x01C10010 },
         { .reg = 0x00009888, .val = 0x0BC10042 },
         { .reg = 0x00009888, .val = 0x0DC10000 },
         { .reg = 0x00009888, .val = 0x11C10200 },
         { .reg = 0x00009888, .val = 0x01E10010 },
         { .reg = 0x00009888, .val = 0x0DE10080 },
         { .reg = 0x00009888, .val = 0x0FE10001 },
         { .reg = 0x00009888, .val = 0x11E10008 },
         { .reg = 0x00009888, .val = 0x00813692 },
         { .reg = 0x00009888, .val = 0x02815923 },
         { .reg = 0x00009888, .val = 0x0481396D },
         { .reg = 0x00009888, .val = 0x06810002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010202 },
         { .reg = 0x00009888, .val = 0x5A010010 },
         { .reg = 0x00009888, .val = 0x5C010401 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010002 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010401 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext16__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext16__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext16__avg_gpu_core_frequency__max,mtlgt3__ext16__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6616, 24, percentage_max_float,mtlgt3__ext16__l3_busy_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6617, 28, percentage_max_float,mtlgt3__ext16__l3_busy_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6618, 32, percentage_max_float,mtlgt3__ext16__l3_busy_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6619, 36, percentage_max_float,mtlgt3__ext16__l3_busy_l3_bank7__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6620, 40, percentage_max_float,mtlgt3__ext16__l3_stall_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6621, 44, percentage_max_float,mtlgt3__ext16__l3_stall_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6622, 48, percentage_max_float,mtlgt3__ext16__l3_stall_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6623, 52, percentage_max_float,mtlgt3__ext16__l3_stall_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext17_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext17";
   query->symbol_name = "Ext17";
   query->guid = "e8a60701-f694-496d-95be-34cc80796a46";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2808005E },
         { .reg = 0x00009888, .val = 0x2C087800 },
         { .reg = 0x00009888, .val = 0x2E080002 },
         { .reg = 0x00009888, .val = 0x2828005E },
         { .reg = 0x00009888, .val = 0x2C287800 },
         { .reg = 0x00009888, .val = 0x2E280002 },
         { .reg = 0x00009888, .val = 0x2848005E },
         { .reg = 0x00009888, .val = 0x2C487800 },
         { .reg = 0x00009888, .val = 0x2E480002 },
         { .reg = 0x00009888, .val = 0x2868005E },
         { .reg = 0x00009888, .val = 0x2C687800 },
         { .reg = 0x00009888, .val = 0x2E680002 },
         { .reg = 0x00009888, .val = 0x06081A54 },
         { .reg = 0x00009888, .val = 0x0E080830 },
         { .reg = 0x00009888, .val = 0x10080B7D },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x06281A54 },
         { .reg = 0x00009888, .val = 0x08280830 },
         { .reg = 0x00009888, .val = 0x12280B7D },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x06481A54 },
         { .reg = 0x00009888, .val = 0x0A480830 },
         { .reg = 0x00009888, .val = 0x14480B7D },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x06681A54 },
         { .reg = 0x00009888, .val = 0x0C680830 },
         { .reg = 0x00009888, .val = 0x16680B7D },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x000150F5 },
         { .reg = 0x00009888, .val = 0x02010F55 },
         { .reg = 0x00009888, .val = 0x00045005 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x000B0FC3 },
         { .reg = 0x00009888, .val = 0x0009A00F },
         { .reg = 0x00009888, .val = 0x020900FA },
         { .reg = 0x00009888, .val = 0x000AA0AA },
         { .reg = 0x00009888, .val = 0x020A0AAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AFAA },
         { .reg = 0x00009888, .val = 0x0202FAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010005 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010600 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext17__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext17__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext17__avg_gpu_core_frequency__max,mtlgt3__ext17__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5840, 24, percentage_max_float,mtlgt3__ext17__load_store_cache_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5841, 28, percentage_max_float,mtlgt3__ext17__load_store_cache_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5842, 32, percentage_max_float,mtlgt3__ext17__load_store_cache_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5843, 36, percentage_max_float,mtlgt3__ext17__load_store_cache_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5844, 40, percentage_max_float,mtlgt3__ext17__load_store_cache_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5845, 44, percentage_max_float,mtlgt3__ext17__load_store_cache_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5846, 48, percentage_max_float,mtlgt3__ext17__load_store_cache_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5847, 52, percentage_max_float,mtlgt3__ext17__load_store_cache_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext18_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext18";
   query->symbol_name = "Ext18";
   query->guid = "1c957158-09ff-4a89-aa5b-3c1b4e46f9ba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2888005E },
         { .reg = 0x00009888, .val = 0x2C887800 },
         { .reg = 0x00009888, .val = 0x2E880002 },
         { .reg = 0x00009888, .val = 0x28A8005E },
         { .reg = 0x00009888, .val = 0x2CA87800 },
         { .reg = 0x00009888, .val = 0x2EA80002 },
         { .reg = 0x00009888, .val = 0x28C8005E },
         { .reg = 0x00009888, .val = 0x2CC87800 },
         { .reg = 0x00009888, .val = 0x2EC80002 },
         { .reg = 0x00009888, .val = 0x28E8005E },
         { .reg = 0x00009888, .val = 0x2CE87800 },
         { .reg = 0x00009888, .val = 0x2EE80002 },
         { .reg = 0x00009888, .val = 0x06881A54 },
         { .reg = 0x00009888, .val = 0x0E880830 },
         { .reg = 0x00009888, .val = 0x16880B7D },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009888, .val = 0x06A81A54 },
         { .reg = 0x00009888, .val = 0x0CA80830 },
         { .reg = 0x00009888, .val = 0x14A80B7D },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009888, .val = 0x06C81A54 },
         { .reg = 0x00009888, .val = 0x0AC80830 },
         { .reg = 0x00009888, .val = 0x12C80B7D },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E81A54 },
         { .reg = 0x00009888, .val = 0x08E80830 },
         { .reg = 0x00009888, .val = 0x10E80B7D },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x002155F0 },
         { .reg = 0x00009888, .val = 0x022155F0 },
         { .reg = 0x00009888, .val = 0x00245500 },
         { .reg = 0x00009888, .val = 0x02245500 },
         { .reg = 0x00009888, .val = 0x002BF0F0 },
         { .reg = 0x00009888, .val = 0x0029AF00 },
         { .reg = 0x00009888, .val = 0x0229AF00 },
         { .reg = 0x00009888, .val = 0x002AAAA0 },
         { .reg = 0x00009888, .val = 0x022AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAF },
         { .reg = 0x00009888, .val = 0x0282AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext18__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext18__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext18__avg_gpu_core_frequency__max,mtlgt3__ext18__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6624, 24, percentage_max_float,mtlgt3__ext18__load_store_cache_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6625, 28, percentage_max_float,mtlgt3__ext18__load_store_cache_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6626, 32, percentage_max_float,mtlgt3__ext18__load_store_cache_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6627, 36, percentage_max_float,mtlgt3__ext18__load_store_cache_input_available_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6628, 40, percentage_max_float,mtlgt3__ext18__load_store_cache_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6629, 44, percentage_max_float,mtlgt3__ext18__load_store_cache_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6630, 48, percentage_max_float,mtlgt3__ext18__load_store_cache_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6631, 52, percentage_max_float,mtlgt3__ext18__load_store_cache_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext21_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext21";
   query->symbol_name = "Ext21";
   query->guid = "a0b46166-6078-4045-8321-6df39b8e8ced";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18080006 },
         { .reg = 0x00009888, .val = 0x1C081800 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x18280006 },
         { .reg = 0x00009888, .val = 0x1C281800 },
         { .reg = 0x00009888, .val = 0x2428001F },
         { .reg = 0x00009888, .val = 0x18480006 },
         { .reg = 0x00009888, .val = 0x1C481800 },
         { .reg = 0x00009888, .val = 0x2448001F },
         { .reg = 0x00009888, .val = 0x18680006 },
         { .reg = 0x00009888, .val = 0x1C681800 },
         { .reg = 0x00009888, .val = 0x2468001F },
         { .reg = 0x00009888, .val = 0x04080808 },
         { .reg = 0x00009888, .val = 0x0E080200 },
         { .reg = 0x00009888, .val = 0x100804D2 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x04280808 },
         { .reg = 0x00009888, .val = 0x0C280200 },
         { .reg = 0x00009888, .val = 0x162804D2 },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x04480808 },
         { .reg = 0x00009888, .val = 0x0A480200 },
         { .reg = 0x00009888, .val = 0x144804D2 },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x04680808 },
         { .reg = 0x00009888, .val = 0x08680200 },
         { .reg = 0x00009888, .val = 0x126804D2 },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x000155F0 },
         { .reg = 0x00009888, .val = 0x02015F05 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02045005 },
         { .reg = 0x00009888, .val = 0x000BC3F0 },
         { .reg = 0x00009888, .val = 0x0009AF00 },
         { .reg = 0x00009888, .val = 0x0209F00A },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x020AAA0A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAF },
         { .reg = 0x00009888, .val = 0x0202AAFA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010605 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext21__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext21__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext21__avg_gpu_core_frequency__max,mtlgt3__ext21__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5848, 24, NULL,mtlgt3__ext21__load_store_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5849, 32, NULL,mtlgt3__ext21__load_store_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5850, 40, NULL,mtlgt3__ext21__load_store_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5851, 48, NULL,mtlgt3__ext21__load_store_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5852, 56, NULL,mtlgt3__ext21__load_store_cache_l3_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5853, 64, NULL,mtlgt3__ext21__load_store_cache_l3_read_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5854, 72, NULL,mtlgt3__ext21__load_store_cache_l3_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5855, 80, NULL,mtlgt3__ext21__load_store_cache_l3_read_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext22_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext22";
   query->symbol_name = "Ext22";
   query->guid = "92371114-aa03-46d8-ab34-6e843fc92123";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18880006 },
         { .reg = 0x00009888, .val = 0x1C881800 },
         { .reg = 0x00009888, .val = 0x2488001F },
         { .reg = 0x00009888, .val = 0x18A80006 },
         { .reg = 0x00009888, .val = 0x1CA81800 },
         { .reg = 0x00009888, .val = 0x24A8001F },
         { .reg = 0x00009888, .val = 0x18C80006 },
         { .reg = 0x00009888, .val = 0x1CC81800 },
         { .reg = 0x00009888, .val = 0x24C8001F },
         { .reg = 0x00009888, .val = 0x18E80006 },
         { .reg = 0x00009888, .val = 0x1CE81800 },
         { .reg = 0x00009888, .val = 0x24E8001F },
         { .reg = 0x00009888, .val = 0x04880808 },
         { .reg = 0x00009888, .val = 0x0E880493 },
         { .reg = 0x00009888, .val = 0x16880200 },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009888, .val = 0x04A80808 },
         { .reg = 0x00009888, .val = 0x0CA80493 },
         { .reg = 0x00009888, .val = 0x14A80200 },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009888, .val = 0x04C80808 },
         { .reg = 0x00009888, .val = 0x0AC80493 },
         { .reg = 0x00009888, .val = 0x12C80200 },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x04E80808 },
         { .reg = 0x00009888, .val = 0x08E80493 },
         { .reg = 0x00009888, .val = 0x10E80200 },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x002155F0 },
         { .reg = 0x00009888, .val = 0x022155F0 },
         { .reg = 0x00009888, .val = 0x00245500 },
         { .reg = 0x00009888, .val = 0x02245500 },
         { .reg = 0x00009888, .val = 0x002BF0F0 },
         { .reg = 0x00009888, .val = 0x0029AF00 },
         { .reg = 0x00009888, .val = 0x0229AF00 },
         { .reg = 0x00009888, .val = 0x002AAAA0 },
         { .reg = 0x00009888, .val = 0x022AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAF },
         { .reg = 0x00009888, .val = 0x0282AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext22__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext22__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext22__avg_gpu_core_frequency__max,mtlgt3__ext22__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6632, 24, NULL,mtlgt3__ext22__load_store_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6633, 32, NULL,mtlgt3__ext22__load_store_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6634, 40, NULL,mtlgt3__ext22__load_store_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6635, 48, NULL,mtlgt3__ext22__load_store_cache_access_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6636, 56, NULL,mtlgt3__ext22__load_store_cache_l3_read_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6637, 64, NULL,mtlgt3__ext22__load_store_cache_l3_read_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6638, 72, NULL,mtlgt3__ext22__load_store_cache_l3_read_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6639, 80, NULL,mtlgt3__ext22__load_store_cache_l3_read_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext23_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext23";
   query->symbol_name = "Ext23";
   query->guid = "c7cd47a5-39e8-4c58-9b4f-a9c6df869db8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x18280003 },
         { .reg = 0x00009888, .val = 0x1C280C00 },
         { .reg = 0x00009888, .val = 0x18480003 },
         { .reg = 0x00009888, .val = 0x1C480C00 },
         { .reg = 0x00009888, .val = 0x18680003 },
         { .reg = 0x00009888, .val = 0x1C680C00 },
         { .reg = 0x00009888, .val = 0x04080080 },
         { .reg = 0x00009888, .val = 0x080800C2 },
         { .reg = 0x00009888, .val = 0x0A0802CA },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x04280080 },
         { .reg = 0x00009888, .val = 0x0C2800C2 },
         { .reg = 0x00009888, .val = 0x0E2802CA },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x04480080 },
         { .reg = 0x00009888, .val = 0x104800C2 },
         { .reg = 0x00009888, .val = 0x124802CA },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x04680080 },
         { .reg = 0x00009888, .val = 0x146800C2 },
         { .reg = 0x00009888, .val = 0x166802CA },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext23__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext23__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext23__avg_gpu_core_frequency__max,mtlgt3__ext23__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5856, 24, NULL,mtlgt3__ext23__load_store_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5857, 32, NULL,mtlgt3__ext23__load_store_cache_hit_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5858, 40, NULL,mtlgt3__ext23__load_store_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5859, 48, NULL,mtlgt3__ext23__load_store_cache_hit_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext24_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext24";
   query->symbol_name = "Ext24";
   query->guid = "2adf2c05-e151-4fa7-9e77-2331bd94235e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18880003 },
         { .reg = 0x00009888, .val = 0x1C880C00 },
         { .reg = 0x00009888, .val = 0x18A80003 },
         { .reg = 0x00009888, .val = 0x1CA80C00 },
         { .reg = 0x00009888, .val = 0x18C80003 },
         { .reg = 0x00009888, .val = 0x1CC80C00 },
         { .reg = 0x00009888, .val = 0x18E80003 },
         { .reg = 0x00009888, .val = 0x1CE80C00 },
         { .reg = 0x00009888, .val = 0x04880080 },
         { .reg = 0x00009888, .val = 0x088800C2 },
         { .reg = 0x00009888, .val = 0x0A8802CA },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x04A80080 },
         { .reg = 0x00009888, .val = 0x0CA800C2 },
         { .reg = 0x00009888, .val = 0x0EA802CA },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x04C80080 },
         { .reg = 0x00009888, .val = 0x10C800C2 },
         { .reg = 0x00009888, .val = 0x12C802CA },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x04E80080 },
         { .reg = 0x00009888, .val = 0x14E800C2 },
         { .reg = 0x00009888, .val = 0x16E802CA },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001800 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006000 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018000 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060000 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext24__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext24__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext24__avg_gpu_core_frequency__max,mtlgt3__ext24__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6640, 24, NULL,mtlgt3__ext24__load_store_cache_hit_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6641, 32, NULL,mtlgt3__ext24__load_store_cache_hit_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6642, 40, NULL,mtlgt3__ext24__load_store_cache_hit_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6643, 48, NULL,mtlgt3__ext24__load_store_cache_hit_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext28_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext28";
   query->symbol_name = "Ext28";
   query->guid = "1fcdcf0a-54da-4397-8832-c884d8d0b3ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18080003 },
         { .reg = 0x00009888, .val = 0x1C080C00 },
         { .reg = 0x00009888, .val = 0x2408001F },
         { .reg = 0x00009888, .val = 0x18280003 },
         { .reg = 0x00009888, .val = 0x1C280C00 },
         { .reg = 0x00009888, .val = 0x2428001F },
         { .reg = 0x00009888, .val = 0x18480003 },
         { .reg = 0x00009888, .val = 0x1C480C00 },
         { .reg = 0x00009888, .val = 0x2448001F },
         { .reg = 0x00009888, .val = 0x18680003 },
         { .reg = 0x00009888, .val = 0x1C680C00 },
         { .reg = 0x00009888, .val = 0x2468001F },
         { .reg = 0x00009888, .val = 0x04080880 },
         { .reg = 0x00009888, .val = 0x0E080554 },
         { .reg = 0x00009888, .val = 0x10080304 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x04280880 },
         { .reg = 0x00009888, .val = 0x0C280554 },
         { .reg = 0x00009888, .val = 0x16280304 },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x04480880 },
         { .reg = 0x00009888, .val = 0x0A480554 },
         { .reg = 0x00009888, .val = 0x14480304 },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x04680880 },
         { .reg = 0x00009888, .val = 0x08680554 },
         { .reg = 0x00009888, .val = 0x12680304 },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x000155F0 },
         { .reg = 0x00009888, .val = 0x02015F05 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02045005 },
         { .reg = 0x00009888, .val = 0x000BC3F0 },
         { .reg = 0x00009888, .val = 0x0009AF00 },
         { .reg = 0x00009888, .val = 0x0209F00A },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x020AAA0A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAF },
         { .reg = 0x00009888, .val = 0x0202AAFA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010605 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext28__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext28__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext28__avg_gpu_core_frequency__max,mtlgt3__ext28__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5860, 24, NULL,mtlgt3__ext28__load_store_cache_l3_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5861, 32, NULL,mtlgt3__ext28__load_store_cache_l3_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5862, 40, NULL,mtlgt3__ext28__load_store_cache_l3_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5863, 48, NULL,mtlgt3__ext28__load_store_cache_l3_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5864, 56, NULL,mtlgt3__ext28__load_store_cache_partial_write_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5865, 64, NULL,mtlgt3__ext28__load_store_cache_partial_write_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5866, 72, NULL,mtlgt3__ext28__load_store_cache_partial_write_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5867, 80, NULL,mtlgt3__ext28__load_store_cache_partial_write_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext29_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext29";
   query->symbol_name = "Ext29";
   query->guid = "9701aca8-76a6-49ee-96c9-ff983f24d29e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18880003 },
         { .reg = 0x00009888, .val = 0x1C880C00 },
         { .reg = 0x00009888, .val = 0x2488001F },
         { .reg = 0x00009888, .val = 0x18A80003 },
         { .reg = 0x00009888, .val = 0x1CA80C00 },
         { .reg = 0x00009888, .val = 0x24A8001F },
         { .reg = 0x00009888, .val = 0x18C80003 },
         { .reg = 0x00009888, .val = 0x1CC80C00 },
         { .reg = 0x00009888, .val = 0x24C8001F },
         { .reg = 0x00009888, .val = 0x18E80003 },
         { .reg = 0x00009888, .val = 0x1CE80C00 },
         { .reg = 0x00009888, .val = 0x24E8001F },
         { .reg = 0x00009888, .val = 0x04880808 },
         { .reg = 0x00009888, .val = 0x0E880304 },
         { .reg = 0x00009888, .val = 0x16880515 },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009888, .val = 0x04A80808 },
         { .reg = 0x00009888, .val = 0x0CA80304 },
         { .reg = 0x00009888, .val = 0x14A80515 },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009888, .val = 0x04C80808 },
         { .reg = 0x00009888, .val = 0x0AC80304 },
         { .reg = 0x00009888, .val = 0x12C80515 },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x04E80808 },
         { .reg = 0x00009888, .val = 0x08E80304 },
         { .reg = 0x00009888, .val = 0x10E80515 },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x002155F0 },
         { .reg = 0x00009888, .val = 0x022155F0 },
         { .reg = 0x00009888, .val = 0x00245500 },
         { .reg = 0x00009888, .val = 0x02245500 },
         { .reg = 0x00009888, .val = 0x002BF0F0 },
         { .reg = 0x00009888, .val = 0x0029AF00 },
         { .reg = 0x00009888, .val = 0x0229AF00 },
         { .reg = 0x00009888, .val = 0x002AAAA0 },
         { .reg = 0x00009888, .val = 0x022AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAF },
         { .reg = 0x00009888, .val = 0x0282AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext29__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext29__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext29__avg_gpu_core_frequency__max,mtlgt3__ext29__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6644, 24, NULL,mtlgt3__ext29__load_store_cache_l3_write_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6645, 32, NULL,mtlgt3__ext29__load_store_cache_l3_write_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6646, 40, NULL,mtlgt3__ext29__load_store_cache_l3_write_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6647, 48, NULL,mtlgt3__ext29__load_store_cache_l3_write_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6648, 56, NULL,mtlgt3__ext29__load_store_cache_partial_write_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6649, 64, NULL,mtlgt3__ext29__load_store_cache_partial_write_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6650, 72, NULL,mtlgt3__ext29__load_store_cache_partial_write_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6651, 80, NULL,mtlgt3__ext29__load_store_cache_partial_write_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext31_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext31";
   query->symbol_name = "Ext31";
   query->guid = "f47e74cf-7966-43ea-bbac-46f9a0d1dc1f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x28280000 },
         { .reg = 0x00009888, .val = 0x2C280000 },
         { .reg = 0x00009888, .val = 0x28480000 },
         { .reg = 0x00009888, .val = 0x2C480000 },
         { .reg = 0x00009888, .val = 0x28680000 },
         { .reg = 0x00009888, .val = 0x2C680000 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x14080824 },
         { .reg = 0x00009888, .val = 0x16080C34 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x06280204 },
         { .reg = 0x00009888, .val = 0x10280824 },
         { .reg = 0x00009888, .val = 0x12280C34 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x06480204 },
         { .reg = 0x00009888, .val = 0x0C480824 },
         { .reg = 0x00009888, .val = 0x0E480C34 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x06680204 },
         { .reg = 0x00009888, .val = 0x08680824 },
         { .reg = 0x00009888, .val = 0x0A680C34 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFF00 },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext31__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext31__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext31__avg_gpu_core_frequency__max,mtlgt3__ext31__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5868, 24, NULL,mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5869, 32, NULL,mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5870, 40, NULL,mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5871, 48, NULL,mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext32_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext32";
   query->symbol_name = "Ext32";
   query->guid = "3e220edc-390e-4964-9e57-4d45f3e01de8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28880000 },
         { .reg = 0x00009888, .val = 0x2C880000 },
         { .reg = 0x00009888, .val = 0x28A80000 },
         { .reg = 0x00009888, .val = 0x2CA80000 },
         { .reg = 0x00009888, .val = 0x28C80000 },
         { .reg = 0x00009888, .val = 0x2CC80000 },
         { .reg = 0x00009888, .val = 0x28E80000 },
         { .reg = 0x00009888, .val = 0x2CE80000 },
         { .reg = 0x00009888, .val = 0x06880204 },
         { .reg = 0x00009888, .val = 0x08880824 },
         { .reg = 0x00009888, .val = 0x0A880C34 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x06A80204 },
         { .reg = 0x00009888, .val = 0x0CA80824 },
         { .reg = 0x00009888, .val = 0x0EA80C34 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x06C80204 },
         { .reg = 0x00009888, .val = 0x10C80824 },
         { .reg = 0x00009888, .val = 0x12C80C34 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E80204 },
         { .reg = 0x00009888, .val = 0x14E80824 },
         { .reg = 0x00009888, .val = 0x16E80C34 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext32__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext32__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext32__avg_gpu_core_frequency__max,mtlgt3__ext32__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6652, 24, NULL,mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6653, 32, NULL,mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6654, 40, NULL,mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6655, 48, NULL,mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext35_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext35";
   query->symbol_name = "Ext35";
   query->guid = "d334294d-8dd2-4ae2-ae31-7d0d4acc2b6b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x28280000 },
         { .reg = 0x00009888, .val = 0x2C280000 },
         { .reg = 0x00009888, .val = 0x28480000 },
         { .reg = 0x00009888, .val = 0x2C480000 },
         { .reg = 0x00009888, .val = 0x28680000 },
         { .reg = 0x00009888, .val = 0x2C680000 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x14080823 },
         { .reg = 0x00009888, .val = 0x16080C33 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x06280204 },
         { .reg = 0x00009888, .val = 0x10280823 },
         { .reg = 0x00009888, .val = 0x12280C33 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x06480204 },
         { .reg = 0x00009888, .val = 0x0C480823 },
         { .reg = 0x00009888, .val = 0x0E480C33 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x06680204 },
         { .reg = 0x00009888, .val = 0x08680823 },
         { .reg = 0x00009888, .val = 0x0A680C33 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFF00 },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext35__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext35__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext35__avg_gpu_core_frequency__max,mtlgt3__ext35__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5872, 24, NULL,mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5873, 32, NULL,mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5874, 40, NULL,mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5875, 48, NULL,mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext36_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext36";
   query->symbol_name = "Ext36";
   query->guid = "b749495f-4fc4-4e54-965e-38990758473b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28880000 },
         { .reg = 0x00009888, .val = 0x2C880000 },
         { .reg = 0x00009888, .val = 0x28A80000 },
         { .reg = 0x00009888, .val = 0x2CA80000 },
         { .reg = 0x00009888, .val = 0x28C80000 },
         { .reg = 0x00009888, .val = 0x2CC80000 },
         { .reg = 0x00009888, .val = 0x28E80000 },
         { .reg = 0x00009888, .val = 0x2CE80000 },
         { .reg = 0x00009888, .val = 0x06880204 },
         { .reg = 0x00009888, .val = 0x08880823 },
         { .reg = 0x00009888, .val = 0x0A880C33 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x06A80204 },
         { .reg = 0x00009888, .val = 0x0CA80823 },
         { .reg = 0x00009888, .val = 0x0EA80C33 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x06C80204 },
         { .reg = 0x00009888, .val = 0x10C80823 },
         { .reg = 0x00009888, .val = 0x12C80C33 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E80204 },
         { .reg = 0x00009888, .val = 0x14E80823 },
         { .reg = 0x00009888, .val = 0x16E80C33 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext36__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext36__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext36__avg_gpu_core_frequency__max,mtlgt3__ext36__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6656, 24, NULL,mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6657, 32, NULL,mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6658, 40, NULL,mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6659, 48, NULL,mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext39_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext39";
   query->symbol_name = "Ext39";
   query->guid = "09c0f842-3711-48f5-bf3e-74c1caa9f791";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x28280001 },
         { .reg = 0x00009888, .val = 0x2C280400 },
         { .reg = 0x00009888, .val = 0x2E280000 },
         { .reg = 0x00009888, .val = 0x28480001 },
         { .reg = 0x00009888, .val = 0x2C480400 },
         { .reg = 0x00009888, .val = 0x2E480000 },
         { .reg = 0x00009888, .val = 0x28680001 },
         { .reg = 0x00009888, .val = 0x2C680400 },
         { .reg = 0x00009888, .val = 0x2E680000 },
         { .reg = 0x00009888, .val = 0x06081A54 },
         { .reg = 0x00009888, .val = 0x14080A27 },
         { .reg = 0x00009888, .val = 0x16080E37 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x06281A54 },
         { .reg = 0x00009888, .val = 0x10280A27 },
         { .reg = 0x00009888, .val = 0x12280E37 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x06481A54 },
         { .reg = 0x00009888, .val = 0x0C480A27 },
         { .reg = 0x00009888, .val = 0x0E480E37 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x06681A54 },
         { .reg = 0x00009888, .val = 0x08680A27 },
         { .reg = 0x00009888, .val = 0x0A680E37 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFF00 },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext39__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext39__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext39__avg_gpu_core_frequency__max,mtlgt3__ext39__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5876, 24, NULL,mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5877, 32, NULL,mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5878, 40, NULL,mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5879, 48, NULL,mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext40_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext40";
   query->symbol_name = "Ext40";
   query->guid = "be7c864e-0538-420d-916d-ce3aed7742ba";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28880001 },
         { .reg = 0x00009888, .val = 0x2C880400 },
         { .reg = 0x00009888, .val = 0x2E880000 },
         { .reg = 0x00009888, .val = 0x28A80001 },
         { .reg = 0x00009888, .val = 0x2CA80400 },
         { .reg = 0x00009888, .val = 0x2EA80000 },
         { .reg = 0x00009888, .val = 0x28C80001 },
         { .reg = 0x00009888, .val = 0x2CC80400 },
         { .reg = 0x00009888, .val = 0x2EC80000 },
         { .reg = 0x00009888, .val = 0x28E80001 },
         { .reg = 0x00009888, .val = 0x2CE80400 },
         { .reg = 0x00009888, .val = 0x2EE80000 },
         { .reg = 0x00009888, .val = 0x06881A54 },
         { .reg = 0x00009888, .val = 0x08880A27 },
         { .reg = 0x00009888, .val = 0x0A880E37 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x06A81A54 },
         { .reg = 0x00009888, .val = 0x0CA80A27 },
         { .reg = 0x00009888, .val = 0x0EA80E37 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x06C81A54 },
         { .reg = 0x00009888, .val = 0x10C80A27 },
         { .reg = 0x00009888, .val = 0x12C80E37 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E81A54 },
         { .reg = 0x00009888, .val = 0x14E80A27 },
         { .reg = 0x00009888, .val = 0x16E80E37 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext40__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext40__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext40__avg_gpu_core_frequency__max,mtlgt3__ext40__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6660, 24, NULL,mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6661, 32, NULL,mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6662, 40, NULL,mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6663, 48, NULL,mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext43_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext43";
   query->symbol_name = "Ext43";
   query->guid = "86cf3d13-947b-4f7f-9685-1ff59ec342dd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x28280001 },
         { .reg = 0x00009888, .val = 0x2C280400 },
         { .reg = 0x00009888, .val = 0x2E280000 },
         { .reg = 0x00009888, .val = 0x06081A54 },
         { .reg = 0x00009888, .val = 0x0E0808A3 },
         { .reg = 0x00009888, .val = 0x10080CE8 },
         { .reg = 0x00009888, .val = 0x12080E32 },
         { .reg = 0x00009888, .val = 0x16080E69 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x06281A54 },
         { .reg = 0x00009888, .val = 0x082808A3 },
         { .reg = 0x00009888, .val = 0x0A280CE8 },
         { .reg = 0x00009888, .val = 0x0C280E32 },
         { .reg = 0x00009888, .val = 0x14280E69 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009AFFF },
         { .reg = 0x00009888, .val = 0x0209AFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext43__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext43__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext43__avg_gpu_core_frequency__max,mtlgt3__ext43__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5880, 24, NULL,mtlgt3__ext43__xve_load_store_cache_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5881, 32, NULL,mtlgt3__ext43__xve_load_store_cache_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5882, 40, NULL,mtlgt3__ext43__xve_load_store_cache_register_request_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5883, 48, NULL,mtlgt3__ext43__xve_load_store_cache_register_request_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext44_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext44";
   query->symbol_name = "Ext44";
   query->guid = "7675136e-a91e-4bf8-b206-32591b878339";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28880001 },
         { .reg = 0x00009888, .val = 0x2C880400 },
         { .reg = 0x00009888, .val = 0x2E880000 },
         { .reg = 0x00009888, .val = 0x28A80001 },
         { .reg = 0x00009888, .val = 0x2CA80400 },
         { .reg = 0x00009888, .val = 0x2EA80000 },
         { .reg = 0x00009888, .val = 0x06881A54 },
         { .reg = 0x00009888, .val = 0x088808A3 },
         { .reg = 0x00009888, .val = 0x0A880CE8 },
         { .reg = 0x00009888, .val = 0x0C880E32 },
         { .reg = 0x00009888, .val = 0x16880A79 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009888, .val = 0x06A81A54 },
         { .reg = 0x00009888, .val = 0x0EA808A3 },
         { .reg = 0x00009888, .val = 0x10A80CE8 },
         { .reg = 0x00009888, .val = 0x12A80E32 },
         { .reg = 0x00009888, .val = 0x14A80A79 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029FAAA },
         { .reg = 0x00009888, .val = 0x0229AFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext44__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext44__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext44__avg_gpu_core_frequency__max,mtlgt3__ext44__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6664, 24, NULL,mtlgt3__ext44__xve_load_store_cache_atomic_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6665, 32, NULL,mtlgt3__ext44__xve_load_store_cache_atomic_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6666, 40, NULL,mtlgt3__ext44__xve_load_store_cache_register_request_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6667, 48, NULL,mtlgt3__ext44__xve_load_store_cache_register_request_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext45_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext45";
   query->symbol_name = "Ext45";
   query->guid = "e953dbdb-3451-4912-80ae-241ecc56a59e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28480001 },
         { .reg = 0x00009888, .val = 0x2C480400 },
         { .reg = 0x00009888, .val = 0x2E480000 },
         { .reg = 0x00009888, .val = 0x28680001 },
         { .reg = 0x00009888, .val = 0x2C680400 },
         { .reg = 0x00009888, .val = 0x2E680000 },
         { .reg = 0x00009888, .val = 0x06481A54 },
         { .reg = 0x00009888, .val = 0x0E4808A3 },
         { .reg = 0x00009888, .val = 0x10480CE8 },
         { .reg = 0x00009888, .val = 0x12480E32 },
         { .reg = 0x00009888, .val = 0x16480E69 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x06681A54 },
         { .reg = 0x00009888, .val = 0x086808A3 },
         { .reg = 0x00009888, .val = 0x0A680CE8 },
         { .reg = 0x00009888, .val = 0x0C680E32 },
         { .reg = 0x00009888, .val = 0x14680E69 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x0201F0FF },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020AA0AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AFFF },
         { .reg = 0x00009888, .val = 0x0202AFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010002 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010400 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext45__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext45__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext45__avg_gpu_core_frequency__max,mtlgt3__ext45__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5884, 24, NULL,mtlgt3__ext45__xve_load_store_cache_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5885, 32, NULL,mtlgt3__ext45__xve_load_store_cache_atomic_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5886, 40, NULL,mtlgt3__ext45__xve_load_store_cache_register_request_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5887, 48, NULL,mtlgt3__ext45__xve_load_store_cache_register_request_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext46_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext46";
   query->symbol_name = "Ext46";
   query->guid = "94219d74-6a23-4b93-bf62-88c9ad4ed4bd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28C80001 },
         { .reg = 0x00009888, .val = 0x2CC80400 },
         { .reg = 0x00009888, .val = 0x2EC80000 },
         { .reg = 0x00009888, .val = 0x28E80001 },
         { .reg = 0x00009888, .val = 0x2CE80400 },
         { .reg = 0x00009888, .val = 0x2EE80000 },
         { .reg = 0x00009888, .val = 0x06C81A54 },
         { .reg = 0x00009888, .val = 0x08C808A3 },
         { .reg = 0x00009888, .val = 0x0AC80CE8 },
         { .reg = 0x00009888, .val = 0x0CC80E32 },
         { .reg = 0x00009888, .val = 0x16C80A79 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E81A54 },
         { .reg = 0x00009888, .val = 0x0EE808A3 },
         { .reg = 0x00009888, .val = 0x10E80CE8 },
         { .reg = 0x00009888, .val = 0x12E80E32 },
         { .reg = 0x00009888, .val = 0x14E80A79 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00210FFF },
         { .reg = 0x00009888, .val = 0x0221F000 },
         { .reg = 0x00009888, .val = 0x002A0AAA },
         { .reg = 0x00009888, .val = 0x022AA000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FAAA },
         { .reg = 0x00009888, .val = 0x0282AFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010400 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010020 },
         { .reg = 0x00009888, .val = 0x50010402 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext46__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext46__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext46__avg_gpu_core_frequency__max,mtlgt3__ext46__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6668, 24, NULL,mtlgt3__ext46__xve_load_store_cache_atomic_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6669, 32, NULL,mtlgt3__ext46__xve_load_store_cache_atomic_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6670, 40, NULL,mtlgt3__ext46__xve_load_store_cache_register_request_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6671, 48, NULL,mtlgt3__ext46__xve_load_store_cache_register_request_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext51_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext51";
   query->symbol_name = "Ext51";
   query->guid = "cab52f96-c6bf-48ca-a34e-17e52cadc8a6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2808001D },
         { .reg = 0x00009888, .val = 0x2C087400 },
         { .reg = 0x00009888, .val = 0x2828001D },
         { .reg = 0x00009888, .val = 0x2C287400 },
         { .reg = 0x00009888, .val = 0x2848001D },
         { .reg = 0x00009888, .val = 0x2C487400 },
         { .reg = 0x00009888, .val = 0x2868001D },
         { .reg = 0x00009888, .val = 0x2C687400 },
         { .reg = 0x00009888, .val = 0x2888001D },
         { .reg = 0x00009888, .val = 0x2C887400 },
         { .reg = 0x00009888, .val = 0x28A8001D },
         { .reg = 0x00009888, .val = 0x2CA87400 },
         { .reg = 0x00009888, .val = 0x28C8001D },
         { .reg = 0x00009888, .val = 0x2CC87400 },
         { .reg = 0x00009888, .val = 0x28E8001D },
         { .reg = 0x00009888, .val = 0x2CE87400 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x0E080D65 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x06280204 },
         { .reg = 0x00009888, .val = 0x0C280D65 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x06480204 },
         { .reg = 0x00009888, .val = 0x0A480D65 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x06680204 },
         { .reg = 0x00009888, .val = 0x08680D65 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x06880204 },
         { .reg = 0x00009888, .val = 0x16880975 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009888, .val = 0x06A80204 },
         { .reg = 0x00009888, .val = 0x14A80975 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009888, .val = 0x06C80204 },
         { .reg = 0x00009888, .val = 0x12C80975 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E80204 },
         { .reg = 0x00009888, .val = 0x10E80975 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x000155F0 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x000B00F0 },
         { .reg = 0x00009888, .val = 0x0009AF00 },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x022155F0 },
         { .reg = 0x00009888, .val = 0x02245500 },
         { .reg = 0x00009888, .val = 0x002BF000 },
         { .reg = 0x00009888, .val = 0x0229AF00 },
         { .reg = 0x00009888, .val = 0x022AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAF },
         { .reg = 0x00009888, .val = 0x0282AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010E00 },
         { .reg = 0x00009888, .val = 0x56010070 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext51__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext51__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext51__avg_gpu_core_frequency__max,mtlgt3__ext51__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5888, 24, NULL,mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5889, 32, NULL,mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5890, 40, NULL,mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5891, 48, NULL,mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6672, 56, NULL,mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6673, 64, NULL,mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6674, 72, NULL,mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6675, 80, NULL,mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext53_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext53";
   query->symbol_name = "Ext53";
   query->guid = "e4597eb9-ffa4-4da5-a180-5e12299f22cc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x28280000 },
         { .reg = 0x00009888, .val = 0x2C280000 },
         { .reg = 0x00009888, .val = 0x28480000 },
         { .reg = 0x00009888, .val = 0x2C480000 },
         { .reg = 0x00009888, .val = 0x28680000 },
         { .reg = 0x00009888, .val = 0x2C680000 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x14080824 },
         { .reg = 0x00009888, .val = 0x16080C34 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x06280204 },
         { .reg = 0x00009888, .val = 0x10280824 },
         { .reg = 0x00009888, .val = 0x12280C34 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x06480204 },
         { .reg = 0x00009888, .val = 0x0C480824 },
         { .reg = 0x00009888, .val = 0x0E480C34 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x06680204 },
         { .reg = 0x00009888, .val = 0x08680824 },
         { .reg = 0x00009888, .val = 0x0A680C34 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFF00 },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext53__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext53__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext53__avg_gpu_core_frequency__max,mtlgt3__ext53__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5892, 24, NULL,mtlgt3__ext53__xve_slm_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5893, 32, NULL,mtlgt3__ext53__xve_slm_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5894, 40, NULL,mtlgt3__ext53__xve_slm_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5895, 48, NULL,mtlgt3__ext53__xve_slm_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext54_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext54";
   query->symbol_name = "Ext54";
   query->guid = "0a11c113-298b-4f77-a085-1b7cac225015";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28880000 },
         { .reg = 0x00009888, .val = 0x2C880000 },
         { .reg = 0x00009888, .val = 0x28A80000 },
         { .reg = 0x00009888, .val = 0x2CA80000 },
         { .reg = 0x00009888, .val = 0x28C80000 },
         { .reg = 0x00009888, .val = 0x2CC80000 },
         { .reg = 0x00009888, .val = 0x28E80000 },
         { .reg = 0x00009888, .val = 0x2CE80000 },
         { .reg = 0x00009888, .val = 0x06880204 },
         { .reg = 0x00009888, .val = 0x08880824 },
         { .reg = 0x00009888, .val = 0x0A880C34 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x06A80204 },
         { .reg = 0x00009888, .val = 0x0CA80824 },
         { .reg = 0x00009888, .val = 0x0EA80C34 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x06C80204 },
         { .reg = 0x00009888, .val = 0x10C80824 },
         { .reg = 0x00009888, .val = 0x12C80C34 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E80204 },
         { .reg = 0x00009888, .val = 0x14E80824 },
         { .reg = 0x00009888, .val = 0x16E80C34 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext54__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext54__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext54__avg_gpu_core_frequency__max,mtlgt3__ext54__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6676, 24, NULL,mtlgt3__ext54__xve_slm_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6677, 32, NULL,mtlgt3__ext54__xve_slm_read_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6678, 40, NULL,mtlgt3__ext54__xve_slm_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6679, 48, NULL,mtlgt3__ext54__xve_slm_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext57_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext57";
   query->symbol_name = "Ext57";
   query->guid = "6f983509-03f1-463a-be88-3e4a40de40b4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28080000 },
         { .reg = 0x00009888, .val = 0x2C080000 },
         { .reg = 0x00009888, .val = 0x28280000 },
         { .reg = 0x00009888, .val = 0x2C280000 },
         { .reg = 0x00009888, .val = 0x28480000 },
         { .reg = 0x00009888, .val = 0x2C480000 },
         { .reg = 0x00009888, .val = 0x28680000 },
         { .reg = 0x00009888, .val = 0x2C680000 },
         { .reg = 0x00009888, .val = 0x06080204 },
         { .reg = 0x00009888, .val = 0x14080823 },
         { .reg = 0x00009888, .val = 0x16080C33 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x06280204 },
         { .reg = 0x00009888, .val = 0x10280823 },
         { .reg = 0x00009888, .val = 0x12280C33 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x06480204 },
         { .reg = 0x00009888, .val = 0x0C480823 },
         { .reg = 0x00009888, .val = 0x0E480C33 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x06680204 },
         { .reg = 0x00009888, .val = 0x08680823 },
         { .reg = 0x00009888, .val = 0x0A680C33 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFF00 },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext57__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext57__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext57__avg_gpu_core_frequency__max,mtlgt3__ext57__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5896, 24, NULL,mtlgt3__ext57__xve_slm_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5897, 32, NULL,mtlgt3__ext57__xve_slm_write_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5898, 40, NULL,mtlgt3__ext57__xve_slm_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5899, 48, NULL,mtlgt3__ext57__xve_slm_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext58_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext58";
   query->symbol_name = "Ext58";
   query->guid = "75d3fdde-e74d-4ec2-a7f0-f88fe5971af3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28880000 },
         { .reg = 0x00009888, .val = 0x2C880000 },
         { .reg = 0x00009888, .val = 0x28A80000 },
         { .reg = 0x00009888, .val = 0x2CA80000 },
         { .reg = 0x00009888, .val = 0x28C80000 },
         { .reg = 0x00009888, .val = 0x2CC80000 },
         { .reg = 0x00009888, .val = 0x28E80000 },
         { .reg = 0x00009888, .val = 0x2CE80000 },
         { .reg = 0x00009888, .val = 0x06880204 },
         { .reg = 0x00009888, .val = 0x08880823 },
         { .reg = 0x00009888, .val = 0x0A880C33 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x06A80204 },
         { .reg = 0x00009888, .val = 0x0CA80823 },
         { .reg = 0x00009888, .val = 0x0EA80C33 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x06C80204 },
         { .reg = 0x00009888, .val = 0x10C80823 },
         { .reg = 0x00009888, .val = 0x12C80C33 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E80204 },
         { .reg = 0x00009888, .val = 0x14E80823 },
         { .reg = 0x00009888, .val = 0x16E80C33 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext58__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext58__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext58__avg_gpu_core_frequency__max,mtlgt3__ext58__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6680, 24, NULL,mtlgt3__ext58__xve_slm_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6681, 32, NULL,mtlgt3__ext58__xve_slm_write_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6682, 40, NULL,mtlgt3__ext58__xve_slm_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6683, 48, NULL,mtlgt3__ext58__xve_slm_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext61_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext61";
   query->symbol_name = "Ext61";
   query->guid = "98c25532-687f-489a-b070-667edd3c41f9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x28280001 },
         { .reg = 0x00009888, .val = 0x2C280400 },
         { .reg = 0x00009888, .val = 0x2E280000 },
         { .reg = 0x00009888, .val = 0x28480001 },
         { .reg = 0x00009888, .val = 0x2C480400 },
         { .reg = 0x00009888, .val = 0x2E480000 },
         { .reg = 0x00009888, .val = 0x28680001 },
         { .reg = 0x00009888, .val = 0x2C680400 },
         { .reg = 0x00009888, .val = 0x2E680000 },
         { .reg = 0x00009888, .val = 0x06081A54 },
         { .reg = 0x00009888, .val = 0x14080A27 },
         { .reg = 0x00009888, .val = 0x16080E37 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x06281A54 },
         { .reg = 0x00009888, .val = 0x10280A27 },
         { .reg = 0x00009888, .val = 0x12280E37 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x06481A54 },
         { .reg = 0x00009888, .val = 0x0C480A27 },
         { .reg = 0x00009888, .val = 0x0E480E37 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x06681A54 },
         { .reg = 0x00009888, .val = 0x08680A27 },
         { .reg = 0x00009888, .val = 0x0A680E37 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFF00 },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext61__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext61__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext61__avg_gpu_core_frequency__max,mtlgt3__ext61__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5900, 24, NULL,mtlgt3__ext61__xve_slm_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5901, 32, NULL,mtlgt3__ext61__xve_slm_fence_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5902, 40, NULL,mtlgt3__ext61__xve_slm_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5903, 48, NULL,mtlgt3__ext61__xve_slm_fence_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext62_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext62";
   query->symbol_name = "Ext62";
   query->guid = "6ee28b50-5390-4655-af96-9d99569aee82";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28880001 },
         { .reg = 0x00009888, .val = 0x2C880400 },
         { .reg = 0x00009888, .val = 0x2E880000 },
         { .reg = 0x00009888, .val = 0x28A80001 },
         { .reg = 0x00009888, .val = 0x2CA80400 },
         { .reg = 0x00009888, .val = 0x2EA80000 },
         { .reg = 0x00009888, .val = 0x28C80001 },
         { .reg = 0x00009888, .val = 0x2CC80400 },
         { .reg = 0x00009888, .val = 0x2EC80000 },
         { .reg = 0x00009888, .val = 0x28E80001 },
         { .reg = 0x00009888, .val = 0x2CE80400 },
         { .reg = 0x00009888, .val = 0x2EE80000 },
         { .reg = 0x00009888, .val = 0x06881A54 },
         { .reg = 0x00009888, .val = 0x08880A27 },
         { .reg = 0x00009888, .val = 0x0A880E37 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x06A81A54 },
         { .reg = 0x00009888, .val = 0x0CA80A27 },
         { .reg = 0x00009888, .val = 0x0EA80E37 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x06C81A54 },
         { .reg = 0x00009888, .val = 0x10C80A27 },
         { .reg = 0x00009888, .val = 0x12C80E37 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E81A54 },
         { .reg = 0x00009888, .val = 0x14E80A27 },
         { .reg = 0x00009888, .val = 0x16E80E37 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext62__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext62__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext62__avg_gpu_core_frequency__max,mtlgt3__ext62__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6684, 24, NULL,mtlgt3__ext62__xve_slm_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6685, 32, NULL,mtlgt3__ext62__xve_slm_fence_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6686, 40, NULL,mtlgt3__ext62__xve_slm_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6687, 48, NULL,mtlgt3__ext62__xve_slm_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext65_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext65";
   query->symbol_name = "Ext65";
   query->guid = "89a4a65b-cbfa-4c75-99fb-e5d7f0def495";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28080001 },
         { .reg = 0x00009888, .val = 0x2C080400 },
         { .reg = 0x00009888, .val = 0x2E080000 },
         { .reg = 0x00009888, .val = 0x28280001 },
         { .reg = 0x00009888, .val = 0x2C280400 },
         { .reg = 0x00009888, .val = 0x2E280000 },
         { .reg = 0x00009888, .val = 0x06081A54 },
         { .reg = 0x00009888, .val = 0x0E0808A3 },
         { .reg = 0x00009888, .val = 0x10080CE8 },
         { .reg = 0x00009888, .val = 0x12080E32 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x06281A54 },
         { .reg = 0x00009888, .val = 0x082808A3 },
         { .reg = 0x00009888, .val = 0x0A280CE8 },
         { .reg = 0x00009888, .val = 0x0C280E32 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x000B0FFF },
         { .reg = 0x00009888, .val = 0x0009AFFF },
         { .reg = 0x00009888, .val = 0x020900AA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x020300AA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext65__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext65__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext65__avg_gpu_core_frequency__max,mtlgt3__ext65__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5904, 24, NULL,mtlgt3__ext65__xve_slm_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5905, 32, NULL,mtlgt3__ext65__xve_slm_atomic_message_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext66_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext66";
   query->symbol_name = "Ext66";
   query->guid = "99e44f76-928f-4835-866f-663e25c69f66";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28480001 },
         { .reg = 0x00009888, .val = 0x2C480400 },
         { .reg = 0x00009888, .val = 0x2E480000 },
         { .reg = 0x00009888, .val = 0x28680001 },
         { .reg = 0x00009888, .val = 0x2C680400 },
         { .reg = 0x00009888, .val = 0x2E680000 },
         { .reg = 0x00009888, .val = 0x06481A54 },
         { .reg = 0x00009888, .val = 0x0E4808A3 },
         { .reg = 0x00009888, .val = 0x10480CE8 },
         { .reg = 0x00009888, .val = 0x12480E32 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x06681A54 },
         { .reg = 0x00009888, .val = 0x086808A3 },
         { .reg = 0x00009888, .val = 0x0A680CE8 },
         { .reg = 0x00009888, .val = 0x0C680E32 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001F000 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AFFF },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x020300AA },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010002 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext66__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext66__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext66__avg_gpu_core_frequency__max,mtlgt3__ext66__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5906, 24, NULL,mtlgt3__ext66__xve_slm_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5907, 32, NULL,mtlgt3__ext66__xve_slm_atomic_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext67_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext67";
   query->symbol_name = "Ext67";
   query->guid = "f45dfc0c-70ef-48bd-83a2-30cf4a6ba0d5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28880001 },
         { .reg = 0x00009888, .val = 0x2C880400 },
         { .reg = 0x00009888, .val = 0x2E880000 },
         { .reg = 0x00009888, .val = 0x28A80001 },
         { .reg = 0x00009888, .val = 0x2CA80400 },
         { .reg = 0x00009888, .val = 0x2EA80000 },
         { .reg = 0x00009888, .val = 0x06881A54 },
         { .reg = 0x00009888, .val = 0x088808A3 },
         { .reg = 0x00009888, .val = 0x0A880CE8 },
         { .reg = 0x00009888, .val = 0x0C880E32 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x06A81A54 },
         { .reg = 0x00009888, .val = 0x0EA808A3 },
         { .reg = 0x00009888, .val = 0x10A80CE8 },
         { .reg = 0x00009888, .val = 0x12A80E32 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02210055 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02240055 },
         { .reg = 0x00009888, .val = 0x002B0FFF },
         { .reg = 0x00009888, .val = 0x0029FAAA },
         { .reg = 0x00009888, .val = 0x022900FF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x028200AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050FFF },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext67__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext67__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext67__avg_gpu_core_frequency__max,mtlgt3__ext67__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6688, 24, NULL,mtlgt3__ext67__xve_slm_atomic_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6689, 32, NULL,mtlgt3__ext67__xve_slm_atomic_message_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext68_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext68";
   query->symbol_name = "Ext68";
   query->guid = "eab0942c-5181-4caf-aeec-44d9a0b69ada";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x28C80001 },
         { .reg = 0x00009888, .val = 0x2CC80400 },
         { .reg = 0x00009888, .val = 0x2EC80000 },
         { .reg = 0x00009888, .val = 0x28E80001 },
         { .reg = 0x00009888, .val = 0x2CE80400 },
         { .reg = 0x00009888, .val = 0x2EE80000 },
         { .reg = 0x00009888, .val = 0x06C81A54 },
         { .reg = 0x00009888, .val = 0x08C808A3 },
         { .reg = 0x00009888, .val = 0x0AC80CE8 },
         { .reg = 0x00009888, .val = 0x0CC80E32 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x06E81A54 },
         { .reg = 0x00009888, .val = 0x0EE808A3 },
         { .reg = 0x00009888, .val = 0x10E80CE8 },
         { .reg = 0x00009888, .val = 0x12E80E32 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00210FFF },
         { .reg = 0x00009888, .val = 0x002A0AAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FAAA },
         { .reg = 0x00009888, .val = 0x028200FF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050FFF },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010400 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010020 },
         { .reg = 0x00009888, .val = 0x50010002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext68__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext68__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext68__avg_gpu_core_frequency__max,mtlgt3__ext68__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6690, 24, NULL,mtlgt3__ext68__xve_slm_atomic_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6691, 32, NULL,mtlgt3__ext68__xve_slm_atomic_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext73_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext73";
   query->symbol_name = "Ext73";
   query->guid = "d9d0c398-6429-4ba8-bc08-6e8556a5880f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1602E6C4 },
         { .reg = 0x00009888, .val = 0x1622E6C0 },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x0E020140 },
         { .reg = 0x00009888, .val = 0x100201C6 },
         { .reg = 0x00009888, .val = 0x12020048 },
         { .reg = 0x00009888, .val = 0x140200C2 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02085555 },
         { .reg = 0x00009888, .val = 0x0422001A },
         { .reg = 0x00009888, .val = 0x06220A00 },
         { .reg = 0x00009888, .val = 0x082201C6 },
         { .reg = 0x00009888, .val = 0x0A220048 },
         { .reg = 0x00009888, .val = 0x0C2200C2 },
         { .reg = 0x00009888, .val = 0x0E220004 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00285555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x0209AAAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext73__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext73__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext73__avg_gpu_core_frequency__max,mtlgt3__ext73__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5908, 24, percentage_max_float,mtlgt3__ext73__dataport_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5909, 28, percentage_max_float,mtlgt3__ext73__dataport_input_available_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext74_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext74";
   query->symbol_name = "Ext74";
   query->guid = "d91bf24f-08af-4d1d-b957-c2293923c9a4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1642E6C4 },
         { .reg = 0x00009888, .val = 0x1662E6C0 },
         { .reg = 0x00009888, .val = 0x0442001A },
         { .reg = 0x00009888, .val = 0x0E420140 },
         { .reg = 0x00009888, .val = 0x104201C6 },
         { .reg = 0x00009888, .val = 0x12420048 },
         { .reg = 0x00009888, .val = 0x144200C2 },
         { .reg = 0x00009888, .val = 0x02420000 },
         { .reg = 0x00009888, .val = 0x02485555 },
         { .reg = 0x00009888, .val = 0x0462001A },
         { .reg = 0x00009888, .val = 0x06620A00 },
         { .reg = 0x00009888, .val = 0x086201C6 },
         { .reg = 0x00009888, .val = 0x0A620048 },
         { .reg = 0x00009888, .val = 0x0C6200C2 },
         { .reg = 0x00009888, .val = 0x0E620004 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00685555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext74__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext74__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext74__avg_gpu_core_frequency__max,mtlgt3__ext74__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5910, 24, percentage_max_float,mtlgt3__ext74__dataport_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5911, 28, percentage_max_float,mtlgt3__ext74__dataport_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext75_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext75";
   query->symbol_name = "Ext75";
   query->guid = "b5c2eaef-cffa-490b-a80e-de2b37ca63d8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1682E6C0 },
         { .reg = 0x00009888, .val = 0x16A2E6C4 },
         { .reg = 0x00009888, .val = 0x0482001A },
         { .reg = 0x00009888, .val = 0x06820A00 },
         { .reg = 0x00009888, .val = 0x088201C6 },
         { .reg = 0x00009888, .val = 0x0A820048 },
         { .reg = 0x00009888, .val = 0x0C8200C2 },
         { .reg = 0x00009888, .val = 0x0E820004 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00885555 },
         { .reg = 0x00009888, .val = 0x04A2001A },
         { .reg = 0x00009888, .val = 0x0EA20140 },
         { .reg = 0x00009888, .val = 0x10A201C6 },
         { .reg = 0x00009888, .val = 0x12A20048 },
         { .reg = 0x00009888, .val = 0x14A200C2 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x02A85555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029AAAA },
         { .reg = 0x00009888, .val = 0x0229FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext75__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext75__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext75__avg_gpu_core_frequency__max,mtlgt3__ext75__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6692, 24, percentage_max_float,mtlgt3__ext75__dataport_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6693, 28, percentage_max_float,mtlgt3__ext75__dataport_input_available_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext76_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext76";
   query->symbol_name = "Ext76";
   query->guid = "d5cdafcf-483d-40f7-8dc9-feca73e94246";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x16C2E6C0 },
         { .reg = 0x00009888, .val = 0x16E2E6C4 },
         { .reg = 0x00009888, .val = 0x04C2001A },
         { .reg = 0x00009888, .val = 0x06C20A00 },
         { .reg = 0x00009888, .val = 0x08C201C6 },
         { .reg = 0x00009888, .val = 0x0AC20048 },
         { .reg = 0x00009888, .val = 0x0CC200C2 },
         { .reg = 0x00009888, .val = 0x0EC20004 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C85555 },
         { .reg = 0x00009888, .val = 0x04E2001A },
         { .reg = 0x00009888, .val = 0x0EE20140 },
         { .reg = 0x00009888, .val = 0x10E201C6 },
         { .reg = 0x00009888, .val = 0x12E20048 },
         { .reg = 0x00009888, .val = 0x14E200C2 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x02E85555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010020 },
         { .reg = 0x00009888, .val = 0x50010402 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010402 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext76__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext76__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext76__avg_gpu_core_frequency__max,mtlgt3__ext76__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6694, 24, percentage_max_float,mtlgt3__ext76__dataport_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6695, 28, percentage_max_float,mtlgt3__ext76__dataport_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext77_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext77";
   query->symbol_name = "Ext77";
   query->guid = "240802cf-de55-472f-9e0a-710270ae9487";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C02C000 },
         { .reg = 0x00009888, .val = 0x0C22C000 },
         { .reg = 0x00009888, .val = 0x0C42C491 },
         { .reg = 0x00009888, .val = 0x0C62C000 },
         { .reg = 0x00009888, .val = 0x04020100 },
         { .reg = 0x00009888, .val = 0x12020400 },
         { .reg = 0x00009888, .val = 0x14020491 },
         { .reg = 0x00009888, .val = 0x16020013 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009888, .val = 0x04220100 },
         { .reg = 0x00009888, .val = 0x0E220400 },
         { .reg = 0x00009888, .val = 0x10220491 },
         { .reg = 0x00009888, .val = 0x12220013 },
         { .reg = 0x00009888, .val = 0x02220000 },
         { .reg = 0x00009888, .val = 0x02280055 },
         { .reg = 0x00009888, .val = 0x04420100 },
         { .reg = 0x00009888, .val = 0x0A420400 },
         { .reg = 0x00009888, .val = 0x0E420013 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00485500 },
         { .reg = 0x00009888, .val = 0x04620100 },
         { .reg = 0x00009888, .val = 0x06622000 },
         { .reg = 0x00009888, .val = 0x08620491 },
         { .reg = 0x00009888, .val = 0x0A620013 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00680055 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFF00 },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext77__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext77__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext77__avg_gpu_core_frequency__max,mtlgt3__ext77__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5912, 24, percentage_max_float,mtlgt3__ext77__dataport_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5913, 28, percentage_max_float,mtlgt3__ext77__dataport_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5914, 32, percentage_max_float,mtlgt3__ext77__dataport_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5915, 36, percentage_max_float,mtlgt3__ext77__dataport_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext78_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext78";
   query->symbol_name = "Ext78";
   query->guid = "3dd49211-aa69-4711-87c2-97289ff9cfff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C82C000 },
         { .reg = 0x00009888, .val = 0x0CA2C491 },
         { .reg = 0x00009888, .val = 0x0CC2C000 },
         { .reg = 0x00009888, .val = 0x0CE2C000 },
         { .reg = 0x00009888, .val = 0x04820100 },
         { .reg = 0x00009888, .val = 0x06822000 },
         { .reg = 0x00009888, .val = 0x08820491 },
         { .reg = 0x00009888, .val = 0x0A820013 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x04A20100 },
         { .reg = 0x00009888, .val = 0x0AA20400 },
         { .reg = 0x00009888, .val = 0x0EA20013 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x04C20100 },
         { .reg = 0x00009888, .val = 0x0EC20400 },
         { .reg = 0x00009888, .val = 0x10C20491 },
         { .reg = 0x00009888, .val = 0x12C20013 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x04E20100 },
         { .reg = 0x00009888, .val = 0x12E20400 },
         { .reg = 0x00009888, .val = 0x14E20491 },
         { .reg = 0x00009888, .val = 0x16E20013 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext78__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext78__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext78__avg_gpu_core_frequency__max,mtlgt3__ext78__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6696, 24, percentage_max_float,mtlgt3__ext78__dataport_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6697, 28, percentage_max_float,mtlgt3__ext78__dataport_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6698, 32, percentage_max_float,mtlgt3__ext78__dataport_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6699, 36, percentage_max_float,mtlgt3__ext78__dataport_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext79_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext79";
   query->symbol_name = "Ext79";
   query->guid = "64aeba75-9dbe-4231-81f6-8c991b84c070";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C02A000 },
         { .reg = 0x00009888, .val = 0x0E02B5C0 },
         { .reg = 0x00009888, .val = 0x0C22A51A },
         { .reg = 0x00009888, .val = 0x0E22B01B },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x10020598 },
         { .reg = 0x00009888, .val = 0x12020559 },
         { .reg = 0x00009888, .val = 0x1402051A },
         { .reg = 0x00009888, .val = 0x1602001B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02085555 },
         { .reg = 0x00009888, .val = 0x04220B00 },
         { .reg = 0x00009888, .val = 0x06222E00 },
         { .reg = 0x00009888, .val = 0x08220598 },
         { .reg = 0x00009888, .val = 0x0A220559 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00285555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x0209AAAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext79__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext79__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext79__avg_gpu_core_frequency__max,mtlgt3__ext79__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5916, 24, NULL,mtlgt3__ext79__dataport_byte_read_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5917, 32, NULL,mtlgt3__ext79__dataport_byte_read_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext80_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext80";
   query->symbol_name = "Ext80";
   query->guid = "3b293ce5-af38-4ae2-96f4-a542d3c68d5e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C42A000 },
         { .reg = 0x00009888, .val = 0x0E42B5C0 },
         { .reg = 0x00009888, .val = 0x0C62A51A },
         { .reg = 0x00009888, .val = 0x0E62B01B },
         { .reg = 0x00009888, .val = 0x04420B00 },
         { .reg = 0x00009888, .val = 0x10420598 },
         { .reg = 0x00009888, .val = 0x12420559 },
         { .reg = 0x00009888, .val = 0x1442051A },
         { .reg = 0x00009888, .val = 0x1642001B },
         { .reg = 0x00009888, .val = 0x02420000 },
         { .reg = 0x00009888, .val = 0x02485555 },
         { .reg = 0x00009888, .val = 0x04620B00 },
         { .reg = 0x00009888, .val = 0x06622E00 },
         { .reg = 0x00009888, .val = 0x08620598 },
         { .reg = 0x00009888, .val = 0x0A620559 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00685555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext80__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext80__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext80__avg_gpu_core_frequency__max,mtlgt3__ext80__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5918, 24, NULL,mtlgt3__ext80__dataport_byte_read_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5919, 32, NULL,mtlgt3__ext80__dataport_byte_read_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext81_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext81";
   query->symbol_name = "Ext81";
   query->guid = "09516dce-66a0-499f-8457-97f78bb921e6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C82A51A },
         { .reg = 0x00009888, .val = 0x0E82B01B },
         { .reg = 0x00009888, .val = 0x0CA2A000 },
         { .reg = 0x00009888, .val = 0x0EA2B5C0 },
         { .reg = 0x00009888, .val = 0x04820B00 },
         { .reg = 0x00009888, .val = 0x06822E00 },
         { .reg = 0x00009888, .val = 0x08820598 },
         { .reg = 0x00009888, .val = 0x0A820559 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00885555 },
         { .reg = 0x00009888, .val = 0x04A20B00 },
         { .reg = 0x00009888, .val = 0x10A20598 },
         { .reg = 0x00009888, .val = 0x12A20559 },
         { .reg = 0x00009888, .val = 0x14A2051A },
         { .reg = 0x00009888, .val = 0x16A2001B },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x02A85555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029AAAA },
         { .reg = 0x00009888, .val = 0x0229FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext81__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext81__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext81__avg_gpu_core_frequency__max,mtlgt3__ext81__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6700, 24, NULL,mtlgt3__ext81__dataport_byte_read_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6701, 32, NULL,mtlgt3__ext81__dataport_byte_read_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext82_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext82";
   query->symbol_name = "Ext82";
   query->guid = "c0bdc35b-af55-4ac9-8078-f22578201756";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0CC2A51A },
         { .reg = 0x00009888, .val = 0x0EC2B01B },
         { .reg = 0x00009888, .val = 0x0CE2A000 },
         { .reg = 0x00009888, .val = 0x0EE2B5C0 },
         { .reg = 0x00009888, .val = 0x04C20B00 },
         { .reg = 0x00009888, .val = 0x06C22E00 },
         { .reg = 0x00009888, .val = 0x08C20598 },
         { .reg = 0x00009888, .val = 0x0AC20559 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C85555 },
         { .reg = 0x00009888, .val = 0x04E20B00 },
         { .reg = 0x00009888, .val = 0x10E20598 },
         { .reg = 0x00009888, .val = 0x12E20559 },
         { .reg = 0x00009888, .val = 0x14E2051A },
         { .reg = 0x00009888, .val = 0x16E2001B },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x02E85555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010020 },
         { .reg = 0x00009888, .val = 0x50010402 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010402 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext82__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext82__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext82__avg_gpu_core_frequency__max,mtlgt3__ext82__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6702, 24, NULL,mtlgt3__ext82__dataport_byte_read_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6703, 32, NULL,mtlgt3__ext82__dataport_byte_read_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext83_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext83";
   query->symbol_name = "Ext83";
   query->guid = "7f4b6bdf-4a28-4e6b-a67b-c9a0d320ddb8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C026800 },
         { .reg = 0x00009888, .val = 0x1E020001 },
         { .reg = 0x00009888, .val = 0x1C226800 },
         { .reg = 0x00009888, .val = 0x1E220001 },
         { .reg = 0x00009888, .val = 0x1C426800 },
         { .reg = 0x00009888, .val = 0x1E420001 },
         { .reg = 0x00009888, .val = 0x1C626800 },
         { .reg = 0x00009888, .val = 0x1E620001 },
         { .reg = 0x00009888, .val = 0x1C820400 },
         { .reg = 0x00009888, .val = 0x1E82001A },
         { .reg = 0x00009888, .val = 0x1CA20400 },
         { .reg = 0x00009888, .val = 0x1EA2001A },
         { .reg = 0x00009888, .val = 0x1CC20400 },
         { .reg = 0x00009888, .val = 0x1EC2001A },
         { .reg = 0x00009888, .val = 0x1CE20400 },
         { .reg = 0x00009888, .val = 0x1EE2001A },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x06020001 },
         { .reg = 0x00009888, .val = 0x0A020022 },
         { .reg = 0x00009888, .val = 0x0E020029 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00084040 },
         { .reg = 0x00009888, .val = 0x04220000 },
         { .reg = 0x00009888, .val = 0x06220001 },
         { .reg = 0x00009888, .val = 0x08220880 },
         { .reg = 0x00009888, .val = 0x0C220A40 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00281010 },
         { .reg = 0x00009888, .val = 0x04420000 },
         { .reg = 0x00009888, .val = 0x06420001 },
         { .reg = 0x00009888, .val = 0x08420022 },
         { .reg = 0x00009888, .val = 0x0C420029 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00480404 },
         { .reg = 0x00009888, .val = 0x04620000 },
         { .reg = 0x00009888, .val = 0x06624401 },
         { .reg = 0x00009888, .val = 0x0A620A40 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00680101 },
         { .reg = 0x00009888, .val = 0x04820000 },
         { .reg = 0x00009888, .val = 0x06820001 },
         { .reg = 0x00009888, .val = 0x12820021 },
         { .reg = 0x00009888, .val = 0x1682002A },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x02884040 },
         { .reg = 0x00009888, .val = 0x04A20000 },
         { .reg = 0x00009888, .val = 0x06A20001 },
         { .reg = 0x00009888, .val = 0x10A20840 },
         { .reg = 0x00009888, .val = 0x14A20A80 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x02A81010 },
         { .reg = 0x00009888, .val = 0x04C20000 },
         { .reg = 0x00009888, .val = 0x06C20001 },
         { .reg = 0x00009888, .val = 0x10C20021 },
         { .reg = 0x00009888, .val = 0x14C2002A },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x02C80404 },
         { .reg = 0x00009888, .val = 0x04E20000 },
         { .reg = 0x00009888, .val = 0x06E20001 },
         { .reg = 0x00009888, .val = 0x0EE20840 },
         { .reg = 0x00009888, .val = 0x12E20A80 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x02E80101 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015C5C },
         { .reg = 0x00009888, .val = 0x00045050 },
         { .reg = 0x00009888, .val = 0x000B00CC },
         { .reg = 0x00009888, .val = 0x0009B0B0 },
         { .reg = 0x00009888, .val = 0x000AA8A8 },
         { .reg = 0x00009888, .val = 0x02215C5C },
         { .reg = 0x00009888, .val = 0x02245050 },
         { .reg = 0x00009888, .val = 0x002BCC00 },
         { .reg = 0x00009888, .val = 0x0229B0B0 },
         { .reg = 0x00009888, .val = 0x022AA8A8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002ABAB },
         { .reg = 0x00009888, .val = 0x0282ABAB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010E00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010070 },
         { .reg = 0x00009888, .val = 0x5C010405 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010605 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010A00 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext83__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext83__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext83__avg_gpu_core_frequency__max,mtlgt3__ext83__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5920, 24, NULL,mtlgt3__ext83__dataport_byte_write_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5921, 32, NULL,mtlgt3__ext83__dataport_byte_write_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5922, 40, NULL,mtlgt3__ext83__dataport_byte_write_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5923, 48, NULL,mtlgt3__ext83__dataport_byte_write_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6704, 56, NULL,mtlgt3__ext83__dataport_byte_write_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6705, 64, NULL,mtlgt3__ext83__dataport_byte_write_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6706, 72, NULL,mtlgt3__ext83__dataport_byte_write_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6707, 80, NULL,mtlgt3__ext83__dataport_byte_write_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5924, 88, NULL,mtlgt3__ext83__dataport_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5925, 96, NULL,mtlgt3__ext83__dataport_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5926, 104, NULL,mtlgt3__ext83__dataport_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5927, 112, NULL,mtlgt3__ext83__dataport_texture_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6708, 120, NULL,mtlgt3__ext83__dataport_texture_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6709, 128, NULL,mtlgt3__ext83__dataport_texture_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6710, 136, NULL,mtlgt3__ext83__dataport_texture_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6711, 144, NULL,mtlgt3__ext83__dataport_texture_cache_access_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext85_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext85";
   query->symbol_name = "Ext85";
   query->guid = "e19c5430-c632-43eb-b27f-eeb3d405bfd8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x1C020000 },
         { .reg = 0x00009888, .val = 0x1822016A },
         { .reg = 0x00009888, .val = 0x1C220000 },
         { .reg = 0x00009888, .val = 0x1842016A },
         { .reg = 0x00009888, .val = 0x1C420000 },
         { .reg = 0x00009888, .val = 0x1862016A },
         { .reg = 0x00009888, .val = 0x1C620000 },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x100201C5 },
         { .reg = 0x00009888, .val = 0x1202000B },
         { .reg = 0x00009888, .val = 0x140209C0 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02081054 },
         { .reg = 0x00009888, .val = 0x0422002C },
         { .reg = 0x00009888, .val = 0x0C220140 },
         { .reg = 0x00009888, .val = 0x0E2202C7 },
         { .reg = 0x00009888, .val = 0x16220027 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x02220000 },
         { .reg = 0x00009888, .val = 0x00285000 },
         { .reg = 0x00009888, .val = 0x02284001 },
         { .reg = 0x00009888, .val = 0x0442002C },
         { .reg = 0x00009888, .val = 0x0A4201C5 },
         { .reg = 0x00009888, .val = 0x0C42000B },
         { .reg = 0x00009888, .val = 0x14420027 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x02420000 },
         { .reg = 0x00009888, .val = 0x00480540 },
         { .reg = 0x00009888, .val = 0x02480400 },
         { .reg = 0x00009888, .val = 0x0462002C },
         { .reg = 0x00009888, .val = 0x06620A00 },
         { .reg = 0x00009888, .val = 0x086202C7 },
         { .reg = 0x00009888, .val = 0x126209C0 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x02620000 },
         { .reg = 0x00009888, .val = 0x00680015 },
         { .reg = 0x00009888, .val = 0x02680100 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015FC0 },
         { .reg = 0x00009888, .val = 0x02015C55 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02045055 },
         { .reg = 0x00009888, .val = 0x000BCFC0 },
         { .reg = 0x00009888, .val = 0x0009F000 },
         { .reg = 0x00009888, .val = 0x0209E0AB },
         { .reg = 0x00009888, .val = 0x000AAA80 },
         { .reg = 0x00009888, .val = 0x020AA8AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AABF },
         { .reg = 0x00009888, .val = 0x0202ABAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010605 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010003 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010A00 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext85__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext85__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext85__avg_gpu_core_frequency__max,mtlgt3__ext85__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5928, 24, NULL,mtlgt3__ext85__xve_dataport_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5929, 32, NULL,mtlgt3__ext85__xve_dataport_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5930, 40, NULL,mtlgt3__ext85__xve_dataport_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5931, 48, NULL,mtlgt3__ext85__xve_dataport_read_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5932, 56, NULL,mtlgt3__ext85__dataport_texture_cache_hit_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5933, 64, NULL,mtlgt3__ext85__dataport_texture_cache_hit_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5934, 72, NULL,mtlgt3__ext85__dataport_texture_cache_hit_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5935, 80, NULL,mtlgt3__ext85__dataport_texture_cache_hit_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext86_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext86";
   query->symbol_name = "Ext86";
   query->guid = "d379e5f5-32f3-4a6b-957f-5ccf607dda00";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1882016A },
         { .reg = 0x00009888, .val = 0x1C820000 },
         { .reg = 0x00009888, .val = 0x18A2016A },
         { .reg = 0x00009888, .val = 0x1CA20000 },
         { .reg = 0x00009888, .val = 0x18C2016A },
         { .reg = 0x00009888, .val = 0x1CC20000 },
         { .reg = 0x00009888, .val = 0x18E2016A },
         { .reg = 0x00009888, .val = 0x1CE20000 },
         { .reg = 0x00009888, .val = 0x0482002C },
         { .reg = 0x00009888, .val = 0x06820A00 },
         { .reg = 0x00009888, .val = 0x088202C7 },
         { .reg = 0x00009888, .val = 0x16820027 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00880015 },
         { .reg = 0x00009888, .val = 0x02884000 },
         { .reg = 0x00009888, .val = 0x04A2002C },
         { .reg = 0x00009888, .val = 0x0AA201C5 },
         { .reg = 0x00009888, .val = 0x0CA2000B },
         { .reg = 0x00009888, .val = 0x14A209C0 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A80540 },
         { .reg = 0x00009888, .val = 0x02A81000 },
         { .reg = 0x00009888, .val = 0x04C2002C },
         { .reg = 0x00009888, .val = 0x0CC20140 },
         { .reg = 0x00009888, .val = 0x0EC202C7 },
         { .reg = 0x00009888, .val = 0x14C20027 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C85000 },
         { .reg = 0x00009888, .val = 0x02C80401 },
         { .reg = 0x00009888, .val = 0x04E2002C },
         { .reg = 0x00009888, .val = 0x10E201C5 },
         { .reg = 0x00009888, .val = 0x12E209CB },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x02E80154 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021F555 },
         { .reg = 0x00009888, .val = 0x02215C03 },
         { .reg = 0x00009888, .val = 0x00240555 },
         { .reg = 0x00009888, .val = 0x02245000 },
         { .reg = 0x00009888, .val = 0x002BC03F },
         { .reg = 0x00009888, .val = 0x00290FEA },
         { .reg = 0x00009888, .val = 0x0229B000 },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AA802 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282ABFE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A03 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010A05 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext86__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext86__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext86__avg_gpu_core_frequency__max,mtlgt3__ext86__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6712, 24, NULL,mtlgt3__ext86__xve_dataport_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6713, 32, NULL,mtlgt3__ext86__xve_dataport_read_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6714, 40, NULL,mtlgt3__ext86__xve_dataport_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6715, 48, NULL,mtlgt3__ext86__xve_dataport_read_message_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6716, 56, NULL,mtlgt3__ext86__dataport_texture_cache_hit_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6717, 64, NULL,mtlgt3__ext86__dataport_texture_cache_hit_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6718, 72, NULL,mtlgt3__ext86__dataport_texture_cache_hit_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6719, 80, NULL,mtlgt3__ext86__dataport_texture_cache_hit_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext87_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext87";
   query->symbol_name = "Ext87";
   query->guid = "3e86ea71-8695-4815-ac18-0fd4510541a1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x1822016A },
         { .reg = 0x00009888, .val = 0x1842016A },
         { .reg = 0x00009888, .val = 0x1862016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x10020206 },
         { .reg = 0x00009888, .val = 0x1202000B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02080054 },
         { .reg = 0x00009888, .val = 0x0422002C },
         { .reg = 0x00009888, .val = 0x0C220180 },
         { .reg = 0x00009888, .val = 0x0E2202C8 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x02220000 },
         { .reg = 0x00009888, .val = 0x00285000 },
         { .reg = 0x00009888, .val = 0x02280001 },
         { .reg = 0x00009888, .val = 0x0442002C },
         { .reg = 0x00009888, .val = 0x0A420206 },
         { .reg = 0x00009888, .val = 0x0C42000B },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00480540 },
         { .reg = 0x00009888, .val = 0x0462002C },
         { .reg = 0x00009888, .val = 0x06620C00 },
         { .reg = 0x00009888, .val = 0x086202C8 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00680015 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015FC0 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x000B0FC0 },
         { .reg = 0x00009888, .val = 0x0009F000 },
         { .reg = 0x00009888, .val = 0x020900AB },
         { .reg = 0x00009888, .val = 0x000AAA80 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AABF },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x020300AA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010605 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010003 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext87__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext87__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext87__avg_gpu_core_frequency__max,mtlgt3__ext87__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5936, 24, NULL,mtlgt3__ext87__xve_dataport_write_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5937, 32, NULL,mtlgt3__ext87__xve_dataport_write_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5938, 40, NULL,mtlgt3__ext87__xve_dataport_write_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5939, 48, NULL,mtlgt3__ext87__xve_dataport_write_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext88_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext88";
   query->symbol_name = "Ext88";
   query->guid = "31ad28aa-7425-4bb4-b1a3-423821d98d84";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1882016A },
         { .reg = 0x00009888, .val = 0x18A2016A },
         { .reg = 0x00009888, .val = 0x18C2016A },
         { .reg = 0x00009888, .val = 0x18E2016A },
         { .reg = 0x00009888, .val = 0x0482002C },
         { .reg = 0x00009888, .val = 0x06820C00 },
         { .reg = 0x00009888, .val = 0x088202C8 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00880015 },
         { .reg = 0x00009888, .val = 0x04A2002C },
         { .reg = 0x00009888, .val = 0x0AA20206 },
         { .reg = 0x00009888, .val = 0x0CA2000B },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A80540 },
         { .reg = 0x00009888, .val = 0x04C2002C },
         { .reg = 0x00009888, .val = 0x0CC20180 },
         { .reg = 0x00009888, .val = 0x0EC202C8 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C85000 },
         { .reg = 0x00009888, .val = 0x02C80001 },
         { .reg = 0x00009888, .val = 0x04E2002C },
         { .reg = 0x00009888, .val = 0x10E20206 },
         { .reg = 0x00009888, .val = 0x12E2000B },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x02E80054 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021F555 },
         { .reg = 0x00009888, .val = 0x02210003 },
         { .reg = 0x00009888, .val = 0x00240555 },
         { .reg = 0x00009888, .val = 0x002B003F },
         { .reg = 0x00009888, .val = 0x00290FEA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A0002 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x028200FE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050FFF },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A03 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0060001C },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x030000C4 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x18000604 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0xC0003004 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext88__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext88__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext88__avg_gpu_core_frequency__max,mtlgt3__ext88__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6720, 24, NULL,mtlgt3__ext88__xve_dataport_write_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6721, 32, NULL,mtlgt3__ext88__xve_dataport_write_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6722, 40, NULL,mtlgt3__ext88__xve_dataport_write_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6723, 48, NULL,mtlgt3__ext88__xve_dataport_write_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext91_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext91";
   query->symbol_name = "Ext91";
   query->guid = "a1963e82-2bad-44e2-9bb1-ee18657c09cd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1802016A },
         { .reg = 0x00009888, .val = 0x1822016A },
         { .reg = 0x00009888, .val = 0x1842016A },
         { .reg = 0x00009888, .val = 0x1862016A },
         { .reg = 0x00009888, .val = 0x0402002C },
         { .reg = 0x00009888, .val = 0x10020185 },
         { .reg = 0x00009888, .val = 0x1202000B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02080054 },
         { .reg = 0x00009888, .val = 0x0422002C },
         { .reg = 0x00009888, .val = 0x0C220140 },
         { .reg = 0x00009888, .val = 0x0E2202C6 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x02220000 },
         { .reg = 0x00009888, .val = 0x00285000 },
         { .reg = 0x00009888, .val = 0x02280001 },
         { .reg = 0x00009888, .val = 0x0442002C },
         { .reg = 0x00009888, .val = 0x0A420185 },
         { .reg = 0x00009888, .val = 0x0C42000B },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00480540 },
         { .reg = 0x00009888, .val = 0x0462002C },
         { .reg = 0x00009888, .val = 0x06620A00 },
         { .reg = 0x00009888, .val = 0x086202C6 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00680015 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015FC0 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040055 },
         { .reg = 0x00009888, .val = 0x000B0FC0 },
         { .reg = 0x00009888, .val = 0x0009F000 },
         { .reg = 0x00009888, .val = 0x020900AB },
         { .reg = 0x00009888, .val = 0x000AAA80 },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AABF },
         { .reg = 0x00009888, .val = 0x020200AA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x020300AA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010605 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010003 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext91__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext91__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext91__avg_gpu_core_frequency__max,mtlgt3__ext91__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5940, 24, NULL,mtlgt3__ext91__xve_dataport_atomic_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5941, 32, NULL,mtlgt3__ext91__xve_dataport_atomic_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5942, 40, NULL,mtlgt3__ext91__xve_dataport_atomic_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5943, 48, NULL,mtlgt3__ext91__xve_dataport_atomic_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext92_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext92";
   query->symbol_name = "Ext92";
   query->guid = "fdf0722d-cb2e-46bd-8c1f-a85c6fbca3ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1882016A },
         { .reg = 0x00009888, .val = 0x18A2016A },
         { .reg = 0x00009888, .val = 0x18C2016A },
         { .reg = 0x00009888, .val = 0x18E2016A },
         { .reg = 0x00009888, .val = 0x0482002C },
         { .reg = 0x00009888, .val = 0x06820A00 },
         { .reg = 0x00009888, .val = 0x088202C6 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00880015 },
         { .reg = 0x00009888, .val = 0x04A2002C },
         { .reg = 0x00009888, .val = 0x0AA20185 },
         { .reg = 0x00009888, .val = 0x0CA2000B },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A80540 },
         { .reg = 0x00009888, .val = 0x04C2002C },
         { .reg = 0x00009888, .val = 0x0CC20140 },
         { .reg = 0x00009888, .val = 0x0EC202C6 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C85000 },
         { .reg = 0x00009888, .val = 0x02C80001 },
         { .reg = 0x00009888, .val = 0x04E2002C },
         { .reg = 0x00009888, .val = 0x10E20185 },
         { .reg = 0x00009888, .val = 0x12E2000B },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x02E80054 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021F555 },
         { .reg = 0x00009888, .val = 0x02210003 },
         { .reg = 0x00009888, .val = 0x00240555 },
         { .reg = 0x00009888, .val = 0x002B003F },
         { .reg = 0x00009888, .val = 0x00290FEA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A0002 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x028200FE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050FFF },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A03 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000021 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x00000101 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000801 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00004001 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext92__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext92__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext92__avg_gpu_core_frequency__max,mtlgt3__ext92__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6724, 24, NULL,mtlgt3__ext92__xve_dataport_atomic_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6725, 32, NULL,mtlgt3__ext92__xve_dataport_atomic_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6726, 40, NULL,mtlgt3__ext92__xve_dataport_atomic_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6727, 48, NULL,mtlgt3__ext92__xve_dataport_atomic_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext93_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext93";
   query->symbol_name = "Ext93";
   query->guid = "e0810ece-3bb5-4786-871b-b504faa00ba7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C02A000 },
         { .reg = 0x00009888, .val = 0x0E02B5C0 },
         { .reg = 0x00009888, .val = 0x0C22A51A },
         { .reg = 0x00009888, .val = 0x0E22B01B },
         { .reg = 0x00009888, .val = 0x04020B00 },
         { .reg = 0x00009888, .val = 0x10020598 },
         { .reg = 0x00009888, .val = 0x12020559 },
         { .reg = 0x00009888, .val = 0x1402051A },
         { .reg = 0x00009888, .val = 0x1602001B },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x02085555 },
         { .reg = 0x00009888, .val = 0x04220B00 },
         { .reg = 0x00009888, .val = 0x06222E00 },
         { .reg = 0x00009888, .val = 0x08220598 },
         { .reg = 0x00009888, .val = 0x0A220559 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00285555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x0209AAAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext93__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext93__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext93__avg_gpu_core_frequency__max,mtlgt3__ext93__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5944, 24, NULL,mtlgt3__ext93__xve_dataport_register_response_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5945, 32, NULL,mtlgt3__ext93__xve_dataport_register_response_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext94_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext94";
   query->symbol_name = "Ext94";
   query->guid = "8697d9f7-3085-4ae7-b88d-e77697972732";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C42A000 },
         { .reg = 0x00009888, .val = 0x0E42B5C0 },
         { .reg = 0x00009888, .val = 0x0C62A51A },
         { .reg = 0x00009888, .val = 0x0E62B01B },
         { .reg = 0x00009888, .val = 0x04420B00 },
         { .reg = 0x00009888, .val = 0x10420598 },
         { .reg = 0x00009888, .val = 0x12420559 },
         { .reg = 0x00009888, .val = 0x1442051A },
         { .reg = 0x00009888, .val = 0x1642001B },
         { .reg = 0x00009888, .val = 0x02420000 },
         { .reg = 0x00009888, .val = 0x02485555 },
         { .reg = 0x00009888, .val = 0x04620B00 },
         { .reg = 0x00009888, .val = 0x06622E00 },
         { .reg = 0x00009888, .val = 0x08620598 },
         { .reg = 0x00009888, .val = 0x0A620559 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00685555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext94__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext94__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext94__avg_gpu_core_frequency__max,mtlgt3__ext94__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5946, 24, NULL,mtlgt3__ext94__xve_dataport_register_response_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5947, 28, NULL,mtlgt3__ext94__xve_dataport_register_response_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext95_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext95";
   query->symbol_name = "Ext95";
   query->guid = "d059b804-fc25-4cbc-9682-ebc806a0d423";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0C82A51A },
         { .reg = 0x00009888, .val = 0x0E82B01B },
         { .reg = 0x00009888, .val = 0x0CA2A000 },
         { .reg = 0x00009888, .val = 0x0EA2B5C0 },
         { .reg = 0x00009888, .val = 0x04820B00 },
         { .reg = 0x00009888, .val = 0x06822E00 },
         { .reg = 0x00009888, .val = 0x08820598 },
         { .reg = 0x00009888, .val = 0x0A820559 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00885555 },
         { .reg = 0x00009888, .val = 0x04A20B00 },
         { .reg = 0x00009888, .val = 0x10A20598 },
         { .reg = 0x00009888, .val = 0x12A20559 },
         { .reg = 0x00009888, .val = 0x14A2051A },
         { .reg = 0x00009888, .val = 0x16A2001B },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x02A85555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029AAAA },
         { .reg = 0x00009888, .val = 0x0229FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext95__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext95__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext95__avg_gpu_core_frequency__max,mtlgt3__ext95__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6728, 24, NULL,mtlgt3__ext95__xve_dataport_register_response_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6729, 28, NULL,mtlgt3__ext95__xve_dataport_register_response_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext96_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext96";
   query->symbol_name = "Ext96";
   query->guid = "ca3c5e8c-b83a-474f-85fa-af7572a1ce27";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0CC2A51A },
         { .reg = 0x00009888, .val = 0x0EC2B01B },
         { .reg = 0x00009888, .val = 0x0CE2A000 },
         { .reg = 0x00009888, .val = 0x0EE2B5C0 },
         { .reg = 0x00009888, .val = 0x04C20B00 },
         { .reg = 0x00009888, .val = 0x06C22E00 },
         { .reg = 0x00009888, .val = 0x08C20598 },
         { .reg = 0x00009888, .val = 0x0AC20559 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C85555 },
         { .reg = 0x00009888, .val = 0x04E20B00 },
         { .reg = 0x00009888, .val = 0x10E20598 },
         { .reg = 0x00009888, .val = 0x12E20559 },
         { .reg = 0x00009888, .val = 0x14E2051A },
         { .reg = 0x00009888, .val = 0x16E2001B },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x02E85555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010020 },
         { .reg = 0x00009888, .val = 0x50010402 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010402 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext96__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext96__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext96__avg_gpu_core_frequency__max,mtlgt3__ext96__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6730, 24, NULL,mtlgt3__ext96__xve_dataport_register_response_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6731, 28, NULL,mtlgt3__ext96__xve_dataport_register_response_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext97_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext97";
   query->symbol_name = "Ext97";
   query->guid = "fbed5532-2b4f-4194-b856-0404c387b2e4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1602EDC0 },
         { .reg = 0x00009888, .val = 0x1622EDC0 },
         { .reg = 0x00009888, .val = 0x1642EDC0 },
         { .reg = 0x00009888, .val = 0x1662EDC0 },
         { .reg = 0x00009888, .val = 0x1682BF4F },
         { .reg = 0x00009888, .val = 0x16A2BF40 },
         { .reg = 0x00009888, .val = 0x16C2BF40 },
         { .reg = 0x00009888, .val = 0x16E2BF40 },
         { .reg = 0x00009888, .val = 0x0402001A },
         { .reg = 0x00009888, .val = 0x0C0201C0 },
         { .reg = 0x00009888, .val = 0x0E02000A },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00085000 },
         { .reg = 0x00009888, .val = 0x0422001A },
         { .reg = 0x00009888, .val = 0x0A2201C0 },
         { .reg = 0x00009888, .val = 0x0C22000A },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00280500 },
         { .reg = 0x00009888, .val = 0x0442001A },
         { .reg = 0x00009888, .val = 0x084201C0 },
         { .reg = 0x00009888, .val = 0x0A42000A },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00480050 },
         { .reg = 0x00009888, .val = 0x0462001A },
         { .reg = 0x00009888, .val = 0x06620E00 },
         { .reg = 0x00009888, .val = 0x0862000A },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00680005 },
         { .reg = 0x00009888, .val = 0x0482001A },
         { .reg = 0x00009888, .val = 0x14820080 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x02885000 },
         { .reg = 0x00009888, .val = 0x04A2001A },
         { .reg = 0x00009888, .val = 0x12A20080 },
         { .reg = 0x00009888, .val = 0x14A2000F },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x02A80500 },
         { .reg = 0x00009888, .val = 0x04C2001A },
         { .reg = 0x00009888, .val = 0x10C20080 },
         { .reg = 0x00009888, .val = 0x12C2000F },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x02C80050 },
         { .reg = 0x00009888, .val = 0x04E2001A },
         { .reg = 0x00009888, .val = 0x0EE20080 },
         { .reg = 0x00009888, .val = 0x10E2000F },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x02E80005 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x000155F0 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x000B00F0 },
         { .reg = 0x00009888, .val = 0x0009AF00 },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x022155F0 },
         { .reg = 0x00009888, .val = 0x02245500 },
         { .reg = 0x00009888, .val = 0x002BF000 },
         { .reg = 0x00009888, .val = 0x0229AF00 },
         { .reg = 0x00009888, .val = 0x022AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAF },
         { .reg = 0x00009888, .val = 0x0282AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010E00 },
         { .reg = 0x00009888, .val = 0x56010070 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext97__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext97__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext97__avg_gpu_core_frequency__max,mtlgt3__ext97__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5948, 24, NULL,mtlgt3__ext97__xve_dataport_register_request_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5949, 32, NULL,mtlgt3__ext97__xve_dataport_register_request_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5950, 40, NULL,mtlgt3__ext97__xve_dataport_register_request_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5951, 48, NULL,mtlgt3__ext97__xve_dataport_register_request_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6732, 56, NULL,mtlgt3__ext97__xve_dataport_register_request_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6733, 64, NULL,mtlgt3__ext97__xve_dataport_register_request_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6734, 72, NULL,mtlgt3__ext97__xve_dataport_register_request_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6735, 80, NULL,mtlgt3__ext97__xve_dataport_register_request_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext98_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext98";
   query->symbol_name = "Ext98";
   query->guid = "4c975484-c2f5-4f29-b8fa-8ec1068de77a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x14033000 },
         { .reg = 0x00009888, .val = 0x14233000 },
         { .reg = 0x00009888, .val = 0x14433000 },
         { .reg = 0x00009888, .val = 0x14633000 },
         { .reg = 0x00009888, .val = 0x02015500 },
         { .reg = 0x00009888, .val = 0x02025500 },
         { .reg = 0x00009888, .val = 0x10030450 },
         { .reg = 0x00009888, .val = 0x120304D2 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02085500 },
         { .reg = 0x00009888, .val = 0x02210055 },
         { .reg = 0x00009888, .val = 0x02220055 },
         { .reg = 0x00009888, .val = 0x0C230450 },
         { .reg = 0x00009888, .val = 0x0E2304D2 },
         { .reg = 0x00009888, .val = 0x04230000 },
         { .reg = 0x00009888, .val = 0x02230000 },
         { .reg = 0x00009888, .val = 0x02280055 },
         { .reg = 0x00009888, .val = 0x00415500 },
         { .reg = 0x00009888, .val = 0x00425500 },
         { .reg = 0x00009888, .val = 0x08430450 },
         { .reg = 0x00009888, .val = 0x0A4304D2 },
         { .reg = 0x00009888, .val = 0x04430000 },
         { .reg = 0x00009888, .val = 0x00430000 },
         { .reg = 0x00009888, .val = 0x00485500 },
         { .reg = 0x00009888, .val = 0x00610055 },
         { .reg = 0x00009888, .val = 0x00620055 },
         { .reg = 0x00009888, .val = 0x04630450 },
         { .reg = 0x00009888, .val = 0x066304D2 },
         { .reg = 0x00009888, .val = 0x00630000 },
         { .reg = 0x00009888, .val = 0x00680055 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFF00 },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext98__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext98__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext98__avg_gpu_core_frequency__max,mtlgt3__ext98__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5952, 24, percentage_max_float,mtlgt3__ext98__sampler_output_ready_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5953, 28, percentage_max_float,mtlgt3__ext98__sampler_output_ready_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5954, 32, percentage_max_float,mtlgt3__ext98__sampler_output_ready_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5955, 36, percentage_max_float,mtlgt3__ext98__sampler_output_ready_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext99_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext99";
   query->symbol_name = "Ext99";
   query->guid = "13017c9d-9d3a-41d1-8f9c-2eafdcbefab4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x14833000 },
         { .reg = 0x00009888, .val = 0x14A33000 },
         { .reg = 0x00009888, .val = 0x14C33000 },
         { .reg = 0x00009888, .val = 0x14E33000 },
         { .reg = 0x00009888, .val = 0x00810055 },
         { .reg = 0x00009888, .val = 0x00820055 },
         { .reg = 0x00009888, .val = 0x04830450 },
         { .reg = 0x00009888, .val = 0x068304D2 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x00A15500 },
         { .reg = 0x00009888, .val = 0x00A25500 },
         { .reg = 0x00009888, .val = 0x08A30450 },
         { .reg = 0x00009888, .val = 0x0AA304D2 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x02C10055 },
         { .reg = 0x00009888, .val = 0x02C20055 },
         { .reg = 0x00009888, .val = 0x0CC30450 },
         { .reg = 0x00009888, .val = 0x0EC304D2 },
         { .reg = 0x00009888, .val = 0x04C30000 },
         { .reg = 0x00009888, .val = 0x02C30000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x02E15500 },
         { .reg = 0x00009888, .val = 0x02E25500 },
         { .reg = 0x00009888, .val = 0x10E30450 },
         { .reg = 0x00009888, .val = 0x12E304D2 },
         { .reg = 0x00009888, .val = 0x04E30000 },
         { .reg = 0x00009888, .val = 0x02E30000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext99__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext99__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext99__avg_gpu_core_frequency__max,mtlgt3__ext99__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6736, 24, percentage_max_float,mtlgt3__ext99__sampler_output_ready_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6737, 28, percentage_max_float,mtlgt3__ext99__sampler_output_ready_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6738, 32, percentage_max_float,mtlgt3__ext99__sampler_output_ready_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6739, 36, percentage_max_float,mtlgt3__ext99__sampler_output_ready_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext100_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext100";
   query->symbol_name = "Ext100";
   query->guid = "a7ef0e01-74c3-48c5-8d0f-00241111cf69";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C010013 },
         { .reg = 0x00009888, .val = 0x1C210013 },
         { .reg = 0x00009888, .val = 0x1C410013 },
         { .reg = 0x00009888, .val = 0x1C610013 },
         { .reg = 0x00009888, .val = 0x04012000 },
         { .reg = 0x00009888, .val = 0x06010004 },
         { .reg = 0x00009888, .val = 0x0C010900 },
         { .reg = 0x00009888, .val = 0x0E010023 },
         { .reg = 0x00009888, .val = 0x16010029 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x00025000 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x00085000 },
         { .reg = 0x00009888, .val = 0x02084000 },
         { .reg = 0x00009888, .val = 0x04212000 },
         { .reg = 0x00009888, .val = 0x06210004 },
         { .reg = 0x00009888, .val = 0x0A210900 },
         { .reg = 0x00009888, .val = 0x0C210023 },
         { .reg = 0x00009888, .val = 0x14210A40 },
         { .reg = 0x00009888, .val = 0x00210000 },
         { .reg = 0x00009888, .val = 0x02210000 },
         { .reg = 0x00009888, .val = 0x00220500 },
         { .reg = 0x00009888, .val = 0x02221000 },
         { .reg = 0x00009888, .val = 0x00280500 },
         { .reg = 0x00009888, .val = 0x02281000 },
         { .reg = 0x00009888, .val = 0x04412000 },
         { .reg = 0x00009888, .val = 0x06410004 },
         { .reg = 0x00009888, .val = 0x08410900 },
         { .reg = 0x00009888, .val = 0x0A410023 },
         { .reg = 0x00009888, .val = 0x14410029 },
         { .reg = 0x00009888, .val = 0x00410000 },
         { .reg = 0x00009888, .val = 0x02410000 },
         { .reg = 0x00009888, .val = 0x00420050 },
         { .reg = 0x00009888, .val = 0x02420400 },
         { .reg = 0x00009888, .val = 0x00480050 },
         { .reg = 0x00009888, .val = 0x02480400 },
         { .reg = 0x00009888, .val = 0x04612000 },
         { .reg = 0x00009888, .val = 0x06611204 },
         { .reg = 0x00009888, .val = 0x08610023 },
         { .reg = 0x00009888, .val = 0x12610A40 },
         { .reg = 0x00009888, .val = 0x00610000 },
         { .reg = 0x00009888, .val = 0x02610000 },
         { .reg = 0x00009888, .val = 0x00620005 },
         { .reg = 0x00009888, .val = 0x02620100 },
         { .reg = 0x00009888, .val = 0x00680005 },
         { .reg = 0x00009888, .val = 0x02680100 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x000155F0 },
         { .reg = 0x00009888, .val = 0x02015C00 },
         { .reg = 0x00009888, .val = 0x00045500 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x000BC0F0 },
         { .reg = 0x00009888, .val = 0x0009AF00 },
         { .reg = 0x00009888, .val = 0x0209B000 },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x020AA800 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAF },
         { .reg = 0x00009888, .val = 0x0202AB00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015500 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AA00 },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x50010A00 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext100__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext100__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext100__avg_gpu_core_frequency__max,mtlgt3__ext100__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5956, 24, percentage_max_float,mtlgt3__ext100__sampler_memory_latency_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5957, 28, percentage_max_float,mtlgt3__ext100__sampler_memory_latency_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5958, 32, percentage_max_float,mtlgt3__ext100__sampler_memory_latency_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5959, 36, percentage_max_float,mtlgt3__ext100__sampler_memory_latency_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5960, 40, percentage_max_float,mtlgt3__ext100__sampler_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5961, 44, percentage_max_float,mtlgt3__ext100__sampler_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5962, 48, percentage_max_float,mtlgt3__ext100__sampler_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5963, 52, percentage_max_float,mtlgt3__ext100__sampler_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext101_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext101";
   query->symbol_name = "Ext101";
   query->guid = "7e86b43f-715e-419a-83eb-e8777fd7c77a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C810013 },
         { .reg = 0x00009888, .val = 0x1CA10013 },
         { .reg = 0x00009888, .val = 0x1CC10013 },
         { .reg = 0x00009888, .val = 0x1CE10013 },
         { .reg = 0x00009888, .val = 0x04812000 },
         { .reg = 0x00009888, .val = 0x06811204 },
         { .reg = 0x00009888, .val = 0x08810023 },
         { .reg = 0x00009888, .val = 0x16810029 },
         { .reg = 0x00009888, .val = 0x00810000 },
         { .reg = 0x00009888, .val = 0x02810000 },
         { .reg = 0x00009888, .val = 0x00820005 },
         { .reg = 0x00009888, .val = 0x02824000 },
         { .reg = 0x00009888, .val = 0x00880005 },
         { .reg = 0x00009888, .val = 0x02884000 },
         { .reg = 0x00009888, .val = 0x04A12000 },
         { .reg = 0x00009888, .val = 0x06A10004 },
         { .reg = 0x00009888, .val = 0x08A10900 },
         { .reg = 0x00009888, .val = 0x0AA10023 },
         { .reg = 0x00009888, .val = 0x14A10A40 },
         { .reg = 0x00009888, .val = 0x00A10000 },
         { .reg = 0x00009888, .val = 0x02A10000 },
         { .reg = 0x00009888, .val = 0x00A20050 },
         { .reg = 0x00009888, .val = 0x02A21000 },
         { .reg = 0x00009888, .val = 0x00A80050 },
         { .reg = 0x00009888, .val = 0x02A81000 },
         { .reg = 0x00009888, .val = 0x04C12000 },
         { .reg = 0x00009888, .val = 0x06C10004 },
         { .reg = 0x00009888, .val = 0x0AC10900 },
         { .reg = 0x00009888, .val = 0x0CC10023 },
         { .reg = 0x00009888, .val = 0x14C10029 },
         { .reg = 0x00009888, .val = 0x00C10000 },
         { .reg = 0x00009888, .val = 0x02C10000 },
         { .reg = 0x00009888, .val = 0x00C20500 },
         { .reg = 0x00009888, .val = 0x02C20400 },
         { .reg = 0x00009888, .val = 0x00C80500 },
         { .reg = 0x00009888, .val = 0x02C80400 },
         { .reg = 0x00009888, .val = 0x04E12000 },
         { .reg = 0x00009888, .val = 0x06E10004 },
         { .reg = 0x00009888, .val = 0x0CE10900 },
         { .reg = 0x00009888, .val = 0x0EE10023 },
         { .reg = 0x00009888, .val = 0x12E10A40 },
         { .reg = 0x00009888, .val = 0x00E10000 },
         { .reg = 0x00009888, .val = 0x02E10000 },
         { .reg = 0x00009888, .val = 0x00E25000 },
         { .reg = 0x00009888, .val = 0x02E20100 },
         { .reg = 0x00009888, .val = 0x00E85000 },
         { .reg = 0x00009888, .val = 0x02E80100 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00210F55 },
         { .reg = 0x00009888, .val = 0x02215C00 },
         { .reg = 0x00009888, .val = 0x00240055 },
         { .reg = 0x00009888, .val = 0x02245000 },
         { .reg = 0x00009888, .val = 0x002BC00F },
         { .reg = 0x00009888, .val = 0x002900FA },
         { .reg = 0x00009888, .val = 0x0229B000 },
         { .reg = 0x00009888, .val = 0x002A0AAA },
         { .reg = 0x00009888, .val = 0x022AA800 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FAAA },
         { .reg = 0x00009888, .val = 0x0282AB00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F0FF },
         { .reg = 0x00009888, .val = 0x0002F0FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015500 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035500 },
         { .reg = 0x00009888, .val = 0x0004F0FF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010A03 },
         { .reg = 0x00009888, .val = 0x5E010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x50010A00 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000600 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext101__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext101__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext101__avg_gpu_core_frequency__max,mtlgt3__ext101__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6740, 24, percentage_max_float,mtlgt3__ext101__sampler_memory_latency_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6741, 28, percentage_max_float,mtlgt3__ext101__sampler_memory_latency_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6742, 32, percentage_max_float,mtlgt3__ext101__sampler_memory_latency_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6743, 36, percentage_max_float,mtlgt3__ext101__sampler_memory_latency_stall_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6744, 40, percentage_max_float,mtlgt3__ext101__sampler_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6745, 44, percentage_max_float,mtlgt3__ext101__sampler_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6746, 48, percentage_max_float,mtlgt3__ext101__sampler_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6747, 52, percentage_max_float,mtlgt3__ext101__sampler_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext102_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext102";
   query->symbol_name = "Ext102";
   query->guid = "1fb36f5f-04a3-412f-a6ca-80233bf408a0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C070000 },
         { .reg = 0x00009888, .val = 0x2C270000 },
         { .reg = 0x00009888, .val = 0x2C470000 },
         { .reg = 0x00009888, .val = 0x2C670000 },
         { .reg = 0x00009888, .val = 0x2C870000 },
         { .reg = 0x00009888, .val = 0x2CA70000 },
         { .reg = 0x00009888, .val = 0x2CC70000 },
         { .reg = 0x00009888, .val = 0x2CE70000 },
         { .reg = 0x00009888, .val = 0x0207000A },
         { .reg = 0x00009888, .val = 0x06070940 },
         { .reg = 0x00009888, .val = 0x0A070900 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x00088080 },
         { .reg = 0x00009888, .val = 0x0227000A },
         { .reg = 0x00009888, .val = 0x06270025 },
         { .reg = 0x00009888, .val = 0x0A270024 },
         { .reg = 0x00009888, .val = 0x04270000 },
         { .reg = 0x00009888, .val = 0x00282020 },
         { .reg = 0x00009888, .val = 0x0247000A },
         { .reg = 0x00009888, .val = 0x04470940 },
         { .reg = 0x00009888, .val = 0x08470900 },
         { .reg = 0x00009888, .val = 0x00480808 },
         { .reg = 0x00009888, .val = 0x0267000A },
         { .reg = 0x00009888, .val = 0x04670025 },
         { .reg = 0x00009888, .val = 0x08670024 },
         { .reg = 0x00009888, .val = 0x00680202 },
         { .reg = 0x00009888, .val = 0x0287000A },
         { .reg = 0x00009888, .val = 0x0E870900 },
         { .reg = 0x00009888, .val = 0x12870940 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x02888080 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x0EA70024 },
         { .reg = 0x00009888, .val = 0x12A70025 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x02A82020 },
         { .reg = 0x00009888, .val = 0x02C7000A },
         { .reg = 0x00009888, .val = 0x0CC70900 },
         { .reg = 0x00009888, .val = 0x10C70940 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x02C80808 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x0CE70024 },
         { .reg = 0x00009888, .val = 0x10E70025 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x02E80202 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015C5C },
         { .reg = 0x00009888, .val = 0x00045050 },
         { .reg = 0x00009888, .val = 0x000B00CC },
         { .reg = 0x00009888, .val = 0x0009B0B0 },
         { .reg = 0x00009888, .val = 0x000AA8A8 },
         { .reg = 0x00009888, .val = 0x02215C5C },
         { .reg = 0x00009888, .val = 0x02245050 },
         { .reg = 0x00009888, .val = 0x002BCC00 },
         { .reg = 0x00009888, .val = 0x0229B0B0 },
         { .reg = 0x00009888, .val = 0x022AA8A8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002ABAB },
         { .reg = 0x00009888, .val = 0x0282ABAB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010E00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010070 },
         { .reg = 0x00009888, .val = 0x5C010405 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010605 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010A00 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext102__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext102__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext102__avg_gpu_core_frequency__max,mtlgt3__ext102__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5964, 24, percentage_max_float,mtlgt3__ext102__thread_dispatch_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5965, 28, percentage_max_float,mtlgt3__ext102__thread_dispatch_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5966, 32, percentage_max_float,mtlgt3__ext102__thread_dispatch_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5967, 36, percentage_max_float,mtlgt3__ext102__thread_dispatch_stall_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5968, 40, percentage_max_float,mtlgt3__ext102__thread_dispatch_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5969, 44, percentage_max_float,mtlgt3__ext102__thread_dispatch_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5970, 48, percentage_max_float,mtlgt3__ext102__thread_dispatch_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5971, 52, percentage_max_float,mtlgt3__ext102__thread_dispatch_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6748, 56, percentage_max_float,mtlgt3__ext102__thread_dispatch_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6749, 60, percentage_max_float,mtlgt3__ext102__thread_dispatch_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6750, 64, percentage_max_float,mtlgt3__ext102__thread_dispatch_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6751, 68, percentage_max_float,mtlgt3__ext102__thread_dispatch_stall_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6752, 72, percentage_max_float,mtlgt3__ext102__thread_dispatch_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6753, 76, percentage_max_float,mtlgt3__ext102__thread_dispatch_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6754, 80, percentage_max_float,mtlgt3__ext102__thread_dispatch_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6755, 84, percentage_max_float,mtlgt3__ext102__thread_dispatch_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext103_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext103";
   query->symbol_name = "Ext103";
   query->guid = "5228137b-8e8d-4d67-b195-d5f64a88f5f0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18030004 },
         { .reg = 0x00009888, .val = 0x18230004 },
         { .reg = 0x00009888, .val = 0x18430004 },
         { .reg = 0x00009888, .val = 0x18630004 },
         { .reg = 0x00009888, .val = 0x18830004 },
         { .reg = 0x00009888, .val = 0x18A30004 },
         { .reg = 0x00009888, .val = 0x18C30004 },
         { .reg = 0x00009888, .val = 0x18E30004 },
         { .reg = 0x00009888, .val = 0x02010101 },
         { .reg = 0x00009888, .val = 0x02020101 },
         { .reg = 0x00009888, .val = 0x0C030032 },
         { .reg = 0x00009888, .val = 0x10030033 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x02030000 },
         { .reg = 0x00009888, .val = 0x02080101 },
         { .reg = 0x00009888, .val = 0x02210404 },
         { .reg = 0x00009888, .val = 0x02220404 },
         { .reg = 0x00009888, .val = 0x0C230C80 },
         { .reg = 0x00009888, .val = 0x10230CC0 },
         { .reg = 0x00009888, .val = 0x04230000 },
         { .reg = 0x00009888, .val = 0x02230000 },
         { .reg = 0x00009888, .val = 0x02280404 },
         { .reg = 0x00009888, .val = 0x02411010 },
         { .reg = 0x00009888, .val = 0x02421010 },
         { .reg = 0x00009888, .val = 0x0E430032 },
         { .reg = 0x00009888, .val = 0x12430033 },
         { .reg = 0x00009888, .val = 0x04430000 },
         { .reg = 0x00009888, .val = 0x02430000 },
         { .reg = 0x00009888, .val = 0x02481010 },
         { .reg = 0x00009888, .val = 0x02614040 },
         { .reg = 0x00009888, .val = 0x02624040 },
         { .reg = 0x00009888, .val = 0x0E630C80 },
         { .reg = 0x00009888, .val = 0x12630CC0 },
         { .reg = 0x00009888, .val = 0x04630000 },
         { .reg = 0x00009888, .val = 0x02630000 },
         { .reg = 0x00009888, .val = 0x02684040 },
         { .reg = 0x00009888, .val = 0x00814040 },
         { .reg = 0x00009888, .val = 0x00824040 },
         { .reg = 0x00009888, .val = 0x06830C80 },
         { .reg = 0x00009888, .val = 0x0A830CC0 },
         { .reg = 0x00009888, .val = 0x04830000 },
         { .reg = 0x00009888, .val = 0x00830000 },
         { .reg = 0x00009888, .val = 0x00884040 },
         { .reg = 0x00009888, .val = 0x00A11010 },
         { .reg = 0x00009888, .val = 0x00A21010 },
         { .reg = 0x00009888, .val = 0x06A30032 },
         { .reg = 0x00009888, .val = 0x0AA30033 },
         { .reg = 0x00009888, .val = 0x04A30000 },
         { .reg = 0x00009888, .val = 0x00A30000 },
         { .reg = 0x00009888, .val = 0x00A81010 },
         { .reg = 0x00009888, .val = 0x00C10404 },
         { .reg = 0x00009888, .val = 0x00C20404 },
         { .reg = 0x00009888, .val = 0x04C30C80 },
         { .reg = 0x00009888, .val = 0x08C30CC0 },
         { .reg = 0x00009888, .val = 0x00C30000 },
         { .reg = 0x00009888, .val = 0x00C80404 },
         { .reg = 0x00009888, .val = 0x00E10101 },
         { .reg = 0x00009888, .val = 0x00E20101 },
         { .reg = 0x00009888, .val = 0x04E30032 },
         { .reg = 0x00009888, .val = 0x08E30033 },
         { .reg = 0x00009888, .val = 0x00E30000 },
         { .reg = 0x00009888, .val = 0x00E80101 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x02013535 },
         { .reg = 0x00009888, .val = 0x02040505 },
         { .reg = 0x00009888, .val = 0x000B3300 },
         { .reg = 0x00009888, .val = 0x02090E0E },
         { .reg = 0x00009888, .val = 0x020A2A2A },
         { .reg = 0x00009888, .val = 0x00215C5C },
         { .reg = 0x00009888, .val = 0x00245050 },
         { .reg = 0x00009888, .val = 0x002B00CC },
         { .reg = 0x00009888, .val = 0x0029B0B0 },
         { .reg = 0x00009888, .val = 0x002AA8A8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0202EAEA },
         { .reg = 0x00009888, .val = 0x0082ABAB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000500FF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x000400FF },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010003 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010407 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010E05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext103__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext103__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext103__avg_gpu_core_frequency__max,mtlgt3__ext103__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5972, 24, NULL,mtlgt3__ext103__sampler_texture_cache_access_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5973, 32, NULL,mtlgt3__ext103__sampler_texture_cache_access_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5974, 40, NULL,mtlgt3__ext103__sampler_texture_cache_access_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5975, 48, NULL,mtlgt3__ext103__sampler_texture_cache_access_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5976, 56, NULL,mtlgt3__ext103__sampler_texture_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5977, 64, NULL,mtlgt3__ext103__sampler_texture_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5978, 72, NULL,mtlgt3__ext103__sampler_texture_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5979, 80, NULL,mtlgt3__ext103__sampler_texture_cache_miss_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6756, 88, NULL,mtlgt3__ext103__sampler_texture_cache_access_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6757, 96, NULL,mtlgt3__ext103__sampler_texture_cache_access_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6758, 104, NULL,mtlgt3__ext103__sampler_texture_cache_access_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6759, 112, NULL,mtlgt3__ext103__sampler_texture_cache_access_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6760, 120, NULL,mtlgt3__ext103__sampler_texture_cache_miss_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6761, 128, NULL,mtlgt3__ext103__sampler_texture_cache_miss_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6762, 136, NULL,mtlgt3__ext103__sampler_texture_cache_miss_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6763, 144, NULL,mtlgt3__ext103__sampler_texture_cache_miss_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext104_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext104";
   query->symbol_name = "Ext104";
   query->guid = "5503160a-7b2a-4099-9ec6-0d3a551cb388";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x3407000C },
         { .reg = 0x00009888, .val = 0x344703CA },
         { .reg = 0x00009888, .val = 0x02070A00 },
         { .reg = 0x00009888, .val = 0x08070C00 },
         { .reg = 0x00009888, .val = 0x0A070CB1 },
         { .reg = 0x00009888, .val = 0x0C070DF3 },
         { .reg = 0x00009888, .val = 0x0E070036 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x0008A800 },
         { .reg = 0x00009888, .val = 0x0208002A },
         { .reg = 0x00009888, .val = 0x0247BA00 },
         { .reg = 0x00009888, .val = 0x04470CF2 },
         { .reg = 0x00009888, .val = 0x06470D74 },
         { .reg = 0x00009888, .val = 0x08470039 },
         { .reg = 0x00009888, .val = 0x004802AA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x000157FF },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02040015 },
         { .reg = 0x00009888, .val = 0x000B07E0 },
         { .reg = 0x00009888, .val = 0x0009A800 },
         { .reg = 0x00009888, .val = 0x0209002A },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A002A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202002A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000207FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203002A },
         { .reg = 0x00009888, .val = 0x4C010600 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000008A },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001802 },
         { .reg = 0x0000D94C, .val = 0x0000F81F },
         { .reg = 0x0000D950, .val = 0x00001102 },
         { .reg = 0x0000D954, .val = 0x0000F81F },
         { .reg = 0x0000D958, .val = 0x000000BA },
         { .reg = 0x0000D95C, .val = 0x0000FFE0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext104__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext104__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext104__avg_gpu_core_frequency__max,mtlgt3__ext104__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5980, 24, NULL,mtlgt3__ext104__async_gpgpu_thread_exit_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5981, 32, NULL,mtlgt3__ext104__task_thread_exit_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5982, 40, NULL,mtlgt3__ext104__gpgpu_threadgroup_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5983, 48, NULL,mtlgt3__ext104__task_threadgroup_count_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext105_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext105";
   query->symbol_name = "Ext105";
   query->guid = "418f87f0-b6d8-4684-883e-4f10a79c5070";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x3427000C },
         { .reg = 0x00009888, .val = 0x346703CA },
         { .reg = 0x00009888, .val = 0x02270A00 },
         { .reg = 0x00009888, .val = 0x08270C00 },
         { .reg = 0x00009888, .val = 0x0A270CB1 },
         { .reg = 0x00009888, .val = 0x0C270DF3 },
         { .reg = 0x00009888, .val = 0x0E270036 },
         { .reg = 0x00009888, .val = 0x04270000 },
         { .reg = 0x00009888, .val = 0x0028A800 },
         { .reg = 0x00009888, .val = 0x0228002A },
         { .reg = 0x00009888, .val = 0x0267BA00 },
         { .reg = 0x00009888, .val = 0x04670CF2 },
         { .reg = 0x00009888, .val = 0x06670D74 },
         { .reg = 0x00009888, .val = 0x08670039 },
         { .reg = 0x00009888, .val = 0x006802AA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02040015 },
         { .reg = 0x00009888, .val = 0x000B07E0 },
         { .reg = 0x00009888, .val = 0x0009FC00 },
         { .reg = 0x00009888, .val = 0x0209003F },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020A002A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002ABFF },
         { .reg = 0x00009888, .val = 0x0202002A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000207FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203002A },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000BA },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFE0 },
         { .reg = 0x0000D950, .val = 0x00001802 },
         { .reg = 0x0000D954, .val = 0x0000F81F },
         { .reg = 0x0000D958, .val = 0x00001102 },
         { .reg = 0x0000D95C, .val = 0x0000F81F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext105__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext105__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext105__avg_gpu_core_frequency__max,mtlgt3__ext105__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5984, 24, NULL,mtlgt3__ext105__async_gpgpu_thread_exit_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5985, 32, NULL,mtlgt3__ext105__task_thread_exit_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5986, 40, NULL,mtlgt3__ext105__gpgpu_threadgroup_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5987, 48, NULL,mtlgt3__ext105__task_threadgroup_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext106_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext106";
   query->symbol_name = "Ext106";
   query->guid = "f5b7256f-9bf6-4c95-94c1-4044cfad0ea6";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x340703CA },
         { .reg = 0x00009888, .val = 0x3447000C },
         { .reg = 0x00009888, .val = 0x0207BA00 },
         { .reg = 0x00009888, .val = 0x0A070CF2 },
         { .reg = 0x00009888, .val = 0x0C070D74 },
         { .reg = 0x00009888, .val = 0x0E070039 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x0008A000 },
         { .reg = 0x00009888, .val = 0x0208002A },
         { .reg = 0x00009888, .val = 0x02470A00 },
         { .reg = 0x00009888, .val = 0x04470C70 },
         { .reg = 0x00009888, .val = 0x06470CF2 },
         { .reg = 0x00009888, .val = 0x08470DB7 },
         { .reg = 0x00009888, .val = 0x00480AAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015FFF },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040015 },
         { .reg = 0x00009888, .val = 0x000B07C0 },
         { .reg = 0x00009888, .val = 0x0009A000 },
         { .reg = 0x00009888, .val = 0x0209002A },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A002A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202002A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000207FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203002A },
         { .reg = 0x00009888, .val = 0x4C010600 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010003 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext106__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext106__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext106__avg_gpu_core_frequency__max,mtlgt3__ext106__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5988, 24, NULL,mtlgt3__ext106__async_gpgpu_thread_exit_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 5989, 32, NULL,mtlgt3__ext106__task_thread_exit_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5990, 40, NULL,mtlgt3__ext106__gpgpu_threadgroup_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 5991, 48, NULL,mtlgt3__ext106__task_threadgroup_count_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext107_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext107";
   query->symbol_name = "Ext107";
   query->guid = "28d75db6-0eb3-4651-b820-513a76013504";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x342703CA },
         { .reg = 0x00009888, .val = 0x3467000C },
         { .reg = 0x00009888, .val = 0x0227BA00 },
         { .reg = 0x00009888, .val = 0x0A270CF2 },
         { .reg = 0x00009888, .val = 0x0C270D74 },
         { .reg = 0x00009888, .val = 0x0E270039 },
         { .reg = 0x00009888, .val = 0x04270000 },
         { .reg = 0x00009888, .val = 0x0028A000 },
         { .reg = 0x00009888, .val = 0x0228002A },
         { .reg = 0x00009888, .val = 0x02670A00 },
         { .reg = 0x00009888, .val = 0x04670C70 },
         { .reg = 0x00009888, .val = 0x06670CF2 },
         { .reg = 0x00009888, .val = 0x08670DB7 },
         { .reg = 0x00009888, .val = 0x00680AAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02040015 },
         { .reg = 0x00009888, .val = 0x000B07C0 },
         { .reg = 0x00009888, .val = 0x0009F000 },
         { .reg = 0x00009888, .val = 0x0209003F },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020A002A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AFFF },
         { .reg = 0x00009888, .val = 0x0202002A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000207FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203002A },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010005 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext107__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext107__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext107__avg_gpu_core_frequency__max,mtlgt3__ext107__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5992, 24, NULL,mtlgt3__ext107__async_gpgpu_thread_exit_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 5993, 32, NULL,mtlgt3__ext107__task_thread_exit_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5994, 40, NULL,mtlgt3__ext107__gpgpu_threadgroup_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 5995, 48, NULL,mtlgt3__ext107__task_threadgroup_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext108_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext108";
   query->symbol_name = "Ext108";
   query->guid = "080da0b6-29a4-416b-b20f-ece0e2527f60";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x3487000C },
         { .reg = 0x00009888, .val = 0x34C703CA },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x04870C70 },
         { .reg = 0x00009888, .val = 0x06870CF2 },
         { .reg = 0x00009888, .val = 0x08870DB7 },
         { .reg = 0x00009888, .val = 0x00880AAA },
         { .reg = 0x00009888, .val = 0x02C7BA00 },
         { .reg = 0x00009888, .val = 0x0AC70CF2 },
         { .reg = 0x00009888, .val = 0x0CC70D74 },
         { .reg = 0x00009888, .val = 0x0EC70039 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x00C8A000 },
         { .reg = 0x00009888, .val = 0x02C8002A },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021F555 },
         { .reg = 0x00009888, .val = 0x0221003F },
         { .reg = 0x00009888, .val = 0x00240555 },
         { .reg = 0x00009888, .val = 0x002B003F },
         { .reg = 0x00009888, .val = 0x00290AAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A002A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282002A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000507FF },
         { .reg = 0x00009888, .val = 0x000207FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030015 },
         { .reg = 0x00009888, .val = 0x000407FF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext108__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext108__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext108__avg_gpu_core_frequency__max,mtlgt3__ext108__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6764, 24, NULL,mtlgt3__ext108__async_gpgpu_thread_exit_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6765, 32, NULL,mtlgt3__ext108__task_thread_exit_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6766, 40, NULL,mtlgt3__ext108__gpgpu_threadgroup_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6767, 48, NULL,mtlgt3__ext108__task_threadgroup_count_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext109_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext109";
   query->symbol_name = "Ext109";
   query->guid = "75a9e66d-9bbe-46d7-971e-71ca8ef680ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x34A7000C },
         { .reg = 0x00009888, .val = 0x34E703CA },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x04A70C70 },
         { .reg = 0x00009888, .val = 0x06A70CF2 },
         { .reg = 0x00009888, .val = 0x08A70DB7 },
         { .reg = 0x00009888, .val = 0x00A80AAA },
         { .reg = 0x00009888, .val = 0x02E7BA00 },
         { .reg = 0x00009888, .val = 0x0AE70CF2 },
         { .reg = 0x00009888, .val = 0x0CE70D74 },
         { .reg = 0x00009888, .val = 0x0EE70039 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x00E8A000 },
         { .reg = 0x00009888, .val = 0x02E8002A },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00210555 },
         { .reg = 0x00009888, .val = 0x00240555 },
         { .reg = 0x00009888, .val = 0x002B003F },
         { .reg = 0x00009888, .val = 0x00290FFF },
         { .reg = 0x00009888, .val = 0x002A0AAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FAAA },
         { .reg = 0x00009888, .val = 0x0282003F },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000507FF },
         { .reg = 0x00009888, .val = 0x000207FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030015 },
         { .reg = 0x00009888, .val = 0x000407FF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010A00 },
         { .reg = 0x00009888, .val = 0x5E010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext109__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext109__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext109__avg_gpu_core_frequency__max,mtlgt3__ext109__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6768, 24, NULL,mtlgt3__ext109__async_gpgpu_thread_exit_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6769, 32, NULL,mtlgt3__ext109__task_thread_exit_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6770, 40, NULL,mtlgt3__ext109__gpgpu_threadgroup_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6771, 48, NULL,mtlgt3__ext109__task_threadgroup_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext110_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext110";
   query->symbol_name = "Ext110";
   query->guid = "ae5589a9-7e09-4343-a611-3161977315d5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x348703CA },
         { .reg = 0x00009888, .val = 0x34C7000C },
         { .reg = 0x00009888, .val = 0x0287BA00 },
         { .reg = 0x00009888, .val = 0x0A870CF2 },
         { .reg = 0x00009888, .val = 0x0C870D74 },
         { .reg = 0x00009888, .val = 0x0E870039 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x0088A000 },
         { .reg = 0x00009888, .val = 0x0288002A },
         { .reg = 0x00009888, .val = 0x02C70A00 },
         { .reg = 0x00009888, .val = 0x04C70C70 },
         { .reg = 0x00009888, .val = 0x06C70CF2 },
         { .reg = 0x00009888, .val = 0x08C70DB7 },
         { .reg = 0x00009888, .val = 0x00C80AAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215FFF },
         { .reg = 0x00009888, .val = 0x02210015 },
         { .reg = 0x00009888, .val = 0x00245000 },
         { .reg = 0x00009888, .val = 0x02240015 },
         { .reg = 0x00009888, .val = 0x002B07C0 },
         { .reg = 0x00009888, .val = 0x0029A000 },
         { .reg = 0x00009888, .val = 0x0229002A },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A002A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282002A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000507FF },
         { .reg = 0x00009888, .val = 0x000207FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030015 },
         { .reg = 0x00009888, .val = 0x000407FF },
         { .reg = 0x00009888, .val = 0x4C010600 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010003 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext110__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext110__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext110__avg_gpu_core_frequency__max,mtlgt3__ext110__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6772, 24, NULL,mtlgt3__ext110__async_gpgpu_thread_exit_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6773, 32, NULL,mtlgt3__ext110__task_thread_exit_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6774, 40, NULL,mtlgt3__ext110__gpgpu_threadgroup_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6775, 48, NULL,mtlgt3__ext110__task_threadgroup_count_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext111_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext111";
   query->symbol_name = "Ext111";
   query->guid = "a5e1e738-1338-4d76-a6a7-5517111cc852";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x34A703CA },
         { .reg = 0x00009888, .val = 0x34E7000C },
         { .reg = 0x00009888, .val = 0x02A7BA00 },
         { .reg = 0x00009888, .val = 0x0AA70CF2 },
         { .reg = 0x00009888, .val = 0x0CA70D74 },
         { .reg = 0x00009888, .val = 0x0EA70039 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x00A8A000 },
         { .reg = 0x00009888, .val = 0x02A8002A },
         { .reg = 0x00009888, .val = 0x02E70A00 },
         { .reg = 0x00009888, .val = 0x04E70C70 },
         { .reg = 0x00009888, .val = 0x06E70CF2 },
         { .reg = 0x00009888, .val = 0x08E70DB7 },
         { .reg = 0x00009888, .val = 0x00E80AAA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215000 },
         { .reg = 0x00009888, .val = 0x02210015 },
         { .reg = 0x00009888, .val = 0x00245000 },
         { .reg = 0x00009888, .val = 0x02240015 },
         { .reg = 0x00009888, .val = 0x002B07C0 },
         { .reg = 0x00009888, .val = 0x0029F000 },
         { .reg = 0x00009888, .val = 0x0229003F },
         { .reg = 0x00009888, .val = 0x002AA000 },
         { .reg = 0x00009888, .val = 0x022A002A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AFFF },
         { .reg = 0x00009888, .val = 0x0282002A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000507FF },
         { .reg = 0x00009888, .val = 0x000207FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030015 },
         { .reg = 0x00009888, .val = 0x000407FF },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010005 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000C2 },
         { .reg = 0x0000D944, .val = 0x0000FFC0 },
         { .reg = 0x0000D948, .val = 0x0000008A },
         { .reg = 0x0000D94C, .val = 0x0000FFC0 },
         { .reg = 0x0000D950, .val = 0x00002E02 },
         { .reg = 0x0000D954, .val = 0x0000F83F },
         { .reg = 0x0000D958, .val = 0x00002202 },
         { .reg = 0x0000D95C, .val = 0x0000F83F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext111__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext111__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext111__avg_gpu_core_frequency__max,mtlgt3__ext111__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6776, 24, NULL,mtlgt3__ext111__async_gpgpu_thread_exit_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6777, 32, NULL,mtlgt3__ext111__task_thread_exit_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6778, 40, NULL,mtlgt3__ext111__gpgpu_threadgroup_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6779, 48, NULL,mtlgt3__ext111__task_threadgroup_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext113_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext113";
   query->symbol_name = "Ext113";
   query->guid = "1a24edc7-8187-43b6-86aa-fcf56c223893";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C070000 },
         { .reg = 0x00009888, .val = 0x340703DD },
         { .reg = 0x00009888, .val = 0x2C270000 },
         { .reg = 0x00009888, .val = 0x342703DD },
         { .reg = 0x00009888, .val = 0x2C470000 },
         { .reg = 0x00009888, .val = 0x344703DD },
         { .reg = 0x00009888, .val = 0x2C670000 },
         { .reg = 0x00009888, .val = 0x346703DD },
         { .reg = 0x00009888, .val = 0x0207BA0A },
         { .reg = 0x00009888, .val = 0x04070821 },
         { .reg = 0x00009888, .val = 0x12070E37 },
         { .reg = 0x00009888, .val = 0x0008000A },
         { .reg = 0x00009888, .val = 0x0208A000 },
         { .reg = 0x00009888, .val = 0x0227BA0A },
         { .reg = 0x00009888, .val = 0x06270821 },
         { .reg = 0x00009888, .val = 0x10270E37 },
         { .reg = 0x00009888, .val = 0x04270000 },
         { .reg = 0x00009888, .val = 0x002800A0 },
         { .reg = 0x00009888, .val = 0x02280A00 },
         { .reg = 0x00009888, .val = 0x0247BA0A },
         { .reg = 0x00009888, .val = 0x08470821 },
         { .reg = 0x00009888, .val = 0x0E470E37 },
         { .reg = 0x00009888, .val = 0x04470000 },
         { .reg = 0x00009888, .val = 0x00480A00 },
         { .reg = 0x00009888, .val = 0x024800A0 },
         { .reg = 0x00009888, .val = 0x0267BA0A },
         { .reg = 0x00009888, .val = 0x0A670821 },
         { .reg = 0x00009888, .val = 0x0C670E37 },
         { .reg = 0x00009888, .val = 0x04670000 },
         { .reg = 0x00009888, .val = 0x0068A000 },
         { .reg = 0x00009888, .val = 0x0268000A },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00010F55 },
         { .reg = 0x00009888, .val = 0x020155F0 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x000BF00F },
         { .reg = 0x00009888, .val = 0x000900FA },
         { .reg = 0x00009888, .val = 0x0209AF00 },
         { .reg = 0x00009888, .val = 0x000A0AAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FAAA },
         { .reg = 0x00009888, .val = 0x0202AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010A03 },
         { .reg = 0x00009888, .val = 0x5E010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext113__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext113__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext113__avg_gpu_core_frequency__max,mtlgt3__ext113__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 5996, 24, percentage_max_float,mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 5997, 28, percentage_max_float,mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 5998, 32, percentage_max_float,mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 5999, 36, percentage_max_float,mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6000, 40, percentage_max_float,mtlgt3__ext113__thread_dispatch_queue0_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6001, 44, percentage_max_float,mtlgt3__ext113__thread_dispatch_queue1_active_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6002, 48, percentage_max_float,mtlgt3__ext113__thread_dispatch_queue0_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6003, 52, percentage_max_float,mtlgt3__ext113__thread_dispatch_queue1_active_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6004, 56, percentage_max_float,mtlgt3__ext113__thread_dispatch_queue0_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6005, 60, percentage_max_float,mtlgt3__ext113__thread_dispatch_queue1_active_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6006, 64, percentage_max_float,mtlgt3__ext113__thread_dispatch_queue0_active_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6007, 68, percentage_max_float,mtlgt3__ext113__thread_dispatch_queue1_active_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext114_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext114";
   query->symbol_name = "Ext114";
   query->guid = "32565d07-8ac7-41c3-89a3-66d0c1100616";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C870000 },
         { .reg = 0x00009888, .val = 0x348703DD },
         { .reg = 0x00009888, .val = 0x2CA70000 },
         { .reg = 0x00009888, .val = 0x34A703DD },
         { .reg = 0x00009888, .val = 0x2CC70000 },
         { .reg = 0x00009888, .val = 0x34C703DD },
         { .reg = 0x00009888, .val = 0x2CE70000 },
         { .reg = 0x00009888, .val = 0x34E703DD },
         { .reg = 0x00009888, .val = 0x0287BA0A },
         { .reg = 0x00009888, .val = 0x04870821 },
         { .reg = 0x00009888, .val = 0x12870E37 },
         { .reg = 0x00009888, .val = 0x0088000A },
         { .reg = 0x00009888, .val = 0x0288A000 },
         { .reg = 0x00009888, .val = 0x02A7BA0A },
         { .reg = 0x00009888, .val = 0x06A70821 },
         { .reg = 0x00009888, .val = 0x10A70E37 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x00A800A0 },
         { .reg = 0x00009888, .val = 0x02A80A00 },
         { .reg = 0x00009888, .val = 0x02C7BA0A },
         { .reg = 0x00009888, .val = 0x08C70821 },
         { .reg = 0x00009888, .val = 0x0EC70E37 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x00C80A00 },
         { .reg = 0x00009888, .val = 0x02C800A0 },
         { .reg = 0x00009888, .val = 0x02E7BA0A },
         { .reg = 0x00009888, .val = 0x0AE70821 },
         { .reg = 0x00009888, .val = 0x0CE70E37 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x00E8A000 },
         { .reg = 0x00009888, .val = 0x02E8000A },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00210F55 },
         { .reg = 0x00009888, .val = 0x022155F0 },
         { .reg = 0x00009888, .val = 0x00240055 },
         { .reg = 0x00009888, .val = 0x02245500 },
         { .reg = 0x00009888, .val = 0x002BF00F },
         { .reg = 0x00009888, .val = 0x002900FA },
         { .reg = 0x00009888, .val = 0x0229AF00 },
         { .reg = 0x00009888, .val = 0x002A0AAA },
         { .reg = 0x00009888, .val = 0x022AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FAAA },
         { .reg = 0x00009888, .val = 0x0282AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010A03 },
         { .reg = 0x00009888, .val = 0x5E010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000000 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000000 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000000 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000000 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext114__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext114__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext114__avg_gpu_core_frequency__max,mtlgt3__ext114__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6780, 24, percentage_max_float,mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6781, 28, percentage_max_float,mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6782, 32, percentage_max_float,mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6783, 36, percentage_max_float,mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6784, 40, percentage_max_float,mtlgt3__ext114__thread_dispatch_queue0_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6785, 44, percentage_max_float,mtlgt3__ext114__thread_dispatch_queue1_active_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6786, 48, percentage_max_float,mtlgt3__ext114__thread_dispatch_queue0_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6787, 52, percentage_max_float,mtlgt3__ext114__thread_dispatch_queue1_active_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6788, 56, percentage_max_float,mtlgt3__ext114__thread_dispatch_queue0_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6789, 60, percentage_max_float,mtlgt3__ext114__thread_dispatch_queue1_active_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6790, 64, percentage_max_float,mtlgt3__ext114__thread_dispatch_queue0_active_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6791, 68, percentage_max_float,mtlgt3__ext114__thread_dispatch_queue1_active_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext116_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext116";
   query->symbol_name = "Ext116";
   query->guid = "f725009a-c5e7-4418-9adf-ddb70cb2edde";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x3407001E },
         { .reg = 0x00009888, .val = 0x3427001E },
         { .reg = 0x00009888, .val = 0x3447001E },
         { .reg = 0x00009888, .val = 0x3467001E },
         { .reg = 0x00009888, .val = 0x02070A00 },
         { .reg = 0x00009888, .val = 0x10070DB7 },
         { .reg = 0x00009888, .val = 0x12070CF5 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x0208AA00 },
         { .reg = 0x00009888, .val = 0x02270A00 },
         { .reg = 0x00009888, .val = 0x0C270DB7 },
         { .reg = 0x00009888, .val = 0x0E270CF5 },
         { .reg = 0x00009888, .val = 0x04270000 },
         { .reg = 0x00009888, .val = 0x022800AA },
         { .reg = 0x00009888, .val = 0x02470A00 },
         { .reg = 0x00009888, .val = 0x08470DB7 },
         { .reg = 0x00009888, .val = 0x0A470CF5 },
         { .reg = 0x00009888, .val = 0x04470000 },
         { .reg = 0x00009888, .val = 0x0048AA00 },
         { .reg = 0x00009888, .val = 0x02670A00 },
         { .reg = 0x00009888, .val = 0x04670DB7 },
         { .reg = 0x00009888, .val = 0x06670CF5 },
         { .reg = 0x00009888, .val = 0x006800AA },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFF00 },
         { .reg = 0x00009888, .val = 0x0209AAFF },
         { .reg = 0x00009888, .val = 0x000AAA00 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010603 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000401 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00004001 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00040001 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext116__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext116__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext116__avg_gpu_core_frequency__max,mtlgt3__ext116__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6008, 24, percentage_max_float,mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6009, 28, percentage_max_float,mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6010, 32, percentage_max_float,mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6011, 36, percentage_max_float,mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext117_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext117";
   query->symbol_name = "Ext117";
   query->guid = "f633497f-c116-461f-a0e9-bb3fdcef7683";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x3487001E },
         { .reg = 0x00009888, .val = 0x34A7001E },
         { .reg = 0x00009888, .val = 0x34C7001E },
         { .reg = 0x00009888, .val = 0x34E7001E },
         { .reg = 0x00009888, .val = 0x02870A00 },
         { .reg = 0x00009888, .val = 0x04870DB7 },
         { .reg = 0x00009888, .val = 0x06870CF5 },
         { .reg = 0x00009888, .val = 0x008800AA },
         { .reg = 0x00009888, .val = 0x02A70A00 },
         { .reg = 0x00009888, .val = 0x08A70DB7 },
         { .reg = 0x00009888, .val = 0x0AA70CF5 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x00A8AA00 },
         { .reg = 0x00009888, .val = 0x02C70A00 },
         { .reg = 0x00009888, .val = 0x0CC70DB7 },
         { .reg = 0x00009888, .val = 0x0EC70CF5 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x02C800AA },
         { .reg = 0x00009888, .val = 0x02E70A00 },
         { .reg = 0x00009888, .val = 0x10E70DB7 },
         { .reg = 0x00009888, .val = 0x12E70CF5 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x02E8AA00 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000041 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000401 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00004001 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00040001 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext117__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext117__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext117__avg_gpu_core_frequency__max,mtlgt3__ext117__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6792, 24, percentage_max_float,mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6793, 28, percentage_max_float,mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6794, 32, percentage_max_float,mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6795, 36, percentage_max_float,mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext118_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext118";
   query->symbol_name = "Ext118";
   query->guid = "bae9e67e-4b5c-4fb9-b21d-21a6966bed46";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x140B0700 },
         { .reg = 0x00009888, .val = 0x160B001A },
         { .reg = 0x00009888, .val = 0x00011555 },
         { .reg = 0x00009888, .val = 0x00041555 },
         { .reg = 0x00009888, .val = 0x020B0010 },
         { .reg = 0x00009888, .val = 0x040B0000 },
         { .reg = 0x00009888, .val = 0x060B0081 },
         { .reg = 0x00009888, .val = 0x080B03C3 },
         { .reg = 0x00009888, .val = 0x0A0B034E },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x000A2AAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x180203C0 },
         { .reg = 0x00009888, .val = 0x1A0200C9 },
         { .reg = 0x00009888, .val = 0x04020800 },
         { .reg = 0x00009888, .val = 0x10020C00 },
         { .reg = 0x00009888, .val = 0x12020939 },
         { .reg = 0x00009888, .val = 0x140209A3 },
         { .reg = 0x00009888, .val = 0x00022AAA },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F87F },
         { .reg = 0x00009888, .val = 0x00011555 },
         { .reg = 0x00009888, .val = 0x02015540 },
         { .reg = 0x00009888, .val = 0x00032AAA },
         { .reg = 0x00009888, .val = 0x0203AA80 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010804 },
         { .reg = 0x00009888, .val = 0x52010040 },
         { .reg = 0x00009888, .val = 0x54010804 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00100060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x0000001A },
         { .reg = 0x0000D954, .val = 0x0000FFFC },
         { .reg = 0x0000D958, .val = 0x00000062 },
         { .reg = 0x0000D95C, .val = 0x0000FFF3 },
         { .reg = 0x0000D960, .val = 0x0000001A },
         { .reg = 0x0000D964, .val = 0x0000FFFC },
         { .reg = 0x0000D968, .val = 0x00000062 },
         { .reg = 0x0000D96C, .val = 0x0000FFF3 },
         { .reg = 0x0000D970, .val = 0x00000282 },
         { .reg = 0x0000D974, .val = 0x0000FF8F },
         { .reg = 0x0000D978, .val = 0x00000082 },
         { .reg = 0x0000D97C, .val = 0x0000FF8F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext118__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext118__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext118__avg_gpu_core_frequency__max,mtlgt3__ext118__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6012, 24, percentage_max_float,mtlgt3__ext118__amfs_stall_all_input_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6013, 28, percentage_max_float,mtlgt3__ext118__amfs_stall_any_input_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6014, 32, NULL,mtlgt3__ext118__amfs_cache_hit_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6015, 40, NULL,mtlgt3__ext118__amfs_cache_miss_slice0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6016, 48, NULL,mtlgt3__ext118__render_cache_hit_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6017, 56, NULL,mtlgt3__ext118__render_cache_read_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6018, 64, NULL,mtlgt3__ext118__render_cache_write_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6019, 72, percentage_max_float,mtlgt3__ext118__render_cache_input_available_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6020, 76, percentage_max_float,mtlgt3__ext118__render_cache_output_ready_l3_node0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext119_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 12);

   query->name = "Ext119";
   query->symbol_name = "Ext119";
   query->guid = "95c08faf-813c-4b71-9062-09569c5ff432";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x142B0700 },
         { .reg = 0x00009888, .val = 0x162B001A },
         { .reg = 0x00009888, .val = 0x00211555 },
         { .reg = 0x00009888, .val = 0x00241555 },
         { .reg = 0x00009888, .val = 0x022B0010 },
         { .reg = 0x00009888, .val = 0x042B0000 },
         { .reg = 0x00009888, .val = 0x062B0081 },
         { .reg = 0x00009888, .val = 0x082B03C3 },
         { .reg = 0x00009888, .val = 0x0A2B034E },
         { .reg = 0x00009888, .val = 0x002B0000 },
         { .reg = 0x00009888, .val = 0x002A2AAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x188203C0 },
         { .reg = 0x00009888, .val = 0x1A820126 },
         { .reg = 0x00009888, .val = 0x04820800 },
         { .reg = 0x00009888, .val = 0x10820C40 },
         { .reg = 0x00009888, .val = 0x12820938 },
         { .reg = 0x00009888, .val = 0x148209A3 },
         { .reg = 0x00009888, .val = 0x00822AAA },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F87F },
         { .reg = 0x00009888, .val = 0x0002F87F },
         { .reg = 0x00009888, .val = 0x00011555 },
         { .reg = 0x00009888, .val = 0x02015540 },
         { .reg = 0x00009888, .val = 0x00031555 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x0004F87F },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010804 },
         { .reg = 0x00009888, .val = 0x52010040 },
         { .reg = 0x00009888, .val = 0x54010804 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000007A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00100060 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x0000001A },
         { .reg = 0x0000D954, .val = 0x0000FFFC },
         { .reg = 0x0000D958, .val = 0x00000062 },
         { .reg = 0x0000D95C, .val = 0x0000FFF3 },
         { .reg = 0x0000D960, .val = 0x00000282 },
         { .reg = 0x0000D964, .val = 0x0000FF8F },
         { .reg = 0x0000D968, .val = 0x00000082 },
         { .reg = 0x0000D96C, .val = 0x0000FF8F },
         { .reg = 0x0000D970, .val = 0x0000001A },
         { .reg = 0x0000D974, .val = 0x0000FFFC },
         { .reg = 0x0000D978, .val = 0x00000062 },
         { .reg = 0x0000D97C, .val = 0x0000FFF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext119__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext119__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext119__avg_gpu_core_frequency__max,mtlgt3__ext119__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6796, 24, percentage_max_float,mtlgt3__ext119__amfs_stall_all_input_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6797, 28, percentage_max_float,mtlgt3__ext119__amfs_stall_any_input_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6798, 32, NULL,mtlgt3__ext119__amfs_cache_hit_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6799, 40, NULL,mtlgt3__ext119__amfs_cache_miss_slice1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6800, 48, NULL,mtlgt3__ext119__render_cache_hit_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6801, 56, NULL,mtlgt3__ext119__render_cache_read_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6802, 64, NULL,mtlgt3__ext119__render_cache_write_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6803, 72, percentage_max_float,mtlgt3__ext119__render_cache_input_available_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6804, 76, percentage_max_float,mtlgt3__ext119__render_cache_output_ready_l3_node1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext120_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext120";
   query->symbol_name = "Ext120";
   query->guid = "045ee54e-4e02-4877-adb1-5bd14ba49100";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C071400 },
         { .reg = 0x00009888, .val = 0x1C271400 },
         { .reg = 0x00009888, .val = 0x1C471400 },
         { .reg = 0x00009888, .val = 0x1C671400 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x04070554 },
         { .reg = 0x00009888, .val = 0x060705D6 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x00270000 },
         { .reg = 0x00009888, .val = 0x10270554 },
         { .reg = 0x00009888, .val = 0x122705D6 },
         { .reg = 0x00009888, .val = 0x04270000 },
         { .reg = 0x00009888, .val = 0x0228AA00 },
         { .reg = 0x00009888, .val = 0x00470000 },
         { .reg = 0x00009888, .val = 0x0C470554 },
         { .reg = 0x00009888, .val = 0x0E4705D6 },
         { .reg = 0x00009888, .val = 0x04470000 },
         { .reg = 0x00009888, .val = 0x024800AA },
         { .reg = 0x00009888, .val = 0x00670000 },
         { .reg = 0x00009888, .val = 0x08670554 },
         { .reg = 0x00009888, .val = 0x0A6705D6 },
         { .reg = 0x00009888, .val = 0x04670000 },
         { .reg = 0x00009888, .val = 0x0068AA00 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00010055 },
         { .reg = 0x00009888, .val = 0x020155FF },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x000BF00F },
         { .reg = 0x00009888, .val = 0x000900AA },
         { .reg = 0x00009888, .val = 0x0209FF00 },
         { .reg = 0x00009888, .val = 0x000A00AA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010A05 },
         { .reg = 0x00009888, .val = 0x5E010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext120__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext120__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext120__avg_gpu_core_frequency__max,mtlgt3__ext120__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6021, 24, percentage_max_float,mtlgt3__ext120__pixel_post_process_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6022, 28, percentage_max_float,mtlgt3__ext120__pixel_post_process_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6023, 32, percentage_max_float,mtlgt3__ext120__pixel_post_process_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6024, 36, percentage_max_float,mtlgt3__ext120__pixel_post_process_input_available_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext121_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext121";
   query->symbol_name = "Ext121";
   query->guid = "2e3894b5-2b6a-49c4-b2b6-0dde7375cb7b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C871400 },
         { .reg = 0x00009888, .val = 0x1CA71400 },
         { .reg = 0x00009888, .val = 0x1CC71400 },
         { .reg = 0x00009888, .val = 0x1CE71400 },
         { .reg = 0x00009888, .val = 0x00870000 },
         { .reg = 0x00009888, .val = 0x04870554 },
         { .reg = 0x00009888, .val = 0x068705D6 },
         { .reg = 0x00009888, .val = 0x008800AA },
         { .reg = 0x00009888, .val = 0x00A70000 },
         { .reg = 0x00009888, .val = 0x08A70554 },
         { .reg = 0x00009888, .val = 0x0AA705D6 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x00A8AA00 },
         { .reg = 0x00009888, .val = 0x00C70000 },
         { .reg = 0x00009888, .val = 0x0CC70554 },
         { .reg = 0x00009888, .val = 0x0EC705D6 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x02C800AA },
         { .reg = 0x00009888, .val = 0x00E70000 },
         { .reg = 0x00009888, .val = 0x10E70554 },
         { .reg = 0x00009888, .val = 0x12E705D6 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x02E8AA00 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000078 },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000780 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x00007800 },
         { .reg = 0x0000D954, .val = 0x0000F0FF },
         { .reg = 0x0000D958, .val = 0x00078000 },
         { .reg = 0x0000D95C, .val = 0x00000FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext121__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext121__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext121__avg_gpu_core_frequency__max,mtlgt3__ext121__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6805, 24, percentage_max_float,mtlgt3__ext121__pixel_post_process_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6806, 28, percentage_max_float,mtlgt3__ext121__pixel_post_process_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6807, 32, percentage_max_float,mtlgt3__ext121__pixel_post_process_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6808, 36, percentage_max_float,mtlgt3__ext121__pixel_post_process_input_available_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext122_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Ext122";
   query->symbol_name = "Ext122";
   query->guid = "25ca1237-2ed3-447a-9767-1a85da89daef";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x160B001A },
         { .reg = 0x00009888, .val = 0x14070038 },
         { .reg = 0x00009888, .val = 0x1E070001 },
         { .reg = 0x00009888, .val = 0x12080007 },
         { .reg = 0x00009888, .val = 0x0E081000 },
         { .reg = 0x00009888, .val = 0x162B001A },
         { .reg = 0x00009888, .val = 0x14270038 },
         { .reg = 0x00009888, .val = 0x1E270001 },
         { .reg = 0x00009888, .val = 0x12280007 },
         { .reg = 0x00009888, .val = 0x0E281C00 },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x02011050 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02041050 },
         { .reg = 0x00009888, .val = 0x020B0002 },
         { .reg = 0x00009888, .val = 0x0E0B01C0 },
         { .reg = 0x00009888, .val = 0x100B0006 },
         { .reg = 0x00009888, .val = 0x000B40C0 },
         { .reg = 0x00009888, .val = 0x00070080 },
         { .reg = 0x00009888, .val = 0x02070010 },
         { .reg = 0x00009888, .val = 0x08070500 },
         { .reg = 0x00009888, .val = 0x0A070013 },
         { .reg = 0x00009888, .val = 0x10070C00 },
         { .reg = 0x00009888, .val = 0x00095000 },
         { .reg = 0x00009888, .val = 0x02091000 },
         { .reg = 0x00009888, .val = 0x00080004 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x0A0800C4 },
         { .reg = 0x00009888, .val = 0x10080C00 },
         { .reg = 0x00009888, .val = 0x04080000 },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020A60A5 },
         { .reg = 0x00009888, .val = 0x00210055 },
         { .reg = 0x00009888, .val = 0x02210100 },
         { .reg = 0x00009888, .val = 0x00240055 },
         { .reg = 0x00009888, .val = 0x02240100 },
         { .reg = 0x00009888, .val = 0x022B0002 },
         { .reg = 0x00009888, .val = 0x042B0E00 },
         { .reg = 0x00009888, .val = 0x062B0006 },
         { .reg = 0x00009888, .val = 0x002B100C },
         { .reg = 0x00009888, .val = 0x00270080 },
         { .reg = 0x00009888, .val = 0x02270010 },
         { .reg = 0x00009888, .val = 0x04270500 },
         { .reg = 0x00009888, .val = 0x06270013 },
         { .reg = 0x00009888, .val = 0x0E270C00 },
         { .reg = 0x00009888, .val = 0x00290050 },
         { .reg = 0x00009888, .val = 0x02290100 },
         { .reg = 0x00009888, .val = 0x00280004 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009888, .val = 0x062800C4 },
         { .reg = 0x00009888, .val = 0x04280000 },
         { .reg = 0x00009888, .val = 0x002A05AA },
         { .reg = 0x00009888, .val = 0x022A0600 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A000 },
         { .reg = 0x00009888, .val = 0x0202A0AA },
         { .reg = 0x00009888, .val = 0x00820AAA },
         { .reg = 0x00009888, .val = 0x02820A00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005303F },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A555 },
         { .reg = 0x00009888, .val = 0x0203A5AA },
         { .reg = 0x00009888, .val = 0x0004303F },
         { .reg = 0x00009888, .val = 0x4C010200 },
         { .reg = 0x00009888, .val = 0x56010010 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010040 },
         { .reg = 0x00009888, .val = 0x5C010404 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010C06 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010040 },
         { .reg = 0x00009888, .val = 0x54010C02 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x30800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext122__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext122__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext122__avg_gpu_core_frequency__max,mtlgt3__ext122__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6025, 24, NULL,mtlgt3__ext122__amfs_4_x4_shading_request_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6026, 32, percentage_max_float,mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6027, 36, percentage_max_float,mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6028, 40, percentage_max_float,mtlgt3__ext122__pixel_post_process_output_ready_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6029, 44, percentage_max_float,mtlgt3__ext122__pixel_post_process_output_ready_cpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6809, 48, NULL,mtlgt3__ext122__amfs_4_x4_shading_request_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6810, 56, percentage_max_float,mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6811, 60, percentage_max_float,mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6812, 64, percentage_max_float,mtlgt3__ext122__pixel_post_process_output_ready_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6813, 68, percentage_max_float,mtlgt3__ext122__pixel_post_process_output_ready_cpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext123_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext123";
   query->symbol_name = "Ext123";
   query->guid = "cf41fd07-c4c2-466c-9d85-774dcde02359";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16035013 },
         { .reg = 0x00009888, .val = 0x160B018A },
         { .reg = 0x00009888, .val = 0x16234C14 },
         { .reg = 0x00009888, .val = 0x162B018A },
         { .reg = 0x00009888, .val = 0x00010050 },
         { .reg = 0x00009888, .val = 0x02015400 },
         { .reg = 0x00009888, .val = 0x02030020 },
         { .reg = 0x00009888, .val = 0x120301C0 },
         { .reg = 0x00009888, .val = 0x14030008 },
         { .reg = 0x00009888, .val = 0x04030000 },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040050 },
         { .reg = 0x00009888, .val = 0x02046800 },
         { .reg = 0x00009888, .val = 0x020B001A },
         { .reg = 0x00009888, .val = 0x060B0000 },
         { .reg = 0x00009888, .val = 0x080B000D },
         { .reg = 0x00009888, .val = 0x140B000F },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x000A00A0 },
         { .reg = 0x00009888, .val = 0x020AA800 },
         { .reg = 0x00009888, .val = 0x00214005 },
         { .reg = 0x00009888, .val = 0x02210005 },
         { .reg = 0x00009888, .val = 0x02230020 },
         { .reg = 0x00009888, .val = 0x0E2303C0 },
         { .reg = 0x00009888, .val = 0x04230000 },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x00244005 },
         { .reg = 0x00009888, .val = 0x0224000A },
         { .reg = 0x00009888, .val = 0x022B001A },
         { .reg = 0x00009888, .val = 0x042B0000 },
         { .reg = 0x00009888, .val = 0x062B000D },
         { .reg = 0x00009888, .val = 0x0C2B000F },
         { .reg = 0x00009888, .val = 0x002B0000 },
         { .reg = 0x00009888, .val = 0x002A800A },
         { .reg = 0x00009888, .val = 0x022A000A },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x18020080 },
         { .reg = 0x00009888, .val = 0x1A0200C9 },
         { .reg = 0x00009888, .val = 0x18820080 },
         { .reg = 0x00009888, .val = 0x1A8200C9 },
         { .reg = 0x00009888, .val = 0x04020800 },
         { .reg = 0x00009888, .val = 0x0A020C20 },
         { .reg = 0x00009888, .val = 0x0C020039 },
         { .reg = 0x00009888, .val = 0x000200A0 },
         { .reg = 0x00009888, .val = 0x0202A800 },
         { .reg = 0x00009888, .val = 0x04820800 },
         { .reg = 0x00009888, .val = 0x10820C20 },
         { .reg = 0x00009888, .val = 0x12820039 },
         { .reg = 0x00009888, .val = 0x0082800A },
         { .reg = 0x00009888, .val = 0x0282000A },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00051F83 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00036AA5 },
         { .reg = 0x00009888, .val = 0x0203A955 },
         { .reg = 0x00009888, .val = 0x00041F83 },
         { .reg = 0x00009888, .val = 0x4C010200 },
         { .reg = 0x00009888, .val = 0x56010010 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010070 },
         { .reg = 0x00009888, .val = 0x5C010E07 },
         { .reg = 0x00009888, .val = 0x5E010010 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010A05 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010602 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000041A },
         { .reg = 0x0000D944, .val = 0x0000FF7C },
         { .reg = 0x0000D948, .val = 0x00040062 },
         { .reg = 0x0000D94C, .val = 0x00007FF3 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext123__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext123__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext123__avg_gpu_core_frequency__max,mtlgt3__ext123__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6035, 24, NULL,mtlgt3__ext123__amfs_l3_access_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6036, 32, NULL,mtlgt3__ext123__amfs_l3_atomic_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6037, 40, NULL,mtlgt3__ext123__clipper_primitive_far_near_clip_slice0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6030, 48, percentage_max_float,mtlgt3__ext123__color_pipe_cache_latency2_stall_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6031, 52, percentage_max_float,mtlgt3__ext123__pixel_backend_input_available_l3_node0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6032, 56, percentage_max_float,mtlgt3__ext123__pixel_backend_output_ready_l3_node0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6814, 64, NULL,mtlgt3__ext123__amfs_l3_access_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6815, 72, NULL,mtlgt3__ext123__amfs_l3_atomic_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6816, 80, NULL,mtlgt3__ext123__clipper_primitive_far_near_clip_slice1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6817, 88, percentage_max_float,mtlgt3__ext123__color_pipe_cache_latency2_stall_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6818, 92, percentage_max_float,mtlgt3__ext123__pixel_backend_input_available_l3_node1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_float(query, 6819, 96, percentage_max_float,mtlgt3__ext123__pixel_backend_output_ready_l3_node1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext124_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "Ext124";
   query->symbol_name = "Ext124";
   query->guid = "2445e8f0-04c4-43f5-87ff-e2f99a2528ed";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16035015 },
         { .reg = 0x00009888, .val = 0x2203041F },
         { .reg = 0x00009888, .val = 0x160401F0 },
         { .reg = 0x00009888, .val = 0x1804001F },
         { .reg = 0x00009888, .val = 0x0A060000 },
         { .reg = 0x00009888, .val = 0x1A070019 },
         { .reg = 0x00009888, .val = 0x16080019 },
         { .reg = 0x00009888, .val = 0x00014105 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x02030020 },
         { .reg = 0x00009888, .val = 0x04030022 },
         { .reg = 0x00009888, .val = 0x0C030080 },
         { .reg = 0x00009888, .val = 0x0E03024B },
         { .reg = 0x00009888, .val = 0x10030020 },
         { .reg = 0x00009888, .val = 0x12030028 },
         { .reg = 0x00009888, .val = 0x14030001 },
         { .reg = 0x00009888, .val = 0x00032000 },
         { .reg = 0x00009888, .val = 0x04040200 },
         { .reg = 0x00009888, .val = 0x0A040027 },
         { .reg = 0x00009888, .val = 0x10040D80 },
         { .reg = 0x00009888, .val = 0x00048005 },
         { .reg = 0x00009888, .val = 0x0204AA2A },
         { .reg = 0x00009888, .val = 0x00052000 },
         { .reg = 0x00009888, .val = 0x02060010 },
         { .reg = 0x00009888, .val = 0x10060031 },
         { .reg = 0x00009888, .val = 0x00060000 },
         { .reg = 0x00009888, .val = 0x000B0003 },
         { .reg = 0x00009888, .val = 0x00072000 },
         { .reg = 0x00009888, .val = 0x02074400 },
         { .reg = 0x00009888, .val = 0x04070021 },
         { .reg = 0x00009888, .val = 0x00090005 },
         { .reg = 0x00009888, .val = 0x00080100 },
         { .reg = 0x00009888, .val = 0x04080452 },
         { .reg = 0x00009888, .val = 0x000A825A },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000282AA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FF9F },
         { .reg = 0x00009888, .val = 0x00014155 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x000382AA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010200 },
         { .reg = 0x00009888, .val = 0x56010010 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5E010010 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010201 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010203 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010201 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFEF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext124__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext124__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext124__avg_gpu_core_frequency__max,mtlgt3__ext124__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6038, 24, percentage_max_float,mtlgt3__ext124__vertex_fetch_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6039, 28, percentage_max_float,mtlgt3__ext124__vertex_fetch_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6040, 32, NULL,mtlgt3__ext124__clipper_input_vertex_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6041, 40, NULL,mtlgt3__ext124__streamout_output_vertex_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6042, 48, percentage_max_float,mtlgt3__ext124__vs_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6043, 52, percentage_max_float,mtlgt3__ext124__clipper_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6044, 56, percentage_max_float,mtlgt3__ext124__clipper_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6045, 64, NULL,mtlgt3__ext124__clipper_primitive_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6046, 72, percentage_max_float,mtlgt3__ext124__stripsfan_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6033, 76, percentage_max_float,mtlgt3__ext124__ps_output_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6034, 80, percentage_max_float,mtlgt3__ext124__ps_output_available_cpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext125_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 14);

   query->name = "Ext125";
   query->symbol_name = "Ext125";
   query->guid = "446192f5-9062-4f1e-a99e-1be87cdcd0b8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16235414 },
         { .reg = 0x00009888, .val = 0x2223041F },
         { .reg = 0x00009888, .val = 0x162401F0 },
         { .reg = 0x00009888, .val = 0x1824001F },
         { .reg = 0x00009888, .val = 0x0A260000 },
         { .reg = 0x00009888, .val = 0x1A270019 },
         { .reg = 0x00009888, .val = 0x16280019 },
         { .reg = 0x00009888, .val = 0x00214105 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x02230020 },
         { .reg = 0x00009888, .val = 0x04230022 },
         { .reg = 0x00009888, .val = 0x0C230800 },
         { .reg = 0x00009888, .val = 0x0E2300C1 },
         { .reg = 0x00009888, .val = 0x1023000A },
         { .reg = 0x00009888, .val = 0x12230268 },
         { .reg = 0x00009888, .val = 0x14230008 },
         { .reg = 0x00009888, .val = 0x00230800 },
         { .reg = 0x00009888, .val = 0x04240200 },
         { .reg = 0x00009888, .val = 0x0A240027 },
         { .reg = 0x00009888, .val = 0x14240D80 },
         { .reg = 0x00009888, .val = 0x00248005 },
         { .reg = 0x00009888, .val = 0x02242AAA },
         { .reg = 0x00009888, .val = 0x00250800 },
         { .reg = 0x00009888, .val = 0x02260010 },
         { .reg = 0x00009888, .val = 0x0E260031 },
         { .reg = 0x00009888, .val = 0x00260000 },
         { .reg = 0x00009888, .val = 0x002B0003 },
         { .reg = 0x00009888, .val = 0x00272000 },
         { .reg = 0x00009888, .val = 0x02274400 },
         { .reg = 0x00009888, .val = 0x04270021 },
         { .reg = 0x00009888, .val = 0x00290005 },
         { .reg = 0x00009888, .val = 0x00280100 },
         { .reg = 0x00009888, .val = 0x04280452 },
         { .reg = 0x00009888, .val = 0x002A825A },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x008282AA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF9F },
         { .reg = 0x00009888, .val = 0x0002FF9F },
         { .reg = 0x00009888, .val = 0x00014155 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00034155 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF9F },
         { .reg = 0x00009888, .val = 0x4C010200 },
         { .reg = 0x00009888, .val = 0x56010010 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5E010010 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010201 },
         { .reg = 0x00009888, .val = 0x4E010010 },
         { .reg = 0x00009888, .val = 0x50010200 },
         { .reg = 0x00009888, .val = 0x52010010 },
         { .reg = 0x00009888, .val = 0x54010601 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FFEF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext125__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext125__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext125__avg_gpu_core_frequency__max,mtlgt3__ext125__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6820, 24, percentage_max_float,mtlgt3__ext125__vertex_fetch_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6821, 28, percentage_max_float,mtlgt3__ext125__vertex_fetch_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6822, 32, NULL,mtlgt3__ext125__clipper_input_vertex_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6823, 40, NULL,mtlgt3__ext125__streamout_output_vertex_count_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6824, 48, percentage_max_float,mtlgt3__ext125__vs_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6825, 52, percentage_max_float,mtlgt3__ext125__clipper_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6826, 56, percentage_max_float,mtlgt3__ext125__clipper_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6827, 64, NULL,mtlgt3__ext125__clipper_primitive_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6828, 72, percentage_max_float,mtlgt3__ext125__stripsfan_output_ready_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6829, 76, percentage_max_float,mtlgt3__ext125__ps_output_available_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6830, 80, percentage_max_float,mtlgt3__ext125__ps_output_available_cpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext126_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext126";
   query->symbol_name = "Ext126";
   query->guid = "9a0ec3ea-1d61-413e-8b9c-169cdec1f9b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x1A030000 },
         { .reg = 0x00009888, .val = 0x16030014 },
         { .reg = 0x00009888, .val = 0x20037FC0 },
         { .reg = 0x00009888, .val = 0x260B7800 },
         { .reg = 0x00009888, .val = 0x280B0000 },
         { .reg = 0x00009888, .val = 0x16090400 },
         { .reg = 0x00009888, .val = 0x180A0001 },
         { .reg = 0x00009888, .val = 0x00010505 },
         { .reg = 0x00009888, .val = 0x02015554 },
         { .reg = 0x00009888, .val = 0x02030007 },
         { .reg = 0x00009888, .val = 0x04030008 },
         { .reg = 0x00009888, .val = 0x100300C2 },
         { .reg = 0x00009888, .val = 0x1203094B },
         { .reg = 0x00009888, .val = 0x14030B6A },
         { .reg = 0x00009888, .val = 0x00030000 },
         { .reg = 0x00009888, .val = 0x00040505 },
         { .reg = 0x00009888, .val = 0x0204AAA4 },
         { .reg = 0x00009888, .val = 0x040B0130 },
         { .reg = 0x00009888, .val = 0x080B0C80 },
         { .reg = 0x00009888, .val = 0x0A0B0030 },
         { .reg = 0x00009888, .val = 0x0E0B003C },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009888, .val = 0x000B0003 },
         { .reg = 0x00009888, .val = 0x04090004 },
         { .reg = 0x00009888, .val = 0x06091870 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x040A0004 },
         { .reg = 0x00009888, .val = 0x080A01C0 },
         { .reg = 0x00009888, .val = 0x0A0A0006 },
         { .reg = 0x00009888, .val = 0x000A0A0A },
         { .reg = 0x00009888, .val = 0x020AAAA8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00020AAA },
         { .reg = 0x00009888, .val = 0x0202AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FE3F },
         { .reg = 0x00009888, .val = 0x00010555 },
         { .reg = 0x00009888, .val = 0x02015554 },
         { .reg = 0x00009888, .val = 0x00030AAA },
         { .reg = 0x00009888, .val = 0x0203AAA8 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010804 },
         { .reg = 0x00009888, .val = 0x5A010010 },
         { .reg = 0x00009888, .val = 0x5C010001 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010200 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext126__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext126__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext126__avg_gpu_core_frequency__max,mtlgt3__ext126__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6047, 24, NULL,mtlgt3__ext126__stripsfan_object_count_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6048, 32, NULL,mtlgt3__ext126__stripsfan_objects_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6049, 40, NULL,mtlgt3__ext126__clipper_transaction_output_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6051, 48, NULL,mtlgt3__ext126__clipper_primitive_cull_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6052, 56, percentage_max_float,mtlgt3__ext126__rasterizer_input_available_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6053, 60, percentage_max_float,mtlgt3__ext126__rasterizer_output_ready_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6050, 64, NULL,mtlgt3__ext126__rasterizer_transaction_output_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext127_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext127";
   query->symbol_name = "Ext127";
   query->guid = "1f70ab0a-6efd-461b-b06e-3b47d3602f36";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x1A230000 },
         { .reg = 0x00009888, .val = 0x16230014 },
         { .reg = 0x00009888, .val = 0x20237FC0 },
         { .reg = 0x00009888, .val = 0x262B7800 },
         { .reg = 0x00009888, .val = 0x282B0000 },
         { .reg = 0x00009888, .val = 0x16290400 },
         { .reg = 0x00009888, .val = 0x182A0001 },
         { .reg = 0x00009888, .val = 0x00210505 },
         { .reg = 0x00009888, .val = 0x02215554 },
         { .reg = 0x00009888, .val = 0x02230007 },
         { .reg = 0x00009888, .val = 0x04230008 },
         { .reg = 0x00009888, .val = 0x102300C2 },
         { .reg = 0x00009888, .val = 0x1223094B },
         { .reg = 0x00009888, .val = 0x14230B6A },
         { .reg = 0x00009888, .val = 0x00230000 },
         { .reg = 0x00009888, .val = 0x00240505 },
         { .reg = 0x00009888, .val = 0x0224AAA4 },
         { .reg = 0x00009888, .val = 0x042B0130 },
         { .reg = 0x00009888, .val = 0x082B0C80 },
         { .reg = 0x00009888, .val = 0x0A2B0030 },
         { .reg = 0x00009888, .val = 0x0E2B003C },
         { .reg = 0x00009888, .val = 0x022B0000 },
         { .reg = 0x00009888, .val = 0x002B0003 },
         { .reg = 0x00009888, .val = 0x04290004 },
         { .reg = 0x00009888, .val = 0x06291870 },
         { .reg = 0x00009888, .val = 0x08290000 },
         { .reg = 0x00009888, .val = 0x00290000 },
         { .reg = 0x00009888, .val = 0x042A0004 },
         { .reg = 0x00009888, .val = 0x082A01C0 },
         { .reg = 0x00009888, .val = 0x0A2A0006 },
         { .reg = 0x00009888, .val = 0x002A0A0A },
         { .reg = 0x00009888, .val = 0x022AAAA8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00820AAA },
         { .reg = 0x00009888, .val = 0x0282AAA8 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FE3F },
         { .reg = 0x00009888, .val = 0x0002FE3F },
         { .reg = 0x00009888, .val = 0x00010555 },
         { .reg = 0x00009888, .val = 0x02015554 },
         { .reg = 0x00009888, .val = 0x00030555 },
         { .reg = 0x00009888, .val = 0x02035554 },
         { .reg = 0x00009888, .val = 0x0004FE3F },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010804 },
         { .reg = 0x00009888, .val = 0x5A010010 },
         { .reg = 0x00009888, .val = 0x5C010001 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010200 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000180 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext127__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext127__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext127__avg_gpu_core_frequency__max,mtlgt3__ext127__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6831, 24, NULL,mtlgt3__ext127__stripsfan_object_count_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6832, 32, NULL,mtlgt3__ext127__stripsfan_objects_cull_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6833, 40, NULL,mtlgt3__ext127__clipper_transaction_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6834, 48, NULL,mtlgt3__ext127__rasterizer_transaction_output_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6835, 56, NULL,mtlgt3__ext127__clipper_primitive_cull_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6836, 64, percentage_max_float,mtlgt3__ext127__rasterizer_input_available_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6837, 68, percentage_max_float,mtlgt3__ext127__rasterizer_output_ready_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext128_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext128";
   query->symbol_name = "Ext128";
   query->guid = "9eedb03f-340b-40ec-8a66-43d01973003e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x1201F513 },
         { .reg = 0x00009888, .val = 0x1C010030 },
         { .reg = 0x00009888, .val = 0x1202F000 },
         { .reg = 0x00009888, .val = 0x14021800 },
         { .reg = 0x00009888, .val = 0x04016200 },
         { .reg = 0x00009888, .val = 0x0A010540 },
         { .reg = 0x00009888, .val = 0x0C0105D6 },
         { .reg = 0x00009888, .val = 0x10010480 },
         { .reg = 0x00009888, .val = 0x16010658 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x0001A02A },
         { .reg = 0x00009888, .val = 0x02010A02 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02029A50 },
         { .reg = 0x00009888, .val = 0x04020027 },
         { .reg = 0x00009888, .val = 0x080208E2 },
         { .reg = 0x00009888, .val = 0x0A020024 },
         { .reg = 0x00009888, .val = 0x0E020C70 },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext128__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext128__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext128__avg_gpu_core_frequency__max,mtlgt3__ext128__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6054, 24, NULL,mtlgt3__ext128__urb_read_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6055, 32, NULL,mtlgt3__ext128__urb_write_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6056, 40, NULL,mtlgt3__ext128__urb_cross_slice_read_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext129_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext129";
   query->symbol_name = "Ext129";
   query->guid = "0e5ffe58-83b2-445b-a439-9ee7a01642d4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x1221F79F },
         { .reg = 0x00009888, .val = 0x1C210030 },
         { .reg = 0x00009888, .val = 0x1222F000 },
         { .reg = 0x00009888, .val = 0x14221800 },
         { .reg = 0x00009888, .val = 0x04212600 },
         { .reg = 0x00009888, .val = 0x08210411 },
         { .reg = 0x00009888, .val = 0x0C2106DC },
         { .reg = 0x00009888, .val = 0x0E21001A },
         { .reg = 0x00009888, .val = 0x1421001D },
         { .reg = 0x00009888, .val = 0x06210000 },
         { .reg = 0x00009888, .val = 0x002180A0 },
         { .reg = 0x00009888, .val = 0x0221A80A },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x02220000 },
         { .reg = 0x00009888, .val = 0x04220C31 },
         { .reg = 0x00009888, .val = 0x08220900 },
         { .reg = 0x00009888, .val = 0x0A2208A3 },
         { .reg = 0x00009888, .val = 0x0E2209C0 },
         { .reg = 0x00009888, .val = 0x10220966 },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext129__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext129__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext129__avg_gpu_core_frequency__max,mtlgt3__ext129__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6838, 24, NULL,mtlgt3__ext129__urb_read_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6839, 32, NULL,mtlgt3__ext129__urb_write_slice1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6840, 40, NULL,mtlgt3__ext129__urb_cross_slice_read_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext130_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext130";
   query->symbol_name = "Ext130";
   query->guid = "78925a28-3e52-4d74-b03b-cb27c6a4401a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x10095400 },
         { .reg = 0x00009888, .val = 0x00010001 },
         { .reg = 0x00009888, .val = 0x02015540 },
         { .reg = 0x00009888, .val = 0x00040001 },
         { .reg = 0x00009888, .val = 0x02045540 },
         { .reg = 0x00009888, .val = 0x000BF801 },
         { .reg = 0x00009888, .val = 0x04090080 },
         { .reg = 0x00009888, .val = 0x06090150 },
         { .reg = 0x00009888, .val = 0x12090491 },
         { .reg = 0x00009888, .val = 0x14090513 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x000A0002 },
         { .reg = 0x00009888, .val = 0x020AAA80 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x00010001 },
         { .reg = 0x00009888, .val = 0x02015540 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x0203AA80 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000400A },
         { .reg = 0x0000D944, .val = 0x0000F7FE },
         { .reg = 0x0000D948, .val = 0x0000800A },
         { .reg = 0x0000D94C, .val = 0x0000EFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0002000A },
         { .reg = 0x0000D95C, .val = 0x0000BFFE },
         { .reg = 0x0000D960, .val = 0x0004000A },
         { .reg = 0x0000D964, .val = 0x00007FFE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext130__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext130__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext130__avg_gpu_core_frequency__max,mtlgt3__ext130__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6057, 24, NULL,mtlgt3__ext130__early_depth_stencil_test_fail_np_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6058, 32, NULL,mtlgt3__ext130__early_depth_stencil_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext131_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext131";
   query->symbol_name = "Ext131";
   query->guid = "1e91d8d9-ced4-4240-bf9e-fdd7d015c058";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x100A5000 },
         { .reg = 0x00009888, .val = 0x040A0080 },
         { .reg = 0x00009888, .val = 0x060A2A00 },
         { .reg = 0x00009888, .val = 0x120A04D4 },
         { .reg = 0x00009888, .val = 0x140A0452 },
         { .reg = 0x00009888, .val = 0x160A0010 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00020002 },
         { .reg = 0x00009888, .val = 0x0202AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x00010001 },
         { .reg = 0x00009888, .val = 0x02015540 },
         { .reg = 0x00009888, .val = 0x00030002 },
         { .reg = 0x00009888, .val = 0x0203AA80 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext131__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext131__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext131__avg_gpu_core_frequency__max,mtlgt3__ext131__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6059, 24, NULL,mtlgt3__ext131__early_depth_stencil_test_fail_np_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6060, 32, NULL,mtlgt3__ext131__early_depth_stencil_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext132_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext132";
   query->symbol_name = "Ext132";
   query->guid = "1cacf022-b4d4-401c-abec-acc0a3353adc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x10295500 },
         { .reg = 0x00009888, .val = 0x00210001 },
         { .reg = 0x00009888, .val = 0x02215540 },
         { .reg = 0x00009888, .val = 0x00240001 },
         { .reg = 0x00009888, .val = 0x02245540 },
         { .reg = 0x00009888, .val = 0x002BF801 },
         { .reg = 0x00009888, .val = 0x04290080 },
         { .reg = 0x00009888, .val = 0x06290150 },
         { .reg = 0x00009888, .val = 0x12290493 },
         { .reg = 0x00009888, .val = 0x14290411 },
         { .reg = 0x00009888, .val = 0x08290000 },
         { .reg = 0x00009888, .val = 0x00290000 },
         { .reg = 0x00009888, .val = 0x02290000 },
         { .reg = 0x00009888, .val = 0x002A0002 },
         { .reg = 0x00009888, .val = 0x022AAA80 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00820002 },
         { .reg = 0x00009888, .val = 0x0282AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F801 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x00010001 },
         { .reg = 0x00009888, .val = 0x02015540 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x0004F801 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext132__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext132__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext132__avg_gpu_core_frequency__max,mtlgt3__ext132__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6841, 24, NULL,mtlgt3__ext132__early_depth_stencil_test_fail_np_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6842, 32, NULL,mtlgt3__ext132__early_depth_stencil_test_fail_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext133_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext133";
   query->symbol_name = "Ext133";
   query->guid = "3c15657a-b3da-4513-8b9c-08bcc1ca0226";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x102A5000 },
         { .reg = 0x00009888, .val = 0x042A0080 },
         { .reg = 0x00009888, .val = 0x062A2A00 },
         { .reg = 0x00009888, .val = 0x122A04D4 },
         { .reg = 0x00009888, .val = 0x142A0452 },
         { .reg = 0x00009888, .val = 0x162A0010 },
         { .reg = 0x00009888, .val = 0x002A0000 },
         { .reg = 0x00009888, .val = 0x022A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x00820002 },
         { .reg = 0x00009888, .val = 0x0282AA80 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F801 },
         { .reg = 0x00009888, .val = 0x0002F801 },
         { .reg = 0x00009888, .val = 0x00010001 },
         { .reg = 0x00009888, .val = 0x02015540 },
         { .reg = 0x00009888, .val = 0x00030001 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x0004F801 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x10800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0004000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x0002000A },
         { .reg = 0x0000D94C, .val = 0x0000BFFE },
         { .reg = 0x0000D950, .val = 0x0001000A },
         { .reg = 0x0000D954, .val = 0x0000DFFE },
         { .reg = 0x0000D958, .val = 0x0000800A },
         { .reg = 0x0000D95C, .val = 0x0000EFFE },
         { .reg = 0x0000D960, .val = 0x0000400A },
         { .reg = 0x0000D964, .val = 0x0000F7FE },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext133__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext133__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext133__avg_gpu_core_frequency__max,mtlgt3__ext133__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6843, 24, NULL,mtlgt3__ext133__early_depth_stencil_test_fail_np_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6844, 32, NULL,mtlgt3__ext133__early_depth_stencil_test_fail_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext134_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext134";
   query->symbol_name = "Ext134";
   query->guid = "da34c79f-d1c6-4d15-b848-2085528bb86b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16095C00 },
         { .reg = 0x00009888, .val = 0x1809001F },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFE0 },
         { .reg = 0x00009888, .val = 0x0409002C },
         { .reg = 0x00009888, .val = 0x0A0900C0 },
         { .reg = 0x00009888, .val = 0x0C090144 },
         { .reg = 0x00009888, .val = 0x0E09038F },
         { .reg = 0x00009888, .val = 0x1009030D },
         { .reg = 0x00009888, .val = 0x1209028B },
         { .reg = 0x00009888, .val = 0x14090209 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A800 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A800 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext134__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext134__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext134__avg_gpu_core_frequency__max,mtlgt3__ext134__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6061, 24, NULL,mtlgt3__ext134__hiz_depth_test_ambig_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext135_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext135";
   query->symbol_name = "Ext135";
   query->guid = "33ceab81-26bc-49f3-a124-5dbb2d592a87";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x180A03F7 },
         { .reg = 0x00009888, .val = 0x040A002C },
         { .reg = 0x00009888, .val = 0x0C0A0103 },
         { .reg = 0x00009888, .val = 0x0E0A03C5 },
         { .reg = 0x00009888, .val = 0x100A034E },
         { .reg = 0x00009888, .val = 0x120A02CC },
         { .reg = 0x00009888, .val = 0x140A024A },
         { .reg = 0x00009888, .val = 0x160A0008 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A800 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A800 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext135__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext135__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext135__avg_gpu_core_frequency__max,mtlgt3__ext135__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6062, 24, NULL,mtlgt3__ext135__hiz_depth_test_ambig_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext136_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext136";
   query->symbol_name = "Ext136";
   query->guid = "d8b7d2f7-7c3a-4a68-b6c1-48d197b22945";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16295C00 },
         { .reg = 0x00009888, .val = 0x1829001F },
         { .reg = 0x00009888, .val = 0x00215400 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245400 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFE0 },
         { .reg = 0x00009888, .val = 0x0429002C },
         { .reg = 0x00009888, .val = 0x0A290140 },
         { .reg = 0x00009888, .val = 0x0C2900C4 },
         { .reg = 0x00009888, .val = 0x0E29038F },
         { .reg = 0x00009888, .val = 0x1029030D },
         { .reg = 0x00009888, .val = 0x1229028B },
         { .reg = 0x00009888, .val = 0x14290209 },
         { .reg = 0x00009888, .val = 0x08290000 },
         { .reg = 0x00009888, .val = 0x00290000 },
         { .reg = 0x00009888, .val = 0x02290000 },
         { .reg = 0x00009888, .val = 0x002AA800 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A800 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFE0 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035400 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFE0 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext136__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext136__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext136__avg_gpu_core_frequency__max,mtlgt3__ext136__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6845, 24, NULL,mtlgt3__ext136__hiz_depth_test_ambig_np_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext137_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext137";
   query->symbol_name = "Ext137";
   query->guid = "01d6bd34-b8d1-4412-b53b-0d16b327abec";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x182A03F7 },
         { .reg = 0x00009888, .val = 0x042A002C },
         { .reg = 0x00009888, .val = 0x0C2A0105 },
         { .reg = 0x00009888, .val = 0x0E2A03C3 },
         { .reg = 0x00009888, .val = 0x102A034E },
         { .reg = 0x00009888, .val = 0x122A02CC },
         { .reg = 0x00009888, .val = 0x142A024A },
         { .reg = 0x00009888, .val = 0x162A0008 },
         { .reg = 0x00009888, .val = 0x002A0000 },
         { .reg = 0x00009888, .val = 0x022A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A800 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFE0 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035400 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFE0 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext137__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext137__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext137__avg_gpu_core_frequency__max,mtlgt3__ext137__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6846, 24, NULL,mtlgt3__ext137__hiz_depth_test_ambig_np_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext138_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext138";
   query->symbol_name = "Ext138";
   query->guid = "7485f9ec-ac5f-4c6d-8c5f-6a023e7d29d5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16095800 },
         { .reg = 0x00009888, .val = 0x18090017 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFE0 },
         { .reg = 0x00009888, .val = 0x0409002C },
         { .reg = 0x00009888, .val = 0x0A090000 },
         { .reg = 0x00009888, .val = 0x0C090081 },
         { .reg = 0x00009888, .val = 0x0E090103 },
         { .reg = 0x00009888, .val = 0x10090185 },
         { .reg = 0x00009888, .val = 0x12090207 },
         { .reg = 0x00009888, .val = 0x14090289 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A800 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A800 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext138__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext138__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext138__avg_gpu_core_frequency__max,mtlgt3__ext138__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6063, 24, NULL,mtlgt3__ext138__hiz_depth_test_ambig_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext139_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext139";
   query->symbol_name = "Ext139";
   query->guid = "944dc12b-b2fd-4bf5-a59d-540e2b280cdd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x180A02F6 },
         { .reg = 0x00009888, .val = 0x040A002C },
         { .reg = 0x00009888, .val = 0x0C0A0040 },
         { .reg = 0x00009888, .val = 0x0E0A00C2 },
         { .reg = 0x00009888, .val = 0x100A0144 },
         { .reg = 0x00009888, .val = 0x120A01C6 },
         { .reg = 0x00009888, .val = 0x140A0248 },
         { .reg = 0x00009888, .val = 0x160A000A },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A800 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A800 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext139__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext139__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext139__avg_gpu_core_frequency__max,mtlgt3__ext139__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6064, 24, NULL,mtlgt3__ext139__hiz_depth_test_ambig_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext140_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext140";
   query->symbol_name = "Ext140";
   query->guid = "5c97330a-b407-4ef8-908f-7fdeec216f81";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16295C00 },
         { .reg = 0x00009888, .val = 0x18290016 },
         { .reg = 0x00009888, .val = 0x00215400 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245400 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFE0 },
         { .reg = 0x00009888, .val = 0x0429002C },
         { .reg = 0x00009888, .val = 0x0A290080 },
         { .reg = 0x00009888, .val = 0x0C290001 },
         { .reg = 0x00009888, .val = 0x0E29038F },
         { .reg = 0x00009888, .val = 0x1029030D },
         { .reg = 0x00009888, .val = 0x1229028B },
         { .reg = 0x00009888, .val = 0x14290209 },
         { .reg = 0x00009888, .val = 0x08290000 },
         { .reg = 0x00009888, .val = 0x00290000 },
         { .reg = 0x00009888, .val = 0x02290000 },
         { .reg = 0x00009888, .val = 0x002AA800 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A800 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFE0 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035400 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFE0 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext140__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext140__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext140__avg_gpu_core_frequency__max,mtlgt3__ext140__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6847, 24, NULL,mtlgt3__ext140__hiz_depth_test_ambig_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext141_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext141";
   query->symbol_name = "Ext141";
   query->guid = "65e4ac2a-db8f-4918-bdd6-ac4d85de160e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x182A02D7 },
         { .reg = 0x00009888, .val = 0x042A002C },
         { .reg = 0x00009888, .val = 0x0C2A0042 },
         { .reg = 0x00009888, .val = 0x0E2A03C0 },
         { .reg = 0x00009888, .val = 0x102A034E },
         { .reg = 0x00009888, .val = 0x122A02CC },
         { .reg = 0x00009888, .val = 0x142A024A },
         { .reg = 0x00009888, .val = 0x162A0008 },
         { .reg = 0x00009888, .val = 0x002A0000 },
         { .reg = 0x00009888, .val = 0x022A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A800 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFE0 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035400 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFE0 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext141__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext141__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext141__avg_gpu_core_frequency__max,mtlgt3__ext141__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6848, 24, NULL,mtlgt3__ext141__hiz_depth_test_ambig_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext142_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext142";
   query->symbol_name = "Ext142";
   query->guid = "0eb11775-ad71-44d4-ad2c-c2fa6431b144";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16094000 },
         { .reg = 0x00009888, .val = 0x18090012 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFE0 },
         { .reg = 0x00009888, .val = 0x0409002C },
         { .reg = 0x00009888, .val = 0x0A090000 },
         { .reg = 0x00009888, .val = 0x0C090081 },
         { .reg = 0x00009888, .val = 0x0E090103 },
         { .reg = 0x00009888, .val = 0x10090185 },
         { .reg = 0x00009888, .val = 0x120902C7 },
         { .reg = 0x00009888, .val = 0x1409034C },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A800 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A800 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext142__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext142__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext142__avg_gpu_core_frequency__max,mtlgt3__ext142__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6065, 24, NULL,mtlgt3__ext142__hiz_depth_test_fail_np_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext143_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext143";
   query->symbol_name = "Ext143";
   query->guid = "d7736d53-f1cb-4899-8f3d-d8aaad1f1c67";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x180A0250 },
         { .reg = 0x00009888, .val = 0x040A002C },
         { .reg = 0x00009888, .val = 0x0C0A0040 },
         { .reg = 0x00009888, .val = 0x0E0A00C2 },
         { .reg = 0x00009888, .val = 0x100A0144 },
         { .reg = 0x00009888, .val = 0x120A01C6 },
         { .reg = 0x00009888, .val = 0x140A030B },
         { .reg = 0x00009888, .val = 0x160A000D },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A800 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A800 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext143__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext143__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext143__avg_gpu_core_frequency__max,mtlgt3__ext143__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6066, 24, NULL,mtlgt3__ext143__hiz_depth_test_fail_np_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext144_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext144";
   query->symbol_name = "Ext144";
   query->guid = "496219cc-316b-4945-9fc4-180e60331262";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16294800 },
         { .reg = 0x00009888, .val = 0x18290010 },
         { .reg = 0x00009888, .val = 0x00215400 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245400 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFE0 },
         { .reg = 0x00009888, .val = 0x0429002C },
         { .reg = 0x00009888, .val = 0x0A290140 },
         { .reg = 0x00009888, .val = 0x0C2900C4 },
         { .reg = 0x00009888, .val = 0x0E29038F },
         { .reg = 0x00009888, .val = 0x1029030D },
         { .reg = 0x00009888, .val = 0x1229028B },
         { .reg = 0x00009888, .val = 0x14290209 },
         { .reg = 0x00009888, .val = 0x08290000 },
         { .reg = 0x00009888, .val = 0x00290000 },
         { .reg = 0x00009888, .val = 0x02290000 },
         { .reg = 0x00009888, .val = 0x002AA800 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A800 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFE0 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035400 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFE0 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext144__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext144__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext144__avg_gpu_core_frequency__max,mtlgt3__ext144__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6849, 24, NULL,mtlgt3__ext144__hiz_depth_test_fail_np_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext145_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext145";
   query->symbol_name = "Ext145";
   query->guid = "c7e6721e-51f9-40af-ba8b-0520a1082855";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x182A0212 },
         { .reg = 0x00009888, .val = 0x042A002C },
         { .reg = 0x00009888, .val = 0x0C2A0105 },
         { .reg = 0x00009888, .val = 0x0E2A03C3 },
         { .reg = 0x00009888, .val = 0x102A034E },
         { .reg = 0x00009888, .val = 0x122A02CC },
         { .reg = 0x00009888, .val = 0x142A024A },
         { .reg = 0x00009888, .val = 0x162A0008 },
         { .reg = 0x00009888, .val = 0x002A0000 },
         { .reg = 0x00009888, .val = 0x022A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A800 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFE0 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035400 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFE0 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext145__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext145__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext145__avg_gpu_core_frequency__max,mtlgt3__ext145__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6850, 24, NULL,mtlgt3__ext145__hiz_depth_test_fail_np_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext146_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext146";
   query->symbol_name = "Ext146";
   query->guid = "0e9b064c-9fa7-4e85-8aaa-cc871010117d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16094400 },
         { .reg = 0x00009888, .val = 0x18090012 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045400 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFE0 },
         { .reg = 0x00009888, .val = 0x0409002C },
         { .reg = 0x00009888, .val = 0x0A090000 },
         { .reg = 0x00009888, .val = 0x0C090081 },
         { .reg = 0x00009888, .val = 0x0E090103 },
         { .reg = 0x00009888, .val = 0x10090185 },
         { .reg = 0x00009888, .val = 0x12090207 },
         { .reg = 0x00009888, .val = 0x14090289 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x000AA800 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A800 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A800 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext146__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext146__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext146__avg_gpu_core_frequency__max,mtlgt3__ext146__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6067, 24, NULL,mtlgt3__ext146__hiz_depth_test_fail_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext147_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext147";
   query->symbol_name = "Ext147";
   query->guid = "44d73f02-f843-4717-a3d5-3d1dfbd3f106";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x180A0251 },
         { .reg = 0x00009888, .val = 0x040A002C },
         { .reg = 0x00009888, .val = 0x0C0A0040 },
         { .reg = 0x00009888, .val = 0x0E0A00C2 },
         { .reg = 0x00009888, .val = 0x100A0144 },
         { .reg = 0x00009888, .val = 0x120A01C6 },
         { .reg = 0x00009888, .val = 0x140A0248 },
         { .reg = 0x00009888, .val = 0x160A000A },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A800 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A800 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext147__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext147__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext147__avg_gpu_core_frequency__max,mtlgt3__ext147__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6068, 24, NULL,mtlgt3__ext147__hiz_depth_test_fail_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext148_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext148";
   query->symbol_name = "Ext148";
   query->guid = "b84f370e-1b64-41d1-a4d8-f095fb79e5f8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16294800 },
         { .reg = 0x00009888, .val = 0x18290011 },
         { .reg = 0x00009888, .val = 0x00215400 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245400 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFE0 },
         { .reg = 0x00009888, .val = 0x0429002C },
         { .reg = 0x00009888, .val = 0x0A290080 },
         { .reg = 0x00009888, .val = 0x0C290001 },
         { .reg = 0x00009888, .val = 0x0E29038F },
         { .reg = 0x00009888, .val = 0x1029030D },
         { .reg = 0x00009888, .val = 0x1229028B },
         { .reg = 0x00009888, .val = 0x14290209 },
         { .reg = 0x00009888, .val = 0x08290000 },
         { .reg = 0x00009888, .val = 0x00290000 },
         { .reg = 0x00009888, .val = 0x02290000 },
         { .reg = 0x00009888, .val = 0x002AA800 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A800 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFE0 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035400 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFE0 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext148__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext148__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext148__avg_gpu_core_frequency__max,mtlgt3__ext148__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6851, 24, NULL,mtlgt3__ext148__hiz_depth_test_fail_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext149_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext149";
   query->symbol_name = "Ext149";
   query->guid = "772a2c24-0a03-480e-baca-72f2f55a5422";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x182A0232 },
         { .reg = 0x00009888, .val = 0x042A002C },
         { .reg = 0x00009888, .val = 0x0C2A0042 },
         { .reg = 0x00009888, .val = 0x0E2A03C0 },
         { .reg = 0x00009888, .val = 0x102A034E },
         { .reg = 0x00009888, .val = 0x122A02CC },
         { .reg = 0x00009888, .val = 0x142A024A },
         { .reg = 0x00009888, .val = 0x162A0008 },
         { .reg = 0x00009888, .val = 0x002A0000 },
         { .reg = 0x00009888, .val = 0x022A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A800 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFE0 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x00015400 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035400 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFE0 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext149__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext149__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext149__avg_gpu_core_frequency__max,mtlgt3__ext149__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6852, 24, NULL,mtlgt3__ext149__hiz_depth_test_fail_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext150_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext150";
   query->symbol_name = "Ext150";
   query->guid = "953d3bf8-af3d-4287-ac22-dcd122c5eb51";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16095C00 },
         { .reg = 0x00009888, .val = 0x18090018 },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045000 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFC0 },
         { .reg = 0x00009888, .val = 0x0409002C },
         { .reg = 0x00009888, .val = 0x0C090187 },
         { .reg = 0x00009888, .val = 0x0E09038F },
         { .reg = 0x00009888, .val = 0x1009030D },
         { .reg = 0x00009888, .val = 0x1209028B },
         { .reg = 0x00009888, .val = 0x14090209 },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x000AA000 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A000 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFC0 },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A000 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext150__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext150__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext150__avg_gpu_core_frequency__max,mtlgt3__ext150__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6069, 24, NULL,mtlgt3__ext150__hiz_depth_test_pass_p_zpipe0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext151_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext151";
   query->symbol_name = "Ext151";
   query->guid = "dbb009c2-98ad-4af0-905a-e7808ac5424c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x180A0317 },
         { .reg = 0x00009888, .val = 0x040A002C },
         { .reg = 0x00009888, .val = 0x0C0A01C0 },
         { .reg = 0x00009888, .val = 0x0E0A03C6 },
         { .reg = 0x00009888, .val = 0x100A034E },
         { .reg = 0x00009888, .val = 0x120A02CC },
         { .reg = 0x00009888, .val = 0x140A024A },
         { .reg = 0x00009888, .val = 0x160A0008 },
         { .reg = 0x00009888, .val = 0x000A0000 },
         { .reg = 0x00009888, .val = 0x020A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002A000 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFC0 },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003A000 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext151__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext151__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext151__avg_gpu_core_frequency__max,mtlgt3__ext151__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6070, 24, NULL,mtlgt3__ext151__hiz_depth_test_pass_p_zpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext152_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext152";
   query->symbol_name = "Ext152";
   query->guid = "16fd8981-676d-4cbc-b010-8d731ba66a06";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16295C00 },
         { .reg = 0x00009888, .val = 0x18290018 },
         { .reg = 0x00009888, .val = 0x00215000 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245000 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFC0 },
         { .reg = 0x00009888, .val = 0x0429002C },
         { .reg = 0x00009888, .val = 0x0C290187 },
         { .reg = 0x00009888, .val = 0x0E29038F },
         { .reg = 0x00009888, .val = 0x1029030D },
         { .reg = 0x00009888, .val = 0x1229028B },
         { .reg = 0x00009888, .val = 0x14290209 },
         { .reg = 0x00009888, .val = 0x08290000 },
         { .reg = 0x00009888, .val = 0x00290000 },
         { .reg = 0x00009888, .val = 0x02290000 },
         { .reg = 0x00009888, .val = 0x002AA000 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A000 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFC0 },
         { .reg = 0x00009888, .val = 0x0002FFC0 },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035000 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFC0 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext152__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext152__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext152__avg_gpu_core_frequency__max,mtlgt3__ext152__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6853, 24, NULL,mtlgt3__ext152__hiz_depth_test_pass_p_zpipe2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext153_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext153";
   query->symbol_name = "Ext153";
   query->guid = "7bcdd766-98a5-461a-ac8e-d8c648958364";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x182A0317 },
         { .reg = 0x00009888, .val = 0x042A002C },
         { .reg = 0x00009888, .val = 0x0C2A01C0 },
         { .reg = 0x00009888, .val = 0x0E2A03C6 },
         { .reg = 0x00009888, .val = 0x102A034E },
         { .reg = 0x00009888, .val = 0x122A02CC },
         { .reg = 0x00009888, .val = 0x142A024A },
         { .reg = 0x00009888, .val = 0x162A0008 },
         { .reg = 0x00009888, .val = 0x002A0000 },
         { .reg = 0x00009888, .val = 0x022A0000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082A000 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFC0 },
         { .reg = 0x00009888, .val = 0x0002FFC0 },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035000 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFC0 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext153__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext153__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext153__avg_gpu_core_frequency__max,mtlgt3__ext153__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6854, 24, NULL,mtlgt3__ext153__hiz_depth_test_pass_p_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext154_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 15);

   query->name = "Ext154";
   query->symbol_name = "Ext154";
   query->guid = "c0459fa8-1790-46b8-a0f8-3064baf7c670";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x16092C00 },
         { .reg = 0x00009888, .val = 0x0C096015 },
         { .reg = 0x00009888, .val = 0x10096000 },
         { .reg = 0x00009888, .val = 0x180A000B },
         { .reg = 0x00009888, .val = 0x0C0A6002 },
         { .reg = 0x00009888, .val = 0x100A601E },
         { .reg = 0x00009888, .val = 0x16292C00 },
         { .reg = 0x00009888, .val = 0x0C296000 },
         { .reg = 0x00009888, .val = 0x10296580 },
         { .reg = 0x00009888, .val = 0x182A000B },
         { .reg = 0x00009888, .val = 0x0C2A6000 },
         { .reg = 0x00009888, .val = 0x102A6580 },
         { .reg = 0x00009888, .val = 0x00011100 },
         { .reg = 0x00009888, .val = 0x02010001 },
         { .reg = 0x00009888, .val = 0x00041100 },
         { .reg = 0x00009888, .val = 0x02040001 },
         { .reg = 0x00009888, .val = 0x000B0150 },
         { .reg = 0x00009888, .val = 0x04090084 },
         { .reg = 0x00009888, .val = 0x0A090002 },
         { .reg = 0x00009888, .val = 0x0E09001E },
         { .reg = 0x00009888, .val = 0x08090000 },
         { .reg = 0x00009888, .val = 0x00090000 },
         { .reg = 0x00009888, .val = 0x02090000 },
         { .reg = 0x00009888, .val = 0x040A0084 },
         { .reg = 0x00009888, .val = 0x0E0A0015 },
         { .reg = 0x00009888, .val = 0x000A2200 },
         { .reg = 0x00009888, .val = 0x020A0002 },
         { .reg = 0x00009888, .val = 0x02214440 },
         { .reg = 0x00009888, .val = 0x02244440 },
         { .reg = 0x00009888, .val = 0x002BA800 },
         { .reg = 0x00009888, .val = 0x04290404 },
         { .reg = 0x00009888, .val = 0x12290740 },
         { .reg = 0x00009888, .val = 0x14290080 },
         { .reg = 0x00009888, .val = 0x08290000 },
         { .reg = 0x00009888, .val = 0x02290000 },
         { .reg = 0x00009888, .val = 0x042A0404 },
         { .reg = 0x00009888, .val = 0x122A0740 },
         { .reg = 0x00009888, .val = 0x142A0080 },
         { .reg = 0x00009888, .val = 0x022A8880 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AA00 },
         { .reg = 0x00009888, .val = 0x0202000A },
         { .reg = 0x00009888, .val = 0x0282AAA0 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FC00 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x00015500 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AA00 },
         { .reg = 0x00009888, .val = 0x0203555A },
         { .reg = 0x00009888, .val = 0x0004FC00 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010406 },
         { .reg = 0x00009888, .val = 0x5E010060 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010C02 },
         { .reg = 0x00009888, .val = 0x4E010040 },
         { .reg = 0x00009888, .val = 0x50010800 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010004 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext154__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext154__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext154__avg_gpu_core_frequency__max,mtlgt3__ext154__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6071, 24, percentage_max_float,mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6072, 28, percentage_max_float,mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6073, 32, percentage_max_float,mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6074, 36, percentage_max_float,mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6075, 40, percentage_max_float,mtlgt3__ext154__iz_output_ready_zpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6076, 44, percentage_max_float,mtlgt3__ext154__iz_output_ready_zpipe1__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6855, 48, percentage_max_float,mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6856, 52, percentage_max_float,mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6857, 56, percentage_max_float,mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6858, 60, percentage_max_float,mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe3__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6859, 64, percentage_max_float,mtlgt3__ext154__iz_output_ready_zpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6860, 68, percentage_max_float,mtlgt3__ext154__iz_output_ready_zpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext155_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext155";
   query->symbol_name = "Ext155";
   query->guid = "304d9439-4bdd-48a9-a82e-15b3533afaf4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x18020010 },
         { .reg = 0x00009888, .val = 0x18010400 },
         { .reg = 0x00009888, .val = 0x20010200 },
         { .reg = 0x00009888, .val = 0x02020002 },
         { .reg = 0x00009888, .val = 0x0C020000 },
         { .reg = 0x00009888, .val = 0x0E020081 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x04010240 },
         { .reg = 0x00009888, .val = 0x08010000 },
         { .reg = 0x00009888, .val = 0x0A010081 },
         { .reg = 0x00009888, .val = 0x0C010248 },
         { .reg = 0x00009888, .val = 0x0E01000A },
         { .reg = 0x00009888, .val = 0x00015000 },
         { .reg = 0x00009888, .val = 0x02010001 },
         { .reg = 0x00009888, .val = 0x4C010200 },
         { .reg = 0x00009888, .val = 0x56010010 },
         { .reg = 0x00009888, .val = 0x58010201 },
         { .reg = 0x00009888, .val = 0x5A010010 },
         { .reg = 0x00009888, .val = 0x5C010001 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext155__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext155__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext155__avg_gpu_core_frequency__max,mtlgt3__ext155__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6077, 24, percentage_max_float,mtlgt3__ext155__command_parser_compute_engine_busy_ccs0__read);

      intel_perf_query_add_counter_float(query, 6078, 28, percentage_max_float,mtlgt3__ext155__command_parser_render_engine_busy__read);

      intel_perf_query_add_counter_float(query, 6079, 32, percentage_max_float,mtlgt3__ext155__command_parser_copy_engine_busy__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext156_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext156";
   query->symbol_name = "Ext156";
   query->guid = "90691d58-782d-459c-a242-f6e515fe9567";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x2001001F },
         { .reg = 0x00009888, .val = 0x1A012000 },
         { .reg = 0x00009888, .val = 0x040101A4 },
         { .reg = 0x00009888, .val = 0x08010000 },
         { .reg = 0x00009888, .val = 0x0A01028B },
         { .reg = 0x00009888, .val = 0x16010300 },
         { .reg = 0x00009888, .val = 0x18010008 },
         { .reg = 0x00009888, .val = 0x00010000 },
         { .reg = 0x00009888, .val = 0x02010000 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000002 },
         { .reg = 0x0000D944, .val = 0x0000FFFE },
         { .reg = 0x0000D948, .val = 0x00000030 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext156__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext156__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext156__avg_gpu_core_frequency__max,mtlgt3__ext156__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6080, 24, NULL,mtlgt3__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs0__read);

      intel_perf_query_add_counter_uint64(query, 6081, 32, NULL,mtlgt3__ext156__command_parser_render_engine_dispatch_kernel_count__read);

      intel_perf_query_add_counter_uint64(query, 6082, 40, NULL,mtlgt3__ext156__command_parser_render_engine_draw_count__read);

      intel_perf_query_add_counter_uint64(query, 6083, 48, NULL,mtlgt3__ext156__command_parser_flush_count__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext158_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext158";
   query->symbol_name = "Ext158";
   query->guid = "cf34a431-3cc9-4b70-a84e-0d31a71170f0";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18057C00 },
         { .reg = 0x00009888, .val = 0x18257C00 },
         { .reg = 0x00009888, .val = 0x18457C00 },
         { .reg = 0x00009888, .val = 0x18657C00 },
         { .reg = 0x00009888, .val = 0x18857C00 },
         { .reg = 0x00009888, .val = 0x18A57C00 },
         { .reg = 0x00009888, .val = 0x18C57C00 },
         { .reg = 0x00009888, .val = 0x18E57C00 },
         { .reg = 0x00009888, .val = 0x0202A000 },
         { .reg = 0x00009888, .val = 0x04050100 },
         { .reg = 0x00009888, .val = 0x14050580 },
         { .reg = 0x00009888, .val = 0x16050017 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x02085000 },
         { .reg = 0x00009888, .val = 0x02220A00 },
         { .reg = 0x00009888, .val = 0x04250100 },
         { .reg = 0x00009888, .val = 0x12250580 },
         { .reg = 0x00009888, .val = 0x14250017 },
         { .reg = 0x00009888, .val = 0x02250000 },
         { .reg = 0x00009888, .val = 0x02280500 },
         { .reg = 0x00009888, .val = 0x024200A0 },
         { .reg = 0x00009888, .val = 0x04450100 },
         { .reg = 0x00009888, .val = 0x10450580 },
         { .reg = 0x00009888, .val = 0x12450017 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02480050 },
         { .reg = 0x00009888, .val = 0x0262000A },
         { .reg = 0x00009888, .val = 0x04650100 },
         { .reg = 0x00009888, .val = 0x0E650580 },
         { .reg = 0x00009888, .val = 0x10650017 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x02680005 },
         { .reg = 0x00009888, .val = 0x0082A000 },
         { .reg = 0x00009888, .val = 0x04850100 },
         { .reg = 0x00009888, .val = 0x0C850580 },
         { .reg = 0x00009888, .val = 0x0E850017 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00885000 },
         { .reg = 0x00009888, .val = 0x00A20A00 },
         { .reg = 0x00009888, .val = 0x04A50100 },
         { .reg = 0x00009888, .val = 0x0AA50580 },
         { .reg = 0x00009888, .val = 0x0CA50017 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A80500 },
         { .reg = 0x00009888, .val = 0x00C200A0 },
         { .reg = 0x00009888, .val = 0x04C50100 },
         { .reg = 0x00009888, .val = 0x08C50580 },
         { .reg = 0x00009888, .val = 0x0AC50017 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C80050 },
         { .reg = 0x00009888, .val = 0x00E2000A },
         { .reg = 0x00009888, .val = 0x04E50100 },
         { .reg = 0x00009888, .val = 0x06E52C00 },
         { .reg = 0x00009888, .val = 0x08E50017 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x00E80005 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x020155F0 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x000BF000 },
         { .reg = 0x00009888, .val = 0x0209AF00 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009888, .val = 0x002155F0 },
         { .reg = 0x00009888, .val = 0x00245500 },
         { .reg = 0x00009888, .val = 0x002B00F0 },
         { .reg = 0x00009888, .val = 0x0029AF00 },
         { .reg = 0x00009888, .val = 0x002AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0202AAAF },
         { .reg = 0x00009888, .val = 0x0082AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x000500FF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x000400FF },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010603 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010E07 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010405 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010402 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext158__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext158__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext158__avg_gpu_core_frequency__max,mtlgt3__ext158__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6084, 24, NULL,mtlgt3__ext158__rt_input_message_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6085, 32, NULL,mtlgt3__ext158__rt_input_message_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6086, 40, NULL,mtlgt3__ext158__rt_input_message_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6087, 48, NULL,mtlgt3__ext158__rt_input_message_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6861, 56, NULL,mtlgt3__ext158__rt_input_message_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6862, 64, NULL,mtlgt3__ext158__rt_input_message_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6863, 72, NULL,mtlgt3__ext158__rt_input_message_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6864, 80, NULL,mtlgt3__ext158__rt_input_message_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext159_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext159";
   query->symbol_name = "Ext159";
   query->guid = "ad3cd014-8897-4613-8653-6d80c6eaff88";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20050105 },
         { .reg = 0x00009888, .val = 0x20250105 },
         { .reg = 0x00009888, .val = 0x20450105 },
         { .reg = 0x00009888, .val = 0x20650105 },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x06056F60 },
         { .reg = 0x00009888, .val = 0x08050FF5 },
         { .reg = 0x00009888, .val = 0x0A05003D },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080055 },
         { .reg = 0x00009888, .val = 0x0022AA00 },
         { .reg = 0x00009888, .val = 0x06250160 },
         { .reg = 0x00009888, .val = 0x0A250DC0 },
         { .reg = 0x00009888, .val = 0x0C250FF5 },
         { .reg = 0x00009888, .val = 0x0E25003D },
         { .reg = 0x00009888, .val = 0x04250000 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x00285500 },
         { .reg = 0x00009888, .val = 0x024200AA },
         { .reg = 0x00009888, .val = 0x06450160 },
         { .reg = 0x00009888, .val = 0x0E450DC0 },
         { .reg = 0x00009888, .val = 0x10450FF5 },
         { .reg = 0x00009888, .val = 0x1245003D },
         { .reg = 0x00009888, .val = 0x04450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02480055 },
         { .reg = 0x00009888, .val = 0x0262AA00 },
         { .reg = 0x00009888, .val = 0x06650160 },
         { .reg = 0x00009888, .val = 0x12650DC0 },
         { .reg = 0x00009888, .val = 0x14650FF5 },
         { .reg = 0x00009888, .val = 0x1665003D },
         { .reg = 0x00009888, .val = 0x04650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x02685500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext159__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext159__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext159__avg_gpu_core_frequency__max,mtlgt3__ext159__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6088, 24, NULL,mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6089, 32, NULL,mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6090, 40, NULL,mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6091, 48, NULL,mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext160_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext160";
   query->symbol_name = "Ext160";
   query->guid = "aa12de63-7d11-4acf-af96-be89807729f7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20850105 },
         { .reg = 0x00009888, .val = 0x20A50105 },
         { .reg = 0x00009888, .val = 0x20C50105 },
         { .reg = 0x00009888, .val = 0x20E50105 },
         { .reg = 0x00009888, .val = 0x008200AA },
         { .reg = 0x00009888, .val = 0x06856F60 },
         { .reg = 0x00009888, .val = 0x08850FF5 },
         { .reg = 0x00009888, .val = 0x0A85003D },
         { .reg = 0x00009888, .val = 0x04850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x00A2AA00 },
         { .reg = 0x00009888, .val = 0x06A50160 },
         { .reg = 0x00009888, .val = 0x0AA50DC0 },
         { .reg = 0x00009888, .val = 0x0CA50FF5 },
         { .reg = 0x00009888, .val = 0x0EA5003D },
         { .reg = 0x00009888, .val = 0x04A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x02C200AA },
         { .reg = 0x00009888, .val = 0x06C50160 },
         { .reg = 0x00009888, .val = 0x0EC50DC0 },
         { .reg = 0x00009888, .val = 0x10C50FF5 },
         { .reg = 0x00009888, .val = 0x12C5003D },
         { .reg = 0x00009888, .val = 0x04C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x02E2AA00 },
         { .reg = 0x00009888, .val = 0x06E50160 },
         { .reg = 0x00009888, .val = 0x12E50DC0 },
         { .reg = 0x00009888, .val = 0x14E50FF5 },
         { .reg = 0x00009888, .val = 0x16E5003D },
         { .reg = 0x00009888, .val = 0x04E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext160__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext160__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext160__avg_gpu_core_frequency__max,mtlgt3__ext160__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6865, 24, NULL,mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6866, 32, NULL,mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6867, 40, NULL,mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6868, 48, NULL,mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext161_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext161";
   query->symbol_name = "Ext161";
   query->guid = "ac013132-7e0c-4143-bc34-ea6428ce3082";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20050105 },
         { .reg = 0x00009888, .val = 0x20250105 },
         { .reg = 0x00009888, .val = 0x20450105 },
         { .reg = 0x00009888, .val = 0x20650105 },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x06056F60 },
         { .reg = 0x00009888, .val = 0x08050FF6 },
         { .reg = 0x00009888, .val = 0x0A05003E },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080055 },
         { .reg = 0x00009888, .val = 0x0022AA00 },
         { .reg = 0x00009888, .val = 0x06250160 },
         { .reg = 0x00009888, .val = 0x0A250DC0 },
         { .reg = 0x00009888, .val = 0x0C250FF6 },
         { .reg = 0x00009888, .val = 0x0E25003E },
         { .reg = 0x00009888, .val = 0x04250000 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x00285500 },
         { .reg = 0x00009888, .val = 0x024200AA },
         { .reg = 0x00009888, .val = 0x06450160 },
         { .reg = 0x00009888, .val = 0x0E450DC0 },
         { .reg = 0x00009888, .val = 0x10450FF6 },
         { .reg = 0x00009888, .val = 0x1245003E },
         { .reg = 0x00009888, .val = 0x04450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02480055 },
         { .reg = 0x00009888, .val = 0x0262AA00 },
         { .reg = 0x00009888, .val = 0x06650160 },
         { .reg = 0x00009888, .val = 0x12650DC0 },
         { .reg = 0x00009888, .val = 0x14650FF6 },
         { .reg = 0x00009888, .val = 0x1665003E },
         { .reg = 0x00009888, .val = 0x04650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x02685500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext161__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext161__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext161__avg_gpu_core_frequency__max,mtlgt3__ext161__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6092, 24, NULL,mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6093, 32, NULL,mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6094, 40, NULL,mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6095, 48, NULL,mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext162_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext162";
   query->symbol_name = "Ext162";
   query->guid = "b9d8323a-7bb4-41b5-b99b-43ed99e23590";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20850105 },
         { .reg = 0x00009888, .val = 0x20A50105 },
         { .reg = 0x00009888, .val = 0x20C50105 },
         { .reg = 0x00009888, .val = 0x20E50105 },
         { .reg = 0x00009888, .val = 0x008200AA },
         { .reg = 0x00009888, .val = 0x06856F60 },
         { .reg = 0x00009888, .val = 0x08850FF6 },
         { .reg = 0x00009888, .val = 0x0A85003E },
         { .reg = 0x00009888, .val = 0x04850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x00A2AA00 },
         { .reg = 0x00009888, .val = 0x06A50160 },
         { .reg = 0x00009888, .val = 0x0AA50DC0 },
         { .reg = 0x00009888, .val = 0x0CA50FF6 },
         { .reg = 0x00009888, .val = 0x0EA5003E },
         { .reg = 0x00009888, .val = 0x04A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x02C200AA },
         { .reg = 0x00009888, .val = 0x06C50160 },
         { .reg = 0x00009888, .val = 0x0EC50DC0 },
         { .reg = 0x00009888, .val = 0x10C50FF6 },
         { .reg = 0x00009888, .val = 0x12C5003E },
         { .reg = 0x00009888, .val = 0x04C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x02E2AA00 },
         { .reg = 0x00009888, .val = 0x06E50160 },
         { .reg = 0x00009888, .val = 0x12E50DC0 },
         { .reg = 0x00009888, .val = 0x14E50FF6 },
         { .reg = 0x00009888, .val = 0x16E5003E },
         { .reg = 0x00009888, .val = 0x04E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext162__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext162__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext162__avg_gpu_core_frequency__max,mtlgt3__ext162__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6869, 24, NULL,mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6870, 32, NULL,mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6871, 40, NULL,mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6872, 48, NULL,mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext163_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext163";
   query->symbol_name = "Ext163";
   query->guid = "6ae2c19e-672c-4ad6-9d59-0a391af1af4f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20050105 },
         { .reg = 0x00009888, .val = 0x20250105 },
         { .reg = 0x00009888, .val = 0x20450105 },
         { .reg = 0x00009888, .val = 0x20650105 },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x06056F60 },
         { .reg = 0x00009888, .val = 0x08050FF4 },
         { .reg = 0x00009888, .val = 0x0A05003C },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080055 },
         { .reg = 0x00009888, .val = 0x0022AA00 },
         { .reg = 0x00009888, .val = 0x06250160 },
         { .reg = 0x00009888, .val = 0x0A250DC0 },
         { .reg = 0x00009888, .val = 0x0C250FF4 },
         { .reg = 0x00009888, .val = 0x0E25003C },
         { .reg = 0x00009888, .val = 0x04250000 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x00285500 },
         { .reg = 0x00009888, .val = 0x024200AA },
         { .reg = 0x00009888, .val = 0x06450160 },
         { .reg = 0x00009888, .val = 0x0E450DC0 },
         { .reg = 0x00009888, .val = 0x10450FF4 },
         { .reg = 0x00009888, .val = 0x1245003C },
         { .reg = 0x00009888, .val = 0x04450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02480055 },
         { .reg = 0x00009888, .val = 0x0262AA00 },
         { .reg = 0x00009888, .val = 0x06650160 },
         { .reg = 0x00009888, .val = 0x12650DC0 },
         { .reg = 0x00009888, .val = 0x14650FF4 },
         { .reg = 0x00009888, .val = 0x1665003C },
         { .reg = 0x00009888, .val = 0x04650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x02685500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext163__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext163__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext163__avg_gpu_core_frequency__max,mtlgt3__ext163__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6096, 24, NULL,mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6097, 32, NULL,mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6098, 40, NULL,mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6099, 48, NULL,mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext164_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext164";
   query->symbol_name = "Ext164";
   query->guid = "c76b6b40-9d7f-48f6-b6da-595252c884f4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20850105 },
         { .reg = 0x00009888, .val = 0x20A50105 },
         { .reg = 0x00009888, .val = 0x20C50105 },
         { .reg = 0x00009888, .val = 0x20E50105 },
         { .reg = 0x00009888, .val = 0x008200AA },
         { .reg = 0x00009888, .val = 0x06856F60 },
         { .reg = 0x00009888, .val = 0x08850FF4 },
         { .reg = 0x00009888, .val = 0x0A85003C },
         { .reg = 0x00009888, .val = 0x04850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x00A2AA00 },
         { .reg = 0x00009888, .val = 0x06A50160 },
         { .reg = 0x00009888, .val = 0x0AA50DC0 },
         { .reg = 0x00009888, .val = 0x0CA50FF4 },
         { .reg = 0x00009888, .val = 0x0EA5003C },
         { .reg = 0x00009888, .val = 0x04A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x02C200AA },
         { .reg = 0x00009888, .val = 0x06C50160 },
         { .reg = 0x00009888, .val = 0x0EC50DC0 },
         { .reg = 0x00009888, .val = 0x10C50FF4 },
         { .reg = 0x00009888, .val = 0x12C5003C },
         { .reg = 0x00009888, .val = 0x04C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x02E2AA00 },
         { .reg = 0x00009888, .val = 0x06E50160 },
         { .reg = 0x00009888, .val = 0x12E50DC0 },
         { .reg = 0x00009888, .val = 0x14E50FF4 },
         { .reg = 0x00009888, .val = 0x16E5003C },
         { .reg = 0x00009888, .val = 0x04E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext164__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext164__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext164__avg_gpu_core_frequency__max,mtlgt3__ext164__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6873, 24, NULL,mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6874, 32, NULL,mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6875, 40, NULL,mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6876, 48, NULL,mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext165_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext165";
   query->symbol_name = "Ext165";
   query->guid = "a85da4d8-d984-45f3-8dbe-c8678eac8aae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20050105 },
         { .reg = 0x00009888, .val = 0x20250105 },
         { .reg = 0x00009888, .val = 0x20450105 },
         { .reg = 0x00009888, .val = 0x20650105 },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x06056F60 },
         { .reg = 0x00009888, .val = 0x08050FF3 },
         { .reg = 0x00009888, .val = 0x0A05003B },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080055 },
         { .reg = 0x00009888, .val = 0x0022AA00 },
         { .reg = 0x00009888, .val = 0x06250160 },
         { .reg = 0x00009888, .val = 0x0A250DC0 },
         { .reg = 0x00009888, .val = 0x0C250FF3 },
         { .reg = 0x00009888, .val = 0x0E25003B },
         { .reg = 0x00009888, .val = 0x04250000 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x00285500 },
         { .reg = 0x00009888, .val = 0x024200AA },
         { .reg = 0x00009888, .val = 0x06450160 },
         { .reg = 0x00009888, .val = 0x0E450DC0 },
         { .reg = 0x00009888, .val = 0x10450FF3 },
         { .reg = 0x00009888, .val = 0x1245003B },
         { .reg = 0x00009888, .val = 0x04450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02480055 },
         { .reg = 0x00009888, .val = 0x0262AA00 },
         { .reg = 0x00009888, .val = 0x06650160 },
         { .reg = 0x00009888, .val = 0x12650DC0 },
         { .reg = 0x00009888, .val = 0x14650FF3 },
         { .reg = 0x00009888, .val = 0x1665003B },
         { .reg = 0x00009888, .val = 0x04650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x02685500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext165__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext165__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext165__avg_gpu_core_frequency__max,mtlgt3__ext165__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6100, 24, NULL,mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6101, 32, NULL,mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6102, 40, NULL,mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6103, 48, NULL,mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext166_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext166";
   query->symbol_name = "Ext166";
   query->guid = "fbc7362e-4d05-451d-833e-f0ce5e7ad8e3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20850105 },
         { .reg = 0x00009888, .val = 0x20A50105 },
         { .reg = 0x00009888, .val = 0x20C50105 },
         { .reg = 0x00009888, .val = 0x20E50105 },
         { .reg = 0x00009888, .val = 0x008200AA },
         { .reg = 0x00009888, .val = 0x06856F60 },
         { .reg = 0x00009888, .val = 0x08850FF3 },
         { .reg = 0x00009888, .val = 0x0A85003B },
         { .reg = 0x00009888, .val = 0x04850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x00A2AA00 },
         { .reg = 0x00009888, .val = 0x06A50160 },
         { .reg = 0x00009888, .val = 0x0AA50DC0 },
         { .reg = 0x00009888, .val = 0x0CA50FF3 },
         { .reg = 0x00009888, .val = 0x0EA5003B },
         { .reg = 0x00009888, .val = 0x04A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x02C200AA },
         { .reg = 0x00009888, .val = 0x06C50160 },
         { .reg = 0x00009888, .val = 0x0EC50DC0 },
         { .reg = 0x00009888, .val = 0x10C50FF3 },
         { .reg = 0x00009888, .val = 0x12C5003B },
         { .reg = 0x00009888, .val = 0x04C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x02E2AA00 },
         { .reg = 0x00009888, .val = 0x06E50160 },
         { .reg = 0x00009888, .val = 0x12E50DC0 },
         { .reg = 0x00009888, .val = 0x14E50FF3 },
         { .reg = 0x00009888, .val = 0x16E5003B },
         { .reg = 0x00009888, .val = 0x04E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext166__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext166__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext166__avg_gpu_core_frequency__max,mtlgt3__ext166__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6877, 24, NULL,mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6878, 32, NULL,mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6879, 40, NULL,mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6880, 48, NULL,mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext167_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext167";
   query->symbol_name = "Ext167";
   query->guid = "881454da-d271-41ba-9dfb-0cc354fb5aea";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20050105 },
         { .reg = 0x00009888, .val = 0x20250105 },
         { .reg = 0x00009888, .val = 0x20450105 },
         { .reg = 0x00009888, .val = 0x20650105 },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x06056F60 },
         { .reg = 0x00009888, .val = 0x08050FF2 },
         { .reg = 0x00009888, .val = 0x0A05003A },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080055 },
         { .reg = 0x00009888, .val = 0x0022AA00 },
         { .reg = 0x00009888, .val = 0x06250160 },
         { .reg = 0x00009888, .val = 0x0A250DC0 },
         { .reg = 0x00009888, .val = 0x0C250FF2 },
         { .reg = 0x00009888, .val = 0x0E25003A },
         { .reg = 0x00009888, .val = 0x04250000 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x00285500 },
         { .reg = 0x00009888, .val = 0x024200AA },
         { .reg = 0x00009888, .val = 0x06450160 },
         { .reg = 0x00009888, .val = 0x0E450DC0 },
         { .reg = 0x00009888, .val = 0x10450FF2 },
         { .reg = 0x00009888, .val = 0x1245003A },
         { .reg = 0x00009888, .val = 0x04450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02480055 },
         { .reg = 0x00009888, .val = 0x0262AA00 },
         { .reg = 0x00009888, .val = 0x06650160 },
         { .reg = 0x00009888, .val = 0x12650DC0 },
         { .reg = 0x00009888, .val = 0x14650FF2 },
         { .reg = 0x00009888, .val = 0x1665003A },
         { .reg = 0x00009888, .val = 0x04650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x02685500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext167__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext167__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext167__avg_gpu_core_frequency__max,mtlgt3__ext167__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6104, 24, NULL,mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6105, 32, NULL,mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6106, 40, NULL,mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6107, 48, NULL,mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext168_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext168";
   query->symbol_name = "Ext168";
   query->guid = "9f2b827b-01c6-4e82-b283-dfe91af30d88";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20850105 },
         { .reg = 0x00009888, .val = 0x20A50105 },
         { .reg = 0x00009888, .val = 0x20C50105 },
         { .reg = 0x00009888, .val = 0x20E50105 },
         { .reg = 0x00009888, .val = 0x008200AA },
         { .reg = 0x00009888, .val = 0x06856F60 },
         { .reg = 0x00009888, .val = 0x08850FF2 },
         { .reg = 0x00009888, .val = 0x0A85003A },
         { .reg = 0x00009888, .val = 0x04850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x00A2AA00 },
         { .reg = 0x00009888, .val = 0x06A50160 },
         { .reg = 0x00009888, .val = 0x0AA50DC0 },
         { .reg = 0x00009888, .val = 0x0CA50FF2 },
         { .reg = 0x00009888, .val = 0x0EA5003A },
         { .reg = 0x00009888, .val = 0x04A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x02C200AA },
         { .reg = 0x00009888, .val = 0x06C50160 },
         { .reg = 0x00009888, .val = 0x0EC50DC0 },
         { .reg = 0x00009888, .val = 0x10C50FF2 },
         { .reg = 0x00009888, .val = 0x12C5003A },
         { .reg = 0x00009888, .val = 0x04C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x02E2AA00 },
         { .reg = 0x00009888, .val = 0x06E50160 },
         { .reg = 0x00009888, .val = 0x12E50DC0 },
         { .reg = 0x00009888, .val = 0x14E50FF2 },
         { .reg = 0x00009888, .val = 0x16E5003A },
         { .reg = 0x00009888, .val = 0x04E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext168__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext168__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext168__avg_gpu_core_frequency__max,mtlgt3__ext168__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6881, 24, NULL,mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6882, 32, NULL,mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6883, 40, NULL,mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6884, 48, NULL,mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext169_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext169";
   query->symbol_name = "Ext169";
   query->guid = "c6b40da2-4783-45d7-8252-9a4f1f75faf4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2005022F },
         { .reg = 0x00009888, .val = 0x2025022F },
         { .reg = 0x00009888, .val = 0x2045022F },
         { .reg = 0x00009888, .val = 0x2065022F },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x06056160 },
         { .reg = 0x00009888, .val = 0x08050E31 },
         { .reg = 0x00009888, .val = 0x0A050039 },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080055 },
         { .reg = 0x00009888, .val = 0x0022AA00 },
         { .reg = 0x00009888, .val = 0x06250160 },
         { .reg = 0x00009888, .val = 0x0A250C00 },
         { .reg = 0x00009888, .val = 0x0C250E31 },
         { .reg = 0x00009888, .val = 0x0E250039 },
         { .reg = 0x00009888, .val = 0x04250000 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x00285500 },
         { .reg = 0x00009888, .val = 0x024200AA },
         { .reg = 0x00009888, .val = 0x06450160 },
         { .reg = 0x00009888, .val = 0x0E450C00 },
         { .reg = 0x00009888, .val = 0x10450E31 },
         { .reg = 0x00009888, .val = 0x12450039 },
         { .reg = 0x00009888, .val = 0x04450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02480055 },
         { .reg = 0x00009888, .val = 0x0262AA00 },
         { .reg = 0x00009888, .val = 0x06650160 },
         { .reg = 0x00009888, .val = 0x12650C00 },
         { .reg = 0x00009888, .val = 0x14650E31 },
         { .reg = 0x00009888, .val = 0x16650039 },
         { .reg = 0x00009888, .val = 0x04650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x02685500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext169__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext169__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext169__avg_gpu_core_frequency__max,mtlgt3__ext169__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6108, 24, NULL,mtlgt3__ext169__rt_traversal_output_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6109, 32, NULL,mtlgt3__ext169__rt_traversal_output_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6110, 40, NULL,mtlgt3__ext169__rt_traversal_output_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6111, 48, NULL,mtlgt3__ext169__rt_traversal_output_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext170_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext170";
   query->symbol_name = "Ext170";
   query->guid = "b5883529-3595-412d-b40f-b7ade9cc3304";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2085022F },
         { .reg = 0x00009888, .val = 0x20A5022F },
         { .reg = 0x00009888, .val = 0x20C5022F },
         { .reg = 0x00009888, .val = 0x20E5022F },
         { .reg = 0x00009888, .val = 0x008200AA },
         { .reg = 0x00009888, .val = 0x06856160 },
         { .reg = 0x00009888, .val = 0x08850E31 },
         { .reg = 0x00009888, .val = 0x0A850039 },
         { .reg = 0x00009888, .val = 0x04850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x00A2AA00 },
         { .reg = 0x00009888, .val = 0x06A50160 },
         { .reg = 0x00009888, .val = 0x0AA50C00 },
         { .reg = 0x00009888, .val = 0x0CA50E31 },
         { .reg = 0x00009888, .val = 0x0EA50039 },
         { .reg = 0x00009888, .val = 0x04A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x02C200AA },
         { .reg = 0x00009888, .val = 0x06C50160 },
         { .reg = 0x00009888, .val = 0x0EC50C00 },
         { .reg = 0x00009888, .val = 0x10C50E31 },
         { .reg = 0x00009888, .val = 0x12C50039 },
         { .reg = 0x00009888, .val = 0x04C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x02E2AA00 },
         { .reg = 0x00009888, .val = 0x06E50160 },
         { .reg = 0x00009888, .val = 0x12E50C00 },
         { .reg = 0x00009888, .val = 0x14E50E31 },
         { .reg = 0x00009888, .val = 0x16E50039 },
         { .reg = 0x00009888, .val = 0x04E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext170__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext170__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext170__avg_gpu_core_frequency__max,mtlgt3__ext170__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6885, 24, NULL,mtlgt3__ext170__rt_traversal_output_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6886, 32, NULL,mtlgt3__ext170__rt_traversal_output_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6887, 40, NULL,mtlgt3__ext170__rt_traversal_output_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6888, 48, NULL,mtlgt3__ext170__rt_traversal_output_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext171_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext171";
   query->symbol_name = "Ext171";
   query->guid = "2455c20b-95bb-4e9f-8db2-597ba9447025";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18057800 },
         { .reg = 0x00009888, .val = 0x14051000 },
         { .reg = 0x00009888, .val = 0x18257800 },
         { .reg = 0x00009888, .val = 0x14251BC0 },
         { .reg = 0x00009888, .val = 0x18457800 },
         { .reg = 0x00009888, .val = 0x1445102F },
         { .reg = 0x00009888, .val = 0x18657800 },
         { .reg = 0x00009888, .val = 0x14651000 },
         { .reg = 0x00009888, .val = 0x0002A000 },
         { .reg = 0x00009888, .val = 0x02028080 },
         { .reg = 0x00009888, .val = 0x04054100 },
         { .reg = 0x00009888, .val = 0x06050005 },
         { .reg = 0x00009888, .val = 0x0C050800 },
         { .reg = 0x00009888, .val = 0x0E050015 },
         { .reg = 0x00009888, .val = 0x1205002C },
         { .reg = 0x00009888, .val = 0x1605002F },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00085000 },
         { .reg = 0x00009888, .val = 0x02084040 },
         { .reg = 0x00009888, .val = 0x00220082 },
         { .reg = 0x00009888, .val = 0x02222020 },
         { .reg = 0x00009888, .val = 0x04254100 },
         { .reg = 0x00009888, .val = 0x06252A05 },
         { .reg = 0x00009888, .val = 0x0A250020 },
         { .reg = 0x00009888, .val = 0x10250B00 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x02250000 },
         { .reg = 0x00009888, .val = 0x00280041 },
         { .reg = 0x00009888, .val = 0x02281010 },
         { .reg = 0x00009888, .val = 0x00420208 },
         { .reg = 0x00009888, .val = 0x02420808 },
         { .reg = 0x00009888, .val = 0x04454100 },
         { .reg = 0x00009888, .val = 0x06450005 },
         { .reg = 0x00009888, .val = 0x08450015 },
         { .reg = 0x00009888, .val = 0x0A450800 },
         { .reg = 0x00009888, .val = 0x1045002C },
         { .reg = 0x00009888, .val = 0x00450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x00480104 },
         { .reg = 0x00009888, .val = 0x02480404 },
         { .reg = 0x00009888, .val = 0x00620820 },
         { .reg = 0x00009888, .val = 0x02620202 },
         { .reg = 0x00009888, .val = 0x04654100 },
         { .reg = 0x00009888, .val = 0x06650005 },
         { .reg = 0x00009888, .val = 0x08650540 },
         { .reg = 0x00009888, .val = 0x0C650020 },
         { .reg = 0x00009888, .val = 0x0E650B00 },
         { .reg = 0x00009888, .val = 0x12650BC0 },
         { .reg = 0x00009888, .val = 0x00650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x00680410 },
         { .reg = 0x00009888, .val = 0x02680101 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001534D },
         { .reg = 0x00009888, .val = 0x02015C5C },
         { .reg = 0x00009888, .val = 0x00045041 },
         { .reg = 0x00009888, .val = 0x02045050 },
         { .reg = 0x00009888, .val = 0x000BCCC9 },
         { .reg = 0x00009888, .val = 0x0009A0C3 },
         { .reg = 0x00009888, .val = 0x0209B0B0 },
         { .reg = 0x00009888, .val = 0x000AA28A },
         { .reg = 0x00009888, .val = 0x020AA8A8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AEBA },
         { .reg = 0x00009888, .val = 0x0202ABAB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010005 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010005 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010605 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010A00 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext171__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext171__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext171__avg_gpu_core_frequency__max,mtlgt3__ext171__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6112, 24, NULL,mtlgt3__ext171__rt_quad_test_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6113, 32, NULL,mtlgt3__ext171__rt_quad_test_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6114, 40, NULL,mtlgt3__ext171__rt_quad_test_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6115, 48, NULL,mtlgt3__ext171__rt_quad_test_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6116, 56, NULL,mtlgt3__ext171__rt_transform_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6117, 64, NULL,mtlgt3__ext171__rt_transform_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6118, 72, NULL,mtlgt3__ext171__rt_transform_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6119, 80, NULL,mtlgt3__ext171__rt_transform_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6120, 88, NULL,mtlgt3__ext171__rt_request_collision_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6121, 96, NULL,mtlgt3__ext171__rt_request_collision_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6122, 104, NULL,mtlgt3__ext171__rt_request_collision_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6123, 112, NULL,mtlgt3__ext171__rt_request_collision_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6124, 120, percentage_max_float,mtlgt3__ext171__rt_message_stall_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6125, 124, percentage_max_float,mtlgt3__ext171__rt_message_stall_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6126, 128, percentage_max_float,mtlgt3__ext171__rt_message_stall_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6127, 132, percentage_max_float,mtlgt3__ext171__rt_message_stall_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext172_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext172";
   query->symbol_name = "Ext172";
   query->guid = "ec18cd0b-7caa-48d0-9a16-418ecbe1096e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18857800 },
         { .reg = 0x00009888, .val = 0x14851000 },
         { .reg = 0x00009888, .val = 0x18A57800 },
         { .reg = 0x00009888, .val = 0x14A51BC0 },
         { .reg = 0x00009888, .val = 0x18C57800 },
         { .reg = 0x00009888, .val = 0x14C5102F },
         { .reg = 0x00009888, .val = 0x18E57800 },
         { .reg = 0x00009888, .val = 0x14E51000 },
         { .reg = 0x00009888, .val = 0x00828080 },
         { .reg = 0x00009888, .val = 0x02828080 },
         { .reg = 0x00009888, .val = 0x04854100 },
         { .reg = 0x00009888, .val = 0x06850005 },
         { .reg = 0x00009888, .val = 0x0A850015 },
         { .reg = 0x00009888, .val = 0x0E850020 },
         { .reg = 0x00009888, .val = 0x1285002C },
         { .reg = 0x00009888, .val = 0x1685002F },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x02850000 },
         { .reg = 0x00009888, .val = 0x00884040 },
         { .reg = 0x00009888, .val = 0x02884040 },
         { .reg = 0x00009888, .val = 0x00A22020 },
         { .reg = 0x00009888, .val = 0x02A22020 },
         { .reg = 0x00009888, .val = 0x04A54100 },
         { .reg = 0x00009888, .val = 0x06A50005 },
         { .reg = 0x00009888, .val = 0x08A50540 },
         { .reg = 0x00009888, .val = 0x0CA50800 },
         { .reg = 0x00009888, .val = 0x10A50B00 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A50000 },
         { .reg = 0x00009888, .val = 0x00A81010 },
         { .reg = 0x00009888, .val = 0x02A81010 },
         { .reg = 0x00009888, .val = 0x00C20808 },
         { .reg = 0x00009888, .val = 0x02C20808 },
         { .reg = 0x00009888, .val = 0x04C54100 },
         { .reg = 0x00009888, .val = 0x06C50005 },
         { .reg = 0x00009888, .val = 0x08C50015 },
         { .reg = 0x00009888, .val = 0x0CC50020 },
         { .reg = 0x00009888, .val = 0x10C5002C },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x00C80404 },
         { .reg = 0x00009888, .val = 0x02C80404 },
         { .reg = 0x00009888, .val = 0x00E20202 },
         { .reg = 0x00009888, .val = 0x02E20202 },
         { .reg = 0x00009888, .val = 0x04E54100 },
         { .reg = 0x00009888, .val = 0x06E52A05 },
         { .reg = 0x00009888, .val = 0x0AE50800 },
         { .reg = 0x00009888, .val = 0x0EE50B00 },
         { .reg = 0x00009888, .val = 0x12E50BC0 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x00E80101 },
         { .reg = 0x00009888, .val = 0x02E80101 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215C5C },
         { .reg = 0x00009888, .val = 0x02215C5C },
         { .reg = 0x00009888, .val = 0x00245050 },
         { .reg = 0x00009888, .val = 0x02245050 },
         { .reg = 0x00009888, .val = 0x002BCCCC },
         { .reg = 0x00009888, .val = 0x0029B0B0 },
         { .reg = 0x00009888, .val = 0x0229B0B0 },
         { .reg = 0x00009888, .val = 0x002AA8A8 },
         { .reg = 0x00009888, .val = 0x022AA8A8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082ABAB },
         { .reg = 0x00009888, .val = 0x0282ABAB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010030 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010003 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010605 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010A00 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext172__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext172__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext172__avg_gpu_core_frequency__max,mtlgt3__ext172__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6889, 24, NULL,mtlgt3__ext172__rt_quad_test_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6890, 32, NULL,mtlgt3__ext172__rt_quad_test_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6891, 40, NULL,mtlgt3__ext172__rt_quad_test_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6892, 48, NULL,mtlgt3__ext172__rt_quad_test_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6893, 56, NULL,mtlgt3__ext172__rt_transform_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6894, 64, NULL,mtlgt3__ext172__rt_transform_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6895, 72, NULL,mtlgt3__ext172__rt_transform_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6896, 80, NULL,mtlgt3__ext172__rt_transform_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6897, 88, NULL,mtlgt3__ext172__rt_request_collision_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6898, 96, NULL,mtlgt3__ext172__rt_request_collision_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6899, 104, NULL,mtlgt3__ext172__rt_request_collision_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6900, 112, NULL,mtlgt3__ext172__rt_request_collision_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6901, 120, percentage_max_float,mtlgt3__ext172__rt_message_stall_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6902, 124, percentage_max_float,mtlgt3__ext172__rt_message_stall_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6903, 128, percentage_max_float,mtlgt3__ext172__rt_message_stall_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6904, 132, percentage_max_float,mtlgt3__ext172__rt_message_stall_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext173_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext173";
   query->symbol_name = "Ext173";
   query->guid = "3628b2de-d9f9-4db2-a74f-32a314e591c5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B000236 },
         { .reg = 0x00009888, .val = 0x0D00016A },
         { .reg = 0x00009888, .val = 0x010052B2 },
         { .reg = 0x00009888, .val = 0x030062F3 },
         { .reg = 0x00009888, .val = 0x05001CC1 },
         { .reg = 0x00009888, .val = 0x09000A11 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x00025555 },
         { .reg = 0x00009888, .val = 0x02025501 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035501 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045501 },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x02085501 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045501 },
         { .reg = 0x00009888, .val = 0x000BF1FF },
         { .reg = 0x00009888, .val = 0x0009AAAA },
         { .reg = 0x00009888, .val = 0x0209AA02 },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA02 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA02 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F1FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AA02 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext173__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext173__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext173__avg_gpu_core_frequency__max,mtlgt3__ext173__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6128, 24, percentage_max_float,mtlgt3__ext173__xve_stall_aluwr_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6129, 28, percentage_max_float,mtlgt3__ext173__xve_stall_barrier_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6130, 32, percentage_max_float,mtlgt3__ext173__xve_stall_instfetch_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6131, 36, percentage_max_float,mtlgt3__ext173__xve_stall_other_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6132, 40, percentage_max_float,mtlgt3__ext173__xve_stall_sbid_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6133, 44, percentage_max_float,mtlgt3__ext173__xve_shared_function_access_hold_xecore0_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6134, 48, percentage_max_float,mtlgt3__ext173__xve_stall_control_xecore0_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext174_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext174";
   query->symbol_name = "Ext174";
   query->guid = "d35ecd39-0a9d-48f7-bf87-d3c318b8fadd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B200236 },
         { .reg = 0x00009888, .val = 0x0D20016A },
         { .reg = 0x00009888, .val = 0x012052B2 },
         { .reg = 0x00009888, .val = 0x032062F3 },
         { .reg = 0x00009888, .val = 0x05201CC1 },
         { .reg = 0x00009888, .val = 0x09200A30 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215501 },
         { .reg = 0x00009888, .val = 0x00225555 },
         { .reg = 0x00009888, .val = 0x02225501 },
         { .reg = 0x00009888, .val = 0x00235555 },
         { .reg = 0x00009888, .val = 0x02235501 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245501 },
         { .reg = 0x00009888, .val = 0x00285555 },
         { .reg = 0x00009888, .val = 0x02285501 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045501 },
         { .reg = 0x00009888, .val = 0x000BF1FF },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x0209FF03 },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA02 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA02 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F1FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AA02 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext174__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext174__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext174__avg_gpu_core_frequency__max,mtlgt3__ext174__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6135, 24, percentage_max_float,mtlgt3__ext174__xve_stall_aluwr_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6136, 28, percentage_max_float,mtlgt3__ext174__xve_stall_barrier_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6137, 32, percentage_max_float,mtlgt3__ext174__xve_stall_instfetch_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6138, 36, percentage_max_float,mtlgt3__ext174__xve_stall_other_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6139, 40, percentage_max_float,mtlgt3__ext174__xve_stall_sbid_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6140, 44, percentage_max_float,mtlgt3__ext174__xve_shared_function_access_hold_xecore1_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6141, 48, percentage_max_float,mtlgt3__ext174__xve_stall_control_xecore1_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext175_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext175";
   query->symbol_name = "Ext175";
   query->guid = "d0d0e9cc-494c-4b01-8a43-683aae5beaff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B400236 },
         { .reg = 0x00009888, .val = 0x0D40016A },
         { .reg = 0x00009888, .val = 0x014052B2 },
         { .reg = 0x00009888, .val = 0x034062F3 },
         { .reg = 0x00009888, .val = 0x05401CC1 },
         { .reg = 0x00009888, .val = 0x09400A30 },
         { .reg = 0x00009888, .val = 0x00415555 },
         { .reg = 0x00009888, .val = 0x02415501 },
         { .reg = 0x00009888, .val = 0x00425555 },
         { .reg = 0x00009888, .val = 0x02425501 },
         { .reg = 0x00009888, .val = 0x00435555 },
         { .reg = 0x00009888, .val = 0x02435501 },
         { .reg = 0x00009888, .val = 0x00445555 },
         { .reg = 0x00009888, .val = 0x02445501 },
         { .reg = 0x00009888, .val = 0x00485555 },
         { .reg = 0x00009888, .val = 0x02485501 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FF03 },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA02 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AA02 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F1FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AA02 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext175__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext175__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext175__avg_gpu_core_frequency__max,mtlgt3__ext175__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6142, 24, percentage_max_float,mtlgt3__ext175__xve_stall_aluwr_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6143, 28, percentage_max_float,mtlgt3__ext175__xve_stall_barrier_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6144, 32, percentage_max_float,mtlgt3__ext175__xve_stall_instfetch_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6145, 36, percentage_max_float,mtlgt3__ext175__xve_stall_other_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6146, 40, percentage_max_float,mtlgt3__ext175__xve_stall_sbid_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6147, 44, percentage_max_float,mtlgt3__ext175__xve_shared_function_access_hold_xecore2_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6148, 48, percentage_max_float,mtlgt3__ext175__xve_stall_control_xecore2_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext176_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext176";
   query->symbol_name = "Ext176";
   query->guid = "c5fde834-52c8-411b-854e-8d3197def109";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B600236 },
         { .reg = 0x00009888, .val = 0x0D60016A },
         { .reg = 0x00009888, .val = 0x016052B2 },
         { .reg = 0x00009888, .val = 0x036062F3 },
         { .reg = 0x00009888, .val = 0x05601CC1 },
         { .reg = 0x00009888, .val = 0x09600A30 },
         { .reg = 0x00009888, .val = 0x00615555 },
         { .reg = 0x00009888, .val = 0x02615501 },
         { .reg = 0x00009888, .val = 0x00625555 },
         { .reg = 0x00009888, .val = 0x02625501 },
         { .reg = 0x00009888, .val = 0x00635555 },
         { .reg = 0x00009888, .val = 0x02635501 },
         { .reg = 0x00009888, .val = 0x00645555 },
         { .reg = 0x00009888, .val = 0x02645501 },
         { .reg = 0x00009888, .val = 0x00685555 },
         { .reg = 0x00009888, .val = 0x02685501 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FF03 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F1FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AA02 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext176__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext176__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext176__avg_gpu_core_frequency__max,mtlgt3__ext176__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6149, 24, percentage_max_float,mtlgt3__ext176__xve_stall_aluwr_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6150, 28, percentage_max_float,mtlgt3__ext176__xve_stall_barrier_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6151, 32, percentage_max_float,mtlgt3__ext176__xve_stall_instfetch_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6152, 36, percentage_max_float,mtlgt3__ext176__xve_stall_other_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6153, 40, percentage_max_float,mtlgt3__ext176__xve_stall_sbid_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6154, 44, percentage_max_float,mtlgt3__ext176__xve_shared_function_access_hold_xecore3_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6155, 48, percentage_max_float,mtlgt3__ext176__xve_stall_control_xecore3_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext177_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext177";
   query->symbol_name = "Ext177";
   query->guid = "55830ebd-062b-40e8-8d5c-e921429957ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B800236 },
         { .reg = 0x00009888, .val = 0x0D80016A },
         { .reg = 0x00009888, .val = 0x018052B2 },
         { .reg = 0x00009888, .val = 0x038062F3 },
         { .reg = 0x00009888, .val = 0x05801CC1 },
         { .reg = 0x00009888, .val = 0x09804051 },
         { .reg = 0x00009888, .val = 0x00815555 },
         { .reg = 0x00009888, .val = 0x02815501 },
         { .reg = 0x00009888, .val = 0x00825555 },
         { .reg = 0x00009888, .val = 0x02825501 },
         { .reg = 0x00009888, .val = 0x00835555 },
         { .reg = 0x00009888, .val = 0x02835501 },
         { .reg = 0x00009888, .val = 0x00845555 },
         { .reg = 0x00009888, .val = 0x02845501 },
         { .reg = 0x00009888, .val = 0x00885555 },
         { .reg = 0x00009888, .val = 0x02885501 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215501 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245501 },
         { .reg = 0x00009888, .val = 0x002BF1FF },
         { .reg = 0x00009888, .val = 0x0029AAAA },
         { .reg = 0x00009888, .val = 0x0229AA02 },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAA02 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AA02 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F1FF },
         { .reg = 0x00009888, .val = 0x0002F1FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035501 },
         { .reg = 0x00009888, .val = 0x0004F1FF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext177__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext177__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext177__avg_gpu_core_frequency__max,mtlgt3__ext177__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6905, 24, percentage_max_float,mtlgt3__ext177__xve_stall_aluwr_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6906, 28, percentage_max_float,mtlgt3__ext177__xve_stall_barrier_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6907, 32, percentage_max_float,mtlgt3__ext177__xve_stall_instfetch_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6908, 36, percentage_max_float,mtlgt3__ext177__xve_stall_other_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6909, 40, percentage_max_float,mtlgt3__ext177__xve_stall_sbid_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6910, 44, percentage_max_float,mtlgt3__ext177__xve_shared_function_access_hold_xecore4_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6911, 48, percentage_max_float,mtlgt3__ext177__xve_stall_control_xecore4_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext178_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext178";
   query->symbol_name = "Ext178";
   query->guid = "9603d88f-e5bf-47b4-85fd-fbbb68f42632";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0BA00236 },
         { .reg = 0x00009888, .val = 0x0DA0016A },
         { .reg = 0x00009888, .val = 0x01A052B2 },
         { .reg = 0x00009888, .val = 0x03A062F3 },
         { .reg = 0x00009888, .val = 0x05A01CC1 },
         { .reg = 0x00009888, .val = 0x09A04051 },
         { .reg = 0x00009888, .val = 0x00A15555 },
         { .reg = 0x00009888, .val = 0x02A15501 },
         { .reg = 0x00009888, .val = 0x00A25555 },
         { .reg = 0x00009888, .val = 0x02A25501 },
         { .reg = 0x00009888, .val = 0x00A35555 },
         { .reg = 0x00009888, .val = 0x02A35501 },
         { .reg = 0x00009888, .val = 0x00A45555 },
         { .reg = 0x00009888, .val = 0x02A45501 },
         { .reg = 0x00009888, .val = 0x00A85555 },
         { .reg = 0x00009888, .val = 0x02A85501 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215501 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245501 },
         { .reg = 0x00009888, .val = 0x002BF1FF },
         { .reg = 0x00009888, .val = 0x0029FFFF },
         { .reg = 0x00009888, .val = 0x0229FF03 },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAA02 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AA02 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F1FF },
         { .reg = 0x00009888, .val = 0x0002F1FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035501 },
         { .reg = 0x00009888, .val = 0x0004F1FF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext178__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext178__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext178__avg_gpu_core_frequency__max,mtlgt3__ext178__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6912, 24, percentage_max_float,mtlgt3__ext178__xve_stall_aluwr_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6913, 28, percentage_max_float,mtlgt3__ext178__xve_stall_barrier_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6914, 32, percentage_max_float,mtlgt3__ext178__xve_stall_instfetch_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6915, 36, percentage_max_float,mtlgt3__ext178__xve_stall_other_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6916, 40, percentage_max_float,mtlgt3__ext178__xve_stall_sbid_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6917, 44, percentage_max_float,mtlgt3__ext178__xve_shared_function_access_hold_xecore5_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6918, 48, percentage_max_float,mtlgt3__ext178__xve_stall_control_xecore5_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext179_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext179";
   query->symbol_name = "Ext179";
   query->guid = "b05bd7bd-387f-4fd7-a1b4-06a1dab5bc14";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0BC00236 },
         { .reg = 0x00009888, .val = 0x0DC0016A },
         { .reg = 0x00009888, .val = 0x01C052B2 },
         { .reg = 0x00009888, .val = 0x03C062F3 },
         { .reg = 0x00009888, .val = 0x05C01CC1 },
         { .reg = 0x00009888, .val = 0x09C04051 },
         { .reg = 0x00009888, .val = 0x00C15555 },
         { .reg = 0x00009888, .val = 0x02C15501 },
         { .reg = 0x00009888, .val = 0x00C25555 },
         { .reg = 0x00009888, .val = 0x02C25501 },
         { .reg = 0x00009888, .val = 0x00C35555 },
         { .reg = 0x00009888, .val = 0x02C35501 },
         { .reg = 0x00009888, .val = 0x00C45555 },
         { .reg = 0x00009888, .val = 0x02C45501 },
         { .reg = 0x00009888, .val = 0x00C85555 },
         { .reg = 0x00009888, .val = 0x02C85501 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021FFFF },
         { .reg = 0x00009888, .val = 0x0221FF03 },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAA02 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AA02 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F1FF },
         { .reg = 0x00009888, .val = 0x0002F1FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035501 },
         { .reg = 0x00009888, .val = 0x0004F1FF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext179__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext179__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext179__avg_gpu_core_frequency__max,mtlgt3__ext179__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6919, 24, percentage_max_float,mtlgt3__ext179__xve_stall_aluwr_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6920, 28, percentage_max_float,mtlgt3__ext179__xve_stall_barrier_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6921, 32, percentage_max_float,mtlgt3__ext179__xve_stall_instfetch_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6922, 36, percentage_max_float,mtlgt3__ext179__xve_stall_other_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6923, 40, percentage_max_float,mtlgt3__ext179__xve_stall_sbid_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6924, 44, percentage_max_float,mtlgt3__ext179__xve_shared_function_access_hold_xecore6_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6925, 48, percentage_max_float,mtlgt3__ext179__xve_stall_control_xecore6_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext180_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 10);

   query->name = "Ext180";
   query->symbol_name = "Ext180";
   query->guid = "49dc9023-be7b-4102-a4a2-d31b9a6b1ce4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0BE00236 },
         { .reg = 0x00009888, .val = 0x0DE0016A },
         { .reg = 0x00009888, .val = 0x01E052B2 },
         { .reg = 0x00009888, .val = 0x03E062F3 },
         { .reg = 0x00009888, .val = 0x05E01CC1 },
         { .reg = 0x00009888, .val = 0x09E04051 },
         { .reg = 0x00009888, .val = 0x00E15555 },
         { .reg = 0x00009888, .val = 0x02E15501 },
         { .reg = 0x00009888, .val = 0x00E25555 },
         { .reg = 0x00009888, .val = 0x02E25501 },
         { .reg = 0x00009888, .val = 0x00E35555 },
         { .reg = 0x00009888, .val = 0x02E35501 },
         { .reg = 0x00009888, .val = 0x00E45555 },
         { .reg = 0x00009888, .val = 0x02E45501 },
         { .reg = 0x00009888, .val = 0x00E85555 },
         { .reg = 0x00009888, .val = 0x02E85501 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FFFF },
         { .reg = 0x00009888, .val = 0x0282FF03 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F1FF },
         { .reg = 0x00009888, .val = 0x0002F1FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015501 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035501 },
         { .reg = 0x00009888, .val = 0x0004F1FF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000018 },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x000003E0 },
         { .reg = 0x0000D94C, .val = 0x0000FF83 },
         { .reg = 0x0000D950, .val = 0x00000002 },
         { .reg = 0x0000D954, .val = 0x0000FE7F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext180__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext180__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext180__avg_gpu_core_frequency__max,mtlgt3__ext180__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6926, 24, percentage_max_float,mtlgt3__ext180__xve_stall_aluwr_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6927, 28, percentage_max_float,mtlgt3__ext180__xve_stall_barrier_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6928, 32, percentage_max_float,mtlgt3__ext180__xve_stall_instfetch_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6929, 36, percentage_max_float,mtlgt3__ext180__xve_stall_other_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6930, 40, percentage_max_float,mtlgt3__ext180__xve_stall_sbid_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6931, 44, percentage_max_float,mtlgt3__ext180__xve_shared_function_access_hold_xecore7_xve0_thread0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6932, 48, percentage_max_float,mtlgt3__ext180__xve_stall_control_xecore7_xve0_thread0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext181_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext181";
   query->symbol_name = "Ext181";
   query->guid = "871d8a6b-7c73-4cd7-a4ed-4bdb58d5b6ee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B006F40 },
         { .reg = 0x00009888, .val = 0x0D000006 },
         { .reg = 0x00009888, .val = 0x0B206F40 },
         { .reg = 0x00009888, .val = 0x0D200006 },
         { .reg = 0x00009888, .val = 0x0B406F40 },
         { .reg = 0x00009888, .val = 0x0D400006 },
         { .reg = 0x00009888, .val = 0x01004EB4 },
         { .reg = 0x00009888, .val = 0x03000166 },
         { .reg = 0x00009888, .val = 0x00010155 },
         { .reg = 0x00009888, .val = 0x00020155 },
         { .reg = 0x00009888, .val = 0x00030155 },
         { .reg = 0x00009888, .val = 0x00040155 },
         { .reg = 0x00009888, .val = 0x00080155 },
         { .reg = 0x00009888, .val = 0x03205000 },
         { .reg = 0x00009888, .val = 0x05201A75 },
         { .reg = 0x00009888, .val = 0x0720000B },
         { .reg = 0x00009888, .val = 0x01200000 },
         { .reg = 0x00009888, .val = 0x00215400 },
         { .reg = 0x00009888, .val = 0x02210005 },
         { .reg = 0x00009888, .val = 0x00225400 },
         { .reg = 0x00009888, .val = 0x02220005 },
         { .reg = 0x00009888, .val = 0x00235400 },
         { .reg = 0x00009888, .val = 0x02230005 },
         { .reg = 0x00009888, .val = 0x00245400 },
         { .reg = 0x00009888, .val = 0x02240005 },
         { .reg = 0x00009888, .val = 0x00285400 },
         { .reg = 0x00009888, .val = 0x02280005 },
         { .reg = 0x00009888, .val = 0x07405680 },
         { .reg = 0x00009888, .val = 0x09402CD3 },
         { .reg = 0x00009888, .val = 0x01400000 },
         { .reg = 0x00009888, .val = 0x02411550 },
         { .reg = 0x00009888, .val = 0x02421550 },
         { .reg = 0x00009888, .val = 0x02431550 },
         { .reg = 0x00009888, .val = 0x02441550 },
         { .reg = 0x00009888, .val = 0x02481550 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02013FF5 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x000B03FF },
         { .reg = 0x00009888, .val = 0x0009FEAA },
         { .reg = 0x00009888, .val = 0x0209000F },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A2AAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02022AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00027FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02011555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02032AAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010003 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000F8 },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F00 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E000 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext181__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext181__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext181__avg_gpu_core_frequency__max,mtlgt3__ext181__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6162, 24, NULL,mtlgt3__ext181__xve_inst_issued_all_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6163, 32, NULL,mtlgt3__ext181__xve_inst_issued_all_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6164, 40, NULL,mtlgt3__ext181__xve_inst_issued_all_xecore2_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext182_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 6);

   query->name = "Ext182";
   query->symbol_name = "Ext182";
   query->guid = "25a2f80d-147e-4363-a0cb-53584b7a837d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B806F40 },
         { .reg = 0x00009888, .val = 0x0D800006 },
         { .reg = 0x00009888, .val = 0x0BA06F40 },
         { .reg = 0x00009888, .val = 0x0DA00006 },
         { .reg = 0x00009888, .val = 0x0BC06F40 },
         { .reg = 0x00009888, .val = 0x0DC00006 },
         { .reg = 0x00009888, .val = 0x01804EB4 },
         { .reg = 0x00009888, .val = 0x03800166 },
         { .reg = 0x00009888, .val = 0x00810155 },
         { .reg = 0x00009888, .val = 0x00820155 },
         { .reg = 0x00009888, .val = 0x00830155 },
         { .reg = 0x00009888, .val = 0x00840155 },
         { .reg = 0x00009888, .val = 0x00880155 },
         { .reg = 0x00009888, .val = 0x03A05000 },
         { .reg = 0x00009888, .val = 0x05A01A75 },
         { .reg = 0x00009888, .val = 0x07A0000B },
         { .reg = 0x00009888, .val = 0x01A00000 },
         { .reg = 0x00009888, .val = 0x00A15400 },
         { .reg = 0x00009888, .val = 0x02A10005 },
         { .reg = 0x00009888, .val = 0x00A25400 },
         { .reg = 0x00009888, .val = 0x02A20005 },
         { .reg = 0x00009888, .val = 0x00A35400 },
         { .reg = 0x00009888, .val = 0x02A30005 },
         { .reg = 0x00009888, .val = 0x00A45400 },
         { .reg = 0x00009888, .val = 0x02A40005 },
         { .reg = 0x00009888, .val = 0x00A85400 },
         { .reg = 0x00009888, .val = 0x02A80005 },
         { .reg = 0x00009888, .val = 0x07C05680 },
         { .reg = 0x00009888, .val = 0x09C02CD3 },
         { .reg = 0x00009888, .val = 0x01C00000 },
         { .reg = 0x00009888, .val = 0x02C11550 },
         { .reg = 0x00009888, .val = 0x02C21550 },
         { .reg = 0x00009888, .val = 0x02C31550 },
         { .reg = 0x00009888, .val = 0x02C41550 },
         { .reg = 0x00009888, .val = 0x02C81550 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02213FF5 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02240005 },
         { .reg = 0x00009888, .val = 0x002B03FF },
         { .reg = 0x00009888, .val = 0x0029FEAA },
         { .reg = 0x00009888, .val = 0x0229000F },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A2AAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x02822AAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00057FFF },
         { .reg = 0x00009888, .val = 0x00027FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02011555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02031555 },
         { .reg = 0x00009888, .val = 0x00047FFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010603 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010003 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x70800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000F8 },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
         { .reg = 0x0000D948, .val = 0x00001F00 },
         { .reg = 0x0000D94C, .val = 0x0000FC1F },
         { .reg = 0x0000D950, .val = 0x0003E000 },
         { .reg = 0x0000D954, .val = 0x000083FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext182__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext182__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext182__avg_gpu_core_frequency__max,mtlgt3__ext182__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6933, 24, NULL,mtlgt3__ext182__xve_inst_issued_all_xecore4_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6934, 32, NULL,mtlgt3__ext182__xve_inst_issued_all_xecore5_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6935, 40, NULL,mtlgt3__ext182__xve_inst_issued_all_xecore6_xve0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext183_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext183";
   query->symbol_name = "Ext183";
   query->guid = "71863fcf-d57c-433b-858f-87f5f11ec3da";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0D000006 },
         { .reg = 0x00009888, .val = 0x0D200006 },
         { .reg = 0x00009888, .val = 0x0D400006 },
         { .reg = 0x00009888, .val = 0x0B606F40 },
         { .reg = 0x00009888, .val = 0x0D600006 },
         { .reg = 0x00009888, .val = 0x0B000016 },
         { .reg = 0x00009888, .val = 0x01000000 },
         { .reg = 0x00009888, .val = 0x02014000 },
         { .reg = 0x00009888, .val = 0x02024000 },
         { .reg = 0x00009888, .val = 0x02034000 },
         { .reg = 0x00009888, .val = 0x02044000 },
         { .reg = 0x00009888, .val = 0x02084000 },
         { .reg = 0x00009888, .val = 0x09205800 },
         { .reg = 0x00009888, .val = 0x01200000 },
         { .reg = 0x00009888, .val = 0x02211000 },
         { .reg = 0x00009888, .val = 0x02221000 },
         { .reg = 0x00009888, .val = 0x02231000 },
         { .reg = 0x00009888, .val = 0x02241000 },
         { .reg = 0x00009888, .val = 0x02281000 },
         { .reg = 0x00009888, .val = 0x094002C0 },
         { .reg = 0x00009888, .val = 0x01400000 },
         { .reg = 0x00009888, .val = 0x02410400 },
         { .reg = 0x00009888, .val = 0x02420400 },
         { .reg = 0x00009888, .val = 0x02430400 },
         { .reg = 0x00009888, .val = 0x02440400 },
         { .reg = 0x00009888, .val = 0x02480400 },
         { .reg = 0x00009888, .val = 0x01604EB4 },
         { .reg = 0x00009888, .val = 0x03600166 },
         { .reg = 0x00009888, .val = 0x09600016 },
         { .reg = 0x00009888, .val = 0x00610155 },
         { .reg = 0x00009888, .val = 0x02610100 },
         { .reg = 0x00009888, .val = 0x00620155 },
         { .reg = 0x00009888, .val = 0x02620100 },
         { .reg = 0x00009888, .val = 0x00630155 },
         { .reg = 0x00009888, .val = 0x02630100 },
         { .reg = 0x00009888, .val = 0x00640155 },
         { .reg = 0x00009888, .val = 0x02640100 },
         { .reg = 0x00009888, .val = 0x00680155 },
         { .reg = 0x00009888, .val = 0x02680100 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x180203C0 },
         { .reg = 0x00009888, .val = 0x04020000 },
         { .reg = 0x00009888, .val = 0x10020940 },
         { .reg = 0x00009888, .val = 0x000203FF },
         { .reg = 0x00009888, .val = 0x0202AB00 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x02015C00 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x000BC000 },
         { .reg = 0x00009888, .val = 0x0209B000 },
         { .reg = 0x00009888, .val = 0x020AA800 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002F81F },
         { .reg = 0x00009888, .val = 0x00010155 },
         { .reg = 0x00009888, .val = 0x02015540 },
         { .reg = 0x00009888, .val = 0x000302AA },
         { .reg = 0x00009888, .val = 0x0203AA80 },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010200 },
         { .reg = 0x00009888, .val = 0x50010A07 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000F8 },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext183__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext183__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext183__avg_gpu_core_frequency__max,mtlgt3__ext183__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6156, 24, percentage_max_float,mtlgt3__ext183__xve_stall_pipestall_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6157, 28, percentage_max_float,mtlgt3__ext183__xve_stall_pipestall_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6158, 32, percentage_max_float,mtlgt3__ext183__xve_stall_pipestall_xecore2_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6159, 36, percentage_max_float,mtlgt3__ext183__xve_stall_pipestall_xecore3_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6160, 40, NULL,mtlgt3__ext183__xve_inst_issued_all_xecore3_xve0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6161, 48, NULL,mtlgt3__ext183__render_cache_alloc_l3_node0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext184_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 9);

   query->name = "Ext184";
   query->symbol_name = "Ext184";
   query->guid = "c29640d9-39eb-4a03-9043-2a54eb5a3112";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0D800006 },
         { .reg = 0x00009888, .val = 0x0DA00006 },
         { .reg = 0x00009888, .val = 0x0DC00006 },
         { .reg = 0x00009888, .val = 0x0BE06F40 },
         { .reg = 0x00009888, .val = 0x0DE00006 },
         { .reg = 0x00009888, .val = 0x0B800016 },
         { .reg = 0x00009888, .val = 0x01800000 },
         { .reg = 0x00009888, .val = 0x02814000 },
         { .reg = 0x00009888, .val = 0x02824000 },
         { .reg = 0x00009888, .val = 0x02834000 },
         { .reg = 0x00009888, .val = 0x02844000 },
         { .reg = 0x00009888, .val = 0x02884000 },
         { .reg = 0x00009888, .val = 0x09A05800 },
         { .reg = 0x00009888, .val = 0x01A00000 },
         { .reg = 0x00009888, .val = 0x02A11000 },
         { .reg = 0x00009888, .val = 0x02A21000 },
         { .reg = 0x00009888, .val = 0x02A31000 },
         { .reg = 0x00009888, .val = 0x02A41000 },
         { .reg = 0x00009888, .val = 0x02A81000 },
         { .reg = 0x00009888, .val = 0x09C002C0 },
         { .reg = 0x00009888, .val = 0x01C00000 },
         { .reg = 0x00009888, .val = 0x02C10400 },
         { .reg = 0x00009888, .val = 0x02C20400 },
         { .reg = 0x00009888, .val = 0x02C30400 },
         { .reg = 0x00009888, .val = 0x02C40400 },
         { .reg = 0x00009888, .val = 0x02C80400 },
         { .reg = 0x00009888, .val = 0x01E04EB4 },
         { .reg = 0x00009888, .val = 0x03E00166 },
         { .reg = 0x00009888, .val = 0x09E00016 },
         { .reg = 0x00009888, .val = 0x00E10155 },
         { .reg = 0x00009888, .val = 0x02E10100 },
         { .reg = 0x00009888, .val = 0x00E20155 },
         { .reg = 0x00009888, .val = 0x02E20100 },
         { .reg = 0x00009888, .val = 0x00E30155 },
         { .reg = 0x00009888, .val = 0x02E30100 },
         { .reg = 0x00009888, .val = 0x00E40155 },
         { .reg = 0x00009888, .val = 0x02E40100 },
         { .reg = 0x00009888, .val = 0x00E80155 },
         { .reg = 0x00009888, .val = 0x02E80100 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x188203C0 },
         { .reg = 0x00009888, .val = 0x04820000 },
         { .reg = 0x00009888, .val = 0x10820940 },
         { .reg = 0x00009888, .val = 0x008203FF },
         { .reg = 0x00009888, .val = 0x0282AB00 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x02215C00 },
         { .reg = 0x00009888, .val = 0x02245000 },
         { .reg = 0x00009888, .val = 0x002BC000 },
         { .reg = 0x00009888, .val = 0x0229B000 },
         { .reg = 0x00009888, .val = 0x022AA800 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F81F },
         { .reg = 0x00009888, .val = 0x0002F81F },
         { .reg = 0x00009888, .val = 0x00010155 },
         { .reg = 0x00009888, .val = 0x02015540 },
         { .reg = 0x00009888, .val = 0x00030155 },
         { .reg = 0x00009888, .val = 0x02035540 },
         { .reg = 0x00009888, .val = 0x0004F81F },
         { .reg = 0x00009888, .val = 0x4C010A00 },
         { .reg = 0x00009888, .val = 0x56010050 },
         { .reg = 0x00009888, .val = 0x58010A05 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x4E010200 },
         { .reg = 0x00009888, .val = 0x50010A07 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000F8 },
         { .reg = 0x0000D944, .val = 0x0000FFE0 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext184__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext184__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext184__avg_gpu_core_frequency__max,mtlgt3__ext184__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6936, 24, percentage_max_float,mtlgt3__ext184__xve_stall_pipestall_xecore4_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6937, 28, percentage_max_float,mtlgt3__ext184__xve_stall_pipestall_xecore5_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6938, 32, percentage_max_float,mtlgt3__ext184__xve_stall_pipestall_xecore6_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6939, 36, percentage_max_float,mtlgt3__ext184__xve_stall_pipestall_xecore7_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6940, 40, NULL,mtlgt3__ext184__xve_inst_issued_all_xecore7_xve0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6941, 48, NULL,mtlgt3__ext184__render_cache_alloc_l3_node1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext185_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext185";
   query->symbol_name = "Ext185";
   query->guid = "00882747-d1dd-4ba5-9b72-96df25dad7bd";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x26284720 },
         { .reg = 0x00009888, .val = 0x2C280239 },
         { .reg = 0x00009888, .val = 0x26484720 },
         { .reg = 0x00009888, .val = 0x2C480239 },
         { .reg = 0x00009888, .val = 0x26684720 },
         { .reg = 0x00009888, .val = 0x2C680239 },
         { .reg = 0x00009888, .val = 0x06080832 },
         { .reg = 0x00009888, .val = 0x08080BE7 },
         { .reg = 0x00009888, .val = 0x0A080FF7 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x06280832 },
         { .reg = 0x00009888, .val = 0x0C280BE7 },
         { .reg = 0x00009888, .val = 0x0E280FF7 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x06480832 },
         { .reg = 0x00009888, .val = 0x10480BE7 },
         { .reg = 0x00009888, .val = 0x12480FF7 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x06680832 },
         { .reg = 0x00009888, .val = 0x14680BE7 },
         { .reg = 0x00009888, .val = 0x16680FF7 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext185__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext185__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext185__avg_gpu_core_frequency__max,mtlgt3__ext185__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6165, 24, NULL,mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6166, 32, NULL,mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6167, 40, NULL,mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6168, 48, NULL,mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext186_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext186";
   query->symbol_name = "Ext186";
   query->guid = "89aea44f-ffa6-43cc-9a9c-103b4930e103";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x26884720 },
         { .reg = 0x00009888, .val = 0x2C880239 },
         { .reg = 0x00009888, .val = 0x26A84720 },
         { .reg = 0x00009888, .val = 0x2CA80239 },
         { .reg = 0x00009888, .val = 0x26C84720 },
         { .reg = 0x00009888, .val = 0x2CC80239 },
         { .reg = 0x00009888, .val = 0x26E84720 },
         { .reg = 0x00009888, .val = 0x2CE80239 },
         { .reg = 0x00009888, .val = 0x06880832 },
         { .reg = 0x00009888, .val = 0x08880BE7 },
         { .reg = 0x00009888, .val = 0x0A880FF7 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x06A80832 },
         { .reg = 0x00009888, .val = 0x0CA80BE7 },
         { .reg = 0x00009888, .val = 0x0EA80FF7 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x06C80832 },
         { .reg = 0x00009888, .val = 0x10C80BE7 },
         { .reg = 0x00009888, .val = 0x12C80FF7 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E80832 },
         { .reg = 0x00009888, .val = 0x14E80BE7 },
         { .reg = 0x00009888, .val = 0x16E80FF7 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext186__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext186__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext186__avg_gpu_core_frequency__max,mtlgt3__ext186__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6942, 24, NULL,mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6943, 32, NULL,mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6944, 40, NULL,mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6945, 48, NULL,mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext188_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext188";
   query->symbol_name = "Ext188";
   query->guid = "11e92a4a-d605-499c-9159-e79797c230de";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x26084720 },
         { .reg = 0x00009888, .val = 0x2C080239 },
         { .reg = 0x00009888, .val = 0x26284720 },
         { .reg = 0x00009888, .val = 0x2C280239 },
         { .reg = 0x00009888, .val = 0x26484720 },
         { .reg = 0x00009888, .val = 0x2C480239 },
         { .reg = 0x00009888, .val = 0x26684720 },
         { .reg = 0x00009888, .val = 0x2C680239 },
         { .reg = 0x00009888, .val = 0x06080832 },
         { .reg = 0x00009888, .val = 0x08080BE7 },
         { .reg = 0x00009888, .val = 0x0A080FF7 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x06280832 },
         { .reg = 0x00009888, .val = 0x0C280BE7 },
         { .reg = 0x00009888, .val = 0x0E280FF7 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x06480832 },
         { .reg = 0x00009888, .val = 0x14480BE7 },
         { .reg = 0x00009888, .val = 0x16480FF7 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x06680832 },
         { .reg = 0x00009888, .val = 0x10680BE7 },
         { .reg = 0x00009888, .val = 0x12680FF7 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x0201FF00 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAA00 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010605 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010603 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext188__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext188__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext188__avg_gpu_core_frequency__max,mtlgt3__ext188__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6169, 24, NULL,mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6170, 32, NULL,mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6171, 40, NULL,mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6172, 48, NULL,mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext189_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext189";
   query->symbol_name = "Ext189";
   query->guid = "27c2ef51-6689-4ffc-acaa-3f46a8e834cf";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x26884720 },
         { .reg = 0x00009888, .val = 0x2C880239 },
         { .reg = 0x00009888, .val = 0x26A84720 },
         { .reg = 0x00009888, .val = 0x2CA80239 },
         { .reg = 0x00009888, .val = 0x26C84720 },
         { .reg = 0x00009888, .val = 0x2CC80239 },
         { .reg = 0x00009888, .val = 0x26E84720 },
         { .reg = 0x00009888, .val = 0x2CE80239 },
         { .reg = 0x00009888, .val = 0x06880832 },
         { .reg = 0x00009888, .val = 0x08880BE7 },
         { .reg = 0x00009888, .val = 0x0A880FF7 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x06A80832 },
         { .reg = 0x00009888, .val = 0x0CA80BE7 },
         { .reg = 0x00009888, .val = 0x0EA80FF7 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x06C80832 },
         { .reg = 0x00009888, .val = 0x10C80BE7 },
         { .reg = 0x00009888, .val = 0x12C80FF7 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E80832 },
         { .reg = 0x00009888, .val = 0x14E80BE7 },
         { .reg = 0x00009888, .val = 0x16E80FF7 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000082 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000202 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00002002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00008002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00020002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext189__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext189__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext189__avg_gpu_core_frequency__max,mtlgt3__ext189__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6946, 24, NULL,mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6947, 32, NULL,mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6948, 40, NULL,mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6949, 48, NULL,mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext190_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext190";
   query->symbol_name = "Ext190";
   query->guid = "1625df84-2f24-4aed-9ced-e652184c9949";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C071400 },
         { .reg = 0x00009888, .val = 0x1C271400 },
         { .reg = 0x00009888, .val = 0x1C471400 },
         { .reg = 0x00009888, .val = 0x1C671400 },
         { .reg = 0x00009888, .val = 0x00070000 },
         { .reg = 0x00009888, .val = 0x04070554 },
         { .reg = 0x00009888, .val = 0x060705D6 },
         { .reg = 0x00009888, .val = 0x000800AA },
         { .reg = 0x00009888, .val = 0x00270000 },
         { .reg = 0x00009888, .val = 0x08270554 },
         { .reg = 0x00009888, .val = 0x0A2705D6 },
         { .reg = 0x00009888, .val = 0x04270000 },
         { .reg = 0x00009888, .val = 0x0028AA00 },
         { .reg = 0x00009888, .val = 0x00470000 },
         { .reg = 0x00009888, .val = 0x0C470554 },
         { .reg = 0x00009888, .val = 0x0E4705D6 },
         { .reg = 0x00009888, .val = 0x04470000 },
         { .reg = 0x00009888, .val = 0x024800AA },
         { .reg = 0x00009888, .val = 0x00670000 },
         { .reg = 0x00009888, .val = 0x10670554 },
         { .reg = 0x00009888, .val = 0x126705D6 },
         { .reg = 0x00009888, .val = 0x04670000 },
         { .reg = 0x00009888, .val = 0x0268AA00 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext190__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext190__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext190__avg_gpu_core_frequency__max,mtlgt3__ext190__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6173, 24, percentage_max_float,mtlgt3__ext190__pixel_post_process_input_available_cpipe0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_float(query, 6174, 28, percentage_max_float,mtlgt3__ext190__pixel_post_process_input_available_cpipe1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext191_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext191";
   query->symbol_name = "Ext191";
   query->guid = "d98e7947-ecee-46a9-b3ac-619d13d32b1a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C871400 },
         { .reg = 0x00009888, .val = 0x1CA71400 },
         { .reg = 0x00009888, .val = 0x1CC71400 },
         { .reg = 0x00009888, .val = 0x1CE71400 },
         { .reg = 0x00009888, .val = 0x00870000 },
         { .reg = 0x00009888, .val = 0x04870554 },
         { .reg = 0x00009888, .val = 0x068705D6 },
         { .reg = 0x00009888, .val = 0x008800AA },
         { .reg = 0x00009888, .val = 0x00A70000 },
         { .reg = 0x00009888, .val = 0x08A70554 },
         { .reg = 0x00009888, .val = 0x0AA705D6 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x00A8AA00 },
         { .reg = 0x00009888, .val = 0x00C70000 },
         { .reg = 0x00009888, .val = 0x0CC70554 },
         { .reg = 0x00009888, .val = 0x0EC705D6 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x02C800AA },
         { .reg = 0x00009888, .val = 0x00E70000 },
         { .reg = 0x00009888, .val = 0x10E70554 },
         { .reg = 0x00009888, .val = 0x12E705D6 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x02E8AA00 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000007F8 },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0007F800 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext191__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext191__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext191__avg_gpu_core_frequency__max,mtlgt3__ext191__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6950, 24, percentage_max_float,mtlgt3__ext191__pixel_post_process_input_available_cpipe2__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_float(query, 6951, 28, percentage_max_float,mtlgt3__ext191__pixel_post_process_input_available_cpipe3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext192_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext192";
   query->symbol_name = "Ext192";
   query->guid = "ed973589-e13c-4115-a2b1-08bc443a4e8d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18055400 },
         { .reg = 0x00009888, .val = 0x1C055C00 },
         { .reg = 0x00009888, .val = 0x1E05001C },
         { .reg = 0x00009888, .val = 0x18255400 },
         { .reg = 0x00009888, .val = 0x1C255C00 },
         { .reg = 0x00009888, .val = 0x1E25001C },
         { .reg = 0x00009888, .val = 0x18455400 },
         { .reg = 0x00009888, .val = 0x1C455C00 },
         { .reg = 0x00009888, .val = 0x1E45001C },
         { .reg = 0x00009888, .val = 0x18655400 },
         { .reg = 0x00009888, .val = 0x1C655C00 },
         { .reg = 0x00009888, .val = 0x1E65001C },
         { .reg = 0x00009888, .val = 0x0002000A },
         { .reg = 0x00009888, .val = 0x0202A000 },
         { .reg = 0x00009888, .val = 0x04050100 },
         { .reg = 0x00009888, .val = 0x06052440 },
         { .reg = 0x00009888, .val = 0x08050013 },
         { .reg = 0x00009888, .val = 0x14050C00 },
         { .reg = 0x00009888, .val = 0x16050038 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x02050000 },
         { .reg = 0x00009888, .val = 0x00080005 },
         { .reg = 0x00009888, .val = 0x02085000 },
         { .reg = 0x00009888, .val = 0x002200A0 },
         { .reg = 0x00009888, .val = 0x02220A00 },
         { .reg = 0x00009888, .val = 0x04250100 },
         { .reg = 0x00009888, .val = 0x06250040 },
         { .reg = 0x00009888, .val = 0x08250480 },
         { .reg = 0x00009888, .val = 0x0A250013 },
         { .reg = 0x00009888, .val = 0x12250C00 },
         { .reg = 0x00009888, .val = 0x14250038 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x02250000 },
         { .reg = 0x00009888, .val = 0x00280050 },
         { .reg = 0x00009888, .val = 0x02280500 },
         { .reg = 0x00009888, .val = 0x00420A00 },
         { .reg = 0x00009888, .val = 0x024200A0 },
         { .reg = 0x00009888, .val = 0x04450100 },
         { .reg = 0x00009888, .val = 0x06450040 },
         { .reg = 0x00009888, .val = 0x0A450480 },
         { .reg = 0x00009888, .val = 0x0C450013 },
         { .reg = 0x00009888, .val = 0x10450C00 },
         { .reg = 0x00009888, .val = 0x12450038 },
         { .reg = 0x00009888, .val = 0x00450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x00480500 },
         { .reg = 0x00009888, .val = 0x02480050 },
         { .reg = 0x00009888, .val = 0x0062A000 },
         { .reg = 0x00009888, .val = 0x0262000A },
         { .reg = 0x00009888, .val = 0x04650100 },
         { .reg = 0x00009888, .val = 0x06650040 },
         { .reg = 0x00009888, .val = 0x0C650480 },
         { .reg = 0x00009888, .val = 0x0E650C13 },
         { .reg = 0x00009888, .val = 0x10650038 },
         { .reg = 0x00009888, .val = 0x00650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x00685000 },
         { .reg = 0x00009888, .val = 0x02680005 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00010F55 },
         { .reg = 0x00009888, .val = 0x020155F0 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x02045500 },
         { .reg = 0x00009888, .val = 0x000BF00F },
         { .reg = 0x00009888, .val = 0x000900FA },
         { .reg = 0x00009888, .val = 0x0209AF00 },
         { .reg = 0x00009888, .val = 0x000A0AAA },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FAAA },
         { .reg = 0x00009888, .val = 0x0202AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010A03 },
         { .reg = 0x00009888, .val = 0x5E010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext192__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext192__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext192__avg_gpu_core_frequency__max,mtlgt3__ext192__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6175, 24, percentage_max_float,mtlgt3__ext192__rt_input_available_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6176, 28, percentage_max_float,mtlgt3__ext192__rt_input_available_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6177, 32, percentage_max_float,mtlgt3__ext192__rt_input_available_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6178, 36, percentage_max_float,mtlgt3__ext192__rt_input_available_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6179, 40, NULL,mtlgt3__ext192__rt_traversal_step_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6180, 48, NULL,mtlgt3__ext192__rt_traversal_step_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6181, 56, NULL,mtlgt3__ext192__rt_traversal_step_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6182, 64, NULL,mtlgt3__ext192__rt_traversal_step_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext193_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext193";
   query->symbol_name = "Ext193";
   query->guid = "9bb6c40a-ec2c-4292-8ac8-d8b413abd301";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18855400 },
         { .reg = 0x00009888, .val = 0x1C857000 },
         { .reg = 0x00009888, .val = 0x1E850017 },
         { .reg = 0x00009888, .val = 0x18A55400 },
         { .reg = 0x00009888, .val = 0x1CA57000 },
         { .reg = 0x00009888, .val = 0x1EA50017 },
         { .reg = 0x00009888, .val = 0x18C55400 },
         { .reg = 0x00009888, .val = 0x1CC57000 },
         { .reg = 0x00009888, .val = 0x1EC50017 },
         { .reg = 0x00009888, .val = 0x18E55400 },
         { .reg = 0x00009888, .val = 0x1CE57000 },
         { .reg = 0x00009888, .val = 0x1EE50017 },
         { .reg = 0x00009888, .val = 0x0082000A },
         { .reg = 0x00009888, .val = 0x0282A000 },
         { .reg = 0x00009888, .val = 0x04850100 },
         { .reg = 0x00009888, .val = 0x06852440 },
         { .reg = 0x00009888, .val = 0x08850013 },
         { .reg = 0x00009888, .val = 0x14850C00 },
         { .reg = 0x00009888, .val = 0x16850038 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x02850000 },
         { .reg = 0x00009888, .val = 0x00880005 },
         { .reg = 0x00009888, .val = 0x02885000 },
         { .reg = 0x00009888, .val = 0x00A200A0 },
         { .reg = 0x00009888, .val = 0x02A20A00 },
         { .reg = 0x00009888, .val = 0x04A50100 },
         { .reg = 0x00009888, .val = 0x06A50040 },
         { .reg = 0x00009888, .val = 0x08A50480 },
         { .reg = 0x00009888, .val = 0x0AA50013 },
         { .reg = 0x00009888, .val = 0x12A50C00 },
         { .reg = 0x00009888, .val = 0x14A50038 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x02A50000 },
         { .reg = 0x00009888, .val = 0x00A80050 },
         { .reg = 0x00009888, .val = 0x02A80500 },
         { .reg = 0x00009888, .val = 0x00C20A00 },
         { .reg = 0x00009888, .val = 0x02C200A0 },
         { .reg = 0x00009888, .val = 0x04C50100 },
         { .reg = 0x00009888, .val = 0x06C50040 },
         { .reg = 0x00009888, .val = 0x0AC50480 },
         { .reg = 0x00009888, .val = 0x0CC50013 },
         { .reg = 0x00009888, .val = 0x10C50C00 },
         { .reg = 0x00009888, .val = 0x12C50038 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x00C80500 },
         { .reg = 0x00009888, .val = 0x02C80050 },
         { .reg = 0x00009888, .val = 0x00E2A000 },
         { .reg = 0x00009888, .val = 0x02E2000A },
         { .reg = 0x00009888, .val = 0x04E50100 },
         { .reg = 0x00009888, .val = 0x06E50040 },
         { .reg = 0x00009888, .val = 0x0CE50480 },
         { .reg = 0x00009888, .val = 0x0EE50C13 },
         { .reg = 0x00009888, .val = 0x10E50038 },
         { .reg = 0x00009888, .val = 0x00E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x00E85000 },
         { .reg = 0x00009888, .val = 0x02E80005 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00210F55 },
         { .reg = 0x00009888, .val = 0x022155F0 },
         { .reg = 0x00009888, .val = 0x00240055 },
         { .reg = 0x00009888, .val = 0x02245500 },
         { .reg = 0x00009888, .val = 0x002BF00F },
         { .reg = 0x00009888, .val = 0x002900FA },
         { .reg = 0x00009888, .val = 0x0229AF00 },
         { .reg = 0x00009888, .val = 0x002A0AAA },
         { .reg = 0x00009888, .val = 0x022AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FAAA },
         { .reg = 0x00009888, .val = 0x0282AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010030 },
         { .reg = 0x00009888, .val = 0x5C010A03 },
         { .reg = 0x00009888, .val = 0x5E010050 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001D },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000065 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000185 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000605 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext193__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext193__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext193__avg_gpu_core_frequency__max,mtlgt3__ext193__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6952, 24, percentage_max_float,mtlgt3__ext193__rt_input_available_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6953, 28, percentage_max_float,mtlgt3__ext193__rt_input_available_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6954, 32, percentage_max_float,mtlgt3__ext193__rt_input_available_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6955, 36, percentage_max_float,mtlgt3__ext193__rt_input_available_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6956, 40, NULL,mtlgt3__ext193__rt_traversal_step_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6957, 48, NULL,mtlgt3__ext193__rt_traversal_step_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6958, 56, NULL,mtlgt3__ext193__rt_traversal_step_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6959, 64, NULL,mtlgt3__ext193__rt_traversal_step_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext195_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext195";
   query->symbol_name = "Ext195";
   query->guid = "9a911d6f-39b5-425d-aea3-15e49e6395fa";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B002960 },
         { .reg = 0x00009888, .val = 0x2C070000 },
         { .reg = 0x00009888, .val = 0x0B202960 },
         { .reg = 0x00009888, .val = 0x2C270000 },
         { .reg = 0x00009888, .val = 0x0B402960 },
         { .reg = 0x00009888, .val = 0x2C470000 },
         { .reg = 0x00009888, .val = 0x0B602960 },
         { .reg = 0x00009888, .val = 0x2C670000 },
         { .reg = 0x00009888, .val = 0x010039E0 },
         { .reg = 0x00009888, .val = 0x00010015 },
         { .reg = 0x00009888, .val = 0x00020015 },
         { .reg = 0x00009888, .val = 0x00030015 },
         { .reg = 0x00009888, .val = 0x00040015 },
         { .reg = 0x00009888, .val = 0x0207000A },
         { .reg = 0x00009888, .val = 0x12070980 },
         { .reg = 0x00009888, .val = 0x04070000 },
         { .reg = 0x00009888, .val = 0x00080015 },
         { .reg = 0x00009888, .val = 0x02088000 },
         { .reg = 0x00009888, .val = 0x032039E0 },
         { .reg = 0x00009888, .val = 0x01200000 },
         { .reg = 0x00009888, .val = 0x00210540 },
         { .reg = 0x00009888, .val = 0x00220540 },
         { .reg = 0x00009888, .val = 0x00230540 },
         { .reg = 0x00009888, .val = 0x00240540 },
         { .reg = 0x00009888, .val = 0x0227000A },
         { .reg = 0x00009888, .val = 0x12270026 },
         { .reg = 0x00009888, .val = 0x04270000 },
         { .reg = 0x00009888, .val = 0x00280540 },
         { .reg = 0x00009888, .val = 0x02282000 },
         { .reg = 0x00009888, .val = 0x054039E0 },
         { .reg = 0x00009888, .val = 0x01400000 },
         { .reg = 0x00009888, .val = 0x00415000 },
         { .reg = 0x00009888, .val = 0x02410001 },
         { .reg = 0x00009888, .val = 0x00425000 },
         { .reg = 0x00009888, .val = 0x02420001 },
         { .reg = 0x00009888, .val = 0x00435000 },
         { .reg = 0x00009888, .val = 0x02430001 },
         { .reg = 0x00009888, .val = 0x00445000 },
         { .reg = 0x00009888, .val = 0x02440001 },
         { .reg = 0x00009888, .val = 0x0247000A },
         { .reg = 0x00009888, .val = 0x10470980 },
         { .reg = 0x00009888, .val = 0x04470000 },
         { .reg = 0x00009888, .val = 0x00485000 },
         { .reg = 0x00009888, .val = 0x02480801 },
         { .reg = 0x00009888, .val = 0x076039E0 },
         { .reg = 0x00009888, .val = 0x01600000 },
         { .reg = 0x00009888, .val = 0x02610054 },
         { .reg = 0x00009888, .val = 0x02620054 },
         { .reg = 0x00009888, .val = 0x02630054 },
         { .reg = 0x00009888, .val = 0x02640054 },
         { .reg = 0x00009888, .val = 0x0267000A },
         { .reg = 0x00009888, .val = 0x10670026 },
         { .reg = 0x00009888, .val = 0x04670000 },
         { .reg = 0x00009888, .val = 0x02680254 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001F555 },
         { .reg = 0x00009888, .val = 0x02015C03 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x02045000 },
         { .reg = 0x00009888, .val = 0x000BC03F },
         { .reg = 0x00009888, .val = 0x00090FEA },
         { .reg = 0x00009888, .val = 0x0209B000 },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AA802 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202ABFE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A03 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010425 },
         { .reg = 0x00009888, .val = 0x52010001 },
         { .reg = 0x00009888, .val = 0x54011008 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext195__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext195__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext195__avg_gpu_core_frequency__max,mtlgt3__ext195__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6183, 24, percentage_max_float,mtlgt3__ext195__xve_multiple_pipe_active_xecore0_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6184, 28, percentage_max_float,mtlgt3__ext195__xve_multiple_pipe_active_xecore1_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6185, 32, percentage_max_float,mtlgt3__ext195__xve_multiple_pipe_active_xecore2_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6186, 36, percentage_max_float,mtlgt3__ext195__xve_multiple_pipe_active_xecore3_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6187, 40, NULL,mtlgt3__ext195__gpgpu_dispatch_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6188, 48, NULL,mtlgt3__ext195__gpgpu_dispatch_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6189, 56, NULL,mtlgt3__ext195__gpgpu_dispatch_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6190, 64, NULL,mtlgt3__ext195__gpgpu_dispatch_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext196_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext196";
   query->symbol_name = "Ext196";
   query->guid = "814b3516-d465-4faa-b89c-67c30c96a256";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x0B802960 },
         { .reg = 0x00009888, .val = 0x2C870000 },
         { .reg = 0x00009888, .val = 0x0BA02960 },
         { .reg = 0x00009888, .val = 0x2CA70000 },
         { .reg = 0x00009888, .val = 0x0BC02960 },
         { .reg = 0x00009888, .val = 0x2CC70000 },
         { .reg = 0x00009888, .val = 0x0BE02960 },
         { .reg = 0x00009888, .val = 0x2CE70000 },
         { .reg = 0x00009888, .val = 0x018039E0 },
         { .reg = 0x00009888, .val = 0x00810015 },
         { .reg = 0x00009888, .val = 0x00820015 },
         { .reg = 0x00009888, .val = 0x00830015 },
         { .reg = 0x00009888, .val = 0x00840015 },
         { .reg = 0x00009888, .val = 0x0287000A },
         { .reg = 0x00009888, .val = 0x12870980 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x00880015 },
         { .reg = 0x00009888, .val = 0x02888000 },
         { .reg = 0x00009888, .val = 0x03A039E0 },
         { .reg = 0x00009888, .val = 0x01A00000 },
         { .reg = 0x00009888, .val = 0x00A10540 },
         { .reg = 0x00009888, .val = 0x00A20540 },
         { .reg = 0x00009888, .val = 0x00A30540 },
         { .reg = 0x00009888, .val = 0x00A40540 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x12A70026 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x00A80540 },
         { .reg = 0x00009888, .val = 0x02A82000 },
         { .reg = 0x00009888, .val = 0x05C039E0 },
         { .reg = 0x00009888, .val = 0x01C00000 },
         { .reg = 0x00009888, .val = 0x00C15000 },
         { .reg = 0x00009888, .val = 0x02C10001 },
         { .reg = 0x00009888, .val = 0x00C25000 },
         { .reg = 0x00009888, .val = 0x02C20001 },
         { .reg = 0x00009888, .val = 0x00C35000 },
         { .reg = 0x00009888, .val = 0x02C30001 },
         { .reg = 0x00009888, .val = 0x00C45000 },
         { .reg = 0x00009888, .val = 0x02C40001 },
         { .reg = 0x00009888, .val = 0x02C7000A },
         { .reg = 0x00009888, .val = 0x10C70980 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x00C85000 },
         { .reg = 0x00009888, .val = 0x02C80801 },
         { .reg = 0x00009888, .val = 0x07E039E0 },
         { .reg = 0x00009888, .val = 0x01E00000 },
         { .reg = 0x00009888, .val = 0x02E10054 },
         { .reg = 0x00009888, .val = 0x02E20054 },
         { .reg = 0x00009888, .val = 0x02E30054 },
         { .reg = 0x00009888, .val = 0x02E40054 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x10E70026 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x02E80254 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021F555 },
         { .reg = 0x00009888, .val = 0x02215C03 },
         { .reg = 0x00009888, .val = 0x00240555 },
         { .reg = 0x00009888, .val = 0x02245000 },
         { .reg = 0x00009888, .val = 0x002BC03F },
         { .reg = 0x00009888, .val = 0x00290FEA },
         { .reg = 0x00009888, .val = 0x0229B000 },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AA802 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282ABFE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A03 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010425 },
         { .reg = 0x00009888, .val = 0x52010001 },
         { .reg = 0x00009888, .val = 0x54011008 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001B },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000000C3 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000603 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00003003 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
         { .reg = 0x0000D960, .val = 0x00000022 },
         { .reg = 0x0000D964, .val = 0x0000FFF8 },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FFC7 },
         { .reg = 0x0000D970, .val = 0x00000802 },
         { .reg = 0x0000D974, .val = 0x0000FE3F },
         { .reg = 0x0000D978, .val = 0x00004002 },
         { .reg = 0x0000D97C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext196__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext196__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext196__avg_gpu_core_frequency__max,mtlgt3__ext196__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 6960, 24, percentage_max_float,mtlgt3__ext196__xve_multiple_pipe_active_xecore4_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 6961, 28, percentage_max_float,mtlgt3__ext196__xve_multiple_pipe_active_xecore5_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 6962, 32, percentage_max_float,mtlgt3__ext196__xve_multiple_pipe_active_xecore6_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 6963, 36, percentage_max_float,mtlgt3__ext196__xve_multiple_pipe_active_xecore7_xve0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6964, 40, NULL,mtlgt3__ext196__gpgpu_dispatch_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6965, 48, NULL,mtlgt3__ext196__gpgpu_dispatch_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6966, 56, NULL,mtlgt3__ext196__gpgpu_dispatch_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6967, 64, NULL,mtlgt3__ext196__gpgpu_dispatch_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext198_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext198";
   query->symbol_name = "Ext198";
   query->guid = "3663ed58-377d-40c3-9af0-913cbc5d954b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x180802D5 },
         { .reg = 0x00009888, .val = 0x182802D5 },
         { .reg = 0x00009888, .val = 0x184802D5 },
         { .reg = 0x00009888, .val = 0x186802D5 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x080801C6 },
         { .reg = 0x00009888, .val = 0x0A080008 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x04280010 },
         { .reg = 0x00009888, .val = 0x0A280180 },
         { .reg = 0x00009888, .val = 0x0C280207 },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x04480010 },
         { .reg = 0x00009888, .val = 0x0E4801C6 },
         { .reg = 0x00009888, .val = 0x10480008 },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x04680010 },
         { .reg = 0x00009888, .val = 0x10680180 },
         { .reg = 0x00009888, .val = 0x12680207 },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001F555 },
         { .reg = 0x00009888, .val = 0x02010003 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x000B003F },
         { .reg = 0x00009888, .val = 0x00090FEA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A0002 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200FE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x020300AA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A03 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext198__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext198__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext198__avg_gpu_core_frequency__max,mtlgt3__ext198__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6191, 24, NULL,mtlgt3__ext198__slm_access_count_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6192, 32, NULL,mtlgt3__ext198__slm_access_count_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6193, 40, NULL,mtlgt3__ext198__slm_access_count_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6194, 48, NULL,mtlgt3__ext198__slm_access_count_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext199_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext199";
   query->symbol_name = "Ext199";
   query->guid = "6ce22a01-9025-4afb-b3e9-652ce0c693b5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x1E080016 },
         { .reg = 0x00009888, .val = 0x1C285400 },
         { .reg = 0x00009888, .val = 0x1E280016 },
         { .reg = 0x00009888, .val = 0x1C485400 },
         { .reg = 0x00009888, .val = 0x1E480016 },
         { .reg = 0x00009888, .val = 0x1C685400 },
         { .reg = 0x00009888, .val = 0x1E680016 },
         { .reg = 0x00009888, .val = 0x04080098 },
         { .reg = 0x00009888, .val = 0x080801C6 },
         { .reg = 0x00009888, .val = 0x0A080008 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x04280098 },
         { .reg = 0x00009888, .val = 0x0A280180 },
         { .reg = 0x00009888, .val = 0x0C280207 },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x04480098 },
         { .reg = 0x00009888, .val = 0x0E4801C6 },
         { .reg = 0x00009888, .val = 0x10480008 },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x04680098 },
         { .reg = 0x00009888, .val = 0x10680180 },
         { .reg = 0x00009888, .val = 0x12680207 },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001F555 },
         { .reg = 0x00009888, .val = 0x02010003 },
         { .reg = 0x00009888, .val = 0x00040555 },
         { .reg = 0x00009888, .val = 0x000B003F },
         { .reg = 0x00009888, .val = 0x00090FEA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A0002 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x020200FE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x020300AA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A03 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext199__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext199__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext199__avg_gpu_core_frequency__max,mtlgt3__ext199__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6195, 24, NULL,mtlgt3__ext199__slm_access_count_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6196, 32, NULL,mtlgt3__ext199__slm_access_count_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6197, 40, NULL,mtlgt3__ext199__slm_access_count_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6198, 48, NULL,mtlgt3__ext199__slm_access_count_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext200_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext200";
   query->symbol_name = "Ext200";
   query->guid = "7f59bef3-f0f1-4856-b4f3-e64fa9913956";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x188802D5 },
         { .reg = 0x00009888, .val = 0x18A802D5 },
         { .reg = 0x00009888, .val = 0x18C802D5 },
         { .reg = 0x00009888, .val = 0x18E802D5 },
         { .reg = 0x00009888, .val = 0x04880010 },
         { .reg = 0x00009888, .val = 0x088801C6 },
         { .reg = 0x00009888, .val = 0x0A880008 },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x04A80010 },
         { .reg = 0x00009888, .val = 0x0AA80180 },
         { .reg = 0x00009888, .val = 0x0CA80207 },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x04C80010 },
         { .reg = 0x00009888, .val = 0x0EC801C6 },
         { .reg = 0x00009888, .val = 0x10C80008 },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x04E80010 },
         { .reg = 0x00009888, .val = 0x10E80180 },
         { .reg = 0x00009888, .val = 0x12E80207 },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021F555 },
         { .reg = 0x00009888, .val = 0x02210003 },
         { .reg = 0x00009888, .val = 0x00240555 },
         { .reg = 0x00009888, .val = 0x002B003F },
         { .reg = 0x00009888, .val = 0x00290FEA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A0002 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x028200FE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050FFF },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A03 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext200__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext200__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext200__avg_gpu_core_frequency__max,mtlgt3__ext200__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6968, 24, NULL,mtlgt3__ext200__slm_access_count_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6969, 32, NULL,mtlgt3__ext200__slm_access_count_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6970, 40, NULL,mtlgt3__ext200__slm_access_count_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6971, 48, NULL,mtlgt3__ext200__slm_access_count_bank0_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext201_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext201";
   query->symbol_name = "Ext201";
   query->guid = "8982721e-16cb-42ec-92dd-eb049ae7a503";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C885400 },
         { .reg = 0x00009888, .val = 0x1E880016 },
         { .reg = 0x00009888, .val = 0x1CA85400 },
         { .reg = 0x00009888, .val = 0x1EA80016 },
         { .reg = 0x00009888, .val = 0x1CC85400 },
         { .reg = 0x00009888, .val = 0x1EC80016 },
         { .reg = 0x00009888, .val = 0x1CE85400 },
         { .reg = 0x00009888, .val = 0x1EE80016 },
         { .reg = 0x00009888, .val = 0x04880098 },
         { .reg = 0x00009888, .val = 0x088801C6 },
         { .reg = 0x00009888, .val = 0x0A880008 },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x04A80098 },
         { .reg = 0x00009888, .val = 0x0AA80180 },
         { .reg = 0x00009888, .val = 0x0CA80207 },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x04C80098 },
         { .reg = 0x00009888, .val = 0x0EC801C6 },
         { .reg = 0x00009888, .val = 0x10C80008 },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x04E80098 },
         { .reg = 0x00009888, .val = 0x10E80180 },
         { .reg = 0x00009888, .val = 0x12E80207 },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021F555 },
         { .reg = 0x00009888, .val = 0x02210003 },
         { .reg = 0x00009888, .val = 0x00240555 },
         { .reg = 0x00009888, .val = 0x002B003F },
         { .reg = 0x00009888, .val = 0x00290FEA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A0002 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x028200FE },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x00050FFF },
         { .reg = 0x00009888, .val = 0x00020FFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010055 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030055 },
         { .reg = 0x00009888, .val = 0x00040FFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010030 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A03 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010005 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x00000038 },
         { .reg = 0x0000D944, .val = 0x0000FFF8 },
         { .reg = 0x0000D948, .val = 0x000001C0 },
         { .reg = 0x0000D94C, .val = 0x0000FFC7 },
         { .reg = 0x0000D950, .val = 0x00000E00 },
         { .reg = 0x0000D954, .val = 0x0000FE3F },
         { .reg = 0x0000D958, .val = 0x00007000 },
         { .reg = 0x0000D95C, .val = 0x0000F1FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext201__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext201__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext201__avg_gpu_core_frequency__max,mtlgt3__ext201__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6972, 24, NULL,mtlgt3__ext201__slm_access_count_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6973, 32, NULL,mtlgt3__ext201__slm_access_count_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6974, 40, NULL,mtlgt3__ext201__slm_access_count_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6975, 48, NULL,mtlgt3__ext201__slm_access_count_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext202_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext202";
   query->symbol_name = "Ext202";
   query->guid = "d86c1224-3af7-4df1-a44d-e4522f22b2ae";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x150100A0 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x02070002 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x02010002 },
         { .reg = 0x00009888, .val = 0x03010004 },
         { .reg = 0x00009888, .val = 0x05010207 },
         { .reg = 0x00009888, .val = 0x07010289 },
         { .reg = 0x00009888, .val = 0x0901030B },
         { .reg = 0x00009888, .val = 0x0B01038D },
         { .reg = 0x00009888, .val = 0x0D01000F },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext202__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext202__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext202__avg_gpu_core_frequency__max,mtlgt3__ext202__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6199, 24, NULL,mtlgt3__ext202__gpu_memory_l3_write_sqidi0__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext203_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext203";
   query->symbol_name = "Ext203";
   query->guid = "03090380-689d-481a-ace2-9725ea0c10d2";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x152100A0 },
         { .reg = 0x00009888, .val = 0x0007FFFF },
         { .reg = 0x00009888, .val = 0x02070003 },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x02010002 },
         { .reg = 0x00009888, .val = 0x03210004 },
         { .reg = 0x00009888, .val = 0x05210207 },
         { .reg = 0x00009888, .val = 0x07210289 },
         { .reg = 0x00009888, .val = 0x0921030B },
         { .reg = 0x00009888, .val = 0x0B21038D },
         { .reg = 0x00009888, .val = 0x0D21000F },
         { .reg = 0x00009888, .val = 0x01210000 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x10800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000018A },
         { .reg = 0x0000D944, .val = 0x0000FE00 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext203__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext203__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext203__avg_gpu_core_frequency__max,mtlgt3__ext203__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6200, 24, NULL,mtlgt3__ext203__gpu_memory_l3_write_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext204_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext204";
   query->symbol_name = "Ext204";
   query->guid = "78a1b79a-a5fd-4fa0-b33d-2ec51404e3b9";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C055C00 },
         { .reg = 0x00009888, .val = 0x1E05001C },
         { .reg = 0x00009888, .val = 0x1C255C00 },
         { .reg = 0x00009888, .val = 0x1E25001C },
         { .reg = 0x00009888, .val = 0x1C455C00 },
         { .reg = 0x00009888, .val = 0x1E45001C },
         { .reg = 0x00009888, .val = 0x1C655C00 },
         { .reg = 0x00009888, .val = 0x1E65001C },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x06056040 },
         { .reg = 0x00009888, .val = 0x08050E35 },
         { .reg = 0x00009888, .val = 0x0A05003D },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080055 },
         { .reg = 0x00009888, .val = 0x0022AA00 },
         { .reg = 0x00009888, .val = 0x06250040 },
         { .reg = 0x00009888, .val = 0x0A250C00 },
         { .reg = 0x00009888, .val = 0x0C250E35 },
         { .reg = 0x00009888, .val = 0x0E25003D },
         { .reg = 0x00009888, .val = 0x04250000 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x00285500 },
         { .reg = 0x00009888, .val = 0x024200AA },
         { .reg = 0x00009888, .val = 0x06450040 },
         { .reg = 0x00009888, .val = 0x0E450C00 },
         { .reg = 0x00009888, .val = 0x10450E35 },
         { .reg = 0x00009888, .val = 0x1245003D },
         { .reg = 0x00009888, .val = 0x04450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02480055 },
         { .reg = 0x00009888, .val = 0x0262AA00 },
         { .reg = 0x00009888, .val = 0x06650040 },
         { .reg = 0x00009888, .val = 0x12650C00 },
         { .reg = 0x00009888, .val = 0x14650E35 },
         { .reg = 0x00009888, .val = 0x1665003D },
         { .reg = 0x00009888, .val = 0x04650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x02685500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext204__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext204__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext204__avg_gpu_core_frequency__max,mtlgt3__ext204__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6201, 24, NULL,mtlgt3__ext204__rt_internal_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6202, 32, NULL,mtlgt3__ext204__rt_internal_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6203, 40, NULL,mtlgt3__ext204__rt_internal_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6204, 48, NULL,mtlgt3__ext204__rt_internal_node_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext205_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext205";
   query->symbol_name = "Ext205";
   query->guid = "b3c2bff1-e203-4c90-8719-66546c370005";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C055C00 },
         { .reg = 0x00009888, .val = 0x1E05001C },
         { .reg = 0x00009888, .val = 0x1C255C00 },
         { .reg = 0x00009888, .val = 0x1E25001C },
         { .reg = 0x00009888, .val = 0x1C455C00 },
         { .reg = 0x00009888, .val = 0x1E45001C },
         { .reg = 0x00009888, .val = 0x1C655C00 },
         { .reg = 0x00009888, .val = 0x1E65001C },
         { .reg = 0x00009888, .val = 0x000200AA },
         { .reg = 0x00009888, .val = 0x06056040 },
         { .reg = 0x00009888, .val = 0x08050E37 },
         { .reg = 0x00009888, .val = 0x0A05003F },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080055 },
         { .reg = 0x00009888, .val = 0x0022AA00 },
         { .reg = 0x00009888, .val = 0x06250040 },
         { .reg = 0x00009888, .val = 0x0A250C00 },
         { .reg = 0x00009888, .val = 0x0C250E37 },
         { .reg = 0x00009888, .val = 0x0E25003F },
         { .reg = 0x00009888, .val = 0x04250000 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x00285500 },
         { .reg = 0x00009888, .val = 0x024200AA },
         { .reg = 0x00009888, .val = 0x06450040 },
         { .reg = 0x00009888, .val = 0x0E450C00 },
         { .reg = 0x00009888, .val = 0x10450E37 },
         { .reg = 0x00009888, .val = 0x1245003F },
         { .reg = 0x00009888, .val = 0x04450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02480055 },
         { .reg = 0x00009888, .val = 0x0262AA00 },
         { .reg = 0x00009888, .val = 0x06650040 },
         { .reg = 0x00009888, .val = 0x12650C00 },
         { .reg = 0x00009888, .val = 0x14650E37 },
         { .reg = 0x00009888, .val = 0x1665003F },
         { .reg = 0x00009888, .val = 0x04650000 },
         { .reg = 0x00009888, .val = 0x02650000 },
         { .reg = 0x00009888, .val = 0x02685500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x020100FF },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x000B00FF },
         { .reg = 0x00009888, .val = 0x0009FFAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext205__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext205__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext205__avg_gpu_core_frequency__max,mtlgt3__ext205__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6205, 24, NULL,mtlgt3__ext205__rt_instance_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6206, 32, NULL,mtlgt3__ext205__rt_instance_node_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6207, 40, NULL,mtlgt3__ext205__rt_instance_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6208, 48, NULL,mtlgt3__ext205__rt_instance_node_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext206_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext206";
   query->symbol_name = "Ext206";
   query->guid = "a209e458-76a6-46fc-bb62-29850f38eb0d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C855C00 },
         { .reg = 0x00009888, .val = 0x1E85001C },
         { .reg = 0x00009888, .val = 0x1CA55C00 },
         { .reg = 0x00009888, .val = 0x1EA5001C },
         { .reg = 0x00009888, .val = 0x1CC55C00 },
         { .reg = 0x00009888, .val = 0x1EC5001C },
         { .reg = 0x00009888, .val = 0x1CE55C00 },
         { .reg = 0x00009888, .val = 0x1EE5001C },
         { .reg = 0x00009888, .val = 0x008200AA },
         { .reg = 0x00009888, .val = 0x06856040 },
         { .reg = 0x00009888, .val = 0x08850E35 },
         { .reg = 0x00009888, .val = 0x0A85003D },
         { .reg = 0x00009888, .val = 0x04850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x00A2AA00 },
         { .reg = 0x00009888, .val = 0x06A50040 },
         { .reg = 0x00009888, .val = 0x0AA50C00 },
         { .reg = 0x00009888, .val = 0x0CA50E35 },
         { .reg = 0x00009888, .val = 0x0EA5003D },
         { .reg = 0x00009888, .val = 0x04A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x02C200AA },
         { .reg = 0x00009888, .val = 0x06C50040 },
         { .reg = 0x00009888, .val = 0x0EC50C00 },
         { .reg = 0x00009888, .val = 0x10C50E35 },
         { .reg = 0x00009888, .val = 0x12C5003D },
         { .reg = 0x00009888, .val = 0x04C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x02E2AA00 },
         { .reg = 0x00009888, .val = 0x06E50040 },
         { .reg = 0x00009888, .val = 0x12E50C00 },
         { .reg = 0x00009888, .val = 0x14E50E35 },
         { .reg = 0x00009888, .val = 0x16E5003D },
         { .reg = 0x00009888, .val = 0x04E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext206__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext206__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext206__avg_gpu_core_frequency__max,mtlgt3__ext206__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6976, 24, NULL,mtlgt3__ext206__rt_internal_node_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6977, 32, NULL,mtlgt3__ext206__rt_internal_node_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6978, 40, NULL,mtlgt3__ext206__rt_internal_node_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6979, 48, NULL,mtlgt3__ext206__rt_internal_node_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext207_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext207";
   query->symbol_name = "Ext207";
   query->guid = "06aea283-f183-4e96-85a5-3bb7193f06c7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C855C00 },
         { .reg = 0x00009888, .val = 0x1E85001C },
         { .reg = 0x00009888, .val = 0x1CA55C00 },
         { .reg = 0x00009888, .val = 0x1EA5001C },
         { .reg = 0x00009888, .val = 0x1CC55C00 },
         { .reg = 0x00009888, .val = 0x1EC5001C },
         { .reg = 0x00009888, .val = 0x1CE55C00 },
         { .reg = 0x00009888, .val = 0x1EE5001C },
         { .reg = 0x00009888, .val = 0x008200AA },
         { .reg = 0x00009888, .val = 0x06856040 },
         { .reg = 0x00009888, .val = 0x08850E37 },
         { .reg = 0x00009888, .val = 0x0A85003F },
         { .reg = 0x00009888, .val = 0x04850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00880055 },
         { .reg = 0x00009888, .val = 0x00A2AA00 },
         { .reg = 0x00009888, .val = 0x06A50040 },
         { .reg = 0x00009888, .val = 0x0AA50C00 },
         { .reg = 0x00009888, .val = 0x0CA50E37 },
         { .reg = 0x00009888, .val = 0x0EA5003F },
         { .reg = 0x00009888, .val = 0x04A50000 },
         { .reg = 0x00009888, .val = 0x00A50000 },
         { .reg = 0x00009888, .val = 0x00A85500 },
         { .reg = 0x00009888, .val = 0x02C200AA },
         { .reg = 0x00009888, .val = 0x06C50040 },
         { .reg = 0x00009888, .val = 0x0EC50C00 },
         { .reg = 0x00009888, .val = 0x10C50E37 },
         { .reg = 0x00009888, .val = 0x12C5003F },
         { .reg = 0x00009888, .val = 0x04C50000 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x02C80055 },
         { .reg = 0x00009888, .val = 0x02E2AA00 },
         { .reg = 0x00009888, .val = 0x06E50040 },
         { .reg = 0x00009888, .val = 0x12E50C00 },
         { .reg = 0x00009888, .val = 0x14E50E37 },
         { .reg = 0x00009888, .val = 0x16E5003F },
         { .reg = 0x00009888, .val = 0x04E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E85500 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x022100FF },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x002B00FF },
         { .reg = 0x00009888, .val = 0x0029FFAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A00AA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010603 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010A03 },
         { .reg = 0x00009888, .val = 0x52010050 },
         { .reg = 0x00009888, .val = 0x54010A05 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000062 },
         { .reg = 0x0000D94C, .val = 0x0000FFF3 },
         { .reg = 0x0000D950, .val = 0x00000182 },
         { .reg = 0x0000D954, .val = 0x0000FFCF },
         { .reg = 0x0000D958, .val = 0x00000602 },
         { .reg = 0x0000D95C, .val = 0x0000FF3F },
         { .reg = 0x0000D960, .val = 0x00001802 },
         { .reg = 0x0000D964, .val = 0x0000FCFF },
         { .reg = 0x0000D968, .val = 0x00006002 },
         { .reg = 0x0000D96C, .val = 0x0000F3FF },
         { .reg = 0x0000D970, .val = 0x00018002 },
         { .reg = 0x0000D974, .val = 0x0000CFFF },
         { .reg = 0x0000D978, .val = 0x00060002 },
         { .reg = 0x0000D97C, .val = 0x00003FFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext207__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext207__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext207__avg_gpu_core_frequency__max,mtlgt3__ext207__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6980, 24, NULL,mtlgt3__ext207__rt_instance_node_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6981, 32, NULL,mtlgt3__ext207__rt_instance_node_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6982, 40, NULL,mtlgt3__ext207__rt_instance_node_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6983, 48, NULL,mtlgt3__ext207__rt_instance_node_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext212_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext212";
   query->symbol_name = "Ext212";
   query->guid = "0c6d24a9-2489-4fcd-a9f6-d44380417dee";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C055C00 },
         { .reg = 0x00009888, .val = 0x1E05001C },
         { .reg = 0x00009888, .val = 0x1C255C00 },
         { .reg = 0x00009888, .val = 0x1E25001C },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x06056040 },
         { .reg = 0x00009888, .val = 0x08050DB5 },
         { .reg = 0x00009888, .val = 0x0A050E37 },
         { .reg = 0x00009888, .val = 0x0C050FBD },
         { .reg = 0x00009888, .val = 0x0E05003F },
         { .reg = 0x00009888, .val = 0x04050000 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00085555 },
         { .reg = 0x00009888, .val = 0x0222AAAA },
         { .reg = 0x00009888, .val = 0x06250040 },
         { .reg = 0x00009888, .val = 0x0E250C00 },
         { .reg = 0x00009888, .val = 0x10250DB5 },
         { .reg = 0x00009888, .val = 0x12250E37 },
         { .reg = 0x00009888, .val = 0x14250FBD },
         { .reg = 0x00009888, .val = 0x1625003F },
         { .reg = 0x00009888, .val = 0x04250000 },
         { .reg = 0x00009888, .val = 0x02250000 },
         { .reg = 0x00009888, .val = 0x02285555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009AAAA },
         { .reg = 0x00009888, .val = 0x0209FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x0000002A },
         { .reg = 0x0000D954, .val = 0x0000FFFA },
         { .reg = 0x0000D958, .val = 0x00000282 },
         { .reg = 0x0000D95C, .val = 0x0000FFAF },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000F0FF },
         { .reg = 0x0000D968, .val = 0x00008002 },
         { .reg = 0x0000D96C, .val = 0x00000FFF },
         { .reg = 0x0000D970, .val = 0x00002802 },
         { .reg = 0x0000D974, .val = 0x0000FAFF },
         { .reg = 0x0000D978, .val = 0x00028002 },
         { .reg = 0x0000D97C, .val = 0x0000AFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext212__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext212__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext212__avg_gpu_core_frequency__max,mtlgt3__ext212__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6209, 24, NULL,mtlgt3__ext212__rt_quad_leaf_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6210, 32, NULL,mtlgt3__ext212__rt_procedural_node_ray_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6211, 40, NULL,mtlgt3__ext212__rt_quad_leaf_ray_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6212, 48, NULL,mtlgt3__ext212__rt_procedural_node_ray_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext213_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext213";
   query->symbol_name = "Ext213";
   query->guid = "39a43efe-ee39-4fa2-88c4-3dfc34a74f4f";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C855C00 },
         { .reg = 0x00009888, .val = 0x1E85001C },
         { .reg = 0x00009888, .val = 0x1CA55C00 },
         { .reg = 0x00009888, .val = 0x1EA5001C },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x06856040 },
         { .reg = 0x00009888, .val = 0x08850DB5 },
         { .reg = 0x00009888, .val = 0x0A850E37 },
         { .reg = 0x00009888, .val = 0x0C850FBD },
         { .reg = 0x00009888, .val = 0x0E85003F },
         { .reg = 0x00009888, .val = 0x04850000 },
         { .reg = 0x00009888, .val = 0x00850000 },
         { .reg = 0x00009888, .val = 0x00885555 },
         { .reg = 0x00009888, .val = 0x02A2AAAA },
         { .reg = 0x00009888, .val = 0x06A50040 },
         { .reg = 0x00009888, .val = 0x0EA50C00 },
         { .reg = 0x00009888, .val = 0x10A50DB5 },
         { .reg = 0x00009888, .val = 0x12A50E37 },
         { .reg = 0x00009888, .val = 0x14A50FBD },
         { .reg = 0x00009888, .val = 0x16A5003F },
         { .reg = 0x00009888, .val = 0x04A50000 },
         { .reg = 0x00009888, .val = 0x02A50000 },
         { .reg = 0x00009888, .val = 0x02A85555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029AAAA },
         { .reg = 0x00009888, .val = 0x0229FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x0000002A },
         { .reg = 0x0000D954, .val = 0x0000FFFA },
         { .reg = 0x0000D958, .val = 0x00000282 },
         { .reg = 0x0000D95C, .val = 0x0000FFAF },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000F0FF },
         { .reg = 0x0000D968, .val = 0x00008002 },
         { .reg = 0x0000D96C, .val = 0x00000FFF },
         { .reg = 0x0000D970, .val = 0x00002802 },
         { .reg = 0x0000D974, .val = 0x0000FAFF },
         { .reg = 0x0000D978, .val = 0x00028002 },
         { .reg = 0x0000D97C, .val = 0x0000AFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext213__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext213__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext213__avg_gpu_core_frequency__max,mtlgt3__ext213__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6984, 24, NULL,mtlgt3__ext213__rt_quad_leaf_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6985, 32, NULL,mtlgt3__ext213__rt_procedural_node_ray_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6986, 40, NULL,mtlgt3__ext213__rt_quad_leaf_ray_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6987, 48, NULL,mtlgt3__ext213__rt_procedural_node_ray_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext214_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext214";
   query->symbol_name = "Ext214";
   query->guid = "f3ca645b-a2b3-496b-bf6d-f8f26b1faa86";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C455C00 },
         { .reg = 0x00009888, .val = 0x1E45001C },
         { .reg = 0x00009888, .val = 0x1C655C00 },
         { .reg = 0x00009888, .val = 0x1E65001C },
         { .reg = 0x00009888, .val = 0x0242AAAA },
         { .reg = 0x00009888, .val = 0x06450040 },
         { .reg = 0x00009888, .val = 0x0E450C00 },
         { .reg = 0x00009888, .val = 0x10450DB5 },
         { .reg = 0x00009888, .val = 0x12450E37 },
         { .reg = 0x00009888, .val = 0x14450FBD },
         { .reg = 0x00009888, .val = 0x1645003F },
         { .reg = 0x00009888, .val = 0x04450000 },
         { .reg = 0x00009888, .val = 0x02450000 },
         { .reg = 0x00009888, .val = 0x02485555 },
         { .reg = 0x00009888, .val = 0x0062AAAA },
         { .reg = 0x00009888, .val = 0x06656040 },
         { .reg = 0x00009888, .val = 0x08650DB5 },
         { .reg = 0x00009888, .val = 0x0A650E37 },
         { .reg = 0x00009888, .val = 0x0C650FBD },
         { .reg = 0x00009888, .val = 0x0E65003F },
         { .reg = 0x00009888, .val = 0x04650000 },
         { .reg = 0x00009888, .val = 0x00650000 },
         { .reg = 0x00009888, .val = 0x00685555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x0000002A },
         { .reg = 0x0000D954, .val = 0x0000FFFA },
         { .reg = 0x0000D958, .val = 0x00000282 },
         { .reg = 0x0000D95C, .val = 0x0000FFAF },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000F0FF },
         { .reg = 0x0000D968, .val = 0x00008002 },
         { .reg = 0x0000D96C, .val = 0x00000FFF },
         { .reg = 0x0000D970, .val = 0x00002802 },
         { .reg = 0x0000D974, .val = 0x0000FAFF },
         { .reg = 0x0000D978, .val = 0x00028002 },
         { .reg = 0x0000D97C, .val = 0x0000AFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext214__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext214__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext214__avg_gpu_core_frequency__max,mtlgt3__ext214__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6213, 24, NULL,mtlgt3__ext214__rt_quad_leaf_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6214, 32, NULL,mtlgt3__ext214__rt_procedural_node_ray_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6215, 40, NULL,mtlgt3__ext214__rt_quad_leaf_ray_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6216, 48, NULL,mtlgt3__ext214__rt_procedural_node_ray_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext215_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 7);

   query->name = "Ext215";
   query->symbol_name = "Ext215";
   query->guid = "947b168e-df39-4e92-a622-0884c81221b3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1CC55C00 },
         { .reg = 0x00009888, .val = 0x1EC5001C },
         { .reg = 0x00009888, .val = 0x1CE55C00 },
         { .reg = 0x00009888, .val = 0x1EE5001C },
         { .reg = 0x00009888, .val = 0x00C2AAAA },
         { .reg = 0x00009888, .val = 0x06C56040 },
         { .reg = 0x00009888, .val = 0x08C50DB5 },
         { .reg = 0x00009888, .val = 0x0AC50E37 },
         { .reg = 0x00009888, .val = 0x0CC50FBD },
         { .reg = 0x00009888, .val = 0x0EC5003F },
         { .reg = 0x00009888, .val = 0x04C50000 },
         { .reg = 0x00009888, .val = 0x00C50000 },
         { .reg = 0x00009888, .val = 0x00C85555 },
         { .reg = 0x00009888, .val = 0x02E2AAAA },
         { .reg = 0x00009888, .val = 0x06E50040 },
         { .reg = 0x00009888, .val = 0x0EE50C00 },
         { .reg = 0x00009888, .val = 0x10E50DB5 },
         { .reg = 0x00009888, .val = 0x12E50E37 },
         { .reg = 0x00009888, .val = 0x14E50FBD },
         { .reg = 0x00009888, .val = 0x16E5003F },
         { .reg = 0x00009888, .val = 0x04E50000 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E85555 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010020 },
         { .reg = 0x00009888, .val = 0x50010402 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010402 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFF0 },
         { .reg = 0x0000D948, .val = 0x00000082 },
         { .reg = 0x0000D94C, .val = 0x0000FF0F },
         { .reg = 0x0000D950, .val = 0x0000002A },
         { .reg = 0x0000D954, .val = 0x0000FFFA },
         { .reg = 0x0000D958, .val = 0x00000282 },
         { .reg = 0x0000D95C, .val = 0x0000FFAF },
         { .reg = 0x0000D960, .val = 0x00000802 },
         { .reg = 0x0000D964, .val = 0x0000F0FF },
         { .reg = 0x0000D968, .val = 0x00008002 },
         { .reg = 0x0000D96C, .val = 0x00000FFF },
         { .reg = 0x0000D970, .val = 0x00002802 },
         { .reg = 0x0000D974, .val = 0x0000FAFF },
         { .reg = 0x0000D978, .val = 0x00028002 },
         { .reg = 0x0000D97C, .val = 0x0000AFFF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext215__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext215__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext215__avg_gpu_core_frequency__max,mtlgt3__ext215__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6988, 24, NULL,mtlgt3__ext215__rt_quad_leaf_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6989, 32, NULL,mtlgt3__ext215__rt_procedural_node_ray_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6990, 40, NULL,mtlgt3__ext215__rt_quad_leaf_ray_count_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6991, 48, NULL,mtlgt3__ext215__rt_procedural_node_ray_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext220_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext220";
   query->symbol_name = "Ext220";
   query->guid = "0722885e-4df8-4c98-8336-72b5e129e6be";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18050000 },
         { .reg = 0x00009888, .val = 0x18250000 },
         { .reg = 0x00009888, .val = 0x18450000 },
         { .reg = 0x00009888, .val = 0x18650000 },
         { .reg = 0x00009888, .val = 0x18850000 },
         { .reg = 0x00009888, .val = 0x18A50000 },
         { .reg = 0x00009888, .val = 0x18C50000 },
         { .reg = 0x00009888, .val = 0x18E50000 },
         { .reg = 0x00009888, .val = 0x0002000A },
         { .reg = 0x00009888, .val = 0x04050080 },
         { .reg = 0x00009888, .val = 0x06052000 },
         { .reg = 0x00009888, .val = 0x08050011 },
         { .reg = 0x00009888, .val = 0x00050000 },
         { .reg = 0x00009888, .val = 0x00080005 },
         { .reg = 0x00009888, .val = 0x002200A0 },
         { .reg = 0x00009888, .val = 0x04250080 },
         { .reg = 0x00009888, .val = 0x08250400 },
         { .reg = 0x00009888, .val = 0x0A250011 },
         { .reg = 0x00009888, .val = 0x00250000 },
         { .reg = 0x00009888, .val = 0x00280050 },
         { .reg = 0x00009888, .val = 0x00420A00 },
         { .reg = 0x00009888, .val = 0x04450080 },
         { .reg = 0x00009888, .val = 0x0A450400 },
         { .reg = 0x00009888, .val = 0x0C450011 },
         { .reg = 0x00009888, .val = 0x00450000 },
         { .reg = 0x00009888, .val = 0x00480500 },
         { .reg = 0x00009888, .val = 0x0062A000 },
         { .reg = 0x00009888, .val = 0x04650080 },
         { .reg = 0x00009888, .val = 0x0C650400 },
         { .reg = 0x00009888, .val = 0x0E650011 },
         { .reg = 0x00009888, .val = 0x00650000 },
         { .reg = 0x00009888, .val = 0x00685000 },
         { .reg = 0x00009888, .val = 0x0282A000 },
         { .reg = 0x00009888, .val = 0x04850080 },
         { .reg = 0x00009888, .val = 0x14850440 },
         { .reg = 0x00009888, .val = 0x16850010 },
         { .reg = 0x00009888, .val = 0x02850000 },
         { .reg = 0x00009888, .val = 0x02885000 },
         { .reg = 0x00009888, .val = 0x02A20A00 },
         { .reg = 0x00009888, .val = 0x04A50080 },
         { .reg = 0x00009888, .val = 0x12A50440 },
         { .reg = 0x00009888, .val = 0x14A50010 },
         { .reg = 0x00009888, .val = 0x02A50000 },
         { .reg = 0x00009888, .val = 0x02A80500 },
         { .reg = 0x00009888, .val = 0x02C200A0 },
         { .reg = 0x00009888, .val = 0x04C50080 },
         { .reg = 0x00009888, .val = 0x10C50440 },
         { .reg = 0x00009888, .val = 0x12C50010 },
         { .reg = 0x00009888, .val = 0x02C50000 },
         { .reg = 0x00009888, .val = 0x02C80050 },
         { .reg = 0x00009888, .val = 0x02E2000A },
         { .reg = 0x00009888, .val = 0x04E50080 },
         { .reg = 0x00009888, .val = 0x0EE50440 },
         { .reg = 0x00009888, .val = 0x10E50010 },
         { .reg = 0x00009888, .val = 0x02E50000 },
         { .reg = 0x00009888, .val = 0x02E80005 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00010F55 },
         { .reg = 0x00009888, .val = 0x00040055 },
         { .reg = 0x00009888, .val = 0x000B000F },
         { .reg = 0x00009888, .val = 0x000900FA },
         { .reg = 0x00009888, .val = 0x000A0AAA },
         { .reg = 0x00009888, .val = 0x022155F0 },
         { .reg = 0x00009888, .val = 0x02245500 },
         { .reg = 0x00009888, .val = 0x002BF000 },
         { .reg = 0x00009888, .val = 0x0229AF00 },
         { .reg = 0x00009888, .val = 0x022AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FAAA },
         { .reg = 0x00009888, .val = 0x0282AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010050 },
         { .reg = 0x00009888, .val = 0x5C010E05 },
         { .reg = 0x00009888, .val = 0x5E010070 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010A05 },
         { .reg = 0x00009888, .val = 0x4E010030 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext220__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext220__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext220__avg_gpu_core_frequency__max,mtlgt3__ext220__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6217, 24, NULL,mtlgt3__ext220__rt_bvh_cache_miss_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6218, 32, NULL,mtlgt3__ext220__rt_bvh_cache_miss_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6219, 40, NULL,mtlgt3__ext220__rt_bvh_cache_miss_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6220, 48, NULL,mtlgt3__ext220__rt_bvh_cache_miss_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6992, 56, NULL,mtlgt3__ext220__rt_bvh_cache_miss_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6993, 64, NULL,mtlgt3__ext220__rt_bvh_cache_miss_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 6994, 72, NULL,mtlgt3__ext220__rt_bvh_cache_miss_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 6995, 80, NULL,mtlgt3__ext220__rt_bvh_cache_miss_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext225_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext225";
   query->symbol_name = "Ext225";
   query->guid = "db4a27f8-40a0-4cb5-aa3a-5368add92cd5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x260B7000 },
         { .reg = 0x00009888, .val = 0x280B001B },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010011 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040011 },
         { .reg = 0x00009888, .val = 0x040B6160 },
         { .reg = 0x00009888, .val = 0x060B0C7D },
         { .reg = 0x00009888, .val = 0x080B0CF2 },
         { .reg = 0x00009888, .val = 0x0A0B0D74 },
         { .reg = 0x00009888, .val = 0x0C0B0DF6 },
         { .reg = 0x00009888, .val = 0x0E0B0FC0 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A0022 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42020001 },
         { .reg = 0x00009888, .val = 0x0602000E },
         { .reg = 0x00009888, .val = 0x10020033 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x000205FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02030022 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010C00 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02020022 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext225__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext225__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext225__avg_gpu_core_frequency__max,mtlgt3__ext225__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6221, 24, NULL,mtlgt3__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext226_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext226";
   query->symbol_name = "Ext226";
   query->guid = "6b5736f5-a627-4cb6-9078-1c05137bc460";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x262B6C00 },
         { .reg = 0x00009888, .val = 0x282B001C },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02210011 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02240011 },
         { .reg = 0x00009888, .val = 0x042B6F60 },
         { .reg = 0x00009888, .val = 0x062B0E35 },
         { .reg = 0x00009888, .val = 0x082B0EB9 },
         { .reg = 0x00009888, .val = 0x0A2B0F3B },
         { .reg = 0x00009888, .val = 0x0C2B0FBD },
         { .reg = 0x00009888, .val = 0x0E2B0FC0 },
         { .reg = 0x00009888, .val = 0x022B0000 },
         { .reg = 0x00009888, .val = 0x002B0000 },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A0022 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42020001 },
         { .reg = 0x00009888, .val = 0x000505FF },
         { .reg = 0x00009888, .val = 0x0602000E },
         { .reg = 0x00009888, .val = 0x10020033 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x000205FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030011 },
         { .reg = 0x00009888, .val = 0x000405FF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60011000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x02820022 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000001A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000032 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000052 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000092 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000112 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000212 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000412 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000812 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext226__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext226__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext226__avg_gpu_core_frequency__max,mtlgt3__ext226__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6996, 24, NULL,mtlgt3__ext226__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext227_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext227";
   query->symbol_name = "Ext227";
   query->guid = "5e6f4959-c37c-4be0-bb4e-2f1c1aef2bb3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x260B6C00 },
         { .reg = 0x00009888, .val = 0x280B001C },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010011 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02040011 },
         { .reg = 0x00009888, .val = 0x040B6F60 },
         { .reg = 0x00009888, .val = 0x060B0E35 },
         { .reg = 0x00009888, .val = 0x080B0EB9 },
         { .reg = 0x00009888, .val = 0x0A0B0F3B },
         { .reg = 0x00009888, .val = 0x0C0B0FBD },
         { .reg = 0x00009888, .val = 0x0E0B0FC0 },
         { .reg = 0x00009888, .val = 0x020B0000 },
         { .reg = 0x00009888, .val = 0x000B0000 },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020A0022 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42020001 },
         { .reg = 0x00009888, .val = 0x0602000E },
         { .reg = 0x00009888, .val = 0x10020033 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x000205FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02030022 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010C00 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x02020022 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF08000FE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext227__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext227__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext227__avg_gpu_core_frequency__max,mtlgt3__ext227__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6222, 24, NULL,mtlgt3__ext227__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext228_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext228";
   query->symbol_name = "Ext228";
   query->guid = "fe2d673e-8b2e-47d0-b9db-2c50e10ee53e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x262B6C00 },
         { .reg = 0x00009888, .val = 0x282B001C },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02210011 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02240011 },
         { .reg = 0x00009888, .val = 0x042B6F60 },
         { .reg = 0x00009888, .val = 0x062B0E35 },
         { .reg = 0x00009888, .val = 0x082B0EB9 },
         { .reg = 0x00009888, .val = 0x0A2B0F3B },
         { .reg = 0x00009888, .val = 0x0C2B0FBD },
         { .reg = 0x00009888, .val = 0x0E2B0FC0 },
         { .reg = 0x00009888, .val = 0x022B0000 },
         { .reg = 0x00009888, .val = 0x002B0000 },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022A0022 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42020001 },
         { .reg = 0x00009888, .val = 0x000505FF },
         { .reg = 0x00009888, .val = 0x0602000E },
         { .reg = 0x00009888, .val = 0x10020033 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x000205FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010015 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02030011 },
         { .reg = 0x00009888, .val = 0x000405FF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60011000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x02820022 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF08000FE },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x0000FFFC },
         { .reg = 0x0000D948, .val = 0x00000022 },
         { .reg = 0x0000D94C, .val = 0x0000FFF9 },
         { .reg = 0x0000D950, .val = 0x00000042 },
         { .reg = 0x0000D954, .val = 0x0000FFF5 },
         { .reg = 0x0000D958, .val = 0x00000082 },
         { .reg = 0x0000D95C, .val = 0x0000FFED },
         { .reg = 0x0000D960, .val = 0x00000102 },
         { .reg = 0x0000D964, .val = 0x0000FFDD },
         { .reg = 0x0000D968, .val = 0x00000202 },
         { .reg = 0x0000D96C, .val = 0x0000FFBD },
         { .reg = 0x0000D970, .val = 0x00000402 },
         { .reg = 0x0000D974, .val = 0x0000FF7D },
         { .reg = 0x0000D978, .val = 0x00000802 },
         { .reg = 0x0000D97C, .val = 0x0000FEFD },
         { .reg = 0x0000D90C, .val = 0x1111111A },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext228__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext228__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext228__avg_gpu_core_frequency__max,mtlgt3__ext228__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 6997, 24, NULL,mtlgt3__ext228__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext229_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext229";
   query->symbol_name = "Ext229";
   query->guid = "cb94a696-bfbe-4566-8225-c337f988600c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x260814C0 },
         { .reg = 0x00009888, .val = 0x2C0800A6 },
         { .reg = 0x00009888, .val = 0x262818A0 },
         { .reg = 0x00009888, .val = 0x2C2800C5 },
         { .reg = 0x00009888, .val = 0x06080832 },
         { .reg = 0x00009888, .val = 0x08080C31 },
         { .reg = 0x00009888, .val = 0x0A080FBF },
         { .reg = 0x00009888, .val = 0x0C080821 },
         { .reg = 0x00009888, .val = 0x0E080BAF },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x06280832 },
         { .reg = 0x00009888, .val = 0x102809E6 },
         { .reg = 0x00009888, .val = 0x12280A68 },
         { .reg = 0x00009888, .val = 0x14280DF6 },
         { .reg = 0x00009888, .val = 0x16280E78 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009AAAA },
         { .reg = 0x00009888, .val = 0x0209FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext229__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext229__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext229__avg_gpu_core_frequency__max,mtlgt3__ext229__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6223, 24, NULL,mtlgt3__ext229__slm_bank_conflict_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6224, 32, NULL,mtlgt3__ext229__slm_bank_conflict_count_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext230_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext230";
   query->symbol_name = "Ext230";
   query->guid = "ec3032cb-df12-445c-9eb2-6b1031d2dc86";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x268814C0 },
         { .reg = 0x00009888, .val = 0x2C8800A6 },
         { .reg = 0x00009888, .val = 0x26A814C0 },
         { .reg = 0x00009888, .val = 0x2CA800A6 },
         { .reg = 0x00009888, .val = 0x06880832 },
         { .reg = 0x00009888, .val = 0x10880C31 },
         { .reg = 0x00009888, .val = 0x12880FBF },
         { .reg = 0x00009888, .val = 0x14880821 },
         { .reg = 0x00009888, .val = 0x16880BAF },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009888, .val = 0x06A80832 },
         { .reg = 0x00009888, .val = 0x08A80C31 },
         { .reg = 0x00009888, .val = 0x0AA80FBF },
         { .reg = 0x00009888, .val = 0x0CA80821 },
         { .reg = 0x00009888, .val = 0x0EA80BAF },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029FFFF },
         { .reg = 0x00009888, .val = 0x0229AAAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext230__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext230__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext230__avg_gpu_core_frequency__max,mtlgt3__ext230__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 6998, 24, NULL,mtlgt3__ext230__slm_bank_conflict_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 6999, 32, NULL,mtlgt3__ext230__slm_bank_conflict_count_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext231_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext231";
   query->symbol_name = "Ext231";
   query->guid = "e5e22fbb-0ff4-44f6-a549-6ed41df0dd27";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x264818A0 },
         { .reg = 0x00009888, .val = 0x2C4800C5 },
         { .reg = 0x00009888, .val = 0x266818A0 },
         { .reg = 0x00009888, .val = 0x2C6800C5 },
         { .reg = 0x00009888, .val = 0x06480832 },
         { .reg = 0x00009888, .val = 0x084809E6 },
         { .reg = 0x00009888, .val = 0x0A480A68 },
         { .reg = 0x00009888, .val = 0x0C480DF6 },
         { .reg = 0x00009888, .val = 0x0E480E78 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x06680832 },
         { .reg = 0x00009888, .val = 0x106809E6 },
         { .reg = 0x00009888, .val = 0x12680A68 },
         { .reg = 0x00009888, .val = 0x14680DF6 },
         { .reg = 0x00009888, .val = 0x16680E78 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010020 },
         { .reg = 0x00009888, .val = 0x50010402 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010402 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext231__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext231__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext231__avg_gpu_core_frequency__max,mtlgt3__ext231__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6225, 24, NULL,mtlgt3__ext231__slm_bank_conflict_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6226, 32, NULL,mtlgt3__ext231__slm_bank_conflict_count_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext232_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext232";
   query->symbol_name = "Ext232";
   query->guid = "b6defb71-0fe8-400e-ae27-565ce9067082";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x26C814C0 },
         { .reg = 0x00009888, .val = 0x2CC800A6 },
         { .reg = 0x00009888, .val = 0x26E814C0 },
         { .reg = 0x00009888, .val = 0x2CE800A6 },
         { .reg = 0x00009888, .val = 0x06C80832 },
         { .reg = 0x00009888, .val = 0x10C80C31 },
         { .reg = 0x00009888, .val = 0x12C80FBF },
         { .reg = 0x00009888, .val = 0x14C80821 },
         { .reg = 0x00009888, .val = 0x16C80BAF },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x06E80832 },
         { .reg = 0x00009888, .val = 0x08E80C31 },
         { .reg = 0x00009888, .val = 0x0AE80FBF },
         { .reg = 0x00009888, .val = 0x0CE80821 },
         { .reg = 0x00009888, .val = 0x0EE80BAF },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0221FFFF },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FFFF },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext232__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext232__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext232__avg_gpu_core_frequency__max,mtlgt3__ext232__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7000, 24, NULL,mtlgt3__ext232__slm_bank_conflict_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7001, 32, NULL,mtlgt3__ext232__slm_bank_conflict_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext236_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 11);

   query->name = "Ext236";
   query->symbol_name = "Ext236";
   query->guid = "98d5c3d9-bca6-4699-99e3-7b95a23025ce";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0B012000 },
         { .reg = 0x00009888, .val = 0x0B212000 },
         { .reg = 0x00009888, .val = 0x0B412000 },
         { .reg = 0x00009888, .val = 0x0B612000 },
         { .reg = 0x00009888, .val = 0x0B812000 },
         { .reg = 0x00009888, .val = 0x0BA12000 },
         { .reg = 0x00009888, .val = 0x0BC12000 },
         { .reg = 0x00009888, .val = 0x0BE12000 },
         { .reg = 0x00009888, .val = 0x02020055 },
         { .reg = 0x00009888, .val = 0x02825500 },
         { .reg = 0x00009888, .val = 0x01010004 },
         { .reg = 0x00009888, .val = 0x0D010002 },
         { .reg = 0x00009888, .val = 0x03010000 },
         { .reg = 0x00009888, .val = 0x01210004 },
         { .reg = 0x00009888, .val = 0x0D210080 },
         { .reg = 0x00009888, .val = 0x03210000 },
         { .reg = 0x00009888, .val = 0x01410004 },
         { .reg = 0x00009888, .val = 0x0F410002 },
         { .reg = 0x00009888, .val = 0x03410000 },
         { .reg = 0x00009888, .val = 0x01610004 },
         { .reg = 0x00009888, .val = 0x0F610080 },
         { .reg = 0x00009888, .val = 0x03610000 },
         { .reg = 0x00009888, .val = 0x02013400 },
         { .reg = 0x00009888, .val = 0x0401002C },
         { .reg = 0x00009888, .val = 0x01810004 },
         { .reg = 0x00009888, .val = 0x13810080 },
         { .reg = 0x00009888, .val = 0x03810000 },
         { .reg = 0x00009888, .val = 0x01A10004 },
         { .reg = 0x00009888, .val = 0x13A10002 },
         { .reg = 0x00009888, .val = 0x03A10000 },
         { .reg = 0x00009888, .val = 0x01C10004 },
         { .reg = 0x00009888, .val = 0x11C10080 },
         { .reg = 0x00009888, .val = 0x03C10000 },
         { .reg = 0x00009888, .val = 0x01E10004 },
         { .reg = 0x00009888, .val = 0x11E10002 },
         { .reg = 0x00009888, .val = 0x03E10000 },
         { .reg = 0x00009888, .val = 0x04813940 },
         { .reg = 0x00009888, .val = 0x06810002 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F000 },
         { .reg = 0x00009888, .val = 0x0002FF00 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x020355AA },
         { .reg = 0x00009888, .val = 0x0004F000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x60010802 },
         { .reg = 0x00009888, .val = 0x4E010040 },
         { .reg = 0x00009888, .val = 0x50010003 },
         { .reg = 0x00009888, .val = 0x52010020 },
         { .reg = 0x00009888, .val = 0x54010401 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext236__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext236__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext236__avg_gpu_core_frequency__max,mtlgt3__ext236__avg_gpu_core_frequency__read);

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6227, 24, NULL,mtlgt3__ext236__l3_miss_l3_bank0__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6228, 32, NULL,mtlgt3__ext236__l3_miss_l3_bank1__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6229, 40, NULL,mtlgt3__ext236__l3_miss_l3_bank2__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 6230, 48, NULL,mtlgt3__ext236__l3_miss_l3_bank3__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 7002, 56, NULL,mtlgt3__ext236__l3_miss_l3_bank4__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 7003, 64, NULL,mtlgt3__ext236__l3_miss_l3_bank5__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 7004, 72, NULL,mtlgt3__ext236__l3_miss_l3_bank6__read);
      }

      if (perf->sys_vars.slice_mask & (3 << (0 * 2))) {
         intel_perf_query_add_counter_uint64(query, 7005, 80, NULL,mtlgt3__ext236__l3_miss_l3_bank7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext237_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 13);

   query->name = "Ext237";
   query->symbol_name = "Ext237";
   query->guid = "4256db1d-9083-4497-9000-59bbcf9eee72";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1E020220 },
         { .reg = 0x00009888, .val = 0x1E220220 },
         { .reg = 0x00009888, .val = 0x1E420220 },
         { .reg = 0x00009888, .val = 0x1E620220 },
         { .reg = 0x00009888, .val = 0x1E820220 },
         { .reg = 0x00009888, .val = 0x1EA20220 },
         { .reg = 0x00009888, .val = 0x1EC20220 },
         { .reg = 0x00009888, .val = 0x1EE20220 },
         { .reg = 0x00009888, .val = 0x04022000 },
         { .reg = 0x00009888, .val = 0x06024C00 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x00080001 },
         { .reg = 0x00009888, .val = 0x04222000 },
         { .reg = 0x00009888, .val = 0x08220026 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x00280004 },
         { .reg = 0x00009888, .val = 0x04422000 },
         { .reg = 0x00009888, .val = 0x08420980 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x00480010 },
         { .reg = 0x00009888, .val = 0x04622000 },
         { .reg = 0x00009888, .val = 0x0A620026 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x00680040 },
         { .reg = 0x00009888, .val = 0x04822000 },
         { .reg = 0x00009888, .val = 0x0A820980 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x00880100 },
         { .reg = 0x00009888, .val = 0x04A22000 },
         { .reg = 0x00009888, .val = 0x0CA20026 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x00A80400 },
         { .reg = 0x00009888, .val = 0x04C22000 },
         { .reg = 0x00009888, .val = 0x0CC20980 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x00C81000 },
         { .reg = 0x00009888, .val = 0x04E22000 },
         { .reg = 0x00009888, .val = 0x0EE20026 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x00E84000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x160B014C },
         { .reg = 0x00009888, .val = 0x162B014C },
         { .reg = 0x00009888, .val = 0x00010035 },
         { .reg = 0x00009888, .val = 0x02010014 },
         { .reg = 0x00009888, .val = 0x00040005 },
         { .reg = 0x00009888, .val = 0x02040014 },
         { .reg = 0x00009888, .val = 0x020B001A },
         { .reg = 0x00009888, .val = 0x0E0B0207 },
         { .reg = 0x00009888, .val = 0x000B0003 },
         { .reg = 0x00009888, .val = 0x0009000E },
         { .reg = 0x00009888, .val = 0x000A002A },
         { .reg = 0x00009888, .val = 0x020A0028 },
         { .reg = 0x00009888, .val = 0x00213500 },
         { .reg = 0x00009888, .val = 0x02210500 },
         { .reg = 0x00009888, .val = 0x00240500 },
         { .reg = 0x00009888, .val = 0x02240500 },
         { .reg = 0x00009888, .val = 0x022B001A },
         { .reg = 0x00009888, .val = 0x102B01C0 },
         { .reg = 0x00009888, .val = 0x122B0008 },
         { .reg = 0x00009888, .val = 0x002B0030 },
         { .reg = 0x00009888, .val = 0x00290E00 },
         { .reg = 0x00009888, .val = 0x002A2A00 },
         { .reg = 0x00009888, .val = 0x022A0A00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x42020001 },
         { .reg = 0x00009888, .val = 0x000530F0 },
         { .reg = 0x00009888, .val = 0x0602000E },
         { .reg = 0x00009888, .val = 0x0E020CC0 },
         { .reg = 0x00009888, .val = 0x12020032 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x000236FF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02010555 },
         { .reg = 0x00009888, .val = 0x000355AA },
         { .reg = 0x00009888, .val = 0x02030528 },
         { .reg = 0x00009888, .val = 0x000430F0 },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010E05 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010600 },
         { .reg = 0x00009888, .val = 0x5E010250 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60011204 },
         { .reg = 0x00009888, .val = 0x4E010290 },
         { .reg = 0x00009888, .val = 0x50010E04 },
         { .reg = 0x00009888, .val = 0x52010070 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x000200EA },
         { .reg = 0x00009888, .val = 0x02020028 },
         { .reg = 0x00009888, .val = 0x0082EA00 },
         { .reg = 0x00009888, .val = 0x02820A00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D90C, .val = 0xAAAAAAA9 },
         { .reg = 0x0000D908, .val = 0xDDDDDDDC },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext237__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext237__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext237__avg_gpu_core_frequency__max,mtlgt3__ext237__avg_gpu_core_frequency__read);

      if (intel_device_info_slice_available(&perf->devinfo, 0)) {
         intel_perf_query_add_counter_uint64(query, 6231, 24, NULL,mtlgt3__ext237__amfs_l3_write_slice0__read);
      }

      if (intel_device_info_slice_available(&perf->devinfo, 1)) {
         intel_perf_query_add_counter_uint64(query, 7006, 32, NULL,mtlgt3__ext237__amfs_l3_write_slice1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6232, 40, NULL,mtlgt3__ext237__xve_dataport_fence_message_count_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6233, 48, NULL,mtlgt3__ext237__xve_dataport_fence_message_count_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6234, 56, NULL,mtlgt3__ext237__xve_dataport_fence_message_count_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6235, 64, NULL,mtlgt3__ext237__xve_dataport_fence_message_count_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7007, 72, NULL,mtlgt3__ext237__xve_dataport_fence_message_count_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7008, 80, NULL,mtlgt3__ext237__xve_dataport_fence_message_count_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7009, 88, NULL,mtlgt3__ext237__xve_dataport_fence_message_count_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7010, 96, NULL,mtlgt3__ext237__xve_dataport_fence_message_count_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext239_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext239";
   query->symbol_name = "Ext239";
   query->guid = "5ba2bf20-ca4e-4872-86fd-9026c9de8c93";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x150100C7 },
         { .reg = 0x00009888, .val = 0x152100A7 },
         { .reg = 0x00009888, .val = 0x0007AAAA },
         { .reg = 0x00009888, .val = 0x0207FFFF },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x03010004 },
         { .reg = 0x00009888, .val = 0x05010205 },
         { .reg = 0x00009888, .val = 0x070102CA },
         { .reg = 0x00009888, .val = 0x0901034C },
         { .reg = 0x00009888, .val = 0x0B0103CE },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03210004 },
         { .reg = 0x00009888, .val = 0x0D210207 },
         { .reg = 0x00009888, .val = 0x0F2102CA },
         { .reg = 0x00009888, .val = 0x1121034C },
         { .reg = 0x00009888, .val = 0x132103CE },
         { .reg = 0x00009888, .val = 0x01210000 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext239__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext239__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext239__avg_gpu_core_frequency__max,mtlgt3__ext239__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6236, 24, NULL,mtlgt3__ext239__gpu_memory_l3_read_sqidi0__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext240_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 4);

   query->name = "Ext240";
   query->symbol_name = "Ext240";
   query->guid = "fe8810c2-457b-47e0-a3b9-50cab24718b4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x150100A7 },
         { .reg = 0x00009888, .val = 0x152100C7 },
         { .reg = 0x00009888, .val = 0x0007FFFF },
         { .reg = 0x00009888, .val = 0x0207AAAA },
         { .reg = 0x00009888, .val = 0x0001AAAA },
         { .reg = 0x00009888, .val = 0x0201AAAA },
         { .reg = 0x00009888, .val = 0x03010004 },
         { .reg = 0x00009888, .val = 0x0D010207 },
         { .reg = 0x00009888, .val = 0x0F0102CA },
         { .reg = 0x00009888, .val = 0x1101034C },
         { .reg = 0x00009888, .val = 0x130103CE },
         { .reg = 0x00009888, .val = 0x01010000 },
         { .reg = 0x00009888, .val = 0x03210004 },
         { .reg = 0x00009888, .val = 0x05210205 },
         { .reg = 0x00009888, .val = 0x072102CA },
         { .reg = 0x00009888, .val = 0x0921034C },
         { .reg = 0x00009888, .val = 0x0B2103CE },
         { .reg = 0x00009888, .val = 0x01210000 },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x30800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x000000CA },
         { .reg = 0x0000D944, .val = 0x0000FF00 },
         { .reg = 0x0000D948, .val = 0x0000C802 },
         { .reg = 0x0000D94C, .val = 0x000000FF },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext240__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext240__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext240__avg_gpu_core_frequency__max,mtlgt3__ext240__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6237, 24, NULL,mtlgt3__ext240__gpu_memory_l3_read_sqidi1__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext500_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext500";
   query->symbol_name = "Ext500";
   query->guid = "ee0cc3d0-9ac8-4608-aaca-b37fd9d18238";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20020006 },
         { .reg = 0x00009888, .val = 0x20220006 },
         { .reg = 0x00009888, .val = 0x20420006 },
         { .reg = 0x00009888, .val = 0x20620006 },
         { .reg = 0x00009888, .val = 0x20820006 },
         { .reg = 0x00009888, .val = 0x20A20006 },
         { .reg = 0x00009888, .val = 0x20C20006 },
         { .reg = 0x00009888, .val = 0x20E20006 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x0A020980 },
         { .reg = 0x00009888, .val = 0x0E020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00080100 },
         { .reg = 0x00009888, .val = 0x02080001 },
         { .reg = 0x00009888, .val = 0x04224000 },
         { .reg = 0x00009888, .val = 0x0C220026 },
         { .reg = 0x00009888, .val = 0x10220025 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x02220000 },
         { .reg = 0x00009888, .val = 0x00280400 },
         { .reg = 0x00009888, .val = 0x02280004 },
         { .reg = 0x00009888, .val = 0x04424000 },
         { .reg = 0x00009888, .val = 0x0C420980 },
         { .reg = 0x00009888, .val = 0x10420940 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x02420000 },
         { .reg = 0x00009888, .val = 0x00481000 },
         { .reg = 0x00009888, .val = 0x02480010 },
         { .reg = 0x00009888, .val = 0x04624000 },
         { .reg = 0x00009888, .val = 0x0E620026 },
         { .reg = 0x00009888, .val = 0x12620025 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x02620000 },
         { .reg = 0x00009888, .val = 0x00684000 },
         { .reg = 0x00009888, .val = 0x02680040 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824C00 },
         { .reg = 0x00009888, .val = 0x16820025 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00880001 },
         { .reg = 0x00009888, .val = 0x02884000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20026 },
         { .reg = 0x00009888, .val = 0x14A20940 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A80004 },
         { .reg = 0x00009888, .val = 0x02A81000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x08C20980 },
         { .reg = 0x00009888, .val = 0x14C20025 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C80010 },
         { .reg = 0x00009888, .val = 0x02C80400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0AE20026 },
         { .reg = 0x00009888, .val = 0x12E20940 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E80040 },
         { .reg = 0x00009888, .val = 0x02E80100 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00013500 },
         { .reg = 0x00009888, .val = 0x02010035 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x000B0330 },
         { .reg = 0x00009888, .val = 0x00090E00 },
         { .reg = 0x00009888, .val = 0x0209000E },
         { .reg = 0x00009888, .val = 0x000A2A00 },
         { .reg = 0x00009888, .val = 0x020A002A },
         { .reg = 0x00009888, .val = 0x00210035 },
         { .reg = 0x00009888, .val = 0x02215C00 },
         { .reg = 0x00009888, .val = 0x00240005 },
         { .reg = 0x00009888, .val = 0x02245000 },
         { .reg = 0x00009888, .val = 0x002BC003 },
         { .reg = 0x00009888, .val = 0x0029000E },
         { .reg = 0x00009888, .val = 0x0229B000 },
         { .reg = 0x00009888, .val = 0x002A002A },
         { .reg = 0x00009888, .val = 0x022AA800 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002EA00 },
         { .reg = 0x00009888, .val = 0x020200EA },
         { .reg = 0x00009888, .val = 0x008200EA },
         { .reg = 0x00009888, .val = 0x0282AB00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F00F },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AA55 },
         { .reg = 0x00009888, .val = 0x020355AA },
         { .reg = 0x00009888, .val = 0x0004F00F },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010A03 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010A02 },
         { .reg = 0x00009888, .val = 0x5E010070 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010A07 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000FEEF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FDDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FBBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000F77F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext500__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext500__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext500__avg_gpu_core_frequency__max,mtlgt3__ext500__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6238, 24, NULL,mtlgt3__ext500__icache_hit_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6239, 32, NULL,mtlgt3__ext500__icache_miss_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6240, 40, NULL,mtlgt3__ext500__icache_hit_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6241, 48, NULL,mtlgt3__ext500__icache_miss_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6242, 56, NULL,mtlgt3__ext500__icache_hit_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6243, 64, NULL,mtlgt3__ext500__icache_miss_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6244, 72, NULL,mtlgt3__ext500__icache_hit_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6245, 80, NULL,mtlgt3__ext500__icache_miss_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7011, 88, NULL,mtlgt3__ext500__icache_hit_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7012, 96, NULL,mtlgt3__ext500__icache_miss_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7013, 104, NULL,mtlgt3__ext500__icache_hit_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7014, 112, NULL,mtlgt3__ext500__icache_miss_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7015, 120, NULL,mtlgt3__ext500__icache_hit_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7016, 128, NULL,mtlgt3__ext500__icache_miss_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7017, 136, NULL,mtlgt3__ext500__icache_hit_bank0_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7018, 144, NULL,mtlgt3__ext500__icache_miss_bank0_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext501_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext501";
   query->symbol_name = "Ext501";
   query->guid = "f6e20d5b-52be-4035-85c2-818a690bf601";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2002000D },
         { .reg = 0x00009888, .val = 0x2022000D },
         { .reg = 0x00009888, .val = 0x2042000D },
         { .reg = 0x00009888, .val = 0x2062000D },
         { .reg = 0x00009888, .val = 0x2082000D },
         { .reg = 0x00009888, .val = 0x20A2000D },
         { .reg = 0x00009888, .val = 0x20C2000D },
         { .reg = 0x00009888, .val = 0x20E2000D },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x0A020980 },
         { .reg = 0x00009888, .val = 0x0E020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00080100 },
         { .reg = 0x00009888, .val = 0x02080001 },
         { .reg = 0x00009888, .val = 0x04224000 },
         { .reg = 0x00009888, .val = 0x0C220026 },
         { .reg = 0x00009888, .val = 0x10220025 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x02220000 },
         { .reg = 0x00009888, .val = 0x00280400 },
         { .reg = 0x00009888, .val = 0x02280004 },
         { .reg = 0x00009888, .val = 0x04424000 },
         { .reg = 0x00009888, .val = 0x0C420980 },
         { .reg = 0x00009888, .val = 0x10420940 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x02420000 },
         { .reg = 0x00009888, .val = 0x00481000 },
         { .reg = 0x00009888, .val = 0x02480010 },
         { .reg = 0x00009888, .val = 0x04624000 },
         { .reg = 0x00009888, .val = 0x0E620026 },
         { .reg = 0x00009888, .val = 0x12620025 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x02620000 },
         { .reg = 0x00009888, .val = 0x00684000 },
         { .reg = 0x00009888, .val = 0x02680040 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824C00 },
         { .reg = 0x00009888, .val = 0x16820025 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00880001 },
         { .reg = 0x00009888, .val = 0x02884000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20026 },
         { .reg = 0x00009888, .val = 0x14A20940 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A80004 },
         { .reg = 0x00009888, .val = 0x02A81000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x08C20980 },
         { .reg = 0x00009888, .val = 0x14C20025 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C80010 },
         { .reg = 0x00009888, .val = 0x02C80400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0AE20026 },
         { .reg = 0x00009888, .val = 0x12E20940 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E80040 },
         { .reg = 0x00009888, .val = 0x02E80100 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00013500 },
         { .reg = 0x00009888, .val = 0x02010035 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x000B0330 },
         { .reg = 0x00009888, .val = 0x00090E00 },
         { .reg = 0x00009888, .val = 0x0209000E },
         { .reg = 0x00009888, .val = 0x000A2A00 },
         { .reg = 0x00009888, .val = 0x020A002A },
         { .reg = 0x00009888, .val = 0x00210035 },
         { .reg = 0x00009888, .val = 0x02215C00 },
         { .reg = 0x00009888, .val = 0x00240005 },
         { .reg = 0x00009888, .val = 0x02245000 },
         { .reg = 0x00009888, .val = 0x002BC003 },
         { .reg = 0x00009888, .val = 0x0029000E },
         { .reg = 0x00009888, .val = 0x0229B000 },
         { .reg = 0x00009888, .val = 0x002A002A },
         { .reg = 0x00009888, .val = 0x022AA800 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002EA00 },
         { .reg = 0x00009888, .val = 0x020200EA },
         { .reg = 0x00009888, .val = 0x008200EA },
         { .reg = 0x00009888, .val = 0x0282AB00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F00F },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AA55 },
         { .reg = 0x00009888, .val = 0x020355AA },
         { .reg = 0x00009888, .val = 0x0004F00F },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010A03 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010A02 },
         { .reg = 0x00009888, .val = 0x5E010070 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010A07 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000FEEF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FDDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FBBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000F77F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext501__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext501__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext501__avg_gpu_core_frequency__max,mtlgt3__ext501__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6246, 24, NULL,mtlgt3__ext501__icache_hit_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6247, 32, NULL,mtlgt3__ext501__icache_miss_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6248, 40, NULL,mtlgt3__ext501__icache_hit_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6249, 48, NULL,mtlgt3__ext501__icache_miss_bank1_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6250, 56, NULL,mtlgt3__ext501__icache_hit_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6251, 64, NULL,mtlgt3__ext501__icache_miss_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6252, 72, NULL,mtlgt3__ext501__icache_hit_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6253, 80, NULL,mtlgt3__ext501__icache_miss_bank1_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7019, 88, NULL,mtlgt3__ext501__icache_hit_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7020, 96, NULL,mtlgt3__ext501__icache_miss_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7021, 104, NULL,mtlgt3__ext501__icache_hit_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7022, 112, NULL,mtlgt3__ext501__icache_miss_bank1_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7023, 120, NULL,mtlgt3__ext501__icache_hit_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7024, 128, NULL,mtlgt3__ext501__icache_miss_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7025, 136, NULL,mtlgt3__ext501__icache_hit_bank1_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7026, 144, NULL,mtlgt3__ext501__icache_miss_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext502_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext502";
   query->symbol_name = "Ext502";
   query->guid = "d09cedef-e3e3-41b5-8ce8-ddc3933339ca";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x20020014 },
         { .reg = 0x00009888, .val = 0x20220014 },
         { .reg = 0x00009888, .val = 0x20420014 },
         { .reg = 0x00009888, .val = 0x20620014 },
         { .reg = 0x00009888, .val = 0x20820014 },
         { .reg = 0x00009888, .val = 0x20A20014 },
         { .reg = 0x00009888, .val = 0x20C20014 },
         { .reg = 0x00009888, .val = 0x20E20014 },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x0A020980 },
         { .reg = 0x00009888, .val = 0x0E020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00080100 },
         { .reg = 0x00009888, .val = 0x02080001 },
         { .reg = 0x00009888, .val = 0x04224000 },
         { .reg = 0x00009888, .val = 0x0C220026 },
         { .reg = 0x00009888, .val = 0x10220025 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x02220000 },
         { .reg = 0x00009888, .val = 0x00280400 },
         { .reg = 0x00009888, .val = 0x02280004 },
         { .reg = 0x00009888, .val = 0x04424000 },
         { .reg = 0x00009888, .val = 0x0C420980 },
         { .reg = 0x00009888, .val = 0x10420940 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x02420000 },
         { .reg = 0x00009888, .val = 0x00481000 },
         { .reg = 0x00009888, .val = 0x02480010 },
         { .reg = 0x00009888, .val = 0x04624000 },
         { .reg = 0x00009888, .val = 0x0E620026 },
         { .reg = 0x00009888, .val = 0x12620025 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x02620000 },
         { .reg = 0x00009888, .val = 0x00684000 },
         { .reg = 0x00009888, .val = 0x02680040 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824C00 },
         { .reg = 0x00009888, .val = 0x16820025 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00880001 },
         { .reg = 0x00009888, .val = 0x02884000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20026 },
         { .reg = 0x00009888, .val = 0x14A20940 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A80004 },
         { .reg = 0x00009888, .val = 0x02A81000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x08C20980 },
         { .reg = 0x00009888, .val = 0x14C20025 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C80010 },
         { .reg = 0x00009888, .val = 0x02C80400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0AE20026 },
         { .reg = 0x00009888, .val = 0x12E20940 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E80040 },
         { .reg = 0x00009888, .val = 0x02E80100 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00013500 },
         { .reg = 0x00009888, .val = 0x02010035 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x000B0330 },
         { .reg = 0x00009888, .val = 0x00090E00 },
         { .reg = 0x00009888, .val = 0x0209000E },
         { .reg = 0x00009888, .val = 0x000A2A00 },
         { .reg = 0x00009888, .val = 0x020A002A },
         { .reg = 0x00009888, .val = 0x00210035 },
         { .reg = 0x00009888, .val = 0x02215C00 },
         { .reg = 0x00009888, .val = 0x00240005 },
         { .reg = 0x00009888, .val = 0x02245000 },
         { .reg = 0x00009888, .val = 0x002BC003 },
         { .reg = 0x00009888, .val = 0x0029000E },
         { .reg = 0x00009888, .val = 0x0229B000 },
         { .reg = 0x00009888, .val = 0x002A002A },
         { .reg = 0x00009888, .val = 0x022AA800 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002EA00 },
         { .reg = 0x00009888, .val = 0x020200EA },
         { .reg = 0x00009888, .val = 0x008200EA },
         { .reg = 0x00009888, .val = 0x0282AB00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F00F },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AA55 },
         { .reg = 0x00009888, .val = 0x020355AA },
         { .reg = 0x00009888, .val = 0x0004F00F },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010A03 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010A02 },
         { .reg = 0x00009888, .val = 0x5E010070 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010A07 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000FEEF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FDDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FBBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000F77F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext502__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext502__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext502__avg_gpu_core_frequency__max,mtlgt3__ext502__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6254, 24, NULL,mtlgt3__ext502__icache_hit_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6255, 32, NULL,mtlgt3__ext502__icache_miss_bank2_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6256, 40, NULL,mtlgt3__ext502__icache_hit_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6257, 48, NULL,mtlgt3__ext502__icache_miss_bank2_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6258, 56, NULL,mtlgt3__ext502__icache_hit_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6259, 64, NULL,mtlgt3__ext502__icache_miss_bank2_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6260, 72, NULL,mtlgt3__ext502__icache_hit_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6261, 80, NULL,mtlgt3__ext502__icache_miss_bank2_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7027, 88, NULL,mtlgt3__ext502__icache_hit_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7028, 96, NULL,mtlgt3__ext502__icache_miss_bank2_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7029, 104, NULL,mtlgt3__ext502__icache_hit_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7030, 112, NULL,mtlgt3__ext502__icache_miss_bank2_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7031, 120, NULL,mtlgt3__ext502__icache_hit_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7032, 128, NULL,mtlgt3__ext502__icache_miss_bank2_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7033, 136, NULL,mtlgt3__ext502__icache_hit_bank2_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7034, 144, NULL,mtlgt3__ext502__icache_miss_bank2_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext503_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext503";
   query->symbol_name = "Ext503";
   query->guid = "96067625-3663-4f9a-8b26-74e47ab1aff4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2002001B },
         { .reg = 0x00009888, .val = 0x2022001B },
         { .reg = 0x00009888, .val = 0x2042001B },
         { .reg = 0x00009888, .val = 0x2062001B },
         { .reg = 0x00009888, .val = 0x2082001B },
         { .reg = 0x00009888, .val = 0x20A2001B },
         { .reg = 0x00009888, .val = 0x20C2001B },
         { .reg = 0x00009888, .val = 0x20E2001B },
         { .reg = 0x00009888, .val = 0x04024000 },
         { .reg = 0x00009888, .val = 0x0A020980 },
         { .reg = 0x00009888, .val = 0x0E020940 },
         { .reg = 0x00009888, .val = 0x00020000 },
         { .reg = 0x00009888, .val = 0x02020000 },
         { .reg = 0x00009888, .val = 0x00080100 },
         { .reg = 0x00009888, .val = 0x02080001 },
         { .reg = 0x00009888, .val = 0x04224000 },
         { .reg = 0x00009888, .val = 0x0C220026 },
         { .reg = 0x00009888, .val = 0x10220025 },
         { .reg = 0x00009888, .val = 0x00220000 },
         { .reg = 0x00009888, .val = 0x02220000 },
         { .reg = 0x00009888, .val = 0x00280400 },
         { .reg = 0x00009888, .val = 0x02280004 },
         { .reg = 0x00009888, .val = 0x04424000 },
         { .reg = 0x00009888, .val = 0x0C420980 },
         { .reg = 0x00009888, .val = 0x10420940 },
         { .reg = 0x00009888, .val = 0x00420000 },
         { .reg = 0x00009888, .val = 0x02420000 },
         { .reg = 0x00009888, .val = 0x00481000 },
         { .reg = 0x00009888, .val = 0x02480010 },
         { .reg = 0x00009888, .val = 0x04624000 },
         { .reg = 0x00009888, .val = 0x0E620026 },
         { .reg = 0x00009888, .val = 0x12620025 },
         { .reg = 0x00009888, .val = 0x00620000 },
         { .reg = 0x00009888, .val = 0x02620000 },
         { .reg = 0x00009888, .val = 0x00684000 },
         { .reg = 0x00009888, .val = 0x02680040 },
         { .reg = 0x00009888, .val = 0x04824000 },
         { .reg = 0x00009888, .val = 0x06824C00 },
         { .reg = 0x00009888, .val = 0x16820025 },
         { .reg = 0x00009888, .val = 0x00820000 },
         { .reg = 0x00009888, .val = 0x02820000 },
         { .reg = 0x00009888, .val = 0x00880001 },
         { .reg = 0x00009888, .val = 0x02884000 },
         { .reg = 0x00009888, .val = 0x04A24000 },
         { .reg = 0x00009888, .val = 0x08A20026 },
         { .reg = 0x00009888, .val = 0x14A20940 },
         { .reg = 0x00009888, .val = 0x00A20000 },
         { .reg = 0x00009888, .val = 0x02A20000 },
         { .reg = 0x00009888, .val = 0x00A80004 },
         { .reg = 0x00009888, .val = 0x02A81000 },
         { .reg = 0x00009888, .val = 0x04C24000 },
         { .reg = 0x00009888, .val = 0x08C20980 },
         { .reg = 0x00009888, .val = 0x14C20025 },
         { .reg = 0x00009888, .val = 0x00C20000 },
         { .reg = 0x00009888, .val = 0x02C20000 },
         { .reg = 0x00009888, .val = 0x00C80010 },
         { .reg = 0x00009888, .val = 0x02C80400 },
         { .reg = 0x00009888, .val = 0x04E24000 },
         { .reg = 0x00009888, .val = 0x0AE20026 },
         { .reg = 0x00009888, .val = 0x12E20940 },
         { .reg = 0x00009888, .val = 0x00E20000 },
         { .reg = 0x00009888, .val = 0x02E20000 },
         { .reg = 0x00009888, .val = 0x00E80040 },
         { .reg = 0x00009888, .val = 0x02E80100 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00013500 },
         { .reg = 0x00009888, .val = 0x02010035 },
         { .reg = 0x00009888, .val = 0x00040500 },
         { .reg = 0x00009888, .val = 0x02040005 },
         { .reg = 0x00009888, .val = 0x000B0330 },
         { .reg = 0x00009888, .val = 0x00090E00 },
         { .reg = 0x00009888, .val = 0x0209000E },
         { .reg = 0x00009888, .val = 0x000A2A00 },
         { .reg = 0x00009888, .val = 0x020A002A },
         { .reg = 0x00009888, .val = 0x00210035 },
         { .reg = 0x00009888, .val = 0x02215C00 },
         { .reg = 0x00009888, .val = 0x00240005 },
         { .reg = 0x00009888, .val = 0x02245000 },
         { .reg = 0x00009888, .val = 0x002BC003 },
         { .reg = 0x00009888, .val = 0x0029000E },
         { .reg = 0x00009888, .val = 0x0229B000 },
         { .reg = 0x00009888, .val = 0x002A002A },
         { .reg = 0x00009888, .val = 0x022AA800 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002EA00 },
         { .reg = 0x00009888, .val = 0x020200EA },
         { .reg = 0x00009888, .val = 0x008200EA },
         { .reg = 0x00009888, .val = 0x0282AB00 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005F00F },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AA55 },
         { .reg = 0x00009888, .val = 0x020355AA },
         { .reg = 0x00009888, .val = 0x0004F00F },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010A03 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010A02 },
         { .reg = 0x00009888, .val = 0x5E010070 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010050 },
         { .reg = 0x00009888, .val = 0x50010A07 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0xF0800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0xF0800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
         { .reg = 0x0000D940, .val = 0x0000000A },
         { .reg = 0x0000D944, .val = 0x00007FFE },
         { .reg = 0x0000D948, .val = 0x00000012 },
         { .reg = 0x0000D94C, .val = 0x0000BFFD },
         { .reg = 0x0000D950, .val = 0x00000022 },
         { .reg = 0x0000D954, .val = 0x0000DFFB },
         { .reg = 0x0000D958, .val = 0x00000042 },
         { .reg = 0x0000D95C, .val = 0x0000EFF7 },
         { .reg = 0x0000D960, .val = 0x00000082 },
         { .reg = 0x0000D964, .val = 0x0000FEEF },
         { .reg = 0x0000D968, .val = 0x00000102 },
         { .reg = 0x0000D96C, .val = 0x0000FDDF },
         { .reg = 0x0000D970, .val = 0x00000202 },
         { .reg = 0x0000D974, .val = 0x0000FBBF },
         { .reg = 0x0000D978, .val = 0x00000402 },
         { .reg = 0x0000D97C, .val = 0x0000F77F },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext503__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext503__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext503__avg_gpu_core_frequency__max,mtlgt3__ext503__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6262, 24, NULL,mtlgt3__ext503__icache_hit_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6263, 32, NULL,mtlgt3__ext503__icache_miss_bank3_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6264, 40, NULL,mtlgt3__ext503__icache_hit_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6265, 48, NULL,mtlgt3__ext503__icache_miss_bank3_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6266, 56, NULL,mtlgt3__ext503__icache_hit_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6267, 64, NULL,mtlgt3__ext503__icache_miss_bank3_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6268, 72, NULL,mtlgt3__ext503__icache_hit_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6269, 80, NULL,mtlgt3__ext503__icache_miss_bank3_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7035, 88, NULL,mtlgt3__ext503__icache_hit_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7036, 96, NULL,mtlgt3__ext503__icache_miss_bank3_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7037, 104, NULL,mtlgt3__ext503__icache_hit_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7038, 112, NULL,mtlgt3__ext503__icache_miss_bank3_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7039, 120, NULL,mtlgt3__ext503__icache_hit_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7040, 128, NULL,mtlgt3__ext503__icache_miss_bank3_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7041, 136, NULL,mtlgt3__ext503__icache_hit_bank3_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7042, 144, NULL,mtlgt3__ext503__icache_miss_bank3_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext508_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext508";
   query->symbol_name = "Ext508";
   query->guid = "2bc8b90d-997c-4d62-b101-fe1aa74036e5";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x180802B4 },
         { .reg = 0x00009888, .val = 0x182802B4 },
         { .reg = 0x00009888, .val = 0x04080010 },
         { .reg = 0x00009888, .val = 0x0A080247 },
         { .reg = 0x00009888, .val = 0x0C0802CA },
         { .reg = 0x00009888, .val = 0x0E08034C },
         { .reg = 0x00009888, .val = 0x1008000E },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x04280010 },
         { .reg = 0x00009888, .val = 0x102801C0 },
         { .reg = 0x00009888, .val = 0x12280289 },
         { .reg = 0x00009888, .val = 0x1428030B },
         { .reg = 0x00009888, .val = 0x1628038D },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFC },
         { .reg = 0x00009888, .val = 0x0009AAA0 },
         { .reg = 0x00009888, .val = 0x0209FFFE },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAA0 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAA0 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext508__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext508__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext508__avg_gpu_core_frequency__max,mtlgt3__ext508__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6270, 24, NULL,mtlgt3__ext508__slm_byte_read_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6271, 32, NULL,mtlgt3__ext508__slm_byte_read_bank0_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext509_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext509";
   query->symbol_name = "Ext509";
   query->guid = "79252877-1dcd-4700-b4bd-58bce74b796d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C085400 },
         { .reg = 0x00009888, .val = 0x1C285400 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x10080000 },
         { .reg = 0x00009888, .val = 0x12080081 },
         { .reg = 0x00009888, .val = 0x14080103 },
         { .reg = 0x00009888, .val = 0x16080185 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009888, .val = 0x04280008 },
         { .reg = 0x00009888, .val = 0x0A280040 },
         { .reg = 0x00009888, .val = 0x0C2800C2 },
         { .reg = 0x00009888, .val = 0x0E280144 },
         { .reg = 0x00009888, .val = 0x10280006 },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFC },
         { .reg = 0x00009888, .val = 0x0009FFF0 },
         { .reg = 0x00009888, .val = 0x0209AAAB },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAA0 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAA0 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext509__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext509__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext509__avg_gpu_core_frequency__max,mtlgt3__ext509__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6272, 24, NULL,mtlgt3__ext509__slm_byte_read_bank1_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6273, 32, NULL,mtlgt3__ext509__slm_byte_read_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext510_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext510";
   query->symbol_name = "Ext510";
   query->guid = "68ac1770-b062-48cd-94f4-44c6ae16867a";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x184802B4 },
         { .reg = 0x00009888, .val = 0x18680295 },
         { .reg = 0x00009888, .val = 0x04480010 },
         { .reg = 0x00009888, .val = 0x0A480007 },
         { .reg = 0x00009888, .val = 0x1248034E },
         { .reg = 0x00009888, .val = 0x144802CC },
         { .reg = 0x00009888, .val = 0x1648024A },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x04680010 },
         { .reg = 0x00009888, .val = 0x0A680180 },
         { .reg = 0x00009888, .val = 0x0C680105 },
         { .reg = 0x00009888, .val = 0x0E680083 },
         { .reg = 0x00009888, .val = 0x106803C1 },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00010030 },
         { .reg = 0x00009888, .val = 0x0201FFF0 },
         { .reg = 0x00009888, .val = 0x000A0020 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x0202AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAA0 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010400 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext510__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext510__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext510__avg_gpu_core_frequency__max,mtlgt3__ext510__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6274, 24, NULL,mtlgt3__ext510__slm_byte_read_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6275, 32, NULL,mtlgt3__ext510__slm_byte_read_bank0_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext511_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext511";
   query->symbol_name = "Ext511";
   query->guid = "443b8a84-7e77-4e9f-8a2a-56743897cba3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C485400 },
         { .reg = 0x00009888, .val = 0x1C685400 },
         { .reg = 0x00009888, .val = 0x04480008 },
         { .reg = 0x00009888, .val = 0x0A480000 },
         { .reg = 0x00009888, .val = 0x12480146 },
         { .reg = 0x00009888, .val = 0x144800C4 },
         { .reg = 0x00009888, .val = 0x16480042 },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009888, .val = 0x04680008 },
         { .reg = 0x00009888, .val = 0x0A680180 },
         { .reg = 0x00009888, .val = 0x0C680105 },
         { .reg = 0x00009888, .val = 0x0E680083 },
         { .reg = 0x00009888, .val = 0x10680001 },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00010030 },
         { .reg = 0x00009888, .val = 0x0201FFF0 },
         { .reg = 0x00009888, .val = 0x000A0020 },
         { .reg = 0x00009888, .val = 0x020AAAA0 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFE0 },
         { .reg = 0x00009888, .val = 0x0202AAAF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAA0 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010400 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010402 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext511__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext511__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext511__avg_gpu_core_frequency__max,mtlgt3__ext511__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6276, 24, NULL,mtlgt3__ext511__slm_byte_read_bank1_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6277, 32, NULL,mtlgt3__ext511__slm_byte_read_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext512_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext512";
   query->symbol_name = "Ext512";
   query->guid = "68581669-8e57-4ff9-bb70-71a99f8454c8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18880295 },
         { .reg = 0x00009888, .val = 0x18A80295 },
         { .reg = 0x00009888, .val = 0x04880010 },
         { .reg = 0x00009888, .val = 0x10880180 },
         { .reg = 0x00009888, .val = 0x12880105 },
         { .reg = 0x00009888, .val = 0x14880083 },
         { .reg = 0x00009888, .val = 0x168803C1 },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009888, .val = 0x04A80010 },
         { .reg = 0x00009888, .val = 0x0AA80146 },
         { .reg = 0x00009888, .val = 0x0CA800C4 },
         { .reg = 0x00009888, .val = 0x0EA80042 },
         { .reg = 0x00009888, .val = 0x10A8000F },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215550 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245550 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFC },
         { .reg = 0x00009888, .val = 0x0029FFF0 },
         { .reg = 0x00009888, .val = 0x0229AAAB },
         { .reg = 0x00009888, .val = 0x002AAAA0 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAA0 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFC },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035550 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFC },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext512__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext512__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext512__avg_gpu_core_frequency__max,mtlgt3__ext512__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7043, 24, NULL,mtlgt3__ext512__slm_byte_read_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7044, 32, NULL,mtlgt3__ext512__slm_byte_read_bank0_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext513_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext513";
   query->symbol_name = "Ext513";
   query->guid = "1b49d31f-4d7c-4dd7-ad31-030ccb59649e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1C885400 },
         { .reg = 0x00009888, .val = 0x1CA85400 },
         { .reg = 0x00009888, .val = 0x04880008 },
         { .reg = 0x00009888, .val = 0x10880180 },
         { .reg = 0x00009888, .val = 0x12880105 },
         { .reg = 0x00009888, .val = 0x14880083 },
         { .reg = 0x00009888, .val = 0x16880001 },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009888, .val = 0x04A80008 },
         { .reg = 0x00009888, .val = 0x0AA80146 },
         { .reg = 0x00009888, .val = 0x0CA800C4 },
         { .reg = 0x00009888, .val = 0x0EA80042 },
         { .reg = 0x00009888, .val = 0x10A80000 },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215550 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245550 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFC },
         { .reg = 0x00009888, .val = 0x0029FFF0 },
         { .reg = 0x00009888, .val = 0x0229AAAB },
         { .reg = 0x00009888, .val = 0x002AAAA0 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAA0 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFC },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035550 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFC },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext513__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext513__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext513__avg_gpu_core_frequency__max,mtlgt3__ext513__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7045, 24, NULL,mtlgt3__ext513__slm_byte_read_bank1_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7046, 32, NULL,mtlgt3__ext513__slm_byte_read_bank1_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext514_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext514";
   query->symbol_name = "Ext514";
   query->guid = "1b0ce68b-c301-4d05-8659-85fad0825057";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18C80295 },
         { .reg = 0x00009888, .val = 0x18E80295 },
         { .reg = 0x00009888, .val = 0x04C80010 },
         { .reg = 0x00009888, .val = 0x10C80180 },
         { .reg = 0x00009888, .val = 0x12C80105 },
         { .reg = 0x00009888, .val = 0x14C80083 },
         { .reg = 0x00009888, .val = 0x16C803C1 },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x04E80010 },
         { .reg = 0x00009888, .val = 0x0AE80146 },
         { .reg = 0x00009888, .val = 0x0CE800C4 },
         { .reg = 0x00009888, .val = 0x0EE80042 },
         { .reg = 0x00009888, .val = 0x10E8000F },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0221FFFC },
         { .reg = 0x00009888, .val = 0x022AAAA8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FFF0 },
         { .reg = 0x00009888, .val = 0x0282AAAB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFC },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035550 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFC },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010002 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext514__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext514__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext514__avg_gpu_core_frequency__max,mtlgt3__ext514__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7047, 24, NULL,mtlgt3__ext514__slm_byte_read_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7048, 32, NULL,mtlgt3__ext514__slm_byte_read_bank0_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext515_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext515";
   query->symbol_name = "Ext515";
   query->guid = "fde32e67-1a87-4946-bf96-c1ff68105749";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x1CC85400 },
         { .reg = 0x00009888, .val = 0x1CE85400 },
         { .reg = 0x00009888, .val = 0x04C80008 },
         { .reg = 0x00009888, .val = 0x10C80180 },
         { .reg = 0x00009888, .val = 0x12C80105 },
         { .reg = 0x00009888, .val = 0x14C80083 },
         { .reg = 0x00009888, .val = 0x16C80001 },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009888, .val = 0x04E80008 },
         { .reg = 0x00009888, .val = 0x0AE80146 },
         { .reg = 0x00009888, .val = 0x0CE800C4 },
         { .reg = 0x00009888, .val = 0x0EE80042 },
         { .reg = 0x00009888, .val = 0x10E80000 },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0221FFFC },
         { .reg = 0x00009888, .val = 0x022AAAA8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FFF0 },
         { .reg = 0x00009888, .val = 0x0282AAAB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFC },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035550 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFC },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010402 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010402 },
         { .reg = 0x00009888, .val = 0x5E010020 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010002 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext515__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext515__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext515__avg_gpu_core_frequency__max,mtlgt3__ext515__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7049, 24, NULL,mtlgt3__ext515__slm_byte_read_bank1_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7050, 32, NULL,mtlgt3__ext515__slm_byte_read_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext516_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext516";
   query->symbol_name = "Ext516";
   query->guid = "bf950c5b-7250-47f4-aa59-d97b22db02ff";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18080004 },
         { .reg = 0x00009888, .val = 0x1C081000 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x08080081 },
         { .reg = 0x00009888, .val = 0x0A080103 },
         { .reg = 0x00009888, .val = 0x0C080185 },
         { .reg = 0x00009888, .val = 0x0E080247 },
         { .reg = 0x00009888, .val = 0x100802CA },
         { .reg = 0x00009888, .val = 0x1208034C },
         { .reg = 0x00009888, .val = 0x140803CE },
         { .reg = 0x00009888, .val = 0x16080200 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009AAAA },
         { .reg = 0x00009888, .val = 0x0209AAAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext516__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext516__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext516__avg_gpu_core_frequency__max,mtlgt3__ext516__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6278, 24, NULL,mtlgt3__ext516__load_store_cache_byte_read_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6279, 32, NULL,mtlgt3__ext516__load_store_cache_byte_read_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext517_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext517";
   query->symbol_name = "Ext517";
   query->guid = "9027ff05-4348-4061-a434-0befaba7c379";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18080005 },
         { .reg = 0x00009888, .val = 0x1C081400 },
         { .reg = 0x00009888, .val = 0x04080008 },
         { .reg = 0x00009888, .val = 0x080803C0 },
         { .reg = 0x00009888, .val = 0x0A08034E },
         { .reg = 0x00009888, .val = 0x0C0802CC },
         { .reg = 0x00009888, .val = 0x0E08024A },
         { .reg = 0x00009888, .val = 0x100801C8 },
         { .reg = 0x00009888, .val = 0x12080146 },
         { .reg = 0x00009888, .val = 0x140800C4 },
         { .reg = 0x00009888, .val = 0x16080042 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009AAAA },
         { .reg = 0x00009888, .val = 0x0209AAAA },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext517__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext517__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext517__avg_gpu_core_frequency__max,mtlgt3__ext517__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6280, 24, NULL,mtlgt3__ext517__load_store_cache_byte_write_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6281, 32, NULL,mtlgt3__ext517__load_store_cache_byte_write_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext518_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext518";
   query->symbol_name = "Ext518";
   query->guid = "6ad0dee9-17bf-4b54-8b70-e30afcc8710b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18280004 },
         { .reg = 0x00009888, .val = 0x1C281000 },
         { .reg = 0x00009888, .val = 0x04280008 },
         { .reg = 0x00009888, .val = 0x08280081 },
         { .reg = 0x00009888, .val = 0x0A280103 },
         { .reg = 0x00009888, .val = 0x0C280185 },
         { .reg = 0x00009888, .val = 0x0E280247 },
         { .reg = 0x00009888, .val = 0x102802CA },
         { .reg = 0x00009888, .val = 0x1228034C },
         { .reg = 0x00009888, .val = 0x142803CE },
         { .reg = 0x00009888, .val = 0x16280200 },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x0209FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext518__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext518__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext518__avg_gpu_core_frequency__max,mtlgt3__ext518__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6282, 24, NULL,mtlgt3__ext518__load_store_cache_byte_read_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6283, 32, NULL,mtlgt3__ext518__load_store_cache_byte_read_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext519_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext519";
   query->symbol_name = "Ext519";
   query->guid = "2c2ecec8-7f33-475c-9ca4-a7e89f949f58";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18280005 },
         { .reg = 0x00009888, .val = 0x1C281400 },
         { .reg = 0x00009888, .val = 0x04280080 },
         { .reg = 0x00009888, .val = 0x08280187 },
         { .reg = 0x00009888, .val = 0x0A280105 },
         { .reg = 0x00009888, .val = 0x0C280083 },
         { .reg = 0x00009888, .val = 0x0E280001 },
         { .reg = 0x00009888, .val = 0x1028038F },
         { .reg = 0x00009888, .val = 0x1228030D },
         { .reg = 0x00009888, .val = 0x1428028B },
         { .reg = 0x00009888, .val = 0x16280209 },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045555 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFF },
         { .reg = 0x00009888, .val = 0x0009FFFF },
         { .reg = 0x00009888, .val = 0x0209FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext519__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext519__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext519__avg_gpu_core_frequency__max,mtlgt3__ext519__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6284, 24, NULL,mtlgt3__ext519__load_store_cache_byte_write_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6285, 32, NULL,mtlgt3__ext519__load_store_cache_byte_write_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext520_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext520";
   query->symbol_name = "Ext520";
   query->guid = "d866e2a8-310e-4691-9edc-f7263b8d5c07";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18480004 },
         { .reg = 0x00009888, .val = 0x1C481000 },
         { .reg = 0x00009888, .val = 0x04480008 },
         { .reg = 0x00009888, .val = 0x08480081 },
         { .reg = 0x00009888, .val = 0x0A480103 },
         { .reg = 0x00009888, .val = 0x0C480185 },
         { .reg = 0x00009888, .val = 0x0E480247 },
         { .reg = 0x00009888, .val = 0x104802CA },
         { .reg = 0x00009888, .val = 0x1248034C },
         { .reg = 0x00009888, .val = 0x144803CE },
         { .reg = 0x00009888, .val = 0x16480200 },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext520__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext520__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext520__avg_gpu_core_frequency__max,mtlgt3__ext520__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6286, 24, NULL,mtlgt3__ext520__load_store_cache_byte_read_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6287, 32, NULL,mtlgt3__ext520__load_store_cache_byte_read_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext521_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext521";
   query->symbol_name = "Ext521";
   query->guid = "e5a95c15-d54f-4d4f-bbe2-533240392df3";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18480005 },
         { .reg = 0x00009888, .val = 0x1C481400 },
         { .reg = 0x00009888, .val = 0x04480080 },
         { .reg = 0x00009888, .val = 0x08480187 },
         { .reg = 0x00009888, .val = 0x0A480105 },
         { .reg = 0x00009888, .val = 0x0C480083 },
         { .reg = 0x00009888, .val = 0x0E480001 },
         { .reg = 0x00009888, .val = 0x1048038F },
         { .reg = 0x00009888, .val = 0x1248030D },
         { .reg = 0x00009888, .val = 0x1448028B },
         { .reg = 0x00009888, .val = 0x16480209 },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FFFF },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x000AAAAA },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAAA },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext521__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext521__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext521__avg_gpu_core_frequency__max,mtlgt3__ext521__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6288, 24, NULL,mtlgt3__ext521__load_store_cache_byte_write_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6289, 32, NULL,mtlgt3__ext521__load_store_cache_byte_write_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext522_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext522";
   query->symbol_name = "Ext522";
   query->guid = "bba76095-18aa-447d-9a79-00461a06f233";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18680004 },
         { .reg = 0x00009888, .val = 0x1C681000 },
         { .reg = 0x00009888, .val = 0x04680008 },
         { .reg = 0x00009888, .val = 0x08680081 },
         { .reg = 0x00009888, .val = 0x0A680103 },
         { .reg = 0x00009888, .val = 0x0C680185 },
         { .reg = 0x00009888, .val = 0x0E680247 },
         { .reg = 0x00009888, .val = 0x106802CA },
         { .reg = 0x00009888, .val = 0x1268034C },
         { .reg = 0x00009888, .val = 0x146803CE },
         { .reg = 0x00009888, .val = 0x16680200 },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext522__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext522__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext522__avg_gpu_core_frequency__max,mtlgt3__ext522__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6290, 24, NULL,mtlgt3__ext522__load_store_cache_byte_read_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6291, 32, NULL,mtlgt3__ext522__load_store_cache_byte_read_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext523_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext523";
   query->symbol_name = "Ext523";
   query->guid = "724a5073-2463-4f7f-aecb-7cdd90c831e1";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18680005 },
         { .reg = 0x00009888, .val = 0x1C681400 },
         { .reg = 0x00009888, .val = 0x04680080 },
         { .reg = 0x00009888, .val = 0x08680187 },
         { .reg = 0x00009888, .val = 0x0A680105 },
         { .reg = 0x00009888, .val = 0x0C680083 },
         { .reg = 0x00009888, .val = 0x0E680001 },
         { .reg = 0x00009888, .val = 0x1068038F },
         { .reg = 0x00009888, .val = 0x1268030D },
         { .reg = 0x00009888, .val = 0x1468028B },
         { .reg = 0x00009888, .val = 0x16680209 },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext523__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext523__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext523__avg_gpu_core_frequency__max,mtlgt3__ext523__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6292, 24, NULL,mtlgt3__ext523__load_store_cache_byte_write_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6293, 32, NULL,mtlgt3__ext523__load_store_cache_byte_write_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext524_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext524";
   query->symbol_name = "Ext524";
   query->guid = "3b94a07f-e4d8-4cf2-969e-ea19bb253a8c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18880004 },
         { .reg = 0x00009888, .val = 0x1C881000 },
         { .reg = 0x00009888, .val = 0x04880008 },
         { .reg = 0x00009888, .val = 0x08880187 },
         { .reg = 0x00009888, .val = 0x0A880105 },
         { .reg = 0x00009888, .val = 0x0C880083 },
         { .reg = 0x00009888, .val = 0x0E880001 },
         { .reg = 0x00009888, .val = 0x1088038F },
         { .reg = 0x00009888, .val = 0x1288030D },
         { .reg = 0x00009888, .val = 0x1488028B },
         { .reg = 0x00009888, .val = 0x16880209 },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029AAAA },
         { .reg = 0x00009888, .val = 0x0229AAAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext524__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext524__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext524__avg_gpu_core_frequency__max,mtlgt3__ext524__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7051, 24, NULL,mtlgt3__ext524__load_store_cache_byte_read_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7052, 32, NULL,mtlgt3__ext524__load_store_cache_byte_read_bank1_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext525_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext525";
   query->symbol_name = "Ext525";
   query->guid = "f4399df4-e808-4a0a-85ff-0c66f9c9e8a4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18880005 },
         { .reg = 0x00009888, .val = 0x1C881400 },
         { .reg = 0x00009888, .val = 0x04880008 },
         { .reg = 0x00009888, .val = 0x08880187 },
         { .reg = 0x00009888, .val = 0x0A880105 },
         { .reg = 0x00009888, .val = 0x0C880083 },
         { .reg = 0x00009888, .val = 0x0E880001 },
         { .reg = 0x00009888, .val = 0x1088038F },
         { .reg = 0x00009888, .val = 0x1288030D },
         { .reg = 0x00009888, .val = 0x1488028B },
         { .reg = 0x00009888, .val = 0x16880209 },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029AAAA },
         { .reg = 0x00009888, .val = 0x0229AAAA },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext525__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext525__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext525__avg_gpu_core_frequency__max,mtlgt3__ext525__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7053, 24, NULL,mtlgt3__ext525__load_store_cache_byte_write_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7054, 32, NULL,mtlgt3__ext525__load_store_cache_byte_write_bank1_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext526_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext526";
   query->symbol_name = "Ext526";
   query->guid = "f588aa78-c29a-4187-9818-480b12d5b076";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18A80004 },
         { .reg = 0x00009888, .val = 0x1CA81000 },
         { .reg = 0x00009888, .val = 0x04A80008 },
         { .reg = 0x00009888, .val = 0x08A80187 },
         { .reg = 0x00009888, .val = 0x0AA80105 },
         { .reg = 0x00009888, .val = 0x0CA80083 },
         { .reg = 0x00009888, .val = 0x0EA80001 },
         { .reg = 0x00009888, .val = 0x10A8038F },
         { .reg = 0x00009888, .val = 0x12A8030D },
         { .reg = 0x00009888, .val = 0x14A8028B },
         { .reg = 0x00009888, .val = 0x16A80209 },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029FFFF },
         { .reg = 0x00009888, .val = 0x0229FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext526__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext526__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext526__avg_gpu_core_frequency__max,mtlgt3__ext526__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7055, 24, NULL,mtlgt3__ext526__load_store_cache_byte_read_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7056, 32, NULL,mtlgt3__ext526__load_store_cache_byte_read_bank1_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext527_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext527";
   query->symbol_name = "Ext527";
   query->guid = "c0a38cc9-f0e9-40f5-9c1e-a4d7eba30825";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18A80005 },
         { .reg = 0x00009888, .val = 0x1CA81400 },
         { .reg = 0x00009888, .val = 0x04A80008 },
         { .reg = 0x00009888, .val = 0x08A80187 },
         { .reg = 0x00009888, .val = 0x0AA80105 },
         { .reg = 0x00009888, .val = 0x0CA80083 },
         { .reg = 0x00009888, .val = 0x0EA80001 },
         { .reg = 0x00009888, .val = 0x10A8038F },
         { .reg = 0x00009888, .val = 0x12A8030D },
         { .reg = 0x00009888, .val = 0x14A8028B },
         { .reg = 0x00009888, .val = 0x16A80209 },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215555 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245555 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFF },
         { .reg = 0x00009888, .val = 0x0029FFFF },
         { .reg = 0x00009888, .val = 0x0229FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext527__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext527__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext527__avg_gpu_core_frequency__max,mtlgt3__ext527__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7057, 24, NULL,mtlgt3__ext527__load_store_cache_byte_write_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7058, 32, NULL,mtlgt3__ext527__load_store_cache_byte_write_bank1_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext528_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext528";
   query->symbol_name = "Ext528";
   query->guid = "1cb1d3ff-ff5d-4c9b-84c9-89b9d235be36";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18C80004 },
         { .reg = 0x00009888, .val = 0x1CC81000 },
         { .reg = 0x00009888, .val = 0x04C80008 },
         { .reg = 0x00009888, .val = 0x08C80187 },
         { .reg = 0x00009888, .val = 0x0AC80105 },
         { .reg = 0x00009888, .val = 0x0CC80083 },
         { .reg = 0x00009888, .val = 0x0EC80001 },
         { .reg = 0x00009888, .val = 0x10C8038F },
         { .reg = 0x00009888, .val = 0x12C8030D },
         { .reg = 0x00009888, .val = 0x14C8028B },
         { .reg = 0x00009888, .val = 0x16C80209 },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021FFFF },
         { .reg = 0x00009888, .val = 0x0221FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext528__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext528__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext528__avg_gpu_core_frequency__max,mtlgt3__ext528__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7059, 24, NULL,mtlgt3__ext528__load_store_cache_byte_read_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7060, 32, NULL,mtlgt3__ext528__load_store_cache_byte_read_bank1_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext529_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext529";
   query->symbol_name = "Ext529";
   query->guid = "4491913e-99ed-4420-9575-75ab7a82c45d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18C80005 },
         { .reg = 0x00009888, .val = 0x1CC81400 },
         { .reg = 0x00009888, .val = 0x04C80008 },
         { .reg = 0x00009888, .val = 0x08C80187 },
         { .reg = 0x00009888, .val = 0x0AC80105 },
         { .reg = 0x00009888, .val = 0x0CC80083 },
         { .reg = 0x00009888, .val = 0x0EC80001 },
         { .reg = 0x00009888, .val = 0x10C8038F },
         { .reg = 0x00009888, .val = 0x12C8030D },
         { .reg = 0x00009888, .val = 0x14C8028B },
         { .reg = 0x00009888, .val = 0x16C80209 },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021FFFF },
         { .reg = 0x00009888, .val = 0x0221FFFF },
         { .reg = 0x00009888, .val = 0x002AAAAA },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAAA },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext529__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext529__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext529__avg_gpu_core_frequency__max,mtlgt3__ext529__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7061, 24, NULL,mtlgt3__ext529__load_store_cache_byte_write_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7062, 32, NULL,mtlgt3__ext529__load_store_cache_byte_write_bank1_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext530_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext530";
   query->symbol_name = "Ext530";
   query->guid = "4fe2fe09-1ef2-45ff-87f5-e789f8405713";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18E80004 },
         { .reg = 0x00009888, .val = 0x1CE81000 },
         { .reg = 0x00009888, .val = 0x04E80008 },
         { .reg = 0x00009888, .val = 0x08E80187 },
         { .reg = 0x00009888, .val = 0x0AE80105 },
         { .reg = 0x00009888, .val = 0x0CE80083 },
         { .reg = 0x00009888, .val = 0x0EE80001 },
         { .reg = 0x00009888, .val = 0x10E8038F },
         { .reg = 0x00009888, .val = 0x12E8030D },
         { .reg = 0x00009888, .val = 0x14E8028B },
         { .reg = 0x00009888, .val = 0x16E80209 },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FFFF },
         { .reg = 0x00009888, .val = 0x0282FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext530__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext530__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext530__avg_gpu_core_frequency__max,mtlgt3__ext530__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7063, 24, NULL,mtlgt3__ext530__load_store_cache_byte_read_bank0_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7064, 32, NULL,mtlgt3__ext530__load_store_cache_byte_read_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext531_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext531";
   query->symbol_name = "Ext531";
   query->guid = "856f213d-954d-4b0a-be6c-307b41d39b18";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18E80005 },
         { .reg = 0x00009888, .val = 0x1CE81400 },
         { .reg = 0x00009888, .val = 0x04E80008 },
         { .reg = 0x00009888, .val = 0x08E80187 },
         { .reg = 0x00009888, .val = 0x0AE80105 },
         { .reg = 0x00009888, .val = 0x0CE80083 },
         { .reg = 0x00009888, .val = 0x0EE80001 },
         { .reg = 0x00009888, .val = 0x10E8038F },
         { .reg = 0x00009888, .val = 0x12E8030D },
         { .reg = 0x00009888, .val = 0x14E8028B },
         { .reg = 0x00009888, .val = 0x16E80209 },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FFFF },
         { .reg = 0x00009888, .val = 0x0282FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFF },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035555 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFF },
         { .reg = 0x00009888, .val = 0x4C010000 },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext531__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext531__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext531__avg_gpu_core_frequency__max,mtlgt3__ext531__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7065, 24, NULL,mtlgt3__ext531__load_store_cache_byte_write_bank0_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7066, 32, NULL,mtlgt3__ext531__load_store_cache_byte_write_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext540_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext540";
   query->symbol_name = "Ext540";
   query->guid = "03eb9c9b-72ee-4c7b-930b-6211dbb60503";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18080014 },
         { .reg = 0x00009888, .val = 0x1C085000 },
         { .reg = 0x00009888, .val = 0x04080080 },
         { .reg = 0x00009888, .val = 0x0A080146 },
         { .reg = 0x00009888, .val = 0x0C0800C4 },
         { .reg = 0x00009888, .val = 0x0E080042 },
         { .reg = 0x00009888, .val = 0x10080380 },
         { .reg = 0x00009888, .val = 0x1208030D },
         { .reg = 0x00009888, .val = 0x1408028B },
         { .reg = 0x00009888, .val = 0x16080209 },
         { .reg = 0x00009888, .val = 0x06080000 },
         { .reg = 0x00009888, .val = 0x00080000 },
         { .reg = 0x00009888, .val = 0x02080000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFC },
         { .reg = 0x00009888, .val = 0x0009AAA0 },
         { .reg = 0x00009888, .val = 0x0209AAAA },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAA0 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAA0 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext540__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext540__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext540__avg_gpu_core_frequency__max,mtlgt3__ext540__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6294, 24, NULL,mtlgt3__ext540__slm_byte_write_bank0_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_uint64(query, 6295, 32, NULL,mtlgt3__ext540__slm_byte_write_bank1_xecore0__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext541_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext541";
   query->symbol_name = "Ext541";
   query->guid = "e3bef1e9-f563-4927-9ce8-1be6e151448c";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18280014 },
         { .reg = 0x00009888, .val = 0x1C285000 },
         { .reg = 0x00009888, .val = 0x04280080 },
         { .reg = 0x00009888, .val = 0x0A280146 },
         { .reg = 0x00009888, .val = 0x0C2800C4 },
         { .reg = 0x00009888, .val = 0x0E280042 },
         { .reg = 0x00009888, .val = 0x10280380 },
         { .reg = 0x00009888, .val = 0x1228030D },
         { .reg = 0x00009888, .val = 0x1428028B },
         { .reg = 0x00009888, .val = 0x16280209 },
         { .reg = 0x00009888, .val = 0x06280000 },
         { .reg = 0x00009888, .val = 0x00280000 },
         { .reg = 0x00009888, .val = 0x02280000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00045550 },
         { .reg = 0x00009888, .val = 0x02045555 },
         { .reg = 0x00009888, .val = 0x000BFFFC },
         { .reg = 0x00009888, .val = 0x0009FFF0 },
         { .reg = 0x00009888, .val = 0x0209FFFF },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAA0 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAA0 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext541__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext541__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext541__avg_gpu_core_frequency__max,mtlgt3__ext541__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6296, 24, NULL,mtlgt3__ext541__slm_byte_write_bank0_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_uint64(query, 6297, 32, NULL,mtlgt3__ext541__slm_byte_write_bank1_xecore1__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext542_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext542";
   query->symbol_name = "Ext542";
   query->guid = "de587fdf-1740-4816-a5c0-08c1cb6b43eb";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18480014 },
         { .reg = 0x00009888, .val = 0x1C485000 },
         { .reg = 0x00009888, .val = 0x04480080 },
         { .reg = 0x00009888, .val = 0x0A480146 },
         { .reg = 0x00009888, .val = 0x0C4800C4 },
         { .reg = 0x00009888, .val = 0x0E480042 },
         { .reg = 0x00009888, .val = 0x10480380 },
         { .reg = 0x00009888, .val = 0x1248030D },
         { .reg = 0x00009888, .val = 0x1448028B },
         { .reg = 0x00009888, .val = 0x16480209 },
         { .reg = 0x00009888, .val = 0x06480000 },
         { .reg = 0x00009888, .val = 0x00480000 },
         { .reg = 0x00009888, .val = 0x02480000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0001FFF0 },
         { .reg = 0x00009888, .val = 0x0201FFFF },
         { .reg = 0x00009888, .val = 0x000AAAA0 },
         { .reg = 0x00009888, .val = 0x020AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002AAA0 },
         { .reg = 0x00009888, .val = 0x0202AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAA0 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext542__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext542__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext542__avg_gpu_core_frequency__max,mtlgt3__ext542__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6298, 24, NULL,mtlgt3__ext542__slm_byte_write_bank0_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_uint64(query, 6299, 32, NULL,mtlgt3__ext542__slm_byte_write_bank1_xecore2__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext543_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext543";
   query->symbol_name = "Ext543";
   query->guid = "cea536f3-f7ef-449c-91fe-42c721e54b52";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18680014 },
         { .reg = 0x00009888, .val = 0x1C685000 },
         { .reg = 0x00009888, .val = 0x04680080 },
         { .reg = 0x00009888, .val = 0x0A680146 },
         { .reg = 0x00009888, .val = 0x0C6800C4 },
         { .reg = 0x00009888, .val = 0x0E680042 },
         { .reg = 0x00009888, .val = 0x10680380 },
         { .reg = 0x00009888, .val = 0x1268030D },
         { .reg = 0x00009888, .val = 0x1468028B },
         { .reg = 0x00009888, .val = 0x16680209 },
         { .reg = 0x00009888, .val = 0x06680000 },
         { .reg = 0x00009888, .val = 0x00680000 },
         { .reg = 0x00009888, .val = 0x02680000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002FFF0 },
         { .reg = 0x00009888, .val = 0x0202FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAA0 },
         { .reg = 0x00009888, .val = 0x0203AAAA },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext543__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext543__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext543__avg_gpu_core_frequency__max,mtlgt3__ext543__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6300, 24, NULL,mtlgt3__ext543__slm_byte_write_bank0_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_uint64(query, 6301, 32, NULL,mtlgt3__ext543__slm_byte_write_bank1_xecore3__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext544_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext544";
   query->symbol_name = "Ext544";
   query->guid = "c3586bbc-f20b-4ffc-bd62-21ea68c161f4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18880014 },
         { .reg = 0x00009888, .val = 0x1C885000 },
         { .reg = 0x00009888, .val = 0x04880008 },
         { .reg = 0x00009888, .val = 0x0A880146 },
         { .reg = 0x00009888, .val = 0x0C8800C4 },
         { .reg = 0x00009888, .val = 0x0E880042 },
         { .reg = 0x00009888, .val = 0x10880380 },
         { .reg = 0x00009888, .val = 0x1288030D },
         { .reg = 0x00009888, .val = 0x1488028B },
         { .reg = 0x00009888, .val = 0x16880209 },
         { .reg = 0x00009888, .val = 0x06880000 },
         { .reg = 0x00009888, .val = 0x00880000 },
         { .reg = 0x00009888, .val = 0x02880000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215550 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245550 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFC },
         { .reg = 0x00009888, .val = 0x0029AAA0 },
         { .reg = 0x00009888, .val = 0x0229AAAA },
         { .reg = 0x00009888, .val = 0x002AAAA0 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAA0 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFC },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035550 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFC },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext544__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext544__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext544__avg_gpu_core_frequency__max,mtlgt3__ext544__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7067, 24, NULL,mtlgt3__ext544__slm_byte_write_bank0_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_uint64(query, 7068, 32, NULL,mtlgt3__ext544__slm_byte_write_bank1_xecore4__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext545_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext545";
   query->symbol_name = "Ext545";
   query->guid = "f3d6345a-b760-4433-844e-e35204b44e09";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18A80014 },
         { .reg = 0x00009888, .val = 0x1CA85000 },
         { .reg = 0x00009888, .val = 0x04A80008 },
         { .reg = 0x00009888, .val = 0x0AA80146 },
         { .reg = 0x00009888, .val = 0x0CA800C4 },
         { .reg = 0x00009888, .val = 0x0EA80042 },
         { .reg = 0x00009888, .val = 0x10A80380 },
         { .reg = 0x00009888, .val = 0x12A8030D },
         { .reg = 0x00009888, .val = 0x14A8028B },
         { .reg = 0x00009888, .val = 0x16A80209 },
         { .reg = 0x00009888, .val = 0x06A80000 },
         { .reg = 0x00009888, .val = 0x00A80000 },
         { .reg = 0x00009888, .val = 0x02A80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00215550 },
         { .reg = 0x00009888, .val = 0x02215555 },
         { .reg = 0x00009888, .val = 0x00245550 },
         { .reg = 0x00009888, .val = 0x02245555 },
         { .reg = 0x00009888, .val = 0x002BFFFC },
         { .reg = 0x00009888, .val = 0x0029FFF0 },
         { .reg = 0x00009888, .val = 0x0229FFFF },
         { .reg = 0x00009888, .val = 0x002AAAA0 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAA0 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFC },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035550 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFC },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext545__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext545__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext545__avg_gpu_core_frequency__max,mtlgt3__ext545__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7069, 24, NULL,mtlgt3__ext545__slm_byte_write_bank0_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_uint64(query, 7070, 32, NULL,mtlgt3__ext545__slm_byte_write_bank1_xecore5__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext546_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext546";
   query->symbol_name = "Ext546";
   query->guid = "f5448b6d-cb2a-4aad-804e-b1a285299582";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18C80014 },
         { .reg = 0x00009888, .val = 0x1CC85000 },
         { .reg = 0x00009888, .val = 0x04C80008 },
         { .reg = 0x00009888, .val = 0x0AC80146 },
         { .reg = 0x00009888, .val = 0x0CC800C4 },
         { .reg = 0x00009888, .val = 0x0EC80042 },
         { .reg = 0x00009888, .val = 0x10C80380 },
         { .reg = 0x00009888, .val = 0x12C8030D },
         { .reg = 0x00009888, .val = 0x14C8028B },
         { .reg = 0x00009888, .val = 0x16C80209 },
         { .reg = 0x00009888, .val = 0x06C80000 },
         { .reg = 0x00009888, .val = 0x00C80000 },
         { .reg = 0x00009888, .val = 0x02C80000 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x0021FFF0 },
         { .reg = 0x00009888, .val = 0x0221FFFF },
         { .reg = 0x00009888, .val = 0x002AAAA0 },
         { .reg = 0x00009888, .val = 0x022AAAAA },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082AAA0 },
         { .reg = 0x00009888, .val = 0x0282AAAA },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFC },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035550 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFC },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext546__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext546__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext546__avg_gpu_core_frequency__max,mtlgt3__ext546__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7071, 24, NULL,mtlgt3__ext546__slm_byte_write_bank0_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_uint64(query, 7072, 32, NULL,mtlgt3__ext546__slm_byte_write_bank1_xecore6__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext547_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 5);

   query->name = "Ext547";
   query->symbol_name = "Ext547";
   query->guid = "7b8b6c53-abff-4570-b413-91cc843181d8";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x18E80014 },
         { .reg = 0x00009888, .val = 0x1CE85000 },
         { .reg = 0x00009888, .val = 0x04E80008 },
         { .reg = 0x00009888, .val = 0x0AE80146 },
         { .reg = 0x00009888, .val = 0x0CE800C4 },
         { .reg = 0x00009888, .val = 0x0EE80042 },
         { .reg = 0x00009888, .val = 0x10E80380 },
         { .reg = 0x00009888, .val = 0x12E8030D },
         { .reg = 0x00009888, .val = 0x14E8028B },
         { .reg = 0x00009888, .val = 0x16E80209 },
         { .reg = 0x00009888, .val = 0x06E80000 },
         { .reg = 0x00009888, .val = 0x00E80000 },
         { .reg = 0x00009888, .val = 0x02E80000 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0082FFF0 },
         { .reg = 0x00009888, .val = 0x0282FFFF },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FFFC },
         { .reg = 0x00009888, .val = 0x0002FFFC },
         { .reg = 0x00009888, .val = 0x00015550 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x00035550 },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FFFC },
         { .reg = 0x00009888, .val = 0x56010000 },
         { .reg = 0x00009888, .val = 0x58010000 },
         { .reg = 0x00009888, .val = 0x5A010000 },
         { .reg = 0x00009888, .val = 0x5C010000 },
         { .reg = 0x00009888, .val = 0x5E010000 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010000 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010000 },
         { .reg = 0x00009888, .val = 0x52010000 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext547__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext547__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext547__avg_gpu_core_frequency__max,mtlgt3__ext547__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7073, 24, NULL,mtlgt3__ext547__slm_byte_write_bank0_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_uint64(query, 7074, 32, NULL,mtlgt3__ext547__slm_byte_write_bank1_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext604_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext604";
   query->symbol_name = "Ext604";
   query->guid = "b83befed-d2db-4806-907c-3f952798e117";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog mux_regs[] = {
         { .reg = 0x00000D04, .val = 0x00000200 },
         { .reg = 0x00009884, .val = 0x0000000C },
         { .reg = 0x00009888, .val = 0x2C070000 },
         { .reg = 0x00009888, .val = 0x2C270000 },
         { .reg = 0x00009888, .val = 0x2C470000 },
         { .reg = 0x00009888, .val = 0x2C670000 },
         { .reg = 0x00009888, .val = 0x2C870000 },
         { .reg = 0x00009888, .val = 0x2CA70000 },
         { .reg = 0x00009888, .val = 0x2CC70000 },
         { .reg = 0x00009888, .val = 0x2CE70000 },
         { .reg = 0x00009888, .val = 0x0207000A },
         { .reg = 0x00009888, .val = 0x04070022 },
         { .reg = 0x00009888, .val = 0x08070023 },
         { .reg = 0x00009888, .val = 0x00080202 },
         { .reg = 0x00009888, .val = 0x0227000A },
         { .reg = 0x00009888, .val = 0x04270880 },
         { .reg = 0x00009888, .val = 0x082708C0 },
         { .reg = 0x00009888, .val = 0x00280808 },
         { .reg = 0x00009888, .val = 0x0247000A },
         { .reg = 0x00009888, .val = 0x06470022 },
         { .reg = 0x00009888, .val = 0x0A470023 },
         { .reg = 0x00009888, .val = 0x04470000 },
         { .reg = 0x00009888, .val = 0x00482020 },
         { .reg = 0x00009888, .val = 0x0267000A },
         { .reg = 0x00009888, .val = 0x06670880 },
         { .reg = 0x00009888, .val = 0x0A6708C0 },
         { .reg = 0x00009888, .val = 0x04670000 },
         { .reg = 0x00009888, .val = 0x00688080 },
         { .reg = 0x00009888, .val = 0x0287000A },
         { .reg = 0x00009888, .val = 0x0E8708C0 },
         { .reg = 0x00009888, .val = 0x12870880 },
         { .reg = 0x00009888, .val = 0x04870000 },
         { .reg = 0x00009888, .val = 0x02888080 },
         { .reg = 0x00009888, .val = 0x02A7000A },
         { .reg = 0x00009888, .val = 0x0EA70023 },
         { .reg = 0x00009888, .val = 0x12A70022 },
         { .reg = 0x00009888, .val = 0x04A70000 },
         { .reg = 0x00009888, .val = 0x02A82020 },
         { .reg = 0x00009888, .val = 0x02C7000A },
         { .reg = 0x00009888, .val = 0x0CC708C0 },
         { .reg = 0x00009888, .val = 0x10C70880 },
         { .reg = 0x00009888, .val = 0x04C70000 },
         { .reg = 0x00009888, .val = 0x02C80808 },
         { .reg = 0x00009888, .val = 0x02E7000A },
         { .reg = 0x00009888, .val = 0x0CE70023 },
         { .reg = 0x00009888, .val = 0x10E70022 },
         { .reg = 0x00009888, .val = 0x04E70000 },
         { .reg = 0x00009888, .val = 0x02E80202 },
         { .reg = 0x00009884, .val = 0x00000004 },
         { .reg = 0x00009888, .val = 0x00013535 },
         { .reg = 0x00009888, .val = 0x00040505 },
         { .reg = 0x00009888, .val = 0x000B0033 },
         { .reg = 0x00009888, .val = 0x00090E0E },
         { .reg = 0x00009888, .val = 0x000A2A2A },
         { .reg = 0x00009888, .val = 0x02215C5C },
         { .reg = 0x00009888, .val = 0x02245050 },
         { .reg = 0x00009888, .val = 0x002BCC00 },
         { .reg = 0x00009888, .val = 0x0229B0B0 },
         { .reg = 0x00009888, .val = 0x022AA8A8 },
         { .reg = 0x00009884, .val = 0x00000008 },
         { .reg = 0x00009888, .val = 0x0002EAEA },
         { .reg = 0x00009888, .val = 0x0282ABAB },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x0005FF00 },
         { .reg = 0x00009888, .val = 0x0002FFFF },
         { .reg = 0x00009888, .val = 0x00015555 },
         { .reg = 0x00009888, .val = 0x02015555 },
         { .reg = 0x00009888, .val = 0x0003AAAA },
         { .reg = 0x00009888, .val = 0x02035555 },
         { .reg = 0x00009888, .val = 0x0004FF00 },
         { .reg = 0x00009888, .val = 0x4C010400 },
         { .reg = 0x00009888, .val = 0x56010020 },
         { .reg = 0x00009888, .val = 0x58010E05 },
         { .reg = 0x00009888, .val = 0x5A010020 },
         { .reg = 0x00009888, .val = 0x5C010A02 },
         { .reg = 0x00009888, .val = 0x5E010070 },
         { .reg = 0x00009888, .val = 0x06010000 },
         { .reg = 0x00009888, .val = 0x60010605 },
         { .reg = 0x00009888, .val = 0x4E010000 },
         { .reg = 0x00009888, .val = 0x50010A00 },
         { .reg = 0x00009888, .val = 0x52010030 },
         { .reg = 0x00009888, .val = 0x54010000 },
         { .reg = 0x00009884, .val = 0x00000000 },
         { .reg = 0x00009888, .val = 0x72010002 },
      };
      query->config.mux_regs = mux_regs;
      query->config.n_mux_regs = ARRAY_SIZE(mux_regs);

      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext604__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext604__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext604__avg_gpu_core_frequency__max,mtlgt3__ext604__avg_gpu_core_frequency__read);

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6302, 24, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6303, 28, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6304, 32, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6305, 36, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 0)) {
         intel_perf_query_add_counter_float(query, 6306, 40, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore0__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 1)) {
         intel_perf_query_add_counter_float(query, 6307, 44, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore1__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 2)) {
         intel_perf_query_add_counter_float(query, 6308, 48, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore2__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 0, 3)) {
         intel_perf_query_add_counter_float(query, 6309, 52, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore3__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 7075, 56, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 7076, 60, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 7077, 64, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 7078, 68, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore7__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 0)) {
         intel_perf_query_add_counter_float(query, 7079, 72, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore4__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 1)) {
         intel_perf_query_add_counter_float(query, 7080, 76, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore5__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 2)) {
         intel_perf_query_add_counter_float(query, 7081, 80, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore6__read);
      }

      if (intel_device_info_subslice_available(&perf->devinfo, 1, 3)) {
         intel_perf_query_add_counter_float(query, 7082, 84, percentage_max_float,mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore7__read);
      }

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1000_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1000";
   query->symbol_name = "Ext1000";
   query->guid = "0d368afb-b8fd-425d-a704-9a45eaaaed3d";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00005004 },
         { .reg = 0x0000E558, .val = 0x00001000 },
         { .reg = 0x0000E658, .val = 0x00002009 },
         { .reg = 0x0000E758, .val = 0x01008001 },
         { .reg = 0x0000E45C, .val = 0x0000300A },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1000__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1000__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1000__avg_gpu_core_frequency__max,mtlgt3__ext1000__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6310, 24, percentage_max_float,mtlgt3__ext1000__xve_active__read);

      intel_perf_query_add_counter_float(query, 6311, 28, percentage_max_float,mtlgt3__ext1000__xve_stall__read);

      intel_perf_query_add_counter_float(query, 6312, 32, percentage_max_float,mtlgt3__ext1000__xve_threads_occupancy_all__read);

      intel_perf_query_add_counter_uint64(query, 6313, 40, mtlgt3__ext1000__xve_inst_executed_alu0_all__max,mtlgt3__ext1000__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 6314, 48, mtlgt3__ext1000__xve_inst_executed_alu1_all__max,mtlgt3__ext1000__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 6315, 56, mtlgt3__ext1000__xve_inst_executed_xmx_all__max,mtlgt3__ext1000__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 6316, 64, mtlgt3__ext1000__xve_inst_executed_send_all__max,mtlgt3__ext1000__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 6317, 72, mtlgt3__ext1000__xve_inst_executed_control_all__max,mtlgt3__ext1000__xve_inst_executed_control_all__read);

      intel_perf_query_add_counter_float(query, 6318, 80, percentage_max_float,mtlgt3__ext1000__xve_pipe_alu0_and_alu1_active__read);

      intel_perf_query_add_counter_float(query, 6319, 84, percentage_max_float,mtlgt3__ext1000__xve_pipe_alu0_and_xmx_active__read);

      intel_perf_query_add_counter_float(query, 6320, 88, percentage_max_float,mtlgt3__ext1000__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6321, 92, percentage_max_float,mtlgt3__ext1000__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6322, 96, percentage_max_float,mtlgt3__ext1000__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6323, 100, percentage_max_float,mtlgt3__ext1000__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6324, 104, percentage_max_float,mtlgt3__ext1000__xve_inst_executed_control_all_utilization__read);

      intel_perf_query_add_counter_uint64(query, 6325, 112, mtlgt3__ext1000__xve_active_cycles__max,mtlgt3__ext1000__xve_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6326, 120, mtlgt3__ext1000__xve_stall_cycles__max,mtlgt3__ext1000__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6327, 128, mtlgt3__ext1000__xve_threads_occupancy_cycles_all__max,mtlgt3__ext1000__xve_threads_occupancy_cycles_all__read);

      intel_perf_query_add_counter_uint64(query, 6328, 136, mtlgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max,mtlgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6329, 144, mtlgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max,mtlgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1001_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Ext1001";
   query->symbol_name = "Ext1001";
   query->guid = "08bee982-b34c-49c1-bf0c-93c1949ffbe7";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00020010 },
         { .reg = 0x0000E558, .val = 0x00050030 },
         { .reg = 0x0000E658, .val = 0x00090060 },
         { .reg = 0x0000E758, .val = 0x00031011 },
         { .reg = 0x0000E45C, .val = 0x00051021 },
         { .reg = 0x0000E55C, .val = 0x00091061 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1001__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1001__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1001__avg_gpu_core_frequency__max,mtlgt3__ext1001__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6330, 24, mtlgt3__ext1001__xve_inst_executed_alu0_vs__max,mtlgt3__ext1001__xve_inst_executed_alu0_vs__read);

      intel_perf_query_add_counter_uint64(query, 6331, 32, mtlgt3__ext1001__xve_inst_executed_alu0_hs__max,mtlgt3__ext1001__xve_inst_executed_alu0_hs__read);

      intel_perf_query_add_counter_uint64(query, 6332, 40, mtlgt3__ext1001__xve_inst_executed_alu0_ds__max,mtlgt3__ext1001__xve_inst_executed_alu0_ds__read);

      intel_perf_query_add_counter_uint64(query, 6333, 48, mtlgt3__ext1001__xve_inst_executed_alu0_ps__max,mtlgt3__ext1001__xve_inst_executed_alu0_ps__read);

      intel_perf_query_add_counter_uint64(query, 6334, 56, mtlgt3__ext1001__xve_inst_executed_alu0_cs__max,mtlgt3__ext1001__xve_inst_executed_alu0_cs__read);

      intel_perf_query_add_counter_uint64(query, 6335, 64, mtlgt3__ext1001__xve_inst_executed_alu0_async_cs__max,mtlgt3__ext1001__xve_inst_executed_alu0_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 6336, 72, mtlgt3__ext1001__xve_inst_executed_alu1_vs__max,mtlgt3__ext1001__xve_inst_executed_alu1_vs__read);

      intel_perf_query_add_counter_uint64(query, 6337, 80, mtlgt3__ext1001__xve_inst_executed_alu1_hs__max,mtlgt3__ext1001__xve_inst_executed_alu1_hs__read);

      intel_perf_query_add_counter_uint64(query, 6338, 88, mtlgt3__ext1001__xve_inst_executed_alu1_ds__max,mtlgt3__ext1001__xve_inst_executed_alu1_ds__read);

      intel_perf_query_add_counter_uint64(query, 6339, 96, mtlgt3__ext1001__xve_inst_executed_alu1_ps__max,mtlgt3__ext1001__xve_inst_executed_alu1_ps__read);

      intel_perf_query_add_counter_uint64(query, 6340, 104, mtlgt3__ext1001__xve_inst_executed_alu1_cs__max,mtlgt3__ext1001__xve_inst_executed_alu1_cs__read);

      intel_perf_query_add_counter_uint64(query, 6341, 112, mtlgt3__ext1001__xve_inst_executed_alu1_async_cs__max,mtlgt3__ext1001__xve_inst_executed_alu1_async_cs__read);

      intel_perf_query_add_counter_float(query, 6342, 120, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu0_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 6343, 124, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu0_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 6344, 128, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu0_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 6345, 132, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu0_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 6346, 136, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu0_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6347, 140, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu0_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6348, 144, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu1_vs_utilization__read);

      intel_perf_query_add_counter_float(query, 6349, 148, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu1_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 6350, 152, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu1_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 6351, 156, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu1_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 6352, 160, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu1_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6353, 164, percentage_max_float,mtlgt3__ext1001__xve_inst_executed_alu1_async_cs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1002_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 21);

   query->name = "Ext1002";
   query->symbol_name = "Ext1002";
   query->guid = "845617a9-5a17-4f1f-9a6f-61ff844065e4";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x000C10C0 },
         { .reg = 0x0000E558, .val = 0x000D00C2 },
         { .reg = 0x0000E658, .val = 0x000D20D1 },
         { .reg = 0x0000E758, .val = 0x000E10E0 },
         { .reg = 0x0000E45C, .val = 0x000000E2 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1002__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1002__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1002__avg_gpu_core_frequency__max,mtlgt3__ext1002__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6354, 24, percentage_max_float,mtlgt3__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 6355, 28, percentage_max_float,mtlgt3__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 6356, 32, percentage_max_float,mtlgt3__ext1002__xve_inst_executed_send_rt_ahs_utilization__read);

      intel_perf_query_add_counter_float(query, 6357, 36, percentage_max_float,mtlgt3__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 6358, 40, percentage_max_float,mtlgt3__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 6359, 44, percentage_max_float,mtlgt3__ext1002__xve_inst_executed_send_rt_chs_utilization__read);

      intel_perf_query_add_counter_float(query, 6360, 48, percentage_max_float,mtlgt3__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6361, 52, percentage_max_float,mtlgt3__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6362, 56, percentage_max_float,mtlgt3__ext1002__xve_inst_executed_send_rt_ms_utilization__read);

      intel_perf_query_add_counter_uint64(query, 6363, 64, mtlgt3__ext1002__xve_inst_executed_alu0_rt_ahs__max,mtlgt3__ext1002__xve_inst_executed_alu0_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 6364, 72, mtlgt3__ext1002__xve_inst_executed_alu1_rt_ahs__max,mtlgt3__ext1002__xve_inst_executed_alu1_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 6365, 80, mtlgt3__ext1002__xve_inst_executed_send_rt_ahs__max,mtlgt3__ext1002__xve_inst_executed_send_rt_ahs__read);

      intel_perf_query_add_counter_uint64(query, 6366, 88, mtlgt3__ext1002__xve_inst_executed_alu0_rt_chs__max,mtlgt3__ext1002__xve_inst_executed_alu0_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 6367, 96, mtlgt3__ext1002__xve_inst_executed_alu1_rt_chs__max,mtlgt3__ext1002__xve_inst_executed_alu1_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 6368, 104, mtlgt3__ext1002__xve_inst_executed_send_rt_chs__max,mtlgt3__ext1002__xve_inst_executed_send_rt_chs__read);

      intel_perf_query_add_counter_uint64(query, 6369, 112, mtlgt3__ext1002__xve_inst_executed_alu0_rt_ms__max,mtlgt3__ext1002__xve_inst_executed_alu0_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 6370, 120, mtlgt3__ext1002__xve_inst_executed_alu1_rt_ms__max,mtlgt3__ext1002__xve_inst_executed_alu1_rt_ms__read);

      intel_perf_query_add_counter_uint64(query, 6371, 128, mtlgt3__ext1002__xve_inst_executed_send_rt_ms__max,mtlgt3__ext1002__xve_inst_executed_send_rt_ms__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1003_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1003";
   query->symbol_name = "Ext1003";
   query->guid = "24e3b1a8-b80e-4c8c-ab21-83640d78f896";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00054014 },
         { .reg = 0x0000E558, .val = 0x00034024 },
         { .reg = 0x0000E658, .val = 0x00094064 },
         { .reg = 0x0000E758, .val = 0x000B40A4 },
         { .reg = 0x0000E45C, .val = 0x00000004 },
         { .reg = 0x0000E55C, .val = 0x000C4000 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1003__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1003__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1003__avg_gpu_core_frequency__max,mtlgt3__ext1003__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6310, 24, percentage_max_float,mtlgt3__ext1003__xve_active__read);

      intel_perf_query_add_counter_float(query, 6372, 28, percentage_max_float,mtlgt3__ext1003__xve_active_ds__read);

      intel_perf_query_add_counter_float(query, 6373, 32, percentage_max_float,mtlgt3__ext1003__xve_active_hs__read);

      intel_perf_query_add_counter_float(query, 6374, 36, percentage_max_float,mtlgt3__ext1003__xve_active_ps__read);

      intel_perf_query_add_counter_float(query, 6375, 40, percentage_max_float,mtlgt3__ext1003__xve_active_vs__read);

      intel_perf_query_add_counter_float(query, 6376, 44, percentage_max_float,mtlgt3__ext1003__xve_active_async_cs__read);

      intel_perf_query_add_counter_float(query, 6377, 48, percentage_max_float,mtlgt3__ext1003__xve_active_cs__read);

      intel_perf_query_add_counter_float(query, 6378, 52, percentage_max_float,mtlgt3__ext1003__xve_active_ms__read);

      intel_perf_query_add_counter_float(query, 6379, 56, percentage_max_float,mtlgt3__ext1003__xve_active_ts__read);

      intel_perf_query_add_counter_float(query, 6380, 60, percentage_max_float,mtlgt3__ext1003__xve_active_rt__read);

      intel_perf_query_add_counter_uint64(query, 6325, 64, mtlgt3__ext1003__xve_active_cycles__max,mtlgt3__ext1003__xve_active_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6381, 72, mtlgt3__ext1003__xve_active_cycles_async_cs__max,mtlgt3__ext1003__xve_active_cycles_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 6382, 80, mtlgt3__ext1003__xve_active_cycles_cs__max,mtlgt3__ext1003__xve_active_cycles_cs__read);

      intel_perf_query_add_counter_uint64(query, 6383, 88, percentage_max_uint64,mtlgt3__ext1003__xve_active_cycles_hs__read);

      intel_perf_query_add_counter_uint64(query, 6384, 96, mtlgt3__ext1003__xve_active_cycles_ps__max,mtlgt3__ext1003__xve_active_cycles_ps__read);

      intel_perf_query_add_counter_uint64(query, 6385, 104, mtlgt3__ext1003__xve_active_cycles_vs__max,mtlgt3__ext1003__xve_active_cycles_vs__read);

      intel_perf_query_add_counter_uint64(query, 6386, 112, mtlgt3__ext1003__xve_active_cycles_ds__max,mtlgt3__ext1003__xve_active_cycles_ds__read);

      intel_perf_query_add_counter_uint64(query, 6387, 120, mtlgt3__ext1003__xve_active_cycles_ms__max,mtlgt3__ext1003__xve_active_cycles_ms__read);

      intel_perf_query_add_counter_uint64(query, 6388, 128, mtlgt3__ext1003__xve_active_cycles_ts__max,mtlgt3__ext1003__xve_active_cycles_ts__read);

      intel_perf_query_add_counter_uint64(query, 6389, 136, mtlgt3__ext1003__xve_active_cycles_rt__max,mtlgt3__ext1003__xve_active_cycles_rt__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1004_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1004";
   query->symbol_name = "Ext1004";
   query->guid = "974d6469-d51f-4e4a-a393-32033f9b562e";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00015005 },
         { .reg = 0x0000E558, .val = 0x000550A5 },
         { .reg = 0x0000E658, .val = 0x000250B5 },
         { .reg = 0x0000E758, .val = 0x00065035 },
         { .reg = 0x0000E45C, .val = 0x00000095 },
         { .reg = 0x0000E55C, .val = 0x000C5000 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1004__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1004__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1004__avg_gpu_core_frequency__max,mtlgt3__ext1004__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6311, 24, percentage_max_float,mtlgt3__ext1004__xve_stall__read);

      intel_perf_query_add_counter_float(query, 6390, 28, percentage_max_float,mtlgt3__ext1004__xve_stall_async_cs__read);

      intel_perf_query_add_counter_float(query, 6391, 32, percentage_max_float,mtlgt3__ext1004__xve_stall_cs__read);

      intel_perf_query_add_counter_float(query, 6392, 36, percentage_max_float,mtlgt3__ext1004__xve_stall_ds__read);

      intel_perf_query_add_counter_float(query, 6393, 40, percentage_max_float,mtlgt3__ext1004__xve_stall_hs__read);

      intel_perf_query_add_counter_float(query, 6394, 44, percentage_max_float,mtlgt3__ext1004__xve_stall_ms__read);

      intel_perf_query_add_counter_float(query, 6395, 48, percentage_max_float,mtlgt3__ext1004__xve_stall_ps__read);

      intel_perf_query_add_counter_float(query, 6396, 52, percentage_max_float,mtlgt3__ext1004__xve_stall_ts__read);

      intel_perf_query_add_counter_float(query, 6397, 56, percentage_max_float,mtlgt3__ext1004__xve_stall_vs__read);

      intel_perf_query_add_counter_float(query, 6398, 60, percentage_max_float,mtlgt3__ext1004__xve_stall_rt__read);

      intel_perf_query_add_counter_uint64(query, 6326, 64, mtlgt3__ext1004__xve_stall_cycles__max,mtlgt3__ext1004__xve_stall_cycles__read);

      intel_perf_query_add_counter_uint64(query, 6399, 72, mtlgt3__ext1004__xve_stall_cycles_async_cs__max,mtlgt3__ext1004__xve_stall_cycles_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 6400, 80, mtlgt3__ext1004__xve_stall_cycles_cs__max,mtlgt3__ext1004__xve_stall_cycles_cs__read);

      intel_perf_query_add_counter_uint64(query, 6401, 88, mtlgt3__ext1004__xve_stall_cycles_ds__max,mtlgt3__ext1004__xve_stall_cycles_ds__read);

      intel_perf_query_add_counter_uint64(query, 6402, 96, mtlgt3__ext1004__xve_stall_cycles_hs__max,mtlgt3__ext1004__xve_stall_cycles_hs__read);

      intel_perf_query_add_counter_uint64(query, 6403, 104, mtlgt3__ext1004__xve_stall_cycles_ms__max,mtlgt3__ext1004__xve_stall_cycles_ms__read);

      intel_perf_query_add_counter_uint64(query, 6404, 112, mtlgt3__ext1004__xve_stall_cycles_ps__max,mtlgt3__ext1004__xve_stall_cycles_ps__read);

      intel_perf_query_add_counter_uint64(query, 6405, 120, mtlgt3__ext1004__xve_stall_cycles_ts__max,mtlgt3__ext1004__xve_stall_cycles_ts__read);

      intel_perf_query_add_counter_uint64(query, 6406, 128, mtlgt3__ext1004__xve_stall_cycles_vs__max,mtlgt3__ext1004__xve_stall_cycles_vs__read);

      intel_perf_query_add_counter_uint64(query, 6407, 136, mtlgt3__ext1004__xve_stall_cycles_rt__max,mtlgt3__ext1004__xve_stall_cycles_rt__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1005_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 27);

   query->name = "Ext1005";
   query->symbol_name = "Ext1005";
   query->guid = "c172fb87-e53f-468d-893a-d8528684accc";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x0000700B },
         { .reg = 0x0000E558, .val = 0x02000006 },
         { .reg = 0x0000E658, .val = 0x0000C00D },
         { .reg = 0x0000E758, .val = 0x0200200F },
         { .reg = 0x0000E45C, .val = 0x0000000E },
         { .reg = 0x0000E55C, .val = 0x00009001 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1005__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1005__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1005__avg_gpu_core_frequency__max,mtlgt3__ext1005__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6313, 24, mtlgt3__ext1005__xve_inst_executed_alu0_all__max,mtlgt3__ext1005__xve_inst_executed_alu0_all__read);

      intel_perf_query_add_counter_uint64(query, 6408, 32, mtlgt3__ext1005__xve_inst_executed_fp16__max,mtlgt3__ext1005__xve_inst_executed_fp16__read);

      intel_perf_query_add_counter_uint64(query, 6409, 40, mtlgt3__ext1005__xve_inst_executed_fp32__max,mtlgt3__ext1005__xve_inst_executed_fp32__read);

      intel_perf_query_add_counter_uint64(query, 6410, 48, mtlgt3__ext1005__xve_inst_executed_fp64__max,mtlgt3__ext1005__xve_inst_executed_fp64__read);

      intel_perf_query_add_counter_uint64(query, 6314, 56, mtlgt3__ext1005__xve_inst_executed_alu1_all__max,mtlgt3__ext1005__xve_inst_executed_alu1_all__read);

      intel_perf_query_add_counter_uint64(query, 6411, 64, mtlgt3__ext1005__xve_inst_executed_int16__max,mtlgt3__ext1005__xve_inst_executed_int16__read);

      intel_perf_query_add_counter_uint64(query, 6412, 72, mtlgt3__ext1005__xve_inst_executed_int32__max,mtlgt3__ext1005__xve_inst_executed_int32__read);

      intel_perf_query_add_counter_uint64(query, 6413, 80, mtlgt3__ext1005__xve_inst_executed_math__max,mtlgt3__ext1005__xve_inst_executed_math__read);

      intel_perf_query_add_counter_uint64(query, 6315, 88, mtlgt3__ext1005__xve_inst_executed_xmx_all__max,mtlgt3__ext1005__xve_inst_executed_xmx_all__read);

      intel_perf_query_add_counter_uint64(query, 6414, 96, mtlgt3__ext1005__xve_inst_executed_xmx_bf16__max,mtlgt3__ext1005__xve_inst_executed_xmx_bf16__read);

      intel_perf_query_add_counter_uint64(query, 6415, 104, mtlgt3__ext1005__xve_inst_executed_xmx_fp16__max,mtlgt3__ext1005__xve_inst_executed_xmx_fp16__read);

      intel_perf_query_add_counter_uint64(query, 6416, 112, mtlgt3__ext1005__xve_inst_executed_xmx_int8__max,mtlgt3__ext1005__xve_inst_executed_xmx_int8__read);

      intel_perf_query_add_counter_float(query, 6320, 120, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_alu0_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6417, 124, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 6418, 128, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_fp32_utilization__read);

      intel_perf_query_add_counter_float(query, 6419, 132, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_fp64_utilization__read);

      intel_perf_query_add_counter_float(query, 6321, 136, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_alu1_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6420, 140, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_int16_utilization__read);

      intel_perf_query_add_counter_float(query, 6421, 144, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_int32_utilization__read);

      intel_perf_query_add_counter_float(query, 6422, 148, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_math_utilization__read);

      intel_perf_query_add_counter_float(query, 6322, 152, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_xmx_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6423, 156, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_xmx_bf16_utilization__read);

      intel_perf_query_add_counter_float(query, 6424, 160, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_xmx_fp16_utilization__read);

      intel_perf_query_add_counter_float(query, 6425, 164, percentage_max_float,mtlgt3__ext1005__xve_inst_executed_xmx_int8_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1006_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 23);

   query->name = "Ext1006";
   query->symbol_name = "Ext1006";
   query->guid = "f739508f-51b2-48df-839c-e92c14d14c64";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x000A2012 },
         { .reg = 0x0000E558, .val = 0x000B2052 },
         { .reg = 0x0000E658, .val = 0x00042022 },
         { .reg = 0x0000E758, .val = 0x00062032 },
         { .reg = 0x0000E45C, .val = 0x00002092 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1006__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1006__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1006__avg_gpu_core_frequency__max,mtlgt3__ext1006__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6316, 24, mtlgt3__ext1006__xve_inst_executed_send_all__max,mtlgt3__ext1006__xve_inst_executed_send_all__read);

      intel_perf_query_add_counter_uint64(query, 6426, 32, mtlgt3__ext1006__xve_inst_executed_send_async_cs__max,mtlgt3__ext1006__xve_inst_executed_send_async_cs__read);

      intel_perf_query_add_counter_uint64(query, 6427, 40, mtlgt3__ext1006__xve_inst_executed_send_cs__max,mtlgt3__ext1006__xve_inst_executed_send_cs__read);

      intel_perf_query_add_counter_uint64(query, 6428, 48, mtlgt3__ext1006__xve_inst_executed_send_ds__max,mtlgt3__ext1006__xve_inst_executed_send_ds__read);

      intel_perf_query_add_counter_uint64(query, 6429, 56, mtlgt3__ext1006__xve_inst_executed_send_gs__max,mtlgt3__ext1006__xve_inst_executed_send_gs__read);

      intel_perf_query_add_counter_uint64(query, 6430, 64, mtlgt3__ext1006__xve_inst_executed_send_hs__max,mtlgt3__ext1006__xve_inst_executed_send_hs__read);

      intel_perf_query_add_counter_uint64(query, 6431, 72, mtlgt3__ext1006__xve_inst_executed_send_ms__max,mtlgt3__ext1006__xve_inst_executed_send_ms__read);

      intel_perf_query_add_counter_uint64(query, 6432, 80, mtlgt3__ext1006__xve_inst_executed_send_ps__max,mtlgt3__ext1006__xve_inst_executed_send_ps__read);

      intel_perf_query_add_counter_uint64(query, 6433, 88, mtlgt3__ext1006__xve_inst_executed_send_ts__max,mtlgt3__ext1006__xve_inst_executed_send_ts__read);

      intel_perf_query_add_counter_uint64(query, 6434, 96, mtlgt3__ext1006__xve_inst_executed_send_vs__max,mtlgt3__ext1006__xve_inst_executed_send_vs__read);

      intel_perf_query_add_counter_float(query, 6323, 104, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_all_utilization__read);

      intel_perf_query_add_counter_float(query, 6435, 108, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_async_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6436, 112, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_cs_utilization__read);

      intel_perf_query_add_counter_float(query, 6437, 116, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_ds_utilization__read);

      intel_perf_query_add_counter_float(query, 6438, 120, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 6439, 124, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_hs_utilization__read);

      intel_perf_query_add_counter_float(query, 6440, 128, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6441, 132, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_ps_utilization__read);

      intel_perf_query_add_counter_float(query, 6442, 136, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 6443, 140, percentage_max_float,mtlgt3__ext1006__xve_inst_executed_send_vs_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1007_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 19);

   query->name = "Ext1007";
   query->symbol_name = "Ext1007";
   query->guid = "926b1773-807e-4ee5-8561-30c9eb0a6344";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);

      static const struct intel_perf_query_register_prog flex_regs[] = {
         { .reg = 0x0000E458, .val = 0x00045044 },
         { .reg = 0x0000E558, .val = 0x00040041 },
         { .reg = 0x0000E658, .val = 0x000B10A1 },
         { .reg = 0x0000E758, .val = 0x000B00A0 },
      };
      query->config.flex_regs = flex_regs;
      query->config.n_flex_regs = ARRAY_SIZE(flex_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1007__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1007__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1007__avg_gpu_core_frequency__max,mtlgt3__ext1007__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_float(query, 6444, 24, percentage_max_float,mtlgt3__ext1007__xve_active_gs__read);

      intel_perf_query_add_counter_float(query, 6445, 28, percentage_max_float,mtlgt3__ext1007__xve_stall_gs__read);

      intel_perf_query_add_counter_uint64(query, 6446, 32, mtlgt3__ext1007__xve_inst_executed_alu0_gs__max,mtlgt3__ext1007__xve_inst_executed_alu0_gs__read);

      intel_perf_query_add_counter_uint64(query, 6447, 40, mtlgt3__ext1007__xve_inst_executed_alu1_gs__max,mtlgt3__ext1007__xve_inst_executed_alu1_gs__read);

      intel_perf_query_add_counter_uint64(query, 6448, 48, mtlgt3__ext1007__xve_active_cycles_gs__max,mtlgt3__ext1007__xve_active_cycles_gs__read);

      intel_perf_query_add_counter_uint64(query, 6449, 56, mtlgt3__ext1007__xve_stall_cycles_gs__max,mtlgt3__ext1007__xve_stall_cycles_gs__read);

      intel_perf_query_add_counter_uint64(query, 6450, 64, mtlgt3__ext1007__xve_inst_executed_alu0_ms__max,mtlgt3__ext1007__xve_inst_executed_alu0_ms__read);

      intel_perf_query_add_counter_uint64(query, 6451, 72, mtlgt3__ext1007__xve_inst_executed_alu0_ts__max,mtlgt3__ext1007__xve_inst_executed_alu0_ts__read);

      intel_perf_query_add_counter_uint64(query, 6452, 80, mtlgt3__ext1007__xve_inst_executed_alu1_ms__max,mtlgt3__ext1007__xve_inst_executed_alu1_ms__read);

      intel_perf_query_add_counter_uint64(query, 6453, 88, mtlgt3__ext1007__xve_inst_executed_alu1_ts__max,mtlgt3__ext1007__xve_inst_executed_alu1_ts__read);

      intel_perf_query_add_counter_float(query, 6454, 96, percentage_max_float,mtlgt3__ext1007__xve_inst_executed_alu0_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 6455, 100, percentage_max_float,mtlgt3__ext1007__xve_inst_executed_alu1_gs_utilization__read);

      intel_perf_query_add_counter_float(query, 6456, 104, percentage_max_float,mtlgt3__ext1007__xve_inst_executed_alu0_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6457, 108, percentage_max_float,mtlgt3__ext1007__xve_inst_executed_alu0_ts_utilization__read);

      intel_perf_query_add_counter_float(query, 6458, 112, percentage_max_float,mtlgt3__ext1007__xve_inst_executed_alu1_ms_utilization__read);

      intel_perf_query_add_counter_float(query, 6459, 116, percentage_max_float,mtlgt3__ext1007__xve_inst_executed_alu1_ts_utilization__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}


static void
mtlgt3_register_ext1010_counter_query(struct intel_perf_config *perf)
{
   struct intel_perf_query_info *query = intel_query_alloc(perf, 8);

   query->name = "Ext1010";
   query->symbol_name = "Ext1010";
   query->guid = "82f69b49-772a-4169-bf9a-b1ef08e0823b";

   struct intel_perf_query_counter *counter = query->counters;

   /* Note: we're assuming there can't be any variation in the definition
    * of a query between contexts so it's ok to describe a query within a
    * global variable which only needs to be initialized once... */

   if (!query->data_size) {
      static const struct intel_perf_query_register_prog b_counter_regs[] = {
         { .reg = 0x0000D900, .val = 0x00000000 },
         { .reg = 0x0000D904, .val = 0x00800000 },
         { .reg = 0x0000D910, .val = 0x00000000 },
         { .reg = 0x0000D914, .val = 0x00800000 },
         { .reg = 0x0000D920, .val = 0x00000000 },
         { .reg = 0x0000DC40, .val = 0x00000000 },
         { .reg = 0x0000DD40, .val = 0x00000000 },
         { .reg = 0x00002B2C, .val = 0x00000000 },
      };
      query->config.b_counter_regs = b_counter_regs;
      query->config.n_b_counter_regs = ARRAY_SIZE(b_counter_regs);


      intel_perf_query_add_counter_uint64(query, 0, 0, NULL,mtlgt3__ext1010__gpu_time__read);

      intel_perf_query_add_counter_uint64(query, 1, 8, NULL,mtlgt3__ext1010__gpu_core_clocks__read);

      intel_perf_query_add_counter_uint64(query, 2, 16, mtlgt3__ext1010__avg_gpu_core_frequency__max,mtlgt3__ext1010__avg_gpu_core_frequency__read);

      intel_perf_query_add_counter_uint64(query, 6460, 24, NULL,mtlgt3__ext1010__sampler_2_x2_read__read);

      intel_perf_query_add_counter_uint64(query, 6461, 32, NULL,mtlgt3__ext1010__pixel_write__read);

      intel_perf_query_add_counter_uint64(query, 6462, 40, NULL,mtlgt3__ext1010__pixel_blend__read);

      intel_perf_query_add_counter_uint64(query, 6463, 48, NULL,mtlgt3__ext1010__rasterizer_sample_output__read);

      intel_perf_query_add_counter_uint64(query, 6464, 56, NULL,mtlgt3__ext1010__postps_depth_stencil_alpha_test_fail__read);

      counter = &query->counters[query->n_counters - 1];
      query->data_size = counter->offset + intel_perf_query_counter_get_size(counter);
   }

   _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query);
}

void
intel_oa_register_queries_mtlgt3(struct intel_perf_config *perf)
{
   mtlgt3_register_render_basic_counter_query(perf);
   mtlgt3_register_compute_basic_counter_query(perf);
   mtlgt3_register_async_compute_counter_query(perf);
   mtlgt3_register_xve_activity_counter_query(perf);
   mtlgt3_register_gpu_busyness_counter_query(perf);
   mtlgt3_register_hdc_and_sf1_counter_query(perf);
   mtlgt3_register_hdc_and_sf2_counter_query(perf);
   mtlgt3_register_l3_counter_query(perf);
   mtlgt3_register_rasterizer_and_pixel_backend1_counter_query(perf);
   mtlgt3_register_rasterizer_and_pixel_backend2_counter_query(perf);
   mtlgt3_register_render_pipe_profile1_counter_query(perf);
   mtlgt3_register_render_pipe_profile2_counter_query(perf);
   mtlgt3_register_sampler_counter_query(perf);
   mtlgt3_register_tdl1_counter_query(perf);
   mtlgt3_register_tdl2_counter_query(perf);
   mtlgt3_register_tdl3_counter_query(perf);
   mtlgt3_register_tdl4_counter_query(perf);
   mtlgt3_register_test_oa_counter_query(perf);
   mtlgt3_register_ext1_counter_query(perf);
   mtlgt3_register_ext3_counter_query(perf);
   mtlgt3_register_ext4_counter_query(perf);
   mtlgt3_register_ext5_counter_query(perf);
   mtlgt3_register_ext6_counter_query(perf);
   mtlgt3_register_ext7_counter_query(perf);
   mtlgt3_register_ext8_counter_query(perf);
   mtlgt3_register_ext9_counter_query(perf);
   mtlgt3_register_ext10_counter_query(perf);
   mtlgt3_register_ext11_counter_query(perf);
   mtlgt3_register_ext12_counter_query(perf);
   mtlgt3_register_ext13_counter_query(perf);
   mtlgt3_register_ext14_counter_query(perf);
   mtlgt3_register_ext15_counter_query(perf);
   mtlgt3_register_ext16_counter_query(perf);
   mtlgt3_register_ext17_counter_query(perf);
   mtlgt3_register_ext18_counter_query(perf);
   mtlgt3_register_ext21_counter_query(perf);
   mtlgt3_register_ext22_counter_query(perf);
   mtlgt3_register_ext23_counter_query(perf);
   mtlgt3_register_ext24_counter_query(perf);
   mtlgt3_register_ext28_counter_query(perf);
   mtlgt3_register_ext29_counter_query(perf);
   mtlgt3_register_ext31_counter_query(perf);
   mtlgt3_register_ext32_counter_query(perf);
   mtlgt3_register_ext35_counter_query(perf);
   mtlgt3_register_ext36_counter_query(perf);
   mtlgt3_register_ext39_counter_query(perf);
   mtlgt3_register_ext40_counter_query(perf);
   mtlgt3_register_ext43_counter_query(perf);
   mtlgt3_register_ext44_counter_query(perf);
   mtlgt3_register_ext45_counter_query(perf);
   mtlgt3_register_ext46_counter_query(perf);
   mtlgt3_register_ext51_counter_query(perf);
   mtlgt3_register_ext53_counter_query(perf);
   mtlgt3_register_ext54_counter_query(perf);
   mtlgt3_register_ext57_counter_query(perf);
   mtlgt3_register_ext58_counter_query(perf);
   mtlgt3_register_ext61_counter_query(perf);
   mtlgt3_register_ext62_counter_query(perf);
   mtlgt3_register_ext65_counter_query(perf);
   mtlgt3_register_ext66_counter_query(perf);
   mtlgt3_register_ext67_counter_query(perf);
   mtlgt3_register_ext68_counter_query(perf);
   mtlgt3_register_ext73_counter_query(perf);
   mtlgt3_register_ext74_counter_query(perf);
   mtlgt3_register_ext75_counter_query(perf);
   mtlgt3_register_ext76_counter_query(perf);
   mtlgt3_register_ext77_counter_query(perf);
   mtlgt3_register_ext78_counter_query(perf);
   mtlgt3_register_ext79_counter_query(perf);
   mtlgt3_register_ext80_counter_query(perf);
   mtlgt3_register_ext81_counter_query(perf);
   mtlgt3_register_ext82_counter_query(perf);
   mtlgt3_register_ext83_counter_query(perf);
   mtlgt3_register_ext85_counter_query(perf);
   mtlgt3_register_ext86_counter_query(perf);
   mtlgt3_register_ext87_counter_query(perf);
   mtlgt3_register_ext88_counter_query(perf);
   mtlgt3_register_ext91_counter_query(perf);
   mtlgt3_register_ext92_counter_query(perf);
   mtlgt3_register_ext93_counter_query(perf);
   mtlgt3_register_ext94_counter_query(perf);
   mtlgt3_register_ext95_counter_query(perf);
   mtlgt3_register_ext96_counter_query(perf);
   mtlgt3_register_ext97_counter_query(perf);
   mtlgt3_register_ext98_counter_query(perf);
   mtlgt3_register_ext99_counter_query(perf);
   mtlgt3_register_ext100_counter_query(perf);
   mtlgt3_register_ext101_counter_query(perf);
   mtlgt3_register_ext102_counter_query(perf);
   mtlgt3_register_ext103_counter_query(perf);
   mtlgt3_register_ext104_counter_query(perf);
   mtlgt3_register_ext105_counter_query(perf);
   mtlgt3_register_ext106_counter_query(perf);
   mtlgt3_register_ext107_counter_query(perf);
   mtlgt3_register_ext108_counter_query(perf);
   mtlgt3_register_ext109_counter_query(perf);
   mtlgt3_register_ext110_counter_query(perf);
   mtlgt3_register_ext111_counter_query(perf);
   mtlgt3_register_ext113_counter_query(perf);
   mtlgt3_register_ext114_counter_query(perf);
   mtlgt3_register_ext116_counter_query(perf);
   mtlgt3_register_ext117_counter_query(perf);
   mtlgt3_register_ext118_counter_query(perf);
   mtlgt3_register_ext119_counter_query(perf);
   mtlgt3_register_ext120_counter_query(perf);
   mtlgt3_register_ext121_counter_query(perf);
   mtlgt3_register_ext122_counter_query(perf);
   mtlgt3_register_ext123_counter_query(perf);
   mtlgt3_register_ext124_counter_query(perf);
   mtlgt3_register_ext125_counter_query(perf);
   mtlgt3_register_ext126_counter_query(perf);
   mtlgt3_register_ext127_counter_query(perf);
   mtlgt3_register_ext128_counter_query(perf);
   mtlgt3_register_ext129_counter_query(perf);
   mtlgt3_register_ext130_counter_query(perf);
   mtlgt3_register_ext131_counter_query(perf);
   mtlgt3_register_ext132_counter_query(perf);
   mtlgt3_register_ext133_counter_query(perf);
   mtlgt3_register_ext134_counter_query(perf);
   mtlgt3_register_ext135_counter_query(perf);
   mtlgt3_register_ext136_counter_query(perf);
   mtlgt3_register_ext137_counter_query(perf);
   mtlgt3_register_ext138_counter_query(perf);
   mtlgt3_register_ext139_counter_query(perf);
   mtlgt3_register_ext140_counter_query(perf);
   mtlgt3_register_ext141_counter_query(perf);
   mtlgt3_register_ext142_counter_query(perf);
   mtlgt3_register_ext143_counter_query(perf);
   mtlgt3_register_ext144_counter_query(perf);
   mtlgt3_register_ext145_counter_query(perf);
   mtlgt3_register_ext146_counter_query(perf);
   mtlgt3_register_ext147_counter_query(perf);
   mtlgt3_register_ext148_counter_query(perf);
   mtlgt3_register_ext149_counter_query(perf);
   mtlgt3_register_ext150_counter_query(perf);
   mtlgt3_register_ext151_counter_query(perf);
   mtlgt3_register_ext152_counter_query(perf);
   mtlgt3_register_ext153_counter_query(perf);
   mtlgt3_register_ext154_counter_query(perf);
   mtlgt3_register_ext155_counter_query(perf);
   mtlgt3_register_ext156_counter_query(perf);
   mtlgt3_register_ext158_counter_query(perf);
   mtlgt3_register_ext159_counter_query(perf);
   mtlgt3_register_ext160_counter_query(perf);
   mtlgt3_register_ext161_counter_query(perf);
   mtlgt3_register_ext162_counter_query(perf);
   mtlgt3_register_ext163_counter_query(perf);
   mtlgt3_register_ext164_counter_query(perf);
   mtlgt3_register_ext165_counter_query(perf);
   mtlgt3_register_ext166_counter_query(perf);
   mtlgt3_register_ext167_counter_query(perf);
   mtlgt3_register_ext168_counter_query(perf);
   mtlgt3_register_ext169_counter_query(perf);
   mtlgt3_register_ext170_counter_query(perf);
   mtlgt3_register_ext171_counter_query(perf);
   mtlgt3_register_ext172_counter_query(perf);
   mtlgt3_register_ext173_counter_query(perf);
   mtlgt3_register_ext174_counter_query(perf);
   mtlgt3_register_ext175_counter_query(perf);
   mtlgt3_register_ext176_counter_query(perf);
   mtlgt3_register_ext177_counter_query(perf);
   mtlgt3_register_ext178_counter_query(perf);
   mtlgt3_register_ext179_counter_query(perf);
   mtlgt3_register_ext180_counter_query(perf);
   mtlgt3_register_ext181_counter_query(perf);
   mtlgt3_register_ext182_counter_query(perf);
   mtlgt3_register_ext183_counter_query(perf);
   mtlgt3_register_ext184_counter_query(perf);
   mtlgt3_register_ext185_counter_query(perf);
   mtlgt3_register_ext186_counter_query(perf);
   mtlgt3_register_ext188_counter_query(perf);
   mtlgt3_register_ext189_counter_query(perf);
   mtlgt3_register_ext190_counter_query(perf);
   mtlgt3_register_ext191_counter_query(perf);
   mtlgt3_register_ext192_counter_query(perf);
   mtlgt3_register_ext193_counter_query(perf);
   mtlgt3_register_ext195_counter_query(perf);
   mtlgt3_register_ext196_counter_query(perf);
   mtlgt3_register_ext198_counter_query(perf);
   mtlgt3_register_ext199_counter_query(perf);
   mtlgt3_register_ext200_counter_query(perf);
   mtlgt3_register_ext201_counter_query(perf);
   mtlgt3_register_ext202_counter_query(perf);
   mtlgt3_register_ext203_counter_query(perf);
   mtlgt3_register_ext204_counter_query(perf);
   mtlgt3_register_ext205_counter_query(perf);
   mtlgt3_register_ext206_counter_query(perf);
   mtlgt3_register_ext207_counter_query(perf);
   mtlgt3_register_ext212_counter_query(perf);
   mtlgt3_register_ext213_counter_query(perf);
   mtlgt3_register_ext214_counter_query(perf);
   mtlgt3_register_ext215_counter_query(perf);
   mtlgt3_register_ext220_counter_query(perf);
   mtlgt3_register_ext225_counter_query(perf);
   mtlgt3_register_ext226_counter_query(perf);
   mtlgt3_register_ext227_counter_query(perf);
   mtlgt3_register_ext228_counter_query(perf);
   mtlgt3_register_ext229_counter_query(perf);
   mtlgt3_register_ext230_counter_query(perf);
   mtlgt3_register_ext231_counter_query(perf);
   mtlgt3_register_ext232_counter_query(perf);
   mtlgt3_register_ext236_counter_query(perf);
   mtlgt3_register_ext237_counter_query(perf);
   mtlgt3_register_ext239_counter_query(perf);
   mtlgt3_register_ext240_counter_query(perf);
   mtlgt3_register_ext500_counter_query(perf);
   mtlgt3_register_ext501_counter_query(perf);
   mtlgt3_register_ext502_counter_query(perf);
   mtlgt3_register_ext503_counter_query(perf);
   mtlgt3_register_ext508_counter_query(perf);
   mtlgt3_register_ext509_counter_query(perf);
   mtlgt3_register_ext510_counter_query(perf);
   mtlgt3_register_ext511_counter_query(perf);
   mtlgt3_register_ext512_counter_query(perf);
   mtlgt3_register_ext513_counter_query(perf);
   mtlgt3_register_ext514_counter_query(perf);
   mtlgt3_register_ext515_counter_query(perf);
   mtlgt3_register_ext516_counter_query(perf);
   mtlgt3_register_ext517_counter_query(perf);
   mtlgt3_register_ext518_counter_query(perf);
   mtlgt3_register_ext519_counter_query(perf);
   mtlgt3_register_ext520_counter_query(perf);
   mtlgt3_register_ext521_counter_query(perf);
   mtlgt3_register_ext522_counter_query(perf);
   mtlgt3_register_ext523_counter_query(perf);
   mtlgt3_register_ext524_counter_query(perf);
   mtlgt3_register_ext525_counter_query(perf);
   mtlgt3_register_ext526_counter_query(perf);
   mtlgt3_register_ext527_counter_query(perf);
   mtlgt3_register_ext528_counter_query(perf);
   mtlgt3_register_ext529_counter_query(perf);
   mtlgt3_register_ext530_counter_query(perf);
   mtlgt3_register_ext531_counter_query(perf);
   mtlgt3_register_ext540_counter_query(perf);
   mtlgt3_register_ext541_counter_query(perf);
   mtlgt3_register_ext542_counter_query(perf);
   mtlgt3_register_ext543_counter_query(perf);
   mtlgt3_register_ext544_counter_query(perf);
   mtlgt3_register_ext545_counter_query(perf);
   mtlgt3_register_ext546_counter_query(perf);
   mtlgt3_register_ext547_counter_query(perf);
   mtlgt3_register_ext604_counter_query(perf);
   mtlgt3_register_ext1000_counter_query(perf);
   mtlgt3_register_ext1001_counter_query(perf);
   mtlgt3_register_ext1002_counter_query(perf);
   mtlgt3_register_ext1003_counter_query(perf);
   mtlgt3_register_ext1004_counter_query(perf);
   mtlgt3_register_ext1005_counter_query(perf);
   mtlgt3_register_ext1006_counter_query(perf);
   mtlgt3_register_ext1007_counter_query(perf);
   mtlgt3_register_ext1010_counter_query(perf);
}
